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radv: clear CMASK layers instead of the whole buffer on GFX8
[mesa.git] / src / amd / vulkan / radv_image.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "vk_format.h"
31 #include "vk_util.h"
32 #include "radv_radeon_winsys.h"
33 #include "sid.h"
34 #include "util/debug.h"
35 #include "util/u_atomic.h"
36
37 static unsigned
38 radv_choose_tiling(struct radv_device *device,
39 const struct radv_image_create_info *create_info)
40 {
41 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
42
43 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) {
44 assert(pCreateInfo->samples <= 1);
45 return RADEON_SURF_MODE_LINEAR_ALIGNED;
46 }
47
48 if (!vk_format_is_compressed(pCreateInfo->format) &&
49 !vk_format_is_depth_or_stencil(pCreateInfo->format)
50 && device->physical_device->rad_info.chip_class <= GFX8) {
51 /* this causes hangs in some VK CTS tests on GFX9. */
52 /* Textures with a very small height are recommended to be linear. */
53 if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
54 /* Only very thin and long 2D textures should benefit from
55 * linear_aligned. */
56 (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
57 return RADEON_SURF_MODE_LINEAR_ALIGNED;
58 }
59
60 /* MSAA resources must be 2D tiled. */
61 if (pCreateInfo->samples > 1)
62 return RADEON_SURF_MODE_2D;
63
64 return RADEON_SURF_MODE_2D;
65 }
66
67 static bool
68 radv_use_tc_compat_htile_for_image(struct radv_device *device,
69 const VkImageCreateInfo *pCreateInfo)
70 {
71 /* TC-compat HTILE is only available for GFX8+. */
72 if (device->physical_device->rad_info.chip_class < GFX8)
73 return false;
74
75 if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
76 (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
77 return false;
78
79 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
80 return false;
81
82 if (pCreateInfo->mipLevels > 1)
83 return false;
84
85 /* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
86 * tests - disable for now */
87 if (pCreateInfo->samples >= 2 &&
88 pCreateInfo->format == VK_FORMAT_D32_SFLOAT_S8_UINT)
89 return false;
90
91 /* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only
92 * supports 32-bit. Though, it's possible to enable TC-compat for
93 * 16-bit depth surfaces if no Z planes are compressed.
94 */
95 if (pCreateInfo->format != VK_FORMAT_D32_SFLOAT_S8_UINT &&
96 pCreateInfo->format != VK_FORMAT_D32_SFLOAT &&
97 pCreateInfo->format != VK_FORMAT_D16_UNORM)
98 return false;
99
100 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
101 const struct VkImageFormatListCreateInfoKHR *format_list =
102 (const struct VkImageFormatListCreateInfoKHR *)
103 vk_find_struct_const(pCreateInfo->pNext,
104 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
105
106 /* We have to ignore the existence of the list if viewFormatCount = 0 */
107 if (format_list && format_list->viewFormatCount) {
108 /* compatibility is transitive, so we only need to check
109 * one format with everything else.
110 */
111 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
112 if (format_list->pViewFormats[i] == VK_FORMAT_UNDEFINED)
113 continue;
114
115 if (pCreateInfo->format != format_list->pViewFormats[i])
116 return false;
117 }
118 } else {
119 return false;
120 }
121 }
122
123 return true;
124 }
125
126 static bool
127 radv_surface_has_scanout(struct radv_device *device, const struct radv_image_create_info *info)
128 {
129 if (info->scanout)
130 return true;
131
132 if (!info->bo_metadata)
133 return false;
134
135 if (device->physical_device->rad_info.chip_class >= GFX9) {
136 return info->bo_metadata->u.gfx9.swizzle_mode == 0 || info->bo_metadata->u.gfx9.swizzle_mode % 4 == 2;
137 } else {
138 return info->bo_metadata->u.legacy.scanout;
139 }
140 }
141
142 static bool
143 radv_use_dcc_for_image(struct radv_device *device,
144 const struct radv_image *image,
145 const struct radv_image_create_info *create_info,
146 const VkImageCreateInfo *pCreateInfo)
147 {
148 bool dcc_compatible_formats;
149 bool blendable;
150
151 /* DCC (Delta Color Compression) is only available for GFX8+. */
152 if (device->physical_device->rad_info.chip_class < GFX8)
153 return false;
154
155 if (device->instance->debug_flags & RADV_DEBUG_NO_DCC)
156 return false;
157
158 if (image->shareable)
159 return false;
160
161 /* TODO: Enable DCC for storage images. */
162 if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
163 (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
164 return false;
165
166 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
167 return false;
168
169 if (vk_format_is_subsampled(pCreateInfo->format) ||
170 vk_format_get_plane_count(pCreateInfo->format) > 1)
171 return false;
172
173 /* TODO: Enable DCC for mipmaps on GFX9+. */
174 if (pCreateInfo->mipLevels > 1 &&
175 device->physical_device->rad_info.chip_class >= GFX9)
176 return false;
177
178 /* TODO: Enable DCC for array layers. */
179 if (pCreateInfo->arrayLayers > 1)
180 return false;
181
182 if (radv_surface_has_scanout(device, create_info))
183 return false;
184
185 /* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet, while
186 * 2x can be enabled with an option.
187 */
188 if (pCreateInfo->samples > 2 ||
189 (pCreateInfo->samples == 2 &&
190 !device->physical_device->dcc_msaa_allowed))
191 return false;
192
193 /* Determine if the formats are DCC compatible. */
194 dcc_compatible_formats =
195 radv_is_colorbuffer_format_supported(pCreateInfo->format,
196 &blendable);
197
198 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
199 const struct VkImageFormatListCreateInfoKHR *format_list =
200 (const struct VkImageFormatListCreateInfoKHR *)
201 vk_find_struct_const(pCreateInfo->pNext,
202 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
203
204 /* We have to ignore the existence of the list if viewFormatCount = 0 */
205 if (format_list && format_list->viewFormatCount) {
206 /* compatibility is transitive, so we only need to check
207 * one format with everything else. */
208 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
209 if (format_list->pViewFormats[i] == VK_FORMAT_UNDEFINED)
210 continue;
211
212 if (!radv_dcc_formats_compatible(pCreateInfo->format,
213 format_list->pViewFormats[i]))
214 dcc_compatible_formats = false;
215 }
216 } else {
217 dcc_compatible_formats = false;
218 }
219 }
220
221 if (!dcc_compatible_formats)
222 return false;
223
224 return true;
225 }
226
227 static bool
228 radv_use_tc_compat_cmask_for_image(struct radv_device *device,
229 struct radv_image *image)
230 {
231 if (!(device->instance->perftest_flags & RADV_PERFTEST_TC_COMPAT_CMASK))
232 return false;
233
234 /* TC-compat CMASK is only available for GFX8+. */
235 if (device->physical_device->rad_info.chip_class < GFX8)
236 return false;
237
238 if (image->usage & VK_IMAGE_USAGE_STORAGE_BIT)
239 return false;
240
241 if (radv_image_has_dcc(image))
242 return false;
243
244 if (!radv_image_has_cmask(image))
245 return false;
246
247 return true;
248 }
249
250 static void
251 radv_prefill_surface_from_metadata(struct radv_device *device,
252 struct radeon_surf *surface,
253 const struct radv_image_create_info *create_info)
254 {
255 const struct radeon_bo_metadata *md = create_info->bo_metadata;
256 if (device->physical_device->rad_info.chip_class >= GFX9) {
257 if (md->u.gfx9.swizzle_mode > 0)
258 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
259 else
260 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
261
262 surface->u.gfx9.surf.swizzle_mode = md->u.gfx9.swizzle_mode;
263 } else {
264 surface->u.legacy.pipe_config = md->u.legacy.pipe_config;
265 surface->u.legacy.bankw = md->u.legacy.bankw;
266 surface->u.legacy.bankh = md->u.legacy.bankh;
267 surface->u.legacy.tile_split = md->u.legacy.tile_split;
268 surface->u.legacy.mtilea = md->u.legacy.mtilea;
269 surface->u.legacy.num_banks = md->u.legacy.num_banks;
270
271 if (md->u.legacy.macrotile == RADEON_LAYOUT_TILED)
272 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
273 else if (md->u.legacy.microtile == RADEON_LAYOUT_TILED)
274 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
275 else
276 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
277
278 }
279 }
280
281 static int
282 radv_init_surface(struct radv_device *device,
283 const struct radv_image *image,
284 struct radeon_surf *surface,
285 unsigned plane_id,
286 const struct radv_image_create_info *create_info)
287 {
288 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
289 unsigned array_mode = radv_choose_tiling(device, create_info);
290 VkFormat format = vk_format_get_plane_format(pCreateInfo->format, plane_id);
291 const struct vk_format_description *desc = vk_format_description(format);
292 bool is_depth, is_stencil;
293
294 is_depth = vk_format_has_depth(desc);
295 is_stencil = vk_format_has_stencil(desc);
296
297 surface->blk_w = vk_format_get_blockwidth(format);
298 surface->blk_h = vk_format_get_blockheight(format);
299
300 surface->bpe = vk_format_get_blocksize(vk_format_depth_only(format));
301 /* align byte per element on dword */
302 if (surface->bpe == 3) {
303 surface->bpe = 4;
304 }
305 if (create_info->bo_metadata) {
306 radv_prefill_surface_from_metadata(device, surface, create_info);
307 } else {
308 surface->flags = RADEON_SURF_SET(array_mode, MODE);
309 }
310
311 switch (pCreateInfo->imageType){
312 case VK_IMAGE_TYPE_1D:
313 if (pCreateInfo->arrayLayers > 1)
314 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
315 else
316 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
317 break;
318 case VK_IMAGE_TYPE_2D:
319 if (pCreateInfo->arrayLayers > 1)
320 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
321 else
322 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
323 break;
324 case VK_IMAGE_TYPE_3D:
325 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
326 break;
327 default:
328 unreachable("unhandled image type");
329 }
330
331 if (is_depth) {
332 surface->flags |= RADEON_SURF_ZBUFFER;
333 if (radv_use_tc_compat_htile_for_image(device, pCreateInfo))
334 surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
335 }
336
337 if (is_stencil)
338 surface->flags |= RADEON_SURF_SBUFFER;
339
340 if (device->physical_device->rad_info.chip_class >= GFX9 &&
341 pCreateInfo->imageType == VK_IMAGE_TYPE_3D &&
342 vk_format_get_blocksizebits(pCreateInfo->format) == 128 &&
343 vk_format_is_compressed(pCreateInfo->format))
344 surface->flags |= RADEON_SURF_NO_RENDER_TARGET;
345
346 surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
347
348 if (!radv_use_dcc_for_image(device, image, create_info, pCreateInfo))
349 surface->flags |= RADEON_SURF_DISABLE_DCC;
350
351 if (radv_surface_has_scanout(device, create_info))
352 surface->flags |= RADEON_SURF_SCANOUT;
353
354 return 0;
355 }
356
357 static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
358 {
359 return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
360 }
361
362 static inline unsigned
363 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
364 {
365 if (stencil)
366 return plane->surface.u.legacy.stencil_tiling_index[level];
367 else
368 return plane->surface.u.legacy.tiling_index[level];
369 }
370
371 static unsigned radv_map_swizzle(unsigned swizzle)
372 {
373 switch (swizzle) {
374 case VK_SWIZZLE_Y:
375 return V_008F0C_SQ_SEL_Y;
376 case VK_SWIZZLE_Z:
377 return V_008F0C_SQ_SEL_Z;
378 case VK_SWIZZLE_W:
379 return V_008F0C_SQ_SEL_W;
380 case VK_SWIZZLE_0:
381 return V_008F0C_SQ_SEL_0;
382 case VK_SWIZZLE_1:
383 return V_008F0C_SQ_SEL_1;
384 default: /* VK_SWIZZLE_X */
385 return V_008F0C_SQ_SEL_X;
386 }
387 }
388
389 static void
390 radv_make_buffer_descriptor(struct radv_device *device,
391 struct radv_buffer *buffer,
392 VkFormat vk_format,
393 unsigned offset,
394 unsigned range,
395 uint32_t *state)
396 {
397 const struct vk_format_description *desc;
398 unsigned stride;
399 uint64_t gpu_address = radv_buffer_get_va(buffer->bo);
400 uint64_t va = gpu_address + buffer->offset;
401 unsigned num_format, data_format;
402 int first_non_void;
403 desc = vk_format_description(vk_format);
404 first_non_void = vk_format_get_first_non_void_channel(vk_format);
405 stride = desc->block.bits / 8;
406
407 num_format = radv_translate_buffer_numformat(desc, first_non_void);
408 data_format = radv_translate_buffer_dataformat(desc, first_non_void);
409
410 assert(data_format != V_008F0C_BUF_DATA_FORMAT_INVALID);
411 assert(num_format != ~0);
412
413 va += offset;
414 state[0] = va;
415 state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
416 S_008F04_STRIDE(stride);
417
418 if (device->physical_device->rad_info.chip_class != GFX8 && stride) {
419 range /= stride;
420 }
421
422 state[2] = range;
423 state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
424 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
425 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
426 S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3])) |
427 S_008F0C_NUM_FORMAT(num_format) |
428 S_008F0C_DATA_FORMAT(data_format);
429 }
430
431 static void
432 si_set_mutable_tex_desc_fields(struct radv_device *device,
433 struct radv_image *image,
434 const struct legacy_surf_level *base_level_info,
435 unsigned plane_id,
436 unsigned base_level, unsigned first_level,
437 unsigned block_width, bool is_stencil,
438 bool is_storage_image, uint32_t *state)
439 {
440 struct radv_image_plane *plane = &image->planes[plane_id];
441 uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0;
442 uint64_t va = gpu_address + plane->offset;
443 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
444 uint64_t meta_va = 0;
445 if (chip_class >= GFX9) {
446 if (is_stencil)
447 va += plane->surface.u.gfx9.stencil_offset;
448 else
449 va += plane->surface.u.gfx9.surf_offset;
450 } else
451 va += base_level_info->offset;
452
453 state[0] = va >> 8;
454 if (chip_class >= GFX9 ||
455 base_level_info->mode == RADEON_SURF_MODE_2D)
456 state[0] |= plane->surface.tile_swizzle;
457 state[1] &= C_008F14_BASE_ADDRESS_HI;
458 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
459
460 if (chip_class >= GFX8) {
461 state[6] &= C_008F28_COMPRESSION_EN;
462 state[7] = 0;
463 if (!is_storage_image && radv_dcc_enabled(image, first_level)) {
464 meta_va = gpu_address + image->dcc_offset;
465 if (chip_class <= GFX8)
466 meta_va += base_level_info->dcc_offset;
467 } else if (!is_storage_image &&
468 radv_image_is_tc_compat_htile(image)) {
469 meta_va = gpu_address + image->htile_offset;
470 }
471
472 if (meta_va) {
473 state[6] |= S_008F28_COMPRESSION_EN(1);
474 state[7] = meta_va >> 8;
475 state[7] |= plane->surface.tile_swizzle;
476 }
477 }
478
479 if (chip_class >= GFX9) {
480 state[3] &= C_008F1C_SW_MODE;
481 state[4] &= C_008F20_PITCH;
482
483 if (is_stencil) {
484 state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.stencil.swizzle_mode);
485 state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.stencil.epitch);
486 } else {
487 state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.surf.swizzle_mode);
488 state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.surf.epitch);
489 }
490
491 state[5] &= C_008F24_META_DATA_ADDRESS &
492 C_008F24_META_PIPE_ALIGNED &
493 C_008F24_META_RB_ALIGNED;
494 if (meta_va) {
495 struct gfx9_surf_meta_flags meta;
496
497 if (image->dcc_offset)
498 meta = plane->surface.u.gfx9.dcc;
499 else
500 meta = plane->surface.u.gfx9.htile;
501
502 state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
503 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
504 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
505 }
506 } else {
507 /* GFX6-GFX8 */
508 unsigned pitch = base_level_info->nblk_x * block_width;
509 unsigned index = si_tile_mode_index(plane, base_level, is_stencil);
510
511 state[3] &= C_008F1C_TILING_INDEX;
512 state[3] |= S_008F1C_TILING_INDEX(index);
513 state[4] &= C_008F20_PITCH;
514 state[4] |= S_008F20_PITCH(pitch - 1);
515 }
516 }
517
518 static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
519 unsigned nr_layers, unsigned nr_samples, bool is_storage_image, bool gfx9)
520 {
521 if (view_type == VK_IMAGE_VIEW_TYPE_CUBE || view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY)
522 return is_storage_image ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_CUBE;
523
524 /* GFX9 allocates 1D textures as 2D. */
525 if (gfx9 && image_type == VK_IMAGE_TYPE_1D)
526 image_type = VK_IMAGE_TYPE_2D;
527 switch (image_type) {
528 case VK_IMAGE_TYPE_1D:
529 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY : V_008F1C_SQ_RSRC_IMG_1D;
530 case VK_IMAGE_TYPE_2D:
531 if (nr_samples > 1)
532 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_MSAA;
533 else
534 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_2D;
535 case VK_IMAGE_TYPE_3D:
536 if (view_type == VK_IMAGE_VIEW_TYPE_3D)
537 return V_008F1C_SQ_RSRC_IMG_3D;
538 else
539 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
540 default:
541 unreachable("illegal image type");
542 }
543 }
544
545 static unsigned gfx9_border_color_swizzle(const enum vk_swizzle swizzle[4])
546 {
547 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
548
549 if (swizzle[3] == VK_SWIZZLE_X) {
550 /* For the pre-defined border color values (white, opaque
551 * black, transparent black), the only thing that matters is
552 * that the alpha channel winds up in the correct place
553 * (because the RGB channels are all the same) so either of
554 * these enumerations will work.
555 */
556 if (swizzle[2] == VK_SWIZZLE_Y)
557 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
558 else
559 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
560 } else if (swizzle[0] == VK_SWIZZLE_X) {
561 if (swizzle[1] == VK_SWIZZLE_Y)
562 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
563 else
564 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
565 } else if (swizzle[1] == VK_SWIZZLE_X) {
566 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
567 } else if (swizzle[2] == VK_SWIZZLE_X) {
568 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
569 }
570
571 return bc_swizzle;
572 }
573
574 /**
575 * Build the sampler view descriptor for a texture.
576 */
577 static void
578 si_make_texture_descriptor(struct radv_device *device,
579 struct radv_image *image,
580 bool is_storage_image,
581 VkImageViewType view_type,
582 VkFormat vk_format,
583 const VkComponentMapping *mapping,
584 unsigned first_level, unsigned last_level,
585 unsigned first_layer, unsigned last_layer,
586 unsigned width, unsigned height, unsigned depth,
587 uint32_t *state,
588 uint32_t *fmask_state)
589 {
590 const struct vk_format_description *desc;
591 enum vk_swizzle swizzle[4];
592 int first_non_void;
593 unsigned num_format, data_format, type;
594
595 desc = vk_format_description(vk_format);
596
597 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
598 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
599 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
600 } else {
601 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
602 }
603
604 first_non_void = vk_format_get_first_non_void_channel(vk_format);
605
606 num_format = radv_translate_tex_numformat(vk_format, desc, first_non_void);
607 if (num_format == ~0) {
608 num_format = 0;
609 }
610
611 data_format = radv_translate_tex_dataformat(vk_format, desc, first_non_void);
612 if (data_format == ~0) {
613 data_format = 0;
614 }
615
616 /* S8 with either Z16 or Z32 HTILE need a special format. */
617 if (device->physical_device->rad_info.chip_class >= GFX9 &&
618 vk_format == VK_FORMAT_S8_UINT &&
619 radv_image_is_tc_compat_htile(image)) {
620 if (image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT)
621 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
622 else if (image->vk_format == VK_FORMAT_D16_UNORM_S8_UINT)
623 data_format = V_008F14_IMG_DATA_FORMAT_S8_16;
624 }
625 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
626 is_storage_image, device->physical_device->rad_info.chip_class >= GFX9);
627 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
628 height = 1;
629 depth = image->info.array_size;
630 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
631 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
632 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
633 depth = image->info.array_size;
634 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
635 depth = image->info.array_size / 6;
636
637 state[0] = 0;
638 state[1] = (S_008F14_DATA_FORMAT(data_format) |
639 S_008F14_NUM_FORMAT(num_format));
640 state[2] = (S_008F18_WIDTH(width - 1) |
641 S_008F18_HEIGHT(height - 1) |
642 S_008F18_PERF_MOD(4));
643 state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
644 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
645 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
646 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
647 S_008F1C_BASE_LEVEL(image->info.samples > 1 ?
648 0 : first_level) |
649 S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
650 util_logbase2(image->info.samples) :
651 last_level) |
652 S_008F1C_TYPE(type));
653 state[4] = 0;
654 state[5] = S_008F24_BASE_ARRAY(first_layer);
655 state[6] = 0;
656 state[7] = 0;
657
658 if (device->physical_device->rad_info.chip_class >= GFX9) {
659 unsigned bc_swizzle = gfx9_border_color_swizzle(swizzle);
660
661 /* Depth is the last accessible layer on Gfx9.
662 * The hw doesn't need to know the total number of layers.
663 */
664 if (type == V_008F1C_SQ_RSRC_IMG_3D)
665 state[4] |= S_008F20_DEPTH(depth - 1);
666 else
667 state[4] |= S_008F20_DEPTH(last_layer);
668
669 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
670 state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ?
671 util_logbase2(image->info.samples) :
672 image->info.levels - 1);
673 } else {
674 state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
675 state[4] |= S_008F20_DEPTH(depth - 1);
676 state[5] |= S_008F24_LAST_ARRAY(last_layer);
677 }
678 if (image->dcc_offset) {
679 unsigned swap = radv_translate_colorswap(vk_format, FALSE);
680
681 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
682 } else {
683 /* The last dword is unused by hw. The shader uses it to clear
684 * bits in the first dword of sampler state.
685 */
686 if (device->physical_device->rad_info.chip_class <= GFX7 && image->info.samples <= 1) {
687 if (first_level == last_level)
688 state[7] = C_008F30_MAX_ANISO_RATIO;
689 else
690 state[7] = 0xffffffff;
691 }
692 }
693
694 /* Initialize the sampler view for FMASK. */
695 if (radv_image_has_fmask(image)) {
696 uint32_t fmask_format, num_format;
697 uint64_t gpu_address = radv_buffer_get_va(image->bo);
698 uint64_t va;
699
700 assert(image->plane_count == 1);
701
702 va = gpu_address + image->offset + image->fmask.offset;
703
704 if (device->physical_device->rad_info.chip_class >= GFX9) {
705 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
706 switch (image->info.samples) {
707 case 2:
708 num_format = V_008F14_IMG_FMASK_8_2_2;
709 break;
710 case 4:
711 num_format = V_008F14_IMG_FMASK_8_4_4;
712 break;
713 case 8:
714 num_format = V_008F14_IMG_FMASK_32_8_8;
715 break;
716 default:
717 unreachable("invalid nr_samples");
718 }
719 } else {
720 switch (image->info.samples) {
721 case 2:
722 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
723 break;
724 case 4:
725 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
726 break;
727 case 8:
728 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
729 break;
730 default:
731 assert(0);
732 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
733 }
734 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
735 }
736
737 fmask_state[0] = va >> 8;
738 fmask_state[0] |= image->fmask.tile_swizzle;
739 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
740 S_008F14_DATA_FORMAT(fmask_format) |
741 S_008F14_NUM_FORMAT(num_format);
742 fmask_state[2] = S_008F18_WIDTH(width - 1) |
743 S_008F18_HEIGHT(height - 1);
744 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
745 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
746 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
747 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
748 S_008F1C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
749 fmask_state[4] = 0;
750 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
751 fmask_state[6] = 0;
752 fmask_state[7] = 0;
753
754 if (device->physical_device->rad_info.chip_class >= GFX9) {
755 fmask_state[3] |= S_008F1C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode);
756 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
757 S_008F20_PITCH(image->planes[0].surface.u.gfx9.fmask.epitch);
758 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->planes[0].surface.u.gfx9.cmask.pipe_aligned) |
759 S_008F24_META_RB_ALIGNED(image->planes[0].surface.u.gfx9.cmask.rb_aligned);
760
761 if (radv_image_is_tc_compat_cmask(image)) {
762 va = gpu_address + image->offset + image->cmask.offset;
763
764 fmask_state[5] |= S_008F24_META_DATA_ADDRESS(va >> 40);
765 fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
766 fmask_state[7] |= va >> 8;
767 }
768 } else {
769 fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
770 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
771 S_008F20_PITCH(image->fmask.pitch_in_pixels - 1);
772 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
773
774 if (radv_image_is_tc_compat_cmask(image)) {
775 va = gpu_address + image->offset + image->cmask.offset;
776
777 fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
778 fmask_state[7] |= va >> 8;
779 }
780 }
781 } else if (fmask_state)
782 memset(fmask_state, 0, 8 * 4);
783 }
784
785 static void
786 radv_query_opaque_metadata(struct radv_device *device,
787 struct radv_image *image,
788 struct radeon_bo_metadata *md)
789 {
790 static const VkComponentMapping fixedmapping;
791 uint32_t desc[8], i;
792
793 assert(image->plane_count == 1);
794
795 /* Metadata image format format version 1:
796 * [0] = 1 (metadata format identifier)
797 * [1] = (VENDOR_ID << 16) | PCI_ID
798 * [2:9] = image descriptor for the whole resource
799 * [2] is always 0, because the base address is cleared
800 * [9] is the DCC offset bits [39:8] from the beginning of
801 * the buffer
802 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
803 */
804 md->metadata[0] = 1; /* metadata image format version 1 */
805
806 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
807 md->metadata[1] = si_get_bo_metadata_word1(device);
808
809
810 si_make_texture_descriptor(device, image, false,
811 (VkImageViewType)image->type, image->vk_format,
812 &fixedmapping, 0, image->info.levels - 1, 0,
813 image->info.array_size - 1,
814 image->info.width, image->info.height,
815 image->info.depth,
816 desc, NULL);
817
818 si_set_mutable_tex_desc_fields(device, image, &image->planes[0].surface.u.legacy.level[0], 0, 0, 0,
819 image->planes[0].surface.blk_w, false, false, desc);
820
821 /* Clear the base address and set the relative DCC offset. */
822 desc[0] = 0;
823 desc[1] &= C_008F14_BASE_ADDRESS_HI;
824 desc[7] = image->dcc_offset >> 8;
825
826 /* Dwords [2:9] contain the image descriptor. */
827 memcpy(&md->metadata[2], desc, sizeof(desc));
828
829 /* Dwords [10:..] contain the mipmap level offsets. */
830 if (device->physical_device->rad_info.chip_class <= GFX8) {
831 for (i = 0; i <= image->info.levels - 1; i++)
832 md->metadata[10+i] = image->planes[0].surface.u.legacy.level[i].offset >> 8;
833 md->size_metadata = (11 + image->info.levels - 1) * 4;
834 }
835 }
836
837 void
838 radv_init_metadata(struct radv_device *device,
839 struct radv_image *image,
840 struct radeon_bo_metadata *metadata)
841 {
842 struct radeon_surf *surface = &image->planes[0].surface;
843
844 memset(metadata, 0, sizeof(*metadata));
845
846 if (device->physical_device->rad_info.chip_class >= GFX9) {
847 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
848 } else {
849 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
850 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
851 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
852 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
853 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
854 metadata->u.legacy.bankw = surface->u.legacy.bankw;
855 metadata->u.legacy.bankh = surface->u.legacy.bankh;
856 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
857 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
858 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
859 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
860 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
861 }
862 radv_query_opaque_metadata(device, image, metadata);
863 }
864
865 void
866 radv_image_override_offset_stride(struct radv_device *device,
867 struct radv_image *image,
868 uint64_t offset, uint32_t stride)
869 {
870 struct radeon_surf *surface = &image->planes[0].surface;
871 unsigned bpe = vk_format_get_blocksizebits(image->vk_format) / 8;
872
873 if (device->physical_device->rad_info.chip_class >= GFX9) {
874 if (stride) {
875 surface->u.gfx9.surf_pitch = stride;
876 surface->u.gfx9.surf_slice_size =
877 (uint64_t)stride * surface->u.gfx9.surf_height * bpe;
878 }
879 surface->u.gfx9.surf_offset = offset;
880 } else {
881 surface->u.legacy.level[0].nblk_x = stride;
882 surface->u.legacy.level[0].slice_size_dw =
883 ((uint64_t)stride * surface->u.legacy.level[0].nblk_y * bpe) / 4;
884
885 if (offset) {
886 for (unsigned i = 0; i < ARRAY_SIZE(surface->u.legacy.level); ++i)
887 surface->u.legacy.level[i].offset += offset;
888 }
889
890 }
891 }
892
893 /* The number of samples can be specified independently of the texture. */
894 static void
895 radv_image_get_fmask_info(struct radv_device *device,
896 struct radv_image *image,
897 unsigned nr_samples,
898 struct radv_fmask_info *out)
899 {
900 if (device->physical_device->rad_info.chip_class >= GFX9) {
901 out->alignment = image->planes[0].surface.fmask_alignment;
902 out->size = image->planes[0].surface.fmask_size;
903 out->tile_swizzle = image->planes[0].surface.fmask_tile_swizzle;
904 return;
905 }
906
907 out->slice_tile_max = image->planes[0].surface.u.legacy.fmask.slice_tile_max;
908 out->tile_mode_index = image->planes[0].surface.u.legacy.fmask.tiling_index;
909 out->pitch_in_pixels = image->planes[0].surface.u.legacy.fmask.pitch_in_pixels;
910 out->slice_size = image->planes[0].surface.u.legacy.fmask.slice_size;
911 out->bank_height = image->planes[0].surface.u.legacy.fmask.bankh;
912 out->tile_swizzle = image->planes[0].surface.fmask_tile_swizzle;
913 out->alignment = image->planes[0].surface.fmask_alignment;
914 out->size = image->planes[0].surface.fmask_size;
915
916 assert(!out->tile_swizzle || !image->shareable);
917 }
918
919 static void
920 radv_image_alloc_fmask(struct radv_device *device,
921 struct radv_image *image)
922 {
923 radv_image_get_fmask_info(device, image, image->info.samples, &image->fmask);
924
925 image->fmask.offset = align64(image->size, image->fmask.alignment);
926 image->size = image->fmask.offset + image->fmask.size;
927 image->alignment = MAX2(image->alignment, image->fmask.alignment);
928 }
929
930 static void
931 radv_image_get_cmask_info(struct radv_device *device,
932 struct radv_image *image,
933 struct radv_cmask_info *out)
934 {
935 assert(image->plane_count == 1);
936
937 if (device->physical_device->rad_info.chip_class >= GFX9) {
938 out->alignment = image->planes[0].surface.cmask_alignment;
939 out->size = image->planes[0].surface.cmask_size;
940 return;
941 }
942
943 out->slice_tile_max = image->planes[0].surface.u.legacy.cmask_slice_tile_max;
944 out->alignment = image->planes[0].surface.cmask_alignment;
945 out->slice_size = image->planes[0].surface.cmask_slice_size;
946 out->size = image->planes[0].surface.cmask_size;
947 }
948
949 static void
950 radv_image_alloc_cmask(struct radv_device *device,
951 struct radv_image *image)
952 {
953 uint32_t clear_value_size = 0;
954 radv_image_get_cmask_info(device, image, &image->cmask);
955
956 image->cmask.offset = align64(image->size, image->cmask.alignment);
957 /* + 8 for storing the clear values */
958 if (!image->clear_value_offset) {
959 image->clear_value_offset = image->cmask.offset + image->cmask.size;
960 clear_value_size = 8;
961 }
962 image->size = image->cmask.offset + image->cmask.size + clear_value_size;
963 image->alignment = MAX2(image->alignment, image->cmask.alignment);
964 }
965
966 static void
967 radv_image_alloc_dcc(struct radv_image *image)
968 {
969 assert(image->plane_count == 1);
970
971 image->dcc_offset = align64(image->size, image->planes[0].surface.dcc_alignment);
972 /* + 24 for storing the clear values + fce pred + dcc pred for each mip */
973 image->clear_value_offset = image->dcc_offset + image->planes[0].surface.dcc_size;
974 image->fce_pred_offset = image->clear_value_offset + 8 * image->info.levels;
975 image->dcc_pred_offset = image->clear_value_offset + 16 * image->info.levels;
976 image->size = image->dcc_offset + image->planes[0].surface.dcc_size + 24 * image->info.levels;
977 image->alignment = MAX2(image->alignment, image->planes[0].surface.dcc_alignment);
978 }
979
980 static void
981 radv_image_alloc_htile(struct radv_image *image)
982 {
983 image->htile_offset = align64(image->size, image->planes[0].surface.htile_alignment);
984
985 /* + 8 for storing the clear values */
986 image->clear_value_offset = image->htile_offset + image->planes[0].surface.htile_size;
987 image->size = image->clear_value_offset + 8;
988 if (radv_image_is_tc_compat_htile(image)) {
989 /* Metadata for the TC-compatible HTILE hardware bug which
990 * have to be fixed by updating ZRANGE_PRECISION when doing
991 * fast depth clears to 0.0f.
992 */
993 image->tc_compat_zrange_offset = image->clear_value_offset + 8;
994 image->size = image->clear_value_offset + 16;
995 }
996 image->alignment = align64(image->alignment, image->planes[0].surface.htile_alignment);
997 }
998
999 static inline bool
1000 radv_image_can_enable_dcc_or_cmask(struct radv_image *image)
1001 {
1002 if (image->info.samples <= 1 &&
1003 image->info.width * image->info.height <= 512 * 512) {
1004 /* Do not enable CMASK or DCC for small surfaces where the cost
1005 * of the eliminate pass can be higher than the benefit of fast
1006 * clear. RadeonSI does this, but the image threshold is
1007 * different.
1008 */
1009 return false;
1010 }
1011
1012 return image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT &&
1013 (image->exclusive || image->queue_family_mask == 1);
1014 }
1015
1016 static inline bool
1017 radv_image_can_enable_dcc(struct radv_image *image)
1018 {
1019 return radv_image_can_enable_dcc_or_cmask(image) &&
1020 radv_image_has_dcc(image);
1021 }
1022
1023 static inline bool
1024 radv_image_can_enable_cmask(struct radv_image *image)
1025 {
1026 if (image->planes[0].surface.bpe > 8 && image->info.samples == 1) {
1027 /* Do not enable CMASK for non-MSAA images (fast color clear)
1028 * because 128 bit formats are not supported, but FMASK might
1029 * still be used.
1030 */
1031 return false;
1032 }
1033
1034 return radv_image_can_enable_dcc_or_cmask(image) &&
1035 image->info.levels == 1 &&
1036 image->info.depth == 1 &&
1037 !image->planes[0].surface.is_linear;
1038 }
1039
1040 static inline bool
1041 radv_image_can_enable_fmask(struct radv_image *image)
1042 {
1043 return image->info.samples > 1 && vk_format_is_color(image->vk_format);
1044 }
1045
1046 static inline bool
1047 radv_image_can_enable_htile(struct radv_image *image)
1048 {
1049 return radv_image_has_htile(image) &&
1050 image->info.levels == 1 &&
1051 image->info.width * image->info.height >= 8 * 8;
1052 }
1053
1054 static void radv_image_disable_dcc(struct radv_image *image)
1055 {
1056 for (unsigned i = 0; i < image->plane_count; ++i)
1057 image->planes[i].surface.dcc_size = 0;
1058 }
1059
1060 static void radv_image_disable_htile(struct radv_image *image)
1061 {
1062 for (unsigned i = 0; i < image->plane_count; ++i)
1063 image->planes[i].surface.htile_size = 0;
1064 }
1065
1066 VkResult
1067 radv_image_create(VkDevice _device,
1068 const struct radv_image_create_info *create_info,
1069 const VkAllocationCallbacks* alloc,
1070 VkImage *pImage)
1071 {
1072 RADV_FROM_HANDLE(radv_device, device, _device);
1073 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
1074 struct radv_image *image = NULL;
1075 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
1076
1077 const unsigned plane_count = vk_format_get_plane_count(pCreateInfo->format);
1078 const size_t image_struct_size = sizeof(*image) + sizeof(struct radv_image_plane) * plane_count;
1079
1080 radv_assert(pCreateInfo->mipLevels > 0);
1081 radv_assert(pCreateInfo->arrayLayers > 0);
1082 radv_assert(pCreateInfo->samples > 0);
1083 radv_assert(pCreateInfo->extent.width > 0);
1084 radv_assert(pCreateInfo->extent.height > 0);
1085 radv_assert(pCreateInfo->extent.depth > 0);
1086
1087 image = vk_zalloc2(&device->alloc, alloc, image_struct_size, 8,
1088 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1089 if (!image)
1090 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1091
1092 image->type = pCreateInfo->imageType;
1093 image->info.width = pCreateInfo->extent.width;
1094 image->info.height = pCreateInfo->extent.height;
1095 image->info.depth = pCreateInfo->extent.depth;
1096 image->info.samples = pCreateInfo->samples;
1097 image->info.storage_samples = pCreateInfo->samples;
1098 image->info.array_size = pCreateInfo->arrayLayers;
1099 image->info.levels = pCreateInfo->mipLevels;
1100 image->info.num_channels = vk_format_get_nr_components(pCreateInfo->format);
1101
1102 image->vk_format = pCreateInfo->format;
1103 image->tiling = pCreateInfo->tiling;
1104 image->usage = pCreateInfo->usage;
1105 image->flags = pCreateInfo->flags;
1106
1107 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
1108 if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
1109 for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
1110 if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL)
1111 image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1112 else
1113 image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
1114 }
1115
1116 image->shareable = vk_find_struct_const(pCreateInfo->pNext,
1117 EXTERNAL_MEMORY_IMAGE_CREATE_INFO) != NULL;
1118 if (!vk_format_is_depth_or_stencil(pCreateInfo->format) &&
1119 !radv_surface_has_scanout(device, create_info) && !image->shareable) {
1120 image->info.surf_index = &device->image_mrt_offset_counter;
1121 }
1122
1123 image->plane_count = plane_count;
1124 image->size = 0;
1125 image->alignment = 1;
1126 for (unsigned plane = 0; plane < plane_count; ++plane) {
1127 struct ac_surf_info info = image->info;
1128 radv_init_surface(device, image, &image->planes[plane].surface, plane, create_info);
1129
1130 if (plane) {
1131 const struct vk_format_description *desc = vk_format_description(pCreateInfo->format);
1132 assert(info.width % desc->width_divisor == 0);
1133 assert(info.height % desc->height_divisor == 0);
1134
1135 info.width /= desc->width_divisor;
1136 info.height /= desc->height_divisor;
1137 }
1138
1139 device->ws->surface_init(device->ws, &info, &image->planes[plane].surface);
1140
1141 image->planes[plane].offset = align(image->size, image->planes[plane].surface.surf_alignment);
1142 image->size = image->planes[plane].offset + image->planes[plane].surface.surf_size;
1143 image->alignment = image->planes[plane].surface.surf_alignment;
1144
1145 image->planes[plane].format = vk_format_get_plane_format(image->vk_format, plane);
1146 }
1147
1148 if (!create_info->no_metadata_planes) {
1149 /* Try to enable DCC first. */
1150 if (radv_image_can_enable_dcc(image)) {
1151 radv_image_alloc_dcc(image);
1152 if (image->info.samples > 1) {
1153 /* CMASK should be enabled because DCC fast
1154 * clear with MSAA needs it.
1155 */
1156 assert(radv_image_can_enable_cmask(image));
1157 radv_image_alloc_cmask(device, image);
1158 }
1159 } else {
1160 /* When DCC cannot be enabled, try CMASK. */
1161 radv_image_disable_dcc(image);
1162 if (radv_image_can_enable_cmask(image)) {
1163 radv_image_alloc_cmask(device, image);
1164 }
1165 }
1166
1167 /* Try to enable FMASK for multisampled images. */
1168 if (radv_image_can_enable_fmask(image)) {
1169 radv_image_alloc_fmask(device, image);
1170
1171 if (radv_use_tc_compat_cmask_for_image(device, image))
1172 image->tc_compatible_cmask = true;
1173 } else {
1174 /* Otherwise, try to enable HTILE for depth surfaces. */
1175 if (radv_image_can_enable_htile(image) &&
1176 !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
1177 image->tc_compatible_htile = image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1178 radv_image_alloc_htile(image);
1179 } else {
1180 radv_image_disable_htile(image);
1181 }
1182 }
1183 } else {
1184 radv_image_disable_dcc(image);
1185 radv_image_disable_htile(image);
1186 }
1187
1188 if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
1189 image->alignment = MAX2(image->alignment, 4096);
1190 image->size = align64(image->size, image->alignment);
1191 image->offset = 0;
1192
1193 image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
1194 0, RADEON_FLAG_VIRTUAL, RADV_BO_PRIORITY_VIRTUAL);
1195 if (!image->bo) {
1196 vk_free2(&device->alloc, alloc, image);
1197 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
1198 }
1199 }
1200
1201 *pImage = radv_image_to_handle(image);
1202
1203 return VK_SUCCESS;
1204 }
1205
1206 static void
1207 radv_image_view_make_descriptor(struct radv_image_view *iview,
1208 struct radv_device *device,
1209 VkFormat vk_format,
1210 const VkComponentMapping *components,
1211 bool is_storage_image, unsigned plane_id,
1212 unsigned descriptor_plane_id)
1213 {
1214 struct radv_image *image = iview->image;
1215 struct radv_image_plane *plane = &image->planes[plane_id];
1216 const struct vk_format_description *format_desc = vk_format_description(image->vk_format);
1217 bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
1218 uint32_t blk_w;
1219 union radv_descriptor *descriptor;
1220 uint32_t hw_level = 0;
1221
1222 if (is_storage_image) {
1223 descriptor = &iview->storage_descriptor;
1224 } else {
1225 descriptor = &iview->descriptor;
1226 }
1227
1228 assert(vk_format_get_plane_count(vk_format) == 1);
1229 assert(plane->surface.blk_w % vk_format_get_blockwidth(plane->format) == 0);
1230 blk_w = plane->surface.blk_w / vk_format_get_blockwidth(plane->format) * vk_format_get_blockwidth(vk_format);
1231
1232 if (device->physical_device->rad_info.chip_class >= GFX9)
1233 hw_level = iview->base_mip;
1234 si_make_texture_descriptor(device, image, is_storage_image,
1235 iview->type,
1236 vk_format,
1237 components,
1238 hw_level, hw_level + iview->level_count - 1,
1239 iview->base_layer,
1240 iview->base_layer + iview->layer_count - 1,
1241 iview->extent.width / (plane_id ? format_desc->width_divisor : 1),
1242 iview->extent.height / (plane_id ? format_desc->height_divisor : 1),
1243 iview->extent.depth,
1244 descriptor->plane_descriptors[descriptor_plane_id],
1245 descriptor_plane_id ? NULL : descriptor->fmask_descriptor);
1246
1247 const struct legacy_surf_level *base_level_info = NULL;
1248 if (device->physical_device->rad_info.chip_class <= GFX9) {
1249 if (is_stencil)
1250 base_level_info = &plane->surface.u.legacy.stencil_level[iview->base_mip];
1251 else
1252 base_level_info = &plane->surface.u.legacy.level[iview->base_mip];
1253 }
1254 si_set_mutable_tex_desc_fields(device, image,
1255 base_level_info,
1256 plane_id,
1257 iview->base_mip,
1258 iview->base_mip,
1259 blk_w, is_stencil, is_storage_image, descriptor->plane_descriptors[descriptor_plane_id]);
1260 }
1261
1262 static unsigned
1263 radv_plane_from_aspect(VkImageAspectFlags mask)
1264 {
1265 switch(mask) {
1266 case VK_IMAGE_ASPECT_PLANE_1_BIT:
1267 return 1;
1268 case VK_IMAGE_ASPECT_PLANE_2_BIT:
1269 return 2;
1270 default:
1271 return 0;
1272 }
1273 }
1274
1275 VkFormat
1276 radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask)
1277 {
1278 switch(mask) {
1279 case VK_IMAGE_ASPECT_PLANE_0_BIT:
1280 return image->planes[0].format;
1281 case VK_IMAGE_ASPECT_PLANE_1_BIT:
1282 return image->planes[1].format;
1283 case VK_IMAGE_ASPECT_PLANE_2_BIT:
1284 return image->planes[2].format;
1285 case VK_IMAGE_ASPECT_STENCIL_BIT:
1286 return vk_format_stencil_only(image->vk_format);
1287 case VK_IMAGE_ASPECT_DEPTH_BIT:
1288 return vk_format_depth_only(image->vk_format);
1289 case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
1290 return vk_format_depth_only(image->vk_format);
1291 default:
1292 return image->vk_format;
1293 }
1294 }
1295
1296 void
1297 radv_image_view_init(struct radv_image_view *iview,
1298 struct radv_device *device,
1299 const VkImageViewCreateInfo* pCreateInfo)
1300 {
1301 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
1302 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
1303
1304 switch (image->type) {
1305 case VK_IMAGE_TYPE_1D:
1306 case VK_IMAGE_TYPE_2D:
1307 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size);
1308 break;
1309 case VK_IMAGE_TYPE_3D:
1310 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
1311 <= radv_minify(image->info.depth, range->baseMipLevel));
1312 break;
1313 default:
1314 unreachable("bad VkImageType");
1315 }
1316 iview->image = image;
1317 iview->bo = image->bo;
1318 iview->type = pCreateInfo->viewType;
1319 iview->plane_id = radv_plane_from_aspect(pCreateInfo->subresourceRange.aspectMask);
1320 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
1321 iview->multiple_planes = vk_format_get_plane_count(image->vk_format) > 1 && iview->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT;
1322 iview->vk_format = pCreateInfo->format;
1323
1324 if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
1325 iview->vk_format = vk_format_stencil_only(iview->vk_format);
1326 } else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
1327 iview->vk_format = vk_format_depth_only(iview->vk_format);
1328 }
1329
1330 if (device->physical_device->rad_info.chip_class >= GFX9) {
1331 iview->extent = (VkExtent3D) {
1332 .width = image->info.width,
1333 .height = image->info.height,
1334 .depth = image->info.depth,
1335 };
1336 } else {
1337 iview->extent = (VkExtent3D) {
1338 .width = radv_minify(image->info.width , range->baseMipLevel),
1339 .height = radv_minify(image->info.height, range->baseMipLevel),
1340 .depth = radv_minify(image->info.depth , range->baseMipLevel),
1341 };
1342 }
1343
1344 if (iview->vk_format != image->planes[iview->plane_id].format) {
1345 unsigned view_bw = vk_format_get_blockwidth(iview->vk_format);
1346 unsigned view_bh = vk_format_get_blockheight(iview->vk_format);
1347 unsigned img_bw = vk_format_get_blockwidth(image->vk_format);
1348 unsigned img_bh = vk_format_get_blockheight(image->vk_format);
1349
1350 iview->extent.width = round_up_u32(iview->extent.width * view_bw, img_bw);
1351 iview->extent.height = round_up_u32(iview->extent.height * view_bh, img_bh);
1352
1353 /* Comment ported from amdvlk -
1354 * If we have the following image:
1355 * Uncompressed pixels Compressed block sizes (4x4)
1356 * mip0: 22 x 22 6 x 6
1357 * mip1: 11 x 11 3 x 3
1358 * mip2: 5 x 5 2 x 2
1359 * mip3: 2 x 2 1 x 1
1360 * mip4: 1 x 1 1 x 1
1361 *
1362 * On GFX9 the descriptor is always programmed with the WIDTH and HEIGHT of the base level and the HW is
1363 * calculating the degradation of the block sizes down the mip-chain as follows (straight-up
1364 * divide-by-two integer math):
1365 * mip0: 6x6
1366 * mip1: 3x3
1367 * mip2: 1x1
1368 * mip3: 1x1
1369 *
1370 * This means that mip2 will be missing texels.
1371 *
1372 * Fix this by calculating the base mip's width and height, then convert that, and round it
1373 * back up to get the level 0 size.
1374 * Clamp the converted size between the original values, and next power of two, which
1375 * means we don't oversize the image.
1376 */
1377 if (device->physical_device->rad_info.chip_class >= GFX9 &&
1378 vk_format_is_compressed(image->vk_format) &&
1379 !vk_format_is_compressed(iview->vk_format)) {
1380 unsigned lvl_width = radv_minify(image->info.width , range->baseMipLevel);
1381 unsigned lvl_height = radv_minify(image->info.height, range->baseMipLevel);
1382
1383 lvl_width = round_up_u32(lvl_width * view_bw, img_bw);
1384 lvl_height = round_up_u32(lvl_height * view_bh, img_bh);
1385
1386 lvl_width <<= range->baseMipLevel;
1387 lvl_height <<= range->baseMipLevel;
1388
1389 iview->extent.width = CLAMP(lvl_width, iview->extent.width, iview->image->planes[0].surface.u.gfx9.surf_pitch);
1390 iview->extent.height = CLAMP(lvl_height, iview->extent.height, iview->image->planes[0].surface.u.gfx9.surf_height);
1391 }
1392 }
1393
1394 iview->base_layer = range->baseArrayLayer;
1395 iview->layer_count = radv_get_layerCount(image, range);
1396 iview->base_mip = range->baseMipLevel;
1397 iview->level_count = radv_get_levelCount(image, range);
1398
1399 for (unsigned i = 0; i < (iview->multiple_planes ? vk_format_get_plane_count(image->vk_format) : 1); ++i) {
1400 VkFormat format = vk_format_get_plane_format(iview->vk_format, i);
1401 radv_image_view_make_descriptor(iview, device, format, &pCreateInfo->components, false, iview->plane_id + i, i);
1402 radv_image_view_make_descriptor(iview, device, format, &pCreateInfo->components, true, iview->plane_id + i, i);
1403 }
1404 }
1405
1406 bool radv_layout_has_htile(const struct radv_image *image,
1407 VkImageLayout layout,
1408 unsigned queue_mask)
1409 {
1410 if (radv_image_is_tc_compat_htile(image))
1411 return layout != VK_IMAGE_LAYOUT_GENERAL;
1412
1413 return radv_image_has_htile(image) &&
1414 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1415 (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1416 queue_mask == (1u << RADV_QUEUE_GENERAL)));
1417 }
1418
1419 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1420 VkImageLayout layout,
1421 unsigned queue_mask)
1422 {
1423 if (radv_image_is_tc_compat_htile(image))
1424 return layout != VK_IMAGE_LAYOUT_GENERAL;
1425
1426 return radv_image_has_htile(image) &&
1427 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1428 (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1429 queue_mask == (1u << RADV_QUEUE_GENERAL)));
1430 }
1431
1432 bool radv_layout_can_fast_clear(const struct radv_image *image,
1433 VkImageLayout layout,
1434 unsigned queue_mask)
1435 {
1436 return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
1437 }
1438
1439 bool radv_layout_dcc_compressed(const struct radv_image *image,
1440 VkImageLayout layout,
1441 unsigned queue_mask)
1442 {
1443 /* Don't compress compute transfer dst, as image stores are not supported. */
1444 if (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1445 (queue_mask & (1u << RADV_QUEUE_COMPUTE)))
1446 return false;
1447
1448 return radv_image_has_dcc(image) && layout != VK_IMAGE_LAYOUT_GENERAL;
1449 }
1450
1451
1452 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
1453 {
1454 if (!image->exclusive)
1455 return image->queue_family_mask;
1456 if (family == VK_QUEUE_FAMILY_EXTERNAL)
1457 return (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1458 if (family == VK_QUEUE_FAMILY_IGNORED)
1459 return 1u << queue_family;
1460 return 1u << family;
1461 }
1462
1463 VkResult
1464 radv_CreateImage(VkDevice device,
1465 const VkImageCreateInfo *pCreateInfo,
1466 const VkAllocationCallbacks *pAllocator,
1467 VkImage *pImage)
1468 {
1469 #ifdef ANDROID
1470 const VkNativeBufferANDROID *gralloc_info =
1471 vk_find_struct_const(pCreateInfo->pNext, NATIVE_BUFFER_ANDROID);
1472
1473 if (gralloc_info)
1474 return radv_image_from_gralloc(device, pCreateInfo, gralloc_info,
1475 pAllocator, pImage);
1476 #endif
1477
1478 const struct wsi_image_create_info *wsi_info =
1479 vk_find_struct_const(pCreateInfo->pNext, WSI_IMAGE_CREATE_INFO_MESA);
1480 bool scanout = wsi_info && wsi_info->scanout;
1481
1482 return radv_image_create(device,
1483 &(struct radv_image_create_info) {
1484 .vk_info = pCreateInfo,
1485 .scanout = scanout,
1486 },
1487 pAllocator,
1488 pImage);
1489 }
1490
1491 void
1492 radv_DestroyImage(VkDevice _device, VkImage _image,
1493 const VkAllocationCallbacks *pAllocator)
1494 {
1495 RADV_FROM_HANDLE(radv_device, device, _device);
1496 RADV_FROM_HANDLE(radv_image, image, _image);
1497
1498 if (!image)
1499 return;
1500
1501 if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
1502 device->ws->buffer_destroy(image->bo);
1503
1504 if (image->owned_memory != VK_NULL_HANDLE)
1505 radv_FreeMemory(_device, image->owned_memory, pAllocator);
1506
1507 vk_free2(&device->alloc, pAllocator, image);
1508 }
1509
1510 void radv_GetImageSubresourceLayout(
1511 VkDevice _device,
1512 VkImage _image,
1513 const VkImageSubresource* pSubresource,
1514 VkSubresourceLayout* pLayout)
1515 {
1516 RADV_FROM_HANDLE(radv_image, image, _image);
1517 RADV_FROM_HANDLE(radv_device, device, _device);
1518 int level = pSubresource->mipLevel;
1519 int layer = pSubresource->arrayLayer;
1520
1521 unsigned plane_id = radv_plane_from_aspect(pSubresource->aspectMask);
1522
1523 struct radv_image_plane *plane = &image->planes[plane_id];
1524 struct radeon_surf *surface = &plane->surface;
1525
1526 if (device->physical_device->rad_info.chip_class >= GFX9) {
1527 pLayout->offset = plane->offset + surface->u.gfx9.offset[level] + surface->u.gfx9.surf_slice_size * layer;
1528 if (image->vk_format == VK_FORMAT_R32G32B32_UINT ||
1529 image->vk_format == VK_FORMAT_R32G32B32_SINT ||
1530 image->vk_format == VK_FORMAT_R32G32B32_SFLOAT) {
1531 /* Adjust the number of bytes between each row because
1532 * the pitch is actually the number of components per
1533 * row.
1534 */
1535 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe / 3;
1536 } else {
1537 assert(util_is_power_of_two_nonzero(surface->bpe));
1538 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe;
1539 }
1540
1541 pLayout->arrayPitch = surface->u.gfx9.surf_slice_size;
1542 pLayout->depthPitch = surface->u.gfx9.surf_slice_size;
1543 pLayout->size = surface->u.gfx9.surf_slice_size;
1544 if (image->type == VK_IMAGE_TYPE_3D)
1545 pLayout->size *= u_minify(image->info.depth, level);
1546 } else {
1547 pLayout->offset = plane->offset + surface->u.legacy.level[level].offset + (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4 * layer;
1548 pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
1549 pLayout->arrayPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1550 pLayout->depthPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1551 pLayout->size = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1552 if (image->type == VK_IMAGE_TYPE_3D)
1553 pLayout->size *= u_minify(image->info.depth, level);
1554 }
1555 }
1556
1557
1558 VkResult
1559 radv_CreateImageView(VkDevice _device,
1560 const VkImageViewCreateInfo *pCreateInfo,
1561 const VkAllocationCallbacks *pAllocator,
1562 VkImageView *pView)
1563 {
1564 RADV_FROM_HANDLE(radv_device, device, _device);
1565 struct radv_image_view *view;
1566
1567 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1568 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1569 if (view == NULL)
1570 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1571
1572 radv_image_view_init(view, device, pCreateInfo);
1573
1574 *pView = radv_image_view_to_handle(view);
1575
1576 return VK_SUCCESS;
1577 }
1578
1579 void
1580 radv_DestroyImageView(VkDevice _device, VkImageView _iview,
1581 const VkAllocationCallbacks *pAllocator)
1582 {
1583 RADV_FROM_HANDLE(radv_device, device, _device);
1584 RADV_FROM_HANDLE(radv_image_view, iview, _iview);
1585
1586 if (!iview)
1587 return;
1588 vk_free2(&device->alloc, pAllocator, iview);
1589 }
1590
1591 void radv_buffer_view_init(struct radv_buffer_view *view,
1592 struct radv_device *device,
1593 const VkBufferViewCreateInfo* pCreateInfo)
1594 {
1595 RADV_FROM_HANDLE(radv_buffer, buffer, pCreateInfo->buffer);
1596
1597 view->bo = buffer->bo;
1598 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
1599 buffer->size - pCreateInfo->offset : pCreateInfo->range;
1600 view->vk_format = pCreateInfo->format;
1601
1602 radv_make_buffer_descriptor(device, buffer, view->vk_format,
1603 pCreateInfo->offset, view->range, view->state);
1604 }
1605
1606 VkResult
1607 radv_CreateBufferView(VkDevice _device,
1608 const VkBufferViewCreateInfo *pCreateInfo,
1609 const VkAllocationCallbacks *pAllocator,
1610 VkBufferView *pView)
1611 {
1612 RADV_FROM_HANDLE(radv_device, device, _device);
1613 struct radv_buffer_view *view;
1614
1615 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1616 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1617 if (!view)
1618 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1619
1620 radv_buffer_view_init(view, device, pCreateInfo);
1621
1622 *pView = radv_buffer_view_to_handle(view);
1623
1624 return VK_SUCCESS;
1625 }
1626
1627 void
1628 radv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
1629 const VkAllocationCallbacks *pAllocator)
1630 {
1631 RADV_FROM_HANDLE(radv_device, device, _device);
1632 RADV_FROM_HANDLE(radv_buffer_view, view, bufferView);
1633
1634 if (!view)
1635 return;
1636
1637 vk_free2(&device->alloc, pAllocator, view);
1638 }