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radv: Add device argument for dcc compression check.
[mesa.git] / src / amd / vulkan / radv_image.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "vk_format.h"
31 #include "vk_util.h"
32 #include "radv_radeon_winsys.h"
33 #include "sid.h"
34 #include "util/debug.h"
35 #include "util/u_atomic.h"
36
37 static unsigned
38 radv_choose_tiling(struct radv_device *device,
39 const struct radv_image_create_info *create_info)
40 {
41 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
42
43 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) {
44 assert(pCreateInfo->samples <= 1);
45 return RADEON_SURF_MODE_LINEAR_ALIGNED;
46 }
47
48 if (!vk_format_is_compressed(pCreateInfo->format) &&
49 !vk_format_is_depth_or_stencil(pCreateInfo->format)
50 && device->physical_device->rad_info.chip_class <= GFX8) {
51 /* this causes hangs in some VK CTS tests on GFX9. */
52 /* Textures with a very small height are recommended to be linear. */
53 if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
54 /* Only very thin and long 2D textures should benefit from
55 * linear_aligned. */
56 (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
57 return RADEON_SURF_MODE_LINEAR_ALIGNED;
58 }
59
60 /* MSAA resources must be 2D tiled. */
61 if (pCreateInfo->samples > 1)
62 return RADEON_SURF_MODE_2D;
63
64 return RADEON_SURF_MODE_2D;
65 }
66
67 static bool
68 radv_use_tc_compat_htile_for_image(struct radv_device *device,
69 const VkImageCreateInfo *pCreateInfo)
70 {
71 /* TC-compat HTILE is only available for GFX8+. */
72 if (device->physical_device->rad_info.chip_class < GFX8)
73 return false;
74
75 if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
76 (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
77 return false;
78
79 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
80 return false;
81
82 if (pCreateInfo->mipLevels > 1)
83 return false;
84
85 /* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
86 * tests - disable for now. On GFX10 D32_SFLOAT is affected as well.
87 */
88 if (pCreateInfo->samples >= 2 &&
89 (pCreateInfo->format == VK_FORMAT_D32_SFLOAT_S8_UINT ||
90 (pCreateInfo->format == VK_FORMAT_D32_SFLOAT &&
91 device->physical_device->rad_info.chip_class == GFX10)))
92 return false;
93
94 /* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only
95 * supports 32-bit. Though, it's possible to enable TC-compat for
96 * 16-bit depth surfaces if no Z planes are compressed.
97 */
98 if (pCreateInfo->format != VK_FORMAT_D32_SFLOAT_S8_UINT &&
99 pCreateInfo->format != VK_FORMAT_D32_SFLOAT &&
100 pCreateInfo->format != VK_FORMAT_D16_UNORM)
101 return false;
102
103 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
104 const struct VkImageFormatListCreateInfoKHR *format_list =
105 (const struct VkImageFormatListCreateInfoKHR *)
106 vk_find_struct_const(pCreateInfo->pNext,
107 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
108
109 /* We have to ignore the existence of the list if viewFormatCount = 0 */
110 if (format_list && format_list->viewFormatCount) {
111 /* compatibility is transitive, so we only need to check
112 * one format with everything else.
113 */
114 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
115 if (format_list->pViewFormats[i] == VK_FORMAT_UNDEFINED)
116 continue;
117
118 if (pCreateInfo->format != format_list->pViewFormats[i])
119 return false;
120 }
121 } else {
122 return false;
123 }
124 }
125
126 return true;
127 }
128
129 static bool
130 radv_surface_has_scanout(struct radv_device *device, const struct radv_image_create_info *info)
131 {
132 if (info->scanout)
133 return true;
134
135 if (!info->bo_metadata)
136 return false;
137
138 if (device->physical_device->rad_info.chip_class >= GFX9) {
139 return info->bo_metadata->u.gfx9.swizzle_mode == 0 || info->bo_metadata->u.gfx9.swizzle_mode % 4 == 2;
140 } else {
141 return info->bo_metadata->u.legacy.scanout;
142 }
143 }
144
145 static bool
146 radv_use_dcc_for_image(struct radv_device *device,
147 const struct radv_image *image,
148 const struct radv_image_create_info *create_info,
149 const VkImageCreateInfo *pCreateInfo)
150 {
151 bool dcc_compatible_formats;
152 bool blendable;
153
154 /* DCC (Delta Color Compression) is only available for GFX8+. */
155 if (device->physical_device->rad_info.chip_class < GFX8)
156 return false;
157
158 if (device->instance->debug_flags & RADV_DEBUG_NO_DCC)
159 return false;
160
161 if (image->shareable)
162 return false;
163
164 /* TODO: Enable DCC for storage images. */
165 if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
166 (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
167 return false;
168
169 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
170 return false;
171
172 if (vk_format_is_subsampled(pCreateInfo->format) ||
173 vk_format_get_plane_count(pCreateInfo->format) > 1)
174 return false;
175
176 /* TODO: Enable DCC for mipmaps on GFX9+. */
177 if ((pCreateInfo->arrayLayers > 1 || pCreateInfo->mipLevels > 1) &&
178 device->physical_device->rad_info.chip_class >= GFX9)
179 return false;
180
181 /* Do not enable DCC for mipmapped arrays because performance is worse. */
182 if (pCreateInfo->arrayLayers > 1 && pCreateInfo->mipLevels > 1)
183 return false;
184
185 if (radv_surface_has_scanout(device, create_info))
186 return false;
187
188 /* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet, while
189 * 2x can be enabled with an option.
190 */
191 if (pCreateInfo->samples > 2 ||
192 (pCreateInfo->samples == 2 &&
193 !device->physical_device->dcc_msaa_allowed))
194 return false;
195
196 /* Determine if the formats are DCC compatible. */
197 dcc_compatible_formats =
198 radv_is_colorbuffer_format_supported(pCreateInfo->format,
199 &blendable);
200
201 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
202 const struct VkImageFormatListCreateInfoKHR *format_list =
203 (const struct VkImageFormatListCreateInfoKHR *)
204 vk_find_struct_const(pCreateInfo->pNext,
205 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
206
207 /* We have to ignore the existence of the list if viewFormatCount = 0 */
208 if (format_list && format_list->viewFormatCount) {
209 /* compatibility is transitive, so we only need to check
210 * one format with everything else. */
211 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
212 if (format_list->pViewFormats[i] == VK_FORMAT_UNDEFINED)
213 continue;
214
215 if (!radv_dcc_formats_compatible(pCreateInfo->format,
216 format_list->pViewFormats[i]))
217 dcc_compatible_formats = false;
218 }
219 } else {
220 dcc_compatible_formats = false;
221 }
222 }
223
224 if (!dcc_compatible_formats)
225 return false;
226
227 return true;
228 }
229
230 static bool
231 radv_use_tc_compat_cmask_for_image(struct radv_device *device,
232 struct radv_image *image)
233 {
234 if (!(device->instance->perftest_flags & RADV_PERFTEST_TC_COMPAT_CMASK))
235 return false;
236
237 /* TC-compat CMASK is only available for GFX8+. */
238 if (device->physical_device->rad_info.chip_class < GFX8)
239 return false;
240
241 if (image->usage & VK_IMAGE_USAGE_STORAGE_BIT)
242 return false;
243
244 if (radv_image_has_dcc(image))
245 return false;
246
247 if (!radv_image_has_cmask(image))
248 return false;
249
250 return true;
251 }
252
253 static void
254 radv_prefill_surface_from_metadata(struct radv_device *device,
255 struct radeon_surf *surface,
256 const struct radv_image_create_info *create_info)
257 {
258 const struct radeon_bo_metadata *md = create_info->bo_metadata;
259 if (device->physical_device->rad_info.chip_class >= GFX9) {
260 if (md->u.gfx9.swizzle_mode > 0)
261 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
262 else
263 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
264
265 surface->u.gfx9.surf.swizzle_mode = md->u.gfx9.swizzle_mode;
266 } else {
267 surface->u.legacy.pipe_config = md->u.legacy.pipe_config;
268 surface->u.legacy.bankw = md->u.legacy.bankw;
269 surface->u.legacy.bankh = md->u.legacy.bankh;
270 surface->u.legacy.tile_split = md->u.legacy.tile_split;
271 surface->u.legacy.mtilea = md->u.legacy.mtilea;
272 surface->u.legacy.num_banks = md->u.legacy.num_banks;
273
274 if (md->u.legacy.macrotile == RADEON_LAYOUT_TILED)
275 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
276 else if (md->u.legacy.microtile == RADEON_LAYOUT_TILED)
277 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
278 else
279 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
280
281 }
282 }
283
284 static int
285 radv_init_surface(struct radv_device *device,
286 const struct radv_image *image,
287 struct radeon_surf *surface,
288 unsigned plane_id,
289 const struct radv_image_create_info *create_info)
290 {
291 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
292 unsigned array_mode = radv_choose_tiling(device, create_info);
293 VkFormat format = vk_format_get_plane_format(pCreateInfo->format, plane_id);
294 const struct vk_format_description *desc = vk_format_description(format);
295 bool is_depth, is_stencil;
296
297 is_depth = vk_format_has_depth(desc);
298 is_stencil = vk_format_has_stencil(desc);
299
300 surface->blk_w = vk_format_get_blockwidth(format);
301 surface->blk_h = vk_format_get_blockheight(format);
302
303 surface->bpe = vk_format_get_blocksize(vk_format_depth_only(format));
304 /* align byte per element on dword */
305 if (surface->bpe == 3) {
306 surface->bpe = 4;
307 }
308 if (create_info->bo_metadata) {
309 radv_prefill_surface_from_metadata(device, surface, create_info);
310 } else {
311 surface->flags = RADEON_SURF_SET(array_mode, MODE);
312 }
313
314 switch (pCreateInfo->imageType){
315 case VK_IMAGE_TYPE_1D:
316 if (pCreateInfo->arrayLayers > 1)
317 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
318 else
319 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
320 break;
321 case VK_IMAGE_TYPE_2D:
322 if (pCreateInfo->arrayLayers > 1)
323 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
324 else
325 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
326 break;
327 case VK_IMAGE_TYPE_3D:
328 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
329 break;
330 default:
331 unreachable("unhandled image type");
332 }
333
334 if (is_depth) {
335 surface->flags |= RADEON_SURF_ZBUFFER;
336 if (radv_use_tc_compat_htile_for_image(device, pCreateInfo))
337 surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
338 }
339
340 if (is_stencil)
341 surface->flags |= RADEON_SURF_SBUFFER;
342
343 if (device->physical_device->rad_info.chip_class >= GFX9 &&
344 pCreateInfo->imageType == VK_IMAGE_TYPE_3D &&
345 vk_format_get_blocksizebits(pCreateInfo->format) == 128 &&
346 vk_format_is_compressed(pCreateInfo->format))
347 surface->flags |= RADEON_SURF_NO_RENDER_TARGET;
348
349 surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
350
351 if (!radv_use_dcc_for_image(device, image, create_info, pCreateInfo))
352 surface->flags |= RADEON_SURF_DISABLE_DCC;
353
354 if (radv_surface_has_scanout(device, create_info))
355 surface->flags |= RADEON_SURF_SCANOUT;
356
357 return 0;
358 }
359
360 static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
361 {
362 return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
363 }
364
365 static inline unsigned
366 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
367 {
368 if (stencil)
369 return plane->surface.u.legacy.stencil_tiling_index[level];
370 else
371 return plane->surface.u.legacy.tiling_index[level];
372 }
373
374 static unsigned radv_map_swizzle(unsigned swizzle)
375 {
376 switch (swizzle) {
377 case VK_SWIZZLE_Y:
378 return V_008F0C_SQ_SEL_Y;
379 case VK_SWIZZLE_Z:
380 return V_008F0C_SQ_SEL_Z;
381 case VK_SWIZZLE_W:
382 return V_008F0C_SQ_SEL_W;
383 case VK_SWIZZLE_0:
384 return V_008F0C_SQ_SEL_0;
385 case VK_SWIZZLE_1:
386 return V_008F0C_SQ_SEL_1;
387 default: /* VK_SWIZZLE_X */
388 return V_008F0C_SQ_SEL_X;
389 }
390 }
391
392 static void
393 radv_make_buffer_descriptor(struct radv_device *device,
394 struct radv_buffer *buffer,
395 VkFormat vk_format,
396 unsigned offset,
397 unsigned range,
398 uint32_t *state)
399 {
400 const struct vk_format_description *desc;
401 unsigned stride;
402 uint64_t gpu_address = radv_buffer_get_va(buffer->bo);
403 uint64_t va = gpu_address + buffer->offset;
404 unsigned num_format, data_format;
405 int first_non_void;
406 desc = vk_format_description(vk_format);
407 first_non_void = vk_format_get_first_non_void_channel(vk_format);
408 stride = desc->block.bits / 8;
409
410 va += offset;
411 state[0] = va;
412 state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
413 S_008F04_STRIDE(stride);
414
415 if (device->physical_device->rad_info.chip_class != GFX8 && stride) {
416 range /= stride;
417 }
418
419 state[2] = range;
420 state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
421 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
422 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
423 S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3]));
424
425 if (device->physical_device->rad_info.chip_class >= GFX10) {
426 const struct gfx10_format *fmt = &gfx10_format_table[vk_format];
427
428 /* OOB_SELECT chooses the out-of-bounds check:
429 * - 0: (index >= NUM_RECORDS) || (offset >= STRIDE)
430 * - 1: index >= NUM_RECORDS
431 * - 2: NUM_RECORDS == 0
432 * - 3: if SWIZZLE_ENABLE == 0: offset >= NUM_RECORDS
433 * else: swizzle_address >= NUM_RECORDS
434 */
435 state[3] |= S_008F0C_FORMAT(fmt->img_format) |
436 S_008F0C_OOB_SELECT(0) |
437 S_008F0C_RESOURCE_LEVEL(1);
438 } else {
439 num_format = radv_translate_buffer_numformat(desc, first_non_void);
440 data_format = radv_translate_buffer_dataformat(desc, first_non_void);
441
442 assert(data_format != V_008F0C_BUF_DATA_FORMAT_INVALID);
443 assert(num_format != ~0);
444
445 state[3] |= S_008F0C_NUM_FORMAT(num_format) |
446 S_008F0C_DATA_FORMAT(data_format);
447 }
448 }
449
450 static void
451 si_set_mutable_tex_desc_fields(struct radv_device *device,
452 struct radv_image *image,
453 const struct legacy_surf_level *base_level_info,
454 unsigned plane_id,
455 unsigned base_level, unsigned first_level,
456 unsigned block_width, bool is_stencil,
457 bool is_storage_image, bool disable_compression,
458 uint32_t *state)
459 {
460 struct radv_image_plane *plane = &image->planes[plane_id];
461 uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0;
462 uint64_t va = gpu_address + plane->offset;
463 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
464 uint64_t meta_va = 0;
465 if (chip_class >= GFX9) {
466 if (is_stencil)
467 va += plane->surface.u.gfx9.stencil_offset;
468 else
469 va += plane->surface.u.gfx9.surf_offset;
470 } else
471 va += base_level_info->offset;
472
473 state[0] = va >> 8;
474 if (chip_class >= GFX9 ||
475 base_level_info->mode == RADEON_SURF_MODE_2D)
476 state[0] |= plane->surface.tile_swizzle;
477 state[1] &= C_008F14_BASE_ADDRESS_HI;
478 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
479
480 if (chip_class >= GFX8) {
481 state[6] &= C_008F28_COMPRESSION_EN;
482 state[7] = 0;
483 if (!disable_compression && radv_dcc_enabled(image, first_level)) {
484 meta_va = gpu_address + image->dcc_offset;
485 if (chip_class <= GFX8)
486 meta_va += base_level_info->dcc_offset;
487
488 unsigned dcc_tile_swizzle = plane->surface.tile_swizzle << 8;
489 dcc_tile_swizzle &= plane->surface.dcc_alignment - 1;
490 meta_va |= dcc_tile_swizzle;
491 } else if (!disable_compression &&
492 radv_image_is_tc_compat_htile(image)) {
493 meta_va = gpu_address + image->htile_offset;
494 }
495
496 if (meta_va) {
497 state[6] |= S_008F28_COMPRESSION_EN(1);
498 if (chip_class <= GFX9)
499 state[7] = meta_va >> 8;
500 }
501 }
502
503 if (chip_class >= GFX10) {
504 state[3] &= C_00A00C_SW_MODE;
505
506 if (is_stencil) {
507 state[3] |= S_00A00C_SW_MODE(plane->surface.u.gfx9.stencil.swizzle_mode);
508 } else {
509 state[3] |= S_00A00C_SW_MODE(plane->surface.u.gfx9.surf.swizzle_mode);
510 }
511
512 state[6] &= C_00A018_META_DATA_ADDRESS_LO &
513 C_00A018_META_PIPE_ALIGNED;
514
515 if (meta_va) {
516 struct gfx9_surf_meta_flags meta;
517
518 if (image->dcc_offset)
519 meta = plane->surface.u.gfx9.dcc;
520 else
521 meta = plane->surface.u.gfx9.htile;
522
523 state[6] |= S_00A018_META_PIPE_ALIGNED(meta.pipe_aligned) |
524 S_00A018_META_DATA_ADDRESS_LO(meta_va >> 8);
525 }
526
527 state[7] = meta_va >> 16;
528 } else if (chip_class == GFX9) {
529 state[3] &= C_008F1C_SW_MODE;
530 state[4] &= C_008F20_PITCH;
531
532 if (is_stencil) {
533 state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.stencil.swizzle_mode);
534 state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.stencil.epitch);
535 } else {
536 state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.surf.swizzle_mode);
537 state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.surf.epitch);
538 }
539
540 state[5] &= C_008F24_META_DATA_ADDRESS &
541 C_008F24_META_PIPE_ALIGNED &
542 C_008F24_META_RB_ALIGNED;
543 if (meta_va) {
544 struct gfx9_surf_meta_flags meta;
545
546 if (image->dcc_offset)
547 meta = plane->surface.u.gfx9.dcc;
548 else
549 meta = plane->surface.u.gfx9.htile;
550
551 state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
552 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
553 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
554 }
555 } else {
556 /* GFX6-GFX8 */
557 unsigned pitch = base_level_info->nblk_x * block_width;
558 unsigned index = si_tile_mode_index(plane, base_level, is_stencil);
559
560 state[3] &= C_008F1C_TILING_INDEX;
561 state[3] |= S_008F1C_TILING_INDEX(index);
562 state[4] &= C_008F20_PITCH;
563 state[4] |= S_008F20_PITCH(pitch - 1);
564 }
565 }
566
567 static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
568 unsigned nr_layers, unsigned nr_samples, bool is_storage_image, bool gfx9)
569 {
570 if (view_type == VK_IMAGE_VIEW_TYPE_CUBE || view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY)
571 return is_storage_image ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_CUBE;
572
573 /* GFX9 allocates 1D textures as 2D. */
574 if (gfx9 && image_type == VK_IMAGE_TYPE_1D)
575 image_type = VK_IMAGE_TYPE_2D;
576 switch (image_type) {
577 case VK_IMAGE_TYPE_1D:
578 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY : V_008F1C_SQ_RSRC_IMG_1D;
579 case VK_IMAGE_TYPE_2D:
580 if (nr_samples > 1)
581 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_MSAA;
582 else
583 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_2D;
584 case VK_IMAGE_TYPE_3D:
585 if (view_type == VK_IMAGE_VIEW_TYPE_3D)
586 return V_008F1C_SQ_RSRC_IMG_3D;
587 else
588 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
589 default:
590 unreachable("illegal image type");
591 }
592 }
593
594 static unsigned gfx9_border_color_swizzle(const enum vk_swizzle swizzle[4])
595 {
596 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
597
598 if (swizzle[3] == VK_SWIZZLE_X) {
599 /* For the pre-defined border color values (white, opaque
600 * black, transparent black), the only thing that matters is
601 * that the alpha channel winds up in the correct place
602 * (because the RGB channels are all the same) so either of
603 * these enumerations will work.
604 */
605 if (swizzle[2] == VK_SWIZZLE_Y)
606 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
607 else
608 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
609 } else if (swizzle[0] == VK_SWIZZLE_X) {
610 if (swizzle[1] == VK_SWIZZLE_Y)
611 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
612 else
613 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
614 } else if (swizzle[1] == VK_SWIZZLE_X) {
615 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
616 } else if (swizzle[2] == VK_SWIZZLE_X) {
617 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
618 }
619
620 return bc_swizzle;
621 }
622
623 static bool vi_alpha_is_on_msb(struct radv_device *device, VkFormat format)
624 {
625 const struct vk_format_description *desc = vk_format_description(format);
626
627 if (device->physical_device->rad_info.chip_class >= GFX10 && desc->nr_channels == 1)
628 return desc->swizzle[3] == VK_SWIZZLE_X;
629
630 return radv_translate_colorswap(format, false) <= 1;
631 }
632 /**
633 * Build the sampler view descriptor for a texture (GFX10).
634 */
635 static void
636 gfx10_make_texture_descriptor(struct radv_device *device,
637 struct radv_image *image,
638 bool is_storage_image,
639 VkImageViewType view_type,
640 VkFormat vk_format,
641 const VkComponentMapping *mapping,
642 unsigned first_level, unsigned last_level,
643 unsigned first_layer, unsigned last_layer,
644 unsigned width, unsigned height, unsigned depth,
645 uint32_t *state,
646 uint32_t *fmask_state)
647 {
648 const struct vk_format_description *desc;
649 enum vk_swizzle swizzle[4];
650 unsigned img_format;
651 unsigned type;
652
653 desc = vk_format_description(vk_format);
654 img_format = gfx10_format_table[vk_format].img_format;
655
656 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
657 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
658 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
659 } else {
660 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
661 }
662
663 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
664 is_storage_image, device->physical_device->rad_info.chip_class == GFX9);
665 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
666 height = 1;
667 depth = image->info.array_size;
668 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
669 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
670 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
671 depth = image->info.array_size;
672 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
673 depth = image->info.array_size / 6;
674
675 state[0] = 0;
676 state[1] = S_00A004_FORMAT(img_format) |
677 S_00A004_WIDTH_LO(width - 1);
678 state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
679 S_00A008_HEIGHT(height - 1) |
680 S_00A008_RESOURCE_LEVEL(1);
681 state[3] = S_00A00C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
682 S_00A00C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
683 S_00A00C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
684 S_00A00C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
685 S_00A00C_BASE_LEVEL(image->info.samples > 1 ?
686 0 : first_level) |
687 S_00A00C_LAST_LEVEL(image->info.samples > 1 ?
688 util_logbase2(image->info.samples) :
689 last_level) |
690 S_00A00C_BC_SWIZZLE(gfx9_border_color_swizzle(swizzle)) |
691 S_00A00C_TYPE(type);
692 /* Depth is the the last accessible layer on gfx9+. The hw doesn't need
693 * to know the total number of layers.
694 */
695 state[4] = S_00A010_DEPTH(type == V_008F1C_SQ_RSRC_IMG_3D ? depth - 1 : last_layer) |
696 S_00A010_BASE_ARRAY(first_layer);
697 state[5] = S_00A014_ARRAY_PITCH(!!(type == V_008F1C_SQ_RSRC_IMG_3D)) |
698 S_00A014_MAX_MIP(image->info.samples > 1 ?
699 util_logbase2(image->info.samples) :
700 image->info.levels - 1) |
701 S_00A014_PERF_MOD(4);
702 state[6] = 0;
703 state[7] = 0;
704
705 if (radv_dcc_enabled(image, first_level)) {
706 state[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
707 S_00A018_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B) |
708 S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(device, vk_format));
709 }
710
711 /* Initialize the sampler view for FMASK. */
712 if (radv_image_has_fmask(image)) {
713 uint64_t gpu_address = radv_buffer_get_va(image->bo);
714 uint32_t format;
715 uint64_t va;
716
717 assert(image->plane_count == 1);
718
719 va = gpu_address + image->offset + image->fmask_offset;
720
721 switch (image->info.samples) {
722 case 2:
723 format = V_008F0C_IMG_FORMAT_FMASK8_S2_F2;
724 break;
725 case 4:
726 format = V_008F0C_IMG_FORMAT_FMASK8_S4_F4;
727 break;
728 case 8:
729 format = V_008F0C_IMG_FORMAT_FMASK32_S8_F8;
730 break;
731 default:
732 unreachable("invalid nr_samples");
733 }
734
735 fmask_state[0] = (va >> 8) | image->planes[0].surface.fmask_tile_swizzle;
736 fmask_state[1] = S_00A004_BASE_ADDRESS_HI(va >> 40) |
737 S_00A004_FORMAT(format) |
738 S_00A004_WIDTH_LO(width - 1);
739 fmask_state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
740 S_00A008_HEIGHT(height - 1) |
741 S_00A008_RESOURCE_LEVEL(1);
742 fmask_state[3] = S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
743 S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
744 S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
745 S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
746 S_00A00C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode) |
747 S_00A00C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
748 fmask_state[4] = S_00A010_DEPTH(last_layer) |
749 S_00A010_BASE_ARRAY(first_layer);
750 fmask_state[5] = 0;
751 fmask_state[6] = S_00A018_META_PIPE_ALIGNED(image->planes[0].surface.u.gfx9.cmask.pipe_aligned);
752 fmask_state[7] = 0;
753 } else if (fmask_state)
754 memset(fmask_state, 0, 8 * 4);
755 }
756
757 /**
758 * Build the sampler view descriptor for a texture (SI-GFX9)
759 */
760 static void
761 si_make_texture_descriptor(struct radv_device *device,
762 struct radv_image *image,
763 bool is_storage_image,
764 VkImageViewType view_type,
765 VkFormat vk_format,
766 const VkComponentMapping *mapping,
767 unsigned first_level, unsigned last_level,
768 unsigned first_layer, unsigned last_layer,
769 unsigned width, unsigned height, unsigned depth,
770 uint32_t *state,
771 uint32_t *fmask_state)
772 {
773 const struct vk_format_description *desc;
774 enum vk_swizzle swizzle[4];
775 int first_non_void;
776 unsigned num_format, data_format, type;
777
778 desc = vk_format_description(vk_format);
779
780 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
781 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
782 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
783 } else {
784 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
785 }
786
787 first_non_void = vk_format_get_first_non_void_channel(vk_format);
788
789 num_format = radv_translate_tex_numformat(vk_format, desc, first_non_void);
790 if (num_format == ~0) {
791 num_format = 0;
792 }
793
794 data_format = radv_translate_tex_dataformat(vk_format, desc, first_non_void);
795 if (data_format == ~0) {
796 data_format = 0;
797 }
798
799 /* S8 with either Z16 or Z32 HTILE need a special format. */
800 if (device->physical_device->rad_info.chip_class == GFX9 &&
801 vk_format == VK_FORMAT_S8_UINT &&
802 radv_image_is_tc_compat_htile(image)) {
803 if (image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT)
804 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
805 else if (image->vk_format == VK_FORMAT_D16_UNORM_S8_UINT)
806 data_format = V_008F14_IMG_DATA_FORMAT_S8_16;
807 }
808 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
809 is_storage_image, device->physical_device->rad_info.chip_class == GFX9);
810 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
811 height = 1;
812 depth = image->info.array_size;
813 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
814 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
815 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
816 depth = image->info.array_size;
817 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
818 depth = image->info.array_size / 6;
819
820 state[0] = 0;
821 state[1] = (S_008F14_DATA_FORMAT(data_format) |
822 S_008F14_NUM_FORMAT(num_format));
823 state[2] = (S_008F18_WIDTH(width - 1) |
824 S_008F18_HEIGHT(height - 1) |
825 S_008F18_PERF_MOD(4));
826 state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
827 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
828 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
829 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
830 S_008F1C_BASE_LEVEL(image->info.samples > 1 ?
831 0 : first_level) |
832 S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
833 util_logbase2(image->info.samples) :
834 last_level) |
835 S_008F1C_TYPE(type));
836 state[4] = 0;
837 state[5] = S_008F24_BASE_ARRAY(first_layer);
838 state[6] = 0;
839 state[7] = 0;
840
841 if (device->physical_device->rad_info.chip_class == GFX9) {
842 unsigned bc_swizzle = gfx9_border_color_swizzle(swizzle);
843
844 /* Depth is the last accessible layer on Gfx9.
845 * The hw doesn't need to know the total number of layers.
846 */
847 if (type == V_008F1C_SQ_RSRC_IMG_3D)
848 state[4] |= S_008F20_DEPTH(depth - 1);
849 else
850 state[4] |= S_008F20_DEPTH(last_layer);
851
852 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
853 state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ?
854 util_logbase2(image->info.samples) :
855 image->info.levels - 1);
856 } else {
857 state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
858 state[4] |= S_008F20_DEPTH(depth - 1);
859 state[5] |= S_008F24_LAST_ARRAY(last_layer);
860 }
861 if (image->dcc_offset) {
862 state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(device, vk_format));
863 } else {
864 /* The last dword is unused by hw. The shader uses it to clear
865 * bits in the first dword of sampler state.
866 */
867 if (device->physical_device->rad_info.chip_class <= GFX7 && image->info.samples <= 1) {
868 if (first_level == last_level)
869 state[7] = C_008F30_MAX_ANISO_RATIO;
870 else
871 state[7] = 0xffffffff;
872 }
873 }
874
875 /* Initialize the sampler view for FMASK. */
876 if (radv_image_has_fmask(image)) {
877 uint32_t fmask_format, num_format;
878 uint64_t gpu_address = radv_buffer_get_va(image->bo);
879 uint64_t va;
880
881 assert(image->plane_count == 1);
882
883 va = gpu_address + image->offset + image->fmask_offset;
884
885 if (device->physical_device->rad_info.chip_class == GFX9) {
886 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
887 switch (image->info.samples) {
888 case 2:
889 num_format = V_008F14_IMG_FMASK_8_2_2;
890 break;
891 case 4:
892 num_format = V_008F14_IMG_FMASK_8_4_4;
893 break;
894 case 8:
895 num_format = V_008F14_IMG_FMASK_32_8_8;
896 break;
897 default:
898 unreachable("invalid nr_samples");
899 }
900 } else {
901 switch (image->info.samples) {
902 case 2:
903 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
904 break;
905 case 4:
906 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
907 break;
908 case 8:
909 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
910 break;
911 default:
912 assert(0);
913 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
914 }
915 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
916 }
917
918 fmask_state[0] = va >> 8;
919 fmask_state[0] |= image->planes[0].surface.fmask_tile_swizzle;
920 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
921 S_008F14_DATA_FORMAT(fmask_format) |
922 S_008F14_NUM_FORMAT(num_format);
923 fmask_state[2] = S_008F18_WIDTH(width - 1) |
924 S_008F18_HEIGHT(height - 1);
925 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
926 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
927 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
928 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
929 S_008F1C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
930 fmask_state[4] = 0;
931 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
932 fmask_state[6] = 0;
933 fmask_state[7] = 0;
934
935 if (device->physical_device->rad_info.chip_class == GFX9) {
936 fmask_state[3] |= S_008F1C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode);
937 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
938 S_008F20_PITCH(image->planes[0].surface.u.gfx9.fmask.epitch);
939 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->planes[0].surface.u.gfx9.cmask.pipe_aligned) |
940 S_008F24_META_RB_ALIGNED(image->planes[0].surface.u.gfx9.cmask.rb_aligned);
941
942 if (radv_image_is_tc_compat_cmask(image)) {
943 va = gpu_address + image->offset + image->cmask_offset;
944
945 fmask_state[5] |= S_008F24_META_DATA_ADDRESS(va >> 40);
946 fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
947 fmask_state[7] |= va >> 8;
948 }
949 } else {
950 fmask_state[3] |= S_008F1C_TILING_INDEX(image->planes[0].surface.u.legacy.fmask.tiling_index);
951 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
952 S_008F20_PITCH(image->planes[0].surface.u.legacy.fmask.pitch_in_pixels - 1);
953 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
954
955 if (radv_image_is_tc_compat_cmask(image)) {
956 va = gpu_address + image->offset + image->cmask_offset;
957
958 fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
959 fmask_state[7] |= va >> 8;
960 }
961 }
962 } else if (fmask_state)
963 memset(fmask_state, 0, 8 * 4);
964 }
965
966 static void
967 radv_make_texture_descriptor(struct radv_device *device,
968 struct radv_image *image,
969 bool is_storage_image,
970 VkImageViewType view_type,
971 VkFormat vk_format,
972 const VkComponentMapping *mapping,
973 unsigned first_level, unsigned last_level,
974 unsigned first_layer, unsigned last_layer,
975 unsigned width, unsigned height, unsigned depth,
976 uint32_t *state,
977 uint32_t *fmask_state)
978 {
979 if (device->physical_device->rad_info.chip_class >= GFX10) {
980 gfx10_make_texture_descriptor(device, image, is_storage_image,
981 view_type, vk_format, mapping,
982 first_level, last_level,
983 first_layer, last_layer,
984 width, height, depth,
985 state, fmask_state);
986 } else {
987 si_make_texture_descriptor(device, image, is_storage_image,
988 view_type, vk_format, mapping,
989 first_level, last_level,
990 first_layer, last_layer,
991 width, height, depth,
992 state, fmask_state);
993 }
994 }
995
996 static void
997 radv_query_opaque_metadata(struct radv_device *device,
998 struct radv_image *image,
999 struct radeon_bo_metadata *md)
1000 {
1001 static const VkComponentMapping fixedmapping;
1002 uint32_t desc[8], i;
1003
1004 assert(image->plane_count == 1);
1005
1006 /* Metadata image format format version 1:
1007 * [0] = 1 (metadata format identifier)
1008 * [1] = (VENDOR_ID << 16) | PCI_ID
1009 * [2:9] = image descriptor for the whole resource
1010 * [2] is always 0, because the base address is cleared
1011 * [9] is the DCC offset bits [39:8] from the beginning of
1012 * the buffer
1013 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
1014 */
1015 md->metadata[0] = 1; /* metadata image format version 1 */
1016
1017 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
1018 md->metadata[1] = si_get_bo_metadata_word1(device);
1019
1020
1021 radv_make_texture_descriptor(device, image, false,
1022 (VkImageViewType)image->type, image->vk_format,
1023 &fixedmapping, 0, image->info.levels - 1, 0,
1024 image->info.array_size - 1,
1025 image->info.width, image->info.height,
1026 image->info.depth,
1027 desc, NULL);
1028
1029 si_set_mutable_tex_desc_fields(device, image, &image->planes[0].surface.u.legacy.level[0], 0, 0, 0,
1030 image->planes[0].surface.blk_w, false, false, false, desc);
1031
1032 /* Clear the base address and set the relative DCC offset. */
1033 desc[0] = 0;
1034 desc[1] &= C_008F14_BASE_ADDRESS_HI;
1035 desc[7] = image->dcc_offset >> 8;
1036
1037 /* Dwords [2:9] contain the image descriptor. */
1038 memcpy(&md->metadata[2], desc, sizeof(desc));
1039
1040 /* Dwords [10:..] contain the mipmap level offsets. */
1041 if (device->physical_device->rad_info.chip_class <= GFX8) {
1042 for (i = 0; i <= image->info.levels - 1; i++)
1043 md->metadata[10+i] = image->planes[0].surface.u.legacy.level[i].offset >> 8;
1044 md->size_metadata = (11 + image->info.levels - 1) * 4;
1045 } else
1046 md->size_metadata = 10 * 4;
1047 }
1048
1049 void
1050 radv_init_metadata(struct radv_device *device,
1051 struct radv_image *image,
1052 struct radeon_bo_metadata *metadata)
1053 {
1054 struct radeon_surf *surface = &image->planes[0].surface;
1055
1056 memset(metadata, 0, sizeof(*metadata));
1057
1058 if (device->physical_device->rad_info.chip_class >= GFX9) {
1059 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
1060 } else {
1061 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
1062 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
1063 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
1064 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
1065 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
1066 metadata->u.legacy.bankw = surface->u.legacy.bankw;
1067 metadata->u.legacy.bankh = surface->u.legacy.bankh;
1068 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
1069 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
1070 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
1071 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
1072 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
1073 }
1074 radv_query_opaque_metadata(device, image, metadata);
1075 }
1076
1077 void
1078 radv_image_override_offset_stride(struct radv_device *device,
1079 struct radv_image *image,
1080 uint64_t offset, uint32_t stride)
1081 {
1082 struct radeon_surf *surface = &image->planes[0].surface;
1083 unsigned bpe = vk_format_get_blocksizebits(image->vk_format) / 8;
1084
1085 if (device->physical_device->rad_info.chip_class >= GFX9) {
1086 if (stride) {
1087 surface->u.gfx9.surf_pitch = stride;
1088 surface->u.gfx9.surf_slice_size =
1089 (uint64_t)stride * surface->u.gfx9.surf_height * bpe;
1090 }
1091 surface->u.gfx9.surf_offset = offset;
1092 } else {
1093 surface->u.legacy.level[0].nblk_x = stride;
1094 surface->u.legacy.level[0].slice_size_dw =
1095 ((uint64_t)stride * surface->u.legacy.level[0].nblk_y * bpe) / 4;
1096
1097 if (offset) {
1098 for (unsigned i = 0; i < ARRAY_SIZE(surface->u.legacy.level); ++i)
1099 surface->u.legacy.level[i].offset += offset;
1100 }
1101
1102 }
1103 }
1104
1105 static void
1106 radv_image_alloc_fmask(struct radv_device *device,
1107 struct radv_image *image)
1108 {
1109 unsigned fmask_alignment = image->planes[0].surface.fmask_alignment;
1110
1111 image->fmask_offset = align64(image->size, fmask_alignment);
1112 image->size = image->fmask_offset + image->planes[0].surface.fmask_size;
1113 image->alignment = MAX2(image->alignment, fmask_alignment);
1114 }
1115
1116 static void
1117 radv_image_alloc_cmask(struct radv_device *device,
1118 struct radv_image *image)
1119 {
1120 unsigned cmask_alignment = image->planes[0].surface.cmask_alignment;
1121 unsigned cmask_size = image->planes[0].surface.cmask_size;
1122 uint32_t clear_value_size = 0;
1123
1124 if (!cmask_size)
1125 return;
1126
1127 assert(cmask_alignment);
1128
1129 image->cmask_offset = align64(image->size, cmask_alignment);
1130 /* + 8 for storing the clear values */
1131 if (!image->clear_value_offset) {
1132 image->clear_value_offset = image->cmask_offset + cmask_size;
1133 clear_value_size = 8;
1134 }
1135 image->size = image->cmask_offset + cmask_size + clear_value_size;
1136 image->alignment = MAX2(image->alignment, cmask_alignment);
1137 }
1138
1139 static void
1140 radv_image_alloc_dcc(struct radv_image *image)
1141 {
1142 assert(image->plane_count == 1);
1143
1144 image->dcc_offset = align64(image->size, image->planes[0].surface.dcc_alignment);
1145 /* + 24 for storing the clear values + fce pred + dcc pred for each mip */
1146 image->clear_value_offset = image->dcc_offset + image->planes[0].surface.dcc_size;
1147 image->fce_pred_offset = image->clear_value_offset + 8 * image->info.levels;
1148 image->dcc_pred_offset = image->clear_value_offset + 16 * image->info.levels;
1149 image->size = image->dcc_offset + image->planes[0].surface.dcc_size + 24 * image->info.levels;
1150 image->alignment = MAX2(image->alignment, image->planes[0].surface.dcc_alignment);
1151 }
1152
1153 static void
1154 radv_image_alloc_htile(struct radv_device *device, struct radv_image *image)
1155 {
1156 image->htile_offset = align64(image->size, image->planes[0].surface.htile_alignment);
1157
1158 /* + 8 for storing the clear values */
1159 image->clear_value_offset = image->htile_offset + image->planes[0].surface.htile_size;
1160 image->size = image->clear_value_offset + 8;
1161 if (radv_image_is_tc_compat_htile(image) &&
1162 device->physical_device->has_tc_compat_zrange_bug) {
1163 /* Metadata for the TC-compatible HTILE hardware bug which
1164 * have to be fixed by updating ZRANGE_PRECISION when doing
1165 * fast depth clears to 0.0f.
1166 */
1167 image->tc_compat_zrange_offset = image->size;
1168 image->size = image->tc_compat_zrange_offset + 4;
1169 }
1170 image->alignment = align64(image->alignment, image->planes[0].surface.htile_alignment);
1171 }
1172
1173 static inline bool
1174 radv_image_can_enable_dcc_or_cmask(struct radv_image *image)
1175 {
1176 if (image->info.samples <= 1 &&
1177 image->info.width * image->info.height <= 512 * 512) {
1178 /* Do not enable CMASK or DCC for small surfaces where the cost
1179 * of the eliminate pass can be higher than the benefit of fast
1180 * clear. RadeonSI does this, but the image threshold is
1181 * different.
1182 */
1183 return false;
1184 }
1185
1186 return image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT &&
1187 (image->exclusive || image->queue_family_mask == 1);
1188 }
1189
1190 static inline bool
1191 radv_image_can_enable_dcc(struct radv_device *device, struct radv_image *image)
1192 {
1193 if (!radv_image_can_enable_dcc_or_cmask(image) ||
1194 !radv_image_has_dcc(image))
1195 return false;
1196
1197 /* On GFX8, DCC layers can be interleaved and it's currently only
1198 * enabled if slice size is equal to the per slice fast clear size
1199 * because the driver assumes that portions of multiple layers are
1200 * contiguous during fast clears.
1201 */
1202 if (image->info.array_size > 1) {
1203 const struct legacy_surf_level *surf_level =
1204 &image->planes[0].surface.u.legacy.level[0];
1205
1206 assert(device->physical_device->rad_info.chip_class == GFX8);
1207
1208 if (image->planes[0].surface.dcc_slice_size != surf_level->dcc_fast_clear_size)
1209 return false;
1210 }
1211
1212 return true;
1213 }
1214
1215 static inline bool
1216 radv_image_can_enable_cmask(struct radv_image *image)
1217 {
1218 if (image->planes[0].surface.bpe > 8 && image->info.samples == 1) {
1219 /* Do not enable CMASK for non-MSAA images (fast color clear)
1220 * because 128 bit formats are not supported, but FMASK might
1221 * still be used.
1222 */
1223 return false;
1224 }
1225
1226 return radv_image_can_enable_dcc_or_cmask(image) &&
1227 image->info.levels == 1 &&
1228 image->info.depth == 1 &&
1229 !image->planes[0].surface.is_linear;
1230 }
1231
1232 static inline bool
1233 radv_image_can_enable_fmask(struct radv_image *image)
1234 {
1235 return image->info.samples > 1 && vk_format_is_color(image->vk_format);
1236 }
1237
1238 static inline bool
1239 radv_image_can_enable_htile(struct radv_image *image)
1240 {
1241 return radv_image_has_htile(image) &&
1242 image->info.levels == 1 &&
1243 image->info.width * image->info.height >= 8 * 8;
1244 }
1245
1246 static void radv_image_disable_dcc(struct radv_image *image)
1247 {
1248 for (unsigned i = 0; i < image->plane_count; ++i)
1249 image->planes[i].surface.dcc_size = 0;
1250 }
1251
1252 static void radv_image_disable_htile(struct radv_image *image)
1253 {
1254 for (unsigned i = 0; i < image->plane_count; ++i)
1255 image->planes[i].surface.htile_size = 0;
1256 }
1257
1258 VkResult
1259 radv_image_create(VkDevice _device,
1260 const struct radv_image_create_info *create_info,
1261 const VkAllocationCallbacks* alloc,
1262 VkImage *pImage)
1263 {
1264 RADV_FROM_HANDLE(radv_device, device, _device);
1265 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
1266 struct radv_image *image = NULL;
1267 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
1268
1269 const unsigned plane_count = vk_format_get_plane_count(pCreateInfo->format);
1270 const size_t image_struct_size = sizeof(*image) + sizeof(struct radv_image_plane) * plane_count;
1271
1272 radv_assert(pCreateInfo->mipLevels > 0);
1273 radv_assert(pCreateInfo->arrayLayers > 0);
1274 radv_assert(pCreateInfo->samples > 0);
1275 radv_assert(pCreateInfo->extent.width > 0);
1276 radv_assert(pCreateInfo->extent.height > 0);
1277 radv_assert(pCreateInfo->extent.depth > 0);
1278
1279 image = vk_zalloc2(&device->alloc, alloc, image_struct_size, 8,
1280 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1281 if (!image)
1282 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1283
1284 image->type = pCreateInfo->imageType;
1285 image->info.width = pCreateInfo->extent.width;
1286 image->info.height = pCreateInfo->extent.height;
1287 image->info.depth = pCreateInfo->extent.depth;
1288 image->info.samples = pCreateInfo->samples;
1289 image->info.storage_samples = pCreateInfo->samples;
1290 image->info.array_size = pCreateInfo->arrayLayers;
1291 image->info.levels = pCreateInfo->mipLevels;
1292 image->info.num_channels = vk_format_get_nr_components(pCreateInfo->format);
1293
1294 image->vk_format = pCreateInfo->format;
1295 image->tiling = pCreateInfo->tiling;
1296 image->usage = pCreateInfo->usage;
1297 image->flags = pCreateInfo->flags;
1298
1299 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
1300 if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
1301 for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
1302 if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL ||
1303 pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_FOREIGN_EXT)
1304 image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1305 else
1306 image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
1307 }
1308
1309 image->shareable = vk_find_struct_const(pCreateInfo->pNext,
1310 EXTERNAL_MEMORY_IMAGE_CREATE_INFO) != NULL;
1311 if (!vk_format_is_depth_or_stencil(pCreateInfo->format) &&
1312 !radv_surface_has_scanout(device, create_info) && !image->shareable) {
1313 image->info.surf_index = &device->image_mrt_offset_counter;
1314 }
1315
1316 image->plane_count = plane_count;
1317 image->size = 0;
1318 image->alignment = 1;
1319 for (unsigned plane = 0; plane < plane_count; ++plane) {
1320 struct ac_surf_info info = image->info;
1321 radv_init_surface(device, image, &image->planes[plane].surface, plane, create_info);
1322
1323 if (plane) {
1324 const struct vk_format_description *desc = vk_format_description(pCreateInfo->format);
1325 assert(info.width % desc->width_divisor == 0);
1326 assert(info.height % desc->height_divisor == 0);
1327
1328 info.width /= desc->width_divisor;
1329 info.height /= desc->height_divisor;
1330 }
1331
1332 device->ws->surface_init(device->ws, &info, &image->planes[plane].surface);
1333
1334 image->planes[plane].offset = align(image->size, image->planes[plane].surface.surf_alignment);
1335 image->size = image->planes[plane].offset + image->planes[plane].surface.surf_size;
1336 image->alignment = image->planes[plane].surface.surf_alignment;
1337
1338 image->planes[plane].format = vk_format_get_plane_format(image->vk_format, plane);
1339 }
1340
1341 if (!create_info->no_metadata_planes) {
1342 /* Try to enable DCC first. */
1343 if (radv_image_can_enable_dcc(device, image)) {
1344 radv_image_alloc_dcc(image);
1345 if (image->info.samples > 1) {
1346 /* CMASK should be enabled because DCC fast
1347 * clear with MSAA needs it.
1348 */
1349 assert(radv_image_can_enable_cmask(image));
1350 radv_image_alloc_cmask(device, image);
1351 }
1352 } else {
1353 /* When DCC cannot be enabled, try CMASK. */
1354 radv_image_disable_dcc(image);
1355 if (radv_image_can_enable_cmask(image)) {
1356 radv_image_alloc_cmask(device, image);
1357 }
1358 }
1359
1360 /* Try to enable FMASK for multisampled images. */
1361 if (radv_image_can_enable_fmask(image)) {
1362 radv_image_alloc_fmask(device, image);
1363
1364 if (radv_use_tc_compat_cmask_for_image(device, image))
1365 image->tc_compatible_cmask = true;
1366 } else {
1367 /* Otherwise, try to enable HTILE for depth surfaces. */
1368 if (radv_image_can_enable_htile(image) &&
1369 !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
1370 image->tc_compatible_htile = image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1371 radv_image_alloc_htile(device, image);
1372 } else {
1373 radv_image_disable_htile(image);
1374 }
1375 }
1376 } else {
1377 radv_image_disable_dcc(image);
1378 radv_image_disable_htile(image);
1379 }
1380
1381 if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
1382 image->alignment = MAX2(image->alignment, 4096);
1383 image->size = align64(image->size, image->alignment);
1384 image->offset = 0;
1385
1386 image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
1387 0, RADEON_FLAG_VIRTUAL, RADV_BO_PRIORITY_VIRTUAL);
1388 if (!image->bo) {
1389 vk_free2(&device->alloc, alloc, image);
1390 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
1391 }
1392 }
1393
1394 *pImage = radv_image_to_handle(image);
1395
1396 return VK_SUCCESS;
1397 }
1398
1399 static void
1400 radv_image_view_make_descriptor(struct radv_image_view *iview,
1401 struct radv_device *device,
1402 VkFormat vk_format,
1403 const VkComponentMapping *components,
1404 bool is_storage_image, bool disable_compression,
1405 unsigned plane_id, unsigned descriptor_plane_id)
1406 {
1407 struct radv_image *image = iview->image;
1408 struct radv_image_plane *plane = &image->planes[plane_id];
1409 const struct vk_format_description *format_desc = vk_format_description(image->vk_format);
1410 bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
1411 uint32_t blk_w;
1412 union radv_descriptor *descriptor;
1413 uint32_t hw_level = 0;
1414
1415 if (is_storage_image) {
1416 descriptor = &iview->storage_descriptor;
1417 } else {
1418 descriptor = &iview->descriptor;
1419 }
1420
1421 assert(vk_format_get_plane_count(vk_format) == 1);
1422 assert(plane->surface.blk_w % vk_format_get_blockwidth(plane->format) == 0);
1423 blk_w = plane->surface.blk_w / vk_format_get_blockwidth(plane->format) * vk_format_get_blockwidth(vk_format);
1424
1425 if (device->physical_device->rad_info.chip_class >= GFX9)
1426 hw_level = iview->base_mip;
1427 radv_make_texture_descriptor(device, image, is_storage_image,
1428 iview->type,
1429 vk_format,
1430 components,
1431 hw_level, hw_level + iview->level_count - 1,
1432 iview->base_layer,
1433 iview->base_layer + iview->layer_count - 1,
1434 iview->extent.width / (plane_id ? format_desc->width_divisor : 1),
1435 iview->extent.height / (plane_id ? format_desc->height_divisor : 1),
1436 iview->extent.depth,
1437 descriptor->plane_descriptors[descriptor_plane_id],
1438 descriptor_plane_id ? NULL : descriptor->fmask_descriptor);
1439
1440 const struct legacy_surf_level *base_level_info = NULL;
1441 if (device->physical_device->rad_info.chip_class <= GFX9) {
1442 if (is_stencil)
1443 base_level_info = &plane->surface.u.legacy.stencil_level[iview->base_mip];
1444 else
1445 base_level_info = &plane->surface.u.legacy.level[iview->base_mip];
1446 }
1447 si_set_mutable_tex_desc_fields(device, image,
1448 base_level_info,
1449 plane_id,
1450 iview->base_mip,
1451 iview->base_mip,
1452 blk_w, is_stencil, is_storage_image,
1453 is_storage_image || disable_compression,
1454 descriptor->plane_descriptors[descriptor_plane_id]);
1455 }
1456
1457 static unsigned
1458 radv_plane_from_aspect(VkImageAspectFlags mask)
1459 {
1460 switch(mask) {
1461 case VK_IMAGE_ASPECT_PLANE_1_BIT:
1462 return 1;
1463 case VK_IMAGE_ASPECT_PLANE_2_BIT:
1464 return 2;
1465 default:
1466 return 0;
1467 }
1468 }
1469
1470 VkFormat
1471 radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask)
1472 {
1473 switch(mask) {
1474 case VK_IMAGE_ASPECT_PLANE_0_BIT:
1475 return image->planes[0].format;
1476 case VK_IMAGE_ASPECT_PLANE_1_BIT:
1477 return image->planes[1].format;
1478 case VK_IMAGE_ASPECT_PLANE_2_BIT:
1479 return image->planes[2].format;
1480 case VK_IMAGE_ASPECT_STENCIL_BIT:
1481 return vk_format_stencil_only(image->vk_format);
1482 case VK_IMAGE_ASPECT_DEPTH_BIT:
1483 return vk_format_depth_only(image->vk_format);
1484 case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
1485 return vk_format_depth_only(image->vk_format);
1486 default:
1487 return image->vk_format;
1488 }
1489 }
1490
1491 void
1492 radv_image_view_init(struct radv_image_view *iview,
1493 struct radv_device *device,
1494 const VkImageViewCreateInfo* pCreateInfo,
1495 const struct radv_image_view_extra_create_info* extra_create_info)
1496 {
1497 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
1498 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
1499
1500 switch (image->type) {
1501 case VK_IMAGE_TYPE_1D:
1502 case VK_IMAGE_TYPE_2D:
1503 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size);
1504 break;
1505 case VK_IMAGE_TYPE_3D:
1506 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
1507 <= radv_minify(image->info.depth, range->baseMipLevel));
1508 break;
1509 default:
1510 unreachable("bad VkImageType");
1511 }
1512 iview->image = image;
1513 iview->bo = image->bo;
1514 iview->type = pCreateInfo->viewType;
1515 iview->plane_id = radv_plane_from_aspect(pCreateInfo->subresourceRange.aspectMask);
1516 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
1517 iview->multiple_planes = vk_format_get_plane_count(image->vk_format) > 1 && iview->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT;
1518 iview->vk_format = pCreateInfo->format;
1519
1520 if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
1521 iview->vk_format = vk_format_stencil_only(iview->vk_format);
1522 } else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
1523 iview->vk_format = vk_format_depth_only(iview->vk_format);
1524 }
1525
1526 if (device->physical_device->rad_info.chip_class >= GFX9) {
1527 iview->extent = (VkExtent3D) {
1528 .width = image->info.width,
1529 .height = image->info.height,
1530 .depth = image->info.depth,
1531 };
1532 } else {
1533 iview->extent = (VkExtent3D) {
1534 .width = radv_minify(image->info.width , range->baseMipLevel),
1535 .height = radv_minify(image->info.height, range->baseMipLevel),
1536 .depth = radv_minify(image->info.depth , range->baseMipLevel),
1537 };
1538 }
1539
1540 if (iview->vk_format != image->planes[iview->plane_id].format) {
1541 unsigned view_bw = vk_format_get_blockwidth(iview->vk_format);
1542 unsigned view_bh = vk_format_get_blockheight(iview->vk_format);
1543 unsigned img_bw = vk_format_get_blockwidth(image->vk_format);
1544 unsigned img_bh = vk_format_get_blockheight(image->vk_format);
1545
1546 iview->extent.width = round_up_u32(iview->extent.width * view_bw, img_bw);
1547 iview->extent.height = round_up_u32(iview->extent.height * view_bh, img_bh);
1548
1549 /* Comment ported from amdvlk -
1550 * If we have the following image:
1551 * Uncompressed pixels Compressed block sizes (4x4)
1552 * mip0: 22 x 22 6 x 6
1553 * mip1: 11 x 11 3 x 3
1554 * mip2: 5 x 5 2 x 2
1555 * mip3: 2 x 2 1 x 1
1556 * mip4: 1 x 1 1 x 1
1557 *
1558 * On GFX9 the descriptor is always programmed with the WIDTH and HEIGHT of the base level and the HW is
1559 * calculating the degradation of the block sizes down the mip-chain as follows (straight-up
1560 * divide-by-two integer math):
1561 * mip0: 6x6
1562 * mip1: 3x3
1563 * mip2: 1x1
1564 * mip3: 1x1
1565 *
1566 * This means that mip2 will be missing texels.
1567 *
1568 * Fix this by calculating the base mip's width and height, then convert that, and round it
1569 * back up to get the level 0 size.
1570 * Clamp the converted size between the original values, and next power of two, which
1571 * means we don't oversize the image.
1572 */
1573 if (device->physical_device->rad_info.chip_class >= GFX9 &&
1574 vk_format_is_compressed(image->vk_format) &&
1575 !vk_format_is_compressed(iview->vk_format)) {
1576 unsigned lvl_width = radv_minify(image->info.width , range->baseMipLevel);
1577 unsigned lvl_height = radv_minify(image->info.height, range->baseMipLevel);
1578
1579 lvl_width = round_up_u32(lvl_width * view_bw, img_bw);
1580 lvl_height = round_up_u32(lvl_height * view_bh, img_bh);
1581
1582 lvl_width <<= range->baseMipLevel;
1583 lvl_height <<= range->baseMipLevel;
1584
1585 iview->extent.width = CLAMP(lvl_width, iview->extent.width, iview->image->planes[0].surface.u.gfx9.surf_pitch);
1586 iview->extent.height = CLAMP(lvl_height, iview->extent.height, iview->image->planes[0].surface.u.gfx9.surf_height);
1587 }
1588 }
1589
1590 iview->base_layer = range->baseArrayLayer;
1591 iview->layer_count = radv_get_layerCount(image, range);
1592 iview->base_mip = range->baseMipLevel;
1593 iview->level_count = radv_get_levelCount(image, range);
1594
1595 bool disable_compression = extra_create_info ? extra_create_info->disable_compression: false;
1596 for (unsigned i = 0; i < (iview->multiple_planes ? vk_format_get_plane_count(image->vk_format) : 1); ++i) {
1597 VkFormat format = vk_format_get_plane_format(iview->vk_format, i);
1598 radv_image_view_make_descriptor(iview, device, format,
1599 &pCreateInfo->components,
1600 false, disable_compression,
1601 iview->plane_id + i, i);
1602 radv_image_view_make_descriptor(iview, device,
1603 format, &pCreateInfo->components,
1604 true, disable_compression,
1605 iview->plane_id + i, i);
1606 }
1607 }
1608
1609 bool radv_layout_has_htile(const struct radv_image *image,
1610 VkImageLayout layout,
1611 bool in_render_loop,
1612 unsigned queue_mask)
1613 {
1614 if (radv_image_is_tc_compat_htile(image))
1615 return !in_render_loop;
1616
1617 return radv_image_has_htile(image) &&
1618 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1619 (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1620 queue_mask == (1u << RADV_QUEUE_GENERAL)));
1621 }
1622
1623 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1624 VkImageLayout layout,
1625 bool in_render_loop,
1626 unsigned queue_mask)
1627 {
1628 if (radv_image_is_tc_compat_htile(image))
1629 return !in_render_loop;
1630
1631 return radv_image_has_htile(image) &&
1632 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1633 (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1634 queue_mask == (1u << RADV_QUEUE_GENERAL)));
1635 }
1636
1637 bool radv_layout_can_fast_clear(const struct radv_image *image,
1638 VkImageLayout layout,
1639 bool in_render_loop,
1640 unsigned queue_mask)
1641 {
1642 return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
1643 }
1644
1645 bool radv_layout_dcc_compressed(const struct radv_device *device,
1646 const struct radv_image *image,
1647 VkImageLayout layout,
1648 bool in_render_loop,
1649 unsigned queue_mask)
1650 {
1651 /* Don't compress compute transfer dst, as image stores are not supported. */
1652 if (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1653 (queue_mask & (1u << RADV_QUEUE_COMPUTE)))
1654 return false;
1655
1656 return radv_image_has_dcc(image) &&!in_render_loop;
1657 }
1658
1659
1660 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
1661 {
1662 if (!image->exclusive)
1663 return image->queue_family_mask;
1664 if (family == VK_QUEUE_FAMILY_EXTERNAL ||
1665 family == VK_QUEUE_FAMILY_FOREIGN_EXT)
1666 return (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1667 if (family == VK_QUEUE_FAMILY_IGNORED)
1668 return 1u << queue_family;
1669 return 1u << family;
1670 }
1671
1672 VkResult
1673 radv_CreateImage(VkDevice device,
1674 const VkImageCreateInfo *pCreateInfo,
1675 const VkAllocationCallbacks *pAllocator,
1676 VkImage *pImage)
1677 {
1678 #ifdef ANDROID
1679 const VkNativeBufferANDROID *gralloc_info =
1680 vk_find_struct_const(pCreateInfo->pNext, NATIVE_BUFFER_ANDROID);
1681
1682 if (gralloc_info)
1683 return radv_image_from_gralloc(device, pCreateInfo, gralloc_info,
1684 pAllocator, pImage);
1685 #endif
1686
1687 const struct wsi_image_create_info *wsi_info =
1688 vk_find_struct_const(pCreateInfo->pNext, WSI_IMAGE_CREATE_INFO_MESA);
1689 bool scanout = wsi_info && wsi_info->scanout;
1690
1691 return radv_image_create(device,
1692 &(struct radv_image_create_info) {
1693 .vk_info = pCreateInfo,
1694 .scanout = scanout,
1695 },
1696 pAllocator,
1697 pImage);
1698 }
1699
1700 void
1701 radv_DestroyImage(VkDevice _device, VkImage _image,
1702 const VkAllocationCallbacks *pAllocator)
1703 {
1704 RADV_FROM_HANDLE(radv_device, device, _device);
1705 RADV_FROM_HANDLE(radv_image, image, _image);
1706
1707 if (!image)
1708 return;
1709
1710 if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
1711 device->ws->buffer_destroy(image->bo);
1712
1713 if (image->owned_memory != VK_NULL_HANDLE)
1714 radv_FreeMemory(_device, image->owned_memory, pAllocator);
1715
1716 vk_free2(&device->alloc, pAllocator, image);
1717 }
1718
1719 void radv_GetImageSubresourceLayout(
1720 VkDevice _device,
1721 VkImage _image,
1722 const VkImageSubresource* pSubresource,
1723 VkSubresourceLayout* pLayout)
1724 {
1725 RADV_FROM_HANDLE(radv_image, image, _image);
1726 RADV_FROM_HANDLE(radv_device, device, _device);
1727 int level = pSubresource->mipLevel;
1728 int layer = pSubresource->arrayLayer;
1729
1730 unsigned plane_id = radv_plane_from_aspect(pSubresource->aspectMask);
1731
1732 struct radv_image_plane *plane = &image->planes[plane_id];
1733 struct radeon_surf *surface = &plane->surface;
1734
1735 if (device->physical_device->rad_info.chip_class >= GFX9) {
1736 pLayout->offset = plane->offset + surface->u.gfx9.offset[level] + surface->u.gfx9.surf_slice_size * layer;
1737 if (image->vk_format == VK_FORMAT_R32G32B32_UINT ||
1738 image->vk_format == VK_FORMAT_R32G32B32_SINT ||
1739 image->vk_format == VK_FORMAT_R32G32B32_SFLOAT) {
1740 /* Adjust the number of bytes between each row because
1741 * the pitch is actually the number of components per
1742 * row.
1743 */
1744 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe / 3;
1745 } else {
1746 assert(util_is_power_of_two_nonzero(surface->bpe));
1747 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe;
1748 }
1749
1750 pLayout->arrayPitch = surface->u.gfx9.surf_slice_size;
1751 pLayout->depthPitch = surface->u.gfx9.surf_slice_size;
1752 pLayout->size = surface->u.gfx9.surf_slice_size;
1753 if (image->type == VK_IMAGE_TYPE_3D)
1754 pLayout->size *= u_minify(image->info.depth, level);
1755 } else {
1756 pLayout->offset = plane->offset + surface->u.legacy.level[level].offset + (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4 * layer;
1757 pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
1758 pLayout->arrayPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1759 pLayout->depthPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1760 pLayout->size = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1761 if (image->type == VK_IMAGE_TYPE_3D)
1762 pLayout->size *= u_minify(image->info.depth, level);
1763 }
1764 }
1765
1766
1767 VkResult
1768 radv_CreateImageView(VkDevice _device,
1769 const VkImageViewCreateInfo *pCreateInfo,
1770 const VkAllocationCallbacks *pAllocator,
1771 VkImageView *pView)
1772 {
1773 RADV_FROM_HANDLE(radv_device, device, _device);
1774 struct radv_image_view *view;
1775
1776 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1777 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1778 if (view == NULL)
1779 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1780
1781 radv_image_view_init(view, device, pCreateInfo, NULL);
1782
1783 *pView = radv_image_view_to_handle(view);
1784
1785 return VK_SUCCESS;
1786 }
1787
1788 void
1789 radv_DestroyImageView(VkDevice _device, VkImageView _iview,
1790 const VkAllocationCallbacks *pAllocator)
1791 {
1792 RADV_FROM_HANDLE(radv_device, device, _device);
1793 RADV_FROM_HANDLE(radv_image_view, iview, _iview);
1794
1795 if (!iview)
1796 return;
1797 vk_free2(&device->alloc, pAllocator, iview);
1798 }
1799
1800 void radv_buffer_view_init(struct radv_buffer_view *view,
1801 struct radv_device *device,
1802 const VkBufferViewCreateInfo* pCreateInfo)
1803 {
1804 RADV_FROM_HANDLE(radv_buffer, buffer, pCreateInfo->buffer);
1805
1806 view->bo = buffer->bo;
1807 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
1808 buffer->size - pCreateInfo->offset : pCreateInfo->range;
1809 view->vk_format = pCreateInfo->format;
1810
1811 radv_make_buffer_descriptor(device, buffer, view->vk_format,
1812 pCreateInfo->offset, view->range, view->state);
1813 }
1814
1815 VkResult
1816 radv_CreateBufferView(VkDevice _device,
1817 const VkBufferViewCreateInfo *pCreateInfo,
1818 const VkAllocationCallbacks *pAllocator,
1819 VkBufferView *pView)
1820 {
1821 RADV_FROM_HANDLE(radv_device, device, _device);
1822 struct radv_buffer_view *view;
1823
1824 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1825 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1826 if (!view)
1827 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1828
1829 radv_buffer_view_init(view, device, pCreateInfo);
1830
1831 *pView = radv_buffer_view_to_handle(view);
1832
1833 return VK_SUCCESS;
1834 }
1835
1836 void
1837 radv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
1838 const VkAllocationCallbacks *pAllocator)
1839 {
1840 RADV_FROM_HANDLE(radv_device, device, _device);
1841 RADV_FROM_HANDLE(radv_buffer_view, view, bufferView);
1842
1843 if (!view)
1844 return;
1845
1846 vk_free2(&device->alloc, pAllocator, view);
1847 }