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radv: Do not decompress on LAYOUT_GENERAL.
[mesa.git] / src / amd / vulkan / radv_image.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "vk_format.h"
31 #include "vk_util.h"
32 #include "radv_radeon_winsys.h"
33 #include "sid.h"
34 #include "util/debug.h"
35 #include "util/u_atomic.h"
36
37 static unsigned
38 radv_choose_tiling(struct radv_device *device,
39 const struct radv_image_create_info *create_info)
40 {
41 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
42
43 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) {
44 assert(pCreateInfo->samples <= 1);
45 return RADEON_SURF_MODE_LINEAR_ALIGNED;
46 }
47
48 if (!vk_format_is_compressed(pCreateInfo->format) &&
49 !vk_format_is_depth_or_stencil(pCreateInfo->format)
50 && device->physical_device->rad_info.chip_class <= GFX8) {
51 /* this causes hangs in some VK CTS tests on GFX9. */
52 /* Textures with a very small height are recommended to be linear. */
53 if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
54 /* Only very thin and long 2D textures should benefit from
55 * linear_aligned. */
56 (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
57 return RADEON_SURF_MODE_LINEAR_ALIGNED;
58 }
59
60 /* MSAA resources must be 2D tiled. */
61 if (pCreateInfo->samples > 1)
62 return RADEON_SURF_MODE_2D;
63
64 return RADEON_SURF_MODE_2D;
65 }
66
67 static bool
68 radv_use_tc_compat_htile_for_image(struct radv_device *device,
69 const VkImageCreateInfo *pCreateInfo)
70 {
71 /* TC-compat HTILE is only available for GFX8+. */
72 if (device->physical_device->rad_info.chip_class < GFX8)
73 return false;
74
75 if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
76 (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
77 return false;
78
79 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
80 return false;
81
82 if (pCreateInfo->mipLevels > 1)
83 return false;
84
85 /* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
86 * tests - disable for now. On GFX10 D32_SFLOAT is affected as well.
87 */
88 if (pCreateInfo->samples >= 2 &&
89 (pCreateInfo->format == VK_FORMAT_D32_SFLOAT_S8_UINT ||
90 (pCreateInfo->format == VK_FORMAT_D32_SFLOAT &&
91 device->physical_device->rad_info.chip_class == GFX10)))
92 return false;
93
94 /* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only
95 * supports 32-bit. Though, it's possible to enable TC-compat for
96 * 16-bit depth surfaces if no Z planes are compressed.
97 */
98 if (pCreateInfo->format != VK_FORMAT_D32_SFLOAT_S8_UINT &&
99 pCreateInfo->format != VK_FORMAT_D32_SFLOAT &&
100 pCreateInfo->format != VK_FORMAT_D16_UNORM)
101 return false;
102
103 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
104 const struct VkImageFormatListCreateInfoKHR *format_list =
105 (const struct VkImageFormatListCreateInfoKHR *)
106 vk_find_struct_const(pCreateInfo->pNext,
107 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
108
109 /* We have to ignore the existence of the list if viewFormatCount = 0 */
110 if (format_list && format_list->viewFormatCount) {
111 /* compatibility is transitive, so we only need to check
112 * one format with everything else.
113 */
114 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
115 if (format_list->pViewFormats[i] == VK_FORMAT_UNDEFINED)
116 continue;
117
118 if (pCreateInfo->format != format_list->pViewFormats[i])
119 return false;
120 }
121 } else {
122 return false;
123 }
124 }
125
126 return true;
127 }
128
129 static bool
130 radv_surface_has_scanout(struct radv_device *device, const struct radv_image_create_info *info)
131 {
132 if (info->scanout)
133 return true;
134
135 if (!info->bo_metadata)
136 return false;
137
138 if (device->physical_device->rad_info.chip_class >= GFX9) {
139 return info->bo_metadata->u.gfx9.swizzle_mode == 0 || info->bo_metadata->u.gfx9.swizzle_mode % 4 == 2;
140 } else {
141 return info->bo_metadata->u.legacy.scanout;
142 }
143 }
144
145 static bool
146 radv_use_dcc_for_image(struct radv_device *device,
147 const struct radv_image *image,
148 const struct radv_image_create_info *create_info,
149 const VkImageCreateInfo *pCreateInfo)
150 {
151 bool dcc_compatible_formats;
152 bool blendable;
153
154 /* DCC (Delta Color Compression) is only available for GFX8+. */
155 if (device->physical_device->rad_info.chip_class < GFX8)
156 return false;
157
158 if (device->instance->debug_flags & RADV_DEBUG_NO_DCC)
159 return false;
160
161 if (image->shareable)
162 return false;
163
164 /* TODO: Enable DCC for storage images. */
165 if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
166 (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
167 return false;
168
169 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
170 return false;
171
172 if (vk_format_is_subsampled(pCreateInfo->format) ||
173 vk_format_get_plane_count(pCreateInfo->format) > 1)
174 return false;
175
176 /* TODO: Enable DCC for mipmaps on GFX9+. */
177 if ((pCreateInfo->arrayLayers > 1 || pCreateInfo->mipLevels > 1) &&
178 device->physical_device->rad_info.chip_class >= GFX9)
179 return false;
180
181 /* Do not enable DCC for mipmapped arrays because performance is worse. */
182 if (pCreateInfo->arrayLayers > 1 && pCreateInfo->mipLevels > 1)
183 return false;
184
185 if (radv_surface_has_scanout(device, create_info))
186 return false;
187
188 /* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet, while
189 * 2x can be enabled with an option.
190 */
191 if (pCreateInfo->samples > 2 ||
192 (pCreateInfo->samples == 2 &&
193 !device->physical_device->dcc_msaa_allowed))
194 return false;
195
196 /* Determine if the formats are DCC compatible. */
197 dcc_compatible_formats =
198 radv_is_colorbuffer_format_supported(pCreateInfo->format,
199 &blendable);
200
201 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
202 const struct VkImageFormatListCreateInfoKHR *format_list =
203 (const struct VkImageFormatListCreateInfoKHR *)
204 vk_find_struct_const(pCreateInfo->pNext,
205 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
206
207 /* We have to ignore the existence of the list if viewFormatCount = 0 */
208 if (format_list && format_list->viewFormatCount) {
209 /* compatibility is transitive, so we only need to check
210 * one format with everything else. */
211 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
212 if (format_list->pViewFormats[i] == VK_FORMAT_UNDEFINED)
213 continue;
214
215 if (!radv_dcc_formats_compatible(pCreateInfo->format,
216 format_list->pViewFormats[i]))
217 dcc_compatible_formats = false;
218 }
219 } else {
220 dcc_compatible_formats = false;
221 }
222 }
223
224 if (!dcc_compatible_formats)
225 return false;
226
227 return true;
228 }
229
230 static bool
231 radv_use_tc_compat_cmask_for_image(struct radv_device *device,
232 struct radv_image *image)
233 {
234 if (!(device->instance->perftest_flags & RADV_PERFTEST_TC_COMPAT_CMASK))
235 return false;
236
237 /* TC-compat CMASK is only available for GFX8+. */
238 if (device->physical_device->rad_info.chip_class < GFX8)
239 return false;
240
241 if (image->usage & VK_IMAGE_USAGE_STORAGE_BIT)
242 return false;
243
244 if (radv_image_has_dcc(image))
245 return false;
246
247 if (!radv_image_has_cmask(image))
248 return false;
249
250 return true;
251 }
252
253 static void
254 radv_prefill_surface_from_metadata(struct radv_device *device,
255 struct radeon_surf *surface,
256 const struct radv_image_create_info *create_info)
257 {
258 const struct radeon_bo_metadata *md = create_info->bo_metadata;
259 if (device->physical_device->rad_info.chip_class >= GFX9) {
260 if (md->u.gfx9.swizzle_mode > 0)
261 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
262 else
263 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
264
265 surface->u.gfx9.surf.swizzle_mode = md->u.gfx9.swizzle_mode;
266 } else {
267 surface->u.legacy.pipe_config = md->u.legacy.pipe_config;
268 surface->u.legacy.bankw = md->u.legacy.bankw;
269 surface->u.legacy.bankh = md->u.legacy.bankh;
270 surface->u.legacy.tile_split = md->u.legacy.tile_split;
271 surface->u.legacy.mtilea = md->u.legacy.mtilea;
272 surface->u.legacy.num_banks = md->u.legacy.num_banks;
273
274 if (md->u.legacy.macrotile == RADEON_LAYOUT_TILED)
275 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
276 else if (md->u.legacy.microtile == RADEON_LAYOUT_TILED)
277 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
278 else
279 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
280
281 }
282 }
283
284 static int
285 radv_init_surface(struct radv_device *device,
286 const struct radv_image *image,
287 struct radeon_surf *surface,
288 unsigned plane_id,
289 const struct radv_image_create_info *create_info)
290 {
291 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
292 unsigned array_mode = radv_choose_tiling(device, create_info);
293 VkFormat format = vk_format_get_plane_format(pCreateInfo->format, plane_id);
294 const struct vk_format_description *desc = vk_format_description(format);
295 bool is_depth, is_stencil;
296
297 is_depth = vk_format_has_depth(desc);
298 is_stencil = vk_format_has_stencil(desc);
299
300 surface->blk_w = vk_format_get_blockwidth(format);
301 surface->blk_h = vk_format_get_blockheight(format);
302
303 surface->bpe = vk_format_get_blocksize(vk_format_depth_only(format));
304 /* align byte per element on dword */
305 if (surface->bpe == 3) {
306 surface->bpe = 4;
307 }
308 if (create_info->bo_metadata) {
309 radv_prefill_surface_from_metadata(device, surface, create_info);
310 } else {
311 surface->flags = RADEON_SURF_SET(array_mode, MODE);
312 }
313
314 switch (pCreateInfo->imageType){
315 case VK_IMAGE_TYPE_1D:
316 if (pCreateInfo->arrayLayers > 1)
317 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
318 else
319 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
320 break;
321 case VK_IMAGE_TYPE_2D:
322 if (pCreateInfo->arrayLayers > 1)
323 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
324 else
325 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
326 break;
327 case VK_IMAGE_TYPE_3D:
328 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
329 break;
330 default:
331 unreachable("unhandled image type");
332 }
333
334 if (is_depth) {
335 surface->flags |= RADEON_SURF_ZBUFFER;
336 if (radv_use_tc_compat_htile_for_image(device, pCreateInfo))
337 surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
338 }
339
340 if (is_stencil)
341 surface->flags |= RADEON_SURF_SBUFFER;
342
343 if (device->physical_device->rad_info.chip_class >= GFX9 &&
344 pCreateInfo->imageType == VK_IMAGE_TYPE_3D &&
345 vk_format_get_blocksizebits(pCreateInfo->format) == 128 &&
346 vk_format_is_compressed(pCreateInfo->format))
347 surface->flags |= RADEON_SURF_NO_RENDER_TARGET;
348
349 surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
350
351 if (!radv_use_dcc_for_image(device, image, create_info, pCreateInfo))
352 surface->flags |= RADEON_SURF_DISABLE_DCC;
353
354 if (radv_surface_has_scanout(device, create_info))
355 surface->flags |= RADEON_SURF_SCANOUT;
356
357 return 0;
358 }
359
360 static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
361 {
362 return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
363 }
364
365 static inline unsigned
366 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
367 {
368 if (stencil)
369 return plane->surface.u.legacy.stencil_tiling_index[level];
370 else
371 return plane->surface.u.legacy.tiling_index[level];
372 }
373
374 static unsigned radv_map_swizzle(unsigned swizzle)
375 {
376 switch (swizzle) {
377 case VK_SWIZZLE_Y:
378 return V_008F0C_SQ_SEL_Y;
379 case VK_SWIZZLE_Z:
380 return V_008F0C_SQ_SEL_Z;
381 case VK_SWIZZLE_W:
382 return V_008F0C_SQ_SEL_W;
383 case VK_SWIZZLE_0:
384 return V_008F0C_SQ_SEL_0;
385 case VK_SWIZZLE_1:
386 return V_008F0C_SQ_SEL_1;
387 default: /* VK_SWIZZLE_X */
388 return V_008F0C_SQ_SEL_X;
389 }
390 }
391
392 static void
393 radv_make_buffer_descriptor(struct radv_device *device,
394 struct radv_buffer *buffer,
395 VkFormat vk_format,
396 unsigned offset,
397 unsigned range,
398 uint32_t *state)
399 {
400 const struct vk_format_description *desc;
401 unsigned stride;
402 uint64_t gpu_address = radv_buffer_get_va(buffer->bo);
403 uint64_t va = gpu_address + buffer->offset;
404 unsigned num_format, data_format;
405 int first_non_void;
406 desc = vk_format_description(vk_format);
407 first_non_void = vk_format_get_first_non_void_channel(vk_format);
408 stride = desc->block.bits / 8;
409
410 va += offset;
411 state[0] = va;
412 state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
413 S_008F04_STRIDE(stride);
414
415 if (device->physical_device->rad_info.chip_class != GFX8 && stride) {
416 range /= stride;
417 }
418
419 state[2] = range;
420 state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
421 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
422 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
423 S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3]));
424
425 if (device->physical_device->rad_info.chip_class >= GFX10) {
426 const struct gfx10_format *fmt = &gfx10_format_table[vk_format];
427
428 /* OOB_SELECT chooses the out-of-bounds check:
429 * - 0: (index >= NUM_RECORDS) || (offset >= STRIDE)
430 * - 1: index >= NUM_RECORDS
431 * - 2: NUM_RECORDS == 0
432 * - 3: if SWIZZLE_ENABLE == 0: offset >= NUM_RECORDS
433 * else: swizzle_address >= NUM_RECORDS
434 */
435 state[3] |= S_008F0C_FORMAT(fmt->img_format) |
436 S_008F0C_OOB_SELECT(0) |
437 S_008F0C_RESOURCE_LEVEL(1);
438 } else {
439 num_format = radv_translate_buffer_numformat(desc, first_non_void);
440 data_format = radv_translate_buffer_dataformat(desc, first_non_void);
441
442 assert(data_format != V_008F0C_BUF_DATA_FORMAT_INVALID);
443 assert(num_format != ~0);
444
445 state[3] |= S_008F0C_NUM_FORMAT(num_format) |
446 S_008F0C_DATA_FORMAT(data_format);
447 }
448 }
449
450 static void
451 si_set_mutable_tex_desc_fields(struct radv_device *device,
452 struct radv_image *image,
453 const struct legacy_surf_level *base_level_info,
454 unsigned plane_id,
455 unsigned base_level, unsigned first_level,
456 unsigned block_width, bool is_stencil,
457 bool is_storage_image, uint32_t *state)
458 {
459 struct radv_image_plane *plane = &image->planes[plane_id];
460 uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0;
461 uint64_t va = gpu_address + plane->offset;
462 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
463 uint64_t meta_va = 0;
464 if (chip_class >= GFX9) {
465 if (is_stencil)
466 va += plane->surface.u.gfx9.stencil_offset;
467 else
468 va += plane->surface.u.gfx9.surf_offset;
469 } else
470 va += base_level_info->offset;
471
472 state[0] = va >> 8;
473 if (chip_class >= GFX9 ||
474 base_level_info->mode == RADEON_SURF_MODE_2D)
475 state[0] |= plane->surface.tile_swizzle;
476 state[1] &= C_008F14_BASE_ADDRESS_HI;
477 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
478
479 if (chip_class >= GFX8) {
480 state[6] &= C_008F28_COMPRESSION_EN;
481 state[7] = 0;
482 if (!is_storage_image && radv_dcc_enabled(image, first_level)) {
483 meta_va = gpu_address + image->dcc_offset;
484 if (chip_class <= GFX8)
485 meta_va += base_level_info->dcc_offset;
486
487 unsigned dcc_tile_swizzle = plane->surface.tile_swizzle << 8;
488 dcc_tile_swizzle &= plane->surface.dcc_alignment - 1;
489 meta_va |= dcc_tile_swizzle;
490 } else if (!is_storage_image &&
491 radv_image_is_tc_compat_htile(image)) {
492 meta_va = gpu_address + image->htile_offset;
493 }
494
495 if (meta_va) {
496 state[6] |= S_008F28_COMPRESSION_EN(1);
497 if (chip_class <= GFX9)
498 state[7] = meta_va >> 8;
499 }
500 }
501
502 if (chip_class >= GFX10) {
503 state[3] &= C_00A00C_SW_MODE;
504
505 if (is_stencil) {
506 state[3] |= S_00A00C_SW_MODE(plane->surface.u.gfx9.stencil.swizzle_mode);
507 } else {
508 state[3] |= S_00A00C_SW_MODE(plane->surface.u.gfx9.surf.swizzle_mode);
509 }
510
511 state[6] &= C_00A018_META_DATA_ADDRESS_LO &
512 C_00A018_META_PIPE_ALIGNED;
513
514 if (meta_va) {
515 struct gfx9_surf_meta_flags meta;
516
517 if (image->dcc_offset)
518 meta = plane->surface.u.gfx9.dcc;
519 else
520 meta = plane->surface.u.gfx9.htile;
521
522 state[6] |= S_00A018_META_PIPE_ALIGNED(meta.pipe_aligned) |
523 S_00A018_META_DATA_ADDRESS_LO(meta_va >> 8);
524 }
525
526 state[7] = meta_va >> 16;
527 } else if (chip_class == GFX9) {
528 state[3] &= C_008F1C_SW_MODE;
529 state[4] &= C_008F20_PITCH;
530
531 if (is_stencil) {
532 state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.stencil.swizzle_mode);
533 state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.stencil.epitch);
534 } else {
535 state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.surf.swizzle_mode);
536 state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.surf.epitch);
537 }
538
539 state[5] &= C_008F24_META_DATA_ADDRESS &
540 C_008F24_META_PIPE_ALIGNED &
541 C_008F24_META_RB_ALIGNED;
542 if (meta_va) {
543 struct gfx9_surf_meta_flags meta;
544
545 if (image->dcc_offset)
546 meta = plane->surface.u.gfx9.dcc;
547 else
548 meta = plane->surface.u.gfx9.htile;
549
550 state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
551 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
552 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
553 }
554 } else {
555 /* GFX6-GFX8 */
556 unsigned pitch = base_level_info->nblk_x * block_width;
557 unsigned index = si_tile_mode_index(plane, base_level, is_stencil);
558
559 state[3] &= C_008F1C_TILING_INDEX;
560 state[3] |= S_008F1C_TILING_INDEX(index);
561 state[4] &= C_008F20_PITCH;
562 state[4] |= S_008F20_PITCH(pitch - 1);
563 }
564 }
565
566 static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
567 unsigned nr_layers, unsigned nr_samples, bool is_storage_image, bool gfx9)
568 {
569 if (view_type == VK_IMAGE_VIEW_TYPE_CUBE || view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY)
570 return is_storage_image ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_CUBE;
571
572 /* GFX9 allocates 1D textures as 2D. */
573 if (gfx9 && image_type == VK_IMAGE_TYPE_1D)
574 image_type = VK_IMAGE_TYPE_2D;
575 switch (image_type) {
576 case VK_IMAGE_TYPE_1D:
577 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY : V_008F1C_SQ_RSRC_IMG_1D;
578 case VK_IMAGE_TYPE_2D:
579 if (nr_samples > 1)
580 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_MSAA;
581 else
582 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_2D;
583 case VK_IMAGE_TYPE_3D:
584 if (view_type == VK_IMAGE_VIEW_TYPE_3D)
585 return V_008F1C_SQ_RSRC_IMG_3D;
586 else
587 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
588 default:
589 unreachable("illegal image type");
590 }
591 }
592
593 static unsigned gfx9_border_color_swizzle(const enum vk_swizzle swizzle[4])
594 {
595 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
596
597 if (swizzle[3] == VK_SWIZZLE_X) {
598 /* For the pre-defined border color values (white, opaque
599 * black, transparent black), the only thing that matters is
600 * that the alpha channel winds up in the correct place
601 * (because the RGB channels are all the same) so either of
602 * these enumerations will work.
603 */
604 if (swizzle[2] == VK_SWIZZLE_Y)
605 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
606 else
607 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
608 } else if (swizzle[0] == VK_SWIZZLE_X) {
609 if (swizzle[1] == VK_SWIZZLE_Y)
610 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
611 else
612 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
613 } else if (swizzle[1] == VK_SWIZZLE_X) {
614 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
615 } else if (swizzle[2] == VK_SWIZZLE_X) {
616 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
617 }
618
619 return bc_swizzle;
620 }
621
622 static bool vi_alpha_is_on_msb(struct radv_device *device, VkFormat format)
623 {
624 const struct vk_format_description *desc = vk_format_description(format);
625
626 if (device->physical_device->rad_info.chip_class >= GFX10 && desc->nr_channels == 1)
627 return desc->swizzle[3] == VK_SWIZZLE_X;
628
629 return radv_translate_colorswap(format, false) <= 1;
630 }
631 /**
632 * Build the sampler view descriptor for a texture (GFX10).
633 */
634 static void
635 gfx10_make_texture_descriptor(struct radv_device *device,
636 struct radv_image *image,
637 bool is_storage_image,
638 VkImageViewType view_type,
639 VkFormat vk_format,
640 const VkComponentMapping *mapping,
641 unsigned first_level, unsigned last_level,
642 unsigned first_layer, unsigned last_layer,
643 unsigned width, unsigned height, unsigned depth,
644 uint32_t *state,
645 uint32_t *fmask_state)
646 {
647 const struct vk_format_description *desc;
648 enum vk_swizzle swizzle[4];
649 unsigned img_format;
650 unsigned type;
651
652 desc = vk_format_description(vk_format);
653 img_format = gfx10_format_table[vk_format].img_format;
654
655 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
656 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
657 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
658 } else {
659 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
660 }
661
662 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
663 is_storage_image, device->physical_device->rad_info.chip_class == GFX9);
664 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
665 height = 1;
666 depth = image->info.array_size;
667 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
668 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
669 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
670 depth = image->info.array_size;
671 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
672 depth = image->info.array_size / 6;
673
674 state[0] = 0;
675 state[1] = S_00A004_FORMAT(img_format) |
676 S_00A004_WIDTH_LO(width - 1);
677 state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
678 S_00A008_HEIGHT(height - 1) |
679 S_00A008_RESOURCE_LEVEL(1);
680 state[3] = S_00A00C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
681 S_00A00C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
682 S_00A00C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
683 S_00A00C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
684 S_00A00C_BASE_LEVEL(image->info.samples > 1 ?
685 0 : first_level) |
686 S_00A00C_LAST_LEVEL(image->info.samples > 1 ?
687 util_logbase2(image->info.samples) :
688 last_level) |
689 S_00A00C_BC_SWIZZLE(gfx9_border_color_swizzle(swizzle)) |
690 S_00A00C_TYPE(type);
691 /* Depth is the the last accessible layer on gfx9+. The hw doesn't need
692 * to know the total number of layers.
693 */
694 state[4] = S_00A010_DEPTH(type == V_008F1C_SQ_RSRC_IMG_3D ? depth - 1 : last_layer) |
695 S_00A010_BASE_ARRAY(first_layer);
696 state[5] = S_00A014_ARRAY_PITCH(!!(type == V_008F1C_SQ_RSRC_IMG_3D)) |
697 S_00A014_MAX_MIP(image->info.samples > 1 ?
698 util_logbase2(image->info.samples) :
699 image->info.levels - 1) |
700 S_00A014_PERF_MOD(4);
701 state[6] = 0;
702 state[7] = 0;
703
704 if (radv_dcc_enabled(image, first_level)) {
705 state[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
706 S_00A018_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B) |
707 S_00A018_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(device, vk_format));
708 }
709
710 /* Initialize the sampler view for FMASK. */
711 if (radv_image_has_fmask(image)) {
712 uint64_t gpu_address = radv_buffer_get_va(image->bo);
713 uint32_t format;
714 uint64_t va;
715
716 assert(image->plane_count == 1);
717
718 va = gpu_address + image->offset + image->fmask_offset;
719
720 switch (image->info.samples) {
721 case 2:
722 format = V_008F0C_IMG_FORMAT_FMASK8_S2_F2;
723 break;
724 case 4:
725 format = V_008F0C_IMG_FORMAT_FMASK8_S4_F4;
726 break;
727 case 8:
728 format = V_008F0C_IMG_FORMAT_FMASK32_S8_F8;
729 break;
730 default:
731 unreachable("invalid nr_samples");
732 }
733
734 fmask_state[0] = (va >> 8) | image->planes[0].surface.fmask_tile_swizzle;
735 fmask_state[1] = S_00A004_BASE_ADDRESS_HI(va >> 40) |
736 S_00A004_FORMAT(format) |
737 S_00A004_WIDTH_LO(width - 1);
738 fmask_state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
739 S_00A008_HEIGHT(height - 1) |
740 S_00A008_RESOURCE_LEVEL(1);
741 fmask_state[3] = S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
742 S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
743 S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
744 S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
745 S_00A00C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode) |
746 S_00A00C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
747 fmask_state[4] = S_00A010_DEPTH(last_layer) |
748 S_00A010_BASE_ARRAY(first_layer);
749 fmask_state[5] = 0;
750 fmask_state[6] = S_00A018_META_PIPE_ALIGNED(image->planes[0].surface.u.gfx9.cmask.pipe_aligned);
751 fmask_state[7] = 0;
752 } else if (fmask_state)
753 memset(fmask_state, 0, 8 * 4);
754 }
755
756 /**
757 * Build the sampler view descriptor for a texture (SI-GFX9)
758 */
759 static void
760 si_make_texture_descriptor(struct radv_device *device,
761 struct radv_image *image,
762 bool is_storage_image,
763 VkImageViewType view_type,
764 VkFormat vk_format,
765 const VkComponentMapping *mapping,
766 unsigned first_level, unsigned last_level,
767 unsigned first_layer, unsigned last_layer,
768 unsigned width, unsigned height, unsigned depth,
769 uint32_t *state,
770 uint32_t *fmask_state)
771 {
772 const struct vk_format_description *desc;
773 enum vk_swizzle swizzle[4];
774 int first_non_void;
775 unsigned num_format, data_format, type;
776
777 desc = vk_format_description(vk_format);
778
779 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
780 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
781 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
782 } else {
783 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
784 }
785
786 first_non_void = vk_format_get_first_non_void_channel(vk_format);
787
788 num_format = radv_translate_tex_numformat(vk_format, desc, first_non_void);
789 if (num_format == ~0) {
790 num_format = 0;
791 }
792
793 data_format = radv_translate_tex_dataformat(vk_format, desc, first_non_void);
794 if (data_format == ~0) {
795 data_format = 0;
796 }
797
798 /* S8 with either Z16 or Z32 HTILE need a special format. */
799 if (device->physical_device->rad_info.chip_class == GFX9 &&
800 vk_format == VK_FORMAT_S8_UINT &&
801 radv_image_is_tc_compat_htile(image)) {
802 if (image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT)
803 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
804 else if (image->vk_format == VK_FORMAT_D16_UNORM_S8_UINT)
805 data_format = V_008F14_IMG_DATA_FORMAT_S8_16;
806 }
807 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
808 is_storage_image, device->physical_device->rad_info.chip_class == GFX9);
809 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
810 height = 1;
811 depth = image->info.array_size;
812 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
813 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
814 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
815 depth = image->info.array_size;
816 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
817 depth = image->info.array_size / 6;
818
819 state[0] = 0;
820 state[1] = (S_008F14_DATA_FORMAT(data_format) |
821 S_008F14_NUM_FORMAT(num_format));
822 state[2] = (S_008F18_WIDTH(width - 1) |
823 S_008F18_HEIGHT(height - 1) |
824 S_008F18_PERF_MOD(4));
825 state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
826 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
827 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
828 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
829 S_008F1C_BASE_LEVEL(image->info.samples > 1 ?
830 0 : first_level) |
831 S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
832 util_logbase2(image->info.samples) :
833 last_level) |
834 S_008F1C_TYPE(type));
835 state[4] = 0;
836 state[5] = S_008F24_BASE_ARRAY(first_layer);
837 state[6] = 0;
838 state[7] = 0;
839
840 if (device->physical_device->rad_info.chip_class == GFX9) {
841 unsigned bc_swizzle = gfx9_border_color_swizzle(swizzle);
842
843 /* Depth is the last accessible layer on Gfx9.
844 * The hw doesn't need to know the total number of layers.
845 */
846 if (type == V_008F1C_SQ_RSRC_IMG_3D)
847 state[4] |= S_008F20_DEPTH(depth - 1);
848 else
849 state[4] |= S_008F20_DEPTH(last_layer);
850
851 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
852 state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ?
853 util_logbase2(image->info.samples) :
854 image->info.levels - 1);
855 } else {
856 state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
857 state[4] |= S_008F20_DEPTH(depth - 1);
858 state[5] |= S_008F24_LAST_ARRAY(last_layer);
859 }
860 if (image->dcc_offset) {
861 state[6] = S_008F28_ALPHA_IS_ON_MSB(vi_alpha_is_on_msb(device, vk_format));
862 } else {
863 /* The last dword is unused by hw. The shader uses it to clear
864 * bits in the first dword of sampler state.
865 */
866 if (device->physical_device->rad_info.chip_class <= GFX7 && image->info.samples <= 1) {
867 if (first_level == last_level)
868 state[7] = C_008F30_MAX_ANISO_RATIO;
869 else
870 state[7] = 0xffffffff;
871 }
872 }
873
874 /* Initialize the sampler view for FMASK. */
875 if (radv_image_has_fmask(image)) {
876 uint32_t fmask_format, num_format;
877 uint64_t gpu_address = radv_buffer_get_va(image->bo);
878 uint64_t va;
879
880 assert(image->plane_count == 1);
881
882 va = gpu_address + image->offset + image->fmask_offset;
883
884 if (device->physical_device->rad_info.chip_class == GFX9) {
885 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
886 switch (image->info.samples) {
887 case 2:
888 num_format = V_008F14_IMG_FMASK_8_2_2;
889 break;
890 case 4:
891 num_format = V_008F14_IMG_FMASK_8_4_4;
892 break;
893 case 8:
894 num_format = V_008F14_IMG_FMASK_32_8_8;
895 break;
896 default:
897 unreachable("invalid nr_samples");
898 }
899 } else {
900 switch (image->info.samples) {
901 case 2:
902 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
903 break;
904 case 4:
905 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
906 break;
907 case 8:
908 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
909 break;
910 default:
911 assert(0);
912 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
913 }
914 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
915 }
916
917 fmask_state[0] = va >> 8;
918 fmask_state[0] |= image->planes[0].surface.fmask_tile_swizzle;
919 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
920 S_008F14_DATA_FORMAT(fmask_format) |
921 S_008F14_NUM_FORMAT(num_format);
922 fmask_state[2] = S_008F18_WIDTH(width - 1) |
923 S_008F18_HEIGHT(height - 1);
924 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
925 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
926 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
927 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
928 S_008F1C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
929 fmask_state[4] = 0;
930 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
931 fmask_state[6] = 0;
932 fmask_state[7] = 0;
933
934 if (device->physical_device->rad_info.chip_class == GFX9) {
935 fmask_state[3] |= S_008F1C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode);
936 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
937 S_008F20_PITCH(image->planes[0].surface.u.gfx9.fmask.epitch);
938 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->planes[0].surface.u.gfx9.cmask.pipe_aligned) |
939 S_008F24_META_RB_ALIGNED(image->planes[0].surface.u.gfx9.cmask.rb_aligned);
940
941 if (radv_image_is_tc_compat_cmask(image)) {
942 va = gpu_address + image->offset + image->cmask_offset;
943
944 fmask_state[5] |= S_008F24_META_DATA_ADDRESS(va >> 40);
945 fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
946 fmask_state[7] |= va >> 8;
947 }
948 } else {
949 fmask_state[3] |= S_008F1C_TILING_INDEX(image->planes[0].surface.u.legacy.fmask.tiling_index);
950 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
951 S_008F20_PITCH(image->planes[0].surface.u.legacy.fmask.pitch_in_pixels - 1);
952 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
953
954 if (radv_image_is_tc_compat_cmask(image)) {
955 va = gpu_address + image->offset + image->cmask_offset;
956
957 fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
958 fmask_state[7] |= va >> 8;
959 }
960 }
961 } else if (fmask_state)
962 memset(fmask_state, 0, 8 * 4);
963 }
964
965 static void
966 radv_make_texture_descriptor(struct radv_device *device,
967 struct radv_image *image,
968 bool is_storage_image,
969 VkImageViewType view_type,
970 VkFormat vk_format,
971 const VkComponentMapping *mapping,
972 unsigned first_level, unsigned last_level,
973 unsigned first_layer, unsigned last_layer,
974 unsigned width, unsigned height, unsigned depth,
975 uint32_t *state,
976 uint32_t *fmask_state)
977 {
978 if (device->physical_device->rad_info.chip_class >= GFX10) {
979 gfx10_make_texture_descriptor(device, image, is_storage_image,
980 view_type, vk_format, mapping,
981 first_level, last_level,
982 first_layer, last_layer,
983 width, height, depth,
984 state, fmask_state);
985 } else {
986 si_make_texture_descriptor(device, image, is_storage_image,
987 view_type, vk_format, mapping,
988 first_level, last_level,
989 first_layer, last_layer,
990 width, height, depth,
991 state, fmask_state);
992 }
993 }
994
995 static void
996 radv_query_opaque_metadata(struct radv_device *device,
997 struct radv_image *image,
998 struct radeon_bo_metadata *md)
999 {
1000 static const VkComponentMapping fixedmapping;
1001 uint32_t desc[8], i;
1002
1003 assert(image->plane_count == 1);
1004
1005 /* Metadata image format format version 1:
1006 * [0] = 1 (metadata format identifier)
1007 * [1] = (VENDOR_ID << 16) | PCI_ID
1008 * [2:9] = image descriptor for the whole resource
1009 * [2] is always 0, because the base address is cleared
1010 * [9] is the DCC offset bits [39:8] from the beginning of
1011 * the buffer
1012 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
1013 */
1014 md->metadata[0] = 1; /* metadata image format version 1 */
1015
1016 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
1017 md->metadata[1] = si_get_bo_metadata_word1(device);
1018
1019
1020 radv_make_texture_descriptor(device, image, false,
1021 (VkImageViewType)image->type, image->vk_format,
1022 &fixedmapping, 0, image->info.levels - 1, 0,
1023 image->info.array_size - 1,
1024 image->info.width, image->info.height,
1025 image->info.depth,
1026 desc, NULL);
1027
1028 si_set_mutable_tex_desc_fields(device, image, &image->planes[0].surface.u.legacy.level[0], 0, 0, 0,
1029 image->planes[0].surface.blk_w, false, false, desc);
1030
1031 /* Clear the base address and set the relative DCC offset. */
1032 desc[0] = 0;
1033 desc[1] &= C_008F14_BASE_ADDRESS_HI;
1034 desc[7] = image->dcc_offset >> 8;
1035
1036 /* Dwords [2:9] contain the image descriptor. */
1037 memcpy(&md->metadata[2], desc, sizeof(desc));
1038
1039 /* Dwords [10:..] contain the mipmap level offsets. */
1040 if (device->physical_device->rad_info.chip_class <= GFX8) {
1041 for (i = 0; i <= image->info.levels - 1; i++)
1042 md->metadata[10+i] = image->planes[0].surface.u.legacy.level[i].offset >> 8;
1043 md->size_metadata = (11 + image->info.levels - 1) * 4;
1044 } else
1045 md->size_metadata = 10 * 4;
1046 }
1047
1048 void
1049 radv_init_metadata(struct radv_device *device,
1050 struct radv_image *image,
1051 struct radeon_bo_metadata *metadata)
1052 {
1053 struct radeon_surf *surface = &image->planes[0].surface;
1054
1055 memset(metadata, 0, sizeof(*metadata));
1056
1057 if (device->physical_device->rad_info.chip_class >= GFX9) {
1058 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
1059 } else {
1060 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
1061 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
1062 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
1063 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
1064 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
1065 metadata->u.legacy.bankw = surface->u.legacy.bankw;
1066 metadata->u.legacy.bankh = surface->u.legacy.bankh;
1067 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
1068 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
1069 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
1070 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
1071 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
1072 }
1073 radv_query_opaque_metadata(device, image, metadata);
1074 }
1075
1076 void
1077 radv_image_override_offset_stride(struct radv_device *device,
1078 struct radv_image *image,
1079 uint64_t offset, uint32_t stride)
1080 {
1081 struct radeon_surf *surface = &image->planes[0].surface;
1082 unsigned bpe = vk_format_get_blocksizebits(image->vk_format) / 8;
1083
1084 if (device->physical_device->rad_info.chip_class >= GFX9) {
1085 if (stride) {
1086 surface->u.gfx9.surf_pitch = stride;
1087 surface->u.gfx9.surf_slice_size =
1088 (uint64_t)stride * surface->u.gfx9.surf_height * bpe;
1089 }
1090 surface->u.gfx9.surf_offset = offset;
1091 } else {
1092 surface->u.legacy.level[0].nblk_x = stride;
1093 surface->u.legacy.level[0].slice_size_dw =
1094 ((uint64_t)stride * surface->u.legacy.level[0].nblk_y * bpe) / 4;
1095
1096 if (offset) {
1097 for (unsigned i = 0; i < ARRAY_SIZE(surface->u.legacy.level); ++i)
1098 surface->u.legacy.level[i].offset += offset;
1099 }
1100
1101 }
1102 }
1103
1104 static void
1105 radv_image_alloc_fmask(struct radv_device *device,
1106 struct radv_image *image)
1107 {
1108 unsigned fmask_alignment = image->planes[0].surface.fmask_alignment;
1109
1110 image->fmask_offset = align64(image->size, fmask_alignment);
1111 image->size = image->fmask_offset + image->planes[0].surface.fmask_size;
1112 image->alignment = MAX2(image->alignment, fmask_alignment);
1113 }
1114
1115 static void
1116 radv_image_alloc_cmask(struct radv_device *device,
1117 struct radv_image *image)
1118 {
1119 unsigned cmask_alignment = image->planes[0].surface.cmask_alignment;
1120 unsigned cmask_size = image->planes[0].surface.cmask_size;
1121 uint32_t clear_value_size = 0;
1122
1123 if (!cmask_size)
1124 return;
1125
1126 assert(cmask_alignment);
1127
1128 image->cmask_offset = align64(image->size, cmask_alignment);
1129 /* + 8 for storing the clear values */
1130 if (!image->clear_value_offset) {
1131 image->clear_value_offset = image->cmask_offset + cmask_size;
1132 clear_value_size = 8;
1133 }
1134 image->size = image->cmask_offset + cmask_size + clear_value_size;
1135 image->alignment = MAX2(image->alignment, cmask_alignment);
1136 }
1137
1138 static void
1139 radv_image_alloc_dcc(struct radv_image *image)
1140 {
1141 assert(image->plane_count == 1);
1142
1143 image->dcc_offset = align64(image->size, image->planes[0].surface.dcc_alignment);
1144 /* + 24 for storing the clear values + fce pred + dcc pred for each mip */
1145 image->clear_value_offset = image->dcc_offset + image->planes[0].surface.dcc_size;
1146 image->fce_pred_offset = image->clear_value_offset + 8 * image->info.levels;
1147 image->dcc_pred_offset = image->clear_value_offset + 16 * image->info.levels;
1148 image->size = image->dcc_offset + image->planes[0].surface.dcc_size + 24 * image->info.levels;
1149 image->alignment = MAX2(image->alignment, image->planes[0].surface.dcc_alignment);
1150 }
1151
1152 static void
1153 radv_image_alloc_htile(struct radv_device *device, struct radv_image *image)
1154 {
1155 image->htile_offset = align64(image->size, image->planes[0].surface.htile_alignment);
1156
1157 /* + 8 for storing the clear values */
1158 image->clear_value_offset = image->htile_offset + image->planes[0].surface.htile_size;
1159 image->size = image->clear_value_offset + 8;
1160 if (radv_image_is_tc_compat_htile(image) &&
1161 device->physical_device->has_tc_compat_zrange_bug) {
1162 /* Metadata for the TC-compatible HTILE hardware bug which
1163 * have to be fixed by updating ZRANGE_PRECISION when doing
1164 * fast depth clears to 0.0f.
1165 */
1166 image->tc_compat_zrange_offset = image->size;
1167 image->size = image->tc_compat_zrange_offset + 4;
1168 }
1169 image->alignment = align64(image->alignment, image->planes[0].surface.htile_alignment);
1170 }
1171
1172 static inline bool
1173 radv_image_can_enable_dcc_or_cmask(struct radv_image *image)
1174 {
1175 if (image->info.samples <= 1 &&
1176 image->info.width * image->info.height <= 512 * 512) {
1177 /* Do not enable CMASK or DCC for small surfaces where the cost
1178 * of the eliminate pass can be higher than the benefit of fast
1179 * clear. RadeonSI does this, but the image threshold is
1180 * different.
1181 */
1182 return false;
1183 }
1184
1185 return image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT &&
1186 (image->exclusive || image->queue_family_mask == 1);
1187 }
1188
1189 static inline bool
1190 radv_image_can_enable_dcc(struct radv_device *device, struct radv_image *image)
1191 {
1192 if (!radv_image_can_enable_dcc_or_cmask(image) ||
1193 !radv_image_has_dcc(image))
1194 return false;
1195
1196 /* On GFX8, DCC layers can be interleaved and it's currently only
1197 * enabled if slice size is equal to the per slice fast clear size
1198 * because the driver assumes that portions of multiple layers are
1199 * contiguous during fast clears.
1200 */
1201 if (image->info.array_size > 1) {
1202 const struct legacy_surf_level *surf_level =
1203 &image->planes[0].surface.u.legacy.level[0];
1204
1205 assert(device->physical_device->rad_info.chip_class == GFX8);
1206
1207 if (image->planes[0].surface.dcc_slice_size != surf_level->dcc_fast_clear_size)
1208 return false;
1209 }
1210
1211 return true;
1212 }
1213
1214 static inline bool
1215 radv_image_can_enable_cmask(struct radv_image *image)
1216 {
1217 if (image->planes[0].surface.bpe > 8 && image->info.samples == 1) {
1218 /* Do not enable CMASK for non-MSAA images (fast color clear)
1219 * because 128 bit formats are not supported, but FMASK might
1220 * still be used.
1221 */
1222 return false;
1223 }
1224
1225 return radv_image_can_enable_dcc_or_cmask(image) &&
1226 image->info.levels == 1 &&
1227 image->info.depth == 1 &&
1228 !image->planes[0].surface.is_linear;
1229 }
1230
1231 static inline bool
1232 radv_image_can_enable_fmask(struct radv_image *image)
1233 {
1234 return image->info.samples > 1 && vk_format_is_color(image->vk_format);
1235 }
1236
1237 static inline bool
1238 radv_image_can_enable_htile(struct radv_image *image)
1239 {
1240 return radv_image_has_htile(image) &&
1241 image->info.levels == 1 &&
1242 image->info.width * image->info.height >= 8 * 8;
1243 }
1244
1245 static void radv_image_disable_dcc(struct radv_image *image)
1246 {
1247 for (unsigned i = 0; i < image->plane_count; ++i)
1248 image->planes[i].surface.dcc_size = 0;
1249 }
1250
1251 static void radv_image_disable_htile(struct radv_image *image)
1252 {
1253 for (unsigned i = 0; i < image->plane_count; ++i)
1254 image->planes[i].surface.htile_size = 0;
1255 }
1256
1257 VkResult
1258 radv_image_create(VkDevice _device,
1259 const struct radv_image_create_info *create_info,
1260 const VkAllocationCallbacks* alloc,
1261 VkImage *pImage)
1262 {
1263 RADV_FROM_HANDLE(radv_device, device, _device);
1264 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
1265 struct radv_image *image = NULL;
1266 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
1267
1268 const unsigned plane_count = vk_format_get_plane_count(pCreateInfo->format);
1269 const size_t image_struct_size = sizeof(*image) + sizeof(struct radv_image_plane) * plane_count;
1270
1271 radv_assert(pCreateInfo->mipLevels > 0);
1272 radv_assert(pCreateInfo->arrayLayers > 0);
1273 radv_assert(pCreateInfo->samples > 0);
1274 radv_assert(pCreateInfo->extent.width > 0);
1275 radv_assert(pCreateInfo->extent.height > 0);
1276 radv_assert(pCreateInfo->extent.depth > 0);
1277
1278 image = vk_zalloc2(&device->alloc, alloc, image_struct_size, 8,
1279 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1280 if (!image)
1281 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1282
1283 image->type = pCreateInfo->imageType;
1284 image->info.width = pCreateInfo->extent.width;
1285 image->info.height = pCreateInfo->extent.height;
1286 image->info.depth = pCreateInfo->extent.depth;
1287 image->info.samples = pCreateInfo->samples;
1288 image->info.storage_samples = pCreateInfo->samples;
1289 image->info.array_size = pCreateInfo->arrayLayers;
1290 image->info.levels = pCreateInfo->mipLevels;
1291 image->info.num_channels = vk_format_get_nr_components(pCreateInfo->format);
1292
1293 image->vk_format = pCreateInfo->format;
1294 image->tiling = pCreateInfo->tiling;
1295 image->usage = pCreateInfo->usage;
1296 image->flags = pCreateInfo->flags;
1297
1298 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
1299 if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
1300 for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
1301 if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL ||
1302 pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_FOREIGN_EXT)
1303 image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1304 else
1305 image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
1306 }
1307
1308 image->shareable = vk_find_struct_const(pCreateInfo->pNext,
1309 EXTERNAL_MEMORY_IMAGE_CREATE_INFO) != NULL;
1310 if (!vk_format_is_depth_or_stencil(pCreateInfo->format) &&
1311 !radv_surface_has_scanout(device, create_info) && !image->shareable) {
1312 image->info.surf_index = &device->image_mrt_offset_counter;
1313 }
1314
1315 image->plane_count = plane_count;
1316 image->size = 0;
1317 image->alignment = 1;
1318 for (unsigned plane = 0; plane < plane_count; ++plane) {
1319 struct ac_surf_info info = image->info;
1320 radv_init_surface(device, image, &image->planes[plane].surface, plane, create_info);
1321
1322 if (plane) {
1323 const struct vk_format_description *desc = vk_format_description(pCreateInfo->format);
1324 assert(info.width % desc->width_divisor == 0);
1325 assert(info.height % desc->height_divisor == 0);
1326
1327 info.width /= desc->width_divisor;
1328 info.height /= desc->height_divisor;
1329 }
1330
1331 device->ws->surface_init(device->ws, &info, &image->planes[plane].surface);
1332
1333 image->planes[plane].offset = align(image->size, image->planes[plane].surface.surf_alignment);
1334 image->size = image->planes[plane].offset + image->planes[plane].surface.surf_size;
1335 image->alignment = image->planes[plane].surface.surf_alignment;
1336
1337 image->planes[plane].format = vk_format_get_plane_format(image->vk_format, plane);
1338 }
1339
1340 if (!create_info->no_metadata_planes) {
1341 /* Try to enable DCC first. */
1342 if (radv_image_can_enable_dcc(device, image)) {
1343 radv_image_alloc_dcc(image);
1344 if (image->info.samples > 1) {
1345 /* CMASK should be enabled because DCC fast
1346 * clear with MSAA needs it.
1347 */
1348 assert(radv_image_can_enable_cmask(image));
1349 radv_image_alloc_cmask(device, image);
1350 }
1351 } else {
1352 /* When DCC cannot be enabled, try CMASK. */
1353 radv_image_disable_dcc(image);
1354 if (radv_image_can_enable_cmask(image)) {
1355 radv_image_alloc_cmask(device, image);
1356 }
1357 }
1358
1359 /* Try to enable FMASK for multisampled images. */
1360 if (radv_image_can_enable_fmask(image)) {
1361 radv_image_alloc_fmask(device, image);
1362
1363 if (radv_use_tc_compat_cmask_for_image(device, image))
1364 image->tc_compatible_cmask = true;
1365 } else {
1366 /* Otherwise, try to enable HTILE for depth surfaces. */
1367 if (radv_image_can_enable_htile(image) &&
1368 !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
1369 image->tc_compatible_htile = image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1370 radv_image_alloc_htile(device, image);
1371 } else {
1372 radv_image_disable_htile(image);
1373 }
1374 }
1375 } else {
1376 radv_image_disable_dcc(image);
1377 radv_image_disable_htile(image);
1378 }
1379
1380 if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
1381 image->alignment = MAX2(image->alignment, 4096);
1382 image->size = align64(image->size, image->alignment);
1383 image->offset = 0;
1384
1385 image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
1386 0, RADEON_FLAG_VIRTUAL, RADV_BO_PRIORITY_VIRTUAL);
1387 if (!image->bo) {
1388 vk_free2(&device->alloc, alloc, image);
1389 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
1390 }
1391 }
1392
1393 *pImage = radv_image_to_handle(image);
1394
1395 return VK_SUCCESS;
1396 }
1397
1398 static void
1399 radv_image_view_make_descriptor(struct radv_image_view *iview,
1400 struct radv_device *device,
1401 VkFormat vk_format,
1402 const VkComponentMapping *components,
1403 bool is_storage_image, unsigned plane_id,
1404 unsigned descriptor_plane_id)
1405 {
1406 struct radv_image *image = iview->image;
1407 struct radv_image_plane *plane = &image->planes[plane_id];
1408 const struct vk_format_description *format_desc = vk_format_description(image->vk_format);
1409 bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
1410 uint32_t blk_w;
1411 union radv_descriptor *descriptor;
1412 uint32_t hw_level = 0;
1413
1414 if (is_storage_image) {
1415 descriptor = &iview->storage_descriptor;
1416 } else {
1417 descriptor = &iview->descriptor;
1418 }
1419
1420 assert(vk_format_get_plane_count(vk_format) == 1);
1421 assert(plane->surface.blk_w % vk_format_get_blockwidth(plane->format) == 0);
1422 blk_w = plane->surface.blk_w / vk_format_get_blockwidth(plane->format) * vk_format_get_blockwidth(vk_format);
1423
1424 if (device->physical_device->rad_info.chip_class >= GFX9)
1425 hw_level = iview->base_mip;
1426 radv_make_texture_descriptor(device, image, is_storage_image,
1427 iview->type,
1428 vk_format,
1429 components,
1430 hw_level, hw_level + iview->level_count - 1,
1431 iview->base_layer,
1432 iview->base_layer + iview->layer_count - 1,
1433 iview->extent.width / (plane_id ? format_desc->width_divisor : 1),
1434 iview->extent.height / (plane_id ? format_desc->height_divisor : 1),
1435 iview->extent.depth,
1436 descriptor->plane_descriptors[descriptor_plane_id],
1437 descriptor_plane_id ? NULL : descriptor->fmask_descriptor);
1438
1439 const struct legacy_surf_level *base_level_info = NULL;
1440 if (device->physical_device->rad_info.chip_class <= GFX9) {
1441 if (is_stencil)
1442 base_level_info = &plane->surface.u.legacy.stencil_level[iview->base_mip];
1443 else
1444 base_level_info = &plane->surface.u.legacy.level[iview->base_mip];
1445 }
1446 si_set_mutable_tex_desc_fields(device, image,
1447 base_level_info,
1448 plane_id,
1449 iview->base_mip,
1450 iview->base_mip,
1451 blk_w, is_stencil, is_storage_image, descriptor->plane_descriptors[descriptor_plane_id]);
1452 }
1453
1454 static unsigned
1455 radv_plane_from_aspect(VkImageAspectFlags mask)
1456 {
1457 switch(mask) {
1458 case VK_IMAGE_ASPECT_PLANE_1_BIT:
1459 return 1;
1460 case VK_IMAGE_ASPECT_PLANE_2_BIT:
1461 return 2;
1462 default:
1463 return 0;
1464 }
1465 }
1466
1467 VkFormat
1468 radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask)
1469 {
1470 switch(mask) {
1471 case VK_IMAGE_ASPECT_PLANE_0_BIT:
1472 return image->planes[0].format;
1473 case VK_IMAGE_ASPECT_PLANE_1_BIT:
1474 return image->planes[1].format;
1475 case VK_IMAGE_ASPECT_PLANE_2_BIT:
1476 return image->planes[2].format;
1477 case VK_IMAGE_ASPECT_STENCIL_BIT:
1478 return vk_format_stencil_only(image->vk_format);
1479 case VK_IMAGE_ASPECT_DEPTH_BIT:
1480 return vk_format_depth_only(image->vk_format);
1481 case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
1482 return vk_format_depth_only(image->vk_format);
1483 default:
1484 return image->vk_format;
1485 }
1486 }
1487
1488 void
1489 radv_image_view_init(struct radv_image_view *iview,
1490 struct radv_device *device,
1491 const VkImageViewCreateInfo* pCreateInfo)
1492 {
1493 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
1494 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
1495
1496 switch (image->type) {
1497 case VK_IMAGE_TYPE_1D:
1498 case VK_IMAGE_TYPE_2D:
1499 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size);
1500 break;
1501 case VK_IMAGE_TYPE_3D:
1502 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
1503 <= radv_minify(image->info.depth, range->baseMipLevel));
1504 break;
1505 default:
1506 unreachable("bad VkImageType");
1507 }
1508 iview->image = image;
1509 iview->bo = image->bo;
1510 iview->type = pCreateInfo->viewType;
1511 iview->plane_id = radv_plane_from_aspect(pCreateInfo->subresourceRange.aspectMask);
1512 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
1513 iview->multiple_planes = vk_format_get_plane_count(image->vk_format) > 1 && iview->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT;
1514 iview->vk_format = pCreateInfo->format;
1515
1516 if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
1517 iview->vk_format = vk_format_stencil_only(iview->vk_format);
1518 } else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
1519 iview->vk_format = vk_format_depth_only(iview->vk_format);
1520 }
1521
1522 if (device->physical_device->rad_info.chip_class >= GFX9) {
1523 iview->extent = (VkExtent3D) {
1524 .width = image->info.width,
1525 .height = image->info.height,
1526 .depth = image->info.depth,
1527 };
1528 } else {
1529 iview->extent = (VkExtent3D) {
1530 .width = radv_minify(image->info.width , range->baseMipLevel),
1531 .height = radv_minify(image->info.height, range->baseMipLevel),
1532 .depth = radv_minify(image->info.depth , range->baseMipLevel),
1533 };
1534 }
1535
1536 if (iview->vk_format != image->planes[iview->plane_id].format) {
1537 unsigned view_bw = vk_format_get_blockwidth(iview->vk_format);
1538 unsigned view_bh = vk_format_get_blockheight(iview->vk_format);
1539 unsigned img_bw = vk_format_get_blockwidth(image->vk_format);
1540 unsigned img_bh = vk_format_get_blockheight(image->vk_format);
1541
1542 iview->extent.width = round_up_u32(iview->extent.width * view_bw, img_bw);
1543 iview->extent.height = round_up_u32(iview->extent.height * view_bh, img_bh);
1544
1545 /* Comment ported from amdvlk -
1546 * If we have the following image:
1547 * Uncompressed pixels Compressed block sizes (4x4)
1548 * mip0: 22 x 22 6 x 6
1549 * mip1: 11 x 11 3 x 3
1550 * mip2: 5 x 5 2 x 2
1551 * mip3: 2 x 2 1 x 1
1552 * mip4: 1 x 1 1 x 1
1553 *
1554 * On GFX9 the descriptor is always programmed with the WIDTH and HEIGHT of the base level and the HW is
1555 * calculating the degradation of the block sizes down the mip-chain as follows (straight-up
1556 * divide-by-two integer math):
1557 * mip0: 6x6
1558 * mip1: 3x3
1559 * mip2: 1x1
1560 * mip3: 1x1
1561 *
1562 * This means that mip2 will be missing texels.
1563 *
1564 * Fix this by calculating the base mip's width and height, then convert that, and round it
1565 * back up to get the level 0 size.
1566 * Clamp the converted size between the original values, and next power of two, which
1567 * means we don't oversize the image.
1568 */
1569 if (device->physical_device->rad_info.chip_class >= GFX9 &&
1570 vk_format_is_compressed(image->vk_format) &&
1571 !vk_format_is_compressed(iview->vk_format)) {
1572 unsigned lvl_width = radv_minify(image->info.width , range->baseMipLevel);
1573 unsigned lvl_height = radv_minify(image->info.height, range->baseMipLevel);
1574
1575 lvl_width = round_up_u32(lvl_width * view_bw, img_bw);
1576 lvl_height = round_up_u32(lvl_height * view_bh, img_bh);
1577
1578 lvl_width <<= range->baseMipLevel;
1579 lvl_height <<= range->baseMipLevel;
1580
1581 iview->extent.width = CLAMP(lvl_width, iview->extent.width, iview->image->planes[0].surface.u.gfx9.surf_pitch);
1582 iview->extent.height = CLAMP(lvl_height, iview->extent.height, iview->image->planes[0].surface.u.gfx9.surf_height);
1583 }
1584 }
1585
1586 iview->base_layer = range->baseArrayLayer;
1587 iview->layer_count = radv_get_layerCount(image, range);
1588 iview->base_mip = range->baseMipLevel;
1589 iview->level_count = radv_get_levelCount(image, range);
1590
1591 for (unsigned i = 0; i < (iview->multiple_planes ? vk_format_get_plane_count(image->vk_format) : 1); ++i) {
1592 VkFormat format = vk_format_get_plane_format(iview->vk_format, i);
1593 radv_image_view_make_descriptor(iview, device, format, &pCreateInfo->components, false, iview->plane_id + i, i);
1594 radv_image_view_make_descriptor(iview, device, format, &pCreateInfo->components, true, iview->plane_id + i, i);
1595 }
1596 }
1597
1598 bool radv_layout_has_htile(const struct radv_image *image,
1599 VkImageLayout layout,
1600 bool in_render_loop,
1601 unsigned queue_mask)
1602 {
1603 if (radv_image_is_tc_compat_htile(image))
1604 return !in_render_loop;
1605
1606 return radv_image_has_htile(image) &&
1607 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1608 (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1609 queue_mask == (1u << RADV_QUEUE_GENERAL)));
1610 }
1611
1612 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1613 VkImageLayout layout,
1614 bool in_render_loop,
1615 unsigned queue_mask)
1616 {
1617 if (radv_image_is_tc_compat_htile(image))
1618 return !in_render_loop;
1619
1620 return radv_image_has_htile(image) &&
1621 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1622 (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1623 queue_mask == (1u << RADV_QUEUE_GENERAL)));
1624 }
1625
1626 bool radv_layout_can_fast_clear(const struct radv_image *image,
1627 VkImageLayout layout,
1628 bool in_render_loop,
1629 unsigned queue_mask)
1630 {
1631 return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
1632 }
1633
1634 bool radv_layout_dcc_compressed(const struct radv_image *image,
1635 VkImageLayout layout,
1636 bool in_render_loop,
1637 unsigned queue_mask)
1638 {
1639 /* Don't compress compute transfer dst, as image stores are not supported. */
1640 if (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1641 (queue_mask & (1u << RADV_QUEUE_COMPUTE)))
1642 return false;
1643
1644 return radv_image_has_dcc(image) &&!in_render_loop;
1645 }
1646
1647
1648 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
1649 {
1650 if (!image->exclusive)
1651 return image->queue_family_mask;
1652 if (family == VK_QUEUE_FAMILY_EXTERNAL ||
1653 family == VK_QUEUE_FAMILY_FOREIGN_EXT)
1654 return (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1655 if (family == VK_QUEUE_FAMILY_IGNORED)
1656 return 1u << queue_family;
1657 return 1u << family;
1658 }
1659
1660 VkResult
1661 radv_CreateImage(VkDevice device,
1662 const VkImageCreateInfo *pCreateInfo,
1663 const VkAllocationCallbacks *pAllocator,
1664 VkImage *pImage)
1665 {
1666 #ifdef ANDROID
1667 const VkNativeBufferANDROID *gralloc_info =
1668 vk_find_struct_const(pCreateInfo->pNext, NATIVE_BUFFER_ANDROID);
1669
1670 if (gralloc_info)
1671 return radv_image_from_gralloc(device, pCreateInfo, gralloc_info,
1672 pAllocator, pImage);
1673 #endif
1674
1675 const struct wsi_image_create_info *wsi_info =
1676 vk_find_struct_const(pCreateInfo->pNext, WSI_IMAGE_CREATE_INFO_MESA);
1677 bool scanout = wsi_info && wsi_info->scanout;
1678
1679 return radv_image_create(device,
1680 &(struct radv_image_create_info) {
1681 .vk_info = pCreateInfo,
1682 .scanout = scanout,
1683 },
1684 pAllocator,
1685 pImage);
1686 }
1687
1688 void
1689 radv_DestroyImage(VkDevice _device, VkImage _image,
1690 const VkAllocationCallbacks *pAllocator)
1691 {
1692 RADV_FROM_HANDLE(radv_device, device, _device);
1693 RADV_FROM_HANDLE(radv_image, image, _image);
1694
1695 if (!image)
1696 return;
1697
1698 if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
1699 device->ws->buffer_destroy(image->bo);
1700
1701 if (image->owned_memory != VK_NULL_HANDLE)
1702 radv_FreeMemory(_device, image->owned_memory, pAllocator);
1703
1704 vk_free2(&device->alloc, pAllocator, image);
1705 }
1706
1707 void radv_GetImageSubresourceLayout(
1708 VkDevice _device,
1709 VkImage _image,
1710 const VkImageSubresource* pSubresource,
1711 VkSubresourceLayout* pLayout)
1712 {
1713 RADV_FROM_HANDLE(radv_image, image, _image);
1714 RADV_FROM_HANDLE(radv_device, device, _device);
1715 int level = pSubresource->mipLevel;
1716 int layer = pSubresource->arrayLayer;
1717
1718 unsigned plane_id = radv_plane_from_aspect(pSubresource->aspectMask);
1719
1720 struct radv_image_plane *plane = &image->planes[plane_id];
1721 struct radeon_surf *surface = &plane->surface;
1722
1723 if (device->physical_device->rad_info.chip_class >= GFX9) {
1724 pLayout->offset = plane->offset + surface->u.gfx9.offset[level] + surface->u.gfx9.surf_slice_size * layer;
1725 if (image->vk_format == VK_FORMAT_R32G32B32_UINT ||
1726 image->vk_format == VK_FORMAT_R32G32B32_SINT ||
1727 image->vk_format == VK_FORMAT_R32G32B32_SFLOAT) {
1728 /* Adjust the number of bytes between each row because
1729 * the pitch is actually the number of components per
1730 * row.
1731 */
1732 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe / 3;
1733 } else {
1734 assert(util_is_power_of_two_nonzero(surface->bpe));
1735 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe;
1736 }
1737
1738 pLayout->arrayPitch = surface->u.gfx9.surf_slice_size;
1739 pLayout->depthPitch = surface->u.gfx9.surf_slice_size;
1740 pLayout->size = surface->u.gfx9.surf_slice_size;
1741 if (image->type == VK_IMAGE_TYPE_3D)
1742 pLayout->size *= u_minify(image->info.depth, level);
1743 } else {
1744 pLayout->offset = plane->offset + surface->u.legacy.level[level].offset + (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4 * layer;
1745 pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
1746 pLayout->arrayPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1747 pLayout->depthPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1748 pLayout->size = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1749 if (image->type == VK_IMAGE_TYPE_3D)
1750 pLayout->size *= u_minify(image->info.depth, level);
1751 }
1752 }
1753
1754
1755 VkResult
1756 radv_CreateImageView(VkDevice _device,
1757 const VkImageViewCreateInfo *pCreateInfo,
1758 const VkAllocationCallbacks *pAllocator,
1759 VkImageView *pView)
1760 {
1761 RADV_FROM_HANDLE(radv_device, device, _device);
1762 struct radv_image_view *view;
1763
1764 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1765 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1766 if (view == NULL)
1767 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1768
1769 radv_image_view_init(view, device, pCreateInfo);
1770
1771 *pView = radv_image_view_to_handle(view);
1772
1773 return VK_SUCCESS;
1774 }
1775
1776 void
1777 radv_DestroyImageView(VkDevice _device, VkImageView _iview,
1778 const VkAllocationCallbacks *pAllocator)
1779 {
1780 RADV_FROM_HANDLE(radv_device, device, _device);
1781 RADV_FROM_HANDLE(radv_image_view, iview, _iview);
1782
1783 if (!iview)
1784 return;
1785 vk_free2(&device->alloc, pAllocator, iview);
1786 }
1787
1788 void radv_buffer_view_init(struct radv_buffer_view *view,
1789 struct radv_device *device,
1790 const VkBufferViewCreateInfo* pCreateInfo)
1791 {
1792 RADV_FROM_HANDLE(radv_buffer, buffer, pCreateInfo->buffer);
1793
1794 view->bo = buffer->bo;
1795 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
1796 buffer->size - pCreateInfo->offset : pCreateInfo->range;
1797 view->vk_format = pCreateInfo->format;
1798
1799 radv_make_buffer_descriptor(device, buffer, view->vk_format,
1800 pCreateInfo->offset, view->range, view->state);
1801 }
1802
1803 VkResult
1804 radv_CreateBufferView(VkDevice _device,
1805 const VkBufferViewCreateInfo *pCreateInfo,
1806 const VkAllocationCallbacks *pAllocator,
1807 VkBufferView *pView)
1808 {
1809 RADV_FROM_HANDLE(radv_device, device, _device);
1810 struct radv_buffer_view *view;
1811
1812 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1813 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1814 if (!view)
1815 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1816
1817 radv_buffer_view_init(view, device, pCreateInfo);
1818
1819 *pView = radv_buffer_view_to_handle(view);
1820
1821 return VK_SUCCESS;
1822 }
1823
1824 void
1825 radv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
1826 const VkAllocationCallbacks *pAllocator)
1827 {
1828 RADV_FROM_HANDLE(radv_device, device, _device);
1829 RADV_FROM_HANDLE(radv_buffer_view, view, bufferView);
1830
1831 if (!view)
1832 return;
1833
1834 vk_free2(&device->alloc, pAllocator, view);
1835 }