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radv/gfx10: implement si_set_mutable_tex_desc_fields()
[mesa.git] / src / amd / vulkan / radv_image.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "vk_format.h"
31 #include "vk_util.h"
32 #include "radv_radeon_winsys.h"
33 #include "sid.h"
34 #include "util/debug.h"
35 #include "util/u_atomic.h"
36
37 static unsigned
38 radv_choose_tiling(struct radv_device *device,
39 const struct radv_image_create_info *create_info)
40 {
41 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
42
43 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) {
44 assert(pCreateInfo->samples <= 1);
45 return RADEON_SURF_MODE_LINEAR_ALIGNED;
46 }
47
48 if (!vk_format_is_compressed(pCreateInfo->format) &&
49 !vk_format_is_depth_or_stencil(pCreateInfo->format)
50 && device->physical_device->rad_info.chip_class <= GFX8) {
51 /* this causes hangs in some VK CTS tests on GFX9. */
52 /* Textures with a very small height are recommended to be linear. */
53 if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
54 /* Only very thin and long 2D textures should benefit from
55 * linear_aligned. */
56 (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
57 return RADEON_SURF_MODE_LINEAR_ALIGNED;
58 }
59
60 /* MSAA resources must be 2D tiled. */
61 if (pCreateInfo->samples > 1)
62 return RADEON_SURF_MODE_2D;
63
64 return RADEON_SURF_MODE_2D;
65 }
66
67 static bool
68 radv_use_tc_compat_htile_for_image(struct radv_device *device,
69 const VkImageCreateInfo *pCreateInfo)
70 {
71 /* TC-compat HTILE is only available for GFX8+. */
72 if (device->physical_device->rad_info.chip_class < GFX8)
73 return false;
74
75 if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
76 (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
77 return false;
78
79 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
80 return false;
81
82 if (pCreateInfo->mipLevels > 1)
83 return false;
84
85 /* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
86 * tests - disable for now */
87 if (pCreateInfo->samples >= 2 &&
88 pCreateInfo->format == VK_FORMAT_D32_SFLOAT_S8_UINT)
89 return false;
90
91 /* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only
92 * supports 32-bit. Though, it's possible to enable TC-compat for
93 * 16-bit depth surfaces if no Z planes are compressed.
94 */
95 if (pCreateInfo->format != VK_FORMAT_D32_SFLOAT_S8_UINT &&
96 pCreateInfo->format != VK_FORMAT_D32_SFLOAT &&
97 pCreateInfo->format != VK_FORMAT_D16_UNORM)
98 return false;
99
100 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
101 const struct VkImageFormatListCreateInfoKHR *format_list =
102 (const struct VkImageFormatListCreateInfoKHR *)
103 vk_find_struct_const(pCreateInfo->pNext,
104 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
105
106 /* We have to ignore the existence of the list if viewFormatCount = 0 */
107 if (format_list && format_list->viewFormatCount) {
108 /* compatibility is transitive, so we only need to check
109 * one format with everything else.
110 */
111 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
112 if (format_list->pViewFormats[i] == VK_FORMAT_UNDEFINED)
113 continue;
114
115 if (pCreateInfo->format != format_list->pViewFormats[i])
116 return false;
117 }
118 } else {
119 return false;
120 }
121 }
122
123 return true;
124 }
125
126 static bool
127 radv_surface_has_scanout(struct radv_device *device, const struct radv_image_create_info *info)
128 {
129 if (info->scanout)
130 return true;
131
132 if (!info->bo_metadata)
133 return false;
134
135 if (device->physical_device->rad_info.chip_class >= GFX9) {
136 return info->bo_metadata->u.gfx9.swizzle_mode == 0 || info->bo_metadata->u.gfx9.swizzle_mode % 4 == 2;
137 } else {
138 return info->bo_metadata->u.legacy.scanout;
139 }
140 }
141
142 static bool
143 radv_use_dcc_for_image(struct radv_device *device,
144 const struct radv_image *image,
145 const struct radv_image_create_info *create_info,
146 const VkImageCreateInfo *pCreateInfo)
147 {
148 bool dcc_compatible_formats;
149 bool blendable;
150
151 /* DCC (Delta Color Compression) is only available for GFX8+. */
152 if (device->physical_device->rad_info.chip_class < GFX8)
153 return false;
154
155 if (device->instance->debug_flags & RADV_DEBUG_NO_DCC)
156 return false;
157
158 if (image->shareable)
159 return false;
160
161 /* TODO: Enable DCC for storage images. */
162 if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
163 (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
164 return false;
165
166 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
167 return false;
168
169 if (vk_format_is_subsampled(pCreateInfo->format) ||
170 vk_format_get_plane_count(pCreateInfo->format) > 1)
171 return false;
172
173 /* TODO: Enable DCC for mipmaps on GFX9+. */
174 if ((pCreateInfo->arrayLayers > 1 || pCreateInfo->mipLevels > 1) &&
175 device->physical_device->rad_info.chip_class >= GFX9)
176 return false;
177
178 /* Do not enable DCC for mipmapped arrays because performance is worse. */
179 if (pCreateInfo->arrayLayers > 1 && pCreateInfo->mipLevels > 1)
180 return false;
181
182 if (radv_surface_has_scanout(device, create_info))
183 return false;
184
185 /* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet, while
186 * 2x can be enabled with an option.
187 */
188 if (pCreateInfo->samples > 2 ||
189 (pCreateInfo->samples == 2 &&
190 !device->physical_device->dcc_msaa_allowed))
191 return false;
192
193 /* Determine if the formats are DCC compatible. */
194 dcc_compatible_formats =
195 radv_is_colorbuffer_format_supported(pCreateInfo->format,
196 &blendable);
197
198 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
199 const struct VkImageFormatListCreateInfoKHR *format_list =
200 (const struct VkImageFormatListCreateInfoKHR *)
201 vk_find_struct_const(pCreateInfo->pNext,
202 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
203
204 /* We have to ignore the existence of the list if viewFormatCount = 0 */
205 if (format_list && format_list->viewFormatCount) {
206 /* compatibility is transitive, so we only need to check
207 * one format with everything else. */
208 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
209 if (format_list->pViewFormats[i] == VK_FORMAT_UNDEFINED)
210 continue;
211
212 if (!radv_dcc_formats_compatible(pCreateInfo->format,
213 format_list->pViewFormats[i]))
214 dcc_compatible_formats = false;
215 }
216 } else {
217 dcc_compatible_formats = false;
218 }
219 }
220
221 if (!dcc_compatible_formats)
222 return false;
223
224 return true;
225 }
226
227 static bool
228 radv_use_tc_compat_cmask_for_image(struct radv_device *device,
229 struct radv_image *image)
230 {
231 if (!(device->instance->perftest_flags & RADV_PERFTEST_TC_COMPAT_CMASK))
232 return false;
233
234 /* TC-compat CMASK is only available for GFX8+. */
235 if (device->physical_device->rad_info.chip_class < GFX8)
236 return false;
237
238 if (image->usage & VK_IMAGE_USAGE_STORAGE_BIT)
239 return false;
240
241 if (radv_image_has_dcc(image))
242 return false;
243
244 if (!radv_image_has_cmask(image))
245 return false;
246
247 return true;
248 }
249
250 static void
251 radv_prefill_surface_from_metadata(struct radv_device *device,
252 struct radeon_surf *surface,
253 const struct radv_image_create_info *create_info)
254 {
255 const struct radeon_bo_metadata *md = create_info->bo_metadata;
256 if (device->physical_device->rad_info.chip_class >= GFX9) {
257 if (md->u.gfx9.swizzle_mode > 0)
258 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
259 else
260 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
261
262 surface->u.gfx9.surf.swizzle_mode = md->u.gfx9.swizzle_mode;
263 } else {
264 surface->u.legacy.pipe_config = md->u.legacy.pipe_config;
265 surface->u.legacy.bankw = md->u.legacy.bankw;
266 surface->u.legacy.bankh = md->u.legacy.bankh;
267 surface->u.legacy.tile_split = md->u.legacy.tile_split;
268 surface->u.legacy.mtilea = md->u.legacy.mtilea;
269 surface->u.legacy.num_banks = md->u.legacy.num_banks;
270
271 if (md->u.legacy.macrotile == RADEON_LAYOUT_TILED)
272 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
273 else if (md->u.legacy.microtile == RADEON_LAYOUT_TILED)
274 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
275 else
276 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
277
278 }
279 }
280
281 static int
282 radv_init_surface(struct radv_device *device,
283 const struct radv_image *image,
284 struct radeon_surf *surface,
285 unsigned plane_id,
286 const struct radv_image_create_info *create_info)
287 {
288 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
289 unsigned array_mode = radv_choose_tiling(device, create_info);
290 VkFormat format = vk_format_get_plane_format(pCreateInfo->format, plane_id);
291 const struct vk_format_description *desc = vk_format_description(format);
292 bool is_depth, is_stencil;
293
294 is_depth = vk_format_has_depth(desc);
295 is_stencil = vk_format_has_stencil(desc);
296
297 surface->blk_w = vk_format_get_blockwidth(format);
298 surface->blk_h = vk_format_get_blockheight(format);
299
300 surface->bpe = vk_format_get_blocksize(vk_format_depth_only(format));
301 /* align byte per element on dword */
302 if (surface->bpe == 3) {
303 surface->bpe = 4;
304 }
305 if (create_info->bo_metadata) {
306 radv_prefill_surface_from_metadata(device, surface, create_info);
307 } else {
308 surface->flags = RADEON_SURF_SET(array_mode, MODE);
309 }
310
311 switch (pCreateInfo->imageType){
312 case VK_IMAGE_TYPE_1D:
313 if (pCreateInfo->arrayLayers > 1)
314 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
315 else
316 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
317 break;
318 case VK_IMAGE_TYPE_2D:
319 if (pCreateInfo->arrayLayers > 1)
320 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
321 else
322 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
323 break;
324 case VK_IMAGE_TYPE_3D:
325 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
326 break;
327 default:
328 unreachable("unhandled image type");
329 }
330
331 if (is_depth) {
332 surface->flags |= RADEON_SURF_ZBUFFER;
333 if (radv_use_tc_compat_htile_for_image(device, pCreateInfo))
334 surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
335 }
336
337 if (is_stencil)
338 surface->flags |= RADEON_SURF_SBUFFER;
339
340 if (device->physical_device->rad_info.chip_class >= GFX9 &&
341 pCreateInfo->imageType == VK_IMAGE_TYPE_3D &&
342 vk_format_get_blocksizebits(pCreateInfo->format) == 128 &&
343 vk_format_is_compressed(pCreateInfo->format))
344 surface->flags |= RADEON_SURF_NO_RENDER_TARGET;
345
346 surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
347
348 if (!radv_use_dcc_for_image(device, image, create_info, pCreateInfo))
349 surface->flags |= RADEON_SURF_DISABLE_DCC;
350
351 if (radv_surface_has_scanout(device, create_info))
352 surface->flags |= RADEON_SURF_SCANOUT;
353
354 return 0;
355 }
356
357 static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
358 {
359 return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
360 }
361
362 static inline unsigned
363 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
364 {
365 if (stencil)
366 return plane->surface.u.legacy.stencil_tiling_index[level];
367 else
368 return plane->surface.u.legacy.tiling_index[level];
369 }
370
371 static unsigned radv_map_swizzle(unsigned swizzle)
372 {
373 switch (swizzle) {
374 case VK_SWIZZLE_Y:
375 return V_008F0C_SQ_SEL_Y;
376 case VK_SWIZZLE_Z:
377 return V_008F0C_SQ_SEL_Z;
378 case VK_SWIZZLE_W:
379 return V_008F0C_SQ_SEL_W;
380 case VK_SWIZZLE_0:
381 return V_008F0C_SQ_SEL_0;
382 case VK_SWIZZLE_1:
383 return V_008F0C_SQ_SEL_1;
384 default: /* VK_SWIZZLE_X */
385 return V_008F0C_SQ_SEL_X;
386 }
387 }
388
389 static void
390 radv_make_buffer_descriptor(struct radv_device *device,
391 struct radv_buffer *buffer,
392 VkFormat vk_format,
393 unsigned offset,
394 unsigned range,
395 uint32_t *state)
396 {
397 const struct vk_format_description *desc;
398 unsigned stride;
399 uint64_t gpu_address = radv_buffer_get_va(buffer->bo);
400 uint64_t va = gpu_address + buffer->offset;
401 unsigned num_format, data_format;
402 int first_non_void;
403 desc = vk_format_description(vk_format);
404 first_non_void = vk_format_get_first_non_void_channel(vk_format);
405 stride = desc->block.bits / 8;
406
407 num_format = radv_translate_buffer_numformat(desc, first_non_void);
408 data_format = radv_translate_buffer_dataformat(desc, first_non_void);
409
410 assert(data_format != V_008F0C_BUF_DATA_FORMAT_INVALID);
411 assert(num_format != ~0);
412
413 va += offset;
414 state[0] = va;
415 state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
416 S_008F04_STRIDE(stride);
417
418 if (device->physical_device->rad_info.chip_class != GFX8 && stride) {
419 range /= stride;
420 }
421
422 state[2] = range;
423 state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
424 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
425 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
426 S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3])) |
427 S_008F0C_NUM_FORMAT(num_format) |
428 S_008F0C_DATA_FORMAT(data_format);
429 }
430
431 static void
432 si_set_mutable_tex_desc_fields(struct radv_device *device,
433 struct radv_image *image,
434 const struct legacy_surf_level *base_level_info,
435 unsigned plane_id,
436 unsigned base_level, unsigned first_level,
437 unsigned block_width, bool is_stencil,
438 bool is_storage_image, uint32_t *state)
439 {
440 struct radv_image_plane *plane = &image->planes[plane_id];
441 uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0;
442 uint64_t va = gpu_address + plane->offset;
443 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
444 uint64_t meta_va = 0;
445 if (chip_class >= GFX9) {
446 if (is_stencil)
447 va += plane->surface.u.gfx9.stencil_offset;
448 else
449 va += plane->surface.u.gfx9.surf_offset;
450 } else
451 va += base_level_info->offset;
452
453 state[0] = va >> 8;
454 if (chip_class >= GFX9 ||
455 base_level_info->mode == RADEON_SURF_MODE_2D)
456 state[0] |= plane->surface.tile_swizzle;
457 state[1] &= C_008F14_BASE_ADDRESS_HI;
458 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
459
460 if (chip_class >= GFX8) {
461 state[6] &= C_008F28_COMPRESSION_EN;
462 state[7] = 0;
463 if (!is_storage_image && radv_dcc_enabled(image, first_level)) {
464 meta_va = gpu_address + image->dcc_offset;
465 if (chip_class <= GFX8)
466 meta_va += base_level_info->dcc_offset;
467 } else if (!is_storage_image &&
468 radv_image_is_tc_compat_htile(image)) {
469 meta_va = gpu_address + image->htile_offset;
470 }
471
472 if (meta_va) {
473 state[6] |= S_008F28_COMPRESSION_EN(1);
474 if (chip_class <= GFX9) {
475 state[7] = meta_va >> 8;
476 state[7] |= plane->surface.tile_swizzle;
477 }
478 }
479 }
480
481 if (chip_class >= GFX10) {
482 state[3] &= C_00A00C_SW_MODE;
483
484 if (is_stencil) {
485 state[3] |= S_00A00C_SW_MODE(plane->surface.u.gfx9.stencil.swizzle_mode);
486 } else {
487 state[3] |= S_00A00C_SW_MODE(plane->surface.u.gfx9.surf.swizzle_mode);
488 }
489
490 state[6] &= C_00A018_META_DATA_ADDRESS_LO &
491 C_00A018_META_PIPE_ALIGNED;
492
493 if (meta_va) {
494 struct gfx9_surf_meta_flags meta;
495
496 if (image->dcc_offset)
497 meta = plane->surface.u.gfx9.dcc;
498 else
499 meta = plane->surface.u.gfx9.htile;
500
501 state[6] |= S_00A018_META_PIPE_ALIGNED(meta.pipe_aligned) |
502 S_00A018_META_DATA_ADDRESS_LO(meta_va >> 8);
503 }
504
505 state[7] = meta_va >> 16;
506 } else if (chip_class >= GFX9) {
507 state[3] &= C_008F1C_SW_MODE;
508 state[4] &= C_008F20_PITCH;
509
510 if (is_stencil) {
511 state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.stencil.swizzle_mode);
512 state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.stencil.epitch);
513 } else {
514 state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.surf.swizzle_mode);
515 state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.surf.epitch);
516 }
517
518 state[5] &= C_008F24_META_DATA_ADDRESS &
519 C_008F24_META_PIPE_ALIGNED &
520 C_008F24_META_RB_ALIGNED;
521 if (meta_va) {
522 struct gfx9_surf_meta_flags meta;
523
524 if (image->dcc_offset)
525 meta = plane->surface.u.gfx9.dcc;
526 else
527 meta = plane->surface.u.gfx9.htile;
528
529 state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
530 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
531 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
532 }
533 } else {
534 /* GFX6-GFX8 */
535 unsigned pitch = base_level_info->nblk_x * block_width;
536 unsigned index = si_tile_mode_index(plane, base_level, is_stencil);
537
538 state[3] &= C_008F1C_TILING_INDEX;
539 state[3] |= S_008F1C_TILING_INDEX(index);
540 state[4] &= C_008F20_PITCH;
541 state[4] |= S_008F20_PITCH(pitch - 1);
542 }
543 }
544
545 static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
546 unsigned nr_layers, unsigned nr_samples, bool is_storage_image, bool gfx9)
547 {
548 if (view_type == VK_IMAGE_VIEW_TYPE_CUBE || view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY)
549 return is_storage_image ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_CUBE;
550
551 /* GFX9 allocates 1D textures as 2D. */
552 if (gfx9 && image_type == VK_IMAGE_TYPE_1D)
553 image_type = VK_IMAGE_TYPE_2D;
554 switch (image_type) {
555 case VK_IMAGE_TYPE_1D:
556 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY : V_008F1C_SQ_RSRC_IMG_1D;
557 case VK_IMAGE_TYPE_2D:
558 if (nr_samples > 1)
559 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_MSAA;
560 else
561 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_2D;
562 case VK_IMAGE_TYPE_3D:
563 if (view_type == VK_IMAGE_VIEW_TYPE_3D)
564 return V_008F1C_SQ_RSRC_IMG_3D;
565 else
566 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
567 default:
568 unreachable("illegal image type");
569 }
570 }
571
572 static unsigned gfx9_border_color_swizzle(const enum vk_swizzle swizzle[4])
573 {
574 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
575
576 if (swizzle[3] == VK_SWIZZLE_X) {
577 /* For the pre-defined border color values (white, opaque
578 * black, transparent black), the only thing that matters is
579 * that the alpha channel winds up in the correct place
580 * (because the RGB channels are all the same) so either of
581 * these enumerations will work.
582 */
583 if (swizzle[2] == VK_SWIZZLE_Y)
584 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
585 else
586 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
587 } else if (swizzle[0] == VK_SWIZZLE_X) {
588 if (swizzle[1] == VK_SWIZZLE_Y)
589 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
590 else
591 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
592 } else if (swizzle[1] == VK_SWIZZLE_X) {
593 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
594 } else if (swizzle[2] == VK_SWIZZLE_X) {
595 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
596 }
597
598 return bc_swizzle;
599 }
600
601 /**
602 * Build the sampler view descriptor for a texture (GFX10).
603 */
604 static void
605 gfx10_make_texture_descriptor(struct radv_device *device,
606 struct radv_image *image,
607 bool is_storage_image,
608 VkImageViewType view_type,
609 VkFormat vk_format,
610 const VkComponentMapping *mapping,
611 unsigned first_level, unsigned last_level,
612 unsigned first_layer, unsigned last_layer,
613 unsigned width, unsigned height, unsigned depth,
614 uint32_t *state,
615 uint32_t *fmask_state)
616 {
617 const struct vk_format_description *desc;
618 enum vk_swizzle swizzle[4];
619 unsigned img_format;
620 unsigned type;
621
622 desc = vk_format_description(vk_format);
623 img_format = gfx10_format_table[vk_format].img_format;
624
625 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
626 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
627 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
628 } else {
629 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
630 }
631
632 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
633 is_storage_image, device->physical_device->rad_info.chip_class >= GFX9);
634 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
635 height = 1;
636 depth = image->info.array_size;
637 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
638 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
639 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
640 depth = image->info.array_size;
641 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
642 depth = image->info.array_size / 6;
643
644 state[0] = 0;
645 state[1] = S_00A004_FORMAT(img_format) |
646 S_00A004_WIDTH_LO(width - 1);
647 state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
648 S_00A008_HEIGHT(height - 1) |
649 S_00A008_RESOURCE_LEVEL(1);
650 state[3] = S_00A00C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
651 S_00A00C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
652 S_00A00C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
653 S_00A00C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
654 S_00A00C_BASE_LEVEL(image->info.samples > 1 ?
655 0 : first_level) |
656 S_00A00C_LAST_LEVEL(image->info.samples > 1 ?
657 util_logbase2(image->info.samples) :
658 last_level) |
659 S_00A00C_BC_SWIZZLE(gfx9_border_color_swizzle(swizzle)) |
660 S_00A00C_TYPE(type);
661 /* Depth is the the last accessible layer on gfx9+. The hw doesn't need
662 * to know the total number of layers.
663 */
664 state[4] = S_00A010_DEPTH(type == V_008F1C_SQ_RSRC_IMG_3D ? depth - 1 : last_layer) |
665 S_00A010_BASE_ARRAY(first_layer);
666 state[5] = S_00A014_ARRAY_PITCH(!!(type == V_008F1C_SQ_RSRC_IMG_3D)) |
667 S_00A014_MAX_MIP(image->info.samples > 1 ?
668 util_logbase2(image->info.samples) :
669 image->info.levels - 1) |
670 S_00A014_PERF_MOD(4);
671 state[6] = 0;
672 state[7] = 0;
673
674 if (radv_dcc_enabled(image, first_level)) {
675 unsigned swap = radv_translate_colorswap(vk_format, FALSE);
676
677 state[6] |= S_00A018_MAX_UNCOMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_256B) |
678 S_00A018_MAX_COMPRESSED_BLOCK_SIZE(V_028C78_MAX_BLOCK_SIZE_128B) |
679 S_00A018_ALPHA_IS_ON_MSB(swap <= 1);
680 }
681
682 /* Initialize the sampler view for FMASK. */
683 if (radv_image_has_fmask(image)) {
684 uint64_t gpu_address = radv_buffer_get_va(image->bo);
685 uint32_t format;
686 uint64_t va;
687
688 assert(image->plane_count == 1);
689
690 va = gpu_address + image->offset + image->fmask.offset;
691
692 switch (image->info.samples) {
693 case 2:
694 format = V_008F0C_IMG_FORMAT_FMASK8_S2_F2;
695 break;
696 case 4:
697 format = V_008F0C_IMG_FORMAT_FMASK8_S4_F4;
698 break;
699 case 8:
700 format = V_008F0C_IMG_FORMAT_FMASK32_S8_F8;
701 break;
702 default:
703 unreachable("invalid nr_samples");
704 }
705
706 fmask_state[0] = (va >> 8) | image->planes[0].surface.fmask_tile_swizzle;
707 fmask_state[1] = S_00A004_BASE_ADDRESS_HI(va >> 40) |
708 S_00A004_FORMAT(format) |
709 S_00A004_WIDTH_LO(width - 1);
710 fmask_state[2] = S_00A008_WIDTH_HI((width - 1) >> 2) |
711 S_00A008_HEIGHT(height - 1) |
712 S_00A008_RESOURCE_LEVEL(1);
713 fmask_state[3] = S_00A00C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
714 S_00A00C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
715 S_00A00C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
716 S_00A00C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
717 S_00A00C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode) |
718 S_00A00C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
719 fmask_state[4] = S_00A010_DEPTH(last_layer) |
720 S_00A010_BASE_ARRAY(first_layer);
721 fmask_state[5] = 0;
722 fmask_state[6] = S_00A018_META_PIPE_ALIGNED(image->planes[0].surface.u.gfx9.cmask.pipe_aligned);
723 fmask_state[7] = 0;
724 } else if (fmask_state)
725 memset(fmask_state, 0, 8 * 4);
726 }
727
728 /**
729 * Build the sampler view descriptor for a texture (SI-GFX9)
730 */
731 static void
732 si_make_texture_descriptor(struct radv_device *device,
733 struct radv_image *image,
734 bool is_storage_image,
735 VkImageViewType view_type,
736 VkFormat vk_format,
737 const VkComponentMapping *mapping,
738 unsigned first_level, unsigned last_level,
739 unsigned first_layer, unsigned last_layer,
740 unsigned width, unsigned height, unsigned depth,
741 uint32_t *state,
742 uint32_t *fmask_state)
743 {
744 const struct vk_format_description *desc;
745 enum vk_swizzle swizzle[4];
746 int first_non_void;
747 unsigned num_format, data_format, type;
748
749 desc = vk_format_description(vk_format);
750
751 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
752 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
753 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
754 } else {
755 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
756 }
757
758 first_non_void = vk_format_get_first_non_void_channel(vk_format);
759
760 num_format = radv_translate_tex_numformat(vk_format, desc, first_non_void);
761 if (num_format == ~0) {
762 num_format = 0;
763 }
764
765 data_format = radv_translate_tex_dataformat(vk_format, desc, first_non_void);
766 if (data_format == ~0) {
767 data_format = 0;
768 }
769
770 /* S8 with either Z16 or Z32 HTILE need a special format. */
771 if (device->physical_device->rad_info.chip_class >= GFX9 &&
772 vk_format == VK_FORMAT_S8_UINT &&
773 radv_image_is_tc_compat_htile(image)) {
774 if (image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT)
775 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
776 else if (image->vk_format == VK_FORMAT_D16_UNORM_S8_UINT)
777 data_format = V_008F14_IMG_DATA_FORMAT_S8_16;
778 }
779 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
780 is_storage_image, device->physical_device->rad_info.chip_class >= GFX9);
781 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
782 height = 1;
783 depth = image->info.array_size;
784 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
785 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
786 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
787 depth = image->info.array_size;
788 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
789 depth = image->info.array_size / 6;
790
791 state[0] = 0;
792 state[1] = (S_008F14_DATA_FORMAT(data_format) |
793 S_008F14_NUM_FORMAT(num_format));
794 state[2] = (S_008F18_WIDTH(width - 1) |
795 S_008F18_HEIGHT(height - 1) |
796 S_008F18_PERF_MOD(4));
797 state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
798 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
799 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
800 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
801 S_008F1C_BASE_LEVEL(image->info.samples > 1 ?
802 0 : first_level) |
803 S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
804 util_logbase2(image->info.samples) :
805 last_level) |
806 S_008F1C_TYPE(type));
807 state[4] = 0;
808 state[5] = S_008F24_BASE_ARRAY(first_layer);
809 state[6] = 0;
810 state[7] = 0;
811
812 if (device->physical_device->rad_info.chip_class >= GFX9) {
813 unsigned bc_swizzle = gfx9_border_color_swizzle(swizzle);
814
815 /* Depth is the last accessible layer on Gfx9.
816 * The hw doesn't need to know the total number of layers.
817 */
818 if (type == V_008F1C_SQ_RSRC_IMG_3D)
819 state[4] |= S_008F20_DEPTH(depth - 1);
820 else
821 state[4] |= S_008F20_DEPTH(last_layer);
822
823 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
824 state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ?
825 util_logbase2(image->info.samples) :
826 image->info.levels - 1);
827 } else {
828 state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
829 state[4] |= S_008F20_DEPTH(depth - 1);
830 state[5] |= S_008F24_LAST_ARRAY(last_layer);
831 }
832 if (image->dcc_offset) {
833 unsigned swap = radv_translate_colorswap(vk_format, FALSE);
834
835 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
836 } else {
837 /* The last dword is unused by hw. The shader uses it to clear
838 * bits in the first dword of sampler state.
839 */
840 if (device->physical_device->rad_info.chip_class <= GFX7 && image->info.samples <= 1) {
841 if (first_level == last_level)
842 state[7] = C_008F30_MAX_ANISO_RATIO;
843 else
844 state[7] = 0xffffffff;
845 }
846 }
847
848 /* Initialize the sampler view for FMASK. */
849 if (radv_image_has_fmask(image)) {
850 uint32_t fmask_format, num_format;
851 uint64_t gpu_address = radv_buffer_get_va(image->bo);
852 uint64_t va;
853
854 assert(image->plane_count == 1);
855
856 va = gpu_address + image->offset + image->fmask.offset;
857
858 if (device->physical_device->rad_info.chip_class >= GFX9) {
859 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
860 switch (image->info.samples) {
861 case 2:
862 num_format = V_008F14_IMG_FMASK_8_2_2;
863 break;
864 case 4:
865 num_format = V_008F14_IMG_FMASK_8_4_4;
866 break;
867 case 8:
868 num_format = V_008F14_IMG_FMASK_32_8_8;
869 break;
870 default:
871 unreachable("invalid nr_samples");
872 }
873 } else {
874 switch (image->info.samples) {
875 case 2:
876 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
877 break;
878 case 4:
879 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
880 break;
881 case 8:
882 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
883 break;
884 default:
885 assert(0);
886 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
887 }
888 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
889 }
890
891 fmask_state[0] = va >> 8;
892 fmask_state[0] |= image->fmask.tile_swizzle;
893 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
894 S_008F14_DATA_FORMAT(fmask_format) |
895 S_008F14_NUM_FORMAT(num_format);
896 fmask_state[2] = S_008F18_WIDTH(width - 1) |
897 S_008F18_HEIGHT(height - 1);
898 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
899 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
900 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
901 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
902 S_008F1C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
903 fmask_state[4] = 0;
904 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
905 fmask_state[6] = 0;
906 fmask_state[7] = 0;
907
908 if (device->physical_device->rad_info.chip_class >= GFX9) {
909 fmask_state[3] |= S_008F1C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode);
910 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
911 S_008F20_PITCH(image->planes[0].surface.u.gfx9.fmask.epitch);
912 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->planes[0].surface.u.gfx9.cmask.pipe_aligned) |
913 S_008F24_META_RB_ALIGNED(image->planes[0].surface.u.gfx9.cmask.rb_aligned);
914
915 if (radv_image_is_tc_compat_cmask(image)) {
916 va = gpu_address + image->offset + image->cmask.offset;
917
918 fmask_state[5] |= S_008F24_META_DATA_ADDRESS(va >> 40);
919 fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
920 fmask_state[7] |= va >> 8;
921 }
922 } else {
923 fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
924 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
925 S_008F20_PITCH(image->fmask.pitch_in_pixels - 1);
926 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
927
928 if (radv_image_is_tc_compat_cmask(image)) {
929 va = gpu_address + image->offset + image->cmask.offset;
930
931 fmask_state[6] |= S_008F28_COMPRESSION_EN(1);
932 fmask_state[7] |= va >> 8;
933 }
934 }
935 } else if (fmask_state)
936 memset(fmask_state, 0, 8 * 4);
937 }
938
939 static void
940 radv_make_texture_descriptor(struct radv_device *device,
941 struct radv_image *image,
942 bool is_storage_image,
943 VkImageViewType view_type,
944 VkFormat vk_format,
945 const VkComponentMapping *mapping,
946 unsigned first_level, unsigned last_level,
947 unsigned first_layer, unsigned last_layer,
948 unsigned width, unsigned height, unsigned depth,
949 uint32_t *state,
950 uint32_t *fmask_state)
951 {
952 if (device->physical_device->rad_info.chip_class >= GFX10) {
953 gfx10_make_texture_descriptor(device, image, is_storage_image,
954 view_type, vk_format, mapping,
955 first_level, last_level,
956 first_layer, last_layer,
957 width, height, depth,
958 state, fmask_state);
959 } else {
960 si_make_texture_descriptor(device, image, is_storage_image,
961 view_type, vk_format, mapping,
962 first_level, last_level,
963 first_layer, last_layer,
964 width, height, depth,
965 state, fmask_state);
966 }
967 }
968
969 static void
970 radv_query_opaque_metadata(struct radv_device *device,
971 struct radv_image *image,
972 struct radeon_bo_metadata *md)
973 {
974 static const VkComponentMapping fixedmapping;
975 uint32_t desc[8], i;
976
977 assert(image->plane_count == 1);
978
979 /* Metadata image format format version 1:
980 * [0] = 1 (metadata format identifier)
981 * [1] = (VENDOR_ID << 16) | PCI_ID
982 * [2:9] = image descriptor for the whole resource
983 * [2] is always 0, because the base address is cleared
984 * [9] is the DCC offset bits [39:8] from the beginning of
985 * the buffer
986 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
987 */
988 md->metadata[0] = 1; /* metadata image format version 1 */
989
990 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
991 md->metadata[1] = si_get_bo_metadata_word1(device);
992
993
994 radv_make_texture_descriptor(device, image, false,
995 (VkImageViewType)image->type, image->vk_format,
996 &fixedmapping, 0, image->info.levels - 1, 0,
997 image->info.array_size - 1,
998 image->info.width, image->info.height,
999 image->info.depth,
1000 desc, NULL);
1001
1002 si_set_mutable_tex_desc_fields(device, image, &image->planes[0].surface.u.legacy.level[0], 0, 0, 0,
1003 image->planes[0].surface.blk_w, false, false, desc);
1004
1005 /* Clear the base address and set the relative DCC offset. */
1006 desc[0] = 0;
1007 desc[1] &= C_008F14_BASE_ADDRESS_HI;
1008 desc[7] = image->dcc_offset >> 8;
1009
1010 /* Dwords [2:9] contain the image descriptor. */
1011 memcpy(&md->metadata[2], desc, sizeof(desc));
1012
1013 /* Dwords [10:..] contain the mipmap level offsets. */
1014 if (device->physical_device->rad_info.chip_class <= GFX8) {
1015 for (i = 0; i <= image->info.levels - 1; i++)
1016 md->metadata[10+i] = image->planes[0].surface.u.legacy.level[i].offset >> 8;
1017 md->size_metadata = (11 + image->info.levels - 1) * 4;
1018 }
1019 }
1020
1021 void
1022 radv_init_metadata(struct radv_device *device,
1023 struct radv_image *image,
1024 struct radeon_bo_metadata *metadata)
1025 {
1026 struct radeon_surf *surface = &image->planes[0].surface;
1027
1028 memset(metadata, 0, sizeof(*metadata));
1029
1030 if (device->physical_device->rad_info.chip_class >= GFX9) {
1031 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
1032 } else {
1033 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
1034 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
1035 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
1036 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
1037 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
1038 metadata->u.legacy.bankw = surface->u.legacy.bankw;
1039 metadata->u.legacy.bankh = surface->u.legacy.bankh;
1040 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
1041 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
1042 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
1043 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
1044 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
1045 }
1046 radv_query_opaque_metadata(device, image, metadata);
1047 }
1048
1049 void
1050 radv_image_override_offset_stride(struct radv_device *device,
1051 struct radv_image *image,
1052 uint64_t offset, uint32_t stride)
1053 {
1054 struct radeon_surf *surface = &image->planes[0].surface;
1055 unsigned bpe = vk_format_get_blocksizebits(image->vk_format) / 8;
1056
1057 if (device->physical_device->rad_info.chip_class >= GFX9) {
1058 if (stride) {
1059 surface->u.gfx9.surf_pitch = stride;
1060 surface->u.gfx9.surf_slice_size =
1061 (uint64_t)stride * surface->u.gfx9.surf_height * bpe;
1062 }
1063 surface->u.gfx9.surf_offset = offset;
1064 } else {
1065 surface->u.legacy.level[0].nblk_x = stride;
1066 surface->u.legacy.level[0].slice_size_dw =
1067 ((uint64_t)stride * surface->u.legacy.level[0].nblk_y * bpe) / 4;
1068
1069 if (offset) {
1070 for (unsigned i = 0; i < ARRAY_SIZE(surface->u.legacy.level); ++i)
1071 surface->u.legacy.level[i].offset += offset;
1072 }
1073
1074 }
1075 }
1076
1077 /* The number of samples can be specified independently of the texture. */
1078 static void
1079 radv_image_get_fmask_info(struct radv_device *device,
1080 struct radv_image *image,
1081 unsigned nr_samples,
1082 struct radv_fmask_info *out)
1083 {
1084 if (device->physical_device->rad_info.chip_class >= GFX9) {
1085 out->alignment = image->planes[0].surface.fmask_alignment;
1086 out->size = image->planes[0].surface.fmask_size;
1087 out->tile_swizzle = image->planes[0].surface.fmask_tile_swizzle;
1088 return;
1089 }
1090
1091 out->slice_tile_max = image->planes[0].surface.u.legacy.fmask.slice_tile_max;
1092 out->tile_mode_index = image->planes[0].surface.u.legacy.fmask.tiling_index;
1093 out->pitch_in_pixels = image->planes[0].surface.u.legacy.fmask.pitch_in_pixels;
1094 out->slice_size = image->planes[0].surface.u.legacy.fmask.slice_size;
1095 out->bank_height = image->planes[0].surface.u.legacy.fmask.bankh;
1096 out->tile_swizzle = image->planes[0].surface.fmask_tile_swizzle;
1097 out->alignment = image->planes[0].surface.fmask_alignment;
1098 out->size = image->planes[0].surface.fmask_size;
1099
1100 assert(!out->tile_swizzle || !image->shareable);
1101 }
1102
1103 static void
1104 radv_image_alloc_fmask(struct radv_device *device,
1105 struct radv_image *image)
1106 {
1107 radv_image_get_fmask_info(device, image, image->info.samples, &image->fmask);
1108
1109 image->fmask.offset = align64(image->size, image->fmask.alignment);
1110 image->size = image->fmask.offset + image->fmask.size;
1111 image->alignment = MAX2(image->alignment, image->fmask.alignment);
1112 }
1113
1114 static void
1115 radv_image_get_cmask_info(struct radv_device *device,
1116 struct radv_image *image,
1117 struct radv_cmask_info *out)
1118 {
1119 assert(image->plane_count == 1);
1120
1121 if (device->physical_device->rad_info.chip_class >= GFX9) {
1122 out->alignment = image->planes[0].surface.cmask_alignment;
1123 out->size = image->planes[0].surface.cmask_size;
1124 return;
1125 }
1126
1127 out->slice_tile_max = image->planes[0].surface.u.legacy.cmask_slice_tile_max;
1128 out->alignment = image->planes[0].surface.cmask_alignment;
1129 out->slice_size = image->planes[0].surface.cmask_slice_size;
1130 out->size = image->planes[0].surface.cmask_size;
1131 }
1132
1133 static void
1134 radv_image_alloc_cmask(struct radv_device *device,
1135 struct radv_image *image)
1136 {
1137 uint32_t clear_value_size = 0;
1138 radv_image_get_cmask_info(device, image, &image->cmask);
1139
1140 image->cmask.offset = align64(image->size, image->cmask.alignment);
1141 /* + 8 for storing the clear values */
1142 if (!image->clear_value_offset) {
1143 image->clear_value_offset = image->cmask.offset + image->cmask.size;
1144 clear_value_size = 8;
1145 }
1146 image->size = image->cmask.offset + image->cmask.size + clear_value_size;
1147 image->alignment = MAX2(image->alignment, image->cmask.alignment);
1148 }
1149
1150 static void
1151 radv_image_alloc_dcc(struct radv_image *image)
1152 {
1153 assert(image->plane_count == 1);
1154
1155 image->dcc_offset = align64(image->size, image->planes[0].surface.dcc_alignment);
1156 /* + 24 for storing the clear values + fce pred + dcc pred for each mip */
1157 image->clear_value_offset = image->dcc_offset + image->planes[0].surface.dcc_size;
1158 image->fce_pred_offset = image->clear_value_offset + 8 * image->info.levels;
1159 image->dcc_pred_offset = image->clear_value_offset + 16 * image->info.levels;
1160 image->size = image->dcc_offset + image->planes[0].surface.dcc_size + 24 * image->info.levels;
1161 image->alignment = MAX2(image->alignment, image->planes[0].surface.dcc_alignment);
1162 }
1163
1164 static void
1165 radv_image_alloc_htile(struct radv_image *image)
1166 {
1167 image->htile_offset = align64(image->size, image->planes[0].surface.htile_alignment);
1168
1169 /* + 8 for storing the clear values */
1170 image->clear_value_offset = image->htile_offset + image->planes[0].surface.htile_size;
1171 image->size = image->clear_value_offset + 8;
1172 if (radv_image_is_tc_compat_htile(image)) {
1173 /* Metadata for the TC-compatible HTILE hardware bug which
1174 * have to be fixed by updating ZRANGE_PRECISION when doing
1175 * fast depth clears to 0.0f.
1176 */
1177 image->tc_compat_zrange_offset = image->size;
1178 image->size = image->tc_compat_zrange_offset + 4;
1179 }
1180 image->alignment = align64(image->alignment, image->planes[0].surface.htile_alignment);
1181 }
1182
1183 static inline bool
1184 radv_image_can_enable_dcc_or_cmask(struct radv_image *image)
1185 {
1186 if (image->info.samples <= 1 &&
1187 image->info.width * image->info.height <= 512 * 512) {
1188 /* Do not enable CMASK or DCC for small surfaces where the cost
1189 * of the eliminate pass can be higher than the benefit of fast
1190 * clear. RadeonSI does this, but the image threshold is
1191 * different.
1192 */
1193 return false;
1194 }
1195
1196 return image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT &&
1197 (image->exclusive || image->queue_family_mask == 1);
1198 }
1199
1200 static inline bool
1201 radv_image_can_enable_dcc(struct radv_device *device, struct radv_image *image)
1202 {
1203 if (!radv_image_can_enable_dcc_or_cmask(image) ||
1204 !radv_image_has_dcc(image))
1205 return false;
1206
1207 /* On GFX8, DCC layers can be interleaved and it's currently only
1208 * enabled if slice size is equal to the per slice fast clear size
1209 * because the driver assumes that portions of multiple layers are
1210 * contiguous during fast clears.
1211 */
1212 if (image->info.array_size > 1) {
1213 const struct legacy_surf_level *surf_level =
1214 &image->planes[0].surface.u.legacy.level[0];
1215
1216 assert(device->physical_device->rad_info.chip_class == GFX8);
1217
1218 if (image->planes[0].surface.dcc_slice_size != surf_level->dcc_fast_clear_size)
1219 return false;
1220 }
1221
1222 return true;
1223 }
1224
1225 static inline bool
1226 radv_image_can_enable_cmask(struct radv_image *image)
1227 {
1228 if (image->planes[0].surface.bpe > 8 && image->info.samples == 1) {
1229 /* Do not enable CMASK for non-MSAA images (fast color clear)
1230 * because 128 bit formats are not supported, but FMASK might
1231 * still be used.
1232 */
1233 return false;
1234 }
1235
1236 return radv_image_can_enable_dcc_or_cmask(image) &&
1237 image->info.levels == 1 &&
1238 image->info.depth == 1 &&
1239 !image->planes[0].surface.is_linear;
1240 }
1241
1242 static inline bool
1243 radv_image_can_enable_fmask(struct radv_image *image)
1244 {
1245 return image->info.samples > 1 && vk_format_is_color(image->vk_format);
1246 }
1247
1248 static inline bool
1249 radv_image_can_enable_htile(struct radv_image *image)
1250 {
1251 return radv_image_has_htile(image) &&
1252 image->info.levels == 1 &&
1253 image->info.width * image->info.height >= 8 * 8;
1254 }
1255
1256 static void radv_image_disable_dcc(struct radv_image *image)
1257 {
1258 for (unsigned i = 0; i < image->plane_count; ++i)
1259 image->planes[i].surface.dcc_size = 0;
1260 }
1261
1262 static void radv_image_disable_htile(struct radv_image *image)
1263 {
1264 for (unsigned i = 0; i < image->plane_count; ++i)
1265 image->planes[i].surface.htile_size = 0;
1266 }
1267
1268 VkResult
1269 radv_image_create(VkDevice _device,
1270 const struct radv_image_create_info *create_info,
1271 const VkAllocationCallbacks* alloc,
1272 VkImage *pImage)
1273 {
1274 RADV_FROM_HANDLE(radv_device, device, _device);
1275 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
1276 struct radv_image *image = NULL;
1277 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
1278
1279 const unsigned plane_count = vk_format_get_plane_count(pCreateInfo->format);
1280 const size_t image_struct_size = sizeof(*image) + sizeof(struct radv_image_plane) * plane_count;
1281
1282 radv_assert(pCreateInfo->mipLevels > 0);
1283 radv_assert(pCreateInfo->arrayLayers > 0);
1284 radv_assert(pCreateInfo->samples > 0);
1285 radv_assert(pCreateInfo->extent.width > 0);
1286 radv_assert(pCreateInfo->extent.height > 0);
1287 radv_assert(pCreateInfo->extent.depth > 0);
1288
1289 image = vk_zalloc2(&device->alloc, alloc, image_struct_size, 8,
1290 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1291 if (!image)
1292 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1293
1294 image->type = pCreateInfo->imageType;
1295 image->info.width = pCreateInfo->extent.width;
1296 image->info.height = pCreateInfo->extent.height;
1297 image->info.depth = pCreateInfo->extent.depth;
1298 image->info.samples = pCreateInfo->samples;
1299 image->info.storage_samples = pCreateInfo->samples;
1300 image->info.array_size = pCreateInfo->arrayLayers;
1301 image->info.levels = pCreateInfo->mipLevels;
1302 image->info.num_channels = vk_format_get_nr_components(pCreateInfo->format);
1303
1304 image->vk_format = pCreateInfo->format;
1305 image->tiling = pCreateInfo->tiling;
1306 image->usage = pCreateInfo->usage;
1307 image->flags = pCreateInfo->flags;
1308
1309 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
1310 if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
1311 for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
1312 if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL ||
1313 pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_FOREIGN_EXT)
1314 image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1315 else
1316 image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
1317 }
1318
1319 image->shareable = vk_find_struct_const(pCreateInfo->pNext,
1320 EXTERNAL_MEMORY_IMAGE_CREATE_INFO) != NULL;
1321 if (!vk_format_is_depth_or_stencil(pCreateInfo->format) &&
1322 !radv_surface_has_scanout(device, create_info) && !image->shareable) {
1323 image->info.surf_index = &device->image_mrt_offset_counter;
1324 }
1325
1326 image->plane_count = plane_count;
1327 image->size = 0;
1328 image->alignment = 1;
1329 for (unsigned plane = 0; plane < plane_count; ++plane) {
1330 struct ac_surf_info info = image->info;
1331 radv_init_surface(device, image, &image->planes[plane].surface, plane, create_info);
1332
1333 if (plane) {
1334 const struct vk_format_description *desc = vk_format_description(pCreateInfo->format);
1335 assert(info.width % desc->width_divisor == 0);
1336 assert(info.height % desc->height_divisor == 0);
1337
1338 info.width /= desc->width_divisor;
1339 info.height /= desc->height_divisor;
1340 }
1341
1342 device->ws->surface_init(device->ws, &info, &image->planes[plane].surface);
1343
1344 image->planes[plane].offset = align(image->size, image->planes[plane].surface.surf_alignment);
1345 image->size = image->planes[plane].offset + image->planes[plane].surface.surf_size;
1346 image->alignment = image->planes[plane].surface.surf_alignment;
1347
1348 image->planes[plane].format = vk_format_get_plane_format(image->vk_format, plane);
1349 }
1350
1351 if (!create_info->no_metadata_planes) {
1352 /* Try to enable DCC first. */
1353 if (radv_image_can_enable_dcc(device, image)) {
1354 radv_image_alloc_dcc(image);
1355 if (image->info.samples > 1) {
1356 /* CMASK should be enabled because DCC fast
1357 * clear with MSAA needs it.
1358 */
1359 assert(radv_image_can_enable_cmask(image));
1360 radv_image_alloc_cmask(device, image);
1361 }
1362 } else {
1363 /* When DCC cannot be enabled, try CMASK. */
1364 radv_image_disable_dcc(image);
1365 if (radv_image_can_enable_cmask(image)) {
1366 radv_image_alloc_cmask(device, image);
1367 }
1368 }
1369
1370 /* Try to enable FMASK for multisampled images. */
1371 if (radv_image_can_enable_fmask(image)) {
1372 radv_image_alloc_fmask(device, image);
1373
1374 if (radv_use_tc_compat_cmask_for_image(device, image))
1375 image->tc_compatible_cmask = true;
1376 } else {
1377 /* Otherwise, try to enable HTILE for depth surfaces. */
1378 if (radv_image_can_enable_htile(image) &&
1379 !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
1380 image->tc_compatible_htile = image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1381 radv_image_alloc_htile(image);
1382 } else {
1383 radv_image_disable_htile(image);
1384 }
1385 }
1386 } else {
1387 radv_image_disable_dcc(image);
1388 radv_image_disable_htile(image);
1389 }
1390
1391 if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
1392 image->alignment = MAX2(image->alignment, 4096);
1393 image->size = align64(image->size, image->alignment);
1394 image->offset = 0;
1395
1396 image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
1397 0, RADEON_FLAG_VIRTUAL, RADV_BO_PRIORITY_VIRTUAL);
1398 if (!image->bo) {
1399 vk_free2(&device->alloc, alloc, image);
1400 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
1401 }
1402 }
1403
1404 *pImage = radv_image_to_handle(image);
1405
1406 return VK_SUCCESS;
1407 }
1408
1409 static void
1410 radv_image_view_make_descriptor(struct radv_image_view *iview,
1411 struct radv_device *device,
1412 VkFormat vk_format,
1413 const VkComponentMapping *components,
1414 bool is_storage_image, unsigned plane_id,
1415 unsigned descriptor_plane_id)
1416 {
1417 struct radv_image *image = iview->image;
1418 struct radv_image_plane *plane = &image->planes[plane_id];
1419 const struct vk_format_description *format_desc = vk_format_description(image->vk_format);
1420 bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
1421 uint32_t blk_w;
1422 union radv_descriptor *descriptor;
1423 uint32_t hw_level = 0;
1424
1425 if (is_storage_image) {
1426 descriptor = &iview->storage_descriptor;
1427 } else {
1428 descriptor = &iview->descriptor;
1429 }
1430
1431 assert(vk_format_get_plane_count(vk_format) == 1);
1432 assert(plane->surface.blk_w % vk_format_get_blockwidth(plane->format) == 0);
1433 blk_w = plane->surface.blk_w / vk_format_get_blockwidth(plane->format) * vk_format_get_blockwidth(vk_format);
1434
1435 if (device->physical_device->rad_info.chip_class >= GFX9)
1436 hw_level = iview->base_mip;
1437 radv_make_texture_descriptor(device, image, is_storage_image,
1438 iview->type,
1439 vk_format,
1440 components,
1441 hw_level, hw_level + iview->level_count - 1,
1442 iview->base_layer,
1443 iview->base_layer + iview->layer_count - 1,
1444 iview->extent.width / (plane_id ? format_desc->width_divisor : 1),
1445 iview->extent.height / (plane_id ? format_desc->height_divisor : 1),
1446 iview->extent.depth,
1447 descriptor->plane_descriptors[descriptor_plane_id],
1448 descriptor_plane_id ? NULL : descriptor->fmask_descriptor);
1449
1450 const struct legacy_surf_level *base_level_info = NULL;
1451 if (device->physical_device->rad_info.chip_class <= GFX9) {
1452 if (is_stencil)
1453 base_level_info = &plane->surface.u.legacy.stencil_level[iview->base_mip];
1454 else
1455 base_level_info = &plane->surface.u.legacy.level[iview->base_mip];
1456 }
1457 si_set_mutable_tex_desc_fields(device, image,
1458 base_level_info,
1459 plane_id,
1460 iview->base_mip,
1461 iview->base_mip,
1462 blk_w, is_stencil, is_storage_image, descriptor->plane_descriptors[descriptor_plane_id]);
1463 }
1464
1465 static unsigned
1466 radv_plane_from_aspect(VkImageAspectFlags mask)
1467 {
1468 switch(mask) {
1469 case VK_IMAGE_ASPECT_PLANE_1_BIT:
1470 return 1;
1471 case VK_IMAGE_ASPECT_PLANE_2_BIT:
1472 return 2;
1473 default:
1474 return 0;
1475 }
1476 }
1477
1478 VkFormat
1479 radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask)
1480 {
1481 switch(mask) {
1482 case VK_IMAGE_ASPECT_PLANE_0_BIT:
1483 return image->planes[0].format;
1484 case VK_IMAGE_ASPECT_PLANE_1_BIT:
1485 return image->planes[1].format;
1486 case VK_IMAGE_ASPECT_PLANE_2_BIT:
1487 return image->planes[2].format;
1488 case VK_IMAGE_ASPECT_STENCIL_BIT:
1489 return vk_format_stencil_only(image->vk_format);
1490 case VK_IMAGE_ASPECT_DEPTH_BIT:
1491 return vk_format_depth_only(image->vk_format);
1492 case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
1493 return vk_format_depth_only(image->vk_format);
1494 default:
1495 return image->vk_format;
1496 }
1497 }
1498
1499 void
1500 radv_image_view_init(struct radv_image_view *iview,
1501 struct radv_device *device,
1502 const VkImageViewCreateInfo* pCreateInfo)
1503 {
1504 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
1505 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
1506
1507 switch (image->type) {
1508 case VK_IMAGE_TYPE_1D:
1509 case VK_IMAGE_TYPE_2D:
1510 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size);
1511 break;
1512 case VK_IMAGE_TYPE_3D:
1513 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
1514 <= radv_minify(image->info.depth, range->baseMipLevel));
1515 break;
1516 default:
1517 unreachable("bad VkImageType");
1518 }
1519 iview->image = image;
1520 iview->bo = image->bo;
1521 iview->type = pCreateInfo->viewType;
1522 iview->plane_id = radv_plane_from_aspect(pCreateInfo->subresourceRange.aspectMask);
1523 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
1524 iview->multiple_planes = vk_format_get_plane_count(image->vk_format) > 1 && iview->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT;
1525 iview->vk_format = pCreateInfo->format;
1526
1527 if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
1528 iview->vk_format = vk_format_stencil_only(iview->vk_format);
1529 } else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
1530 iview->vk_format = vk_format_depth_only(iview->vk_format);
1531 }
1532
1533 if (device->physical_device->rad_info.chip_class >= GFX9) {
1534 iview->extent = (VkExtent3D) {
1535 .width = image->info.width,
1536 .height = image->info.height,
1537 .depth = image->info.depth,
1538 };
1539 } else {
1540 iview->extent = (VkExtent3D) {
1541 .width = radv_minify(image->info.width , range->baseMipLevel),
1542 .height = radv_minify(image->info.height, range->baseMipLevel),
1543 .depth = radv_minify(image->info.depth , range->baseMipLevel),
1544 };
1545 }
1546
1547 if (iview->vk_format != image->planes[iview->plane_id].format) {
1548 unsigned view_bw = vk_format_get_blockwidth(iview->vk_format);
1549 unsigned view_bh = vk_format_get_blockheight(iview->vk_format);
1550 unsigned img_bw = vk_format_get_blockwidth(image->vk_format);
1551 unsigned img_bh = vk_format_get_blockheight(image->vk_format);
1552
1553 iview->extent.width = round_up_u32(iview->extent.width * view_bw, img_bw);
1554 iview->extent.height = round_up_u32(iview->extent.height * view_bh, img_bh);
1555
1556 /* Comment ported from amdvlk -
1557 * If we have the following image:
1558 * Uncompressed pixels Compressed block sizes (4x4)
1559 * mip0: 22 x 22 6 x 6
1560 * mip1: 11 x 11 3 x 3
1561 * mip2: 5 x 5 2 x 2
1562 * mip3: 2 x 2 1 x 1
1563 * mip4: 1 x 1 1 x 1
1564 *
1565 * On GFX9 the descriptor is always programmed with the WIDTH and HEIGHT of the base level and the HW is
1566 * calculating the degradation of the block sizes down the mip-chain as follows (straight-up
1567 * divide-by-two integer math):
1568 * mip0: 6x6
1569 * mip1: 3x3
1570 * mip2: 1x1
1571 * mip3: 1x1
1572 *
1573 * This means that mip2 will be missing texels.
1574 *
1575 * Fix this by calculating the base mip's width and height, then convert that, and round it
1576 * back up to get the level 0 size.
1577 * Clamp the converted size between the original values, and next power of two, which
1578 * means we don't oversize the image.
1579 */
1580 if (device->physical_device->rad_info.chip_class >= GFX9 &&
1581 vk_format_is_compressed(image->vk_format) &&
1582 !vk_format_is_compressed(iview->vk_format)) {
1583 unsigned lvl_width = radv_minify(image->info.width , range->baseMipLevel);
1584 unsigned lvl_height = radv_minify(image->info.height, range->baseMipLevel);
1585
1586 lvl_width = round_up_u32(lvl_width * view_bw, img_bw);
1587 lvl_height = round_up_u32(lvl_height * view_bh, img_bh);
1588
1589 lvl_width <<= range->baseMipLevel;
1590 lvl_height <<= range->baseMipLevel;
1591
1592 iview->extent.width = CLAMP(lvl_width, iview->extent.width, iview->image->planes[0].surface.u.gfx9.surf_pitch);
1593 iview->extent.height = CLAMP(lvl_height, iview->extent.height, iview->image->planes[0].surface.u.gfx9.surf_height);
1594 }
1595 }
1596
1597 iview->base_layer = range->baseArrayLayer;
1598 iview->layer_count = radv_get_layerCount(image, range);
1599 iview->base_mip = range->baseMipLevel;
1600 iview->level_count = radv_get_levelCount(image, range);
1601
1602 for (unsigned i = 0; i < (iview->multiple_planes ? vk_format_get_plane_count(image->vk_format) : 1); ++i) {
1603 VkFormat format = vk_format_get_plane_format(iview->vk_format, i);
1604 radv_image_view_make_descriptor(iview, device, format, &pCreateInfo->components, false, iview->plane_id + i, i);
1605 radv_image_view_make_descriptor(iview, device, format, &pCreateInfo->components, true, iview->plane_id + i, i);
1606 }
1607 }
1608
1609 bool radv_layout_has_htile(const struct radv_image *image,
1610 VkImageLayout layout,
1611 unsigned queue_mask)
1612 {
1613 if (radv_image_is_tc_compat_htile(image))
1614 return layout != VK_IMAGE_LAYOUT_GENERAL;
1615
1616 return radv_image_has_htile(image) &&
1617 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1618 (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1619 queue_mask == (1u << RADV_QUEUE_GENERAL)));
1620 }
1621
1622 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1623 VkImageLayout layout,
1624 unsigned queue_mask)
1625 {
1626 if (radv_image_is_tc_compat_htile(image))
1627 return layout != VK_IMAGE_LAYOUT_GENERAL;
1628
1629 return radv_image_has_htile(image) &&
1630 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1631 (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1632 queue_mask == (1u << RADV_QUEUE_GENERAL)));
1633 }
1634
1635 bool radv_layout_can_fast_clear(const struct radv_image *image,
1636 VkImageLayout layout,
1637 unsigned queue_mask)
1638 {
1639 return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
1640 }
1641
1642 bool radv_layout_dcc_compressed(const struct radv_image *image,
1643 VkImageLayout layout,
1644 unsigned queue_mask)
1645 {
1646 /* Don't compress compute transfer dst, as image stores are not supported. */
1647 if (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1648 (queue_mask & (1u << RADV_QUEUE_COMPUTE)))
1649 return false;
1650
1651 return radv_image_has_dcc(image) && layout != VK_IMAGE_LAYOUT_GENERAL;
1652 }
1653
1654
1655 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
1656 {
1657 if (!image->exclusive)
1658 return image->queue_family_mask;
1659 if (family == VK_QUEUE_FAMILY_EXTERNAL ||
1660 family == VK_QUEUE_FAMILY_FOREIGN_EXT)
1661 return (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1662 if (family == VK_QUEUE_FAMILY_IGNORED)
1663 return 1u << queue_family;
1664 return 1u << family;
1665 }
1666
1667 VkResult
1668 radv_CreateImage(VkDevice device,
1669 const VkImageCreateInfo *pCreateInfo,
1670 const VkAllocationCallbacks *pAllocator,
1671 VkImage *pImage)
1672 {
1673 #ifdef ANDROID
1674 const VkNativeBufferANDROID *gralloc_info =
1675 vk_find_struct_const(pCreateInfo->pNext, NATIVE_BUFFER_ANDROID);
1676
1677 if (gralloc_info)
1678 return radv_image_from_gralloc(device, pCreateInfo, gralloc_info,
1679 pAllocator, pImage);
1680 #endif
1681
1682 const struct wsi_image_create_info *wsi_info =
1683 vk_find_struct_const(pCreateInfo->pNext, WSI_IMAGE_CREATE_INFO_MESA);
1684 bool scanout = wsi_info && wsi_info->scanout;
1685
1686 return radv_image_create(device,
1687 &(struct radv_image_create_info) {
1688 .vk_info = pCreateInfo,
1689 .scanout = scanout,
1690 },
1691 pAllocator,
1692 pImage);
1693 }
1694
1695 void
1696 radv_DestroyImage(VkDevice _device, VkImage _image,
1697 const VkAllocationCallbacks *pAllocator)
1698 {
1699 RADV_FROM_HANDLE(radv_device, device, _device);
1700 RADV_FROM_HANDLE(radv_image, image, _image);
1701
1702 if (!image)
1703 return;
1704
1705 if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
1706 device->ws->buffer_destroy(image->bo);
1707
1708 if (image->owned_memory != VK_NULL_HANDLE)
1709 radv_FreeMemory(_device, image->owned_memory, pAllocator);
1710
1711 vk_free2(&device->alloc, pAllocator, image);
1712 }
1713
1714 void radv_GetImageSubresourceLayout(
1715 VkDevice _device,
1716 VkImage _image,
1717 const VkImageSubresource* pSubresource,
1718 VkSubresourceLayout* pLayout)
1719 {
1720 RADV_FROM_HANDLE(radv_image, image, _image);
1721 RADV_FROM_HANDLE(radv_device, device, _device);
1722 int level = pSubresource->mipLevel;
1723 int layer = pSubresource->arrayLayer;
1724
1725 unsigned plane_id = radv_plane_from_aspect(pSubresource->aspectMask);
1726
1727 struct radv_image_plane *plane = &image->planes[plane_id];
1728 struct radeon_surf *surface = &plane->surface;
1729
1730 if (device->physical_device->rad_info.chip_class >= GFX9) {
1731 pLayout->offset = plane->offset + surface->u.gfx9.offset[level] + surface->u.gfx9.surf_slice_size * layer;
1732 if (image->vk_format == VK_FORMAT_R32G32B32_UINT ||
1733 image->vk_format == VK_FORMAT_R32G32B32_SINT ||
1734 image->vk_format == VK_FORMAT_R32G32B32_SFLOAT) {
1735 /* Adjust the number of bytes between each row because
1736 * the pitch is actually the number of components per
1737 * row.
1738 */
1739 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe / 3;
1740 } else {
1741 assert(util_is_power_of_two_nonzero(surface->bpe));
1742 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe;
1743 }
1744
1745 pLayout->arrayPitch = surface->u.gfx9.surf_slice_size;
1746 pLayout->depthPitch = surface->u.gfx9.surf_slice_size;
1747 pLayout->size = surface->u.gfx9.surf_slice_size;
1748 if (image->type == VK_IMAGE_TYPE_3D)
1749 pLayout->size *= u_minify(image->info.depth, level);
1750 } else {
1751 pLayout->offset = plane->offset + surface->u.legacy.level[level].offset + (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4 * layer;
1752 pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
1753 pLayout->arrayPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1754 pLayout->depthPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1755 pLayout->size = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1756 if (image->type == VK_IMAGE_TYPE_3D)
1757 pLayout->size *= u_minify(image->info.depth, level);
1758 }
1759 }
1760
1761
1762 VkResult
1763 radv_CreateImageView(VkDevice _device,
1764 const VkImageViewCreateInfo *pCreateInfo,
1765 const VkAllocationCallbacks *pAllocator,
1766 VkImageView *pView)
1767 {
1768 RADV_FROM_HANDLE(radv_device, device, _device);
1769 struct radv_image_view *view;
1770
1771 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1772 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1773 if (view == NULL)
1774 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1775
1776 radv_image_view_init(view, device, pCreateInfo);
1777
1778 *pView = radv_image_view_to_handle(view);
1779
1780 return VK_SUCCESS;
1781 }
1782
1783 void
1784 radv_DestroyImageView(VkDevice _device, VkImageView _iview,
1785 const VkAllocationCallbacks *pAllocator)
1786 {
1787 RADV_FROM_HANDLE(radv_device, device, _device);
1788 RADV_FROM_HANDLE(radv_image_view, iview, _iview);
1789
1790 if (!iview)
1791 return;
1792 vk_free2(&device->alloc, pAllocator, iview);
1793 }
1794
1795 void radv_buffer_view_init(struct radv_buffer_view *view,
1796 struct radv_device *device,
1797 const VkBufferViewCreateInfo* pCreateInfo)
1798 {
1799 RADV_FROM_HANDLE(radv_buffer, buffer, pCreateInfo->buffer);
1800
1801 view->bo = buffer->bo;
1802 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
1803 buffer->size - pCreateInfo->offset : pCreateInfo->range;
1804 view->vk_format = pCreateInfo->format;
1805
1806 radv_make_buffer_descriptor(device, buffer, view->vk_format,
1807 pCreateInfo->offset, view->range, view->state);
1808 }
1809
1810 VkResult
1811 radv_CreateBufferView(VkDevice _device,
1812 const VkBufferViewCreateInfo *pCreateInfo,
1813 const VkAllocationCallbacks *pAllocator,
1814 VkBufferView *pView)
1815 {
1816 RADV_FROM_HANDLE(radv_device, device, _device);
1817 struct radv_buffer_view *view;
1818
1819 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1820 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1821 if (!view)
1822 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1823
1824 radv_buffer_view_init(view, device, pCreateInfo);
1825
1826 *pView = radv_buffer_view_to_handle(view);
1827
1828 return VK_SUCCESS;
1829 }
1830
1831 void
1832 radv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
1833 const VkAllocationCallbacks *pAllocator)
1834 {
1835 RADV_FROM_HANDLE(radv_device, device, _device);
1836 RADV_FROM_HANDLE(radv_buffer_view, view, bufferView);
1837
1838 if (!view)
1839 return;
1840
1841 vk_free2(&device->alloc, pAllocator, view);
1842 }