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radv: allocate DCC metadata for each mip
[mesa.git] / src / amd / vulkan / radv_image.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "vk_format.h"
31 #include "vk_util.h"
32 #include "radv_radeon_winsys.h"
33 #include "sid.h"
34 #include "util/debug.h"
35 #include "util/u_atomic.h"
36
37 static unsigned
38 radv_choose_tiling(struct radv_device *device,
39 const struct radv_image_create_info *create_info)
40 {
41 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
42
43 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) {
44 assert(pCreateInfo->samples <= 1);
45 return RADEON_SURF_MODE_LINEAR_ALIGNED;
46 }
47
48 if (!vk_format_is_compressed(pCreateInfo->format) &&
49 !vk_format_is_depth_or_stencil(pCreateInfo->format)
50 && device->physical_device->rad_info.chip_class <= GFX8) {
51 /* this causes hangs in some VK CTS tests on GFX9. */
52 /* Textures with a very small height are recommended to be linear. */
53 if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
54 /* Only very thin and long 2D textures should benefit from
55 * linear_aligned. */
56 (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
57 return RADEON_SURF_MODE_LINEAR_ALIGNED;
58 }
59
60 /* MSAA resources must be 2D tiled. */
61 if (pCreateInfo->samples > 1)
62 return RADEON_SURF_MODE_2D;
63
64 return RADEON_SURF_MODE_2D;
65 }
66
67 static bool
68 radv_use_tc_compat_htile_for_image(struct radv_device *device,
69 const VkImageCreateInfo *pCreateInfo)
70 {
71 /* TC-compat HTILE is only available for GFX8+. */
72 if (device->physical_device->rad_info.chip_class < GFX8)
73 return false;
74
75 if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
76 (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
77 return false;
78
79 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
80 return false;
81
82 if (pCreateInfo->mipLevels > 1)
83 return false;
84
85 /* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
86 * tests - disable for now */
87 if (pCreateInfo->samples >= 2 &&
88 pCreateInfo->format == VK_FORMAT_D32_SFLOAT_S8_UINT)
89 return false;
90
91 /* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only
92 * supports 32-bit. Though, it's possible to enable TC-compat for
93 * 16-bit depth surfaces if no Z planes are compressed.
94 */
95 if (pCreateInfo->format != VK_FORMAT_D32_SFLOAT_S8_UINT &&
96 pCreateInfo->format != VK_FORMAT_D32_SFLOAT &&
97 pCreateInfo->format != VK_FORMAT_D16_UNORM)
98 return false;
99
100 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
101 const struct VkImageFormatListCreateInfoKHR *format_list =
102 (const struct VkImageFormatListCreateInfoKHR *)
103 vk_find_struct_const(pCreateInfo->pNext,
104 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
105
106 /* We have to ignore the existence of the list if viewFormatCount = 0 */
107 if (format_list && format_list->viewFormatCount) {
108 /* compatibility is transitive, so we only need to check
109 * one format with everything else.
110 */
111 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
112 if (format_list->pViewFormats[i] == VK_FORMAT_UNDEFINED)
113 continue;
114
115 if (pCreateInfo->format != format_list->pViewFormats[i])
116 return false;
117 }
118 } else {
119 return false;
120 }
121 }
122
123 return true;
124 }
125
126 static bool
127 radv_surface_has_scanout(struct radv_device *device, const struct radv_image_create_info *info)
128 {
129 if (info->scanout)
130 return true;
131
132 if (!info->bo_metadata)
133 return false;
134
135 if (device->physical_device->rad_info.chip_class >= GFX9) {
136 return info->bo_metadata->u.gfx9.swizzle_mode == 0 || info->bo_metadata->u.gfx9.swizzle_mode % 4 == 2;
137 } else {
138 return info->bo_metadata->u.legacy.scanout;
139 }
140 }
141
142 static bool
143 radv_use_dcc_for_image(struct radv_device *device,
144 const struct radv_image *image,
145 const struct radv_image_create_info *create_info,
146 const VkImageCreateInfo *pCreateInfo)
147 {
148 bool dcc_compatible_formats;
149 bool blendable;
150
151 /* DCC (Delta Color Compression) is only available for GFX8+. */
152 if (device->physical_device->rad_info.chip_class < GFX8)
153 return false;
154
155 if (device->instance->debug_flags & RADV_DEBUG_NO_DCC)
156 return false;
157
158 if (image->shareable)
159 return false;
160
161 /* TODO: Enable DCC for storage images. */
162 if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
163 (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
164 return false;
165
166 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
167 return false;
168
169 if (vk_format_is_subsampled(pCreateInfo->format) ||
170 vk_format_get_plane_count(pCreateInfo->format) > 1)
171 return false;
172
173 /* TODO: Enable DCC for mipmaps and array layers. */
174 if (pCreateInfo->mipLevels > 1 || pCreateInfo->arrayLayers > 1)
175 return false;
176
177 if (radv_surface_has_scanout(device, create_info))
178 return false;
179
180 /* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet, while
181 * 2x can be enabled with an option.
182 */
183 if (pCreateInfo->samples > 2 ||
184 (pCreateInfo->samples == 2 &&
185 !device->physical_device->dcc_msaa_allowed))
186 return false;
187
188 /* Determine if the formats are DCC compatible. */
189 dcc_compatible_formats =
190 radv_is_colorbuffer_format_supported(pCreateInfo->format,
191 &blendable);
192
193 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
194 const struct VkImageFormatListCreateInfoKHR *format_list =
195 (const struct VkImageFormatListCreateInfoKHR *)
196 vk_find_struct_const(pCreateInfo->pNext,
197 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
198
199 /* We have to ignore the existence of the list if viewFormatCount = 0 */
200 if (format_list && format_list->viewFormatCount) {
201 /* compatibility is transitive, so we only need to check
202 * one format with everything else. */
203 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
204 if (format_list->pViewFormats[i] == VK_FORMAT_UNDEFINED)
205 continue;
206
207 if (!radv_dcc_formats_compatible(pCreateInfo->format,
208 format_list->pViewFormats[i]))
209 dcc_compatible_formats = false;
210 }
211 } else {
212 dcc_compatible_formats = false;
213 }
214 }
215
216 if (!dcc_compatible_formats)
217 return false;
218
219 return true;
220 }
221
222 static void
223 radv_prefill_surface_from_metadata(struct radv_device *device,
224 struct radeon_surf *surface,
225 const struct radv_image_create_info *create_info)
226 {
227 const struct radeon_bo_metadata *md = create_info->bo_metadata;
228 if (device->physical_device->rad_info.chip_class >= GFX9) {
229 if (md->u.gfx9.swizzle_mode > 0)
230 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
231 else
232 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
233
234 surface->u.gfx9.surf.swizzle_mode = md->u.gfx9.swizzle_mode;
235 } else {
236 surface->u.legacy.pipe_config = md->u.legacy.pipe_config;
237 surface->u.legacy.bankw = md->u.legacy.bankw;
238 surface->u.legacy.bankh = md->u.legacy.bankh;
239 surface->u.legacy.tile_split = md->u.legacy.tile_split;
240 surface->u.legacy.mtilea = md->u.legacy.mtilea;
241 surface->u.legacy.num_banks = md->u.legacy.num_banks;
242
243 if (md->u.legacy.macrotile == RADEON_LAYOUT_TILED)
244 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_2D, MODE);
245 else if (md->u.legacy.microtile == RADEON_LAYOUT_TILED)
246 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_1D, MODE);
247 else
248 surface->flags |= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED, MODE);
249
250 }
251 }
252
253 static int
254 radv_init_surface(struct radv_device *device,
255 const struct radv_image *image,
256 struct radeon_surf *surface,
257 unsigned plane_id,
258 const struct radv_image_create_info *create_info)
259 {
260 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
261 unsigned array_mode = radv_choose_tiling(device, create_info);
262 VkFormat format = vk_format_get_plane_format(pCreateInfo->format, plane_id);
263 const struct vk_format_description *desc = vk_format_description(format);
264 bool is_depth, is_stencil;
265
266 is_depth = vk_format_has_depth(desc);
267 is_stencil = vk_format_has_stencil(desc);
268
269 surface->blk_w = vk_format_get_blockwidth(format);
270 surface->blk_h = vk_format_get_blockheight(format);
271
272 surface->bpe = vk_format_get_blocksize(vk_format_depth_only(format));
273 /* align byte per element on dword */
274 if (surface->bpe == 3) {
275 surface->bpe = 4;
276 }
277 if (create_info->bo_metadata) {
278 radv_prefill_surface_from_metadata(device, surface, create_info);
279 } else {
280 surface->flags = RADEON_SURF_SET(array_mode, MODE);
281 }
282
283 switch (pCreateInfo->imageType){
284 case VK_IMAGE_TYPE_1D:
285 if (pCreateInfo->arrayLayers > 1)
286 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
287 else
288 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
289 break;
290 case VK_IMAGE_TYPE_2D:
291 if (pCreateInfo->arrayLayers > 1)
292 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
293 else
294 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
295 break;
296 case VK_IMAGE_TYPE_3D:
297 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
298 break;
299 default:
300 unreachable("unhandled image type");
301 }
302
303 if (is_depth) {
304 surface->flags |= RADEON_SURF_ZBUFFER;
305 if (radv_use_tc_compat_htile_for_image(device, pCreateInfo))
306 surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
307 }
308
309 if (is_stencil)
310 surface->flags |= RADEON_SURF_SBUFFER;
311
312 if (device->physical_device->rad_info.chip_class >= GFX9 &&
313 pCreateInfo->imageType == VK_IMAGE_TYPE_3D &&
314 vk_format_get_blocksizebits(pCreateInfo->format) == 128 &&
315 vk_format_is_compressed(pCreateInfo->format))
316 surface->flags |= RADEON_SURF_NO_RENDER_TARGET;
317
318 surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
319
320 if (!radv_use_dcc_for_image(device, image, create_info, pCreateInfo))
321 surface->flags |= RADEON_SURF_DISABLE_DCC;
322
323 if (radv_surface_has_scanout(device, create_info))
324 surface->flags |= RADEON_SURF_SCANOUT;
325
326 return 0;
327 }
328
329 static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
330 {
331 return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
332 }
333
334 static inline unsigned
335 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
336 {
337 if (stencil)
338 return plane->surface.u.legacy.stencil_tiling_index[level];
339 else
340 return plane->surface.u.legacy.tiling_index[level];
341 }
342
343 static unsigned radv_map_swizzle(unsigned swizzle)
344 {
345 switch (swizzle) {
346 case VK_SWIZZLE_Y:
347 return V_008F0C_SQ_SEL_Y;
348 case VK_SWIZZLE_Z:
349 return V_008F0C_SQ_SEL_Z;
350 case VK_SWIZZLE_W:
351 return V_008F0C_SQ_SEL_W;
352 case VK_SWIZZLE_0:
353 return V_008F0C_SQ_SEL_0;
354 case VK_SWIZZLE_1:
355 return V_008F0C_SQ_SEL_1;
356 default: /* VK_SWIZZLE_X */
357 return V_008F0C_SQ_SEL_X;
358 }
359 }
360
361 static void
362 radv_make_buffer_descriptor(struct radv_device *device,
363 struct radv_buffer *buffer,
364 VkFormat vk_format,
365 unsigned offset,
366 unsigned range,
367 uint32_t *state)
368 {
369 const struct vk_format_description *desc;
370 unsigned stride;
371 uint64_t gpu_address = radv_buffer_get_va(buffer->bo);
372 uint64_t va = gpu_address + buffer->offset;
373 unsigned num_format, data_format;
374 int first_non_void;
375 desc = vk_format_description(vk_format);
376 first_non_void = vk_format_get_first_non_void_channel(vk_format);
377 stride = desc->block.bits / 8;
378
379 num_format = radv_translate_buffer_numformat(desc, first_non_void);
380 data_format = radv_translate_buffer_dataformat(desc, first_non_void);
381
382 assert(data_format != V_008F0C_BUF_DATA_FORMAT_INVALID);
383 assert(num_format != ~0);
384
385 va += offset;
386 state[0] = va;
387 state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
388 S_008F04_STRIDE(stride);
389
390 if (device->physical_device->rad_info.chip_class != GFX8 && stride) {
391 range /= stride;
392 }
393
394 state[2] = range;
395 state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
396 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
397 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
398 S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3])) |
399 S_008F0C_NUM_FORMAT(num_format) |
400 S_008F0C_DATA_FORMAT(data_format);
401 }
402
403 static void
404 si_set_mutable_tex_desc_fields(struct radv_device *device,
405 struct radv_image *image,
406 const struct legacy_surf_level *base_level_info,
407 unsigned plane_id,
408 unsigned base_level, unsigned first_level,
409 unsigned block_width, bool is_stencil,
410 bool is_storage_image, uint32_t *state)
411 {
412 struct radv_image_plane *plane = &image->planes[plane_id];
413 uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0;
414 uint64_t va = gpu_address + plane->offset;
415 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
416 uint64_t meta_va = 0;
417 if (chip_class >= GFX9) {
418 if (is_stencil)
419 va += plane->surface.u.gfx9.stencil_offset;
420 else
421 va += plane->surface.u.gfx9.surf_offset;
422 } else
423 va += base_level_info->offset;
424
425 state[0] = va >> 8;
426 if (chip_class >= GFX9 ||
427 base_level_info->mode == RADEON_SURF_MODE_2D)
428 state[0] |= plane->surface.tile_swizzle;
429 state[1] &= C_008F14_BASE_ADDRESS_HI;
430 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
431
432 if (chip_class >= GFX8) {
433 state[6] &= C_008F28_COMPRESSION_EN;
434 state[7] = 0;
435 if (!is_storage_image && radv_dcc_enabled(image, first_level)) {
436 meta_va = gpu_address + image->dcc_offset;
437 if (chip_class <= GFX8)
438 meta_va += base_level_info->dcc_offset;
439 } else if (!is_storage_image &&
440 radv_image_is_tc_compat_htile(image)) {
441 meta_va = gpu_address + image->htile_offset;
442 }
443
444 if (meta_va) {
445 state[6] |= S_008F28_COMPRESSION_EN(1);
446 state[7] = meta_va >> 8;
447 state[7] |= plane->surface.tile_swizzle;
448 }
449 }
450
451 if (chip_class >= GFX9) {
452 state[3] &= C_008F1C_SW_MODE;
453 state[4] &= C_008F20_PITCH;
454
455 if (is_stencil) {
456 state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.stencil.swizzle_mode);
457 state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.stencil.epitch);
458 } else {
459 state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.surf.swizzle_mode);
460 state[4] |= S_008F20_PITCH(plane->surface.u.gfx9.surf.epitch);
461 }
462
463 state[5] &= C_008F24_META_DATA_ADDRESS &
464 C_008F24_META_PIPE_ALIGNED &
465 C_008F24_META_RB_ALIGNED;
466 if (meta_va) {
467 struct gfx9_surf_meta_flags meta;
468
469 if (image->dcc_offset)
470 meta = plane->surface.u.gfx9.dcc;
471 else
472 meta = plane->surface.u.gfx9.htile;
473
474 state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
475 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
476 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
477 }
478 } else {
479 /* GFX6-GFX8 */
480 unsigned pitch = base_level_info->nblk_x * block_width;
481 unsigned index = si_tile_mode_index(plane, base_level, is_stencil);
482
483 state[3] &= C_008F1C_TILING_INDEX;
484 state[3] |= S_008F1C_TILING_INDEX(index);
485 state[4] &= C_008F20_PITCH;
486 state[4] |= S_008F20_PITCH(pitch - 1);
487 }
488 }
489
490 static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
491 unsigned nr_layers, unsigned nr_samples, bool is_storage_image, bool gfx9)
492 {
493 if (view_type == VK_IMAGE_VIEW_TYPE_CUBE || view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY)
494 return is_storage_image ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_CUBE;
495
496 /* GFX9 allocates 1D textures as 2D. */
497 if (gfx9 && image_type == VK_IMAGE_TYPE_1D)
498 image_type = VK_IMAGE_TYPE_2D;
499 switch (image_type) {
500 case VK_IMAGE_TYPE_1D:
501 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY : V_008F1C_SQ_RSRC_IMG_1D;
502 case VK_IMAGE_TYPE_2D:
503 if (nr_samples > 1)
504 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_MSAA;
505 else
506 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_2D;
507 case VK_IMAGE_TYPE_3D:
508 if (view_type == VK_IMAGE_VIEW_TYPE_3D)
509 return V_008F1C_SQ_RSRC_IMG_3D;
510 else
511 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
512 default:
513 unreachable("illegal image type");
514 }
515 }
516
517 static unsigned gfx9_border_color_swizzle(const enum vk_swizzle swizzle[4])
518 {
519 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
520
521 if (swizzle[3] == VK_SWIZZLE_X) {
522 /* For the pre-defined border color values (white, opaque
523 * black, transparent black), the only thing that matters is
524 * that the alpha channel winds up in the correct place
525 * (because the RGB channels are all the same) so either of
526 * these enumerations will work.
527 */
528 if (swizzle[2] == VK_SWIZZLE_Y)
529 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
530 else
531 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
532 } else if (swizzle[0] == VK_SWIZZLE_X) {
533 if (swizzle[1] == VK_SWIZZLE_Y)
534 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
535 else
536 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
537 } else if (swizzle[1] == VK_SWIZZLE_X) {
538 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
539 } else if (swizzle[2] == VK_SWIZZLE_X) {
540 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
541 }
542
543 return bc_swizzle;
544 }
545
546 /**
547 * Build the sampler view descriptor for a texture.
548 */
549 static void
550 si_make_texture_descriptor(struct radv_device *device,
551 struct radv_image *image,
552 bool is_storage_image,
553 VkImageViewType view_type,
554 VkFormat vk_format,
555 const VkComponentMapping *mapping,
556 unsigned first_level, unsigned last_level,
557 unsigned first_layer, unsigned last_layer,
558 unsigned width, unsigned height, unsigned depth,
559 uint32_t *state,
560 uint32_t *fmask_state)
561 {
562 const struct vk_format_description *desc;
563 enum vk_swizzle swizzle[4];
564 int first_non_void;
565 unsigned num_format, data_format, type;
566
567 desc = vk_format_description(vk_format);
568
569 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
570 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
571 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
572 } else {
573 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
574 }
575
576 first_non_void = vk_format_get_first_non_void_channel(vk_format);
577
578 num_format = radv_translate_tex_numformat(vk_format, desc, first_non_void);
579 if (num_format == ~0) {
580 num_format = 0;
581 }
582
583 data_format = radv_translate_tex_dataformat(vk_format, desc, first_non_void);
584 if (data_format == ~0) {
585 data_format = 0;
586 }
587
588 /* S8 with either Z16 or Z32 HTILE need a special format. */
589 if (device->physical_device->rad_info.chip_class >= GFX9 &&
590 vk_format == VK_FORMAT_S8_UINT &&
591 radv_image_is_tc_compat_htile(image)) {
592 if (image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT)
593 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
594 else if (image->vk_format == VK_FORMAT_D16_UNORM_S8_UINT)
595 data_format = V_008F14_IMG_DATA_FORMAT_S8_16;
596 }
597 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
598 is_storage_image, device->physical_device->rad_info.chip_class >= GFX9);
599 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
600 height = 1;
601 depth = image->info.array_size;
602 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
603 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
604 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
605 depth = image->info.array_size;
606 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
607 depth = image->info.array_size / 6;
608
609 state[0] = 0;
610 state[1] = (S_008F14_DATA_FORMAT(data_format) |
611 S_008F14_NUM_FORMAT(num_format));
612 state[2] = (S_008F18_WIDTH(width - 1) |
613 S_008F18_HEIGHT(height - 1) |
614 S_008F18_PERF_MOD(4));
615 state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
616 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
617 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
618 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
619 S_008F1C_BASE_LEVEL(image->info.samples > 1 ?
620 0 : first_level) |
621 S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
622 util_logbase2(image->info.samples) :
623 last_level) |
624 S_008F1C_TYPE(type));
625 state[4] = 0;
626 state[5] = S_008F24_BASE_ARRAY(first_layer);
627 state[6] = 0;
628 state[7] = 0;
629
630 if (device->physical_device->rad_info.chip_class >= GFX9) {
631 unsigned bc_swizzle = gfx9_border_color_swizzle(swizzle);
632
633 /* Depth is the last accessible layer on Gfx9.
634 * The hw doesn't need to know the total number of layers.
635 */
636 if (type == V_008F1C_SQ_RSRC_IMG_3D)
637 state[4] |= S_008F20_DEPTH(depth - 1);
638 else
639 state[4] |= S_008F20_DEPTH(last_layer);
640
641 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
642 state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ?
643 util_logbase2(image->info.samples) :
644 image->info.levels - 1);
645 } else {
646 state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
647 state[4] |= S_008F20_DEPTH(depth - 1);
648 state[5] |= S_008F24_LAST_ARRAY(last_layer);
649 }
650 if (image->dcc_offset) {
651 unsigned swap = radv_translate_colorswap(vk_format, FALSE);
652
653 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
654 } else {
655 /* The last dword is unused by hw. The shader uses it to clear
656 * bits in the first dword of sampler state.
657 */
658 if (device->physical_device->rad_info.chip_class <= GFX7 && image->info.samples <= 1) {
659 if (first_level == last_level)
660 state[7] = C_008F30_MAX_ANISO_RATIO;
661 else
662 state[7] = 0xffffffff;
663 }
664 }
665
666 /* Initialize the sampler view for FMASK. */
667 if (radv_image_has_fmask(image)) {
668 uint32_t fmask_format, num_format;
669 uint64_t gpu_address = radv_buffer_get_va(image->bo);
670 uint64_t va;
671
672 assert(image->plane_count == 1);
673
674 va = gpu_address + image->offset + image->fmask.offset;
675
676 if (device->physical_device->rad_info.chip_class >= GFX9) {
677 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
678 switch (image->info.samples) {
679 case 2:
680 num_format = V_008F14_IMG_FMASK_8_2_2;
681 break;
682 case 4:
683 num_format = V_008F14_IMG_FMASK_8_4_4;
684 break;
685 case 8:
686 num_format = V_008F14_IMG_FMASK_32_8_8;
687 break;
688 default:
689 unreachable("invalid nr_samples");
690 }
691 } else {
692 switch (image->info.samples) {
693 case 2:
694 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
695 break;
696 case 4:
697 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
698 break;
699 case 8:
700 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
701 break;
702 default:
703 assert(0);
704 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
705 }
706 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
707 }
708
709 fmask_state[0] = va >> 8;
710 fmask_state[0] |= image->fmask.tile_swizzle;
711 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
712 S_008F14_DATA_FORMAT(fmask_format) |
713 S_008F14_NUM_FORMAT(num_format);
714 fmask_state[2] = S_008F18_WIDTH(width - 1) |
715 S_008F18_HEIGHT(height - 1);
716 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
717 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
718 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
719 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
720 S_008F1C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
721 fmask_state[4] = 0;
722 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
723 fmask_state[6] = 0;
724 fmask_state[7] = 0;
725
726 if (device->physical_device->rad_info.chip_class >= GFX9) {
727 fmask_state[3] |= S_008F1C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode);
728 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
729 S_008F20_PITCH(image->planes[0].surface.u.gfx9.fmask.epitch);
730 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->planes[0].surface.u.gfx9.cmask.pipe_aligned) |
731 S_008F24_META_RB_ALIGNED(image->planes[0].surface.u.gfx9.cmask.rb_aligned);
732 } else {
733 fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
734 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
735 S_008F20_PITCH(image->fmask.pitch_in_pixels - 1);
736 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
737 }
738 } else if (fmask_state)
739 memset(fmask_state, 0, 8 * 4);
740 }
741
742 static void
743 radv_query_opaque_metadata(struct radv_device *device,
744 struct radv_image *image,
745 struct radeon_bo_metadata *md)
746 {
747 static const VkComponentMapping fixedmapping;
748 uint32_t desc[8], i;
749
750 assert(image->plane_count == 1);
751
752 /* Metadata image format format version 1:
753 * [0] = 1 (metadata format identifier)
754 * [1] = (VENDOR_ID << 16) | PCI_ID
755 * [2:9] = image descriptor for the whole resource
756 * [2] is always 0, because the base address is cleared
757 * [9] is the DCC offset bits [39:8] from the beginning of
758 * the buffer
759 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
760 */
761 md->metadata[0] = 1; /* metadata image format version 1 */
762
763 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
764 md->metadata[1] = si_get_bo_metadata_word1(device);
765
766
767 si_make_texture_descriptor(device, image, false,
768 (VkImageViewType)image->type, image->vk_format,
769 &fixedmapping, 0, image->info.levels - 1, 0,
770 image->info.array_size - 1,
771 image->info.width, image->info.height,
772 image->info.depth,
773 desc, NULL);
774
775 si_set_mutable_tex_desc_fields(device, image, &image->planes[0].surface.u.legacy.level[0], 0, 0, 0,
776 image->planes[0].surface.blk_w, false, false, desc);
777
778 /* Clear the base address and set the relative DCC offset. */
779 desc[0] = 0;
780 desc[1] &= C_008F14_BASE_ADDRESS_HI;
781 desc[7] = image->dcc_offset >> 8;
782
783 /* Dwords [2:9] contain the image descriptor. */
784 memcpy(&md->metadata[2], desc, sizeof(desc));
785
786 /* Dwords [10:..] contain the mipmap level offsets. */
787 if (device->physical_device->rad_info.chip_class <= GFX8) {
788 for (i = 0; i <= image->info.levels - 1; i++)
789 md->metadata[10+i] = image->planes[0].surface.u.legacy.level[i].offset >> 8;
790 md->size_metadata = (11 + image->info.levels - 1) * 4;
791 }
792 }
793
794 void
795 radv_init_metadata(struct radv_device *device,
796 struct radv_image *image,
797 struct radeon_bo_metadata *metadata)
798 {
799 struct radeon_surf *surface = &image->planes[0].surface;
800
801 memset(metadata, 0, sizeof(*metadata));
802
803 if (device->physical_device->rad_info.chip_class >= GFX9) {
804 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
805 } else {
806 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
807 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
808 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
809 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
810 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
811 metadata->u.legacy.bankw = surface->u.legacy.bankw;
812 metadata->u.legacy.bankh = surface->u.legacy.bankh;
813 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
814 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
815 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
816 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
817 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
818 }
819 radv_query_opaque_metadata(device, image, metadata);
820 }
821
822 void
823 radv_image_override_offset_stride(struct radv_device *device,
824 struct radv_image *image,
825 uint64_t offset, uint32_t stride)
826 {
827 struct radeon_surf *surface = &image->planes[0].surface;
828 unsigned bpe = vk_format_get_blocksizebits(image->vk_format) / 8;
829
830 if (device->physical_device->rad_info.chip_class >= GFX9) {
831 if (stride) {
832 surface->u.gfx9.surf_pitch = stride;
833 surface->u.gfx9.surf_slice_size =
834 (uint64_t)stride * surface->u.gfx9.surf_height * bpe;
835 }
836 surface->u.gfx9.surf_offset = offset;
837 } else {
838 surface->u.legacy.level[0].nblk_x = stride;
839 surface->u.legacy.level[0].slice_size_dw =
840 ((uint64_t)stride * surface->u.legacy.level[0].nblk_y * bpe) / 4;
841
842 if (offset) {
843 for (unsigned i = 0; i < ARRAY_SIZE(surface->u.legacy.level); ++i)
844 surface->u.legacy.level[i].offset += offset;
845 }
846
847 }
848 }
849
850 /* The number of samples can be specified independently of the texture. */
851 static void
852 radv_image_get_fmask_info(struct radv_device *device,
853 struct radv_image *image,
854 unsigned nr_samples,
855 struct radv_fmask_info *out)
856 {
857 if (device->physical_device->rad_info.chip_class >= GFX9) {
858 out->alignment = image->planes[0].surface.fmask_alignment;
859 out->size = image->planes[0].surface.fmask_size;
860 out->tile_swizzle = image->planes[0].surface.fmask_tile_swizzle;
861 return;
862 }
863
864 out->slice_tile_max = image->planes[0].surface.u.legacy.fmask.slice_tile_max;
865 out->tile_mode_index = image->planes[0].surface.u.legacy.fmask.tiling_index;
866 out->pitch_in_pixels = image->planes[0].surface.u.legacy.fmask.pitch_in_pixels;
867 out->bank_height = image->planes[0].surface.u.legacy.fmask.bankh;
868 out->tile_swizzle = image->planes[0].surface.fmask_tile_swizzle;
869 out->alignment = image->planes[0].surface.fmask_alignment;
870 out->size = image->planes[0].surface.fmask_size;
871
872 assert(!out->tile_swizzle || !image->shareable);
873 }
874
875 static void
876 radv_image_alloc_fmask(struct radv_device *device,
877 struct radv_image *image)
878 {
879 radv_image_get_fmask_info(device, image, image->info.samples, &image->fmask);
880
881 image->fmask.offset = align64(image->size, image->fmask.alignment);
882 image->size = image->fmask.offset + image->fmask.size;
883 image->alignment = MAX2(image->alignment, image->fmask.alignment);
884 }
885
886 static void
887 radv_image_get_cmask_info(struct radv_device *device,
888 struct radv_image *image,
889 struct radv_cmask_info *out)
890 {
891 assert(image->plane_count == 1);
892
893 if (device->physical_device->rad_info.chip_class >= GFX9) {
894 out->alignment = image->planes[0].surface.cmask_alignment;
895 out->size = image->planes[0].surface.cmask_size;
896 return;
897 }
898
899 out->slice_tile_max = image->planes[0].surface.u.legacy.cmask_slice_tile_max;
900 out->alignment = image->planes[0].surface.cmask_alignment;
901 out->size = image->planes[0].surface.cmask_size;
902 }
903
904 static void
905 radv_image_alloc_cmask(struct radv_device *device,
906 struct radv_image *image)
907 {
908 uint32_t clear_value_size = 0;
909 radv_image_get_cmask_info(device, image, &image->cmask);
910
911 image->cmask.offset = align64(image->size, image->cmask.alignment);
912 /* + 8 for storing the clear values */
913 if (!image->clear_value_offset) {
914 image->clear_value_offset = image->cmask.offset + image->cmask.size;
915 clear_value_size = 8;
916 }
917 image->size = image->cmask.offset + image->cmask.size + clear_value_size;
918 image->alignment = MAX2(image->alignment, image->cmask.alignment);
919 }
920
921 static void
922 radv_image_alloc_dcc(struct radv_image *image)
923 {
924 assert(image->plane_count == 1);
925
926 image->dcc_offset = align64(image->size, image->planes[0].surface.dcc_alignment);
927 /* + 24 for storing the clear values + fce pred + dcc pred for each mip */
928 image->clear_value_offset = image->dcc_offset + image->planes[0].surface.dcc_size;
929 image->fce_pred_offset = image->clear_value_offset + 8 * image->info.levels;
930 image->dcc_pred_offset = image->clear_value_offset + 16 * image->info.levels;
931 image->size = image->dcc_offset + image->planes[0].surface.dcc_size + 24 * image->info.levels;
932 image->alignment = MAX2(image->alignment, image->planes[0].surface.dcc_alignment);
933 }
934
935 static void
936 radv_image_alloc_htile(struct radv_image *image)
937 {
938 image->htile_offset = align64(image->size, image->planes[0].surface.htile_alignment);
939
940 /* + 8 for storing the clear values */
941 image->clear_value_offset = image->htile_offset + image->planes[0].surface.htile_size;
942 image->size = image->clear_value_offset + 8;
943 if (radv_image_is_tc_compat_htile(image)) {
944 /* Metadata for the TC-compatible HTILE hardware bug which
945 * have to be fixed by updating ZRANGE_PRECISION when doing
946 * fast depth clears to 0.0f.
947 */
948 image->tc_compat_zrange_offset = image->clear_value_offset + 8;
949 image->size = image->clear_value_offset + 16;
950 }
951 image->alignment = align64(image->alignment, image->planes[0].surface.htile_alignment);
952 }
953
954 static inline bool
955 radv_image_can_enable_dcc_or_cmask(struct radv_image *image)
956 {
957 if (image->info.samples <= 1 &&
958 image->info.width * image->info.height <= 512 * 512) {
959 /* Do not enable CMASK or DCC for small surfaces where the cost
960 * of the eliminate pass can be higher than the benefit of fast
961 * clear. RadeonSI does this, but the image threshold is
962 * different.
963 */
964 return false;
965 }
966
967 return image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT &&
968 (image->exclusive || image->queue_family_mask == 1);
969 }
970
971 static inline bool
972 radv_image_can_enable_dcc(struct radv_image *image)
973 {
974 return radv_image_can_enable_dcc_or_cmask(image) &&
975 radv_image_has_dcc(image);
976 }
977
978 static inline bool
979 radv_image_can_enable_cmask(struct radv_image *image)
980 {
981 if (image->planes[0].surface.bpe > 8 && image->info.samples == 1) {
982 /* Do not enable CMASK for non-MSAA images (fast color clear)
983 * because 128 bit formats are not supported, but FMASK might
984 * still be used.
985 */
986 return false;
987 }
988
989 return radv_image_can_enable_dcc_or_cmask(image) &&
990 image->info.levels == 1 &&
991 image->info.depth == 1 &&
992 !image->planes[0].surface.is_linear;
993 }
994
995 static inline bool
996 radv_image_can_enable_fmask(struct radv_image *image)
997 {
998 return image->info.samples > 1 && vk_format_is_color(image->vk_format);
999 }
1000
1001 static inline bool
1002 radv_image_can_enable_htile(struct radv_image *image)
1003 {
1004 return radv_image_has_htile(image) &&
1005 image->info.levels == 1 &&
1006 image->info.width * image->info.height >= 8 * 8;
1007 }
1008
1009 static void radv_image_disable_dcc(struct radv_image *image)
1010 {
1011 for (unsigned i = 0; i < image->plane_count; ++i)
1012 image->planes[i].surface.dcc_size = 0;
1013 }
1014
1015 static void radv_image_disable_htile(struct radv_image *image)
1016 {
1017 for (unsigned i = 0; i < image->plane_count; ++i)
1018 image->planes[i].surface.htile_size = 0;
1019 }
1020
1021 VkResult
1022 radv_image_create(VkDevice _device,
1023 const struct radv_image_create_info *create_info,
1024 const VkAllocationCallbacks* alloc,
1025 VkImage *pImage)
1026 {
1027 RADV_FROM_HANDLE(radv_device, device, _device);
1028 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
1029 struct radv_image *image = NULL;
1030 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
1031
1032 const unsigned plane_count = vk_format_get_plane_count(pCreateInfo->format);
1033 const size_t image_struct_size = sizeof(*image) + sizeof(struct radv_image_plane) * plane_count;
1034
1035 radv_assert(pCreateInfo->mipLevels > 0);
1036 radv_assert(pCreateInfo->arrayLayers > 0);
1037 radv_assert(pCreateInfo->samples > 0);
1038 radv_assert(pCreateInfo->extent.width > 0);
1039 radv_assert(pCreateInfo->extent.height > 0);
1040 radv_assert(pCreateInfo->extent.depth > 0);
1041
1042 image = vk_zalloc2(&device->alloc, alloc, image_struct_size, 8,
1043 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1044 if (!image)
1045 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1046
1047 image->type = pCreateInfo->imageType;
1048 image->info.width = pCreateInfo->extent.width;
1049 image->info.height = pCreateInfo->extent.height;
1050 image->info.depth = pCreateInfo->extent.depth;
1051 image->info.samples = pCreateInfo->samples;
1052 image->info.storage_samples = pCreateInfo->samples;
1053 image->info.array_size = pCreateInfo->arrayLayers;
1054 image->info.levels = pCreateInfo->mipLevels;
1055 image->info.num_channels = vk_format_get_nr_components(pCreateInfo->format);
1056
1057 image->vk_format = pCreateInfo->format;
1058 image->tiling = pCreateInfo->tiling;
1059 image->usage = pCreateInfo->usage;
1060 image->flags = pCreateInfo->flags;
1061
1062 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
1063 if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
1064 for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
1065 if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL)
1066 image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1067 else
1068 image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
1069 }
1070
1071 image->shareable = vk_find_struct_const(pCreateInfo->pNext,
1072 EXTERNAL_MEMORY_IMAGE_CREATE_INFO) != NULL;
1073 if (!vk_format_is_depth_or_stencil(pCreateInfo->format) &&
1074 !radv_surface_has_scanout(device, create_info) && !image->shareable) {
1075 image->info.surf_index = &device->image_mrt_offset_counter;
1076 }
1077
1078 image->plane_count = plane_count;
1079 image->size = 0;
1080 image->alignment = 1;
1081 for (unsigned plane = 0; plane < plane_count; ++plane) {
1082 struct ac_surf_info info = image->info;
1083 radv_init_surface(device, image, &image->planes[plane].surface, plane, create_info);
1084
1085 if (plane) {
1086 const struct vk_format_description *desc = vk_format_description(pCreateInfo->format);
1087 assert(info.width % desc->width_divisor == 0);
1088 assert(info.height % desc->height_divisor == 0);
1089
1090 info.width /= desc->width_divisor;
1091 info.height /= desc->height_divisor;
1092 }
1093
1094 device->ws->surface_init(device->ws, &info, &image->planes[plane].surface);
1095
1096 image->planes[plane].offset = align(image->size, image->planes[plane].surface.surf_alignment);
1097 image->size = image->planes[plane].offset + image->planes[plane].surface.surf_size;
1098 image->alignment = image->planes[plane].surface.surf_alignment;
1099
1100 image->planes[plane].format = vk_format_get_plane_format(image->vk_format, plane);
1101 }
1102
1103 if (!create_info->no_metadata_planes) {
1104 /* Try to enable DCC first. */
1105 if (radv_image_can_enable_dcc(image)) {
1106 radv_image_alloc_dcc(image);
1107 if (image->info.samples > 1) {
1108 /* CMASK should be enabled because DCC fast
1109 * clear with MSAA needs it.
1110 */
1111 assert(radv_image_can_enable_cmask(image));
1112 radv_image_alloc_cmask(device, image);
1113 }
1114 } else {
1115 /* When DCC cannot be enabled, try CMASK. */
1116 radv_image_disable_dcc(image);
1117 if (radv_image_can_enable_cmask(image)) {
1118 radv_image_alloc_cmask(device, image);
1119 }
1120 }
1121
1122 /* Try to enable FMASK for multisampled images. */
1123 if (radv_image_can_enable_fmask(image)) {
1124 radv_image_alloc_fmask(device, image);
1125 } else {
1126 /* Otherwise, try to enable HTILE for depth surfaces. */
1127 if (radv_image_can_enable_htile(image) &&
1128 !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
1129 image->tc_compatible_htile = image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1130 radv_image_alloc_htile(image);
1131 } else {
1132 radv_image_disable_htile(image);
1133 }
1134 }
1135 } else {
1136 radv_image_disable_dcc(image);
1137 radv_image_disable_htile(image);
1138 }
1139
1140 if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
1141 image->alignment = MAX2(image->alignment, 4096);
1142 image->size = align64(image->size, image->alignment);
1143 image->offset = 0;
1144
1145 image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
1146 0, RADEON_FLAG_VIRTUAL, RADV_BO_PRIORITY_VIRTUAL);
1147 if (!image->bo) {
1148 vk_free2(&device->alloc, alloc, image);
1149 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
1150 }
1151 }
1152
1153 *pImage = radv_image_to_handle(image);
1154
1155 return VK_SUCCESS;
1156 }
1157
1158 static void
1159 radv_image_view_make_descriptor(struct radv_image_view *iview,
1160 struct radv_device *device,
1161 VkFormat vk_format,
1162 const VkComponentMapping *components,
1163 bool is_storage_image, unsigned plane_id,
1164 unsigned descriptor_plane_id)
1165 {
1166 struct radv_image *image = iview->image;
1167 struct radv_image_plane *plane = &image->planes[plane_id];
1168 const struct vk_format_description *format_desc = vk_format_description(image->vk_format);
1169 bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
1170 uint32_t blk_w;
1171 union radv_descriptor *descriptor;
1172 uint32_t hw_level = 0;
1173
1174 if (is_storage_image) {
1175 descriptor = &iview->storage_descriptor;
1176 } else {
1177 descriptor = &iview->descriptor;
1178 }
1179
1180 assert(vk_format_get_plane_count(vk_format) == 1);
1181 assert(plane->surface.blk_w % vk_format_get_blockwidth(plane->format) == 0);
1182 blk_w = plane->surface.blk_w / vk_format_get_blockwidth(plane->format) * vk_format_get_blockwidth(vk_format);
1183
1184 if (device->physical_device->rad_info.chip_class >= GFX9)
1185 hw_level = iview->base_mip;
1186 si_make_texture_descriptor(device, image, is_storage_image,
1187 iview->type,
1188 vk_format,
1189 components,
1190 hw_level, hw_level + iview->level_count - 1,
1191 iview->base_layer,
1192 iview->base_layer + iview->layer_count - 1,
1193 iview->extent.width / (plane_id ? format_desc->width_divisor : 1),
1194 iview->extent.height / (plane_id ? format_desc->height_divisor : 1),
1195 iview->extent.depth,
1196 descriptor->plane_descriptors[descriptor_plane_id],
1197 descriptor_plane_id ? NULL : descriptor->fmask_descriptor);
1198
1199 const struct legacy_surf_level *base_level_info = NULL;
1200 if (device->physical_device->rad_info.chip_class <= GFX9) {
1201 if (is_stencil)
1202 base_level_info = &plane->surface.u.legacy.stencil_level[iview->base_mip];
1203 else
1204 base_level_info = &plane->surface.u.legacy.level[iview->base_mip];
1205 }
1206 si_set_mutable_tex_desc_fields(device, image,
1207 base_level_info,
1208 plane_id,
1209 iview->base_mip,
1210 iview->base_mip,
1211 blk_w, is_stencil, is_storage_image, descriptor->plane_descriptors[descriptor_plane_id]);
1212 }
1213
1214 static unsigned
1215 radv_plane_from_aspect(VkImageAspectFlags mask)
1216 {
1217 switch(mask) {
1218 case VK_IMAGE_ASPECT_PLANE_1_BIT:
1219 return 1;
1220 case VK_IMAGE_ASPECT_PLANE_2_BIT:
1221 return 2;
1222 default:
1223 return 0;
1224 }
1225 }
1226
1227 VkFormat
1228 radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask)
1229 {
1230 switch(mask) {
1231 case VK_IMAGE_ASPECT_PLANE_0_BIT:
1232 return image->planes[0].format;
1233 case VK_IMAGE_ASPECT_PLANE_1_BIT:
1234 return image->planes[1].format;
1235 case VK_IMAGE_ASPECT_PLANE_2_BIT:
1236 return image->planes[2].format;
1237 case VK_IMAGE_ASPECT_STENCIL_BIT:
1238 return vk_format_stencil_only(image->vk_format);
1239 case VK_IMAGE_ASPECT_DEPTH_BIT:
1240 return vk_format_depth_only(image->vk_format);
1241 case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
1242 return vk_format_depth_only(image->vk_format);
1243 default:
1244 return image->vk_format;
1245 }
1246 }
1247
1248 void
1249 radv_image_view_init(struct radv_image_view *iview,
1250 struct radv_device *device,
1251 const VkImageViewCreateInfo* pCreateInfo)
1252 {
1253 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
1254 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
1255
1256 switch (image->type) {
1257 case VK_IMAGE_TYPE_1D:
1258 case VK_IMAGE_TYPE_2D:
1259 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size);
1260 break;
1261 case VK_IMAGE_TYPE_3D:
1262 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
1263 <= radv_minify(image->info.depth, range->baseMipLevel));
1264 break;
1265 default:
1266 unreachable("bad VkImageType");
1267 }
1268 iview->image = image;
1269 iview->bo = image->bo;
1270 iview->type = pCreateInfo->viewType;
1271 iview->plane_id = radv_plane_from_aspect(pCreateInfo->subresourceRange.aspectMask);
1272 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
1273 iview->multiple_planes = vk_format_get_plane_count(image->vk_format) > 1 && iview->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT;
1274 iview->vk_format = pCreateInfo->format;
1275
1276 if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
1277 iview->vk_format = vk_format_stencil_only(iview->vk_format);
1278 } else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
1279 iview->vk_format = vk_format_depth_only(iview->vk_format);
1280 }
1281
1282 if (device->physical_device->rad_info.chip_class >= GFX9) {
1283 iview->extent = (VkExtent3D) {
1284 .width = image->info.width,
1285 .height = image->info.height,
1286 .depth = image->info.depth,
1287 };
1288 } else {
1289 iview->extent = (VkExtent3D) {
1290 .width = radv_minify(image->info.width , range->baseMipLevel),
1291 .height = radv_minify(image->info.height, range->baseMipLevel),
1292 .depth = radv_minify(image->info.depth , range->baseMipLevel),
1293 };
1294 }
1295
1296 if (iview->vk_format != image->planes[iview->plane_id].format) {
1297 unsigned view_bw = vk_format_get_blockwidth(iview->vk_format);
1298 unsigned view_bh = vk_format_get_blockheight(iview->vk_format);
1299 unsigned img_bw = vk_format_get_blockwidth(image->vk_format);
1300 unsigned img_bh = vk_format_get_blockheight(image->vk_format);
1301
1302 iview->extent.width = round_up_u32(iview->extent.width * view_bw, img_bw);
1303 iview->extent.height = round_up_u32(iview->extent.height * view_bh, img_bh);
1304
1305 /* Comment ported from amdvlk -
1306 * If we have the following image:
1307 * Uncompressed pixels Compressed block sizes (4x4)
1308 * mip0: 22 x 22 6 x 6
1309 * mip1: 11 x 11 3 x 3
1310 * mip2: 5 x 5 2 x 2
1311 * mip3: 2 x 2 1 x 1
1312 * mip4: 1 x 1 1 x 1
1313 *
1314 * On GFX9 the descriptor is always programmed with the WIDTH and HEIGHT of the base level and the HW is
1315 * calculating the degradation of the block sizes down the mip-chain as follows (straight-up
1316 * divide-by-two integer math):
1317 * mip0: 6x6
1318 * mip1: 3x3
1319 * mip2: 1x1
1320 * mip3: 1x1
1321 *
1322 * This means that mip2 will be missing texels.
1323 *
1324 * Fix this by calculating the base mip's width and height, then convert that, and round it
1325 * back up to get the level 0 size.
1326 * Clamp the converted size between the original values, and next power of two, which
1327 * means we don't oversize the image.
1328 */
1329 if (device->physical_device->rad_info.chip_class >= GFX9 &&
1330 vk_format_is_compressed(image->vk_format) &&
1331 !vk_format_is_compressed(iview->vk_format)) {
1332 unsigned lvl_width = radv_minify(image->info.width , range->baseMipLevel);
1333 unsigned lvl_height = radv_minify(image->info.height, range->baseMipLevel);
1334
1335 lvl_width = round_up_u32(lvl_width * view_bw, img_bw);
1336 lvl_height = round_up_u32(lvl_height * view_bh, img_bh);
1337
1338 lvl_width <<= range->baseMipLevel;
1339 lvl_height <<= range->baseMipLevel;
1340
1341 iview->extent.width = CLAMP(lvl_width, iview->extent.width, iview->image->planes[0].surface.u.gfx9.surf_pitch);
1342 iview->extent.height = CLAMP(lvl_height, iview->extent.height, iview->image->planes[0].surface.u.gfx9.surf_height);
1343 }
1344 }
1345
1346 iview->base_layer = range->baseArrayLayer;
1347 iview->layer_count = radv_get_layerCount(image, range);
1348 iview->base_mip = range->baseMipLevel;
1349 iview->level_count = radv_get_levelCount(image, range);
1350
1351 for (unsigned i = 0; i < (iview->multiple_planes ? vk_format_get_plane_count(image->vk_format) : 1); ++i) {
1352 VkFormat format = vk_format_get_plane_format(iview->vk_format, i);
1353 radv_image_view_make_descriptor(iview, device, format, &pCreateInfo->components, false, iview->plane_id + i, i);
1354 radv_image_view_make_descriptor(iview, device, format, &pCreateInfo->components, true, iview->plane_id + i, i);
1355 }
1356 }
1357
1358 bool radv_layout_has_htile(const struct radv_image *image,
1359 VkImageLayout layout,
1360 unsigned queue_mask)
1361 {
1362 if (radv_image_is_tc_compat_htile(image))
1363 return layout != VK_IMAGE_LAYOUT_GENERAL;
1364
1365 return radv_image_has_htile(image) &&
1366 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1367 (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1368 queue_mask == (1u << RADV_QUEUE_GENERAL)));
1369 }
1370
1371 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1372 VkImageLayout layout,
1373 unsigned queue_mask)
1374 {
1375 if (radv_image_is_tc_compat_htile(image))
1376 return layout != VK_IMAGE_LAYOUT_GENERAL;
1377
1378 return radv_image_has_htile(image) &&
1379 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1380 (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1381 queue_mask == (1u << RADV_QUEUE_GENERAL)));
1382 }
1383
1384 bool radv_layout_can_fast_clear(const struct radv_image *image,
1385 VkImageLayout layout,
1386 unsigned queue_mask)
1387 {
1388 return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
1389 }
1390
1391 bool radv_layout_dcc_compressed(const struct radv_image *image,
1392 VkImageLayout layout,
1393 unsigned queue_mask)
1394 {
1395 /* Don't compress compute transfer dst, as image stores are not supported. */
1396 if (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1397 (queue_mask & (1u << RADV_QUEUE_COMPUTE)))
1398 return false;
1399
1400 return radv_image_has_dcc(image) && layout != VK_IMAGE_LAYOUT_GENERAL;
1401 }
1402
1403
1404 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
1405 {
1406 if (!image->exclusive)
1407 return image->queue_family_mask;
1408 if (family == VK_QUEUE_FAMILY_EXTERNAL)
1409 return (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1410 if (family == VK_QUEUE_FAMILY_IGNORED)
1411 return 1u << queue_family;
1412 return 1u << family;
1413 }
1414
1415 VkResult
1416 radv_CreateImage(VkDevice device,
1417 const VkImageCreateInfo *pCreateInfo,
1418 const VkAllocationCallbacks *pAllocator,
1419 VkImage *pImage)
1420 {
1421 #ifdef ANDROID
1422 const VkNativeBufferANDROID *gralloc_info =
1423 vk_find_struct_const(pCreateInfo->pNext, NATIVE_BUFFER_ANDROID);
1424
1425 if (gralloc_info)
1426 return radv_image_from_gralloc(device, pCreateInfo, gralloc_info,
1427 pAllocator, pImage);
1428 #endif
1429
1430 const struct wsi_image_create_info *wsi_info =
1431 vk_find_struct_const(pCreateInfo->pNext, WSI_IMAGE_CREATE_INFO_MESA);
1432 bool scanout = wsi_info && wsi_info->scanout;
1433
1434 return radv_image_create(device,
1435 &(struct radv_image_create_info) {
1436 .vk_info = pCreateInfo,
1437 .scanout = scanout,
1438 },
1439 pAllocator,
1440 pImage);
1441 }
1442
1443 void
1444 radv_DestroyImage(VkDevice _device, VkImage _image,
1445 const VkAllocationCallbacks *pAllocator)
1446 {
1447 RADV_FROM_HANDLE(radv_device, device, _device);
1448 RADV_FROM_HANDLE(radv_image, image, _image);
1449
1450 if (!image)
1451 return;
1452
1453 if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
1454 device->ws->buffer_destroy(image->bo);
1455
1456 if (image->owned_memory != VK_NULL_HANDLE)
1457 radv_FreeMemory(_device, image->owned_memory, pAllocator);
1458
1459 vk_free2(&device->alloc, pAllocator, image);
1460 }
1461
1462 void radv_GetImageSubresourceLayout(
1463 VkDevice _device,
1464 VkImage _image,
1465 const VkImageSubresource* pSubresource,
1466 VkSubresourceLayout* pLayout)
1467 {
1468 RADV_FROM_HANDLE(radv_image, image, _image);
1469 RADV_FROM_HANDLE(radv_device, device, _device);
1470 int level = pSubresource->mipLevel;
1471 int layer = pSubresource->arrayLayer;
1472
1473 unsigned plane_id = radv_plane_from_aspect(pSubresource->aspectMask);
1474
1475 struct radv_image_plane *plane = &image->planes[plane_id];
1476 struct radeon_surf *surface = &plane->surface;
1477
1478 if (device->physical_device->rad_info.chip_class >= GFX9) {
1479 pLayout->offset = plane->offset + surface->u.gfx9.offset[level] + surface->u.gfx9.surf_slice_size * layer;
1480 if (image->vk_format == VK_FORMAT_R32G32B32_UINT ||
1481 image->vk_format == VK_FORMAT_R32G32B32_SINT ||
1482 image->vk_format == VK_FORMAT_R32G32B32_SFLOAT) {
1483 /* Adjust the number of bytes between each row because
1484 * the pitch is actually the number of components per
1485 * row.
1486 */
1487 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe / 3;
1488 } else {
1489 assert(util_is_power_of_two_nonzero(surface->bpe));
1490 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe;
1491 }
1492
1493 pLayout->arrayPitch = surface->u.gfx9.surf_slice_size;
1494 pLayout->depthPitch = surface->u.gfx9.surf_slice_size;
1495 pLayout->size = surface->u.gfx9.surf_slice_size;
1496 if (image->type == VK_IMAGE_TYPE_3D)
1497 pLayout->size *= u_minify(image->info.depth, level);
1498 } else {
1499 pLayout->offset = plane->offset + surface->u.legacy.level[level].offset + (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4 * layer;
1500 pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
1501 pLayout->arrayPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1502 pLayout->depthPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1503 pLayout->size = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1504 if (image->type == VK_IMAGE_TYPE_3D)
1505 pLayout->size *= u_minify(image->info.depth, level);
1506 }
1507 }
1508
1509
1510 VkResult
1511 radv_CreateImageView(VkDevice _device,
1512 const VkImageViewCreateInfo *pCreateInfo,
1513 const VkAllocationCallbacks *pAllocator,
1514 VkImageView *pView)
1515 {
1516 RADV_FROM_HANDLE(radv_device, device, _device);
1517 struct radv_image_view *view;
1518
1519 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1520 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1521 if (view == NULL)
1522 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1523
1524 radv_image_view_init(view, device, pCreateInfo);
1525
1526 *pView = radv_image_view_to_handle(view);
1527
1528 return VK_SUCCESS;
1529 }
1530
1531 void
1532 radv_DestroyImageView(VkDevice _device, VkImageView _iview,
1533 const VkAllocationCallbacks *pAllocator)
1534 {
1535 RADV_FROM_HANDLE(radv_device, device, _device);
1536 RADV_FROM_HANDLE(radv_image_view, iview, _iview);
1537
1538 if (!iview)
1539 return;
1540 vk_free2(&device->alloc, pAllocator, iview);
1541 }
1542
1543 void radv_buffer_view_init(struct radv_buffer_view *view,
1544 struct radv_device *device,
1545 const VkBufferViewCreateInfo* pCreateInfo)
1546 {
1547 RADV_FROM_HANDLE(radv_buffer, buffer, pCreateInfo->buffer);
1548
1549 view->bo = buffer->bo;
1550 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
1551 buffer->size - pCreateInfo->offset : pCreateInfo->range;
1552 view->vk_format = pCreateInfo->format;
1553
1554 radv_make_buffer_descriptor(device, buffer, view->vk_format,
1555 pCreateInfo->offset, view->range, view->state);
1556 }
1557
1558 VkResult
1559 radv_CreateBufferView(VkDevice _device,
1560 const VkBufferViewCreateInfo *pCreateInfo,
1561 const VkAllocationCallbacks *pAllocator,
1562 VkBufferView *pView)
1563 {
1564 RADV_FROM_HANDLE(radv_device, device, _device);
1565 struct radv_buffer_view *view;
1566
1567 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1568 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1569 if (!view)
1570 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1571
1572 radv_buffer_view_init(view, device, pCreateInfo);
1573
1574 *pView = radv_buffer_view_to_handle(view);
1575
1576 return VK_SUCCESS;
1577 }
1578
1579 void
1580 radv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
1581 const VkAllocationCallbacks *pAllocator)
1582 {
1583 RADV_FROM_HANDLE(radv_device, device, _device);
1584 RADV_FROM_HANDLE(radv_buffer_view, view, bufferView);
1585
1586 if (!view)
1587 return;
1588
1589 vk_free2(&device->alloc, pAllocator, view);
1590 }