2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "vk_format.h"
32 #include "radv_radeon_winsys.h"
34 #include "util/debug.h"
35 #include "util/u_atomic.h"
38 radv_choose_tiling(struct radv_device
*device
,
39 const struct radv_image_create_info
*create_info
)
41 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
43 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
) {
44 assert(pCreateInfo
->samples
<= 1);
45 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
48 if (!vk_format_is_compressed(pCreateInfo
->format
) &&
49 !vk_format_is_depth_or_stencil(pCreateInfo
->format
)
50 && device
->physical_device
->rad_info
.chip_class
<= GFX8
) {
51 /* this causes hangs in some VK CTS tests on GFX9. */
52 /* Textures with a very small height are recommended to be linear. */
53 if (pCreateInfo
->imageType
== VK_IMAGE_TYPE_1D
||
54 /* Only very thin and long 2D textures should benefit from
56 (pCreateInfo
->extent
.width
> 8 && pCreateInfo
->extent
.height
<= 2))
57 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
60 /* MSAA resources must be 2D tiled. */
61 if (pCreateInfo
->samples
> 1)
62 return RADEON_SURF_MODE_2D
;
64 return RADEON_SURF_MODE_2D
;
68 radv_use_tc_compat_htile_for_image(struct radv_device
*device
,
69 const VkImageCreateInfo
*pCreateInfo
)
71 /* TC-compat HTILE is only available for GFX8+. */
72 if (device
->physical_device
->rad_info
.chip_class
< GFX8
)
75 if ((pCreateInfo
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
) ||
76 (pCreateInfo
->flags
& VK_IMAGE_CREATE_EXTENDED_USAGE_BIT
))
79 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
)
82 if (pCreateInfo
->mipLevels
> 1)
85 /* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
86 * tests - disable for now */
87 if (pCreateInfo
->samples
>= 2 &&
88 pCreateInfo
->format
== VK_FORMAT_D32_SFLOAT_S8_UINT
)
91 /* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only
92 * supports 32-bit. Though, it's possible to enable TC-compat for
93 * 16-bit depth surfaces if no Z planes are compressed.
95 if (pCreateInfo
->format
!= VK_FORMAT_D32_SFLOAT_S8_UINT
&&
96 pCreateInfo
->format
!= VK_FORMAT_D32_SFLOAT
&&
97 pCreateInfo
->format
!= VK_FORMAT_D16_UNORM
)
100 if (pCreateInfo
->flags
& VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
) {
101 const struct VkImageFormatListCreateInfoKHR
*format_list
=
102 (const struct VkImageFormatListCreateInfoKHR
*)
103 vk_find_struct_const(pCreateInfo
->pNext
,
104 IMAGE_FORMAT_LIST_CREATE_INFO_KHR
);
106 /* We have to ignore the existence of the list if viewFormatCount = 0 */
107 if (format_list
&& format_list
->viewFormatCount
) {
108 /* compatibility is transitive, so we only need to check
109 * one format with everything else.
111 for (unsigned i
= 0; i
< format_list
->viewFormatCount
; ++i
) {
112 if (format_list
->pViewFormats
[i
] == VK_FORMAT_UNDEFINED
)
115 if (pCreateInfo
->format
!= format_list
->pViewFormats
[i
])
127 radv_surface_has_scanout(struct radv_device
*device
, const struct radv_image_create_info
*info
)
132 if (!info
->bo_metadata
)
135 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
136 return info
->bo_metadata
->u
.gfx9
.swizzle_mode
== 0 || info
->bo_metadata
->u
.gfx9
.swizzle_mode
% 4 == 2;
138 return info
->bo_metadata
->u
.legacy
.scanout
;
143 radv_use_dcc_for_image(struct radv_device
*device
,
144 const struct radv_image
*image
,
145 const struct radv_image_create_info
*create_info
,
146 const VkImageCreateInfo
*pCreateInfo
)
148 bool dcc_compatible_formats
;
151 /* DCC (Delta Color Compression) is only available for GFX8+. */
152 if (device
->physical_device
->rad_info
.chip_class
< GFX8
)
155 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_DCC
)
158 if (image
->shareable
)
161 /* TODO: Enable DCC for storage images. */
162 if ((pCreateInfo
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
) ||
163 (pCreateInfo
->flags
& VK_IMAGE_CREATE_EXTENDED_USAGE_BIT
))
166 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
)
169 if (vk_format_is_subsampled(pCreateInfo
->format
) ||
170 vk_format_get_plane_count(pCreateInfo
->format
) > 1)
173 /* TODO: Enable DCC for mipmaps on GFX9+. */
174 if ((pCreateInfo
->arrayLayers
> 1 || pCreateInfo
->mipLevels
> 1) &&
175 device
->physical_device
->rad_info
.chip_class
>= GFX9
)
178 /* Do not enable DCC for mipmapped arrays because performance is worse. */
179 if (pCreateInfo
->arrayLayers
> 1 && pCreateInfo
->mipLevels
> 1)
182 if (radv_surface_has_scanout(device
, create_info
))
185 /* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet, while
186 * 2x can be enabled with an option.
188 if (pCreateInfo
->samples
> 2 ||
189 (pCreateInfo
->samples
== 2 &&
190 !device
->physical_device
->dcc_msaa_allowed
))
193 /* Determine if the formats are DCC compatible. */
194 dcc_compatible_formats
=
195 radv_is_colorbuffer_format_supported(pCreateInfo
->format
,
198 if (pCreateInfo
->flags
& VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
) {
199 const struct VkImageFormatListCreateInfoKHR
*format_list
=
200 (const struct VkImageFormatListCreateInfoKHR
*)
201 vk_find_struct_const(pCreateInfo
->pNext
,
202 IMAGE_FORMAT_LIST_CREATE_INFO_KHR
);
204 /* We have to ignore the existence of the list if viewFormatCount = 0 */
205 if (format_list
&& format_list
->viewFormatCount
) {
206 /* compatibility is transitive, so we only need to check
207 * one format with everything else. */
208 for (unsigned i
= 0; i
< format_list
->viewFormatCount
; ++i
) {
209 if (format_list
->pViewFormats
[i
] == VK_FORMAT_UNDEFINED
)
212 if (!radv_dcc_formats_compatible(pCreateInfo
->format
,
213 format_list
->pViewFormats
[i
]))
214 dcc_compatible_formats
= false;
217 dcc_compatible_formats
= false;
221 if (!dcc_compatible_formats
)
228 radv_use_tc_compat_cmask_for_image(struct radv_device
*device
,
229 struct radv_image
*image
)
231 if (!(device
->instance
->perftest_flags
& RADV_PERFTEST_TC_COMPAT_CMASK
))
234 /* TC-compat CMASK is only available for GFX8+. */
235 if (device
->physical_device
->rad_info
.chip_class
< GFX8
)
238 if (image
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
)
241 if (radv_image_has_dcc(image
))
244 if (!radv_image_has_cmask(image
))
251 radv_prefill_surface_from_metadata(struct radv_device
*device
,
252 struct radeon_surf
*surface
,
253 const struct radv_image_create_info
*create_info
)
255 const struct radeon_bo_metadata
*md
= create_info
->bo_metadata
;
256 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
257 if (md
->u
.gfx9
.swizzle_mode
> 0)
258 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
260 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED
, MODE
);
262 surface
->u
.gfx9
.surf
.swizzle_mode
= md
->u
.gfx9
.swizzle_mode
;
264 surface
->u
.legacy
.pipe_config
= md
->u
.legacy
.pipe_config
;
265 surface
->u
.legacy
.bankw
= md
->u
.legacy
.bankw
;
266 surface
->u
.legacy
.bankh
= md
->u
.legacy
.bankh
;
267 surface
->u
.legacy
.tile_split
= md
->u
.legacy
.tile_split
;
268 surface
->u
.legacy
.mtilea
= md
->u
.legacy
.mtilea
;
269 surface
->u
.legacy
.num_banks
= md
->u
.legacy
.num_banks
;
271 if (md
->u
.legacy
.macrotile
== RADEON_LAYOUT_TILED
)
272 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_2D
, MODE
);
273 else if (md
->u
.legacy
.microtile
== RADEON_LAYOUT_TILED
)
274 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_1D
, MODE
);
276 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_MODE_LINEAR_ALIGNED
, MODE
);
282 radv_init_surface(struct radv_device
*device
,
283 const struct radv_image
*image
,
284 struct radeon_surf
*surface
,
286 const struct radv_image_create_info
*create_info
)
288 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
289 unsigned array_mode
= radv_choose_tiling(device
, create_info
);
290 VkFormat format
= vk_format_get_plane_format(pCreateInfo
->format
, plane_id
);
291 const struct vk_format_description
*desc
= vk_format_description(format
);
292 bool is_depth
, is_stencil
;
294 is_depth
= vk_format_has_depth(desc
);
295 is_stencil
= vk_format_has_stencil(desc
);
297 surface
->blk_w
= vk_format_get_blockwidth(format
);
298 surface
->blk_h
= vk_format_get_blockheight(format
);
300 surface
->bpe
= vk_format_get_blocksize(vk_format_depth_only(format
));
301 /* align byte per element on dword */
302 if (surface
->bpe
== 3) {
305 if (create_info
->bo_metadata
) {
306 radv_prefill_surface_from_metadata(device
, surface
, create_info
);
308 surface
->flags
= RADEON_SURF_SET(array_mode
, MODE
);
311 switch (pCreateInfo
->imageType
){
312 case VK_IMAGE_TYPE_1D
:
313 if (pCreateInfo
->arrayLayers
> 1)
314 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
316 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
318 case VK_IMAGE_TYPE_2D
:
319 if (pCreateInfo
->arrayLayers
> 1)
320 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
322 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
324 case VK_IMAGE_TYPE_3D
:
325 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
328 unreachable("unhandled image type");
332 surface
->flags
|= RADEON_SURF_ZBUFFER
;
333 if (radv_use_tc_compat_htile_for_image(device
, pCreateInfo
))
334 surface
->flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
338 surface
->flags
|= RADEON_SURF_SBUFFER
;
340 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
341 pCreateInfo
->imageType
== VK_IMAGE_TYPE_3D
&&
342 vk_format_get_blocksizebits(pCreateInfo
->format
) == 128 &&
343 vk_format_is_compressed(pCreateInfo
->format
))
344 surface
->flags
|= RADEON_SURF_NO_RENDER_TARGET
;
346 surface
->flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
348 if (!radv_use_dcc_for_image(device
, image
, create_info
, pCreateInfo
))
349 surface
->flags
|= RADEON_SURF_DISABLE_DCC
;
351 if (radv_surface_has_scanout(device
, create_info
))
352 surface
->flags
|= RADEON_SURF_SCANOUT
;
357 static uint32_t si_get_bo_metadata_word1(struct radv_device
*device
)
359 return (ATI_VENDOR_ID
<< 16) | device
->physical_device
->rad_info
.pci_id
;
362 static inline unsigned
363 si_tile_mode_index(const struct radv_image_plane
*plane
, unsigned level
, bool stencil
)
366 return plane
->surface
.u
.legacy
.stencil_tiling_index
[level
];
368 return plane
->surface
.u
.legacy
.tiling_index
[level
];
371 static unsigned radv_map_swizzle(unsigned swizzle
)
375 return V_008F0C_SQ_SEL_Y
;
377 return V_008F0C_SQ_SEL_Z
;
379 return V_008F0C_SQ_SEL_W
;
381 return V_008F0C_SQ_SEL_0
;
383 return V_008F0C_SQ_SEL_1
;
384 default: /* VK_SWIZZLE_X */
385 return V_008F0C_SQ_SEL_X
;
390 radv_make_buffer_descriptor(struct radv_device
*device
,
391 struct radv_buffer
*buffer
,
397 const struct vk_format_description
*desc
;
399 uint64_t gpu_address
= radv_buffer_get_va(buffer
->bo
);
400 uint64_t va
= gpu_address
+ buffer
->offset
;
401 unsigned num_format
, data_format
;
403 desc
= vk_format_description(vk_format
);
404 first_non_void
= vk_format_get_first_non_void_channel(vk_format
);
405 stride
= desc
->block
.bits
/ 8;
407 num_format
= radv_translate_buffer_numformat(desc
, first_non_void
);
408 data_format
= radv_translate_buffer_dataformat(desc
, first_non_void
);
410 assert(data_format
!= V_008F0C_BUF_DATA_FORMAT_INVALID
);
411 assert(num_format
!= ~0);
415 state
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
416 S_008F04_STRIDE(stride
);
418 if (device
->physical_device
->rad_info
.chip_class
!= GFX8
&& stride
) {
423 state
[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc
->swizzle
[0])) |
424 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc
->swizzle
[1])) |
425 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc
->swizzle
[2])) |
426 S_008F0C_DST_SEL_W(radv_map_swizzle(desc
->swizzle
[3])) |
427 S_008F0C_NUM_FORMAT(num_format
) |
428 S_008F0C_DATA_FORMAT(data_format
);
432 si_set_mutable_tex_desc_fields(struct radv_device
*device
,
433 struct radv_image
*image
,
434 const struct legacy_surf_level
*base_level_info
,
436 unsigned base_level
, unsigned first_level
,
437 unsigned block_width
, bool is_stencil
,
438 bool is_storage_image
, uint32_t *state
)
440 struct radv_image_plane
*plane
= &image
->planes
[plane_id
];
441 uint64_t gpu_address
= image
->bo
? radv_buffer_get_va(image
->bo
) + image
->offset
: 0;
442 uint64_t va
= gpu_address
+ plane
->offset
;
443 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
444 uint64_t meta_va
= 0;
445 if (chip_class
>= GFX9
) {
447 va
+= plane
->surface
.u
.gfx9
.stencil_offset
;
449 va
+= plane
->surface
.u
.gfx9
.surf_offset
;
451 va
+= base_level_info
->offset
;
454 if (chip_class
>= GFX9
||
455 base_level_info
->mode
== RADEON_SURF_MODE_2D
)
456 state
[0] |= plane
->surface
.tile_swizzle
;
457 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
458 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
460 if (chip_class
>= GFX8
) {
461 state
[6] &= C_008F28_COMPRESSION_EN
;
463 if (!is_storage_image
&& radv_dcc_enabled(image
, first_level
)) {
464 meta_va
= gpu_address
+ image
->dcc_offset
;
465 if (chip_class
<= GFX8
)
466 meta_va
+= base_level_info
->dcc_offset
;
467 } else if (!is_storage_image
&&
468 radv_image_is_tc_compat_htile(image
)) {
469 meta_va
= gpu_address
+ image
->htile_offset
;
473 state
[6] |= S_008F28_COMPRESSION_EN(1);
474 state
[7] = meta_va
>> 8;
475 state
[7] |= plane
->surface
.tile_swizzle
;
479 if (chip_class
>= GFX9
) {
480 state
[3] &= C_008F1C_SW_MODE
;
481 state
[4] &= C_008F20_PITCH
;
484 state
[3] |= S_008F1C_SW_MODE(plane
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
485 state
[4] |= S_008F20_PITCH(plane
->surface
.u
.gfx9
.stencil
.epitch
);
487 state
[3] |= S_008F1C_SW_MODE(plane
->surface
.u
.gfx9
.surf
.swizzle_mode
);
488 state
[4] |= S_008F20_PITCH(plane
->surface
.u
.gfx9
.surf
.epitch
);
491 state
[5] &= C_008F24_META_DATA_ADDRESS
&
492 C_008F24_META_PIPE_ALIGNED
&
493 C_008F24_META_RB_ALIGNED
;
495 struct gfx9_surf_meta_flags meta
;
497 if (image
->dcc_offset
)
498 meta
= plane
->surface
.u
.gfx9
.dcc
;
500 meta
= plane
->surface
.u
.gfx9
.htile
;
502 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
503 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
504 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
508 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
509 unsigned index
= si_tile_mode_index(plane
, base_level
, is_stencil
);
511 state
[3] &= C_008F1C_TILING_INDEX
;
512 state
[3] |= S_008F1C_TILING_INDEX(index
);
513 state
[4] &= C_008F20_PITCH
;
514 state
[4] |= S_008F20_PITCH(pitch
- 1);
518 static unsigned radv_tex_dim(VkImageType image_type
, VkImageViewType view_type
,
519 unsigned nr_layers
, unsigned nr_samples
, bool is_storage_image
, bool gfx9
)
521 if (view_type
== VK_IMAGE_VIEW_TYPE_CUBE
|| view_type
== VK_IMAGE_VIEW_TYPE_CUBE_ARRAY
)
522 return is_storage_image
? V_008F1C_SQ_RSRC_IMG_2D_ARRAY
: V_008F1C_SQ_RSRC_IMG_CUBE
;
524 /* GFX9 allocates 1D textures as 2D. */
525 if (gfx9
&& image_type
== VK_IMAGE_TYPE_1D
)
526 image_type
= VK_IMAGE_TYPE_2D
;
527 switch (image_type
) {
528 case VK_IMAGE_TYPE_1D
:
529 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY
: V_008F1C_SQ_RSRC_IMG_1D
;
530 case VK_IMAGE_TYPE_2D
:
532 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
: V_008F1C_SQ_RSRC_IMG_2D_MSAA
;
534 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY
: V_008F1C_SQ_RSRC_IMG_2D
;
535 case VK_IMAGE_TYPE_3D
:
536 if (view_type
== VK_IMAGE_VIEW_TYPE_3D
)
537 return V_008F1C_SQ_RSRC_IMG_3D
;
539 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
541 unreachable("illegal image type");
545 static unsigned gfx9_border_color_swizzle(const enum vk_swizzle swizzle
[4])
547 unsigned bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
549 if (swizzle
[3] == VK_SWIZZLE_X
) {
550 /* For the pre-defined border color values (white, opaque
551 * black, transparent black), the only thing that matters is
552 * that the alpha channel winds up in the correct place
553 * (because the RGB channels are all the same) so either of
554 * these enumerations will work.
556 if (swizzle
[2] == VK_SWIZZLE_Y
)
557 bc_swizzle
= V_008F20_BC_SWIZZLE_WZYX
;
559 bc_swizzle
= V_008F20_BC_SWIZZLE_WXYZ
;
560 } else if (swizzle
[0] == VK_SWIZZLE_X
) {
561 if (swizzle
[1] == VK_SWIZZLE_Y
)
562 bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
564 bc_swizzle
= V_008F20_BC_SWIZZLE_XWYZ
;
565 } else if (swizzle
[1] == VK_SWIZZLE_X
) {
566 bc_swizzle
= V_008F20_BC_SWIZZLE_YXWZ
;
567 } else if (swizzle
[2] == VK_SWIZZLE_X
) {
568 bc_swizzle
= V_008F20_BC_SWIZZLE_ZYXW
;
575 * Build the sampler view descriptor for a texture.
578 si_make_texture_descriptor(struct radv_device
*device
,
579 struct radv_image
*image
,
580 bool is_storage_image
,
581 VkImageViewType view_type
,
583 const VkComponentMapping
*mapping
,
584 unsigned first_level
, unsigned last_level
,
585 unsigned first_layer
, unsigned last_layer
,
586 unsigned width
, unsigned height
, unsigned depth
,
588 uint32_t *fmask_state
)
590 const struct vk_format_description
*desc
;
591 enum vk_swizzle swizzle
[4];
593 unsigned num_format
, data_format
, type
;
595 desc
= vk_format_description(vk_format
);
597 if (desc
->colorspace
== VK_FORMAT_COLORSPACE_ZS
) {
598 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
599 vk_format_compose_swizzles(mapping
, swizzle_xxxx
, swizzle
);
601 vk_format_compose_swizzles(mapping
, desc
->swizzle
, swizzle
);
604 first_non_void
= vk_format_get_first_non_void_channel(vk_format
);
606 num_format
= radv_translate_tex_numformat(vk_format
, desc
, first_non_void
);
607 if (num_format
== ~0) {
611 data_format
= radv_translate_tex_dataformat(vk_format
, desc
, first_non_void
);
612 if (data_format
== ~0) {
616 /* S8 with either Z16 or Z32 HTILE need a special format. */
617 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
618 vk_format
== VK_FORMAT_S8_UINT
&&
619 radv_image_is_tc_compat_htile(image
)) {
620 if (image
->vk_format
== VK_FORMAT_D32_SFLOAT_S8_UINT
)
621 data_format
= V_008F14_IMG_DATA_FORMAT_S8_32
;
622 else if (image
->vk_format
== VK_FORMAT_D16_UNORM_S8_UINT
)
623 data_format
= V_008F14_IMG_DATA_FORMAT_S8_16
;
625 type
= radv_tex_dim(image
->type
, view_type
, image
->info
.array_size
, image
->info
.samples
,
626 is_storage_image
, device
->physical_device
->rad_info
.chip_class
>= GFX9
);
627 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
629 depth
= image
->info
.array_size
;
630 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
631 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
632 if (view_type
!= VK_IMAGE_VIEW_TYPE_3D
)
633 depth
= image
->info
.array_size
;
634 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
635 depth
= image
->info
.array_size
/ 6;
638 state
[1] = (S_008F14_DATA_FORMAT(data_format
) |
639 S_008F14_NUM_FORMAT(num_format
));
640 state
[2] = (S_008F18_WIDTH(width
- 1) |
641 S_008F18_HEIGHT(height
- 1) |
642 S_008F18_PERF_MOD(4));
643 state
[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle
[0])) |
644 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle
[1])) |
645 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle
[2])) |
646 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle
[3])) |
647 S_008F1C_BASE_LEVEL(image
->info
.samples
> 1 ?
649 S_008F1C_LAST_LEVEL(image
->info
.samples
> 1 ?
650 util_logbase2(image
->info
.samples
) :
652 S_008F1C_TYPE(type
));
654 state
[5] = S_008F24_BASE_ARRAY(first_layer
);
658 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
659 unsigned bc_swizzle
= gfx9_border_color_swizzle(swizzle
);
661 /* Depth is the last accessible layer on Gfx9.
662 * The hw doesn't need to know the total number of layers.
664 if (type
== V_008F1C_SQ_RSRC_IMG_3D
)
665 state
[4] |= S_008F20_DEPTH(depth
- 1);
667 state
[4] |= S_008F20_DEPTH(last_layer
);
669 state
[4] |= S_008F20_BC_SWIZZLE(bc_swizzle
);
670 state
[5] |= S_008F24_MAX_MIP(image
->info
.samples
> 1 ?
671 util_logbase2(image
->info
.samples
) :
672 image
->info
.levels
- 1);
674 state
[3] |= S_008F1C_POW2_PAD(image
->info
.levels
> 1);
675 state
[4] |= S_008F20_DEPTH(depth
- 1);
676 state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
678 if (image
->dcc_offset
) {
679 unsigned swap
= radv_translate_colorswap(vk_format
, FALSE
);
681 state
[6] = S_008F28_ALPHA_IS_ON_MSB(swap
<= 1);
683 /* The last dword is unused by hw. The shader uses it to clear
684 * bits in the first dword of sampler state.
686 if (device
->physical_device
->rad_info
.chip_class
<= GFX7
&& image
->info
.samples
<= 1) {
687 if (first_level
== last_level
)
688 state
[7] = C_008F30_MAX_ANISO_RATIO
;
690 state
[7] = 0xffffffff;
694 /* Initialize the sampler view for FMASK. */
695 if (radv_image_has_fmask(image
)) {
696 uint32_t fmask_format
, num_format
;
697 uint64_t gpu_address
= radv_buffer_get_va(image
->bo
);
700 assert(image
->plane_count
== 1);
702 va
= gpu_address
+ image
->offset
+ image
->fmask
.offset
;
704 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
705 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK
;
706 switch (image
->info
.samples
) {
708 num_format
= V_008F14_IMG_FMASK_8_2_2
;
711 num_format
= V_008F14_IMG_FMASK_8_4_4
;
714 num_format
= V_008F14_IMG_FMASK_32_8_8
;
717 unreachable("invalid nr_samples");
720 switch (image
->info
.samples
) {
722 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
725 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
728 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
732 fmask_format
= V_008F14_IMG_DATA_FORMAT_INVALID
;
734 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
737 fmask_state
[0] = va
>> 8;
738 fmask_state
[0] |= image
->fmask
.tile_swizzle
;
739 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
740 S_008F14_DATA_FORMAT(fmask_format
) |
741 S_008F14_NUM_FORMAT(num_format
);
742 fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
743 S_008F18_HEIGHT(height
- 1);
744 fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
745 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
746 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
747 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
748 S_008F1C_TYPE(radv_tex_dim(image
->type
, view_type
, image
->info
.array_size
, 0, false, false));
750 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
);
754 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
755 fmask_state
[3] |= S_008F1C_SW_MODE(image
->planes
[0].surface
.u
.gfx9
.fmask
.swizzle_mode
);
756 fmask_state
[4] |= S_008F20_DEPTH(last_layer
) |
757 S_008F20_PITCH(image
->planes
[0].surface
.u
.gfx9
.fmask
.epitch
);
758 fmask_state
[5] |= S_008F24_META_PIPE_ALIGNED(image
->planes
[0].surface
.u
.gfx9
.cmask
.pipe_aligned
) |
759 S_008F24_META_RB_ALIGNED(image
->planes
[0].surface
.u
.gfx9
.cmask
.rb_aligned
);
761 if (radv_image_is_tc_compat_cmask(image
)) {
762 va
= gpu_address
+ image
->offset
+ image
->cmask
.offset
;
764 fmask_state
[5] |= S_008F24_META_DATA_ADDRESS(va
>> 40);
765 fmask_state
[6] |= S_008F28_COMPRESSION_EN(1);
766 fmask_state
[7] |= va
>> 8;
769 fmask_state
[3] |= S_008F1C_TILING_INDEX(image
->fmask
.tile_mode_index
);
770 fmask_state
[4] |= S_008F20_DEPTH(depth
- 1) |
771 S_008F20_PITCH(image
->fmask
.pitch_in_pixels
- 1);
772 fmask_state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
774 if (radv_image_is_tc_compat_cmask(image
)) {
775 va
= gpu_address
+ image
->offset
+ image
->cmask
.offset
;
777 fmask_state
[6] |= S_008F28_COMPRESSION_EN(1);
778 fmask_state
[7] |= va
>> 8;
781 } else if (fmask_state
)
782 memset(fmask_state
, 0, 8 * 4);
786 radv_query_opaque_metadata(struct radv_device
*device
,
787 struct radv_image
*image
,
788 struct radeon_bo_metadata
*md
)
790 static const VkComponentMapping fixedmapping
;
793 assert(image
->plane_count
== 1);
795 /* Metadata image format format version 1:
796 * [0] = 1 (metadata format identifier)
797 * [1] = (VENDOR_ID << 16) | PCI_ID
798 * [2:9] = image descriptor for the whole resource
799 * [2] is always 0, because the base address is cleared
800 * [9] is the DCC offset bits [39:8] from the beginning of
802 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
804 md
->metadata
[0] = 1; /* metadata image format version 1 */
806 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
807 md
->metadata
[1] = si_get_bo_metadata_word1(device
);
810 si_make_texture_descriptor(device
, image
, false,
811 (VkImageViewType
)image
->type
, image
->vk_format
,
812 &fixedmapping
, 0, image
->info
.levels
- 1, 0,
813 image
->info
.array_size
- 1,
814 image
->info
.width
, image
->info
.height
,
818 si_set_mutable_tex_desc_fields(device
, image
, &image
->planes
[0].surface
.u
.legacy
.level
[0], 0, 0, 0,
819 image
->planes
[0].surface
.blk_w
, false, false, desc
);
821 /* Clear the base address and set the relative DCC offset. */
823 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
824 desc
[7] = image
->dcc_offset
>> 8;
826 /* Dwords [2:9] contain the image descriptor. */
827 memcpy(&md
->metadata
[2], desc
, sizeof(desc
));
829 /* Dwords [10:..] contain the mipmap level offsets. */
830 if (device
->physical_device
->rad_info
.chip_class
<= GFX8
) {
831 for (i
= 0; i
<= image
->info
.levels
- 1; i
++)
832 md
->metadata
[10+i
] = image
->planes
[0].surface
.u
.legacy
.level
[i
].offset
>> 8;
833 md
->size_metadata
= (11 + image
->info
.levels
- 1) * 4;
838 radv_init_metadata(struct radv_device
*device
,
839 struct radv_image
*image
,
840 struct radeon_bo_metadata
*metadata
)
842 struct radeon_surf
*surface
= &image
->planes
[0].surface
;
844 memset(metadata
, 0, sizeof(*metadata
));
846 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
847 metadata
->u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
849 metadata
->u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
850 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
851 metadata
->u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
852 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
853 metadata
->u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
854 metadata
->u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
855 metadata
->u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
856 metadata
->u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
857 metadata
->u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
858 metadata
->u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
859 metadata
->u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
860 metadata
->u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
862 radv_query_opaque_metadata(device
, image
, metadata
);
866 radv_image_override_offset_stride(struct radv_device
*device
,
867 struct radv_image
*image
,
868 uint64_t offset
, uint32_t stride
)
870 struct radeon_surf
*surface
= &image
->planes
[0].surface
;
871 unsigned bpe
= vk_format_get_blocksizebits(image
->vk_format
) / 8;
873 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
875 surface
->u
.gfx9
.surf_pitch
= stride
;
876 surface
->u
.gfx9
.surf_slice_size
=
877 (uint64_t)stride
* surface
->u
.gfx9
.surf_height
* bpe
;
879 surface
->u
.gfx9
.surf_offset
= offset
;
881 surface
->u
.legacy
.level
[0].nblk_x
= stride
;
882 surface
->u
.legacy
.level
[0].slice_size_dw
=
883 ((uint64_t)stride
* surface
->u
.legacy
.level
[0].nblk_y
* bpe
) / 4;
886 for (unsigned i
= 0; i
< ARRAY_SIZE(surface
->u
.legacy
.level
); ++i
)
887 surface
->u
.legacy
.level
[i
].offset
+= offset
;
893 /* The number of samples can be specified independently of the texture. */
895 radv_image_get_fmask_info(struct radv_device
*device
,
896 struct radv_image
*image
,
898 struct radv_fmask_info
*out
)
900 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
901 out
->alignment
= image
->planes
[0].surface
.fmask_alignment
;
902 out
->size
= image
->planes
[0].surface
.fmask_size
;
903 out
->tile_swizzle
= image
->planes
[0].surface
.fmask_tile_swizzle
;
907 out
->slice_tile_max
= image
->planes
[0].surface
.u
.legacy
.fmask
.slice_tile_max
;
908 out
->tile_mode_index
= image
->planes
[0].surface
.u
.legacy
.fmask
.tiling_index
;
909 out
->pitch_in_pixels
= image
->planes
[0].surface
.u
.legacy
.fmask
.pitch_in_pixels
;
910 out
->slice_size
= image
->planes
[0].surface
.u
.legacy
.fmask
.slice_size
;
911 out
->bank_height
= image
->planes
[0].surface
.u
.legacy
.fmask
.bankh
;
912 out
->tile_swizzle
= image
->planes
[0].surface
.fmask_tile_swizzle
;
913 out
->alignment
= image
->planes
[0].surface
.fmask_alignment
;
914 out
->size
= image
->planes
[0].surface
.fmask_size
;
916 assert(!out
->tile_swizzle
|| !image
->shareable
);
920 radv_image_alloc_fmask(struct radv_device
*device
,
921 struct radv_image
*image
)
923 radv_image_get_fmask_info(device
, image
, image
->info
.samples
, &image
->fmask
);
925 image
->fmask
.offset
= align64(image
->size
, image
->fmask
.alignment
);
926 image
->size
= image
->fmask
.offset
+ image
->fmask
.size
;
927 image
->alignment
= MAX2(image
->alignment
, image
->fmask
.alignment
);
931 radv_image_get_cmask_info(struct radv_device
*device
,
932 struct radv_image
*image
,
933 struct radv_cmask_info
*out
)
935 assert(image
->plane_count
== 1);
937 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
938 out
->alignment
= image
->planes
[0].surface
.cmask_alignment
;
939 out
->size
= image
->planes
[0].surface
.cmask_size
;
943 out
->slice_tile_max
= image
->planes
[0].surface
.u
.legacy
.cmask_slice_tile_max
;
944 out
->alignment
= image
->planes
[0].surface
.cmask_alignment
;
945 out
->slice_size
= image
->planes
[0].surface
.cmask_slice_size
;
946 out
->size
= image
->planes
[0].surface
.cmask_size
;
950 radv_image_alloc_cmask(struct radv_device
*device
,
951 struct radv_image
*image
)
953 uint32_t clear_value_size
= 0;
954 radv_image_get_cmask_info(device
, image
, &image
->cmask
);
956 image
->cmask
.offset
= align64(image
->size
, image
->cmask
.alignment
);
957 /* + 8 for storing the clear values */
958 if (!image
->clear_value_offset
) {
959 image
->clear_value_offset
= image
->cmask
.offset
+ image
->cmask
.size
;
960 clear_value_size
= 8;
962 image
->size
= image
->cmask
.offset
+ image
->cmask
.size
+ clear_value_size
;
963 image
->alignment
= MAX2(image
->alignment
, image
->cmask
.alignment
);
967 radv_image_alloc_dcc(struct radv_image
*image
)
969 assert(image
->plane_count
== 1);
971 image
->dcc_offset
= align64(image
->size
, image
->planes
[0].surface
.dcc_alignment
);
972 /* + 24 for storing the clear values + fce pred + dcc pred for each mip */
973 image
->clear_value_offset
= image
->dcc_offset
+ image
->planes
[0].surface
.dcc_size
;
974 image
->fce_pred_offset
= image
->clear_value_offset
+ 8 * image
->info
.levels
;
975 image
->dcc_pred_offset
= image
->clear_value_offset
+ 16 * image
->info
.levels
;
976 image
->size
= image
->dcc_offset
+ image
->planes
[0].surface
.dcc_size
+ 24 * image
->info
.levels
;
977 image
->alignment
= MAX2(image
->alignment
, image
->planes
[0].surface
.dcc_alignment
);
981 radv_image_alloc_htile(struct radv_image
*image
)
983 image
->htile_offset
= align64(image
->size
, image
->planes
[0].surface
.htile_alignment
);
985 /* + 8 for storing the clear values */
986 image
->clear_value_offset
= image
->htile_offset
+ image
->planes
[0].surface
.htile_size
;
987 image
->size
= image
->clear_value_offset
+ 8;
988 if (radv_image_is_tc_compat_htile(image
)) {
989 /* Metadata for the TC-compatible HTILE hardware bug which
990 * have to be fixed by updating ZRANGE_PRECISION when doing
991 * fast depth clears to 0.0f.
993 image
->tc_compat_zrange_offset
= image
->clear_value_offset
+ 8;
994 image
->size
= image
->clear_value_offset
+ 16;
996 image
->alignment
= align64(image
->alignment
, image
->planes
[0].surface
.htile_alignment
);
1000 radv_image_can_enable_dcc_or_cmask(struct radv_image
*image
)
1002 if (image
->info
.samples
<= 1 &&
1003 image
->info
.width
* image
->info
.height
<= 512 * 512) {
1004 /* Do not enable CMASK or DCC for small surfaces where the cost
1005 * of the eliminate pass can be higher than the benefit of fast
1006 * clear. RadeonSI does this, but the image threshold is
1012 return image
->usage
& VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
&&
1013 (image
->exclusive
|| image
->queue_family_mask
== 1);
1017 radv_image_can_enable_dcc(struct radv_device
*device
, struct radv_image
*image
)
1019 if (!radv_image_can_enable_dcc_or_cmask(image
) ||
1020 !radv_image_has_dcc(image
))
1023 /* On GFX8, DCC layers can be interleaved and it's currently only
1024 * enabled if slice size is equal to the per slice fast clear size
1025 * because the driver assumes that portions of multiple layers are
1026 * contiguous during fast clears.
1028 if (image
->info
.array_size
> 1) {
1029 const struct legacy_surf_level
*surf_level
=
1030 &image
->planes
[0].surface
.u
.legacy
.level
[0];
1032 assert(device
->physical_device
->rad_info
.chip_class
== GFX8
);
1034 if (image
->planes
[0].surface
.dcc_slice_size
!= surf_level
->dcc_fast_clear_size
)
1042 radv_image_can_enable_cmask(struct radv_image
*image
)
1044 if (image
->planes
[0].surface
.bpe
> 8 && image
->info
.samples
== 1) {
1045 /* Do not enable CMASK for non-MSAA images (fast color clear)
1046 * because 128 bit formats are not supported, but FMASK might
1052 return radv_image_can_enable_dcc_or_cmask(image
) &&
1053 image
->info
.levels
== 1 &&
1054 image
->info
.depth
== 1 &&
1055 !image
->planes
[0].surface
.is_linear
;
1059 radv_image_can_enable_fmask(struct radv_image
*image
)
1061 return image
->info
.samples
> 1 && vk_format_is_color(image
->vk_format
);
1065 radv_image_can_enable_htile(struct radv_image
*image
)
1067 return radv_image_has_htile(image
) &&
1068 image
->info
.levels
== 1 &&
1069 image
->info
.width
* image
->info
.height
>= 8 * 8;
1072 static void radv_image_disable_dcc(struct radv_image
*image
)
1074 for (unsigned i
= 0; i
< image
->plane_count
; ++i
)
1075 image
->planes
[i
].surface
.dcc_size
= 0;
1078 static void radv_image_disable_htile(struct radv_image
*image
)
1080 for (unsigned i
= 0; i
< image
->plane_count
; ++i
)
1081 image
->planes
[i
].surface
.htile_size
= 0;
1085 radv_image_create(VkDevice _device
,
1086 const struct radv_image_create_info
*create_info
,
1087 const VkAllocationCallbacks
* alloc
,
1090 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1091 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
1092 struct radv_image
*image
= NULL
;
1093 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO
);
1095 const unsigned plane_count
= vk_format_get_plane_count(pCreateInfo
->format
);
1096 const size_t image_struct_size
= sizeof(*image
) + sizeof(struct radv_image_plane
) * plane_count
;
1098 radv_assert(pCreateInfo
->mipLevels
> 0);
1099 radv_assert(pCreateInfo
->arrayLayers
> 0);
1100 radv_assert(pCreateInfo
->samples
> 0);
1101 radv_assert(pCreateInfo
->extent
.width
> 0);
1102 radv_assert(pCreateInfo
->extent
.height
> 0);
1103 radv_assert(pCreateInfo
->extent
.depth
> 0);
1105 image
= vk_zalloc2(&device
->alloc
, alloc
, image_struct_size
, 8,
1106 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1108 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1110 image
->type
= pCreateInfo
->imageType
;
1111 image
->info
.width
= pCreateInfo
->extent
.width
;
1112 image
->info
.height
= pCreateInfo
->extent
.height
;
1113 image
->info
.depth
= pCreateInfo
->extent
.depth
;
1114 image
->info
.samples
= pCreateInfo
->samples
;
1115 image
->info
.storage_samples
= pCreateInfo
->samples
;
1116 image
->info
.array_size
= pCreateInfo
->arrayLayers
;
1117 image
->info
.levels
= pCreateInfo
->mipLevels
;
1118 image
->info
.num_channels
= vk_format_get_nr_components(pCreateInfo
->format
);
1120 image
->vk_format
= pCreateInfo
->format
;
1121 image
->tiling
= pCreateInfo
->tiling
;
1122 image
->usage
= pCreateInfo
->usage
;
1123 image
->flags
= pCreateInfo
->flags
;
1125 image
->exclusive
= pCreateInfo
->sharingMode
== VK_SHARING_MODE_EXCLUSIVE
;
1126 if (pCreateInfo
->sharingMode
== VK_SHARING_MODE_CONCURRENT
) {
1127 for (uint32_t i
= 0; i
< pCreateInfo
->queueFamilyIndexCount
; ++i
)
1128 if (pCreateInfo
->pQueueFamilyIndices
[i
] == VK_QUEUE_FAMILY_EXTERNAL
)
1129 image
->queue_family_mask
|= (1u << RADV_MAX_QUEUE_FAMILIES
) - 1u;
1131 image
->queue_family_mask
|= 1u << pCreateInfo
->pQueueFamilyIndices
[i
];
1134 image
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
1135 EXTERNAL_MEMORY_IMAGE_CREATE_INFO
) != NULL
;
1136 if (!vk_format_is_depth_or_stencil(pCreateInfo
->format
) &&
1137 !radv_surface_has_scanout(device
, create_info
) && !image
->shareable
) {
1138 image
->info
.surf_index
= &device
->image_mrt_offset_counter
;
1141 image
->plane_count
= plane_count
;
1143 image
->alignment
= 1;
1144 for (unsigned plane
= 0; plane
< plane_count
; ++plane
) {
1145 struct ac_surf_info info
= image
->info
;
1146 radv_init_surface(device
, image
, &image
->planes
[plane
].surface
, plane
, create_info
);
1149 const struct vk_format_description
*desc
= vk_format_description(pCreateInfo
->format
);
1150 assert(info
.width
% desc
->width_divisor
== 0);
1151 assert(info
.height
% desc
->height_divisor
== 0);
1153 info
.width
/= desc
->width_divisor
;
1154 info
.height
/= desc
->height_divisor
;
1157 device
->ws
->surface_init(device
->ws
, &info
, &image
->planes
[plane
].surface
);
1159 image
->planes
[plane
].offset
= align(image
->size
, image
->planes
[plane
].surface
.surf_alignment
);
1160 image
->size
= image
->planes
[plane
].offset
+ image
->planes
[plane
].surface
.surf_size
;
1161 image
->alignment
= image
->planes
[plane
].surface
.surf_alignment
;
1163 image
->planes
[plane
].format
= vk_format_get_plane_format(image
->vk_format
, plane
);
1166 if (!create_info
->no_metadata_planes
) {
1167 /* Try to enable DCC first. */
1168 if (radv_image_can_enable_dcc(device
, image
)) {
1169 radv_image_alloc_dcc(image
);
1170 if (image
->info
.samples
> 1) {
1171 /* CMASK should be enabled because DCC fast
1172 * clear with MSAA needs it.
1174 assert(radv_image_can_enable_cmask(image
));
1175 radv_image_alloc_cmask(device
, image
);
1178 /* When DCC cannot be enabled, try CMASK. */
1179 radv_image_disable_dcc(image
);
1180 if (radv_image_can_enable_cmask(image
)) {
1181 radv_image_alloc_cmask(device
, image
);
1185 /* Try to enable FMASK for multisampled images. */
1186 if (radv_image_can_enable_fmask(image
)) {
1187 radv_image_alloc_fmask(device
, image
);
1189 if (radv_use_tc_compat_cmask_for_image(device
, image
))
1190 image
->tc_compatible_cmask
= true;
1192 /* Otherwise, try to enable HTILE for depth surfaces. */
1193 if (radv_image_can_enable_htile(image
) &&
1194 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_HIZ
)) {
1195 image
->tc_compatible_htile
= image
->planes
[0].surface
.flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
;
1196 radv_image_alloc_htile(image
);
1198 radv_image_disable_htile(image
);
1202 radv_image_disable_dcc(image
);
1203 radv_image_disable_htile(image
);
1206 if (pCreateInfo
->flags
& VK_IMAGE_CREATE_SPARSE_BINDING_BIT
) {
1207 image
->alignment
= MAX2(image
->alignment
, 4096);
1208 image
->size
= align64(image
->size
, image
->alignment
);
1211 image
->bo
= device
->ws
->buffer_create(device
->ws
, image
->size
, image
->alignment
,
1212 0, RADEON_FLAG_VIRTUAL
, RADV_BO_PRIORITY_VIRTUAL
);
1214 vk_free2(&device
->alloc
, alloc
, image
);
1215 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1219 *pImage
= radv_image_to_handle(image
);
1225 radv_image_view_make_descriptor(struct radv_image_view
*iview
,
1226 struct radv_device
*device
,
1228 const VkComponentMapping
*components
,
1229 bool is_storage_image
, unsigned plane_id
,
1230 unsigned descriptor_plane_id
)
1232 struct radv_image
*image
= iview
->image
;
1233 struct radv_image_plane
*plane
= &image
->planes
[plane_id
];
1234 const struct vk_format_description
*format_desc
= vk_format_description(image
->vk_format
);
1235 bool is_stencil
= iview
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
;
1237 union radv_descriptor
*descriptor
;
1238 uint32_t hw_level
= 0;
1240 if (is_storage_image
) {
1241 descriptor
= &iview
->storage_descriptor
;
1243 descriptor
= &iview
->descriptor
;
1246 assert(vk_format_get_plane_count(vk_format
) == 1);
1247 assert(plane
->surface
.blk_w
% vk_format_get_blockwidth(plane
->format
) == 0);
1248 blk_w
= plane
->surface
.blk_w
/ vk_format_get_blockwidth(plane
->format
) * vk_format_get_blockwidth(vk_format
);
1250 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1251 hw_level
= iview
->base_mip
;
1252 si_make_texture_descriptor(device
, image
, is_storage_image
,
1256 hw_level
, hw_level
+ iview
->level_count
- 1,
1258 iview
->base_layer
+ iview
->layer_count
- 1,
1259 iview
->extent
.width
/ (plane_id
? format_desc
->width_divisor
: 1),
1260 iview
->extent
.height
/ (plane_id
? format_desc
->height_divisor
: 1),
1261 iview
->extent
.depth
,
1262 descriptor
->plane_descriptors
[descriptor_plane_id
],
1263 descriptor_plane_id
? NULL
: descriptor
->fmask_descriptor
);
1265 const struct legacy_surf_level
*base_level_info
= NULL
;
1266 if (device
->physical_device
->rad_info
.chip_class
<= GFX9
) {
1268 base_level_info
= &plane
->surface
.u
.legacy
.stencil_level
[iview
->base_mip
];
1270 base_level_info
= &plane
->surface
.u
.legacy
.level
[iview
->base_mip
];
1272 si_set_mutable_tex_desc_fields(device
, image
,
1277 blk_w
, is_stencil
, is_storage_image
, descriptor
->plane_descriptors
[descriptor_plane_id
]);
1281 radv_plane_from_aspect(VkImageAspectFlags mask
)
1284 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
1286 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
1294 radv_get_aspect_format(struct radv_image
*image
, VkImageAspectFlags mask
)
1297 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
1298 return image
->planes
[0].format
;
1299 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
1300 return image
->planes
[1].format
;
1301 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
1302 return image
->planes
[2].format
;
1303 case VK_IMAGE_ASPECT_STENCIL_BIT
:
1304 return vk_format_stencil_only(image
->vk_format
);
1305 case VK_IMAGE_ASPECT_DEPTH_BIT
:
1306 return vk_format_depth_only(image
->vk_format
);
1307 case VK_IMAGE_ASPECT_DEPTH_BIT
| VK_IMAGE_ASPECT_STENCIL_BIT
:
1308 return vk_format_depth_only(image
->vk_format
);
1310 return image
->vk_format
;
1315 radv_image_view_init(struct radv_image_view
*iview
,
1316 struct radv_device
*device
,
1317 const VkImageViewCreateInfo
* pCreateInfo
)
1319 RADV_FROM_HANDLE(radv_image
, image
, pCreateInfo
->image
);
1320 const VkImageSubresourceRange
*range
= &pCreateInfo
->subresourceRange
;
1322 switch (image
->type
) {
1323 case VK_IMAGE_TYPE_1D
:
1324 case VK_IMAGE_TYPE_2D
:
1325 assert(range
->baseArrayLayer
+ radv_get_layerCount(image
, range
) - 1 <= image
->info
.array_size
);
1327 case VK_IMAGE_TYPE_3D
:
1328 assert(range
->baseArrayLayer
+ radv_get_layerCount(image
, range
) - 1
1329 <= radv_minify(image
->info
.depth
, range
->baseMipLevel
));
1332 unreachable("bad VkImageType");
1334 iview
->image
= image
;
1335 iview
->bo
= image
->bo
;
1336 iview
->type
= pCreateInfo
->viewType
;
1337 iview
->plane_id
= radv_plane_from_aspect(pCreateInfo
->subresourceRange
.aspectMask
);
1338 iview
->aspect_mask
= pCreateInfo
->subresourceRange
.aspectMask
;
1339 iview
->multiple_planes
= vk_format_get_plane_count(image
->vk_format
) > 1 && iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
;
1340 iview
->vk_format
= pCreateInfo
->format
;
1342 if (iview
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
) {
1343 iview
->vk_format
= vk_format_stencil_only(iview
->vk_format
);
1344 } else if (iview
->aspect_mask
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
1345 iview
->vk_format
= vk_format_depth_only(iview
->vk_format
);
1348 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1349 iview
->extent
= (VkExtent3D
) {
1350 .width
= image
->info
.width
,
1351 .height
= image
->info
.height
,
1352 .depth
= image
->info
.depth
,
1355 iview
->extent
= (VkExtent3D
) {
1356 .width
= radv_minify(image
->info
.width
, range
->baseMipLevel
),
1357 .height
= radv_minify(image
->info
.height
, range
->baseMipLevel
),
1358 .depth
= radv_minify(image
->info
.depth
, range
->baseMipLevel
),
1362 if (iview
->vk_format
!= image
->planes
[iview
->plane_id
].format
) {
1363 unsigned view_bw
= vk_format_get_blockwidth(iview
->vk_format
);
1364 unsigned view_bh
= vk_format_get_blockheight(iview
->vk_format
);
1365 unsigned img_bw
= vk_format_get_blockwidth(image
->vk_format
);
1366 unsigned img_bh
= vk_format_get_blockheight(image
->vk_format
);
1368 iview
->extent
.width
= round_up_u32(iview
->extent
.width
* view_bw
, img_bw
);
1369 iview
->extent
.height
= round_up_u32(iview
->extent
.height
* view_bh
, img_bh
);
1371 /* Comment ported from amdvlk -
1372 * If we have the following image:
1373 * Uncompressed pixels Compressed block sizes (4x4)
1374 * mip0: 22 x 22 6 x 6
1375 * mip1: 11 x 11 3 x 3
1380 * On GFX9 the descriptor is always programmed with the WIDTH and HEIGHT of the base level and the HW is
1381 * calculating the degradation of the block sizes down the mip-chain as follows (straight-up
1382 * divide-by-two integer math):
1388 * This means that mip2 will be missing texels.
1390 * Fix this by calculating the base mip's width and height, then convert that, and round it
1391 * back up to get the level 0 size.
1392 * Clamp the converted size between the original values, and next power of two, which
1393 * means we don't oversize the image.
1395 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
1396 vk_format_is_compressed(image
->vk_format
) &&
1397 !vk_format_is_compressed(iview
->vk_format
)) {
1398 unsigned lvl_width
= radv_minify(image
->info
.width
, range
->baseMipLevel
);
1399 unsigned lvl_height
= radv_minify(image
->info
.height
, range
->baseMipLevel
);
1401 lvl_width
= round_up_u32(lvl_width
* view_bw
, img_bw
);
1402 lvl_height
= round_up_u32(lvl_height
* view_bh
, img_bh
);
1404 lvl_width
<<= range
->baseMipLevel
;
1405 lvl_height
<<= range
->baseMipLevel
;
1407 iview
->extent
.width
= CLAMP(lvl_width
, iview
->extent
.width
, iview
->image
->planes
[0].surface
.u
.gfx9
.surf_pitch
);
1408 iview
->extent
.height
= CLAMP(lvl_height
, iview
->extent
.height
, iview
->image
->planes
[0].surface
.u
.gfx9
.surf_height
);
1412 iview
->base_layer
= range
->baseArrayLayer
;
1413 iview
->layer_count
= radv_get_layerCount(image
, range
);
1414 iview
->base_mip
= range
->baseMipLevel
;
1415 iview
->level_count
= radv_get_levelCount(image
, range
);
1417 for (unsigned i
= 0; i
< (iview
->multiple_planes
? vk_format_get_plane_count(image
->vk_format
) : 1); ++i
) {
1418 VkFormat format
= vk_format_get_plane_format(iview
->vk_format
, i
);
1419 radv_image_view_make_descriptor(iview
, device
, format
, &pCreateInfo
->components
, false, iview
->plane_id
+ i
, i
);
1420 radv_image_view_make_descriptor(iview
, device
, format
, &pCreateInfo
->components
, true, iview
->plane_id
+ i
, i
);
1424 bool radv_layout_has_htile(const struct radv_image
*image
,
1425 VkImageLayout layout
,
1426 unsigned queue_mask
)
1428 if (radv_image_is_tc_compat_htile(image
))
1429 return layout
!= VK_IMAGE_LAYOUT_GENERAL
;
1431 return radv_image_has_htile(image
) &&
1432 (layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
1433 (layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
&&
1434 queue_mask
== (1u << RADV_QUEUE_GENERAL
)));
1437 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1438 VkImageLayout layout
,
1439 unsigned queue_mask
)
1441 if (radv_image_is_tc_compat_htile(image
))
1442 return layout
!= VK_IMAGE_LAYOUT_GENERAL
;
1444 return radv_image_has_htile(image
) &&
1445 (layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
1446 (layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
&&
1447 queue_mask
== (1u << RADV_QUEUE_GENERAL
)));
1450 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1451 VkImageLayout layout
,
1452 unsigned queue_mask
)
1454 return layout
== VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
1457 bool radv_layout_dcc_compressed(const struct radv_image
*image
,
1458 VkImageLayout layout
,
1459 unsigned queue_mask
)
1461 /* Don't compress compute transfer dst, as image stores are not supported. */
1462 if (layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
&&
1463 (queue_mask
& (1u << RADV_QUEUE_COMPUTE
)))
1466 return radv_image_has_dcc(image
) && layout
!= VK_IMAGE_LAYOUT_GENERAL
;
1470 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
)
1472 if (!image
->exclusive
)
1473 return image
->queue_family_mask
;
1474 if (family
== VK_QUEUE_FAMILY_EXTERNAL
)
1475 return (1u << RADV_MAX_QUEUE_FAMILIES
) - 1u;
1476 if (family
== VK_QUEUE_FAMILY_IGNORED
)
1477 return 1u << queue_family
;
1478 return 1u << family
;
1482 radv_CreateImage(VkDevice device
,
1483 const VkImageCreateInfo
*pCreateInfo
,
1484 const VkAllocationCallbacks
*pAllocator
,
1488 const VkNativeBufferANDROID
*gralloc_info
=
1489 vk_find_struct_const(pCreateInfo
->pNext
, NATIVE_BUFFER_ANDROID
);
1492 return radv_image_from_gralloc(device
, pCreateInfo
, gralloc_info
,
1493 pAllocator
, pImage
);
1496 const struct wsi_image_create_info
*wsi_info
=
1497 vk_find_struct_const(pCreateInfo
->pNext
, WSI_IMAGE_CREATE_INFO_MESA
);
1498 bool scanout
= wsi_info
&& wsi_info
->scanout
;
1500 return radv_image_create(device
,
1501 &(struct radv_image_create_info
) {
1502 .vk_info
= pCreateInfo
,
1510 radv_DestroyImage(VkDevice _device
, VkImage _image
,
1511 const VkAllocationCallbacks
*pAllocator
)
1513 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1514 RADV_FROM_HANDLE(radv_image
, image
, _image
);
1519 if (image
->flags
& VK_IMAGE_CREATE_SPARSE_BINDING_BIT
)
1520 device
->ws
->buffer_destroy(image
->bo
);
1522 if (image
->owned_memory
!= VK_NULL_HANDLE
)
1523 radv_FreeMemory(_device
, image
->owned_memory
, pAllocator
);
1525 vk_free2(&device
->alloc
, pAllocator
, image
);
1528 void radv_GetImageSubresourceLayout(
1531 const VkImageSubresource
* pSubresource
,
1532 VkSubresourceLayout
* pLayout
)
1534 RADV_FROM_HANDLE(radv_image
, image
, _image
);
1535 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1536 int level
= pSubresource
->mipLevel
;
1537 int layer
= pSubresource
->arrayLayer
;
1539 unsigned plane_id
= radv_plane_from_aspect(pSubresource
->aspectMask
);
1541 struct radv_image_plane
*plane
= &image
->planes
[plane_id
];
1542 struct radeon_surf
*surface
= &plane
->surface
;
1544 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1545 pLayout
->offset
= plane
->offset
+ surface
->u
.gfx9
.offset
[level
] + surface
->u
.gfx9
.surf_slice_size
* layer
;
1546 if (image
->vk_format
== VK_FORMAT_R32G32B32_UINT
||
1547 image
->vk_format
== VK_FORMAT_R32G32B32_SINT
||
1548 image
->vk_format
== VK_FORMAT_R32G32B32_SFLOAT
) {
1549 /* Adjust the number of bytes between each row because
1550 * the pitch is actually the number of components per
1553 pLayout
->rowPitch
= surface
->u
.gfx9
.surf_pitch
* surface
->bpe
/ 3;
1555 assert(util_is_power_of_two_nonzero(surface
->bpe
));
1556 pLayout
->rowPitch
= surface
->u
.gfx9
.surf_pitch
* surface
->bpe
;
1559 pLayout
->arrayPitch
= surface
->u
.gfx9
.surf_slice_size
;
1560 pLayout
->depthPitch
= surface
->u
.gfx9
.surf_slice_size
;
1561 pLayout
->size
= surface
->u
.gfx9
.surf_slice_size
;
1562 if (image
->type
== VK_IMAGE_TYPE_3D
)
1563 pLayout
->size
*= u_minify(image
->info
.depth
, level
);
1565 pLayout
->offset
= plane
->offset
+ surface
->u
.legacy
.level
[level
].offset
+ (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4 * layer
;
1566 pLayout
->rowPitch
= surface
->u
.legacy
.level
[level
].nblk_x
* surface
->bpe
;
1567 pLayout
->arrayPitch
= (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4;
1568 pLayout
->depthPitch
= (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4;
1569 pLayout
->size
= (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4;
1570 if (image
->type
== VK_IMAGE_TYPE_3D
)
1571 pLayout
->size
*= u_minify(image
->info
.depth
, level
);
1577 radv_CreateImageView(VkDevice _device
,
1578 const VkImageViewCreateInfo
*pCreateInfo
,
1579 const VkAllocationCallbacks
*pAllocator
,
1582 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1583 struct radv_image_view
*view
;
1585 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1586 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1588 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1590 radv_image_view_init(view
, device
, pCreateInfo
);
1592 *pView
= radv_image_view_to_handle(view
);
1598 radv_DestroyImageView(VkDevice _device
, VkImageView _iview
,
1599 const VkAllocationCallbacks
*pAllocator
)
1601 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1602 RADV_FROM_HANDLE(radv_image_view
, iview
, _iview
);
1606 vk_free2(&device
->alloc
, pAllocator
, iview
);
1609 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1610 struct radv_device
*device
,
1611 const VkBufferViewCreateInfo
* pCreateInfo
)
1613 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCreateInfo
->buffer
);
1615 view
->bo
= buffer
->bo
;
1616 view
->range
= pCreateInfo
->range
== VK_WHOLE_SIZE
?
1617 buffer
->size
- pCreateInfo
->offset
: pCreateInfo
->range
;
1618 view
->vk_format
= pCreateInfo
->format
;
1620 radv_make_buffer_descriptor(device
, buffer
, view
->vk_format
,
1621 pCreateInfo
->offset
, view
->range
, view
->state
);
1625 radv_CreateBufferView(VkDevice _device
,
1626 const VkBufferViewCreateInfo
*pCreateInfo
,
1627 const VkAllocationCallbacks
*pAllocator
,
1628 VkBufferView
*pView
)
1630 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1631 struct radv_buffer_view
*view
;
1633 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1634 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1636 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1638 radv_buffer_view_init(view
, device
, pCreateInfo
);
1640 *pView
= radv_buffer_view_to_handle(view
);
1646 radv_DestroyBufferView(VkDevice _device
, VkBufferView bufferView
,
1647 const VkAllocationCallbacks
*pAllocator
)
1649 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1650 RADV_FROM_HANDLE(radv_buffer_view
, view
, bufferView
);
1655 vk_free2(&device
->alloc
, pAllocator
, view
);