2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "vk_format.h"
32 #include "radv_radeon_winsys.h"
35 #include "util/debug.h"
36 #include "util/u_atomic.h"
38 radv_choose_tiling(struct radv_device
*device
,
39 const struct radv_image_create_info
*create_info
)
41 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
43 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
) {
44 assert(pCreateInfo
->samples
<= 1);
45 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
48 if (!vk_format_is_compressed(pCreateInfo
->format
) &&
49 !vk_format_is_depth_or_stencil(pCreateInfo
->format
)
50 && device
->physical_device
->rad_info
.chip_class
<= VI
) {
51 /* this causes hangs in some VK CTS tests on GFX9. */
52 /* Textures with a very small height are recommended to be linear. */
53 if (pCreateInfo
->imageType
== VK_IMAGE_TYPE_1D
||
54 /* Only very thin and long 2D textures should benefit from
56 (pCreateInfo
->extent
.width
> 8 && pCreateInfo
->extent
.height
<= 2))
57 return RADEON_SURF_MODE_LINEAR_ALIGNED
;
60 /* MSAA resources must be 2D tiled. */
61 if (pCreateInfo
->samples
> 1)
62 return RADEON_SURF_MODE_2D
;
64 return RADEON_SURF_MODE_2D
;
68 radv_use_tc_compat_htile_for_image(struct radv_device
*device
,
69 const VkImageCreateInfo
*pCreateInfo
)
71 /* TC-compat HTILE is only available for GFX8+. */
72 if (device
->physical_device
->rad_info
.chip_class
< VI
)
75 if ((pCreateInfo
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
) ||
76 (pCreateInfo
->flags
& VK_IMAGE_CREATE_EXTENDED_USAGE_BIT
))
79 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
)
82 if (pCreateInfo
->mipLevels
> 1)
85 /* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
86 * tests - disable for now */
87 if (pCreateInfo
->samples
>= 2 &&
88 pCreateInfo
->format
== VK_FORMAT_D32_SFLOAT_S8_UINT
)
91 /* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only
92 * supports 32-bit. Though, it's possible to enable TC-compat for
93 * 16-bit depth surfaces if no Z planes are compressed.
95 if (pCreateInfo
->format
!= VK_FORMAT_D32_SFLOAT_S8_UINT
&&
96 pCreateInfo
->format
!= VK_FORMAT_D32_SFLOAT
&&
97 pCreateInfo
->format
!= VK_FORMAT_D16_UNORM
)
100 if (pCreateInfo
->flags
& VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
) {
101 const struct VkImageFormatListCreateInfoKHR
*format_list
=
102 (const struct VkImageFormatListCreateInfoKHR
*)
103 vk_find_struct_const(pCreateInfo
->pNext
,
104 IMAGE_FORMAT_LIST_CREATE_INFO_KHR
);
106 /* We have to ignore the existence of the list if viewFormatCount = 0 */
107 if (format_list
&& format_list
->viewFormatCount
) {
108 /* compatibility is transitive, so we only need to check
109 * one format with everything else.
111 for (unsigned i
= 0; i
< format_list
->viewFormatCount
; ++i
) {
112 if (pCreateInfo
->format
!= format_list
->pViewFormats
[i
])
124 radv_use_dcc_for_image(struct radv_device
*device
,
125 const struct radv_image
*image
,
126 const struct radv_image_create_info
*create_info
,
127 const VkImageCreateInfo
*pCreateInfo
)
129 bool dcc_compatible_formats
;
132 /* DCC (Delta Color Compression) is only available for GFX8+. */
133 if (device
->physical_device
->rad_info
.chip_class
< VI
)
136 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_DCC
)
139 /* FIXME: DCC is broken for shareable images starting with GFX9 */
140 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
144 /* TODO: Enable DCC for storage images. */
145 if ((pCreateInfo
->usage
& VK_IMAGE_USAGE_STORAGE_BIT
) ||
146 (pCreateInfo
->flags
& VK_IMAGE_CREATE_EXTENDED_USAGE_BIT
))
149 if (pCreateInfo
->tiling
== VK_IMAGE_TILING_LINEAR
)
152 if (vk_format_is_subsampled(pCreateInfo
->format
) ||
153 vk_format_get_plane_count(pCreateInfo
->format
) > 1)
156 /* TODO: Enable DCC for mipmaps and array layers. */
157 if (pCreateInfo
->mipLevels
> 1 || pCreateInfo
->arrayLayers
> 1)
160 if (create_info
->scanout
)
163 /* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet, while
164 * 2x can be enabled with an option.
166 if (pCreateInfo
->samples
> 2 ||
167 (pCreateInfo
->samples
== 2 &&
168 !device
->physical_device
->dcc_msaa_allowed
))
171 /* Determine if the formats are DCC compatible. */
172 dcc_compatible_formats
=
173 radv_is_colorbuffer_format_supported(pCreateInfo
->format
,
176 if (pCreateInfo
->flags
& VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT
) {
177 const struct VkImageFormatListCreateInfoKHR
*format_list
=
178 (const struct VkImageFormatListCreateInfoKHR
*)
179 vk_find_struct_const(pCreateInfo
->pNext
,
180 IMAGE_FORMAT_LIST_CREATE_INFO_KHR
);
182 /* We have to ignore the existence of the list if viewFormatCount = 0 */
183 if (format_list
&& format_list
->viewFormatCount
) {
184 /* compatibility is transitive, so we only need to check
185 * one format with everything else. */
186 for (unsigned i
= 0; i
< format_list
->viewFormatCount
; ++i
) {
187 if (!radv_dcc_formats_compatible(pCreateInfo
->format
,
188 format_list
->pViewFormats
[i
]))
189 dcc_compatible_formats
= false;
192 dcc_compatible_formats
= false;
196 if (!dcc_compatible_formats
)
203 radv_init_surface(struct radv_device
*device
,
204 const struct radv_image
*image
,
205 struct radeon_surf
*surface
,
207 const struct radv_image_create_info
*create_info
)
209 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
210 unsigned array_mode
= radv_choose_tiling(device
, create_info
);
211 VkFormat format
= vk_format_get_plane_format(pCreateInfo
->format
, plane_id
);
212 const struct vk_format_description
*desc
= vk_format_description(format
);
213 bool is_depth
, is_stencil
;
215 is_depth
= vk_format_has_depth(desc
);
216 is_stencil
= vk_format_has_stencil(desc
);
218 surface
->blk_w
= vk_format_get_blockwidth(format
);
219 surface
->blk_h
= vk_format_get_blockheight(format
);
221 surface
->bpe
= vk_format_get_blocksize(vk_format_depth_only(format
));
222 /* align byte per element on dword */
223 if (surface
->bpe
== 3) {
226 surface
->flags
= RADEON_SURF_SET(array_mode
, MODE
);
228 switch (pCreateInfo
->imageType
){
229 case VK_IMAGE_TYPE_1D
:
230 if (pCreateInfo
->arrayLayers
> 1)
231 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY
, TYPE
);
233 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_1D
, TYPE
);
235 case VK_IMAGE_TYPE_2D
:
236 if (pCreateInfo
->arrayLayers
> 1)
237 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY
, TYPE
);
239 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_2D
, TYPE
);
241 case VK_IMAGE_TYPE_3D
:
242 surface
->flags
|= RADEON_SURF_SET(RADEON_SURF_TYPE_3D
, TYPE
);
245 unreachable("unhandled image type");
249 surface
->flags
|= RADEON_SURF_ZBUFFER
;
250 if (radv_use_tc_compat_htile_for_image(device
, pCreateInfo
))
251 surface
->flags
|= RADEON_SURF_TC_COMPATIBLE_HTILE
;
255 surface
->flags
|= RADEON_SURF_SBUFFER
;
257 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
258 pCreateInfo
->imageType
== VK_IMAGE_TYPE_3D
&&
259 vk_format_get_blocksizebits(pCreateInfo
->format
) == 128 &&
260 vk_format_is_compressed(pCreateInfo
->format
))
261 surface
->flags
|= RADEON_SURF_NO_RENDER_TARGET
;
263 surface
->flags
|= RADEON_SURF_OPTIMIZE_FOR_SPACE
;
265 if (!radv_use_dcc_for_image(device
, image
, create_info
, pCreateInfo
))
266 surface
->flags
|= RADEON_SURF_DISABLE_DCC
;
268 if (create_info
->scanout
)
269 surface
->flags
|= RADEON_SURF_SCANOUT
;
273 static uint32_t si_get_bo_metadata_word1(struct radv_device
*device
)
275 return (ATI_VENDOR_ID
<< 16) | device
->physical_device
->rad_info
.pci_id
;
278 static inline unsigned
279 si_tile_mode_index(const struct radv_image_plane
*plane
, unsigned level
, bool stencil
)
282 return plane
->surface
.u
.legacy
.stencil_tiling_index
[level
];
284 return plane
->surface
.u
.legacy
.tiling_index
[level
];
287 static unsigned radv_map_swizzle(unsigned swizzle
)
291 return V_008F0C_SQ_SEL_Y
;
293 return V_008F0C_SQ_SEL_Z
;
295 return V_008F0C_SQ_SEL_W
;
297 return V_008F0C_SQ_SEL_0
;
299 return V_008F0C_SQ_SEL_1
;
300 default: /* VK_SWIZZLE_X */
301 return V_008F0C_SQ_SEL_X
;
306 radv_make_buffer_descriptor(struct radv_device
*device
,
307 struct radv_buffer
*buffer
,
313 const struct vk_format_description
*desc
;
315 uint64_t gpu_address
= radv_buffer_get_va(buffer
->bo
);
316 uint64_t va
= gpu_address
+ buffer
->offset
;
317 unsigned num_format
, data_format
;
319 desc
= vk_format_description(vk_format
);
320 first_non_void
= vk_format_get_first_non_void_channel(vk_format
);
321 stride
= desc
->block
.bits
/ 8;
323 num_format
= radv_translate_buffer_numformat(desc
, first_non_void
);
324 data_format
= radv_translate_buffer_dataformat(desc
, first_non_void
);
328 state
[1] = S_008F04_BASE_ADDRESS_HI(va
>> 32) |
329 S_008F04_STRIDE(stride
);
331 if (device
->physical_device
->rad_info
.chip_class
!= VI
&& stride
) {
336 state
[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc
->swizzle
[0])) |
337 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc
->swizzle
[1])) |
338 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc
->swizzle
[2])) |
339 S_008F0C_DST_SEL_W(radv_map_swizzle(desc
->swizzle
[3])) |
340 S_008F0C_NUM_FORMAT(num_format
) |
341 S_008F0C_DATA_FORMAT(data_format
);
345 si_set_mutable_tex_desc_fields(struct radv_device
*device
,
346 struct radv_image
*image
,
347 const struct legacy_surf_level
*base_level_info
,
349 unsigned base_level
, unsigned first_level
,
350 unsigned block_width
, bool is_stencil
,
351 bool is_storage_image
, uint32_t *state
)
353 struct radv_image_plane
*plane
= &image
->planes
[plane_id
];
354 uint64_t gpu_address
= image
->bo
? radv_buffer_get_va(image
->bo
) + image
->offset
: 0;
355 uint64_t va
= gpu_address
+ plane
->offset
;
356 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
357 uint64_t meta_va
= 0;
358 if (chip_class
>= GFX9
) {
360 va
+= plane
->surface
.u
.gfx9
.stencil_offset
;
362 va
+= plane
->surface
.u
.gfx9
.surf_offset
;
364 va
+= base_level_info
->offset
;
367 if (chip_class
>= GFX9
||
368 base_level_info
->mode
== RADEON_SURF_MODE_2D
)
369 state
[0] |= plane
->surface
.tile_swizzle
;
370 state
[1] &= C_008F14_BASE_ADDRESS_HI
;
371 state
[1] |= S_008F14_BASE_ADDRESS_HI(va
>> 40);
373 if (chip_class
>= VI
) {
374 state
[6] &= C_008F28_COMPRESSION_EN
;
376 if (!is_storage_image
&& radv_dcc_enabled(image
, first_level
)) {
377 meta_va
= gpu_address
+ image
->dcc_offset
;
378 if (chip_class
<= VI
)
379 meta_va
+= base_level_info
->dcc_offset
;
380 } else if (!is_storage_image
&&
381 radv_image_is_tc_compat_htile(image
)) {
382 meta_va
= gpu_address
+ image
->htile_offset
;
386 state
[6] |= S_008F28_COMPRESSION_EN(1);
387 state
[7] = meta_va
>> 8;
388 state
[7] |= plane
->surface
.tile_swizzle
;
392 if (chip_class
>= GFX9
) {
393 state
[3] &= C_008F1C_SW_MODE
;
394 state
[4] &= C_008F20_PITCH_GFX9
;
397 state
[3] |= S_008F1C_SW_MODE(plane
->surface
.u
.gfx9
.stencil
.swizzle_mode
);
398 state
[4] |= S_008F20_PITCH_GFX9(plane
->surface
.u
.gfx9
.stencil
.epitch
);
400 state
[3] |= S_008F1C_SW_MODE(plane
->surface
.u
.gfx9
.surf
.swizzle_mode
);
401 state
[4] |= S_008F20_PITCH_GFX9(plane
->surface
.u
.gfx9
.surf
.epitch
);
404 state
[5] &= C_008F24_META_DATA_ADDRESS
&
405 C_008F24_META_PIPE_ALIGNED
&
406 C_008F24_META_RB_ALIGNED
;
408 struct gfx9_surf_meta_flags meta
;
410 if (image
->dcc_offset
)
411 meta
= plane
->surface
.u
.gfx9
.dcc
;
413 meta
= plane
->surface
.u
.gfx9
.htile
;
415 state
[5] |= S_008F24_META_DATA_ADDRESS(meta_va
>> 40) |
416 S_008F24_META_PIPE_ALIGNED(meta
.pipe_aligned
) |
417 S_008F24_META_RB_ALIGNED(meta
.rb_aligned
);
421 unsigned pitch
= base_level_info
->nblk_x
* block_width
;
422 unsigned index
= si_tile_mode_index(plane
, base_level
, is_stencil
);
424 state
[3] &= C_008F1C_TILING_INDEX
;
425 state
[3] |= S_008F1C_TILING_INDEX(index
);
426 state
[4] &= C_008F20_PITCH_GFX6
;
427 state
[4] |= S_008F20_PITCH_GFX6(pitch
- 1);
431 static unsigned radv_tex_dim(VkImageType image_type
, VkImageViewType view_type
,
432 unsigned nr_layers
, unsigned nr_samples
, bool is_storage_image
, bool gfx9
)
434 if (view_type
== VK_IMAGE_VIEW_TYPE_CUBE
|| view_type
== VK_IMAGE_VIEW_TYPE_CUBE_ARRAY
)
435 return is_storage_image
? V_008F1C_SQ_RSRC_IMG_2D_ARRAY
: V_008F1C_SQ_RSRC_IMG_CUBE
;
437 /* GFX9 allocates 1D textures as 2D. */
438 if (gfx9
&& image_type
== VK_IMAGE_TYPE_1D
)
439 image_type
= VK_IMAGE_TYPE_2D
;
440 switch (image_type
) {
441 case VK_IMAGE_TYPE_1D
:
442 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY
: V_008F1C_SQ_RSRC_IMG_1D
;
443 case VK_IMAGE_TYPE_2D
:
445 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
: V_008F1C_SQ_RSRC_IMG_2D_MSAA
;
447 return nr_layers
> 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY
: V_008F1C_SQ_RSRC_IMG_2D
;
448 case VK_IMAGE_TYPE_3D
:
449 if (view_type
== VK_IMAGE_VIEW_TYPE_3D
)
450 return V_008F1C_SQ_RSRC_IMG_3D
;
452 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY
;
454 unreachable("illegal image type");
458 static unsigned gfx9_border_color_swizzle(const enum vk_swizzle swizzle
[4])
460 unsigned bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
462 if (swizzle
[3] == VK_SWIZZLE_X
) {
463 /* For the pre-defined border color values (white, opaque
464 * black, transparent black), the only thing that matters is
465 * that the alpha channel winds up in the correct place
466 * (because the RGB channels are all the same) so either of
467 * these enumerations will work.
469 if (swizzle
[2] == VK_SWIZZLE_Y
)
470 bc_swizzle
= V_008F20_BC_SWIZZLE_WZYX
;
472 bc_swizzle
= V_008F20_BC_SWIZZLE_WXYZ
;
473 } else if (swizzle
[0] == VK_SWIZZLE_X
) {
474 if (swizzle
[1] == VK_SWIZZLE_Y
)
475 bc_swizzle
= V_008F20_BC_SWIZZLE_XYZW
;
477 bc_swizzle
= V_008F20_BC_SWIZZLE_XWYZ
;
478 } else if (swizzle
[1] == VK_SWIZZLE_X
) {
479 bc_swizzle
= V_008F20_BC_SWIZZLE_YXWZ
;
480 } else if (swizzle
[2] == VK_SWIZZLE_X
) {
481 bc_swizzle
= V_008F20_BC_SWIZZLE_ZYXW
;
488 * Build the sampler view descriptor for a texture.
491 si_make_texture_descriptor(struct radv_device
*device
,
492 struct radv_image
*image
,
493 bool is_storage_image
,
494 VkImageViewType view_type
,
496 const VkComponentMapping
*mapping
,
497 unsigned first_level
, unsigned last_level
,
498 unsigned first_layer
, unsigned last_layer
,
499 unsigned width
, unsigned height
, unsigned depth
,
501 uint32_t *fmask_state
)
503 const struct vk_format_description
*desc
;
504 enum vk_swizzle swizzle
[4];
506 unsigned num_format
, data_format
, type
;
508 desc
= vk_format_description(vk_format
);
510 if (desc
->colorspace
== VK_FORMAT_COLORSPACE_ZS
) {
511 const unsigned char swizzle_xxxx
[4] = {0, 0, 0, 0};
512 vk_format_compose_swizzles(mapping
, swizzle_xxxx
, swizzle
);
514 vk_format_compose_swizzles(mapping
, desc
->swizzle
, swizzle
);
517 first_non_void
= vk_format_get_first_non_void_channel(vk_format
);
519 num_format
= radv_translate_tex_numformat(vk_format
, desc
, first_non_void
);
520 if (num_format
== ~0) {
524 data_format
= radv_translate_tex_dataformat(vk_format
, desc
, first_non_void
);
525 if (data_format
== ~0) {
529 /* S8 with either Z16 or Z32 HTILE need a special format. */
530 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
531 vk_format
== VK_FORMAT_S8_UINT
&&
532 radv_image_is_tc_compat_htile(image
)) {
533 if (image
->vk_format
== VK_FORMAT_D32_SFLOAT_S8_UINT
)
534 data_format
= V_008F14_IMG_DATA_FORMAT_S8_32
;
535 else if (image
->vk_format
== VK_FORMAT_D16_UNORM_S8_UINT
)
536 data_format
= V_008F14_IMG_DATA_FORMAT_S8_16
;
538 type
= radv_tex_dim(image
->type
, view_type
, image
->info
.array_size
, image
->info
.samples
,
539 is_storage_image
, device
->physical_device
->rad_info
.chip_class
>= GFX9
);
540 if (type
== V_008F1C_SQ_RSRC_IMG_1D_ARRAY
) {
542 depth
= image
->info
.array_size
;
543 } else if (type
== V_008F1C_SQ_RSRC_IMG_2D_ARRAY
||
544 type
== V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY
) {
545 if (view_type
!= VK_IMAGE_VIEW_TYPE_3D
)
546 depth
= image
->info
.array_size
;
547 } else if (type
== V_008F1C_SQ_RSRC_IMG_CUBE
)
548 depth
= image
->info
.array_size
/ 6;
551 state
[1] = (S_008F14_DATA_FORMAT_GFX6(data_format
) |
552 S_008F14_NUM_FORMAT_GFX6(num_format
));
553 state
[2] = (S_008F18_WIDTH(width
- 1) |
554 S_008F18_HEIGHT(height
- 1) |
555 S_008F18_PERF_MOD(4));
556 state
[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle
[0])) |
557 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle
[1])) |
558 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle
[2])) |
559 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle
[3])) |
560 S_008F1C_BASE_LEVEL(image
->info
.samples
> 1 ?
562 S_008F1C_LAST_LEVEL(image
->info
.samples
> 1 ?
563 util_logbase2(image
->info
.samples
) :
565 S_008F1C_TYPE(type
));
567 state
[5] = S_008F24_BASE_ARRAY(first_layer
);
571 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
572 unsigned bc_swizzle
= gfx9_border_color_swizzle(swizzle
);
574 /* Depth is the last accessible layer on Gfx9.
575 * The hw doesn't need to know the total number of layers.
577 if (type
== V_008F1C_SQ_RSRC_IMG_3D
)
578 state
[4] |= S_008F20_DEPTH(depth
- 1);
580 state
[4] |= S_008F20_DEPTH(last_layer
);
582 state
[4] |= S_008F20_BC_SWIZZLE(bc_swizzle
);
583 state
[5] |= S_008F24_MAX_MIP(image
->info
.samples
> 1 ?
584 util_logbase2(image
->info
.samples
) :
585 image
->info
.levels
- 1);
587 state
[3] |= S_008F1C_POW2_PAD(image
->info
.levels
> 1);
588 state
[4] |= S_008F20_DEPTH(depth
- 1);
589 state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
591 if (image
->dcc_offset
) {
592 unsigned swap
= radv_translate_colorswap(vk_format
, FALSE
);
594 state
[6] = S_008F28_ALPHA_IS_ON_MSB(swap
<= 1);
596 /* The last dword is unused by hw. The shader uses it to clear
597 * bits in the first dword of sampler state.
599 if (device
->physical_device
->rad_info
.chip_class
<= CIK
&& image
->info
.samples
<= 1) {
600 if (first_level
== last_level
)
601 state
[7] = C_008F30_MAX_ANISO_RATIO
;
603 state
[7] = 0xffffffff;
607 /* Initialize the sampler view for FMASK. */
608 if (radv_image_has_fmask(image
)) {
609 uint32_t fmask_format
, num_format
;
610 uint64_t gpu_address
= radv_buffer_get_va(image
->bo
);
613 assert(image
->plane_count
== 1);
615 va
= gpu_address
+ image
->offset
+ image
->fmask
.offset
;
617 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
618 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK
;
619 switch (image
->info
.samples
) {
621 num_format
= V_008F14_IMG_FMASK_8_2_2
;
624 num_format
= V_008F14_IMG_FMASK_8_4_4
;
627 num_format
= V_008F14_IMG_FMASK_32_8_8
;
630 unreachable("invalid nr_samples");
633 switch (image
->info
.samples
) {
635 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2
;
638 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4
;
641 fmask_format
= V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8
;
645 fmask_format
= V_008F14_IMG_DATA_FORMAT_INVALID
;
647 num_format
= V_008F14_IMG_NUM_FORMAT_UINT
;
650 fmask_state
[0] = va
>> 8;
651 fmask_state
[0] |= image
->fmask
.tile_swizzle
;
652 fmask_state
[1] = S_008F14_BASE_ADDRESS_HI(va
>> 40) |
653 S_008F14_DATA_FORMAT_GFX6(fmask_format
) |
654 S_008F14_NUM_FORMAT_GFX6(num_format
);
655 fmask_state
[2] = S_008F18_WIDTH(width
- 1) |
656 S_008F18_HEIGHT(height
- 1);
657 fmask_state
[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X
) |
658 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X
) |
659 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X
) |
660 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X
) |
661 S_008F1C_TYPE(radv_tex_dim(image
->type
, view_type
, image
->info
.array_size
, 0, false, false));
663 fmask_state
[5] = S_008F24_BASE_ARRAY(first_layer
);
667 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
668 fmask_state
[3] |= S_008F1C_SW_MODE(image
->planes
[0].surface
.u
.gfx9
.fmask
.swizzle_mode
);
669 fmask_state
[4] |= S_008F20_DEPTH(last_layer
) |
670 S_008F20_PITCH_GFX9(image
->planes
[0].surface
.u
.gfx9
.fmask
.epitch
);
671 fmask_state
[5] |= S_008F24_META_PIPE_ALIGNED(image
->planes
[0].surface
.u
.gfx9
.cmask
.pipe_aligned
) |
672 S_008F24_META_RB_ALIGNED(image
->planes
[0].surface
.u
.gfx9
.cmask
.rb_aligned
);
674 fmask_state
[3] |= S_008F1C_TILING_INDEX(image
->fmask
.tile_mode_index
);
675 fmask_state
[4] |= S_008F20_DEPTH(depth
- 1) |
676 S_008F20_PITCH_GFX6(image
->fmask
.pitch_in_pixels
- 1);
677 fmask_state
[5] |= S_008F24_LAST_ARRAY(last_layer
);
679 } else if (fmask_state
)
680 memset(fmask_state
, 0, 8 * 4);
684 radv_query_opaque_metadata(struct radv_device
*device
,
685 struct radv_image
*image
,
686 struct radeon_bo_metadata
*md
)
688 static const VkComponentMapping fixedmapping
;
691 assert(image
->plane_count
== 1);
693 /* Metadata image format format version 1:
694 * [0] = 1 (metadata format identifier)
695 * [1] = (VENDOR_ID << 16) | PCI_ID
696 * [2:9] = image descriptor for the whole resource
697 * [2] is always 0, because the base address is cleared
698 * [9] is the DCC offset bits [39:8] from the beginning of
700 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
702 md
->metadata
[0] = 1; /* metadata image format version 1 */
704 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
705 md
->metadata
[1] = si_get_bo_metadata_word1(device
);
708 si_make_texture_descriptor(device
, image
, false,
709 (VkImageViewType
)image
->type
, image
->vk_format
,
710 &fixedmapping
, 0, image
->info
.levels
- 1, 0,
711 image
->info
.array_size
- 1,
712 image
->info
.width
, image
->info
.height
,
716 si_set_mutable_tex_desc_fields(device
, image
, &image
->planes
[0].surface
.u
.legacy
.level
[0], 0, 0, 0,
717 image
->planes
[0].surface
.blk_w
, false, false, desc
);
719 /* Clear the base address and set the relative DCC offset. */
721 desc
[1] &= C_008F14_BASE_ADDRESS_HI
;
722 desc
[7] = image
->dcc_offset
>> 8;
724 /* Dwords [2:9] contain the image descriptor. */
725 memcpy(&md
->metadata
[2], desc
, sizeof(desc
));
727 /* Dwords [10:..] contain the mipmap level offsets. */
728 if (device
->physical_device
->rad_info
.chip_class
<= VI
) {
729 for (i
= 0; i
<= image
->info
.levels
- 1; i
++)
730 md
->metadata
[10+i
] = image
->planes
[0].surface
.u
.legacy
.level
[i
].offset
>> 8;
731 md
->size_metadata
= (11 + image
->info
.levels
- 1) * 4;
736 radv_init_metadata(struct radv_device
*device
,
737 struct radv_image
*image
,
738 struct radeon_bo_metadata
*metadata
)
740 struct radeon_surf
*surface
= &image
->planes
[0].surface
;
742 memset(metadata
, 0, sizeof(*metadata
));
744 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
745 metadata
->u
.gfx9
.swizzle_mode
= surface
->u
.gfx9
.surf
.swizzle_mode
;
747 metadata
->u
.legacy
.microtile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_1D
?
748 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
749 metadata
->u
.legacy
.macrotile
= surface
->u
.legacy
.level
[0].mode
>= RADEON_SURF_MODE_2D
?
750 RADEON_LAYOUT_TILED
: RADEON_LAYOUT_LINEAR
;
751 metadata
->u
.legacy
.pipe_config
= surface
->u
.legacy
.pipe_config
;
752 metadata
->u
.legacy
.bankw
= surface
->u
.legacy
.bankw
;
753 metadata
->u
.legacy
.bankh
= surface
->u
.legacy
.bankh
;
754 metadata
->u
.legacy
.tile_split
= surface
->u
.legacy
.tile_split
;
755 metadata
->u
.legacy
.mtilea
= surface
->u
.legacy
.mtilea
;
756 metadata
->u
.legacy
.num_banks
= surface
->u
.legacy
.num_banks
;
757 metadata
->u
.legacy
.stride
= surface
->u
.legacy
.level
[0].nblk_x
* surface
->bpe
;
758 metadata
->u
.legacy
.scanout
= (surface
->flags
& RADEON_SURF_SCANOUT
) != 0;
760 radv_query_opaque_metadata(device
, image
, metadata
);
763 /* The number of samples can be specified independently of the texture. */
765 radv_image_get_fmask_info(struct radv_device
*device
,
766 struct radv_image
*image
,
768 struct radv_fmask_info
*out
)
770 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
771 out
->alignment
= image
->planes
[0].surface
.fmask_alignment
;
772 out
->size
= image
->planes
[0].surface
.fmask_size
;
773 out
->tile_swizzle
= image
->planes
[0].surface
.fmask_tile_swizzle
;
777 out
->slice_tile_max
= image
->planes
[0].surface
.u
.legacy
.fmask
.slice_tile_max
;
778 out
->tile_mode_index
= image
->planes
[0].surface
.u
.legacy
.fmask
.tiling_index
;
779 out
->pitch_in_pixels
= image
->planes
[0].surface
.u
.legacy
.fmask
.pitch_in_pixels
;
780 out
->bank_height
= image
->planes
[0].surface
.u
.legacy
.fmask
.bankh
;
781 out
->tile_swizzle
= image
->planes
[0].surface
.fmask_tile_swizzle
;
782 out
->alignment
= image
->planes
[0].surface
.fmask_alignment
;
783 out
->size
= image
->planes
[0].surface
.fmask_size
;
785 assert(!out
->tile_swizzle
|| !image
->shareable
);
789 radv_image_alloc_fmask(struct radv_device
*device
,
790 struct radv_image
*image
)
792 radv_image_get_fmask_info(device
, image
, image
->info
.samples
, &image
->fmask
);
794 image
->fmask
.offset
= align64(image
->size
, image
->fmask
.alignment
);
795 image
->size
= image
->fmask
.offset
+ image
->fmask
.size
;
796 image
->alignment
= MAX2(image
->alignment
, image
->fmask
.alignment
);
800 radv_image_get_cmask_info(struct radv_device
*device
,
801 struct radv_image
*image
,
802 struct radv_cmask_info
*out
)
804 unsigned pipe_interleave_bytes
= device
->physical_device
->rad_info
.pipe_interleave_bytes
;
805 unsigned num_pipes
= device
->physical_device
->rad_info
.num_tile_pipes
;
806 unsigned cl_width
, cl_height
;
808 assert(image
->plane_count
== 1);
810 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
811 out
->alignment
= image
->planes
[0].surface
.cmask_alignment
;
812 out
->size
= image
->planes
[0].surface
.cmask_size
;
829 case 16: /* Hawaii */
838 unsigned base_align
= num_pipes
* pipe_interleave_bytes
;
840 unsigned width
= align(image
->planes
[0].surface
.u
.legacy
.level
[0].nblk_x
, cl_width
*8);
841 unsigned height
= align(image
->planes
[0].surface
.u
.legacy
.level
[0].nblk_y
, cl_height
*8);
842 unsigned slice_elements
= (width
* height
) / (8*8);
844 /* Each element of CMASK is a nibble. */
845 unsigned slice_bytes
= slice_elements
/ 2;
847 out
->slice_tile_max
= (width
* height
) / (128*128);
848 if (out
->slice_tile_max
)
849 out
->slice_tile_max
-= 1;
851 out
->alignment
= MAX2(256, base_align
);
852 out
->size
= (image
->type
== VK_IMAGE_TYPE_3D
? image
->info
.depth
: image
->info
.array_size
) *
853 align(slice_bytes
, base_align
);
857 radv_image_alloc_cmask(struct radv_device
*device
,
858 struct radv_image
*image
)
860 uint32_t clear_value_size
= 0;
861 radv_image_get_cmask_info(device
, image
, &image
->cmask
);
863 image
->cmask
.offset
= align64(image
->size
, image
->cmask
.alignment
);
864 /* + 8 for storing the clear values */
865 if (!image
->clear_value_offset
) {
866 image
->clear_value_offset
= image
->cmask
.offset
+ image
->cmask
.size
;
867 clear_value_size
= 8;
869 image
->size
= image
->cmask
.offset
+ image
->cmask
.size
+ clear_value_size
;
870 image
->alignment
= MAX2(image
->alignment
, image
->cmask
.alignment
);
874 radv_image_alloc_dcc(struct radv_image
*image
)
876 assert(image
->plane_count
== 1);
878 image
->dcc_offset
= align64(image
->size
, image
->planes
[0].surface
.dcc_alignment
);
879 /* + 16 for storing the clear values + dcc pred */
880 image
->clear_value_offset
= image
->dcc_offset
+ image
->planes
[0].surface
.dcc_size
;
881 image
->fce_pred_offset
= image
->clear_value_offset
+ 8;
882 image
->dcc_pred_offset
= image
->clear_value_offset
+ 16;
883 image
->size
= image
->dcc_offset
+ image
->planes
[0].surface
.dcc_size
+ 24;
884 image
->alignment
= MAX2(image
->alignment
, image
->planes
[0].surface
.dcc_alignment
);
888 radv_image_alloc_htile(struct radv_image
*image
)
890 image
->htile_offset
= align64(image
->size
, image
->planes
[0].surface
.htile_alignment
);
892 /* + 8 for storing the clear values */
893 image
->clear_value_offset
= image
->htile_offset
+ image
->planes
[0].surface
.htile_size
;
894 image
->size
= image
->clear_value_offset
+ 8;
895 if (radv_image_is_tc_compat_htile(image
)) {
896 /* Metadata for the TC-compatible HTILE hardware bug which
897 * have to be fixed by updating ZRANGE_PRECISION when doing
898 * fast depth clears to 0.0f.
900 image
->tc_compat_zrange_offset
= image
->clear_value_offset
+ 8;
901 image
->size
= image
->clear_value_offset
+ 16;
903 image
->alignment
= align64(image
->alignment
, image
->planes
[0].surface
.htile_alignment
);
907 radv_image_can_enable_dcc_or_cmask(struct radv_image
*image
)
909 if (image
->info
.samples
<= 1 &&
910 image
->info
.width
* image
->info
.height
<= 512 * 512) {
911 /* Do not enable CMASK or DCC for small surfaces where the cost
912 * of the eliminate pass can be higher than the benefit of fast
913 * clear. RadeonSI does this, but the image threshold is
919 return image
->usage
& VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT
&&
920 (image
->exclusive
|| image
->queue_family_mask
== 1);
924 radv_image_can_enable_dcc(struct radv_image
*image
)
926 return radv_image_can_enable_dcc_or_cmask(image
) &&
927 radv_image_has_dcc(image
);
931 radv_image_can_enable_cmask(struct radv_image
*image
)
933 if (image
->planes
[0].surface
.bpe
> 8 && image
->info
.samples
== 1) {
934 /* Do not enable CMASK for non-MSAA images (fast color clear)
935 * because 128 bit formats are not supported, but FMASK might
941 return radv_image_can_enable_dcc_or_cmask(image
) &&
942 image
->info
.levels
== 1 &&
943 image
->info
.depth
== 1 &&
944 !image
->planes
[0].surface
.is_linear
;
948 radv_image_can_enable_fmask(struct radv_image
*image
)
950 return image
->info
.samples
> 1 && vk_format_is_color(image
->vk_format
);
954 radv_image_can_enable_htile(struct radv_image
*image
)
956 return radv_image_has_htile(image
) &&
957 image
->info
.levels
== 1 &&
958 image
->info
.width
* image
->info
.height
>= 8 * 8;
961 static void radv_image_disable_dcc(struct radv_image
*image
)
963 for (unsigned i
= 0; i
< image
->plane_count
; ++i
)
964 image
->planes
[i
].surface
.dcc_size
= 0;
967 static void radv_image_disable_htile(struct radv_image
*image
)
969 for (unsigned i
= 0; i
< image
->plane_count
; ++i
)
970 image
->planes
[i
].surface
.htile_size
= 0;
974 radv_image_create(VkDevice _device
,
975 const struct radv_image_create_info
*create_info
,
976 const VkAllocationCallbacks
* alloc
,
979 RADV_FROM_HANDLE(radv_device
, device
, _device
);
980 const VkImageCreateInfo
*pCreateInfo
= create_info
->vk_info
;
981 struct radv_image
*image
= NULL
;
982 assert(pCreateInfo
->sType
== VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO
);
984 const unsigned plane_count
= vk_format_get_plane_count(pCreateInfo
->format
);
985 const size_t image_struct_size
= sizeof(*image
) + sizeof(struct radv_image_plane
) * plane_count
;
987 radv_assert(pCreateInfo
->mipLevels
> 0);
988 radv_assert(pCreateInfo
->arrayLayers
> 0);
989 radv_assert(pCreateInfo
->samples
> 0);
990 radv_assert(pCreateInfo
->extent
.width
> 0);
991 radv_assert(pCreateInfo
->extent
.height
> 0);
992 radv_assert(pCreateInfo
->extent
.depth
> 0);
994 image
= vk_zalloc2(&device
->alloc
, alloc
, image_struct_size
, 8,
995 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
997 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
999 image
->type
= pCreateInfo
->imageType
;
1000 image
->info
.width
= pCreateInfo
->extent
.width
;
1001 image
->info
.height
= pCreateInfo
->extent
.height
;
1002 image
->info
.depth
= pCreateInfo
->extent
.depth
;
1003 image
->info
.samples
= pCreateInfo
->samples
;
1004 image
->info
.storage_samples
= pCreateInfo
->samples
;
1005 image
->info
.array_size
= pCreateInfo
->arrayLayers
;
1006 image
->info
.levels
= pCreateInfo
->mipLevels
;
1007 image
->info
.num_channels
= vk_format_get_nr_components(pCreateInfo
->format
);
1009 image
->vk_format
= pCreateInfo
->format
;
1010 image
->tiling
= pCreateInfo
->tiling
;
1011 image
->usage
= pCreateInfo
->usage
;
1012 image
->flags
= pCreateInfo
->flags
;
1014 image
->exclusive
= pCreateInfo
->sharingMode
== VK_SHARING_MODE_EXCLUSIVE
;
1015 if (pCreateInfo
->sharingMode
== VK_SHARING_MODE_CONCURRENT
) {
1016 for (uint32_t i
= 0; i
< pCreateInfo
->queueFamilyIndexCount
; ++i
)
1017 if (pCreateInfo
->pQueueFamilyIndices
[i
] == VK_QUEUE_FAMILY_EXTERNAL
)
1018 image
->queue_family_mask
|= (1u << RADV_MAX_QUEUE_FAMILIES
) - 1u;
1020 image
->queue_family_mask
|= 1u << pCreateInfo
->pQueueFamilyIndices
[i
];
1023 image
->shareable
= vk_find_struct_const(pCreateInfo
->pNext
,
1024 EXTERNAL_MEMORY_IMAGE_CREATE_INFO
) != NULL
;
1025 if (!vk_format_is_depth_or_stencil(pCreateInfo
->format
) && !create_info
->scanout
&& !image
->shareable
) {
1026 image
->info
.surf_index
= &device
->image_mrt_offset_counter
;
1029 image
->plane_count
= plane_count
;
1031 image
->alignment
= 1;
1032 for (unsigned plane
= 0; plane
< plane_count
; ++plane
) {
1033 struct ac_surf_info info
= image
->info
;
1034 radv_init_surface(device
, image
, &image
->planes
[plane
].surface
, plane
, create_info
);
1037 const struct vk_format_description
*desc
= vk_format_description(pCreateInfo
->format
);
1038 assert(info
.width
% desc
->width_divisor
== 0);
1039 assert(info
.height
% desc
->height_divisor
== 0);
1041 info
.width
/= desc
->width_divisor
;
1042 info
.height
/= desc
->height_divisor
;
1045 device
->ws
->surface_init(device
->ws
, &info
, &image
->planes
[plane
].surface
);
1047 image
->planes
[plane
].offset
= align(image
->size
, image
->planes
[plane
].surface
.surf_alignment
);
1048 image
->size
= image
->planes
[plane
].offset
+ image
->planes
[plane
].surface
.surf_size
;
1049 image
->alignment
= image
->planes
[plane
].surface
.surf_alignment
;
1051 image
->planes
[plane
].format
= vk_format_get_plane_format(image
->vk_format
, plane
);
1054 if (!create_info
->no_metadata_planes
) {
1055 /* Try to enable DCC first. */
1056 if (radv_image_can_enable_dcc(image
)) {
1057 radv_image_alloc_dcc(image
);
1058 if (image
->info
.samples
> 1) {
1059 /* CMASK should be enabled because DCC fast
1060 * clear with MSAA needs it.
1062 assert(radv_image_can_enable_cmask(image
));
1063 radv_image_alloc_cmask(device
, image
);
1066 /* When DCC cannot be enabled, try CMASK. */
1067 radv_image_disable_dcc(image
);
1068 if (radv_image_can_enable_cmask(image
)) {
1069 radv_image_alloc_cmask(device
, image
);
1073 /* Try to enable FMASK for multisampled images. */
1074 if (radv_image_can_enable_fmask(image
)) {
1075 radv_image_alloc_fmask(device
, image
);
1077 /* Otherwise, try to enable HTILE for depth surfaces. */
1078 if (radv_image_can_enable_htile(image
) &&
1079 !(device
->instance
->debug_flags
& RADV_DEBUG_NO_HIZ
)) {
1080 image
->tc_compatible_htile
= image
->planes
[0].surface
.flags
& RADEON_SURF_TC_COMPATIBLE_HTILE
;
1081 radv_image_alloc_htile(image
);
1083 radv_image_disable_htile(image
);
1087 radv_image_disable_dcc(image
);
1088 radv_image_disable_htile(image
);
1091 if (pCreateInfo
->flags
& VK_IMAGE_CREATE_SPARSE_BINDING_BIT
) {
1092 image
->alignment
= MAX2(image
->alignment
, 4096);
1093 image
->size
= align64(image
->size
, image
->alignment
);
1096 image
->bo
= device
->ws
->buffer_create(device
->ws
, image
->size
, image
->alignment
,
1097 0, RADEON_FLAG_VIRTUAL
, RADV_BO_PRIORITY_VIRTUAL
);
1099 vk_free2(&device
->alloc
, alloc
, image
);
1100 return vk_error(device
->instance
, VK_ERROR_OUT_OF_DEVICE_MEMORY
);
1104 *pImage
= radv_image_to_handle(image
);
1110 radv_image_view_make_descriptor(struct radv_image_view
*iview
,
1111 struct radv_device
*device
,
1113 const VkComponentMapping
*components
,
1114 bool is_storage_image
, unsigned plane_id
,
1115 unsigned descriptor_plane_id
)
1117 struct radv_image
*image
= iview
->image
;
1118 struct radv_image_plane
*plane
= &image
->planes
[plane_id
];
1119 const struct vk_format_description
*format_desc
= vk_format_description(image
->vk_format
);
1120 bool is_stencil
= iview
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
;
1122 union radv_descriptor
*descriptor
;
1123 uint32_t hw_level
= 0;
1125 if (is_storage_image
) {
1126 descriptor
= &iview
->storage_descriptor
;
1128 descriptor
= &iview
->descriptor
;
1131 assert(vk_format_get_plane_count(vk_format
) == 1);
1132 assert(plane
->surface
.blk_w
% vk_format_get_blockwidth(plane
->format
) == 0);
1133 blk_w
= plane
->surface
.blk_w
/ vk_format_get_blockwidth(plane
->format
) * vk_format_get_blockwidth(vk_format
);
1135 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1136 hw_level
= iview
->base_mip
;
1137 si_make_texture_descriptor(device
, image
, is_storage_image
,
1141 hw_level
, hw_level
+ iview
->level_count
- 1,
1143 iview
->base_layer
+ iview
->layer_count
- 1,
1144 iview
->extent
.width
/ (plane_id
? format_desc
->width_divisor
: 1),
1145 iview
->extent
.height
/ (plane_id
? format_desc
->height_divisor
: 1),
1146 iview
->extent
.depth
,
1147 descriptor
->plane_descriptors
[descriptor_plane_id
],
1148 descriptor_plane_id
? NULL
: descriptor
->fmask_descriptor
);
1150 const struct legacy_surf_level
*base_level_info
= NULL
;
1151 if (device
->physical_device
->rad_info
.chip_class
<= GFX9
) {
1153 base_level_info
= &plane
->surface
.u
.legacy
.stencil_level
[iview
->base_mip
];
1155 base_level_info
= &plane
->surface
.u
.legacy
.level
[iview
->base_mip
];
1157 si_set_mutable_tex_desc_fields(device
, image
,
1162 blk_w
, is_stencil
, is_storage_image
, descriptor
->plane_descriptors
[descriptor_plane_id
]);
1166 radv_plane_from_aspect(VkImageAspectFlags mask
)
1169 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
1171 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
1179 radv_get_aspect_format(struct radv_image
*image
, VkImageAspectFlags mask
)
1182 case VK_IMAGE_ASPECT_PLANE_0_BIT
:
1183 return image
->planes
[0].format
;
1184 case VK_IMAGE_ASPECT_PLANE_1_BIT
:
1185 return image
->planes
[1].format
;
1186 case VK_IMAGE_ASPECT_PLANE_2_BIT
:
1187 return image
->planes
[2].format
;
1188 case VK_IMAGE_ASPECT_STENCIL_BIT
:
1189 return vk_format_stencil_only(image
->vk_format
);
1190 case VK_IMAGE_ASPECT_DEPTH_BIT
:
1191 return vk_format_depth_only(image
->vk_format
);
1193 return image
->vk_format
;
1198 radv_image_view_init(struct radv_image_view
*iview
,
1199 struct radv_device
*device
,
1200 const VkImageViewCreateInfo
* pCreateInfo
)
1202 RADV_FROM_HANDLE(radv_image
, image
, pCreateInfo
->image
);
1203 const VkImageSubresourceRange
*range
= &pCreateInfo
->subresourceRange
;
1205 switch (image
->type
) {
1206 case VK_IMAGE_TYPE_1D
:
1207 case VK_IMAGE_TYPE_2D
:
1208 assert(range
->baseArrayLayer
+ radv_get_layerCount(image
, range
) - 1 <= image
->info
.array_size
);
1210 case VK_IMAGE_TYPE_3D
:
1211 assert(range
->baseArrayLayer
+ radv_get_layerCount(image
, range
) - 1
1212 <= radv_minify(image
->info
.depth
, range
->baseMipLevel
));
1215 unreachable("bad VkImageType");
1217 iview
->image
= image
;
1218 iview
->bo
= image
->bo
;
1219 iview
->type
= pCreateInfo
->viewType
;
1220 iview
->plane_id
= radv_plane_from_aspect(pCreateInfo
->subresourceRange
.aspectMask
);
1221 iview
->aspect_mask
= pCreateInfo
->subresourceRange
.aspectMask
;
1222 iview
->multiple_planes
= vk_format_get_plane_count(image
->vk_format
) > 1 && iview
->aspect_mask
== VK_IMAGE_ASPECT_COLOR_BIT
;
1223 iview
->vk_format
= pCreateInfo
->format
;
1225 if (iview
->aspect_mask
== VK_IMAGE_ASPECT_STENCIL_BIT
) {
1226 iview
->vk_format
= vk_format_stencil_only(iview
->vk_format
);
1227 } else if (iview
->aspect_mask
== VK_IMAGE_ASPECT_DEPTH_BIT
) {
1228 iview
->vk_format
= vk_format_depth_only(iview
->vk_format
);
1231 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1232 iview
->extent
= (VkExtent3D
) {
1233 .width
= image
->info
.width
,
1234 .height
= image
->info
.height
,
1235 .depth
= image
->info
.depth
,
1238 iview
->extent
= (VkExtent3D
) {
1239 .width
= radv_minify(image
->info
.width
, range
->baseMipLevel
),
1240 .height
= radv_minify(image
->info
.height
, range
->baseMipLevel
),
1241 .depth
= radv_minify(image
->info
.depth
, range
->baseMipLevel
),
1245 if (iview
->vk_format
!= image
->planes
[iview
->plane_id
].format
) {
1246 unsigned view_bw
= vk_format_get_blockwidth(iview
->vk_format
);
1247 unsigned view_bh
= vk_format_get_blockheight(iview
->vk_format
);
1248 unsigned img_bw
= vk_format_get_blockwidth(image
->vk_format
);
1249 unsigned img_bh
= vk_format_get_blockheight(image
->vk_format
);
1251 iview
->extent
.width
= round_up_u32(iview
->extent
.width
* view_bw
, img_bw
);
1252 iview
->extent
.height
= round_up_u32(iview
->extent
.height
* view_bh
, img_bh
);
1254 /* Comment ported from amdvlk -
1255 * If we have the following image:
1256 * Uncompressed pixels Compressed block sizes (4x4)
1257 * mip0: 22 x 22 6 x 6
1258 * mip1: 11 x 11 3 x 3
1263 * On GFX9 the descriptor is always programmed with the WIDTH and HEIGHT of the base level and the HW is
1264 * calculating the degradation of the block sizes down the mip-chain as follows (straight-up
1265 * divide-by-two integer math):
1271 * This means that mip2 will be missing texels.
1273 * Fix this by calculating the base mip's width and height, then convert that, and round it
1274 * back up to get the level 0 size.
1275 * Clamp the converted size between the original values, and next power of two, which
1276 * means we don't oversize the image.
1278 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
1279 vk_format_is_compressed(image
->vk_format
) &&
1280 !vk_format_is_compressed(iview
->vk_format
)) {
1281 unsigned lvl_width
= radv_minify(image
->info
.width
, range
->baseMipLevel
);
1282 unsigned lvl_height
= radv_minify(image
->info
.height
, range
->baseMipLevel
);
1284 lvl_width
= round_up_u32(lvl_width
* view_bw
, img_bw
);
1285 lvl_height
= round_up_u32(lvl_height
* view_bh
, img_bh
);
1287 lvl_width
<<= range
->baseMipLevel
;
1288 lvl_height
<<= range
->baseMipLevel
;
1290 iview
->extent
.width
= CLAMP(lvl_width
, iview
->extent
.width
, iview
->image
->planes
[0].surface
.u
.gfx9
.surf_pitch
);
1291 iview
->extent
.height
= CLAMP(lvl_height
, iview
->extent
.height
, iview
->image
->planes
[0].surface
.u
.gfx9
.surf_height
);
1295 iview
->base_layer
= range
->baseArrayLayer
;
1296 iview
->layer_count
= radv_get_layerCount(image
, range
);
1297 iview
->base_mip
= range
->baseMipLevel
;
1298 iview
->level_count
= radv_get_levelCount(image
, range
);
1300 for (unsigned i
= 0; i
< (iview
->multiple_planes
? vk_format_get_plane_count(image
->vk_format
) : 1); ++i
) {
1301 VkFormat format
= vk_format_get_plane_format(iview
->vk_format
, i
);
1302 radv_image_view_make_descriptor(iview
, device
, format
, &pCreateInfo
->components
, false, iview
->plane_id
+ i
, i
);
1303 radv_image_view_make_descriptor(iview
, device
, format
, &pCreateInfo
->components
, true, iview
->plane_id
+ i
, i
);
1307 bool radv_layout_has_htile(const struct radv_image
*image
,
1308 VkImageLayout layout
,
1309 unsigned queue_mask
)
1311 if (radv_image_is_tc_compat_htile(image
))
1312 return layout
!= VK_IMAGE_LAYOUT_GENERAL
;
1314 return radv_image_has_htile(image
) &&
1315 (layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
1316 (layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
&&
1317 queue_mask
== (1u << RADV_QUEUE_GENERAL
)));
1320 bool radv_layout_is_htile_compressed(const struct radv_image
*image
,
1321 VkImageLayout layout
,
1322 unsigned queue_mask
)
1324 if (radv_image_is_tc_compat_htile(image
))
1325 return layout
!= VK_IMAGE_LAYOUT_GENERAL
;
1327 return radv_image_has_htile(image
) &&
1328 (layout
== VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL
||
1329 (layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
&&
1330 queue_mask
== (1u << RADV_QUEUE_GENERAL
)));
1333 bool radv_layout_can_fast_clear(const struct radv_image
*image
,
1334 VkImageLayout layout
,
1335 unsigned queue_mask
)
1337 return layout
== VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL
;
1340 bool radv_layout_dcc_compressed(const struct radv_image
*image
,
1341 VkImageLayout layout
,
1342 unsigned queue_mask
)
1344 /* Don't compress compute transfer dst, as image stores are not supported. */
1345 if (layout
== VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL
&&
1346 (queue_mask
& (1u << RADV_QUEUE_COMPUTE
)))
1349 return radv_image_has_dcc(image
) && layout
!= VK_IMAGE_LAYOUT_GENERAL
;
1353 unsigned radv_image_queue_family_mask(const struct radv_image
*image
, uint32_t family
, uint32_t queue_family
)
1355 if (!image
->exclusive
)
1356 return image
->queue_family_mask
;
1357 if (family
== VK_QUEUE_FAMILY_EXTERNAL
)
1358 return (1u << RADV_MAX_QUEUE_FAMILIES
) - 1u;
1359 if (family
== VK_QUEUE_FAMILY_IGNORED
)
1360 return 1u << queue_family
;
1361 return 1u << family
;
1365 radv_CreateImage(VkDevice device
,
1366 const VkImageCreateInfo
*pCreateInfo
,
1367 const VkAllocationCallbacks
*pAllocator
,
1371 const VkNativeBufferANDROID
*gralloc_info
=
1372 vk_find_struct_const(pCreateInfo
->pNext
, NATIVE_BUFFER_ANDROID
);
1375 return radv_image_from_gralloc(device
, pCreateInfo
, gralloc_info
,
1376 pAllocator
, pImage
);
1379 const struct wsi_image_create_info
*wsi_info
=
1380 vk_find_struct_const(pCreateInfo
->pNext
, WSI_IMAGE_CREATE_INFO_MESA
);
1381 bool scanout
= wsi_info
&& wsi_info
->scanout
;
1383 return radv_image_create(device
,
1384 &(struct radv_image_create_info
) {
1385 .vk_info
= pCreateInfo
,
1393 radv_DestroyImage(VkDevice _device
, VkImage _image
,
1394 const VkAllocationCallbacks
*pAllocator
)
1396 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1397 RADV_FROM_HANDLE(radv_image
, image
, _image
);
1402 if (image
->flags
& VK_IMAGE_CREATE_SPARSE_BINDING_BIT
)
1403 device
->ws
->buffer_destroy(image
->bo
);
1405 if (image
->owned_memory
!= VK_NULL_HANDLE
)
1406 radv_FreeMemory(_device
, image
->owned_memory
, pAllocator
);
1408 vk_free2(&device
->alloc
, pAllocator
, image
);
1411 void radv_GetImageSubresourceLayout(
1414 const VkImageSubresource
* pSubresource
,
1415 VkSubresourceLayout
* pLayout
)
1417 RADV_FROM_HANDLE(radv_image
, image
, _image
);
1418 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1419 int level
= pSubresource
->mipLevel
;
1420 int layer
= pSubresource
->arrayLayer
;
1422 unsigned plane_id
= radv_plane_from_aspect(pSubresource
->aspectMask
);
1424 struct radv_image_plane
*plane
= &image
->planes
[plane_id
];
1425 struct radeon_surf
*surface
= &plane
->surface
;
1427 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
1428 pLayout
->offset
= plane
->offset
+ surface
->u
.gfx9
.offset
[level
] + surface
->u
.gfx9
.surf_slice_size
* layer
;
1429 pLayout
->rowPitch
= surface
->u
.gfx9
.surf_pitch
* surface
->bpe
;
1430 pLayout
->arrayPitch
= surface
->u
.gfx9
.surf_slice_size
;
1431 pLayout
->depthPitch
= surface
->u
.gfx9
.surf_slice_size
;
1432 pLayout
->size
= surface
->u
.gfx9
.surf_slice_size
;
1433 if (image
->type
== VK_IMAGE_TYPE_3D
)
1434 pLayout
->size
*= u_minify(image
->info
.depth
, level
);
1436 pLayout
->offset
= plane
->offset
+ surface
->u
.legacy
.level
[level
].offset
+ (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4 * layer
;
1437 pLayout
->rowPitch
= surface
->u
.legacy
.level
[level
].nblk_x
* surface
->bpe
;
1438 pLayout
->arrayPitch
= (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4;
1439 pLayout
->depthPitch
= (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4;
1440 pLayout
->size
= (uint64_t)surface
->u
.legacy
.level
[level
].slice_size_dw
* 4;
1441 if (image
->type
== VK_IMAGE_TYPE_3D
)
1442 pLayout
->size
*= u_minify(image
->info
.depth
, level
);
1448 radv_CreateImageView(VkDevice _device
,
1449 const VkImageViewCreateInfo
*pCreateInfo
,
1450 const VkAllocationCallbacks
*pAllocator
,
1453 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1454 struct radv_image_view
*view
;
1456 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1457 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1459 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1461 radv_image_view_init(view
, device
, pCreateInfo
);
1463 *pView
= radv_image_view_to_handle(view
);
1469 radv_DestroyImageView(VkDevice _device
, VkImageView _iview
,
1470 const VkAllocationCallbacks
*pAllocator
)
1472 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1473 RADV_FROM_HANDLE(radv_image_view
, iview
, _iview
);
1477 vk_free2(&device
->alloc
, pAllocator
, iview
);
1480 void radv_buffer_view_init(struct radv_buffer_view
*view
,
1481 struct radv_device
*device
,
1482 const VkBufferViewCreateInfo
* pCreateInfo
)
1484 RADV_FROM_HANDLE(radv_buffer
, buffer
, pCreateInfo
->buffer
);
1486 view
->bo
= buffer
->bo
;
1487 view
->range
= pCreateInfo
->range
== VK_WHOLE_SIZE
?
1488 buffer
->size
- pCreateInfo
->offset
: pCreateInfo
->range
;
1489 view
->vk_format
= pCreateInfo
->format
;
1491 radv_make_buffer_descriptor(device
, buffer
, view
->vk_format
,
1492 pCreateInfo
->offset
, view
->range
, view
->state
);
1496 radv_CreateBufferView(VkDevice _device
,
1497 const VkBufferViewCreateInfo
*pCreateInfo
,
1498 const VkAllocationCallbacks
*pAllocator
,
1499 VkBufferView
*pView
)
1501 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1502 struct radv_buffer_view
*view
;
1504 view
= vk_alloc2(&device
->alloc
, pAllocator
, sizeof(*view
), 8,
1505 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
1507 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
1509 radv_buffer_view_init(view
, device
, pCreateInfo
);
1511 *pView
= radv_buffer_view_to_handle(view
);
1517 radv_DestroyBufferView(VkDevice _device
, VkBufferView bufferView
,
1518 const VkAllocationCallbacks
*pAllocator
)
1520 RADV_FROM_HANDLE(radv_device
, device
, _device
);
1521 RADV_FROM_HANDLE(radv_buffer_view
, view
, bufferView
);
1526 vk_free2(&device
->alloc
, pAllocator
, view
);