projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: fix rowPitch for R32G32B32 formats on GFX9
[mesa.git] / src / amd / vulkan / radv_image.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_debug.h"
29 #include "radv_private.h"
30 #include "vk_format.h"
31 #include "vk_util.h"
32 #include "radv_radeon_winsys.h"
33 #include "sid.h"
34 #include "gfx9d.h"
35 #include "util/debug.h"
36 #include "util/u_atomic.h"
37 static unsigned
38 radv_choose_tiling(struct radv_device *device,
39 const struct radv_image_create_info *create_info)
40 {
41 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
42
43 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR) {
44 assert(pCreateInfo->samples <= 1);
45 return RADEON_SURF_MODE_LINEAR_ALIGNED;
46 }
47
48 if (!vk_format_is_compressed(pCreateInfo->format) &&
49 !vk_format_is_depth_or_stencil(pCreateInfo->format)
50 && device->physical_device->rad_info.chip_class <= VI) {
51 /* this causes hangs in some VK CTS tests on GFX9. */
52 /* Textures with a very small height are recommended to be linear. */
53 if (pCreateInfo->imageType == VK_IMAGE_TYPE_1D ||
54 /* Only very thin and long 2D textures should benefit from
55 * linear_aligned. */
56 (pCreateInfo->extent.width > 8 && pCreateInfo->extent.height <= 2))
57 return RADEON_SURF_MODE_LINEAR_ALIGNED;
58 }
59
60 /* MSAA resources must be 2D tiled. */
61 if (pCreateInfo->samples > 1)
62 return RADEON_SURF_MODE_2D;
63
64 return RADEON_SURF_MODE_2D;
65 }
66
67 static bool
68 radv_use_tc_compat_htile_for_image(struct radv_device *device,
69 const VkImageCreateInfo *pCreateInfo)
70 {
71 /* TC-compat HTILE is only available for GFX8+. */
72 if (device->physical_device->rad_info.chip_class < VI)
73 return false;
74
75 if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
76 (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
77 return false;
78
79 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
80 return false;
81
82 if (pCreateInfo->mipLevels > 1)
83 return false;
84
85 /* FIXME: for some reason TC compat with 2/4/8 samples breaks some cts
86 * tests - disable for now */
87 if (pCreateInfo->samples >= 2 &&
88 pCreateInfo->format == VK_FORMAT_D32_SFLOAT_S8_UINT)
89 return false;
90
91 /* GFX9 supports both 32-bit and 16-bit depth surfaces, while GFX8 only
92 * supports 32-bit. Though, it's possible to enable TC-compat for
93 * 16-bit depth surfaces if no Z planes are compressed.
94 */
95 if (pCreateInfo->format != VK_FORMAT_D32_SFLOAT_S8_UINT &&
96 pCreateInfo->format != VK_FORMAT_D32_SFLOAT &&
97 pCreateInfo->format != VK_FORMAT_D16_UNORM)
98 return false;
99
100 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
101 const struct VkImageFormatListCreateInfoKHR *format_list =
102 (const struct VkImageFormatListCreateInfoKHR *)
103 vk_find_struct_const(pCreateInfo->pNext,
104 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
105
106 /* We have to ignore the existence of the list if viewFormatCount = 0 */
107 if (format_list && format_list->viewFormatCount) {
108 /* compatibility is transitive, so we only need to check
109 * one format with everything else.
110 */
111 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
112 if (pCreateInfo->format != format_list->pViewFormats[i])
113 return false;
114 }
115 } else {
116 return false;
117 }
118 }
119
120 return true;
121 }
122
123 static bool
124 radv_use_dcc_for_image(struct radv_device *device,
125 const struct radv_image *image,
126 const struct radv_image_create_info *create_info,
127 const VkImageCreateInfo *pCreateInfo)
128 {
129 bool dcc_compatible_formats;
130 bool blendable;
131
132 /* DCC (Delta Color Compression) is only available for GFX8+. */
133 if (device->physical_device->rad_info.chip_class < VI)
134 return false;
135
136 if (device->instance->debug_flags & RADV_DEBUG_NO_DCC)
137 return false;
138
139 /* FIXME: DCC is broken for shareable images starting with GFX9 */
140 if (device->physical_device->rad_info.chip_class >= GFX9 &&
141 image->shareable)
142 return false;
143
144 /* TODO: Enable DCC for storage images. */
145 if ((pCreateInfo->usage & VK_IMAGE_USAGE_STORAGE_BIT) ||
146 (pCreateInfo->flags & VK_IMAGE_CREATE_EXTENDED_USAGE_BIT))
147 return false;
148
149 if (pCreateInfo->tiling == VK_IMAGE_TILING_LINEAR)
150 return false;
151
152 if (vk_format_is_subsampled(pCreateInfo->format) ||
153 vk_format_get_plane_count(pCreateInfo->format) > 1)
154 return false;
155
156 /* TODO: Enable DCC for mipmaps and array layers. */
157 if (pCreateInfo->mipLevels > 1 || pCreateInfo->arrayLayers > 1)
158 return false;
159
160 if (create_info->scanout)
161 return false;
162
163 /* FIXME: DCC for MSAA with 4x and 8x samples doesn't work yet, while
164 * 2x can be enabled with an option.
165 */
166 if (pCreateInfo->samples > 2 ||
167 (pCreateInfo->samples == 2 &&
168 !device->physical_device->dcc_msaa_allowed))
169 return false;
170
171 /* Determine if the formats are DCC compatible. */
172 dcc_compatible_formats =
173 radv_is_colorbuffer_format_supported(pCreateInfo->format,
174 &blendable);
175
176 if (pCreateInfo->flags & VK_IMAGE_CREATE_MUTABLE_FORMAT_BIT) {
177 const struct VkImageFormatListCreateInfoKHR *format_list =
178 (const struct VkImageFormatListCreateInfoKHR *)
179 vk_find_struct_const(pCreateInfo->pNext,
180 IMAGE_FORMAT_LIST_CREATE_INFO_KHR);
181
182 /* We have to ignore the existence of the list if viewFormatCount = 0 */
183 if (format_list && format_list->viewFormatCount) {
184 /* compatibility is transitive, so we only need to check
185 * one format with everything else. */
186 for (unsigned i = 0; i < format_list->viewFormatCount; ++i) {
187 if (!radv_dcc_formats_compatible(pCreateInfo->format,
188 format_list->pViewFormats[i]))
189 dcc_compatible_formats = false;
190 }
191 } else {
192 dcc_compatible_formats = false;
193 }
194 }
195
196 if (!dcc_compatible_formats)
197 return false;
198
199 return true;
200 }
201
202 static int
203 radv_init_surface(struct radv_device *device,
204 const struct radv_image *image,
205 struct radeon_surf *surface,
206 unsigned plane_id,
207 const struct radv_image_create_info *create_info)
208 {
209 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
210 unsigned array_mode = radv_choose_tiling(device, create_info);
211 VkFormat format = vk_format_get_plane_format(pCreateInfo->format, plane_id);
212 const struct vk_format_description *desc = vk_format_description(format);
213 bool is_depth, is_stencil;
214
215 is_depth = vk_format_has_depth(desc);
216 is_stencil = vk_format_has_stencil(desc);
217
218 surface->blk_w = vk_format_get_blockwidth(format);
219 surface->blk_h = vk_format_get_blockheight(format);
220
221 surface->bpe = vk_format_get_blocksize(vk_format_depth_only(format));
222 /* align byte per element on dword */
223 if (surface->bpe == 3) {
224 surface->bpe = 4;
225 }
226 surface->flags = RADEON_SURF_SET(array_mode, MODE);
227
228 switch (pCreateInfo->imageType){
229 case VK_IMAGE_TYPE_1D:
230 if (pCreateInfo->arrayLayers > 1)
231 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D_ARRAY, TYPE);
232 else
233 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_1D, TYPE);
234 break;
235 case VK_IMAGE_TYPE_2D:
236 if (pCreateInfo->arrayLayers > 1)
237 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D_ARRAY, TYPE);
238 else
239 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_2D, TYPE);
240 break;
241 case VK_IMAGE_TYPE_3D:
242 surface->flags |= RADEON_SURF_SET(RADEON_SURF_TYPE_3D, TYPE);
243 break;
244 default:
245 unreachable("unhandled image type");
246 }
247
248 if (is_depth) {
249 surface->flags |= RADEON_SURF_ZBUFFER;
250 if (radv_use_tc_compat_htile_for_image(device, pCreateInfo))
251 surface->flags |= RADEON_SURF_TC_COMPATIBLE_HTILE;
252 }
253
254 if (is_stencil)
255 surface->flags |= RADEON_SURF_SBUFFER;
256
257 if (device->physical_device->rad_info.chip_class >= GFX9 &&
258 pCreateInfo->imageType == VK_IMAGE_TYPE_3D &&
259 vk_format_get_blocksizebits(pCreateInfo->format) == 128 &&
260 vk_format_is_compressed(pCreateInfo->format))
261 surface->flags |= RADEON_SURF_NO_RENDER_TARGET;
262
263 surface->flags |= RADEON_SURF_OPTIMIZE_FOR_SPACE;
264
265 if (!radv_use_dcc_for_image(device, image, create_info, pCreateInfo))
266 surface->flags |= RADEON_SURF_DISABLE_DCC;
267
268 if (create_info->scanout)
269 surface->flags |= RADEON_SURF_SCANOUT;
270 return 0;
271 }
272
273 static uint32_t si_get_bo_metadata_word1(struct radv_device *device)
274 {
275 return (ATI_VENDOR_ID << 16) | device->physical_device->rad_info.pci_id;
276 }
277
278 static inline unsigned
279 si_tile_mode_index(const struct radv_image_plane *plane, unsigned level, bool stencil)
280 {
281 if (stencil)
282 return plane->surface.u.legacy.stencil_tiling_index[level];
283 else
284 return plane->surface.u.legacy.tiling_index[level];
285 }
286
287 static unsigned radv_map_swizzle(unsigned swizzle)
288 {
289 switch (swizzle) {
290 case VK_SWIZZLE_Y:
291 return V_008F0C_SQ_SEL_Y;
292 case VK_SWIZZLE_Z:
293 return V_008F0C_SQ_SEL_Z;
294 case VK_SWIZZLE_W:
295 return V_008F0C_SQ_SEL_W;
296 case VK_SWIZZLE_0:
297 return V_008F0C_SQ_SEL_0;
298 case VK_SWIZZLE_1:
299 return V_008F0C_SQ_SEL_1;
300 default: /* VK_SWIZZLE_X */
301 return V_008F0C_SQ_SEL_X;
302 }
303 }
304
305 static void
306 radv_make_buffer_descriptor(struct radv_device *device,
307 struct radv_buffer *buffer,
308 VkFormat vk_format,
309 unsigned offset,
310 unsigned range,
311 uint32_t *state)
312 {
313 const struct vk_format_description *desc;
314 unsigned stride;
315 uint64_t gpu_address = radv_buffer_get_va(buffer->bo);
316 uint64_t va = gpu_address + buffer->offset;
317 unsigned num_format, data_format;
318 int first_non_void;
319 desc = vk_format_description(vk_format);
320 first_non_void = vk_format_get_first_non_void_channel(vk_format);
321 stride = desc->block.bits / 8;
322
323 num_format = radv_translate_buffer_numformat(desc, first_non_void);
324 data_format = radv_translate_buffer_dataformat(desc, first_non_void);
325
326 va += offset;
327 state[0] = va;
328 state[1] = S_008F04_BASE_ADDRESS_HI(va >> 32) |
329 S_008F04_STRIDE(stride);
330
331 if (device->physical_device->rad_info.chip_class != VI && stride) {
332 range /= stride;
333 }
334
335 state[2] = range;
336 state[3] = S_008F0C_DST_SEL_X(radv_map_swizzle(desc->swizzle[0])) |
337 S_008F0C_DST_SEL_Y(radv_map_swizzle(desc->swizzle[1])) |
338 S_008F0C_DST_SEL_Z(radv_map_swizzle(desc->swizzle[2])) |
339 S_008F0C_DST_SEL_W(radv_map_swizzle(desc->swizzle[3])) |
340 S_008F0C_NUM_FORMAT(num_format) |
341 S_008F0C_DATA_FORMAT(data_format);
342 }
343
344 static void
345 si_set_mutable_tex_desc_fields(struct radv_device *device,
346 struct radv_image *image,
347 const struct legacy_surf_level *base_level_info,
348 unsigned plane_id,
349 unsigned base_level, unsigned first_level,
350 unsigned block_width, bool is_stencil,
351 bool is_storage_image, uint32_t *state)
352 {
353 struct radv_image_plane *plane = &image->planes[plane_id];
354 uint64_t gpu_address = image->bo ? radv_buffer_get_va(image->bo) + image->offset : 0;
355 uint64_t va = gpu_address + plane->offset;
356 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
357 uint64_t meta_va = 0;
358 if (chip_class >= GFX9) {
359 if (is_stencil)
360 va += plane->surface.u.gfx9.stencil_offset;
361 else
362 va += plane->surface.u.gfx9.surf_offset;
363 } else
364 va += base_level_info->offset;
365
366 state[0] = va >> 8;
367 if (chip_class >= GFX9 ||
368 base_level_info->mode == RADEON_SURF_MODE_2D)
369 state[0] |= plane->surface.tile_swizzle;
370 state[1] &= C_008F14_BASE_ADDRESS_HI;
371 state[1] |= S_008F14_BASE_ADDRESS_HI(va >> 40);
372
373 if (chip_class >= VI) {
374 state[6] &= C_008F28_COMPRESSION_EN;
375 state[7] = 0;
376 if (!is_storage_image && radv_dcc_enabled(image, first_level)) {
377 meta_va = gpu_address + image->dcc_offset;
378 if (chip_class <= VI)
379 meta_va += base_level_info->dcc_offset;
380 } else if (!is_storage_image &&
381 radv_image_is_tc_compat_htile(image)) {
382 meta_va = gpu_address + image->htile_offset;
383 }
384
385 if (meta_va) {
386 state[6] |= S_008F28_COMPRESSION_EN(1);
387 state[7] = meta_va >> 8;
388 state[7] |= plane->surface.tile_swizzle;
389 }
390 }
391
392 if (chip_class >= GFX9) {
393 state[3] &= C_008F1C_SW_MODE;
394 state[4] &= C_008F20_PITCH_GFX9;
395
396 if (is_stencil) {
397 state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.stencil.swizzle_mode);
398 state[4] |= S_008F20_PITCH_GFX9(plane->surface.u.gfx9.stencil.epitch);
399 } else {
400 state[3] |= S_008F1C_SW_MODE(plane->surface.u.gfx9.surf.swizzle_mode);
401 state[4] |= S_008F20_PITCH_GFX9(plane->surface.u.gfx9.surf.epitch);
402 }
403
404 state[5] &= C_008F24_META_DATA_ADDRESS &
405 C_008F24_META_PIPE_ALIGNED &
406 C_008F24_META_RB_ALIGNED;
407 if (meta_va) {
408 struct gfx9_surf_meta_flags meta;
409
410 if (image->dcc_offset)
411 meta = plane->surface.u.gfx9.dcc;
412 else
413 meta = plane->surface.u.gfx9.htile;
414
415 state[5] |= S_008F24_META_DATA_ADDRESS(meta_va >> 40) |
416 S_008F24_META_PIPE_ALIGNED(meta.pipe_aligned) |
417 S_008F24_META_RB_ALIGNED(meta.rb_aligned);
418 }
419 } else {
420 /* SI-CI-VI */
421 unsigned pitch = base_level_info->nblk_x * block_width;
422 unsigned index = si_tile_mode_index(plane, base_level, is_stencil);
423
424 state[3] &= C_008F1C_TILING_INDEX;
425 state[3] |= S_008F1C_TILING_INDEX(index);
426 state[4] &= C_008F20_PITCH_GFX6;
427 state[4] |= S_008F20_PITCH_GFX6(pitch - 1);
428 }
429 }
430
431 static unsigned radv_tex_dim(VkImageType image_type, VkImageViewType view_type,
432 unsigned nr_layers, unsigned nr_samples, bool is_storage_image, bool gfx9)
433 {
434 if (view_type == VK_IMAGE_VIEW_TYPE_CUBE || view_type == VK_IMAGE_VIEW_TYPE_CUBE_ARRAY)
435 return is_storage_image ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_CUBE;
436
437 /* GFX9 allocates 1D textures as 2D. */
438 if (gfx9 && image_type == VK_IMAGE_TYPE_1D)
439 image_type = VK_IMAGE_TYPE_2D;
440 switch (image_type) {
441 case VK_IMAGE_TYPE_1D:
442 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_1D_ARRAY : V_008F1C_SQ_RSRC_IMG_1D;
443 case VK_IMAGE_TYPE_2D:
444 if (nr_samples > 1)
445 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY : V_008F1C_SQ_RSRC_IMG_2D_MSAA;
446 else
447 return nr_layers > 1 ? V_008F1C_SQ_RSRC_IMG_2D_ARRAY : V_008F1C_SQ_RSRC_IMG_2D;
448 case VK_IMAGE_TYPE_3D:
449 if (view_type == VK_IMAGE_VIEW_TYPE_3D)
450 return V_008F1C_SQ_RSRC_IMG_3D;
451 else
452 return V_008F1C_SQ_RSRC_IMG_2D_ARRAY;
453 default:
454 unreachable("illegal image type");
455 }
456 }
457
458 static unsigned gfx9_border_color_swizzle(const enum vk_swizzle swizzle[4])
459 {
460 unsigned bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
461
462 if (swizzle[3] == VK_SWIZZLE_X) {
463 /* For the pre-defined border color values (white, opaque
464 * black, transparent black), the only thing that matters is
465 * that the alpha channel winds up in the correct place
466 * (because the RGB channels are all the same) so either of
467 * these enumerations will work.
468 */
469 if (swizzle[2] == VK_SWIZZLE_Y)
470 bc_swizzle = V_008F20_BC_SWIZZLE_WZYX;
471 else
472 bc_swizzle = V_008F20_BC_SWIZZLE_WXYZ;
473 } else if (swizzle[0] == VK_SWIZZLE_X) {
474 if (swizzle[1] == VK_SWIZZLE_Y)
475 bc_swizzle = V_008F20_BC_SWIZZLE_XYZW;
476 else
477 bc_swizzle = V_008F20_BC_SWIZZLE_XWYZ;
478 } else if (swizzle[1] == VK_SWIZZLE_X) {
479 bc_swizzle = V_008F20_BC_SWIZZLE_YXWZ;
480 } else if (swizzle[2] == VK_SWIZZLE_X) {
481 bc_swizzle = V_008F20_BC_SWIZZLE_ZYXW;
482 }
483
484 return bc_swizzle;
485 }
486
487 /**
488 * Build the sampler view descriptor for a texture.
489 */
490 static void
491 si_make_texture_descriptor(struct radv_device *device,
492 struct radv_image *image,
493 bool is_storage_image,
494 VkImageViewType view_type,
495 VkFormat vk_format,
496 const VkComponentMapping *mapping,
497 unsigned first_level, unsigned last_level,
498 unsigned first_layer, unsigned last_layer,
499 unsigned width, unsigned height, unsigned depth,
500 uint32_t *state,
501 uint32_t *fmask_state)
502 {
503 const struct vk_format_description *desc;
504 enum vk_swizzle swizzle[4];
505 int first_non_void;
506 unsigned num_format, data_format, type;
507
508 desc = vk_format_description(vk_format);
509
510 if (desc->colorspace == VK_FORMAT_COLORSPACE_ZS) {
511 const unsigned char swizzle_xxxx[4] = {0, 0, 0, 0};
512 vk_format_compose_swizzles(mapping, swizzle_xxxx, swizzle);
513 } else {
514 vk_format_compose_swizzles(mapping, desc->swizzle, swizzle);
515 }
516
517 first_non_void = vk_format_get_first_non_void_channel(vk_format);
518
519 num_format = radv_translate_tex_numformat(vk_format, desc, first_non_void);
520 if (num_format == ~0) {
521 num_format = 0;
522 }
523
524 data_format = radv_translate_tex_dataformat(vk_format, desc, first_non_void);
525 if (data_format == ~0) {
526 data_format = 0;
527 }
528
529 /* S8 with either Z16 or Z32 HTILE need a special format. */
530 if (device->physical_device->rad_info.chip_class >= GFX9 &&
531 vk_format == VK_FORMAT_S8_UINT &&
532 radv_image_is_tc_compat_htile(image)) {
533 if (image->vk_format == VK_FORMAT_D32_SFLOAT_S8_UINT)
534 data_format = V_008F14_IMG_DATA_FORMAT_S8_32;
535 else if (image->vk_format == VK_FORMAT_D16_UNORM_S8_UINT)
536 data_format = V_008F14_IMG_DATA_FORMAT_S8_16;
537 }
538 type = radv_tex_dim(image->type, view_type, image->info.array_size, image->info.samples,
539 is_storage_image, device->physical_device->rad_info.chip_class >= GFX9);
540 if (type == V_008F1C_SQ_RSRC_IMG_1D_ARRAY) {
541 height = 1;
542 depth = image->info.array_size;
543 } else if (type == V_008F1C_SQ_RSRC_IMG_2D_ARRAY ||
544 type == V_008F1C_SQ_RSRC_IMG_2D_MSAA_ARRAY) {
545 if (view_type != VK_IMAGE_VIEW_TYPE_3D)
546 depth = image->info.array_size;
547 } else if (type == V_008F1C_SQ_RSRC_IMG_CUBE)
548 depth = image->info.array_size / 6;
549
550 state[0] = 0;
551 state[1] = (S_008F14_DATA_FORMAT_GFX6(data_format) |
552 S_008F14_NUM_FORMAT_GFX6(num_format));
553 state[2] = (S_008F18_WIDTH(width - 1) |
554 S_008F18_HEIGHT(height - 1) |
555 S_008F18_PERF_MOD(4));
556 state[3] = (S_008F1C_DST_SEL_X(radv_map_swizzle(swizzle[0])) |
557 S_008F1C_DST_SEL_Y(radv_map_swizzle(swizzle[1])) |
558 S_008F1C_DST_SEL_Z(radv_map_swizzle(swizzle[2])) |
559 S_008F1C_DST_SEL_W(radv_map_swizzle(swizzle[3])) |
560 S_008F1C_BASE_LEVEL(image->info.samples > 1 ?
561 0 : first_level) |
562 S_008F1C_LAST_LEVEL(image->info.samples > 1 ?
563 util_logbase2(image->info.samples) :
564 last_level) |
565 S_008F1C_TYPE(type));
566 state[4] = 0;
567 state[5] = S_008F24_BASE_ARRAY(first_layer);
568 state[6] = 0;
569 state[7] = 0;
570
571 if (device->physical_device->rad_info.chip_class >= GFX9) {
572 unsigned bc_swizzle = gfx9_border_color_swizzle(swizzle);
573
574 /* Depth is the last accessible layer on Gfx9.
575 * The hw doesn't need to know the total number of layers.
576 */
577 if (type == V_008F1C_SQ_RSRC_IMG_3D)
578 state[4] |= S_008F20_DEPTH(depth - 1);
579 else
580 state[4] |= S_008F20_DEPTH(last_layer);
581
582 state[4] |= S_008F20_BC_SWIZZLE(bc_swizzle);
583 state[5] |= S_008F24_MAX_MIP(image->info.samples > 1 ?
584 util_logbase2(image->info.samples) :
585 image->info.levels - 1);
586 } else {
587 state[3] |= S_008F1C_POW2_PAD(image->info.levels > 1);
588 state[4] |= S_008F20_DEPTH(depth - 1);
589 state[5] |= S_008F24_LAST_ARRAY(last_layer);
590 }
591 if (image->dcc_offset) {
592 unsigned swap = radv_translate_colorswap(vk_format, FALSE);
593
594 state[6] = S_008F28_ALPHA_IS_ON_MSB(swap <= 1);
595 } else {
596 /* The last dword is unused by hw. The shader uses it to clear
597 * bits in the first dword of sampler state.
598 */
599 if (device->physical_device->rad_info.chip_class <= CIK && image->info.samples <= 1) {
600 if (first_level == last_level)
601 state[7] = C_008F30_MAX_ANISO_RATIO;
602 else
603 state[7] = 0xffffffff;
604 }
605 }
606
607 /* Initialize the sampler view for FMASK. */
608 if (radv_image_has_fmask(image)) {
609 uint32_t fmask_format, num_format;
610 uint64_t gpu_address = radv_buffer_get_va(image->bo);
611 uint64_t va;
612
613 assert(image->plane_count == 1);
614
615 va = gpu_address + image->offset + image->fmask.offset;
616
617 if (device->physical_device->rad_info.chip_class >= GFX9) {
618 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK;
619 switch (image->info.samples) {
620 case 2:
621 num_format = V_008F14_IMG_FMASK_8_2_2;
622 break;
623 case 4:
624 num_format = V_008F14_IMG_FMASK_8_4_4;
625 break;
626 case 8:
627 num_format = V_008F14_IMG_FMASK_32_8_8;
628 break;
629 default:
630 unreachable("invalid nr_samples");
631 }
632 } else {
633 switch (image->info.samples) {
634 case 2:
635 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S2_F2;
636 break;
637 case 4:
638 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK8_S4_F4;
639 break;
640 case 8:
641 fmask_format = V_008F14_IMG_DATA_FORMAT_FMASK32_S8_F8;
642 break;
643 default:
644 assert(0);
645 fmask_format = V_008F14_IMG_DATA_FORMAT_INVALID;
646 }
647 num_format = V_008F14_IMG_NUM_FORMAT_UINT;
648 }
649
650 fmask_state[0] = va >> 8;
651 fmask_state[0] |= image->fmask.tile_swizzle;
652 fmask_state[1] = S_008F14_BASE_ADDRESS_HI(va >> 40) |
653 S_008F14_DATA_FORMAT_GFX6(fmask_format) |
654 S_008F14_NUM_FORMAT_GFX6(num_format);
655 fmask_state[2] = S_008F18_WIDTH(width - 1) |
656 S_008F18_HEIGHT(height - 1);
657 fmask_state[3] = S_008F1C_DST_SEL_X(V_008F1C_SQ_SEL_X) |
658 S_008F1C_DST_SEL_Y(V_008F1C_SQ_SEL_X) |
659 S_008F1C_DST_SEL_Z(V_008F1C_SQ_SEL_X) |
660 S_008F1C_DST_SEL_W(V_008F1C_SQ_SEL_X) |
661 S_008F1C_TYPE(radv_tex_dim(image->type, view_type, image->info.array_size, 0, false, false));
662 fmask_state[4] = 0;
663 fmask_state[5] = S_008F24_BASE_ARRAY(first_layer);
664 fmask_state[6] = 0;
665 fmask_state[7] = 0;
666
667 if (device->physical_device->rad_info.chip_class >= GFX9) {
668 fmask_state[3] |= S_008F1C_SW_MODE(image->planes[0].surface.u.gfx9.fmask.swizzle_mode);
669 fmask_state[4] |= S_008F20_DEPTH(last_layer) |
670 S_008F20_PITCH_GFX9(image->planes[0].surface.u.gfx9.fmask.epitch);
671 fmask_state[5] |= S_008F24_META_PIPE_ALIGNED(image->planes[0].surface.u.gfx9.cmask.pipe_aligned) |
672 S_008F24_META_RB_ALIGNED(image->planes[0].surface.u.gfx9.cmask.rb_aligned);
673 } else {
674 fmask_state[3] |= S_008F1C_TILING_INDEX(image->fmask.tile_mode_index);
675 fmask_state[4] |= S_008F20_DEPTH(depth - 1) |
676 S_008F20_PITCH_GFX6(image->fmask.pitch_in_pixels - 1);
677 fmask_state[5] |= S_008F24_LAST_ARRAY(last_layer);
678 }
679 } else if (fmask_state)
680 memset(fmask_state, 0, 8 * 4);
681 }
682
683 static void
684 radv_query_opaque_metadata(struct radv_device *device,
685 struct radv_image *image,
686 struct radeon_bo_metadata *md)
687 {
688 static const VkComponentMapping fixedmapping;
689 uint32_t desc[8], i;
690
691 assert(image->plane_count == 1);
692
693 /* Metadata image format format version 1:
694 * [0] = 1 (metadata format identifier)
695 * [1] = (VENDOR_ID << 16) | PCI_ID
696 * [2:9] = image descriptor for the whole resource
697 * [2] is always 0, because the base address is cleared
698 * [9] is the DCC offset bits [39:8] from the beginning of
699 * the buffer
700 * [10:10+LAST_LEVEL] = mipmap level offset bits [39:8] for each level
701 */
702 md->metadata[0] = 1; /* metadata image format version 1 */
703
704 /* TILE_MODE_INDEX is ambiguous without a PCI ID. */
705 md->metadata[1] = si_get_bo_metadata_word1(device);
706
707
708 si_make_texture_descriptor(device, image, false,
709 (VkImageViewType)image->type, image->vk_format,
710 &fixedmapping, 0, image->info.levels - 1, 0,
711 image->info.array_size - 1,
712 image->info.width, image->info.height,
713 image->info.depth,
714 desc, NULL);
715
716 si_set_mutable_tex_desc_fields(device, image, &image->planes[0].surface.u.legacy.level[0], 0, 0, 0,
717 image->planes[0].surface.blk_w, false, false, desc);
718
719 /* Clear the base address and set the relative DCC offset. */
720 desc[0] = 0;
721 desc[1] &= C_008F14_BASE_ADDRESS_HI;
722 desc[7] = image->dcc_offset >> 8;
723
724 /* Dwords [2:9] contain the image descriptor. */
725 memcpy(&md->metadata[2], desc, sizeof(desc));
726
727 /* Dwords [10:..] contain the mipmap level offsets. */
728 if (device->physical_device->rad_info.chip_class <= VI) {
729 for (i = 0; i <= image->info.levels - 1; i++)
730 md->metadata[10+i] = image->planes[0].surface.u.legacy.level[i].offset >> 8;
731 md->size_metadata = (11 + image->info.levels - 1) * 4;
732 }
733 }
734
735 void
736 radv_init_metadata(struct radv_device *device,
737 struct radv_image *image,
738 struct radeon_bo_metadata *metadata)
739 {
740 struct radeon_surf *surface = &image->planes[0].surface;
741
742 memset(metadata, 0, sizeof(*metadata));
743
744 if (device->physical_device->rad_info.chip_class >= GFX9) {
745 metadata->u.gfx9.swizzle_mode = surface->u.gfx9.surf.swizzle_mode;
746 } else {
747 metadata->u.legacy.microtile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_1D ?
748 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
749 metadata->u.legacy.macrotile = surface->u.legacy.level[0].mode >= RADEON_SURF_MODE_2D ?
750 RADEON_LAYOUT_TILED : RADEON_LAYOUT_LINEAR;
751 metadata->u.legacy.pipe_config = surface->u.legacy.pipe_config;
752 metadata->u.legacy.bankw = surface->u.legacy.bankw;
753 metadata->u.legacy.bankh = surface->u.legacy.bankh;
754 metadata->u.legacy.tile_split = surface->u.legacy.tile_split;
755 metadata->u.legacy.mtilea = surface->u.legacy.mtilea;
756 metadata->u.legacy.num_banks = surface->u.legacy.num_banks;
757 metadata->u.legacy.stride = surface->u.legacy.level[0].nblk_x * surface->bpe;
758 metadata->u.legacy.scanout = (surface->flags & RADEON_SURF_SCANOUT) != 0;
759 }
760 radv_query_opaque_metadata(device, image, metadata);
761 }
762
763 void
764 radv_image_override_offset_stride(struct radv_device *device,
765 struct radv_image *image,
766 uint64_t offset, uint32_t stride)
767 {
768 struct radeon_surf *surface = &image->planes[0].surface;
769 unsigned bpe = vk_format_get_blocksizebits(image->vk_format) / 8;
770
771 if (device->physical_device->rad_info.chip_class >= GFX9) {
772 if (stride) {
773 surface->u.gfx9.surf_pitch = stride;
774 surface->u.gfx9.surf_slice_size =
775 (uint64_t)stride * surface->u.gfx9.surf_height * bpe;
776 }
777 surface->u.gfx9.surf_offset = offset;
778 } else {
779 surface->u.legacy.level[0].nblk_x = stride;
780 surface->u.legacy.level[0].slice_size_dw =
781 ((uint64_t)stride * surface->u.legacy.level[0].nblk_y * bpe) / 4;
782
783 if (offset) {
784 for (unsigned i = 0; i < ARRAY_SIZE(surface->u.legacy.level); ++i)
785 surface->u.legacy.level[i].offset += offset;
786 }
787
788 }
789 }
790
791 /* The number of samples can be specified independently of the texture. */
792 static void
793 radv_image_get_fmask_info(struct radv_device *device,
794 struct radv_image *image,
795 unsigned nr_samples,
796 struct radv_fmask_info *out)
797 {
798 if (device->physical_device->rad_info.chip_class >= GFX9) {
799 out->alignment = image->planes[0].surface.fmask_alignment;
800 out->size = image->planes[0].surface.fmask_size;
801 out->tile_swizzle = image->planes[0].surface.fmask_tile_swizzle;
802 return;
803 }
804
805 out->slice_tile_max = image->planes[0].surface.u.legacy.fmask.slice_tile_max;
806 out->tile_mode_index = image->planes[0].surface.u.legacy.fmask.tiling_index;
807 out->pitch_in_pixels = image->planes[0].surface.u.legacy.fmask.pitch_in_pixels;
808 out->bank_height = image->planes[0].surface.u.legacy.fmask.bankh;
809 out->tile_swizzle = image->planes[0].surface.fmask_tile_swizzle;
810 out->alignment = image->planes[0].surface.fmask_alignment;
811 out->size = image->planes[0].surface.fmask_size;
812
813 assert(!out->tile_swizzle || !image->shareable);
814 }
815
816 static void
817 radv_image_alloc_fmask(struct radv_device *device,
818 struct radv_image *image)
819 {
820 radv_image_get_fmask_info(device, image, image->info.samples, &image->fmask);
821
822 image->fmask.offset = align64(image->size, image->fmask.alignment);
823 image->size = image->fmask.offset + image->fmask.size;
824 image->alignment = MAX2(image->alignment, image->fmask.alignment);
825 }
826
827 static void
828 radv_image_get_cmask_info(struct radv_device *device,
829 struct radv_image *image,
830 struct radv_cmask_info *out)
831 {
832 unsigned pipe_interleave_bytes = device->physical_device->rad_info.pipe_interleave_bytes;
833 unsigned num_pipes = device->physical_device->rad_info.num_tile_pipes;
834 unsigned cl_width, cl_height;
835
836 assert(image->plane_count == 1);
837
838 if (device->physical_device->rad_info.chip_class >= GFX9) {
839 out->alignment = image->planes[0].surface.cmask_alignment;
840 out->size = image->planes[0].surface.cmask_size;
841 return;
842 }
843
844 switch (num_pipes) {
845 case 2:
846 cl_width = 32;
847 cl_height = 16;
848 break;
849 case 4:
850 cl_width = 32;
851 cl_height = 32;
852 break;
853 case 8:
854 cl_width = 64;
855 cl_height = 32;
856 break;
857 case 16: /* Hawaii */
858 cl_width = 64;
859 cl_height = 64;
860 break;
861 default:
862 assert(0);
863 return;
864 }
865
866 unsigned base_align = num_pipes * pipe_interleave_bytes;
867
868 unsigned width = align(image->planes[0].surface.u.legacy.level[0].nblk_x, cl_width*8);
869 unsigned height = align(image->planes[0].surface.u.legacy.level[0].nblk_y, cl_height*8);
870 unsigned slice_elements = (width * height) / (8*8);
871
872 /* Each element of CMASK is a nibble. */
873 unsigned slice_bytes = slice_elements / 2;
874
875 out->slice_tile_max = (width * height) / (128*128);
876 if (out->slice_tile_max)
877 out->slice_tile_max -= 1;
878
879 out->alignment = MAX2(256, base_align);
880 out->size = (image->type == VK_IMAGE_TYPE_3D ? image->info.depth : image->info.array_size) *
881 align(slice_bytes, base_align);
882 }
883
884 static void
885 radv_image_alloc_cmask(struct radv_device *device,
886 struct radv_image *image)
887 {
888 uint32_t clear_value_size = 0;
889 radv_image_get_cmask_info(device, image, &image->cmask);
890
891 image->cmask.offset = align64(image->size, image->cmask.alignment);
892 /* + 8 for storing the clear values */
893 if (!image->clear_value_offset) {
894 image->clear_value_offset = image->cmask.offset + image->cmask.size;
895 clear_value_size = 8;
896 }
897 image->size = image->cmask.offset + image->cmask.size + clear_value_size;
898 image->alignment = MAX2(image->alignment, image->cmask.alignment);
899 }
900
901 static void
902 radv_image_alloc_dcc(struct radv_image *image)
903 {
904 assert(image->plane_count == 1);
905
906 image->dcc_offset = align64(image->size, image->planes[0].surface.dcc_alignment);
907 /* + 16 for storing the clear values + dcc pred */
908 image->clear_value_offset = image->dcc_offset + image->planes[0].surface.dcc_size;
909 image->fce_pred_offset = image->clear_value_offset + 8;
910 image->dcc_pred_offset = image->clear_value_offset + 16;
911 image->size = image->dcc_offset + image->planes[0].surface.dcc_size + 24;
912 image->alignment = MAX2(image->alignment, image->planes[0].surface.dcc_alignment);
913 }
914
915 static void
916 radv_image_alloc_htile(struct radv_image *image)
917 {
918 image->htile_offset = align64(image->size, image->planes[0].surface.htile_alignment);
919
920 /* + 8 for storing the clear values */
921 image->clear_value_offset = image->htile_offset + image->planes[0].surface.htile_size;
922 image->size = image->clear_value_offset + 8;
923 if (radv_image_is_tc_compat_htile(image)) {
924 /* Metadata for the TC-compatible HTILE hardware bug which
925 * have to be fixed by updating ZRANGE_PRECISION when doing
926 * fast depth clears to 0.0f.
927 */
928 image->tc_compat_zrange_offset = image->clear_value_offset + 8;
929 image->size = image->clear_value_offset + 16;
930 }
931 image->alignment = align64(image->alignment, image->planes[0].surface.htile_alignment);
932 }
933
934 static inline bool
935 radv_image_can_enable_dcc_or_cmask(struct radv_image *image)
936 {
937 if (image->info.samples <= 1 &&
938 image->info.width * image->info.height <= 512 * 512) {
939 /* Do not enable CMASK or DCC for small surfaces where the cost
940 * of the eliminate pass can be higher than the benefit of fast
941 * clear. RadeonSI does this, but the image threshold is
942 * different.
943 */
944 return false;
945 }
946
947 return image->usage & VK_IMAGE_USAGE_COLOR_ATTACHMENT_BIT &&
948 (image->exclusive || image->queue_family_mask == 1);
949 }
950
951 static inline bool
952 radv_image_can_enable_dcc(struct radv_image *image)
953 {
954 return radv_image_can_enable_dcc_or_cmask(image) &&
955 radv_image_has_dcc(image);
956 }
957
958 static inline bool
959 radv_image_can_enable_cmask(struct radv_image *image)
960 {
961 if (image->planes[0].surface.bpe > 8 && image->info.samples == 1) {
962 /* Do not enable CMASK for non-MSAA images (fast color clear)
963 * because 128 bit formats are not supported, but FMASK might
964 * still be used.
965 */
966 return false;
967 }
968
969 return radv_image_can_enable_dcc_or_cmask(image) &&
970 image->info.levels == 1 &&
971 image->info.depth == 1 &&
972 !image->planes[0].surface.is_linear;
973 }
974
975 static inline bool
976 radv_image_can_enable_fmask(struct radv_image *image)
977 {
978 return image->info.samples > 1 && vk_format_is_color(image->vk_format);
979 }
980
981 static inline bool
982 radv_image_can_enable_htile(struct radv_image *image)
983 {
984 return radv_image_has_htile(image) &&
985 image->info.levels == 1 &&
986 image->info.width * image->info.height >= 8 * 8;
987 }
988
989 static void radv_image_disable_dcc(struct radv_image *image)
990 {
991 for (unsigned i = 0; i < image->plane_count; ++i)
992 image->planes[i].surface.dcc_size = 0;
993 }
994
995 static void radv_image_disable_htile(struct radv_image *image)
996 {
997 for (unsigned i = 0; i < image->plane_count; ++i)
998 image->planes[i].surface.htile_size = 0;
999 }
1000
1001 VkResult
1002 radv_image_create(VkDevice _device,
1003 const struct radv_image_create_info *create_info,
1004 const VkAllocationCallbacks* alloc,
1005 VkImage *pImage)
1006 {
1007 RADV_FROM_HANDLE(radv_device, device, _device);
1008 const VkImageCreateInfo *pCreateInfo = create_info->vk_info;
1009 struct radv_image *image = NULL;
1010 assert(pCreateInfo->sType == VK_STRUCTURE_TYPE_IMAGE_CREATE_INFO);
1011
1012 const unsigned plane_count = vk_format_get_plane_count(pCreateInfo->format);
1013 const size_t image_struct_size = sizeof(*image) + sizeof(struct radv_image_plane) * plane_count;
1014
1015 radv_assert(pCreateInfo->mipLevels > 0);
1016 radv_assert(pCreateInfo->arrayLayers > 0);
1017 radv_assert(pCreateInfo->samples > 0);
1018 radv_assert(pCreateInfo->extent.width > 0);
1019 radv_assert(pCreateInfo->extent.height > 0);
1020 radv_assert(pCreateInfo->extent.depth > 0);
1021
1022 image = vk_zalloc2(&device->alloc, alloc, image_struct_size, 8,
1023 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1024 if (!image)
1025 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1026
1027 image->type = pCreateInfo->imageType;
1028 image->info.width = pCreateInfo->extent.width;
1029 image->info.height = pCreateInfo->extent.height;
1030 image->info.depth = pCreateInfo->extent.depth;
1031 image->info.samples = pCreateInfo->samples;
1032 image->info.storage_samples = pCreateInfo->samples;
1033 image->info.array_size = pCreateInfo->arrayLayers;
1034 image->info.levels = pCreateInfo->mipLevels;
1035 image->info.num_channels = vk_format_get_nr_components(pCreateInfo->format);
1036
1037 image->vk_format = pCreateInfo->format;
1038 image->tiling = pCreateInfo->tiling;
1039 image->usage = pCreateInfo->usage;
1040 image->flags = pCreateInfo->flags;
1041
1042 image->exclusive = pCreateInfo->sharingMode == VK_SHARING_MODE_EXCLUSIVE;
1043 if (pCreateInfo->sharingMode == VK_SHARING_MODE_CONCURRENT) {
1044 for (uint32_t i = 0; i < pCreateInfo->queueFamilyIndexCount; ++i)
1045 if (pCreateInfo->pQueueFamilyIndices[i] == VK_QUEUE_FAMILY_EXTERNAL)
1046 image->queue_family_mask |= (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1047 else
1048 image->queue_family_mask |= 1u << pCreateInfo->pQueueFamilyIndices[i];
1049 }
1050
1051 image->shareable = vk_find_struct_const(pCreateInfo->pNext,
1052 EXTERNAL_MEMORY_IMAGE_CREATE_INFO) != NULL;
1053 if (!vk_format_is_depth_or_stencil(pCreateInfo->format) && !create_info->scanout && !image->shareable) {
1054 image->info.surf_index = &device->image_mrt_offset_counter;
1055 }
1056
1057 image->plane_count = plane_count;
1058 image->size = 0;
1059 image->alignment = 1;
1060 for (unsigned plane = 0; plane < plane_count; ++plane) {
1061 struct ac_surf_info info = image->info;
1062 radv_init_surface(device, image, &image->planes[plane].surface, plane, create_info);
1063
1064 if (plane) {
1065 const struct vk_format_description *desc = vk_format_description(pCreateInfo->format);
1066 assert(info.width % desc->width_divisor == 0);
1067 assert(info.height % desc->height_divisor == 0);
1068
1069 info.width /= desc->width_divisor;
1070 info.height /= desc->height_divisor;
1071 }
1072
1073 device->ws->surface_init(device->ws, &info, &image->planes[plane].surface);
1074
1075 image->planes[plane].offset = align(image->size, image->planes[plane].surface.surf_alignment);
1076 image->size = image->planes[plane].offset + image->planes[plane].surface.surf_size;
1077 image->alignment = image->planes[plane].surface.surf_alignment;
1078
1079 image->planes[plane].format = vk_format_get_plane_format(image->vk_format, plane);
1080 }
1081
1082 if (!create_info->no_metadata_planes) {
1083 /* Try to enable DCC first. */
1084 if (radv_image_can_enable_dcc(image)) {
1085 radv_image_alloc_dcc(image);
1086 if (image->info.samples > 1) {
1087 /* CMASK should be enabled because DCC fast
1088 * clear with MSAA needs it.
1089 */
1090 assert(radv_image_can_enable_cmask(image));
1091 radv_image_alloc_cmask(device, image);
1092 }
1093 } else {
1094 /* When DCC cannot be enabled, try CMASK. */
1095 radv_image_disable_dcc(image);
1096 if (radv_image_can_enable_cmask(image)) {
1097 radv_image_alloc_cmask(device, image);
1098 }
1099 }
1100
1101 /* Try to enable FMASK for multisampled images. */
1102 if (radv_image_can_enable_fmask(image)) {
1103 radv_image_alloc_fmask(device, image);
1104 } else {
1105 /* Otherwise, try to enable HTILE for depth surfaces. */
1106 if (radv_image_can_enable_htile(image) &&
1107 !(device->instance->debug_flags & RADV_DEBUG_NO_HIZ)) {
1108 image->tc_compatible_htile = image->planes[0].surface.flags & RADEON_SURF_TC_COMPATIBLE_HTILE;
1109 radv_image_alloc_htile(image);
1110 } else {
1111 radv_image_disable_htile(image);
1112 }
1113 }
1114 } else {
1115 radv_image_disable_dcc(image);
1116 radv_image_disable_htile(image);
1117 }
1118
1119 if (pCreateInfo->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT) {
1120 image->alignment = MAX2(image->alignment, 4096);
1121 image->size = align64(image->size, image->alignment);
1122 image->offset = 0;
1123
1124 image->bo = device->ws->buffer_create(device->ws, image->size, image->alignment,
1125 0, RADEON_FLAG_VIRTUAL, RADV_BO_PRIORITY_VIRTUAL);
1126 if (!image->bo) {
1127 vk_free2(&device->alloc, alloc, image);
1128 return vk_error(device->instance, VK_ERROR_OUT_OF_DEVICE_MEMORY);
1129 }
1130 }
1131
1132 *pImage = radv_image_to_handle(image);
1133
1134 return VK_SUCCESS;
1135 }
1136
1137 static void
1138 radv_image_view_make_descriptor(struct radv_image_view *iview,
1139 struct radv_device *device,
1140 VkFormat vk_format,
1141 const VkComponentMapping *components,
1142 bool is_storage_image, unsigned plane_id,
1143 unsigned descriptor_plane_id)
1144 {
1145 struct radv_image *image = iview->image;
1146 struct radv_image_plane *plane = &image->planes[plane_id];
1147 const struct vk_format_description *format_desc = vk_format_description(image->vk_format);
1148 bool is_stencil = iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT;
1149 uint32_t blk_w;
1150 union radv_descriptor *descriptor;
1151 uint32_t hw_level = 0;
1152
1153 if (is_storage_image) {
1154 descriptor = &iview->storage_descriptor;
1155 } else {
1156 descriptor = &iview->descriptor;
1157 }
1158
1159 assert(vk_format_get_plane_count(vk_format) == 1);
1160 assert(plane->surface.blk_w % vk_format_get_blockwidth(plane->format) == 0);
1161 blk_w = plane->surface.blk_w / vk_format_get_blockwidth(plane->format) * vk_format_get_blockwidth(vk_format);
1162
1163 if (device->physical_device->rad_info.chip_class >= GFX9)
1164 hw_level = iview->base_mip;
1165 si_make_texture_descriptor(device, image, is_storage_image,
1166 iview->type,
1167 vk_format,
1168 components,
1169 hw_level, hw_level + iview->level_count - 1,
1170 iview->base_layer,
1171 iview->base_layer + iview->layer_count - 1,
1172 iview->extent.width / (plane_id ? format_desc->width_divisor : 1),
1173 iview->extent.height / (plane_id ? format_desc->height_divisor : 1),
1174 iview->extent.depth,
1175 descriptor->plane_descriptors[descriptor_plane_id],
1176 descriptor_plane_id ? NULL : descriptor->fmask_descriptor);
1177
1178 const struct legacy_surf_level *base_level_info = NULL;
1179 if (device->physical_device->rad_info.chip_class <= GFX9) {
1180 if (is_stencil)
1181 base_level_info = &plane->surface.u.legacy.stencil_level[iview->base_mip];
1182 else
1183 base_level_info = &plane->surface.u.legacy.level[iview->base_mip];
1184 }
1185 si_set_mutable_tex_desc_fields(device, image,
1186 base_level_info,
1187 plane_id,
1188 iview->base_mip,
1189 iview->base_mip,
1190 blk_w, is_stencil, is_storage_image, descriptor->plane_descriptors[descriptor_plane_id]);
1191 }
1192
1193 static unsigned
1194 radv_plane_from_aspect(VkImageAspectFlags mask)
1195 {
1196 switch(mask) {
1197 case VK_IMAGE_ASPECT_PLANE_1_BIT:
1198 return 1;
1199 case VK_IMAGE_ASPECT_PLANE_2_BIT:
1200 return 2;
1201 default:
1202 return 0;
1203 }
1204 }
1205
1206 VkFormat
1207 radv_get_aspect_format(struct radv_image *image, VkImageAspectFlags mask)
1208 {
1209 switch(mask) {
1210 case VK_IMAGE_ASPECT_PLANE_0_BIT:
1211 return image->planes[0].format;
1212 case VK_IMAGE_ASPECT_PLANE_1_BIT:
1213 return image->planes[1].format;
1214 case VK_IMAGE_ASPECT_PLANE_2_BIT:
1215 return image->planes[2].format;
1216 case VK_IMAGE_ASPECT_STENCIL_BIT:
1217 return vk_format_stencil_only(image->vk_format);
1218 case VK_IMAGE_ASPECT_DEPTH_BIT:
1219 return vk_format_depth_only(image->vk_format);
1220 case VK_IMAGE_ASPECT_DEPTH_BIT | VK_IMAGE_ASPECT_STENCIL_BIT:
1221 return vk_format_depth_only(image->vk_format);
1222 default:
1223 return image->vk_format;
1224 }
1225 }
1226
1227 void
1228 radv_image_view_init(struct radv_image_view *iview,
1229 struct radv_device *device,
1230 const VkImageViewCreateInfo* pCreateInfo)
1231 {
1232 RADV_FROM_HANDLE(radv_image, image, pCreateInfo->image);
1233 const VkImageSubresourceRange *range = &pCreateInfo->subresourceRange;
1234
1235 switch (image->type) {
1236 case VK_IMAGE_TYPE_1D:
1237 case VK_IMAGE_TYPE_2D:
1238 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1 <= image->info.array_size);
1239 break;
1240 case VK_IMAGE_TYPE_3D:
1241 assert(range->baseArrayLayer + radv_get_layerCount(image, range) - 1
1242 <= radv_minify(image->info.depth, range->baseMipLevel));
1243 break;
1244 default:
1245 unreachable("bad VkImageType");
1246 }
1247 iview->image = image;
1248 iview->bo = image->bo;
1249 iview->type = pCreateInfo->viewType;
1250 iview->plane_id = radv_plane_from_aspect(pCreateInfo->subresourceRange.aspectMask);
1251 iview->aspect_mask = pCreateInfo->subresourceRange.aspectMask;
1252 iview->multiple_planes = vk_format_get_plane_count(image->vk_format) > 1 && iview->aspect_mask == VK_IMAGE_ASPECT_COLOR_BIT;
1253 iview->vk_format = pCreateInfo->format;
1254
1255 if (iview->aspect_mask == VK_IMAGE_ASPECT_STENCIL_BIT) {
1256 iview->vk_format = vk_format_stencil_only(iview->vk_format);
1257 } else if (iview->aspect_mask == VK_IMAGE_ASPECT_DEPTH_BIT) {
1258 iview->vk_format = vk_format_depth_only(iview->vk_format);
1259 }
1260
1261 if (device->physical_device->rad_info.chip_class >= GFX9) {
1262 iview->extent = (VkExtent3D) {
1263 .width = image->info.width,
1264 .height = image->info.height,
1265 .depth = image->info.depth,
1266 };
1267 } else {
1268 iview->extent = (VkExtent3D) {
1269 .width = radv_minify(image->info.width , range->baseMipLevel),
1270 .height = radv_minify(image->info.height, range->baseMipLevel),
1271 .depth = radv_minify(image->info.depth , range->baseMipLevel),
1272 };
1273 }
1274
1275 if (iview->vk_format != image->planes[iview->plane_id].format) {
1276 unsigned view_bw = vk_format_get_blockwidth(iview->vk_format);
1277 unsigned view_bh = vk_format_get_blockheight(iview->vk_format);
1278 unsigned img_bw = vk_format_get_blockwidth(image->vk_format);
1279 unsigned img_bh = vk_format_get_blockheight(image->vk_format);
1280
1281 iview->extent.width = round_up_u32(iview->extent.width * view_bw, img_bw);
1282 iview->extent.height = round_up_u32(iview->extent.height * view_bh, img_bh);
1283
1284 /* Comment ported from amdvlk -
1285 * If we have the following image:
1286 * Uncompressed pixels Compressed block sizes (4x4)
1287 * mip0: 22 x 22 6 x 6
1288 * mip1: 11 x 11 3 x 3
1289 * mip2: 5 x 5 2 x 2
1290 * mip3: 2 x 2 1 x 1
1291 * mip4: 1 x 1 1 x 1
1292 *
1293 * On GFX9 the descriptor is always programmed with the WIDTH and HEIGHT of the base level and the HW is
1294 * calculating the degradation of the block sizes down the mip-chain as follows (straight-up
1295 * divide-by-two integer math):
1296 * mip0: 6x6
1297 * mip1: 3x3
1298 * mip2: 1x1
1299 * mip3: 1x1
1300 *
1301 * This means that mip2 will be missing texels.
1302 *
1303 * Fix this by calculating the base mip's width and height, then convert that, and round it
1304 * back up to get the level 0 size.
1305 * Clamp the converted size between the original values, and next power of two, which
1306 * means we don't oversize the image.
1307 */
1308 if (device->physical_device->rad_info.chip_class >= GFX9 &&
1309 vk_format_is_compressed(image->vk_format) &&
1310 !vk_format_is_compressed(iview->vk_format)) {
1311 unsigned lvl_width = radv_minify(image->info.width , range->baseMipLevel);
1312 unsigned lvl_height = radv_minify(image->info.height, range->baseMipLevel);
1313
1314 lvl_width = round_up_u32(lvl_width * view_bw, img_bw);
1315 lvl_height = round_up_u32(lvl_height * view_bh, img_bh);
1316
1317 lvl_width <<= range->baseMipLevel;
1318 lvl_height <<= range->baseMipLevel;
1319
1320 iview->extent.width = CLAMP(lvl_width, iview->extent.width, iview->image->planes[0].surface.u.gfx9.surf_pitch);
1321 iview->extent.height = CLAMP(lvl_height, iview->extent.height, iview->image->planes[0].surface.u.gfx9.surf_height);
1322 }
1323 }
1324
1325 iview->base_layer = range->baseArrayLayer;
1326 iview->layer_count = radv_get_layerCount(image, range);
1327 iview->base_mip = range->baseMipLevel;
1328 iview->level_count = radv_get_levelCount(image, range);
1329
1330 for (unsigned i = 0; i < (iview->multiple_planes ? vk_format_get_plane_count(image->vk_format) : 1); ++i) {
1331 VkFormat format = vk_format_get_plane_format(iview->vk_format, i);
1332 radv_image_view_make_descriptor(iview, device, format, &pCreateInfo->components, false, iview->plane_id + i, i);
1333 radv_image_view_make_descriptor(iview, device, format, &pCreateInfo->components, true, iview->plane_id + i, i);
1334 }
1335 }
1336
1337 bool radv_layout_has_htile(const struct radv_image *image,
1338 VkImageLayout layout,
1339 unsigned queue_mask)
1340 {
1341 if (radv_image_is_tc_compat_htile(image))
1342 return layout != VK_IMAGE_LAYOUT_GENERAL;
1343
1344 return radv_image_has_htile(image) &&
1345 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1346 (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1347 queue_mask == (1u << RADV_QUEUE_GENERAL)));
1348 }
1349
1350 bool radv_layout_is_htile_compressed(const struct radv_image *image,
1351 VkImageLayout layout,
1352 unsigned queue_mask)
1353 {
1354 if (radv_image_is_tc_compat_htile(image))
1355 return layout != VK_IMAGE_LAYOUT_GENERAL;
1356
1357 return radv_image_has_htile(image) &&
1358 (layout == VK_IMAGE_LAYOUT_DEPTH_STENCIL_ATTACHMENT_OPTIMAL ||
1359 (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1360 queue_mask == (1u << RADV_QUEUE_GENERAL)));
1361 }
1362
1363 bool radv_layout_can_fast_clear(const struct radv_image *image,
1364 VkImageLayout layout,
1365 unsigned queue_mask)
1366 {
1367 return layout == VK_IMAGE_LAYOUT_COLOR_ATTACHMENT_OPTIMAL;
1368 }
1369
1370 bool radv_layout_dcc_compressed(const struct radv_image *image,
1371 VkImageLayout layout,
1372 unsigned queue_mask)
1373 {
1374 /* Don't compress compute transfer dst, as image stores are not supported. */
1375 if (layout == VK_IMAGE_LAYOUT_TRANSFER_DST_OPTIMAL &&
1376 (queue_mask & (1u << RADV_QUEUE_COMPUTE)))
1377 return false;
1378
1379 return radv_image_has_dcc(image) && layout != VK_IMAGE_LAYOUT_GENERAL;
1380 }
1381
1382
1383 unsigned radv_image_queue_family_mask(const struct radv_image *image, uint32_t family, uint32_t queue_family)
1384 {
1385 if (!image->exclusive)
1386 return image->queue_family_mask;
1387 if (family == VK_QUEUE_FAMILY_EXTERNAL)
1388 return (1u << RADV_MAX_QUEUE_FAMILIES) - 1u;
1389 if (family == VK_QUEUE_FAMILY_IGNORED)
1390 return 1u << queue_family;
1391 return 1u << family;
1392 }
1393
1394 VkResult
1395 radv_CreateImage(VkDevice device,
1396 const VkImageCreateInfo *pCreateInfo,
1397 const VkAllocationCallbacks *pAllocator,
1398 VkImage *pImage)
1399 {
1400 #ifdef ANDROID
1401 const VkNativeBufferANDROID *gralloc_info =
1402 vk_find_struct_const(pCreateInfo->pNext, NATIVE_BUFFER_ANDROID);
1403
1404 if (gralloc_info)
1405 return radv_image_from_gralloc(device, pCreateInfo, gralloc_info,
1406 pAllocator, pImage);
1407 #endif
1408
1409 const struct wsi_image_create_info *wsi_info =
1410 vk_find_struct_const(pCreateInfo->pNext, WSI_IMAGE_CREATE_INFO_MESA);
1411 bool scanout = wsi_info && wsi_info->scanout;
1412
1413 return radv_image_create(device,
1414 &(struct radv_image_create_info) {
1415 .vk_info = pCreateInfo,
1416 .scanout = scanout,
1417 },
1418 pAllocator,
1419 pImage);
1420 }
1421
1422 void
1423 radv_DestroyImage(VkDevice _device, VkImage _image,
1424 const VkAllocationCallbacks *pAllocator)
1425 {
1426 RADV_FROM_HANDLE(radv_device, device, _device);
1427 RADV_FROM_HANDLE(radv_image, image, _image);
1428
1429 if (!image)
1430 return;
1431
1432 if (image->flags & VK_IMAGE_CREATE_SPARSE_BINDING_BIT)
1433 device->ws->buffer_destroy(image->bo);
1434
1435 if (image->owned_memory != VK_NULL_HANDLE)
1436 radv_FreeMemory(_device, image->owned_memory, pAllocator);
1437
1438 vk_free2(&device->alloc, pAllocator, image);
1439 }
1440
1441 void radv_GetImageSubresourceLayout(
1442 VkDevice _device,
1443 VkImage _image,
1444 const VkImageSubresource* pSubresource,
1445 VkSubresourceLayout* pLayout)
1446 {
1447 RADV_FROM_HANDLE(radv_image, image, _image);
1448 RADV_FROM_HANDLE(radv_device, device, _device);
1449 int level = pSubresource->mipLevel;
1450 int layer = pSubresource->arrayLayer;
1451
1452 unsigned plane_id = radv_plane_from_aspect(pSubresource->aspectMask);
1453
1454 struct radv_image_plane *plane = &image->planes[plane_id];
1455 struct radeon_surf *surface = &plane->surface;
1456
1457 if (device->physical_device->rad_info.chip_class >= GFX9) {
1458 pLayout->offset = plane->offset + surface->u.gfx9.offset[level] + surface->u.gfx9.surf_slice_size * layer;
1459 if (image->vk_format == VK_FORMAT_R32G32B32_UINT ||
1460 image->vk_format == VK_FORMAT_R32G32B32_SINT ||
1461 image->vk_format == VK_FORMAT_R32G32B32_SFLOAT) {
1462 /* Adjust the number of bytes between each row because
1463 * the pitch is actually the number of components per
1464 * row.
1465 */
1466 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe / 3;
1467 } else {
1468 assert(util_is_power_of_two_nonzero(surface->bpe));
1469 pLayout->rowPitch = surface->u.gfx9.surf_pitch * surface->bpe;
1470 }
1471
1472 pLayout->arrayPitch = surface->u.gfx9.surf_slice_size;
1473 pLayout->depthPitch = surface->u.gfx9.surf_slice_size;
1474 pLayout->size = surface->u.gfx9.surf_slice_size;
1475 if (image->type == VK_IMAGE_TYPE_3D)
1476 pLayout->size *= u_minify(image->info.depth, level);
1477 } else {
1478 pLayout->offset = plane->offset + surface->u.legacy.level[level].offset + (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4 * layer;
1479 pLayout->rowPitch = surface->u.legacy.level[level].nblk_x * surface->bpe;
1480 pLayout->arrayPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1481 pLayout->depthPitch = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1482 pLayout->size = (uint64_t)surface->u.legacy.level[level].slice_size_dw * 4;
1483 if (image->type == VK_IMAGE_TYPE_3D)
1484 pLayout->size *= u_minify(image->info.depth, level);
1485 }
1486 }
1487
1488
1489 VkResult
1490 radv_CreateImageView(VkDevice _device,
1491 const VkImageViewCreateInfo *pCreateInfo,
1492 const VkAllocationCallbacks *pAllocator,
1493 VkImageView *pView)
1494 {
1495 RADV_FROM_HANDLE(radv_device, device, _device);
1496 struct radv_image_view *view;
1497
1498 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1499 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1500 if (view == NULL)
1501 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1502
1503 radv_image_view_init(view, device, pCreateInfo);
1504
1505 *pView = radv_image_view_to_handle(view);
1506
1507 return VK_SUCCESS;
1508 }
1509
1510 void
1511 radv_DestroyImageView(VkDevice _device, VkImageView _iview,
1512 const VkAllocationCallbacks *pAllocator)
1513 {
1514 RADV_FROM_HANDLE(radv_device, device, _device);
1515 RADV_FROM_HANDLE(radv_image_view, iview, _iview);
1516
1517 if (!iview)
1518 return;
1519 vk_free2(&device->alloc, pAllocator, iview);
1520 }
1521
1522 void radv_buffer_view_init(struct radv_buffer_view *view,
1523 struct radv_device *device,
1524 const VkBufferViewCreateInfo* pCreateInfo)
1525 {
1526 RADV_FROM_HANDLE(radv_buffer, buffer, pCreateInfo->buffer);
1527
1528 view->bo = buffer->bo;
1529 view->range = pCreateInfo->range == VK_WHOLE_SIZE ?
1530 buffer->size - pCreateInfo->offset : pCreateInfo->range;
1531 view->vk_format = pCreateInfo->format;
1532
1533 radv_make_buffer_descriptor(device, buffer, view->vk_format,
1534 pCreateInfo->offset, view->range, view->state);
1535 }
1536
1537 VkResult
1538 radv_CreateBufferView(VkDevice _device,
1539 const VkBufferViewCreateInfo *pCreateInfo,
1540 const VkAllocationCallbacks *pAllocator,
1541 VkBufferView *pView)
1542 {
1543 RADV_FROM_HANDLE(radv_device, device, _device);
1544 struct radv_buffer_view *view;
1545
1546 view = vk_alloc2(&device->alloc, pAllocator, sizeof(*view), 8,
1547 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
1548 if (!view)
1549 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
1550
1551 radv_buffer_view_init(view, device, pCreateInfo);
1552
1553 *pView = radv_buffer_view_to_handle(view);
1554
1555 return VK_SUCCESS;
1556 }
1557
1558 void
1559 radv_DestroyBufferView(VkDevice _device, VkBufferView bufferView,
1560 const VkAllocationCallbacks *pAllocator)
1561 {
1562 RADV_FROM_HANDLE(radv_device, device, _device);
1563 RADV_FROM_HANDLE(radv_buffer_view, view, bufferView);
1564
1565 if (!view)
1566 return;
1567
1568 vk_free2(&device->alloc, pAllocator, view);
1569 }