radv/meta: cleanup some unused code path
[mesa.git] / src / amd / vulkan / radv_meta.c
1 /*
2 * Copyright © 2016 Red Hat
3 * based on intel anv code:
4 * Copyright © 2015 Intel Corporation
5 *
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
12 *
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
15 * Software.
16 *
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
23 * IN THE SOFTWARE.
24 */
25
26 #include "radv_meta.h"
27
28 #include <fcntl.h>
29 #include <limits.h>
30 #include <pwd.h>
31 #include <sys/stat.h>
32
33 static void
34 radv_meta_save_novertex(struct radv_meta_saved_state *state,
35 const struct radv_cmd_buffer *cmd_buffer,
36 uint32_t dynamic_mask)
37 {
38 state->old_pipeline = cmd_buffer->state.pipeline;
39
40 state->dynamic_mask = dynamic_mask;
41 radv_dynamic_state_copy(&state->dynamic, &cmd_buffer->state.dynamic,
42 dynamic_mask);
43
44 memcpy(state->push_constants, cmd_buffer->push_constants, MAX_PUSH_CONSTANTS_SIZE);
45 state->vertex_saved = false;
46 }
47
48 void
49 radv_meta_restore(const struct radv_meta_saved_state *state,
50 struct radv_cmd_buffer *cmd_buffer)
51 {
52 cmd_buffer->state.pipeline = state->old_pipeline;
53 if (state->vertex_saved) {
54 cmd_buffer->state.descriptors[0] = state->old_descriptor_set0;
55 cmd_buffer->state.descriptors_dirty |= (1u << 0);
56 memcpy(cmd_buffer->state.vertex_bindings, state->old_vertex_bindings,
57 sizeof(state->old_vertex_bindings));
58 cmd_buffer->state.vb_dirty |= (1 << RADV_META_VERTEX_BINDING_COUNT) - 1;
59 }
60
61 cmd_buffer->state.dirty |= RADV_CMD_DIRTY_PIPELINE;
62
63 radv_dynamic_state_copy(&cmd_buffer->state.dynamic, &state->dynamic,
64 state->dynamic_mask);
65 cmd_buffer->state.dirty |= state->dynamic_mask;
66
67 memcpy(cmd_buffer->push_constants, state->push_constants, MAX_PUSH_CONSTANTS_SIZE);
68 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_ALL_GRAPHICS | VK_SHADER_STAGE_COMPUTE_BIT;
69 }
70
71 void
72 radv_meta_save_pass(struct radv_meta_saved_pass_state *state,
73 const struct radv_cmd_buffer *cmd_buffer)
74 {
75 state->pass = cmd_buffer->state.pass;
76 state->subpass = cmd_buffer->state.subpass;
77 state->framebuffer = cmd_buffer->state.framebuffer;
78 state->attachments = cmd_buffer->state.attachments;
79 state->render_area = cmd_buffer->state.render_area;
80 }
81
82 void
83 radv_meta_restore_pass(const struct radv_meta_saved_pass_state *state,
84 struct radv_cmd_buffer *cmd_buffer)
85 {
86 cmd_buffer->state.pass = state->pass;
87 cmd_buffer->state.subpass = state->subpass;
88 cmd_buffer->state.framebuffer = state->framebuffer;
89 cmd_buffer->state.attachments = state->attachments;
90 cmd_buffer->state.render_area = state->render_area;
91 if (state->subpass)
92 radv_emit_framebuffer_state(cmd_buffer);
93 }
94
95 void
96 radv_meta_save_compute(struct radv_meta_saved_compute_state *state,
97 const struct radv_cmd_buffer *cmd_buffer,
98 unsigned push_constant_size)
99 {
100 state->old_pipeline = cmd_buffer->state.compute_pipeline;
101 state->old_descriptor_set0 = cmd_buffer->state.descriptors[0];
102
103 if (push_constant_size)
104 memcpy(state->push_constants, cmd_buffer->push_constants, push_constant_size);
105 }
106
107 void
108 radv_meta_restore_compute(const struct radv_meta_saved_compute_state *state,
109 struct radv_cmd_buffer *cmd_buffer,
110 unsigned push_constant_size)
111 {
112 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer), VK_PIPELINE_BIND_POINT_COMPUTE,
113 radv_pipeline_to_handle(state->old_pipeline));
114
115 cmd_buffer->state.descriptors[0] = state->old_descriptor_set0;
116 cmd_buffer->state.descriptors_dirty |= (1u << 0);
117
118 if (push_constant_size) {
119 memcpy(cmd_buffer->push_constants, state->push_constants, push_constant_size);
120 cmd_buffer->push_constant_stages |= VK_SHADER_STAGE_COMPUTE_BIT;
121 }
122 }
123
124 VkImageViewType
125 radv_meta_get_view_type(const struct radv_image *image)
126 {
127 switch (image->type) {
128 case VK_IMAGE_TYPE_1D: return VK_IMAGE_VIEW_TYPE_1D;
129 case VK_IMAGE_TYPE_2D: return VK_IMAGE_VIEW_TYPE_2D;
130 case VK_IMAGE_TYPE_3D: return VK_IMAGE_VIEW_TYPE_3D;
131 default:
132 unreachable("bad VkImageViewType");
133 }
134 }
135
136 /**
137 * When creating a destination VkImageView, this function provides the needed
138 * VkImageViewCreateInfo::subresourceRange::baseArrayLayer.
139 */
140 uint32_t
141 radv_meta_get_iview_layer(const struct radv_image *dest_image,
142 const VkImageSubresourceLayers *dest_subresource,
143 const VkOffset3D *dest_offset)
144 {
145 switch (dest_image->type) {
146 case VK_IMAGE_TYPE_1D:
147 case VK_IMAGE_TYPE_2D:
148 return dest_subresource->baseArrayLayer;
149 case VK_IMAGE_TYPE_3D:
150 /* HACK: Vulkan does not allow attaching a 3D image to a framebuffer,
151 * but meta does it anyway. When doing so, we translate the
152 * destination's z offset into an array offset.
153 */
154 return dest_offset->z;
155 default:
156 assert(!"bad VkImageType");
157 return 0;
158 }
159 }
160
161 static void *
162 meta_alloc(void* _device, size_t size, size_t alignment,
163 VkSystemAllocationScope allocationScope)
164 {
165 struct radv_device *device = _device;
166 return device->alloc.pfnAllocation(device->alloc.pUserData, size, alignment,
167 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
168 }
169
170 static void *
171 meta_realloc(void* _device, void *original, size_t size, size_t alignment,
172 VkSystemAllocationScope allocationScope)
173 {
174 struct radv_device *device = _device;
175 return device->alloc.pfnReallocation(device->alloc.pUserData, original,
176 size, alignment,
177 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE);
178 }
179
180 static void
181 meta_free(void* _device, void *data)
182 {
183 struct radv_device *device = _device;
184 return device->alloc.pfnFree(device->alloc.pUserData, data);
185 }
186
187 static bool
188 radv_builtin_cache_path(char *path)
189 {
190 char *xdg_cache_home = getenv("XDG_CACHE_HOME");
191 const char *suffix = "/radv_builtin_shaders";
192 const char *suffix2 = "/.cache/radv_builtin_shaders";
193 struct passwd pwd, *result;
194 char path2[PATH_MAX + 1]; /* PATH_MAX is not a real max,but suffices here. */
195
196 if (xdg_cache_home) {
197
198 if (strlen(xdg_cache_home) + strlen(suffix) > PATH_MAX)
199 return false;
200
201 strcpy(path, xdg_cache_home);
202 strcat(path, suffix);
203 return true;
204 }
205
206 getpwuid_r(getuid(), &pwd, path2, PATH_MAX - strlen(suffix2), &result);
207 if (!result)
208 return false;
209
210 strcpy(path, pwd.pw_dir);
211 strcat(path, "/.cache");
212 mkdir(path, 0755);
213
214 strcat(path, suffix);
215 return true;
216 }
217
218 static void
219 radv_load_meta_pipeline(struct radv_device *device)
220 {
221 char path[PATH_MAX + 1];
222 struct stat st;
223 void *data = NULL;
224
225 if (!radv_builtin_cache_path(path))
226 return;
227
228 int fd = open(path, O_RDONLY);
229 if (fd < 0)
230 return;
231 if (fstat(fd, &st))
232 goto fail;
233 data = malloc(st.st_size);
234 if (!data)
235 goto fail;
236 if(read(fd, data, st.st_size) == -1)
237 goto fail;
238
239 radv_pipeline_cache_load(&device->meta_state.cache, data, st.st_size);
240 fail:
241 free(data);
242 close(fd);
243 }
244
245 static void
246 radv_store_meta_pipeline(struct radv_device *device)
247 {
248 char path[PATH_MAX + 1], path2[PATH_MAX + 7];
249 size_t size;
250 void *data = NULL;
251
252 if (!device->meta_state.cache.modified)
253 return;
254
255 if (radv_GetPipelineCacheData(radv_device_to_handle(device),
256 radv_pipeline_cache_to_handle(&device->meta_state.cache),
257 &size, NULL))
258 return;
259
260 if (!radv_builtin_cache_path(path))
261 return;
262
263 strcpy(path2, path);
264 strcat(path2, "XXXXXX");
265 int fd = mkstemp(path2);//open(path, O_WRONLY | O_CREAT, 0600);
266 if (fd < 0)
267 return;
268 data = malloc(size);
269 if (!data)
270 goto fail;
271
272 if (radv_GetPipelineCacheData(radv_device_to_handle(device),
273 radv_pipeline_cache_to_handle(&device->meta_state.cache),
274 &size, data))
275 goto fail;
276 if(write(fd, data, size) == -1)
277 goto fail;
278
279 rename(path2, path);
280 fail:
281 free(data);
282 close(fd);
283 unlink(path2);
284 }
285
286 VkResult
287 radv_device_init_meta(struct radv_device *device)
288 {
289 VkResult result;
290
291 device->meta_state.alloc = (VkAllocationCallbacks) {
292 .pUserData = device,
293 .pfnAllocation = meta_alloc,
294 .pfnReallocation = meta_realloc,
295 .pfnFree = meta_free,
296 };
297
298 device->meta_state.cache.alloc = device->meta_state.alloc;
299 radv_pipeline_cache_init(&device->meta_state.cache, device);
300 radv_load_meta_pipeline(device);
301
302 result = radv_device_init_meta_clear_state(device);
303 if (result != VK_SUCCESS)
304 goto fail_clear;
305
306 result = radv_device_init_meta_resolve_state(device);
307 if (result != VK_SUCCESS)
308 goto fail_resolve;
309
310 result = radv_device_init_meta_blit_state(device);
311 if (result != VK_SUCCESS)
312 goto fail_blit;
313
314 result = radv_device_init_meta_blit2d_state(device);
315 if (result != VK_SUCCESS)
316 goto fail_blit2d;
317
318 result = radv_device_init_meta_bufimage_state(device);
319 if (result != VK_SUCCESS)
320 goto fail_bufimage;
321
322 result = radv_device_init_meta_depth_decomp_state(device);
323 if (result != VK_SUCCESS)
324 goto fail_depth_decomp;
325
326 result = radv_device_init_meta_buffer_state(device);
327 if (result != VK_SUCCESS)
328 goto fail_buffer;
329
330 result = radv_device_init_meta_query_state(device);
331 if (result != VK_SUCCESS)
332 goto fail_query;
333
334 result = radv_device_init_meta_fast_clear_flush_state(device);
335 if (result != VK_SUCCESS)
336 goto fail_fast_clear;
337
338 result = radv_device_init_meta_resolve_compute_state(device);
339 if (result != VK_SUCCESS)
340 goto fail_resolve_compute;
341
342 result = radv_device_init_meta_resolve_fragment_state(device);
343 if (result != VK_SUCCESS)
344 goto fail_resolve_fragment;
345 return VK_SUCCESS;
346
347 fail_resolve_fragment:
348 radv_device_finish_meta_resolve_compute_state(device);
349 fail_resolve_compute:
350 radv_device_finish_meta_fast_clear_flush_state(device);
351 fail_fast_clear:
352 radv_device_finish_meta_buffer_state(device);
353 fail_query:
354 radv_device_finish_meta_query_state(device);
355 fail_buffer:
356 radv_device_finish_meta_depth_decomp_state(device);
357 fail_depth_decomp:
358 radv_device_finish_meta_bufimage_state(device);
359 fail_bufimage:
360 radv_device_finish_meta_blit2d_state(device);
361 fail_blit2d:
362 radv_device_finish_meta_blit_state(device);
363 fail_blit:
364 radv_device_finish_meta_resolve_state(device);
365 fail_resolve:
366 radv_device_finish_meta_clear_state(device);
367 fail_clear:
368 radv_pipeline_cache_finish(&device->meta_state.cache);
369 return result;
370 }
371
372 void
373 radv_device_finish_meta(struct radv_device *device)
374 {
375 radv_device_finish_meta_clear_state(device);
376 radv_device_finish_meta_resolve_state(device);
377 radv_device_finish_meta_blit_state(device);
378 radv_device_finish_meta_blit2d_state(device);
379 radv_device_finish_meta_bufimage_state(device);
380 radv_device_finish_meta_depth_decomp_state(device);
381 radv_device_finish_meta_query_state(device);
382 radv_device_finish_meta_buffer_state(device);
383 radv_device_finish_meta_fast_clear_flush_state(device);
384 radv_device_finish_meta_resolve_compute_state(device);
385 radv_device_finish_meta_resolve_fragment_state(device);
386
387 radv_store_meta_pipeline(device);
388 radv_pipeline_cache_finish(&device->meta_state.cache);
389 }
390
391 /*
392 * The most common meta operations all want to have the viewport
393 * reset and any scissors disabled. The rest of the dynamic state
394 * should have no effect.
395 */
396 void
397 radv_meta_save_graphics_reset_vport_scissor_novertex(struct radv_meta_saved_state *saved_state,
398 struct radv_cmd_buffer *cmd_buffer)
399 {
400 uint32_t dirty_state = (1 << VK_DYNAMIC_STATE_VIEWPORT) | (1 << VK_DYNAMIC_STATE_SCISSOR);
401 radv_meta_save_novertex(saved_state, cmd_buffer, dirty_state);
402 cmd_buffer->state.dynamic.viewport.count = 0;
403 cmd_buffer->state.dynamic.scissor.count = 0;
404 cmd_buffer->state.dirty |= dirty_state;
405 }
406
407 nir_ssa_def *radv_meta_gen_rect_vertices_comp2(nir_builder *vs_b, nir_ssa_def *comp2)
408 {
409
410 nir_intrinsic_instr *vertex_id = nir_intrinsic_instr_create(vs_b->shader, nir_intrinsic_load_vertex_id_zero_base);
411 nir_ssa_dest_init(&vertex_id->instr, &vertex_id->dest, 1, 32, "vertexid");
412 nir_builder_instr_insert(vs_b, &vertex_id->instr);
413
414 /* vertex 0 - -1.0, -1.0 */
415 /* vertex 1 - -1.0, 1.0 */
416 /* vertex 2 - 1.0, -1.0 */
417 /* so channel 0 is vertex_id != 2 ? -1.0 : 1.0
418 channel 1 is vertex id != 1 ? -1.0 : 1.0 */
419
420 nir_ssa_def *c0cmp = nir_ine(vs_b, &vertex_id->dest.ssa,
421 nir_imm_int(vs_b, 2));
422 nir_ssa_def *c1cmp = nir_ine(vs_b, &vertex_id->dest.ssa,
423 nir_imm_int(vs_b, 1));
424
425 nir_ssa_def *comp[4];
426 comp[0] = nir_bcsel(vs_b, c0cmp,
427 nir_imm_float(vs_b, -1.0),
428 nir_imm_float(vs_b, 1.0));
429
430 comp[1] = nir_bcsel(vs_b, c1cmp,
431 nir_imm_float(vs_b, -1.0),
432 nir_imm_float(vs_b, 1.0));
433 comp[2] = comp2;
434 comp[3] = nir_imm_float(vs_b, 1.0);
435 nir_ssa_def *outvec = nir_vec(vs_b, comp, 4);
436
437 return outvec;
438 }
439
440 nir_ssa_def *radv_meta_gen_rect_vertices(nir_builder *vs_b)
441 {
442 return radv_meta_gen_rect_vertices_comp2(vs_b, nir_imm_float(vs_b, 0.0));
443 }
444
445 /* vertex shader that generates vertices */
446 nir_shader *
447 radv_meta_build_nir_vs_generate_vertices(void)
448 {
449 const struct glsl_type *vec4 = glsl_vec4_type();
450
451 nir_builder b;
452 nir_variable *v_position;
453
454 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_VERTEX, NULL);
455 b.shader->info->name = ralloc_strdup(b.shader, "meta_vs_gen_verts");
456
457 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&b);
458
459 v_position = nir_variable_create(b.shader, nir_var_shader_out, vec4,
460 "gl_Position");
461 v_position->data.location = VARYING_SLOT_POS;
462
463 nir_store_var(&b, v_position, outvec, 0xf);
464
465 return b.shader;
466 }
467
468 nir_shader *
469 radv_meta_build_nir_fs_noop(void)
470 {
471 nir_builder b;
472
473 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
474 b.shader->info->name = ralloc_asprintf(b.shader,
475 "meta_noop_fs");
476
477 return b.shader;
478 }
479
480 static nir_ssa_def *radv_meta_build_resolve_srgb_conversion(nir_builder *b,
481 nir_ssa_def *input)
482 {
483 nir_const_value v;
484 unsigned i;
485 v.u32[0] = 0x3b4d2e1c; // 0.00313080009
486
487 nir_ssa_def *cmp[3];
488 for (i = 0; i < 3; i++)
489 cmp[i] = nir_flt(b, nir_channel(b, input, i),
490 nir_build_imm(b, 1, 32, v));
491
492 nir_ssa_def *ltvals[3];
493 v.f32[0] = 12.92;
494 for (i = 0; i < 3; i++)
495 ltvals[i] = nir_fmul(b, nir_channel(b, input, i),
496 nir_build_imm(b, 1, 32, v));
497
498 nir_ssa_def *gtvals[3];
499
500 for (i = 0; i < 3; i++) {
501 v.f32[0] = 1.0/2.4;
502 gtvals[i] = nir_fpow(b, nir_channel(b, input, i),
503 nir_build_imm(b, 1, 32, v));
504 v.f32[0] = 1.055;
505 gtvals[i] = nir_fmul(b, gtvals[i],
506 nir_build_imm(b, 1, 32, v));
507 v.f32[0] = 0.055;
508 gtvals[i] = nir_fsub(b, gtvals[i],
509 nir_build_imm(b, 1, 32, v));
510 }
511
512 nir_ssa_def *comp[4];
513 for (i = 0; i < 3; i++)
514 comp[i] = nir_bcsel(b, cmp[i], ltvals[i], gtvals[i]);
515 comp[3] = nir_channels(b, input, 3);
516 return nir_vec(b, comp, 4);
517 }
518
519 void radv_meta_build_resolve_shader_core(nir_builder *b,
520 bool is_integer,
521 bool is_srgb,
522 int samples,
523 nir_variable *input_img,
524 nir_variable *color,
525 nir_ssa_def *img_coord)
526 {
527 /* do a txf_ms on each sample */
528 nir_ssa_def *tmp;
529 nir_if *outer_if = NULL;
530
531 nir_tex_instr *tex = nir_tex_instr_create(b->shader, 2);
532 tex->sampler_dim = GLSL_SAMPLER_DIM_MS;
533 tex->op = nir_texop_txf_ms;
534 tex->src[0].src_type = nir_tex_src_coord;
535 tex->src[0].src = nir_src_for_ssa(img_coord);
536 tex->src[1].src_type = nir_tex_src_ms_index;
537 tex->src[1].src = nir_src_for_ssa(nir_imm_int(b, 0));
538 tex->dest_type = nir_type_float;
539 tex->is_array = false;
540 tex->coord_components = 2;
541 tex->texture = nir_deref_var_create(tex, input_img);
542 tex->sampler = NULL;
543
544 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
545 nir_builder_instr_insert(b, &tex->instr);
546
547 tmp = &tex->dest.ssa;
548
549 if (!is_integer && samples > 1) {
550 nir_tex_instr *tex_all_same = nir_tex_instr_create(b->shader, 1);
551 tex_all_same->sampler_dim = GLSL_SAMPLER_DIM_MS;
552 tex_all_same->op = nir_texop_samples_identical;
553 tex_all_same->src[0].src_type = nir_tex_src_coord;
554 tex_all_same->src[0].src = nir_src_for_ssa(img_coord);
555 tex_all_same->dest_type = nir_type_float;
556 tex_all_same->is_array = false;
557 tex_all_same->coord_components = 2;
558 tex_all_same->texture = nir_deref_var_create(tex_all_same, input_img);
559 tex_all_same->sampler = NULL;
560
561 nir_ssa_dest_init(&tex_all_same->instr, &tex_all_same->dest, 1, 32, "tex");
562 nir_builder_instr_insert(b, &tex_all_same->instr);
563
564 nir_ssa_def *all_same = nir_ine(b, &tex_all_same->dest.ssa, nir_imm_int(b, 0));
565 nir_if *if_stmt = nir_if_create(b->shader);
566 if_stmt->condition = nir_src_for_ssa(all_same);
567 nir_cf_node_insert(b->cursor, &if_stmt->cf_node);
568
569 b->cursor = nir_after_cf_list(&if_stmt->then_list);
570 for (int i = 1; i < samples; i++) {
571 nir_tex_instr *tex_add = nir_tex_instr_create(b->shader, 2);
572 tex_add->sampler_dim = GLSL_SAMPLER_DIM_MS;
573 tex_add->op = nir_texop_txf_ms;
574 tex_add->src[0].src_type = nir_tex_src_coord;
575 tex_add->src[0].src = nir_src_for_ssa(img_coord);
576 tex_add->src[1].src_type = nir_tex_src_ms_index;
577 tex_add->src[1].src = nir_src_for_ssa(nir_imm_int(b, i));
578 tex_add->dest_type = nir_type_float;
579 tex_add->is_array = false;
580 tex_add->coord_components = 2;
581 tex_add->texture = nir_deref_var_create(tex_add, input_img);
582 tex_add->sampler = NULL;
583
584 nir_ssa_dest_init(&tex_add->instr, &tex_add->dest, 4, 32, "tex");
585 nir_builder_instr_insert(b, &tex_add->instr);
586
587 tmp = nir_fadd(b, tmp, &tex_add->dest.ssa);
588 }
589
590 tmp = nir_fdiv(b, tmp, nir_imm_float(b, samples));
591 nir_store_var(b, color, tmp, 0xf);
592 b->cursor = nir_after_cf_list(&if_stmt->else_list);
593 outer_if = if_stmt;
594 }
595 nir_store_var(b, color, &tex->dest.ssa, 0xf);
596
597 if (outer_if)
598 b->cursor = nir_after_cf_node(&outer_if->cf_node);
599
600 if (is_srgb) {
601 nir_ssa_def *newv = nir_load_var(b, color);
602 newv = radv_meta_build_resolve_srgb_conversion(b, newv);
603 nir_store_var(b, color, newv, 0xf);
604 }
605 }