2 * Copyright © 2016 Red Hat
3 * based on intel anv code:
4 * Copyright © 2015 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "radv_meta.h"
34 radv_meta_save_novertex(struct radv_meta_saved_state
*state
,
35 const struct radv_cmd_buffer
*cmd_buffer
,
36 uint32_t dynamic_mask
)
38 state
->old_pipeline
= cmd_buffer
->state
.pipeline
;
39 state
->old_descriptor_set0
= cmd_buffer
->state
.descriptors
[0];
41 state
->dynamic_mask
= dynamic_mask
;
42 radv_dynamic_state_copy(&state
->dynamic
, &cmd_buffer
->state
.dynamic
,
45 memcpy(state
->push_constants
, cmd_buffer
->push_constants
, MAX_PUSH_CONSTANTS_SIZE
);
46 state
->vertex_saved
= false;
50 radv_meta_restore(const struct radv_meta_saved_state
*state
,
51 struct radv_cmd_buffer
*cmd_buffer
)
53 cmd_buffer
->state
.pipeline
= state
->old_pipeline
;
54 cmd_buffer
->state
.descriptors
[0] = state
->old_descriptor_set0
;
55 cmd_buffer
->state
.descriptors_dirty
|= (1u << 0);
56 if (state
->vertex_saved
) {
57 memcpy(cmd_buffer
->state
.vertex_bindings
, state
->old_vertex_bindings
,
58 sizeof(state
->old_vertex_bindings
));
59 cmd_buffer
->state
.vb_dirty
|= (1 << RADV_META_VERTEX_BINDING_COUNT
) - 1;
62 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
64 radv_dynamic_state_copy(&cmd_buffer
->state
.dynamic
, &state
->dynamic
,
66 cmd_buffer
->state
.dirty
|= state
->dynamic_mask
;
68 memcpy(cmd_buffer
->push_constants
, state
->push_constants
, MAX_PUSH_CONSTANTS_SIZE
);
69 cmd_buffer
->push_constant_stages
|= VK_SHADER_STAGE_ALL_GRAPHICS
| VK_SHADER_STAGE_COMPUTE_BIT
;
73 radv_meta_save_pass(struct radv_meta_saved_pass_state
*state
,
74 const struct radv_cmd_buffer
*cmd_buffer
)
76 state
->pass
= cmd_buffer
->state
.pass
;
77 state
->subpass
= cmd_buffer
->state
.subpass
;
78 state
->framebuffer
= cmd_buffer
->state
.framebuffer
;
79 state
->attachments
= cmd_buffer
->state
.attachments
;
80 state
->render_area
= cmd_buffer
->state
.render_area
;
84 radv_meta_restore_pass(const struct radv_meta_saved_pass_state
*state
,
85 struct radv_cmd_buffer
*cmd_buffer
)
87 cmd_buffer
->state
.pass
= state
->pass
;
88 cmd_buffer
->state
.subpass
= state
->subpass
;
89 cmd_buffer
->state
.framebuffer
= state
->framebuffer
;
90 cmd_buffer
->state
.attachments
= state
->attachments
;
91 cmd_buffer
->state
.render_area
= state
->render_area
;
93 radv_emit_framebuffer_state(cmd_buffer
);
97 radv_meta_save_compute(struct radv_meta_saved_compute_state
*state
,
98 const struct radv_cmd_buffer
*cmd_buffer
,
99 unsigned push_constant_size
)
101 state
->old_pipeline
= cmd_buffer
->state
.compute_pipeline
;
102 state
->old_descriptor_set0
= cmd_buffer
->state
.descriptors
[0];
104 if (push_constant_size
)
105 memcpy(state
->push_constants
, cmd_buffer
->push_constants
, push_constant_size
);
109 radv_meta_restore_compute(const struct radv_meta_saved_compute_state
*state
,
110 struct radv_cmd_buffer
*cmd_buffer
,
111 unsigned push_constant_size
)
113 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
), VK_PIPELINE_BIND_POINT_COMPUTE
,
114 radv_pipeline_to_handle(state
->old_pipeline
));
116 cmd_buffer
->state
.descriptors
[0] = state
->old_descriptor_set0
;
117 cmd_buffer
->state
.descriptors_dirty
|= (1u << 0);
119 if (push_constant_size
) {
120 memcpy(cmd_buffer
->push_constants
, state
->push_constants
, push_constant_size
);
121 cmd_buffer
->push_constant_stages
|= VK_SHADER_STAGE_COMPUTE_BIT
;
126 radv_meta_get_view_type(const struct radv_image
*image
)
128 switch (image
->type
) {
129 case VK_IMAGE_TYPE_1D
: return VK_IMAGE_VIEW_TYPE_1D
;
130 case VK_IMAGE_TYPE_2D
: return VK_IMAGE_VIEW_TYPE_2D
;
131 case VK_IMAGE_TYPE_3D
: return VK_IMAGE_VIEW_TYPE_3D
;
133 unreachable("bad VkImageViewType");
138 * When creating a destination VkImageView, this function provides the needed
139 * VkImageViewCreateInfo::subresourceRange::baseArrayLayer.
142 radv_meta_get_iview_layer(const struct radv_image
*dest_image
,
143 const VkImageSubresourceLayers
*dest_subresource
,
144 const VkOffset3D
*dest_offset
)
146 switch (dest_image
->type
) {
147 case VK_IMAGE_TYPE_1D
:
148 case VK_IMAGE_TYPE_2D
:
149 return dest_subresource
->baseArrayLayer
;
150 case VK_IMAGE_TYPE_3D
:
151 /* HACK: Vulkan does not allow attaching a 3D image to a framebuffer,
152 * but meta does it anyway. When doing so, we translate the
153 * destination's z offset into an array offset.
155 return dest_offset
->z
;
157 assert(!"bad VkImageType");
163 meta_alloc(void* _device
, size_t size
, size_t alignment
,
164 VkSystemAllocationScope allocationScope
)
166 struct radv_device
*device
= _device
;
167 return device
->alloc
.pfnAllocation(device
->alloc
.pUserData
, size
, alignment
,
168 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
172 meta_realloc(void* _device
, void *original
, size_t size
, size_t alignment
,
173 VkSystemAllocationScope allocationScope
)
175 struct radv_device
*device
= _device
;
176 return device
->alloc
.pfnReallocation(device
->alloc
.pUserData
, original
,
178 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
182 meta_free(void* _device
, void *data
)
184 struct radv_device
*device
= _device
;
185 return device
->alloc
.pfnFree(device
->alloc
.pUserData
, data
);
189 radv_builtin_cache_path(char *path
)
191 char *xdg_cache_home
= getenv("XDG_CACHE_HOME");
192 const char *suffix
= "/radv_builtin_shaders";
193 const char *suffix2
= "/.cache/radv_builtin_shaders";
194 struct passwd pwd
, *result
;
195 char path2
[PATH_MAX
+ 1]; /* PATH_MAX is not a real max,but suffices here. */
197 if (xdg_cache_home
) {
199 if (strlen(xdg_cache_home
) + strlen(suffix
) > PATH_MAX
)
202 strcpy(path
, xdg_cache_home
);
203 strcat(path
, suffix
);
207 getpwuid_r(getuid(), &pwd
, path2
, PATH_MAX
- strlen(suffix2
), &result
);
211 strcpy(path
, pwd
.pw_dir
);
212 strcat(path
, "/.cache");
215 strcat(path
, suffix
);
220 radv_load_meta_pipeline(struct radv_device
*device
)
222 char path
[PATH_MAX
+ 1];
226 if (!radv_builtin_cache_path(path
))
229 int fd
= open(path
, O_RDONLY
);
234 data
= malloc(st
.st_size
);
237 if(read(fd
, data
, st
.st_size
) == -1)
240 radv_pipeline_cache_load(&device
->meta_state
.cache
, data
, st
.st_size
);
247 radv_store_meta_pipeline(struct radv_device
*device
)
249 char path
[PATH_MAX
+ 1], path2
[PATH_MAX
+ 7];
253 if (!device
->meta_state
.cache
.modified
)
256 if (radv_GetPipelineCacheData(radv_device_to_handle(device
),
257 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
261 if (!radv_builtin_cache_path(path
))
265 strcat(path2
, "XXXXXX");
266 int fd
= mkstemp(path2
);//open(path, O_WRONLY | O_CREAT, 0600);
273 if (radv_GetPipelineCacheData(radv_device_to_handle(device
),
274 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
277 if(write(fd
, data
, size
) == -1)
288 radv_device_init_meta(struct radv_device
*device
)
292 device
->meta_state
.alloc
= (VkAllocationCallbacks
) {
294 .pfnAllocation
= meta_alloc
,
295 .pfnReallocation
= meta_realloc
,
296 .pfnFree
= meta_free
,
299 device
->meta_state
.cache
.alloc
= device
->meta_state
.alloc
;
300 radv_pipeline_cache_init(&device
->meta_state
.cache
, device
);
301 radv_load_meta_pipeline(device
);
303 result
= radv_device_init_meta_clear_state(device
);
304 if (result
!= VK_SUCCESS
)
307 result
= radv_device_init_meta_resolve_state(device
);
308 if (result
!= VK_SUCCESS
)
311 result
= radv_device_init_meta_blit_state(device
);
312 if (result
!= VK_SUCCESS
)
315 result
= radv_device_init_meta_blit2d_state(device
);
316 if (result
!= VK_SUCCESS
)
319 result
= radv_device_init_meta_bufimage_state(device
);
320 if (result
!= VK_SUCCESS
)
323 result
= radv_device_init_meta_depth_decomp_state(device
);
324 if (result
!= VK_SUCCESS
)
325 goto fail_depth_decomp
;
327 result
= radv_device_init_meta_buffer_state(device
);
328 if (result
!= VK_SUCCESS
)
331 result
= radv_device_init_meta_query_state(device
);
332 if (result
!= VK_SUCCESS
)
335 result
= radv_device_init_meta_fast_clear_flush_state(device
);
336 if (result
!= VK_SUCCESS
)
337 goto fail_fast_clear
;
339 result
= radv_device_init_meta_resolve_compute_state(device
);
340 if (result
!= VK_SUCCESS
)
341 goto fail_resolve_compute
;
343 result
= radv_device_init_meta_resolve_fragment_state(device
);
344 if (result
!= VK_SUCCESS
)
345 goto fail_resolve_fragment
;
348 fail_resolve_fragment
:
349 radv_device_finish_meta_resolve_compute_state(device
);
350 fail_resolve_compute
:
351 radv_device_finish_meta_fast_clear_flush_state(device
);
353 radv_device_finish_meta_buffer_state(device
);
355 radv_device_finish_meta_query_state(device
);
357 radv_device_finish_meta_depth_decomp_state(device
);
359 radv_device_finish_meta_bufimage_state(device
);
361 radv_device_finish_meta_blit2d_state(device
);
363 radv_device_finish_meta_blit_state(device
);
365 radv_device_finish_meta_resolve_state(device
);
367 radv_device_finish_meta_clear_state(device
);
369 radv_pipeline_cache_finish(&device
->meta_state
.cache
);
374 radv_device_finish_meta(struct radv_device
*device
)
376 radv_device_finish_meta_clear_state(device
);
377 radv_device_finish_meta_resolve_state(device
);
378 radv_device_finish_meta_blit_state(device
);
379 radv_device_finish_meta_blit2d_state(device
);
380 radv_device_finish_meta_bufimage_state(device
);
381 radv_device_finish_meta_depth_decomp_state(device
);
382 radv_device_finish_meta_query_state(device
);
383 radv_device_finish_meta_buffer_state(device
);
384 radv_device_finish_meta_fast_clear_flush_state(device
);
385 radv_device_finish_meta_resolve_compute_state(device
);
386 radv_device_finish_meta_resolve_fragment_state(device
);
388 radv_store_meta_pipeline(device
);
389 radv_pipeline_cache_finish(&device
->meta_state
.cache
);
393 * The most common meta operations all want to have the viewport
394 * reset and any scissors disabled. The rest of the dynamic state
395 * should have no effect.
398 radv_meta_save_graphics_reset_vport_scissor_novertex(struct radv_meta_saved_state
*saved_state
,
399 struct radv_cmd_buffer
*cmd_buffer
)
401 uint32_t dirty_state
= (1 << VK_DYNAMIC_STATE_VIEWPORT
) | (1 << VK_DYNAMIC_STATE_SCISSOR
);
402 radv_meta_save_novertex(saved_state
, cmd_buffer
, dirty_state
);
403 cmd_buffer
->state
.dynamic
.viewport
.count
= 0;
404 cmd_buffer
->state
.dynamic
.scissor
.count
= 0;
405 cmd_buffer
->state
.dirty
|= dirty_state
;
408 nir_ssa_def
*radv_meta_gen_rect_vertices_comp2(nir_builder
*vs_b
, nir_ssa_def
*comp2
)
411 nir_intrinsic_instr
*vertex_id
= nir_intrinsic_instr_create(vs_b
->shader
, nir_intrinsic_load_vertex_id_zero_base
);
412 nir_ssa_dest_init(&vertex_id
->instr
, &vertex_id
->dest
, 1, 32, "vertexid");
413 nir_builder_instr_insert(vs_b
, &vertex_id
->instr
);
415 /* vertex 0 - -1.0, -1.0 */
416 /* vertex 1 - -1.0, 1.0 */
417 /* vertex 2 - 1.0, -1.0 */
418 /* so channel 0 is vertex_id != 2 ? -1.0 : 1.0
419 channel 1 is vertex id != 1 ? -1.0 : 1.0 */
421 nir_ssa_def
*c0cmp
= nir_ine(vs_b
, &vertex_id
->dest
.ssa
,
422 nir_imm_int(vs_b
, 2));
423 nir_ssa_def
*c1cmp
= nir_ine(vs_b
, &vertex_id
->dest
.ssa
,
424 nir_imm_int(vs_b
, 1));
426 nir_ssa_def
*comp
[4];
427 comp
[0] = nir_bcsel(vs_b
, c0cmp
,
428 nir_imm_float(vs_b
, -1.0),
429 nir_imm_float(vs_b
, 1.0));
431 comp
[1] = nir_bcsel(vs_b
, c1cmp
,
432 nir_imm_float(vs_b
, -1.0),
433 nir_imm_float(vs_b
, 1.0));
435 comp
[3] = nir_imm_float(vs_b
, 1.0);
436 nir_ssa_def
*outvec
= nir_vec(vs_b
, comp
, 4);
441 nir_ssa_def
*radv_meta_gen_rect_vertices(nir_builder
*vs_b
)
443 return radv_meta_gen_rect_vertices_comp2(vs_b
, nir_imm_float(vs_b
, 0.0));
446 /* vertex shader that generates vertices */
448 radv_meta_build_nir_vs_generate_vertices(void)
450 const struct glsl_type
*vec4
= glsl_vec4_type();
453 nir_variable
*v_position
;
455 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_VERTEX
, NULL
);
456 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, "meta_vs_gen_verts");
458 nir_ssa_def
*outvec
= radv_meta_gen_rect_vertices(&b
);
460 v_position
= nir_variable_create(b
.shader
, nir_var_shader_out
, vec4
,
462 v_position
->data
.location
= VARYING_SLOT_POS
;
464 nir_store_var(&b
, v_position
, outvec
, 0xf);
470 radv_meta_build_nir_fs_noop(void)
474 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
475 b
.shader
->info
.name
= ralloc_asprintf(b
.shader
,
481 static nir_ssa_def
*radv_meta_build_resolve_srgb_conversion(nir_builder
*b
,
486 v
.u32
[0] = 0x3b4d2e1c; // 0.00313080009
489 for (i
= 0; i
< 3; i
++)
490 cmp
[i
] = nir_flt(b
, nir_channel(b
, input
, i
),
491 nir_build_imm(b
, 1, 32, v
));
493 nir_ssa_def
*ltvals
[3];
495 for (i
= 0; i
< 3; i
++)
496 ltvals
[i
] = nir_fmul(b
, nir_channel(b
, input
, i
),
497 nir_build_imm(b
, 1, 32, v
));
499 nir_ssa_def
*gtvals
[3];
501 for (i
= 0; i
< 3; i
++) {
503 gtvals
[i
] = nir_fpow(b
, nir_channel(b
, input
, i
),
504 nir_build_imm(b
, 1, 32, v
));
506 gtvals
[i
] = nir_fmul(b
, gtvals
[i
],
507 nir_build_imm(b
, 1, 32, v
));
509 gtvals
[i
] = nir_fsub(b
, gtvals
[i
],
510 nir_build_imm(b
, 1, 32, v
));
513 nir_ssa_def
*comp
[4];
514 for (i
= 0; i
< 3; i
++)
515 comp
[i
] = nir_bcsel(b
, cmp
[i
], ltvals
[i
], gtvals
[i
]);
516 comp
[3] = nir_channels(b
, input
, 3);
517 return nir_vec(b
, comp
, 4);
520 void radv_meta_build_resolve_shader_core(nir_builder
*b
,
524 nir_variable
*input_img
,
526 nir_ssa_def
*img_coord
)
528 /* do a txf_ms on each sample */
530 nir_if
*outer_if
= NULL
;
532 nir_tex_instr
*tex
= nir_tex_instr_create(b
->shader
, 2);
533 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
534 tex
->op
= nir_texop_txf_ms
;
535 tex
->src
[0].src_type
= nir_tex_src_coord
;
536 tex
->src
[0].src
= nir_src_for_ssa(img_coord
);
537 tex
->src
[1].src_type
= nir_tex_src_ms_index
;
538 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
539 tex
->dest_type
= nir_type_float
;
540 tex
->is_array
= false;
541 tex
->coord_components
= 2;
542 tex
->texture
= nir_deref_var_create(tex
, input_img
);
545 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, "tex");
546 nir_builder_instr_insert(b
, &tex
->instr
);
548 tmp
= &tex
->dest
.ssa
;
550 if (!is_integer
&& samples
> 1) {
551 nir_tex_instr
*tex_all_same
= nir_tex_instr_create(b
->shader
, 1);
552 tex_all_same
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
553 tex_all_same
->op
= nir_texop_samples_identical
;
554 tex_all_same
->src
[0].src_type
= nir_tex_src_coord
;
555 tex_all_same
->src
[0].src
= nir_src_for_ssa(img_coord
);
556 tex_all_same
->dest_type
= nir_type_float
;
557 tex_all_same
->is_array
= false;
558 tex_all_same
->coord_components
= 2;
559 tex_all_same
->texture
= nir_deref_var_create(tex_all_same
, input_img
);
560 tex_all_same
->sampler
= NULL
;
562 nir_ssa_dest_init(&tex_all_same
->instr
, &tex_all_same
->dest
, 1, 32, "tex");
563 nir_builder_instr_insert(b
, &tex_all_same
->instr
);
565 nir_ssa_def
*all_same
= nir_ine(b
, &tex_all_same
->dest
.ssa
, nir_imm_int(b
, 0));
566 nir_if
*if_stmt
= nir_if_create(b
->shader
);
567 if_stmt
->condition
= nir_src_for_ssa(all_same
);
568 nir_cf_node_insert(b
->cursor
, &if_stmt
->cf_node
);
570 b
->cursor
= nir_after_cf_list(&if_stmt
->then_list
);
571 for (int i
= 1; i
< samples
; i
++) {
572 nir_tex_instr
*tex_add
= nir_tex_instr_create(b
->shader
, 2);
573 tex_add
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
574 tex_add
->op
= nir_texop_txf_ms
;
575 tex_add
->src
[0].src_type
= nir_tex_src_coord
;
576 tex_add
->src
[0].src
= nir_src_for_ssa(img_coord
);
577 tex_add
->src
[1].src_type
= nir_tex_src_ms_index
;
578 tex_add
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, i
));
579 tex_add
->dest_type
= nir_type_float
;
580 tex_add
->is_array
= false;
581 tex_add
->coord_components
= 2;
582 tex_add
->texture
= nir_deref_var_create(tex_add
, input_img
);
583 tex_add
->sampler
= NULL
;
585 nir_ssa_dest_init(&tex_add
->instr
, &tex_add
->dest
, 4, 32, "tex");
586 nir_builder_instr_insert(b
, &tex_add
->instr
);
588 tmp
= nir_fadd(b
, tmp
, &tex_add
->dest
.ssa
);
591 tmp
= nir_fdiv(b
, tmp
, nir_imm_float(b
, samples
));
592 nir_store_var(b
, color
, tmp
, 0xf);
593 b
->cursor
= nir_after_cf_list(&if_stmt
->else_list
);
596 nir_store_var(b
, color
, &tex
->dest
.ssa
, 0xf);
599 b
->cursor
= nir_after_cf_node(&outer_if
->cf_node
);
602 nir_ssa_def
*newv
= nir_load_var(b
, color
);
603 newv
= radv_meta_build_resolve_srgb_conversion(b
, newv
);
604 nir_store_var(b
, color
, newv
, 0xf);