2 * Copyright © 2016 Red Hat
3 * based on intel anv code:
4 * Copyright © 2015 Intel Corporation
6 * Permission is hereby granted, free of charge, to any person obtaining a
7 * copy of this software and associated documentation files (the "Software"),
8 * to deal in the Software without restriction, including without limitation
9 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
10 * and/or sell copies of the Software, and to permit persons to whom the
11 * Software is furnished to do so, subject to the following conditions:
13 * The above copyright notice and this permission notice (including the next
14 * paragraph) shall be included in all copies or substantial portions of the
17 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
18 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
19 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
20 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
21 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
22 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
26 #include "radv_meta.h"
34 radv_meta_save_novertex(struct radv_meta_saved_state
*state
,
35 const struct radv_cmd_buffer
*cmd_buffer
,
36 uint32_t dynamic_mask
)
38 state
->old_pipeline
= cmd_buffer
->state
.pipeline
;
40 state
->dynamic_mask
= dynamic_mask
;
41 radv_dynamic_state_copy(&state
->dynamic
, &cmd_buffer
->state
.dynamic
,
44 memcpy(state
->push_constants
, cmd_buffer
->push_constants
, MAX_PUSH_CONSTANTS_SIZE
);
45 state
->vertex_saved
= false;
49 radv_meta_save(struct radv_meta_saved_state
*state
,
50 const struct radv_cmd_buffer
*cmd_buffer
,
51 uint32_t dynamic_mask
)
53 radv_meta_save_novertex(state
, cmd_buffer
, dynamic_mask
);
54 state
->old_descriptor_set0
= cmd_buffer
->state
.descriptors
[0];
55 memcpy(state
->old_vertex_bindings
, cmd_buffer
->state
.vertex_bindings
,
56 sizeof(state
->old_vertex_bindings
));
57 state
->vertex_saved
= true;
61 radv_meta_restore(const struct radv_meta_saved_state
*state
,
62 struct radv_cmd_buffer
*cmd_buffer
)
64 cmd_buffer
->state
.pipeline
= state
->old_pipeline
;
65 if (state
->vertex_saved
) {
66 cmd_buffer
->state
.descriptors
[0] = state
->old_descriptor_set0
;
67 cmd_buffer
->state
.descriptors_dirty
|= (1u << 0);
68 memcpy(cmd_buffer
->state
.vertex_bindings
, state
->old_vertex_bindings
,
69 sizeof(state
->old_vertex_bindings
));
70 cmd_buffer
->state
.vb_dirty
|= (1 << RADV_META_VERTEX_BINDING_COUNT
) - 1;
73 cmd_buffer
->state
.dirty
|= RADV_CMD_DIRTY_PIPELINE
;
75 radv_dynamic_state_copy(&cmd_buffer
->state
.dynamic
, &state
->dynamic
,
77 cmd_buffer
->state
.dirty
|= state
->dynamic_mask
;
79 memcpy(cmd_buffer
->push_constants
, state
->push_constants
, MAX_PUSH_CONSTANTS_SIZE
);
80 cmd_buffer
->push_constant_stages
|= VK_SHADER_STAGE_ALL_GRAPHICS
| VK_SHADER_STAGE_COMPUTE_BIT
;
84 radv_meta_save_pass(struct radv_meta_saved_pass_state
*state
,
85 const struct radv_cmd_buffer
*cmd_buffer
)
87 state
->pass
= cmd_buffer
->state
.pass
;
88 state
->subpass
= cmd_buffer
->state
.subpass
;
89 state
->framebuffer
= cmd_buffer
->state
.framebuffer
;
90 state
->attachments
= cmd_buffer
->state
.attachments
;
91 state
->render_area
= cmd_buffer
->state
.render_area
;
95 radv_meta_restore_pass(const struct radv_meta_saved_pass_state
*state
,
96 struct radv_cmd_buffer
*cmd_buffer
)
98 cmd_buffer
->state
.pass
= state
->pass
;
99 cmd_buffer
->state
.subpass
= state
->subpass
;
100 cmd_buffer
->state
.framebuffer
= state
->framebuffer
;
101 cmd_buffer
->state
.attachments
= state
->attachments
;
102 cmd_buffer
->state
.render_area
= state
->render_area
;
104 radv_emit_framebuffer_state(cmd_buffer
);
108 radv_meta_save_compute(struct radv_meta_saved_compute_state
*state
,
109 const struct radv_cmd_buffer
*cmd_buffer
,
110 unsigned push_constant_size
)
112 state
->old_pipeline
= cmd_buffer
->state
.compute_pipeline
;
113 state
->old_descriptor_set0
= cmd_buffer
->state
.descriptors
[0];
115 if (push_constant_size
)
116 memcpy(state
->push_constants
, cmd_buffer
->push_constants
, push_constant_size
);
120 radv_meta_restore_compute(const struct radv_meta_saved_compute_state
*state
,
121 struct radv_cmd_buffer
*cmd_buffer
,
122 unsigned push_constant_size
)
124 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
), VK_PIPELINE_BIND_POINT_COMPUTE
,
125 radv_pipeline_to_handle(state
->old_pipeline
));
127 cmd_buffer
->state
.descriptors
[0] = state
->old_descriptor_set0
;
128 cmd_buffer
->state
.descriptors_dirty
|= (1u << 0);
130 if (push_constant_size
) {
131 memcpy(cmd_buffer
->push_constants
, state
->push_constants
, push_constant_size
);
132 cmd_buffer
->push_constant_stages
|= VK_SHADER_STAGE_COMPUTE_BIT
;
137 radv_meta_get_view_type(const struct radv_image
*image
)
139 switch (image
->type
) {
140 case VK_IMAGE_TYPE_1D
: return VK_IMAGE_VIEW_TYPE_1D
;
141 case VK_IMAGE_TYPE_2D
: return VK_IMAGE_VIEW_TYPE_2D
;
142 case VK_IMAGE_TYPE_3D
: return VK_IMAGE_VIEW_TYPE_3D
;
144 unreachable("bad VkImageViewType");
149 * When creating a destination VkImageView, this function provides the needed
150 * VkImageViewCreateInfo::subresourceRange::baseArrayLayer.
153 radv_meta_get_iview_layer(const struct radv_image
*dest_image
,
154 const VkImageSubresourceLayers
*dest_subresource
,
155 const VkOffset3D
*dest_offset
)
157 switch (dest_image
->type
) {
158 case VK_IMAGE_TYPE_1D
:
159 case VK_IMAGE_TYPE_2D
:
160 return dest_subresource
->baseArrayLayer
;
161 case VK_IMAGE_TYPE_3D
:
162 /* HACK: Vulkan does not allow attaching a 3D image to a framebuffer,
163 * but meta does it anyway. When doing so, we translate the
164 * destination's z offset into an array offset.
166 return dest_offset
->z
;
168 assert(!"bad VkImageType");
174 meta_alloc(void* _device
, size_t size
, size_t alignment
,
175 VkSystemAllocationScope allocationScope
)
177 struct radv_device
*device
= _device
;
178 return device
->alloc
.pfnAllocation(device
->alloc
.pUserData
, size
, alignment
,
179 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
183 meta_realloc(void* _device
, void *original
, size_t size
, size_t alignment
,
184 VkSystemAllocationScope allocationScope
)
186 struct radv_device
*device
= _device
;
187 return device
->alloc
.pfnReallocation(device
->alloc
.pUserData
, original
,
189 VK_SYSTEM_ALLOCATION_SCOPE_DEVICE
);
193 meta_free(void* _device
, void *data
)
195 struct radv_device
*device
= _device
;
196 return device
->alloc
.pfnFree(device
->alloc
.pUserData
, data
);
200 radv_builtin_cache_path(char *path
)
202 char *xdg_cache_home
= getenv("XDG_CACHE_HOME");
203 const char *suffix
= "/radv_builtin_shaders";
204 const char *suffix2
= "/.cache/radv_builtin_shaders";
205 struct passwd pwd
, *result
;
206 char path2
[PATH_MAX
+ 1]; /* PATH_MAX is not a real max,but suffices here. */
208 if (xdg_cache_home
) {
210 if (strlen(xdg_cache_home
) + strlen(suffix
) > PATH_MAX
)
213 strcpy(path
, xdg_cache_home
);
214 strcat(path
, suffix
);
218 getpwuid_r(getuid(), &pwd
, path2
, PATH_MAX
- strlen(suffix2
), &result
);
222 strcpy(path
, pwd
.pw_dir
);
223 strcat(path
, "/.cache");
226 strcat(path
, suffix
);
231 radv_load_meta_pipeline(struct radv_device
*device
)
233 char path
[PATH_MAX
+ 1];
237 if (!radv_builtin_cache_path(path
))
240 int fd
= open(path
, O_RDONLY
);
245 data
= malloc(st
.st_size
);
248 if(read(fd
, data
, st
.st_size
) == -1)
251 radv_pipeline_cache_load(&device
->meta_state
.cache
, data
, st
.st_size
);
258 radv_store_meta_pipeline(struct radv_device
*device
)
260 char path
[PATH_MAX
+ 1], path2
[PATH_MAX
+ 7];
264 if (!device
->meta_state
.cache
.modified
)
267 if (radv_GetPipelineCacheData(radv_device_to_handle(device
),
268 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
272 if (!radv_builtin_cache_path(path
))
276 strcat(path2
, "XXXXXX");
277 int fd
= mkstemp(path2
);//open(path, O_WRONLY | O_CREAT, 0600);
284 if (radv_GetPipelineCacheData(radv_device_to_handle(device
),
285 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
288 if(write(fd
, data
, size
) == -1)
299 radv_device_init_meta(struct radv_device
*device
)
303 device
->meta_state
.alloc
= (VkAllocationCallbacks
) {
305 .pfnAllocation
= meta_alloc
,
306 .pfnReallocation
= meta_realloc
,
307 .pfnFree
= meta_free
,
310 device
->meta_state
.cache
.alloc
= device
->meta_state
.alloc
;
311 radv_pipeline_cache_init(&device
->meta_state
.cache
, device
);
312 radv_load_meta_pipeline(device
);
314 result
= radv_device_init_meta_clear_state(device
);
315 if (result
!= VK_SUCCESS
)
318 result
= radv_device_init_meta_resolve_state(device
);
319 if (result
!= VK_SUCCESS
)
322 result
= radv_device_init_meta_blit_state(device
);
323 if (result
!= VK_SUCCESS
)
326 result
= radv_device_init_meta_blit2d_state(device
);
327 if (result
!= VK_SUCCESS
)
330 result
= radv_device_init_meta_bufimage_state(device
);
331 if (result
!= VK_SUCCESS
)
334 result
= radv_device_init_meta_depth_decomp_state(device
);
335 if (result
!= VK_SUCCESS
)
336 goto fail_depth_decomp
;
338 result
= radv_device_init_meta_buffer_state(device
);
339 if (result
!= VK_SUCCESS
)
342 result
= radv_device_init_meta_query_state(device
);
343 if (result
!= VK_SUCCESS
)
346 result
= radv_device_init_meta_fast_clear_flush_state(device
);
347 if (result
!= VK_SUCCESS
)
348 goto fail_fast_clear
;
350 result
= radv_device_init_meta_resolve_compute_state(device
);
351 if (result
!= VK_SUCCESS
)
352 goto fail_resolve_compute
;
355 fail_resolve_compute
:
356 radv_device_finish_meta_fast_clear_flush_state(device
);
358 radv_device_finish_meta_buffer_state(device
);
360 radv_device_finish_meta_query_state(device
);
362 radv_device_finish_meta_depth_decomp_state(device
);
364 radv_device_finish_meta_bufimage_state(device
);
366 radv_device_finish_meta_blit2d_state(device
);
368 radv_device_finish_meta_blit_state(device
);
370 radv_device_finish_meta_resolve_state(device
);
372 radv_device_finish_meta_clear_state(device
);
374 radv_pipeline_cache_finish(&device
->meta_state
.cache
);
379 radv_device_finish_meta(struct radv_device
*device
)
381 radv_device_finish_meta_clear_state(device
);
382 radv_device_finish_meta_resolve_state(device
);
383 radv_device_finish_meta_blit_state(device
);
384 radv_device_finish_meta_blit2d_state(device
);
385 radv_device_finish_meta_bufimage_state(device
);
386 radv_device_finish_meta_depth_decomp_state(device
);
387 radv_device_finish_meta_query_state(device
);
388 radv_device_finish_meta_buffer_state(device
);
389 radv_device_finish_meta_fast_clear_flush_state(device
);
390 radv_device_finish_meta_resolve_compute_state(device
);
392 radv_store_meta_pipeline(device
);
393 radv_pipeline_cache_finish(&device
->meta_state
.cache
);
397 * The most common meta operations all want to have the viewport
398 * reset and any scissors disabled. The rest of the dynamic state
399 * should have no effect.
402 radv_meta_save_graphics_reset_vport_scissor(struct radv_meta_saved_state
*saved_state
,
403 struct radv_cmd_buffer
*cmd_buffer
)
405 uint32_t dirty_state
= (1 << VK_DYNAMIC_STATE_VIEWPORT
) | (1 << VK_DYNAMIC_STATE_SCISSOR
);
406 radv_meta_save(saved_state
, cmd_buffer
, dirty_state
);
407 cmd_buffer
->state
.dynamic
.viewport
.count
= 0;
408 cmd_buffer
->state
.dynamic
.scissor
.count
= 0;
409 cmd_buffer
->state
.dirty
|= dirty_state
;
413 radv_meta_save_graphics_reset_vport_scissor_novertex(struct radv_meta_saved_state
*saved_state
,
414 struct radv_cmd_buffer
*cmd_buffer
)
416 uint32_t dirty_state
= (1 << VK_DYNAMIC_STATE_VIEWPORT
) | (1 << VK_DYNAMIC_STATE_SCISSOR
);
417 radv_meta_save_novertex(saved_state
, cmd_buffer
, dirty_state
);
418 cmd_buffer
->state
.dynamic
.viewport
.count
= 0;
419 cmd_buffer
->state
.dynamic
.scissor
.count
= 0;
420 cmd_buffer
->state
.dirty
|= dirty_state
;
423 nir_ssa_def
*radv_meta_gen_rect_vertices_comp2(nir_builder
*vs_b
, nir_ssa_def
*comp2
)
426 nir_intrinsic_instr
*vertex_id
= nir_intrinsic_instr_create(vs_b
->shader
, nir_intrinsic_load_vertex_id_zero_base
);
427 nir_ssa_dest_init(&vertex_id
->instr
, &vertex_id
->dest
, 1, 32, "vertexid");
428 nir_builder_instr_insert(vs_b
, &vertex_id
->instr
);
430 /* vertex 0 - -1.0, -1.0 */
431 /* vertex 1 - -1.0, 1.0 */
432 /* vertex 2 - 1.0, -1.0 */
433 /* so channel 0 is vertex_id != 2 ? -1.0 : 1.0
434 channel 1 is vertex id != 1 ? -1.0 : 1.0 */
436 nir_ssa_def
*c0cmp
= nir_ine(vs_b
, &vertex_id
->dest
.ssa
,
437 nir_imm_int(vs_b
, 2));
438 nir_ssa_def
*c1cmp
= nir_ine(vs_b
, &vertex_id
->dest
.ssa
,
439 nir_imm_int(vs_b
, 1));
441 nir_ssa_def
*comp
[4];
442 comp
[0] = nir_bcsel(vs_b
, c0cmp
,
443 nir_imm_float(vs_b
, -1.0),
444 nir_imm_float(vs_b
, 1.0));
446 comp
[1] = nir_bcsel(vs_b
, c1cmp
,
447 nir_imm_float(vs_b
, -1.0),
448 nir_imm_float(vs_b
, 1.0));
450 comp
[3] = nir_imm_float(vs_b
, 1.0);
451 nir_ssa_def
*outvec
= nir_vec(vs_b
, comp
, 4);
456 nir_ssa_def
*radv_meta_gen_rect_vertices(nir_builder
*vs_b
)
458 return radv_meta_gen_rect_vertices_comp2(vs_b
, nir_imm_float(vs_b
, 0.0));
461 /* vertex shader that generates vertices */
463 radv_meta_build_nir_vs_generate_vertices(void)
465 const struct glsl_type
*vec4
= glsl_vec4_type();
468 nir_variable
*v_position
;
470 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_VERTEX
, NULL
);
471 b
.shader
->info
->name
= ralloc_strdup(b
.shader
, "meta_vs_gen_verts");
473 nir_ssa_def
*outvec
= radv_meta_gen_rect_vertices(&b
);
475 v_position
= nir_variable_create(b
.shader
, nir_var_shader_out
, vec4
,
477 v_position
->data
.location
= VARYING_SLOT_POS
;
479 nir_store_var(&b
, v_position
, outvec
, 0xf);
485 radv_meta_build_nir_fs_noop(void)
489 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
490 b
.shader
->info
->name
= ralloc_asprintf(b
.shader
,
496 static nir_ssa_def
*radv_meta_build_resolve_srgb_conversion(nir_builder
*b
,
501 v
.u32
[0] = 0x3b4d2e1c; // 0.00313080009
504 for (i
= 0; i
< 3; i
++)
505 cmp
[i
] = nir_flt(b
, nir_channel(b
, input
, i
),
506 nir_build_imm(b
, 1, 32, v
));
508 nir_ssa_def
*ltvals
[3];
510 for (i
= 0; i
< 3; i
++)
511 ltvals
[i
] = nir_fmul(b
, nir_channel(b
, input
, i
),
512 nir_build_imm(b
, 1, 32, v
));
514 nir_ssa_def
*gtvals
[3];
516 for (i
= 0; i
< 3; i
++) {
518 gtvals
[i
] = nir_fpow(b
, nir_channel(b
, input
, i
),
519 nir_build_imm(b
, 1, 32, v
));
521 gtvals
[i
] = nir_fmul(b
, gtvals
[i
],
522 nir_build_imm(b
, 1, 32, v
));
524 gtvals
[i
] = nir_fsub(b
, gtvals
[i
],
525 nir_build_imm(b
, 1, 32, v
));
528 nir_ssa_def
*comp
[4];
529 for (i
= 0; i
< 3; i
++)
530 comp
[i
] = nir_bcsel(b
, cmp
[i
], ltvals
[i
], gtvals
[i
]);
531 comp
[3] = nir_channels(b
, input
, 3);
532 return nir_vec(b
, comp
, 4);
535 void radv_meta_build_resolve_shader_core(nir_builder
*b
,
539 nir_variable
*input_img
,
541 nir_ssa_def
*img_coord
)
543 /* do a txf_ms on each sample */
545 nir_if
*outer_if
= NULL
;
547 nir_tex_instr
*tex
= nir_tex_instr_create(b
->shader
, 2);
548 tex
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
549 tex
->op
= nir_texop_txf_ms
;
550 tex
->src
[0].src_type
= nir_tex_src_coord
;
551 tex
->src
[0].src
= nir_src_for_ssa(img_coord
);
552 tex
->src
[1].src_type
= nir_tex_src_ms_index
;
553 tex
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, 0));
554 tex
->dest_type
= nir_type_float
;
555 tex
->is_array
= false;
556 tex
->coord_components
= 2;
557 tex
->texture
= nir_deref_var_create(tex
, input_img
);
560 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, "tex");
561 nir_builder_instr_insert(b
, &tex
->instr
);
563 tmp
= &tex
->dest
.ssa
;
565 if (!is_integer
&& samples
> 1) {
566 nir_tex_instr
*tex_all_same
= nir_tex_instr_create(b
->shader
, 1);
567 tex_all_same
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
568 tex_all_same
->op
= nir_texop_samples_identical
;
569 tex_all_same
->src
[0].src_type
= nir_tex_src_coord
;
570 tex_all_same
->src
[0].src
= nir_src_for_ssa(img_coord
);
571 tex_all_same
->dest_type
= nir_type_float
;
572 tex_all_same
->is_array
= false;
573 tex_all_same
->coord_components
= 2;
574 tex_all_same
->texture
= nir_deref_var_create(tex_all_same
, input_img
);
575 tex_all_same
->sampler
= NULL
;
577 nir_ssa_dest_init(&tex_all_same
->instr
, &tex_all_same
->dest
, 1, 32, "tex");
578 nir_builder_instr_insert(b
, &tex_all_same
->instr
);
580 nir_ssa_def
*all_same
= nir_ine(b
, &tex_all_same
->dest
.ssa
, nir_imm_int(b
, 0));
581 nir_if
*if_stmt
= nir_if_create(b
->shader
);
582 if_stmt
->condition
= nir_src_for_ssa(all_same
);
583 nir_cf_node_insert(b
->cursor
, &if_stmt
->cf_node
);
585 b
->cursor
= nir_after_cf_list(&if_stmt
->then_list
);
586 for (int i
= 1; i
< samples
; i
++) {
587 nir_tex_instr
*tex_add
= nir_tex_instr_create(b
->shader
, 2);
588 tex_add
->sampler_dim
= GLSL_SAMPLER_DIM_MS
;
589 tex_add
->op
= nir_texop_txf_ms
;
590 tex_add
->src
[0].src_type
= nir_tex_src_coord
;
591 tex_add
->src
[0].src
= nir_src_for_ssa(img_coord
);
592 tex_add
->src
[1].src_type
= nir_tex_src_ms_index
;
593 tex_add
->src
[1].src
= nir_src_for_ssa(nir_imm_int(b
, i
));
594 tex_add
->dest_type
= nir_type_float
;
595 tex_add
->is_array
= false;
596 tex_add
->coord_components
= 2;
597 tex_add
->texture
= nir_deref_var_create(tex_add
, input_img
);
598 tex_add
->sampler
= NULL
;
600 nir_ssa_dest_init(&tex_add
->instr
, &tex_add
->dest
, 4, 32, "tex");
601 nir_builder_instr_insert(b
, &tex_add
->instr
);
603 tmp
= nir_fadd(b
, tmp
, &tex_add
->dest
.ssa
);
606 tmp
= nir_fdiv(b
, tmp
, nir_imm_float(b
, samples
));
607 nir_store_var(b
, color
, tmp
, 0xf);
608 b
->cursor
= nir_after_cf_list(&if_stmt
->else_list
);
611 nir_store_var(b
, color
, &tex
->dest
.ssa
, 0xf);
614 b
->cursor
= nir_after_cf_node(&outer_if
->cf_node
);
617 nir_ssa_def
*newv
= nir_load_var(b
, color
);
618 newv
= radv_meta_build_resolve_srgb_conversion(b
, newv
);
619 nir_store_var(b
, color
, newv
, 0xf);