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radv: Refactor blit pipeline creation.
[mesa.git] / src / amd / vulkan / radv_meta_blit.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "radv_meta.h"
25 #include "nir/nir_builder.h"
26
27 struct blit_region {
28 VkOffset3D src_offset;
29 VkExtent3D src_extent;
30 VkOffset3D dest_offset;
31 VkExtent3D dest_extent;
32 };
33
34 static nir_shader *
35 build_nir_vertex_shader(void)
36 {
37 const struct glsl_type *vec4 = glsl_vec4_type();
38 nir_builder b;
39
40 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_VERTEX, NULL);
41 b.shader->info.name = ralloc_strdup(b.shader, "meta_blit_vs");
42
43 nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out,
44 vec4, "gl_Position");
45 pos_out->data.location = VARYING_SLOT_POS;
46
47 nir_variable *tex_pos_out = nir_variable_create(b.shader, nir_var_shader_out,
48 vec4, "v_tex_pos");
49 tex_pos_out->data.location = VARYING_SLOT_VAR0;
50 tex_pos_out->data.interpolation = INTERP_MODE_SMOOTH;
51
52 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&b);
53
54 nir_store_var(&b, pos_out, outvec, 0xf);
55
56 nir_intrinsic_instr *src_box = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
57 src_box->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
58 nir_intrinsic_set_base(src_box, 0);
59 nir_intrinsic_set_range(src_box, 16);
60 src_box->num_components = 4;
61 nir_ssa_dest_init(&src_box->instr, &src_box->dest, 4, 32, "src_box");
62 nir_builder_instr_insert(&b, &src_box->instr);
63
64 nir_intrinsic_instr *src0_z = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
65 src0_z->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
66 nir_intrinsic_set_base(src0_z, 16);
67 nir_intrinsic_set_range(src0_z, 4);
68 src0_z->num_components = 1;
69 nir_ssa_dest_init(&src0_z->instr, &src0_z->dest, 1, 32, "src0_z");
70 nir_builder_instr_insert(&b, &src0_z->instr);
71
72 nir_intrinsic_instr *vertex_id = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_vertex_id_zero_base);
73 nir_ssa_dest_init(&vertex_id->instr, &vertex_id->dest, 1, 32, "vertexid");
74 nir_builder_instr_insert(&b, &vertex_id->instr);
75
76 /* vertex 0 - src0_x, src0_y, src0_z */
77 /* vertex 1 - src0_x, src1_y, src0_z*/
78 /* vertex 2 - src1_x, src0_y, src0_z */
79 /* so channel 0 is vertex_id != 2 ? src_x : src_x + w
80 channel 1 is vertex id != 1 ? src_y : src_y + w */
81
82 nir_ssa_def *c0cmp = nir_ine(&b, &vertex_id->dest.ssa,
83 nir_imm_int(&b, 2));
84 nir_ssa_def *c1cmp = nir_ine(&b, &vertex_id->dest.ssa,
85 nir_imm_int(&b, 1));
86
87 nir_ssa_def *comp[4];
88 comp[0] = nir_bcsel(&b, c0cmp,
89 nir_channel(&b, &src_box->dest.ssa, 0),
90 nir_channel(&b, &src_box->dest.ssa, 2));
91
92 comp[1] = nir_bcsel(&b, c1cmp,
93 nir_channel(&b, &src_box->dest.ssa, 1),
94 nir_channel(&b, &src_box->dest.ssa, 3));
95 comp[2] = &src0_z->dest.ssa;
96 comp[3] = nir_imm_float(&b, 1.0);
97 nir_ssa_def *out_tex_vec = nir_vec(&b, comp, 4);
98 nir_store_var(&b, tex_pos_out, out_tex_vec, 0xf);
99 return b.shader;
100 }
101
102 static nir_shader *
103 build_nir_copy_fragment_shader(enum glsl_sampler_dim tex_dim)
104 {
105 char shader_name[64];
106 const struct glsl_type *vec4 = glsl_vec4_type();
107 nir_builder b;
108
109 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
110
111 sprintf(shader_name, "meta_blit_fs.%d", tex_dim);
112 b.shader->info.name = ralloc_strdup(b.shader, shader_name);
113
114 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
115 vec4, "v_tex_pos");
116 tex_pos_in->data.location = VARYING_SLOT_VAR0;
117
118 /* Swizzle the array index which comes in as Z coordinate into the right
119 * position.
120 */
121 unsigned swz[] = { 0, (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 1), 2 };
122 nir_ssa_def *const tex_pos =
123 nir_swizzle(&b, nir_load_var(&b, tex_pos_in), swz,
124 (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 3), false);
125
126 const struct glsl_type *sampler_type =
127 glsl_sampler_type(tex_dim, false, tex_dim != GLSL_SAMPLER_DIM_3D,
128 glsl_get_base_type(vec4));
129 nir_variable *sampler = nir_variable_create(b.shader, nir_var_uniform,
130 sampler_type, "s_tex");
131 sampler->data.descriptor_set = 0;
132 sampler->data.binding = 0;
133
134 nir_ssa_def *tex_deref = &nir_build_deref_var(&b, sampler)->dest.ssa;
135
136 nir_tex_instr *tex = nir_tex_instr_create(b.shader, 3);
137 tex->sampler_dim = tex_dim;
138 tex->op = nir_texop_tex;
139 tex->src[0].src_type = nir_tex_src_coord;
140 tex->src[0].src = nir_src_for_ssa(tex_pos);
141 tex->src[1].src_type = nir_tex_src_texture_deref;
142 tex->src[1].src = nir_src_for_ssa(tex_deref);
143 tex->src[2].src_type = nir_tex_src_sampler_deref;
144 tex->src[2].src = nir_src_for_ssa(tex_deref);
145 tex->dest_type = nir_type_float; /* TODO */
146 tex->is_array = glsl_sampler_type_is_array(sampler_type);
147 tex->coord_components = tex_pos->num_components;
148
149 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
150 nir_builder_instr_insert(&b, &tex->instr);
151
152 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
153 vec4, "f_color");
154 color_out->data.location = FRAG_RESULT_DATA0;
155 nir_store_var(&b, color_out, &tex->dest.ssa, 0xf);
156
157 return b.shader;
158 }
159
160 static nir_shader *
161 build_nir_copy_fragment_shader_depth(enum glsl_sampler_dim tex_dim)
162 {
163 char shader_name[64];
164 const struct glsl_type *vec4 = glsl_vec4_type();
165 nir_builder b;
166
167 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
168
169 sprintf(shader_name, "meta_blit_depth_fs.%d", tex_dim);
170 b.shader->info.name = ralloc_strdup(b.shader, shader_name);
171
172 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
173 vec4, "v_tex_pos");
174 tex_pos_in->data.location = VARYING_SLOT_VAR0;
175
176 /* Swizzle the array index which comes in as Z coordinate into the right
177 * position.
178 */
179 unsigned swz[] = { 0, (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 1), 2 };
180 nir_ssa_def *const tex_pos =
181 nir_swizzle(&b, nir_load_var(&b, tex_pos_in), swz,
182 (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 3), false);
183
184 const struct glsl_type *sampler_type =
185 glsl_sampler_type(tex_dim, false, tex_dim != GLSL_SAMPLER_DIM_3D,
186 glsl_get_base_type(vec4));
187 nir_variable *sampler = nir_variable_create(b.shader, nir_var_uniform,
188 sampler_type, "s_tex");
189 sampler->data.descriptor_set = 0;
190 sampler->data.binding = 0;
191
192 nir_ssa_def *tex_deref = &nir_build_deref_var(&b, sampler)->dest.ssa;
193
194 nir_tex_instr *tex = nir_tex_instr_create(b.shader, 3);
195 tex->sampler_dim = tex_dim;
196 tex->op = nir_texop_tex;
197 tex->src[0].src_type = nir_tex_src_coord;
198 tex->src[0].src = nir_src_for_ssa(tex_pos);
199 tex->src[1].src_type = nir_tex_src_texture_deref;
200 tex->src[1].src = nir_src_for_ssa(tex_deref);
201 tex->src[2].src_type = nir_tex_src_sampler_deref;
202 tex->src[2].src = nir_src_for_ssa(tex_deref);
203 tex->dest_type = nir_type_float; /* TODO */
204 tex->is_array = glsl_sampler_type_is_array(sampler_type);
205 tex->coord_components = tex_pos->num_components;
206
207 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
208 nir_builder_instr_insert(&b, &tex->instr);
209
210 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
211 vec4, "f_color");
212 color_out->data.location = FRAG_RESULT_DEPTH;
213 nir_store_var(&b, color_out, &tex->dest.ssa, 0x1);
214
215 return b.shader;
216 }
217
218 static nir_shader *
219 build_nir_copy_fragment_shader_stencil(enum glsl_sampler_dim tex_dim)
220 {
221 char shader_name[64];
222 const struct glsl_type *vec4 = glsl_vec4_type();
223 nir_builder b;
224
225 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
226
227 sprintf(shader_name, "meta_blit_stencil_fs.%d", tex_dim);
228 b.shader->info.name = ralloc_strdup(b.shader, shader_name);
229
230 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
231 vec4, "v_tex_pos");
232 tex_pos_in->data.location = VARYING_SLOT_VAR0;
233
234 /* Swizzle the array index which comes in as Z coordinate into the right
235 * position.
236 */
237 unsigned swz[] = { 0, (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 1), 2 };
238 nir_ssa_def *const tex_pos =
239 nir_swizzle(&b, nir_load_var(&b, tex_pos_in), swz,
240 (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 3), false);
241
242 const struct glsl_type *sampler_type =
243 glsl_sampler_type(tex_dim, false, tex_dim != GLSL_SAMPLER_DIM_3D,
244 glsl_get_base_type(vec4));
245 nir_variable *sampler = nir_variable_create(b.shader, nir_var_uniform,
246 sampler_type, "s_tex");
247 sampler->data.descriptor_set = 0;
248 sampler->data.binding = 0;
249
250 nir_ssa_def *tex_deref = &nir_build_deref_var(&b, sampler)->dest.ssa;
251
252 nir_tex_instr *tex = nir_tex_instr_create(b.shader, 3);
253 tex->sampler_dim = tex_dim;
254 tex->op = nir_texop_tex;
255 tex->src[0].src_type = nir_tex_src_coord;
256 tex->src[0].src = nir_src_for_ssa(tex_pos);
257 tex->src[1].src_type = nir_tex_src_texture_deref;
258 tex->src[1].src = nir_src_for_ssa(tex_deref);
259 tex->src[2].src_type = nir_tex_src_sampler_deref;
260 tex->src[2].src = nir_src_for_ssa(tex_deref);
261 tex->dest_type = nir_type_float; /* TODO */
262 tex->is_array = glsl_sampler_type_is_array(sampler_type);
263 tex->coord_components = tex_pos->num_components;
264
265 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
266 nir_builder_instr_insert(&b, &tex->instr);
267
268 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
269 vec4, "f_color");
270 color_out->data.location = FRAG_RESULT_STENCIL;
271 nir_store_var(&b, color_out, &tex->dest.ssa, 0x1);
272
273 return b.shader;
274 }
275
276 static void
277 meta_emit_blit(struct radv_cmd_buffer *cmd_buffer,
278 struct radv_image *src_image,
279 struct radv_image_view *src_iview,
280 VkImageLayout src_image_layout,
281 VkOffset3D src_offset_0,
282 VkOffset3D src_offset_1,
283 struct radv_image *dest_image,
284 struct radv_image_view *dest_iview,
285 VkImageLayout dest_image_layout,
286 VkOffset2D dest_offset_0,
287 VkOffset2D dest_offset_1,
288 VkRect2D dest_box,
289 VkFilter blit_filter)
290 {
291 struct radv_device *device = cmd_buffer->device;
292 uint32_t src_width = radv_minify(src_iview->image->info.width, src_iview->base_mip);
293 uint32_t src_height = radv_minify(src_iview->image->info.height, src_iview->base_mip);
294 uint32_t src_depth = radv_minify(src_iview->image->info.depth, src_iview->base_mip);
295 uint32_t dst_width = radv_minify(dest_iview->image->info.width, dest_iview->base_mip);
296 uint32_t dst_height = radv_minify(dest_iview->image->info.height, dest_iview->base_mip);
297
298 assert(src_image->info.samples == dest_image->info.samples);
299
300 float vertex_push_constants[5] = {
301 (float)src_offset_0.x / (float)src_width,
302 (float)src_offset_0.y / (float)src_height,
303 (float)src_offset_1.x / (float)src_width,
304 (float)src_offset_1.y / (float)src_height,
305 (float)src_offset_0.z / (float)src_depth,
306 };
307
308 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
309 device->meta_state.blit.pipeline_layout,
310 VK_SHADER_STAGE_VERTEX_BIT, 0, 20,
311 vertex_push_constants);
312
313 VkSampler sampler;
314 radv_CreateSampler(radv_device_to_handle(device),
315 &(VkSamplerCreateInfo) {
316 .sType = VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO,
317 .magFilter = blit_filter,
318 .minFilter = blit_filter,
319 .addressModeU = VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE,
320 .addressModeV = VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE,
321 .addressModeW = VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE,
322 }, &cmd_buffer->pool->alloc, &sampler);
323
324 VkFramebuffer fb;
325 radv_CreateFramebuffer(radv_device_to_handle(device),
326 &(VkFramebufferCreateInfo) {
327 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
328 .attachmentCount = 1,
329 .pAttachments = (VkImageView[]) {
330 radv_image_view_to_handle(dest_iview),
331 },
332 .width = dst_width,
333 .height = dst_height,
334 .layers = 1,
335 }, &cmd_buffer->pool->alloc, &fb);
336 VkPipeline pipeline;
337 switch (src_iview->aspect_mask) {
338 case VK_IMAGE_ASPECT_COLOR_BIT: {
339 unsigned fs_key = radv_format_meta_fs_key(dest_image->vk_format);
340 unsigned dst_layout = radv_meta_dst_layout_from_layout(dest_image_layout);
341
342 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
343 &(VkRenderPassBeginInfo) {
344 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
345 .renderPass = device->meta_state.blit.render_pass[fs_key][dst_layout],
346 .framebuffer = fb,
347 .renderArea = {
348 .offset = { dest_box.offset.x, dest_box.offset.y },
349 .extent = { dest_box.extent.width, dest_box.extent.height },
350 },
351 .clearValueCount = 0,
352 .pClearValues = NULL,
353 }, VK_SUBPASS_CONTENTS_INLINE);
354 switch (src_image->type) {
355 case VK_IMAGE_TYPE_1D:
356 pipeline = device->meta_state.blit.pipeline_1d_src[fs_key];
357 break;
358 case VK_IMAGE_TYPE_2D:
359 pipeline = device->meta_state.blit.pipeline_2d_src[fs_key];
360 break;
361 case VK_IMAGE_TYPE_3D:
362 pipeline = device->meta_state.blit.pipeline_3d_src[fs_key];
363 break;
364 default:
365 unreachable(!"bad VkImageType");
366 }
367 break;
368 }
369 case VK_IMAGE_ASPECT_DEPTH_BIT: {
370 enum radv_blit_ds_layout ds_layout = radv_meta_blit_ds_to_type(dest_image_layout);
371 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
372 &(VkRenderPassBeginInfo) {
373 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
374 .renderPass = device->meta_state.blit.depth_only_rp[ds_layout],
375 .framebuffer = fb,
376 .renderArea = {
377 .offset = { dest_box.offset.x, dest_box.offset.y },
378 .extent = { dest_box.extent.width, dest_box.extent.height },
379 },
380 .clearValueCount = 0,
381 .pClearValues = NULL,
382 }, VK_SUBPASS_CONTENTS_INLINE);
383 switch (src_image->type) {
384 case VK_IMAGE_TYPE_1D:
385 pipeline = device->meta_state.blit.depth_only_1d_pipeline;
386 break;
387 case VK_IMAGE_TYPE_2D:
388 pipeline = device->meta_state.blit.depth_only_2d_pipeline;
389 break;
390 case VK_IMAGE_TYPE_3D:
391 pipeline = device->meta_state.blit.depth_only_3d_pipeline;
392 break;
393 default:
394 unreachable(!"bad VkImageType");
395 }
396 break;
397 }
398 case VK_IMAGE_ASPECT_STENCIL_BIT: {
399 enum radv_blit_ds_layout ds_layout = radv_meta_blit_ds_to_type(dest_image_layout);
400 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
401 &(VkRenderPassBeginInfo) {
402 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
403 .renderPass = device->meta_state.blit.stencil_only_rp[ds_layout],
404 .framebuffer = fb,
405 .renderArea = {
406 .offset = { dest_box.offset.x, dest_box.offset.y },
407 .extent = { dest_box.extent.width, dest_box.extent.height },
408 },
409 .clearValueCount = 0,
410 .pClearValues = NULL,
411 }, VK_SUBPASS_CONTENTS_INLINE);
412 switch (src_image->type) {
413 case VK_IMAGE_TYPE_1D:
414 pipeline = device->meta_state.blit.stencil_only_1d_pipeline;
415 break;
416 case VK_IMAGE_TYPE_2D:
417 pipeline = device->meta_state.blit.stencil_only_2d_pipeline;
418 break;
419 case VK_IMAGE_TYPE_3D:
420 pipeline = device->meta_state.blit.stencil_only_3d_pipeline;
421 break;
422 default:
423 unreachable(!"bad VkImageType");
424 }
425 break;
426 }
427 default:
428 unreachable(!"bad VkImageType");
429 }
430
431 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
432 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
433
434 radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_GRAPHICS,
435 device->meta_state.blit.pipeline_layout,
436 0, /* set */
437 1, /* descriptorWriteCount */
438 (VkWriteDescriptorSet[]) {
439 {
440 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
441 .dstBinding = 0,
442 .dstArrayElement = 0,
443 .descriptorCount = 1,
444 .descriptorType = VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER,
445 .pImageInfo = (VkDescriptorImageInfo[]) {
446 {
447 .sampler = sampler,
448 .imageView = radv_image_view_to_handle(src_iview),
449 .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
450 },
451 }
452 }
453 });
454
455 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
456 .x = dest_offset_0.x,
457 .y = dest_offset_0.y,
458 .width = dest_offset_1.x - dest_offset_0.x,
459 .height = dest_offset_1.y - dest_offset_0.y,
460 .minDepth = 0.0f,
461 .maxDepth = 1.0f
462 });
463
464 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkRect2D) {
465 .offset = (VkOffset2D) { MIN2(dest_offset_0.x, dest_offset_1.x), MIN2(dest_offset_0.y, dest_offset_1.y) },
466 .extent = (VkExtent2D) {
467 abs(dest_offset_1.x - dest_offset_0.x),
468 abs(dest_offset_1.y - dest_offset_0.y)
469 },
470 });
471
472 radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
473
474 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
475
476 /* At the point where we emit the draw call, all data from the
477 * descriptor sets, etc. has been used. We are free to delete it.
478 */
479 /* TODO: above comment is not valid for at least descriptor sets/pools,
480 * as we may not free them till after execution finishes. Check others. */
481
482 radv_DestroySampler(radv_device_to_handle(device), sampler,
483 &cmd_buffer->pool->alloc);
484 radv_DestroyFramebuffer(radv_device_to_handle(device), fb,
485 &cmd_buffer->pool->alloc);
486 }
487
488 static bool
489 flip_coords(unsigned *src0, unsigned *src1, unsigned *dst0, unsigned *dst1)
490 {
491 bool flip = false;
492 if (*src0 > *src1) {
493 unsigned tmp = *src0;
494 *src0 = *src1;
495 *src1 = tmp;
496 flip = !flip;
497 }
498
499 if (*dst0 > *dst1) {
500 unsigned tmp = *dst0;
501 *dst0 = *dst1;
502 *dst1 = tmp;
503 flip = !flip;
504 }
505 return flip;
506 }
507
508 void radv_CmdBlitImage(
509 VkCommandBuffer commandBuffer,
510 VkImage srcImage,
511 VkImageLayout srcImageLayout,
512 VkImage destImage,
513 VkImageLayout destImageLayout,
514 uint32_t regionCount,
515 const VkImageBlit* pRegions,
516 VkFilter filter)
517
518 {
519 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
520 RADV_FROM_HANDLE(radv_image, src_image, srcImage);
521 RADV_FROM_HANDLE(radv_image, dest_image, destImage);
522 struct radv_meta_saved_state saved_state;
523 bool old_predicating;
524
525 /* From the Vulkan 1.0 spec:
526 *
527 * vkCmdBlitImage must not be used for multisampled source or
528 * destination images. Use vkCmdResolveImage for this purpose.
529 */
530 assert(src_image->info.samples == 1);
531 assert(dest_image->info.samples == 1);
532
533 radv_meta_save(&saved_state, cmd_buffer,
534 RADV_META_SAVE_GRAPHICS_PIPELINE |
535 RADV_META_SAVE_CONSTANTS |
536 RADV_META_SAVE_DESCRIPTORS);
537
538 /* VK_EXT_conditional_rendering says that blit commands should not be
539 * affected by conditional rendering.
540 */
541 old_predicating = cmd_buffer->state.predicating;
542 cmd_buffer->state.predicating = false;
543
544 for (unsigned r = 0; r < regionCount; r++) {
545 const VkImageSubresourceLayers *src_res = &pRegions[r].srcSubresource;
546 const VkImageSubresourceLayers *dst_res = &pRegions[r].dstSubresource;
547
548 unsigned dst_start, dst_end;
549 if (dest_image->type == VK_IMAGE_TYPE_3D) {
550 assert(dst_res->baseArrayLayer == 0);
551 dst_start = pRegions[r].dstOffsets[0].z;
552 dst_end = pRegions[r].dstOffsets[1].z;
553 } else {
554 dst_start = dst_res->baseArrayLayer;
555 dst_end = dst_start + dst_res->layerCount;
556 }
557
558 unsigned src_start, src_end;
559 if (src_image->type == VK_IMAGE_TYPE_3D) {
560 assert(src_res->baseArrayLayer == 0);
561 src_start = pRegions[r].srcOffsets[0].z;
562 src_end = pRegions[r].srcOffsets[1].z;
563 } else {
564 src_start = src_res->baseArrayLayer;
565 src_end = src_start + src_res->layerCount;
566 }
567
568 bool flip_z = flip_coords(&src_start, &src_end, &dst_start, &dst_end);
569 float src_z_step = (float)(src_end + 1 - src_start) /
570 (float)(dst_end + 1 - dst_start);
571
572 if (flip_z) {
573 src_start = src_end;
574 src_z_step *= -1;
575 }
576
577 unsigned src_x0 = pRegions[r].srcOffsets[0].x;
578 unsigned src_x1 = pRegions[r].srcOffsets[1].x;
579 unsigned dst_x0 = pRegions[r].dstOffsets[0].x;
580 unsigned dst_x1 = pRegions[r].dstOffsets[1].x;
581
582 unsigned src_y0 = pRegions[r].srcOffsets[0].y;
583 unsigned src_y1 = pRegions[r].srcOffsets[1].y;
584 unsigned dst_y0 = pRegions[r].dstOffsets[0].y;
585 unsigned dst_y1 = pRegions[r].dstOffsets[1].y;
586
587 VkRect2D dest_box;
588 dest_box.offset.x = MIN2(dst_x0, dst_x1);
589 dest_box.offset.y = MIN2(dst_y0, dst_y1);
590 dest_box.extent.width = abs(dst_x1 - dst_x0);
591 dest_box.extent.height = abs(dst_y1 - dst_y0);
592
593 const unsigned num_layers = dst_end - dst_start;
594 for (unsigned i = 0; i < num_layers; i++) {
595 struct radv_image_view dest_iview, src_iview;
596
597 const VkOffset2D dest_offset_0 = {
598 .x = dst_x0,
599 .y = dst_y0,
600 };
601 const VkOffset2D dest_offset_1 = {
602 .x = dst_x1,
603 .y = dst_y1,
604 };
605 VkOffset3D src_offset_0 = {
606 .x = src_x0,
607 .y = src_y0,
608 .z = src_start + i * src_z_step,
609 };
610 VkOffset3D src_offset_1 = {
611 .x = src_x1,
612 .y = src_y1,
613 .z = src_start + i * src_z_step,
614 };
615 const uint32_t dest_array_slice = dst_start + i;
616
617 /* 3D images have just 1 layer */
618 const uint32_t src_array_slice = src_image->type == VK_IMAGE_TYPE_3D ? 0 : src_start + i;
619
620 radv_image_view_init(&dest_iview, cmd_buffer->device,
621 &(VkImageViewCreateInfo) {
622 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
623 .image = destImage,
624 .viewType = radv_meta_get_view_type(dest_image),
625 .format = dest_image->vk_format,
626 .subresourceRange = {
627 .aspectMask = dst_res->aspectMask,
628 .baseMipLevel = dst_res->mipLevel,
629 .levelCount = 1,
630 .baseArrayLayer = dest_array_slice,
631 .layerCount = 1
632 },
633 });
634 radv_image_view_init(&src_iview, cmd_buffer->device,
635 &(VkImageViewCreateInfo) {
636 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
637 .image = srcImage,
638 .viewType = radv_meta_get_view_type(src_image),
639 .format = src_image->vk_format,
640 .subresourceRange = {
641 .aspectMask = src_res->aspectMask,
642 .baseMipLevel = src_res->mipLevel,
643 .levelCount = 1,
644 .baseArrayLayer = src_array_slice,
645 .layerCount = 1
646 },
647 });
648 meta_emit_blit(cmd_buffer,
649 src_image, &src_iview, srcImageLayout,
650 src_offset_0, src_offset_1,
651 dest_image, &dest_iview, destImageLayout,
652 dest_offset_0, dest_offset_1,
653 dest_box,
654 filter);
655 }
656 }
657
658 /* Restore conditional rendering. */
659 cmd_buffer->state.predicating = old_predicating;
660
661 radv_meta_restore(&saved_state, cmd_buffer);
662 }
663
664 void
665 radv_device_finish_meta_blit_state(struct radv_device *device)
666 {
667 struct radv_meta_state *state = &device->meta_state;
668
669 for (unsigned i = 0; i < NUM_META_FS_KEYS; ++i) {
670 for (unsigned j = 0; j < RADV_META_DST_LAYOUT_COUNT; ++j) {
671 radv_DestroyRenderPass(radv_device_to_handle(device),
672 state->blit.render_pass[i][j],
673 &state->alloc);
674 }
675 radv_DestroyPipeline(radv_device_to_handle(device),
676 state->blit.pipeline_1d_src[i],
677 &state->alloc);
678 radv_DestroyPipeline(radv_device_to_handle(device),
679 state->blit.pipeline_2d_src[i],
680 &state->alloc);
681 radv_DestroyPipeline(radv_device_to_handle(device),
682 state->blit.pipeline_3d_src[i],
683 &state->alloc);
684 }
685
686 for (enum radv_blit_ds_layout i = RADV_BLIT_DS_LAYOUT_TILE_ENABLE; i < RADV_BLIT_DS_LAYOUT_COUNT; i++) {
687 radv_DestroyRenderPass(radv_device_to_handle(device),
688 state->blit.depth_only_rp[i], &state->alloc);
689 radv_DestroyRenderPass(radv_device_to_handle(device),
690 state->blit.stencil_only_rp[i], &state->alloc);
691 }
692
693 radv_DestroyPipeline(radv_device_to_handle(device),
694 state->blit.depth_only_1d_pipeline, &state->alloc);
695 radv_DestroyPipeline(radv_device_to_handle(device),
696 state->blit.depth_only_2d_pipeline, &state->alloc);
697 radv_DestroyPipeline(radv_device_to_handle(device),
698 state->blit.depth_only_3d_pipeline, &state->alloc);
699
700 radv_DestroyPipeline(radv_device_to_handle(device),
701 state->blit.stencil_only_1d_pipeline,
702 &state->alloc);
703 radv_DestroyPipeline(radv_device_to_handle(device),
704 state->blit.stencil_only_2d_pipeline,
705 &state->alloc);
706 radv_DestroyPipeline(radv_device_to_handle(device),
707 state->blit.stencil_only_3d_pipeline,
708 &state->alloc);
709
710
711 radv_DestroyPipelineLayout(radv_device_to_handle(device),
712 state->blit.pipeline_layout, &state->alloc);
713 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
714 state->blit.ds_layout, &state->alloc);
715 }
716
717 static VkResult
718 build_pipeline(struct radv_device *device,
719 VkImageAspectFlagBits aspect,
720 enum glsl_sampler_dim tex_dim,
721 unsigned fs_key,
722 VkPipeline *pipeline)
723 {
724 VkResult result = VK_SUCCESS;
725 struct radv_shader_module fs = {0};
726 struct radv_shader_module vs = {.nir = build_nir_vertex_shader()};
727 VkRenderPass rp;
728
729 switch(aspect) {
730 case VK_IMAGE_ASPECT_COLOR_BIT:
731 fs.nir = build_nir_copy_fragment_shader(tex_dim);
732 rp = device->meta_state.blit.render_pass[fs_key][0];
733 break;
734 case VK_IMAGE_ASPECT_DEPTH_BIT:
735 fs.nir = build_nir_copy_fragment_shader_depth(tex_dim);
736 rp = device->meta_state.blit.depth_only_rp[0];
737 break;
738 case VK_IMAGE_ASPECT_STENCIL_BIT:
739 fs.nir = build_nir_copy_fragment_shader_stencil(tex_dim);
740 rp = device->meta_state.blit.stencil_only_rp[0];
741 break;
742 default:
743 unreachable("Unhandled aspect");
744 }
745 VkPipelineVertexInputStateCreateInfo vi_create_info = {
746 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
747 .vertexBindingDescriptionCount = 0,
748 .vertexAttributeDescriptionCount = 0,
749 };
750
751 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
752 {
753 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
754 .stage = VK_SHADER_STAGE_VERTEX_BIT,
755 .module = radv_shader_module_to_handle(&vs),
756 .pName = "main",
757 .pSpecializationInfo = NULL
758 }, {
759 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
760 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
761 .module = radv_shader_module_to_handle(&fs),
762 .pName = "main",
763 .pSpecializationInfo = NULL
764 },
765 };
766
767 VkGraphicsPipelineCreateInfo vk_pipeline_info = {
768 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
769 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
770 .pStages = pipeline_shader_stages,
771 .pVertexInputState = &vi_create_info,
772 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
773 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
774 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
775 .primitiveRestartEnable = false,
776 },
777 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
778 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
779 .viewportCount = 1,
780 .scissorCount = 1,
781 },
782 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
783 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
784 .rasterizerDiscardEnable = false,
785 .polygonMode = VK_POLYGON_MODE_FILL,
786 .cullMode = VK_CULL_MODE_NONE,
787 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
788 },
789 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
790 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
791 .rasterizationSamples = 1,
792 .sampleShadingEnable = false,
793 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
794 },
795 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
796 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
797 .dynamicStateCount = 4,
798 .pDynamicStates = (VkDynamicState[]) {
799 VK_DYNAMIC_STATE_VIEWPORT,
800 VK_DYNAMIC_STATE_SCISSOR,
801 VK_DYNAMIC_STATE_LINE_WIDTH,
802 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
803 },
804 },
805 .flags = 0,
806 .layout = device->meta_state.blit.pipeline_layout,
807 .renderPass = rp,
808 .subpass = 0,
809 };
810
811 switch(aspect) {
812 case VK_IMAGE_ASPECT_COLOR_BIT:
813 vk_pipeline_info.pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
814 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
815 .attachmentCount = 1,
816 .pAttachments = (VkPipelineColorBlendAttachmentState []) {
817 { .colorWriteMask =
818 VK_COLOR_COMPONENT_A_BIT |
819 VK_COLOR_COMPONENT_R_BIT |
820 VK_COLOR_COMPONENT_G_BIT |
821 VK_COLOR_COMPONENT_B_BIT },
822 }
823 };
824 break;
825 case VK_IMAGE_ASPECT_DEPTH_BIT:
826 vk_pipeline_info.pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
827 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
828 .depthTestEnable = true,
829 .depthWriteEnable = true,
830 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
831 };
832 break;
833 case VK_IMAGE_ASPECT_STENCIL_BIT:
834 vk_pipeline_info.pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
835 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
836 .depthTestEnable = false,
837 .depthWriteEnable = false,
838 .stencilTestEnable = true,
839 .front = {
840 .failOp = VK_STENCIL_OP_REPLACE,
841 .passOp = VK_STENCIL_OP_REPLACE,
842 .depthFailOp = VK_STENCIL_OP_REPLACE,
843 .compareOp = VK_COMPARE_OP_ALWAYS,
844 .compareMask = 0xff,
845 .writeMask = 0xff,
846 .reference = 0
847 },
848 .back = {
849 .failOp = VK_STENCIL_OP_REPLACE,
850 .passOp = VK_STENCIL_OP_REPLACE,
851 .depthFailOp = VK_STENCIL_OP_REPLACE,
852 .compareOp = VK_COMPARE_OP_ALWAYS,
853 .compareMask = 0xff,
854 .writeMask = 0xff,
855 .reference = 0
856 },
857 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
858 };
859 break;
860 default:
861 unreachable("Unhandled aspect");
862 }
863
864 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
865 .use_rectlist = true
866 };
867
868 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
869 radv_pipeline_cache_to_handle(&device->meta_state.cache),
870 &vk_pipeline_info, &radv_pipeline_info,
871 &device->meta_state.alloc, pipeline);
872 ralloc_free(vs.nir);
873 ralloc_free(fs.nir);
874 return result;
875 }
876
877 static VkResult
878 radv_device_init_meta_blit_color(struct radv_device *device)
879 {
880 VkResult result;
881
882 for (unsigned i = 0; i < NUM_META_FS_KEYS; ++i) {
883 unsigned key = radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]);
884 for(unsigned j = 0; j < RADV_META_DST_LAYOUT_COUNT; ++j) {
885 VkImageLayout layout = radv_meta_dst_layout_to_layout(j);
886 result = radv_CreateRenderPass(radv_device_to_handle(device),
887 &(VkRenderPassCreateInfo) {
888 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
889 .attachmentCount = 1,
890 .pAttachments = &(VkAttachmentDescription) {
891 .format = radv_fs_key_format_exemplars[i],
892 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
893 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
894 .initialLayout = layout,
895 .finalLayout = layout,
896 },
897 .subpassCount = 1,
898 .pSubpasses = &(VkSubpassDescription) {
899 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
900 .inputAttachmentCount = 0,
901 .colorAttachmentCount = 1,
902 .pColorAttachments = &(VkAttachmentReference) {
903 .attachment = 0,
904 .layout = layout,
905 },
906 .pResolveAttachments = NULL,
907 .pDepthStencilAttachment = &(VkAttachmentReference) {
908 .attachment = VK_ATTACHMENT_UNUSED,
909 .layout = VK_IMAGE_LAYOUT_GENERAL,
910 },
911 .preserveAttachmentCount = 1,
912 .pPreserveAttachments = (uint32_t[]) { 0 },
913 },
914 .dependencyCount = 0,
915 }, &device->meta_state.alloc, &device->meta_state.blit.render_pass[key][j]);
916 if (result != VK_SUCCESS)
917 goto fail;
918 }
919
920 result = build_pipeline(device, VK_IMAGE_ASPECT_COLOR_BIT, GLSL_SAMPLER_DIM_1D, key, &device->meta_state.blit.pipeline_1d_src[key]);
921 if (result != VK_SUCCESS)
922 goto fail;
923
924 result = build_pipeline(device, VK_IMAGE_ASPECT_COLOR_BIT, GLSL_SAMPLER_DIM_2D, key, &device->meta_state.blit.pipeline_2d_src[key]);
925 if (result != VK_SUCCESS)
926 goto fail;
927
928 result = build_pipeline(device, VK_IMAGE_ASPECT_COLOR_BIT, GLSL_SAMPLER_DIM_3D, key, &device->meta_state.blit.pipeline_3d_src[key]);
929 if (result != VK_SUCCESS)
930 goto fail;
931
932 }
933
934 result = VK_SUCCESS;
935 fail:
936 return result;
937 }
938
939 static VkResult
940 radv_device_init_meta_blit_depth(struct radv_device *device)
941 {
942 VkResult result;
943
944 for (enum radv_blit_ds_layout ds_layout = RADV_BLIT_DS_LAYOUT_TILE_ENABLE; ds_layout < RADV_BLIT_DS_LAYOUT_COUNT; ds_layout++) {
945 VkImageLayout layout = radv_meta_blit_ds_to_layout(ds_layout);
946 result = radv_CreateRenderPass(radv_device_to_handle(device),
947 &(VkRenderPassCreateInfo) {
948 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
949 .attachmentCount = 1,
950 .pAttachments = &(VkAttachmentDescription) {
951 .format = VK_FORMAT_D32_SFLOAT,
952 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
953 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
954 .initialLayout = layout,
955 .finalLayout = layout,
956 },
957 .subpassCount = 1,
958 .pSubpasses = &(VkSubpassDescription) {
959 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
960 .inputAttachmentCount = 0,
961 .colorAttachmentCount = 0,
962 .pColorAttachments = NULL,
963 .pResolveAttachments = NULL,
964 .pDepthStencilAttachment = &(VkAttachmentReference) {
965 .attachment = 0,
966 .layout = layout,
967 },
968 .preserveAttachmentCount = 1,
969 .pPreserveAttachments = (uint32_t[]) { 0 },
970 },
971 .dependencyCount = 0,
972 }, &device->meta_state.alloc, &device->meta_state.blit.depth_only_rp[ds_layout]);
973 if (result != VK_SUCCESS)
974 goto fail;
975 }
976
977 result = build_pipeline(device, VK_IMAGE_ASPECT_DEPTH_BIT, GLSL_SAMPLER_DIM_1D, 0, &device->meta_state.blit.depth_only_1d_pipeline);
978 if (result != VK_SUCCESS)
979 goto fail;
980
981 result = build_pipeline(device, VK_IMAGE_ASPECT_DEPTH_BIT, GLSL_SAMPLER_DIM_2D, 0, &device->meta_state.blit.depth_only_2d_pipeline);
982 if (result != VK_SUCCESS)
983 goto fail;
984
985 result = build_pipeline(device, VK_IMAGE_ASPECT_DEPTH_BIT, GLSL_SAMPLER_DIM_3D, 0, &device->meta_state.blit.depth_only_3d_pipeline);
986 if (result != VK_SUCCESS)
987 goto fail;
988
989 fail:
990 return result;
991 }
992
993 static VkResult
994 radv_device_init_meta_blit_stencil(struct radv_device *device)
995 {
996 VkResult result;
997
998 for (enum radv_blit_ds_layout ds_layout = RADV_BLIT_DS_LAYOUT_TILE_ENABLE; ds_layout < RADV_BLIT_DS_LAYOUT_COUNT; ds_layout++) {
999 VkImageLayout layout = radv_meta_blit_ds_to_layout(ds_layout);
1000 result = radv_CreateRenderPass(radv_device_to_handle(device),
1001 &(VkRenderPassCreateInfo) {
1002 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1003 .attachmentCount = 1,
1004 .pAttachments = &(VkAttachmentDescription) {
1005 .format = VK_FORMAT_S8_UINT,
1006 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1007 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1008 .initialLayout = layout,
1009 .finalLayout = layout,
1010 },
1011 .subpassCount = 1,
1012 .pSubpasses = &(VkSubpassDescription) {
1013 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1014 .inputAttachmentCount = 0,
1015 .colorAttachmentCount = 0,
1016 .pColorAttachments = NULL,
1017 .pResolveAttachments = NULL,
1018 .pDepthStencilAttachment = &(VkAttachmentReference) {
1019 .attachment = 0,
1020 .layout = layout,
1021 },
1022 .preserveAttachmentCount = 1,
1023 .pPreserveAttachments = (uint32_t[]) { 0 },
1024 },
1025 .dependencyCount = 0,
1026 }, &device->meta_state.alloc, &device->meta_state.blit.stencil_only_rp[ds_layout]);
1027 }
1028 if (result != VK_SUCCESS)
1029 goto fail;
1030
1031
1032 result = build_pipeline(device, VK_IMAGE_ASPECT_STENCIL_BIT, GLSL_SAMPLER_DIM_1D, 0, &device->meta_state.blit.stencil_only_1d_pipeline);
1033 if (result != VK_SUCCESS)
1034 goto fail;
1035
1036 result = build_pipeline(device, VK_IMAGE_ASPECT_STENCIL_BIT, GLSL_SAMPLER_DIM_2D, 0, &device->meta_state.blit.stencil_only_2d_pipeline);
1037 if (result != VK_SUCCESS)
1038 goto fail;
1039
1040 result = build_pipeline(device, VK_IMAGE_ASPECT_STENCIL_BIT, GLSL_SAMPLER_DIM_3D, 0, &device->meta_state.blit.stencil_only_3d_pipeline);
1041 if (result != VK_SUCCESS)
1042 goto fail;
1043
1044
1045 fail:
1046 return result;
1047 }
1048
1049 VkResult
1050 radv_device_init_meta_blit_state(struct radv_device *device)
1051 {
1052 VkResult result;
1053
1054 VkDescriptorSetLayoutCreateInfo ds_layout_info = {
1055 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1056 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
1057 .bindingCount = 1,
1058 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1059 {
1060 .binding = 0,
1061 .descriptorType = VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER,
1062 .descriptorCount = 1,
1063 .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
1064 .pImmutableSamplers = NULL
1065 },
1066 }
1067 };
1068 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1069 &ds_layout_info,
1070 &device->meta_state.alloc,
1071 &device->meta_state.blit.ds_layout);
1072 if (result != VK_SUCCESS)
1073 goto fail;
1074
1075 const VkPushConstantRange push_constant_range = {VK_SHADER_STAGE_VERTEX_BIT, 0, 20};
1076
1077 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1078 &(VkPipelineLayoutCreateInfo) {
1079 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1080 .setLayoutCount = 1,
1081 .pSetLayouts = &device->meta_state.blit.ds_layout,
1082 .pushConstantRangeCount = 1,
1083 .pPushConstantRanges = &push_constant_range,
1084 },
1085 &device->meta_state.alloc, &device->meta_state.blit.pipeline_layout);
1086 if (result != VK_SUCCESS)
1087 goto fail;
1088
1089 result = radv_device_init_meta_blit_color(device);
1090 if (result != VK_SUCCESS)
1091 goto fail;
1092
1093 result = radv_device_init_meta_blit_depth(device);
1094 if (result != VK_SUCCESS)
1095 goto fail;
1096
1097 result = radv_device_init_meta_blit_stencil(device);
1098
1099 fail:
1100 if (result != VK_SUCCESS)
1101 radv_device_finish_meta_blit_state(device);
1102 return result;
1103 }