projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: don't use iview for meta image width/height.
[mesa.git] / src / amd / vulkan / radv_meta_blit.c
1 /*
2 * Copyright © 2015 Intel Corporation
3 *
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
10 *
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
13 * Software.
14 *
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
21 * IN THE SOFTWARE.
22 */
23
24 #include "radv_meta.h"
25 #include "nir/nir_builder.h"
26
27 struct blit_region {
28 VkOffset3D src_offset;
29 VkExtent3D src_extent;
30 VkOffset3D dest_offset;
31 VkExtent3D dest_extent;
32 };
33
34 static nir_shader *
35 build_nir_vertex_shader(void)
36 {
37 const struct glsl_type *vec4 = glsl_vec4_type();
38 nir_builder b;
39
40 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_VERTEX, NULL);
41 b.shader->info.name = ralloc_strdup(b.shader, "meta_blit_vs");
42
43 nir_variable *pos_out = nir_variable_create(b.shader, nir_var_shader_out,
44 vec4, "gl_Position");
45 pos_out->data.location = VARYING_SLOT_POS;
46
47 nir_variable *tex_pos_out = nir_variable_create(b.shader, nir_var_shader_out,
48 vec4, "v_tex_pos");
49 tex_pos_out->data.location = VARYING_SLOT_VAR0;
50 tex_pos_out->data.interpolation = INTERP_MODE_SMOOTH;
51
52 nir_ssa_def *outvec = radv_meta_gen_rect_vertices(&b);
53
54 nir_store_var(&b, pos_out, outvec, 0xf);
55
56 nir_intrinsic_instr *src_box = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
57 src_box->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
58 nir_intrinsic_set_base(src_box, 0);
59 nir_intrinsic_set_range(src_box, 16);
60 src_box->num_components = 4;
61 nir_ssa_dest_init(&src_box->instr, &src_box->dest, 4, 32, "src_box");
62 nir_builder_instr_insert(&b, &src_box->instr);
63
64 nir_intrinsic_instr *src0_z = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
65 src0_z->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
66 nir_intrinsic_set_base(src0_z, 16);
67 nir_intrinsic_set_range(src0_z, 4);
68 src0_z->num_components = 1;
69 nir_ssa_dest_init(&src0_z->instr, &src0_z->dest, 1, 32, "src0_z");
70 nir_builder_instr_insert(&b, &src0_z->instr);
71
72 nir_intrinsic_instr *vertex_id = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_vertex_id_zero_base);
73 nir_ssa_dest_init(&vertex_id->instr, &vertex_id->dest, 1, 32, "vertexid");
74 nir_builder_instr_insert(&b, &vertex_id->instr);
75
76 /* vertex 0 - src0_x, src0_y, src0_z */
77 /* vertex 1 - src0_x, src1_y, src0_z*/
78 /* vertex 2 - src1_x, src0_y, src0_z */
79 /* so channel 0 is vertex_id != 2 ? src_x : src_x + w
80 channel 1 is vertex id != 1 ? src_y : src_y + w */
81
82 nir_ssa_def *c0cmp = nir_ine(&b, &vertex_id->dest.ssa,
83 nir_imm_int(&b, 2));
84 nir_ssa_def *c1cmp = nir_ine(&b, &vertex_id->dest.ssa,
85 nir_imm_int(&b, 1));
86
87 nir_ssa_def *comp[4];
88 comp[0] = nir_bcsel(&b, c0cmp,
89 nir_channel(&b, &src_box->dest.ssa, 0),
90 nir_channel(&b, &src_box->dest.ssa, 2));
91
92 comp[1] = nir_bcsel(&b, c1cmp,
93 nir_channel(&b, &src_box->dest.ssa, 1),
94 nir_channel(&b, &src_box->dest.ssa, 3));
95 comp[2] = &src0_z->dest.ssa;
96 comp[3] = nir_imm_float(&b, 1.0);
97 nir_ssa_def *out_tex_vec = nir_vec(&b, comp, 4);
98 nir_store_var(&b, tex_pos_out, out_tex_vec, 0xf);
99 return b.shader;
100 }
101
102 static nir_shader *
103 build_nir_copy_fragment_shader(enum glsl_sampler_dim tex_dim)
104 {
105 char shader_name[64];
106 const struct glsl_type *vec4 = glsl_vec4_type();
107 nir_builder b;
108
109 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
110
111 sprintf(shader_name, "meta_blit_fs.%d", tex_dim);
112 b.shader->info.name = ralloc_strdup(b.shader, shader_name);
113
114 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
115 vec4, "v_tex_pos");
116 tex_pos_in->data.location = VARYING_SLOT_VAR0;
117
118 /* Swizzle the array index which comes in as Z coordinate into the right
119 * position.
120 */
121 unsigned swz[] = { 0, (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 1), 2 };
122 nir_ssa_def *const tex_pos =
123 nir_swizzle(&b, nir_load_var(&b, tex_pos_in), swz,
124 (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 3), false);
125
126 const struct glsl_type *sampler_type =
127 glsl_sampler_type(tex_dim, false, tex_dim != GLSL_SAMPLER_DIM_3D,
128 glsl_get_base_type(vec4));
129 nir_variable *sampler = nir_variable_create(b.shader, nir_var_uniform,
130 sampler_type, "s_tex");
131 sampler->data.descriptor_set = 0;
132 sampler->data.binding = 0;
133
134 nir_tex_instr *tex = nir_tex_instr_create(b.shader, 1);
135 tex->sampler_dim = tex_dim;
136 tex->op = nir_texop_tex;
137 tex->src[0].src_type = nir_tex_src_coord;
138 tex->src[0].src = nir_src_for_ssa(tex_pos);
139 tex->dest_type = nir_type_float; /* TODO */
140 tex->is_array = glsl_sampler_type_is_array(sampler_type);
141 tex->coord_components = tex_pos->num_components;
142 tex->texture = nir_deref_var_create(tex, sampler);
143 tex->sampler = nir_deref_var_create(tex, sampler);
144
145 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
146 nir_builder_instr_insert(&b, &tex->instr);
147
148 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
149 vec4, "f_color");
150 color_out->data.location = FRAG_RESULT_DATA0;
151 nir_store_var(&b, color_out, &tex->dest.ssa, 0xf);
152
153 return b.shader;
154 }
155
156 static nir_shader *
157 build_nir_copy_fragment_shader_depth(enum glsl_sampler_dim tex_dim)
158 {
159 char shader_name[64];
160 const struct glsl_type *vec4 = glsl_vec4_type();
161 nir_builder b;
162
163 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
164
165 sprintf(shader_name, "meta_blit_depth_fs.%d", tex_dim);
166 b.shader->info.name = ralloc_strdup(b.shader, shader_name);
167
168 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
169 vec4, "v_tex_pos");
170 tex_pos_in->data.location = VARYING_SLOT_VAR0;
171
172 /* Swizzle the array index which comes in as Z coordinate into the right
173 * position.
174 */
175 unsigned swz[] = { 0, (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 1), 2 };
176 nir_ssa_def *const tex_pos =
177 nir_swizzle(&b, nir_load_var(&b, tex_pos_in), swz,
178 (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 3), false);
179
180 const struct glsl_type *sampler_type =
181 glsl_sampler_type(tex_dim, false, tex_dim != GLSL_SAMPLER_DIM_3D,
182 glsl_get_base_type(vec4));
183 nir_variable *sampler = nir_variable_create(b.shader, nir_var_uniform,
184 sampler_type, "s_tex");
185 sampler->data.descriptor_set = 0;
186 sampler->data.binding = 0;
187
188 nir_tex_instr *tex = nir_tex_instr_create(b.shader, 1);
189 tex->sampler_dim = tex_dim;
190 tex->op = nir_texop_tex;
191 tex->src[0].src_type = nir_tex_src_coord;
192 tex->src[0].src = nir_src_for_ssa(tex_pos);
193 tex->dest_type = nir_type_float; /* TODO */
194 tex->is_array = glsl_sampler_type_is_array(sampler_type);
195 tex->coord_components = tex_pos->num_components;
196 tex->texture = nir_deref_var_create(tex, sampler);
197 tex->sampler = nir_deref_var_create(tex, sampler);
198
199 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
200 nir_builder_instr_insert(&b, &tex->instr);
201
202 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
203 vec4, "f_color");
204 color_out->data.location = FRAG_RESULT_DEPTH;
205 nir_store_var(&b, color_out, &tex->dest.ssa, 0x1);
206
207 return b.shader;
208 }
209
210 static nir_shader *
211 build_nir_copy_fragment_shader_stencil(enum glsl_sampler_dim tex_dim)
212 {
213 char shader_name[64];
214 const struct glsl_type *vec4 = glsl_vec4_type();
215 nir_builder b;
216
217 nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_FRAGMENT, NULL);
218
219 sprintf(shader_name, "meta_blit_stencil_fs.%d", tex_dim);
220 b.shader->info.name = ralloc_strdup(b.shader, shader_name);
221
222 nir_variable *tex_pos_in = nir_variable_create(b.shader, nir_var_shader_in,
223 vec4, "v_tex_pos");
224 tex_pos_in->data.location = VARYING_SLOT_VAR0;
225
226 /* Swizzle the array index which comes in as Z coordinate into the right
227 * position.
228 */
229 unsigned swz[] = { 0, (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 1), 2 };
230 nir_ssa_def *const tex_pos =
231 nir_swizzle(&b, nir_load_var(&b, tex_pos_in), swz,
232 (tex_dim == GLSL_SAMPLER_DIM_1D ? 2 : 3), false);
233
234 const struct glsl_type *sampler_type =
235 glsl_sampler_type(tex_dim, false, tex_dim != GLSL_SAMPLER_DIM_3D,
236 glsl_get_base_type(vec4));
237 nir_variable *sampler = nir_variable_create(b.shader, nir_var_uniform,
238 sampler_type, "s_tex");
239 sampler->data.descriptor_set = 0;
240 sampler->data.binding = 0;
241
242 nir_tex_instr *tex = nir_tex_instr_create(b.shader, 1);
243 tex->sampler_dim = tex_dim;
244 tex->op = nir_texop_tex;
245 tex->src[0].src_type = nir_tex_src_coord;
246 tex->src[0].src = nir_src_for_ssa(tex_pos);
247 tex->dest_type = nir_type_float; /* TODO */
248 tex->is_array = glsl_sampler_type_is_array(sampler_type);
249 tex->coord_components = tex_pos->num_components;
250 tex->texture = nir_deref_var_create(tex, sampler);
251 tex->sampler = nir_deref_var_create(tex, sampler);
252
253 nir_ssa_dest_init(&tex->instr, &tex->dest, 4, 32, "tex");
254 nir_builder_instr_insert(&b, &tex->instr);
255
256 nir_variable *color_out = nir_variable_create(b.shader, nir_var_shader_out,
257 vec4, "f_color");
258 color_out->data.location = FRAG_RESULT_STENCIL;
259 nir_store_var(&b, color_out, &tex->dest.ssa, 0x1);
260
261 return b.shader;
262 }
263
264 static void
265 meta_emit_blit(struct radv_cmd_buffer *cmd_buffer,
266 struct radv_image *src_image,
267 struct radv_image_view *src_iview,
268 VkOffset3D src_offset_0,
269 VkOffset3D src_offset_1,
270 struct radv_image *dest_image,
271 struct radv_image_view *dest_iview,
272 VkOffset3D dest_offset_0,
273 VkOffset3D dest_offset_1,
274 VkRect2D dest_box,
275 VkFilter blit_filter)
276 {
277 struct radv_device *device = cmd_buffer->device;
278 uint32_t src_width = radv_minify(src_iview->image->info.width, src_iview->base_mip);
279 uint32_t src_height = radv_minify(src_iview->image->info.height, src_iview->base_mip);
280 uint32_t src_depth = radv_minify(src_iview->image->info.depth, src_iview->base_mip);
281 uint32_t dst_width = radv_minify(dest_iview->image->info.width, dest_iview->base_mip);
282 uint32_t dst_height = radv_minify(dest_iview->image->info.height, dest_iview->base_mip);
283
284 assert(src_image->info.samples == dest_image->info.samples);
285
286 float vertex_push_constants[5] = {
287 (float)src_offset_0.x / (float)src_width,
288 (float)src_offset_0.y / (float)src_height,
289 (float)src_offset_1.x / (float)src_width,
290 (float)src_offset_1.y / (float)src_height,
291 (float)src_offset_0.z / (float)src_depth,
292 };
293
294 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
295 device->meta_state.blit.pipeline_layout,
296 VK_SHADER_STAGE_VERTEX_BIT, 0, 20,
297 vertex_push_constants);
298
299 VkSampler sampler;
300 radv_CreateSampler(radv_device_to_handle(device),
301 &(VkSamplerCreateInfo) {
302 .sType = VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO,
303 .magFilter = blit_filter,
304 .minFilter = blit_filter,
305 .addressModeU = VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE,
306 .addressModeV = VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE,
307 .addressModeW = VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE,
308 }, &cmd_buffer->pool->alloc, &sampler);
309
310 VkFramebuffer fb;
311 radv_CreateFramebuffer(radv_device_to_handle(device),
312 &(VkFramebufferCreateInfo) {
313 .sType = VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO,
314 .attachmentCount = 1,
315 .pAttachments = (VkImageView[]) {
316 radv_image_view_to_handle(dest_iview),
317 },
318 .width = dst_width,
319 .height = dst_height,
320 .layers = 1,
321 }, &cmd_buffer->pool->alloc, &fb);
322 VkPipeline pipeline;
323 switch (src_iview->aspect_mask) {
324 case VK_IMAGE_ASPECT_COLOR_BIT: {
325 unsigned fs_key = radv_format_meta_fs_key(dest_image->vk_format);
326
327 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
328 &(VkRenderPassBeginInfo) {
329 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
330 .renderPass = device->meta_state.blit.render_pass[fs_key],
331 .framebuffer = fb,
332 .renderArea = {
333 .offset = { dest_box.offset.x, dest_box.offset.y },
334 .extent = { dest_box.extent.width, dest_box.extent.height },
335 },
336 .clearValueCount = 0,
337 .pClearValues = NULL,
338 }, VK_SUBPASS_CONTENTS_INLINE);
339 switch (src_image->type) {
340 case VK_IMAGE_TYPE_1D:
341 pipeline = device->meta_state.blit.pipeline_1d_src[fs_key];
342 break;
343 case VK_IMAGE_TYPE_2D:
344 pipeline = device->meta_state.blit.pipeline_2d_src[fs_key];
345 break;
346 case VK_IMAGE_TYPE_3D:
347 pipeline = device->meta_state.blit.pipeline_3d_src[fs_key];
348 break;
349 default:
350 unreachable(!"bad VkImageType");
351 }
352 break;
353 }
354 case VK_IMAGE_ASPECT_DEPTH_BIT:
355 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
356 &(VkRenderPassBeginInfo) {
357 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
358 .renderPass = device->meta_state.blit.depth_only_rp,
359 .framebuffer = fb,
360 .renderArea = {
361 .offset = { dest_box.offset.x, dest_box.offset.y },
362 .extent = { dest_box.extent.width, dest_box.extent.height },
363 },
364 .clearValueCount = 0,
365 .pClearValues = NULL,
366 }, VK_SUBPASS_CONTENTS_INLINE);
367 switch (src_image->type) {
368 case VK_IMAGE_TYPE_1D:
369 pipeline = device->meta_state.blit.depth_only_1d_pipeline;
370 break;
371 case VK_IMAGE_TYPE_2D:
372 pipeline = device->meta_state.blit.depth_only_2d_pipeline;
373 break;
374 case VK_IMAGE_TYPE_3D:
375 pipeline = device->meta_state.blit.depth_only_3d_pipeline;
376 break;
377 default:
378 unreachable(!"bad VkImageType");
379 }
380 break;
381 case VK_IMAGE_ASPECT_STENCIL_BIT:
382 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer),
383 &(VkRenderPassBeginInfo) {
384 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO,
385 .renderPass = device->meta_state.blit.stencil_only_rp,
386 .framebuffer = fb,
387 .renderArea = {
388 .offset = { dest_box.offset.x, dest_box.offset.y },
389 .extent = { dest_box.extent.width, dest_box.extent.height },
390 },
391 .clearValueCount = 0,
392 .pClearValues = NULL,
393 }, VK_SUBPASS_CONTENTS_INLINE);
394 switch (src_image->type) {
395 case VK_IMAGE_TYPE_1D:
396 pipeline = device->meta_state.blit.stencil_only_1d_pipeline;
397 break;
398 case VK_IMAGE_TYPE_2D:
399 pipeline = device->meta_state.blit.stencil_only_2d_pipeline;
400 break;
401 case VK_IMAGE_TYPE_3D:
402 pipeline = device->meta_state.blit.stencil_only_3d_pipeline;
403 break;
404 default:
405 unreachable(!"bad VkImageType");
406 }
407 break;
408 default:
409 unreachable(!"bad VkImageType");
410 }
411
412 if (cmd_buffer->state.pipeline != radv_pipeline_from_handle(pipeline)) {
413 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
414 VK_PIPELINE_BIND_POINT_GRAPHICS, pipeline);
415 }
416
417 radv_meta_push_descriptor_set(cmd_buffer, VK_PIPELINE_BIND_POINT_GRAPHICS,
418 device->meta_state.blit.pipeline_layout,
419 0, /* set */
420 1, /* descriptorWriteCount */
421 (VkWriteDescriptorSet[]) {
422 {
423 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
424 .dstBinding = 0,
425 .dstArrayElement = 0,
426 .descriptorCount = 1,
427 .descriptorType = VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER,
428 .pImageInfo = (VkDescriptorImageInfo[]) {
429 {
430 .sampler = sampler,
431 .imageView = radv_image_view_to_handle(src_iview),
432 .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
433 },
434 }
435 }
436 });
437
438 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkViewport) {
439 .x = dest_offset_0.x,
440 .y = dest_offset_0.y,
441 .width = dest_offset_1.x - dest_offset_0.x,
442 .height = dest_offset_1.y - dest_offset_0.y,
443 .minDepth = 0.0f,
444 .maxDepth = 1.0f
445 });
446
447 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer), 0, 1, &(VkRect2D) {
448 .offset = (VkOffset2D) { MIN2(dest_offset_0.x, dest_offset_1.x), MIN2(dest_offset_0.y, dest_offset_1.y) },
449 .extent = (VkExtent2D) {
450 abs(dest_offset_1.x - dest_offset_0.x),
451 abs(dest_offset_1.y - dest_offset_0.y)
452 },
453 });
454
455 radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer), 3, 1, 0, 0);
456
457 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer));
458
459 /* At the point where we emit the draw call, all data from the
460 * descriptor sets, etc. has been used. We are free to delete it.
461 */
462 /* TODO: above comment is not valid for at least descriptor sets/pools,
463 * as we may not free them till after execution finishes. Check others. */
464
465 radv_DestroySampler(radv_device_to_handle(device), sampler,
466 &cmd_buffer->pool->alloc);
467 radv_DestroyFramebuffer(radv_device_to_handle(device), fb,
468 &cmd_buffer->pool->alloc);
469 }
470
471 static bool
472 flip_coords(unsigned *src0, unsigned *src1, unsigned *dst0, unsigned *dst1)
473 {
474 bool flip = false;
475 if (*src0 > *src1) {
476 unsigned tmp = *src0;
477 *src0 = *src1;
478 *src1 = tmp;
479 flip = !flip;
480 }
481
482 if (*dst0 > *dst1) {
483 unsigned tmp = *dst0;
484 *dst0 = *dst1;
485 *dst1 = tmp;
486 flip = !flip;
487 }
488 return flip;
489 }
490
491 void radv_CmdBlitImage(
492 VkCommandBuffer commandBuffer,
493 VkImage srcImage,
494 VkImageLayout srcImageLayout,
495 VkImage destImage,
496 VkImageLayout destImageLayout,
497 uint32_t regionCount,
498 const VkImageBlit* pRegions,
499 VkFilter filter)
500
501 {
502 RADV_FROM_HANDLE(radv_cmd_buffer, cmd_buffer, commandBuffer);
503 RADV_FROM_HANDLE(radv_image, src_image, srcImage);
504 RADV_FROM_HANDLE(radv_image, dest_image, destImage);
505 struct radv_meta_saved_state saved_state;
506
507 /* From the Vulkan 1.0 spec:
508 *
509 * vkCmdBlitImage must not be used for multisampled source or
510 * destination images. Use vkCmdResolveImage for this purpose.
511 */
512 assert(src_image->info.samples == 1);
513 assert(dest_image->info.samples == 1);
514
515 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state, cmd_buffer);
516
517 for (unsigned r = 0; r < regionCount; r++) {
518 const VkImageSubresourceLayers *src_res = &pRegions[r].srcSubresource;
519 const VkImageSubresourceLayers *dst_res = &pRegions[r].dstSubresource;
520 struct radv_image_view src_iview;
521 radv_image_view_init(&src_iview, cmd_buffer->device,
522 &(VkImageViewCreateInfo) {
523 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
524 .image = srcImage,
525 .viewType = radv_meta_get_view_type(src_image),
526 .format = src_image->vk_format,
527 .subresourceRange = {
528 .aspectMask = src_res->aspectMask,
529 .baseMipLevel = src_res->mipLevel,
530 .levelCount = 1,
531 .baseArrayLayer = src_res->baseArrayLayer,
532 .layerCount = 1
533 },
534 });
535
536 unsigned dst_start, dst_end;
537 if (dest_image->type == VK_IMAGE_TYPE_3D) {
538 assert(dst_res->baseArrayLayer == 0);
539 dst_start = pRegions[r].dstOffsets[0].z;
540 dst_end = pRegions[r].dstOffsets[1].z;
541 } else {
542 dst_start = dst_res->baseArrayLayer;
543 dst_end = dst_start + dst_res->layerCount;
544 }
545
546 unsigned src_start, src_end;
547 if (src_image->type == VK_IMAGE_TYPE_3D) {
548 assert(src_res->baseArrayLayer == 0);
549 src_start = pRegions[r].srcOffsets[0].z;
550 src_end = pRegions[r].srcOffsets[1].z;
551 } else {
552 src_start = src_res->baseArrayLayer;
553 src_end = src_start + src_res->layerCount;
554 }
555
556 bool flip_z = flip_coords(&src_start, &src_end, &dst_start, &dst_end);
557 float src_z_step = (float)(src_end + 1 - src_start) /
558 (float)(dst_end + 1 - dst_start);
559
560 if (flip_z) {
561 src_start = src_end;
562 src_z_step *= -1;
563 }
564
565 unsigned src_x0 = pRegions[r].srcOffsets[0].x;
566 unsigned src_x1 = pRegions[r].srcOffsets[1].x;
567 unsigned dst_x0 = pRegions[r].dstOffsets[0].x;
568 unsigned dst_x1 = pRegions[r].dstOffsets[1].x;
569
570 unsigned src_y0 = pRegions[r].srcOffsets[0].y;
571 unsigned src_y1 = pRegions[r].srcOffsets[1].y;
572 unsigned dst_y0 = pRegions[r].dstOffsets[0].y;
573 unsigned dst_y1 = pRegions[r].dstOffsets[1].y;
574
575 VkRect2D dest_box;
576 dest_box.offset.x = MIN2(dst_x0, dst_x1);
577 dest_box.offset.y = MIN2(dst_y0, dst_y1);
578 dest_box.extent.width = abs(dst_x1 - dst_x0);
579 dest_box.extent.height = abs(dst_y1 - dst_y0);
580
581 struct radv_image_view dest_iview;
582 const unsigned num_layers = dst_end - dst_start;
583 for (unsigned i = 0; i < num_layers; i++) {
584 const VkOffset3D dest_offset_0 = {
585 .x = dst_x0,
586 .y = dst_y0,
587 .z = dst_start + i ,
588 };
589 const VkOffset3D dest_offset_1 = {
590 .x = dst_x1,
591 .y = dst_y1,
592 .z = dst_start + i ,
593 };
594 VkOffset3D src_offset_0 = {
595 .x = src_x0,
596 .y = src_y0,
597 .z = src_start + i * src_z_step,
598 };
599 VkOffset3D src_offset_1 = {
600 .x = src_x1,
601 .y = src_y1,
602 .z = src_start + i * src_z_step,
603 };
604 const uint32_t dest_array_slice =
605 radv_meta_get_iview_layer(dest_image, dst_res,
606 &dest_offset_0);
607
608 radv_image_view_init(&dest_iview, cmd_buffer->device,
609 &(VkImageViewCreateInfo) {
610 .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
611 .image = destImage,
612 .viewType = radv_meta_get_view_type(dest_image),
613 .format = dest_image->vk_format,
614 .subresourceRange = {
615 .aspectMask = dst_res->aspectMask,
616 .baseMipLevel = dst_res->mipLevel,
617 .levelCount = 1,
618 .baseArrayLayer = dest_array_slice,
619 .layerCount = 1
620 },
621 });
622 meta_emit_blit(cmd_buffer,
623 src_image, &src_iview,
624 src_offset_0, src_offset_1,
625 dest_image, &dest_iview,
626 dest_offset_0, dest_offset_1,
627 dest_box,
628 filter);
629 }
630 }
631
632 radv_meta_restore(&saved_state, cmd_buffer);
633 }
634
635 void
636 radv_device_finish_meta_blit_state(struct radv_device *device)
637 {
638 for (unsigned i = 0; i < NUM_META_FS_KEYS; ++i) {
639 if (device->meta_state.blit.render_pass[i])
640 radv_DestroyRenderPass(radv_device_to_handle(device),
641 device->meta_state.blit.render_pass[i],
642 &device->meta_state.alloc);
643 if (device->meta_state.blit.pipeline_1d_src[i])
644 radv_DestroyPipeline(radv_device_to_handle(device),
645 device->meta_state.blit.pipeline_1d_src[i],
646 &device->meta_state.alloc);
647 if (device->meta_state.blit.pipeline_2d_src[i])
648 radv_DestroyPipeline(radv_device_to_handle(device),
649 device->meta_state.blit.pipeline_2d_src[i],
650 &device->meta_state.alloc);
651 if (device->meta_state.blit.pipeline_3d_src[i])
652 radv_DestroyPipeline(radv_device_to_handle(device),
653 device->meta_state.blit.pipeline_3d_src[i],
654 &device->meta_state.alloc);
655 }
656
657 if (device->meta_state.blit.depth_only_rp)
658 radv_DestroyRenderPass(radv_device_to_handle(device),
659 device->meta_state.blit.depth_only_rp,
660 &device->meta_state.alloc);
661 if (device->meta_state.blit.depth_only_1d_pipeline)
662 radv_DestroyPipeline(radv_device_to_handle(device),
663 device->meta_state.blit.depth_only_1d_pipeline,
664 &device->meta_state.alloc);
665 if (device->meta_state.blit.depth_only_2d_pipeline)
666 radv_DestroyPipeline(radv_device_to_handle(device),
667 device->meta_state.blit.depth_only_2d_pipeline,
668 &device->meta_state.alloc);
669 if (device->meta_state.blit.depth_only_3d_pipeline)
670 radv_DestroyPipeline(radv_device_to_handle(device),
671 device->meta_state.blit.depth_only_3d_pipeline,
672 &device->meta_state.alloc);
673 if (device->meta_state.blit.stencil_only_rp)
674 radv_DestroyRenderPass(radv_device_to_handle(device),
675 device->meta_state.blit.stencil_only_rp,
676 &device->meta_state.alloc);
677 if (device->meta_state.blit.stencil_only_1d_pipeline)
678 radv_DestroyPipeline(radv_device_to_handle(device),
679 device->meta_state.blit.stencil_only_1d_pipeline,
680 &device->meta_state.alloc);
681 if (device->meta_state.blit.stencil_only_2d_pipeline)
682 radv_DestroyPipeline(radv_device_to_handle(device),
683 device->meta_state.blit.stencil_only_2d_pipeline,
684 &device->meta_state.alloc);
685 if (device->meta_state.blit.stencil_only_3d_pipeline)
686 radv_DestroyPipeline(radv_device_to_handle(device),
687 device->meta_state.blit.stencil_only_3d_pipeline,
688 &device->meta_state.alloc);
689 if (device->meta_state.blit.pipeline_layout)
690 radv_DestroyPipelineLayout(radv_device_to_handle(device),
691 device->meta_state.blit.pipeline_layout,
692 &device->meta_state.alloc);
693 if (device->meta_state.blit.ds_layout)
694 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
695 device->meta_state.blit.ds_layout,
696 &device->meta_state.alloc);
697 }
698
699 static VkFormat pipeline_formats[] = {
700 VK_FORMAT_R8G8B8A8_UNORM,
701 VK_FORMAT_R8G8B8A8_UINT,
702 VK_FORMAT_R8G8B8A8_SINT,
703 VK_FORMAT_A2R10G10B10_UINT_PACK32,
704 VK_FORMAT_A2R10G10B10_SINT_PACK32,
705 VK_FORMAT_R16G16B16A16_UNORM,
706 VK_FORMAT_R16G16B16A16_SNORM,
707 VK_FORMAT_R16G16B16A16_UINT,
708 VK_FORMAT_R16G16B16A16_SINT,
709 VK_FORMAT_R32_SFLOAT,
710 VK_FORMAT_R32G32_SFLOAT,
711 VK_FORMAT_R32G32B32A32_SFLOAT
712 };
713
714 static VkResult
715 radv_device_init_meta_blit_color(struct radv_device *device,
716 struct radv_shader_module *vs)
717 {
718 struct radv_shader_module fs_1d = {0}, fs_2d = {0}, fs_3d = {0};
719 VkResult result;
720
721 fs_1d.nir = build_nir_copy_fragment_shader(GLSL_SAMPLER_DIM_1D);
722 fs_2d.nir = build_nir_copy_fragment_shader(GLSL_SAMPLER_DIM_2D);
723 fs_3d.nir = build_nir_copy_fragment_shader(GLSL_SAMPLER_DIM_3D);
724
725 for (unsigned i = 0; i < ARRAY_SIZE(pipeline_formats); ++i) {
726 unsigned key = radv_format_meta_fs_key(pipeline_formats[i]);
727 result = radv_CreateRenderPass(radv_device_to_handle(device),
728 &(VkRenderPassCreateInfo) {
729 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
730 .attachmentCount = 1,
731 .pAttachments = &(VkAttachmentDescription) {
732 .format = pipeline_formats[i],
733 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
734 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
735 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
736 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
737 },
738 .subpassCount = 1,
739 .pSubpasses = &(VkSubpassDescription) {
740 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
741 .inputAttachmentCount = 0,
742 .colorAttachmentCount = 1,
743 .pColorAttachments = &(VkAttachmentReference) {
744 .attachment = 0,
745 .layout = VK_IMAGE_LAYOUT_GENERAL,
746 },
747 .pResolveAttachments = NULL,
748 .pDepthStencilAttachment = &(VkAttachmentReference) {
749 .attachment = VK_ATTACHMENT_UNUSED,
750 .layout = VK_IMAGE_LAYOUT_GENERAL,
751 },
752 .preserveAttachmentCount = 1,
753 .pPreserveAttachments = (uint32_t[]) { 0 },
754 },
755 .dependencyCount = 0,
756 }, &device->meta_state.alloc, &device->meta_state.blit.render_pass[key]);
757 if (result != VK_SUCCESS)
758 goto fail;
759
760 VkPipelineVertexInputStateCreateInfo vi_create_info = {
761 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
762 .vertexBindingDescriptionCount = 0,
763 .vertexAttributeDescriptionCount = 0,
764 };
765
766 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
767 {
768 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
769 .stage = VK_SHADER_STAGE_VERTEX_BIT,
770 .module = radv_shader_module_to_handle(vs),
771 .pName = "main",
772 .pSpecializationInfo = NULL
773 }, {
774 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
775 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
776 .module = VK_NULL_HANDLE, /* TEMPLATE VALUE! FILL ME IN! */
777 .pName = "main",
778 .pSpecializationInfo = NULL
779 },
780 };
781
782 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
783 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
784 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
785 .pStages = pipeline_shader_stages,
786 .pVertexInputState = &vi_create_info,
787 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
788 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
789 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
790 .primitiveRestartEnable = false,
791 },
792 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
793 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
794 .viewportCount = 1,
795 .scissorCount = 1,
796 },
797 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
798 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
799 .rasterizerDiscardEnable = false,
800 .polygonMode = VK_POLYGON_MODE_FILL,
801 .cullMode = VK_CULL_MODE_NONE,
802 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
803 },
804 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
805 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
806 .rasterizationSamples = 1,
807 .sampleShadingEnable = false,
808 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
809 },
810 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
811 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
812 .attachmentCount = 1,
813 .pAttachments = (VkPipelineColorBlendAttachmentState []) {
814 { .colorWriteMask =
815 VK_COLOR_COMPONENT_A_BIT |
816 VK_COLOR_COMPONENT_R_BIT |
817 VK_COLOR_COMPONENT_G_BIT |
818 VK_COLOR_COMPONENT_B_BIT },
819 }
820 },
821 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
822 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
823 .dynamicStateCount = 4,
824 .pDynamicStates = (VkDynamicState[]) {
825 VK_DYNAMIC_STATE_VIEWPORT,
826 VK_DYNAMIC_STATE_SCISSOR,
827 VK_DYNAMIC_STATE_LINE_WIDTH,
828 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
829 },
830 },
831 .flags = 0,
832 .layout = device->meta_state.blit.pipeline_layout,
833 .renderPass = device->meta_state.blit.render_pass[key],
834 .subpass = 0,
835 };
836
837 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
838 .use_rectlist = true
839 };
840
841 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_1d);
842 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
843 radv_pipeline_cache_to_handle(&device->meta_state.cache),
844 &vk_pipeline_info, &radv_pipeline_info,
845 &device->meta_state.alloc, &device->meta_state.blit.pipeline_1d_src[key]);
846 if (result != VK_SUCCESS)
847 goto fail;
848
849 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_2d);
850 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
851 radv_pipeline_cache_to_handle(&device->meta_state.cache),
852 &vk_pipeline_info, &radv_pipeline_info,
853 &device->meta_state.alloc, &device->meta_state.blit.pipeline_2d_src[key]);
854 if (result != VK_SUCCESS)
855 goto fail;
856
857 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_3d);
858 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
859 radv_pipeline_cache_to_handle(&device->meta_state.cache),
860 &vk_pipeline_info, &radv_pipeline_info,
861 &device->meta_state.alloc, &device->meta_state.blit.pipeline_3d_src[key]);
862 if (result != VK_SUCCESS)
863 goto fail;
864
865 }
866
867 result = VK_SUCCESS;
868 fail:
869 ralloc_free(fs_1d.nir);
870 ralloc_free(fs_2d.nir);
871 ralloc_free(fs_3d.nir);
872 return result;
873 }
874
875 static VkResult
876 radv_device_init_meta_blit_depth(struct radv_device *device,
877 struct radv_shader_module *vs)
878 {
879 struct radv_shader_module fs_1d = {0}, fs_2d = {0}, fs_3d = {0};
880 VkResult result;
881
882 fs_1d.nir = build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_1D);
883 fs_2d.nir = build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_2D);
884 fs_3d.nir = build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_3D);
885
886 result = radv_CreateRenderPass(radv_device_to_handle(device),
887 &(VkRenderPassCreateInfo) {
888 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
889 .attachmentCount = 1,
890 .pAttachments = &(VkAttachmentDescription) {
891 .format = VK_FORMAT_D32_SFLOAT,
892 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
893 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
894 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
895 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
896 },
897 .subpassCount = 1,
898 .pSubpasses = &(VkSubpassDescription) {
899 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
900 .inputAttachmentCount = 0,
901 .colorAttachmentCount = 0,
902 .pColorAttachments = NULL,
903 .pResolveAttachments = NULL,
904 .pDepthStencilAttachment = &(VkAttachmentReference) {
905 .attachment = 0,
906 .layout = VK_IMAGE_LAYOUT_GENERAL,
907 },
908 .preserveAttachmentCount = 1,
909 .pPreserveAttachments = (uint32_t[]) { 0 },
910 },
911 .dependencyCount = 0,
912 }, &device->meta_state.alloc, &device->meta_state.blit.depth_only_rp);
913 if (result != VK_SUCCESS)
914 goto fail;
915
916 VkPipelineVertexInputStateCreateInfo vi_create_info = {
917 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
918 .vertexBindingDescriptionCount = 0,
919 .vertexAttributeDescriptionCount = 0,
920 };
921
922 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
923 {
924 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
925 .stage = VK_SHADER_STAGE_VERTEX_BIT,
926 .module = radv_shader_module_to_handle(vs),
927 .pName = "main",
928 .pSpecializationInfo = NULL
929 }, {
930 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
931 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
932 .module = VK_NULL_HANDLE, /* TEMPLATE VALUE! FILL ME IN! */
933 .pName = "main",
934 .pSpecializationInfo = NULL
935 },
936 };
937
938 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
939 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
940 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
941 .pStages = pipeline_shader_stages,
942 .pVertexInputState = &vi_create_info,
943 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
944 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
945 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
946 .primitiveRestartEnable = false,
947 },
948 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
949 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
950 .viewportCount = 1,
951 .scissorCount = 1,
952 },
953 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
954 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
955 .rasterizerDiscardEnable = false,
956 .polygonMode = VK_POLYGON_MODE_FILL,
957 .cullMode = VK_CULL_MODE_NONE,
958 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
959 },
960 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
961 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
962 .rasterizationSamples = 1,
963 .sampleShadingEnable = false,
964 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
965 },
966 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
967 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
968 .attachmentCount = 0,
969 .pAttachments = NULL,
970 },
971 .pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
972 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
973 .depthTestEnable = true,
974 .depthWriteEnable = true,
975 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
976 },
977 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
978 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
979 .dynamicStateCount = 9,
980 .pDynamicStates = (VkDynamicState[]) {
981 VK_DYNAMIC_STATE_VIEWPORT,
982 VK_DYNAMIC_STATE_SCISSOR,
983 VK_DYNAMIC_STATE_LINE_WIDTH,
984 VK_DYNAMIC_STATE_DEPTH_BIAS,
985 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
986 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
987 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK,
988 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK,
989 VK_DYNAMIC_STATE_STENCIL_REFERENCE,
990 },
991 },
992 .flags = 0,
993 .layout = device->meta_state.blit.pipeline_layout,
994 .renderPass = device->meta_state.blit.depth_only_rp,
995 .subpass = 0,
996 };
997
998 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
999 .use_rectlist = true
1000 };
1001
1002 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_1d);
1003 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1004 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1005 &vk_pipeline_info, &radv_pipeline_info,
1006 &device->meta_state.alloc, &device->meta_state.blit.depth_only_1d_pipeline);
1007 if (result != VK_SUCCESS)
1008 goto fail;
1009
1010 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_2d);
1011 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1012 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1013 &vk_pipeline_info, &radv_pipeline_info,
1014 &device->meta_state.alloc, &device->meta_state.blit.depth_only_2d_pipeline);
1015 if (result != VK_SUCCESS)
1016 goto fail;
1017
1018 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_3d);
1019 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1020 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1021 &vk_pipeline_info, &radv_pipeline_info,
1022 &device->meta_state.alloc, &device->meta_state.blit.depth_only_3d_pipeline);
1023 if (result != VK_SUCCESS)
1024 goto fail;
1025
1026 fail:
1027 ralloc_free(fs_1d.nir);
1028 ralloc_free(fs_2d.nir);
1029 ralloc_free(fs_3d.nir);
1030 return result;
1031 }
1032
1033 static VkResult
1034 radv_device_init_meta_blit_stencil(struct radv_device *device,
1035 struct radv_shader_module *vs)
1036 {
1037 struct radv_shader_module fs_1d = {0}, fs_2d = {0}, fs_3d = {0};
1038 VkResult result;
1039
1040 fs_1d.nir = build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_1D);
1041 fs_2d.nir = build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_2D);
1042 fs_3d.nir = build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_3D);
1043
1044 result = radv_CreateRenderPass(radv_device_to_handle(device),
1045 &(VkRenderPassCreateInfo) {
1046 .sType = VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO,
1047 .attachmentCount = 1,
1048 .pAttachments = &(VkAttachmentDescription) {
1049 .format = VK_FORMAT_S8_UINT,
1050 .loadOp = VK_ATTACHMENT_LOAD_OP_LOAD,
1051 .storeOp = VK_ATTACHMENT_STORE_OP_STORE,
1052 .initialLayout = VK_IMAGE_LAYOUT_GENERAL,
1053 .finalLayout = VK_IMAGE_LAYOUT_GENERAL,
1054 },
1055 .subpassCount = 1,
1056 .pSubpasses = &(VkSubpassDescription) {
1057 .pipelineBindPoint = VK_PIPELINE_BIND_POINT_GRAPHICS,
1058 .inputAttachmentCount = 0,
1059 .colorAttachmentCount = 0,
1060 .pColorAttachments = NULL,
1061 .pResolveAttachments = NULL,
1062 .pDepthStencilAttachment = &(VkAttachmentReference) {
1063 .attachment = 0,
1064 .layout = VK_IMAGE_LAYOUT_GENERAL,
1065 },
1066 .preserveAttachmentCount = 1,
1067 .pPreserveAttachments = (uint32_t[]) { 0 },
1068 },
1069 .dependencyCount = 0,
1070 }, &device->meta_state.alloc, &device->meta_state.blit.stencil_only_rp);
1071 if (result != VK_SUCCESS)
1072 goto fail;
1073
1074 VkPipelineVertexInputStateCreateInfo vi_create_info = {
1075 .sType = VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO,
1076 .vertexBindingDescriptionCount = 0,
1077 .vertexAttributeDescriptionCount = 0,
1078 };
1079
1080 VkPipelineShaderStageCreateInfo pipeline_shader_stages[] = {
1081 {
1082 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1083 .stage = VK_SHADER_STAGE_VERTEX_BIT,
1084 .module = radv_shader_module_to_handle(vs),
1085 .pName = "main",
1086 .pSpecializationInfo = NULL
1087 }, {
1088 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
1089 .stage = VK_SHADER_STAGE_FRAGMENT_BIT,
1090 .module = VK_NULL_HANDLE, /* TEMPLATE VALUE! FILL ME IN! */
1091 .pName = "main",
1092 .pSpecializationInfo = NULL
1093 },
1094 };
1095
1096 const VkGraphicsPipelineCreateInfo vk_pipeline_info = {
1097 .sType = VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO,
1098 .stageCount = ARRAY_SIZE(pipeline_shader_stages),
1099 .pStages = pipeline_shader_stages,
1100 .pVertexInputState = &vi_create_info,
1101 .pInputAssemblyState = &(VkPipelineInputAssemblyStateCreateInfo) {
1102 .sType = VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO,
1103 .topology = VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP,
1104 .primitiveRestartEnable = false,
1105 },
1106 .pViewportState = &(VkPipelineViewportStateCreateInfo) {
1107 .sType = VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO,
1108 .viewportCount = 1,
1109 .scissorCount = 1,
1110 },
1111 .pRasterizationState = &(VkPipelineRasterizationStateCreateInfo) {
1112 .sType = VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO,
1113 .rasterizerDiscardEnable = false,
1114 .polygonMode = VK_POLYGON_MODE_FILL,
1115 .cullMode = VK_CULL_MODE_NONE,
1116 .frontFace = VK_FRONT_FACE_COUNTER_CLOCKWISE
1117 },
1118 .pMultisampleState = &(VkPipelineMultisampleStateCreateInfo) {
1119 .sType = VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO,
1120 .rasterizationSamples = 1,
1121 .sampleShadingEnable = false,
1122 .pSampleMask = (VkSampleMask[]) { UINT32_MAX },
1123 },
1124 .pColorBlendState = &(VkPipelineColorBlendStateCreateInfo) {
1125 .sType = VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO,
1126 .attachmentCount = 0,
1127 .pAttachments = NULL,
1128 },
1129 .pDepthStencilState = &(VkPipelineDepthStencilStateCreateInfo) {
1130 .sType = VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO,
1131 .depthTestEnable = false,
1132 .depthWriteEnable = false,
1133 .stencilTestEnable = true,
1134 .front = {
1135 .failOp = VK_STENCIL_OP_REPLACE,
1136 .passOp = VK_STENCIL_OP_REPLACE,
1137 .depthFailOp = VK_STENCIL_OP_REPLACE,
1138 .compareOp = VK_COMPARE_OP_ALWAYS,
1139 .compareMask = 0xff,
1140 .writeMask = 0xff,
1141 .reference = 0
1142 },
1143 .back = {
1144 .failOp = VK_STENCIL_OP_REPLACE,
1145 .passOp = VK_STENCIL_OP_REPLACE,
1146 .depthFailOp = VK_STENCIL_OP_REPLACE,
1147 .compareOp = VK_COMPARE_OP_ALWAYS,
1148 .compareMask = 0xff,
1149 .writeMask = 0xff,
1150 .reference = 0
1151 },
1152 .depthCompareOp = VK_COMPARE_OP_ALWAYS,
1153 },
1154
1155 .pDynamicState = &(VkPipelineDynamicStateCreateInfo) {
1156 .sType = VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO,
1157 .dynamicStateCount = 6,
1158 .pDynamicStates = (VkDynamicState[]) {
1159 VK_DYNAMIC_STATE_VIEWPORT,
1160 VK_DYNAMIC_STATE_SCISSOR,
1161 VK_DYNAMIC_STATE_LINE_WIDTH,
1162 VK_DYNAMIC_STATE_DEPTH_BIAS,
1163 VK_DYNAMIC_STATE_BLEND_CONSTANTS,
1164 VK_DYNAMIC_STATE_DEPTH_BOUNDS,
1165 },
1166 },
1167 .flags = 0,
1168 .layout = device->meta_state.blit.pipeline_layout,
1169 .renderPass = device->meta_state.blit.stencil_only_rp,
1170 .subpass = 0,
1171 };
1172
1173 const struct radv_graphics_pipeline_create_info radv_pipeline_info = {
1174 .use_rectlist = true
1175 };
1176
1177 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_1d);
1178 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1179 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1180 &vk_pipeline_info, &radv_pipeline_info,
1181 &device->meta_state.alloc, &device->meta_state.blit.stencil_only_1d_pipeline);
1182 if (result != VK_SUCCESS)
1183 goto fail;
1184
1185 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_2d);
1186 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1187 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1188 &vk_pipeline_info, &radv_pipeline_info,
1189 &device->meta_state.alloc, &device->meta_state.blit.stencil_only_2d_pipeline);
1190 if (result != VK_SUCCESS)
1191 goto fail;
1192
1193 pipeline_shader_stages[1].module = radv_shader_module_to_handle(&fs_3d);
1194 result = radv_graphics_pipeline_create(radv_device_to_handle(device),
1195 radv_pipeline_cache_to_handle(&device->meta_state.cache),
1196 &vk_pipeline_info, &radv_pipeline_info,
1197 &device->meta_state.alloc, &device->meta_state.blit.stencil_only_3d_pipeline);
1198 if (result != VK_SUCCESS)
1199 goto fail;
1200
1201 fail:
1202 ralloc_free(fs_1d.nir);
1203 ralloc_free(fs_2d.nir);
1204 ralloc_free(fs_3d.nir);
1205 return result;
1206 }
1207
1208 VkResult
1209 radv_device_init_meta_blit_state(struct radv_device *device)
1210 {
1211 VkResult result;
1212 struct radv_shader_module vs = {0};
1213 zero(device->meta_state.blit);
1214
1215 VkDescriptorSetLayoutCreateInfo ds_layout_info = {
1216 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
1217 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
1218 .bindingCount = 1,
1219 .pBindings = (VkDescriptorSetLayoutBinding[]) {
1220 {
1221 .binding = 0,
1222 .descriptorType = VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER,
1223 .descriptorCount = 1,
1224 .stageFlags = VK_SHADER_STAGE_FRAGMENT_BIT,
1225 .pImmutableSamplers = NULL
1226 },
1227 }
1228 };
1229 result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
1230 &ds_layout_info,
1231 &device->meta_state.alloc,
1232 &device->meta_state.blit.ds_layout);
1233 if (result != VK_SUCCESS)
1234 goto fail;
1235
1236 const VkPushConstantRange push_constant_range = {VK_SHADER_STAGE_VERTEX_BIT, 0, 20};
1237
1238 result = radv_CreatePipelineLayout(radv_device_to_handle(device),
1239 &(VkPipelineLayoutCreateInfo) {
1240 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
1241 .setLayoutCount = 1,
1242 .pSetLayouts = &device->meta_state.blit.ds_layout,
1243 .pushConstantRangeCount = 1,
1244 .pPushConstantRanges = &push_constant_range,
1245 },
1246 &device->meta_state.alloc, &device->meta_state.blit.pipeline_layout);
1247 if (result != VK_SUCCESS)
1248 goto fail;
1249
1250 vs.nir = build_nir_vertex_shader();
1251
1252 result = radv_device_init_meta_blit_color(device, &vs);
1253 if (result != VK_SUCCESS)
1254 goto fail;
1255
1256 result = radv_device_init_meta_blit_depth(device, &vs);
1257 if (result != VK_SUCCESS)
1258 goto fail;
1259
1260 result = radv_device_init_meta_blit_stencil(device, &vs);
1261
1262 fail:
1263 ralloc_free(vs.nir);
1264 if (result != VK_SUCCESS)
1265 radv_device_finish_meta_blit_state(device);
1266 return result;
1267 }