2 * Copyright © 2015 Intel Corporation
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
24 #include "radv_meta.h"
25 #include "nir/nir_builder.h"
28 VkOffset3D src_offset
;
29 VkExtent3D src_extent
;
30 VkOffset3D dest_offset
;
31 VkExtent3D dest_extent
;
35 build_nir_vertex_shader(void)
37 const struct glsl_type
*vec4
= glsl_vec4_type();
40 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_VERTEX
, NULL
);
41 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, "meta_blit_vs");
43 nir_variable
*pos_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
45 pos_out
->data
.location
= VARYING_SLOT_POS
;
47 nir_variable
*tex_pos_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
49 tex_pos_out
->data
.location
= VARYING_SLOT_VAR0
;
50 tex_pos_out
->data
.interpolation
= INTERP_MODE_SMOOTH
;
52 nir_ssa_def
*outvec
= radv_meta_gen_rect_vertices(&b
);
54 nir_store_var(&b
, pos_out
, outvec
, 0xf);
56 nir_intrinsic_instr
*src_box
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_push_constant
);
57 src_box
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
58 nir_intrinsic_set_base(src_box
, 0);
59 nir_intrinsic_set_range(src_box
, 16);
60 src_box
->num_components
= 4;
61 nir_ssa_dest_init(&src_box
->instr
, &src_box
->dest
, 4, 32, "src_box");
62 nir_builder_instr_insert(&b
, &src_box
->instr
);
64 nir_intrinsic_instr
*src0_z
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_push_constant
);
65 src0_z
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
66 nir_intrinsic_set_base(src0_z
, 16);
67 nir_intrinsic_set_range(src0_z
, 4);
68 src0_z
->num_components
= 1;
69 nir_ssa_dest_init(&src0_z
->instr
, &src0_z
->dest
, 1, 32, "src0_z");
70 nir_builder_instr_insert(&b
, &src0_z
->instr
);
72 nir_intrinsic_instr
*vertex_id
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_vertex_id_zero_base
);
73 nir_ssa_dest_init(&vertex_id
->instr
, &vertex_id
->dest
, 1, 32, "vertexid");
74 nir_builder_instr_insert(&b
, &vertex_id
->instr
);
76 /* vertex 0 - src0_x, src0_y, src0_z */
77 /* vertex 1 - src0_x, src1_y, src0_z*/
78 /* vertex 2 - src1_x, src0_y, src0_z */
79 /* so channel 0 is vertex_id != 2 ? src_x : src_x + w
80 channel 1 is vertex id != 1 ? src_y : src_y + w */
82 nir_ssa_def
*c0cmp
= nir_ine(&b
, &vertex_id
->dest
.ssa
,
84 nir_ssa_def
*c1cmp
= nir_ine(&b
, &vertex_id
->dest
.ssa
,
88 comp
[0] = nir_bcsel(&b
, c0cmp
,
89 nir_channel(&b
, &src_box
->dest
.ssa
, 0),
90 nir_channel(&b
, &src_box
->dest
.ssa
, 2));
92 comp
[1] = nir_bcsel(&b
, c1cmp
,
93 nir_channel(&b
, &src_box
->dest
.ssa
, 1),
94 nir_channel(&b
, &src_box
->dest
.ssa
, 3));
95 comp
[2] = &src0_z
->dest
.ssa
;
96 comp
[3] = nir_imm_float(&b
, 1.0);
97 nir_ssa_def
*out_tex_vec
= nir_vec(&b
, comp
, 4);
98 nir_store_var(&b
, tex_pos_out
, out_tex_vec
, 0xf);
103 build_nir_copy_fragment_shader(enum glsl_sampler_dim tex_dim
)
105 char shader_name
[64];
106 const struct glsl_type
*vec4
= glsl_vec4_type();
109 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
111 sprintf(shader_name
, "meta_blit_fs.%d", tex_dim
);
112 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, shader_name
);
114 nir_variable
*tex_pos_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
116 tex_pos_in
->data
.location
= VARYING_SLOT_VAR0
;
118 /* Swizzle the array index which comes in as Z coordinate into the right
121 unsigned swz
[] = { 0, (tex_dim
== GLSL_SAMPLER_DIM_1D
? 2 : 1), 2 };
122 nir_ssa_def
*const tex_pos
=
123 nir_swizzle(&b
, nir_load_var(&b
, tex_pos_in
), swz
,
124 (tex_dim
== GLSL_SAMPLER_DIM_1D
? 2 : 3), false);
126 const struct glsl_type
*sampler_type
=
127 glsl_sampler_type(tex_dim
, false, tex_dim
!= GLSL_SAMPLER_DIM_3D
,
128 glsl_get_base_type(vec4
));
129 nir_variable
*sampler
= nir_variable_create(b
.shader
, nir_var_uniform
,
130 sampler_type
, "s_tex");
131 sampler
->data
.descriptor_set
= 0;
132 sampler
->data
.binding
= 0;
134 nir_tex_instr
*tex
= nir_tex_instr_create(b
.shader
, 1);
135 tex
->sampler_dim
= tex_dim
;
136 tex
->op
= nir_texop_tex
;
137 tex
->src
[0].src_type
= nir_tex_src_coord
;
138 tex
->src
[0].src
= nir_src_for_ssa(tex_pos
);
139 tex
->dest_type
= nir_type_float
; /* TODO */
140 tex
->is_array
= glsl_sampler_type_is_array(sampler_type
);
141 tex
->coord_components
= tex_pos
->num_components
;
142 tex
->texture
= nir_deref_var_create(tex
, sampler
);
143 tex
->sampler
= nir_deref_var_create(tex
, sampler
);
145 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, "tex");
146 nir_builder_instr_insert(&b
, &tex
->instr
);
148 nir_variable
*color_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
150 color_out
->data
.location
= FRAG_RESULT_DATA0
;
151 nir_store_var(&b
, color_out
, &tex
->dest
.ssa
, 0xf);
157 build_nir_copy_fragment_shader_depth(enum glsl_sampler_dim tex_dim
)
159 char shader_name
[64];
160 const struct glsl_type
*vec4
= glsl_vec4_type();
163 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
165 sprintf(shader_name
, "meta_blit_depth_fs.%d", tex_dim
);
166 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, shader_name
);
168 nir_variable
*tex_pos_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
170 tex_pos_in
->data
.location
= VARYING_SLOT_VAR0
;
172 /* Swizzle the array index which comes in as Z coordinate into the right
175 unsigned swz
[] = { 0, (tex_dim
== GLSL_SAMPLER_DIM_1D
? 2 : 1), 2 };
176 nir_ssa_def
*const tex_pos
=
177 nir_swizzle(&b
, nir_load_var(&b
, tex_pos_in
), swz
,
178 (tex_dim
== GLSL_SAMPLER_DIM_1D
? 2 : 3), false);
180 const struct glsl_type
*sampler_type
=
181 glsl_sampler_type(tex_dim
, false, tex_dim
!= GLSL_SAMPLER_DIM_3D
,
182 glsl_get_base_type(vec4
));
183 nir_variable
*sampler
= nir_variable_create(b
.shader
, nir_var_uniform
,
184 sampler_type
, "s_tex");
185 sampler
->data
.descriptor_set
= 0;
186 sampler
->data
.binding
= 0;
188 nir_tex_instr
*tex
= nir_tex_instr_create(b
.shader
, 1);
189 tex
->sampler_dim
= tex_dim
;
190 tex
->op
= nir_texop_tex
;
191 tex
->src
[0].src_type
= nir_tex_src_coord
;
192 tex
->src
[0].src
= nir_src_for_ssa(tex_pos
);
193 tex
->dest_type
= nir_type_float
; /* TODO */
194 tex
->is_array
= glsl_sampler_type_is_array(sampler_type
);
195 tex
->coord_components
= tex_pos
->num_components
;
196 tex
->texture
= nir_deref_var_create(tex
, sampler
);
197 tex
->sampler
= nir_deref_var_create(tex
, sampler
);
199 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, "tex");
200 nir_builder_instr_insert(&b
, &tex
->instr
);
202 nir_variable
*color_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
204 color_out
->data
.location
= FRAG_RESULT_DEPTH
;
205 nir_store_var(&b
, color_out
, &tex
->dest
.ssa
, 0x1);
211 build_nir_copy_fragment_shader_stencil(enum glsl_sampler_dim tex_dim
)
213 char shader_name
[64];
214 const struct glsl_type
*vec4
= glsl_vec4_type();
217 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
219 sprintf(shader_name
, "meta_blit_stencil_fs.%d", tex_dim
);
220 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, shader_name
);
222 nir_variable
*tex_pos_in
= nir_variable_create(b
.shader
, nir_var_shader_in
,
224 tex_pos_in
->data
.location
= VARYING_SLOT_VAR0
;
226 /* Swizzle the array index which comes in as Z coordinate into the right
229 unsigned swz
[] = { 0, (tex_dim
== GLSL_SAMPLER_DIM_1D
? 2 : 1), 2 };
230 nir_ssa_def
*const tex_pos
=
231 nir_swizzle(&b
, nir_load_var(&b
, tex_pos_in
), swz
,
232 (tex_dim
== GLSL_SAMPLER_DIM_1D
? 2 : 3), false);
234 const struct glsl_type
*sampler_type
=
235 glsl_sampler_type(tex_dim
, false, tex_dim
!= GLSL_SAMPLER_DIM_3D
,
236 glsl_get_base_type(vec4
));
237 nir_variable
*sampler
= nir_variable_create(b
.shader
, nir_var_uniform
,
238 sampler_type
, "s_tex");
239 sampler
->data
.descriptor_set
= 0;
240 sampler
->data
.binding
= 0;
242 nir_tex_instr
*tex
= nir_tex_instr_create(b
.shader
, 1);
243 tex
->sampler_dim
= tex_dim
;
244 tex
->op
= nir_texop_tex
;
245 tex
->src
[0].src_type
= nir_tex_src_coord
;
246 tex
->src
[0].src
= nir_src_for_ssa(tex_pos
);
247 tex
->dest_type
= nir_type_float
; /* TODO */
248 tex
->is_array
= glsl_sampler_type_is_array(sampler_type
);
249 tex
->coord_components
= tex_pos
->num_components
;
250 tex
->texture
= nir_deref_var_create(tex
, sampler
);
251 tex
->sampler
= nir_deref_var_create(tex
, sampler
);
253 nir_ssa_dest_init(&tex
->instr
, &tex
->dest
, 4, 32, "tex");
254 nir_builder_instr_insert(&b
, &tex
->instr
);
256 nir_variable
*color_out
= nir_variable_create(b
.shader
, nir_var_shader_out
,
258 color_out
->data
.location
= FRAG_RESULT_STENCIL
;
259 nir_store_var(&b
, color_out
, &tex
->dest
.ssa
, 0x1);
265 meta_emit_blit(struct radv_cmd_buffer
*cmd_buffer
,
266 struct radv_image
*src_image
,
267 struct radv_image_view
*src_iview
,
268 VkOffset3D src_offset_0
,
269 VkOffset3D src_offset_1
,
270 struct radv_image
*dest_image
,
271 struct radv_image_view
*dest_iview
,
272 VkOffset3D dest_offset_0
,
273 VkOffset3D dest_offset_1
,
275 VkFilter blit_filter
)
277 struct radv_device
*device
= cmd_buffer
->device
;
278 uint32_t src_width
= radv_minify(src_iview
->image
->info
.width
, src_iview
->base_mip
);
279 uint32_t src_height
= radv_minify(src_iview
->image
->info
.height
, src_iview
->base_mip
);
280 uint32_t src_depth
= radv_minify(src_iview
->image
->info
.depth
, src_iview
->base_mip
);
281 uint32_t dst_width
= radv_minify(dest_iview
->image
->info
.width
, dest_iview
->base_mip
);
282 uint32_t dst_height
= radv_minify(dest_iview
->image
->info
.height
, dest_iview
->base_mip
);
284 assert(src_image
->info
.samples
== dest_image
->info
.samples
);
286 float vertex_push_constants
[5] = {
287 (float)src_offset_0
.x
/ (float)src_width
,
288 (float)src_offset_0
.y
/ (float)src_height
,
289 (float)src_offset_1
.x
/ (float)src_width
,
290 (float)src_offset_1
.y
/ (float)src_height
,
291 (float)src_offset_0
.z
/ (float)src_depth
,
294 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
295 device
->meta_state
.blit
.pipeline_layout
,
296 VK_SHADER_STAGE_VERTEX_BIT
, 0, 20,
297 vertex_push_constants
);
300 radv_CreateSampler(radv_device_to_handle(device
),
301 &(VkSamplerCreateInfo
) {
302 .sType
= VK_STRUCTURE_TYPE_SAMPLER_CREATE_INFO
,
303 .magFilter
= blit_filter
,
304 .minFilter
= blit_filter
,
305 .addressModeU
= VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
,
306 .addressModeV
= VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
,
307 .addressModeW
= VK_SAMPLER_ADDRESS_MODE_CLAMP_TO_EDGE
,
308 }, &cmd_buffer
->pool
->alloc
, &sampler
);
311 radv_CreateFramebuffer(radv_device_to_handle(device
),
312 &(VkFramebufferCreateInfo
) {
313 .sType
= VK_STRUCTURE_TYPE_FRAMEBUFFER_CREATE_INFO
,
314 .attachmentCount
= 1,
315 .pAttachments
= (VkImageView
[]) {
316 radv_image_view_to_handle(dest_iview
),
319 .height
= dst_height
,
321 }, &cmd_buffer
->pool
->alloc
, &fb
);
323 switch (src_iview
->aspect_mask
) {
324 case VK_IMAGE_ASPECT_COLOR_BIT
: {
325 unsigned fs_key
= radv_format_meta_fs_key(dest_image
->vk_format
);
327 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
328 &(VkRenderPassBeginInfo
) {
329 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
330 .renderPass
= device
->meta_state
.blit
.render_pass
[fs_key
],
333 .offset
= { dest_box
.offset
.x
, dest_box
.offset
.y
},
334 .extent
= { dest_box
.extent
.width
, dest_box
.extent
.height
},
336 .clearValueCount
= 0,
337 .pClearValues
= NULL
,
338 }, VK_SUBPASS_CONTENTS_INLINE
);
339 switch (src_image
->type
) {
340 case VK_IMAGE_TYPE_1D
:
341 pipeline
= device
->meta_state
.blit
.pipeline_1d_src
[fs_key
];
343 case VK_IMAGE_TYPE_2D
:
344 pipeline
= device
->meta_state
.blit
.pipeline_2d_src
[fs_key
];
346 case VK_IMAGE_TYPE_3D
:
347 pipeline
= device
->meta_state
.blit
.pipeline_3d_src
[fs_key
];
350 unreachable(!"bad VkImageType");
354 case VK_IMAGE_ASPECT_DEPTH_BIT
:
355 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
356 &(VkRenderPassBeginInfo
) {
357 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
358 .renderPass
= device
->meta_state
.blit
.depth_only_rp
,
361 .offset
= { dest_box
.offset
.x
, dest_box
.offset
.y
},
362 .extent
= { dest_box
.extent
.width
, dest_box
.extent
.height
},
364 .clearValueCount
= 0,
365 .pClearValues
= NULL
,
366 }, VK_SUBPASS_CONTENTS_INLINE
);
367 switch (src_image
->type
) {
368 case VK_IMAGE_TYPE_1D
:
369 pipeline
= device
->meta_state
.blit
.depth_only_1d_pipeline
;
371 case VK_IMAGE_TYPE_2D
:
372 pipeline
= device
->meta_state
.blit
.depth_only_2d_pipeline
;
374 case VK_IMAGE_TYPE_3D
:
375 pipeline
= device
->meta_state
.blit
.depth_only_3d_pipeline
;
378 unreachable(!"bad VkImageType");
381 case VK_IMAGE_ASPECT_STENCIL_BIT
:
382 radv_CmdBeginRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
),
383 &(VkRenderPassBeginInfo
) {
384 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_BEGIN_INFO
,
385 .renderPass
= device
->meta_state
.blit
.stencil_only_rp
,
388 .offset
= { dest_box
.offset
.x
, dest_box
.offset
.y
},
389 .extent
= { dest_box
.extent
.width
, dest_box
.extent
.height
},
391 .clearValueCount
= 0,
392 .pClearValues
= NULL
,
393 }, VK_SUBPASS_CONTENTS_INLINE
);
394 switch (src_image
->type
) {
395 case VK_IMAGE_TYPE_1D
:
396 pipeline
= device
->meta_state
.blit
.stencil_only_1d_pipeline
;
398 case VK_IMAGE_TYPE_2D
:
399 pipeline
= device
->meta_state
.blit
.stencil_only_2d_pipeline
;
401 case VK_IMAGE_TYPE_3D
:
402 pipeline
= device
->meta_state
.blit
.stencil_only_3d_pipeline
;
405 unreachable(!"bad VkImageType");
409 unreachable(!"bad VkImageType");
412 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
413 VK_PIPELINE_BIND_POINT_GRAPHICS
, pipeline
);
415 radv_meta_push_descriptor_set(cmd_buffer
, VK_PIPELINE_BIND_POINT_GRAPHICS
,
416 device
->meta_state
.blit
.pipeline_layout
,
418 1, /* descriptorWriteCount */
419 (VkWriteDescriptorSet
[]) {
421 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
423 .dstArrayElement
= 0,
424 .descriptorCount
= 1,
425 .descriptorType
= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
,
426 .pImageInfo
= (VkDescriptorImageInfo
[]) {
429 .imageView
= radv_image_view_to_handle(src_iview
),
430 .imageLayout
= VK_IMAGE_LAYOUT_GENERAL
,
436 radv_CmdSetViewport(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &(VkViewport
) {
437 .x
= dest_offset_0
.x
,
438 .y
= dest_offset_0
.y
,
439 .width
= dest_offset_1
.x
- dest_offset_0
.x
,
440 .height
= dest_offset_1
.y
- dest_offset_0
.y
,
445 radv_CmdSetScissor(radv_cmd_buffer_to_handle(cmd_buffer
), 0, 1, &(VkRect2D
) {
446 .offset
= (VkOffset2D
) { MIN2(dest_offset_0
.x
, dest_offset_1
.x
), MIN2(dest_offset_0
.y
, dest_offset_1
.y
) },
447 .extent
= (VkExtent2D
) {
448 abs(dest_offset_1
.x
- dest_offset_0
.x
),
449 abs(dest_offset_1
.y
- dest_offset_0
.y
)
453 radv_CmdDraw(radv_cmd_buffer_to_handle(cmd_buffer
), 3, 1, 0, 0);
455 radv_CmdEndRenderPass(radv_cmd_buffer_to_handle(cmd_buffer
));
457 /* At the point where we emit the draw call, all data from the
458 * descriptor sets, etc. has been used. We are free to delete it.
460 /* TODO: above comment is not valid for at least descriptor sets/pools,
461 * as we may not free them till after execution finishes. Check others. */
463 radv_DestroySampler(radv_device_to_handle(device
), sampler
,
464 &cmd_buffer
->pool
->alloc
);
465 radv_DestroyFramebuffer(radv_device_to_handle(device
), fb
,
466 &cmd_buffer
->pool
->alloc
);
470 flip_coords(unsigned *src0
, unsigned *src1
, unsigned *dst0
, unsigned *dst1
)
474 unsigned tmp
= *src0
;
481 unsigned tmp
= *dst0
;
489 void radv_CmdBlitImage(
490 VkCommandBuffer commandBuffer
,
492 VkImageLayout srcImageLayout
,
494 VkImageLayout destImageLayout
,
495 uint32_t regionCount
,
496 const VkImageBlit
* pRegions
,
500 RADV_FROM_HANDLE(radv_cmd_buffer
, cmd_buffer
, commandBuffer
);
501 RADV_FROM_HANDLE(radv_image
, src_image
, srcImage
);
502 RADV_FROM_HANDLE(radv_image
, dest_image
, destImage
);
503 struct radv_meta_saved_state saved_state
;
505 /* From the Vulkan 1.0 spec:
507 * vkCmdBlitImage must not be used for multisampled source or
508 * destination images. Use vkCmdResolveImage for this purpose.
510 assert(src_image
->info
.samples
== 1);
511 assert(dest_image
->info
.samples
== 1);
513 radv_meta_save_graphics_reset_vport_scissor_novertex(&saved_state
, cmd_buffer
);
515 for (unsigned r
= 0; r
< regionCount
; r
++) {
516 const VkImageSubresourceLayers
*src_res
= &pRegions
[r
].srcSubresource
;
517 const VkImageSubresourceLayers
*dst_res
= &pRegions
[r
].dstSubresource
;
518 struct radv_image_view src_iview
;
519 radv_image_view_init(&src_iview
, cmd_buffer
->device
,
520 &(VkImageViewCreateInfo
) {
521 .sType
= VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO
,
523 .viewType
= radv_meta_get_view_type(src_image
),
524 .format
= src_image
->vk_format
,
525 .subresourceRange
= {
526 .aspectMask
= src_res
->aspectMask
,
527 .baseMipLevel
= src_res
->mipLevel
,
529 .baseArrayLayer
= src_res
->baseArrayLayer
,
534 unsigned dst_start
, dst_end
;
535 if (dest_image
->type
== VK_IMAGE_TYPE_3D
) {
536 assert(dst_res
->baseArrayLayer
== 0);
537 dst_start
= pRegions
[r
].dstOffsets
[0].z
;
538 dst_end
= pRegions
[r
].dstOffsets
[1].z
;
540 dst_start
= dst_res
->baseArrayLayer
;
541 dst_end
= dst_start
+ dst_res
->layerCount
;
544 unsigned src_start
, src_end
;
545 if (src_image
->type
== VK_IMAGE_TYPE_3D
) {
546 assert(src_res
->baseArrayLayer
== 0);
547 src_start
= pRegions
[r
].srcOffsets
[0].z
;
548 src_end
= pRegions
[r
].srcOffsets
[1].z
;
550 src_start
= src_res
->baseArrayLayer
;
551 src_end
= src_start
+ src_res
->layerCount
;
554 bool flip_z
= flip_coords(&src_start
, &src_end
, &dst_start
, &dst_end
);
555 float src_z_step
= (float)(src_end
+ 1 - src_start
) /
556 (float)(dst_end
+ 1 - dst_start
);
563 unsigned src_x0
= pRegions
[r
].srcOffsets
[0].x
;
564 unsigned src_x1
= pRegions
[r
].srcOffsets
[1].x
;
565 unsigned dst_x0
= pRegions
[r
].dstOffsets
[0].x
;
566 unsigned dst_x1
= pRegions
[r
].dstOffsets
[1].x
;
568 unsigned src_y0
= pRegions
[r
].srcOffsets
[0].y
;
569 unsigned src_y1
= pRegions
[r
].srcOffsets
[1].y
;
570 unsigned dst_y0
= pRegions
[r
].dstOffsets
[0].y
;
571 unsigned dst_y1
= pRegions
[r
].dstOffsets
[1].y
;
574 dest_box
.offset
.x
= MIN2(dst_x0
, dst_x1
);
575 dest_box
.offset
.y
= MIN2(dst_y0
, dst_y1
);
576 dest_box
.extent
.width
= abs(dst_x1
- dst_x0
);
577 dest_box
.extent
.height
= abs(dst_y1
- dst_y0
);
579 struct radv_image_view dest_iview
;
580 const unsigned num_layers
= dst_end
- dst_start
;
581 for (unsigned i
= 0; i
< num_layers
; i
++) {
582 const VkOffset3D dest_offset_0
= {
587 const VkOffset3D dest_offset_1
= {
592 VkOffset3D src_offset_0
= {
595 .z
= src_start
+ i
* src_z_step
,
597 VkOffset3D src_offset_1
= {
600 .z
= src_start
+ i
* src_z_step
,
602 const uint32_t dest_array_slice
=
603 radv_meta_get_iview_layer(dest_image
, dst_res
,
606 radv_image_view_init(&dest_iview
, cmd_buffer
->device
,
607 &(VkImageViewCreateInfo
) {
608 .sType
= VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO
,
610 .viewType
= radv_meta_get_view_type(dest_image
),
611 .format
= dest_image
->vk_format
,
612 .subresourceRange
= {
613 .aspectMask
= dst_res
->aspectMask
,
614 .baseMipLevel
= dst_res
->mipLevel
,
616 .baseArrayLayer
= dest_array_slice
,
620 meta_emit_blit(cmd_buffer
,
621 src_image
, &src_iview
,
622 src_offset_0
, src_offset_1
,
623 dest_image
, &dest_iview
,
624 dest_offset_0
, dest_offset_1
,
630 radv_meta_restore(&saved_state
, cmd_buffer
);
634 radv_device_finish_meta_blit_state(struct radv_device
*device
)
636 struct radv_meta_state
*state
= &device
->meta_state
;
638 for (unsigned i
= 0; i
< NUM_META_FS_KEYS
; ++i
) {
639 radv_DestroyRenderPass(radv_device_to_handle(device
),
640 state
->blit
.render_pass
[i
],
642 radv_DestroyPipeline(radv_device_to_handle(device
),
643 state
->blit
.pipeline_1d_src
[i
],
645 radv_DestroyPipeline(radv_device_to_handle(device
),
646 state
->blit
.pipeline_2d_src
[i
],
648 radv_DestroyPipeline(radv_device_to_handle(device
),
649 state
->blit
.pipeline_3d_src
[i
],
653 radv_DestroyRenderPass(radv_device_to_handle(device
),
654 state
->blit
.depth_only_rp
, &state
->alloc
);
655 radv_DestroyPipeline(radv_device_to_handle(device
),
656 state
->blit
.depth_only_1d_pipeline
, &state
->alloc
);
657 radv_DestroyPipeline(radv_device_to_handle(device
),
658 state
->blit
.depth_only_2d_pipeline
, &state
->alloc
);
659 radv_DestroyPipeline(radv_device_to_handle(device
),
660 state
->blit
.depth_only_3d_pipeline
, &state
->alloc
);
662 radv_DestroyRenderPass(radv_device_to_handle(device
),
663 state
->blit
.stencil_only_rp
, &state
->alloc
);
664 radv_DestroyPipeline(radv_device_to_handle(device
),
665 state
->blit
.stencil_only_1d_pipeline
,
667 radv_DestroyPipeline(radv_device_to_handle(device
),
668 state
->blit
.stencil_only_2d_pipeline
,
670 radv_DestroyPipeline(radv_device_to_handle(device
),
671 state
->blit
.stencil_only_3d_pipeline
,
674 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
675 state
->blit
.pipeline_layout
, &state
->alloc
);
676 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device
),
677 state
->blit
.ds_layout
, &state
->alloc
);
680 static VkFormat pipeline_formats
[] = {
681 VK_FORMAT_R8G8B8A8_UNORM
,
682 VK_FORMAT_R8G8B8A8_UINT
,
683 VK_FORMAT_R8G8B8A8_SINT
,
684 VK_FORMAT_A2R10G10B10_UINT_PACK32
,
685 VK_FORMAT_A2R10G10B10_SINT_PACK32
,
686 VK_FORMAT_R16G16B16A16_UNORM
,
687 VK_FORMAT_R16G16B16A16_SNORM
,
688 VK_FORMAT_R16G16B16A16_UINT
,
689 VK_FORMAT_R16G16B16A16_SINT
,
690 VK_FORMAT_R32_SFLOAT
,
691 VK_FORMAT_R32G32_SFLOAT
,
692 VK_FORMAT_R32G32B32A32_SFLOAT
696 radv_device_init_meta_blit_color(struct radv_device
*device
,
697 struct radv_shader_module
*vs
)
699 struct radv_shader_module fs_1d
= {0}, fs_2d
= {0}, fs_3d
= {0};
702 fs_1d
.nir
= build_nir_copy_fragment_shader(GLSL_SAMPLER_DIM_1D
);
703 fs_2d
.nir
= build_nir_copy_fragment_shader(GLSL_SAMPLER_DIM_2D
);
704 fs_3d
.nir
= build_nir_copy_fragment_shader(GLSL_SAMPLER_DIM_3D
);
706 for (unsigned i
= 0; i
< ARRAY_SIZE(pipeline_formats
); ++i
) {
707 unsigned key
= radv_format_meta_fs_key(pipeline_formats
[i
]);
708 result
= radv_CreateRenderPass(radv_device_to_handle(device
),
709 &(VkRenderPassCreateInfo
) {
710 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
711 .attachmentCount
= 1,
712 .pAttachments
= &(VkAttachmentDescription
) {
713 .format
= pipeline_formats
[i
],
714 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
715 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
716 .initialLayout
= VK_IMAGE_LAYOUT_GENERAL
,
717 .finalLayout
= VK_IMAGE_LAYOUT_GENERAL
,
720 .pSubpasses
= &(VkSubpassDescription
) {
721 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
722 .inputAttachmentCount
= 0,
723 .colorAttachmentCount
= 1,
724 .pColorAttachments
= &(VkAttachmentReference
) {
726 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
728 .pResolveAttachments
= NULL
,
729 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
730 .attachment
= VK_ATTACHMENT_UNUSED
,
731 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
733 .preserveAttachmentCount
= 1,
734 .pPreserveAttachments
= (uint32_t[]) { 0 },
736 .dependencyCount
= 0,
737 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit
.render_pass
[key
]);
738 if (result
!= VK_SUCCESS
)
741 VkPipelineVertexInputStateCreateInfo vi_create_info
= {
742 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO
,
743 .vertexBindingDescriptionCount
= 0,
744 .vertexAttributeDescriptionCount
= 0,
747 VkPipelineShaderStageCreateInfo pipeline_shader_stages
[] = {
749 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
750 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
751 .module
= radv_shader_module_to_handle(vs
),
753 .pSpecializationInfo
= NULL
755 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
756 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
757 .module
= VK_NULL_HANDLE
, /* TEMPLATE VALUE! FILL ME IN! */
759 .pSpecializationInfo
= NULL
763 const VkGraphicsPipelineCreateInfo vk_pipeline_info
= {
764 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
765 .stageCount
= ARRAY_SIZE(pipeline_shader_stages
),
766 .pStages
= pipeline_shader_stages
,
767 .pVertexInputState
= &vi_create_info
,
768 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
769 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
770 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
771 .primitiveRestartEnable
= false,
773 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
774 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
778 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
779 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
780 .rasterizerDiscardEnable
= false,
781 .polygonMode
= VK_POLYGON_MODE_FILL
,
782 .cullMode
= VK_CULL_MODE_NONE
,
783 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
785 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
786 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
787 .rasterizationSamples
= 1,
788 .sampleShadingEnable
= false,
789 .pSampleMask
= (VkSampleMask
[]) { UINT32_MAX
},
791 .pColorBlendState
= &(VkPipelineColorBlendStateCreateInfo
) {
792 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
793 .attachmentCount
= 1,
794 .pAttachments
= (VkPipelineColorBlendAttachmentState
[]) {
796 VK_COLOR_COMPONENT_A_BIT
|
797 VK_COLOR_COMPONENT_R_BIT
|
798 VK_COLOR_COMPONENT_G_BIT
|
799 VK_COLOR_COMPONENT_B_BIT
},
802 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
803 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
804 .dynamicStateCount
= 4,
805 .pDynamicStates
= (VkDynamicState
[]) {
806 VK_DYNAMIC_STATE_VIEWPORT
,
807 VK_DYNAMIC_STATE_SCISSOR
,
808 VK_DYNAMIC_STATE_LINE_WIDTH
,
809 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
813 .layout
= device
->meta_state
.blit
.pipeline_layout
,
814 .renderPass
= device
->meta_state
.blit
.render_pass
[key
],
818 const struct radv_graphics_pipeline_create_info radv_pipeline_info
= {
822 pipeline_shader_stages
[1].module
= radv_shader_module_to_handle(&fs_1d
);
823 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
824 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
825 &vk_pipeline_info
, &radv_pipeline_info
,
826 &device
->meta_state
.alloc
, &device
->meta_state
.blit
.pipeline_1d_src
[key
]);
827 if (result
!= VK_SUCCESS
)
830 pipeline_shader_stages
[1].module
= radv_shader_module_to_handle(&fs_2d
);
831 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
832 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
833 &vk_pipeline_info
, &radv_pipeline_info
,
834 &device
->meta_state
.alloc
, &device
->meta_state
.blit
.pipeline_2d_src
[key
]);
835 if (result
!= VK_SUCCESS
)
838 pipeline_shader_stages
[1].module
= radv_shader_module_to_handle(&fs_3d
);
839 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
840 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
841 &vk_pipeline_info
, &radv_pipeline_info
,
842 &device
->meta_state
.alloc
, &device
->meta_state
.blit
.pipeline_3d_src
[key
]);
843 if (result
!= VK_SUCCESS
)
850 ralloc_free(fs_1d
.nir
);
851 ralloc_free(fs_2d
.nir
);
852 ralloc_free(fs_3d
.nir
);
857 radv_device_init_meta_blit_depth(struct radv_device
*device
,
858 struct radv_shader_module
*vs
)
860 struct radv_shader_module fs_1d
= {0}, fs_2d
= {0}, fs_3d
= {0};
863 fs_1d
.nir
= build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_1D
);
864 fs_2d
.nir
= build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_2D
);
865 fs_3d
.nir
= build_nir_copy_fragment_shader_depth(GLSL_SAMPLER_DIM_3D
);
867 result
= radv_CreateRenderPass(radv_device_to_handle(device
),
868 &(VkRenderPassCreateInfo
) {
869 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
870 .attachmentCount
= 1,
871 .pAttachments
= &(VkAttachmentDescription
) {
872 .format
= VK_FORMAT_D32_SFLOAT
,
873 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
874 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
875 .initialLayout
= VK_IMAGE_LAYOUT_GENERAL
,
876 .finalLayout
= VK_IMAGE_LAYOUT_GENERAL
,
879 .pSubpasses
= &(VkSubpassDescription
) {
880 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
881 .inputAttachmentCount
= 0,
882 .colorAttachmentCount
= 0,
883 .pColorAttachments
= NULL
,
884 .pResolveAttachments
= NULL
,
885 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
887 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
889 .preserveAttachmentCount
= 1,
890 .pPreserveAttachments
= (uint32_t[]) { 0 },
892 .dependencyCount
= 0,
893 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit
.depth_only_rp
);
894 if (result
!= VK_SUCCESS
)
897 VkPipelineVertexInputStateCreateInfo vi_create_info
= {
898 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO
,
899 .vertexBindingDescriptionCount
= 0,
900 .vertexAttributeDescriptionCount
= 0,
903 VkPipelineShaderStageCreateInfo pipeline_shader_stages
[] = {
905 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
906 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
907 .module
= radv_shader_module_to_handle(vs
),
909 .pSpecializationInfo
= NULL
911 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
912 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
913 .module
= VK_NULL_HANDLE
, /* TEMPLATE VALUE! FILL ME IN! */
915 .pSpecializationInfo
= NULL
919 const VkGraphicsPipelineCreateInfo vk_pipeline_info
= {
920 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
921 .stageCount
= ARRAY_SIZE(pipeline_shader_stages
),
922 .pStages
= pipeline_shader_stages
,
923 .pVertexInputState
= &vi_create_info
,
924 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
925 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
926 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
927 .primitiveRestartEnable
= false,
929 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
930 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
934 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
935 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
936 .rasterizerDiscardEnable
= false,
937 .polygonMode
= VK_POLYGON_MODE_FILL
,
938 .cullMode
= VK_CULL_MODE_NONE
,
939 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
941 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
942 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
943 .rasterizationSamples
= 1,
944 .sampleShadingEnable
= false,
945 .pSampleMask
= (VkSampleMask
[]) { UINT32_MAX
},
947 .pColorBlendState
= &(VkPipelineColorBlendStateCreateInfo
) {
948 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
949 .attachmentCount
= 0,
950 .pAttachments
= NULL
,
952 .pDepthStencilState
= &(VkPipelineDepthStencilStateCreateInfo
) {
953 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
954 .depthTestEnable
= true,
955 .depthWriteEnable
= true,
956 .depthCompareOp
= VK_COMPARE_OP_ALWAYS
,
958 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
959 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
960 .dynamicStateCount
= 9,
961 .pDynamicStates
= (VkDynamicState
[]) {
962 VK_DYNAMIC_STATE_VIEWPORT
,
963 VK_DYNAMIC_STATE_SCISSOR
,
964 VK_DYNAMIC_STATE_LINE_WIDTH
,
965 VK_DYNAMIC_STATE_DEPTH_BIAS
,
966 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
967 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
968 VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
,
969 VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
,
970 VK_DYNAMIC_STATE_STENCIL_REFERENCE
,
974 .layout
= device
->meta_state
.blit
.pipeline_layout
,
975 .renderPass
= device
->meta_state
.blit
.depth_only_rp
,
979 const struct radv_graphics_pipeline_create_info radv_pipeline_info
= {
983 pipeline_shader_stages
[1].module
= radv_shader_module_to_handle(&fs_1d
);
984 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
985 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
986 &vk_pipeline_info
, &radv_pipeline_info
,
987 &device
->meta_state
.alloc
, &device
->meta_state
.blit
.depth_only_1d_pipeline
);
988 if (result
!= VK_SUCCESS
)
991 pipeline_shader_stages
[1].module
= radv_shader_module_to_handle(&fs_2d
);
992 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
993 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
994 &vk_pipeline_info
, &radv_pipeline_info
,
995 &device
->meta_state
.alloc
, &device
->meta_state
.blit
.depth_only_2d_pipeline
);
996 if (result
!= VK_SUCCESS
)
999 pipeline_shader_stages
[1].module
= radv_shader_module_to_handle(&fs_3d
);
1000 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
1001 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
1002 &vk_pipeline_info
, &radv_pipeline_info
,
1003 &device
->meta_state
.alloc
, &device
->meta_state
.blit
.depth_only_3d_pipeline
);
1004 if (result
!= VK_SUCCESS
)
1008 ralloc_free(fs_1d
.nir
);
1009 ralloc_free(fs_2d
.nir
);
1010 ralloc_free(fs_3d
.nir
);
1015 radv_device_init_meta_blit_stencil(struct radv_device
*device
,
1016 struct radv_shader_module
*vs
)
1018 struct radv_shader_module fs_1d
= {0}, fs_2d
= {0}, fs_3d
= {0};
1021 fs_1d
.nir
= build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_1D
);
1022 fs_2d
.nir
= build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_2D
);
1023 fs_3d
.nir
= build_nir_copy_fragment_shader_stencil(GLSL_SAMPLER_DIM_3D
);
1025 result
= radv_CreateRenderPass(radv_device_to_handle(device
),
1026 &(VkRenderPassCreateInfo
) {
1027 .sType
= VK_STRUCTURE_TYPE_RENDER_PASS_CREATE_INFO
,
1028 .attachmentCount
= 1,
1029 .pAttachments
= &(VkAttachmentDescription
) {
1030 .format
= VK_FORMAT_S8_UINT
,
1031 .loadOp
= VK_ATTACHMENT_LOAD_OP_LOAD
,
1032 .storeOp
= VK_ATTACHMENT_STORE_OP_STORE
,
1033 .initialLayout
= VK_IMAGE_LAYOUT_GENERAL
,
1034 .finalLayout
= VK_IMAGE_LAYOUT_GENERAL
,
1037 .pSubpasses
= &(VkSubpassDescription
) {
1038 .pipelineBindPoint
= VK_PIPELINE_BIND_POINT_GRAPHICS
,
1039 .inputAttachmentCount
= 0,
1040 .colorAttachmentCount
= 0,
1041 .pColorAttachments
= NULL
,
1042 .pResolveAttachments
= NULL
,
1043 .pDepthStencilAttachment
= &(VkAttachmentReference
) {
1045 .layout
= VK_IMAGE_LAYOUT_GENERAL
,
1047 .preserveAttachmentCount
= 1,
1048 .pPreserveAttachments
= (uint32_t[]) { 0 },
1050 .dependencyCount
= 0,
1051 }, &device
->meta_state
.alloc
, &device
->meta_state
.blit
.stencil_only_rp
);
1052 if (result
!= VK_SUCCESS
)
1055 VkPipelineVertexInputStateCreateInfo vi_create_info
= {
1056 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VERTEX_INPUT_STATE_CREATE_INFO
,
1057 .vertexBindingDescriptionCount
= 0,
1058 .vertexAttributeDescriptionCount
= 0,
1061 VkPipelineShaderStageCreateInfo pipeline_shader_stages
[] = {
1063 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
1064 .stage
= VK_SHADER_STAGE_VERTEX_BIT
,
1065 .module
= radv_shader_module_to_handle(vs
),
1067 .pSpecializationInfo
= NULL
1069 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
1070 .stage
= VK_SHADER_STAGE_FRAGMENT_BIT
,
1071 .module
= VK_NULL_HANDLE
, /* TEMPLATE VALUE! FILL ME IN! */
1073 .pSpecializationInfo
= NULL
1077 const VkGraphicsPipelineCreateInfo vk_pipeline_info
= {
1078 .sType
= VK_STRUCTURE_TYPE_GRAPHICS_PIPELINE_CREATE_INFO
,
1079 .stageCount
= ARRAY_SIZE(pipeline_shader_stages
),
1080 .pStages
= pipeline_shader_stages
,
1081 .pVertexInputState
= &vi_create_info
,
1082 .pInputAssemblyState
= &(VkPipelineInputAssemblyStateCreateInfo
) {
1083 .sType
= VK_STRUCTURE_TYPE_PIPELINE_INPUT_ASSEMBLY_STATE_CREATE_INFO
,
1084 .topology
= VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
,
1085 .primitiveRestartEnable
= false,
1087 .pViewportState
= &(VkPipelineViewportStateCreateInfo
) {
1088 .sType
= VK_STRUCTURE_TYPE_PIPELINE_VIEWPORT_STATE_CREATE_INFO
,
1092 .pRasterizationState
= &(VkPipelineRasterizationStateCreateInfo
) {
1093 .sType
= VK_STRUCTURE_TYPE_PIPELINE_RASTERIZATION_STATE_CREATE_INFO
,
1094 .rasterizerDiscardEnable
= false,
1095 .polygonMode
= VK_POLYGON_MODE_FILL
,
1096 .cullMode
= VK_CULL_MODE_NONE
,
1097 .frontFace
= VK_FRONT_FACE_COUNTER_CLOCKWISE
1099 .pMultisampleState
= &(VkPipelineMultisampleStateCreateInfo
) {
1100 .sType
= VK_STRUCTURE_TYPE_PIPELINE_MULTISAMPLE_STATE_CREATE_INFO
,
1101 .rasterizationSamples
= 1,
1102 .sampleShadingEnable
= false,
1103 .pSampleMask
= (VkSampleMask
[]) { UINT32_MAX
},
1105 .pColorBlendState
= &(VkPipelineColorBlendStateCreateInfo
) {
1106 .sType
= VK_STRUCTURE_TYPE_PIPELINE_COLOR_BLEND_STATE_CREATE_INFO
,
1107 .attachmentCount
= 0,
1108 .pAttachments
= NULL
,
1110 .pDepthStencilState
= &(VkPipelineDepthStencilStateCreateInfo
) {
1111 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DEPTH_STENCIL_STATE_CREATE_INFO
,
1112 .depthTestEnable
= false,
1113 .depthWriteEnable
= false,
1114 .stencilTestEnable
= true,
1116 .failOp
= VK_STENCIL_OP_REPLACE
,
1117 .passOp
= VK_STENCIL_OP_REPLACE
,
1118 .depthFailOp
= VK_STENCIL_OP_REPLACE
,
1119 .compareOp
= VK_COMPARE_OP_ALWAYS
,
1120 .compareMask
= 0xff,
1125 .failOp
= VK_STENCIL_OP_REPLACE
,
1126 .passOp
= VK_STENCIL_OP_REPLACE
,
1127 .depthFailOp
= VK_STENCIL_OP_REPLACE
,
1128 .compareOp
= VK_COMPARE_OP_ALWAYS
,
1129 .compareMask
= 0xff,
1133 .depthCompareOp
= VK_COMPARE_OP_ALWAYS
,
1136 .pDynamicState
= &(VkPipelineDynamicStateCreateInfo
) {
1137 .sType
= VK_STRUCTURE_TYPE_PIPELINE_DYNAMIC_STATE_CREATE_INFO
,
1138 .dynamicStateCount
= 6,
1139 .pDynamicStates
= (VkDynamicState
[]) {
1140 VK_DYNAMIC_STATE_VIEWPORT
,
1141 VK_DYNAMIC_STATE_SCISSOR
,
1142 VK_DYNAMIC_STATE_LINE_WIDTH
,
1143 VK_DYNAMIC_STATE_DEPTH_BIAS
,
1144 VK_DYNAMIC_STATE_BLEND_CONSTANTS
,
1145 VK_DYNAMIC_STATE_DEPTH_BOUNDS
,
1149 .layout
= device
->meta_state
.blit
.pipeline_layout
,
1150 .renderPass
= device
->meta_state
.blit
.stencil_only_rp
,
1154 const struct radv_graphics_pipeline_create_info radv_pipeline_info
= {
1155 .use_rectlist
= true
1158 pipeline_shader_stages
[1].module
= radv_shader_module_to_handle(&fs_1d
);
1159 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
1160 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
1161 &vk_pipeline_info
, &radv_pipeline_info
,
1162 &device
->meta_state
.alloc
, &device
->meta_state
.blit
.stencil_only_1d_pipeline
);
1163 if (result
!= VK_SUCCESS
)
1166 pipeline_shader_stages
[1].module
= radv_shader_module_to_handle(&fs_2d
);
1167 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
1168 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
1169 &vk_pipeline_info
, &radv_pipeline_info
,
1170 &device
->meta_state
.alloc
, &device
->meta_state
.blit
.stencil_only_2d_pipeline
);
1171 if (result
!= VK_SUCCESS
)
1174 pipeline_shader_stages
[1].module
= radv_shader_module_to_handle(&fs_3d
);
1175 result
= radv_graphics_pipeline_create(radv_device_to_handle(device
),
1176 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
1177 &vk_pipeline_info
, &radv_pipeline_info
,
1178 &device
->meta_state
.alloc
, &device
->meta_state
.blit
.stencil_only_3d_pipeline
);
1179 if (result
!= VK_SUCCESS
)
1183 ralloc_free(fs_1d
.nir
);
1184 ralloc_free(fs_2d
.nir
);
1185 ralloc_free(fs_3d
.nir
);
1190 radv_device_init_meta_blit_state(struct radv_device
*device
)
1193 struct radv_shader_module vs
= {0};
1195 VkDescriptorSetLayoutCreateInfo ds_layout_info
= {
1196 .sType
= VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO
,
1197 .flags
= VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
,
1199 .pBindings
= (VkDescriptorSetLayoutBinding
[]) {
1202 .descriptorType
= VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
,
1203 .descriptorCount
= 1,
1204 .stageFlags
= VK_SHADER_STAGE_FRAGMENT_BIT
,
1205 .pImmutableSamplers
= NULL
1209 result
= radv_CreateDescriptorSetLayout(radv_device_to_handle(device
),
1211 &device
->meta_state
.alloc
,
1212 &device
->meta_state
.blit
.ds_layout
);
1213 if (result
!= VK_SUCCESS
)
1216 const VkPushConstantRange push_constant_range
= {VK_SHADER_STAGE_VERTEX_BIT
, 0, 20};
1218 result
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
1219 &(VkPipelineLayoutCreateInfo
) {
1220 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
1221 .setLayoutCount
= 1,
1222 .pSetLayouts
= &device
->meta_state
.blit
.ds_layout
,
1223 .pushConstantRangeCount
= 1,
1224 .pPushConstantRanges
= &push_constant_range
,
1226 &device
->meta_state
.alloc
, &device
->meta_state
.blit
.pipeline_layout
);
1227 if (result
!= VK_SUCCESS
)
1230 vs
.nir
= build_nir_vertex_shader();
1232 result
= radv_device_init_meta_blit_color(device
, &vs
);
1233 if (result
!= VK_SUCCESS
)
1236 result
= radv_device_init_meta_blit_depth(device
, &vs
);
1237 if (result
!= VK_SUCCESS
)
1240 result
= radv_device_init_meta_blit_stencil(device
, &vs
);
1243 ralloc_free(vs
.nir
);
1244 if (result
!= VK_SUCCESS
)
1245 radv_device_finish_meta_blit_state(device
);