2 * Copyright © 2016 Dave Airlie
4 * Permission is hereby granted, free of charge, to any person obtaining a
5 * copy of this software and associated documentation files (the "Software"),
6 * to deal in the Software without restriction, including without limitation
7 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
8 * and/or sell copies of the Software, and to permit persons to whom the
9 * Software is furnished to do so, subject to the following conditions:
11 * The above copyright notice and this permission notice (including the next
12 * paragraph) shall be included in all copies or substantial portions of the
15 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
16 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
17 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
18 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
19 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
20 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_meta.h"
29 #include "radv_private.h"
30 #include "nir/nir_builder.h"
32 #include "vk_format.h"
34 static nir_ssa_def
*radv_meta_build_resolve_srgb_conversion(nir_builder
*b
,
40 for (i
= 0; i
< 3; i
++)
41 cmp
[i
] = nir_flt(b
, nir_channel(b
, input
, i
),
42 nir_imm_int(b
, 0x3b4d2e1c));
44 nir_ssa_def
*ltvals
[3];
45 for (i
= 0; i
< 3; i
++)
46 ltvals
[i
] = nir_fmul(b
, nir_channel(b
, input
, i
),
47 nir_imm_float(b
, 12.92));
49 nir_ssa_def
*gtvals
[3];
51 for (i
= 0; i
< 3; i
++) {
52 gtvals
[i
] = nir_fpow(b
, nir_channel(b
, input
, i
),
53 nir_imm_float(b
, 1.0/2.4));
54 gtvals
[i
] = nir_fmul(b
, gtvals
[i
],
55 nir_imm_float(b
, 1.055));
56 gtvals
[i
] = nir_fsub(b
, gtvals
[i
],
57 nir_imm_float(b
, 0.055));
61 for (i
= 0; i
< 3; i
++)
62 comp
[i
] = nir_bcsel(b
, cmp
[i
], ltvals
[i
], gtvals
[i
]);
63 comp
[3] = nir_channels(b
, input
, 1 << 3);
64 return nir_vec(b
, comp
, 4);
68 build_resolve_compute_shader(struct radv_device
*dev
, bool is_integer
, bool is_srgb
, int samples
)
72 const struct glsl_type
*sampler_type
= glsl_sampler_type(GLSL_SAMPLER_DIM_MS
,
76 const struct glsl_type
*img_type
= glsl_sampler_type(GLSL_SAMPLER_DIM_2D
,
80 snprintf(name
, 64, "meta_resolve_cs-%d-%s", samples
, is_integer
? "int" : (is_srgb
? "srgb" : "float"));
81 nir_builder_init_simple_shader(&b
, NULL
, MESA_SHADER_COMPUTE
, NULL
);
82 b
.shader
->info
.name
= ralloc_strdup(b
.shader
, name
);
83 b
.shader
->info
.cs
.local_size
[0] = 16;
84 b
.shader
->info
.cs
.local_size
[1] = 16;
85 b
.shader
->info
.cs
.local_size
[2] = 1;
87 nir_variable
*input_img
= nir_variable_create(b
.shader
, nir_var_uniform
,
88 sampler_type
, "s_tex");
89 input_img
->data
.descriptor_set
= 0;
90 input_img
->data
.binding
= 0;
92 nir_variable
*output_img
= nir_variable_create(b
.shader
, nir_var_uniform
,
94 output_img
->data
.descriptor_set
= 0;
95 output_img
->data
.binding
= 1;
96 nir_ssa_def
*invoc_id
= nir_load_local_invocation_id(&b
);
97 nir_ssa_def
*wg_id
= nir_load_work_group_id(&b
);
98 nir_ssa_def
*block_size
= nir_imm_ivec4(&b
,
99 b
.shader
->info
.cs
.local_size
[0],
100 b
.shader
->info
.cs
.local_size
[1],
101 b
.shader
->info
.cs
.local_size
[2], 0);
103 nir_ssa_def
*global_id
= nir_iadd(&b
, nir_imul(&b
, wg_id
, block_size
), invoc_id
);
105 nir_intrinsic_instr
*src_offset
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_push_constant
);
106 nir_intrinsic_set_base(src_offset
, 0);
107 nir_intrinsic_set_range(src_offset
, 16);
108 src_offset
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 0));
109 src_offset
->num_components
= 2;
110 nir_ssa_dest_init(&src_offset
->instr
, &src_offset
->dest
, 2, 32, "src_offset");
111 nir_builder_instr_insert(&b
, &src_offset
->instr
);
113 nir_intrinsic_instr
*dst_offset
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_load_push_constant
);
114 nir_intrinsic_set_base(dst_offset
, 0);
115 nir_intrinsic_set_range(dst_offset
, 16);
116 dst_offset
->src
[0] = nir_src_for_ssa(nir_imm_int(&b
, 8));
117 dst_offset
->num_components
= 2;
118 nir_ssa_dest_init(&dst_offset
->instr
, &dst_offset
->dest
, 2, 32, "dst_offset");
119 nir_builder_instr_insert(&b
, &dst_offset
->instr
);
121 nir_ssa_def
*img_coord
= nir_channels(&b
, nir_iadd(&b
, global_id
, &src_offset
->dest
.ssa
), 0x3);
122 nir_variable
*color
= nir_local_variable_create(b
.impl
, glsl_vec4_type(), "color");
124 radv_meta_build_resolve_shader_core(&b
, is_integer
, samples
, input_img
,
127 nir_ssa_def
*outval
= nir_load_var(&b
, color
);
129 outval
= radv_meta_build_resolve_srgb_conversion(&b
, outval
);
131 nir_ssa_def
*coord
= nir_iadd(&b
, global_id
, &dst_offset
->dest
.ssa
);
132 nir_intrinsic_instr
*store
= nir_intrinsic_instr_create(b
.shader
, nir_intrinsic_image_deref_store
);
133 store
->num_components
= 4;
134 store
->src
[0] = nir_src_for_ssa(&nir_build_deref_var(&b
, output_img
)->dest
.ssa
);
135 store
->src
[1] = nir_src_for_ssa(coord
);
136 store
->src
[2] = nir_src_for_ssa(nir_ssa_undef(&b
, 1, 32));
137 store
->src
[3] = nir_src_for_ssa(outval
);
138 nir_builder_instr_insert(&b
, &store
->instr
);
144 create_layout(struct radv_device
*device
)
148 * two descriptors one for the image being sampled
149 * one for the buffer being written.
151 VkDescriptorSetLayoutCreateInfo ds_create_info
= {
152 .sType
= VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO
,
153 .flags
= VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR
,
155 .pBindings
= (VkDescriptorSetLayoutBinding
[]) {
158 .descriptorType
= VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
,
159 .descriptorCount
= 1,
160 .stageFlags
= VK_SHADER_STAGE_COMPUTE_BIT
,
161 .pImmutableSamplers
= NULL
165 .descriptorType
= VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
,
166 .descriptorCount
= 1,
167 .stageFlags
= VK_SHADER_STAGE_COMPUTE_BIT
,
168 .pImmutableSamplers
= NULL
173 result
= radv_CreateDescriptorSetLayout(radv_device_to_handle(device
),
175 &device
->meta_state
.alloc
,
176 &device
->meta_state
.resolve_compute
.ds_layout
);
177 if (result
!= VK_SUCCESS
)
181 VkPipelineLayoutCreateInfo pl_create_info
= {
182 .sType
= VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO
,
184 .pSetLayouts
= &device
->meta_state
.resolve_compute
.ds_layout
,
185 .pushConstantRangeCount
= 1,
186 .pPushConstantRanges
= &(VkPushConstantRange
){VK_SHADER_STAGE_COMPUTE_BIT
, 0, 16},
189 result
= radv_CreatePipelineLayout(radv_device_to_handle(device
),
191 &device
->meta_state
.alloc
,
192 &device
->meta_state
.resolve_compute
.p_layout
);
193 if (result
!= VK_SUCCESS
)
201 create_resolve_pipeline(struct radv_device
*device
,
205 VkPipeline
*pipeline
)
208 struct radv_shader_module cs
= { .nir
= NULL
};
210 mtx_lock(&device
->meta_state
.mtx
);
212 mtx_unlock(&device
->meta_state
.mtx
);
216 cs
.nir
= build_resolve_compute_shader(device
, is_integer
, is_srgb
, samples
);
220 VkPipelineShaderStageCreateInfo pipeline_shader_stage
= {
221 .sType
= VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO
,
222 .stage
= VK_SHADER_STAGE_COMPUTE_BIT
,
223 .module
= radv_shader_module_to_handle(&cs
),
225 .pSpecializationInfo
= NULL
,
228 VkComputePipelineCreateInfo vk_pipeline_info
= {
229 .sType
= VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO
,
230 .stage
= pipeline_shader_stage
,
232 .layout
= device
->meta_state
.resolve_compute
.p_layout
,
235 result
= radv_CreateComputePipelines(radv_device_to_handle(device
),
236 radv_pipeline_cache_to_handle(&device
->meta_state
.cache
),
237 1, &vk_pipeline_info
, NULL
,
239 if (result
!= VK_SUCCESS
)
243 mtx_unlock(&device
->meta_state
.mtx
);
247 mtx_unlock(&device
->meta_state
.mtx
);
252 radv_device_init_meta_resolve_compute_state(struct radv_device
*device
, bool on_demand
)
254 struct radv_meta_state
*state
= &device
->meta_state
;
257 res
= create_layout(device
);
258 if (res
!= VK_SUCCESS
)
264 for (uint32_t i
= 0; i
< MAX_SAMPLES_LOG2
; ++i
) {
265 uint32_t samples
= 1 << i
;
267 res
= create_resolve_pipeline(device
, samples
, false, false,
268 &state
->resolve_compute
.rc
[i
].pipeline
);
269 if (res
!= VK_SUCCESS
)
272 res
= create_resolve_pipeline(device
, samples
, true, false,
273 &state
->resolve_compute
.rc
[i
].i_pipeline
);
274 if (res
!= VK_SUCCESS
)
277 res
= create_resolve_pipeline(device
, samples
, false, true,
278 &state
->resolve_compute
.rc
[i
].srgb_pipeline
);
279 if (res
!= VK_SUCCESS
)
286 radv_device_finish_meta_resolve_compute_state(device
);
291 radv_device_finish_meta_resolve_compute_state(struct radv_device
*device
)
293 struct radv_meta_state
*state
= &device
->meta_state
;
294 for (uint32_t i
= 0; i
< MAX_SAMPLES_LOG2
; ++i
) {
295 radv_DestroyPipeline(radv_device_to_handle(device
),
296 state
->resolve_compute
.rc
[i
].pipeline
,
299 radv_DestroyPipeline(radv_device_to_handle(device
),
300 state
->resolve_compute
.rc
[i
].i_pipeline
,
303 radv_DestroyPipeline(radv_device_to_handle(device
),
304 state
->resolve_compute
.rc
[i
].srgb_pipeline
,
308 radv_DestroyDescriptorSetLayout(radv_device_to_handle(device
),
309 state
->resolve_compute
.ds_layout
,
311 radv_DestroyPipelineLayout(radv_device_to_handle(device
),
312 state
->resolve_compute
.p_layout
,
317 radv_get_resolve_pipeline(struct radv_cmd_buffer
*cmd_buffer
,
318 struct radv_image_view
*src_iview
)
320 struct radv_device
*device
= cmd_buffer
->device
;
321 struct radv_meta_state
*state
= &device
->meta_state
;
322 uint32_t samples
= src_iview
->image
->info
.samples
;
323 uint32_t samples_log2
= ffs(samples
) - 1;
324 VkPipeline
*pipeline
;
326 if (vk_format_is_int(src_iview
->vk_format
))
327 pipeline
= &state
->resolve_compute
.rc
[samples_log2
].i_pipeline
;
328 else if (vk_format_is_srgb(src_iview
->vk_format
))
329 pipeline
= &state
->resolve_compute
.rc
[samples_log2
].srgb_pipeline
;
331 pipeline
= &state
->resolve_compute
.rc
[samples_log2
].pipeline
;
336 ret
= create_resolve_pipeline(device
, samples
,
337 vk_format_is_int(src_iview
->vk_format
),
338 vk_format_is_srgb(src_iview
->vk_format
),
340 if (ret
!= VK_SUCCESS
) {
341 cmd_buffer
->record_result
= ret
;
350 emit_resolve(struct radv_cmd_buffer
*cmd_buffer
,
351 struct radv_image_view
*src_iview
,
352 struct radv_image_view
*dest_iview
,
353 const VkOffset2D
*src_offset
,
354 const VkOffset2D
*dest_offset
,
355 const VkExtent2D
*resolve_extent
)
357 struct radv_device
*device
= cmd_buffer
->device
;
358 VkPipeline
*pipeline
;
360 radv_meta_push_descriptor_set(cmd_buffer
,
361 VK_PIPELINE_BIND_POINT_COMPUTE
,
362 device
->meta_state
.resolve_compute
.p_layout
,
364 2, /* descriptorWriteCount */
365 (VkWriteDescriptorSet
[]) {
367 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
369 .dstArrayElement
= 0,
370 .descriptorCount
= 1,
371 .descriptorType
= VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE
,
372 .pImageInfo
= (VkDescriptorImageInfo
[]) {
374 .sampler
= VK_NULL_HANDLE
,
375 .imageView
= radv_image_view_to_handle(src_iview
),
376 .imageLayout
= VK_IMAGE_LAYOUT_GENERAL
},
380 .sType
= VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET
,
382 .dstArrayElement
= 0,
383 .descriptorCount
= 1,
384 .descriptorType
= VK_DESCRIPTOR_TYPE_STORAGE_IMAGE
,
385 .pImageInfo
= (VkDescriptorImageInfo
[]) {
387 .sampler
= VK_NULL_HANDLE
,
388 .imageView
= radv_image_view_to_handle(dest_iview
),
389 .imageLayout
= VK_IMAGE_LAYOUT_GENERAL
,
395 pipeline
= radv_get_resolve_pipeline(cmd_buffer
, src_iview
);
397 radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer
),
398 VK_PIPELINE_BIND_POINT_COMPUTE
, *pipeline
);
400 unsigned push_constants
[4] = {
406 radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer
),
407 device
->meta_state
.resolve_compute
.p_layout
,
408 VK_SHADER_STAGE_COMPUTE_BIT
, 0, 16,
410 radv_unaligned_dispatch(cmd_buffer
, resolve_extent
->width
, resolve_extent
->height
, 1);
414 void radv_meta_resolve_compute_image(struct radv_cmd_buffer
*cmd_buffer
,
415 struct radv_image
*src_image
,
417 VkImageLayout src_image_layout
,
418 struct radv_image
*dest_image
,
419 VkFormat dest_format
,
420 VkImageLayout dest_image_layout
,
421 uint32_t region_count
,
422 const VkImageResolve
*regions
)
424 struct radv_meta_saved_state saved_state
;
426 radv_decompress_resolve_src(cmd_buffer
, src_image
, src_image_layout
,
427 region_count
, regions
);
429 radv_meta_save(&saved_state
, cmd_buffer
,
430 RADV_META_SAVE_COMPUTE_PIPELINE
|
431 RADV_META_SAVE_CONSTANTS
|
432 RADV_META_SAVE_DESCRIPTORS
);
434 for (uint32_t r
= 0; r
< region_count
; ++r
) {
435 const VkImageResolve
*region
= ®ions
[r
];
437 assert(region
->srcSubresource
.aspectMask
== VK_IMAGE_ASPECT_COLOR_BIT
);
438 assert(region
->dstSubresource
.aspectMask
== VK_IMAGE_ASPECT_COLOR_BIT
);
439 assert(region
->srcSubresource
.layerCount
== region
->dstSubresource
.layerCount
);
441 const uint32_t src_base_layer
=
442 radv_meta_get_iview_layer(src_image
, ®ion
->srcSubresource
,
445 const uint32_t dest_base_layer
=
446 radv_meta_get_iview_layer(dest_image
, ®ion
->dstSubresource
,
449 const struct VkExtent3D extent
=
450 radv_sanitize_image_extent(src_image
->type
, region
->extent
);
451 const struct VkOffset3D srcOffset
=
452 radv_sanitize_image_offset(src_image
->type
, region
->srcOffset
);
453 const struct VkOffset3D dstOffset
=
454 radv_sanitize_image_offset(dest_image
->type
, region
->dstOffset
);
456 for (uint32_t layer
= 0; layer
< region
->srcSubresource
.layerCount
;
459 struct radv_image_view src_iview
;
460 radv_image_view_init(&src_iview
, cmd_buffer
->device
,
461 &(VkImageViewCreateInfo
) {
462 .sType
= VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO
,
463 .image
= radv_image_to_handle(src_image
),
464 .viewType
= radv_meta_get_view_type(src_image
),
465 .format
= src_format
,
466 .subresourceRange
= {
467 .aspectMask
= VK_IMAGE_ASPECT_COLOR_BIT
,
468 .baseMipLevel
= region
->srcSubresource
.mipLevel
,
470 .baseArrayLayer
= src_base_layer
+ layer
,
475 struct radv_image_view dest_iview
;
476 radv_image_view_init(&dest_iview
, cmd_buffer
->device
,
477 &(VkImageViewCreateInfo
) {
478 .sType
= VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO
,
479 .image
= radv_image_to_handle(dest_image
),
480 .viewType
= radv_meta_get_view_type(dest_image
),
481 .format
= vk_to_non_srgb_format(dest_format
),
482 .subresourceRange
= {
483 .aspectMask
= VK_IMAGE_ASPECT_COLOR_BIT
,
484 .baseMipLevel
= region
->dstSubresource
.mipLevel
,
486 .baseArrayLayer
= dest_base_layer
+ layer
,
491 emit_resolve(cmd_buffer
,
494 &(VkOffset2D
) {srcOffset
.x
, srcOffset
.y
},
495 &(VkOffset2D
) {dstOffset
.x
, dstOffset
.y
},
496 &(VkExtent2D
) {extent
.width
, extent
.height
});
499 radv_meta_restore(&saved_state
, cmd_buffer
);
503 * Emit any needed resolves for the current subpass.
506 radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer
*cmd_buffer
)
508 struct radv_framebuffer
*fb
= cmd_buffer
->state
.framebuffer
;
509 const struct radv_subpass
*subpass
= cmd_buffer
->state
.subpass
;
510 struct radv_subpass_barrier barrier
;
512 /* Resolves happen before the end-of-subpass barriers get executed, so
513 * we have to make the attachment shader-readable.
515 barrier
.src_stage_mask
= VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT
;
516 barrier
.src_access_mask
= VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT
;
517 barrier
.dst_access_mask
= VK_ACCESS_INPUT_ATTACHMENT_READ_BIT
;
518 radv_subpass_barrier(cmd_buffer
, &barrier
);
520 for (uint32_t i
= 0; i
< subpass
->color_count
; ++i
) {
521 struct radv_subpass_attachment src_att
= subpass
->color_attachments
[i
];
522 struct radv_subpass_attachment dst_att
= subpass
->resolve_attachments
[i
];
523 struct radv_image_view
*src_iview
= fb
->attachments
[src_att
.attachment
].attachment
;
524 struct radv_image_view
*dst_iview
= fb
->attachments
[dst_att
.attachment
].attachment
;
526 if (dst_att
.attachment
== VK_ATTACHMENT_UNUSED
)
529 VkImageResolve region
= {
530 .extent
= (VkExtent3D
){ fb
->width
, fb
->height
, 0 },
531 .srcSubresource
= (VkImageSubresourceLayers
) {
532 .aspectMask
= VK_IMAGE_ASPECT_COLOR_BIT
,
533 .mipLevel
= src_iview
->base_mip
,
535 .layerCount
= src_iview
->image
->info
.array_size
537 .dstSubresource
= (VkImageSubresourceLayers
) {
538 .aspectMask
= VK_IMAGE_ASPECT_COLOR_BIT
,
539 .mipLevel
= dst_iview
->base_mip
,
541 .layerCount
= dst_iview
->image
->info
.array_size
543 .srcOffset
= (VkOffset3D
){ 0, 0, 0 },
544 .dstOffset
= (VkOffset3D
){ 0, 0, 0 },
547 radv_meta_resolve_compute_image(cmd_buffer
,
549 src_iview
->vk_format
,
552 dst_iview
->vk_format
,
557 cmd_buffer
->state
.flush_bits
|= RADV_CMD_FLAG_CS_PARTIAL_FLUSH
|
558 RADV_CMD_FLAG_INV_VMEM_L1
;