src/amd/vulkan/radv_meta_resolve_cs.c

   1 /*
   2  * Copyright © 2016 Dave Airlie
   3  *
   4  * Permission is hereby granted, free of charge, to any person obtaining a
   5  * copy of this software and associated documentation files (the "Software"),
   6  * to deal in the Software without restriction, including without limitation
   7  * the rights to use, copy, modify, merge, publish, distribute, sublicense,
   8  * and/or sell copies of the Software, and to permit persons to whom the
   9  * Software is furnished to do so, subject to the following conditions:
  10  *
  11  * The above copyright notice and this permission notice (including the next
  12  * paragraph) shall be included in all copies or substantial portions of the
  13  * Software.
  14  *
  15  * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
  16  * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
  17  * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT.  IN NO EVENT SHALL
  18  * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
  19  * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
  20  * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
  21  * IN THE SOFTWARE.
  22  */
  23
  24
  25 #include <assert.h>
  26 #include <stdbool.h>
  27
  28 #include "radv_meta.h"
  29 #include "radv_private.h"
  30 #include "nir/nir_builder.h"
  31 #include "sid.h"
  32 #include "vk_format.h"
  33
  34 static nir_ssa_def *radv_meta_build_resolve_srgb_conversion(nir_builder *b,
  35                                                             nir_ssa_def *input)
  36 {
  37         nir_const_value v;
  38         unsigned i;
  39         v.u32[0] = 0x3b4d2e1c; // 0.00313080009
  40
  41         nir_ssa_def *cmp[3];
  42         for (i = 0; i < 3; i++)
  43                 cmp[i] = nir_flt(b, nir_channel(b, input, i),
  44                                  nir_build_imm(b, 1, 32, v));
  45
  46         nir_ssa_def *ltvals[3];
  47         v.f32[0] = 12.92;
  48         for (i = 0; i < 3; i++)
  49                 ltvals[i] = nir_fmul(b, nir_channel(b, input, i),
  50                                      nir_build_imm(b, 1, 32, v));
  51
  52         nir_ssa_def *gtvals[3];
  53
  54         for (i = 0; i < 3; i++) {
  55                 v.f32[0] = 1.0/2.4;
  56                 gtvals[i] = nir_fpow(b, nir_channel(b, input, i),
  57                                      nir_build_imm(b, 1, 32, v));
  58                 v.f32[0] = 1.055;
  59                 gtvals[i] = nir_fmul(b, gtvals[i],
  60                                      nir_build_imm(b, 1, 32, v));
  61                 v.f32[0] = 0.055;
  62                 gtvals[i] = nir_fsub(b, gtvals[i],
  63                                      nir_build_imm(b, 1, 32, v));
  64         }
  65
  66         nir_ssa_def *comp[4];
  67         for (i = 0; i < 3; i++)
  68                 comp[i] = nir_bcsel(b, cmp[i], ltvals[i], gtvals[i]);
  69         comp[3] = nir_channels(b, input, 1 << 3);
  70         return nir_vec(b, comp, 4);
  71 }
  72
  73 static nir_shader *
  74 build_resolve_compute_shader(struct radv_device *dev, bool is_integer, bool is_srgb, int samples)
  75 {
  76         nir_builder b;
  77         char name[64];
  78         const struct glsl_type *sampler_type = glsl_sampler_type(GLSL_SAMPLER_DIM_MS,
  79                                                                  false,
  80                                                                  false,
  81                                                                  GLSL_TYPE_FLOAT);
  82         const struct glsl_type *img_type = glsl_sampler_type(GLSL_SAMPLER_DIM_2D,
  83                                                              false,
  84                                                              false,
  85                                                              GLSL_TYPE_FLOAT);
  86         snprintf(name, 64, "meta_resolve_cs-%d-%s", samples, is_integer ? "int" : (is_srgb ? "srgb" : "float"));
  87         nir_builder_init_simple_shader(&b, NULL, MESA_SHADER_COMPUTE, NULL);
  88         b.shader->info.name = ralloc_strdup(b.shader, name);
  89         b.shader->info.cs.local_size[0] = 16;
  90         b.shader->info.cs.local_size[1] = 16;
  91         b.shader->info.cs.local_size[2] = 1;
  92
  93         nir_variable *input_img = nir_variable_create(b.shader, nir_var_uniform,
  94                                                       sampler_type, "s_tex");
  95         input_img->data.descriptor_set = 0;
  96         input_img->data.binding = 0;
  97
  98         nir_variable *output_img = nir_variable_create(b.shader, nir_var_uniform,
  99                                                        img_type, "out_img");
 100         output_img->data.descriptor_set = 0;
 101         output_img->data.binding = 1;
 102         nir_ssa_def *invoc_id = nir_load_system_value(&b, nir_intrinsic_load_local_invocation_id, 0);
 103         nir_ssa_def *wg_id = nir_load_system_value(&b, nir_intrinsic_load_work_group_id, 0);
 104         nir_ssa_def *block_size = nir_imm_ivec4(&b,
 105                                                 b.shader->info.cs.local_size[0],
 106                                                 b.shader->info.cs.local_size[1],
 107                                                 b.shader->info.cs.local_size[2], 0);
 108
 109         nir_ssa_def *global_id = nir_iadd(&b, nir_imul(&b, wg_id, block_size), invoc_id);
 110
 111         nir_intrinsic_instr *src_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
 112         nir_intrinsic_set_base(src_offset, 0);
 113         nir_intrinsic_set_range(src_offset, 16);
 114         src_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 0));
 115         src_offset->num_components = 2;
 116         nir_ssa_dest_init(&src_offset->instr, &src_offset->dest, 2, 32, "src_offset");
 117         nir_builder_instr_insert(&b, &src_offset->instr);
 118
 119         nir_intrinsic_instr *dst_offset = nir_intrinsic_instr_create(b.shader, nir_intrinsic_load_push_constant);
 120         nir_intrinsic_set_base(dst_offset, 0);
 121         nir_intrinsic_set_range(dst_offset, 16);
 122         dst_offset->src[0] = nir_src_for_ssa(nir_imm_int(&b, 8));
 123         dst_offset->num_components = 2;
 124         nir_ssa_dest_init(&dst_offset->instr, &dst_offset->dest, 2, 32, "dst_offset");
 125         nir_builder_instr_insert(&b, &dst_offset->instr);
 126
 127         nir_ssa_def *img_coord = nir_channels(&b, nir_iadd(&b, global_id, &src_offset->dest.ssa), 0x3);
 128         nir_variable *color = nir_local_variable_create(b.impl, glsl_vec4_type(), "color");
 129
 130         radv_meta_build_resolve_shader_core(&b, is_integer, samples, input_img,
 131                                             color, img_coord);
 132
 133         nir_ssa_def *outval = nir_load_var(&b, color);
 134         if (is_srgb)
 135                 outval = radv_meta_build_resolve_srgb_conversion(&b, outval);
 136
 137         nir_ssa_def *coord = nir_iadd(&b, global_id, &dst_offset->dest.ssa);
 138         nir_intrinsic_instr *store = nir_intrinsic_instr_create(b.shader, nir_intrinsic_image_deref_store);
 139         store->num_components = 4;
 140         store->src[0] = nir_src_for_ssa(&nir_build_deref_var(&b, output_img)->dest.ssa);
 141         store->src[1] = nir_src_for_ssa(coord);
 142         store->src[2] = nir_src_for_ssa(nir_ssa_undef(&b, 1, 32));
 143         store->src[3] = nir_src_for_ssa(outval);
 144         nir_builder_instr_insert(&b, &store->instr);
 145         return b.shader;
 146 }
 147
 148
 149 static VkResult
 150 create_layout(struct radv_device *device)
 151 {
 152         VkResult result;
 153         /*
 154          * two descriptors one for the image being sampled
 155          * one for the buffer being written.
 156          */
 157         VkDescriptorSetLayoutCreateInfo ds_create_info = {
 158                 .sType = VK_STRUCTURE_TYPE_DESCRIPTOR_SET_LAYOUT_CREATE_INFO,
 159                 .flags = VK_DESCRIPTOR_SET_LAYOUT_CREATE_PUSH_DESCRIPTOR_BIT_KHR,
 160                 .bindingCount = 2,
 161                 .pBindings = (VkDescriptorSetLayoutBinding[]) {
 162                         {
 163                                 .binding = 0,
 164                                 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
 165                                 .descriptorCount = 1,
 166                                 .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
 167                                 .pImmutableSamplers = NULL
 168                         },
 169                         {
 170                                 .binding = 1,
 171                                 .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
 172                                 .descriptorCount = 1,
 173                                 .stageFlags = VK_SHADER_STAGE_COMPUTE_BIT,
 174                                 .pImmutableSamplers = NULL
 175                         },
 176                 }
 177         };
 178
 179         result = radv_CreateDescriptorSetLayout(radv_device_to_handle(device),
 180                                                 &ds_create_info,
 181                                                 &device->meta_state.alloc,
 182                                                 &device->meta_state.resolve_compute.ds_layout);
 183         if (result != VK_SUCCESS)
 184                 goto fail;
 185
 186
 187         VkPipelineLayoutCreateInfo pl_create_info = {
 188                 .sType = VK_STRUCTURE_TYPE_PIPELINE_LAYOUT_CREATE_INFO,
 189                 .setLayoutCount = 1,
 190                 .pSetLayouts = &device->meta_state.resolve_compute.ds_layout,
 191                 .pushConstantRangeCount = 1,
 192                 .pPushConstantRanges = &(VkPushConstantRange){VK_SHADER_STAGE_COMPUTE_BIT, 0, 16},
 193         };
 194
 195         result = radv_CreatePipelineLayout(radv_device_to_handle(device),
 196                                           &pl_create_info,
 197                                           &device->meta_state.alloc,
 198                                           &device->meta_state.resolve_compute.p_layout);
 199         if (result != VK_SUCCESS)
 200                 goto fail;
 201         return VK_SUCCESS;
 202 fail:
 203         return result;
 204 }
 205
 206 static VkResult
 207 create_resolve_pipeline(struct radv_device *device,
 208                         int samples,
 209                         bool is_integer,
 210                         bool is_srgb,
 211                         VkPipeline *pipeline)
 212 {
 213         VkResult result;
 214         struct radv_shader_module cs = { .nir = NULL };
 215
 216         mtx_lock(&device->meta_state.mtx);
 217         if (*pipeline) {
 218                 mtx_unlock(&device->meta_state.mtx);
 219                 return VK_SUCCESS;
 220         }
 221
 222         cs.nir = build_resolve_compute_shader(device, is_integer, is_srgb, samples);
 223
 224         /* compute shader */
 225
 226         VkPipelineShaderStageCreateInfo pipeline_shader_stage = {
 227                 .sType = VK_STRUCTURE_TYPE_PIPELINE_SHADER_STAGE_CREATE_INFO,
 228                 .stage = VK_SHADER_STAGE_COMPUTE_BIT,
 229                 .module = radv_shader_module_to_handle(&cs),
 230                 .pName = "main",
 231                 .pSpecializationInfo = NULL,
 232         };
 233
 234         VkComputePipelineCreateInfo vk_pipeline_info = {
 235                 .sType = VK_STRUCTURE_TYPE_COMPUTE_PIPELINE_CREATE_INFO,
 236                 .stage = pipeline_shader_stage,
 237                 .flags = 0,
 238                 .layout = device->meta_state.resolve_compute.p_layout,
 239         };
 240
 241         result = radv_CreateComputePipelines(radv_device_to_handle(device),
 242                                              radv_pipeline_cache_to_handle(&device->meta_state.cache),
 243                                              1, &vk_pipeline_info, NULL,
 244                                              pipeline);
 245         if (result != VK_SUCCESS)
 246                 goto fail;
 247
 248         ralloc_free(cs.nir);
 249         mtx_unlock(&device->meta_state.mtx);
 250         return VK_SUCCESS;
 251 fail:
 252         ralloc_free(cs.nir);
 253         mtx_unlock(&device->meta_state.mtx);
 254         return result;
 255 }
 256
 257 VkResult
 258 radv_device_init_meta_resolve_compute_state(struct radv_device *device, bool on_demand)
 259 {
 260         struct radv_meta_state *state = &device->meta_state;
 261         VkResult res;
 262
 263         res = create_layout(device);
 264         if (res != VK_SUCCESS)
 265                 goto fail;
 266
 267         if (on_demand)
 268                 return VK_SUCCESS;
 269
 270         for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
 271                 uint32_t samples = 1 << i;
 272
 273                 res = create_resolve_pipeline(device, samples, false, false,
 274                                               &state->resolve_compute.rc[i].pipeline);
 275                 if (res != VK_SUCCESS)
 276                         goto fail;
 277
 278                 res = create_resolve_pipeline(device, samples, true, false,
 279                                               &state->resolve_compute.rc[i].i_pipeline);
 280                 if (res != VK_SUCCESS)
 281                         goto fail;
 282
 283                 res = create_resolve_pipeline(device, samples, false, true,
 284                                               &state->resolve_compute.rc[i].srgb_pipeline);
 285                 if (res != VK_SUCCESS)
 286                         goto fail;
 287
 288         }
 289
 290         return VK_SUCCESS;
 291 fail:
 292         radv_device_finish_meta_resolve_compute_state(device);
 293         return res;
 294 }
 295
 296 void
 297 radv_device_finish_meta_resolve_compute_state(struct radv_device *device)
 298 {
 299         struct radv_meta_state *state = &device->meta_state;
 300         for (uint32_t i = 0; i < MAX_SAMPLES_LOG2; ++i) {
 301                 radv_DestroyPipeline(radv_device_to_handle(device),
 302                                      state->resolve_compute.rc[i].pipeline,
 303                                      &state->alloc);
 304
 305                 radv_DestroyPipeline(radv_device_to_handle(device),
 306                                      state->resolve_compute.rc[i].i_pipeline,
 307                                      &state->alloc);
 308
 309                 radv_DestroyPipeline(radv_device_to_handle(device),
 310                                      state->resolve_compute.rc[i].srgb_pipeline,
 311                                      &state->alloc);
 312         }
 313
 314         radv_DestroyDescriptorSetLayout(radv_device_to_handle(device),
 315                                         state->resolve_compute.ds_layout,
 316                                         &state->alloc);
 317         radv_DestroyPipelineLayout(radv_device_to_handle(device),
 318                                    state->resolve_compute.p_layout,
 319                                    &state->alloc);
 320 }
 321
 322 static void
 323 emit_resolve(struct radv_cmd_buffer *cmd_buffer,
 324              struct radv_image_view *src_iview,
 325              struct radv_image_view *dest_iview,
 326              const VkOffset2D *src_offset,
 327              const VkOffset2D *dest_offset,
 328              const VkExtent2D *resolve_extent)
 329 {
 330         struct radv_device *device = cmd_buffer->device;
 331         const uint32_t samples = src_iview->image->info.samples;
 332         const uint32_t samples_log2 = ffs(samples) - 1;
 333         radv_meta_push_descriptor_set(cmd_buffer,
 334                                       VK_PIPELINE_BIND_POINT_COMPUTE,
 335                                       device->meta_state.resolve_compute.p_layout,
 336                                       0, /* set */
 337                                       2, /* descriptorWriteCount */
 338                                       (VkWriteDescriptorSet[]) {
 339                                         {
 340                                                 .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
 341                                                 .dstBinding = 0,
 342                                                 .dstArrayElement = 0,
 343                                                 .descriptorCount = 1,
 344                                                 .descriptorType = VK_DESCRIPTOR_TYPE_SAMPLED_IMAGE,
 345                                               .pImageInfo = (VkDescriptorImageInfo[]) {
 346                                               {
 347                                               .sampler = VK_NULL_HANDLE,
 348                                               .imageView = radv_image_view_to_handle(src_iview),
 349                                               .imageLayout = VK_IMAGE_LAYOUT_GENERAL                                  },
 350                               }
 351                               },
 352                               {
 353                                       .sType = VK_STRUCTURE_TYPE_WRITE_DESCRIPTOR_SET,
 354                                       .dstBinding = 1,
 355                                       .dstArrayElement = 0,
 356                                       .descriptorCount = 1,
 357                                       .descriptorType = VK_DESCRIPTOR_TYPE_STORAGE_IMAGE,
 358                               .pImageInfo = (VkDescriptorImageInfo[]) {
 359                               {
 360                                       .sampler = VK_NULL_HANDLE,
 361                                      .imageView = radv_image_view_to_handle(dest_iview),
 362                                      .imageLayout = VK_IMAGE_LAYOUT_GENERAL,
 363                               },
 364                       }
 365                               }
 366                                       });
 367
 368         VkPipeline *pipeline;
 369         if (vk_format_is_int(src_iview->image->vk_format))
 370                 pipeline = &device->meta_state.resolve_compute.rc[samples_log2].i_pipeline;
 371         else if (vk_format_is_srgb(src_iview->image->vk_format))
 372                 pipeline = &device->meta_state.resolve_compute.rc[samples_log2].srgb_pipeline;
 373         else
 374                 pipeline = &device->meta_state.resolve_compute.rc[samples_log2].pipeline;
 375
 376         if (!*pipeline) {
 377                 VkResult ret = create_resolve_pipeline(device, samples,
 378                                                        vk_format_is_int(src_iview->image->vk_format),
 379                                                        vk_format_is_srgb(src_iview->image->vk_format),
 380                                                        pipeline);
 381                 if (ret != VK_SUCCESS) {
 382                         cmd_buffer->record_result = ret;
 383                         return;
 384                 }
 385         }
 386
 387         radv_CmdBindPipeline(radv_cmd_buffer_to_handle(cmd_buffer),
 388                              VK_PIPELINE_BIND_POINT_COMPUTE, *pipeline);
 389
 390         unsigned push_constants[4] = {
 391                 src_offset->x,
 392                 src_offset->y,
 393                 dest_offset->x,
 394                 dest_offset->y,
 395         };
 396         radv_CmdPushConstants(radv_cmd_buffer_to_handle(cmd_buffer),
 397                               device->meta_state.resolve_compute.p_layout,
 398                               VK_SHADER_STAGE_COMPUTE_BIT, 0, 16,
 399                               push_constants);
 400         radv_unaligned_dispatch(cmd_buffer, resolve_extent->width, resolve_extent->height, 1);
 401
 402 }
 403
 404 void radv_meta_resolve_compute_image(struct radv_cmd_buffer *cmd_buffer,
 405                                      struct radv_image *src_image,
 406                                      VkImageLayout src_image_layout,
 407                                      struct radv_image *dest_image,
 408                                      VkImageLayout dest_image_layout,
 409                                      uint32_t region_count,
 410                                      const VkImageResolve *regions)
 411 {
 412         struct radv_meta_saved_state saved_state;
 413
 414         radv_decompress_resolve_src(cmd_buffer, src_image, src_image_layout,
 415                                     region_count, regions);
 416
 417         radv_meta_save(&saved_state, cmd_buffer,
 418                        RADV_META_SAVE_COMPUTE_PIPELINE |
 419                        RADV_META_SAVE_CONSTANTS |
 420                        RADV_META_SAVE_DESCRIPTORS);
 421
 422         for (uint32_t r = 0; r < region_count; ++r) {
 423                 const VkImageResolve *region = &regions[r];
 424
 425                 assert(region->srcSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
 426                 assert(region->dstSubresource.aspectMask == VK_IMAGE_ASPECT_COLOR_BIT);
 427                 assert(region->srcSubresource.layerCount == region->dstSubresource.layerCount);
 428
 429                 const uint32_t src_base_layer =
 430                         radv_meta_get_iview_layer(src_image, &region->srcSubresource,
 431                                                   &region->srcOffset);
 432
 433                 const uint32_t dest_base_layer =
 434                         radv_meta_get_iview_layer(dest_image, &region->dstSubresource,
 435                                                   &region->dstOffset);
 436
 437                 const struct VkExtent3D extent =
 438                         radv_sanitize_image_extent(src_image->type, region->extent);
 439                 const struct VkOffset3D srcOffset =
 440                         radv_sanitize_image_offset(src_image->type, region->srcOffset);
 441                 const struct VkOffset3D dstOffset =
 442                         radv_sanitize_image_offset(dest_image->type, region->dstOffset);
 443
 444                 for (uint32_t layer = 0; layer < region->srcSubresource.layerCount;
 445                      ++layer) {
 446
 447                         struct radv_image_view src_iview;
 448                         radv_image_view_init(&src_iview, cmd_buffer->device,
 449                                              &(VkImageViewCreateInfo) {
 450                                                      .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
 451                                                              .image = radv_image_to_handle(src_image),
 452                                                              .viewType = radv_meta_get_view_type(src_image),
 453                                                              .format = src_image->vk_format,
 454                                                              .subresourceRange = {
 455                                                              .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
 456                                                              .baseMipLevel = region->srcSubresource.mipLevel,
 457                                                              .levelCount = 1,
 458                                                              .baseArrayLayer = src_base_layer + layer,
 459                                                              .layerCount = 1,
 460                                                      },
 461                                              });
 462
 463                         struct radv_image_view dest_iview;
 464                         radv_image_view_init(&dest_iview, cmd_buffer->device,
 465                                              &(VkImageViewCreateInfo) {
 466                                                      .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
 467                                                              .image = radv_image_to_handle(dest_image),
 468                                                              .viewType = radv_meta_get_view_type(dest_image),
 469                                                              .format = vk_to_non_srgb_format(dest_image->vk_format),
 470                                                              .subresourceRange = {
 471                                                              .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
 472                                                              .baseMipLevel = region->dstSubresource.mipLevel,
 473                                                              .levelCount = 1,
 474                                                              .baseArrayLayer = dest_base_layer + layer,
 475                                                              .layerCount = 1,
 476                                                      },
 477                                              });
 478
 479                         emit_resolve(cmd_buffer,
 480                                      &src_iview,
 481                                      &dest_iview,
 482                                      &(VkOffset2D) {srcOffset.x, srcOffset.y },
 483                                      &(VkOffset2D) {dstOffset.x, dstOffset.y },
 484                                      &(VkExtent2D) {extent.width, extent.height });
 485                 }
 486         }
 487         radv_meta_restore(&saved_state, cmd_buffer);
 488 }
 489
 490 /**
 491  * Emit any needed resolves for the current subpass.
 492  */
 493 void
 494 radv_cmd_buffer_resolve_subpass_cs(struct radv_cmd_buffer *cmd_buffer)
 495 {
 496         struct radv_framebuffer *fb = cmd_buffer->state.framebuffer;
 497         const struct radv_subpass *subpass = cmd_buffer->state.subpass;
 498         struct radv_meta_saved_state saved_state;
 499         struct radv_subpass_barrier barrier;
 500
 501         /* Resolves happen before the end-of-subpass barriers get executed, so
 502          * we have to make the attachment shader-readable.
 503          */
 504         barrier.src_stage_mask = VK_PIPELINE_STAGE_COLOR_ATTACHMENT_OUTPUT_BIT;
 505         barrier.src_access_mask = VK_ACCESS_COLOR_ATTACHMENT_WRITE_BIT;
 506         barrier.dst_access_mask = VK_ACCESS_INPUT_ATTACHMENT_READ_BIT;
 507         radv_subpass_barrier(cmd_buffer, &barrier);
 508
 509         radv_decompress_resolve_subpass_src(cmd_buffer);
 510
 511         radv_meta_save(&saved_state, cmd_buffer,
 512                        RADV_META_SAVE_COMPUTE_PIPELINE |
 513                        RADV_META_SAVE_CONSTANTS |
 514                        RADV_META_SAVE_DESCRIPTORS);
 515
 516         for (uint32_t i = 0; i < subpass->color_count; ++i) {
 517                 struct radv_subpass_attachment src_att = subpass->color_attachments[i];
 518                 struct radv_subpass_attachment dest_att = subpass->resolve_attachments[i];
 519                 struct radv_image_view *src_iview = cmd_buffer->state.framebuffer->attachments[src_att.attachment].attachment;
 520                 struct radv_image_view *dst_iview = cmd_buffer->state.framebuffer->attachments[dest_att.attachment].attachment;
 521                 if (dest_att.attachment == VK_ATTACHMENT_UNUSED)
 522                         continue;
 523
 524                 struct radv_image *src_image = src_iview->image;
 525                 struct radv_image *dst_image = dst_iview->image;
 526                 for (uint32_t layer = 0; layer < src_image->info.array_size; layer++) {
 527
 528                         struct radv_image_view tsrc_iview;
 529                         radv_image_view_init(&tsrc_iview, cmd_buffer->device,
 530                                              &(VkImageViewCreateInfo) {
 531                                                      .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
 532                                                              .image = radv_image_to_handle(src_image),
 533                                                              .viewType = radv_meta_get_view_type(src_image),
 534                                                              .format = src_image->vk_format,
 535                                                              .subresourceRange = {
 536                                                              .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
 537                                                              .baseMipLevel = src_iview->base_mip,
 538                                                              .levelCount = 1,
 539                                                              .baseArrayLayer = layer,
 540                                                              .layerCount = 1,
 541                                                      },
 542                                              });
 543
 544                         struct radv_image_view tdst_iview;
 545                         radv_image_view_init(&tdst_iview, cmd_buffer->device,
 546                                              &(VkImageViewCreateInfo) {
 547                                                      .sType = VK_STRUCTURE_TYPE_IMAGE_VIEW_CREATE_INFO,
 548                                                              .image = radv_image_to_handle(dst_image),
 549                                                              .viewType = radv_meta_get_view_type(dst_image),
 550                                                              .format = vk_to_non_srgb_format(dst_image->vk_format),
 551                                                              .subresourceRange = {
 552                                                              .aspectMask = VK_IMAGE_ASPECT_COLOR_BIT,
 553                                                              .baseMipLevel = dst_iview->base_mip,
 554                                                              .levelCount = 1,
 555                                                              .baseArrayLayer = layer,
 556                                                              .layerCount = 1,
 557                                                      },
 558                                              });
 559                         emit_resolve(cmd_buffer,
 560                                      &tsrc_iview,
 561                                      &tdst_iview,
 562                                      &(VkOffset2D) { 0, 0 },
 563                                      &(VkOffset2D) { 0, 0 },
 564                                      &(VkExtent2D) { fb->width, fb->height });
 565                 }
 566         }
 567
 568         cmd_buffer->state.flush_bits |= RADV_CMD_FLAG_CS_PARTIAL_FLUSH |
 569                                         RADV_CMD_FLAG_INV_VMEM_L1;
 570
 571         radv_meta_restore(&saved_state, cmd_buffer);
 572 }