2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "radv_shader_helper.h"
31 #include "radv_shader_args.h"
34 #include <llvm-c/Core.h>
35 #include <llvm-c/TargetMachine.h>
36 #include <llvm-c/Transforms/Scalar.h>
37 #include <llvm-c/Transforms/Utils.h>
40 #include "ac_binary.h"
41 #include "ac_llvm_util.h"
42 #include "ac_llvm_build.h"
43 #include "ac_shader_abi.h"
44 #include "ac_shader_util.h"
45 #include "ac_exp_param.h"
47 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
49 struct radv_shader_context
{
50 struct ac_llvm_context ac
;
51 const struct nir_shader
*shader
;
52 struct ac_shader_abi abi
;
53 const struct radv_shader_args
*args
;
55 gl_shader_stage stage
;
57 unsigned max_workgroup_size
;
58 LLVMContextRef context
;
59 LLVMValueRef main_function
;
61 LLVMValueRef descriptor_sets
[MAX_SETS
];
63 LLVMValueRef ring_offsets
;
65 LLVMValueRef rel_auto_id
;
67 LLVMValueRef gs_wave_id
;
68 LLVMValueRef gs_vtx_offset
[6];
70 LLVMValueRef esgs_ring
;
71 LLVMValueRef gsvs_ring
[4];
72 LLVMValueRef hs_ring_tess_offchip
;
73 LLVMValueRef hs_ring_tess_factor
;
75 LLVMValueRef inputs
[RADEON_LLVM_MAX_INPUTS
* 4];
79 LLVMValueRef gs_next_vertex
[4];
80 LLVMValueRef gs_curprim_verts
[4];
81 LLVMValueRef gs_generated_prims
[4];
82 LLVMValueRef gs_ngg_emit
;
83 LLVMValueRef gs_ngg_scratch
;
85 uint32_t tcs_num_inputs
;
86 uint32_t tcs_num_patches
;
88 LLVMValueRef vertexptr
; /* GFX10 only */
91 struct radv_shader_output_values
{
92 LLVMValueRef values
[4];
98 static inline struct radv_shader_context
*
99 radv_shader_context_from_abi(struct ac_shader_abi
*abi
)
101 struct radv_shader_context
*ctx
= NULL
;
102 return container_of(abi
, ctx
, abi
);
105 static LLVMValueRef
get_rel_patch_id(struct radv_shader_context
*ctx
)
107 switch (ctx
->stage
) {
108 case MESA_SHADER_TESS_CTRL
:
109 return ac_unpack_param(&ctx
->ac
,
110 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.tcs_rel_ids
),
112 case MESA_SHADER_TESS_EVAL
:
113 return ac_get_arg(&ctx
->ac
, ctx
->args
->tes_rel_patch_id
);
116 unreachable("Illegal stage");
121 get_tcs_num_patches(struct radv_shader_context
*ctx
)
123 unsigned num_tcs_input_cp
= ctx
->args
->options
->key
.tcs
.input_vertices
;
124 unsigned num_tcs_output_cp
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
125 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
126 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
127 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
128 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.patch_outputs_written
);
129 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
130 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
131 uint32_t output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
132 unsigned num_patches
;
133 unsigned hardware_lds_size
;
135 /* Ensure that we only need one wave per SIMD so we don't need to check
136 * resource usage. Also ensures that the number of tcs in and out
137 * vertices per threadgroup are at most 256.
139 num_patches
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
) * 4;
140 /* Make sure that the data fits in LDS. This assumes the shaders only
141 * use LDS for the inputs and outputs.
143 hardware_lds_size
= 32768;
145 /* Looks like STONEY hangs if we use more than 32 KiB LDS in a single
146 * threadgroup, even though there is more than 32 KiB LDS.
148 * Test: dEQP-VK.tessellation.shader_input_output.barrier
150 if (ctx
->args
->options
->chip_class
>= GFX7
&& ctx
->args
->options
->family
!= CHIP_STONEY
)
151 hardware_lds_size
= 65536;
153 num_patches
= MIN2(num_patches
, hardware_lds_size
/ (input_patch_size
+ output_patch_size
));
154 /* Make sure the output data fits in the offchip buffer */
155 num_patches
= MIN2(num_patches
, (ctx
->args
->options
->tess_offchip_block_dw_size
* 4) / output_patch_size
);
156 /* Not necessary for correctness, but improves performance. The
157 * specific value is taken from the proprietary driver.
159 num_patches
= MIN2(num_patches
, 40);
161 /* GFX6 bug workaround - limit LS-HS threadgroups to only one wave. */
162 if (ctx
->args
->options
->chip_class
== GFX6
) {
163 unsigned one_wave
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
);
164 num_patches
= MIN2(num_patches
, one_wave
);
170 calculate_tess_lds_size(struct radv_shader_context
*ctx
)
172 unsigned num_tcs_input_cp
= ctx
->args
->options
->key
.tcs
.input_vertices
;
173 unsigned num_tcs_output_cp
;
174 unsigned num_tcs_outputs
, num_tcs_patch_outputs
;
175 unsigned input_vertex_size
, output_vertex_size
;
176 unsigned input_patch_size
, output_patch_size
;
177 unsigned pervertex_output_patch_size
;
178 unsigned output_patch0_offset
;
179 unsigned num_patches
;
182 num_tcs_output_cp
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
183 num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
184 num_tcs_patch_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.patch_outputs_written
);
186 input_vertex_size
= ctx
->tcs_num_inputs
* 16;
187 output_vertex_size
= num_tcs_outputs
* 16;
189 input_patch_size
= num_tcs_input_cp
* input_vertex_size
;
191 pervertex_output_patch_size
= num_tcs_output_cp
* output_vertex_size
;
192 output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
194 num_patches
= ctx
->tcs_num_patches
;
195 output_patch0_offset
= input_patch_size
* num_patches
;
197 lds_size
= output_patch0_offset
+ output_patch_size
* num_patches
;
201 /* Tessellation shaders pass outputs to the next shader using LDS.
203 * LS outputs = TCS inputs
204 * TCS outputs = TES inputs
207 * - TCS inputs for patch 0
208 * - TCS inputs for patch 1
209 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
211 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
212 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
213 * - TCS outputs for patch 1
214 * - Per-patch TCS outputs for patch 1
215 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
216 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
219 * All three shaders VS(LS), TCS, TES share the same LDS space.
222 get_tcs_in_patch_stride(struct radv_shader_context
*ctx
)
224 assert(ctx
->stage
== MESA_SHADER_TESS_CTRL
);
225 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
226 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
228 input_patch_size
/= 4;
229 return LLVMConstInt(ctx
->ac
.i32
, input_patch_size
, false);
233 get_tcs_out_patch_stride(struct radv_shader_context
*ctx
)
235 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
236 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.patch_outputs_written
);
237 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
238 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
239 uint32_t output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
240 output_patch_size
/= 4;
241 return LLVMConstInt(ctx
->ac
.i32
, output_patch_size
, false);
245 get_tcs_out_vertex_stride(struct radv_shader_context
*ctx
)
247 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
248 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
249 output_vertex_size
/= 4;
250 return LLVMConstInt(ctx
->ac
.i32
, output_vertex_size
, false);
254 get_tcs_out_patch0_offset(struct radv_shader_context
*ctx
)
256 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
257 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
258 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
259 uint32_t output_patch0_offset
= input_patch_size
;
260 unsigned num_patches
= ctx
->tcs_num_patches
;
262 output_patch0_offset
*= num_patches
;
263 output_patch0_offset
/= 4;
264 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
268 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context
*ctx
)
270 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
271 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
272 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
273 uint32_t output_patch0_offset
= input_patch_size
;
275 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
276 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
277 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
278 unsigned num_patches
= ctx
->tcs_num_patches
;
280 output_patch0_offset
*= num_patches
;
281 output_patch0_offset
+= pervertex_output_patch_size
;
282 output_patch0_offset
/= 4;
283 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
287 get_tcs_in_current_patch_offset(struct radv_shader_context
*ctx
)
289 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
290 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
292 return LLVMBuildMul(ctx
->ac
.builder
, patch_stride
, rel_patch_id
, "");
296 get_tcs_out_current_patch_offset(struct radv_shader_context
*ctx
)
298 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
299 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
300 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
302 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
,
307 get_tcs_out_current_patch_data_offset(struct radv_shader_context
*ctx
)
309 LLVMValueRef patch0_patch_data_offset
=
310 get_tcs_out_patch0_patch_data_offset(ctx
);
311 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
312 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
314 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
,
315 patch0_patch_data_offset
);
319 create_llvm_function(struct ac_llvm_context
*ctx
, LLVMModuleRef module
,
320 LLVMBuilderRef builder
,
321 struct ac_shader_args
*args
,
322 enum ac_llvm_calling_convention convention
,
323 unsigned max_workgroup_size
,
324 const struct radv_nir_compiler_options
*options
)
326 LLVMValueRef main_function
=
327 ac_build_main(args
, ctx
, convention
, "main", ctx
->voidt
, module
);
329 if (options
->address32_hi
) {
330 ac_llvm_add_target_dep_function_attr(main_function
,
331 "amdgpu-32bit-address-high-bits",
332 options
->address32_hi
);
335 ac_llvm_set_workgroup_size(main_function
, max_workgroup_size
);
337 return main_function
;
342 set_loc(struct radv_userdata_info
*ud_info
, uint8_t *sgpr_idx
,
345 ud_info
->sgpr_idx
= *sgpr_idx
;
346 ud_info
->num_sgprs
= num_sgprs
;
347 *sgpr_idx
+= num_sgprs
;
351 set_loc_shader(struct radv_shader_args
*args
, int idx
, uint8_t *sgpr_idx
,
354 struct radv_userdata_info
*ud_info
=
355 &args
->shader_info
->user_sgprs_locs
.shader_data
[idx
];
358 set_loc(ud_info
, sgpr_idx
, num_sgprs
);
362 set_loc_shader_ptr(struct radv_shader_args
*args
, int idx
, uint8_t *sgpr_idx
)
364 bool use_32bit_pointers
= idx
!= AC_UD_SCRATCH_RING_OFFSETS
;
366 set_loc_shader(args
, idx
, sgpr_idx
, use_32bit_pointers
? 1 : 2);
370 set_loc_desc(struct radv_shader_args
*args
, int idx
, uint8_t *sgpr_idx
)
372 struct radv_userdata_locations
*locs
=
373 &args
->shader_info
->user_sgprs_locs
;
374 struct radv_userdata_info
*ud_info
= &locs
->descriptor_sets
[idx
];
377 set_loc(ud_info
, sgpr_idx
, 1);
379 locs
->descriptor_sets_enabled
|= 1 << idx
;
382 struct user_sgpr_info
{
383 bool need_ring_offsets
;
384 bool indirect_all_descriptor_sets
;
385 uint8_t remaining_sgprs
;
388 static bool needs_view_index_sgpr(struct radv_shader_args
*args
,
389 gl_shader_stage stage
)
392 case MESA_SHADER_VERTEX
:
393 if (args
->shader_info
->needs_multiview_view_index
||
394 (!args
->options
->key
.vs_common_out
.as_es
&& !args
->options
->key
.vs_common_out
.as_ls
&& args
->options
->key
.has_multiview_view_index
))
397 case MESA_SHADER_TESS_EVAL
:
398 if (args
->shader_info
->needs_multiview_view_index
|| (!args
->options
->key
.vs_common_out
.as_es
&& args
->options
->key
.has_multiview_view_index
))
401 case MESA_SHADER_GEOMETRY
:
402 case MESA_SHADER_TESS_CTRL
:
403 if (args
->shader_info
->needs_multiview_view_index
)
413 count_vs_user_sgprs(struct radv_shader_args
*args
)
417 if (args
->shader_info
->vs
.has_vertex_buffers
)
419 count
+= args
->shader_info
->vs
.needs_draw_id
? 3 : 2;
424 static void allocate_inline_push_consts(struct radv_shader_args
*args
,
425 struct user_sgpr_info
*user_sgpr_info
)
427 uint8_t remaining_sgprs
= user_sgpr_info
->remaining_sgprs
;
429 /* Only supported if shaders use push constants. */
430 if (args
->shader_info
->min_push_constant_used
== UINT8_MAX
)
433 /* Only supported if shaders don't have indirect push constants. */
434 if (args
->shader_info
->has_indirect_push_constants
)
437 /* Only supported for 32-bit push constants. */
438 if (!args
->shader_info
->has_only_32bit_push_constants
)
441 uint8_t num_push_consts
=
442 (args
->shader_info
->max_push_constant_used
-
443 args
->shader_info
->min_push_constant_used
) / 4;
445 /* Check if the number of user SGPRs is large enough. */
446 if (num_push_consts
< remaining_sgprs
) {
447 args
->shader_info
->num_inline_push_consts
= num_push_consts
;
449 args
->shader_info
->num_inline_push_consts
= remaining_sgprs
;
452 /* Clamp to the maximum number of allowed inlined push constants. */
453 if (args
->shader_info
->num_inline_push_consts
> AC_MAX_INLINE_PUSH_CONSTS
)
454 args
->shader_info
->num_inline_push_consts
= AC_MAX_INLINE_PUSH_CONSTS
;
456 if (args
->shader_info
->num_inline_push_consts
== num_push_consts
&&
457 !args
->shader_info
->loads_dynamic_offsets
) {
458 /* Disable the default push constants path if all constants are
459 * inlined and if shaders don't use dynamic descriptors.
461 args
->shader_info
->loads_push_constants
= false;
464 args
->shader_info
->base_inline_push_consts
=
465 args
->shader_info
->min_push_constant_used
/ 4;
468 static void allocate_user_sgprs(struct radv_shader_args
*args
,
469 gl_shader_stage stage
,
470 bool has_previous_stage
,
471 gl_shader_stage previous_stage
,
472 bool needs_view_index
,
473 struct user_sgpr_info
*user_sgpr_info
)
475 uint8_t user_sgpr_count
= 0;
477 memset(user_sgpr_info
, 0, sizeof(struct user_sgpr_info
));
479 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
480 if (stage
== MESA_SHADER_GEOMETRY
||
481 stage
== MESA_SHADER_VERTEX
||
482 stage
== MESA_SHADER_TESS_CTRL
||
483 stage
== MESA_SHADER_TESS_EVAL
||
484 args
->is_gs_copy_shader
)
485 user_sgpr_info
->need_ring_offsets
= true;
487 if (stage
== MESA_SHADER_FRAGMENT
&&
488 args
->shader_info
->ps
.needs_sample_positions
)
489 user_sgpr_info
->need_ring_offsets
= true;
491 /* 2 user sgprs will nearly always be allocated for scratch/rings */
492 if (args
->options
->supports_spill
|| user_sgpr_info
->need_ring_offsets
) {
493 user_sgpr_count
+= 2;
497 case MESA_SHADER_COMPUTE
:
498 if (args
->shader_info
->cs
.uses_grid_size
)
499 user_sgpr_count
+= 3;
501 case MESA_SHADER_FRAGMENT
:
502 user_sgpr_count
+= args
->shader_info
->ps
.needs_sample_positions
;
504 case MESA_SHADER_VERTEX
:
505 if (!args
->is_gs_copy_shader
)
506 user_sgpr_count
+= count_vs_user_sgprs(args
);
508 case MESA_SHADER_TESS_CTRL
:
509 if (has_previous_stage
) {
510 if (previous_stage
== MESA_SHADER_VERTEX
)
511 user_sgpr_count
+= count_vs_user_sgprs(args
);
514 case MESA_SHADER_TESS_EVAL
:
516 case MESA_SHADER_GEOMETRY
:
517 if (has_previous_stage
) {
518 if (previous_stage
== MESA_SHADER_VERTEX
) {
519 user_sgpr_count
+= count_vs_user_sgprs(args
);
527 if (needs_view_index
)
530 if (args
->shader_info
->loads_push_constants
)
533 if (args
->shader_info
->so
.num_outputs
)
536 uint32_t available_sgprs
= args
->options
->chip_class
>= GFX9
&& stage
!= MESA_SHADER_COMPUTE
? 32 : 16;
537 uint32_t remaining_sgprs
= available_sgprs
- user_sgpr_count
;
538 uint32_t num_desc_set
=
539 util_bitcount(args
->shader_info
->desc_set_used_mask
);
541 if (remaining_sgprs
< num_desc_set
) {
542 user_sgpr_info
->indirect_all_descriptor_sets
= true;
543 user_sgpr_info
->remaining_sgprs
= remaining_sgprs
- 1;
545 user_sgpr_info
->remaining_sgprs
= remaining_sgprs
- num_desc_set
;
548 allocate_inline_push_consts(args
, user_sgpr_info
);
552 declare_global_input_sgprs(struct radv_shader_args
*args
,
553 const struct user_sgpr_info
*user_sgpr_info
)
555 /* 1 for each descriptor set */
556 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
557 uint32_t mask
= args
->shader_info
->desc_set_used_mask
;
560 int i
= u_bit_scan(&mask
);
562 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_CONST_PTR
,
563 &args
->descriptor_sets
[i
]);
566 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_CONST_PTR_PTR
,
567 &args
->descriptor_sets
[0]);
570 if (args
->shader_info
->loads_push_constants
) {
571 /* 1 for push constants and dynamic descriptors */
572 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_CONST_PTR
,
573 &args
->ac
.push_constants
);
576 for (unsigned i
= 0; i
< args
->shader_info
->num_inline_push_consts
; i
++) {
577 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
,
578 &args
->ac
.inline_push_consts
[i
]);
580 args
->ac
.num_inline_push_consts
= args
->shader_info
->num_inline_push_consts
;
581 args
->ac
.base_inline_push_consts
= args
->shader_info
->base_inline_push_consts
;
583 if (args
->shader_info
->so
.num_outputs
) {
584 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_CONST_DESC_PTR
,
585 &args
->streamout_buffers
);
590 declare_vs_specific_input_sgprs(struct radv_shader_args
*args
,
591 gl_shader_stage stage
,
592 bool has_previous_stage
,
593 gl_shader_stage previous_stage
)
595 if (!args
->is_gs_copy_shader
&&
596 (stage
== MESA_SHADER_VERTEX
||
597 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
598 if (args
->shader_info
->vs
.has_vertex_buffers
) {
599 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_CONST_DESC_PTR
,
600 &args
->vertex_buffers
);
602 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
, &args
->ac
.base_vertex
);
603 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
, &args
->ac
.start_instance
);
604 if (args
->shader_info
->vs
.needs_draw_id
) {
605 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
, &args
->ac
.draw_id
);
611 declare_vs_input_vgprs(struct radv_shader_args
*args
)
613 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
, &args
->ac
.vertex_id
);
614 if (!args
->is_gs_copy_shader
) {
615 if (args
->options
->key
.vs_common_out
.as_ls
) {
616 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
, &args
->rel_auto_id
);
617 if (args
->options
->chip_class
>= GFX10
) {
618 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
, NULL
); /* user vgpr */
619 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
, &args
->ac
.instance_id
);
621 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
, &args
->ac
.instance_id
);
622 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
, NULL
); /* unused */
625 if (args
->options
->chip_class
>= GFX10
) {
626 if (args
->options
->key
.vs_common_out
.as_ngg
) {
627 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
, NULL
); /* user vgpr */
628 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
, NULL
); /* user vgpr */
629 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
, &args
->ac
.instance_id
);
631 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
, NULL
); /* unused */
632 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
, &args
->vs_prim_id
);
633 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
, &args
->ac
.instance_id
);
636 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
, &args
->ac
.instance_id
);
637 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
, &args
->vs_prim_id
);
638 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
, NULL
); /* unused */
645 declare_streamout_sgprs(struct radv_shader_args
*args
, gl_shader_stage stage
)
649 if (args
->options
->use_ngg_streamout
) {
650 if (stage
== MESA_SHADER_TESS_EVAL
)
651 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
, NULL
);
655 /* Streamout SGPRs. */
656 if (args
->shader_info
->so
.num_outputs
) {
657 assert(stage
== MESA_SHADER_VERTEX
||
658 stage
== MESA_SHADER_TESS_EVAL
);
660 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
, &args
->streamout_config
);
661 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
, &args
->streamout_write_idx
);
662 } else if (stage
== MESA_SHADER_TESS_EVAL
) {
663 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
, NULL
);
666 /* A streamout buffer offset is loaded if the stride is non-zero. */
667 for (i
= 0; i
< 4; i
++) {
668 if (!args
->shader_info
->so
.strides
[i
])
671 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
, &args
->streamout_offset
[i
]);
676 declare_tes_input_vgprs(struct radv_shader_args
*args
)
678 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_FLOAT
, &args
->tes_u
);
679 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_FLOAT
, &args
->tes_v
);
680 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
, &args
->tes_rel_patch_id
);
681 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
, &args
->ac
.tes_patch_id
);
685 set_global_input_locs(struct radv_shader_args
*args
,
686 const struct user_sgpr_info
*user_sgpr_info
,
687 uint8_t *user_sgpr_idx
)
689 uint32_t mask
= args
->shader_info
->desc_set_used_mask
;
691 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
693 int i
= u_bit_scan(&mask
);
695 set_loc_desc(args
, i
, user_sgpr_idx
);
698 set_loc_shader_ptr(args
, AC_UD_INDIRECT_DESCRIPTOR_SETS
,
701 args
->shader_info
->need_indirect_descriptor_sets
= true;
704 if (args
->shader_info
->loads_push_constants
) {
705 set_loc_shader_ptr(args
, AC_UD_PUSH_CONSTANTS
, user_sgpr_idx
);
708 if (args
->shader_info
->num_inline_push_consts
) {
709 set_loc_shader(args
, AC_UD_INLINE_PUSH_CONSTANTS
, user_sgpr_idx
,
710 args
->shader_info
->num_inline_push_consts
);
713 if (args
->streamout_buffers
.used
) {
714 set_loc_shader_ptr(args
, AC_UD_STREAMOUT_BUFFERS
,
720 load_descriptor_sets(struct radv_shader_context
*ctx
)
722 uint32_t mask
= ctx
->args
->shader_info
->desc_set_used_mask
;
723 if (ctx
->args
->shader_info
->need_indirect_descriptor_sets
) {
724 LLVMValueRef desc_sets
=
725 ac_get_arg(&ctx
->ac
, ctx
->args
->descriptor_sets
[0]);
727 int i
= u_bit_scan(&mask
);
729 ctx
->descriptor_sets
[i
] =
730 ac_build_load_to_sgpr(&ctx
->ac
, desc_sets
,
731 LLVMConstInt(ctx
->ac
.i32
, i
, false));
736 int i
= u_bit_scan(&mask
);
738 ctx
->descriptor_sets
[i
] =
739 ac_get_arg(&ctx
->ac
, ctx
->args
->descriptor_sets
[i
]);
746 set_vs_specific_input_locs(struct radv_shader_args
*args
,
747 gl_shader_stage stage
, bool has_previous_stage
,
748 gl_shader_stage previous_stage
,
749 uint8_t *user_sgpr_idx
)
751 if (!args
->is_gs_copy_shader
&&
752 (stage
== MESA_SHADER_VERTEX
||
753 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
754 if (args
->shader_info
->vs
.has_vertex_buffers
) {
755 set_loc_shader_ptr(args
, AC_UD_VS_VERTEX_BUFFERS
,
760 if (args
->shader_info
->vs
.needs_draw_id
)
763 set_loc_shader(args
, AC_UD_VS_BASE_VERTEX_START_INSTANCE
,
764 user_sgpr_idx
, vs_num
);
768 static enum ac_llvm_calling_convention
769 get_llvm_calling_convention(LLVMValueRef func
, gl_shader_stage stage
)
772 case MESA_SHADER_VERTEX
:
773 case MESA_SHADER_TESS_EVAL
:
774 return AC_LLVM_AMDGPU_VS
;
776 case MESA_SHADER_GEOMETRY
:
777 return AC_LLVM_AMDGPU_GS
;
779 case MESA_SHADER_TESS_CTRL
:
780 return AC_LLVM_AMDGPU_HS
;
782 case MESA_SHADER_FRAGMENT
:
783 return AC_LLVM_AMDGPU_PS
;
785 case MESA_SHADER_COMPUTE
:
786 return AC_LLVM_AMDGPU_CS
;
789 unreachable("Unhandle shader type");
793 /* Returns whether the stage is a stage that can be directly before the GS */
794 static bool is_pre_gs_stage(gl_shader_stage stage
)
796 return stage
== MESA_SHADER_VERTEX
|| stage
== MESA_SHADER_TESS_EVAL
;
799 static void declare_inputs(struct radv_shader_args
*args
,
800 gl_shader_stage stage
,
801 bool has_previous_stage
,
802 gl_shader_stage previous_stage
)
804 struct user_sgpr_info user_sgpr_info
;
805 bool needs_view_index
= needs_view_index_sgpr(args
, stage
);
807 if (args
->options
->chip_class
>= GFX10
) {
808 if (is_pre_gs_stage(stage
) && args
->options
->key
.vs_common_out
.as_ngg
) {
809 /* On GFX10, VS is merged into GS for NGG. */
810 previous_stage
= stage
;
811 stage
= MESA_SHADER_GEOMETRY
;
812 has_previous_stage
= true;
816 for (int i
= 0; i
< MAX_SETS
; i
++)
817 args
->shader_info
->user_sgprs_locs
.descriptor_sets
[i
].sgpr_idx
= -1;
818 for (int i
= 0; i
< AC_UD_MAX_UD
; i
++)
819 args
->shader_info
->user_sgprs_locs
.shader_data
[i
].sgpr_idx
= -1;
822 allocate_user_sgprs(args
, stage
, has_previous_stage
,
823 previous_stage
, needs_view_index
, &user_sgpr_info
);
825 if (user_sgpr_info
.need_ring_offsets
&& !args
->options
->supports_spill
) {
826 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 2, AC_ARG_CONST_DESC_PTR
,
827 &args
->ring_offsets
);
831 case MESA_SHADER_COMPUTE
:
832 declare_global_input_sgprs(args
, &user_sgpr_info
);
834 if (args
->shader_info
->cs
.uses_grid_size
) {
835 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 3, AC_ARG_INT
,
836 &args
->ac
.num_work_groups
);
839 for (int i
= 0; i
< 3; i
++) {
840 if (args
->shader_info
->cs
.uses_block_id
[i
]) {
841 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
,
842 &args
->ac
.workgroup_ids
[i
]);
846 if (args
->shader_info
->cs
.uses_local_invocation_idx
) {
847 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
,
851 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 3, AC_ARG_INT
,
852 &args
->ac
.local_invocation_ids
);
854 case MESA_SHADER_VERTEX
:
855 declare_global_input_sgprs(args
, &user_sgpr_info
);
857 declare_vs_specific_input_sgprs(args
, stage
, has_previous_stage
,
860 if (needs_view_index
) {
861 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
,
862 &args
->ac
.view_index
);
865 if (args
->options
->key
.vs_common_out
.as_es
) {
866 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
,
867 &args
->es2gs_offset
);
868 } else if (args
->options
->key
.vs_common_out
.as_ls
) {
869 /* no extra parameters */
871 declare_streamout_sgprs(args
, stage
);
874 declare_vs_input_vgprs(args
);
876 case MESA_SHADER_TESS_CTRL
:
877 if (has_previous_stage
) {
878 // First 6 system regs
879 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
, &args
->oc_lds
);
880 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
,
881 &args
->merged_wave_info
);
882 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
,
883 &args
->tess_factor_offset
);
885 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
, NULL
); // scratch offset
886 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
, NULL
); // unknown
887 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
, NULL
); // unknown
889 declare_global_input_sgprs(args
, &user_sgpr_info
);
891 declare_vs_specific_input_sgprs(args
, stage
,
895 if (needs_view_index
) {
896 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
,
897 &args
->ac
.view_index
);
900 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
,
901 &args
->ac
.tcs_patch_id
);
902 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
,
903 &args
->ac
.tcs_rel_ids
);
905 declare_vs_input_vgprs(args
);
907 declare_global_input_sgprs(args
, &user_sgpr_info
);
909 if (needs_view_index
) {
910 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
,
911 &args
->ac
.view_index
);
914 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
, &args
->oc_lds
);
915 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
,
916 &args
->tess_factor_offset
);
917 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
,
918 &args
->ac
.tcs_patch_id
);
919 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
,
920 &args
->ac
.tcs_rel_ids
);
923 case MESA_SHADER_TESS_EVAL
:
924 declare_global_input_sgprs(args
, &user_sgpr_info
);
926 if (needs_view_index
)
927 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
,
928 &args
->ac
.view_index
);
930 if (args
->options
->key
.vs_common_out
.as_es
) {
931 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
, &args
->oc_lds
);
932 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
, NULL
);
933 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
,
934 &args
->es2gs_offset
);
936 declare_streamout_sgprs(args
, stage
);
937 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
, &args
->oc_lds
);
939 declare_tes_input_vgprs(args
);
941 case MESA_SHADER_GEOMETRY
:
942 if (has_previous_stage
) {
943 // First 6 system regs
944 if (args
->options
->key
.vs_common_out
.as_ngg
) {
945 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
,
948 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
,
949 &args
->gs2vs_offset
);
952 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
,
953 &args
->merged_wave_info
);
954 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
, &args
->oc_lds
);
956 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
, NULL
); // scratch offset
957 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
, NULL
); // unknown
958 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
, NULL
); // unknown
960 declare_global_input_sgprs(args
, &user_sgpr_info
);
962 if (previous_stage
!= MESA_SHADER_TESS_EVAL
) {
963 declare_vs_specific_input_sgprs(args
, stage
,
968 if (needs_view_index
) {
969 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
,
970 &args
->ac
.view_index
);
973 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
,
974 &args
->gs_vtx_offset
[0]);
975 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
,
976 &args
->gs_vtx_offset
[2]);
977 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
,
978 &args
->ac
.gs_prim_id
);
979 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
,
980 &args
->ac
.gs_invocation_id
);
981 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
,
982 &args
->gs_vtx_offset
[4]);
984 if (previous_stage
== MESA_SHADER_VERTEX
) {
985 declare_vs_input_vgprs(args
);
987 declare_tes_input_vgprs(args
);
990 declare_global_input_sgprs(args
, &user_sgpr_info
);
992 if (needs_view_index
) {
993 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
,
994 &args
->ac
.view_index
);
997 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
, &args
->gs2vs_offset
);
998 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
, &args
->gs_wave_id
);
999 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
,
1000 &args
->gs_vtx_offset
[0]);
1001 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
,
1002 &args
->gs_vtx_offset
[1]);
1003 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
,
1004 &args
->ac
.gs_prim_id
);
1005 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
,
1006 &args
->gs_vtx_offset
[2]);
1007 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
,
1008 &args
->gs_vtx_offset
[3]);
1009 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
,
1010 &args
->gs_vtx_offset
[4]);
1011 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
,
1012 &args
->gs_vtx_offset
[5]);
1013 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
,
1014 &args
->ac
.gs_invocation_id
);
1017 case MESA_SHADER_FRAGMENT
:
1018 declare_global_input_sgprs(args
, &user_sgpr_info
);
1020 ac_add_arg(&args
->ac
, AC_ARG_SGPR
, 1, AC_ARG_INT
, &args
->ac
.prim_mask
);
1021 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 2, AC_ARG_INT
, &args
->ac
.persp_sample
);
1022 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 2, AC_ARG_INT
, &args
->ac
.persp_center
);
1023 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 2, AC_ARG_INT
, &args
->ac
.persp_centroid
);
1024 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 3, AC_ARG_INT
, NULL
); /* persp pull model */
1025 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 2, AC_ARG_INT
, &args
->ac
.linear_sample
);
1026 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 2, AC_ARG_INT
, &args
->ac
.linear_center
);
1027 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 2, AC_ARG_INT
, &args
->ac
.linear_centroid
);
1028 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_FLOAT
, NULL
); /* line stipple tex */
1029 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_FLOAT
, &args
->ac
.frag_pos
[0]);
1030 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_FLOAT
, &args
->ac
.frag_pos
[1]);
1031 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_FLOAT
, &args
->ac
.frag_pos
[2]);
1032 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_FLOAT
, &args
->ac
.frag_pos
[3]);
1033 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
, &args
->ac
.front_face
);
1034 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
, &args
->ac
.ancillary
);
1035 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
, &args
->ac
.sample_coverage
);
1036 ac_add_arg(&args
->ac
, AC_ARG_VGPR
, 1, AC_ARG_INT
, NULL
); /* fixed pt */
1039 unreachable("Shader stage not implemented");
1042 args
->shader_info
->num_input_vgprs
= 0;
1043 args
->shader_info
->num_input_sgprs
= args
->options
->supports_spill
? 2 : 0;
1044 args
->shader_info
->num_input_sgprs
+= args
->ac
.num_sgprs_used
;
1046 if (stage
!= MESA_SHADER_FRAGMENT
)
1047 args
->shader_info
->num_input_vgprs
= args
->ac
.num_vgprs_used
;
1049 uint8_t user_sgpr_idx
= 0;
1051 if (args
->options
->supports_spill
|| user_sgpr_info
.need_ring_offsets
) {
1052 set_loc_shader_ptr(args
, AC_UD_SCRATCH_RING_OFFSETS
,
1056 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1057 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1058 if (has_previous_stage
)
1061 set_global_input_locs(args
, &user_sgpr_info
, &user_sgpr_idx
);
1064 case MESA_SHADER_COMPUTE
:
1065 if (args
->shader_info
->cs
.uses_grid_size
) {
1066 set_loc_shader(args
, AC_UD_CS_GRID_SIZE
,
1070 case MESA_SHADER_VERTEX
:
1071 set_vs_specific_input_locs(args
, stage
, has_previous_stage
,
1072 previous_stage
, &user_sgpr_idx
);
1073 if (args
->ac
.view_index
.used
)
1074 set_loc_shader(args
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1076 case MESA_SHADER_TESS_CTRL
:
1077 set_vs_specific_input_locs(args
, stage
, has_previous_stage
,
1078 previous_stage
, &user_sgpr_idx
);
1079 if (args
->ac
.view_index
.used
)
1080 set_loc_shader(args
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1082 case MESA_SHADER_TESS_EVAL
:
1083 if (args
->ac
.view_index
.used
)
1084 set_loc_shader(args
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1086 case MESA_SHADER_GEOMETRY
:
1087 if (has_previous_stage
) {
1088 if (previous_stage
== MESA_SHADER_VERTEX
)
1089 set_vs_specific_input_locs(args
, stage
,
1094 if (args
->ac
.view_index
.used
)
1095 set_loc_shader(args
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1097 case MESA_SHADER_FRAGMENT
:
1100 unreachable("Shader stage not implemented");
1103 args
->shader_info
->num_user_sgprs
= user_sgpr_idx
;
1106 static void create_function(struct radv_shader_context
*ctx
,
1107 gl_shader_stage stage
,
1108 bool has_previous_stage
)
1110 if (ctx
->ac
.chip_class
>= GFX10
) {
1111 if (is_pre_gs_stage(stage
) && ctx
->args
->options
->key
.vs_common_out
.as_ngg
) {
1112 /* On GFX10, VS is merged into GS for NGG. */
1113 stage
= MESA_SHADER_GEOMETRY
;
1114 has_previous_stage
= true;
1118 ctx
->main_function
= create_llvm_function(
1119 &ctx
->ac
, ctx
->ac
.module
, ctx
->ac
.builder
, &ctx
->args
->ac
,
1120 get_llvm_calling_convention(ctx
->main_function
, stage
),
1121 ctx
->max_workgroup_size
,
1122 ctx
->args
->options
);
1124 if (ctx
->args
->options
->supports_spill
) {
1125 ctx
->ring_offsets
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.implicit.buffer.ptr",
1126 LLVMPointerType(ctx
->ac
.i8
, AC_ADDR_SPACE_CONST
),
1127 NULL
, 0, AC_FUNC_ATTR_READNONE
);
1128 ctx
->ring_offsets
= LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->ring_offsets
,
1129 ac_array_in_const_addr_space(ctx
->ac
.v4i32
), "");
1130 } else if (ctx
->args
->ring_offsets
.used
) {
1131 ctx
->ring_offsets
= ac_get_arg(&ctx
->ac
, ctx
->args
->ring_offsets
);
1134 load_descriptor_sets(ctx
);
1136 if (stage
== MESA_SHADER_TESS_CTRL
||
1137 (stage
== MESA_SHADER_VERTEX
&& ctx
->args
->options
->key
.vs_common_out
.as_ls
) ||
1138 /* GFX9 has the ESGS ring buffer in LDS. */
1139 (stage
== MESA_SHADER_GEOMETRY
&& has_previous_stage
)) {
1140 ac_declare_lds_as_pointer(&ctx
->ac
);
1147 radv_load_resource(struct ac_shader_abi
*abi
, LLVMValueRef index
,
1148 unsigned desc_set
, unsigned binding
)
1150 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1151 LLVMValueRef desc_ptr
= ctx
->descriptor_sets
[desc_set
];
1152 struct radv_pipeline_layout
*pipeline_layout
= ctx
->args
->options
->layout
;
1153 struct radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
1154 unsigned base_offset
= layout
->binding
[binding
].offset
;
1155 LLVMValueRef offset
, stride
;
1157 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
1158 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
1159 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+
1160 layout
->binding
[binding
].dynamic_offset_offset
;
1161 desc_ptr
= ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.push_constants
);
1162 base_offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
1163 stride
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
1165 stride
= LLVMConstInt(ctx
->ac
.i32
, layout
->binding
[binding
].size
, false);
1167 offset
= LLVMConstInt(ctx
->ac
.i32
, base_offset
, false);
1169 if (layout
->binding
[binding
].type
!= VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
1170 offset
= ac_build_imad(&ctx
->ac
, index
, stride
, offset
);
1173 desc_ptr
= LLVMBuildGEP(ctx
->ac
.builder
, desc_ptr
, &offset
, 1, "");
1174 desc_ptr
= ac_cast_ptr(&ctx
->ac
, desc_ptr
, ctx
->ac
.v4i32
);
1175 LLVMSetMetadata(desc_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1177 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
1178 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1179 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1180 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1181 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
1183 if (ctx
->ac
.chip_class
>= GFX10
) {
1184 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
1185 S_008F0C_OOB_SELECT(3) |
1186 S_008F0C_RESOURCE_LEVEL(1);
1188 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1189 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1192 LLVMValueRef desc_components
[4] = {
1193 LLVMBuildPtrToInt(ctx
->ac
.builder
, desc_ptr
, ctx
->ac
.intptr
, ""),
1194 LLVMConstInt(ctx
->ac
.i32
, S_008F04_BASE_ADDRESS_HI(ctx
->args
->options
->address32_hi
), false),
1195 /* High limit to support variable sizes. */
1196 LLVMConstInt(ctx
->ac
.i32
, 0xffffffff, false),
1197 LLVMConstInt(ctx
->ac
.i32
, desc_type
, false),
1200 return ac_build_gather_values(&ctx
->ac
, desc_components
, 4);
1207 /* The offchip buffer layout for TCS->TES is
1209 * - attribute 0 of patch 0 vertex 0
1210 * - attribute 0 of patch 0 vertex 1
1211 * - attribute 0 of patch 0 vertex 2
1213 * - attribute 0 of patch 1 vertex 0
1214 * - attribute 0 of patch 1 vertex 1
1216 * - attribute 1 of patch 0 vertex 0
1217 * - attribute 1 of patch 0 vertex 1
1219 * - per patch attribute 0 of patch 0
1220 * - per patch attribute 0 of patch 1
1223 * Note that every attribute has 4 components.
1225 static LLVMValueRef
get_non_vertex_index_offset(struct radv_shader_context
*ctx
)
1227 uint32_t num_patches
= ctx
->tcs_num_patches
;
1228 uint32_t num_tcs_outputs
;
1229 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
1230 num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
1232 num_tcs_outputs
= ctx
->args
->options
->key
.tes
.tcs_num_outputs
;
1234 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
1235 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
1237 return LLVMConstInt(ctx
->ac
.i32
, pervertex_output_patch_size
* num_patches
, false);
1240 static LLVMValueRef
calc_param_stride(struct radv_shader_context
*ctx
,
1241 LLVMValueRef vertex_index
)
1243 LLVMValueRef param_stride
;
1245 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.tess
.tcs_vertices_out
* ctx
->tcs_num_patches
, false);
1247 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_num_patches
, false);
1248 return param_stride
;
1251 static LLVMValueRef
get_tcs_tes_buffer_address(struct radv_shader_context
*ctx
,
1252 LLVMValueRef vertex_index
,
1253 LLVMValueRef param_index
)
1255 LLVMValueRef base_addr
;
1256 LLVMValueRef param_stride
, constant16
;
1257 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
1258 LLVMValueRef vertices_per_patch
= LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.tess
.tcs_vertices_out
, false);
1259 constant16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
1260 param_stride
= calc_param_stride(ctx
, vertex_index
);
1262 base_addr
= ac_build_imad(&ctx
->ac
, rel_patch_id
,
1263 vertices_per_patch
, vertex_index
);
1265 base_addr
= rel_patch_id
;
1268 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
1269 LLVMBuildMul(ctx
->ac
.builder
, param_index
,
1270 param_stride
, ""), "");
1272 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, base_addr
, constant16
, "");
1274 if (!vertex_index
) {
1275 LLVMValueRef patch_data_offset
= get_non_vertex_index_offset(ctx
);
1277 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
1278 patch_data_offset
, "");
1283 static LLVMValueRef
get_tcs_tes_buffer_address_params(struct radv_shader_context
*ctx
,
1285 unsigned const_index
,
1287 LLVMValueRef vertex_index
,
1288 LLVMValueRef indir_index
)
1290 LLVMValueRef param_index
;
1293 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, param
, false),
1296 if (const_index
&& !is_compact
)
1297 param
+= const_index
;
1298 param_index
= LLVMConstInt(ctx
->ac
.i32
, param
, false);
1300 return get_tcs_tes_buffer_address(ctx
, vertex_index
, param_index
);
1304 get_dw_address(struct radv_shader_context
*ctx
,
1305 LLVMValueRef dw_addr
,
1307 unsigned const_index
,
1308 bool compact_const_index
,
1309 LLVMValueRef vertex_index
,
1310 LLVMValueRef stride
,
1311 LLVMValueRef indir_index
)
1316 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1317 LLVMBuildMul(ctx
->ac
.builder
,
1323 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1324 LLVMBuildMul(ctx
->ac
.builder
, indir_index
,
1325 LLVMConstInt(ctx
->ac
.i32
, 4, false), ""), "");
1326 else if (const_index
&& !compact_const_index
)
1327 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1328 LLVMConstInt(ctx
->ac
.i32
, const_index
* 4, false), "");
1330 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1331 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false), "");
1333 if (const_index
&& compact_const_index
)
1334 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1335 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
1340 load_tcs_varyings(struct ac_shader_abi
*abi
,
1342 LLVMValueRef vertex_index
,
1343 LLVMValueRef indir_index
,
1344 unsigned const_index
,
1346 unsigned driver_location
,
1348 unsigned num_components
,
1353 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1354 LLVMValueRef dw_addr
, stride
;
1355 LLVMValueRef value
[4], result
;
1356 unsigned param
= shader_io_get_unique_index(location
);
1359 uint32_t input_vertex_size
= (ctx
->tcs_num_inputs
* 16) / 4;
1360 stride
= LLVMConstInt(ctx
->ac
.i32
, input_vertex_size
, false);
1361 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
1364 stride
= get_tcs_out_vertex_stride(ctx
);
1365 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1367 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1372 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
1375 for (unsigned i
= 0; i
< num_components
+ component
; i
++) {
1376 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
1377 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1380 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1385 store_tcs_output(struct ac_shader_abi
*abi
,
1386 const nir_variable
*var
,
1387 LLVMValueRef vertex_index
,
1388 LLVMValueRef param_index
,
1389 unsigned const_index
,
1393 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1394 const unsigned location
= var
->data
.location
;
1395 unsigned component
= var
->data
.location_frac
;
1396 const bool is_patch
= var
->data
.patch
;
1397 const bool is_compact
= var
->data
.compact
;
1398 LLVMValueRef dw_addr
;
1399 LLVMValueRef stride
= NULL
;
1400 LLVMValueRef buf_addr
= NULL
;
1401 LLVMValueRef oc_lds
= ac_get_arg(&ctx
->ac
, ctx
->args
->oc_lds
);
1403 bool store_lds
= true;
1406 if (!(ctx
->shader
->info
.patch_outputs_read
& (1U << (location
- VARYING_SLOT_PATCH0
))))
1409 if (!(ctx
->shader
->info
.outputs_read
& (1ULL << location
)))
1413 param
= shader_io_get_unique_index(location
);
1414 if ((location
== VARYING_SLOT_CLIP_DIST0
|| location
== VARYING_SLOT_CLIP_DIST1
) && is_compact
) {
1415 const_index
+= component
;
1418 if (const_index
>= 4) {
1425 stride
= get_tcs_out_vertex_stride(ctx
);
1426 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1428 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1431 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
1433 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
, is_compact
,
1434 vertex_index
, param_index
);
1436 bool is_tess_factor
= false;
1437 if (location
== VARYING_SLOT_TESS_LEVEL_INNER
||
1438 location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
1439 is_tess_factor
= true;
1441 unsigned base
= is_compact
? const_index
: 0;
1442 for (unsigned chan
= 0; chan
< 8; chan
++) {
1443 if (!(writemask
& (1 << chan
)))
1445 LLVMValueRef value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- component
);
1446 value
= ac_to_integer(&ctx
->ac
, value
);
1447 value
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
1449 if (store_lds
|| is_tess_factor
) {
1450 LLVMValueRef dw_addr_chan
=
1451 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1452 LLVMConstInt(ctx
->ac
.i32
, chan
, false), "");
1453 ac_lds_store(&ctx
->ac
, dw_addr_chan
, value
);
1456 if (!is_tess_factor
&& writemask
!= 0xF)
1457 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, value
, 1,
1459 4 * (base
+ chan
), ac_glc
, false);
1462 if (writemask
== 0xF) {
1463 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, src
, 4,
1465 (base
* 4), ac_glc
, false);
1470 load_tes_input(struct ac_shader_abi
*abi
,
1472 LLVMValueRef vertex_index
,
1473 LLVMValueRef param_index
,
1474 unsigned const_index
,
1476 unsigned driver_location
,
1478 unsigned num_components
,
1483 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1484 LLVMValueRef buf_addr
;
1485 LLVMValueRef result
;
1486 LLVMValueRef oc_lds
= ac_get_arg(&ctx
->ac
, ctx
->args
->oc_lds
);
1487 unsigned param
= shader_io_get_unique_index(location
);
1489 if ((location
== VARYING_SLOT_CLIP_DIST0
|| location
== VARYING_SLOT_CLIP_DIST1
) && is_compact
) {
1490 const_index
+= component
;
1492 if (const_index
>= 4) {
1498 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
,
1499 is_compact
, vertex_index
, param_index
);
1501 LLVMValueRef comp_offset
= LLVMConstInt(ctx
->ac
.i32
, component
* 4, false);
1502 buf_addr
= LLVMBuildAdd(ctx
->ac
.builder
, buf_addr
, comp_offset
, "");
1504 result
= ac_build_buffer_load(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, num_components
, NULL
,
1505 buf_addr
, oc_lds
, is_compact
? (4 * const_index
) : 0, ac_glc
, true, false);
1506 result
= ac_trim_vector(&ctx
->ac
, result
, num_components
);
1511 radv_emit_fetch_64bit(struct radv_shader_context
*ctx
,
1512 LLVMTypeRef type
, LLVMValueRef a
, LLVMValueRef b
)
1514 LLVMValueRef values
[2] = {
1515 ac_to_integer(&ctx
->ac
, a
),
1516 ac_to_integer(&ctx
->ac
, b
),
1518 LLVMValueRef result
= ac_build_gather_values(&ctx
->ac
, values
, 2);
1519 return LLVMBuildBitCast(ctx
->ac
.builder
, result
, type
, "");
1523 load_gs_input(struct ac_shader_abi
*abi
,
1525 unsigned driver_location
,
1527 unsigned num_components
,
1528 unsigned vertex_index
,
1529 unsigned const_index
,
1532 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1533 LLVMValueRef vtx_offset
;
1534 unsigned param
, vtx_offset_param
;
1535 LLVMValueRef value
[4], result
;
1537 vtx_offset_param
= vertex_index
;
1538 assert(vtx_offset_param
< 6);
1539 vtx_offset
= LLVMBuildMul(ctx
->ac
.builder
, ctx
->gs_vtx_offset
[vtx_offset_param
],
1540 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
1542 param
= shader_io_get_unique_index(location
);
1544 for (unsigned i
= component
; i
< num_components
+ component
; i
++) {
1545 if (ctx
->ac
.chip_class
>= GFX9
) {
1546 LLVMValueRef dw_addr
= ctx
->gs_vtx_offset
[vtx_offset_param
];
1547 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1548 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
, 0), "");
1549 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
1551 if (ac_get_type_size(type
) == 8) {
1552 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1553 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
+ 1, 0), "");
1554 LLVMValueRef tmp
= ac_lds_load(&ctx
->ac
, dw_addr
);
1556 value
[i
] = radv_emit_fetch_64bit(ctx
, type
, value
[i
], tmp
);
1559 LLVMValueRef soffset
=
1560 LLVMConstInt(ctx
->ac
.i32
,
1561 (param
* 4 + i
+ const_index
) * 256,
1564 value
[i
] = ac_build_buffer_load(&ctx
->ac
,
1567 vtx_offset
, soffset
,
1568 0, ac_glc
, true, false);
1570 if (ac_get_type_size(type
) == 8) {
1571 soffset
= LLVMConstInt(ctx
->ac
.i32
,
1572 (param
* 4 + i
+ const_index
+ 1) * 256,
1576 ac_build_buffer_load(&ctx
->ac
,
1579 vtx_offset
, soffset
,
1580 0, ac_glc
, true, false);
1582 value
[i
] = radv_emit_fetch_64bit(ctx
, type
, value
[i
], tmp
);
1586 if (ac_get_type_size(type
) == 2) {
1587 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
], ctx
->ac
.i32
, "");
1588 value
[i
] = LLVMBuildTrunc(ctx
->ac
.builder
, value
[i
], ctx
->ac
.i16
, "");
1590 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
], type
, "");
1592 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1593 result
= ac_to_integer(&ctx
->ac
, result
);
1598 static void radv_emit_kill(struct ac_shader_abi
*abi
, LLVMValueRef visible
)
1600 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1601 ac_build_kill_if_false(&ctx
->ac
, visible
);
1605 radv_get_sample_pos_offset(uint32_t num_samples
)
1607 uint32_t sample_pos_offset
= 0;
1609 switch (num_samples
) {
1611 sample_pos_offset
= 1;
1614 sample_pos_offset
= 3;
1617 sample_pos_offset
= 7;
1622 return sample_pos_offset
;
1625 static LLVMValueRef
load_sample_position(struct ac_shader_abi
*abi
,
1626 LLVMValueRef sample_id
)
1628 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1630 LLVMValueRef result
;
1631 LLVMValueRef index
= LLVMConstInt(ctx
->ac
.i32
, RING_PS_SAMPLE_POSITIONS
, false);
1632 LLVMValueRef ptr
= LLVMBuildGEP(ctx
->ac
.builder
, ctx
->ring_offsets
, &index
, 1, "");
1634 ptr
= LLVMBuildBitCast(ctx
->ac
.builder
, ptr
,
1635 ac_array_in_const_addr_space(ctx
->ac
.v2f32
), "");
1637 uint32_t sample_pos_offset
=
1638 radv_get_sample_pos_offset(ctx
->args
->options
->key
.fs
.num_samples
);
1641 LLVMBuildAdd(ctx
->ac
.builder
, sample_id
,
1642 LLVMConstInt(ctx
->ac
.i32
, sample_pos_offset
, false), "");
1643 result
= ac_build_load_invariant(&ctx
->ac
, ptr
, sample_id
);
1649 static LLVMValueRef
load_sample_mask_in(struct ac_shader_abi
*abi
)
1651 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1652 uint8_t log2_ps_iter_samples
;
1654 if (ctx
->args
->shader_info
->ps
.force_persample
) {
1655 log2_ps_iter_samples
=
1656 util_logbase2(ctx
->args
->options
->key
.fs
.num_samples
);
1658 log2_ps_iter_samples
= ctx
->args
->options
->key
.fs
.log2_ps_iter_samples
;
1661 /* The bit pattern matches that used by fixed function fragment
1663 static const uint16_t ps_iter_masks
[] = {
1664 0xffff, /* not used */
1670 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
1672 uint32_t ps_iter_mask
= ps_iter_masks
[log2_ps_iter_samples
];
1674 LLVMValueRef result
, sample_id
;
1675 sample_id
= ac_unpack_param(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.ancillary
), 8, 4);
1676 sample_id
= LLVMBuildShl(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, ps_iter_mask
, false), sample_id
, "");
1677 result
= LLVMBuildAnd(ctx
->ac
.builder
, sample_id
,
1678 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.sample_coverage
), "");
1683 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context
*ctx
,
1685 LLVMValueRef
*addrs
);
1688 visit_emit_vertex(struct ac_shader_abi
*abi
, unsigned stream
, LLVMValueRef
*addrs
)
1690 LLVMValueRef gs_next_vertex
;
1691 LLVMValueRef can_emit
;
1692 unsigned offset
= 0;
1693 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1695 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg
) {
1696 gfx10_ngg_gs_emit_vertex(ctx
, stream
, addrs
);
1700 /* Write vertex attribute values to GSVS ring */
1701 gs_next_vertex
= LLVMBuildLoad(ctx
->ac
.builder
,
1702 ctx
->gs_next_vertex
[stream
],
1705 /* If this thread has already emitted the declared maximum number of
1706 * vertices, don't emit any more: excessive vertex emissions are not
1707 * supposed to have any effect.
1709 can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
, gs_next_vertex
,
1710 LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.gs
.vertices_out
, false), "");
1712 bool use_kill
= !ctx
->args
->shader_info
->gs
.writes_memory
;
1714 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
1716 ac_build_ifcc(&ctx
->ac
, can_emit
, 6505);
1718 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
1719 unsigned output_usage_mask
=
1720 ctx
->args
->shader_info
->gs
.output_usage_mask
[i
];
1721 uint8_t output_stream
=
1722 ctx
->args
->shader_info
->gs
.output_streams
[i
];
1723 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
1724 int length
= util_last_bit(output_usage_mask
);
1726 if (!(ctx
->output_mask
& (1ull << i
)) ||
1727 output_stream
!= stream
)
1730 for (unsigned j
= 0; j
< length
; j
++) {
1731 if (!(output_usage_mask
& (1 << j
)))
1734 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
,
1736 LLVMValueRef voffset
=
1737 LLVMConstInt(ctx
->ac
.i32
, offset
*
1738 ctx
->shader
->info
.gs
.vertices_out
, false);
1742 voffset
= LLVMBuildAdd(ctx
->ac
.builder
, voffset
, gs_next_vertex
, "");
1743 voffset
= LLVMBuildMul(ctx
->ac
.builder
, voffset
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
1745 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
1746 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
1748 ac_build_buffer_store_dword(&ctx
->ac
,
1749 ctx
->gsvs_ring
[stream
],
1752 ac_get_arg(&ctx
->ac
,
1753 ctx
->args
->gs2vs_offset
),
1754 0, ac_glc
| ac_slc
, true);
1758 gs_next_vertex
= LLVMBuildAdd(ctx
->ac
.builder
, gs_next_vertex
,
1760 LLVMBuildStore(ctx
->ac
.builder
, gs_next_vertex
, ctx
->gs_next_vertex
[stream
]);
1762 ac_build_sendmsg(&ctx
->ac
,
1763 AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (stream
<< 8),
1767 ac_build_endif(&ctx
->ac
, 6505);
1771 visit_end_primitive(struct ac_shader_abi
*abi
, unsigned stream
)
1773 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1775 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg
) {
1776 LLVMBuildStore(ctx
->ac
.builder
, ctx
->ac
.i32_0
, ctx
->gs_curprim_verts
[stream
]);
1780 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (stream
<< 8), ctx
->gs_wave_id
);
1784 load_tess_coord(struct ac_shader_abi
*abi
)
1786 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1788 LLVMValueRef coord
[4] = {
1789 ac_get_arg(&ctx
->ac
, ctx
->args
->tes_u
),
1790 ac_get_arg(&ctx
->ac
, ctx
->args
->tes_v
),
1795 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
)
1796 coord
[2] = LLVMBuildFSub(ctx
->ac
.builder
, ctx
->ac
.f32_1
,
1797 LLVMBuildFAdd(ctx
->ac
.builder
, coord
[0], coord
[1], ""), "");
1799 return ac_build_gather_values(&ctx
->ac
, coord
, 3);
1803 load_patch_vertices_in(struct ac_shader_abi
*abi
)
1805 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1806 return LLVMConstInt(ctx
->ac
.i32
, ctx
->args
->options
->key
.tcs
.input_vertices
, false);
1810 static LLVMValueRef
radv_load_base_vertex(struct ac_shader_abi
*abi
)
1812 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1813 return ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.base_vertex
);
1816 static LLVMValueRef
radv_load_ssbo(struct ac_shader_abi
*abi
,
1817 LLVMValueRef buffer_ptr
, bool write
)
1819 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1820 LLVMValueRef result
;
1822 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1824 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
1825 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
1830 static LLVMValueRef
radv_load_ubo(struct ac_shader_abi
*abi
, LLVMValueRef buffer_ptr
)
1832 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1833 LLVMValueRef result
;
1835 if (LLVMGetTypeKind(LLVMTypeOf(buffer_ptr
)) != LLVMPointerTypeKind
) {
1836 /* Do not load the descriptor for inlined uniform blocks. */
1840 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1842 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
1843 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
1848 static LLVMValueRef
radv_get_sampler_desc(struct ac_shader_abi
*abi
,
1849 unsigned descriptor_set
,
1850 unsigned base_index
,
1851 unsigned constant_index
,
1853 enum ac_descriptor_type desc_type
,
1854 bool image
, bool write
,
1857 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1858 LLVMValueRef list
= ctx
->descriptor_sets
[descriptor_set
];
1859 struct radv_descriptor_set_layout
*layout
= ctx
->args
->options
->layout
->set
[descriptor_set
].layout
;
1860 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
1861 unsigned offset
= binding
->offset
;
1862 unsigned stride
= binding
->size
;
1864 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1867 assert(base_index
< layout
->binding_count
);
1869 switch (desc_type
) {
1871 type
= ctx
->ac
.v8i32
;
1875 type
= ctx
->ac
.v8i32
;
1879 case AC_DESC_SAMPLER
:
1880 type
= ctx
->ac
.v4i32
;
1881 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
) {
1882 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
1887 case AC_DESC_BUFFER
:
1888 type
= ctx
->ac
.v4i32
;
1891 case AC_DESC_PLANE_0
:
1892 case AC_DESC_PLANE_1
:
1893 case AC_DESC_PLANE_2
:
1894 type
= ctx
->ac
.v8i32
;
1896 offset
+= 32 * (desc_type
- AC_DESC_PLANE_0
);
1899 unreachable("invalid desc_type\n");
1902 offset
+= constant_index
* stride
;
1904 if (desc_type
== AC_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
1905 (!index
|| binding
->immutable_samplers_equal
)) {
1906 if (binding
->immutable_samplers_equal
)
1909 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
1911 LLVMValueRef constants
[] = {
1912 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 0], 0),
1913 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 1], 0),
1914 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 2], 0),
1915 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 3], 0),
1917 return ac_build_gather_values(&ctx
->ac
, constants
, 4);
1920 assert(stride
% type_size
== 0);
1922 LLVMValueRef adjusted_index
= index
;
1923 if (!adjusted_index
)
1924 adjusted_index
= ctx
->ac
.i32_0
;
1926 adjusted_index
= LLVMBuildMul(builder
, adjusted_index
, LLVMConstInt(ctx
->ac
.i32
, stride
/ type_size
, 0), "");
1928 LLVMValueRef val_offset
= LLVMConstInt(ctx
->ac
.i32
, offset
, 0);
1929 list
= LLVMBuildGEP(builder
, list
, &val_offset
, 1, "");
1930 list
= LLVMBuildPointerCast(builder
, list
,
1931 ac_array_in_const32_addr_space(type
), "");
1933 LLVMValueRef descriptor
= ac_build_load_to_sgpr(&ctx
->ac
, list
, adjusted_index
);
1935 /* 3 plane formats always have same size and format for plane 1 & 2, so
1936 * use the tail from plane 1 so that we can store only the first 16 bytes
1937 * of the last plane. */
1938 if (desc_type
== AC_DESC_PLANE_2
) {
1939 LLVMValueRef descriptor2
= radv_get_sampler_desc(abi
, descriptor_set
, base_index
, constant_index
, index
, AC_DESC_PLANE_1
,image
, write
, bindless
);
1941 LLVMValueRef components
[8];
1942 for (unsigned i
= 0; i
< 4; ++i
)
1943 components
[i
] = ac_llvm_extract_elem(&ctx
->ac
, descriptor
, i
);
1945 for (unsigned i
= 4; i
< 8; ++i
)
1946 components
[i
] = ac_llvm_extract_elem(&ctx
->ac
, descriptor2
, i
);
1947 descriptor
= ac_build_gather_values(&ctx
->ac
, components
, 8);
1953 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
1954 * so we may need to fix it up. */
1956 adjust_vertex_fetch_alpha(struct radv_shader_context
*ctx
,
1957 unsigned adjustment
,
1960 if (adjustment
== RADV_ALPHA_ADJUST_NONE
)
1963 LLVMValueRef c30
= LLVMConstInt(ctx
->ac
.i32
, 30, 0);
1965 alpha
= LLVMBuildBitCast(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
1967 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
1968 alpha
= LLVMBuildFPToUI(ctx
->ac
.builder
, alpha
, ctx
->ac
.i32
, "");
1970 alpha
= ac_to_integer(&ctx
->ac
, alpha
);
1972 /* For the integer-like cases, do a natural sign extension.
1974 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
1975 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
1978 alpha
= LLVMBuildShl(ctx
->ac
.builder
, alpha
,
1979 adjustment
== RADV_ALPHA_ADJUST_SNORM
?
1980 LLVMConstInt(ctx
->ac
.i32
, 7, 0) : c30
, "");
1981 alpha
= LLVMBuildAShr(ctx
->ac
.builder
, alpha
, c30
, "");
1983 /* Convert back to the right type. */
1984 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
1986 LLVMValueRef neg_one
= LLVMConstReal(ctx
->ac
.f32
, -1.0);
1987 alpha
= LLVMBuildSIToFP(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
1988 clamp
= LLVMBuildFCmp(ctx
->ac
.builder
, LLVMRealULT
, alpha
, neg_one
, "");
1989 alpha
= LLVMBuildSelect(ctx
->ac
.builder
, clamp
, neg_one
, alpha
, "");
1990 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
1991 alpha
= LLVMBuildSIToFP(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
1994 return LLVMBuildBitCast(ctx
->ac
.builder
, alpha
, ctx
->ac
.i32
, "");
1998 get_num_channels_from_data_format(unsigned data_format
)
2000 switch (data_format
) {
2001 case V_008F0C_BUF_DATA_FORMAT_8
:
2002 case V_008F0C_BUF_DATA_FORMAT_16
:
2003 case V_008F0C_BUF_DATA_FORMAT_32
:
2005 case V_008F0C_BUF_DATA_FORMAT_8_8
:
2006 case V_008F0C_BUF_DATA_FORMAT_16_16
:
2007 case V_008F0C_BUF_DATA_FORMAT_32_32
:
2009 case V_008F0C_BUF_DATA_FORMAT_10_11_11
:
2010 case V_008F0C_BUF_DATA_FORMAT_11_11_10
:
2011 case V_008F0C_BUF_DATA_FORMAT_32_32_32
:
2013 case V_008F0C_BUF_DATA_FORMAT_8_8_8_8
:
2014 case V_008F0C_BUF_DATA_FORMAT_10_10_10_2
:
2015 case V_008F0C_BUF_DATA_FORMAT_2_10_10_10
:
2016 case V_008F0C_BUF_DATA_FORMAT_16_16_16_16
:
2017 case V_008F0C_BUF_DATA_FORMAT_32_32_32_32
:
2027 radv_fixup_vertex_input_fetches(struct radv_shader_context
*ctx
,
2029 unsigned num_channels
,
2032 LLVMValueRef zero
= is_float
? ctx
->ac
.f32_0
: ctx
->ac
.i32_0
;
2033 LLVMValueRef one
= is_float
? ctx
->ac
.f32_1
: ctx
->ac
.i32_1
;
2034 LLVMValueRef chan
[4];
2036 if (LLVMGetTypeKind(LLVMTypeOf(value
)) == LLVMVectorTypeKind
) {
2037 unsigned vec_size
= LLVMGetVectorSize(LLVMTypeOf(value
));
2039 if (num_channels
== 4 && num_channels
== vec_size
)
2042 num_channels
= MIN2(num_channels
, vec_size
);
2044 for (unsigned i
= 0; i
< num_channels
; i
++)
2045 chan
[i
] = ac_llvm_extract_elem(&ctx
->ac
, value
, i
);
2048 assert(num_channels
== 1);
2053 for (unsigned i
= num_channels
; i
< 4; i
++) {
2054 chan
[i
] = i
== 3 ? one
: zero
;
2055 chan
[i
] = ac_to_integer(&ctx
->ac
, chan
[i
]);
2058 return ac_build_gather_values(&ctx
->ac
, chan
, 4);
2062 handle_vs_input_decl(struct radv_shader_context
*ctx
,
2063 struct nir_variable
*variable
)
2065 LLVMValueRef t_list_ptr
= ac_get_arg(&ctx
->ac
, ctx
->args
->vertex_buffers
);
2066 LLVMValueRef t_offset
;
2067 LLVMValueRef t_list
;
2069 LLVMValueRef buffer_index
;
2070 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, true);
2071 uint8_t input_usage_mask
=
2072 ctx
->args
->shader_info
->vs
.input_usage_mask
[variable
->data
.location
];
2073 unsigned num_input_channels
= util_last_bit(input_usage_mask
);
2075 variable
->data
.driver_location
= variable
->data
.location
* 4;
2077 enum glsl_base_type type
= glsl_get_base_type(variable
->type
);
2078 for (unsigned i
= 0; i
< attrib_count
; ++i
) {
2079 LLVMValueRef output
[4];
2080 unsigned attrib_index
= variable
->data
.location
+ i
- VERT_ATTRIB_GENERIC0
;
2081 unsigned attrib_format
= ctx
->args
->options
->key
.vs
.vertex_attribute_formats
[attrib_index
];
2082 unsigned data_format
= attrib_format
& 0x0f;
2083 unsigned num_format
= (attrib_format
>> 4) & 0x07;
2084 bool is_float
= num_format
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
2085 num_format
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
2087 if (ctx
->args
->options
->key
.vs
.instance_rate_inputs
& (1u << attrib_index
)) {
2088 uint32_t divisor
= ctx
->args
->options
->key
.vs
.instance_rate_divisors
[attrib_index
];
2091 buffer_index
= ctx
->abi
.instance_id
;
2094 buffer_index
= LLVMBuildUDiv(ctx
->ac
.builder
, buffer_index
,
2095 LLVMConstInt(ctx
->ac
.i32
, divisor
, 0), "");
2098 buffer_index
= ctx
->ac
.i32_0
;
2101 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
,
2102 ac_get_arg(&ctx
->ac
,
2103 ctx
->args
->ac
.start_instance
),\
2106 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
,
2108 ac_get_arg(&ctx
->ac
,
2109 ctx
->args
->ac
.base_vertex
), "");
2112 /* Adjust the number of channels to load based on the vertex
2115 unsigned num_format_channels
= get_num_channels_from_data_format(data_format
);
2116 unsigned num_channels
= MIN2(num_input_channels
, num_format_channels
);
2117 unsigned attrib_binding
= ctx
->args
->options
->key
.vs
.vertex_attribute_bindings
[attrib_index
];
2118 unsigned attrib_offset
= ctx
->args
->options
->key
.vs
.vertex_attribute_offsets
[attrib_index
];
2119 unsigned attrib_stride
= ctx
->args
->options
->key
.vs
.vertex_attribute_strides
[attrib_index
];
2121 if (ctx
->args
->options
->key
.vs
.post_shuffle
& (1 << attrib_index
)) {
2122 /* Always load, at least, 3 channels for formats that
2123 * need to be shuffled because X<->Z.
2125 num_channels
= MAX2(num_channels
, 3);
2128 if (attrib_stride
!= 0 && attrib_offset
> attrib_stride
) {
2129 LLVMValueRef buffer_offset
=
2130 LLVMConstInt(ctx
->ac
.i32
,
2131 attrib_offset
/ attrib_stride
, false);
2133 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
,
2137 attrib_offset
= attrib_offset
% attrib_stride
;
2140 t_offset
= LLVMConstInt(ctx
->ac
.i32
, attrib_binding
, false);
2141 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
2143 input
= ac_build_struct_tbuffer_load(&ctx
->ac
, t_list
,
2145 LLVMConstInt(ctx
->ac
.i32
, attrib_offset
, false),
2146 ctx
->ac
.i32_0
, ctx
->ac
.i32_0
,
2148 data_format
, num_format
, 0, true);
2150 if (ctx
->args
->options
->key
.vs
.post_shuffle
& (1 << attrib_index
)) {
2152 c
[0] = ac_llvm_extract_elem(&ctx
->ac
, input
, 2);
2153 c
[1] = ac_llvm_extract_elem(&ctx
->ac
, input
, 1);
2154 c
[2] = ac_llvm_extract_elem(&ctx
->ac
, input
, 0);
2155 c
[3] = ac_llvm_extract_elem(&ctx
->ac
, input
, 3);
2157 input
= ac_build_gather_values(&ctx
->ac
, c
, 4);
2160 input
= radv_fixup_vertex_input_fetches(ctx
, input
, num_channels
,
2163 for (unsigned chan
= 0; chan
< 4; chan
++) {
2164 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
2165 output
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
, input
, llvm_chan
, "");
2166 if (type
== GLSL_TYPE_FLOAT16
) {
2167 output
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.f32
, "");
2168 output
[chan
] = LLVMBuildFPTrunc(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.f16
, "");
2172 unsigned alpha_adjust
= (ctx
->args
->options
->key
.vs
.alpha_adjust
>> (attrib_index
* 2)) & 3;
2173 output
[3] = adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, output
[3]);
2175 for (unsigned chan
= 0; chan
< 4; chan
++) {
2176 output
[chan
] = ac_to_integer(&ctx
->ac
, output
[chan
]);
2177 if (type
== GLSL_TYPE_UINT16
|| type
== GLSL_TYPE_INT16
)
2178 output
[chan
] = LLVMBuildTrunc(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.i16
, "");
2180 ctx
->inputs
[ac_llvm_reg_index_soa(variable
->data
.location
+ i
, chan
)] = output
[chan
];
2186 handle_vs_inputs(struct radv_shader_context
*ctx
,
2187 struct nir_shader
*nir
) {
2188 nir_foreach_variable(variable
, &nir
->inputs
)
2189 handle_vs_input_decl(ctx
, variable
);
2193 prepare_interp_optimize(struct radv_shader_context
*ctx
,
2194 struct nir_shader
*nir
)
2196 bool uses_center
= false;
2197 bool uses_centroid
= false;
2198 nir_foreach_variable(variable
, &nir
->inputs
) {
2199 if (glsl_get_base_type(glsl_without_array(variable
->type
)) != GLSL_TYPE_FLOAT
||
2200 variable
->data
.sample
)
2203 if (variable
->data
.centroid
)
2204 uses_centroid
= true;
2209 ctx
->abi
.persp_centroid
= ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.persp_centroid
);
2210 ctx
->abi
.linear_centroid
= ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.linear_centroid
);
2212 if (uses_center
&& uses_centroid
) {
2213 LLVMValueRef sel
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntSLT
,
2214 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.prim_mask
),
2216 ctx
->abi
.persp_centroid
=
2217 LLVMBuildSelect(ctx
->ac
.builder
, sel
,
2218 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.persp_center
),
2219 ctx
->abi
.persp_centroid
, "");
2220 ctx
->abi
.linear_centroid
=
2221 LLVMBuildSelect(ctx
->ac
.builder
, sel
,
2222 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.linear_center
),
2223 ctx
->abi
.linear_centroid
, "");
2228 scan_shader_output_decl(struct radv_shader_context
*ctx
,
2229 struct nir_variable
*variable
,
2230 struct nir_shader
*shader
,
2231 gl_shader_stage stage
)
2233 int idx
= variable
->data
.location
+ variable
->data
.index
;
2234 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
2235 uint64_t mask_attribs
;
2237 variable
->data
.driver_location
= idx
* 4;
2239 /* tess ctrl has it's own load/store paths for outputs */
2240 if (stage
== MESA_SHADER_TESS_CTRL
)
2243 if (variable
->data
.compact
) {
2244 unsigned component_count
= variable
->data
.location_frac
+
2245 glsl_get_length(variable
->type
);
2246 attrib_count
= (component_count
+ 3) / 4;
2249 mask_attribs
= ((1ull << attrib_count
) - 1) << idx
;
2251 ctx
->output_mask
|= mask_attribs
;
2255 /* Initialize arguments for the shader export intrinsic */
2257 si_llvm_init_export_args(struct radv_shader_context
*ctx
,
2258 LLVMValueRef
*values
,
2259 unsigned enabled_channels
,
2261 struct ac_export_args
*args
)
2263 /* Specify the channels that are enabled. */
2264 args
->enabled_channels
= enabled_channels
;
2266 /* Specify whether the EXEC mask represents the valid mask */
2267 args
->valid_mask
= 0;
2269 /* Specify whether this is the last export */
2272 /* Specify the target we are exporting */
2273 args
->target
= target
;
2275 args
->compr
= false;
2276 args
->out
[0] = LLVMGetUndef(ctx
->ac
.f32
);
2277 args
->out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
2278 args
->out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
2279 args
->out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
2284 bool is_16bit
= ac_get_type_size(LLVMTypeOf(values
[0])) == 2;
2285 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
2286 unsigned index
= target
- V_008DFC_SQ_EXP_MRT
;
2287 unsigned col_format
= (ctx
->args
->options
->key
.fs
.col_format
>> (4 * index
)) & 0xf;
2288 bool is_int8
= (ctx
->args
->options
->key
.fs
.is_int8
>> index
) & 1;
2289 bool is_int10
= (ctx
->args
->options
->key
.fs
.is_int10
>> index
) & 1;
2292 LLVMValueRef (*packf
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2]) = NULL
;
2293 LLVMValueRef (*packi
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2],
2294 unsigned bits
, bool hi
) = NULL
;
2296 switch(col_format
) {
2297 case V_028714_SPI_SHADER_ZERO
:
2298 args
->enabled_channels
= 0; /* writemask */
2299 args
->target
= V_008DFC_SQ_EXP_NULL
;
2302 case V_028714_SPI_SHADER_32_R
:
2303 args
->enabled_channels
= 1;
2304 args
->out
[0] = values
[0];
2307 case V_028714_SPI_SHADER_32_GR
:
2308 args
->enabled_channels
= 0x3;
2309 args
->out
[0] = values
[0];
2310 args
->out
[1] = values
[1];
2313 case V_028714_SPI_SHADER_32_AR
:
2314 if (ctx
->ac
.chip_class
>= GFX10
) {
2315 args
->enabled_channels
= 0x3;
2316 args
->out
[0] = values
[0];
2317 args
->out
[1] = values
[3];
2319 args
->enabled_channels
= 0x9;
2320 args
->out
[0] = values
[0];
2321 args
->out
[3] = values
[3];
2325 case V_028714_SPI_SHADER_FP16_ABGR
:
2326 args
->enabled_channels
= 0x5;
2327 packf
= ac_build_cvt_pkrtz_f16
;
2329 for (unsigned chan
= 0; chan
< 4; chan
++)
2330 values
[chan
] = LLVMBuildFPExt(ctx
->ac
.builder
,
2336 case V_028714_SPI_SHADER_UNORM16_ABGR
:
2337 args
->enabled_channels
= 0x5;
2338 packf
= ac_build_cvt_pknorm_u16
;
2341 case V_028714_SPI_SHADER_SNORM16_ABGR
:
2342 args
->enabled_channels
= 0x5;
2343 packf
= ac_build_cvt_pknorm_i16
;
2346 case V_028714_SPI_SHADER_UINT16_ABGR
:
2347 args
->enabled_channels
= 0x5;
2348 packi
= ac_build_cvt_pk_u16
;
2350 for (unsigned chan
= 0; chan
< 4; chan
++)
2351 values
[chan
] = LLVMBuildZExt(ctx
->ac
.builder
,
2352 ac_to_integer(&ctx
->ac
, values
[chan
]),
2357 case V_028714_SPI_SHADER_SINT16_ABGR
:
2358 args
->enabled_channels
= 0x5;
2359 packi
= ac_build_cvt_pk_i16
;
2361 for (unsigned chan
= 0; chan
< 4; chan
++)
2362 values
[chan
] = LLVMBuildSExt(ctx
->ac
.builder
,
2363 ac_to_integer(&ctx
->ac
, values
[chan
]),
2369 case V_028714_SPI_SHADER_32_ABGR
:
2370 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
2374 /* Pack f16 or norm_i16/u16. */
2376 for (chan
= 0; chan
< 2; chan
++) {
2377 LLVMValueRef pack_args
[2] = {
2379 values
[2 * chan
+ 1]
2381 LLVMValueRef packed
;
2383 packed
= packf(&ctx
->ac
, pack_args
);
2384 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2386 args
->compr
= 1; /* COMPR flag */
2391 for (chan
= 0; chan
< 2; chan
++) {
2392 LLVMValueRef pack_args
[2] = {
2393 ac_to_integer(&ctx
->ac
, values
[2 * chan
]),
2394 ac_to_integer(&ctx
->ac
, values
[2 * chan
+ 1])
2396 LLVMValueRef packed
;
2398 packed
= packi(&ctx
->ac
, pack_args
,
2399 is_int8
? 8 : is_int10
? 10 : 16,
2401 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2403 args
->compr
= 1; /* COMPR flag */
2409 for (unsigned chan
= 0; chan
< 4; chan
++) {
2410 values
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, values
[chan
], ctx
->ac
.i16
, "");
2411 args
->out
[chan
] = LLVMBuildZExt(ctx
->ac
.builder
, values
[chan
], ctx
->ac
.i32
, "");
2414 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
2416 for (unsigned i
= 0; i
< 4; ++i
)
2417 args
->out
[i
] = ac_to_float(&ctx
->ac
, args
->out
[i
]);
2421 radv_export_param(struct radv_shader_context
*ctx
, unsigned index
,
2422 LLVMValueRef
*values
, unsigned enabled_channels
)
2424 struct ac_export_args args
;
2426 si_llvm_init_export_args(ctx
, values
, enabled_channels
,
2427 V_008DFC_SQ_EXP_PARAM
+ index
, &args
);
2428 ac_build_export(&ctx
->ac
, &args
);
2432 radv_load_output(struct radv_shader_context
*ctx
, unsigned index
, unsigned chan
)
2434 LLVMValueRef output
= ctx
->abi
.outputs
[ac_llvm_reg_index_soa(index
, chan
)];
2435 return LLVMBuildLoad(ctx
->ac
.builder
, output
, "");
2439 radv_emit_stream_output(struct radv_shader_context
*ctx
,
2440 LLVMValueRef
const *so_buffers
,
2441 LLVMValueRef
const *so_write_offsets
,
2442 const struct radv_stream_output
*output
,
2443 struct radv_shader_output_values
*shader_out
)
2445 unsigned num_comps
= util_bitcount(output
->component_mask
);
2446 unsigned buf
= output
->buffer
;
2447 unsigned offset
= output
->offset
;
2449 LLVMValueRef out
[4];
2451 assert(num_comps
&& num_comps
<= 4);
2452 if (!num_comps
|| num_comps
> 4)
2455 /* Get the first component. */
2456 start
= ffs(output
->component_mask
) - 1;
2458 /* Load the output as int. */
2459 for (int i
= 0; i
< num_comps
; i
++) {
2460 out
[i
] = ac_to_integer(&ctx
->ac
, shader_out
->values
[start
+ i
]);
2463 /* Pack the output. */
2464 LLVMValueRef vdata
= NULL
;
2466 switch (num_comps
) {
2467 case 1: /* as i32 */
2470 case 2: /* as v2i32 */
2471 case 3: /* as v4i32 (aligned to 4) */
2472 out
[3] = LLVMGetUndef(ctx
->ac
.i32
);
2474 case 4: /* as v4i32 */
2475 vdata
= ac_build_gather_values(&ctx
->ac
, out
,
2476 !ac_has_vec3_support(ctx
->ac
.chip_class
, false) ?
2477 util_next_power_of_two(num_comps
) :
2482 ac_build_buffer_store_dword(&ctx
->ac
, so_buffers
[buf
],
2483 vdata
, num_comps
, so_write_offsets
[buf
],
2484 ctx
->ac
.i32_0
, offset
,
2485 ac_glc
| ac_slc
, false);
2489 radv_emit_streamout(struct radv_shader_context
*ctx
, unsigned stream
)
2493 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2494 assert(ctx
->args
->streamout_config
.used
);
2495 LLVMValueRef so_vtx_count
=
2496 ac_build_bfe(&ctx
->ac
,
2497 ac_get_arg(&ctx
->ac
, ctx
->args
->streamout_config
),
2498 LLVMConstInt(ctx
->ac
.i32
, 16, false),
2499 LLVMConstInt(ctx
->ac
.i32
, 7, false), false);
2501 LLVMValueRef tid
= ac_get_thread_id(&ctx
->ac
);
2503 /* can_emit = tid < so_vtx_count; */
2504 LLVMValueRef can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
,
2505 tid
, so_vtx_count
, "");
2507 /* Emit the streamout code conditionally. This actually avoids
2508 * out-of-bounds buffer access. The hw tells us via the SGPR
2509 * (so_vtx_count) which threads are allowed to emit streamout data.
2511 ac_build_ifcc(&ctx
->ac
, can_emit
, 6501);
2513 /* The buffer offset is computed as follows:
2514 * ByteOffset = streamout_offset[buffer_id]*4 +
2515 * (streamout_write_index + thread_id)*stride[buffer_id] +
2518 LLVMValueRef so_write_index
=
2519 ac_get_arg(&ctx
->ac
, ctx
->args
->streamout_write_idx
);
2521 /* Compute (streamout_write_index + thread_id). */
2523 LLVMBuildAdd(ctx
->ac
.builder
, so_write_index
, tid
, "");
2525 /* Load the descriptor and compute the write offset for each
2528 LLVMValueRef so_write_offset
[4] = {};
2529 LLVMValueRef so_buffers
[4] = {};
2530 LLVMValueRef buf_ptr
= ac_get_arg(&ctx
->ac
, ctx
->args
->streamout_buffers
);
2532 for (i
= 0; i
< 4; i
++) {
2533 uint16_t stride
= ctx
->args
->shader_info
->so
.strides
[i
];
2538 LLVMValueRef offset
=
2539 LLVMConstInt(ctx
->ac
.i32
, i
, false);
2541 so_buffers
[i
] = ac_build_load_to_sgpr(&ctx
->ac
,
2544 LLVMValueRef so_offset
=
2545 ac_get_arg(&ctx
->ac
, ctx
->args
->streamout_offset
[i
]);
2547 so_offset
= LLVMBuildMul(ctx
->ac
.builder
, so_offset
,
2548 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
2550 so_write_offset
[i
] =
2551 ac_build_imad(&ctx
->ac
, so_write_index
,
2552 LLVMConstInt(ctx
->ac
.i32
,
2557 /* Write streamout data. */
2558 for (i
= 0; i
< ctx
->args
->shader_info
->so
.num_outputs
; i
++) {
2559 struct radv_shader_output_values shader_out
= {};
2560 struct radv_stream_output
*output
=
2561 &ctx
->args
->shader_info
->so
.outputs
[i
];
2563 if (stream
!= output
->stream
)
2566 for (int j
= 0; j
< 4; j
++) {
2567 shader_out
.values
[j
] =
2568 radv_load_output(ctx
, output
->location
, j
);
2571 radv_emit_stream_output(ctx
, so_buffers
,so_write_offset
,
2572 output
, &shader_out
);
2575 ac_build_endif(&ctx
->ac
, 6501);
2579 radv_build_param_exports(struct radv_shader_context
*ctx
,
2580 struct radv_shader_output_values
*outputs
,
2582 struct radv_vs_output_info
*outinfo
,
2583 bool export_clip_dists
)
2585 unsigned param_count
= 0;
2587 for (unsigned i
= 0; i
< noutput
; i
++) {
2588 unsigned slot_name
= outputs
[i
].slot_name
;
2589 unsigned usage_mask
= outputs
[i
].usage_mask
;
2591 if (slot_name
!= VARYING_SLOT_LAYER
&&
2592 slot_name
!= VARYING_SLOT_PRIMITIVE_ID
&&
2593 slot_name
!= VARYING_SLOT_CLIP_DIST0
&&
2594 slot_name
!= VARYING_SLOT_CLIP_DIST1
&&
2595 slot_name
< VARYING_SLOT_VAR0
)
2598 if ((slot_name
== VARYING_SLOT_CLIP_DIST0
||
2599 slot_name
== VARYING_SLOT_CLIP_DIST1
) && !export_clip_dists
)
2602 radv_export_param(ctx
, param_count
, outputs
[i
].values
, usage_mask
);
2604 assert(i
< ARRAY_SIZE(outinfo
->vs_output_param_offset
));
2605 outinfo
->vs_output_param_offset
[slot_name
] = param_count
++;
2608 outinfo
->param_exports
= param_count
;
2611 /* Generate export instructions for hardware VS shader stage or NGG GS stage
2612 * (position and parameter data only).
2615 radv_llvm_export_vs(struct radv_shader_context
*ctx
,
2616 struct radv_shader_output_values
*outputs
,
2618 struct radv_vs_output_info
*outinfo
,
2619 bool export_clip_dists
)
2621 LLVMValueRef psize_value
= NULL
, layer_value
= NULL
, viewport_value
= NULL
;
2622 struct ac_export_args pos_args
[4] = {};
2623 unsigned pos_idx
, index
;
2626 /* Build position exports */
2627 for (i
= 0; i
< noutput
; i
++) {
2628 switch (outputs
[i
].slot_name
) {
2629 case VARYING_SLOT_POS
:
2630 si_llvm_init_export_args(ctx
, outputs
[i
].values
, 0xf,
2631 V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
2633 case VARYING_SLOT_PSIZ
:
2634 psize_value
= outputs
[i
].values
[0];
2636 case VARYING_SLOT_LAYER
:
2637 layer_value
= outputs
[i
].values
[0];
2639 case VARYING_SLOT_VIEWPORT
:
2640 viewport_value
= outputs
[i
].values
[0];
2642 case VARYING_SLOT_CLIP_DIST0
:
2643 case VARYING_SLOT_CLIP_DIST1
:
2644 index
= 2 + outputs
[i
].slot_index
;
2645 si_llvm_init_export_args(ctx
, outputs
[i
].values
, 0xf,
2646 V_008DFC_SQ_EXP_POS
+ index
,
2654 /* We need to add the position output manually if it's missing. */
2655 if (!pos_args
[0].out
[0]) {
2656 pos_args
[0].enabled_channels
= 0xf; /* writemask */
2657 pos_args
[0].valid_mask
= 0; /* EXEC mask */
2658 pos_args
[0].done
= 0; /* last export? */
2659 pos_args
[0].target
= V_008DFC_SQ_EXP_POS
;
2660 pos_args
[0].compr
= 0; /* COMPR flag */
2661 pos_args
[0].out
[0] = ctx
->ac
.f32_0
; /* X */
2662 pos_args
[0].out
[1] = ctx
->ac
.f32_0
; /* Y */
2663 pos_args
[0].out
[2] = ctx
->ac
.f32_0
; /* Z */
2664 pos_args
[0].out
[3] = ctx
->ac
.f32_1
; /* W */
2667 if (outinfo
->writes_pointsize
||
2668 outinfo
->writes_layer
||
2669 outinfo
->writes_viewport_index
) {
2670 pos_args
[1].enabled_channels
= ((outinfo
->writes_pointsize
== true ? 1 : 0) |
2671 (outinfo
->writes_layer
== true ? 4 : 0));
2672 pos_args
[1].valid_mask
= 0;
2673 pos_args
[1].done
= 0;
2674 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
2675 pos_args
[1].compr
= 0;
2676 pos_args
[1].out
[0] = ctx
->ac
.f32_0
; /* X */
2677 pos_args
[1].out
[1] = ctx
->ac
.f32_0
; /* Y */
2678 pos_args
[1].out
[2] = ctx
->ac
.f32_0
; /* Z */
2679 pos_args
[1].out
[3] = ctx
->ac
.f32_0
; /* W */
2681 if (outinfo
->writes_pointsize
== true)
2682 pos_args
[1].out
[0] = psize_value
;
2683 if (outinfo
->writes_layer
== true)
2684 pos_args
[1].out
[2] = layer_value
;
2685 if (outinfo
->writes_viewport_index
== true) {
2686 if (ctx
->args
->options
->chip_class
>= GFX9
) {
2687 /* GFX9 has the layer in out.z[10:0] and the viewport
2688 * index in out.z[19:16].
2690 LLVMValueRef v
= viewport_value
;
2691 v
= ac_to_integer(&ctx
->ac
, v
);
2692 v
= LLVMBuildShl(ctx
->ac
.builder
, v
,
2693 LLVMConstInt(ctx
->ac
.i32
, 16, false),
2695 v
= LLVMBuildOr(ctx
->ac
.builder
, v
,
2696 ac_to_integer(&ctx
->ac
, pos_args
[1].out
[2]), "");
2698 pos_args
[1].out
[2] = ac_to_float(&ctx
->ac
, v
);
2699 pos_args
[1].enabled_channels
|= 1 << 2;
2701 pos_args
[1].out
[3] = viewport_value
;
2702 pos_args
[1].enabled_channels
|= 1 << 3;
2707 for (i
= 0; i
< 4; i
++) {
2708 if (pos_args
[i
].out
[0])
2709 outinfo
->pos_exports
++;
2712 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
2713 * Setting valid_mask=1 prevents it and has no other effect.
2715 if (ctx
->ac
.family
== CHIP_NAVI10
||
2716 ctx
->ac
.family
== CHIP_NAVI12
||
2717 ctx
->ac
.family
== CHIP_NAVI14
)
2718 pos_args
[0].valid_mask
= 1;
2721 for (i
= 0; i
< 4; i
++) {
2722 if (!pos_args
[i
].out
[0])
2725 /* Specify the target we are exporting */
2726 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
2728 if (pos_idx
== outinfo
->pos_exports
)
2729 /* Specify that this is the last export */
2730 pos_args
[i
].done
= 1;
2732 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
2735 /* Build parameter exports */
2736 radv_build_param_exports(ctx
, outputs
, noutput
, outinfo
, export_clip_dists
);
2740 handle_vs_outputs_post(struct radv_shader_context
*ctx
,
2741 bool export_prim_id
,
2742 bool export_clip_dists
,
2743 struct radv_vs_output_info
*outinfo
)
2745 struct radv_shader_output_values
*outputs
;
2746 unsigned noutput
= 0;
2748 if (ctx
->args
->options
->key
.has_multiview_view_index
) {
2749 LLVMValueRef
* tmp_out
= &ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
2751 for(unsigned i
= 0; i
< 4; ++i
)
2752 ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, i
)] =
2753 ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
2756 LLVMValueRef view_index
= ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.view_index
);
2757 LLVMBuildStore(ctx
->ac
.builder
, ac_to_float(&ctx
->ac
, view_index
), *tmp_out
);
2758 ctx
->output_mask
|= 1ull << VARYING_SLOT_LAYER
;
2761 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
2762 sizeof(outinfo
->vs_output_param_offset
));
2763 outinfo
->pos_exports
= 0;
2765 if (!ctx
->args
->options
->use_ngg_streamout
&&
2766 ctx
->args
->shader_info
->so
.num_outputs
&&
2767 !ctx
->args
->is_gs_copy_shader
) {
2768 /* The GS copy shader emission already emits streamout. */
2769 radv_emit_streamout(ctx
, 0);
2772 /* Allocate a temporary array for the output values. */
2773 unsigned num_outputs
= util_bitcount64(ctx
->output_mask
) + export_prim_id
;
2774 outputs
= malloc(num_outputs
* sizeof(outputs
[0]));
2776 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2777 if (!(ctx
->output_mask
& (1ull << i
)))
2780 outputs
[noutput
].slot_name
= i
;
2781 outputs
[noutput
].slot_index
= i
== VARYING_SLOT_CLIP_DIST1
;
2783 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
2784 !ctx
->args
->is_gs_copy_shader
) {
2785 outputs
[noutput
].usage_mask
=
2786 ctx
->args
->shader_info
->vs
.output_usage_mask
[i
];
2787 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
2788 outputs
[noutput
].usage_mask
=
2789 ctx
->args
->shader_info
->tes
.output_usage_mask
[i
];
2791 assert(ctx
->args
->is_gs_copy_shader
);
2792 outputs
[noutput
].usage_mask
=
2793 ctx
->args
->shader_info
->gs
.output_usage_mask
[i
];
2796 for (unsigned j
= 0; j
< 4; j
++) {
2797 outputs
[noutput
].values
[j
] =
2798 ac_to_float(&ctx
->ac
, radv_load_output(ctx
, i
, j
));
2804 /* Export PrimitiveID. */
2805 if (export_prim_id
) {
2806 outputs
[noutput
].slot_name
= VARYING_SLOT_PRIMITIVE_ID
;
2807 outputs
[noutput
].slot_index
= 0;
2808 outputs
[noutput
].usage_mask
= 0x1;
2809 outputs
[noutput
].values
[0] =
2810 ac_get_arg(&ctx
->ac
, ctx
->args
->vs_prim_id
);
2811 for (unsigned j
= 1; j
< 4; j
++)
2812 outputs
[noutput
].values
[j
] = ctx
->ac
.f32_0
;
2816 radv_llvm_export_vs(ctx
, outputs
, noutput
, outinfo
, export_clip_dists
);
2822 handle_es_outputs_post(struct radv_shader_context
*ctx
,
2823 struct radv_es_output_info
*outinfo
)
2826 LLVMValueRef lds_base
= NULL
;
2828 if (ctx
->ac
.chip_class
>= GFX9
) {
2829 unsigned itemsize_dw
= outinfo
->esgs_itemsize
/ 4;
2830 LLVMValueRef vertex_idx
= ac_get_thread_id(&ctx
->ac
);
2831 LLVMValueRef wave_idx
=
2832 ac_unpack_param(&ctx
->ac
,
2833 ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
), 24, 4);
2834 vertex_idx
= LLVMBuildOr(ctx
->ac
.builder
, vertex_idx
,
2835 LLVMBuildMul(ctx
->ac
.builder
, wave_idx
,
2836 LLVMConstInt(ctx
->ac
.i32
,
2837 ctx
->ac
.wave_size
, false), ""), "");
2838 lds_base
= LLVMBuildMul(ctx
->ac
.builder
, vertex_idx
,
2839 LLVMConstInt(ctx
->ac
.i32
, itemsize_dw
, 0), "");
2842 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2843 LLVMValueRef dw_addr
= NULL
;
2844 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
2845 unsigned output_usage_mask
;
2848 if (!(ctx
->output_mask
& (1ull << i
)))
2851 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2853 ctx
->args
->shader_info
->vs
.output_usage_mask
[i
];
2855 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
2857 ctx
->args
->shader_info
->tes
.output_usage_mask
[i
];
2860 param_index
= shader_io_get_unique_index(i
);
2863 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
2864 LLVMConstInt(ctx
->ac
.i32
, param_index
* 4, false),
2868 for (j
= 0; j
< 4; j
++) {
2869 if (!(output_usage_mask
& (1 << j
)))
2872 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
2873 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
2874 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
2876 if (ctx
->ac
.chip_class
>= GFX9
) {
2877 LLVMValueRef dw_addr_offset
=
2878 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2879 LLVMConstInt(ctx
->ac
.i32
,
2882 ac_lds_store(&ctx
->ac
, dw_addr_offset
, out_val
);
2884 ac_build_buffer_store_dword(&ctx
->ac
,
2888 ac_get_arg(&ctx
->ac
, ctx
->args
->es2gs_offset
),
2889 (4 * param_index
+ j
) * 4,
2890 ac_glc
| ac_slc
, true);
2897 handle_ls_outputs_post(struct radv_shader_context
*ctx
)
2899 LLVMValueRef vertex_id
= ctx
->rel_auto_id
;
2900 uint32_t num_tcs_inputs
= util_last_bit64(ctx
->args
->shader_info
->vs
.ls_outputs_written
);
2901 LLVMValueRef vertex_dw_stride
= LLVMConstInt(ctx
->ac
.i32
, num_tcs_inputs
* 4, false);
2902 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->ac
.builder
, vertex_id
,
2903 vertex_dw_stride
, "");
2905 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2906 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
2908 if (!(ctx
->output_mask
& (1ull << i
)))
2911 int param
= shader_io_get_unique_index(i
);
2912 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_dw_addr
,
2913 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false),
2915 for (unsigned j
= 0; j
< 4; j
++) {
2916 LLVMValueRef value
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
2917 value
= ac_to_integer(&ctx
->ac
, value
);
2918 value
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
2919 ac_lds_store(&ctx
->ac
, dw_addr
, value
);
2920 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
, ctx
->ac
.i32_1
, "");
2925 static LLVMValueRef
get_wave_id_in_tg(struct radv_shader_context
*ctx
)
2927 return ac_unpack_param(&ctx
->ac
,
2928 ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
), 24, 4);
2931 static LLVMValueRef
get_tgsize(struct radv_shader_context
*ctx
)
2933 return ac_unpack_param(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
), 28, 4);
2936 static LLVMValueRef
get_thread_id_in_tg(struct radv_shader_context
*ctx
)
2938 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2940 tmp
= LLVMBuildMul(builder
, get_wave_id_in_tg(ctx
),
2941 LLVMConstInt(ctx
->ac
.i32
, ctx
->ac
.wave_size
, false), "");
2942 return LLVMBuildAdd(builder
, tmp
, ac_get_thread_id(&ctx
->ac
), "");
2945 static LLVMValueRef
ngg_get_vtx_cnt(struct radv_shader_context
*ctx
)
2947 return ac_build_bfe(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->gs_tg_info
),
2948 LLVMConstInt(ctx
->ac
.i32
, 12, false),
2949 LLVMConstInt(ctx
->ac
.i32
, 9, false),
2953 static LLVMValueRef
ngg_get_prim_cnt(struct radv_shader_context
*ctx
)
2955 return ac_build_bfe(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->gs_tg_info
),
2956 LLVMConstInt(ctx
->ac
.i32
, 22, false),
2957 LLVMConstInt(ctx
->ac
.i32
, 9, false),
2961 static LLVMValueRef
ngg_get_ordered_id(struct radv_shader_context
*ctx
)
2963 return ac_build_bfe(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->gs_tg_info
),
2965 LLVMConstInt(ctx
->ac
.i32
, 11, false),
2970 ngg_gs_get_vertex_storage(struct radv_shader_context
*ctx
)
2972 unsigned num_outputs
= util_bitcount64(ctx
->output_mask
);
2974 if (ctx
->args
->options
->key
.has_multiview_view_index
)
2977 LLVMTypeRef elements
[2] = {
2978 LLVMArrayType(ctx
->ac
.i32
, 4 * num_outputs
),
2979 LLVMArrayType(ctx
->ac
.i8
, 4),
2981 LLVMTypeRef type
= LLVMStructTypeInContext(ctx
->ac
.context
, elements
, 2, false);
2982 type
= LLVMPointerType(LLVMArrayType(type
, 0), AC_ADDR_SPACE_LDS
);
2983 return LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->gs_ngg_emit
, type
, "");
2987 * Return a pointer to the LDS storage reserved for the N'th vertex, where N
2988 * is in emit order; that is:
2989 * - during the epilogue, N is the threadidx (relative to the entire threadgroup)
2990 * - during vertex emit, i.e. while the API GS shader invocation is running,
2991 * N = threadidx * gs_max_out_vertices + emitidx
2993 * Goals of the LDS memory layout:
2994 * 1. Eliminate bank conflicts on write for geometry shaders that have all emits
2995 * in uniform control flow
2996 * 2. Eliminate bank conflicts on read for export if, additionally, there is no
2998 * 3. Agnostic to the number of waves (since we don't know it before compiling)
2999 * 4. Allow coalescing of LDS instructions (ds_write_b128 etc.)
3000 * 5. Avoid wasting memory.
3002 * We use an AoS layout due to point 4 (this also helps point 3). In an AoS
3003 * layout, elimination of bank conflicts requires that each vertex occupy an
3004 * odd number of dwords. We use the additional dword to store the output stream
3005 * index as well as a flag to indicate whether this vertex ends a primitive
3006 * for rasterization.
3008 * Swizzling is required to satisfy points 1 and 2 simultaneously.
3010 * Vertices are stored in export order (gsthread * gs_max_out_vertices + emitidx).
3011 * Indices are swizzled in groups of 32, which ensures point 1 without
3012 * disturbing point 2.
3014 * \return an LDS pointer to type {[N x i32], [4 x i8]}
3017 ngg_gs_vertex_ptr(struct radv_shader_context
*ctx
, LLVMValueRef vertexidx
)
3019 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3020 LLVMValueRef storage
= ngg_gs_get_vertex_storage(ctx
);
3022 /* gs_max_out_vertices = 2^(write_stride_2exp) * some odd number */
3023 unsigned write_stride_2exp
= ffs(ctx
->shader
->info
.gs
.vertices_out
) - 1;
3024 if (write_stride_2exp
) {
3026 LLVMBuildLShr(builder
, vertexidx
,
3027 LLVMConstInt(ctx
->ac
.i32
, 5, false), "");
3028 LLVMValueRef swizzle
=
3029 LLVMBuildAnd(builder
, row
,
3030 LLVMConstInt(ctx
->ac
.i32
, (1u << write_stride_2exp
) - 1,
3032 vertexidx
= LLVMBuildXor(builder
, vertexidx
, swizzle
, "");
3035 return ac_build_gep0(&ctx
->ac
, storage
, vertexidx
);
3039 ngg_gs_emit_vertex_ptr(struct radv_shader_context
*ctx
, LLVMValueRef gsthread
,
3040 LLVMValueRef emitidx
)
3042 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3045 tmp
= LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.gs
.vertices_out
, false);
3046 tmp
= LLVMBuildMul(builder
, tmp
, gsthread
, "");
3047 const LLVMValueRef vertexidx
= LLVMBuildAdd(builder
, tmp
, emitidx
, "");
3048 return ngg_gs_vertex_ptr(ctx
, vertexidx
);
3051 /* Send GS Alloc Req message from the first wave of the group to SPI.
3052 * Message payload is:
3053 * - bits 0..10: vertices in group
3054 * - bits 12..22: primitives in group
3056 static void build_sendmsg_gs_alloc_req(struct radv_shader_context
*ctx
,
3057 LLVMValueRef vtx_cnt
,
3058 LLVMValueRef prim_cnt
)
3060 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3063 tmp
= LLVMBuildICmp(builder
, LLVMIntEQ
, get_wave_id_in_tg(ctx
), ctx
->ac
.i32_0
, "");
3064 ac_build_ifcc(&ctx
->ac
, tmp
, 5020);
3066 tmp
= LLVMBuildShl(builder
, prim_cnt
, LLVMConstInt(ctx
->ac
.i32
, 12, false),"");
3067 tmp
= LLVMBuildOr(builder
, tmp
, vtx_cnt
, "");
3068 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_ALLOC_REQ
, tmp
);
3070 ac_build_endif(&ctx
->ac
, 5020);
3074 unsigned num_vertices
;
3075 LLVMValueRef isnull
;
3077 LLVMValueRef index
[3];
3078 LLVMValueRef edgeflag
[3];
3081 static void build_export_prim(struct radv_shader_context
*ctx
,
3082 const struct ngg_prim
*prim
)
3084 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3085 struct ac_export_args args
;
3086 LLVMValueRef vertices
[3];
3087 LLVMValueRef odd
, even
;
3090 tmp
= LLVMBuildZExt(builder
, prim
->isnull
, ctx
->ac
.i32
, "");
3091 args
.out
[0] = LLVMBuildShl(builder
, tmp
, LLVMConstInt(ctx
->ac
.i32
, 31, false), "");
3093 for (unsigned i
= 0; i
< prim
->num_vertices
; ++i
) {
3094 tmp
= LLVMBuildZExt(builder
, prim
->edgeflag
[i
], ctx
->ac
.i32
, "");
3095 tmp
= LLVMBuildShl(builder
, tmp
,
3096 LLVMConstInt(ctx
->ac
.i32
, 9, false), "");
3097 vertices
[i
] = LLVMBuildOr(builder
, prim
->index
[i
], tmp
, "");
3100 switch (prim
->num_vertices
) {
3102 args
.out
[0] = LLVMBuildOr(builder
, args
.out
[0], vertices
[0], "");
3105 tmp
= LLVMBuildShl(builder
, vertices
[1],
3106 LLVMConstInt(ctx
->ac
.i32
, 10, false), "");
3107 tmp
= LLVMBuildOr(builder
, args
.out
[0], tmp
, "");
3108 args
.out
[0] = LLVMBuildOr(builder
, tmp
, vertices
[0], "");
3111 /* Swap vertices if needed to follow drawing order. */
3112 tmp
= LLVMBuildShl(builder
, vertices
[2],
3113 LLVMConstInt(ctx
->ac
.i32
, 20, false), "");
3114 even
= LLVMBuildOr(builder
, args
.out
[0], tmp
, "");
3115 tmp
= LLVMBuildShl(builder
, vertices
[1],
3116 LLVMConstInt(ctx
->ac
.i32
, 10, false), "");
3117 even
= LLVMBuildOr(builder
, even
, tmp
, "");
3118 even
= LLVMBuildOr(builder
, even
, vertices
[0], "");
3120 tmp
= LLVMBuildShl(builder
, vertices
[1],
3121 LLVMConstInt(ctx
->ac
.i32
, 20, false), "");
3122 odd
= LLVMBuildOr(builder
, args
.out
[0], tmp
, "");
3123 tmp
= LLVMBuildShl(builder
, vertices
[2],
3124 LLVMConstInt(ctx
->ac
.i32
, 10, false), "");
3125 odd
= LLVMBuildOr(builder
, odd
, tmp
, "");
3126 odd
= LLVMBuildOr(builder
, odd
, vertices
[0], "");
3128 args
.out
[0] = LLVMBuildSelect(builder
, prim
->swap
, odd
, even
, "");
3131 unreachable("invalid number of vertices");
3134 args
.out
[0] = LLVMBuildBitCast(builder
, args
.out
[0], ctx
->ac
.f32
, "");
3135 args
.out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
3136 args
.out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
3137 args
.out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
3139 args
.target
= V_008DFC_SQ_EXP_PRIM
;
3140 args
.enabled_channels
= 1;
3142 args
.valid_mask
= false;
3145 ac_build_export(&ctx
->ac
, &args
);
3148 static struct radv_stream_output
*
3149 radv_get_stream_output_by_loc(struct radv_streamout_info
*so
, unsigned location
)
3151 for (unsigned i
= 0; i
< so
->num_outputs
; ++i
) {
3152 if (so
->outputs
[i
].location
== location
)
3153 return &so
->outputs
[i
];
3159 static void build_streamout_vertex(struct radv_shader_context
*ctx
,
3160 LLVMValueRef
*so_buffer
, LLVMValueRef
*wg_offset_dw
,
3161 unsigned stream
, LLVMValueRef offset_vtx
,
3162 LLVMValueRef vertexptr
)
3164 struct radv_streamout_info
*so
= &ctx
->args
->shader_info
->so
;
3165 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3166 LLVMValueRef offset
[4] = {};
3169 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
3170 if (!wg_offset_dw
[buffer
])
3173 tmp
= LLVMBuildMul(builder
, offset_vtx
,
3174 LLVMConstInt(ctx
->ac
.i32
, so
->strides
[buffer
], false), "");
3175 tmp
= LLVMBuildAdd(builder
, wg_offset_dw
[buffer
], tmp
, "");
3176 offset
[buffer
] = LLVMBuildShl(builder
, tmp
, LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
3179 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
3180 struct radv_shader_output_values outputs
[AC_LLVM_MAX_OUTPUTS
];
3181 unsigned noutput
= 0;
3182 unsigned out_idx
= 0;
3184 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3185 unsigned output_usage_mask
=
3186 ctx
->args
->shader_info
->gs
.output_usage_mask
[i
];
3187 uint8_t output_stream
=
3188 output_stream
= ctx
->args
->shader_info
->gs
.output_streams
[i
];
3190 if (!(ctx
->output_mask
& (1ull << i
)) ||
3191 output_stream
!= stream
)
3194 outputs
[noutput
].slot_name
= i
;
3195 outputs
[noutput
].slot_index
= i
== VARYING_SLOT_CLIP_DIST1
;
3196 outputs
[noutput
].usage_mask
= output_usage_mask
;
3198 int length
= util_last_bit(output_usage_mask
);
3200 for (unsigned j
= 0; j
< length
; j
++, out_idx
++) {
3201 if (!(output_usage_mask
& (1 << j
)))
3204 tmp
= ac_build_gep0(&ctx
->ac
, vertexptr
,
3205 LLVMConstInt(ctx
->ac
.i32
, out_idx
, false));
3206 outputs
[noutput
].values
[j
] = LLVMBuildLoad(builder
, tmp
, "");
3209 for (unsigned j
= length
; j
< 4; j
++)
3210 outputs
[noutput
].values
[j
] = LLVMGetUndef(ctx
->ac
.f32
);
3215 for (unsigned i
= 0; i
< noutput
; i
++) {
3216 struct radv_stream_output
*output
=
3217 radv_get_stream_output_by_loc(so
, outputs
[i
].slot_name
);
3220 output
->stream
!= stream
)
3223 struct radv_shader_output_values out
= {};
3225 for (unsigned j
= 0; j
< 4; j
++) {
3226 out
.values
[j
] = outputs
[i
].values
[j
];
3229 radv_emit_stream_output(ctx
, so_buffer
, offset
, output
, &out
);
3232 for (unsigned i
= 0; i
< so
->num_outputs
; ++i
) {
3233 struct radv_stream_output
*output
=
3234 &ctx
->args
->shader_info
->so
.outputs
[i
];
3236 if (stream
!= output
->stream
)
3239 struct radv_shader_output_values out
= {};
3241 for (unsigned comp
= 0; comp
< 4; comp
++) {
3242 if (!(output
->component_mask
& (1 << comp
)))
3245 tmp
= ac_build_gep0(&ctx
->ac
, vertexptr
,
3246 LLVMConstInt(ctx
->ac
.i32
, 4 * i
+ comp
, false));
3247 out
.values
[comp
] = LLVMBuildLoad(builder
, tmp
, "");
3250 radv_emit_stream_output(ctx
, so_buffer
, offset
, output
, &out
);
3255 struct ngg_streamout
{
3256 LLVMValueRef num_vertices
;
3258 /* per-thread data */
3259 LLVMValueRef prim_enable
[4]; /* i1 per stream */
3260 LLVMValueRef vertices
[3]; /* [N x i32] addrspace(LDS)* */
3263 LLVMValueRef emit
[4]; /* per-stream emitted primitives (only valid for used streams) */
3267 * Build streamout logic.
3269 * Implies a barrier.
3271 * Writes number of emitted primitives to gs_ngg_scratch[4:7].
3273 * Clobbers gs_ngg_scratch[8:].
3275 static void build_streamout(struct radv_shader_context
*ctx
,
3276 struct ngg_streamout
*nggso
)
3278 struct radv_streamout_info
*so
= &ctx
->args
->shader_info
->so
;
3279 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3280 LLVMValueRef buf_ptr
= ac_get_arg(&ctx
->ac
, ctx
->args
->streamout_buffers
);
3281 LLVMValueRef tid
= get_thread_id_in_tg(ctx
);
3282 LLVMValueRef cond
, tmp
, tmp2
;
3283 LLVMValueRef i32_2
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
3284 LLVMValueRef i32_4
= LLVMConstInt(ctx
->ac
.i32
, 4, false);
3285 LLVMValueRef i32_8
= LLVMConstInt(ctx
->ac
.i32
, 8, false);
3286 LLVMValueRef so_buffer
[4] = {};
3287 unsigned max_num_vertices
= 1 + (nggso
->vertices
[1] ? 1 : 0) +
3288 (nggso
->vertices
[2] ? 1 : 0);
3289 LLVMValueRef prim_stride_dw
[4] = {};
3290 LLVMValueRef prim_stride_dw_vgpr
= LLVMGetUndef(ctx
->ac
.i32
);
3291 int stream_for_buffer
[4] = { -1, -1, -1, -1 };
3292 unsigned bufmask_for_stream
[4] = {};
3293 bool isgs
= ctx
->stage
== MESA_SHADER_GEOMETRY
;
3294 unsigned scratch_emit_base
= isgs
? 4 : 0;
3295 LLVMValueRef scratch_emit_basev
= isgs
? i32_4
: ctx
->ac
.i32_0
;
3296 unsigned scratch_offset_base
= isgs
? 8 : 4;
3297 LLVMValueRef scratch_offset_basev
= isgs
? i32_8
: i32_4
;
3299 ac_llvm_add_target_dep_function_attr(ctx
->main_function
,
3300 "amdgpu-gds-size", 256);
3302 /* Determine the mapping of streamout buffers to vertex streams. */
3303 for (unsigned i
= 0; i
< so
->num_outputs
; ++i
) {
3304 unsigned buf
= so
->outputs
[i
].buffer
;
3305 unsigned stream
= so
->outputs
[i
].stream
;
3306 assert(stream_for_buffer
[buf
] < 0 || stream_for_buffer
[buf
] == stream
);
3307 stream_for_buffer
[buf
] = stream
;
3308 bufmask_for_stream
[stream
] |= 1 << buf
;
3311 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
3312 if (stream_for_buffer
[buffer
] == -1)
3315 assert(so
->strides
[buffer
]);
3317 LLVMValueRef stride_for_buffer
=
3318 LLVMConstInt(ctx
->ac
.i32
, so
->strides
[buffer
], false);
3319 prim_stride_dw
[buffer
] =
3320 LLVMBuildMul(builder
, stride_for_buffer
,
3321 nggso
->num_vertices
, "");
3322 prim_stride_dw_vgpr
= ac_build_writelane(
3323 &ctx
->ac
, prim_stride_dw_vgpr
, prim_stride_dw
[buffer
],
3324 LLVMConstInt(ctx
->ac
.i32
, buffer
, false));
3326 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, buffer
, false);
3327 so_buffer
[buffer
] = ac_build_load_to_sgpr(&ctx
->ac
, buf_ptr
,
3331 cond
= LLVMBuildICmp(builder
, LLVMIntEQ
, get_wave_id_in_tg(ctx
), ctx
->ac
.i32_0
, "");
3332 ac_build_ifcc(&ctx
->ac
, cond
, 5200);
3334 LLVMTypeRef gdsptr
= LLVMPointerType(ctx
->ac
.i32
, AC_ADDR_SPACE_GDS
);
3335 LLVMValueRef gdsbase
= LLVMBuildIntToPtr(builder
, ctx
->ac
.i32_0
, gdsptr
, "");
3337 /* Advance the streamout offsets in GDS. */
3338 LLVMValueRef offsets_vgpr
= ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.i32
, "");
3339 LLVMValueRef generated_by_stream_vgpr
= ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.i32
, "");
3341 cond
= LLVMBuildICmp(builder
, LLVMIntULT
, ac_get_thread_id(&ctx
->ac
), i32_4
, "");
3342 ac_build_ifcc(&ctx
->ac
, cond
, 5210);
3344 /* Fetch the number of generated primitives and store
3345 * it in GDS for later use.
3348 tmp
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, tid
);
3349 tmp
= LLVMBuildLoad(builder
, tmp
, "");
3351 tmp
= ac_build_writelane(&ctx
->ac
, ctx
->ac
.i32_0
,
3352 ngg_get_prim_cnt(ctx
), ctx
->ac
.i32_0
);
3354 LLVMBuildStore(builder
, tmp
, generated_by_stream_vgpr
);
3356 unsigned swizzle
[4];
3357 int unused_stream
= -1;
3358 for (unsigned stream
= 0; stream
< 4; ++stream
) {
3359 if (!ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
]) {
3360 unused_stream
= stream
;
3364 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
3365 if (stream_for_buffer
[buffer
] >= 0) {
3366 swizzle
[buffer
] = stream_for_buffer
[buffer
];
3368 assert(unused_stream
>= 0);
3369 swizzle
[buffer
] = unused_stream
;
3373 tmp
= ac_build_quad_swizzle(&ctx
->ac
, tmp
,
3374 swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
3375 tmp
= LLVMBuildMul(builder
, tmp
, prim_stride_dw_vgpr
, "");
3377 LLVMValueRef args
[] = {
3378 LLVMBuildIntToPtr(builder
, ngg_get_ordered_id(ctx
), gdsptr
, ""),
3380 ctx
->ac
.i32_0
, // ordering
3381 ctx
->ac
.i32_0
, // scope
3382 ctx
->ac
.i1false
, // isVolatile
3383 LLVMConstInt(ctx
->ac
.i32
, 4 << 24, false), // OA index
3384 ctx
->ac
.i1true
, // wave release
3385 ctx
->ac
.i1true
, // wave done
3388 tmp
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.ds.ordered.add",
3389 ctx
->ac
.i32
, args
, ARRAY_SIZE(args
), 0);
3391 /* Keep offsets in a VGPR for quick retrieval via readlane by
3392 * the first wave for bounds checking, and also store in LDS
3393 * for retrieval by all waves later. */
3394 LLVMBuildStore(builder
, tmp
, offsets_vgpr
);
3396 tmp2
= LLVMBuildAdd(builder
, ac_get_thread_id(&ctx
->ac
),
3397 scratch_offset_basev
, "");
3398 tmp2
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, tmp2
);
3399 LLVMBuildStore(builder
, tmp
, tmp2
);
3401 ac_build_endif(&ctx
->ac
, 5210);
3403 /* Determine the max emit per buffer. This is done via the SALU, in part
3404 * because LLVM can't generate divide-by-multiply if we try to do this
3405 * via VALU with one lane per buffer.
3407 LLVMValueRef max_emit
[4] = {};
3408 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
3409 if (stream_for_buffer
[buffer
] == -1)
3412 /* Compute the streamout buffer size in DWORD. */
3413 LLVMValueRef bufsize_dw
=
3414 LLVMBuildLShr(builder
,
3415 LLVMBuildExtractElement(builder
, so_buffer
[buffer
], i32_2
, ""),
3418 /* Load the streamout buffer offset from GDS. */
3419 tmp
= LLVMBuildLoad(builder
, offsets_vgpr
, "");
3420 LLVMValueRef offset_dw
=
3421 ac_build_readlane(&ctx
->ac
, tmp
,
3422 LLVMConstInt(ctx
->ac
.i32
, buffer
, false));
3424 /* Compute the remaining size to emit. */
3425 LLVMValueRef remaining_dw
=
3426 LLVMBuildSub(builder
, bufsize_dw
, offset_dw
, "");
3427 tmp
= LLVMBuildUDiv(builder
, remaining_dw
,
3428 prim_stride_dw
[buffer
], "");
3430 cond
= LLVMBuildICmp(builder
, LLVMIntULT
,
3431 bufsize_dw
, offset_dw
, "");
3432 max_emit
[buffer
] = LLVMBuildSelect(builder
, cond
,
3433 ctx
->ac
.i32_0
, tmp
, "");
3436 /* Determine the number of emitted primitives per stream and fixup the
3437 * GDS counter if necessary.
3439 * This is complicated by the fact that a single stream can emit to
3440 * multiple buffers (but luckily not vice versa).
3442 LLVMValueRef emit_vgpr
= ctx
->ac
.i32_0
;
3444 for (unsigned stream
= 0; stream
< 4; ++stream
) {
3445 if (!ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
])
3448 /* Load the number of generated primitives from GDS and
3449 * determine that number for the given stream.
3451 tmp
= LLVMBuildLoad(builder
, generated_by_stream_vgpr
, "");
3452 LLVMValueRef generated
=
3453 ac_build_readlane(&ctx
->ac
, tmp
,
3454 LLVMConstInt(ctx
->ac
.i32
, stream
, false));
3457 /* Compute the number of emitted primitives. */
3458 LLVMValueRef emit
= generated
;
3459 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
3460 if (stream_for_buffer
[buffer
] == stream
)
3461 emit
= ac_build_umin(&ctx
->ac
, emit
, max_emit
[buffer
]);
3464 /* Store the number of emitted primitives for that
3467 emit_vgpr
= ac_build_writelane(&ctx
->ac
, emit_vgpr
, emit
,
3468 LLVMConstInt(ctx
->ac
.i32
, stream
, false));
3470 /* Fixup the offset using a plain GDS atomic if we overflowed. */
3471 cond
= LLVMBuildICmp(builder
, LLVMIntULT
, emit
, generated
, "");
3472 ac_build_ifcc(&ctx
->ac
, cond
, 5221); /* scalar branch */
3473 tmp
= LLVMBuildLShr(builder
,
3474 LLVMConstInt(ctx
->ac
.i32
, bufmask_for_stream
[stream
], false),
3475 ac_get_thread_id(&ctx
->ac
), "");
3476 tmp
= LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
3477 ac_build_ifcc(&ctx
->ac
, tmp
, 5222);
3479 tmp
= LLVMBuildSub(builder
, generated
, emit
, "");
3480 tmp
= LLVMBuildMul(builder
, tmp
, prim_stride_dw_vgpr
, "");
3481 tmp2
= LLVMBuildGEP(builder
, gdsbase
, &tid
, 1, "");
3482 LLVMBuildAtomicRMW(builder
, LLVMAtomicRMWBinOpSub
, tmp2
, tmp
,
3483 LLVMAtomicOrderingMonotonic
, false);
3485 ac_build_endif(&ctx
->ac
, 5222);
3486 ac_build_endif(&ctx
->ac
, 5221);
3489 /* Store the number of emitted primitives to LDS for later use. */
3490 cond
= LLVMBuildICmp(builder
, LLVMIntULT
, ac_get_thread_id(&ctx
->ac
), i32_4
, "");
3491 ac_build_ifcc(&ctx
->ac
, cond
, 5225);
3493 tmp
= LLVMBuildAdd(builder
, ac_get_thread_id(&ctx
->ac
),
3494 scratch_emit_basev
, "");
3495 tmp
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, tmp
);
3496 LLVMBuildStore(builder
, emit_vgpr
, tmp
);
3498 ac_build_endif(&ctx
->ac
, 5225);
3500 ac_build_endif(&ctx
->ac
, 5200);
3502 /* Determine the workgroup-relative per-thread / primitive offset into
3503 * the streamout buffers */
3504 struct ac_wg_scan primemit_scan
[4] = {};
3507 for (unsigned stream
= 0; stream
< 4; ++stream
) {
3508 if (!ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
])
3511 primemit_scan
[stream
].enable_exclusive
= true;
3512 primemit_scan
[stream
].op
= nir_op_iadd
;
3513 primemit_scan
[stream
].src
= nggso
->prim_enable
[stream
];
3514 primemit_scan
[stream
].scratch
=
3515 ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
,
3516 LLVMConstInt(ctx
->ac
.i32
, 12 + 8 * stream
, false));
3517 primemit_scan
[stream
].waveidx
= get_wave_id_in_tg(ctx
);
3518 primemit_scan
[stream
].numwaves
= get_tgsize(ctx
);
3519 primemit_scan
[stream
].maxwaves
= 8;
3520 ac_build_wg_scan_top(&ctx
->ac
, &primemit_scan
[stream
]);
3524 ac_build_s_barrier(&ctx
->ac
);
3526 /* Fetch the per-buffer offsets and per-stream emit counts in all waves. */
3527 LLVMValueRef wgoffset_dw
[4] = {};
3530 LLVMValueRef scratch_vgpr
;
3532 tmp
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, ac_get_thread_id(&ctx
->ac
));
3533 scratch_vgpr
= LLVMBuildLoad(builder
, tmp
, "");
3535 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
3536 if (stream_for_buffer
[buffer
] >= 0) {
3537 wgoffset_dw
[buffer
] = ac_build_readlane(
3538 &ctx
->ac
, scratch_vgpr
,
3539 LLVMConstInt(ctx
->ac
.i32
, scratch_offset_base
+ buffer
, false));
3543 for (unsigned stream
= 0; stream
< 4; ++stream
) {
3544 if (ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
]) {
3545 nggso
->emit
[stream
] = ac_build_readlane(
3546 &ctx
->ac
, scratch_vgpr
,
3547 LLVMConstInt(ctx
->ac
.i32
, scratch_emit_base
+ stream
, false));
3552 /* Write out primitive data */
3553 for (unsigned stream
= 0; stream
< 4; ++stream
) {
3554 if (!ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
])
3558 ac_build_wg_scan_bottom(&ctx
->ac
, &primemit_scan
[stream
]);
3560 primemit_scan
[stream
].result_exclusive
= tid
;
3563 cond
= LLVMBuildICmp(builder
, LLVMIntULT
,
3564 primemit_scan
[stream
].result_exclusive
,
3565 nggso
->emit
[stream
], "");
3566 cond
= LLVMBuildAnd(builder
, cond
, nggso
->prim_enable
[stream
], "");
3567 ac_build_ifcc(&ctx
->ac
, cond
, 5240);
3569 LLVMValueRef offset_vtx
=
3570 LLVMBuildMul(builder
, primemit_scan
[stream
].result_exclusive
,
3571 nggso
->num_vertices
, "");
3573 for (unsigned i
= 0; i
< max_num_vertices
; ++i
) {
3574 cond
= LLVMBuildICmp(builder
, LLVMIntULT
,
3575 LLVMConstInt(ctx
->ac
.i32
, i
, false),
3576 nggso
->num_vertices
, "");
3577 ac_build_ifcc(&ctx
->ac
, cond
, 5241);
3578 build_streamout_vertex(ctx
, so_buffer
, wgoffset_dw
,
3579 stream
, offset_vtx
, nggso
->vertices
[i
]);
3580 ac_build_endif(&ctx
->ac
, 5241);
3581 offset_vtx
= LLVMBuildAdd(builder
, offset_vtx
, ctx
->ac
.i32_1
, "");
3584 ac_build_endif(&ctx
->ac
, 5240);
3588 static unsigned ngg_nogs_vertex_size(struct radv_shader_context
*ctx
)
3590 unsigned lds_vertex_size
= 0;
3592 if (ctx
->args
->shader_info
->so
.num_outputs
)
3593 lds_vertex_size
= 4 * ctx
->args
->shader_info
->so
.num_outputs
+ 1;
3595 return lds_vertex_size
;
3599 * Returns an `[N x i32] addrspace(LDS)*` pointing at contiguous LDS storage
3600 * for the vertex outputs.
3602 static LLVMValueRef
ngg_nogs_vertex_ptr(struct radv_shader_context
*ctx
,
3605 /* The extra dword is used to avoid LDS bank conflicts. */
3606 unsigned vertex_size
= ngg_nogs_vertex_size(ctx
);
3607 LLVMTypeRef ai32
= LLVMArrayType(ctx
->ac
.i32
, vertex_size
);
3608 LLVMTypeRef pai32
= LLVMPointerType(ai32
, AC_ADDR_SPACE_LDS
);
3609 LLVMValueRef tmp
= LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->esgs_ring
, pai32
, "");
3610 return LLVMBuildGEP(ctx
->ac
.builder
, tmp
, &vtxid
, 1, "");
3614 handle_ngg_outputs_post_1(struct radv_shader_context
*ctx
)
3616 struct radv_streamout_info
*so
= &ctx
->args
->shader_info
->so
;
3617 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3618 LLVMValueRef vertex_ptr
= NULL
;
3619 LLVMValueRef tmp
, tmp2
;
3621 assert((ctx
->stage
== MESA_SHADER_VERTEX
||
3622 ctx
->stage
== MESA_SHADER_TESS_EVAL
) && !ctx
->args
->is_gs_copy_shader
);
3624 if (!ctx
->args
->shader_info
->so
.num_outputs
)
3627 vertex_ptr
= ngg_nogs_vertex_ptr(ctx
, get_thread_id_in_tg(ctx
));
3629 for (unsigned i
= 0; i
< so
->num_outputs
; ++i
) {
3630 struct radv_stream_output
*output
=
3631 &ctx
->args
->shader_info
->so
.outputs
[i
];
3633 unsigned loc
= output
->location
;
3635 for (unsigned comp
= 0; comp
< 4; comp
++) {
3636 if (!(output
->component_mask
& (1 << comp
)))
3639 tmp
= ac_build_gep0(&ctx
->ac
, vertex_ptr
,
3640 LLVMConstInt(ctx
->ac
.i32
, 4 * i
+ comp
, false));
3641 tmp2
= LLVMBuildLoad(builder
,
3642 ctx
->abi
.outputs
[4 * loc
+ comp
], "");
3643 tmp2
= ac_to_integer(&ctx
->ac
, tmp2
);
3644 LLVMBuildStore(builder
, tmp2
, tmp
);
3650 handle_ngg_outputs_post_2(struct radv_shader_context
*ctx
)
3652 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3655 assert((ctx
->stage
== MESA_SHADER_VERTEX
||
3656 ctx
->stage
== MESA_SHADER_TESS_EVAL
) && !ctx
->args
->is_gs_copy_shader
);
3658 LLVMValueRef prims_in_wave
= ac_unpack_param(&ctx
->ac
,
3659 ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
), 8, 8);
3660 LLVMValueRef vtx_in_wave
= ac_unpack_param(&ctx
->ac
,
3661 ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
), 0, 8);
3662 LLVMValueRef is_gs_thread
= LLVMBuildICmp(builder
, LLVMIntULT
,
3663 ac_get_thread_id(&ctx
->ac
), prims_in_wave
, "");
3664 LLVMValueRef is_es_thread
= LLVMBuildICmp(builder
, LLVMIntULT
,
3665 ac_get_thread_id(&ctx
->ac
), vtx_in_wave
, "");
3666 LLVMValueRef vtxindex
[] = {
3667 ac_unpack_param(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->gs_vtx_offset
[0]), 0, 16),
3668 ac_unpack_param(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->gs_vtx_offset
[0]), 16, 16),
3669 ac_unpack_param(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->gs_vtx_offset
[2]), 0, 16),
3672 /* Determine the number of vertices per primitive. */
3673 unsigned num_vertices
;
3674 LLVMValueRef num_vertices_val
;
3676 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
3677 LLVMValueRef outprim_val
=
3678 LLVMConstInt(ctx
->ac
.i32
,
3679 ctx
->args
->options
->key
.vs
.outprim
, false);
3680 num_vertices_val
= LLVMBuildAdd(builder
, outprim_val
,
3682 num_vertices
= 3; /* TODO: optimize for points & lines */
3684 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
3686 if (ctx
->shader
->info
.tess
.point_mode
)
3688 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
3693 num_vertices_val
= LLVMConstInt(ctx
->ac
.i32
, num_vertices
, false);
3697 if (ctx
->args
->shader_info
->so
.num_outputs
) {
3698 struct ngg_streamout nggso
= {};
3700 nggso
.num_vertices
= num_vertices_val
;
3701 nggso
.prim_enable
[0] = is_gs_thread
;
3703 for (unsigned i
= 0; i
< num_vertices
; ++i
)
3704 nggso
.vertices
[i
] = ngg_nogs_vertex_ptr(ctx
, vtxindex
[i
]);
3706 build_streamout(ctx
, &nggso
);
3709 /* Copy Primitive IDs from GS threads to the LDS address corresponding
3710 * to the ES thread of the provoking vertex.
3712 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
3713 ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
3714 if (ctx
->args
->shader_info
->so
.num_outputs
)
3715 ac_build_s_barrier(&ctx
->ac
);
3717 ac_build_ifcc(&ctx
->ac
, is_gs_thread
, 5400);
3718 /* Extract the PROVOKING_VTX_INDEX field. */
3719 LLVMValueRef provoking_vtx_in_prim
=
3720 LLVMConstInt(ctx
->ac
.i32
, 0, false);
3722 /* provoking_vtx_index = vtxindex[provoking_vtx_in_prim]; */
3723 LLVMValueRef indices
= ac_build_gather_values(&ctx
->ac
, vtxindex
, 3);
3724 LLVMValueRef provoking_vtx_index
=
3725 LLVMBuildExtractElement(builder
, indices
, provoking_vtx_in_prim
, "");
3727 LLVMBuildStore(builder
, ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.gs_prim_id
),
3728 ac_build_gep0(&ctx
->ac
, ctx
->esgs_ring
, provoking_vtx_index
));
3729 ac_build_endif(&ctx
->ac
, 5400);
3732 /* TODO: primitive culling */
3734 build_sendmsg_gs_alloc_req(ctx
, ngg_get_vtx_cnt(ctx
), ngg_get_prim_cnt(ctx
));
3736 /* TODO: streamout queries */
3737 /* Export primitive data to the index buffer. Format is:
3738 * - bits 0..8: index 0
3739 * - bit 9: edge flag 0
3740 * - bits 10..18: index 1
3741 * - bit 19: edge flag 1
3742 * - bits 20..28: index 2
3743 * - bit 29: edge flag 2
3744 * - bit 31: null primitive (skip)
3746 * For the first version, we will always build up all three indices
3747 * independent of the primitive type. The additional garbage data
3750 * TODO: culling depends on the primitive type, so can have some
3753 ac_build_ifcc(&ctx
->ac
, is_gs_thread
, 6001);
3755 struct ngg_prim prim
= {};
3757 prim
.num_vertices
= num_vertices
;
3758 prim
.isnull
= ctx
->ac
.i1false
;
3759 prim
.swap
= ctx
->ac
.i1false
;
3760 memcpy(prim
.index
, vtxindex
, sizeof(vtxindex
[0]) * 3);
3762 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
3763 tmp
= LLVMBuildLShr(builder
,
3764 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.gs_invocation_id
),
3765 LLVMConstInt(ctx
->ac
.i32
, 8 + i
, false), "");
3766 prim
.edgeflag
[i
] = LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
3769 build_export_prim(ctx
, &prim
);
3771 ac_build_endif(&ctx
->ac
, 6001);
3773 /* Export per-vertex data (positions and parameters). */
3774 ac_build_ifcc(&ctx
->ac
, is_es_thread
, 6002);
3776 struct radv_vs_output_info
*outinfo
=
3777 ctx
->stage
== MESA_SHADER_TESS_EVAL
?
3778 &ctx
->args
->shader_info
->tes
.outinfo
: &ctx
->args
->shader_info
->vs
.outinfo
;
3780 /* Exporting the primitive ID is handled below. */
3781 /* TODO: use the new VS export path */
3782 handle_vs_outputs_post(ctx
, false,
3783 ctx
->args
->options
->key
.vs_common_out
.export_clip_dists
,
3786 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
3787 unsigned param_count
= outinfo
->param_exports
;
3788 LLVMValueRef values
[4];
3790 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
3791 /* Wait for GS stores to finish. */
3792 ac_build_s_barrier(&ctx
->ac
);
3794 tmp
= ac_build_gep0(&ctx
->ac
, ctx
->esgs_ring
,
3795 get_thread_id_in_tg(ctx
));
3796 values
[0] = LLVMBuildLoad(builder
, tmp
, "");
3798 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
3799 values
[0] = ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.tes_patch_id
);
3802 values
[0] = ac_to_float(&ctx
->ac
, values
[0]);
3803 for (unsigned j
= 1; j
< 4; j
++)
3804 values
[j
] = ctx
->ac
.f32_0
;
3806 radv_export_param(ctx
, param_count
, values
, 0x1);
3808 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
++;
3809 outinfo
->param_exports
= param_count
;
3812 ac_build_endif(&ctx
->ac
, 6002);
3815 static void gfx10_ngg_gs_emit_prologue(struct radv_shader_context
*ctx
)
3817 /* Zero out the part of LDS scratch that is used to accumulate the
3818 * per-stream generated primitive count.
3820 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3821 LLVMValueRef scratchptr
= ctx
->gs_ngg_scratch
;
3822 LLVMValueRef tid
= get_thread_id_in_tg(ctx
);
3823 LLVMBasicBlockRef merge_block
;
3826 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
->ac
.builder
));
3827 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
3828 merge_block
= LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
3830 cond
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
3831 LLVMBuildCondBr(ctx
->ac
.builder
, cond
, then_block
, merge_block
);
3832 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, then_block
);
3834 LLVMValueRef ptr
= ac_build_gep0(&ctx
->ac
, scratchptr
, tid
);
3835 LLVMBuildStore(builder
, ctx
->ac
.i32_0
, ptr
);
3837 LLVMBuildBr(ctx
->ac
.builder
, merge_block
);
3838 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, merge_block
);
3840 ac_build_s_barrier(&ctx
->ac
);
3843 static void gfx10_ngg_gs_emit_epilogue_1(struct radv_shader_context
*ctx
)
3845 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3846 LLVMValueRef i8_0
= LLVMConstInt(ctx
->ac
.i8
, 0, false);
3849 /* Zero out remaining (non-emitted) primitive flags.
3851 * Note: Alternatively, we could pass the relevant gs_next_vertex to
3852 * the emit threads via LDS. This is likely worse in the expected
3853 * typical case where each GS thread emits the full set of
3856 for (unsigned stream
= 0; stream
< 4; ++stream
) {
3857 unsigned num_components
;
3860 ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
];
3861 if (!num_components
)
3864 const LLVMValueRef gsthread
= get_thread_id_in_tg(ctx
);
3866 ac_build_bgnloop(&ctx
->ac
, 5100);
3868 const LLVMValueRef vertexidx
=
3869 LLVMBuildLoad(builder
, ctx
->gs_next_vertex
[stream
], "");
3870 tmp
= LLVMBuildICmp(builder
, LLVMIntUGE
, vertexidx
,
3871 LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.gs
.vertices_out
, false), "");
3872 ac_build_ifcc(&ctx
->ac
, tmp
, 5101);
3873 ac_build_break(&ctx
->ac
);
3874 ac_build_endif(&ctx
->ac
, 5101);
3876 tmp
= LLVMBuildAdd(builder
, vertexidx
, ctx
->ac
.i32_1
, "");
3877 LLVMBuildStore(builder
, tmp
, ctx
->gs_next_vertex
[stream
]);
3879 tmp
= ngg_gs_emit_vertex_ptr(ctx
, gsthread
, vertexidx
);
3880 LLVMValueRef gep_idx
[3] = {
3881 ctx
->ac
.i32_0
, /* implied C-style array */
3882 ctx
->ac
.i32_1
, /* second entry of struct */
3883 LLVMConstInt(ctx
->ac
.i32
, stream
, false),
3885 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3886 LLVMBuildStore(builder
, i8_0
, tmp
);
3888 ac_build_endloop(&ctx
->ac
, 5100);
3891 /* Accumulate generated primitives counts across the entire threadgroup. */
3892 for (unsigned stream
= 0; stream
< 4; ++stream
) {
3893 unsigned num_components
;
3896 ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
];
3897 if (!num_components
)
3900 LLVMValueRef numprims
=
3901 LLVMBuildLoad(builder
, ctx
->gs_generated_prims
[stream
], "");
3902 numprims
= ac_build_reduce(&ctx
->ac
, numprims
, nir_op_iadd
, ctx
->ac
.wave_size
);
3904 tmp
= LLVMBuildICmp(builder
, LLVMIntEQ
, ac_get_thread_id(&ctx
->ac
), ctx
->ac
.i32_0
, "");
3905 ac_build_ifcc(&ctx
->ac
, tmp
, 5105);
3907 LLVMBuildAtomicRMW(builder
, LLVMAtomicRMWBinOpAdd
,
3908 ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
,
3909 LLVMConstInt(ctx
->ac
.i32
, stream
, false)),
3910 numprims
, LLVMAtomicOrderingMonotonic
, false);
3912 ac_build_endif(&ctx
->ac
, 5105);
3916 static void gfx10_ngg_gs_emit_epilogue_2(struct radv_shader_context
*ctx
)
3918 const unsigned verts_per_prim
= si_conv_gl_prim_to_vertices(ctx
->shader
->info
.gs
.output_primitive
);
3919 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3920 LLVMValueRef tmp
, tmp2
;
3922 ac_build_s_barrier(&ctx
->ac
);
3924 const LLVMValueRef tid
= get_thread_id_in_tg(ctx
);
3925 LLVMValueRef num_emit_threads
= ngg_get_prim_cnt(ctx
);
3928 if (ctx
->args
->shader_info
->so
.num_outputs
) {
3929 struct ngg_streamout nggso
= {};
3931 nggso
.num_vertices
= LLVMConstInt(ctx
->ac
.i32
, verts_per_prim
, false);
3933 LLVMValueRef vertexptr
= ngg_gs_vertex_ptr(ctx
, tid
);
3934 for (unsigned stream
= 0; stream
< 4; ++stream
) {
3935 if (!ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
])
3938 LLVMValueRef gep_idx
[3] = {
3939 ctx
->ac
.i32_0
, /* implicit C-style array */
3940 ctx
->ac
.i32_1
, /* second value of struct */
3941 LLVMConstInt(ctx
->ac
.i32
, stream
, false),
3943 tmp
= LLVMBuildGEP(builder
, vertexptr
, gep_idx
, 3, "");
3944 tmp
= LLVMBuildLoad(builder
, tmp
, "");
3945 tmp
= LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
3946 tmp2
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, num_emit_threads
, "");
3947 nggso
.prim_enable
[stream
] = LLVMBuildAnd(builder
, tmp
, tmp2
, "");
3950 for (unsigned i
= 0; i
< verts_per_prim
; ++i
) {
3951 tmp
= LLVMBuildSub(builder
, tid
,
3952 LLVMConstInt(ctx
->ac
.i32
, verts_per_prim
- i
- 1, false), "");
3953 tmp
= ngg_gs_vertex_ptr(ctx
, tmp
);
3954 nggso
.vertices
[i
] = ac_build_gep0(&ctx
->ac
, tmp
, ctx
->ac
.i32_0
);
3957 build_streamout(ctx
, &nggso
);
3962 /* Determine vertex liveness. */
3963 LLVMValueRef vertliveptr
= ac_build_alloca(&ctx
->ac
, ctx
->ac
.i1
, "vertexlive");
3965 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, num_emit_threads
, "");
3966 ac_build_ifcc(&ctx
->ac
, tmp
, 5120);
3968 for (unsigned i
= 0; i
< verts_per_prim
; ++i
) {
3969 const LLVMValueRef primidx
=
3970 LLVMBuildAdd(builder
, tid
,
3971 LLVMConstInt(ctx
->ac
.i32
, i
, false), "");
3974 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, primidx
, num_emit_threads
, "");
3975 ac_build_ifcc(&ctx
->ac
, tmp
, 5121 + i
);
3978 /* Load primitive liveness */
3979 tmp
= ngg_gs_vertex_ptr(ctx
, primidx
);
3980 LLVMValueRef gep_idx
[3] = {
3981 ctx
->ac
.i32_0
, /* implicit C-style array */
3982 ctx
->ac
.i32_1
, /* second value of struct */
3983 ctx
->ac
.i32_0
, /* stream 0 */
3985 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3986 tmp
= LLVMBuildLoad(builder
, tmp
, "");
3987 const LLVMValueRef primlive
=
3988 LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
3990 tmp
= LLVMBuildLoad(builder
, vertliveptr
, "");
3991 tmp
= LLVMBuildOr(builder
, tmp
, primlive
, ""),
3992 LLVMBuildStore(builder
, tmp
, vertliveptr
);
3995 ac_build_endif(&ctx
->ac
, 5121 + i
);
3998 ac_build_endif(&ctx
->ac
, 5120);
4000 /* Inclusive scan addition across the current wave. */
4001 LLVMValueRef vertlive
= LLVMBuildLoad(builder
, vertliveptr
, "");
4002 struct ac_wg_scan vertlive_scan
= {};
4003 vertlive_scan
.op
= nir_op_iadd
;
4004 vertlive_scan
.enable_reduce
= true;
4005 vertlive_scan
.enable_exclusive
= true;
4006 vertlive_scan
.src
= vertlive
;
4007 vertlive_scan
.scratch
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, ctx
->ac
.i32_0
);
4008 vertlive_scan
.waveidx
= get_wave_id_in_tg(ctx
);
4009 vertlive_scan
.numwaves
= get_tgsize(ctx
);
4010 vertlive_scan
.maxwaves
= 8;
4012 ac_build_wg_scan(&ctx
->ac
, &vertlive_scan
);
4014 /* Skip all exports (including index exports) when possible. At least on
4015 * early gfx10 revisions this is also to avoid hangs.
4017 LLVMValueRef have_exports
=
4018 LLVMBuildICmp(builder
, LLVMIntNE
, vertlive_scan
.result_reduce
, ctx
->ac
.i32_0
, "");
4020 LLVMBuildSelect(builder
, have_exports
, num_emit_threads
, ctx
->ac
.i32_0
, "");
4022 /* Allocate export space. Send this message as early as possible, to
4023 * hide the latency of the SQ <-> SPI roundtrip.
4025 * Note: We could consider compacting primitives for export as well.
4026 * PA processes 1 non-null prim / clock, but it fetches 4 DW of
4027 * prim data per clock and skips null primitives at no additional
4028 * cost. So compacting primitives can only be beneficial when
4029 * there are 4 or more contiguous null primitives in the export
4030 * (in the common case of single-dword prim exports).
4032 build_sendmsg_gs_alloc_req(ctx
, vertlive_scan
.result_reduce
, num_emit_threads
);
4034 /* Setup the reverse vertex compaction permutation. We re-use stream 1
4035 * of the primitive liveness flags, relying on the fact that each
4036 * threadgroup can have at most 256 threads. */
4037 ac_build_ifcc(&ctx
->ac
, vertlive
, 5130);
4039 tmp
= ngg_gs_vertex_ptr(ctx
, vertlive_scan
.result_exclusive
);
4040 LLVMValueRef gep_idx
[3] = {
4041 ctx
->ac
.i32_0
, /* implicit C-style array */
4042 ctx
->ac
.i32_1
, /* second value of struct */
4043 ctx
->ac
.i32_1
, /* stream 1 */
4045 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
4046 tmp2
= LLVMBuildTrunc(builder
, tid
, ctx
->ac
.i8
, "");
4047 LLVMBuildStore(builder
, tmp2
, tmp
);
4049 ac_build_endif(&ctx
->ac
, 5130);
4051 ac_build_s_barrier(&ctx
->ac
);
4053 /* Export primitive data */
4054 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, num_emit_threads
, "");
4055 ac_build_ifcc(&ctx
->ac
, tmp
, 5140);
4057 struct ngg_prim prim
= {};
4058 prim
.num_vertices
= verts_per_prim
;
4060 tmp
= ngg_gs_vertex_ptr(ctx
, tid
);
4061 LLVMValueRef gep_idx
[3] = {
4062 ctx
->ac
.i32_0
, /* implicit C-style array */
4063 ctx
->ac
.i32_1
, /* second value of struct */
4064 ctx
->ac
.i32_0
, /* primflag */
4066 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
4067 tmp
= LLVMBuildLoad(builder
, tmp
, "");
4068 prim
.isnull
= LLVMBuildICmp(builder
, LLVMIntEQ
, tmp
,
4069 LLVMConstInt(ctx
->ac
.i8
, 0, false), "");
4070 prim
.swap
= LLVMBuildICmp(builder
, LLVMIntEQ
,
4071 LLVMBuildAnd(builder
, tid
, LLVMConstInt(ctx
->ac
.i32
, 1, false), ""),
4072 LLVMConstInt(ctx
->ac
.i32
, 1, false), "");
4074 for (unsigned i
= 0; i
< verts_per_prim
; ++i
) {
4075 prim
.index
[i
] = LLVMBuildSub(builder
, vertlive_scan
.result_exclusive
,
4076 LLVMConstInt(ctx
->ac
.i32
, verts_per_prim
- i
- 1, false), "");
4077 prim
.edgeflag
[i
] = ctx
->ac
.i1false
;
4080 build_export_prim(ctx
, &prim
);
4082 ac_build_endif(&ctx
->ac
, 5140);
4084 /* Export position and parameter data */
4085 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, vertlive_scan
.result_reduce
, "");
4086 ac_build_ifcc(&ctx
->ac
, tmp
, 5145);
4088 struct radv_vs_output_info
*outinfo
= &ctx
->args
->shader_info
->vs
.outinfo
;
4089 bool export_view_index
= ctx
->args
->options
->key
.has_multiview_view_index
;
4090 struct radv_shader_output_values
*outputs
;
4091 unsigned noutput
= 0;
4093 /* Allocate a temporary array for the output values. */
4094 unsigned num_outputs
= util_bitcount64(ctx
->output_mask
) + export_view_index
;
4095 outputs
= calloc(num_outputs
, sizeof(outputs
[0]));
4097 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
4098 sizeof(outinfo
->vs_output_param_offset
));
4099 outinfo
->pos_exports
= 0;
4101 tmp
= ngg_gs_vertex_ptr(ctx
, tid
);
4102 LLVMValueRef gep_idx
[3] = {
4103 ctx
->ac
.i32_0
, /* implicit C-style array */
4104 ctx
->ac
.i32_1
, /* second value of struct */
4105 ctx
->ac
.i32_1
, /* stream 1: source data index */
4107 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
4108 tmp
= LLVMBuildLoad(builder
, tmp
, "");
4109 tmp
= LLVMBuildZExt(builder
, tmp
, ctx
->ac
.i32
, "");
4110 const LLVMValueRef vertexptr
= ngg_gs_vertex_ptr(ctx
, tmp
);
4112 unsigned out_idx
= 0;
4113 gep_idx
[1] = ctx
->ac
.i32_0
;
4114 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
4115 unsigned output_usage_mask
=
4116 ctx
->args
->shader_info
->gs
.output_usage_mask
[i
];
4117 int length
= util_last_bit(output_usage_mask
);
4119 if (!(ctx
->output_mask
& (1ull << i
)))
4122 outputs
[noutput
].slot_name
= i
;
4123 outputs
[noutput
].slot_index
= i
== VARYING_SLOT_CLIP_DIST1
;
4124 outputs
[noutput
].usage_mask
= output_usage_mask
;
4126 for (unsigned j
= 0; j
< length
; j
++, out_idx
++) {
4127 if (!(output_usage_mask
& (1 << j
)))
4130 gep_idx
[2] = LLVMConstInt(ctx
->ac
.i32
, out_idx
, false);
4131 tmp
= LLVMBuildGEP(builder
, vertexptr
, gep_idx
, 3, "");
4132 tmp
= LLVMBuildLoad(builder
, tmp
, "");
4134 LLVMTypeRef type
= LLVMGetAllocatedType(ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
4135 if (ac_get_type_size(type
) == 2) {
4136 tmp
= ac_to_integer(&ctx
->ac
, tmp
);
4137 tmp
= LLVMBuildTrunc(ctx
->ac
.builder
, tmp
, ctx
->ac
.i16
, "");
4140 outputs
[noutput
].values
[j
] = ac_to_float(&ctx
->ac
, tmp
);
4143 for (unsigned j
= length
; j
< 4; j
++)
4144 outputs
[noutput
].values
[j
] = LLVMGetUndef(ctx
->ac
.f32
);
4149 /* Export ViewIndex. */
4150 if (export_view_index
) {
4151 outputs
[noutput
].slot_name
= VARYING_SLOT_LAYER
;
4152 outputs
[noutput
].slot_index
= 0;
4153 outputs
[noutput
].usage_mask
= 0x1;
4154 outputs
[noutput
].values
[0] =
4155 ac_to_float(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.view_index
));
4156 for (unsigned j
= 1; j
< 4; j
++)
4157 outputs
[noutput
].values
[j
] = ctx
->ac
.f32_0
;
4161 radv_llvm_export_vs(ctx
, outputs
, noutput
, outinfo
,
4162 ctx
->args
->options
->key
.vs_common_out
.export_clip_dists
);
4165 ac_build_endif(&ctx
->ac
, 5145);
4168 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context
*ctx
,
4170 LLVMValueRef
*addrs
)
4172 LLVMBuilderRef builder
= ctx
->ac
.builder
;
4174 const LLVMValueRef vertexidx
=
4175 LLVMBuildLoad(builder
, ctx
->gs_next_vertex
[stream
], "");
4177 /* If this thread has already emitted the declared maximum number of
4178 * vertices, skip the write: excessive vertex emissions are not
4179 * supposed to have any effect.
4181 const LLVMValueRef can_emit
=
4182 LLVMBuildICmp(builder
, LLVMIntULT
, vertexidx
,
4183 LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.gs
.vertices_out
, false), "");
4184 ac_build_ifcc(&ctx
->ac
, can_emit
, 9001);
4186 tmp
= LLVMBuildAdd(builder
, vertexidx
, ctx
->ac
.i32_1
, "");
4187 tmp
= LLVMBuildSelect(builder
, can_emit
, tmp
, vertexidx
, "");
4188 LLVMBuildStore(builder
, tmp
, ctx
->gs_next_vertex
[stream
]);
4190 const LLVMValueRef vertexptr
=
4191 ngg_gs_emit_vertex_ptr(ctx
, get_thread_id_in_tg(ctx
), vertexidx
);
4192 unsigned out_idx
= 0;
4193 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
4194 unsigned output_usage_mask
=
4195 ctx
->args
->shader_info
->gs
.output_usage_mask
[i
];
4196 uint8_t output_stream
=
4197 ctx
->args
->shader_info
->gs
.output_streams
[i
];
4198 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
4199 int length
= util_last_bit(output_usage_mask
);
4201 if (!(ctx
->output_mask
& (1ull << i
)) ||
4202 output_stream
!= stream
)
4205 for (unsigned j
= 0; j
< length
; j
++, out_idx
++) {
4206 if (!(output_usage_mask
& (1 << j
)))
4209 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
,
4211 LLVMValueRef gep_idx
[3] = {
4212 ctx
->ac
.i32_0
, /* implied C-style array */
4213 ctx
->ac
.i32_0
, /* first entry of struct */
4214 LLVMConstInt(ctx
->ac
.i32
, out_idx
, false),
4216 LLVMValueRef ptr
= LLVMBuildGEP(builder
, vertexptr
, gep_idx
, 3, "");
4218 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
4219 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
4221 LLVMBuildStore(builder
, out_val
, ptr
);
4224 assert(out_idx
* 4 <= ctx
->args
->shader_info
->gs
.gsvs_vertex_size
);
4226 /* Determine and store whether this vertex completed a primitive. */
4227 const LLVMValueRef curverts
= LLVMBuildLoad(builder
, ctx
->gs_curprim_verts
[stream
], "");
4229 tmp
= LLVMConstInt(ctx
->ac
.i32
, si_conv_gl_prim_to_vertices(ctx
->shader
->info
.gs
.output_primitive
) - 1, false);
4230 const LLVMValueRef iscompleteprim
=
4231 LLVMBuildICmp(builder
, LLVMIntUGE
, curverts
, tmp
, "");
4233 tmp
= LLVMBuildAdd(builder
, curverts
, ctx
->ac
.i32_1
, "");
4234 LLVMBuildStore(builder
, tmp
, ctx
->gs_curprim_verts
[stream
]);
4236 LLVMValueRef gep_idx
[3] = {
4237 ctx
->ac
.i32_0
, /* implied C-style array */
4238 ctx
->ac
.i32_1
, /* second struct entry */
4239 LLVMConstInt(ctx
->ac
.i32
, stream
, false),
4241 const LLVMValueRef primflagptr
=
4242 LLVMBuildGEP(builder
, vertexptr
, gep_idx
, 3, "");
4244 tmp
= LLVMBuildZExt(builder
, iscompleteprim
, ctx
->ac
.i8
, "");
4245 LLVMBuildStore(builder
, tmp
, primflagptr
);
4247 tmp
= LLVMBuildLoad(builder
, ctx
->gs_generated_prims
[stream
], "");
4248 tmp
= LLVMBuildAdd(builder
, tmp
, LLVMBuildZExt(builder
, iscompleteprim
, ctx
->ac
.i32
, ""), "");
4249 LLVMBuildStore(builder
, tmp
, ctx
->gs_generated_prims
[stream
]);
4251 ac_build_endif(&ctx
->ac
, 9001);
4255 write_tess_factors(struct radv_shader_context
*ctx
)
4257 unsigned stride
, outer_comps
, inner_comps
;
4258 LLVMValueRef tcs_rel_ids
= ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.tcs_rel_ids
);
4259 LLVMValueRef invocation_id
= ac_unpack_param(&ctx
->ac
, tcs_rel_ids
, 8, 5);
4260 LLVMValueRef rel_patch_id
= ac_unpack_param(&ctx
->ac
, tcs_rel_ids
, 0, 8);
4261 unsigned tess_inner_index
= 0, tess_outer_index
;
4262 LLVMValueRef lds_base
, lds_inner
= NULL
, lds_outer
, byteoffset
, buffer
;
4263 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
4265 ac_emit_barrier(&ctx
->ac
, ctx
->stage
);
4267 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
4287 ac_build_ifcc(&ctx
->ac
,
4288 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
4289 invocation_id
, ctx
->ac
.i32_0
, ""), 6503);
4291 lds_base
= get_tcs_out_current_patch_data_offset(ctx
);
4294 tess_inner_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
4295 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
4296 LLVMConstInt(ctx
->ac
.i32
, tess_inner_index
* 4, false), "");
4299 tess_outer_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
4300 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
4301 LLVMConstInt(ctx
->ac
.i32
, tess_outer_index
* 4, false), "");
4303 for (i
= 0; i
< 4; i
++) {
4304 inner
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
4305 outer
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
4309 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
4310 outer
[0] = out
[1] = ac_lds_load(&ctx
->ac
, lds_outer
);
4311 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
4313 outer
[1] = out
[0] = ac_lds_load(&ctx
->ac
, lds_outer
);
4315 for (i
= 0; i
< outer_comps
; i
++) {
4317 ac_lds_load(&ctx
->ac
, lds_outer
);
4318 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
4321 for (i
= 0; i
< inner_comps
; i
++) {
4322 inner
[i
] = out
[outer_comps
+i
] =
4323 ac_lds_load(&ctx
->ac
, lds_inner
);
4324 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_inner
,
4329 /* Convert the outputs to vectors for stores. */
4330 vec0
= ac_build_gather_values(&ctx
->ac
, out
, MIN2(stride
, 4));
4334 vec1
= ac_build_gather_values(&ctx
->ac
, out
+ 4, stride
- 4);
4337 buffer
= ctx
->hs_ring_tess_factor
;
4338 tf_base
= ac_get_arg(&ctx
->ac
, ctx
->args
->tess_factor_offset
);
4339 byteoffset
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
4340 LLVMConstInt(ctx
->ac
.i32
, 4 * stride
, false), "");
4341 unsigned tf_offset
= 0;
4343 if (ctx
->ac
.chip_class
<= GFX8
) {
4344 ac_build_ifcc(&ctx
->ac
,
4345 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
4346 rel_patch_id
, ctx
->ac
.i32_0
, ""), 6504);
4348 /* Store the dynamic HS control word. */
4349 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
4350 LLVMConstInt(ctx
->ac
.i32
, 0x80000000, false),
4351 1, ctx
->ac
.i32_0
, tf_base
,
4355 ac_build_endif(&ctx
->ac
, 6504);
4358 /* Store the tessellation factors. */
4359 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
4360 MIN2(stride
, 4), byteoffset
, tf_base
,
4361 tf_offset
, ac_glc
, false);
4363 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
4364 stride
- 4, byteoffset
, tf_base
,
4365 16 + tf_offset
, ac_glc
, false);
4367 //store to offchip for TES to read - only if TES reads them
4368 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
4369 LLVMValueRef inner_vec
, outer_vec
, tf_outer_offset
;
4370 LLVMValueRef tf_inner_offset
;
4371 unsigned param_outer
, param_inner
;
4373 param_outer
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
4374 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
4375 LLVMConstInt(ctx
->ac
.i32
, param_outer
, 0));
4377 outer_vec
= ac_build_gather_values(&ctx
->ac
, outer
,
4378 util_next_power_of_two(outer_comps
));
4380 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, outer_vec
,
4381 outer_comps
, tf_outer_offset
,
4382 ac_get_arg(&ctx
->ac
, ctx
->args
->oc_lds
),
4385 param_inner
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
4386 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
4387 LLVMConstInt(ctx
->ac
.i32
, param_inner
, 0));
4389 inner_vec
= inner_comps
== 1 ? inner
[0] :
4390 ac_build_gather_values(&ctx
->ac
, inner
, inner_comps
);
4391 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, inner_vec
,
4392 inner_comps
, tf_inner_offset
,
4393 ac_get_arg(&ctx
->ac
, ctx
->args
->oc_lds
),
4398 ac_build_endif(&ctx
->ac
, 6503);
4402 handle_tcs_outputs_post(struct radv_shader_context
*ctx
)
4404 write_tess_factors(ctx
);
4408 si_export_mrt_color(struct radv_shader_context
*ctx
,
4409 LLVMValueRef
*color
, unsigned index
,
4410 struct ac_export_args
*args
)
4413 si_llvm_init_export_args(ctx
, color
, 0xf,
4414 V_008DFC_SQ_EXP_MRT
+ index
, args
);
4415 if (!args
->enabled_channels
)
4416 return false; /* unnecessary NULL export */
4422 radv_export_mrt_z(struct radv_shader_context
*ctx
,
4423 LLVMValueRef depth
, LLVMValueRef stencil
,
4424 LLVMValueRef samplemask
)
4426 struct ac_export_args args
;
4428 ac_export_mrt_z(&ctx
->ac
, depth
, stencil
, samplemask
, &args
);
4430 ac_build_export(&ctx
->ac
, &args
);
4434 handle_fs_outputs_post(struct radv_shader_context
*ctx
)
4437 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
4438 struct ac_export_args color_args
[8];
4440 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
4441 LLVMValueRef values
[4];
4443 if (!(ctx
->output_mask
& (1ull << i
)))
4446 if (i
< FRAG_RESULT_DATA0
)
4449 for (unsigned j
= 0; j
< 4; j
++)
4450 values
[j
] = ac_to_float(&ctx
->ac
,
4451 radv_load_output(ctx
, i
, j
));
4453 bool ret
= si_export_mrt_color(ctx
, values
,
4454 i
- FRAG_RESULT_DATA0
,
4455 &color_args
[index
]);
4460 /* Process depth, stencil, samplemask. */
4461 if (ctx
->args
->shader_info
->ps
.writes_z
) {
4462 depth
= ac_to_float(&ctx
->ac
,
4463 radv_load_output(ctx
, FRAG_RESULT_DEPTH
, 0));
4465 if (ctx
->args
->shader_info
->ps
.writes_stencil
) {
4466 stencil
= ac_to_float(&ctx
->ac
,
4467 radv_load_output(ctx
, FRAG_RESULT_STENCIL
, 0));
4469 if (ctx
->args
->shader_info
->ps
.writes_sample_mask
) {
4470 samplemask
= ac_to_float(&ctx
->ac
,
4471 radv_load_output(ctx
, FRAG_RESULT_SAMPLE_MASK
, 0));
4474 /* Set the DONE bit on last non-null color export only if Z isn't
4478 !ctx
->args
->shader_info
->ps
.writes_z
&&
4479 !ctx
->args
->shader_info
->ps
.writes_stencil
&&
4480 !ctx
->args
->shader_info
->ps
.writes_sample_mask
) {
4481 unsigned last
= index
- 1;
4483 color_args
[last
].valid_mask
= 1; /* whether the EXEC mask is valid */
4484 color_args
[last
].done
= 1; /* DONE bit */
4487 /* Export PS outputs. */
4488 for (unsigned i
= 0; i
< index
; i
++)
4489 ac_build_export(&ctx
->ac
, &color_args
[i
]);
4491 if (depth
|| stencil
|| samplemask
)
4492 radv_export_mrt_z(ctx
, depth
, stencil
, samplemask
);
4494 ac_build_export_null(&ctx
->ac
);
4498 emit_gs_epilogue(struct radv_shader_context
*ctx
)
4500 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg
) {
4501 gfx10_ngg_gs_emit_epilogue_1(ctx
);
4505 if (ctx
->ac
.chip_class
>= GFX10
)
4506 LLVMBuildFence(ctx
->ac
.builder
, LLVMAtomicOrderingRelease
, false, "");
4508 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
, ctx
->gs_wave_id
);
4512 handle_shader_outputs_post(struct ac_shader_abi
*abi
, unsigned max_outputs
,
4513 LLVMValueRef
*addrs
)
4515 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4517 switch (ctx
->stage
) {
4518 case MESA_SHADER_VERTEX
:
4519 if (ctx
->args
->options
->key
.vs_common_out
.as_ls
)
4520 handle_ls_outputs_post(ctx
);
4521 else if (ctx
->args
->options
->key
.vs_common_out
.as_es
)
4522 handle_es_outputs_post(ctx
, &ctx
->args
->shader_info
->vs
.es_info
);
4523 else if (ctx
->args
->options
->key
.vs_common_out
.as_ngg
)
4524 handle_ngg_outputs_post_1(ctx
);
4526 handle_vs_outputs_post(ctx
, ctx
->args
->options
->key
.vs_common_out
.export_prim_id
,
4527 ctx
->args
->options
->key
.vs_common_out
.export_clip_dists
,
4528 &ctx
->args
->shader_info
->vs
.outinfo
);
4530 case MESA_SHADER_FRAGMENT
:
4531 handle_fs_outputs_post(ctx
);
4533 case MESA_SHADER_GEOMETRY
:
4534 emit_gs_epilogue(ctx
);
4536 case MESA_SHADER_TESS_CTRL
:
4537 handle_tcs_outputs_post(ctx
);
4539 case MESA_SHADER_TESS_EVAL
:
4540 if (ctx
->args
->options
->key
.vs_common_out
.as_es
)
4541 handle_es_outputs_post(ctx
, &ctx
->args
->shader_info
->tes
.es_info
);
4542 else if (ctx
->args
->options
->key
.vs_common_out
.as_ngg
)
4543 handle_ngg_outputs_post_1(ctx
);
4545 handle_vs_outputs_post(ctx
, ctx
->args
->options
->key
.vs_common_out
.export_prim_id
,
4546 ctx
->args
->options
->key
.vs_common_out
.export_clip_dists
,
4547 &ctx
->args
->shader_info
->tes
.outinfo
);
4554 static void ac_llvm_finalize_module(struct radv_shader_context
*ctx
,
4555 LLVMPassManagerRef passmgr
,
4556 const struct radv_nir_compiler_options
*options
)
4558 LLVMRunPassManager(passmgr
, ctx
->ac
.module
);
4559 LLVMDisposeBuilder(ctx
->ac
.builder
);
4561 ac_llvm_context_dispose(&ctx
->ac
);
4565 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context
*ctx
)
4567 struct radv_vs_output_info
*outinfo
;
4569 switch (ctx
->stage
) {
4570 case MESA_SHADER_FRAGMENT
:
4571 case MESA_SHADER_COMPUTE
:
4572 case MESA_SHADER_TESS_CTRL
:
4573 case MESA_SHADER_GEOMETRY
:
4575 case MESA_SHADER_VERTEX
:
4576 if (ctx
->args
->options
->key
.vs_common_out
.as_ls
||
4577 ctx
->args
->options
->key
.vs_common_out
.as_es
)
4579 outinfo
= &ctx
->args
->shader_info
->vs
.outinfo
;
4581 case MESA_SHADER_TESS_EVAL
:
4582 if (ctx
->args
->options
->key
.vs_common_out
.as_es
)
4584 outinfo
= &ctx
->args
->shader_info
->tes
.outinfo
;
4587 unreachable("Unhandled shader type");
4590 ac_optimize_vs_outputs(&ctx
->ac
,
4592 outinfo
->vs_output_param_offset
,
4594 &outinfo
->param_exports
);
4598 ac_setup_rings(struct radv_shader_context
*ctx
)
4600 if (ctx
->args
->options
->chip_class
<= GFX8
&&
4601 (ctx
->stage
== MESA_SHADER_GEOMETRY
||
4602 ctx
->args
->options
->key
.vs_common_out
.as_es
|| ctx
->args
->options
->key
.vs_common_out
.as_es
)) {
4603 unsigned ring
= ctx
->stage
== MESA_SHADER_GEOMETRY
? RING_ESGS_GS
4605 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, ring
, false);
4607 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
,
4612 if (ctx
->args
->is_gs_copy_shader
) {
4614 ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
,
4615 LLVMConstInt(ctx
->ac
.i32
,
4616 RING_GSVS_VS
, false));
4619 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
4620 /* The conceptual layout of the GSVS ring is
4621 * v0c0 .. vLv0 v0c1 .. vLc1 ..
4622 * but the real memory layout is swizzled across
4624 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
4626 * Override the buffer descriptor accordingly.
4628 LLVMTypeRef v2i64
= LLVMVectorType(ctx
->ac
.i64
, 2);
4629 uint64_t stream_offset
= 0;
4630 unsigned num_records
= ctx
->ac
.wave_size
;
4631 LLVMValueRef base_ring
;
4634 ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
,
4635 LLVMConstInt(ctx
->ac
.i32
,
4636 RING_GSVS_GS
, false));
4638 for (unsigned stream
= 0; stream
< 4; stream
++) {
4639 unsigned num_components
, stride
;
4640 LLVMValueRef ring
, tmp
;
4643 ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
];
4645 if (!num_components
)
4648 stride
= 4 * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
4650 /* Limit on the stride field for <= GFX7. */
4651 assert(stride
< (1 << 14));
4653 ring
= LLVMBuildBitCast(ctx
->ac
.builder
,
4654 base_ring
, v2i64
, "");
4655 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
,
4656 ring
, ctx
->ac
.i32_0
, "");
4657 tmp
= LLVMBuildAdd(ctx
->ac
.builder
, tmp
,
4658 LLVMConstInt(ctx
->ac
.i64
,
4659 stream_offset
, 0), "");
4660 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
,
4661 ring
, tmp
, ctx
->ac
.i32_0
, "");
4663 stream_offset
+= stride
* ctx
->ac
.wave_size
;
4665 ring
= LLVMBuildBitCast(ctx
->ac
.builder
, ring
,
4668 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
, ring
,
4670 tmp
= LLVMBuildOr(ctx
->ac
.builder
, tmp
,
4671 LLVMConstInt(ctx
->ac
.i32
,
4672 S_008F04_STRIDE(stride
), false), "");
4673 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ring
, tmp
,
4676 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ring
,
4677 LLVMConstInt(ctx
->ac
.i32
,
4678 num_records
, false),
4679 LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
4681 ctx
->gsvs_ring
[stream
] = ring
;
4685 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
4686 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
4687 ctx
->hs_ring_tess_offchip
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_OFFCHIP
, false));
4688 ctx
->hs_ring_tess_factor
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_FACTOR
, false));
4693 radv_nir_get_max_workgroup_size(enum chip_class chip_class
,
4694 gl_shader_stage stage
,
4695 const struct nir_shader
*nir
)
4697 const unsigned backup_sizes
[] = {chip_class
>= GFX9
? 128 : 64, 1, 1};
4699 for (unsigned i
= 0; i
< 3; i
++)
4700 sizes
[i
] = nir
? nir
->info
.cs
.local_size
[i
] : backup_sizes
[i
];
4701 return radv_get_max_workgroup_size(chip_class
, stage
, sizes
);
4704 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
4705 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context
*ctx
)
4707 LLVMValueRef count
=
4708 ac_unpack_param(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
), 8, 8);
4709 LLVMValueRef hs_empty
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, count
,
4711 ctx
->abi
.instance_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
,
4712 ac_get_arg(&ctx
->ac
, ctx
->args
->rel_auto_id
),
4713 ctx
->abi
.instance_id
, "");
4714 ctx
->rel_auto_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
,
4715 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.tcs_rel_ids
),
4718 ctx
->abi
.vertex_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
,
4719 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.tcs_patch_id
),
4720 ctx
->abi
.vertex_id
, "");
4723 static void prepare_gs_input_vgprs(struct radv_shader_context
*ctx
, bool merged
)
4726 for(int i
= 5; i
>= 0; --i
) {
4727 ctx
->gs_vtx_offset
[i
] =
4728 ac_unpack_param(&ctx
->ac
,
4729 ac_get_arg(&ctx
->ac
, ctx
->args
->gs_vtx_offset
[i
& ~1]),
4733 ctx
->gs_wave_id
= ac_unpack_param(&ctx
->ac
,
4734 ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
),
4737 for (int i
= 0; i
< 6; i
++)
4738 ctx
->gs_vtx_offset
[i
] = ac_get_arg(&ctx
->ac
, ctx
->args
->gs_vtx_offset
[i
]);
4739 ctx
->gs_wave_id
= ac_get_arg(&ctx
->ac
, ctx
->args
->gs_wave_id
);
4743 /* Ensure that the esgs ring is declared.
4745 * We declare it with 64KB alignment as a hint that the
4746 * pointer value will always be 0.
4748 static void declare_esgs_ring(struct radv_shader_context
*ctx
)
4753 assert(!LLVMGetNamedGlobal(ctx
->ac
.module
, "esgs_ring"));
4755 ctx
->esgs_ring
= LLVMAddGlobalInAddressSpace(
4756 ctx
->ac
.module
, LLVMArrayType(ctx
->ac
.i32
, 0),
4759 LLVMSetLinkage(ctx
->esgs_ring
, LLVMExternalLinkage
);
4760 LLVMSetAlignment(ctx
->esgs_ring
, 64 * 1024);
4764 LLVMModuleRef
ac_translate_nir_to_llvm(struct ac_llvm_compiler
*ac_llvm
,
4765 struct nir_shader
*const *shaders
,
4767 struct radv_shader_info
*shader_info
,
4768 const struct radv_nir_compiler_options
*options
)
4770 struct radv_shader_context ctx
= {0};
4771 struct radv_shader_args args
= {0};
4772 args
.options
= options
;
4773 args
.shader_info
= shader_info
;
4776 declare_inputs(&args
, shaders
[shader_count
- 1]->info
.stage
, shader_count
>= 2,
4777 shader_count
>= 2 ? shaders
[shader_count
- 2]->info
.stage
: MESA_SHADER_VERTEX
);
4779 enum ac_float_mode float_mode
= AC_FLOAT_MODE_DEFAULT
;
4781 if (shader_info
->float_controls_mode
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
) {
4782 float_mode
= AC_FLOAT_MODE_DENORM_FLUSH_TO_ZERO
;
4785 ac_llvm_context_init(&ctx
.ac
, ac_llvm
, options
->chip_class
,
4786 options
->family
, float_mode
, shader_info
->wave_size
, 64);
4787 ctx
.context
= ctx
.ac
.context
;
4789 ctx
.max_workgroup_size
= 0;
4790 for (int i
= 0; i
< shader_count
; ++i
) {
4791 ctx
.max_workgroup_size
= MAX2(ctx
.max_workgroup_size
,
4792 radv_nir_get_max_workgroup_size(args
.options
->chip_class
,
4793 shaders
[i
]->info
.stage
,
4797 if (ctx
.ac
.chip_class
>= GFX10
) {
4798 if (is_pre_gs_stage(shaders
[0]->info
.stage
) &&
4799 options
->key
.vs_common_out
.as_ngg
) {
4800 ctx
.max_workgroup_size
= 128;
4804 create_function(&ctx
, shaders
[shader_count
- 1]->info
.stage
, shader_count
>= 2);
4806 ctx
.abi
.inputs
= &ctx
.inputs
[0];
4807 ctx
.abi
.emit_outputs
= handle_shader_outputs_post
;
4808 ctx
.abi
.emit_vertex
= visit_emit_vertex
;
4809 ctx
.abi
.load_ubo
= radv_load_ubo
;
4810 ctx
.abi
.load_ssbo
= radv_load_ssbo
;
4811 ctx
.abi
.load_sampler_desc
= radv_get_sampler_desc
;
4812 ctx
.abi
.load_resource
= radv_load_resource
;
4813 ctx
.abi
.clamp_shadow_reference
= false;
4814 ctx
.abi
.robust_buffer_access
= options
->robust_buffer_access
;
4816 bool is_ngg
= is_pre_gs_stage(shaders
[0]->info
.stage
) && args
.options
->key
.vs_common_out
.as_ngg
;
4817 if (shader_count
>= 2 || is_ngg
)
4818 ac_init_exec_full_mask(&ctx
.ac
);
4820 if (args
.ac
.vertex_id
.used
)
4821 ctx
.abi
.vertex_id
= ac_get_arg(&ctx
.ac
, args
.ac
.vertex_id
);
4822 if (args
.rel_auto_id
.used
)
4823 ctx
.rel_auto_id
= ac_get_arg(&ctx
.ac
, args
.rel_auto_id
);
4824 if (args
.ac
.instance_id
.used
)
4825 ctx
.abi
.instance_id
= ac_get_arg(&ctx
.ac
, args
.ac
.instance_id
);
4827 if (options
->has_ls_vgpr_init_bug
&&
4828 shaders
[shader_count
- 1]->info
.stage
== MESA_SHADER_TESS_CTRL
)
4829 ac_nir_fixup_ls_hs_input_vgprs(&ctx
);
4832 /* Declare scratch space base for streamout and vertex
4833 * compaction. Whether space is actually allocated is
4834 * determined during linking / PM4 creation.
4836 * Add an extra dword per vertex to ensure an odd stride, which
4837 * avoids bank conflicts for SoA accesses.
4839 declare_esgs_ring(&ctx
);
4841 /* This is really only needed when streamout and / or vertex
4842 * compaction is enabled.
4844 LLVMTypeRef asi32
= LLVMArrayType(ctx
.ac
.i32
, 8);
4845 ctx
.gs_ngg_scratch
= LLVMAddGlobalInAddressSpace(ctx
.ac
.module
,
4846 asi32
, "ngg_scratch", AC_ADDR_SPACE_LDS
);
4847 LLVMSetInitializer(ctx
.gs_ngg_scratch
, LLVMGetUndef(asi32
));
4848 LLVMSetAlignment(ctx
.gs_ngg_scratch
, 4);
4851 for(int i
= 0; i
< shader_count
; ++i
) {
4852 ctx
.stage
= shaders
[i
]->info
.stage
;
4853 ctx
.shader
= shaders
[i
];
4854 ctx
.output_mask
= 0;
4856 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
4857 for (int i
= 0; i
< 4; i
++) {
4858 ctx
.gs_next_vertex
[i
] =
4859 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
4861 if (args
.options
->key
.vs_common_out
.as_ngg
) {
4862 for (unsigned i
= 0; i
< 4; ++i
) {
4863 ctx
.gs_curprim_verts
[i
] =
4864 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
4865 ctx
.gs_generated_prims
[i
] =
4866 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
4869 unsigned scratch_size
= 8;
4870 if (args
.shader_info
->so
.num_outputs
)
4873 LLVMTypeRef ai32
= LLVMArrayType(ctx
.ac
.i32
, scratch_size
);
4874 ctx
.gs_ngg_scratch
=
4875 LLVMAddGlobalInAddressSpace(ctx
.ac
.module
,
4876 ai32
, "ngg_scratch", AC_ADDR_SPACE_LDS
);
4877 LLVMSetInitializer(ctx
.gs_ngg_scratch
, LLVMGetUndef(ai32
));
4878 LLVMSetAlignment(ctx
.gs_ngg_scratch
, 4);
4880 ctx
.gs_ngg_emit
= LLVMAddGlobalInAddressSpace(ctx
.ac
.module
,
4881 LLVMArrayType(ctx
.ac
.i32
, 0), "ngg_emit", AC_ADDR_SPACE_LDS
);
4882 LLVMSetLinkage(ctx
.gs_ngg_emit
, LLVMExternalLinkage
);
4883 LLVMSetAlignment(ctx
.gs_ngg_emit
, 4);
4886 ctx
.abi
.load_inputs
= load_gs_input
;
4887 ctx
.abi
.emit_primitive
= visit_end_primitive
;
4888 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4889 ctx
.abi
.load_tess_varyings
= load_tcs_varyings
;
4890 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
4891 ctx
.abi
.store_tcs_outputs
= store_tcs_output
;
4892 if (shader_count
== 1)
4893 ctx
.tcs_num_inputs
= args
.options
->key
.tcs
.num_inputs
;
4895 ctx
.tcs_num_inputs
= util_last_bit64(shader_info
->vs
.ls_outputs_written
);
4896 ctx
.tcs_num_patches
= get_tcs_num_patches(&ctx
);
4897 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4898 ctx
.abi
.load_tess_varyings
= load_tes_input
;
4899 ctx
.abi
.load_tess_coord
= load_tess_coord
;
4900 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
4901 ctx
.tcs_num_patches
= args
.options
->key
.tes
.num_patches
;
4902 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
) {
4903 ctx
.abi
.load_base_vertex
= radv_load_base_vertex
;
4904 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
) {
4905 ctx
.abi
.load_sample_position
= load_sample_position
;
4906 ctx
.abi
.load_sample_mask_in
= load_sample_mask_in
;
4907 ctx
.abi
.emit_kill
= radv_emit_kill
;
4910 if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
&&
4911 args
.options
->key
.vs_common_out
.as_ngg
&&
4912 args
.options
->key
.vs_common_out
.export_prim_id
) {
4913 declare_esgs_ring(&ctx
);
4916 bool nested_barrier
= false;
4919 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
&&
4920 args
.options
->key
.vs_common_out
.as_ngg
) {
4921 gfx10_ngg_gs_emit_prologue(&ctx
);
4922 nested_barrier
= false;
4924 nested_barrier
= true;
4928 if (nested_barrier
) {
4929 /* Execute a barrier before the second shader in
4932 * Execute the barrier inside the conditional block,
4933 * so that empty waves can jump directly to s_endpgm,
4934 * which will also signal the barrier.
4936 * This is possible in gfx9, because an empty wave
4937 * for the second shader does not participate in
4938 * the epilogue. With NGG, empty waves may still
4939 * be required to export data (e.g. GS output vertices),
4940 * so we cannot let them exit early.
4942 * If the shader is TCS and the TCS epilog is present
4943 * and contains a barrier, it will wait there and then
4946 ac_emit_barrier(&ctx
.ac
, ctx
.stage
);
4949 nir_foreach_variable(variable
, &shaders
[i
]->outputs
)
4950 scan_shader_output_decl(&ctx
, variable
, shaders
[i
], shaders
[i
]->info
.stage
);
4952 ac_setup_rings(&ctx
);
4954 LLVMBasicBlockRef merge_block
;
4955 if (shader_count
>= 2 || is_ngg
) {
4956 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
4957 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
4958 merge_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
4960 LLVMValueRef count
=
4961 ac_unpack_param(&ctx
.ac
,
4962 ac_get_arg(&ctx
.ac
, args
.merged_wave_info
),
4964 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
.ac
);
4965 LLVMValueRef cond
= LLVMBuildICmp(ctx
.ac
.builder
, LLVMIntULT
,
4966 thread_id
, count
, "");
4967 LLVMBuildCondBr(ctx
.ac
.builder
, cond
, then_block
, merge_block
);
4969 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, then_block
);
4972 if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
)
4973 prepare_interp_optimize(&ctx
, shaders
[i
]);
4974 else if(shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
)
4975 handle_vs_inputs(&ctx
, shaders
[i
]);
4976 else if(shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
)
4977 prepare_gs_input_vgprs(&ctx
, shader_count
>= 2);
4979 ac_nir_translate(&ctx
.ac
, &ctx
.abi
, &args
.ac
, shaders
[i
]);
4981 if (shader_count
>= 2 || is_ngg
) {
4982 LLVMBuildBr(ctx
.ac
.builder
, merge_block
);
4983 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, merge_block
);
4986 /* This needs to be outside the if wrapping the shader body, as sometimes
4987 * the HW generates waves with 0 es/vs threads. */
4988 if (is_pre_gs_stage(shaders
[i
]->info
.stage
) &&
4989 args
.options
->key
.vs_common_out
.as_ngg
&&
4990 i
== shader_count
- 1) {
4991 handle_ngg_outputs_post_2(&ctx
);
4992 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
&&
4993 args
.options
->key
.vs_common_out
.as_ngg
) {
4994 gfx10_ngg_gs_emit_epilogue_2(&ctx
);
4997 if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4998 shader_info
->tcs
.num_patches
= ctx
.tcs_num_patches
;
4999 shader_info
->tcs
.lds_size
= calculate_tess_lds_size(&ctx
);
5003 LLVMBuildRetVoid(ctx
.ac
.builder
);
5005 if (options
->dump_preoptir
) {
5006 fprintf(stderr
, "%s LLVM IR:\n\n",
5007 radv_get_shader_name(shader_info
,
5008 shaders
[shader_count
- 1]->info
.stage
));
5009 ac_dump_module(ctx
.ac
.module
);
5010 fprintf(stderr
, "\n");
5013 ac_llvm_finalize_module(&ctx
, ac_llvm
->passmgr
, options
);
5015 if (shader_count
== 1)
5016 ac_nir_eliminate_const_vs_outputs(&ctx
);
5018 if (options
->dump_shader
) {
5019 args
.shader_info
->private_mem_vgprs
=
5020 ac_count_scratch_private_memory(ctx
.main_function
);
5023 return ctx
.ac
.module
;
5026 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di
, void *context
)
5028 unsigned *retval
= (unsigned *)context
;
5029 LLVMDiagnosticSeverity severity
= LLVMGetDiagInfoSeverity(di
);
5030 char *description
= LLVMGetDiagInfoDescription(di
);
5032 if (severity
== LLVMDSError
) {
5034 fprintf(stderr
, "LLVM triggered Diagnostic Handler: %s\n",
5038 LLVMDisposeMessage(description
);
5041 static unsigned radv_llvm_compile(LLVMModuleRef M
,
5042 char **pelf_buffer
, size_t *pelf_size
,
5043 struct ac_llvm_compiler
*ac_llvm
)
5045 unsigned retval
= 0;
5046 LLVMContextRef llvm_ctx
;
5048 /* Setup Diagnostic Handler*/
5049 llvm_ctx
= LLVMGetModuleContext(M
);
5051 LLVMContextSetDiagnosticHandler(llvm_ctx
, ac_diagnostic_handler
,
5055 if (!radv_compile_to_elf(ac_llvm
, M
, pelf_buffer
, pelf_size
))
5060 static void ac_compile_llvm_module(struct ac_llvm_compiler
*ac_llvm
,
5061 LLVMModuleRef llvm_module
,
5062 struct radv_shader_binary
**rbinary
,
5063 gl_shader_stage stage
,
5065 const struct radv_nir_compiler_options
*options
)
5067 char *elf_buffer
= NULL
;
5068 size_t elf_size
= 0;
5069 char *llvm_ir_string
= NULL
;
5071 if (options
->dump_shader
) {
5072 fprintf(stderr
, "%s LLVM IR:\n\n", name
);
5073 ac_dump_module(llvm_module
);
5074 fprintf(stderr
, "\n");
5077 if (options
->record_ir
) {
5078 char *llvm_ir
= LLVMPrintModuleToString(llvm_module
);
5079 llvm_ir_string
= strdup(llvm_ir
);
5080 LLVMDisposeMessage(llvm_ir
);
5083 int v
= radv_llvm_compile(llvm_module
, &elf_buffer
, &elf_size
, ac_llvm
);
5085 fprintf(stderr
, "compile failed\n");
5088 LLVMContextRef ctx
= LLVMGetModuleContext(llvm_module
);
5089 LLVMDisposeModule(llvm_module
);
5090 LLVMContextDispose(ctx
);
5092 size_t llvm_ir_size
= llvm_ir_string
? strlen(llvm_ir_string
) : 0;
5093 size_t alloc_size
= sizeof(struct radv_shader_binary_rtld
) + elf_size
+ llvm_ir_size
+ 1;
5094 struct radv_shader_binary_rtld
*rbin
= calloc(1, alloc_size
);
5095 memcpy(rbin
->data
, elf_buffer
, elf_size
);
5097 memcpy(rbin
->data
+ elf_size
, llvm_ir_string
, llvm_ir_size
+ 1);
5099 rbin
->base
.type
= RADV_BINARY_TYPE_RTLD
;
5100 rbin
->base
.stage
= stage
;
5101 rbin
->base
.total_size
= alloc_size
;
5102 rbin
->elf_size
= elf_size
;
5103 rbin
->llvm_ir_size
= llvm_ir_size
;
5104 *rbinary
= &rbin
->base
;
5106 free(llvm_ir_string
);
5111 radv_compile_nir_shader(struct ac_llvm_compiler
*ac_llvm
,
5112 struct radv_shader_binary
**rbinary
,
5113 struct radv_shader_info
*shader_info
,
5114 struct nir_shader
*const *nir
,
5116 const struct radv_nir_compiler_options
*options
)
5119 LLVMModuleRef llvm_module
;
5121 llvm_module
= ac_translate_nir_to_llvm(ac_llvm
, nir
, nir_count
, shader_info
,
5124 ac_compile_llvm_module(ac_llvm
, llvm_module
, rbinary
,
5125 nir
[nir_count
- 1]->info
.stage
,
5126 radv_get_shader_name(shader_info
,
5127 nir
[nir_count
- 1]->info
.stage
),
5130 /* Determine the ES type (VS or TES) for the GS on GFX9. */
5131 if (options
->chip_class
>= GFX9
) {
5132 if (nir_count
== 2 &&
5133 nir
[1]->info
.stage
== MESA_SHADER_GEOMETRY
) {
5134 shader_info
->gs
.es_type
= nir
[0]->info
.stage
;
5140 ac_gs_copy_shader_emit(struct radv_shader_context
*ctx
)
5142 LLVMValueRef vtx_offset
=
5143 LLVMBuildMul(ctx
->ac
.builder
, ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.vertex_id
),
5144 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
5145 LLVMValueRef stream_id
;
5147 /* Fetch the vertex stream ID. */
5148 if (!ctx
->args
->options
->use_ngg_streamout
&&
5149 ctx
->args
->shader_info
->so
.num_outputs
) {
5151 ac_unpack_param(&ctx
->ac
,
5152 ac_get_arg(&ctx
->ac
,
5153 ctx
->args
->streamout_config
),
5156 stream_id
= ctx
->ac
.i32_0
;
5159 LLVMBasicBlockRef end_bb
;
5160 LLVMValueRef switch_inst
;
5162 end_bb
= LLVMAppendBasicBlockInContext(ctx
->ac
.context
,
5163 ctx
->main_function
, "end");
5164 switch_inst
= LLVMBuildSwitch(ctx
->ac
.builder
, stream_id
, end_bb
, 4);
5166 for (unsigned stream
= 0; stream
< 4; stream
++) {
5167 unsigned num_components
=
5168 ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
];
5169 LLVMBasicBlockRef bb
;
5172 if (stream
> 0 && !num_components
)
5175 if (stream
> 0 && !ctx
->args
->shader_info
->so
.num_outputs
)
5178 bb
= LLVMInsertBasicBlockInContext(ctx
->ac
.context
, end_bb
, "out");
5179 LLVMAddCase(switch_inst
, LLVMConstInt(ctx
->ac
.i32
, stream
, 0), bb
);
5180 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, bb
);
5183 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
5184 unsigned output_usage_mask
=
5185 ctx
->args
->shader_info
->gs
.output_usage_mask
[i
];
5186 unsigned output_stream
=
5187 ctx
->args
->shader_info
->gs
.output_streams
[i
];
5188 int length
= util_last_bit(output_usage_mask
);
5190 if (!(ctx
->output_mask
& (1ull << i
)) ||
5191 output_stream
!= stream
)
5194 for (unsigned j
= 0; j
< length
; j
++) {
5195 LLVMValueRef value
, soffset
;
5197 if (!(output_usage_mask
& (1 << j
)))
5200 soffset
= LLVMConstInt(ctx
->ac
.i32
,
5202 ctx
->shader
->info
.gs
.vertices_out
* 16 * 4, false);
5206 value
= ac_build_buffer_load(&ctx
->ac
,
5209 vtx_offset
, soffset
,
5210 0, ac_glc
| ac_slc
, true, false);
5212 LLVMTypeRef type
= LLVMGetAllocatedType(ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
5213 if (ac_get_type_size(type
) == 2) {
5214 value
= LLVMBuildBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
5215 value
= LLVMBuildTrunc(ctx
->ac
.builder
, value
, ctx
->ac
.i16
, "");
5218 LLVMBuildStore(ctx
->ac
.builder
,
5219 ac_to_float(&ctx
->ac
, value
), ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
5223 if (!ctx
->args
->options
->use_ngg_streamout
&&
5224 ctx
->args
->shader_info
->so
.num_outputs
)
5225 radv_emit_streamout(ctx
, stream
);
5228 handle_vs_outputs_post(ctx
, false, true,
5229 &ctx
->args
->shader_info
->vs
.outinfo
);
5232 LLVMBuildBr(ctx
->ac
.builder
, end_bb
);
5235 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, end_bb
);
5239 radv_compile_gs_copy_shader(struct ac_llvm_compiler
*ac_llvm
,
5240 struct nir_shader
*geom_shader
,
5241 struct radv_shader_binary
**rbinary
,
5242 struct radv_shader_info
*shader_info
,
5243 const struct radv_nir_compiler_options
*options
)
5245 struct radv_shader_context ctx
= {0};
5246 struct radv_shader_args args
= {0};
5247 args
.options
= options
;
5248 args
.shader_info
= shader_info
;
5251 args
.is_gs_copy_shader
= true;
5252 declare_inputs(&args
, MESA_SHADER_VERTEX
, false, MESA_SHADER_VERTEX
);
5254 ac_llvm_context_init(&ctx
.ac
, ac_llvm
, options
->chip_class
,
5255 options
->family
, AC_FLOAT_MODE_DEFAULT
, 64, 64);
5256 ctx
.context
= ctx
.ac
.context
;
5258 ctx
.stage
= MESA_SHADER_VERTEX
;
5259 ctx
.shader
= geom_shader
;
5261 create_function(&ctx
, MESA_SHADER_VERTEX
, false);
5263 ac_setup_rings(&ctx
);
5265 nir_foreach_variable(variable
, &geom_shader
->outputs
) {
5266 scan_shader_output_decl(&ctx
, variable
, geom_shader
, MESA_SHADER_VERTEX
);
5267 ac_handle_shader_output_decl(&ctx
.ac
, &ctx
.abi
, geom_shader
,
5268 variable
, MESA_SHADER_VERTEX
);
5271 ac_gs_copy_shader_emit(&ctx
);
5273 LLVMBuildRetVoid(ctx
.ac
.builder
);
5275 ac_llvm_finalize_module(&ctx
, ac_llvm
->passmgr
, options
);
5277 ac_compile_llvm_module(ac_llvm
, ctx
.ac
.module
, rbinary
,
5278 MESA_SHADER_VERTEX
, "GS Copy Shader", options
);
5279 (*rbinary
)->is_gs_copy_shader
= true;