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Revert "ac,radeonsi: fix compilations issues with LLVM 11"
[mesa.git] / src / amd / vulkan / radv_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "radv_shader_helper.h"
31 #include "radv_shader_args.h"
32 #include "radv_debug.h"
33 #include "nir/nir.h"
34
35 #include "sid.h"
36 #include "ac_binary.h"
37 #include "ac_llvm_util.h"
38 #include "ac_llvm_build.h"
39 #include "ac_shader_abi.h"
40 #include "ac_shader_util.h"
41 #include "ac_exp_param.h"
42
43 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
44
45 struct radv_shader_context {
46 struct ac_llvm_context ac;
47 const struct nir_shader *shader;
48 struct ac_shader_abi abi;
49 const struct radv_shader_args *args;
50
51 gl_shader_stage stage;
52
53 unsigned max_workgroup_size;
54 LLVMContextRef context;
55 LLVMValueRef main_function;
56
57 LLVMValueRef descriptor_sets[MAX_SETS];
58
59 LLVMValueRef ring_offsets;
60
61 LLVMValueRef rel_auto_id;
62
63 LLVMValueRef gs_wave_id;
64 LLVMValueRef gs_vtx_offset[6];
65
66 LLVMValueRef esgs_ring;
67 LLVMValueRef gsvs_ring[4];
68 LLVMValueRef hs_ring_tess_offchip;
69 LLVMValueRef hs_ring_tess_factor;
70
71 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
72
73 uint64_t output_mask;
74
75 LLVMValueRef gs_next_vertex[4];
76 LLVMValueRef gs_curprim_verts[4];
77 LLVMValueRef gs_generated_prims[4];
78 LLVMValueRef gs_ngg_emit;
79 LLVMValueRef gs_ngg_scratch;
80
81 uint32_t tcs_num_inputs;
82 uint32_t tcs_num_patches;
83
84 LLVMValueRef vertexptr; /* GFX10 only */
85 };
86
87 struct radv_shader_output_values {
88 LLVMValueRef values[4];
89 unsigned slot_name;
90 unsigned slot_index;
91 unsigned usage_mask;
92 };
93
94 static inline struct radv_shader_context *
95 radv_shader_context_from_abi(struct ac_shader_abi *abi)
96 {
97 struct radv_shader_context *ctx = NULL;
98 return container_of(abi, ctx, abi);
99 }
100
101 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
102 {
103 switch (ctx->stage) {
104 case MESA_SHADER_TESS_CTRL:
105 return ac_unpack_param(&ctx->ac,
106 ac_get_arg(&ctx->ac, ctx->args->ac.tcs_rel_ids),
107 0, 8);
108 case MESA_SHADER_TESS_EVAL:
109 return ac_get_arg(&ctx->ac, ctx->args->tes_rel_patch_id);
110 break;
111 default:
112 unreachable("Illegal stage");
113 }
114 }
115
116 /* Tessellation shaders pass outputs to the next shader using LDS.
117 *
118 * LS outputs = TCS inputs
119 * TCS outputs = TES inputs
120 *
121 * The LDS layout is:
122 * - TCS inputs for patch 0
123 * - TCS inputs for patch 1
124 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
125 * - ...
126 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
127 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
128 * - TCS outputs for patch 1
129 * - Per-patch TCS outputs for patch 1
130 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
131 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
132 * - ...
133 *
134 * All three shaders VS(LS), TCS, TES share the same LDS space.
135 */
136 static LLVMValueRef
137 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
138 {
139 assert(ctx->stage == MESA_SHADER_TESS_CTRL);
140 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
141 uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * input_vertex_size;
142
143 input_patch_size /= 4;
144 return LLVMConstInt(ctx->ac.i32, input_patch_size, false);
145 }
146
147 static LLVMValueRef
148 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
149 {
150 uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
151 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->args->shader_info->tcs.patch_outputs_written);
152 uint32_t output_vertex_size = num_tcs_outputs * 16;
153 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
154 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
155 output_patch_size /= 4;
156 return LLVMConstInt(ctx->ac.i32, output_patch_size, false);
157 }
158
159 static LLVMValueRef
160 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
161 {
162 uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
163 uint32_t output_vertex_size = num_tcs_outputs * 16;
164 output_vertex_size /= 4;
165 return LLVMConstInt(ctx->ac.i32, output_vertex_size, false);
166 }
167
168 static LLVMValueRef
169 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
170 {
171 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
172 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
173 uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * input_vertex_size;
174 uint32_t output_patch0_offset = input_patch_size;
175 unsigned num_patches = ctx->tcs_num_patches;
176
177 output_patch0_offset *= num_patches;
178 output_patch0_offset /= 4;
179 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
180 }
181
182 static LLVMValueRef
183 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
184 {
185 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
186 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
187 uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * input_vertex_size;
188 uint32_t output_patch0_offset = input_patch_size;
189
190 uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
191 uint32_t output_vertex_size = num_tcs_outputs * 16;
192 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
193 unsigned num_patches = ctx->tcs_num_patches;
194
195 output_patch0_offset *= num_patches;
196 output_patch0_offset += pervertex_output_patch_size;
197 output_patch0_offset /= 4;
198 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
199 }
200
201 static LLVMValueRef
202 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
203 {
204 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
205 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
206
207 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
208 }
209
210 static LLVMValueRef
211 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
212 {
213 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
214 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
215 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
216
217 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
218 patch0_offset);
219 }
220
221 static LLVMValueRef
222 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
223 {
224 LLVMValueRef patch0_patch_data_offset =
225 get_tcs_out_patch0_patch_data_offset(ctx);
226 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
227 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
228
229 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
230 patch0_patch_data_offset);
231 }
232
233 static LLVMValueRef
234 create_llvm_function(struct ac_llvm_context *ctx, LLVMModuleRef module,
235 LLVMBuilderRef builder,
236 const struct ac_shader_args *args,
237 enum ac_llvm_calling_convention convention,
238 unsigned max_workgroup_size,
239 const struct radv_nir_compiler_options *options)
240 {
241 LLVMValueRef main_function =
242 ac_build_main(args, ctx, convention, "main", ctx->voidt, module);
243
244 if (options->address32_hi) {
245 ac_llvm_add_target_dep_function_attr(main_function,
246 "amdgpu-32bit-address-high-bits",
247 options->address32_hi);
248 }
249
250 ac_llvm_set_workgroup_size(main_function, max_workgroup_size);
251
252 return main_function;
253 }
254
255 static void
256 load_descriptor_sets(struct radv_shader_context *ctx)
257 {
258 uint32_t mask = ctx->args->shader_info->desc_set_used_mask;
259 if (ctx->args->shader_info->need_indirect_descriptor_sets) {
260 LLVMValueRef desc_sets =
261 ac_get_arg(&ctx->ac, ctx->args->descriptor_sets[0]);
262 while (mask) {
263 int i = u_bit_scan(&mask);
264
265 ctx->descriptor_sets[i] =
266 ac_build_load_to_sgpr(&ctx->ac, desc_sets,
267 LLVMConstInt(ctx->ac.i32, i, false));
268
269 }
270 } else {
271 while (mask) {
272 int i = u_bit_scan(&mask);
273
274 ctx->descriptor_sets[i] =
275 ac_get_arg(&ctx->ac, ctx->args->descriptor_sets[i]);
276 }
277 }
278 }
279
280 static enum ac_llvm_calling_convention
281 get_llvm_calling_convention(LLVMValueRef func, gl_shader_stage stage)
282 {
283 switch (stage) {
284 case MESA_SHADER_VERTEX:
285 case MESA_SHADER_TESS_EVAL:
286 return AC_LLVM_AMDGPU_VS;
287 break;
288 case MESA_SHADER_GEOMETRY:
289 return AC_LLVM_AMDGPU_GS;
290 break;
291 case MESA_SHADER_TESS_CTRL:
292 return AC_LLVM_AMDGPU_HS;
293 break;
294 case MESA_SHADER_FRAGMENT:
295 return AC_LLVM_AMDGPU_PS;
296 break;
297 case MESA_SHADER_COMPUTE:
298 return AC_LLVM_AMDGPU_CS;
299 break;
300 default:
301 unreachable("Unhandle shader type");
302 }
303 }
304
305 /* Returns whether the stage is a stage that can be directly before the GS */
306 static bool is_pre_gs_stage(gl_shader_stage stage)
307 {
308 return stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL;
309 }
310
311 static void create_function(struct radv_shader_context *ctx,
312 gl_shader_stage stage,
313 bool has_previous_stage)
314 {
315 if (ctx->ac.chip_class >= GFX10) {
316 if (is_pre_gs_stage(stage) && ctx->args->options->key.vs_common_out.as_ngg) {
317 /* On GFX10, VS is merged into GS for NGG. */
318 stage = MESA_SHADER_GEOMETRY;
319 has_previous_stage = true;
320 }
321 }
322
323 ctx->main_function = create_llvm_function(
324 &ctx->ac, ctx->ac.module, ctx->ac.builder, &ctx->args->ac,
325 get_llvm_calling_convention(ctx->main_function, stage),
326 ctx->max_workgroup_size,
327 ctx->args->options);
328
329 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
330 LLVMPointerType(ctx->ac.i8, AC_ADDR_SPACE_CONST),
331 NULL, 0, AC_FUNC_ATTR_READNONE);
332 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
333 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
334
335 load_descriptor_sets(ctx);
336
337 if (stage == MESA_SHADER_TESS_CTRL ||
338 (stage == MESA_SHADER_VERTEX && ctx->args->options->key.vs_common_out.as_ls) ||
339 /* GFX9 has the ESGS ring buffer in LDS. */
340 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
341 ac_declare_lds_as_pointer(&ctx->ac);
342 }
343
344 }
345
346
347 static LLVMValueRef
348 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
349 unsigned desc_set, unsigned binding)
350 {
351 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
352 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
353 struct radv_pipeline_layout *pipeline_layout = ctx->args->options->layout;
354 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
355 unsigned base_offset = layout->binding[binding].offset;
356 LLVMValueRef offset, stride;
357
358 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
359 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
360 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
361 layout->binding[binding].dynamic_offset_offset;
362 desc_ptr = ac_get_arg(&ctx->ac, ctx->args->ac.push_constants);
363 base_offset = pipeline_layout->push_constant_size + 16 * idx;
364 stride = LLVMConstInt(ctx->ac.i32, 16, false);
365 } else
366 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
367
368 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
369
370 if (layout->binding[binding].type != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
371 offset = ac_build_imad(&ctx->ac, index, stride, offset);
372 }
373
374 desc_ptr = LLVMBuildGEP(ctx->ac.builder, desc_ptr, &offset, 1, "");
375 desc_ptr = ac_cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
376 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
377
378 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
379 uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
380 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
381 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
382 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
383
384 if (ctx->ac.chip_class >= GFX10) {
385 desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
386 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
387 S_008F0C_RESOURCE_LEVEL(1);
388 } else {
389 desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
390 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
391 }
392
393 LLVMValueRef desc_components[4] = {
394 LLVMBuildPtrToInt(ctx->ac.builder, desc_ptr, ctx->ac.intptr, ""),
395 LLVMConstInt(ctx->ac.i32, S_008F04_BASE_ADDRESS_HI(ctx->args->options->address32_hi), false),
396 /* High limit to support variable sizes. */
397 LLVMConstInt(ctx->ac.i32, 0xffffffff, false),
398 LLVMConstInt(ctx->ac.i32, desc_type, false),
399 };
400
401 return ac_build_gather_values(&ctx->ac, desc_components, 4);
402 }
403
404 return desc_ptr;
405 }
406
407
408 /* The offchip buffer layout for TCS->TES is
409 *
410 * - attribute 0 of patch 0 vertex 0
411 * - attribute 0 of patch 0 vertex 1
412 * - attribute 0 of patch 0 vertex 2
413 * ...
414 * - attribute 0 of patch 1 vertex 0
415 * - attribute 0 of patch 1 vertex 1
416 * ...
417 * - attribute 1 of patch 0 vertex 0
418 * - attribute 1 of patch 0 vertex 1
419 * ...
420 * - per patch attribute 0 of patch 0
421 * - per patch attribute 0 of patch 1
422 * ...
423 *
424 * Note that every attribute has 4 components.
425 */
426 static LLVMValueRef get_non_vertex_index_offset(struct radv_shader_context *ctx)
427 {
428 uint32_t num_patches = ctx->tcs_num_patches;
429 uint32_t num_tcs_outputs;
430 if (ctx->stage == MESA_SHADER_TESS_CTRL)
431 num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
432 else
433 num_tcs_outputs = ctx->args->options->key.tes.tcs_num_outputs;
434
435 uint32_t output_vertex_size = num_tcs_outputs * 16;
436 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
437
438 return LLVMConstInt(ctx->ac.i32, pervertex_output_patch_size * num_patches, false);
439 }
440
441 static LLVMValueRef calc_param_stride(struct radv_shader_context *ctx,
442 LLVMValueRef vertex_index)
443 {
444 LLVMValueRef param_stride;
445 if (vertex_index)
446 param_stride = LLVMConstInt(ctx->ac.i32, ctx->shader->info.tess.tcs_vertices_out * ctx->tcs_num_patches, false);
447 else
448 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_num_patches, false);
449 return param_stride;
450 }
451
452 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
453 LLVMValueRef vertex_index,
454 LLVMValueRef param_index)
455 {
456 LLVMValueRef base_addr;
457 LLVMValueRef param_stride, constant16;
458 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
459 LLVMValueRef vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->shader->info.tess.tcs_vertices_out, false);
460 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
461 param_stride = calc_param_stride(ctx, vertex_index);
462 if (vertex_index) {
463 base_addr = ac_build_imad(&ctx->ac, rel_patch_id,
464 vertices_per_patch, vertex_index);
465 } else {
466 base_addr = rel_patch_id;
467 }
468
469 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
470 LLVMBuildMul(ctx->ac.builder, param_index,
471 param_stride, ""), "");
472
473 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
474
475 if (!vertex_index) {
476 LLVMValueRef patch_data_offset = get_non_vertex_index_offset(ctx);
477
478 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
479 patch_data_offset, "");
480 }
481 return base_addr;
482 }
483
484 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
485 unsigned param,
486 unsigned const_index,
487 bool is_compact,
488 LLVMValueRef vertex_index,
489 LLVMValueRef indir_index)
490 {
491 LLVMValueRef param_index;
492
493 if (indir_index)
494 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
495 indir_index, "");
496 else {
497 if (const_index && !is_compact)
498 param += const_index;
499 param_index = LLVMConstInt(ctx->ac.i32, param, false);
500 }
501 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
502 }
503
504 static LLVMValueRef
505 get_dw_address(struct radv_shader_context *ctx,
506 LLVMValueRef dw_addr,
507 unsigned param,
508 unsigned const_index,
509 bool compact_const_index,
510 LLVMValueRef vertex_index,
511 LLVMValueRef stride,
512 LLVMValueRef indir_index)
513
514 {
515
516 if (vertex_index) {
517 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
518 LLVMBuildMul(ctx->ac.builder,
519 vertex_index,
520 stride, ""), "");
521 }
522
523 if (indir_index)
524 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
525 LLVMBuildMul(ctx->ac.builder, indir_index,
526 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
527 else if (const_index && !compact_const_index)
528 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
529 LLVMConstInt(ctx->ac.i32, const_index * 4, false), "");
530
531 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
532 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
533
534 if (const_index && compact_const_index)
535 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
536 LLVMConstInt(ctx->ac.i32, const_index, false), "");
537 return dw_addr;
538 }
539
540 static LLVMValueRef
541 load_tcs_varyings(struct ac_shader_abi *abi,
542 LLVMTypeRef type,
543 LLVMValueRef vertex_index,
544 LLVMValueRef indir_index,
545 unsigned const_index,
546 unsigned location,
547 unsigned driver_location,
548 unsigned component,
549 unsigned num_components,
550 bool is_patch,
551 bool is_compact,
552 bool load_input)
553 {
554 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
555 LLVMValueRef dw_addr, stride;
556 LLVMValueRef value[4], result;
557 unsigned param = shader_io_get_unique_index(location);
558
559 if (load_input) {
560 uint32_t input_vertex_size = (ctx->tcs_num_inputs * 16) / 4;
561 stride = LLVMConstInt(ctx->ac.i32, input_vertex_size, false);
562 dw_addr = get_tcs_in_current_patch_offset(ctx);
563 } else {
564 if (!is_patch) {
565 stride = get_tcs_out_vertex_stride(ctx);
566 dw_addr = get_tcs_out_current_patch_offset(ctx);
567 } else {
568 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
569 stride = NULL;
570 }
571 }
572
573 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
574 indir_index);
575
576 for (unsigned i = 0; i < num_components + component; i++) {
577 value[i] = ac_lds_load(&ctx->ac, dw_addr);
578 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
579 ctx->ac.i32_1, "");
580 }
581 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
582 return result;
583 }
584
585 static void
586 store_tcs_output(struct ac_shader_abi *abi,
587 const nir_variable *var,
588 LLVMValueRef vertex_index,
589 LLVMValueRef param_index,
590 unsigned const_index,
591 LLVMValueRef src,
592 unsigned writemask)
593 {
594 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
595 const unsigned location = var->data.location;
596 unsigned component = var->data.location_frac;
597 const bool is_patch = var->data.patch;
598 const bool is_compact = var->data.compact;
599 LLVMValueRef dw_addr;
600 LLVMValueRef stride = NULL;
601 LLVMValueRef buf_addr = NULL;
602 LLVMValueRef oc_lds = ac_get_arg(&ctx->ac, ctx->args->oc_lds);
603 unsigned param;
604 bool store_lds = true;
605
606 if (is_patch) {
607 if (!(ctx->shader->info.patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
608 store_lds = false;
609 } else {
610 if (!(ctx->shader->info.outputs_read & (1ULL << location)))
611 store_lds = false;
612 }
613
614 param = shader_io_get_unique_index(location);
615 if ((location == VARYING_SLOT_CLIP_DIST0 || location == VARYING_SLOT_CLIP_DIST1) && is_compact) {
616 const_index += component;
617 component = 0;
618
619 if (const_index >= 4) {
620 const_index -= 4;
621 param++;
622 }
623 }
624
625 if (!is_patch) {
626 stride = get_tcs_out_vertex_stride(ctx);
627 dw_addr = get_tcs_out_current_patch_offset(ctx);
628 } else {
629 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
630 }
631
632 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
633 param_index);
634 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
635 vertex_index, param_index);
636
637 bool is_tess_factor = false;
638 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
639 location == VARYING_SLOT_TESS_LEVEL_OUTER)
640 is_tess_factor = true;
641
642 unsigned base = is_compact ? const_index : 0;
643 for (unsigned chan = 0; chan < 8; chan++) {
644 if (!(writemask & (1 << chan)))
645 continue;
646 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
647 value = ac_to_integer(&ctx->ac, value);
648 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
649
650 if (store_lds || is_tess_factor) {
651 LLVMValueRef dw_addr_chan =
652 LLVMBuildAdd(ctx->ac.builder, dw_addr,
653 LLVMConstInt(ctx->ac.i32, chan, false), "");
654 ac_lds_store(&ctx->ac, dw_addr_chan, value);
655 }
656
657 if (!is_tess_factor && writemask != 0xF)
658 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
659 buf_addr, oc_lds,
660 4 * (base + chan), ac_glc);
661 }
662
663 if (writemask == 0xF) {
664 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
665 buf_addr, oc_lds,
666 (base * 4), ac_glc);
667 }
668 }
669
670 static LLVMValueRef
671 load_tes_input(struct ac_shader_abi *abi,
672 LLVMTypeRef type,
673 LLVMValueRef vertex_index,
674 LLVMValueRef param_index,
675 unsigned const_index,
676 unsigned location,
677 unsigned driver_location,
678 unsigned component,
679 unsigned num_components,
680 bool is_patch,
681 bool is_compact,
682 bool load_input)
683 {
684 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
685 LLVMValueRef buf_addr;
686 LLVMValueRef result;
687 LLVMValueRef oc_lds = ac_get_arg(&ctx->ac, ctx->args->oc_lds);
688 unsigned param = shader_io_get_unique_index(location);
689
690 if ((location == VARYING_SLOT_CLIP_DIST0 || location == VARYING_SLOT_CLIP_DIST1) && is_compact) {
691 const_index += component;
692 component = 0;
693 if (const_index >= 4) {
694 const_index -= 4;
695 param++;
696 }
697 }
698
699 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
700 is_compact, vertex_index, param_index);
701
702 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
703 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
704
705 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
706 buf_addr, oc_lds, is_compact ? (4 * const_index) : 0, ac_glc, true, false);
707 result = ac_trim_vector(&ctx->ac, result, num_components);
708 return result;
709 }
710
711 static LLVMValueRef
712 radv_emit_fetch_64bit(struct radv_shader_context *ctx,
713 LLVMTypeRef type, LLVMValueRef a, LLVMValueRef b)
714 {
715 LLVMValueRef values[2] = {
716 ac_to_integer(&ctx->ac, a),
717 ac_to_integer(&ctx->ac, b),
718 };
719 LLVMValueRef result = ac_build_gather_values(&ctx->ac, values, 2);
720 return LLVMBuildBitCast(ctx->ac.builder, result, type, "");
721 }
722
723 static LLVMValueRef
724 load_gs_input(struct ac_shader_abi *abi,
725 unsigned location,
726 unsigned driver_location,
727 unsigned component,
728 unsigned num_components,
729 unsigned vertex_index,
730 unsigned const_index,
731 LLVMTypeRef type)
732 {
733 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
734 LLVMValueRef vtx_offset;
735 unsigned param, vtx_offset_param;
736 LLVMValueRef value[4], result;
737
738 vtx_offset_param = vertex_index;
739 assert(vtx_offset_param < 6);
740 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
741 LLVMConstInt(ctx->ac.i32, 4, false), "");
742
743 param = shader_io_get_unique_index(location);
744
745 for (unsigned i = component; i < num_components + component; i++) {
746 if (ctx->ac.chip_class >= GFX9) {
747 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
748 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
749 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
750 value[i] = ac_lds_load(&ctx->ac, dw_addr);
751
752 if (ac_get_type_size(type) == 8) {
753 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
754 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index + 1, 0), "");
755 LLVMValueRef tmp = ac_lds_load(&ctx->ac, dw_addr);
756
757 value[i] = radv_emit_fetch_64bit(ctx, type, value[i], tmp);
758 }
759 } else {
760 LLVMValueRef soffset =
761 LLVMConstInt(ctx->ac.i32,
762 (param * 4 + i + const_index) * 256,
763 false);
764
765 value[i] = ac_build_buffer_load(&ctx->ac,
766 ctx->esgs_ring, 1,
767 ctx->ac.i32_0,
768 vtx_offset, soffset,
769 0, ac_glc, true, false);
770
771 if (ac_get_type_size(type) == 8) {
772 soffset = LLVMConstInt(ctx->ac.i32,
773 (param * 4 + i + const_index + 1) * 256,
774 false);
775
776 LLVMValueRef tmp =
777 ac_build_buffer_load(&ctx->ac,
778 ctx->esgs_ring, 1,
779 ctx->ac.i32_0,
780 vtx_offset, soffset,
781 0, ac_glc, true, false);
782
783 value[i] = radv_emit_fetch_64bit(ctx, type, value[i], tmp);
784 }
785 }
786
787 if (ac_get_type_size(type) == 2) {
788 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], ctx->ac.i32, "");
789 value[i] = LLVMBuildTrunc(ctx->ac.builder, value[i], ctx->ac.i16, "");
790 }
791 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], type, "");
792 }
793 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
794 result = ac_to_integer(&ctx->ac, result);
795 return result;
796 }
797
798 static uint32_t
799 radv_get_sample_pos_offset(uint32_t num_samples)
800 {
801 uint32_t sample_pos_offset = 0;
802
803 switch (num_samples) {
804 case 2:
805 sample_pos_offset = 1;
806 break;
807 case 4:
808 sample_pos_offset = 3;
809 break;
810 case 8:
811 sample_pos_offset = 7;
812 break;
813 default:
814 break;
815 }
816 return sample_pos_offset;
817 }
818
819 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
820 LLVMValueRef sample_id)
821 {
822 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
823
824 LLVMValueRef result;
825 LLVMValueRef index = LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false);
826 LLVMValueRef ptr = LLVMBuildGEP(ctx->ac.builder, ctx->ring_offsets, &index, 1, "");
827
828 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
829 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
830
831 uint32_t sample_pos_offset =
832 radv_get_sample_pos_offset(ctx->args->options->key.fs.num_samples);
833
834 sample_id =
835 LLVMBuildAdd(ctx->ac.builder, sample_id,
836 LLVMConstInt(ctx->ac.i32, sample_pos_offset, false), "");
837 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
838
839 return result;
840 }
841
842
843 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
844 {
845 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
846 uint8_t log2_ps_iter_samples;
847
848 if (ctx->args->shader_info->ps.force_persample) {
849 log2_ps_iter_samples =
850 util_logbase2(ctx->args->options->key.fs.num_samples);
851 } else {
852 log2_ps_iter_samples = ctx->args->options->key.fs.log2_ps_iter_samples;
853 }
854
855 /* The bit pattern matches that used by fixed function fragment
856 * processing. */
857 static const uint16_t ps_iter_masks[] = {
858 0xffff, /* not used */
859 0x5555,
860 0x1111,
861 0x0101,
862 0x0001,
863 };
864 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
865
866 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
867
868 LLVMValueRef result, sample_id;
869 sample_id = ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->ac.ancillary), 8, 4);
870 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
871 result = LLVMBuildAnd(ctx->ac.builder, sample_id,
872 ac_get_arg(&ctx->ac, ctx->args->ac.sample_coverage), "");
873 return result;
874 }
875
876
877 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context *ctx,
878 unsigned stream,
879 LLVMValueRef vertexidx,
880 LLVMValueRef *addrs);
881
882 static void
883 visit_emit_vertex_with_counter(struct ac_shader_abi *abi, unsigned stream,
884 LLVMValueRef vertexidx, LLVMValueRef *addrs)
885 {
886 unsigned offset = 0;
887 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
888
889 if (ctx->args->options->key.vs_common_out.as_ngg) {
890 gfx10_ngg_gs_emit_vertex(ctx, stream, vertexidx, addrs);
891 return;
892 }
893
894 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
895 unsigned output_usage_mask =
896 ctx->args->shader_info->gs.output_usage_mask[i];
897 uint8_t output_stream =
898 ctx->args->shader_info->gs.output_streams[i];
899 LLVMValueRef *out_ptr = &addrs[i * 4];
900 int length = util_last_bit(output_usage_mask);
901
902 if (!(ctx->output_mask & (1ull << i)) ||
903 output_stream != stream)
904 continue;
905
906 for (unsigned j = 0; j < length; j++) {
907 if (!(output_usage_mask & (1 << j)))
908 continue;
909
910 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
911 out_ptr[j], "");
912 LLVMValueRef voffset =
913 LLVMConstInt(ctx->ac.i32, offset *
914 ctx->shader->info.gs.vertices_out, false);
915
916 offset++;
917
918 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, vertexidx, "");
919 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
920
921 out_val = ac_to_integer(&ctx->ac, out_val);
922 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
923
924 ac_build_buffer_store_dword(&ctx->ac,
925 ctx->gsvs_ring[stream],
926 out_val, 1,
927 voffset,
928 ac_get_arg(&ctx->ac,
929 ctx->args->gs2vs_offset),
930 0, ac_glc | ac_slc | ac_swizzled);
931 }
932 }
933
934 ac_build_sendmsg(&ctx->ac,
935 AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
936 ctx->gs_wave_id);
937 }
938
939 static void
940 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
941 {
942 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
943
944 if (ctx->args->options->key.vs_common_out.as_ngg) {
945 LLVMBuildStore(ctx->ac.builder, ctx->ac.i32_0, ctx->gs_curprim_verts[stream]);
946 return;
947 }
948
949 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
950 }
951
952 static LLVMValueRef
953 load_tess_coord(struct ac_shader_abi *abi)
954 {
955 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
956
957 LLVMValueRef coord[4] = {
958 ac_get_arg(&ctx->ac, ctx->args->tes_u),
959 ac_get_arg(&ctx->ac, ctx->args->tes_v),
960 ctx->ac.f32_0,
961 ctx->ac.f32_0,
962 };
963
964 if (ctx->shader->info.tess.primitive_mode == GL_TRIANGLES)
965 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
966 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
967
968 return ac_build_gather_values(&ctx->ac, coord, 3);
969 }
970
971 static LLVMValueRef
972 load_patch_vertices_in(struct ac_shader_abi *abi)
973 {
974 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
975 return LLVMConstInt(ctx->ac.i32, ctx->args->options->key.tcs.input_vertices, false);
976 }
977
978
979 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
980 {
981 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
982 return ac_get_arg(&ctx->ac, ctx->args->ac.base_vertex);
983 }
984
985 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
986 LLVMValueRef buffer_ptr, bool write)
987 {
988 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
989 LLVMValueRef result;
990
991 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
992
993 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
994 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
995
996 return result;
997 }
998
999 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
1000 {
1001 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1002 LLVMValueRef result;
1003
1004 if (LLVMGetTypeKind(LLVMTypeOf(buffer_ptr)) != LLVMPointerTypeKind) {
1005 /* Do not load the descriptor for inlined uniform blocks. */
1006 return buffer_ptr;
1007 }
1008
1009 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1010
1011 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1012 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1013
1014 return result;
1015 }
1016
1017 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
1018 unsigned descriptor_set,
1019 unsigned base_index,
1020 unsigned constant_index,
1021 LLVMValueRef index,
1022 enum ac_descriptor_type desc_type,
1023 bool image, bool write,
1024 bool bindless)
1025 {
1026 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1027 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
1028 struct radv_descriptor_set_layout *layout = ctx->args->options->layout->set[descriptor_set].layout;
1029 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
1030 unsigned offset = binding->offset;
1031 unsigned stride = binding->size;
1032 unsigned type_size;
1033 LLVMBuilderRef builder = ctx->ac.builder;
1034 LLVMTypeRef type;
1035
1036 assert(base_index < layout->binding_count);
1037
1038 switch (desc_type) {
1039 case AC_DESC_IMAGE:
1040 type = ctx->ac.v8i32;
1041 type_size = 32;
1042 break;
1043 case AC_DESC_FMASK:
1044 type = ctx->ac.v8i32;
1045 offset += 32;
1046 type_size = 32;
1047 break;
1048 case AC_DESC_SAMPLER:
1049 type = ctx->ac.v4i32;
1050 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER) {
1051 offset += radv_combined_image_descriptor_sampler_offset(binding);
1052 }
1053
1054 type_size = 16;
1055 break;
1056 case AC_DESC_BUFFER:
1057 type = ctx->ac.v4i32;
1058 type_size = 16;
1059 break;
1060 case AC_DESC_PLANE_0:
1061 case AC_DESC_PLANE_1:
1062 case AC_DESC_PLANE_2:
1063 type = ctx->ac.v8i32;
1064 type_size = 32;
1065 offset += 32 * (desc_type - AC_DESC_PLANE_0);
1066 break;
1067 default:
1068 unreachable("invalid desc_type\n");
1069 }
1070
1071 offset += constant_index * stride;
1072
1073 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
1074 (!index || binding->immutable_samplers_equal)) {
1075 if (binding->immutable_samplers_equal)
1076 constant_index = 0;
1077
1078 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
1079
1080 LLVMValueRef constants[] = {
1081 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
1082 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
1083 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
1084 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
1085 };
1086 return ac_build_gather_values(&ctx->ac, constants, 4);
1087 }
1088
1089 assert(stride % type_size == 0);
1090
1091 LLVMValueRef adjusted_index = index;
1092 if (!adjusted_index)
1093 adjusted_index = ctx->ac.i32_0;
1094
1095 adjusted_index = LLVMBuildMul(builder, adjusted_index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
1096
1097 LLVMValueRef val_offset = LLVMConstInt(ctx->ac.i32, offset, 0);
1098 list = LLVMBuildGEP(builder, list, &val_offset, 1, "");
1099 list = LLVMBuildPointerCast(builder, list,
1100 ac_array_in_const32_addr_space(type), "");
1101
1102 LLVMValueRef descriptor = ac_build_load_to_sgpr(&ctx->ac, list, adjusted_index);
1103
1104 /* 3 plane formats always have same size and format for plane 1 & 2, so
1105 * use the tail from plane 1 so that we can store only the first 16 bytes
1106 * of the last plane. */
1107 if (desc_type == AC_DESC_PLANE_2) {
1108 LLVMValueRef descriptor2 = radv_get_sampler_desc(abi, descriptor_set, base_index, constant_index, index, AC_DESC_PLANE_1,image, write, bindless);
1109
1110 LLVMValueRef components[8];
1111 for (unsigned i = 0; i < 4; ++i)
1112 components[i] = ac_llvm_extract_elem(&ctx->ac, descriptor, i);
1113
1114 for (unsigned i = 4; i < 8; ++i)
1115 components[i] = ac_llvm_extract_elem(&ctx->ac, descriptor2, i);
1116 descriptor = ac_build_gather_values(&ctx->ac, components, 8);
1117 }
1118
1119 return descriptor;
1120 }
1121
1122 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
1123 * so we may need to fix it up. */
1124 static LLVMValueRef
1125 adjust_vertex_fetch_alpha(struct radv_shader_context *ctx,
1126 unsigned adjustment,
1127 LLVMValueRef alpha)
1128 {
1129 if (adjustment == RADV_ALPHA_ADJUST_NONE)
1130 return alpha;
1131
1132 LLVMValueRef c30 = LLVMConstInt(ctx->ac.i32, 30, 0);
1133
1134 alpha = LLVMBuildBitCast(ctx->ac.builder, alpha, ctx->ac.f32, "");
1135
1136 if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
1137 alpha = LLVMBuildFPToUI(ctx->ac.builder, alpha, ctx->ac.i32, "");
1138 else
1139 alpha = ac_to_integer(&ctx->ac, alpha);
1140
1141 /* For the integer-like cases, do a natural sign extension.
1142 *
1143 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
1144 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
1145 * exponent.
1146 */
1147 alpha = LLVMBuildShl(ctx->ac.builder, alpha,
1148 adjustment == RADV_ALPHA_ADJUST_SNORM ?
1149 LLVMConstInt(ctx->ac.i32, 7, 0) : c30, "");
1150 alpha = LLVMBuildAShr(ctx->ac.builder, alpha, c30, "");
1151
1152 /* Convert back to the right type. */
1153 if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
1154 LLVMValueRef clamp;
1155 LLVMValueRef neg_one = LLVMConstReal(ctx->ac.f32, -1.0);
1156 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1157 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, alpha, neg_one, "");
1158 alpha = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, alpha, "");
1159 } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
1160 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1161 }
1162
1163 return LLVMBuildBitCast(ctx->ac.builder, alpha, ctx->ac.i32, "");
1164 }
1165
1166 static LLVMValueRef
1167 radv_fixup_vertex_input_fetches(struct radv_shader_context *ctx,
1168 LLVMValueRef value,
1169 unsigned num_channels,
1170 bool is_float)
1171 {
1172 LLVMValueRef zero = is_float ? ctx->ac.f32_0 : ctx->ac.i32_0;
1173 LLVMValueRef one = is_float ? ctx->ac.f32_1 : ctx->ac.i32_1;
1174 LLVMValueRef chan[4];
1175
1176 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMVectorTypeKind) {
1177 unsigned vec_size = LLVMGetVectorSize(LLVMTypeOf(value));
1178
1179 if (num_channels == 4 && num_channels == vec_size)
1180 return value;
1181
1182 num_channels = MIN2(num_channels, vec_size);
1183
1184 for (unsigned i = 0; i < num_channels; i++)
1185 chan[i] = ac_llvm_extract_elem(&ctx->ac, value, i);
1186 } else {
1187 assert(num_channels == 1);
1188 chan[0] = value;
1189 }
1190
1191 for (unsigned i = num_channels; i < 4; i++) {
1192 chan[i] = i == 3 ? one : zero;
1193 chan[i] = ac_to_integer(&ctx->ac, chan[i]);
1194 }
1195
1196 return ac_build_gather_values(&ctx->ac, chan, 4);
1197 }
1198
1199 static void
1200 handle_vs_input_decl(struct radv_shader_context *ctx,
1201 struct nir_variable *variable)
1202 {
1203 LLVMValueRef t_list_ptr = ac_get_arg(&ctx->ac, ctx->args->vertex_buffers);
1204 LLVMValueRef t_offset;
1205 LLVMValueRef t_list;
1206 LLVMValueRef input;
1207 LLVMValueRef buffer_index;
1208 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
1209 uint8_t input_usage_mask =
1210 ctx->args->shader_info->vs.input_usage_mask[variable->data.location];
1211 unsigned num_input_channels = util_last_bit(input_usage_mask);
1212
1213 variable->data.driver_location = variable->data.location * 4;
1214
1215 enum glsl_base_type type = glsl_get_base_type(variable->type);
1216 for (unsigned i = 0; i < attrib_count; ++i) {
1217 LLVMValueRef output[4];
1218 unsigned attrib_index = variable->data.location + i - VERT_ATTRIB_GENERIC0;
1219 unsigned attrib_format = ctx->args->options->key.vs.vertex_attribute_formats[attrib_index];
1220 unsigned data_format = attrib_format & 0x0f;
1221 unsigned num_format = (attrib_format >> 4) & 0x07;
1222 bool is_float = num_format != V_008F0C_BUF_NUM_FORMAT_UINT &&
1223 num_format != V_008F0C_BUF_NUM_FORMAT_SINT;
1224
1225 if (ctx->args->options->key.vs.instance_rate_inputs & (1u << attrib_index)) {
1226 uint32_t divisor = ctx->args->options->key.vs.instance_rate_divisors[attrib_index];
1227
1228 if (divisor) {
1229 buffer_index = ctx->abi.instance_id;
1230
1231 if (divisor != 1) {
1232 buffer_index = LLVMBuildUDiv(ctx->ac.builder, buffer_index,
1233 LLVMConstInt(ctx->ac.i32, divisor, 0), "");
1234 }
1235 } else {
1236 buffer_index = ctx->ac.i32_0;
1237 }
1238
1239 buffer_index = LLVMBuildAdd(ctx->ac.builder,
1240 ac_get_arg(&ctx->ac,
1241 ctx->args->ac.start_instance),\
1242 buffer_index, "");
1243 } else {
1244 buffer_index = LLVMBuildAdd(ctx->ac.builder,
1245 ctx->abi.vertex_id,
1246 ac_get_arg(&ctx->ac,
1247 ctx->args->ac.base_vertex), "");
1248 }
1249
1250 const struct ac_data_format_info *vtx_info = ac_get_data_format_info(data_format);
1251
1252 /* Adjust the number of channels to load based on the vertex
1253 * attribute format.
1254 */
1255 unsigned num_channels = MIN2(num_input_channels, vtx_info->num_channels);
1256 unsigned attrib_binding = ctx->args->options->key.vs.vertex_attribute_bindings[attrib_index];
1257 unsigned attrib_offset = ctx->args->options->key.vs.vertex_attribute_offsets[attrib_index];
1258 unsigned attrib_stride = ctx->args->options->key.vs.vertex_attribute_strides[attrib_index];
1259
1260 if (ctx->args->options->key.vs.post_shuffle & (1 << attrib_index)) {
1261 /* Always load, at least, 3 channels for formats that
1262 * need to be shuffled because X<->Z.
1263 */
1264 num_channels = MAX2(num_channels, 3);
1265 }
1266
1267 t_offset = LLVMConstInt(ctx->ac.i32, attrib_binding, false);
1268 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
1269
1270 /* Perform per-channel vertex fetch operations if unaligned
1271 * access are detected. Only GFX6 and GFX10 are affected.
1272 */
1273 bool unaligned_vertex_fetches = false;
1274 if ((ctx->ac.chip_class == GFX6 || ctx->ac.chip_class == GFX10) &&
1275 vtx_info->chan_format != data_format &&
1276 ((attrib_offset % vtx_info->element_size) ||
1277 (attrib_stride % vtx_info->element_size)))
1278 unaligned_vertex_fetches = true;
1279
1280 if (unaligned_vertex_fetches) {
1281 unsigned chan_format = vtx_info->chan_format;
1282 LLVMValueRef values[4];
1283
1284 assert(ctx->ac.chip_class == GFX6 ||
1285 ctx->ac.chip_class == GFX10);
1286
1287 for (unsigned chan = 0; chan < num_channels; chan++) {
1288 unsigned chan_offset = attrib_offset + chan * vtx_info->chan_byte_size;
1289 LLVMValueRef chan_index = buffer_index;
1290
1291 if (attrib_stride != 0 && chan_offset > attrib_stride) {
1292 LLVMValueRef buffer_offset =
1293 LLVMConstInt(ctx->ac.i32,
1294 chan_offset / attrib_stride, false);
1295
1296 chan_index = LLVMBuildAdd(ctx->ac.builder,
1297 buffer_index,
1298 buffer_offset, "");
1299
1300 chan_offset = chan_offset % attrib_stride;
1301 }
1302
1303 values[chan] = ac_build_struct_tbuffer_load(&ctx->ac, t_list,
1304 chan_index,
1305 LLVMConstInt(ctx->ac.i32, chan_offset, false),
1306 ctx->ac.i32_0, ctx->ac.i32_0, 1,
1307 chan_format, num_format, 0, true);
1308 }
1309
1310 input = ac_build_gather_values(&ctx->ac, values, num_channels);
1311 } else {
1312 if (attrib_stride != 0 && attrib_offset > attrib_stride) {
1313 LLVMValueRef buffer_offset =
1314 LLVMConstInt(ctx->ac.i32,
1315 attrib_offset / attrib_stride, false);
1316
1317 buffer_index = LLVMBuildAdd(ctx->ac.builder,
1318 buffer_index,
1319 buffer_offset, "");
1320
1321 attrib_offset = attrib_offset % attrib_stride;
1322 }
1323
1324 input = ac_build_struct_tbuffer_load(&ctx->ac, t_list,
1325 buffer_index,
1326 LLVMConstInt(ctx->ac.i32, attrib_offset, false),
1327 ctx->ac.i32_0, ctx->ac.i32_0,
1328 num_channels,
1329 data_format, num_format, 0, true);
1330 }
1331
1332 if (ctx->args->options->key.vs.post_shuffle & (1 << attrib_index)) {
1333 LLVMValueRef c[4];
1334 c[0] = ac_llvm_extract_elem(&ctx->ac, input, 2);
1335 c[1] = ac_llvm_extract_elem(&ctx->ac, input, 1);
1336 c[2] = ac_llvm_extract_elem(&ctx->ac, input, 0);
1337 c[3] = ac_llvm_extract_elem(&ctx->ac, input, 3);
1338
1339 input = ac_build_gather_values(&ctx->ac, c, 4);
1340 }
1341
1342 input = radv_fixup_vertex_input_fetches(ctx, input, num_channels,
1343 is_float);
1344
1345 for (unsigned chan = 0; chan < 4; chan++) {
1346 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
1347 output[chan] = LLVMBuildExtractElement(ctx->ac.builder, input, llvm_chan, "");
1348 if (type == GLSL_TYPE_FLOAT16) {
1349 output[chan] = LLVMBuildBitCast(ctx->ac.builder, output[chan], ctx->ac.f32, "");
1350 output[chan] = LLVMBuildFPTrunc(ctx->ac.builder, output[chan], ctx->ac.f16, "");
1351 }
1352 }
1353
1354 unsigned alpha_adjust = (ctx->args->options->key.vs.alpha_adjust >> (attrib_index * 2)) & 3;
1355 output[3] = adjust_vertex_fetch_alpha(ctx, alpha_adjust, output[3]);
1356
1357 for (unsigned chan = 0; chan < 4; chan++) {
1358 output[chan] = ac_to_integer(&ctx->ac, output[chan]);
1359 if (type == GLSL_TYPE_UINT16 || type == GLSL_TYPE_INT16)
1360 output[chan] = LLVMBuildTrunc(ctx->ac.builder, output[chan], ctx->ac.i16, "");
1361
1362 ctx->inputs[ac_llvm_reg_index_soa(variable->data.location + i, chan)] = output[chan];
1363 }
1364 }
1365 }
1366
1367 static void
1368 handle_vs_inputs(struct radv_shader_context *ctx,
1369 struct nir_shader *nir) {
1370 nir_foreach_variable(variable, &nir->inputs)
1371 handle_vs_input_decl(ctx, variable);
1372 }
1373
1374 static void
1375 prepare_interp_optimize(struct radv_shader_context *ctx,
1376 struct nir_shader *nir)
1377 {
1378 bool uses_center = false;
1379 bool uses_centroid = false;
1380 nir_foreach_variable(variable, &nir->inputs) {
1381 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
1382 variable->data.sample)
1383 continue;
1384
1385 if (variable->data.centroid)
1386 uses_centroid = true;
1387 else
1388 uses_center = true;
1389 }
1390
1391 ctx->abi.persp_centroid = ac_get_arg(&ctx->ac, ctx->args->ac.persp_centroid);
1392 ctx->abi.linear_centroid = ac_get_arg(&ctx->ac, ctx->args->ac.linear_centroid);
1393
1394 if (uses_center && uses_centroid) {
1395 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT,
1396 ac_get_arg(&ctx->ac, ctx->args->ac.prim_mask),
1397 ctx->ac.i32_0, "");
1398 ctx->abi.persp_centroid =
1399 LLVMBuildSelect(ctx->ac.builder, sel,
1400 ac_get_arg(&ctx->ac, ctx->args->ac.persp_center),
1401 ctx->abi.persp_centroid, "");
1402 ctx->abi.linear_centroid =
1403 LLVMBuildSelect(ctx->ac.builder, sel,
1404 ac_get_arg(&ctx->ac, ctx->args->ac.linear_center),
1405 ctx->abi.linear_centroid, "");
1406 }
1407 }
1408
1409 static void
1410 scan_shader_output_decl(struct radv_shader_context *ctx,
1411 struct nir_variable *variable,
1412 struct nir_shader *shader,
1413 gl_shader_stage stage)
1414 {
1415 int idx = variable->data.location + variable->data.index;
1416 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
1417 uint64_t mask_attribs;
1418
1419 variable->data.driver_location = idx * 4;
1420
1421 /* tess ctrl has it's own load/store paths for outputs */
1422 if (stage == MESA_SHADER_TESS_CTRL)
1423 return;
1424
1425 if (variable->data.compact) {
1426 unsigned component_count = variable->data.location_frac +
1427 glsl_get_length(variable->type);
1428 attrib_count = (component_count + 3) / 4;
1429 }
1430
1431 mask_attribs = ((1ull << attrib_count) - 1) << idx;
1432
1433 ctx->output_mask |= mask_attribs;
1434 }
1435
1436
1437 /* Initialize arguments for the shader export intrinsic */
1438 static void
1439 si_llvm_init_export_args(struct radv_shader_context *ctx,
1440 LLVMValueRef *values,
1441 unsigned enabled_channels,
1442 unsigned target,
1443 struct ac_export_args *args)
1444 {
1445 /* Specify the channels that are enabled. */
1446 args->enabled_channels = enabled_channels;
1447
1448 /* Specify whether the EXEC mask represents the valid mask */
1449 args->valid_mask = 0;
1450
1451 /* Specify whether this is the last export */
1452 args->done = 0;
1453
1454 /* Specify the target we are exporting */
1455 args->target = target;
1456
1457 args->compr = false;
1458 args->out[0] = LLVMGetUndef(ctx->ac.f32);
1459 args->out[1] = LLVMGetUndef(ctx->ac.f32);
1460 args->out[2] = LLVMGetUndef(ctx->ac.f32);
1461 args->out[3] = LLVMGetUndef(ctx->ac.f32);
1462
1463 if (!values)
1464 return;
1465
1466 bool is_16bit = ac_get_type_size(LLVMTypeOf(values[0])) == 2;
1467 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1468 unsigned index = target - V_008DFC_SQ_EXP_MRT;
1469 unsigned col_format = (ctx->args->options->key.fs.col_format >> (4 * index)) & 0xf;
1470 bool is_int8 = (ctx->args->options->key.fs.is_int8 >> index) & 1;
1471 bool is_int10 = (ctx->args->options->key.fs.is_int10 >> index) & 1;
1472 unsigned chan;
1473
1474 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
1475 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
1476 unsigned bits, bool hi) = NULL;
1477
1478 switch(col_format) {
1479 case V_028714_SPI_SHADER_ZERO:
1480 args->enabled_channels = 0; /* writemask */
1481 args->target = V_008DFC_SQ_EXP_NULL;
1482 break;
1483
1484 case V_028714_SPI_SHADER_32_R:
1485 args->enabled_channels = 1;
1486 args->out[0] = values[0];
1487 break;
1488
1489 case V_028714_SPI_SHADER_32_GR:
1490 args->enabled_channels = 0x3;
1491 args->out[0] = values[0];
1492 args->out[1] = values[1];
1493 break;
1494
1495 case V_028714_SPI_SHADER_32_AR:
1496 if (ctx->ac.chip_class >= GFX10) {
1497 args->enabled_channels = 0x3;
1498 args->out[0] = values[0];
1499 args->out[1] = values[3];
1500 } else {
1501 args->enabled_channels = 0x9;
1502 args->out[0] = values[0];
1503 args->out[3] = values[3];
1504 }
1505 break;
1506
1507 case V_028714_SPI_SHADER_FP16_ABGR:
1508 args->enabled_channels = 0x5;
1509 packf = ac_build_cvt_pkrtz_f16;
1510 if (is_16bit) {
1511 for (unsigned chan = 0; chan < 4; chan++)
1512 values[chan] = LLVMBuildFPExt(ctx->ac.builder,
1513 values[chan],
1514 ctx->ac.f32, "");
1515 }
1516 break;
1517
1518 case V_028714_SPI_SHADER_UNORM16_ABGR:
1519 args->enabled_channels = 0x5;
1520 packf = ac_build_cvt_pknorm_u16;
1521 break;
1522
1523 case V_028714_SPI_SHADER_SNORM16_ABGR:
1524 args->enabled_channels = 0x5;
1525 packf = ac_build_cvt_pknorm_i16;
1526 break;
1527
1528 case V_028714_SPI_SHADER_UINT16_ABGR:
1529 args->enabled_channels = 0x5;
1530 packi = ac_build_cvt_pk_u16;
1531 if (is_16bit) {
1532 for (unsigned chan = 0; chan < 4; chan++)
1533 values[chan] = LLVMBuildZExt(ctx->ac.builder,
1534 ac_to_integer(&ctx->ac, values[chan]),
1535 ctx->ac.i32, "");
1536 }
1537 break;
1538
1539 case V_028714_SPI_SHADER_SINT16_ABGR:
1540 args->enabled_channels = 0x5;
1541 packi = ac_build_cvt_pk_i16;
1542 if (is_16bit) {
1543 for (unsigned chan = 0; chan < 4; chan++)
1544 values[chan] = LLVMBuildSExt(ctx->ac.builder,
1545 ac_to_integer(&ctx->ac, values[chan]),
1546 ctx->ac.i32, "");
1547 }
1548 break;
1549
1550 default:
1551 case V_028714_SPI_SHADER_32_ABGR:
1552 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
1553 break;
1554 }
1555
1556 /* Pack f16 or norm_i16/u16. */
1557 if (packf) {
1558 for (chan = 0; chan < 2; chan++) {
1559 LLVMValueRef pack_args[2] = {
1560 values[2 * chan],
1561 values[2 * chan + 1]
1562 };
1563 LLVMValueRef packed;
1564
1565 packed = packf(&ctx->ac, pack_args);
1566 args->out[chan] = ac_to_float(&ctx->ac, packed);
1567 }
1568 args->compr = 1; /* COMPR flag */
1569 }
1570
1571 /* Pack i16/u16. */
1572 if (packi) {
1573 for (chan = 0; chan < 2; chan++) {
1574 LLVMValueRef pack_args[2] = {
1575 ac_to_integer(&ctx->ac, values[2 * chan]),
1576 ac_to_integer(&ctx->ac, values[2 * chan + 1])
1577 };
1578 LLVMValueRef packed;
1579
1580 packed = packi(&ctx->ac, pack_args,
1581 is_int8 ? 8 : is_int10 ? 10 : 16,
1582 chan == 1);
1583 args->out[chan] = ac_to_float(&ctx->ac, packed);
1584 }
1585 args->compr = 1; /* COMPR flag */
1586 }
1587 return;
1588 }
1589
1590 if (is_16bit) {
1591 for (unsigned chan = 0; chan < 4; chan++) {
1592 values[chan] = LLVMBuildBitCast(ctx->ac.builder, values[chan], ctx->ac.i16, "");
1593 args->out[chan] = LLVMBuildZExt(ctx->ac.builder, values[chan], ctx->ac.i32, "");
1594 }
1595 } else
1596 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
1597
1598 for (unsigned i = 0; i < 4; ++i)
1599 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
1600 }
1601
1602 static void
1603 radv_export_param(struct radv_shader_context *ctx, unsigned index,
1604 LLVMValueRef *values, unsigned enabled_channels)
1605 {
1606 struct ac_export_args args;
1607
1608 si_llvm_init_export_args(ctx, values, enabled_channels,
1609 V_008DFC_SQ_EXP_PARAM + index, &args);
1610 ac_build_export(&ctx->ac, &args);
1611 }
1612
1613 static LLVMValueRef
1614 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
1615 {
1616 LLVMValueRef output = ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
1617 return LLVMBuildLoad(ctx->ac.builder, output, "");
1618 }
1619
1620 static void
1621 radv_emit_stream_output(struct radv_shader_context *ctx,
1622 LLVMValueRef const *so_buffers,
1623 LLVMValueRef const *so_write_offsets,
1624 const struct radv_stream_output *output,
1625 struct radv_shader_output_values *shader_out)
1626 {
1627 unsigned num_comps = util_bitcount(output->component_mask);
1628 unsigned buf = output->buffer;
1629 unsigned offset = output->offset;
1630 unsigned start;
1631 LLVMValueRef out[4];
1632
1633 assert(num_comps && num_comps <= 4);
1634 if (!num_comps || num_comps > 4)
1635 return;
1636
1637 /* Get the first component. */
1638 start = ffs(output->component_mask) - 1;
1639
1640 /* Load the output as int. */
1641 for (int i = 0; i < num_comps; i++) {
1642 out[i] = ac_to_integer(&ctx->ac, shader_out->values[start + i]);
1643 }
1644
1645 /* Pack the output. */
1646 LLVMValueRef vdata = NULL;
1647
1648 switch (num_comps) {
1649 case 1: /* as i32 */
1650 vdata = out[0];
1651 break;
1652 case 2: /* as v2i32 */
1653 case 3: /* as v4i32 (aligned to 4) */
1654 out[3] = LLVMGetUndef(ctx->ac.i32);
1655 /* fall through */
1656 case 4: /* as v4i32 */
1657 vdata = ac_build_gather_values(&ctx->ac, out,
1658 !ac_has_vec3_support(ctx->ac.chip_class, false) ?
1659 util_next_power_of_two(num_comps) :
1660 num_comps);
1661 break;
1662 }
1663
1664 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf],
1665 vdata, num_comps, so_write_offsets[buf],
1666 ctx->ac.i32_0, offset,
1667 ac_glc | ac_slc);
1668 }
1669
1670 static void
1671 radv_emit_streamout(struct radv_shader_context *ctx, unsigned stream)
1672 {
1673 int i;
1674
1675 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1676 assert(ctx->args->streamout_config.used);
1677 LLVMValueRef so_vtx_count =
1678 ac_build_bfe(&ctx->ac,
1679 ac_get_arg(&ctx->ac, ctx->args->streamout_config),
1680 LLVMConstInt(ctx->ac.i32, 16, false),
1681 LLVMConstInt(ctx->ac.i32, 7, false), false);
1682
1683 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
1684
1685 /* can_emit = tid < so_vtx_count; */
1686 LLVMValueRef can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
1687 tid, so_vtx_count, "");
1688
1689 /* Emit the streamout code conditionally. This actually avoids
1690 * out-of-bounds buffer access. The hw tells us via the SGPR
1691 * (so_vtx_count) which threads are allowed to emit streamout data.
1692 */
1693 ac_build_ifcc(&ctx->ac, can_emit, 6501);
1694 {
1695 /* The buffer offset is computed as follows:
1696 * ByteOffset = streamout_offset[buffer_id]*4 +
1697 * (streamout_write_index + thread_id)*stride[buffer_id] +
1698 * attrib_offset
1699 */
1700 LLVMValueRef so_write_index =
1701 ac_get_arg(&ctx->ac, ctx->args->streamout_write_idx);
1702
1703 /* Compute (streamout_write_index + thread_id). */
1704 so_write_index =
1705 LLVMBuildAdd(ctx->ac.builder, so_write_index, tid, "");
1706
1707 /* Load the descriptor and compute the write offset for each
1708 * enabled buffer.
1709 */
1710 LLVMValueRef so_write_offset[4] = {};
1711 LLVMValueRef so_buffers[4] = {};
1712 LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac, ctx->args->streamout_buffers);
1713
1714 for (i = 0; i < 4; i++) {
1715 uint16_t stride = ctx->args->shader_info->so.strides[i];
1716
1717 if (!stride)
1718 continue;
1719
1720 LLVMValueRef offset =
1721 LLVMConstInt(ctx->ac.i32, i, false);
1722
1723 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac,
1724 buf_ptr, offset);
1725
1726 LLVMValueRef so_offset =
1727 ac_get_arg(&ctx->ac, ctx->args->streamout_offset[i]);
1728
1729 so_offset = LLVMBuildMul(ctx->ac.builder, so_offset,
1730 LLVMConstInt(ctx->ac.i32, 4, false), "");
1731
1732 so_write_offset[i] =
1733 ac_build_imad(&ctx->ac, so_write_index,
1734 LLVMConstInt(ctx->ac.i32,
1735 stride * 4, false),
1736 so_offset);
1737 }
1738
1739 /* Write streamout data. */
1740 for (i = 0; i < ctx->args->shader_info->so.num_outputs; i++) {
1741 struct radv_shader_output_values shader_out = {};
1742 struct radv_stream_output *output =
1743 &ctx->args->shader_info->so.outputs[i];
1744
1745 if (stream != output->stream)
1746 continue;
1747
1748 for (int j = 0; j < 4; j++) {
1749 shader_out.values[j] =
1750 radv_load_output(ctx, output->location, j);
1751 }
1752
1753 radv_emit_stream_output(ctx, so_buffers,so_write_offset,
1754 output, &shader_out);
1755 }
1756 }
1757 ac_build_endif(&ctx->ac, 6501);
1758 }
1759
1760 static void
1761 radv_build_param_exports(struct radv_shader_context *ctx,
1762 struct radv_shader_output_values *outputs,
1763 unsigned noutput,
1764 struct radv_vs_output_info *outinfo,
1765 bool export_clip_dists)
1766 {
1767 unsigned param_count = 0;
1768
1769 for (unsigned i = 0; i < noutput; i++) {
1770 unsigned slot_name = outputs[i].slot_name;
1771 unsigned usage_mask = outputs[i].usage_mask;
1772
1773 if (slot_name != VARYING_SLOT_LAYER &&
1774 slot_name != VARYING_SLOT_PRIMITIVE_ID &&
1775 slot_name != VARYING_SLOT_VIEWPORT &&
1776 slot_name != VARYING_SLOT_CLIP_DIST0 &&
1777 slot_name != VARYING_SLOT_CLIP_DIST1 &&
1778 slot_name < VARYING_SLOT_VAR0)
1779 continue;
1780
1781 if ((slot_name == VARYING_SLOT_CLIP_DIST0 ||
1782 slot_name == VARYING_SLOT_CLIP_DIST1) && !export_clip_dists)
1783 continue;
1784
1785 radv_export_param(ctx, param_count, outputs[i].values, usage_mask);
1786
1787 assert(i < ARRAY_SIZE(outinfo->vs_output_param_offset));
1788 outinfo->vs_output_param_offset[slot_name] = param_count++;
1789 }
1790
1791 outinfo->param_exports = param_count;
1792 }
1793
1794 /* Generate export instructions for hardware VS shader stage or NGG GS stage
1795 * (position and parameter data only).
1796 */
1797 static void
1798 radv_llvm_export_vs(struct radv_shader_context *ctx,
1799 struct radv_shader_output_values *outputs,
1800 unsigned noutput,
1801 struct radv_vs_output_info *outinfo,
1802 bool export_clip_dists)
1803 {
1804 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_value = NULL;
1805 struct ac_export_args pos_args[4] = {};
1806 unsigned pos_idx, index;
1807 int i;
1808
1809 /* Build position exports */
1810 for (i = 0; i < noutput; i++) {
1811 switch (outputs[i].slot_name) {
1812 case VARYING_SLOT_POS:
1813 si_llvm_init_export_args(ctx, outputs[i].values, 0xf,
1814 V_008DFC_SQ_EXP_POS, &pos_args[0]);
1815 break;
1816 case VARYING_SLOT_PSIZ:
1817 psize_value = outputs[i].values[0];
1818 break;
1819 case VARYING_SLOT_LAYER:
1820 layer_value = outputs[i].values[0];
1821 break;
1822 case VARYING_SLOT_VIEWPORT:
1823 viewport_value = outputs[i].values[0];
1824 break;
1825 case VARYING_SLOT_CLIP_DIST0:
1826 case VARYING_SLOT_CLIP_DIST1:
1827 index = 2 + outputs[i].slot_index;
1828 si_llvm_init_export_args(ctx, outputs[i].values, 0xf,
1829 V_008DFC_SQ_EXP_POS + index,
1830 &pos_args[index]);
1831 break;
1832 default:
1833 break;
1834 }
1835 }
1836
1837 /* We need to add the position output manually if it's missing. */
1838 if (!pos_args[0].out[0]) {
1839 pos_args[0].enabled_channels = 0xf; /* writemask */
1840 pos_args[0].valid_mask = 0; /* EXEC mask */
1841 pos_args[0].done = 0; /* last export? */
1842 pos_args[0].target = V_008DFC_SQ_EXP_POS;
1843 pos_args[0].compr = 0; /* COMPR flag */
1844 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
1845 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
1846 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
1847 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
1848 }
1849
1850 if (outinfo->writes_pointsize ||
1851 outinfo->writes_layer ||
1852 outinfo->writes_viewport_index) {
1853 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
1854 (outinfo->writes_layer == true ? 4 : 0));
1855 pos_args[1].valid_mask = 0;
1856 pos_args[1].done = 0;
1857 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
1858 pos_args[1].compr = 0;
1859 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
1860 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
1861 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
1862 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
1863
1864 if (outinfo->writes_pointsize == true)
1865 pos_args[1].out[0] = psize_value;
1866 if (outinfo->writes_layer == true)
1867 pos_args[1].out[2] = layer_value;
1868 if (outinfo->writes_viewport_index == true) {
1869 if (ctx->args->options->chip_class >= GFX9) {
1870 /* GFX9 has the layer in out.z[10:0] and the viewport
1871 * index in out.z[19:16].
1872 */
1873 LLVMValueRef v = viewport_value;
1874 v = ac_to_integer(&ctx->ac, v);
1875 v = LLVMBuildShl(ctx->ac.builder, v,
1876 LLVMConstInt(ctx->ac.i32, 16, false),
1877 "");
1878 v = LLVMBuildOr(ctx->ac.builder, v,
1879 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
1880
1881 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
1882 pos_args[1].enabled_channels |= 1 << 2;
1883 } else {
1884 pos_args[1].out[3] = viewport_value;
1885 pos_args[1].enabled_channels |= 1 << 3;
1886 }
1887 }
1888 }
1889
1890 for (i = 0; i < 4; i++) {
1891 if (pos_args[i].out[0])
1892 outinfo->pos_exports++;
1893 }
1894
1895 /* GFX10 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
1896 * Setting valid_mask=1 prevents it and has no other effect.
1897 */
1898 if (ctx->ac.chip_class == GFX10)
1899 pos_args[0].valid_mask = 1;
1900
1901 pos_idx = 0;
1902 for (i = 0; i < 4; i++) {
1903 if (!pos_args[i].out[0])
1904 continue;
1905
1906 /* Specify the target we are exporting */
1907 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
1908
1909 if (pos_idx == outinfo->pos_exports)
1910 /* Specify that this is the last export */
1911 pos_args[i].done = 1;
1912
1913 ac_build_export(&ctx->ac, &pos_args[i]);
1914 }
1915
1916 /* Build parameter exports */
1917 radv_build_param_exports(ctx, outputs, noutput, outinfo, export_clip_dists);
1918 }
1919
1920 static void
1921 handle_vs_outputs_post(struct radv_shader_context *ctx,
1922 bool export_prim_id,
1923 bool export_clip_dists,
1924 struct radv_vs_output_info *outinfo)
1925 {
1926 struct radv_shader_output_values *outputs;
1927 unsigned noutput = 0;
1928
1929 if (ctx->args->options->key.has_multiview_view_index) {
1930 LLVMValueRef* tmp_out = &ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
1931 if(!*tmp_out) {
1932 for(unsigned i = 0; i < 4; ++i)
1933 ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
1934 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
1935 }
1936
1937 LLVMValueRef view_index = ac_get_arg(&ctx->ac, ctx->args->ac.view_index);
1938 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, view_index), *tmp_out);
1939 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
1940 }
1941
1942 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
1943 sizeof(outinfo->vs_output_param_offset));
1944 outinfo->pos_exports = 0;
1945
1946 if (!ctx->args->options->use_ngg_streamout &&
1947 ctx->args->shader_info->so.num_outputs &&
1948 !ctx->args->is_gs_copy_shader) {
1949 /* The GS copy shader emission already emits streamout. */
1950 radv_emit_streamout(ctx, 0);
1951 }
1952
1953 /* Allocate a temporary array for the output values. */
1954 unsigned num_outputs = util_bitcount64(ctx->output_mask) + export_prim_id;
1955 outputs = malloc(num_outputs * sizeof(outputs[0]));
1956
1957 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
1958 if (!(ctx->output_mask & (1ull << i)))
1959 continue;
1960
1961 outputs[noutput].slot_name = i;
1962 outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
1963
1964 if (ctx->stage == MESA_SHADER_VERTEX &&
1965 !ctx->args->is_gs_copy_shader) {
1966 outputs[noutput].usage_mask =
1967 ctx->args->shader_info->vs.output_usage_mask[i];
1968 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
1969 outputs[noutput].usage_mask =
1970 ctx->args->shader_info->tes.output_usage_mask[i];
1971 } else {
1972 assert(ctx->args->is_gs_copy_shader);
1973 outputs[noutput].usage_mask =
1974 ctx->args->shader_info->gs.output_usage_mask[i];
1975 }
1976
1977 for (unsigned j = 0; j < 4; j++) {
1978 outputs[noutput].values[j] =
1979 ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
1980 }
1981
1982 noutput++;
1983 }
1984
1985 /* Export PrimitiveID. */
1986 if (export_prim_id) {
1987 outputs[noutput].slot_name = VARYING_SLOT_PRIMITIVE_ID;
1988 outputs[noutput].slot_index = 0;
1989 outputs[noutput].usage_mask = 0x1;
1990 outputs[noutput].values[0] =
1991 ac_get_arg(&ctx->ac, ctx->args->vs_prim_id);
1992 for (unsigned j = 1; j < 4; j++)
1993 outputs[noutput].values[j] = ctx->ac.f32_0;
1994 noutput++;
1995 }
1996
1997 radv_llvm_export_vs(ctx, outputs, noutput, outinfo, export_clip_dists);
1998
1999 free(outputs);
2000 }
2001
2002 static void
2003 handle_es_outputs_post(struct radv_shader_context *ctx,
2004 struct radv_es_output_info *outinfo)
2005 {
2006 int j;
2007 LLVMValueRef lds_base = NULL;
2008
2009 if (ctx->ac.chip_class >= GFX9) {
2010 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
2011 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
2012 LLVMValueRef wave_idx =
2013 ac_unpack_param(&ctx->ac,
2014 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 24, 4);
2015 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
2016 LLVMBuildMul(ctx->ac.builder, wave_idx,
2017 LLVMConstInt(ctx->ac.i32,
2018 ctx->ac.wave_size, false), ""), "");
2019 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
2020 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
2021 }
2022
2023 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2024 LLVMValueRef dw_addr = NULL;
2025 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2026 unsigned output_usage_mask;
2027 int param_index;
2028
2029 if (!(ctx->output_mask & (1ull << i)))
2030 continue;
2031
2032 if (ctx->stage == MESA_SHADER_VERTEX) {
2033 output_usage_mask =
2034 ctx->args->shader_info->vs.output_usage_mask[i];
2035 } else {
2036 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2037 output_usage_mask =
2038 ctx->args->shader_info->tes.output_usage_mask[i];
2039 }
2040
2041 param_index = shader_io_get_unique_index(i);
2042
2043 if (lds_base) {
2044 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2045 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
2046 "");
2047 }
2048
2049 for (j = 0; j < 4; j++) {
2050 if (!(output_usage_mask & (1 << j)))
2051 continue;
2052
2053 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2054 out_val = ac_to_integer(&ctx->ac, out_val);
2055 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
2056
2057 if (ctx->ac.chip_class >= GFX9) {
2058 LLVMValueRef dw_addr_offset =
2059 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2060 LLVMConstInt(ctx->ac.i32,
2061 j, false), "");
2062
2063 ac_lds_store(&ctx->ac, dw_addr_offset, out_val);
2064 } else {
2065 ac_build_buffer_store_dword(&ctx->ac,
2066 ctx->esgs_ring,
2067 out_val, 1,
2068 NULL,
2069 ac_get_arg(&ctx->ac, ctx->args->es2gs_offset),
2070 (4 * param_index + j) * 4,
2071 ac_glc | ac_slc | ac_swizzled);
2072 }
2073 }
2074 }
2075 }
2076
2077 static void
2078 handle_ls_outputs_post(struct radv_shader_context *ctx)
2079 {
2080 LLVMValueRef vertex_id = ctx->rel_auto_id;
2081 uint32_t num_tcs_inputs = util_last_bit64(ctx->args->shader_info->vs.ls_outputs_written);
2082 LLVMValueRef vertex_dw_stride = LLVMConstInt(ctx->ac.i32, num_tcs_inputs * 4, false);
2083 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
2084 vertex_dw_stride, "");
2085
2086 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2087 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2088
2089 if (!(ctx->output_mask & (1ull << i)))
2090 continue;
2091
2092 int param = shader_io_get_unique_index(i);
2093 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
2094 LLVMConstInt(ctx->ac.i32, param * 4, false),
2095 "");
2096 for (unsigned j = 0; j < 4; j++) {
2097 LLVMValueRef value = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2098 value = ac_to_integer(&ctx->ac, value);
2099 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
2100 ac_lds_store(&ctx->ac, dw_addr, value);
2101 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2102 }
2103 }
2104 }
2105
2106 static LLVMValueRef get_wave_id_in_tg(struct radv_shader_context *ctx)
2107 {
2108 return ac_unpack_param(&ctx->ac,
2109 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 24, 4);
2110 }
2111
2112 static LLVMValueRef get_tgsize(struct radv_shader_context *ctx)
2113 {
2114 return ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 28, 4);
2115 }
2116
2117 static LLVMValueRef get_thread_id_in_tg(struct radv_shader_context *ctx)
2118 {
2119 LLVMBuilderRef builder = ctx->ac.builder;
2120 LLVMValueRef tmp;
2121 tmp = LLVMBuildMul(builder, get_wave_id_in_tg(ctx),
2122 LLVMConstInt(ctx->ac.i32, ctx->ac.wave_size, false), "");
2123 return LLVMBuildAdd(builder, tmp, ac_get_thread_id(&ctx->ac), "");
2124 }
2125
2126 static LLVMValueRef ngg_get_vtx_cnt(struct radv_shader_context *ctx)
2127 {
2128 return ac_build_bfe(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_tg_info),
2129 LLVMConstInt(ctx->ac.i32, 12, false),
2130 LLVMConstInt(ctx->ac.i32, 9, false),
2131 false);
2132 }
2133
2134 static LLVMValueRef ngg_get_prim_cnt(struct radv_shader_context *ctx)
2135 {
2136 return ac_build_bfe(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_tg_info),
2137 LLVMConstInt(ctx->ac.i32, 22, false),
2138 LLVMConstInt(ctx->ac.i32, 9, false),
2139 false);
2140 }
2141
2142 static LLVMValueRef ngg_get_ordered_id(struct radv_shader_context *ctx)
2143 {
2144 return ac_build_bfe(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_tg_info),
2145 ctx->ac.i32_0,
2146 LLVMConstInt(ctx->ac.i32, 12, false),
2147 false);
2148 }
2149
2150 static LLVMValueRef
2151 ngg_gs_get_vertex_storage(struct radv_shader_context *ctx)
2152 {
2153 unsigned num_outputs = util_bitcount64(ctx->output_mask);
2154
2155 if (ctx->args->options->key.has_multiview_view_index)
2156 num_outputs++;
2157
2158 LLVMTypeRef elements[2] = {
2159 LLVMArrayType(ctx->ac.i32, 4 * num_outputs),
2160 LLVMArrayType(ctx->ac.i8, 4),
2161 };
2162 LLVMTypeRef type = LLVMStructTypeInContext(ctx->ac.context, elements, 2, false);
2163 type = LLVMPointerType(LLVMArrayType(type, 0), AC_ADDR_SPACE_LDS);
2164 return LLVMBuildBitCast(ctx->ac.builder, ctx->gs_ngg_emit, type, "");
2165 }
2166
2167 /**
2168 * Return a pointer to the LDS storage reserved for the N'th vertex, where N
2169 * is in emit order; that is:
2170 * - during the epilogue, N is the threadidx (relative to the entire threadgroup)
2171 * - during vertex emit, i.e. while the API GS shader invocation is running,
2172 * N = threadidx * gs_max_out_vertices + emitidx
2173 *
2174 * Goals of the LDS memory layout:
2175 * 1. Eliminate bank conflicts on write for geometry shaders that have all emits
2176 * in uniform control flow
2177 * 2. Eliminate bank conflicts on read for export if, additionally, there is no
2178 * culling
2179 * 3. Agnostic to the number of waves (since we don't know it before compiling)
2180 * 4. Allow coalescing of LDS instructions (ds_write_b128 etc.)
2181 * 5. Avoid wasting memory.
2182 *
2183 * We use an AoS layout due to point 4 (this also helps point 3). In an AoS
2184 * layout, elimination of bank conflicts requires that each vertex occupy an
2185 * odd number of dwords. We use the additional dword to store the output stream
2186 * index as well as a flag to indicate whether this vertex ends a primitive
2187 * for rasterization.
2188 *
2189 * Swizzling is required to satisfy points 1 and 2 simultaneously.
2190 *
2191 * Vertices are stored in export order (gsthread * gs_max_out_vertices + emitidx).
2192 * Indices are swizzled in groups of 32, which ensures point 1 without
2193 * disturbing point 2.
2194 *
2195 * \return an LDS pointer to type {[N x i32], [4 x i8]}
2196 */
2197 static LLVMValueRef
2198 ngg_gs_vertex_ptr(struct radv_shader_context *ctx, LLVMValueRef vertexidx)
2199 {
2200 LLVMBuilderRef builder = ctx->ac.builder;
2201 LLVMValueRef storage = ngg_gs_get_vertex_storage(ctx);
2202
2203 /* gs_max_out_vertices = 2^(write_stride_2exp) * some odd number */
2204 unsigned write_stride_2exp = ffs(ctx->shader->info.gs.vertices_out) - 1;
2205 if (write_stride_2exp) {
2206 LLVMValueRef row =
2207 LLVMBuildLShr(builder, vertexidx,
2208 LLVMConstInt(ctx->ac.i32, 5, false), "");
2209 LLVMValueRef swizzle =
2210 LLVMBuildAnd(builder, row,
2211 LLVMConstInt(ctx->ac.i32, (1u << write_stride_2exp) - 1,
2212 false), "");
2213 vertexidx = LLVMBuildXor(builder, vertexidx, swizzle, "");
2214 }
2215
2216 return ac_build_gep0(&ctx->ac, storage, vertexidx);
2217 }
2218
2219 static LLVMValueRef
2220 ngg_gs_emit_vertex_ptr(struct radv_shader_context *ctx, LLVMValueRef gsthread,
2221 LLVMValueRef emitidx)
2222 {
2223 LLVMBuilderRef builder = ctx->ac.builder;
2224 LLVMValueRef tmp;
2225
2226 tmp = LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false);
2227 tmp = LLVMBuildMul(builder, tmp, gsthread, "");
2228 const LLVMValueRef vertexidx = LLVMBuildAdd(builder, tmp, emitidx, "");
2229 return ngg_gs_vertex_ptr(ctx, vertexidx);
2230 }
2231
2232 static LLVMValueRef
2233 ngg_gs_get_emit_output_ptr(struct radv_shader_context *ctx, LLVMValueRef vertexptr,
2234 unsigned out_idx)
2235 {
2236 LLVMValueRef gep_idx[3] = {
2237 ctx->ac.i32_0, /* implied C-style array */
2238 ctx->ac.i32_0, /* first struct entry */
2239 LLVMConstInt(ctx->ac.i32, out_idx, false),
2240 };
2241 return LLVMBuildGEP(ctx->ac.builder, vertexptr, gep_idx, 3, "");
2242 }
2243
2244 static LLVMValueRef
2245 ngg_gs_get_emit_primflag_ptr(struct radv_shader_context *ctx, LLVMValueRef vertexptr,
2246 unsigned stream)
2247 {
2248 LLVMValueRef gep_idx[3] = {
2249 ctx->ac.i32_0, /* implied C-style array */
2250 ctx->ac.i32_1, /* second struct entry */
2251 LLVMConstInt(ctx->ac.i32, stream, false),
2252 };
2253 return LLVMBuildGEP(ctx->ac.builder, vertexptr, gep_idx, 3, "");
2254 }
2255
2256 static struct radv_stream_output *
2257 radv_get_stream_output_by_loc(struct radv_streamout_info *so, unsigned location)
2258 {
2259 for (unsigned i = 0; i < so->num_outputs; ++i) {
2260 if (so->outputs[i].location == location)
2261 return &so->outputs[i];
2262 }
2263
2264 return NULL;
2265 }
2266
2267 static void build_streamout_vertex(struct radv_shader_context *ctx,
2268 LLVMValueRef *so_buffer, LLVMValueRef *wg_offset_dw,
2269 unsigned stream, LLVMValueRef offset_vtx,
2270 LLVMValueRef vertexptr)
2271 {
2272 struct radv_streamout_info *so = &ctx->args->shader_info->so;
2273 LLVMBuilderRef builder = ctx->ac.builder;
2274 LLVMValueRef offset[4] = {};
2275 LLVMValueRef tmp;
2276
2277 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2278 if (!wg_offset_dw[buffer])
2279 continue;
2280
2281 tmp = LLVMBuildMul(builder, offset_vtx,
2282 LLVMConstInt(ctx->ac.i32, so->strides[buffer], false), "");
2283 tmp = LLVMBuildAdd(builder, wg_offset_dw[buffer], tmp, "");
2284 offset[buffer] = LLVMBuildShl(builder, tmp, LLVMConstInt(ctx->ac.i32, 2, false), "");
2285 }
2286
2287 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2288 struct radv_shader_output_values outputs[AC_LLVM_MAX_OUTPUTS];
2289 unsigned noutput = 0;
2290 unsigned out_idx = 0;
2291
2292 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2293 unsigned output_usage_mask =
2294 ctx->args->shader_info->gs.output_usage_mask[i];
2295 uint8_t output_stream =
2296 output_stream = ctx->args->shader_info->gs.output_streams[i];
2297
2298 if (!(ctx->output_mask & (1ull << i)) ||
2299 output_stream != stream)
2300 continue;
2301
2302 outputs[noutput].slot_name = i;
2303 outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
2304 outputs[noutput].usage_mask = output_usage_mask;
2305
2306 int length = util_last_bit(output_usage_mask);
2307
2308 for (unsigned j = 0; j < length; j++, out_idx++) {
2309 if (!(output_usage_mask & (1 << j)))
2310 continue;
2311
2312 tmp = ac_build_gep0(&ctx->ac, vertexptr,
2313 LLVMConstInt(ctx->ac.i32, out_idx, false));
2314 outputs[noutput].values[j] = LLVMBuildLoad(builder, tmp, "");
2315 }
2316
2317 for (unsigned j = length; j < 4; j++)
2318 outputs[noutput].values[j] = LLVMGetUndef(ctx->ac.f32);
2319
2320 noutput++;
2321 }
2322
2323 for (unsigned i = 0; i < noutput; i++) {
2324 struct radv_stream_output *output =
2325 radv_get_stream_output_by_loc(so, outputs[i].slot_name);
2326
2327 if (!output ||
2328 output->stream != stream)
2329 continue;
2330
2331 struct radv_shader_output_values out = {};
2332
2333 for (unsigned j = 0; j < 4; j++) {
2334 out.values[j] = outputs[i].values[j];
2335 }
2336
2337 radv_emit_stream_output(ctx, so_buffer, offset, output, &out);
2338 }
2339 } else {
2340 for (unsigned i = 0; i < so->num_outputs; ++i) {
2341 struct radv_stream_output *output =
2342 &ctx->args->shader_info->so.outputs[i];
2343
2344 if (stream != output->stream)
2345 continue;
2346
2347 struct radv_shader_output_values out = {};
2348
2349 for (unsigned comp = 0; comp < 4; comp++) {
2350 if (!(output->component_mask & (1 << comp)))
2351 continue;
2352
2353 tmp = ac_build_gep0(&ctx->ac, vertexptr,
2354 LLVMConstInt(ctx->ac.i32, 4 * i + comp, false));
2355 out.values[comp] = LLVMBuildLoad(builder, tmp, "");
2356 }
2357
2358 radv_emit_stream_output(ctx, so_buffer, offset, output, &out);
2359 }
2360 }
2361 }
2362
2363 struct ngg_streamout {
2364 LLVMValueRef num_vertices;
2365
2366 /* per-thread data */
2367 LLVMValueRef prim_enable[4]; /* i1 per stream */
2368 LLVMValueRef vertices[3]; /* [N x i32] addrspace(LDS)* */
2369
2370 /* Output */
2371 LLVMValueRef emit[4]; /* per-stream emitted primitives (only valid for used streams) */
2372 };
2373
2374 /**
2375 * Build streamout logic.
2376 *
2377 * Implies a barrier.
2378 *
2379 * Writes number of emitted primitives to gs_ngg_scratch[4:7].
2380 *
2381 * Clobbers gs_ngg_scratch[8:].
2382 */
2383 static void build_streamout(struct radv_shader_context *ctx,
2384 struct ngg_streamout *nggso)
2385 {
2386 struct radv_streamout_info *so = &ctx->args->shader_info->so;
2387 LLVMBuilderRef builder = ctx->ac.builder;
2388 LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac, ctx->args->streamout_buffers);
2389 LLVMValueRef tid = get_thread_id_in_tg(ctx);
2390 LLVMValueRef cond, tmp, tmp2;
2391 LLVMValueRef i32_2 = LLVMConstInt(ctx->ac.i32, 2, false);
2392 LLVMValueRef i32_4 = LLVMConstInt(ctx->ac.i32, 4, false);
2393 LLVMValueRef i32_8 = LLVMConstInt(ctx->ac.i32, 8, false);
2394 LLVMValueRef so_buffer[4] = {};
2395 unsigned max_num_vertices = 1 + (nggso->vertices[1] ? 1 : 0) +
2396 (nggso->vertices[2] ? 1 : 0);
2397 LLVMValueRef prim_stride_dw[4] = {};
2398 LLVMValueRef prim_stride_dw_vgpr = LLVMGetUndef(ctx->ac.i32);
2399 int stream_for_buffer[4] = { -1, -1, -1, -1 };
2400 unsigned bufmask_for_stream[4] = {};
2401 bool isgs = ctx->stage == MESA_SHADER_GEOMETRY;
2402 unsigned scratch_emit_base = isgs ? 4 : 0;
2403 LLVMValueRef scratch_emit_basev = isgs ? i32_4 : ctx->ac.i32_0;
2404 unsigned scratch_offset_base = isgs ? 8 : 4;
2405 LLVMValueRef scratch_offset_basev = isgs ? i32_8 : i32_4;
2406
2407 ac_llvm_add_target_dep_function_attr(ctx->main_function,
2408 "amdgpu-gds-size", 256);
2409
2410 /* Determine the mapping of streamout buffers to vertex streams. */
2411 for (unsigned i = 0; i < so->num_outputs; ++i) {
2412 unsigned buf = so->outputs[i].buffer;
2413 unsigned stream = so->outputs[i].stream;
2414 assert(stream_for_buffer[buf] < 0 || stream_for_buffer[buf] == stream);
2415 stream_for_buffer[buf] = stream;
2416 bufmask_for_stream[stream] |= 1 << buf;
2417 }
2418
2419 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2420 if (stream_for_buffer[buffer] == -1)
2421 continue;
2422
2423 assert(so->strides[buffer]);
2424
2425 LLVMValueRef stride_for_buffer =
2426 LLVMConstInt(ctx->ac.i32, so->strides[buffer], false);
2427 prim_stride_dw[buffer] =
2428 LLVMBuildMul(builder, stride_for_buffer,
2429 nggso->num_vertices, "");
2430 prim_stride_dw_vgpr = ac_build_writelane(
2431 &ctx->ac, prim_stride_dw_vgpr, prim_stride_dw[buffer],
2432 LLVMConstInt(ctx->ac.i32, buffer, false));
2433
2434 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, buffer, false);
2435 so_buffer[buffer] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr,
2436 offset);
2437 }
2438
2439 cond = LLVMBuildICmp(builder, LLVMIntEQ, get_wave_id_in_tg(ctx), ctx->ac.i32_0, "");
2440 ac_build_ifcc(&ctx->ac, cond, 5200);
2441 {
2442 LLVMTypeRef gdsptr = LLVMPointerType(ctx->ac.i32, AC_ADDR_SPACE_GDS);
2443 LLVMValueRef gdsbase = LLVMBuildIntToPtr(builder, ctx->ac.i32_0, gdsptr, "");
2444
2445 /* Advance the streamout offsets in GDS. */
2446 LLVMValueRef offsets_vgpr = ac_build_alloca_undef(&ctx->ac, ctx->ac.i32, "");
2447 LLVMValueRef generated_by_stream_vgpr = ac_build_alloca_undef(&ctx->ac, ctx->ac.i32, "");
2448
2449 cond = LLVMBuildICmp(builder, LLVMIntULT, ac_get_thread_id(&ctx->ac), i32_4, "");
2450 ac_build_ifcc(&ctx->ac, cond, 5210);
2451 {
2452 /* Fetch the number of generated primitives and store
2453 * it in GDS for later use.
2454 */
2455 if (isgs) {
2456 tmp = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tid);
2457 tmp = LLVMBuildLoad(builder, tmp, "");
2458 } else {
2459 tmp = ac_build_writelane(&ctx->ac, ctx->ac.i32_0,
2460 ngg_get_prim_cnt(ctx), ctx->ac.i32_0);
2461 }
2462 LLVMBuildStore(builder, tmp, generated_by_stream_vgpr);
2463
2464 unsigned swizzle[4];
2465 int unused_stream = -1;
2466 for (unsigned stream = 0; stream < 4; ++stream) {
2467 if (!ctx->args->shader_info->gs.num_stream_output_components[stream]) {
2468 unused_stream = stream;
2469 break;
2470 }
2471 }
2472 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2473 if (stream_for_buffer[buffer] >= 0) {
2474 swizzle[buffer] = stream_for_buffer[buffer];
2475 } else {
2476 assert(unused_stream >= 0);
2477 swizzle[buffer] = unused_stream;
2478 }
2479 }
2480
2481 tmp = ac_build_quad_swizzle(&ctx->ac, tmp,
2482 swizzle[0], swizzle[1], swizzle[2], swizzle[3]);
2483 tmp = LLVMBuildMul(builder, tmp, prim_stride_dw_vgpr, "");
2484
2485 LLVMValueRef args[] = {
2486 LLVMBuildIntToPtr(builder, ngg_get_ordered_id(ctx), gdsptr, ""),
2487 tmp,
2488 ctx->ac.i32_0, // ordering
2489 ctx->ac.i32_0, // scope
2490 ctx->ac.i1false, // isVolatile
2491 LLVMConstInt(ctx->ac.i32, 4 << 24, false), // OA index
2492 ctx->ac.i1true, // wave release
2493 ctx->ac.i1true, // wave done
2494 };
2495
2496 tmp = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.ds.ordered.add",
2497 ctx->ac.i32, args, ARRAY_SIZE(args), 0);
2498
2499 /* Keep offsets in a VGPR for quick retrieval via readlane by
2500 * the first wave for bounds checking, and also store in LDS
2501 * for retrieval by all waves later. */
2502 LLVMBuildStore(builder, tmp, offsets_vgpr);
2503
2504 tmp2 = LLVMBuildAdd(builder, ac_get_thread_id(&ctx->ac),
2505 scratch_offset_basev, "");
2506 tmp2 = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tmp2);
2507 LLVMBuildStore(builder, tmp, tmp2);
2508 }
2509 ac_build_endif(&ctx->ac, 5210);
2510
2511 /* Determine the max emit per buffer. This is done via the SALU, in part
2512 * because LLVM can't generate divide-by-multiply if we try to do this
2513 * via VALU with one lane per buffer.
2514 */
2515 LLVMValueRef max_emit[4] = {};
2516 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2517 if (stream_for_buffer[buffer] == -1)
2518 continue;
2519
2520 /* Compute the streamout buffer size in DWORD. */
2521 LLVMValueRef bufsize_dw =
2522 LLVMBuildLShr(builder,
2523 LLVMBuildExtractElement(builder, so_buffer[buffer], i32_2, ""),
2524 i32_2, "");
2525
2526 /* Load the streamout buffer offset from GDS. */
2527 tmp = LLVMBuildLoad(builder, offsets_vgpr, "");
2528 LLVMValueRef offset_dw =
2529 ac_build_readlane(&ctx->ac, tmp,
2530 LLVMConstInt(ctx->ac.i32, buffer, false));
2531
2532 /* Compute the remaining size to emit. */
2533 LLVMValueRef remaining_dw =
2534 LLVMBuildSub(builder, bufsize_dw, offset_dw, "");
2535 tmp = LLVMBuildUDiv(builder, remaining_dw,
2536 prim_stride_dw[buffer], "");
2537
2538 cond = LLVMBuildICmp(builder, LLVMIntULT,
2539 bufsize_dw, offset_dw, "");
2540 max_emit[buffer] = LLVMBuildSelect(builder, cond,
2541 ctx->ac.i32_0, tmp, "");
2542 }
2543
2544 /* Determine the number of emitted primitives per stream and fixup the
2545 * GDS counter if necessary.
2546 *
2547 * This is complicated by the fact that a single stream can emit to
2548 * multiple buffers (but luckily not vice versa).
2549 */
2550 LLVMValueRef emit_vgpr = ctx->ac.i32_0;
2551
2552 for (unsigned stream = 0; stream < 4; ++stream) {
2553 if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
2554 continue;
2555
2556 /* Load the number of generated primitives from GDS and
2557 * determine that number for the given stream.
2558 */
2559 tmp = LLVMBuildLoad(builder, generated_by_stream_vgpr, "");
2560 LLVMValueRef generated =
2561 ac_build_readlane(&ctx->ac, tmp,
2562 LLVMConstInt(ctx->ac.i32, stream, false));
2563
2564
2565 /* Compute the number of emitted primitives. */
2566 LLVMValueRef emit = generated;
2567 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2568 if (stream_for_buffer[buffer] == stream)
2569 emit = ac_build_umin(&ctx->ac, emit, max_emit[buffer]);
2570 }
2571
2572 /* Store the number of emitted primitives for that
2573 * stream.
2574 */
2575 emit_vgpr = ac_build_writelane(&ctx->ac, emit_vgpr, emit,
2576 LLVMConstInt(ctx->ac.i32, stream, false));
2577
2578 /* Fixup the offset using a plain GDS atomic if we overflowed. */
2579 cond = LLVMBuildICmp(builder, LLVMIntULT, emit, generated, "");
2580 ac_build_ifcc(&ctx->ac, cond, 5221); /* scalar branch */
2581 tmp = LLVMBuildLShr(builder,
2582 LLVMConstInt(ctx->ac.i32, bufmask_for_stream[stream], false),
2583 ac_get_thread_id(&ctx->ac), "");
2584 tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
2585 ac_build_ifcc(&ctx->ac, tmp, 5222);
2586 {
2587 tmp = LLVMBuildSub(builder, generated, emit, "");
2588 tmp = LLVMBuildMul(builder, tmp, prim_stride_dw_vgpr, "");
2589 tmp2 = LLVMBuildGEP(builder, gdsbase, &tid, 1, "");
2590 LLVMBuildAtomicRMW(builder, LLVMAtomicRMWBinOpSub, tmp2, tmp,
2591 LLVMAtomicOrderingMonotonic, false);
2592 }
2593 ac_build_endif(&ctx->ac, 5222);
2594 ac_build_endif(&ctx->ac, 5221);
2595 }
2596
2597 /* Store the number of emitted primitives to LDS for later use. */
2598 cond = LLVMBuildICmp(builder, LLVMIntULT, ac_get_thread_id(&ctx->ac), i32_4, "");
2599 ac_build_ifcc(&ctx->ac, cond, 5225);
2600 {
2601 tmp = LLVMBuildAdd(builder, ac_get_thread_id(&ctx->ac),
2602 scratch_emit_basev, "");
2603 tmp = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tmp);
2604 LLVMBuildStore(builder, emit_vgpr, tmp);
2605 }
2606 ac_build_endif(&ctx->ac, 5225);
2607 }
2608 ac_build_endif(&ctx->ac, 5200);
2609
2610 /* Determine the workgroup-relative per-thread / primitive offset into
2611 * the streamout buffers */
2612 struct ac_wg_scan primemit_scan[4] = {};
2613
2614 if (isgs) {
2615 for (unsigned stream = 0; stream < 4; ++stream) {
2616 if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
2617 continue;
2618
2619 primemit_scan[stream].enable_exclusive = true;
2620 primemit_scan[stream].op = nir_op_iadd;
2621 primemit_scan[stream].src = nggso->prim_enable[stream];
2622 primemit_scan[stream].scratch =
2623 ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch,
2624 LLVMConstInt(ctx->ac.i32, 12 + 8 * stream, false));
2625 primemit_scan[stream].waveidx = get_wave_id_in_tg(ctx);
2626 primemit_scan[stream].numwaves = get_tgsize(ctx);
2627 primemit_scan[stream].maxwaves = 8;
2628 ac_build_wg_scan_top(&ctx->ac, &primemit_scan[stream]);
2629 }
2630 }
2631
2632 ac_build_s_barrier(&ctx->ac);
2633
2634 /* Fetch the per-buffer offsets and per-stream emit counts in all waves. */
2635 LLVMValueRef wgoffset_dw[4] = {};
2636
2637 {
2638 LLVMValueRef scratch_vgpr;
2639
2640 tmp = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, ac_get_thread_id(&ctx->ac));
2641 scratch_vgpr = LLVMBuildLoad(builder, tmp, "");
2642
2643 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2644 if (stream_for_buffer[buffer] >= 0) {
2645 wgoffset_dw[buffer] = ac_build_readlane(
2646 &ctx->ac, scratch_vgpr,
2647 LLVMConstInt(ctx->ac.i32, scratch_offset_base + buffer, false));
2648 }
2649 }
2650
2651 for (unsigned stream = 0; stream < 4; ++stream) {
2652 if (ctx->args->shader_info->gs.num_stream_output_components[stream]) {
2653 nggso->emit[stream] = ac_build_readlane(
2654 &ctx->ac, scratch_vgpr,
2655 LLVMConstInt(ctx->ac.i32, scratch_emit_base + stream, false));
2656 }
2657 }
2658 }
2659
2660 /* Write out primitive data */
2661 for (unsigned stream = 0; stream < 4; ++stream) {
2662 if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
2663 continue;
2664
2665 if (isgs) {
2666 ac_build_wg_scan_bottom(&ctx->ac, &primemit_scan[stream]);
2667 } else {
2668 primemit_scan[stream].result_exclusive = tid;
2669 }
2670
2671 cond = LLVMBuildICmp(builder, LLVMIntULT,
2672 primemit_scan[stream].result_exclusive,
2673 nggso->emit[stream], "");
2674 cond = LLVMBuildAnd(builder, cond, nggso->prim_enable[stream], "");
2675 ac_build_ifcc(&ctx->ac, cond, 5240);
2676 {
2677 LLVMValueRef offset_vtx =
2678 LLVMBuildMul(builder, primemit_scan[stream].result_exclusive,
2679 nggso->num_vertices, "");
2680
2681 for (unsigned i = 0; i < max_num_vertices; ++i) {
2682 cond = LLVMBuildICmp(builder, LLVMIntULT,
2683 LLVMConstInt(ctx->ac.i32, i, false),
2684 nggso->num_vertices, "");
2685 ac_build_ifcc(&ctx->ac, cond, 5241);
2686 build_streamout_vertex(ctx, so_buffer, wgoffset_dw,
2687 stream, offset_vtx, nggso->vertices[i]);
2688 ac_build_endif(&ctx->ac, 5241);
2689 offset_vtx = LLVMBuildAdd(builder, offset_vtx, ctx->ac.i32_1, "");
2690 }
2691 }
2692 ac_build_endif(&ctx->ac, 5240);
2693 }
2694 }
2695
2696 static unsigned ngg_nogs_vertex_size(struct radv_shader_context *ctx)
2697 {
2698 unsigned lds_vertex_size = 0;
2699
2700 if (ctx->args->shader_info->so.num_outputs)
2701 lds_vertex_size = 4 * ctx->args->shader_info->so.num_outputs + 1;
2702
2703 return lds_vertex_size;
2704 }
2705
2706 /**
2707 * Returns an `[N x i32] addrspace(LDS)*` pointing at contiguous LDS storage
2708 * for the vertex outputs.
2709 */
2710 static LLVMValueRef ngg_nogs_vertex_ptr(struct radv_shader_context *ctx,
2711 LLVMValueRef vtxid)
2712 {
2713 /* The extra dword is used to avoid LDS bank conflicts. */
2714 unsigned vertex_size = ngg_nogs_vertex_size(ctx);
2715 LLVMTypeRef ai32 = LLVMArrayType(ctx->ac.i32, vertex_size);
2716 LLVMTypeRef pai32 = LLVMPointerType(ai32, AC_ADDR_SPACE_LDS);
2717 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, ctx->esgs_ring, pai32, "");
2718 return LLVMBuildGEP(ctx->ac.builder, tmp, &vtxid, 1, "");
2719 }
2720
2721 static void
2722 handle_ngg_outputs_post_1(struct radv_shader_context *ctx)
2723 {
2724 struct radv_streamout_info *so = &ctx->args->shader_info->so;
2725 LLVMBuilderRef builder = ctx->ac.builder;
2726 LLVMValueRef vertex_ptr = NULL;
2727 LLVMValueRef tmp, tmp2;
2728
2729 assert((ctx->stage == MESA_SHADER_VERTEX ||
2730 ctx->stage == MESA_SHADER_TESS_EVAL) && !ctx->args->is_gs_copy_shader);
2731
2732 if (!ctx->args->shader_info->so.num_outputs)
2733 return;
2734
2735 vertex_ptr = ngg_nogs_vertex_ptr(ctx, get_thread_id_in_tg(ctx));
2736
2737 for (unsigned i = 0; i < so->num_outputs; ++i) {
2738 struct radv_stream_output *output =
2739 &ctx->args->shader_info->so.outputs[i];
2740
2741 unsigned loc = output->location;
2742
2743 for (unsigned comp = 0; comp < 4; comp++) {
2744 if (!(output->component_mask & (1 << comp)))
2745 continue;
2746
2747 tmp = ac_build_gep0(&ctx->ac, vertex_ptr,
2748 LLVMConstInt(ctx->ac.i32, 4 * i + comp, false));
2749 tmp2 = LLVMBuildLoad(builder,
2750 ctx->abi.outputs[4 * loc + comp], "");
2751 tmp2 = ac_to_integer(&ctx->ac, tmp2);
2752 LLVMBuildStore(builder, tmp2, tmp);
2753 }
2754 }
2755 }
2756
2757 static void
2758 handle_ngg_outputs_post_2(struct radv_shader_context *ctx)
2759 {
2760 LLVMBuilderRef builder = ctx->ac.builder;
2761 LLVMValueRef tmp;
2762
2763 assert((ctx->stage == MESA_SHADER_VERTEX ||
2764 ctx->stage == MESA_SHADER_TESS_EVAL) && !ctx->args->is_gs_copy_shader);
2765
2766 LLVMValueRef prims_in_wave = ac_unpack_param(&ctx->ac,
2767 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 8, 8);
2768 LLVMValueRef vtx_in_wave = ac_unpack_param(&ctx->ac,
2769 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 0, 8);
2770 LLVMValueRef is_gs_thread = LLVMBuildICmp(builder, LLVMIntULT,
2771 ac_get_thread_id(&ctx->ac), prims_in_wave, "");
2772 LLVMValueRef is_es_thread = LLVMBuildICmp(builder, LLVMIntULT,
2773 ac_get_thread_id(&ctx->ac), vtx_in_wave, "");
2774 LLVMValueRef vtxindex[] = {
2775 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[0]), 0, 16),
2776 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[0]), 16, 16),
2777 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[2]), 0, 16),
2778 };
2779
2780 /* Determine the number of vertices per primitive. */
2781 unsigned num_vertices;
2782 LLVMValueRef num_vertices_val;
2783
2784 if (ctx->stage == MESA_SHADER_VERTEX) {
2785 LLVMValueRef outprim_val =
2786 LLVMConstInt(ctx->ac.i32,
2787 ctx->args->options->key.vs.outprim, false);
2788 num_vertices_val = LLVMBuildAdd(builder, outprim_val,
2789 ctx->ac.i32_1, "");
2790 num_vertices = 3; /* TODO: optimize for points & lines */
2791 } else {
2792 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2793
2794 if (ctx->shader->info.tess.point_mode)
2795 num_vertices = 1;
2796 else if (ctx->shader->info.tess.primitive_mode == GL_ISOLINES)
2797 num_vertices = 2;
2798 else
2799 num_vertices = 3;
2800
2801 num_vertices_val = LLVMConstInt(ctx->ac.i32, num_vertices, false);
2802 }
2803
2804 /* Streamout */
2805 if (ctx->args->shader_info->so.num_outputs) {
2806 struct ngg_streamout nggso = {};
2807
2808 nggso.num_vertices = num_vertices_val;
2809 nggso.prim_enable[0] = is_gs_thread;
2810
2811 for (unsigned i = 0; i < num_vertices; ++i)
2812 nggso.vertices[i] = ngg_nogs_vertex_ptr(ctx, vtxindex[i]);
2813
2814 build_streamout(ctx, &nggso);
2815 }
2816
2817 /* Copy Primitive IDs from GS threads to the LDS address corresponding
2818 * to the ES thread of the provoking vertex.
2819 */
2820 if (ctx->stage == MESA_SHADER_VERTEX &&
2821 ctx->args->options->key.vs_common_out.export_prim_id) {
2822 if (ctx->args->shader_info->so.num_outputs)
2823 ac_build_s_barrier(&ctx->ac);
2824
2825 ac_build_ifcc(&ctx->ac, is_gs_thread, 5400);
2826 /* Extract the PROVOKING_VTX_INDEX field. */
2827 LLVMValueRef provoking_vtx_in_prim =
2828 LLVMConstInt(ctx->ac.i32, 0, false);
2829
2830 /* provoking_vtx_index = vtxindex[provoking_vtx_in_prim]; */
2831 LLVMValueRef indices = ac_build_gather_values(&ctx->ac, vtxindex, 3);
2832 LLVMValueRef provoking_vtx_index =
2833 LLVMBuildExtractElement(builder, indices, provoking_vtx_in_prim, "");
2834
2835 LLVMBuildStore(builder, ac_get_arg(&ctx->ac, ctx->args->ac.gs_prim_id),
2836 ac_build_gep0(&ctx->ac, ctx->esgs_ring, provoking_vtx_index));
2837 ac_build_endif(&ctx->ac, 5400);
2838 }
2839
2840 /* TODO: primitive culling */
2841
2842 ac_build_sendmsg_gs_alloc_req(&ctx->ac, get_wave_id_in_tg(ctx),
2843 ngg_get_vtx_cnt(ctx), ngg_get_prim_cnt(ctx));
2844
2845 /* TODO: streamout queries */
2846 /* Export primitive data to the index buffer.
2847 *
2848 * For the first version, we will always build up all three indices
2849 * independent of the primitive type. The additional garbage data
2850 * shouldn't hurt.
2851 *
2852 * TODO: culling depends on the primitive type, so can have some
2853 * interaction here.
2854 */
2855 ac_build_ifcc(&ctx->ac, is_gs_thread, 6001);
2856 {
2857 struct ac_ngg_prim prim = {};
2858
2859 if (ctx->args->options->key.vs_common_out.as_ngg_passthrough) {
2860 prim.passthrough = ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[0]);
2861 } else {
2862 prim.num_vertices = num_vertices;
2863 prim.isnull = ctx->ac.i1false;
2864 memcpy(prim.index, vtxindex, sizeof(vtxindex[0]) * 3);
2865
2866 for (unsigned i = 0; i < num_vertices; ++i) {
2867 tmp = LLVMBuildLShr(builder,
2868 ac_get_arg(&ctx->ac, ctx->args->ac.gs_invocation_id),
2869 LLVMConstInt(ctx->ac.i32, 8 + i, false), "");
2870 prim.edgeflag[i] = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
2871 }
2872 }
2873
2874 ac_build_export_prim(&ctx->ac, &prim);
2875 }
2876 ac_build_endif(&ctx->ac, 6001);
2877
2878 /* Export per-vertex data (positions and parameters). */
2879 ac_build_ifcc(&ctx->ac, is_es_thread, 6002);
2880 {
2881 struct radv_vs_output_info *outinfo =
2882 ctx->stage == MESA_SHADER_TESS_EVAL ?
2883 &ctx->args->shader_info->tes.outinfo : &ctx->args->shader_info->vs.outinfo;
2884
2885 /* Exporting the primitive ID is handled below. */
2886 /* TODO: use the new VS export path */
2887 handle_vs_outputs_post(ctx, false,
2888 ctx->args->options->key.vs_common_out.export_clip_dists,
2889 outinfo);
2890
2891 if (ctx->args->options->key.vs_common_out.export_prim_id) {
2892 unsigned param_count = outinfo->param_exports;
2893 LLVMValueRef values[4];
2894
2895 if (ctx->stage == MESA_SHADER_VERTEX) {
2896 /* Wait for GS stores to finish. */
2897 ac_build_s_barrier(&ctx->ac);
2898
2899 tmp = ac_build_gep0(&ctx->ac, ctx->esgs_ring,
2900 get_thread_id_in_tg(ctx));
2901 values[0] = LLVMBuildLoad(builder, tmp, "");
2902 } else {
2903 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2904 values[0] = ac_get_arg(&ctx->ac, ctx->args->ac.tes_patch_id);
2905 }
2906
2907 values[0] = ac_to_float(&ctx->ac, values[0]);
2908 for (unsigned j = 1; j < 4; j++)
2909 values[j] = ctx->ac.f32_0;
2910
2911 radv_export_param(ctx, param_count, values, 0x1);
2912
2913 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
2914 outinfo->param_exports = param_count;
2915 }
2916 }
2917 ac_build_endif(&ctx->ac, 6002);
2918 }
2919
2920 static void gfx10_ngg_gs_emit_prologue(struct radv_shader_context *ctx)
2921 {
2922 /* Zero out the part of LDS scratch that is used to accumulate the
2923 * per-stream generated primitive count.
2924 */
2925 LLVMBuilderRef builder = ctx->ac.builder;
2926 LLVMValueRef scratchptr = ctx->gs_ngg_scratch;
2927 LLVMValueRef tid = get_thread_id_in_tg(ctx);
2928 LLVMBasicBlockRef merge_block;
2929 LLVMValueRef cond;
2930
2931 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
2932 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
2933 merge_block = LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
2934
2935 cond = LLVMBuildICmp(builder, LLVMIntULT, tid, LLVMConstInt(ctx->ac.i32, 4, false), "");
2936 LLVMBuildCondBr(ctx->ac.builder, cond, then_block, merge_block);
2937 LLVMPositionBuilderAtEnd(ctx->ac.builder, then_block);
2938
2939 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, scratchptr, tid);
2940 LLVMBuildStore(builder, ctx->ac.i32_0, ptr);
2941
2942 LLVMBuildBr(ctx->ac.builder, merge_block);
2943 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
2944
2945 ac_build_s_barrier(&ctx->ac);
2946 }
2947
2948 static void gfx10_ngg_gs_emit_epilogue_1(struct radv_shader_context *ctx)
2949 {
2950 LLVMBuilderRef builder = ctx->ac.builder;
2951 LLVMValueRef i8_0 = LLVMConstInt(ctx->ac.i8, 0, false);
2952 LLVMValueRef tmp;
2953
2954 /* Zero out remaining (non-emitted) primitive flags.
2955 *
2956 * Note: Alternatively, we could pass the relevant gs_next_vertex to
2957 * the emit threads via LDS. This is likely worse in the expected
2958 * typical case where each GS thread emits the full set of
2959 * vertices.
2960 */
2961 for (unsigned stream = 0; stream < 4; ++stream) {
2962 unsigned num_components;
2963
2964 num_components =
2965 ctx->args->shader_info->gs.num_stream_output_components[stream];
2966 if (!num_components)
2967 continue;
2968
2969 const LLVMValueRef gsthread = get_thread_id_in_tg(ctx);
2970
2971 ac_build_bgnloop(&ctx->ac, 5100);
2972
2973 const LLVMValueRef vertexidx =
2974 LLVMBuildLoad(builder, ctx->gs_next_vertex[stream], "");
2975 tmp = LLVMBuildICmp(builder, LLVMIntUGE, vertexidx,
2976 LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false), "");
2977 ac_build_ifcc(&ctx->ac, tmp, 5101);
2978 ac_build_break(&ctx->ac);
2979 ac_build_endif(&ctx->ac, 5101);
2980
2981 tmp = LLVMBuildAdd(builder, vertexidx, ctx->ac.i32_1, "");
2982 LLVMBuildStore(builder, tmp, ctx->gs_next_vertex[stream]);
2983
2984 tmp = ngg_gs_emit_vertex_ptr(ctx, gsthread, vertexidx);
2985 LLVMBuildStore(builder, i8_0,
2986 ngg_gs_get_emit_primflag_ptr(ctx, tmp, stream));
2987
2988 ac_build_endloop(&ctx->ac, 5100);
2989 }
2990
2991 /* Accumulate generated primitives counts across the entire threadgroup. */
2992 for (unsigned stream = 0; stream < 4; ++stream) {
2993 unsigned num_components;
2994
2995 num_components =
2996 ctx->args->shader_info->gs.num_stream_output_components[stream];
2997 if (!num_components)
2998 continue;
2999
3000 LLVMValueRef numprims =
3001 LLVMBuildLoad(builder, ctx->gs_generated_prims[stream], "");
3002 numprims = ac_build_reduce(&ctx->ac, numprims, nir_op_iadd, ctx->ac.wave_size);
3003
3004 tmp = LLVMBuildICmp(builder, LLVMIntEQ, ac_get_thread_id(&ctx->ac), ctx->ac.i32_0, "");
3005 ac_build_ifcc(&ctx->ac, tmp, 5105);
3006 {
3007 LLVMBuildAtomicRMW(builder, LLVMAtomicRMWBinOpAdd,
3008 ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch,
3009 LLVMConstInt(ctx->ac.i32, stream, false)),
3010 numprims, LLVMAtomicOrderingMonotonic, false);
3011 }
3012 ac_build_endif(&ctx->ac, 5105);
3013 }
3014 }
3015
3016 static void gfx10_ngg_gs_emit_epilogue_2(struct radv_shader_context *ctx)
3017 {
3018 const unsigned verts_per_prim = si_conv_gl_prim_to_vertices(ctx->shader->info.gs.output_primitive);
3019 LLVMBuilderRef builder = ctx->ac.builder;
3020 LLVMValueRef tmp, tmp2;
3021
3022 ac_build_s_barrier(&ctx->ac);
3023
3024 const LLVMValueRef tid = get_thread_id_in_tg(ctx);
3025 LLVMValueRef num_emit_threads = ngg_get_prim_cnt(ctx);
3026
3027 /* Streamout */
3028 if (ctx->args->shader_info->so.num_outputs) {
3029 struct ngg_streamout nggso = {};
3030
3031 nggso.num_vertices = LLVMConstInt(ctx->ac.i32, verts_per_prim, false);
3032
3033 LLVMValueRef vertexptr = ngg_gs_vertex_ptr(ctx, tid);
3034 for (unsigned stream = 0; stream < 4; ++stream) {
3035 if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
3036 continue;
3037
3038 tmp = LLVMBuildLoad(builder,
3039 ngg_gs_get_emit_primflag_ptr(ctx, vertexptr, stream), "");
3040 tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3041 tmp2 = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
3042 nggso.prim_enable[stream] = LLVMBuildAnd(builder, tmp, tmp2, "");
3043 }
3044
3045 for (unsigned i = 0; i < verts_per_prim; ++i) {
3046 tmp = LLVMBuildSub(builder, tid,
3047 LLVMConstInt(ctx->ac.i32, verts_per_prim - i - 1, false), "");
3048 tmp = ngg_gs_vertex_ptr(ctx, tmp);
3049 nggso.vertices[i] = ac_build_gep0(&ctx->ac, tmp, ctx->ac.i32_0);
3050 }
3051
3052 build_streamout(ctx, &nggso);
3053 }
3054
3055 /* Write shader query data. */
3056 tmp = ac_get_arg(&ctx->ac, ctx->args->ngg_gs_state);
3057 tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3058 ac_build_ifcc(&ctx->ac, tmp, 5109);
3059 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid,
3060 LLVMConstInt(ctx->ac.i32, 4, false), "");
3061 ac_build_ifcc(&ctx->ac, tmp, 5110);
3062 {
3063 tmp = LLVMBuildLoad(builder, ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tid), "");
3064
3065 ac_llvm_add_target_dep_function_attr(ctx->main_function,
3066 "amdgpu-gds-size", 256);
3067
3068 LLVMTypeRef gdsptr = LLVMPointerType(ctx->ac.i32, AC_ADDR_SPACE_GDS);
3069 LLVMValueRef gdsbase = LLVMBuildIntToPtr(builder, ctx->ac.i32_0, gdsptr, "");
3070
3071 const char *sync_scope = LLVM_VERSION_MAJOR >= 9 ? "workgroup-one-as" : "workgroup";
3072
3073 /* Use a plain GDS atomic to accumulate the number of generated
3074 * primitives.
3075 */
3076 ac_build_atomic_rmw(&ctx->ac, LLVMAtomicRMWBinOpAdd, gdsbase,
3077 tmp, sync_scope);
3078 }
3079 ac_build_endif(&ctx->ac, 5110);
3080 ac_build_endif(&ctx->ac, 5109);
3081
3082 /* TODO: culling */
3083
3084 /* Determine vertex liveness. */
3085 LLVMValueRef vertliveptr = ac_build_alloca(&ctx->ac, ctx->ac.i1, "vertexlive");
3086
3087 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
3088 ac_build_ifcc(&ctx->ac, tmp, 5120);
3089 {
3090 for (unsigned i = 0; i < verts_per_prim; ++i) {
3091 const LLVMValueRef primidx =
3092 LLVMBuildAdd(builder, tid,
3093 LLVMConstInt(ctx->ac.i32, i, false), "");
3094
3095 if (i > 0) {
3096 tmp = LLVMBuildICmp(builder, LLVMIntULT, primidx, num_emit_threads, "");
3097 ac_build_ifcc(&ctx->ac, tmp, 5121 + i);
3098 }
3099
3100 /* Load primitive liveness */
3101 tmp = ngg_gs_vertex_ptr(ctx, primidx);
3102 tmp = LLVMBuildLoad(builder,
3103 ngg_gs_get_emit_primflag_ptr(ctx, tmp, 0), "");
3104 const LLVMValueRef primlive =
3105 LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3106
3107 tmp = LLVMBuildLoad(builder, vertliveptr, "");
3108 tmp = LLVMBuildOr(builder, tmp, primlive, ""),
3109 LLVMBuildStore(builder, tmp, vertliveptr);
3110
3111 if (i > 0)
3112 ac_build_endif(&ctx->ac, 5121 + i);
3113 }
3114 }
3115 ac_build_endif(&ctx->ac, 5120);
3116
3117 /* Inclusive scan addition across the current wave. */
3118 LLVMValueRef vertlive = LLVMBuildLoad(builder, vertliveptr, "");
3119 struct ac_wg_scan vertlive_scan = {};
3120 vertlive_scan.op = nir_op_iadd;
3121 vertlive_scan.enable_reduce = true;
3122 vertlive_scan.enable_exclusive = true;
3123 vertlive_scan.src = vertlive;
3124 vertlive_scan.scratch = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, ctx->ac.i32_0);
3125 vertlive_scan.waveidx = get_wave_id_in_tg(ctx);
3126 vertlive_scan.numwaves = get_tgsize(ctx);
3127 vertlive_scan.maxwaves = 8;
3128
3129 ac_build_wg_scan(&ctx->ac, &vertlive_scan);
3130
3131 /* Skip all exports (including index exports) when possible. At least on
3132 * early gfx10 revisions this is also to avoid hangs.
3133 */
3134 LLVMValueRef have_exports =
3135 LLVMBuildICmp(builder, LLVMIntNE, vertlive_scan.result_reduce, ctx->ac.i32_0, "");
3136 num_emit_threads =
3137 LLVMBuildSelect(builder, have_exports, num_emit_threads, ctx->ac.i32_0, "");
3138
3139 /* Allocate export space. Send this message as early as possible, to
3140 * hide the latency of the SQ <-> SPI roundtrip.
3141 *
3142 * Note: We could consider compacting primitives for export as well.
3143 * PA processes 1 non-null prim / clock, but it fetches 4 DW of
3144 * prim data per clock and skips null primitives at no additional
3145 * cost. So compacting primitives can only be beneficial when
3146 * there are 4 or more contiguous null primitives in the export
3147 * (in the common case of single-dword prim exports).
3148 */
3149 ac_build_sendmsg_gs_alloc_req(&ctx->ac, get_wave_id_in_tg(ctx),
3150 vertlive_scan.result_reduce, num_emit_threads);
3151
3152 /* Setup the reverse vertex compaction permutation. We re-use stream 1
3153 * of the primitive liveness flags, relying on the fact that each
3154 * threadgroup can have at most 256 threads. */
3155 ac_build_ifcc(&ctx->ac, vertlive, 5130);
3156 {
3157 tmp = ngg_gs_vertex_ptr(ctx, vertlive_scan.result_exclusive);
3158 tmp2 = LLVMBuildTrunc(builder, tid, ctx->ac.i8, "");
3159 LLVMBuildStore(builder, tmp2,
3160 ngg_gs_get_emit_primflag_ptr(ctx, tmp, 1));
3161 }
3162 ac_build_endif(&ctx->ac, 5130);
3163
3164 ac_build_s_barrier(&ctx->ac);
3165
3166 /* Export primitive data */
3167 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
3168 ac_build_ifcc(&ctx->ac, tmp, 5140);
3169 {
3170 LLVMValueRef flags;
3171 struct ac_ngg_prim prim = {};
3172 prim.num_vertices = verts_per_prim;
3173
3174 tmp = ngg_gs_vertex_ptr(ctx, tid);
3175 flags = LLVMBuildLoad(builder,
3176 ngg_gs_get_emit_primflag_ptr(ctx, tmp, 0), "");
3177 prim.isnull = LLVMBuildNot(builder, LLVMBuildTrunc(builder, flags, ctx->ac.i1, ""), "");
3178
3179 for (unsigned i = 0; i < verts_per_prim; ++i) {
3180 prim.index[i] = LLVMBuildSub(builder, vertlive_scan.result_exclusive,
3181 LLVMConstInt(ctx->ac.i32, verts_per_prim - i - 1, false), "");
3182 prim.edgeflag[i] = ctx->ac.i1false;
3183 }
3184
3185 /* Geometry shaders output triangle strips, but NGG expects
3186 * triangles. We need to change the vertex order for odd
3187 * triangles to get correct front/back facing by swapping 2
3188 * vertex indices, but we also have to keep the provoking
3189 * vertex in the same place.
3190 */
3191 if (verts_per_prim == 3) {
3192 LLVMValueRef is_odd = LLVMBuildLShr(builder, flags, ctx->ac.i8_1, "");
3193 is_odd = LLVMBuildTrunc(builder, is_odd, ctx->ac.i1, "");
3194
3195 struct ac_ngg_prim in = prim;
3196 prim.index[0] = in.index[0];
3197 prim.index[1] = LLVMBuildSelect(builder, is_odd,
3198 in.index[2], in.index[1], "");
3199 prim.index[2] = LLVMBuildSelect(builder, is_odd,
3200 in.index[1], in.index[2], "");
3201 }
3202
3203 ac_build_export_prim(&ctx->ac, &prim);
3204 }
3205 ac_build_endif(&ctx->ac, 5140);
3206
3207 /* Export position and parameter data */
3208 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, vertlive_scan.result_reduce, "");
3209 ac_build_ifcc(&ctx->ac, tmp, 5145);
3210 {
3211 struct radv_vs_output_info *outinfo = &ctx->args->shader_info->vs.outinfo;
3212 bool export_view_index = ctx->args->options->key.has_multiview_view_index;
3213 struct radv_shader_output_values *outputs;
3214 unsigned noutput = 0;
3215
3216 /* Allocate a temporary array for the output values. */
3217 unsigned num_outputs = util_bitcount64(ctx->output_mask) + export_view_index;
3218 outputs = calloc(num_outputs, sizeof(outputs[0]));
3219
3220 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
3221 sizeof(outinfo->vs_output_param_offset));
3222 outinfo->pos_exports = 0;
3223
3224 tmp = ngg_gs_vertex_ptr(ctx, tid);
3225 tmp = LLVMBuildLoad(builder,
3226 ngg_gs_get_emit_primflag_ptr(ctx, tmp, 1), "");
3227 tmp = LLVMBuildZExt(builder, tmp, ctx->ac.i32, "");
3228 const LLVMValueRef vertexptr = ngg_gs_vertex_ptr(ctx, tmp);
3229
3230 unsigned out_idx = 0;
3231 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3232 unsigned output_usage_mask =
3233 ctx->args->shader_info->gs.output_usage_mask[i];
3234 int length = util_last_bit(output_usage_mask);
3235
3236 if (!(ctx->output_mask & (1ull << i)))
3237 continue;
3238
3239 outputs[noutput].slot_name = i;
3240 outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
3241 outputs[noutput].usage_mask = output_usage_mask;
3242
3243 for (unsigned j = 0; j < length; j++, out_idx++) {
3244 if (!(output_usage_mask & (1 << j)))
3245 continue;
3246
3247 tmp = ngg_gs_get_emit_output_ptr(ctx, vertexptr, out_idx);
3248 tmp = LLVMBuildLoad(builder, tmp, "");
3249
3250 LLVMTypeRef type = LLVMGetAllocatedType(ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
3251 if (ac_get_type_size(type) == 2) {
3252 tmp = ac_to_integer(&ctx->ac, tmp);
3253 tmp = LLVMBuildTrunc(ctx->ac.builder, tmp, ctx->ac.i16, "");
3254 }
3255
3256 outputs[noutput].values[j] = ac_to_float(&ctx->ac, tmp);
3257 }
3258
3259 for (unsigned j = length; j < 4; j++)
3260 outputs[noutput].values[j] = LLVMGetUndef(ctx->ac.f32);
3261
3262 noutput++;
3263 }
3264
3265 /* Export ViewIndex. */
3266 if (export_view_index) {
3267 outputs[noutput].slot_name = VARYING_SLOT_LAYER;
3268 outputs[noutput].slot_index = 0;
3269 outputs[noutput].usage_mask = 0x1;
3270 outputs[noutput].values[0] =
3271 ac_to_float(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->ac.view_index));
3272 for (unsigned j = 1; j < 4; j++)
3273 outputs[noutput].values[j] = ctx->ac.f32_0;
3274 noutput++;
3275 }
3276
3277 radv_llvm_export_vs(ctx, outputs, noutput, outinfo,
3278 ctx->args->options->key.vs_common_out.export_clip_dists);
3279 FREE(outputs);
3280 }
3281 ac_build_endif(&ctx->ac, 5145);
3282 }
3283
3284 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context *ctx,
3285 unsigned stream,
3286 LLVMValueRef vertexidx,
3287 LLVMValueRef *addrs)
3288 {
3289 LLVMBuilderRef builder = ctx->ac.builder;
3290 LLVMValueRef tmp;
3291
3292 const LLVMValueRef vertexptr =
3293 ngg_gs_emit_vertex_ptr(ctx, get_thread_id_in_tg(ctx), vertexidx);
3294 unsigned out_idx = 0;
3295 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3296 unsigned output_usage_mask =
3297 ctx->args->shader_info->gs.output_usage_mask[i];
3298 uint8_t output_stream =
3299 ctx->args->shader_info->gs.output_streams[i];
3300 LLVMValueRef *out_ptr = &addrs[i * 4];
3301 int length = util_last_bit(output_usage_mask);
3302
3303 if (!(ctx->output_mask & (1ull << i)) ||
3304 output_stream != stream)
3305 continue;
3306
3307 for (unsigned j = 0; j < length; j++, out_idx++) {
3308 if (!(output_usage_mask & (1 << j)))
3309 continue;
3310
3311 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
3312 out_ptr[j], "");
3313 out_val = ac_to_integer(&ctx->ac, out_val);
3314 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
3315
3316 LLVMBuildStore(builder, out_val,
3317 ngg_gs_get_emit_output_ptr(ctx, vertexptr, out_idx));
3318 }
3319 }
3320 assert(out_idx * 4 <= ctx->args->shader_info->gs.gsvs_vertex_size);
3321
3322 /* Store the current number of emitted vertices to zero out remaining
3323 * primitive flags in case the geometry shader doesn't emit the maximum
3324 * number of vertices.
3325 */
3326 tmp = LLVMBuildAdd(builder, vertexidx, ctx->ac.i32_1, "");
3327 LLVMBuildStore(builder, tmp, ctx->gs_next_vertex[stream]);
3328
3329 /* Determine and store whether this vertex completed a primitive. */
3330 const LLVMValueRef curverts = LLVMBuildLoad(builder, ctx->gs_curprim_verts[stream], "");
3331
3332 tmp = LLVMConstInt(ctx->ac.i32, si_conv_gl_prim_to_vertices(ctx->shader->info.gs.output_primitive) - 1, false);
3333 const LLVMValueRef iscompleteprim =
3334 LLVMBuildICmp(builder, LLVMIntUGE, curverts, tmp, "");
3335
3336 /* Since the geometry shader emits triangle strips, we need to
3337 * track which primitive is odd and swap vertex indices to get
3338 * the correct vertex order.
3339 */
3340 LLVMValueRef is_odd = ctx->ac.i1false;
3341 if (stream == 0 &&
3342 si_conv_gl_prim_to_vertices(ctx->shader->info.gs.output_primitive) == 3) {
3343 tmp = LLVMBuildAnd(builder, curverts, ctx->ac.i32_1, "");
3344 is_odd = LLVMBuildICmp(builder, LLVMIntEQ, tmp, ctx->ac.i32_1, "");
3345 }
3346
3347 tmp = LLVMBuildAdd(builder, curverts, ctx->ac.i32_1, "");
3348 LLVMBuildStore(builder, tmp, ctx->gs_curprim_verts[stream]);
3349
3350 /* The per-vertex primitive flag encoding:
3351 * bit 0: whether this vertex finishes a primitive
3352 * bit 1: whether the primitive is odd (if we are emitting triangle strips)
3353 */
3354 tmp = LLVMBuildZExt(builder, iscompleteprim, ctx->ac.i8, "");
3355 tmp = LLVMBuildOr(builder, tmp,
3356 LLVMBuildShl(builder,
3357 LLVMBuildZExt(builder, is_odd, ctx->ac.i8, ""),
3358 ctx->ac.i8_1, ""), "");
3359 LLVMBuildStore(builder, tmp,
3360 ngg_gs_get_emit_primflag_ptr(ctx, vertexptr, stream));
3361
3362 tmp = LLVMBuildLoad(builder, ctx->gs_generated_prims[stream], "");
3363 tmp = LLVMBuildAdd(builder, tmp, LLVMBuildZExt(builder, iscompleteprim, ctx->ac.i32, ""), "");
3364 LLVMBuildStore(builder, tmp, ctx->gs_generated_prims[stream]);
3365 }
3366
3367 static void
3368 write_tess_factors(struct radv_shader_context *ctx)
3369 {
3370 unsigned stride, outer_comps, inner_comps;
3371 LLVMValueRef tcs_rel_ids = ac_get_arg(&ctx->ac, ctx->args->ac.tcs_rel_ids);
3372 LLVMValueRef invocation_id = ac_unpack_param(&ctx->ac, tcs_rel_ids, 8, 5);
3373 LLVMValueRef rel_patch_id = ac_unpack_param(&ctx->ac, tcs_rel_ids, 0, 8);
3374 unsigned tess_inner_index = 0, tess_outer_index;
3375 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
3376 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
3377 int i;
3378 ac_emit_barrier(&ctx->ac, ctx->stage);
3379
3380 switch (ctx->args->options->key.tcs.primitive_mode) {
3381 case GL_ISOLINES:
3382 stride = 2;
3383 outer_comps = 2;
3384 inner_comps = 0;
3385 break;
3386 case GL_TRIANGLES:
3387 stride = 4;
3388 outer_comps = 3;
3389 inner_comps = 1;
3390 break;
3391 case GL_QUADS:
3392 stride = 6;
3393 outer_comps = 4;
3394 inner_comps = 2;
3395 break;
3396 default:
3397 return;
3398 }
3399
3400 ac_build_ifcc(&ctx->ac,
3401 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3402 invocation_id, ctx->ac.i32_0, ""), 6503);
3403
3404 lds_base = get_tcs_out_current_patch_data_offset(ctx);
3405
3406 if (inner_comps) {
3407 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
3408 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
3409 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
3410 }
3411
3412 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
3413 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
3414 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
3415
3416 for (i = 0; i < 4; i++) {
3417 inner[i] = LLVMGetUndef(ctx->ac.i32);
3418 outer[i] = LLVMGetUndef(ctx->ac.i32);
3419 }
3420
3421 // LINES reversal
3422 if (ctx->args->options->key.tcs.primitive_mode == GL_ISOLINES) {
3423 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
3424 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
3425 ctx->ac.i32_1, "");
3426 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
3427 } else {
3428 for (i = 0; i < outer_comps; i++) {
3429 outer[i] = out[i] =
3430 ac_lds_load(&ctx->ac, lds_outer);
3431 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
3432 ctx->ac.i32_1, "");
3433 }
3434 for (i = 0; i < inner_comps; i++) {
3435 inner[i] = out[outer_comps+i] =
3436 ac_lds_load(&ctx->ac, lds_inner);
3437 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
3438 ctx->ac.i32_1, "");
3439 }
3440 }
3441
3442 /* Convert the outputs to vectors for stores. */
3443 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
3444 vec1 = NULL;
3445
3446 if (stride > 4)
3447 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
3448
3449
3450 buffer = ctx->hs_ring_tess_factor;
3451 tf_base = ac_get_arg(&ctx->ac, ctx->args->tess_factor_offset);
3452 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
3453 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
3454 unsigned tf_offset = 0;
3455
3456 if (ctx->ac.chip_class <= GFX8) {
3457 ac_build_ifcc(&ctx->ac,
3458 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3459 rel_patch_id, ctx->ac.i32_0, ""), 6504);
3460
3461 /* Store the dynamic HS control word. */
3462 ac_build_buffer_store_dword(&ctx->ac, buffer,
3463 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
3464 1, ctx->ac.i32_0, tf_base,
3465 0, ac_glc);
3466 tf_offset += 4;
3467
3468 ac_build_endif(&ctx->ac, 6504);
3469 }
3470
3471 /* Store the tessellation factors. */
3472 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
3473 MIN2(stride, 4), byteoffset, tf_base,
3474 tf_offset, ac_glc);
3475 if (vec1)
3476 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
3477 stride - 4, byteoffset, tf_base,
3478 16 + tf_offset, ac_glc);
3479
3480 //store to offchip for TES to read - only if TES reads them
3481 if (ctx->args->options->key.tcs.tes_reads_tess_factors) {
3482 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
3483 LLVMValueRef tf_inner_offset;
3484 unsigned param_outer, param_inner;
3485
3486 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
3487 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
3488 LLVMConstInt(ctx->ac.i32, param_outer, 0));
3489
3490 outer_vec = ac_build_gather_values(&ctx->ac, outer,
3491 util_next_power_of_two(outer_comps));
3492
3493 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
3494 outer_comps, tf_outer_offset,
3495 ac_get_arg(&ctx->ac, ctx->args->oc_lds),
3496 0, ac_glc);
3497 if (inner_comps) {
3498 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
3499 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
3500 LLVMConstInt(ctx->ac.i32, param_inner, 0));
3501
3502 inner_vec = inner_comps == 1 ? inner[0] :
3503 ac_build_gather_values(&ctx->ac, inner, inner_comps);
3504 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
3505 inner_comps, tf_inner_offset,
3506 ac_get_arg(&ctx->ac, ctx->args->oc_lds),
3507 0, ac_glc);
3508 }
3509 }
3510
3511 ac_build_endif(&ctx->ac, 6503);
3512 }
3513
3514 static void
3515 handle_tcs_outputs_post(struct radv_shader_context *ctx)
3516 {
3517 write_tess_factors(ctx);
3518 }
3519
3520 static bool
3521 si_export_mrt_color(struct radv_shader_context *ctx,
3522 LLVMValueRef *color, unsigned index,
3523 struct ac_export_args *args)
3524 {
3525 /* Export */
3526 si_llvm_init_export_args(ctx, color, 0xf,
3527 V_008DFC_SQ_EXP_MRT + index, args);
3528 if (!args->enabled_channels)
3529 return false; /* unnecessary NULL export */
3530
3531 return true;
3532 }
3533
3534 static void
3535 radv_export_mrt_z(struct radv_shader_context *ctx,
3536 LLVMValueRef depth, LLVMValueRef stencil,
3537 LLVMValueRef samplemask)
3538 {
3539 struct ac_export_args args;
3540
3541 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3542
3543 ac_build_export(&ctx->ac, &args);
3544 }
3545
3546 static void
3547 handle_fs_outputs_post(struct radv_shader_context *ctx)
3548 {
3549 unsigned index = 0;
3550 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3551 struct ac_export_args color_args[8];
3552
3553 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3554 LLVMValueRef values[4];
3555
3556 if (!(ctx->output_mask & (1ull << i)))
3557 continue;
3558
3559 if (i < FRAG_RESULT_DATA0)
3560 continue;
3561
3562 for (unsigned j = 0; j < 4; j++)
3563 values[j] = ac_to_float(&ctx->ac,
3564 radv_load_output(ctx, i, j));
3565
3566 bool ret = si_export_mrt_color(ctx, values,
3567 i - FRAG_RESULT_DATA0,
3568 &color_args[index]);
3569 if (ret)
3570 index++;
3571 }
3572
3573 /* Process depth, stencil, samplemask. */
3574 if (ctx->args->shader_info->ps.writes_z) {
3575 depth = ac_to_float(&ctx->ac,
3576 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
3577 }
3578 if (ctx->args->shader_info->ps.writes_stencil) {
3579 stencil = ac_to_float(&ctx->ac,
3580 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
3581 }
3582 if (ctx->args->shader_info->ps.writes_sample_mask) {
3583 samplemask = ac_to_float(&ctx->ac,
3584 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
3585 }
3586
3587 /* Set the DONE bit on last non-null color export only if Z isn't
3588 * exported.
3589 */
3590 if (index > 0 &&
3591 !ctx->args->shader_info->ps.writes_z &&
3592 !ctx->args->shader_info->ps.writes_stencil &&
3593 !ctx->args->shader_info->ps.writes_sample_mask) {
3594 unsigned last = index - 1;
3595
3596 color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */
3597 color_args[last].done = 1; /* DONE bit */
3598 }
3599
3600 /* Export PS outputs. */
3601 for (unsigned i = 0; i < index; i++)
3602 ac_build_export(&ctx->ac, &color_args[i]);
3603
3604 if (depth || stencil || samplemask)
3605 radv_export_mrt_z(ctx, depth, stencil, samplemask);
3606 else if (!index)
3607 ac_build_export_null(&ctx->ac);
3608 }
3609
3610 static void
3611 emit_gs_epilogue(struct radv_shader_context *ctx)
3612 {
3613 if (ctx->args->options->key.vs_common_out.as_ngg) {
3614 gfx10_ngg_gs_emit_epilogue_1(ctx);
3615 return;
3616 }
3617
3618 if (ctx->ac.chip_class >= GFX10)
3619 LLVMBuildFence(ctx->ac.builder, LLVMAtomicOrderingRelease, false, "");
3620
3621 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
3622 }
3623
3624 static void
3625 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
3626 LLVMValueRef *addrs)
3627 {
3628 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3629
3630 switch (ctx->stage) {
3631 case MESA_SHADER_VERTEX:
3632 if (ctx->args->options->key.vs_common_out.as_ls)
3633 handle_ls_outputs_post(ctx);
3634 else if (ctx->args->options->key.vs_common_out.as_es)
3635 handle_es_outputs_post(ctx, &ctx->args->shader_info->vs.es_info);
3636 else if (ctx->args->options->key.vs_common_out.as_ngg)
3637 handle_ngg_outputs_post_1(ctx);
3638 else
3639 handle_vs_outputs_post(ctx, ctx->args->options->key.vs_common_out.export_prim_id,
3640 ctx->args->options->key.vs_common_out.export_clip_dists,
3641 &ctx->args->shader_info->vs.outinfo);
3642 break;
3643 case MESA_SHADER_FRAGMENT:
3644 handle_fs_outputs_post(ctx);
3645 break;
3646 case MESA_SHADER_GEOMETRY:
3647 emit_gs_epilogue(ctx);
3648 break;
3649 case MESA_SHADER_TESS_CTRL:
3650 handle_tcs_outputs_post(ctx);
3651 break;
3652 case MESA_SHADER_TESS_EVAL:
3653 if (ctx->args->options->key.vs_common_out.as_es)
3654 handle_es_outputs_post(ctx, &ctx->args->shader_info->tes.es_info);
3655 else if (ctx->args->options->key.vs_common_out.as_ngg)
3656 handle_ngg_outputs_post_1(ctx);
3657 else
3658 handle_vs_outputs_post(ctx, ctx->args->options->key.vs_common_out.export_prim_id,
3659 ctx->args->options->key.vs_common_out.export_clip_dists,
3660 &ctx->args->shader_info->tes.outinfo);
3661 break;
3662 default:
3663 break;
3664 }
3665 }
3666
3667 static void ac_llvm_finalize_module(struct radv_shader_context *ctx,
3668 LLVMPassManagerRef passmgr,
3669 const struct radv_nir_compiler_options *options)
3670 {
3671 LLVMRunPassManager(passmgr, ctx->ac.module);
3672 LLVMDisposeBuilder(ctx->ac.builder);
3673
3674 ac_llvm_context_dispose(&ctx->ac);
3675 }
3676
3677 static void
3678 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
3679 {
3680 struct radv_vs_output_info *outinfo;
3681
3682 switch (ctx->stage) {
3683 case MESA_SHADER_FRAGMENT:
3684 case MESA_SHADER_COMPUTE:
3685 case MESA_SHADER_TESS_CTRL:
3686 case MESA_SHADER_GEOMETRY:
3687 return;
3688 case MESA_SHADER_VERTEX:
3689 if (ctx->args->options->key.vs_common_out.as_ls ||
3690 ctx->args->options->key.vs_common_out.as_es)
3691 return;
3692 outinfo = &ctx->args->shader_info->vs.outinfo;
3693 break;
3694 case MESA_SHADER_TESS_EVAL:
3695 if (ctx->args->options->key.vs_common_out.as_es)
3696 return;
3697 outinfo = &ctx->args->shader_info->tes.outinfo;
3698 break;
3699 default:
3700 unreachable("Unhandled shader type");
3701 }
3702
3703 ac_optimize_vs_outputs(&ctx->ac,
3704 ctx->main_function,
3705 outinfo->vs_output_param_offset,
3706 VARYING_SLOT_MAX, 0,
3707 &outinfo->param_exports);
3708 }
3709
3710 static void
3711 ac_setup_rings(struct radv_shader_context *ctx)
3712 {
3713 if (ctx->args->options->chip_class <= GFX8 &&
3714 (ctx->stage == MESA_SHADER_GEOMETRY ||
3715 ctx->args->options->key.vs_common_out.as_es || ctx->args->options->key.vs_common_out.as_es)) {
3716 unsigned ring = ctx->stage == MESA_SHADER_GEOMETRY ? RING_ESGS_GS
3717 : RING_ESGS_VS;
3718 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, ring, false);
3719
3720 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac,
3721 ctx->ring_offsets,
3722 offset);
3723 }
3724
3725 if (ctx->args->is_gs_copy_shader) {
3726 ctx->gsvs_ring[0] =
3727 ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets,
3728 LLVMConstInt(ctx->ac.i32,
3729 RING_GSVS_VS, false));
3730 }
3731
3732 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3733 /* The conceptual layout of the GSVS ring is
3734 * v0c0 .. vLv0 v0c1 .. vLc1 ..
3735 * but the real memory layout is swizzled across
3736 * threads:
3737 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
3738 * t16v0c0 ..
3739 * Override the buffer descriptor accordingly.
3740 */
3741 LLVMTypeRef v2i64 = LLVMVectorType(ctx->ac.i64, 2);
3742 uint64_t stream_offset = 0;
3743 unsigned num_records = ctx->ac.wave_size;
3744 LLVMValueRef base_ring;
3745
3746 base_ring =
3747 ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets,
3748 LLVMConstInt(ctx->ac.i32,
3749 RING_GSVS_GS, false));
3750
3751 for (unsigned stream = 0; stream < 4; stream++) {
3752 unsigned num_components, stride;
3753 LLVMValueRef ring, tmp;
3754
3755 num_components =
3756 ctx->args->shader_info->gs.num_stream_output_components[stream];
3757
3758 if (!num_components)
3759 continue;
3760
3761 stride = 4 * num_components * ctx->shader->info.gs.vertices_out;
3762
3763 /* Limit on the stride field for <= GFX7. */
3764 assert(stride < (1 << 14));
3765
3766 ring = LLVMBuildBitCast(ctx->ac.builder,
3767 base_ring, v2i64, "");
3768 tmp = LLVMBuildExtractElement(ctx->ac.builder,
3769 ring, ctx->ac.i32_0, "");
3770 tmp = LLVMBuildAdd(ctx->ac.builder, tmp,
3771 LLVMConstInt(ctx->ac.i64,
3772 stream_offset, 0), "");
3773 ring = LLVMBuildInsertElement(ctx->ac.builder,
3774 ring, tmp, ctx->ac.i32_0, "");
3775
3776 stream_offset += stride * ctx->ac.wave_size;
3777
3778 ring = LLVMBuildBitCast(ctx->ac.builder, ring,
3779 ctx->ac.v4i32, "");
3780
3781 tmp = LLVMBuildExtractElement(ctx->ac.builder, ring,
3782 ctx->ac.i32_1, "");
3783 tmp = LLVMBuildOr(ctx->ac.builder, tmp,
3784 LLVMConstInt(ctx->ac.i32,
3785 S_008F04_STRIDE(stride), false), "");
3786 ring = LLVMBuildInsertElement(ctx->ac.builder, ring, tmp,
3787 ctx->ac.i32_1, "");
3788
3789 ring = LLVMBuildInsertElement(ctx->ac.builder, ring,
3790 LLVMConstInt(ctx->ac.i32,
3791 num_records, false),
3792 LLVMConstInt(ctx->ac.i32, 2, false), "");
3793
3794 ctx->gsvs_ring[stream] = ring;
3795 }
3796 }
3797
3798 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3799 ctx->stage == MESA_SHADER_TESS_EVAL) {
3800 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
3801 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
3802 }
3803 }
3804
3805 unsigned
3806 radv_nir_get_max_workgroup_size(enum chip_class chip_class,
3807 gl_shader_stage stage,
3808 const struct nir_shader *nir)
3809 {
3810 const unsigned backup_sizes[] = {chip_class >= GFX9 ? 128 : 64, 1, 1};
3811 unsigned sizes[3];
3812 for (unsigned i = 0; i < 3; i++)
3813 sizes[i] = nir ? nir->info.cs.local_size[i] : backup_sizes[i];
3814 return radv_get_max_workgroup_size(chip_class, stage, sizes);
3815 }
3816
3817 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
3818 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
3819 {
3820 LLVMValueRef count =
3821 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 8, 8);
3822 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
3823 ctx->ac.i32_0, "");
3824 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty,
3825 ac_get_arg(&ctx->ac, ctx->args->rel_auto_id),
3826 ctx->abi.instance_id, "");
3827 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty,
3828 ac_get_arg(&ctx->ac, ctx->args->ac.tcs_rel_ids),
3829 ctx->rel_auto_id,
3830 "");
3831 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty,
3832 ac_get_arg(&ctx->ac, ctx->args->ac.tcs_patch_id),
3833 ctx->abi.vertex_id, "");
3834 }
3835
3836 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx, bool merged)
3837 {
3838 if (merged) {
3839 for(int i = 5; i >= 0; --i) {
3840 ctx->gs_vtx_offset[i] =
3841 ac_unpack_param(&ctx->ac,
3842 ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[i & ~1]),
3843 (i & 1) * 16, 16);
3844 }
3845
3846 ctx->gs_wave_id = ac_unpack_param(&ctx->ac,
3847 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info),
3848 16, 8);
3849 } else {
3850 for (int i = 0; i < 6; i++)
3851 ctx->gs_vtx_offset[i] = ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[i]);
3852 ctx->gs_wave_id = ac_get_arg(&ctx->ac, ctx->args->gs_wave_id);
3853 }
3854 }
3855
3856 /* Ensure that the esgs ring is declared.
3857 *
3858 * We declare it with 64KB alignment as a hint that the
3859 * pointer value will always be 0.
3860 */
3861 static void declare_esgs_ring(struct radv_shader_context *ctx)
3862 {
3863 if (ctx->esgs_ring)
3864 return;
3865
3866 assert(!LLVMGetNamedGlobal(ctx->ac.module, "esgs_ring"));
3867
3868 ctx->esgs_ring = LLVMAddGlobalInAddressSpace(
3869 ctx->ac.module, LLVMArrayType(ctx->ac.i32, 0),
3870 "esgs_ring",
3871 AC_ADDR_SPACE_LDS);
3872 LLVMSetLinkage(ctx->esgs_ring, LLVMExternalLinkage);
3873 LLVMSetAlignment(ctx->esgs_ring, 64 * 1024);
3874 }
3875
3876 static
3877 LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
3878 struct nir_shader *const *shaders,
3879 int shader_count,
3880 const struct radv_shader_args *args)
3881 {
3882 struct radv_shader_context ctx = {0};
3883 ctx.args = args;
3884
3885 enum ac_float_mode float_mode = AC_FLOAT_MODE_DEFAULT;
3886
3887 if (args->shader_info->float_controls_mode & FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32) {
3888 float_mode = AC_FLOAT_MODE_DENORM_FLUSH_TO_ZERO;
3889 }
3890
3891 ac_llvm_context_init(&ctx.ac, ac_llvm, args->options->chip_class,
3892 args->options->family, float_mode,
3893 args->shader_info->wave_size,
3894 args->shader_info->ballot_bit_size);
3895 ctx.context = ctx.ac.context;
3896
3897 ctx.max_workgroup_size = 0;
3898 for (int i = 0; i < shader_count; ++i) {
3899 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
3900 radv_nir_get_max_workgroup_size(args->options->chip_class,
3901 shaders[i]->info.stage,
3902 shaders[i]));
3903 }
3904
3905 if (ctx.ac.chip_class >= GFX10) {
3906 if (is_pre_gs_stage(shaders[0]->info.stage) &&
3907 args->options->key.vs_common_out.as_ngg) {
3908 ctx.max_workgroup_size = 128;
3909 }
3910 }
3911
3912 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2);
3913
3914 ctx.abi.inputs = &ctx.inputs[0];
3915 ctx.abi.emit_outputs = handle_shader_outputs_post;
3916 ctx.abi.emit_vertex_with_counter = visit_emit_vertex_with_counter;
3917 ctx.abi.load_ubo = radv_load_ubo;
3918 ctx.abi.load_ssbo = radv_load_ssbo;
3919 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
3920 ctx.abi.load_resource = radv_load_resource;
3921 ctx.abi.clamp_shadow_reference = false;
3922 ctx.abi.robust_buffer_access = args->options->robust_buffer_access;
3923
3924 bool is_ngg = is_pre_gs_stage(shaders[0]->info.stage) && args->options->key.vs_common_out.as_ngg;
3925 if (shader_count >= 2 || is_ngg)
3926 ac_init_exec_full_mask(&ctx.ac);
3927
3928 if (args->ac.vertex_id.used)
3929 ctx.abi.vertex_id = ac_get_arg(&ctx.ac, args->ac.vertex_id);
3930 if (args->rel_auto_id.used)
3931 ctx.rel_auto_id = ac_get_arg(&ctx.ac, args->rel_auto_id);
3932 if (args->ac.instance_id.used)
3933 ctx.abi.instance_id = ac_get_arg(&ctx.ac, args->ac.instance_id);
3934
3935 if (args->options->has_ls_vgpr_init_bug &&
3936 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
3937 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
3938
3939 if (is_ngg) {
3940 /* Declare scratch space base for streamout and vertex
3941 * compaction. Whether space is actually allocated is
3942 * determined during linking / PM4 creation.
3943 *
3944 * Add an extra dword per vertex to ensure an odd stride, which
3945 * avoids bank conflicts for SoA accesses.
3946 */
3947 if (!args->options->key.vs_common_out.as_ngg_passthrough)
3948 declare_esgs_ring(&ctx);
3949
3950 /* This is really only needed when streamout and / or vertex
3951 * compaction is enabled.
3952 */
3953 if (args->shader_info->so.num_outputs) {
3954 LLVMTypeRef asi32 = LLVMArrayType(ctx.ac.i32, 8);
3955 ctx.gs_ngg_scratch = LLVMAddGlobalInAddressSpace(ctx.ac.module,
3956 asi32, "ngg_scratch", AC_ADDR_SPACE_LDS);
3957 LLVMSetInitializer(ctx.gs_ngg_scratch, LLVMGetUndef(asi32));
3958 LLVMSetAlignment(ctx.gs_ngg_scratch, 4);
3959 }
3960 }
3961
3962 for(int i = 0; i < shader_count; ++i) {
3963 ctx.stage = shaders[i]->info.stage;
3964 ctx.shader = shaders[i];
3965 ctx.output_mask = 0;
3966
3967 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3968 for (int i = 0; i < 4; i++) {
3969 ctx.gs_next_vertex[i] =
3970 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
3971 }
3972 if (args->options->key.vs_common_out.as_ngg) {
3973 for (unsigned i = 0; i < 4; ++i) {
3974 ctx.gs_curprim_verts[i] =
3975 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
3976 ctx.gs_generated_prims[i] =
3977 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
3978 }
3979
3980 unsigned scratch_size = 8;
3981 if (args->shader_info->so.num_outputs)
3982 scratch_size = 44;
3983
3984 LLVMTypeRef ai32 = LLVMArrayType(ctx.ac.i32, scratch_size);
3985 ctx.gs_ngg_scratch =
3986 LLVMAddGlobalInAddressSpace(ctx.ac.module,
3987 ai32, "ngg_scratch", AC_ADDR_SPACE_LDS);
3988 LLVMSetInitializer(ctx.gs_ngg_scratch, LLVMGetUndef(ai32));
3989 LLVMSetAlignment(ctx.gs_ngg_scratch, 4);
3990
3991 ctx.gs_ngg_emit = LLVMAddGlobalInAddressSpace(ctx.ac.module,
3992 LLVMArrayType(ctx.ac.i32, 0), "ngg_emit", AC_ADDR_SPACE_LDS);
3993 LLVMSetLinkage(ctx.gs_ngg_emit, LLVMExternalLinkage);
3994 LLVMSetAlignment(ctx.gs_ngg_emit, 4);
3995 }
3996
3997 ctx.abi.load_inputs = load_gs_input;
3998 ctx.abi.emit_primitive = visit_end_primitive;
3999 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
4000 ctx.abi.load_tess_varyings = load_tcs_varyings;
4001 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
4002 ctx.abi.store_tcs_outputs = store_tcs_output;
4003 if (shader_count == 1)
4004 ctx.tcs_num_inputs = args->options->key.tcs.num_inputs;
4005 else
4006 ctx.tcs_num_inputs = util_last_bit64(args->shader_info->vs.ls_outputs_written);
4007 unsigned tcs_num_outputs = util_last_bit64(ctx.args->shader_info->tcs.outputs_written);
4008 unsigned tcs_num_patch_outputs = util_last_bit64(ctx.args->shader_info->tcs.patch_outputs_written);
4009 ctx.tcs_num_patches =
4010 get_tcs_num_patches(
4011 ctx.args->options->key.tcs.input_vertices,
4012 ctx.shader->info.tess.tcs_vertices_out,
4013 ctx.tcs_num_inputs,
4014 tcs_num_outputs,
4015 tcs_num_patch_outputs,
4016 ctx.args->options->tess_offchip_block_dw_size,
4017 ctx.args->options->chip_class,
4018 ctx.args->options->family);
4019 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
4020 ctx.abi.load_tess_varyings = load_tes_input;
4021 ctx.abi.load_tess_coord = load_tess_coord;
4022 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
4023 ctx.tcs_num_patches = args->options->key.tes.num_patches;
4024 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
4025 ctx.abi.load_base_vertex = radv_load_base_vertex;
4026 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
4027 ctx.abi.load_sample_position = load_sample_position;
4028 ctx.abi.load_sample_mask_in = load_sample_mask_in;
4029 }
4030
4031 if (shaders[i]->info.stage == MESA_SHADER_VERTEX &&
4032 args->options->key.vs_common_out.as_ngg &&
4033 args->options->key.vs_common_out.export_prim_id) {
4034 declare_esgs_ring(&ctx);
4035 }
4036
4037 bool nested_barrier = false;
4038
4039 if (i) {
4040 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
4041 args->options->key.vs_common_out.as_ngg) {
4042 gfx10_ngg_gs_emit_prologue(&ctx);
4043 nested_barrier = false;
4044 } else {
4045 nested_barrier = true;
4046 }
4047 }
4048
4049 if (nested_barrier) {
4050 /* Execute a barrier before the second shader in
4051 * a merged shader.
4052 *
4053 * Execute the barrier inside the conditional block,
4054 * so that empty waves can jump directly to s_endpgm,
4055 * which will also signal the barrier.
4056 *
4057 * This is possible in gfx9, because an empty wave
4058 * for the second shader does not participate in
4059 * the epilogue. With NGG, empty waves may still
4060 * be required to export data (e.g. GS output vertices),
4061 * so we cannot let them exit early.
4062 *
4063 * If the shader is TCS and the TCS epilog is present
4064 * and contains a barrier, it will wait there and then
4065 * reach s_endpgm.
4066 */
4067 ac_emit_barrier(&ctx.ac, ctx.stage);
4068 }
4069
4070 nir_foreach_variable(variable, &shaders[i]->outputs)
4071 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
4072
4073 ac_setup_rings(&ctx);
4074
4075 LLVMBasicBlockRef merge_block = NULL;
4076 if (shader_count >= 2 || is_ngg) {
4077 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
4078 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
4079 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
4080
4081 LLVMValueRef count =
4082 ac_unpack_param(&ctx.ac,
4083 ac_get_arg(&ctx.ac, args->merged_wave_info),
4084 8 * i, 8);
4085 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
4086 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
4087 thread_id, count, "");
4088 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
4089
4090 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
4091 }
4092
4093 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
4094 prepare_interp_optimize(&ctx, shaders[i]);
4095 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
4096 handle_vs_inputs(&ctx, shaders[i]);
4097 else if(shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
4098 prepare_gs_input_vgprs(&ctx, shader_count >= 2);
4099
4100 ac_nir_translate(&ctx.ac, &ctx.abi, &args->ac, shaders[i]);
4101
4102 if (shader_count >= 2 || is_ngg) {
4103 LLVMBuildBr(ctx.ac.builder, merge_block);
4104 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
4105 }
4106
4107 /* This needs to be outside the if wrapping the shader body, as sometimes
4108 * the HW generates waves with 0 es/vs threads. */
4109 if (is_pre_gs_stage(shaders[i]->info.stage) &&
4110 args->options->key.vs_common_out.as_ngg &&
4111 i == shader_count - 1) {
4112 handle_ngg_outputs_post_2(&ctx);
4113 } else if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
4114 args->options->key.vs_common_out.as_ngg) {
4115 gfx10_ngg_gs_emit_epilogue_2(&ctx);
4116 }
4117
4118 if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
4119 unsigned tcs_num_outputs = util_last_bit64(ctx.args->shader_info->tcs.outputs_written);
4120 unsigned tcs_num_patch_outputs = util_last_bit64(ctx.args->shader_info->tcs.patch_outputs_written);
4121 args->shader_info->tcs.num_patches = ctx.tcs_num_patches;
4122 args->shader_info->tcs.lds_size =
4123 calculate_tess_lds_size(
4124 ctx.args->options->key.tcs.input_vertices,
4125 ctx.shader->info.tess.tcs_vertices_out,
4126 ctx.tcs_num_inputs,
4127 ctx.tcs_num_patches,
4128 tcs_num_outputs,
4129 tcs_num_patch_outputs);
4130 }
4131 }
4132
4133 LLVMBuildRetVoid(ctx.ac.builder);
4134
4135 if (args->options->dump_preoptir) {
4136 fprintf(stderr, "%s LLVM IR:\n\n",
4137 radv_get_shader_name(args->shader_info,
4138 shaders[shader_count - 1]->info.stage));
4139 ac_dump_module(ctx.ac.module);
4140 fprintf(stderr, "\n");
4141 }
4142
4143 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, args->options);
4144
4145 if (shader_count == 1)
4146 ac_nir_eliminate_const_vs_outputs(&ctx);
4147
4148 if (args->options->dump_shader) {
4149 args->shader_info->private_mem_vgprs =
4150 ac_count_scratch_private_memory(ctx.main_function);
4151 }
4152
4153 return ctx.ac.module;
4154 }
4155
4156 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
4157 {
4158 unsigned *retval = (unsigned *)context;
4159 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
4160 char *description = LLVMGetDiagInfoDescription(di);
4161
4162 if (severity == LLVMDSError) {
4163 *retval = 1;
4164 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
4165 description);
4166 }
4167
4168 LLVMDisposeMessage(description);
4169 }
4170
4171 static unsigned radv_llvm_compile(LLVMModuleRef M,
4172 char **pelf_buffer, size_t *pelf_size,
4173 struct ac_llvm_compiler *ac_llvm)
4174 {
4175 unsigned retval = 0;
4176 LLVMContextRef llvm_ctx;
4177
4178 /* Setup Diagnostic Handler*/
4179 llvm_ctx = LLVMGetModuleContext(M);
4180
4181 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
4182 &retval);
4183
4184 /* Compile IR*/
4185 if (!radv_compile_to_elf(ac_llvm, M, pelf_buffer, pelf_size))
4186 retval = 1;
4187 return retval;
4188 }
4189
4190 static void ac_compile_llvm_module(struct ac_llvm_compiler *ac_llvm,
4191 LLVMModuleRef llvm_module,
4192 struct radv_shader_binary **rbinary,
4193 gl_shader_stage stage,
4194 const char *name,
4195 const struct radv_nir_compiler_options *options)
4196 {
4197 char *elf_buffer = NULL;
4198 size_t elf_size = 0;
4199 char *llvm_ir_string = NULL;
4200
4201 if (options->dump_shader) {
4202 fprintf(stderr, "%s LLVM IR:\n\n", name);
4203 ac_dump_module(llvm_module);
4204 fprintf(stderr, "\n");
4205 }
4206
4207 if (options->record_ir) {
4208 char *llvm_ir = LLVMPrintModuleToString(llvm_module);
4209 llvm_ir_string = strdup(llvm_ir);
4210 LLVMDisposeMessage(llvm_ir);
4211 }
4212
4213 int v = radv_llvm_compile(llvm_module, &elf_buffer, &elf_size, ac_llvm);
4214 if (v) {
4215 fprintf(stderr, "compile failed\n");
4216 }
4217
4218 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
4219 LLVMDisposeModule(llvm_module);
4220 LLVMContextDispose(ctx);
4221
4222 size_t llvm_ir_size = llvm_ir_string ? strlen(llvm_ir_string) : 0;
4223 size_t alloc_size = sizeof(struct radv_shader_binary_rtld) + elf_size + llvm_ir_size + 1;
4224 struct radv_shader_binary_rtld *rbin = calloc(1, alloc_size);
4225 memcpy(rbin->data, elf_buffer, elf_size);
4226 if (llvm_ir_string)
4227 memcpy(rbin->data + elf_size, llvm_ir_string, llvm_ir_size + 1);
4228
4229 rbin->base.type = RADV_BINARY_TYPE_RTLD;
4230 rbin->base.stage = stage;
4231 rbin->base.total_size = alloc_size;
4232 rbin->elf_size = elf_size;
4233 rbin->llvm_ir_size = llvm_ir_size;
4234 *rbinary = &rbin->base;
4235
4236 free(llvm_ir_string);
4237 free(elf_buffer);
4238 }
4239
4240 static void
4241 radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
4242 struct radv_shader_binary **rbinary,
4243 const struct radv_shader_args *args,
4244 struct nir_shader *const *nir,
4245 int nir_count)
4246 {
4247
4248 LLVMModuleRef llvm_module;
4249
4250 llvm_module = ac_translate_nir_to_llvm(ac_llvm, nir, nir_count, args);
4251
4252 ac_compile_llvm_module(ac_llvm, llvm_module, rbinary,
4253 nir[nir_count - 1]->info.stage,
4254 radv_get_shader_name(args->shader_info,
4255 nir[nir_count - 1]->info.stage),
4256 args->options);
4257
4258 /* Determine the ES type (VS or TES) for the GS on GFX9. */
4259 if (args->options->chip_class >= GFX9) {
4260 if (nir_count == 2 &&
4261 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
4262 args->shader_info->gs.es_type = nir[0]->info.stage;
4263 }
4264 }
4265 }
4266
4267 static void
4268 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
4269 {
4270 LLVMValueRef vtx_offset =
4271 LLVMBuildMul(ctx->ac.builder, ac_get_arg(&ctx->ac, ctx->args->ac.vertex_id),
4272 LLVMConstInt(ctx->ac.i32, 4, false), "");
4273 LLVMValueRef stream_id;
4274
4275 /* Fetch the vertex stream ID. */
4276 if (!ctx->args->options->use_ngg_streamout &&
4277 ctx->args->shader_info->so.num_outputs) {
4278 stream_id =
4279 ac_unpack_param(&ctx->ac,
4280 ac_get_arg(&ctx->ac,
4281 ctx->args->streamout_config),
4282 24, 2);
4283 } else {
4284 stream_id = ctx->ac.i32_0;
4285 }
4286
4287 LLVMBasicBlockRef end_bb;
4288 LLVMValueRef switch_inst;
4289
4290 end_bb = LLVMAppendBasicBlockInContext(ctx->ac.context,
4291 ctx->main_function, "end");
4292 switch_inst = LLVMBuildSwitch(ctx->ac.builder, stream_id, end_bb, 4);
4293
4294 for (unsigned stream = 0; stream < 4; stream++) {
4295 unsigned num_components =
4296 ctx->args->shader_info->gs.num_stream_output_components[stream];
4297 LLVMBasicBlockRef bb;
4298 unsigned offset;
4299
4300 if (stream > 0 && !num_components)
4301 continue;
4302
4303 if (stream > 0 && !ctx->args->shader_info->so.num_outputs)
4304 continue;
4305
4306 bb = LLVMInsertBasicBlockInContext(ctx->ac.context, end_bb, "out");
4307 LLVMAddCase(switch_inst, LLVMConstInt(ctx->ac.i32, stream, 0), bb);
4308 LLVMPositionBuilderAtEnd(ctx->ac.builder, bb);
4309
4310 offset = 0;
4311 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
4312 unsigned output_usage_mask =
4313 ctx->args->shader_info->gs.output_usage_mask[i];
4314 unsigned output_stream =
4315 ctx->args->shader_info->gs.output_streams[i];
4316 int length = util_last_bit(output_usage_mask);
4317
4318 if (!(ctx->output_mask & (1ull << i)) ||
4319 output_stream != stream)
4320 continue;
4321
4322 for (unsigned j = 0; j < length; j++) {
4323 LLVMValueRef value, soffset;
4324
4325 if (!(output_usage_mask & (1 << j)))
4326 continue;
4327
4328 soffset = LLVMConstInt(ctx->ac.i32,
4329 offset *
4330 ctx->shader->info.gs.vertices_out * 16 * 4, false);
4331
4332 offset++;
4333
4334 value = ac_build_buffer_load(&ctx->ac,
4335 ctx->gsvs_ring[0],
4336 1, ctx->ac.i32_0,
4337 vtx_offset, soffset,
4338 0, ac_glc | ac_slc, true, false);
4339
4340 LLVMTypeRef type = LLVMGetAllocatedType(ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
4341 if (ac_get_type_size(type) == 2) {
4342 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
4343 value = LLVMBuildTrunc(ctx->ac.builder, value, ctx->ac.i16, "");
4344 }
4345
4346 LLVMBuildStore(ctx->ac.builder,
4347 ac_to_float(&ctx->ac, value), ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
4348 }
4349 }
4350
4351 if (!ctx->args->options->use_ngg_streamout &&
4352 ctx->args->shader_info->so.num_outputs)
4353 radv_emit_streamout(ctx, stream);
4354
4355 if (stream == 0) {
4356 handle_vs_outputs_post(ctx, false, true,
4357 &ctx->args->shader_info->vs.outinfo);
4358 }
4359
4360 LLVMBuildBr(ctx->ac.builder, end_bb);
4361 }
4362
4363 LLVMPositionBuilderAtEnd(ctx->ac.builder, end_bb);
4364 }
4365
4366 static void
4367 radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
4368 struct nir_shader *geom_shader,
4369 struct radv_shader_binary **rbinary,
4370 const struct radv_shader_args *args)
4371 {
4372 struct radv_shader_context ctx = {0};
4373 ctx.args = args;
4374
4375 assert(args->is_gs_copy_shader);
4376
4377 ac_llvm_context_init(&ctx.ac, ac_llvm, args->options->chip_class,
4378 args->options->family, AC_FLOAT_MODE_DEFAULT, 64, 64);
4379 ctx.context = ctx.ac.context;
4380
4381 ctx.stage = MESA_SHADER_VERTEX;
4382 ctx.shader = geom_shader;
4383
4384 create_function(&ctx, MESA_SHADER_VERTEX, false);
4385
4386 ac_setup_rings(&ctx);
4387
4388 nir_foreach_variable(variable, &geom_shader->outputs) {
4389 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
4390 ac_handle_shader_output_decl(&ctx.ac, &ctx.abi, geom_shader,
4391 variable, MESA_SHADER_VERTEX);
4392 }
4393
4394 ac_gs_copy_shader_emit(&ctx);
4395
4396 LLVMBuildRetVoid(ctx.ac.builder);
4397
4398 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, args->options);
4399
4400 ac_compile_llvm_module(ac_llvm, ctx.ac.module, rbinary,
4401 MESA_SHADER_VERTEX, "GS Copy Shader", args->options);
4402 (*rbinary)->is_gs_copy_shader = true;
4403
4404 }
4405
4406 void
4407 llvm_compile_shader(struct radv_device *device,
4408 unsigned shader_count,
4409 struct nir_shader *const *shaders,
4410 struct radv_shader_binary **binary,
4411 struct radv_shader_args *args)
4412 {
4413 enum ac_target_machine_options tm_options = 0;
4414 struct ac_llvm_compiler ac_llvm;
4415 bool thread_compiler;
4416
4417 tm_options |= AC_TM_SUPPORTS_SPILL;
4418 if (args->options->check_ir)
4419 tm_options |= AC_TM_CHECK_IR;
4420 if (device->instance->debug_flags & RADV_DEBUG_NO_LOAD_STORE_OPT)
4421 tm_options |= AC_TM_NO_LOAD_STORE_OPT;
4422
4423 thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM);
4424
4425 radv_init_llvm_compiler(&ac_llvm, thread_compiler,
4426 args->options->family, tm_options,
4427 args->shader_info->wave_size);
4428
4429 if (args->is_gs_copy_shader) {
4430 radv_compile_gs_copy_shader(&ac_llvm, *shaders, binary, args);
4431 } else {
4432 radv_compile_nir_shader(&ac_llvm, binary, args,
4433 shaders, shader_count);
4434 }
4435
4436 radv_destroy_llvm_compiler(&ac_llvm, thread_compiler);
4437 }