2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "radv_shader_helper.h"
31 #include "radv_shader_args.h"
32 #include "radv_debug.h"
36 #include "ac_binary.h"
37 #include "ac_llvm_util.h"
38 #include "ac_llvm_build.h"
39 #include "ac_shader_abi.h"
40 #include "ac_shader_util.h"
41 #include "ac_exp_param.h"
43 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
45 struct radv_shader_context
{
46 struct ac_llvm_context ac
;
47 const struct nir_shader
*shader
;
48 struct ac_shader_abi abi
;
49 const struct radv_shader_args
*args
;
51 gl_shader_stage stage
;
53 unsigned max_workgroup_size
;
54 LLVMContextRef context
;
55 LLVMValueRef main_function
;
57 LLVMValueRef descriptor_sets
[MAX_SETS
];
59 LLVMValueRef ring_offsets
;
61 LLVMValueRef rel_auto_id
;
63 LLVMValueRef gs_wave_id
;
64 LLVMValueRef gs_vtx_offset
[6];
66 LLVMValueRef esgs_ring
;
67 LLVMValueRef gsvs_ring
[4];
68 LLVMValueRef hs_ring_tess_offchip
;
69 LLVMValueRef hs_ring_tess_factor
;
71 LLVMValueRef inputs
[RADEON_LLVM_MAX_INPUTS
* 4];
75 LLVMValueRef gs_next_vertex
[4];
76 LLVMValueRef gs_curprim_verts
[4];
77 LLVMValueRef gs_generated_prims
[4];
78 LLVMValueRef gs_ngg_emit
;
79 LLVMValueRef gs_ngg_scratch
;
81 uint32_t tcs_num_inputs
;
82 uint32_t tcs_num_patches
;
84 LLVMValueRef vertexptr
; /* GFX10 only */
87 struct radv_shader_output_values
{
88 LLVMValueRef values
[4];
94 static inline struct radv_shader_context
*
95 radv_shader_context_from_abi(struct ac_shader_abi
*abi
)
97 struct radv_shader_context
*ctx
= NULL
;
98 return container_of(abi
, ctx
, abi
);
101 static LLVMValueRef
get_rel_patch_id(struct radv_shader_context
*ctx
)
103 switch (ctx
->stage
) {
104 case MESA_SHADER_TESS_CTRL
:
105 return ac_unpack_param(&ctx
->ac
,
106 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.tcs_rel_ids
),
108 case MESA_SHADER_TESS_EVAL
:
109 return ac_get_arg(&ctx
->ac
, ctx
->args
->tes_rel_patch_id
);
112 unreachable("Illegal stage");
116 /* Tessellation shaders pass outputs to the next shader using LDS.
118 * LS outputs = TCS inputs
119 * TCS outputs = TES inputs
122 * - TCS inputs for patch 0
123 * - TCS inputs for patch 1
124 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
126 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
127 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
128 * - TCS outputs for patch 1
129 * - Per-patch TCS outputs for patch 1
130 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
131 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
134 * All three shaders VS(LS), TCS, TES share the same LDS space.
137 get_tcs_in_patch_stride(struct radv_shader_context
*ctx
)
139 assert(ctx
->stage
== MESA_SHADER_TESS_CTRL
);
140 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
141 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
143 input_patch_size
/= 4;
144 return LLVMConstInt(ctx
->ac
.i32
, input_patch_size
, false);
148 get_tcs_out_patch_stride(struct radv_shader_context
*ctx
)
150 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
151 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.patch_outputs_written
);
152 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
153 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
154 uint32_t output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
155 output_patch_size
/= 4;
156 return LLVMConstInt(ctx
->ac
.i32
, output_patch_size
, false);
160 get_tcs_out_vertex_stride(struct radv_shader_context
*ctx
)
162 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
163 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
164 output_vertex_size
/= 4;
165 return LLVMConstInt(ctx
->ac
.i32
, output_vertex_size
, false);
169 get_tcs_out_patch0_offset(struct radv_shader_context
*ctx
)
171 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
172 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
173 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
174 uint32_t output_patch0_offset
= input_patch_size
;
175 unsigned num_patches
= ctx
->tcs_num_patches
;
177 output_patch0_offset
*= num_patches
;
178 output_patch0_offset
/= 4;
179 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
183 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context
*ctx
)
185 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
186 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
187 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
188 uint32_t output_patch0_offset
= input_patch_size
;
190 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
191 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
192 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
193 unsigned num_patches
= ctx
->tcs_num_patches
;
195 output_patch0_offset
*= num_patches
;
196 output_patch0_offset
+= pervertex_output_patch_size
;
197 output_patch0_offset
/= 4;
198 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
202 get_tcs_in_current_patch_offset(struct radv_shader_context
*ctx
)
204 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
205 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
207 return LLVMBuildMul(ctx
->ac
.builder
, patch_stride
, rel_patch_id
, "");
211 get_tcs_out_current_patch_offset(struct radv_shader_context
*ctx
)
213 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
214 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
215 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
217 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
,
222 get_tcs_out_current_patch_data_offset(struct radv_shader_context
*ctx
)
224 LLVMValueRef patch0_patch_data_offset
=
225 get_tcs_out_patch0_patch_data_offset(ctx
);
226 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
227 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
229 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
,
230 patch0_patch_data_offset
);
234 create_llvm_function(struct ac_llvm_context
*ctx
, LLVMModuleRef module
,
235 LLVMBuilderRef builder
,
236 const struct ac_shader_args
*args
,
237 enum ac_llvm_calling_convention convention
,
238 unsigned max_workgroup_size
,
239 const struct radv_nir_compiler_options
*options
)
241 LLVMValueRef main_function
=
242 ac_build_main(args
, ctx
, convention
, "main", ctx
->voidt
, module
);
244 if (options
->address32_hi
) {
245 ac_llvm_add_target_dep_function_attr(main_function
,
246 "amdgpu-32bit-address-high-bits",
247 options
->address32_hi
);
250 ac_llvm_set_workgroup_size(main_function
, max_workgroup_size
);
252 return main_function
;
256 load_descriptor_sets(struct radv_shader_context
*ctx
)
258 uint32_t mask
= ctx
->args
->shader_info
->desc_set_used_mask
;
259 if (ctx
->args
->shader_info
->need_indirect_descriptor_sets
) {
260 LLVMValueRef desc_sets
=
261 ac_get_arg(&ctx
->ac
, ctx
->args
->descriptor_sets
[0]);
263 int i
= u_bit_scan(&mask
);
265 ctx
->descriptor_sets
[i
] =
266 ac_build_load_to_sgpr(&ctx
->ac
, desc_sets
,
267 LLVMConstInt(ctx
->ac
.i32
, i
, false));
272 int i
= u_bit_scan(&mask
);
274 ctx
->descriptor_sets
[i
] =
275 ac_get_arg(&ctx
->ac
, ctx
->args
->descriptor_sets
[i
]);
280 static enum ac_llvm_calling_convention
281 get_llvm_calling_convention(LLVMValueRef func
, gl_shader_stage stage
)
284 case MESA_SHADER_VERTEX
:
285 case MESA_SHADER_TESS_EVAL
:
286 return AC_LLVM_AMDGPU_VS
;
288 case MESA_SHADER_GEOMETRY
:
289 return AC_LLVM_AMDGPU_GS
;
291 case MESA_SHADER_TESS_CTRL
:
292 return AC_LLVM_AMDGPU_HS
;
294 case MESA_SHADER_FRAGMENT
:
295 return AC_LLVM_AMDGPU_PS
;
297 case MESA_SHADER_COMPUTE
:
298 return AC_LLVM_AMDGPU_CS
;
301 unreachable("Unhandle shader type");
305 /* Returns whether the stage is a stage that can be directly before the GS */
306 static bool is_pre_gs_stage(gl_shader_stage stage
)
308 return stage
== MESA_SHADER_VERTEX
|| stage
== MESA_SHADER_TESS_EVAL
;
311 static void create_function(struct radv_shader_context
*ctx
,
312 gl_shader_stage stage
,
313 bool has_previous_stage
)
315 if (ctx
->ac
.chip_class
>= GFX10
) {
316 if (is_pre_gs_stage(stage
) && ctx
->args
->options
->key
.vs_common_out
.as_ngg
) {
317 /* On GFX10, VS is merged into GS for NGG. */
318 stage
= MESA_SHADER_GEOMETRY
;
319 has_previous_stage
= true;
323 ctx
->main_function
= create_llvm_function(
324 &ctx
->ac
, ctx
->ac
.module
, ctx
->ac
.builder
, &ctx
->args
->ac
,
325 get_llvm_calling_convention(ctx
->main_function
, stage
),
326 ctx
->max_workgroup_size
,
329 ctx
->ring_offsets
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.implicit.buffer.ptr",
330 LLVMPointerType(ctx
->ac
.i8
, AC_ADDR_SPACE_CONST
),
331 NULL
, 0, AC_FUNC_ATTR_READNONE
);
332 ctx
->ring_offsets
= LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->ring_offsets
,
333 ac_array_in_const_addr_space(ctx
->ac
.v4i32
), "");
335 load_descriptor_sets(ctx
);
337 if (stage
== MESA_SHADER_TESS_CTRL
||
338 (stage
== MESA_SHADER_VERTEX
&& ctx
->args
->options
->key
.vs_common_out
.as_ls
) ||
339 /* GFX9 has the ESGS ring buffer in LDS. */
340 (stage
== MESA_SHADER_GEOMETRY
&& has_previous_stage
)) {
341 ac_declare_lds_as_pointer(&ctx
->ac
);
348 radv_load_resource(struct ac_shader_abi
*abi
, LLVMValueRef index
,
349 unsigned desc_set
, unsigned binding
)
351 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
352 LLVMValueRef desc_ptr
= ctx
->descriptor_sets
[desc_set
];
353 struct radv_pipeline_layout
*pipeline_layout
= ctx
->args
->options
->layout
;
354 struct radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
355 unsigned base_offset
= layout
->binding
[binding
].offset
;
356 LLVMValueRef offset
, stride
;
358 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
359 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
360 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+
361 layout
->binding
[binding
].dynamic_offset_offset
;
362 desc_ptr
= ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.push_constants
);
363 base_offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
364 stride
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
366 stride
= LLVMConstInt(ctx
->ac
.i32
, layout
->binding
[binding
].size
, false);
368 offset
= LLVMConstInt(ctx
->ac
.i32
, base_offset
, false);
370 if (layout
->binding
[binding
].type
!= VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
371 offset
= ac_build_imad(&ctx
->ac
, index
, stride
, offset
);
374 desc_ptr
= LLVMBuildGEP(ctx
->ac
.builder
, desc_ptr
, &offset
, 1, "");
375 desc_ptr
= ac_cast_ptr(&ctx
->ac
, desc_ptr
, ctx
->ac
.v4i32
);
376 LLVMSetMetadata(desc_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
378 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
379 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
380 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
381 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
382 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
384 if (ctx
->ac
.chip_class
>= GFX10
) {
385 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
386 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW
) |
387 S_008F0C_RESOURCE_LEVEL(1);
389 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
390 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
393 LLVMValueRef desc_components
[4] = {
394 LLVMBuildPtrToInt(ctx
->ac
.builder
, desc_ptr
, ctx
->ac
.intptr
, ""),
395 LLVMConstInt(ctx
->ac
.i32
, S_008F04_BASE_ADDRESS_HI(ctx
->args
->options
->address32_hi
), false),
396 /* High limit to support variable sizes. */
397 LLVMConstInt(ctx
->ac
.i32
, 0xffffffff, false),
398 LLVMConstInt(ctx
->ac
.i32
, desc_type
, false),
401 return ac_build_gather_values(&ctx
->ac
, desc_components
, 4);
408 /* The offchip buffer layout for TCS->TES is
410 * - attribute 0 of patch 0 vertex 0
411 * - attribute 0 of patch 0 vertex 1
412 * - attribute 0 of patch 0 vertex 2
414 * - attribute 0 of patch 1 vertex 0
415 * - attribute 0 of patch 1 vertex 1
417 * - attribute 1 of patch 0 vertex 0
418 * - attribute 1 of patch 0 vertex 1
420 * - per patch attribute 0 of patch 0
421 * - per patch attribute 0 of patch 1
424 * Note that every attribute has 4 components.
426 static LLVMValueRef
get_non_vertex_index_offset(struct radv_shader_context
*ctx
)
428 uint32_t num_patches
= ctx
->tcs_num_patches
;
429 uint32_t num_tcs_outputs
;
430 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
431 num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
433 num_tcs_outputs
= ctx
->args
->options
->key
.tes
.tcs_num_outputs
;
435 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
436 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
438 return LLVMConstInt(ctx
->ac
.i32
, pervertex_output_patch_size
* num_patches
, false);
441 static LLVMValueRef
calc_param_stride(struct radv_shader_context
*ctx
,
442 LLVMValueRef vertex_index
)
444 LLVMValueRef param_stride
;
446 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.tess
.tcs_vertices_out
* ctx
->tcs_num_patches
, false);
448 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_num_patches
, false);
452 static LLVMValueRef
get_tcs_tes_buffer_address(struct radv_shader_context
*ctx
,
453 LLVMValueRef vertex_index
,
454 LLVMValueRef param_index
)
456 LLVMValueRef base_addr
;
457 LLVMValueRef param_stride
, constant16
;
458 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
459 LLVMValueRef vertices_per_patch
= LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.tess
.tcs_vertices_out
, false);
460 constant16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
461 param_stride
= calc_param_stride(ctx
, vertex_index
);
463 base_addr
= ac_build_imad(&ctx
->ac
, rel_patch_id
,
464 vertices_per_patch
, vertex_index
);
466 base_addr
= rel_patch_id
;
469 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
470 LLVMBuildMul(ctx
->ac
.builder
, param_index
,
471 param_stride
, ""), "");
473 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, base_addr
, constant16
, "");
476 LLVMValueRef patch_data_offset
= get_non_vertex_index_offset(ctx
);
478 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
479 patch_data_offset
, "");
484 static LLVMValueRef
get_tcs_tes_buffer_address_params(struct radv_shader_context
*ctx
,
486 unsigned const_index
,
488 LLVMValueRef vertex_index
,
489 LLVMValueRef indir_index
)
491 LLVMValueRef param_index
;
494 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, param
, false),
497 if (const_index
&& !is_compact
)
498 param
+= const_index
;
499 param_index
= LLVMConstInt(ctx
->ac
.i32
, param
, false);
501 return get_tcs_tes_buffer_address(ctx
, vertex_index
, param_index
);
505 get_dw_address(struct radv_shader_context
*ctx
,
506 LLVMValueRef dw_addr
,
508 unsigned const_index
,
509 bool compact_const_index
,
510 LLVMValueRef vertex_index
,
512 LLVMValueRef indir_index
)
517 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
518 LLVMBuildMul(ctx
->ac
.builder
,
524 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
525 LLVMBuildMul(ctx
->ac
.builder
, indir_index
,
526 LLVMConstInt(ctx
->ac
.i32
, 4, false), ""), "");
527 else if (const_index
&& !compact_const_index
)
528 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
529 LLVMConstInt(ctx
->ac
.i32
, const_index
* 4, false), "");
531 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
532 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false), "");
534 if (const_index
&& compact_const_index
)
535 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
536 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
541 load_tcs_varyings(struct ac_shader_abi
*abi
,
543 LLVMValueRef vertex_index
,
544 LLVMValueRef indir_index
,
545 unsigned const_index
,
547 unsigned driver_location
,
549 unsigned num_components
,
554 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
555 LLVMValueRef dw_addr
, stride
;
556 LLVMValueRef value
[4], result
;
557 unsigned param
= shader_io_get_unique_index(location
);
560 uint32_t input_vertex_size
= (ctx
->tcs_num_inputs
* 16) / 4;
561 stride
= LLVMConstInt(ctx
->ac
.i32
, input_vertex_size
, false);
562 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
565 stride
= get_tcs_out_vertex_stride(ctx
);
566 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
568 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
573 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
576 for (unsigned i
= 0; i
< num_components
+ component
; i
++) {
577 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
578 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
581 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
586 store_tcs_output(struct ac_shader_abi
*abi
,
587 const nir_variable
*var
,
588 LLVMValueRef vertex_index
,
589 LLVMValueRef param_index
,
590 unsigned const_index
,
594 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
595 const unsigned location
= var
->data
.location
;
596 unsigned component
= var
->data
.location_frac
;
597 const bool is_patch
= var
->data
.patch
;
598 const bool is_compact
= var
->data
.compact
;
599 LLVMValueRef dw_addr
;
600 LLVMValueRef stride
= NULL
;
601 LLVMValueRef buf_addr
= NULL
;
602 LLVMValueRef oc_lds
= ac_get_arg(&ctx
->ac
, ctx
->args
->oc_lds
);
604 bool store_lds
= true;
607 if (!(ctx
->shader
->info
.patch_outputs_read
& (1U << (location
- VARYING_SLOT_PATCH0
))))
610 if (!(ctx
->shader
->info
.outputs_read
& (1ULL << location
)))
614 param
= shader_io_get_unique_index(location
);
615 if ((location
== VARYING_SLOT_CLIP_DIST0
|| location
== VARYING_SLOT_CLIP_DIST1
) && is_compact
) {
616 const_index
+= component
;
619 if (const_index
>= 4) {
626 stride
= get_tcs_out_vertex_stride(ctx
);
627 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
629 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
632 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
634 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
, is_compact
,
635 vertex_index
, param_index
);
637 bool is_tess_factor
= false;
638 if (location
== VARYING_SLOT_TESS_LEVEL_INNER
||
639 location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
640 is_tess_factor
= true;
642 unsigned base
= is_compact
? const_index
: 0;
643 for (unsigned chan
= 0; chan
< 8; chan
++) {
644 if (!(writemask
& (1 << chan
)))
646 LLVMValueRef value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- component
);
647 value
= ac_to_integer(&ctx
->ac
, value
);
648 value
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
650 if (store_lds
|| is_tess_factor
) {
651 LLVMValueRef dw_addr_chan
=
652 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
653 LLVMConstInt(ctx
->ac
.i32
, chan
, false), "");
654 ac_lds_store(&ctx
->ac
, dw_addr_chan
, value
);
657 if (!is_tess_factor
&& writemask
!= 0xF)
658 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, value
, 1,
660 4 * (base
+ chan
), ac_glc
);
663 if (writemask
== 0xF) {
664 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, src
, 4,
671 load_tes_input(struct ac_shader_abi
*abi
,
673 LLVMValueRef vertex_index
,
674 LLVMValueRef param_index
,
675 unsigned const_index
,
677 unsigned driver_location
,
679 unsigned num_components
,
684 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
685 LLVMValueRef buf_addr
;
687 LLVMValueRef oc_lds
= ac_get_arg(&ctx
->ac
, ctx
->args
->oc_lds
);
688 unsigned param
= shader_io_get_unique_index(location
);
690 if ((location
== VARYING_SLOT_CLIP_DIST0
|| location
== VARYING_SLOT_CLIP_DIST1
) && is_compact
) {
691 const_index
+= component
;
693 if (const_index
>= 4) {
699 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
,
700 is_compact
, vertex_index
, param_index
);
702 LLVMValueRef comp_offset
= LLVMConstInt(ctx
->ac
.i32
, component
* 4, false);
703 buf_addr
= LLVMBuildAdd(ctx
->ac
.builder
, buf_addr
, comp_offset
, "");
705 result
= ac_build_buffer_load(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, num_components
, NULL
,
706 buf_addr
, oc_lds
, is_compact
? (4 * const_index
) : 0, ac_glc
, true, false);
707 result
= ac_trim_vector(&ctx
->ac
, result
, num_components
);
712 radv_emit_fetch_64bit(struct radv_shader_context
*ctx
,
713 LLVMTypeRef type
, LLVMValueRef a
, LLVMValueRef b
)
715 LLVMValueRef values
[2] = {
716 ac_to_integer(&ctx
->ac
, a
),
717 ac_to_integer(&ctx
->ac
, b
),
719 LLVMValueRef result
= ac_build_gather_values(&ctx
->ac
, values
, 2);
720 return LLVMBuildBitCast(ctx
->ac
.builder
, result
, type
, "");
724 load_gs_input(struct ac_shader_abi
*abi
,
726 unsigned driver_location
,
728 unsigned num_components
,
729 unsigned vertex_index
,
730 unsigned const_index
,
733 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
734 LLVMValueRef vtx_offset
;
735 unsigned param
, vtx_offset_param
;
736 LLVMValueRef value
[4], result
;
738 vtx_offset_param
= vertex_index
;
739 assert(vtx_offset_param
< 6);
740 vtx_offset
= LLVMBuildMul(ctx
->ac
.builder
, ctx
->gs_vtx_offset
[vtx_offset_param
],
741 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
743 param
= shader_io_get_unique_index(location
);
745 for (unsigned i
= component
; i
< num_components
+ component
; i
++) {
746 if (ctx
->ac
.chip_class
>= GFX9
) {
747 LLVMValueRef dw_addr
= ctx
->gs_vtx_offset
[vtx_offset_param
];
748 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
749 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
, 0), "");
750 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
752 if (ac_get_type_size(type
) == 8) {
753 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
754 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
+ 1, 0), "");
755 LLVMValueRef tmp
= ac_lds_load(&ctx
->ac
, dw_addr
);
757 value
[i
] = radv_emit_fetch_64bit(ctx
, type
, value
[i
], tmp
);
760 LLVMValueRef soffset
=
761 LLVMConstInt(ctx
->ac
.i32
,
762 (param
* 4 + i
+ const_index
) * 256,
765 value
[i
] = ac_build_buffer_load(&ctx
->ac
,
769 0, ac_glc
, true, false);
771 if (ac_get_type_size(type
) == 8) {
772 soffset
= LLVMConstInt(ctx
->ac
.i32
,
773 (param
* 4 + i
+ const_index
+ 1) * 256,
777 ac_build_buffer_load(&ctx
->ac
,
781 0, ac_glc
, true, false);
783 value
[i
] = radv_emit_fetch_64bit(ctx
, type
, value
[i
], tmp
);
787 if (ac_get_type_size(type
) == 2) {
788 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
], ctx
->ac
.i32
, "");
789 value
[i
] = LLVMBuildTrunc(ctx
->ac
.builder
, value
[i
], ctx
->ac
.i16
, "");
791 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
], type
, "");
793 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
794 result
= ac_to_integer(&ctx
->ac
, result
);
799 radv_get_sample_pos_offset(uint32_t num_samples
)
801 uint32_t sample_pos_offset
= 0;
803 switch (num_samples
) {
805 sample_pos_offset
= 1;
808 sample_pos_offset
= 3;
811 sample_pos_offset
= 7;
816 return sample_pos_offset
;
819 static LLVMValueRef
load_sample_position(struct ac_shader_abi
*abi
,
820 LLVMValueRef sample_id
)
822 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
825 LLVMValueRef index
= LLVMConstInt(ctx
->ac
.i32
, RING_PS_SAMPLE_POSITIONS
, false);
826 LLVMValueRef ptr
= LLVMBuildGEP(ctx
->ac
.builder
, ctx
->ring_offsets
, &index
, 1, "");
828 ptr
= LLVMBuildBitCast(ctx
->ac
.builder
, ptr
,
829 ac_array_in_const_addr_space(ctx
->ac
.v2f32
), "");
831 uint32_t sample_pos_offset
=
832 radv_get_sample_pos_offset(ctx
->args
->options
->key
.fs
.num_samples
);
835 LLVMBuildAdd(ctx
->ac
.builder
, sample_id
,
836 LLVMConstInt(ctx
->ac
.i32
, sample_pos_offset
, false), "");
837 result
= ac_build_load_invariant(&ctx
->ac
, ptr
, sample_id
);
843 static LLVMValueRef
load_sample_mask_in(struct ac_shader_abi
*abi
)
845 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
846 uint8_t log2_ps_iter_samples
;
848 if (ctx
->args
->shader_info
->ps
.force_persample
) {
849 log2_ps_iter_samples
=
850 util_logbase2(ctx
->args
->options
->key
.fs
.num_samples
);
852 log2_ps_iter_samples
= ctx
->args
->options
->key
.fs
.log2_ps_iter_samples
;
855 /* The bit pattern matches that used by fixed function fragment
857 static const uint16_t ps_iter_masks
[] = {
858 0xffff, /* not used */
864 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
866 uint32_t ps_iter_mask
= ps_iter_masks
[log2_ps_iter_samples
];
868 LLVMValueRef result
, sample_id
;
869 sample_id
= ac_unpack_param(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.ancillary
), 8, 4);
870 sample_id
= LLVMBuildShl(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, ps_iter_mask
, false), sample_id
, "");
871 result
= LLVMBuildAnd(ctx
->ac
.builder
, sample_id
,
872 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.sample_coverage
), "");
877 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context
*ctx
,
879 LLVMValueRef
*addrs
);
882 visit_emit_vertex(struct ac_shader_abi
*abi
, unsigned stream
, LLVMValueRef
*addrs
)
884 LLVMValueRef gs_next_vertex
;
885 LLVMValueRef can_emit
;
887 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
889 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg
) {
890 gfx10_ngg_gs_emit_vertex(ctx
, stream
, addrs
);
894 /* Write vertex attribute values to GSVS ring */
895 gs_next_vertex
= LLVMBuildLoad(ctx
->ac
.builder
,
896 ctx
->gs_next_vertex
[stream
],
899 /* If this thread has already emitted the declared maximum number of
900 * vertices, don't emit any more: excessive vertex emissions are not
901 * supposed to have any effect.
903 can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
, gs_next_vertex
,
904 LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.gs
.vertices_out
, false), "");
906 bool use_kill
= !ctx
->args
->shader_info
->gs
.writes_memory
;
908 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
910 ac_build_ifcc(&ctx
->ac
, can_emit
, 6505);
912 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
913 unsigned output_usage_mask
=
914 ctx
->args
->shader_info
->gs
.output_usage_mask
[i
];
915 uint8_t output_stream
=
916 ctx
->args
->shader_info
->gs
.output_streams
[i
];
917 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
918 int length
= util_last_bit(output_usage_mask
);
920 if (!(ctx
->output_mask
& (1ull << i
)) ||
921 output_stream
!= stream
)
924 for (unsigned j
= 0; j
< length
; j
++) {
925 if (!(output_usage_mask
& (1 << j
)))
928 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
,
930 LLVMValueRef voffset
=
931 LLVMConstInt(ctx
->ac
.i32
, offset
*
932 ctx
->shader
->info
.gs
.vertices_out
, false);
936 voffset
= LLVMBuildAdd(ctx
->ac
.builder
, voffset
, gs_next_vertex
, "");
937 voffset
= LLVMBuildMul(ctx
->ac
.builder
, voffset
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
939 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
940 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
942 ac_build_buffer_store_dword(&ctx
->ac
,
943 ctx
->gsvs_ring
[stream
],
947 ctx
->args
->gs2vs_offset
),
948 0, ac_glc
| ac_slc
| ac_swizzled
);
952 gs_next_vertex
= LLVMBuildAdd(ctx
->ac
.builder
, gs_next_vertex
,
954 LLVMBuildStore(ctx
->ac
.builder
, gs_next_vertex
, ctx
->gs_next_vertex
[stream
]);
956 ac_build_sendmsg(&ctx
->ac
,
957 AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (stream
<< 8),
961 ac_build_endif(&ctx
->ac
, 6505);
965 visit_end_primitive(struct ac_shader_abi
*abi
, unsigned stream
)
967 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
969 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg
) {
970 LLVMBuildStore(ctx
->ac
.builder
, ctx
->ac
.i32_0
, ctx
->gs_curprim_verts
[stream
]);
974 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (stream
<< 8), ctx
->gs_wave_id
);
978 load_tess_coord(struct ac_shader_abi
*abi
)
980 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
982 LLVMValueRef coord
[4] = {
983 ac_get_arg(&ctx
->ac
, ctx
->args
->tes_u
),
984 ac_get_arg(&ctx
->ac
, ctx
->args
->tes_v
),
989 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
)
990 coord
[2] = LLVMBuildFSub(ctx
->ac
.builder
, ctx
->ac
.f32_1
,
991 LLVMBuildFAdd(ctx
->ac
.builder
, coord
[0], coord
[1], ""), "");
993 return ac_build_gather_values(&ctx
->ac
, coord
, 3);
997 load_patch_vertices_in(struct ac_shader_abi
*abi
)
999 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1000 return LLVMConstInt(ctx
->ac
.i32
, ctx
->args
->options
->key
.tcs
.input_vertices
, false);
1004 static LLVMValueRef
radv_load_base_vertex(struct ac_shader_abi
*abi
)
1006 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1007 return ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.base_vertex
);
1010 static LLVMValueRef
radv_load_ssbo(struct ac_shader_abi
*abi
,
1011 LLVMValueRef buffer_ptr
, bool write
)
1013 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1014 LLVMValueRef result
;
1016 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1018 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
1019 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
1024 static LLVMValueRef
radv_load_ubo(struct ac_shader_abi
*abi
, LLVMValueRef buffer_ptr
)
1026 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1027 LLVMValueRef result
;
1029 if (LLVMGetTypeKind(LLVMTypeOf(buffer_ptr
)) != LLVMPointerTypeKind
) {
1030 /* Do not load the descriptor for inlined uniform blocks. */
1034 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1036 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
1037 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
1042 static LLVMValueRef
radv_get_sampler_desc(struct ac_shader_abi
*abi
,
1043 unsigned descriptor_set
,
1044 unsigned base_index
,
1045 unsigned constant_index
,
1047 enum ac_descriptor_type desc_type
,
1048 bool image
, bool write
,
1051 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1052 LLVMValueRef list
= ctx
->descriptor_sets
[descriptor_set
];
1053 struct radv_descriptor_set_layout
*layout
= ctx
->args
->options
->layout
->set
[descriptor_set
].layout
;
1054 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
1055 unsigned offset
= binding
->offset
;
1056 unsigned stride
= binding
->size
;
1058 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1061 assert(base_index
< layout
->binding_count
);
1063 switch (desc_type
) {
1065 type
= ctx
->ac
.v8i32
;
1069 type
= ctx
->ac
.v8i32
;
1073 case AC_DESC_SAMPLER
:
1074 type
= ctx
->ac
.v4i32
;
1075 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
) {
1076 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
1081 case AC_DESC_BUFFER
:
1082 type
= ctx
->ac
.v4i32
;
1085 case AC_DESC_PLANE_0
:
1086 case AC_DESC_PLANE_1
:
1087 case AC_DESC_PLANE_2
:
1088 type
= ctx
->ac
.v8i32
;
1090 offset
+= 32 * (desc_type
- AC_DESC_PLANE_0
);
1093 unreachable("invalid desc_type\n");
1096 offset
+= constant_index
* stride
;
1098 if (desc_type
== AC_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
1099 (!index
|| binding
->immutable_samplers_equal
)) {
1100 if (binding
->immutable_samplers_equal
)
1103 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
1105 LLVMValueRef constants
[] = {
1106 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 0], 0),
1107 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 1], 0),
1108 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 2], 0),
1109 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 3], 0),
1111 return ac_build_gather_values(&ctx
->ac
, constants
, 4);
1114 assert(stride
% type_size
== 0);
1116 LLVMValueRef adjusted_index
= index
;
1117 if (!adjusted_index
)
1118 adjusted_index
= ctx
->ac
.i32_0
;
1120 adjusted_index
= LLVMBuildMul(builder
, adjusted_index
, LLVMConstInt(ctx
->ac
.i32
, stride
/ type_size
, 0), "");
1122 LLVMValueRef val_offset
= LLVMConstInt(ctx
->ac
.i32
, offset
, 0);
1123 list
= LLVMBuildGEP(builder
, list
, &val_offset
, 1, "");
1124 list
= LLVMBuildPointerCast(builder
, list
,
1125 ac_array_in_const32_addr_space(type
), "");
1127 LLVMValueRef descriptor
= ac_build_load_to_sgpr(&ctx
->ac
, list
, adjusted_index
);
1129 /* 3 plane formats always have same size and format for plane 1 & 2, so
1130 * use the tail from plane 1 so that we can store only the first 16 bytes
1131 * of the last plane. */
1132 if (desc_type
== AC_DESC_PLANE_2
) {
1133 LLVMValueRef descriptor2
= radv_get_sampler_desc(abi
, descriptor_set
, base_index
, constant_index
, index
, AC_DESC_PLANE_1
,image
, write
, bindless
);
1135 LLVMValueRef components
[8];
1136 for (unsigned i
= 0; i
< 4; ++i
)
1137 components
[i
] = ac_llvm_extract_elem(&ctx
->ac
, descriptor
, i
);
1139 for (unsigned i
= 4; i
< 8; ++i
)
1140 components
[i
] = ac_llvm_extract_elem(&ctx
->ac
, descriptor2
, i
);
1141 descriptor
= ac_build_gather_values(&ctx
->ac
, components
, 8);
1147 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
1148 * so we may need to fix it up. */
1150 adjust_vertex_fetch_alpha(struct radv_shader_context
*ctx
,
1151 unsigned adjustment
,
1154 if (adjustment
== RADV_ALPHA_ADJUST_NONE
)
1157 LLVMValueRef c30
= LLVMConstInt(ctx
->ac
.i32
, 30, 0);
1159 alpha
= LLVMBuildBitCast(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
1161 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
1162 alpha
= LLVMBuildFPToUI(ctx
->ac
.builder
, alpha
, ctx
->ac
.i32
, "");
1164 alpha
= ac_to_integer(&ctx
->ac
, alpha
);
1166 /* For the integer-like cases, do a natural sign extension.
1168 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
1169 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
1172 alpha
= LLVMBuildShl(ctx
->ac
.builder
, alpha
,
1173 adjustment
== RADV_ALPHA_ADJUST_SNORM
?
1174 LLVMConstInt(ctx
->ac
.i32
, 7, 0) : c30
, "");
1175 alpha
= LLVMBuildAShr(ctx
->ac
.builder
, alpha
, c30
, "");
1177 /* Convert back to the right type. */
1178 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
1180 LLVMValueRef neg_one
= LLVMConstReal(ctx
->ac
.f32
, -1.0);
1181 alpha
= LLVMBuildSIToFP(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
1182 clamp
= LLVMBuildFCmp(ctx
->ac
.builder
, LLVMRealULT
, alpha
, neg_one
, "");
1183 alpha
= LLVMBuildSelect(ctx
->ac
.builder
, clamp
, neg_one
, alpha
, "");
1184 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
1185 alpha
= LLVMBuildSIToFP(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
1188 return LLVMBuildBitCast(ctx
->ac
.builder
, alpha
, ctx
->ac
.i32
, "");
1192 radv_fixup_vertex_input_fetches(struct radv_shader_context
*ctx
,
1194 unsigned num_channels
,
1197 LLVMValueRef zero
= is_float
? ctx
->ac
.f32_0
: ctx
->ac
.i32_0
;
1198 LLVMValueRef one
= is_float
? ctx
->ac
.f32_1
: ctx
->ac
.i32_1
;
1199 LLVMValueRef chan
[4];
1201 if (LLVMGetTypeKind(LLVMTypeOf(value
)) == LLVMVectorTypeKind
) {
1202 unsigned vec_size
= LLVMGetVectorSize(LLVMTypeOf(value
));
1204 if (num_channels
== 4 && num_channels
== vec_size
)
1207 num_channels
= MIN2(num_channels
, vec_size
);
1209 for (unsigned i
= 0; i
< num_channels
; i
++)
1210 chan
[i
] = ac_llvm_extract_elem(&ctx
->ac
, value
, i
);
1212 assert(num_channels
== 1);
1216 for (unsigned i
= num_channels
; i
< 4; i
++) {
1217 chan
[i
] = i
== 3 ? one
: zero
;
1218 chan
[i
] = ac_to_integer(&ctx
->ac
, chan
[i
]);
1221 return ac_build_gather_values(&ctx
->ac
, chan
, 4);
1225 handle_vs_input_decl(struct radv_shader_context
*ctx
,
1226 struct nir_variable
*variable
)
1228 LLVMValueRef t_list_ptr
= ac_get_arg(&ctx
->ac
, ctx
->args
->vertex_buffers
);
1229 LLVMValueRef t_offset
;
1230 LLVMValueRef t_list
;
1232 LLVMValueRef buffer_index
;
1233 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, true);
1234 uint8_t input_usage_mask
=
1235 ctx
->args
->shader_info
->vs
.input_usage_mask
[variable
->data
.location
];
1236 unsigned num_input_channels
= util_last_bit(input_usage_mask
);
1238 variable
->data
.driver_location
= variable
->data
.location
* 4;
1240 enum glsl_base_type type
= glsl_get_base_type(variable
->type
);
1241 for (unsigned i
= 0; i
< attrib_count
; ++i
) {
1242 LLVMValueRef output
[4];
1243 unsigned attrib_index
= variable
->data
.location
+ i
- VERT_ATTRIB_GENERIC0
;
1244 unsigned attrib_format
= ctx
->args
->options
->key
.vs
.vertex_attribute_formats
[attrib_index
];
1245 unsigned data_format
= attrib_format
& 0x0f;
1246 unsigned num_format
= (attrib_format
>> 4) & 0x07;
1247 bool is_float
= num_format
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
1248 num_format
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
1250 if (ctx
->args
->options
->key
.vs
.instance_rate_inputs
& (1u << attrib_index
)) {
1251 uint32_t divisor
= ctx
->args
->options
->key
.vs
.instance_rate_divisors
[attrib_index
];
1254 buffer_index
= ctx
->abi
.instance_id
;
1257 buffer_index
= LLVMBuildUDiv(ctx
->ac
.builder
, buffer_index
,
1258 LLVMConstInt(ctx
->ac
.i32
, divisor
, 0), "");
1261 buffer_index
= ctx
->ac
.i32_0
;
1264 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
,
1265 ac_get_arg(&ctx
->ac
,
1266 ctx
->args
->ac
.start_instance
),\
1269 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
,
1271 ac_get_arg(&ctx
->ac
,
1272 ctx
->args
->ac
.base_vertex
), "");
1275 const struct ac_data_format_info
*vtx_info
= ac_get_data_format_info(data_format
);
1277 /* Adjust the number of channels to load based on the vertex
1280 unsigned num_channels
= MIN2(num_input_channels
, vtx_info
->num_channels
);
1281 unsigned attrib_binding
= ctx
->args
->options
->key
.vs
.vertex_attribute_bindings
[attrib_index
];
1282 unsigned attrib_offset
= ctx
->args
->options
->key
.vs
.vertex_attribute_offsets
[attrib_index
];
1283 unsigned attrib_stride
= ctx
->args
->options
->key
.vs
.vertex_attribute_strides
[attrib_index
];
1285 if (ctx
->args
->options
->key
.vs
.post_shuffle
& (1 << attrib_index
)) {
1286 /* Always load, at least, 3 channels for formats that
1287 * need to be shuffled because X<->Z.
1289 num_channels
= MAX2(num_channels
, 3);
1292 t_offset
= LLVMConstInt(ctx
->ac
.i32
, attrib_binding
, false);
1293 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
1295 /* Perform per-channel vertex fetch operations if unaligned
1296 * access are detected. Only GFX6 and GFX10 are affected.
1298 bool unaligned_vertex_fetches
= false;
1299 if ((ctx
->ac
.chip_class
== GFX6
|| ctx
->ac
.chip_class
== GFX10
) &&
1300 vtx_info
->chan_format
!= data_format
&&
1301 ((attrib_offset
% vtx_info
->element_size
) ||
1302 (attrib_stride
% vtx_info
->element_size
)))
1303 unaligned_vertex_fetches
= true;
1305 if (unaligned_vertex_fetches
) {
1306 unsigned chan_format
= vtx_info
->chan_format
;
1307 LLVMValueRef values
[4];
1309 assert(ctx
->ac
.chip_class
== GFX6
||
1310 ctx
->ac
.chip_class
== GFX10
);
1312 for (unsigned chan
= 0; chan
< num_channels
; chan
++) {
1313 unsigned chan_offset
= attrib_offset
+ chan
* vtx_info
->chan_byte_size
;
1314 LLVMValueRef chan_index
= buffer_index
;
1316 if (attrib_stride
!= 0 && chan_offset
> attrib_stride
) {
1317 LLVMValueRef buffer_offset
=
1318 LLVMConstInt(ctx
->ac
.i32
,
1319 chan_offset
/ attrib_stride
, false);
1321 chan_index
= LLVMBuildAdd(ctx
->ac
.builder
,
1325 chan_offset
= chan_offset
% attrib_stride
;
1328 values
[chan
] = ac_build_struct_tbuffer_load(&ctx
->ac
, t_list
,
1330 LLVMConstInt(ctx
->ac
.i32
, chan_offset
, false),
1331 ctx
->ac
.i32_0
, ctx
->ac
.i32_0
, 1,
1332 chan_format
, num_format
, 0, true);
1335 input
= ac_build_gather_values(&ctx
->ac
, values
, num_channels
);
1337 if (attrib_stride
!= 0 && attrib_offset
> attrib_stride
) {
1338 LLVMValueRef buffer_offset
=
1339 LLVMConstInt(ctx
->ac
.i32
,
1340 attrib_offset
/ attrib_stride
, false);
1342 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
,
1346 attrib_offset
= attrib_offset
% attrib_stride
;
1349 input
= ac_build_struct_tbuffer_load(&ctx
->ac
, t_list
,
1351 LLVMConstInt(ctx
->ac
.i32
, attrib_offset
, false),
1352 ctx
->ac
.i32_0
, ctx
->ac
.i32_0
,
1354 data_format
, num_format
, 0, true);
1357 if (ctx
->args
->options
->key
.vs
.post_shuffle
& (1 << attrib_index
)) {
1359 c
[0] = ac_llvm_extract_elem(&ctx
->ac
, input
, 2);
1360 c
[1] = ac_llvm_extract_elem(&ctx
->ac
, input
, 1);
1361 c
[2] = ac_llvm_extract_elem(&ctx
->ac
, input
, 0);
1362 c
[3] = ac_llvm_extract_elem(&ctx
->ac
, input
, 3);
1364 input
= ac_build_gather_values(&ctx
->ac
, c
, 4);
1367 input
= radv_fixup_vertex_input_fetches(ctx
, input
, num_channels
,
1370 for (unsigned chan
= 0; chan
< 4; chan
++) {
1371 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
1372 output
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
, input
, llvm_chan
, "");
1373 if (type
== GLSL_TYPE_FLOAT16
) {
1374 output
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.f32
, "");
1375 output
[chan
] = LLVMBuildFPTrunc(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.f16
, "");
1379 unsigned alpha_adjust
= (ctx
->args
->options
->key
.vs
.alpha_adjust
>> (attrib_index
* 2)) & 3;
1380 output
[3] = adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, output
[3]);
1382 for (unsigned chan
= 0; chan
< 4; chan
++) {
1383 output
[chan
] = ac_to_integer(&ctx
->ac
, output
[chan
]);
1384 if (type
== GLSL_TYPE_UINT16
|| type
== GLSL_TYPE_INT16
)
1385 output
[chan
] = LLVMBuildTrunc(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.i16
, "");
1387 ctx
->inputs
[ac_llvm_reg_index_soa(variable
->data
.location
+ i
, chan
)] = output
[chan
];
1393 handle_vs_inputs(struct radv_shader_context
*ctx
,
1394 struct nir_shader
*nir
) {
1395 nir_foreach_variable(variable
, &nir
->inputs
)
1396 handle_vs_input_decl(ctx
, variable
);
1400 prepare_interp_optimize(struct radv_shader_context
*ctx
,
1401 struct nir_shader
*nir
)
1403 bool uses_center
= false;
1404 bool uses_centroid
= false;
1405 nir_foreach_variable(variable
, &nir
->inputs
) {
1406 if (glsl_get_base_type(glsl_without_array(variable
->type
)) != GLSL_TYPE_FLOAT
||
1407 variable
->data
.sample
)
1410 if (variable
->data
.centroid
)
1411 uses_centroid
= true;
1416 ctx
->abi
.persp_centroid
= ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.persp_centroid
);
1417 ctx
->abi
.linear_centroid
= ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.linear_centroid
);
1419 if (uses_center
&& uses_centroid
) {
1420 LLVMValueRef sel
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntSLT
,
1421 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.prim_mask
),
1423 ctx
->abi
.persp_centroid
=
1424 LLVMBuildSelect(ctx
->ac
.builder
, sel
,
1425 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.persp_center
),
1426 ctx
->abi
.persp_centroid
, "");
1427 ctx
->abi
.linear_centroid
=
1428 LLVMBuildSelect(ctx
->ac
.builder
, sel
,
1429 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.linear_center
),
1430 ctx
->abi
.linear_centroid
, "");
1435 scan_shader_output_decl(struct radv_shader_context
*ctx
,
1436 struct nir_variable
*variable
,
1437 struct nir_shader
*shader
,
1438 gl_shader_stage stage
)
1440 int idx
= variable
->data
.location
+ variable
->data
.index
;
1441 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
1442 uint64_t mask_attribs
;
1444 variable
->data
.driver_location
= idx
* 4;
1446 /* tess ctrl has it's own load/store paths for outputs */
1447 if (stage
== MESA_SHADER_TESS_CTRL
)
1450 if (variable
->data
.compact
) {
1451 unsigned component_count
= variable
->data
.location_frac
+
1452 glsl_get_length(variable
->type
);
1453 attrib_count
= (component_count
+ 3) / 4;
1456 mask_attribs
= ((1ull << attrib_count
) - 1) << idx
;
1458 ctx
->output_mask
|= mask_attribs
;
1462 /* Initialize arguments for the shader export intrinsic */
1464 si_llvm_init_export_args(struct radv_shader_context
*ctx
,
1465 LLVMValueRef
*values
,
1466 unsigned enabled_channels
,
1468 struct ac_export_args
*args
)
1470 /* Specify the channels that are enabled. */
1471 args
->enabled_channels
= enabled_channels
;
1473 /* Specify whether the EXEC mask represents the valid mask */
1474 args
->valid_mask
= 0;
1476 /* Specify whether this is the last export */
1479 /* Specify the target we are exporting */
1480 args
->target
= target
;
1482 args
->compr
= false;
1483 args
->out
[0] = LLVMGetUndef(ctx
->ac
.f32
);
1484 args
->out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
1485 args
->out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
1486 args
->out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
1491 bool is_16bit
= ac_get_type_size(LLVMTypeOf(values
[0])) == 2;
1492 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1493 unsigned index
= target
- V_008DFC_SQ_EXP_MRT
;
1494 unsigned col_format
= (ctx
->args
->options
->key
.fs
.col_format
>> (4 * index
)) & 0xf;
1495 bool is_int8
= (ctx
->args
->options
->key
.fs
.is_int8
>> index
) & 1;
1496 bool is_int10
= (ctx
->args
->options
->key
.fs
.is_int10
>> index
) & 1;
1499 LLVMValueRef (*packf
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2]) = NULL
;
1500 LLVMValueRef (*packi
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2],
1501 unsigned bits
, bool hi
) = NULL
;
1503 switch(col_format
) {
1504 case V_028714_SPI_SHADER_ZERO
:
1505 args
->enabled_channels
= 0; /* writemask */
1506 args
->target
= V_008DFC_SQ_EXP_NULL
;
1509 case V_028714_SPI_SHADER_32_R
:
1510 args
->enabled_channels
= 1;
1511 args
->out
[0] = values
[0];
1514 case V_028714_SPI_SHADER_32_GR
:
1515 args
->enabled_channels
= 0x3;
1516 args
->out
[0] = values
[0];
1517 args
->out
[1] = values
[1];
1520 case V_028714_SPI_SHADER_32_AR
:
1521 if (ctx
->ac
.chip_class
>= GFX10
) {
1522 args
->enabled_channels
= 0x3;
1523 args
->out
[0] = values
[0];
1524 args
->out
[1] = values
[3];
1526 args
->enabled_channels
= 0x9;
1527 args
->out
[0] = values
[0];
1528 args
->out
[3] = values
[3];
1532 case V_028714_SPI_SHADER_FP16_ABGR
:
1533 args
->enabled_channels
= 0x5;
1534 packf
= ac_build_cvt_pkrtz_f16
;
1536 for (unsigned chan
= 0; chan
< 4; chan
++)
1537 values
[chan
] = LLVMBuildFPExt(ctx
->ac
.builder
,
1543 case V_028714_SPI_SHADER_UNORM16_ABGR
:
1544 args
->enabled_channels
= 0x5;
1545 packf
= ac_build_cvt_pknorm_u16
;
1548 case V_028714_SPI_SHADER_SNORM16_ABGR
:
1549 args
->enabled_channels
= 0x5;
1550 packf
= ac_build_cvt_pknorm_i16
;
1553 case V_028714_SPI_SHADER_UINT16_ABGR
:
1554 args
->enabled_channels
= 0x5;
1555 packi
= ac_build_cvt_pk_u16
;
1557 for (unsigned chan
= 0; chan
< 4; chan
++)
1558 values
[chan
] = LLVMBuildZExt(ctx
->ac
.builder
,
1559 ac_to_integer(&ctx
->ac
, values
[chan
]),
1564 case V_028714_SPI_SHADER_SINT16_ABGR
:
1565 args
->enabled_channels
= 0x5;
1566 packi
= ac_build_cvt_pk_i16
;
1568 for (unsigned chan
= 0; chan
< 4; chan
++)
1569 values
[chan
] = LLVMBuildSExt(ctx
->ac
.builder
,
1570 ac_to_integer(&ctx
->ac
, values
[chan
]),
1576 case V_028714_SPI_SHADER_32_ABGR
:
1577 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
1581 /* Pack f16 or norm_i16/u16. */
1583 for (chan
= 0; chan
< 2; chan
++) {
1584 LLVMValueRef pack_args
[2] = {
1586 values
[2 * chan
+ 1]
1588 LLVMValueRef packed
;
1590 packed
= packf(&ctx
->ac
, pack_args
);
1591 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
1593 args
->compr
= 1; /* COMPR flag */
1598 for (chan
= 0; chan
< 2; chan
++) {
1599 LLVMValueRef pack_args
[2] = {
1600 ac_to_integer(&ctx
->ac
, values
[2 * chan
]),
1601 ac_to_integer(&ctx
->ac
, values
[2 * chan
+ 1])
1603 LLVMValueRef packed
;
1605 packed
= packi(&ctx
->ac
, pack_args
,
1606 is_int8
? 8 : is_int10
? 10 : 16,
1608 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
1610 args
->compr
= 1; /* COMPR flag */
1616 for (unsigned chan
= 0; chan
< 4; chan
++) {
1617 values
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, values
[chan
], ctx
->ac
.i16
, "");
1618 args
->out
[chan
] = LLVMBuildZExt(ctx
->ac
.builder
, values
[chan
], ctx
->ac
.i32
, "");
1621 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
1623 for (unsigned i
= 0; i
< 4; ++i
)
1624 args
->out
[i
] = ac_to_float(&ctx
->ac
, args
->out
[i
]);
1628 radv_export_param(struct radv_shader_context
*ctx
, unsigned index
,
1629 LLVMValueRef
*values
, unsigned enabled_channels
)
1631 struct ac_export_args args
;
1633 si_llvm_init_export_args(ctx
, values
, enabled_channels
,
1634 V_008DFC_SQ_EXP_PARAM
+ index
, &args
);
1635 ac_build_export(&ctx
->ac
, &args
);
1639 radv_load_output(struct radv_shader_context
*ctx
, unsigned index
, unsigned chan
)
1641 LLVMValueRef output
= ctx
->abi
.outputs
[ac_llvm_reg_index_soa(index
, chan
)];
1642 return LLVMBuildLoad(ctx
->ac
.builder
, output
, "");
1646 radv_emit_stream_output(struct radv_shader_context
*ctx
,
1647 LLVMValueRef
const *so_buffers
,
1648 LLVMValueRef
const *so_write_offsets
,
1649 const struct radv_stream_output
*output
,
1650 struct radv_shader_output_values
*shader_out
)
1652 unsigned num_comps
= util_bitcount(output
->component_mask
);
1653 unsigned buf
= output
->buffer
;
1654 unsigned offset
= output
->offset
;
1656 LLVMValueRef out
[4];
1658 assert(num_comps
&& num_comps
<= 4);
1659 if (!num_comps
|| num_comps
> 4)
1662 /* Get the first component. */
1663 start
= ffs(output
->component_mask
) - 1;
1665 /* Load the output as int. */
1666 for (int i
= 0; i
< num_comps
; i
++) {
1667 out
[i
] = ac_to_integer(&ctx
->ac
, shader_out
->values
[start
+ i
]);
1670 /* Pack the output. */
1671 LLVMValueRef vdata
= NULL
;
1673 switch (num_comps
) {
1674 case 1: /* as i32 */
1677 case 2: /* as v2i32 */
1678 case 3: /* as v4i32 (aligned to 4) */
1679 out
[3] = LLVMGetUndef(ctx
->ac
.i32
);
1681 case 4: /* as v4i32 */
1682 vdata
= ac_build_gather_values(&ctx
->ac
, out
,
1683 !ac_has_vec3_support(ctx
->ac
.chip_class
, false) ?
1684 util_next_power_of_two(num_comps
) :
1689 ac_build_buffer_store_dword(&ctx
->ac
, so_buffers
[buf
],
1690 vdata
, num_comps
, so_write_offsets
[buf
],
1691 ctx
->ac
.i32_0
, offset
,
1696 radv_emit_streamout(struct radv_shader_context
*ctx
, unsigned stream
)
1700 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1701 assert(ctx
->args
->streamout_config
.used
);
1702 LLVMValueRef so_vtx_count
=
1703 ac_build_bfe(&ctx
->ac
,
1704 ac_get_arg(&ctx
->ac
, ctx
->args
->streamout_config
),
1705 LLVMConstInt(ctx
->ac
.i32
, 16, false),
1706 LLVMConstInt(ctx
->ac
.i32
, 7, false), false);
1708 LLVMValueRef tid
= ac_get_thread_id(&ctx
->ac
);
1710 /* can_emit = tid < so_vtx_count; */
1711 LLVMValueRef can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
,
1712 tid
, so_vtx_count
, "");
1714 /* Emit the streamout code conditionally. This actually avoids
1715 * out-of-bounds buffer access. The hw tells us via the SGPR
1716 * (so_vtx_count) which threads are allowed to emit streamout data.
1718 ac_build_ifcc(&ctx
->ac
, can_emit
, 6501);
1720 /* The buffer offset is computed as follows:
1721 * ByteOffset = streamout_offset[buffer_id]*4 +
1722 * (streamout_write_index + thread_id)*stride[buffer_id] +
1725 LLVMValueRef so_write_index
=
1726 ac_get_arg(&ctx
->ac
, ctx
->args
->streamout_write_idx
);
1728 /* Compute (streamout_write_index + thread_id). */
1730 LLVMBuildAdd(ctx
->ac
.builder
, so_write_index
, tid
, "");
1732 /* Load the descriptor and compute the write offset for each
1735 LLVMValueRef so_write_offset
[4] = {};
1736 LLVMValueRef so_buffers
[4] = {};
1737 LLVMValueRef buf_ptr
= ac_get_arg(&ctx
->ac
, ctx
->args
->streamout_buffers
);
1739 for (i
= 0; i
< 4; i
++) {
1740 uint16_t stride
= ctx
->args
->shader_info
->so
.strides
[i
];
1745 LLVMValueRef offset
=
1746 LLVMConstInt(ctx
->ac
.i32
, i
, false);
1748 so_buffers
[i
] = ac_build_load_to_sgpr(&ctx
->ac
,
1751 LLVMValueRef so_offset
=
1752 ac_get_arg(&ctx
->ac
, ctx
->args
->streamout_offset
[i
]);
1754 so_offset
= LLVMBuildMul(ctx
->ac
.builder
, so_offset
,
1755 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
1757 so_write_offset
[i
] =
1758 ac_build_imad(&ctx
->ac
, so_write_index
,
1759 LLVMConstInt(ctx
->ac
.i32
,
1764 /* Write streamout data. */
1765 for (i
= 0; i
< ctx
->args
->shader_info
->so
.num_outputs
; i
++) {
1766 struct radv_shader_output_values shader_out
= {};
1767 struct radv_stream_output
*output
=
1768 &ctx
->args
->shader_info
->so
.outputs
[i
];
1770 if (stream
!= output
->stream
)
1773 for (int j
= 0; j
< 4; j
++) {
1774 shader_out
.values
[j
] =
1775 radv_load_output(ctx
, output
->location
, j
);
1778 radv_emit_stream_output(ctx
, so_buffers
,so_write_offset
,
1779 output
, &shader_out
);
1782 ac_build_endif(&ctx
->ac
, 6501);
1786 radv_build_param_exports(struct radv_shader_context
*ctx
,
1787 struct radv_shader_output_values
*outputs
,
1789 struct radv_vs_output_info
*outinfo
,
1790 bool export_clip_dists
)
1792 unsigned param_count
= 0;
1794 for (unsigned i
= 0; i
< noutput
; i
++) {
1795 unsigned slot_name
= outputs
[i
].slot_name
;
1796 unsigned usage_mask
= outputs
[i
].usage_mask
;
1798 if (slot_name
!= VARYING_SLOT_LAYER
&&
1799 slot_name
!= VARYING_SLOT_PRIMITIVE_ID
&&
1800 slot_name
!= VARYING_SLOT_CLIP_DIST0
&&
1801 slot_name
!= VARYING_SLOT_CLIP_DIST1
&&
1802 slot_name
< VARYING_SLOT_VAR0
)
1805 if ((slot_name
== VARYING_SLOT_CLIP_DIST0
||
1806 slot_name
== VARYING_SLOT_CLIP_DIST1
) && !export_clip_dists
)
1809 radv_export_param(ctx
, param_count
, outputs
[i
].values
, usage_mask
);
1811 assert(i
< ARRAY_SIZE(outinfo
->vs_output_param_offset
));
1812 outinfo
->vs_output_param_offset
[slot_name
] = param_count
++;
1815 outinfo
->param_exports
= param_count
;
1818 /* Generate export instructions for hardware VS shader stage or NGG GS stage
1819 * (position and parameter data only).
1822 radv_llvm_export_vs(struct radv_shader_context
*ctx
,
1823 struct radv_shader_output_values
*outputs
,
1825 struct radv_vs_output_info
*outinfo
,
1826 bool export_clip_dists
)
1828 LLVMValueRef psize_value
= NULL
, layer_value
= NULL
, viewport_value
= NULL
;
1829 struct ac_export_args pos_args
[4] = {};
1830 unsigned pos_idx
, index
;
1833 /* Build position exports */
1834 for (i
= 0; i
< noutput
; i
++) {
1835 switch (outputs
[i
].slot_name
) {
1836 case VARYING_SLOT_POS
:
1837 si_llvm_init_export_args(ctx
, outputs
[i
].values
, 0xf,
1838 V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
1840 case VARYING_SLOT_PSIZ
:
1841 psize_value
= outputs
[i
].values
[0];
1843 case VARYING_SLOT_LAYER
:
1844 layer_value
= outputs
[i
].values
[0];
1846 case VARYING_SLOT_VIEWPORT
:
1847 viewport_value
= outputs
[i
].values
[0];
1849 case VARYING_SLOT_CLIP_DIST0
:
1850 case VARYING_SLOT_CLIP_DIST1
:
1851 index
= 2 + outputs
[i
].slot_index
;
1852 si_llvm_init_export_args(ctx
, outputs
[i
].values
, 0xf,
1853 V_008DFC_SQ_EXP_POS
+ index
,
1861 /* We need to add the position output manually if it's missing. */
1862 if (!pos_args
[0].out
[0]) {
1863 pos_args
[0].enabled_channels
= 0xf; /* writemask */
1864 pos_args
[0].valid_mask
= 0; /* EXEC mask */
1865 pos_args
[0].done
= 0; /* last export? */
1866 pos_args
[0].target
= V_008DFC_SQ_EXP_POS
;
1867 pos_args
[0].compr
= 0; /* COMPR flag */
1868 pos_args
[0].out
[0] = ctx
->ac
.f32_0
; /* X */
1869 pos_args
[0].out
[1] = ctx
->ac
.f32_0
; /* Y */
1870 pos_args
[0].out
[2] = ctx
->ac
.f32_0
; /* Z */
1871 pos_args
[0].out
[3] = ctx
->ac
.f32_1
; /* W */
1874 if (outinfo
->writes_pointsize
||
1875 outinfo
->writes_layer
||
1876 outinfo
->writes_viewport_index
) {
1877 pos_args
[1].enabled_channels
= ((outinfo
->writes_pointsize
== true ? 1 : 0) |
1878 (outinfo
->writes_layer
== true ? 4 : 0));
1879 pos_args
[1].valid_mask
= 0;
1880 pos_args
[1].done
= 0;
1881 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
1882 pos_args
[1].compr
= 0;
1883 pos_args
[1].out
[0] = ctx
->ac
.f32_0
; /* X */
1884 pos_args
[1].out
[1] = ctx
->ac
.f32_0
; /* Y */
1885 pos_args
[1].out
[2] = ctx
->ac
.f32_0
; /* Z */
1886 pos_args
[1].out
[3] = ctx
->ac
.f32_0
; /* W */
1888 if (outinfo
->writes_pointsize
== true)
1889 pos_args
[1].out
[0] = psize_value
;
1890 if (outinfo
->writes_layer
== true)
1891 pos_args
[1].out
[2] = layer_value
;
1892 if (outinfo
->writes_viewport_index
== true) {
1893 if (ctx
->args
->options
->chip_class
>= GFX9
) {
1894 /* GFX9 has the layer in out.z[10:0] and the viewport
1895 * index in out.z[19:16].
1897 LLVMValueRef v
= viewport_value
;
1898 v
= ac_to_integer(&ctx
->ac
, v
);
1899 v
= LLVMBuildShl(ctx
->ac
.builder
, v
,
1900 LLVMConstInt(ctx
->ac
.i32
, 16, false),
1902 v
= LLVMBuildOr(ctx
->ac
.builder
, v
,
1903 ac_to_integer(&ctx
->ac
, pos_args
[1].out
[2]), "");
1905 pos_args
[1].out
[2] = ac_to_float(&ctx
->ac
, v
);
1906 pos_args
[1].enabled_channels
|= 1 << 2;
1908 pos_args
[1].out
[3] = viewport_value
;
1909 pos_args
[1].enabled_channels
|= 1 << 3;
1914 for (i
= 0; i
< 4; i
++) {
1915 if (pos_args
[i
].out
[0])
1916 outinfo
->pos_exports
++;
1919 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
1920 * Setting valid_mask=1 prevents it and has no other effect.
1922 if (ctx
->ac
.family
== CHIP_NAVI10
||
1923 ctx
->ac
.family
== CHIP_NAVI12
||
1924 ctx
->ac
.family
== CHIP_NAVI14
)
1925 pos_args
[0].valid_mask
= 1;
1928 for (i
= 0; i
< 4; i
++) {
1929 if (!pos_args
[i
].out
[0])
1932 /* Specify the target we are exporting */
1933 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
1935 if (pos_idx
== outinfo
->pos_exports
)
1936 /* Specify that this is the last export */
1937 pos_args
[i
].done
= 1;
1939 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
1942 /* Build parameter exports */
1943 radv_build_param_exports(ctx
, outputs
, noutput
, outinfo
, export_clip_dists
);
1947 handle_vs_outputs_post(struct radv_shader_context
*ctx
,
1948 bool export_prim_id
,
1949 bool export_clip_dists
,
1950 struct radv_vs_output_info
*outinfo
)
1952 struct radv_shader_output_values
*outputs
;
1953 unsigned noutput
= 0;
1955 if (ctx
->args
->options
->key
.has_multiview_view_index
) {
1956 LLVMValueRef
* tmp_out
= &ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
1958 for(unsigned i
= 0; i
< 4; ++i
)
1959 ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, i
)] =
1960 ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
1963 LLVMValueRef view_index
= ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.view_index
);
1964 LLVMBuildStore(ctx
->ac
.builder
, ac_to_float(&ctx
->ac
, view_index
), *tmp_out
);
1965 ctx
->output_mask
|= 1ull << VARYING_SLOT_LAYER
;
1968 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
1969 sizeof(outinfo
->vs_output_param_offset
));
1970 outinfo
->pos_exports
= 0;
1972 if (!ctx
->args
->options
->use_ngg_streamout
&&
1973 ctx
->args
->shader_info
->so
.num_outputs
&&
1974 !ctx
->args
->is_gs_copy_shader
) {
1975 /* The GS copy shader emission already emits streamout. */
1976 radv_emit_streamout(ctx
, 0);
1979 /* Allocate a temporary array for the output values. */
1980 unsigned num_outputs
= util_bitcount64(ctx
->output_mask
) + export_prim_id
;
1981 outputs
= malloc(num_outputs
* sizeof(outputs
[0]));
1983 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
1984 if (!(ctx
->output_mask
& (1ull << i
)))
1987 outputs
[noutput
].slot_name
= i
;
1988 outputs
[noutput
].slot_index
= i
== VARYING_SLOT_CLIP_DIST1
;
1990 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
1991 !ctx
->args
->is_gs_copy_shader
) {
1992 outputs
[noutput
].usage_mask
=
1993 ctx
->args
->shader_info
->vs
.output_usage_mask
[i
];
1994 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
1995 outputs
[noutput
].usage_mask
=
1996 ctx
->args
->shader_info
->tes
.output_usage_mask
[i
];
1998 assert(ctx
->args
->is_gs_copy_shader
);
1999 outputs
[noutput
].usage_mask
=
2000 ctx
->args
->shader_info
->gs
.output_usage_mask
[i
];
2003 for (unsigned j
= 0; j
< 4; j
++) {
2004 outputs
[noutput
].values
[j
] =
2005 ac_to_float(&ctx
->ac
, radv_load_output(ctx
, i
, j
));
2011 /* Export PrimitiveID. */
2012 if (export_prim_id
) {
2013 outputs
[noutput
].slot_name
= VARYING_SLOT_PRIMITIVE_ID
;
2014 outputs
[noutput
].slot_index
= 0;
2015 outputs
[noutput
].usage_mask
= 0x1;
2016 outputs
[noutput
].values
[0] =
2017 ac_get_arg(&ctx
->ac
, ctx
->args
->vs_prim_id
);
2018 for (unsigned j
= 1; j
< 4; j
++)
2019 outputs
[noutput
].values
[j
] = ctx
->ac
.f32_0
;
2023 radv_llvm_export_vs(ctx
, outputs
, noutput
, outinfo
, export_clip_dists
);
2029 handle_es_outputs_post(struct radv_shader_context
*ctx
,
2030 struct radv_es_output_info
*outinfo
)
2033 LLVMValueRef lds_base
= NULL
;
2035 if (ctx
->ac
.chip_class
>= GFX9
) {
2036 unsigned itemsize_dw
= outinfo
->esgs_itemsize
/ 4;
2037 LLVMValueRef vertex_idx
= ac_get_thread_id(&ctx
->ac
);
2038 LLVMValueRef wave_idx
=
2039 ac_unpack_param(&ctx
->ac
,
2040 ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
), 24, 4);
2041 vertex_idx
= LLVMBuildOr(ctx
->ac
.builder
, vertex_idx
,
2042 LLVMBuildMul(ctx
->ac
.builder
, wave_idx
,
2043 LLVMConstInt(ctx
->ac
.i32
,
2044 ctx
->ac
.wave_size
, false), ""), "");
2045 lds_base
= LLVMBuildMul(ctx
->ac
.builder
, vertex_idx
,
2046 LLVMConstInt(ctx
->ac
.i32
, itemsize_dw
, 0), "");
2049 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2050 LLVMValueRef dw_addr
= NULL
;
2051 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
2052 unsigned output_usage_mask
;
2055 if (!(ctx
->output_mask
& (1ull << i
)))
2058 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2060 ctx
->args
->shader_info
->vs
.output_usage_mask
[i
];
2062 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
2064 ctx
->args
->shader_info
->tes
.output_usage_mask
[i
];
2067 param_index
= shader_io_get_unique_index(i
);
2070 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
2071 LLVMConstInt(ctx
->ac
.i32
, param_index
* 4, false),
2075 for (j
= 0; j
< 4; j
++) {
2076 if (!(output_usage_mask
& (1 << j
)))
2079 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
2080 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
2081 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
2083 if (ctx
->ac
.chip_class
>= GFX9
) {
2084 LLVMValueRef dw_addr_offset
=
2085 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2086 LLVMConstInt(ctx
->ac
.i32
,
2089 ac_lds_store(&ctx
->ac
, dw_addr_offset
, out_val
);
2091 ac_build_buffer_store_dword(&ctx
->ac
,
2095 ac_get_arg(&ctx
->ac
, ctx
->args
->es2gs_offset
),
2096 (4 * param_index
+ j
) * 4,
2097 ac_glc
| ac_slc
| ac_swizzled
);
2104 handle_ls_outputs_post(struct radv_shader_context
*ctx
)
2106 LLVMValueRef vertex_id
= ctx
->rel_auto_id
;
2107 uint32_t num_tcs_inputs
= util_last_bit64(ctx
->args
->shader_info
->vs
.ls_outputs_written
);
2108 LLVMValueRef vertex_dw_stride
= LLVMConstInt(ctx
->ac
.i32
, num_tcs_inputs
* 4, false);
2109 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->ac
.builder
, vertex_id
,
2110 vertex_dw_stride
, "");
2112 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2113 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
2115 if (!(ctx
->output_mask
& (1ull << i
)))
2118 int param
= shader_io_get_unique_index(i
);
2119 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_dw_addr
,
2120 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false),
2122 for (unsigned j
= 0; j
< 4; j
++) {
2123 LLVMValueRef value
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
2124 value
= ac_to_integer(&ctx
->ac
, value
);
2125 value
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
2126 ac_lds_store(&ctx
->ac
, dw_addr
, value
);
2127 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
, ctx
->ac
.i32_1
, "");
2132 static LLVMValueRef
get_wave_id_in_tg(struct radv_shader_context
*ctx
)
2134 return ac_unpack_param(&ctx
->ac
,
2135 ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
), 24, 4);
2138 static LLVMValueRef
get_tgsize(struct radv_shader_context
*ctx
)
2140 return ac_unpack_param(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
), 28, 4);
2143 static LLVMValueRef
get_thread_id_in_tg(struct radv_shader_context
*ctx
)
2145 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2147 tmp
= LLVMBuildMul(builder
, get_wave_id_in_tg(ctx
),
2148 LLVMConstInt(ctx
->ac
.i32
, ctx
->ac
.wave_size
, false), "");
2149 return LLVMBuildAdd(builder
, tmp
, ac_get_thread_id(&ctx
->ac
), "");
2152 static LLVMValueRef
ngg_get_vtx_cnt(struct radv_shader_context
*ctx
)
2154 return ac_build_bfe(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->gs_tg_info
),
2155 LLVMConstInt(ctx
->ac
.i32
, 12, false),
2156 LLVMConstInt(ctx
->ac
.i32
, 9, false),
2160 static LLVMValueRef
ngg_get_prim_cnt(struct radv_shader_context
*ctx
)
2162 return ac_build_bfe(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->gs_tg_info
),
2163 LLVMConstInt(ctx
->ac
.i32
, 22, false),
2164 LLVMConstInt(ctx
->ac
.i32
, 9, false),
2168 static LLVMValueRef
ngg_get_ordered_id(struct radv_shader_context
*ctx
)
2170 return ac_build_bfe(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->gs_tg_info
),
2172 LLVMConstInt(ctx
->ac
.i32
, 12, false),
2177 ngg_gs_get_vertex_storage(struct radv_shader_context
*ctx
)
2179 unsigned num_outputs
= util_bitcount64(ctx
->output_mask
);
2181 if (ctx
->args
->options
->key
.has_multiview_view_index
)
2184 LLVMTypeRef elements
[2] = {
2185 LLVMArrayType(ctx
->ac
.i32
, 4 * num_outputs
),
2186 LLVMArrayType(ctx
->ac
.i8
, 4),
2188 LLVMTypeRef type
= LLVMStructTypeInContext(ctx
->ac
.context
, elements
, 2, false);
2189 type
= LLVMPointerType(LLVMArrayType(type
, 0), AC_ADDR_SPACE_LDS
);
2190 return LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->gs_ngg_emit
, type
, "");
2194 * Return a pointer to the LDS storage reserved for the N'th vertex, where N
2195 * is in emit order; that is:
2196 * - during the epilogue, N is the threadidx (relative to the entire threadgroup)
2197 * - during vertex emit, i.e. while the API GS shader invocation is running,
2198 * N = threadidx * gs_max_out_vertices + emitidx
2200 * Goals of the LDS memory layout:
2201 * 1. Eliminate bank conflicts on write for geometry shaders that have all emits
2202 * in uniform control flow
2203 * 2. Eliminate bank conflicts on read for export if, additionally, there is no
2205 * 3. Agnostic to the number of waves (since we don't know it before compiling)
2206 * 4. Allow coalescing of LDS instructions (ds_write_b128 etc.)
2207 * 5. Avoid wasting memory.
2209 * We use an AoS layout due to point 4 (this also helps point 3). In an AoS
2210 * layout, elimination of bank conflicts requires that each vertex occupy an
2211 * odd number of dwords. We use the additional dword to store the output stream
2212 * index as well as a flag to indicate whether this vertex ends a primitive
2213 * for rasterization.
2215 * Swizzling is required to satisfy points 1 and 2 simultaneously.
2217 * Vertices are stored in export order (gsthread * gs_max_out_vertices + emitidx).
2218 * Indices are swizzled in groups of 32, which ensures point 1 without
2219 * disturbing point 2.
2221 * \return an LDS pointer to type {[N x i32], [4 x i8]}
2224 ngg_gs_vertex_ptr(struct radv_shader_context
*ctx
, LLVMValueRef vertexidx
)
2226 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2227 LLVMValueRef storage
= ngg_gs_get_vertex_storage(ctx
);
2229 /* gs_max_out_vertices = 2^(write_stride_2exp) * some odd number */
2230 unsigned write_stride_2exp
= ffs(ctx
->shader
->info
.gs
.vertices_out
) - 1;
2231 if (write_stride_2exp
) {
2233 LLVMBuildLShr(builder
, vertexidx
,
2234 LLVMConstInt(ctx
->ac
.i32
, 5, false), "");
2235 LLVMValueRef swizzle
=
2236 LLVMBuildAnd(builder
, row
,
2237 LLVMConstInt(ctx
->ac
.i32
, (1u << write_stride_2exp
) - 1,
2239 vertexidx
= LLVMBuildXor(builder
, vertexidx
, swizzle
, "");
2242 return ac_build_gep0(&ctx
->ac
, storage
, vertexidx
);
2246 ngg_gs_emit_vertex_ptr(struct radv_shader_context
*ctx
, LLVMValueRef gsthread
,
2247 LLVMValueRef emitidx
)
2249 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2252 tmp
= LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.gs
.vertices_out
, false);
2253 tmp
= LLVMBuildMul(builder
, tmp
, gsthread
, "");
2254 const LLVMValueRef vertexidx
= LLVMBuildAdd(builder
, tmp
, emitidx
, "");
2255 return ngg_gs_vertex_ptr(ctx
, vertexidx
);
2259 ngg_gs_get_emit_output_ptr(struct radv_shader_context
*ctx
, LLVMValueRef vertexptr
,
2262 LLVMValueRef gep_idx
[3] = {
2263 ctx
->ac
.i32_0
, /* implied C-style array */
2264 ctx
->ac
.i32_0
, /* first struct entry */
2265 LLVMConstInt(ctx
->ac
.i32
, out_idx
, false),
2267 return LLVMBuildGEP(ctx
->ac
.builder
, vertexptr
, gep_idx
, 3, "");
2271 ngg_gs_get_emit_primflag_ptr(struct radv_shader_context
*ctx
, LLVMValueRef vertexptr
,
2274 LLVMValueRef gep_idx
[3] = {
2275 ctx
->ac
.i32_0
, /* implied C-style array */
2276 ctx
->ac
.i32_1
, /* second struct entry */
2277 LLVMConstInt(ctx
->ac
.i32
, stream
, false),
2279 return LLVMBuildGEP(ctx
->ac
.builder
, vertexptr
, gep_idx
, 3, "");
2282 static struct radv_stream_output
*
2283 radv_get_stream_output_by_loc(struct radv_streamout_info
*so
, unsigned location
)
2285 for (unsigned i
= 0; i
< so
->num_outputs
; ++i
) {
2286 if (so
->outputs
[i
].location
== location
)
2287 return &so
->outputs
[i
];
2293 static void build_streamout_vertex(struct radv_shader_context
*ctx
,
2294 LLVMValueRef
*so_buffer
, LLVMValueRef
*wg_offset_dw
,
2295 unsigned stream
, LLVMValueRef offset_vtx
,
2296 LLVMValueRef vertexptr
)
2298 struct radv_streamout_info
*so
= &ctx
->args
->shader_info
->so
;
2299 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2300 LLVMValueRef offset
[4] = {};
2303 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
2304 if (!wg_offset_dw
[buffer
])
2307 tmp
= LLVMBuildMul(builder
, offset_vtx
,
2308 LLVMConstInt(ctx
->ac
.i32
, so
->strides
[buffer
], false), "");
2309 tmp
= LLVMBuildAdd(builder
, wg_offset_dw
[buffer
], tmp
, "");
2310 offset
[buffer
] = LLVMBuildShl(builder
, tmp
, LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
2313 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
2314 struct radv_shader_output_values outputs
[AC_LLVM_MAX_OUTPUTS
];
2315 unsigned noutput
= 0;
2316 unsigned out_idx
= 0;
2318 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2319 unsigned output_usage_mask
=
2320 ctx
->args
->shader_info
->gs
.output_usage_mask
[i
];
2321 uint8_t output_stream
=
2322 output_stream
= ctx
->args
->shader_info
->gs
.output_streams
[i
];
2324 if (!(ctx
->output_mask
& (1ull << i
)) ||
2325 output_stream
!= stream
)
2328 outputs
[noutput
].slot_name
= i
;
2329 outputs
[noutput
].slot_index
= i
== VARYING_SLOT_CLIP_DIST1
;
2330 outputs
[noutput
].usage_mask
= output_usage_mask
;
2332 int length
= util_last_bit(output_usage_mask
);
2334 for (unsigned j
= 0; j
< length
; j
++, out_idx
++) {
2335 if (!(output_usage_mask
& (1 << j
)))
2338 tmp
= ac_build_gep0(&ctx
->ac
, vertexptr
,
2339 LLVMConstInt(ctx
->ac
.i32
, out_idx
, false));
2340 outputs
[noutput
].values
[j
] = LLVMBuildLoad(builder
, tmp
, "");
2343 for (unsigned j
= length
; j
< 4; j
++)
2344 outputs
[noutput
].values
[j
] = LLVMGetUndef(ctx
->ac
.f32
);
2349 for (unsigned i
= 0; i
< noutput
; i
++) {
2350 struct radv_stream_output
*output
=
2351 radv_get_stream_output_by_loc(so
, outputs
[i
].slot_name
);
2354 output
->stream
!= stream
)
2357 struct radv_shader_output_values out
= {};
2359 for (unsigned j
= 0; j
< 4; j
++) {
2360 out
.values
[j
] = outputs
[i
].values
[j
];
2363 radv_emit_stream_output(ctx
, so_buffer
, offset
, output
, &out
);
2366 for (unsigned i
= 0; i
< so
->num_outputs
; ++i
) {
2367 struct radv_stream_output
*output
=
2368 &ctx
->args
->shader_info
->so
.outputs
[i
];
2370 if (stream
!= output
->stream
)
2373 struct radv_shader_output_values out
= {};
2375 for (unsigned comp
= 0; comp
< 4; comp
++) {
2376 if (!(output
->component_mask
& (1 << comp
)))
2379 tmp
= ac_build_gep0(&ctx
->ac
, vertexptr
,
2380 LLVMConstInt(ctx
->ac
.i32
, 4 * i
+ comp
, false));
2381 out
.values
[comp
] = LLVMBuildLoad(builder
, tmp
, "");
2384 radv_emit_stream_output(ctx
, so_buffer
, offset
, output
, &out
);
2389 struct ngg_streamout
{
2390 LLVMValueRef num_vertices
;
2392 /* per-thread data */
2393 LLVMValueRef prim_enable
[4]; /* i1 per stream */
2394 LLVMValueRef vertices
[3]; /* [N x i32] addrspace(LDS)* */
2397 LLVMValueRef emit
[4]; /* per-stream emitted primitives (only valid for used streams) */
2401 * Build streamout logic.
2403 * Implies a barrier.
2405 * Writes number of emitted primitives to gs_ngg_scratch[4:7].
2407 * Clobbers gs_ngg_scratch[8:].
2409 static void build_streamout(struct radv_shader_context
*ctx
,
2410 struct ngg_streamout
*nggso
)
2412 struct radv_streamout_info
*so
= &ctx
->args
->shader_info
->so
;
2413 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2414 LLVMValueRef buf_ptr
= ac_get_arg(&ctx
->ac
, ctx
->args
->streamout_buffers
);
2415 LLVMValueRef tid
= get_thread_id_in_tg(ctx
);
2416 LLVMValueRef cond
, tmp
, tmp2
;
2417 LLVMValueRef i32_2
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
2418 LLVMValueRef i32_4
= LLVMConstInt(ctx
->ac
.i32
, 4, false);
2419 LLVMValueRef i32_8
= LLVMConstInt(ctx
->ac
.i32
, 8, false);
2420 LLVMValueRef so_buffer
[4] = {};
2421 unsigned max_num_vertices
= 1 + (nggso
->vertices
[1] ? 1 : 0) +
2422 (nggso
->vertices
[2] ? 1 : 0);
2423 LLVMValueRef prim_stride_dw
[4] = {};
2424 LLVMValueRef prim_stride_dw_vgpr
= LLVMGetUndef(ctx
->ac
.i32
);
2425 int stream_for_buffer
[4] = { -1, -1, -1, -1 };
2426 unsigned bufmask_for_stream
[4] = {};
2427 bool isgs
= ctx
->stage
== MESA_SHADER_GEOMETRY
;
2428 unsigned scratch_emit_base
= isgs
? 4 : 0;
2429 LLVMValueRef scratch_emit_basev
= isgs
? i32_4
: ctx
->ac
.i32_0
;
2430 unsigned scratch_offset_base
= isgs
? 8 : 4;
2431 LLVMValueRef scratch_offset_basev
= isgs
? i32_8
: i32_4
;
2433 ac_llvm_add_target_dep_function_attr(ctx
->main_function
,
2434 "amdgpu-gds-size", 256);
2436 /* Determine the mapping of streamout buffers to vertex streams. */
2437 for (unsigned i
= 0; i
< so
->num_outputs
; ++i
) {
2438 unsigned buf
= so
->outputs
[i
].buffer
;
2439 unsigned stream
= so
->outputs
[i
].stream
;
2440 assert(stream_for_buffer
[buf
] < 0 || stream_for_buffer
[buf
] == stream
);
2441 stream_for_buffer
[buf
] = stream
;
2442 bufmask_for_stream
[stream
] |= 1 << buf
;
2445 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
2446 if (stream_for_buffer
[buffer
] == -1)
2449 assert(so
->strides
[buffer
]);
2451 LLVMValueRef stride_for_buffer
=
2452 LLVMConstInt(ctx
->ac
.i32
, so
->strides
[buffer
], false);
2453 prim_stride_dw
[buffer
] =
2454 LLVMBuildMul(builder
, stride_for_buffer
,
2455 nggso
->num_vertices
, "");
2456 prim_stride_dw_vgpr
= ac_build_writelane(
2457 &ctx
->ac
, prim_stride_dw_vgpr
, prim_stride_dw
[buffer
],
2458 LLVMConstInt(ctx
->ac
.i32
, buffer
, false));
2460 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, buffer
, false);
2461 so_buffer
[buffer
] = ac_build_load_to_sgpr(&ctx
->ac
, buf_ptr
,
2465 cond
= LLVMBuildICmp(builder
, LLVMIntEQ
, get_wave_id_in_tg(ctx
), ctx
->ac
.i32_0
, "");
2466 ac_build_ifcc(&ctx
->ac
, cond
, 5200);
2468 LLVMTypeRef gdsptr
= LLVMPointerType(ctx
->ac
.i32
, AC_ADDR_SPACE_GDS
);
2469 LLVMValueRef gdsbase
= LLVMBuildIntToPtr(builder
, ctx
->ac
.i32_0
, gdsptr
, "");
2471 /* Advance the streamout offsets in GDS. */
2472 LLVMValueRef offsets_vgpr
= ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.i32
, "");
2473 LLVMValueRef generated_by_stream_vgpr
= ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.i32
, "");
2475 cond
= LLVMBuildICmp(builder
, LLVMIntULT
, ac_get_thread_id(&ctx
->ac
), i32_4
, "");
2476 ac_build_ifcc(&ctx
->ac
, cond
, 5210);
2478 /* Fetch the number of generated primitives and store
2479 * it in GDS for later use.
2482 tmp
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, tid
);
2483 tmp
= LLVMBuildLoad(builder
, tmp
, "");
2485 tmp
= ac_build_writelane(&ctx
->ac
, ctx
->ac
.i32_0
,
2486 ngg_get_prim_cnt(ctx
), ctx
->ac
.i32_0
);
2488 LLVMBuildStore(builder
, tmp
, generated_by_stream_vgpr
);
2490 unsigned swizzle
[4];
2491 int unused_stream
= -1;
2492 for (unsigned stream
= 0; stream
< 4; ++stream
) {
2493 if (!ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
]) {
2494 unused_stream
= stream
;
2498 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
2499 if (stream_for_buffer
[buffer
] >= 0) {
2500 swizzle
[buffer
] = stream_for_buffer
[buffer
];
2502 assert(unused_stream
>= 0);
2503 swizzle
[buffer
] = unused_stream
;
2507 tmp
= ac_build_quad_swizzle(&ctx
->ac
, tmp
,
2508 swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2509 tmp
= LLVMBuildMul(builder
, tmp
, prim_stride_dw_vgpr
, "");
2511 LLVMValueRef args
[] = {
2512 LLVMBuildIntToPtr(builder
, ngg_get_ordered_id(ctx
), gdsptr
, ""),
2514 ctx
->ac
.i32_0
, // ordering
2515 ctx
->ac
.i32_0
, // scope
2516 ctx
->ac
.i1false
, // isVolatile
2517 LLVMConstInt(ctx
->ac
.i32
, 4 << 24, false), // OA index
2518 ctx
->ac
.i1true
, // wave release
2519 ctx
->ac
.i1true
, // wave done
2522 tmp
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.ds.ordered.add",
2523 ctx
->ac
.i32
, args
, ARRAY_SIZE(args
), 0);
2525 /* Keep offsets in a VGPR for quick retrieval via readlane by
2526 * the first wave for bounds checking, and also store in LDS
2527 * for retrieval by all waves later. */
2528 LLVMBuildStore(builder
, tmp
, offsets_vgpr
);
2530 tmp2
= LLVMBuildAdd(builder
, ac_get_thread_id(&ctx
->ac
),
2531 scratch_offset_basev
, "");
2532 tmp2
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, tmp2
);
2533 LLVMBuildStore(builder
, tmp
, tmp2
);
2535 ac_build_endif(&ctx
->ac
, 5210);
2537 /* Determine the max emit per buffer. This is done via the SALU, in part
2538 * because LLVM can't generate divide-by-multiply if we try to do this
2539 * via VALU with one lane per buffer.
2541 LLVMValueRef max_emit
[4] = {};
2542 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
2543 if (stream_for_buffer
[buffer
] == -1)
2546 /* Compute the streamout buffer size in DWORD. */
2547 LLVMValueRef bufsize_dw
=
2548 LLVMBuildLShr(builder
,
2549 LLVMBuildExtractElement(builder
, so_buffer
[buffer
], i32_2
, ""),
2552 /* Load the streamout buffer offset from GDS. */
2553 tmp
= LLVMBuildLoad(builder
, offsets_vgpr
, "");
2554 LLVMValueRef offset_dw
=
2555 ac_build_readlane(&ctx
->ac
, tmp
,
2556 LLVMConstInt(ctx
->ac
.i32
, buffer
, false));
2558 /* Compute the remaining size to emit. */
2559 LLVMValueRef remaining_dw
=
2560 LLVMBuildSub(builder
, bufsize_dw
, offset_dw
, "");
2561 tmp
= LLVMBuildUDiv(builder
, remaining_dw
,
2562 prim_stride_dw
[buffer
], "");
2564 cond
= LLVMBuildICmp(builder
, LLVMIntULT
,
2565 bufsize_dw
, offset_dw
, "");
2566 max_emit
[buffer
] = LLVMBuildSelect(builder
, cond
,
2567 ctx
->ac
.i32_0
, tmp
, "");
2570 /* Determine the number of emitted primitives per stream and fixup the
2571 * GDS counter if necessary.
2573 * This is complicated by the fact that a single stream can emit to
2574 * multiple buffers (but luckily not vice versa).
2576 LLVMValueRef emit_vgpr
= ctx
->ac
.i32_0
;
2578 for (unsigned stream
= 0; stream
< 4; ++stream
) {
2579 if (!ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
])
2582 /* Load the number of generated primitives from GDS and
2583 * determine that number for the given stream.
2585 tmp
= LLVMBuildLoad(builder
, generated_by_stream_vgpr
, "");
2586 LLVMValueRef generated
=
2587 ac_build_readlane(&ctx
->ac
, tmp
,
2588 LLVMConstInt(ctx
->ac
.i32
, stream
, false));
2591 /* Compute the number of emitted primitives. */
2592 LLVMValueRef emit
= generated
;
2593 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
2594 if (stream_for_buffer
[buffer
] == stream
)
2595 emit
= ac_build_umin(&ctx
->ac
, emit
, max_emit
[buffer
]);
2598 /* Store the number of emitted primitives for that
2601 emit_vgpr
= ac_build_writelane(&ctx
->ac
, emit_vgpr
, emit
,
2602 LLVMConstInt(ctx
->ac
.i32
, stream
, false));
2604 /* Fixup the offset using a plain GDS atomic if we overflowed. */
2605 cond
= LLVMBuildICmp(builder
, LLVMIntULT
, emit
, generated
, "");
2606 ac_build_ifcc(&ctx
->ac
, cond
, 5221); /* scalar branch */
2607 tmp
= LLVMBuildLShr(builder
,
2608 LLVMConstInt(ctx
->ac
.i32
, bufmask_for_stream
[stream
], false),
2609 ac_get_thread_id(&ctx
->ac
), "");
2610 tmp
= LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
2611 ac_build_ifcc(&ctx
->ac
, tmp
, 5222);
2613 tmp
= LLVMBuildSub(builder
, generated
, emit
, "");
2614 tmp
= LLVMBuildMul(builder
, tmp
, prim_stride_dw_vgpr
, "");
2615 tmp2
= LLVMBuildGEP(builder
, gdsbase
, &tid
, 1, "");
2616 LLVMBuildAtomicRMW(builder
, LLVMAtomicRMWBinOpSub
, tmp2
, tmp
,
2617 LLVMAtomicOrderingMonotonic
, false);
2619 ac_build_endif(&ctx
->ac
, 5222);
2620 ac_build_endif(&ctx
->ac
, 5221);
2623 /* Store the number of emitted primitives to LDS for later use. */
2624 cond
= LLVMBuildICmp(builder
, LLVMIntULT
, ac_get_thread_id(&ctx
->ac
), i32_4
, "");
2625 ac_build_ifcc(&ctx
->ac
, cond
, 5225);
2627 tmp
= LLVMBuildAdd(builder
, ac_get_thread_id(&ctx
->ac
),
2628 scratch_emit_basev
, "");
2629 tmp
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, tmp
);
2630 LLVMBuildStore(builder
, emit_vgpr
, tmp
);
2632 ac_build_endif(&ctx
->ac
, 5225);
2634 ac_build_endif(&ctx
->ac
, 5200);
2636 /* Determine the workgroup-relative per-thread / primitive offset into
2637 * the streamout buffers */
2638 struct ac_wg_scan primemit_scan
[4] = {};
2641 for (unsigned stream
= 0; stream
< 4; ++stream
) {
2642 if (!ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
])
2645 primemit_scan
[stream
].enable_exclusive
= true;
2646 primemit_scan
[stream
].op
= nir_op_iadd
;
2647 primemit_scan
[stream
].src
= nggso
->prim_enable
[stream
];
2648 primemit_scan
[stream
].scratch
=
2649 ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
,
2650 LLVMConstInt(ctx
->ac
.i32
, 12 + 8 * stream
, false));
2651 primemit_scan
[stream
].waveidx
= get_wave_id_in_tg(ctx
);
2652 primemit_scan
[stream
].numwaves
= get_tgsize(ctx
);
2653 primemit_scan
[stream
].maxwaves
= 8;
2654 ac_build_wg_scan_top(&ctx
->ac
, &primemit_scan
[stream
]);
2658 ac_build_s_barrier(&ctx
->ac
);
2660 /* Fetch the per-buffer offsets and per-stream emit counts in all waves. */
2661 LLVMValueRef wgoffset_dw
[4] = {};
2664 LLVMValueRef scratch_vgpr
;
2666 tmp
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, ac_get_thread_id(&ctx
->ac
));
2667 scratch_vgpr
= LLVMBuildLoad(builder
, tmp
, "");
2669 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
2670 if (stream_for_buffer
[buffer
] >= 0) {
2671 wgoffset_dw
[buffer
] = ac_build_readlane(
2672 &ctx
->ac
, scratch_vgpr
,
2673 LLVMConstInt(ctx
->ac
.i32
, scratch_offset_base
+ buffer
, false));
2677 for (unsigned stream
= 0; stream
< 4; ++stream
) {
2678 if (ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
]) {
2679 nggso
->emit
[stream
] = ac_build_readlane(
2680 &ctx
->ac
, scratch_vgpr
,
2681 LLVMConstInt(ctx
->ac
.i32
, scratch_emit_base
+ stream
, false));
2686 /* Write out primitive data */
2687 for (unsigned stream
= 0; stream
< 4; ++stream
) {
2688 if (!ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
])
2692 ac_build_wg_scan_bottom(&ctx
->ac
, &primemit_scan
[stream
]);
2694 primemit_scan
[stream
].result_exclusive
= tid
;
2697 cond
= LLVMBuildICmp(builder
, LLVMIntULT
,
2698 primemit_scan
[stream
].result_exclusive
,
2699 nggso
->emit
[stream
], "");
2700 cond
= LLVMBuildAnd(builder
, cond
, nggso
->prim_enable
[stream
], "");
2701 ac_build_ifcc(&ctx
->ac
, cond
, 5240);
2703 LLVMValueRef offset_vtx
=
2704 LLVMBuildMul(builder
, primemit_scan
[stream
].result_exclusive
,
2705 nggso
->num_vertices
, "");
2707 for (unsigned i
= 0; i
< max_num_vertices
; ++i
) {
2708 cond
= LLVMBuildICmp(builder
, LLVMIntULT
,
2709 LLVMConstInt(ctx
->ac
.i32
, i
, false),
2710 nggso
->num_vertices
, "");
2711 ac_build_ifcc(&ctx
->ac
, cond
, 5241);
2712 build_streamout_vertex(ctx
, so_buffer
, wgoffset_dw
,
2713 stream
, offset_vtx
, nggso
->vertices
[i
]);
2714 ac_build_endif(&ctx
->ac
, 5241);
2715 offset_vtx
= LLVMBuildAdd(builder
, offset_vtx
, ctx
->ac
.i32_1
, "");
2718 ac_build_endif(&ctx
->ac
, 5240);
2722 static unsigned ngg_nogs_vertex_size(struct radv_shader_context
*ctx
)
2724 unsigned lds_vertex_size
= 0;
2726 if (ctx
->args
->shader_info
->so
.num_outputs
)
2727 lds_vertex_size
= 4 * ctx
->args
->shader_info
->so
.num_outputs
+ 1;
2729 return lds_vertex_size
;
2733 * Returns an `[N x i32] addrspace(LDS)*` pointing at contiguous LDS storage
2734 * for the vertex outputs.
2736 static LLVMValueRef
ngg_nogs_vertex_ptr(struct radv_shader_context
*ctx
,
2739 /* The extra dword is used to avoid LDS bank conflicts. */
2740 unsigned vertex_size
= ngg_nogs_vertex_size(ctx
);
2741 LLVMTypeRef ai32
= LLVMArrayType(ctx
->ac
.i32
, vertex_size
);
2742 LLVMTypeRef pai32
= LLVMPointerType(ai32
, AC_ADDR_SPACE_LDS
);
2743 LLVMValueRef tmp
= LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->esgs_ring
, pai32
, "");
2744 return LLVMBuildGEP(ctx
->ac
.builder
, tmp
, &vtxid
, 1, "");
2748 handle_ngg_outputs_post_1(struct radv_shader_context
*ctx
)
2750 struct radv_streamout_info
*so
= &ctx
->args
->shader_info
->so
;
2751 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2752 LLVMValueRef vertex_ptr
= NULL
;
2753 LLVMValueRef tmp
, tmp2
;
2755 assert((ctx
->stage
== MESA_SHADER_VERTEX
||
2756 ctx
->stage
== MESA_SHADER_TESS_EVAL
) && !ctx
->args
->is_gs_copy_shader
);
2758 if (!ctx
->args
->shader_info
->so
.num_outputs
)
2761 vertex_ptr
= ngg_nogs_vertex_ptr(ctx
, get_thread_id_in_tg(ctx
));
2763 for (unsigned i
= 0; i
< so
->num_outputs
; ++i
) {
2764 struct radv_stream_output
*output
=
2765 &ctx
->args
->shader_info
->so
.outputs
[i
];
2767 unsigned loc
= output
->location
;
2769 for (unsigned comp
= 0; comp
< 4; comp
++) {
2770 if (!(output
->component_mask
& (1 << comp
)))
2773 tmp
= ac_build_gep0(&ctx
->ac
, vertex_ptr
,
2774 LLVMConstInt(ctx
->ac
.i32
, 4 * i
+ comp
, false));
2775 tmp2
= LLVMBuildLoad(builder
,
2776 ctx
->abi
.outputs
[4 * loc
+ comp
], "");
2777 tmp2
= ac_to_integer(&ctx
->ac
, tmp2
);
2778 LLVMBuildStore(builder
, tmp2
, tmp
);
2784 handle_ngg_outputs_post_2(struct radv_shader_context
*ctx
)
2786 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2789 assert((ctx
->stage
== MESA_SHADER_VERTEX
||
2790 ctx
->stage
== MESA_SHADER_TESS_EVAL
) && !ctx
->args
->is_gs_copy_shader
);
2792 LLVMValueRef prims_in_wave
= ac_unpack_param(&ctx
->ac
,
2793 ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
), 8, 8);
2794 LLVMValueRef vtx_in_wave
= ac_unpack_param(&ctx
->ac
,
2795 ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
), 0, 8);
2796 LLVMValueRef is_gs_thread
= LLVMBuildICmp(builder
, LLVMIntULT
,
2797 ac_get_thread_id(&ctx
->ac
), prims_in_wave
, "");
2798 LLVMValueRef is_es_thread
= LLVMBuildICmp(builder
, LLVMIntULT
,
2799 ac_get_thread_id(&ctx
->ac
), vtx_in_wave
, "");
2800 LLVMValueRef vtxindex
[] = {
2801 ac_unpack_param(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->gs_vtx_offset
[0]), 0, 16),
2802 ac_unpack_param(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->gs_vtx_offset
[0]), 16, 16),
2803 ac_unpack_param(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->gs_vtx_offset
[2]), 0, 16),
2806 /* Determine the number of vertices per primitive. */
2807 unsigned num_vertices
;
2808 LLVMValueRef num_vertices_val
;
2810 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2811 LLVMValueRef outprim_val
=
2812 LLVMConstInt(ctx
->ac
.i32
,
2813 ctx
->args
->options
->key
.vs
.outprim
, false);
2814 num_vertices_val
= LLVMBuildAdd(builder
, outprim_val
,
2816 num_vertices
= 3; /* TODO: optimize for points & lines */
2818 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
2820 if (ctx
->shader
->info
.tess
.point_mode
)
2822 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
2827 num_vertices_val
= LLVMConstInt(ctx
->ac
.i32
, num_vertices
, false);
2831 if (ctx
->args
->shader_info
->so
.num_outputs
) {
2832 struct ngg_streamout nggso
= {};
2834 nggso
.num_vertices
= num_vertices_val
;
2835 nggso
.prim_enable
[0] = is_gs_thread
;
2837 for (unsigned i
= 0; i
< num_vertices
; ++i
)
2838 nggso
.vertices
[i
] = ngg_nogs_vertex_ptr(ctx
, vtxindex
[i
]);
2840 build_streamout(ctx
, &nggso
);
2843 /* Copy Primitive IDs from GS threads to the LDS address corresponding
2844 * to the ES thread of the provoking vertex.
2846 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
2847 ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
2848 if (ctx
->args
->shader_info
->so
.num_outputs
)
2849 ac_build_s_barrier(&ctx
->ac
);
2851 ac_build_ifcc(&ctx
->ac
, is_gs_thread
, 5400);
2852 /* Extract the PROVOKING_VTX_INDEX field. */
2853 LLVMValueRef provoking_vtx_in_prim
=
2854 LLVMConstInt(ctx
->ac
.i32
, 0, false);
2856 /* provoking_vtx_index = vtxindex[provoking_vtx_in_prim]; */
2857 LLVMValueRef indices
= ac_build_gather_values(&ctx
->ac
, vtxindex
, 3);
2858 LLVMValueRef provoking_vtx_index
=
2859 LLVMBuildExtractElement(builder
, indices
, provoking_vtx_in_prim
, "");
2861 LLVMBuildStore(builder
, ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.gs_prim_id
),
2862 ac_build_gep0(&ctx
->ac
, ctx
->esgs_ring
, provoking_vtx_index
));
2863 ac_build_endif(&ctx
->ac
, 5400);
2866 /* TODO: primitive culling */
2868 ac_build_sendmsg_gs_alloc_req(&ctx
->ac
, get_wave_id_in_tg(ctx
),
2869 ngg_get_vtx_cnt(ctx
), ngg_get_prim_cnt(ctx
));
2871 /* TODO: streamout queries */
2872 /* Export primitive data to the index buffer.
2874 * For the first version, we will always build up all three indices
2875 * independent of the primitive type. The additional garbage data
2878 * TODO: culling depends on the primitive type, so can have some
2881 ac_build_ifcc(&ctx
->ac
, is_gs_thread
, 6001);
2883 struct ac_ngg_prim prim
= {};
2885 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg_passthrough
) {
2886 prim
.passthrough
= ac_get_arg(&ctx
->ac
, ctx
->args
->gs_vtx_offset
[0]);
2888 prim
.num_vertices
= num_vertices
;
2889 prim
.isnull
= ctx
->ac
.i1false
;
2890 memcpy(prim
.index
, vtxindex
, sizeof(vtxindex
[0]) * 3);
2892 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
2893 tmp
= LLVMBuildLShr(builder
,
2894 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.gs_invocation_id
),
2895 LLVMConstInt(ctx
->ac
.i32
, 8 + i
, false), "");
2896 prim
.edgeflag
[i
] = LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
2900 ac_build_export_prim(&ctx
->ac
, &prim
);
2902 ac_build_endif(&ctx
->ac
, 6001);
2904 /* Export per-vertex data (positions and parameters). */
2905 ac_build_ifcc(&ctx
->ac
, is_es_thread
, 6002);
2907 struct radv_vs_output_info
*outinfo
=
2908 ctx
->stage
== MESA_SHADER_TESS_EVAL
?
2909 &ctx
->args
->shader_info
->tes
.outinfo
: &ctx
->args
->shader_info
->vs
.outinfo
;
2911 /* Exporting the primitive ID is handled below. */
2912 /* TODO: use the new VS export path */
2913 handle_vs_outputs_post(ctx
, false,
2914 ctx
->args
->options
->key
.vs_common_out
.export_clip_dists
,
2917 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
2918 unsigned param_count
= outinfo
->param_exports
;
2919 LLVMValueRef values
[4];
2921 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2922 /* Wait for GS stores to finish. */
2923 ac_build_s_barrier(&ctx
->ac
);
2925 tmp
= ac_build_gep0(&ctx
->ac
, ctx
->esgs_ring
,
2926 get_thread_id_in_tg(ctx
));
2927 values
[0] = LLVMBuildLoad(builder
, tmp
, "");
2929 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
2930 values
[0] = ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.tes_patch_id
);
2933 values
[0] = ac_to_float(&ctx
->ac
, values
[0]);
2934 for (unsigned j
= 1; j
< 4; j
++)
2935 values
[j
] = ctx
->ac
.f32_0
;
2937 radv_export_param(ctx
, param_count
, values
, 0x1);
2939 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
++;
2940 outinfo
->param_exports
= param_count
;
2943 ac_build_endif(&ctx
->ac
, 6002);
2946 static void gfx10_ngg_gs_emit_prologue(struct radv_shader_context
*ctx
)
2948 /* Zero out the part of LDS scratch that is used to accumulate the
2949 * per-stream generated primitive count.
2951 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2952 LLVMValueRef scratchptr
= ctx
->gs_ngg_scratch
;
2953 LLVMValueRef tid
= get_thread_id_in_tg(ctx
);
2954 LLVMBasicBlockRef merge_block
;
2957 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
->ac
.builder
));
2958 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
2959 merge_block
= LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
2961 cond
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
2962 LLVMBuildCondBr(ctx
->ac
.builder
, cond
, then_block
, merge_block
);
2963 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, then_block
);
2965 LLVMValueRef ptr
= ac_build_gep0(&ctx
->ac
, scratchptr
, tid
);
2966 LLVMBuildStore(builder
, ctx
->ac
.i32_0
, ptr
);
2968 LLVMBuildBr(ctx
->ac
.builder
, merge_block
);
2969 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, merge_block
);
2971 ac_build_s_barrier(&ctx
->ac
);
2974 static void gfx10_ngg_gs_emit_epilogue_1(struct radv_shader_context
*ctx
)
2976 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2977 LLVMValueRef i8_0
= LLVMConstInt(ctx
->ac
.i8
, 0, false);
2980 /* Zero out remaining (non-emitted) primitive flags.
2982 * Note: Alternatively, we could pass the relevant gs_next_vertex to
2983 * the emit threads via LDS. This is likely worse in the expected
2984 * typical case where each GS thread emits the full set of
2987 for (unsigned stream
= 0; stream
< 4; ++stream
) {
2988 unsigned num_components
;
2991 ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
];
2992 if (!num_components
)
2995 const LLVMValueRef gsthread
= get_thread_id_in_tg(ctx
);
2997 ac_build_bgnloop(&ctx
->ac
, 5100);
2999 const LLVMValueRef vertexidx
=
3000 LLVMBuildLoad(builder
, ctx
->gs_next_vertex
[stream
], "");
3001 tmp
= LLVMBuildICmp(builder
, LLVMIntUGE
, vertexidx
,
3002 LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.gs
.vertices_out
, false), "");
3003 ac_build_ifcc(&ctx
->ac
, tmp
, 5101);
3004 ac_build_break(&ctx
->ac
);
3005 ac_build_endif(&ctx
->ac
, 5101);
3007 tmp
= LLVMBuildAdd(builder
, vertexidx
, ctx
->ac
.i32_1
, "");
3008 LLVMBuildStore(builder
, tmp
, ctx
->gs_next_vertex
[stream
]);
3010 tmp
= ngg_gs_emit_vertex_ptr(ctx
, gsthread
, vertexidx
);
3011 LLVMBuildStore(builder
, i8_0
,
3012 ngg_gs_get_emit_primflag_ptr(ctx
, tmp
, stream
));
3014 ac_build_endloop(&ctx
->ac
, 5100);
3017 /* Accumulate generated primitives counts across the entire threadgroup. */
3018 for (unsigned stream
= 0; stream
< 4; ++stream
) {
3019 unsigned num_components
;
3022 ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
];
3023 if (!num_components
)
3026 LLVMValueRef numprims
=
3027 LLVMBuildLoad(builder
, ctx
->gs_generated_prims
[stream
], "");
3028 numprims
= ac_build_reduce(&ctx
->ac
, numprims
, nir_op_iadd
, ctx
->ac
.wave_size
);
3030 tmp
= LLVMBuildICmp(builder
, LLVMIntEQ
, ac_get_thread_id(&ctx
->ac
), ctx
->ac
.i32_0
, "");
3031 ac_build_ifcc(&ctx
->ac
, tmp
, 5105);
3033 LLVMBuildAtomicRMW(builder
, LLVMAtomicRMWBinOpAdd
,
3034 ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
,
3035 LLVMConstInt(ctx
->ac
.i32
, stream
, false)),
3036 numprims
, LLVMAtomicOrderingMonotonic
, false);
3038 ac_build_endif(&ctx
->ac
, 5105);
3042 static void gfx10_ngg_gs_emit_epilogue_2(struct radv_shader_context
*ctx
)
3044 const unsigned verts_per_prim
= si_conv_gl_prim_to_vertices(ctx
->shader
->info
.gs
.output_primitive
);
3045 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3046 LLVMValueRef tmp
, tmp2
;
3048 ac_build_s_barrier(&ctx
->ac
);
3050 const LLVMValueRef tid
= get_thread_id_in_tg(ctx
);
3051 LLVMValueRef num_emit_threads
= ngg_get_prim_cnt(ctx
);
3054 if (ctx
->args
->shader_info
->so
.num_outputs
) {
3055 struct ngg_streamout nggso
= {};
3057 nggso
.num_vertices
= LLVMConstInt(ctx
->ac
.i32
, verts_per_prim
, false);
3059 LLVMValueRef vertexptr
= ngg_gs_vertex_ptr(ctx
, tid
);
3060 for (unsigned stream
= 0; stream
< 4; ++stream
) {
3061 if (!ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
])
3064 tmp
= LLVMBuildLoad(builder
,
3065 ngg_gs_get_emit_primflag_ptr(ctx
, vertexptr
, stream
), "");
3066 tmp
= LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
3067 tmp2
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, num_emit_threads
, "");
3068 nggso
.prim_enable
[stream
] = LLVMBuildAnd(builder
, tmp
, tmp2
, "");
3071 for (unsigned i
= 0; i
< verts_per_prim
; ++i
) {
3072 tmp
= LLVMBuildSub(builder
, tid
,
3073 LLVMConstInt(ctx
->ac
.i32
, verts_per_prim
- i
- 1, false), "");
3074 tmp
= ngg_gs_vertex_ptr(ctx
, tmp
);
3075 nggso
.vertices
[i
] = ac_build_gep0(&ctx
->ac
, tmp
, ctx
->ac
.i32_0
);
3078 build_streamout(ctx
, &nggso
);
3081 /* Write shader query data. */
3082 tmp
= ac_get_arg(&ctx
->ac
, ctx
->args
->ngg_gs_state
);
3083 tmp
= LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
3084 ac_build_ifcc(&ctx
->ac
, tmp
, 5109);
3085 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
,
3086 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
3087 ac_build_ifcc(&ctx
->ac
, tmp
, 5110);
3089 tmp
= LLVMBuildLoad(builder
, ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, tid
), "");
3091 ac_llvm_add_target_dep_function_attr(ctx
->main_function
,
3092 "amdgpu-gds-size", 256);
3094 LLVMTypeRef gdsptr
= LLVMPointerType(ctx
->ac
.i32
, AC_ADDR_SPACE_GDS
);
3095 LLVMValueRef gdsbase
= LLVMBuildIntToPtr(builder
, ctx
->ac
.i32_0
, gdsptr
, "");
3097 const char *sync_scope
= LLVM_VERSION_MAJOR
>= 9 ? "workgroup-one-as" : "workgroup";
3099 /* Use a plain GDS atomic to accumulate the number of generated
3102 ac_build_atomic_rmw(&ctx
->ac
, LLVMAtomicRMWBinOpAdd
, gdsbase
,
3105 ac_build_endif(&ctx
->ac
, 5110);
3106 ac_build_endif(&ctx
->ac
, 5109);
3110 /* Determine vertex liveness. */
3111 LLVMValueRef vertliveptr
= ac_build_alloca(&ctx
->ac
, ctx
->ac
.i1
, "vertexlive");
3113 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, num_emit_threads
, "");
3114 ac_build_ifcc(&ctx
->ac
, tmp
, 5120);
3116 for (unsigned i
= 0; i
< verts_per_prim
; ++i
) {
3117 const LLVMValueRef primidx
=
3118 LLVMBuildAdd(builder
, tid
,
3119 LLVMConstInt(ctx
->ac
.i32
, i
, false), "");
3122 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, primidx
, num_emit_threads
, "");
3123 ac_build_ifcc(&ctx
->ac
, tmp
, 5121 + i
);
3126 /* Load primitive liveness */
3127 tmp
= ngg_gs_vertex_ptr(ctx
, primidx
);
3128 tmp
= LLVMBuildLoad(builder
,
3129 ngg_gs_get_emit_primflag_ptr(ctx
, tmp
, 0), "");
3130 const LLVMValueRef primlive
=
3131 LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
3133 tmp
= LLVMBuildLoad(builder
, vertliveptr
, "");
3134 tmp
= LLVMBuildOr(builder
, tmp
, primlive
, ""),
3135 LLVMBuildStore(builder
, tmp
, vertliveptr
);
3138 ac_build_endif(&ctx
->ac
, 5121 + i
);
3141 ac_build_endif(&ctx
->ac
, 5120);
3143 /* Inclusive scan addition across the current wave. */
3144 LLVMValueRef vertlive
= LLVMBuildLoad(builder
, vertliveptr
, "");
3145 struct ac_wg_scan vertlive_scan
= {};
3146 vertlive_scan
.op
= nir_op_iadd
;
3147 vertlive_scan
.enable_reduce
= true;
3148 vertlive_scan
.enable_exclusive
= true;
3149 vertlive_scan
.src
= vertlive
;
3150 vertlive_scan
.scratch
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, ctx
->ac
.i32_0
);
3151 vertlive_scan
.waveidx
= get_wave_id_in_tg(ctx
);
3152 vertlive_scan
.numwaves
= get_tgsize(ctx
);
3153 vertlive_scan
.maxwaves
= 8;
3155 ac_build_wg_scan(&ctx
->ac
, &vertlive_scan
);
3157 /* Skip all exports (including index exports) when possible. At least on
3158 * early gfx10 revisions this is also to avoid hangs.
3160 LLVMValueRef have_exports
=
3161 LLVMBuildICmp(builder
, LLVMIntNE
, vertlive_scan
.result_reduce
, ctx
->ac
.i32_0
, "");
3163 LLVMBuildSelect(builder
, have_exports
, num_emit_threads
, ctx
->ac
.i32_0
, "");
3165 /* Allocate export space. Send this message as early as possible, to
3166 * hide the latency of the SQ <-> SPI roundtrip.
3168 * Note: We could consider compacting primitives for export as well.
3169 * PA processes 1 non-null prim / clock, but it fetches 4 DW of
3170 * prim data per clock and skips null primitives at no additional
3171 * cost. So compacting primitives can only be beneficial when
3172 * there are 4 or more contiguous null primitives in the export
3173 * (in the common case of single-dword prim exports).
3175 ac_build_sendmsg_gs_alloc_req(&ctx
->ac
, get_wave_id_in_tg(ctx
),
3176 vertlive_scan
.result_reduce
, num_emit_threads
);
3178 /* Setup the reverse vertex compaction permutation. We re-use stream 1
3179 * of the primitive liveness flags, relying on the fact that each
3180 * threadgroup can have at most 256 threads. */
3181 ac_build_ifcc(&ctx
->ac
, vertlive
, 5130);
3183 tmp
= ngg_gs_vertex_ptr(ctx
, vertlive_scan
.result_exclusive
);
3184 tmp2
= LLVMBuildTrunc(builder
, tid
, ctx
->ac
.i8
, "");
3185 LLVMBuildStore(builder
, tmp2
,
3186 ngg_gs_get_emit_primflag_ptr(ctx
, tmp
, 1));
3188 ac_build_endif(&ctx
->ac
, 5130);
3190 ac_build_s_barrier(&ctx
->ac
);
3192 /* Export primitive data */
3193 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, num_emit_threads
, "");
3194 ac_build_ifcc(&ctx
->ac
, tmp
, 5140);
3197 struct ac_ngg_prim prim
= {};
3198 prim
.num_vertices
= verts_per_prim
;
3200 tmp
= ngg_gs_vertex_ptr(ctx
, tid
);
3201 flags
= LLVMBuildLoad(builder
,
3202 ngg_gs_get_emit_primflag_ptr(ctx
, tmp
, 0), "");
3203 prim
.isnull
= LLVMBuildNot(builder
, LLVMBuildTrunc(builder
, flags
, ctx
->ac
.i1
, ""), "");
3205 for (unsigned i
= 0; i
< verts_per_prim
; ++i
) {
3206 prim
.index
[i
] = LLVMBuildSub(builder
, vertlive_scan
.result_exclusive
,
3207 LLVMConstInt(ctx
->ac
.i32
, verts_per_prim
- i
- 1, false), "");
3208 prim
.edgeflag
[i
] = ctx
->ac
.i1false
;
3211 /* Geometry shaders output triangle strips, but NGG expects
3212 * triangles. We need to change the vertex order for odd
3213 * triangles to get correct front/back facing by swapping 2
3214 * vertex indices, but we also have to keep the provoking
3215 * vertex in the same place.
3217 if (verts_per_prim
== 3) {
3218 LLVMValueRef is_odd
= LLVMBuildLShr(builder
, flags
, ctx
->ac
.i8_1
, "");
3219 is_odd
= LLVMBuildTrunc(builder
, is_odd
, ctx
->ac
.i1
, "");
3221 struct ac_ngg_prim in
= prim
;
3222 prim
.index
[0] = in
.index
[0];
3223 prim
.index
[1] = LLVMBuildSelect(builder
, is_odd
,
3224 in
.index
[2], in
.index
[1], "");
3225 prim
.index
[2] = LLVMBuildSelect(builder
, is_odd
,
3226 in
.index
[1], in
.index
[2], "");
3229 ac_build_export_prim(&ctx
->ac
, &prim
);
3231 ac_build_endif(&ctx
->ac
, 5140);
3233 /* Export position and parameter data */
3234 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, vertlive_scan
.result_reduce
, "");
3235 ac_build_ifcc(&ctx
->ac
, tmp
, 5145);
3237 struct radv_vs_output_info
*outinfo
= &ctx
->args
->shader_info
->vs
.outinfo
;
3238 bool export_view_index
= ctx
->args
->options
->key
.has_multiview_view_index
;
3239 struct radv_shader_output_values
*outputs
;
3240 unsigned noutput
= 0;
3242 /* Allocate a temporary array for the output values. */
3243 unsigned num_outputs
= util_bitcount64(ctx
->output_mask
) + export_view_index
;
3244 outputs
= calloc(num_outputs
, sizeof(outputs
[0]));
3246 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
3247 sizeof(outinfo
->vs_output_param_offset
));
3248 outinfo
->pos_exports
= 0;
3250 tmp
= ngg_gs_vertex_ptr(ctx
, tid
);
3251 tmp
= LLVMBuildLoad(builder
,
3252 ngg_gs_get_emit_primflag_ptr(ctx
, tmp
, 1), "");
3253 tmp
= LLVMBuildZExt(builder
, tmp
, ctx
->ac
.i32
, "");
3254 const LLVMValueRef vertexptr
= ngg_gs_vertex_ptr(ctx
, tmp
);
3256 unsigned out_idx
= 0;
3257 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3258 unsigned output_usage_mask
=
3259 ctx
->args
->shader_info
->gs
.output_usage_mask
[i
];
3260 int length
= util_last_bit(output_usage_mask
);
3262 if (!(ctx
->output_mask
& (1ull << i
)))
3265 outputs
[noutput
].slot_name
= i
;
3266 outputs
[noutput
].slot_index
= i
== VARYING_SLOT_CLIP_DIST1
;
3267 outputs
[noutput
].usage_mask
= output_usage_mask
;
3269 for (unsigned j
= 0; j
< length
; j
++, out_idx
++) {
3270 if (!(output_usage_mask
& (1 << j
)))
3273 tmp
= ngg_gs_get_emit_output_ptr(ctx
, vertexptr
, out_idx
);
3274 tmp
= LLVMBuildLoad(builder
, tmp
, "");
3276 LLVMTypeRef type
= LLVMGetAllocatedType(ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
3277 if (ac_get_type_size(type
) == 2) {
3278 tmp
= ac_to_integer(&ctx
->ac
, tmp
);
3279 tmp
= LLVMBuildTrunc(ctx
->ac
.builder
, tmp
, ctx
->ac
.i16
, "");
3282 outputs
[noutput
].values
[j
] = ac_to_float(&ctx
->ac
, tmp
);
3285 for (unsigned j
= length
; j
< 4; j
++)
3286 outputs
[noutput
].values
[j
] = LLVMGetUndef(ctx
->ac
.f32
);
3291 /* Export ViewIndex. */
3292 if (export_view_index
) {
3293 outputs
[noutput
].slot_name
= VARYING_SLOT_LAYER
;
3294 outputs
[noutput
].slot_index
= 0;
3295 outputs
[noutput
].usage_mask
= 0x1;
3296 outputs
[noutput
].values
[0] =
3297 ac_to_float(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.view_index
));
3298 for (unsigned j
= 1; j
< 4; j
++)
3299 outputs
[noutput
].values
[j
] = ctx
->ac
.f32_0
;
3303 radv_llvm_export_vs(ctx
, outputs
, noutput
, outinfo
,
3304 ctx
->args
->options
->key
.vs_common_out
.export_clip_dists
);
3307 ac_build_endif(&ctx
->ac
, 5145);
3310 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context
*ctx
,
3312 LLVMValueRef
*addrs
)
3314 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3316 const LLVMValueRef vertexidx
=
3317 LLVMBuildLoad(builder
, ctx
->gs_next_vertex
[stream
], "");
3319 /* If this thread has already emitted the declared maximum number of
3320 * vertices, skip the write: excessive vertex emissions are not
3321 * supposed to have any effect.
3323 const LLVMValueRef can_emit
=
3324 LLVMBuildICmp(builder
, LLVMIntULT
, vertexidx
,
3325 LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.gs
.vertices_out
, false), "");
3326 ac_build_ifcc(&ctx
->ac
, can_emit
, 9001);
3328 tmp
= LLVMBuildAdd(builder
, vertexidx
, ctx
->ac
.i32_1
, "");
3329 tmp
= LLVMBuildSelect(builder
, can_emit
, tmp
, vertexidx
, "");
3330 LLVMBuildStore(builder
, tmp
, ctx
->gs_next_vertex
[stream
]);
3332 const LLVMValueRef vertexptr
=
3333 ngg_gs_emit_vertex_ptr(ctx
, get_thread_id_in_tg(ctx
), vertexidx
);
3334 unsigned out_idx
= 0;
3335 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3336 unsigned output_usage_mask
=
3337 ctx
->args
->shader_info
->gs
.output_usage_mask
[i
];
3338 uint8_t output_stream
=
3339 ctx
->args
->shader_info
->gs
.output_streams
[i
];
3340 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
3341 int length
= util_last_bit(output_usage_mask
);
3343 if (!(ctx
->output_mask
& (1ull << i
)) ||
3344 output_stream
!= stream
)
3347 for (unsigned j
= 0; j
< length
; j
++, out_idx
++) {
3348 if (!(output_usage_mask
& (1 << j
)))
3351 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
,
3353 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
3354 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
3356 LLVMBuildStore(builder
, out_val
,
3357 ngg_gs_get_emit_output_ptr(ctx
, vertexptr
, out_idx
));
3360 assert(out_idx
* 4 <= ctx
->args
->shader_info
->gs
.gsvs_vertex_size
);
3362 /* Determine and store whether this vertex completed a primitive. */
3363 const LLVMValueRef curverts
= LLVMBuildLoad(builder
, ctx
->gs_curprim_verts
[stream
], "");
3365 tmp
= LLVMConstInt(ctx
->ac
.i32
, si_conv_gl_prim_to_vertices(ctx
->shader
->info
.gs
.output_primitive
) - 1, false);
3366 const LLVMValueRef iscompleteprim
=
3367 LLVMBuildICmp(builder
, LLVMIntUGE
, curverts
, tmp
, "");
3369 /* Since the geometry shader emits triangle strips, we need to
3370 * track which primitive is odd and swap vertex indices to get
3371 * the correct vertex order.
3373 LLVMValueRef is_odd
= ctx
->ac
.i1false
;
3375 si_conv_gl_prim_to_vertices(ctx
->shader
->info
.gs
.output_primitive
) == 3) {
3376 tmp
= LLVMBuildAnd(builder
, curverts
, ctx
->ac
.i32_1
, "");
3377 is_odd
= LLVMBuildICmp(builder
, LLVMIntEQ
, tmp
, ctx
->ac
.i32_1
, "");
3380 tmp
= LLVMBuildAdd(builder
, curverts
, ctx
->ac
.i32_1
, "");
3381 LLVMBuildStore(builder
, tmp
, ctx
->gs_curprim_verts
[stream
]);
3383 /* The per-vertex primitive flag encoding:
3384 * bit 0: whether this vertex finishes a primitive
3385 * bit 1: whether the primitive is odd (if we are emitting triangle strips)
3387 tmp
= LLVMBuildZExt(builder
, iscompleteprim
, ctx
->ac
.i8
, "");
3388 tmp
= LLVMBuildOr(builder
, tmp
,
3389 LLVMBuildShl(builder
,
3390 LLVMBuildZExt(builder
, is_odd
, ctx
->ac
.i8
, ""),
3391 ctx
->ac
.i8_1
, ""), "");
3392 LLVMBuildStore(builder
, tmp
,
3393 ngg_gs_get_emit_primflag_ptr(ctx
, vertexptr
, stream
));
3395 tmp
= LLVMBuildLoad(builder
, ctx
->gs_generated_prims
[stream
], "");
3396 tmp
= LLVMBuildAdd(builder
, tmp
, LLVMBuildZExt(builder
, iscompleteprim
, ctx
->ac
.i32
, ""), "");
3397 LLVMBuildStore(builder
, tmp
, ctx
->gs_generated_prims
[stream
]);
3399 ac_build_endif(&ctx
->ac
, 9001);
3403 write_tess_factors(struct radv_shader_context
*ctx
)
3405 unsigned stride
, outer_comps
, inner_comps
;
3406 LLVMValueRef tcs_rel_ids
= ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.tcs_rel_ids
);
3407 LLVMValueRef invocation_id
= ac_unpack_param(&ctx
->ac
, tcs_rel_ids
, 8, 5);
3408 LLVMValueRef rel_patch_id
= ac_unpack_param(&ctx
->ac
, tcs_rel_ids
, 0, 8);
3409 unsigned tess_inner_index
= 0, tess_outer_index
;
3410 LLVMValueRef lds_base
, lds_inner
= NULL
, lds_outer
, byteoffset
, buffer
;
3411 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
3413 ac_emit_barrier(&ctx
->ac
, ctx
->stage
);
3415 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
3435 ac_build_ifcc(&ctx
->ac
,
3436 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3437 invocation_id
, ctx
->ac
.i32_0
, ""), 6503);
3439 lds_base
= get_tcs_out_current_patch_data_offset(ctx
);
3442 tess_inner_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
3443 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3444 LLVMConstInt(ctx
->ac
.i32
, tess_inner_index
* 4, false), "");
3447 tess_outer_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
3448 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3449 LLVMConstInt(ctx
->ac
.i32
, tess_outer_index
* 4, false), "");
3451 for (i
= 0; i
< 4; i
++) {
3452 inner
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
3453 outer
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
3457 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
3458 outer
[0] = out
[1] = ac_lds_load(&ctx
->ac
, lds_outer
);
3459 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
3461 outer
[1] = out
[0] = ac_lds_load(&ctx
->ac
, lds_outer
);
3463 for (i
= 0; i
< outer_comps
; i
++) {
3465 ac_lds_load(&ctx
->ac
, lds_outer
);
3466 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
3469 for (i
= 0; i
< inner_comps
; i
++) {
3470 inner
[i
] = out
[outer_comps
+i
] =
3471 ac_lds_load(&ctx
->ac
, lds_inner
);
3472 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_inner
,
3477 /* Convert the outputs to vectors for stores. */
3478 vec0
= ac_build_gather_values(&ctx
->ac
, out
, MIN2(stride
, 4));
3482 vec1
= ac_build_gather_values(&ctx
->ac
, out
+ 4, stride
- 4);
3485 buffer
= ctx
->hs_ring_tess_factor
;
3486 tf_base
= ac_get_arg(&ctx
->ac
, ctx
->args
->tess_factor_offset
);
3487 byteoffset
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
3488 LLVMConstInt(ctx
->ac
.i32
, 4 * stride
, false), "");
3489 unsigned tf_offset
= 0;
3491 if (ctx
->ac
.chip_class
<= GFX8
) {
3492 ac_build_ifcc(&ctx
->ac
,
3493 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3494 rel_patch_id
, ctx
->ac
.i32_0
, ""), 6504);
3496 /* Store the dynamic HS control word. */
3497 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
3498 LLVMConstInt(ctx
->ac
.i32
, 0x80000000, false),
3499 1, ctx
->ac
.i32_0
, tf_base
,
3503 ac_build_endif(&ctx
->ac
, 6504);
3506 /* Store the tessellation factors. */
3507 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
3508 MIN2(stride
, 4), byteoffset
, tf_base
,
3511 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
3512 stride
- 4, byteoffset
, tf_base
,
3513 16 + tf_offset
, ac_glc
);
3515 //store to offchip for TES to read - only if TES reads them
3516 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
3517 LLVMValueRef inner_vec
, outer_vec
, tf_outer_offset
;
3518 LLVMValueRef tf_inner_offset
;
3519 unsigned param_outer
, param_inner
;
3521 param_outer
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
3522 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
3523 LLVMConstInt(ctx
->ac
.i32
, param_outer
, 0));
3525 outer_vec
= ac_build_gather_values(&ctx
->ac
, outer
,
3526 util_next_power_of_two(outer_comps
));
3528 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, outer_vec
,
3529 outer_comps
, tf_outer_offset
,
3530 ac_get_arg(&ctx
->ac
, ctx
->args
->oc_lds
),
3533 param_inner
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
3534 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
3535 LLVMConstInt(ctx
->ac
.i32
, param_inner
, 0));
3537 inner_vec
= inner_comps
== 1 ? inner
[0] :
3538 ac_build_gather_values(&ctx
->ac
, inner
, inner_comps
);
3539 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, inner_vec
,
3540 inner_comps
, tf_inner_offset
,
3541 ac_get_arg(&ctx
->ac
, ctx
->args
->oc_lds
),
3546 ac_build_endif(&ctx
->ac
, 6503);
3550 handle_tcs_outputs_post(struct radv_shader_context
*ctx
)
3552 write_tess_factors(ctx
);
3556 si_export_mrt_color(struct radv_shader_context
*ctx
,
3557 LLVMValueRef
*color
, unsigned index
,
3558 struct ac_export_args
*args
)
3561 si_llvm_init_export_args(ctx
, color
, 0xf,
3562 V_008DFC_SQ_EXP_MRT
+ index
, args
);
3563 if (!args
->enabled_channels
)
3564 return false; /* unnecessary NULL export */
3570 radv_export_mrt_z(struct radv_shader_context
*ctx
,
3571 LLVMValueRef depth
, LLVMValueRef stencil
,
3572 LLVMValueRef samplemask
)
3574 struct ac_export_args args
;
3576 ac_export_mrt_z(&ctx
->ac
, depth
, stencil
, samplemask
, &args
);
3578 ac_build_export(&ctx
->ac
, &args
);
3582 handle_fs_outputs_post(struct radv_shader_context
*ctx
)
3585 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
3586 struct ac_export_args color_args
[8];
3588 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3589 LLVMValueRef values
[4];
3591 if (!(ctx
->output_mask
& (1ull << i
)))
3594 if (i
< FRAG_RESULT_DATA0
)
3597 for (unsigned j
= 0; j
< 4; j
++)
3598 values
[j
] = ac_to_float(&ctx
->ac
,
3599 radv_load_output(ctx
, i
, j
));
3601 bool ret
= si_export_mrt_color(ctx
, values
,
3602 i
- FRAG_RESULT_DATA0
,
3603 &color_args
[index
]);
3608 /* Process depth, stencil, samplemask. */
3609 if (ctx
->args
->shader_info
->ps
.writes_z
) {
3610 depth
= ac_to_float(&ctx
->ac
,
3611 radv_load_output(ctx
, FRAG_RESULT_DEPTH
, 0));
3613 if (ctx
->args
->shader_info
->ps
.writes_stencil
) {
3614 stencil
= ac_to_float(&ctx
->ac
,
3615 radv_load_output(ctx
, FRAG_RESULT_STENCIL
, 0));
3617 if (ctx
->args
->shader_info
->ps
.writes_sample_mask
) {
3618 samplemask
= ac_to_float(&ctx
->ac
,
3619 radv_load_output(ctx
, FRAG_RESULT_SAMPLE_MASK
, 0));
3622 /* Set the DONE bit on last non-null color export only if Z isn't
3626 !ctx
->args
->shader_info
->ps
.writes_z
&&
3627 !ctx
->args
->shader_info
->ps
.writes_stencil
&&
3628 !ctx
->args
->shader_info
->ps
.writes_sample_mask
) {
3629 unsigned last
= index
- 1;
3631 color_args
[last
].valid_mask
= 1; /* whether the EXEC mask is valid */
3632 color_args
[last
].done
= 1; /* DONE bit */
3635 /* Export PS outputs. */
3636 for (unsigned i
= 0; i
< index
; i
++)
3637 ac_build_export(&ctx
->ac
, &color_args
[i
]);
3639 if (depth
|| stencil
|| samplemask
)
3640 radv_export_mrt_z(ctx
, depth
, stencil
, samplemask
);
3642 ac_build_export_null(&ctx
->ac
);
3646 emit_gs_epilogue(struct radv_shader_context
*ctx
)
3648 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg
) {
3649 gfx10_ngg_gs_emit_epilogue_1(ctx
);
3653 if (ctx
->ac
.chip_class
>= GFX10
)
3654 LLVMBuildFence(ctx
->ac
.builder
, LLVMAtomicOrderingRelease
, false, "");
3656 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
, ctx
->gs_wave_id
);
3660 handle_shader_outputs_post(struct ac_shader_abi
*abi
, unsigned max_outputs
,
3661 LLVMValueRef
*addrs
)
3663 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
3665 switch (ctx
->stage
) {
3666 case MESA_SHADER_VERTEX
:
3667 if (ctx
->args
->options
->key
.vs_common_out
.as_ls
)
3668 handle_ls_outputs_post(ctx
);
3669 else if (ctx
->args
->options
->key
.vs_common_out
.as_es
)
3670 handle_es_outputs_post(ctx
, &ctx
->args
->shader_info
->vs
.es_info
);
3671 else if (ctx
->args
->options
->key
.vs_common_out
.as_ngg
)
3672 handle_ngg_outputs_post_1(ctx
);
3674 handle_vs_outputs_post(ctx
, ctx
->args
->options
->key
.vs_common_out
.export_prim_id
,
3675 ctx
->args
->options
->key
.vs_common_out
.export_clip_dists
,
3676 &ctx
->args
->shader_info
->vs
.outinfo
);
3678 case MESA_SHADER_FRAGMENT
:
3679 handle_fs_outputs_post(ctx
);
3681 case MESA_SHADER_GEOMETRY
:
3682 emit_gs_epilogue(ctx
);
3684 case MESA_SHADER_TESS_CTRL
:
3685 handle_tcs_outputs_post(ctx
);
3687 case MESA_SHADER_TESS_EVAL
:
3688 if (ctx
->args
->options
->key
.vs_common_out
.as_es
)
3689 handle_es_outputs_post(ctx
, &ctx
->args
->shader_info
->tes
.es_info
);
3690 else if (ctx
->args
->options
->key
.vs_common_out
.as_ngg
)
3691 handle_ngg_outputs_post_1(ctx
);
3693 handle_vs_outputs_post(ctx
, ctx
->args
->options
->key
.vs_common_out
.export_prim_id
,
3694 ctx
->args
->options
->key
.vs_common_out
.export_clip_dists
,
3695 &ctx
->args
->shader_info
->tes
.outinfo
);
3702 static void ac_llvm_finalize_module(struct radv_shader_context
*ctx
,
3703 LLVMPassManagerRef passmgr
,
3704 const struct radv_nir_compiler_options
*options
)
3706 LLVMRunPassManager(passmgr
, ctx
->ac
.module
);
3707 LLVMDisposeBuilder(ctx
->ac
.builder
);
3709 ac_llvm_context_dispose(&ctx
->ac
);
3713 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context
*ctx
)
3715 struct radv_vs_output_info
*outinfo
;
3717 switch (ctx
->stage
) {
3718 case MESA_SHADER_FRAGMENT
:
3719 case MESA_SHADER_COMPUTE
:
3720 case MESA_SHADER_TESS_CTRL
:
3721 case MESA_SHADER_GEOMETRY
:
3723 case MESA_SHADER_VERTEX
:
3724 if (ctx
->args
->options
->key
.vs_common_out
.as_ls
||
3725 ctx
->args
->options
->key
.vs_common_out
.as_es
)
3727 outinfo
= &ctx
->args
->shader_info
->vs
.outinfo
;
3729 case MESA_SHADER_TESS_EVAL
:
3730 if (ctx
->args
->options
->key
.vs_common_out
.as_es
)
3732 outinfo
= &ctx
->args
->shader_info
->tes
.outinfo
;
3735 unreachable("Unhandled shader type");
3738 ac_optimize_vs_outputs(&ctx
->ac
,
3740 outinfo
->vs_output_param_offset
,
3742 &outinfo
->param_exports
);
3746 ac_setup_rings(struct radv_shader_context
*ctx
)
3748 if (ctx
->args
->options
->chip_class
<= GFX8
&&
3749 (ctx
->stage
== MESA_SHADER_GEOMETRY
||
3750 ctx
->args
->options
->key
.vs_common_out
.as_es
|| ctx
->args
->options
->key
.vs_common_out
.as_es
)) {
3751 unsigned ring
= ctx
->stage
== MESA_SHADER_GEOMETRY
? RING_ESGS_GS
3753 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, ring
, false);
3755 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
,
3760 if (ctx
->args
->is_gs_copy_shader
) {
3762 ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
,
3763 LLVMConstInt(ctx
->ac
.i32
,
3764 RING_GSVS_VS
, false));
3767 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
3768 /* The conceptual layout of the GSVS ring is
3769 * v0c0 .. vLv0 v0c1 .. vLc1 ..
3770 * but the real memory layout is swizzled across
3772 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
3774 * Override the buffer descriptor accordingly.
3776 LLVMTypeRef v2i64
= LLVMVectorType(ctx
->ac
.i64
, 2);
3777 uint64_t stream_offset
= 0;
3778 unsigned num_records
= ctx
->ac
.wave_size
;
3779 LLVMValueRef base_ring
;
3782 ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
,
3783 LLVMConstInt(ctx
->ac
.i32
,
3784 RING_GSVS_GS
, false));
3786 for (unsigned stream
= 0; stream
< 4; stream
++) {
3787 unsigned num_components
, stride
;
3788 LLVMValueRef ring
, tmp
;
3791 ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
];
3793 if (!num_components
)
3796 stride
= 4 * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
3798 /* Limit on the stride field for <= GFX7. */
3799 assert(stride
< (1 << 14));
3801 ring
= LLVMBuildBitCast(ctx
->ac
.builder
,
3802 base_ring
, v2i64
, "");
3803 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
,
3804 ring
, ctx
->ac
.i32_0
, "");
3805 tmp
= LLVMBuildAdd(ctx
->ac
.builder
, tmp
,
3806 LLVMConstInt(ctx
->ac
.i64
,
3807 stream_offset
, 0), "");
3808 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
,
3809 ring
, tmp
, ctx
->ac
.i32_0
, "");
3811 stream_offset
+= stride
* ctx
->ac
.wave_size
;
3813 ring
= LLVMBuildBitCast(ctx
->ac
.builder
, ring
,
3816 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
, ring
,
3818 tmp
= LLVMBuildOr(ctx
->ac
.builder
, tmp
,
3819 LLVMConstInt(ctx
->ac
.i32
,
3820 S_008F04_STRIDE(stride
), false), "");
3821 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ring
, tmp
,
3824 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ring
,
3825 LLVMConstInt(ctx
->ac
.i32
,
3826 num_records
, false),
3827 LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
3829 ctx
->gsvs_ring
[stream
] = ring
;
3833 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
3834 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
3835 ctx
->hs_ring_tess_offchip
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_OFFCHIP
, false));
3836 ctx
->hs_ring_tess_factor
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_FACTOR
, false));
3841 radv_nir_get_max_workgroup_size(enum chip_class chip_class
,
3842 gl_shader_stage stage
,
3843 const struct nir_shader
*nir
)
3845 const unsigned backup_sizes
[] = {chip_class
>= GFX9
? 128 : 64, 1, 1};
3847 for (unsigned i
= 0; i
< 3; i
++)
3848 sizes
[i
] = nir
? nir
->info
.cs
.local_size
[i
] : backup_sizes
[i
];
3849 return radv_get_max_workgroup_size(chip_class
, stage
, sizes
);
3852 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
3853 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context
*ctx
)
3855 LLVMValueRef count
=
3856 ac_unpack_param(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
), 8, 8);
3857 LLVMValueRef hs_empty
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, count
,
3859 ctx
->abi
.instance_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
,
3860 ac_get_arg(&ctx
->ac
, ctx
->args
->rel_auto_id
),
3861 ctx
->abi
.instance_id
, "");
3862 ctx
->rel_auto_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
,
3863 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.tcs_rel_ids
),
3866 ctx
->abi
.vertex_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
,
3867 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.tcs_patch_id
),
3868 ctx
->abi
.vertex_id
, "");
3871 static void prepare_gs_input_vgprs(struct radv_shader_context
*ctx
, bool merged
)
3874 for(int i
= 5; i
>= 0; --i
) {
3875 ctx
->gs_vtx_offset
[i
] =
3876 ac_unpack_param(&ctx
->ac
,
3877 ac_get_arg(&ctx
->ac
, ctx
->args
->gs_vtx_offset
[i
& ~1]),
3881 ctx
->gs_wave_id
= ac_unpack_param(&ctx
->ac
,
3882 ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
),
3885 for (int i
= 0; i
< 6; i
++)
3886 ctx
->gs_vtx_offset
[i
] = ac_get_arg(&ctx
->ac
, ctx
->args
->gs_vtx_offset
[i
]);
3887 ctx
->gs_wave_id
= ac_get_arg(&ctx
->ac
, ctx
->args
->gs_wave_id
);
3891 /* Ensure that the esgs ring is declared.
3893 * We declare it with 64KB alignment as a hint that the
3894 * pointer value will always be 0.
3896 static void declare_esgs_ring(struct radv_shader_context
*ctx
)
3901 assert(!LLVMGetNamedGlobal(ctx
->ac
.module
, "esgs_ring"));
3903 ctx
->esgs_ring
= LLVMAddGlobalInAddressSpace(
3904 ctx
->ac
.module
, LLVMArrayType(ctx
->ac
.i32
, 0),
3907 LLVMSetLinkage(ctx
->esgs_ring
, LLVMExternalLinkage
);
3908 LLVMSetAlignment(ctx
->esgs_ring
, 64 * 1024);
3912 LLVMModuleRef
ac_translate_nir_to_llvm(struct ac_llvm_compiler
*ac_llvm
,
3913 struct nir_shader
*const *shaders
,
3915 const struct radv_shader_args
*args
)
3917 struct radv_shader_context ctx
= {0};
3920 enum ac_float_mode float_mode
= AC_FLOAT_MODE_DEFAULT
;
3922 if (args
->shader_info
->float_controls_mode
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
) {
3923 float_mode
= AC_FLOAT_MODE_DENORM_FLUSH_TO_ZERO
;
3926 ac_llvm_context_init(&ctx
.ac
, ac_llvm
, args
->options
->chip_class
,
3927 args
->options
->family
, float_mode
,
3928 args
->shader_info
->wave_size
,
3929 args
->shader_info
->ballot_bit_size
);
3930 ctx
.context
= ctx
.ac
.context
;
3932 ctx
.max_workgroup_size
= 0;
3933 for (int i
= 0; i
< shader_count
; ++i
) {
3934 ctx
.max_workgroup_size
= MAX2(ctx
.max_workgroup_size
,
3935 radv_nir_get_max_workgroup_size(args
->options
->chip_class
,
3936 shaders
[i
]->info
.stage
,
3940 if (ctx
.ac
.chip_class
>= GFX10
) {
3941 if (is_pre_gs_stage(shaders
[0]->info
.stage
) &&
3942 args
->options
->key
.vs_common_out
.as_ngg
) {
3943 ctx
.max_workgroup_size
= 128;
3947 create_function(&ctx
, shaders
[shader_count
- 1]->info
.stage
, shader_count
>= 2);
3949 ctx
.abi
.inputs
= &ctx
.inputs
[0];
3950 ctx
.abi
.emit_outputs
= handle_shader_outputs_post
;
3951 ctx
.abi
.emit_vertex
= visit_emit_vertex
;
3952 ctx
.abi
.load_ubo
= radv_load_ubo
;
3953 ctx
.abi
.load_ssbo
= radv_load_ssbo
;
3954 ctx
.abi
.load_sampler_desc
= radv_get_sampler_desc
;
3955 ctx
.abi
.load_resource
= radv_load_resource
;
3956 ctx
.abi
.clamp_shadow_reference
= false;
3957 ctx
.abi
.robust_buffer_access
= args
->options
->robust_buffer_access
;
3959 bool is_ngg
= is_pre_gs_stage(shaders
[0]->info
.stage
) && args
->options
->key
.vs_common_out
.as_ngg
;
3960 if (shader_count
>= 2 || is_ngg
)
3961 ac_init_exec_full_mask(&ctx
.ac
);
3963 if (args
->ac
.vertex_id
.used
)
3964 ctx
.abi
.vertex_id
= ac_get_arg(&ctx
.ac
, args
->ac
.vertex_id
);
3965 if (args
->rel_auto_id
.used
)
3966 ctx
.rel_auto_id
= ac_get_arg(&ctx
.ac
, args
->rel_auto_id
);
3967 if (args
->ac
.instance_id
.used
)
3968 ctx
.abi
.instance_id
= ac_get_arg(&ctx
.ac
, args
->ac
.instance_id
);
3970 if (args
->options
->has_ls_vgpr_init_bug
&&
3971 shaders
[shader_count
- 1]->info
.stage
== MESA_SHADER_TESS_CTRL
)
3972 ac_nir_fixup_ls_hs_input_vgprs(&ctx
);
3975 /* Declare scratch space base for streamout and vertex
3976 * compaction. Whether space is actually allocated is
3977 * determined during linking / PM4 creation.
3979 * Add an extra dword per vertex to ensure an odd stride, which
3980 * avoids bank conflicts for SoA accesses.
3982 if (!args
->options
->key
.vs_common_out
.as_ngg_passthrough
)
3983 declare_esgs_ring(&ctx
);
3985 /* This is really only needed when streamout and / or vertex
3986 * compaction is enabled.
3988 if (args
->shader_info
->so
.num_outputs
) {
3989 LLVMTypeRef asi32
= LLVMArrayType(ctx
.ac
.i32
, 8);
3990 ctx
.gs_ngg_scratch
= LLVMAddGlobalInAddressSpace(ctx
.ac
.module
,
3991 asi32
, "ngg_scratch", AC_ADDR_SPACE_LDS
);
3992 LLVMSetInitializer(ctx
.gs_ngg_scratch
, LLVMGetUndef(asi32
));
3993 LLVMSetAlignment(ctx
.gs_ngg_scratch
, 4);
3997 for(int i
= 0; i
< shader_count
; ++i
) {
3998 ctx
.stage
= shaders
[i
]->info
.stage
;
3999 ctx
.shader
= shaders
[i
];
4000 ctx
.output_mask
= 0;
4002 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
4003 for (int i
= 0; i
< 4; i
++) {
4004 ctx
.gs_next_vertex
[i
] =
4005 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
4007 if (args
->options
->key
.vs_common_out
.as_ngg
) {
4008 for (unsigned i
= 0; i
< 4; ++i
) {
4009 ctx
.gs_curprim_verts
[i
] =
4010 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
4011 ctx
.gs_generated_prims
[i
] =
4012 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
4015 unsigned scratch_size
= 8;
4016 if (args
->shader_info
->so
.num_outputs
)
4019 LLVMTypeRef ai32
= LLVMArrayType(ctx
.ac
.i32
, scratch_size
);
4020 ctx
.gs_ngg_scratch
=
4021 LLVMAddGlobalInAddressSpace(ctx
.ac
.module
,
4022 ai32
, "ngg_scratch", AC_ADDR_SPACE_LDS
);
4023 LLVMSetInitializer(ctx
.gs_ngg_scratch
, LLVMGetUndef(ai32
));
4024 LLVMSetAlignment(ctx
.gs_ngg_scratch
, 4);
4026 ctx
.gs_ngg_emit
= LLVMAddGlobalInAddressSpace(ctx
.ac
.module
,
4027 LLVMArrayType(ctx
.ac
.i32
, 0), "ngg_emit", AC_ADDR_SPACE_LDS
);
4028 LLVMSetLinkage(ctx
.gs_ngg_emit
, LLVMExternalLinkage
);
4029 LLVMSetAlignment(ctx
.gs_ngg_emit
, 4);
4032 ctx
.abi
.load_inputs
= load_gs_input
;
4033 ctx
.abi
.emit_primitive
= visit_end_primitive
;
4034 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4035 ctx
.abi
.load_tess_varyings
= load_tcs_varyings
;
4036 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
4037 ctx
.abi
.store_tcs_outputs
= store_tcs_output
;
4038 if (shader_count
== 1)
4039 ctx
.tcs_num_inputs
= args
->options
->key
.tcs
.num_inputs
;
4041 ctx
.tcs_num_inputs
= util_last_bit64(args
->shader_info
->vs
.ls_outputs_written
);
4042 ctx
.tcs_num_patches
=
4043 get_tcs_num_patches(
4044 ctx
.args
->options
->key
.tcs
.input_vertices
,
4045 ctx
.shader
->info
.tess
.tcs_vertices_out
,
4047 ctx
.args
->shader_info
->tcs
.outputs_written
,
4048 ctx
.args
->shader_info
->tcs
.patch_outputs_written
,
4049 ctx
.args
->options
->tess_offchip_block_dw_size
,
4050 ctx
.args
->options
->chip_class
,
4051 ctx
.args
->options
->family
);
4052 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4053 ctx
.abi
.load_tess_varyings
= load_tes_input
;
4054 ctx
.abi
.load_tess_coord
= load_tess_coord
;
4055 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
4056 ctx
.tcs_num_patches
= args
->options
->key
.tes
.num_patches
;
4057 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
) {
4058 ctx
.abi
.load_base_vertex
= radv_load_base_vertex
;
4059 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
) {
4060 ctx
.abi
.load_sample_position
= load_sample_position
;
4061 ctx
.abi
.load_sample_mask_in
= load_sample_mask_in
;
4064 if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
&&
4065 args
->options
->key
.vs_common_out
.as_ngg
&&
4066 args
->options
->key
.vs_common_out
.export_prim_id
) {
4067 declare_esgs_ring(&ctx
);
4070 bool nested_barrier
= false;
4073 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
&&
4074 args
->options
->key
.vs_common_out
.as_ngg
) {
4075 gfx10_ngg_gs_emit_prologue(&ctx
);
4076 nested_barrier
= false;
4078 nested_barrier
= true;
4082 if (nested_barrier
) {
4083 /* Execute a barrier before the second shader in
4086 * Execute the barrier inside the conditional block,
4087 * so that empty waves can jump directly to s_endpgm,
4088 * which will also signal the barrier.
4090 * This is possible in gfx9, because an empty wave
4091 * for the second shader does not participate in
4092 * the epilogue. With NGG, empty waves may still
4093 * be required to export data (e.g. GS output vertices),
4094 * so we cannot let them exit early.
4096 * If the shader is TCS and the TCS epilog is present
4097 * and contains a barrier, it will wait there and then
4100 ac_emit_barrier(&ctx
.ac
, ctx
.stage
);
4103 nir_foreach_variable(variable
, &shaders
[i
]->outputs
)
4104 scan_shader_output_decl(&ctx
, variable
, shaders
[i
], shaders
[i
]->info
.stage
);
4106 ac_setup_rings(&ctx
);
4108 LLVMBasicBlockRef merge_block
= NULL
;
4109 if (shader_count
>= 2 || is_ngg
) {
4110 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
4111 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
4112 merge_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
4114 LLVMValueRef count
=
4115 ac_unpack_param(&ctx
.ac
,
4116 ac_get_arg(&ctx
.ac
, args
->merged_wave_info
),
4118 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
.ac
);
4119 LLVMValueRef cond
= LLVMBuildICmp(ctx
.ac
.builder
, LLVMIntULT
,
4120 thread_id
, count
, "");
4121 LLVMBuildCondBr(ctx
.ac
.builder
, cond
, then_block
, merge_block
);
4123 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, then_block
);
4126 if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
)
4127 prepare_interp_optimize(&ctx
, shaders
[i
]);
4128 else if(shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
)
4129 handle_vs_inputs(&ctx
, shaders
[i
]);
4130 else if(shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
)
4131 prepare_gs_input_vgprs(&ctx
, shader_count
>= 2);
4133 ac_nir_translate(&ctx
.ac
, &ctx
.abi
, &args
->ac
, shaders
[i
]);
4135 if (shader_count
>= 2 || is_ngg
) {
4136 LLVMBuildBr(ctx
.ac
.builder
, merge_block
);
4137 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, merge_block
);
4140 /* This needs to be outside the if wrapping the shader body, as sometimes
4141 * the HW generates waves with 0 es/vs threads. */
4142 if (is_pre_gs_stage(shaders
[i
]->info
.stage
) &&
4143 args
->options
->key
.vs_common_out
.as_ngg
&&
4144 i
== shader_count
- 1) {
4145 handle_ngg_outputs_post_2(&ctx
);
4146 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
&&
4147 args
->options
->key
.vs_common_out
.as_ngg
) {
4148 gfx10_ngg_gs_emit_epilogue_2(&ctx
);
4151 if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4152 args
->shader_info
->tcs
.num_patches
= ctx
.tcs_num_patches
;
4153 args
->shader_info
->tcs
.lds_size
=
4154 calculate_tess_lds_size(
4155 ctx
.args
->options
->key
.tcs
.input_vertices
,
4156 ctx
.shader
->info
.tess
.tcs_vertices_out
,
4158 ctx
.tcs_num_patches
,
4159 ctx
.args
->shader_info
->tcs
.outputs_written
,
4160 ctx
.args
->shader_info
->tcs
.patch_outputs_written
);
4164 LLVMBuildRetVoid(ctx
.ac
.builder
);
4166 if (args
->options
->dump_preoptir
) {
4167 fprintf(stderr
, "%s LLVM IR:\n\n",
4168 radv_get_shader_name(args
->shader_info
,
4169 shaders
[shader_count
- 1]->info
.stage
));
4170 ac_dump_module(ctx
.ac
.module
);
4171 fprintf(stderr
, "\n");
4174 ac_llvm_finalize_module(&ctx
, ac_llvm
->passmgr
, args
->options
);
4176 if (shader_count
== 1)
4177 ac_nir_eliminate_const_vs_outputs(&ctx
);
4179 if (args
->options
->dump_shader
) {
4180 args
->shader_info
->private_mem_vgprs
=
4181 ac_count_scratch_private_memory(ctx
.main_function
);
4184 return ctx
.ac
.module
;
4187 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di
, void *context
)
4189 unsigned *retval
= (unsigned *)context
;
4190 LLVMDiagnosticSeverity severity
= LLVMGetDiagInfoSeverity(di
);
4191 char *description
= LLVMGetDiagInfoDescription(di
);
4193 if (severity
== LLVMDSError
) {
4195 fprintf(stderr
, "LLVM triggered Diagnostic Handler: %s\n",
4199 LLVMDisposeMessage(description
);
4202 static unsigned radv_llvm_compile(LLVMModuleRef M
,
4203 char **pelf_buffer
, size_t *pelf_size
,
4204 struct ac_llvm_compiler
*ac_llvm
)
4206 unsigned retval
= 0;
4207 LLVMContextRef llvm_ctx
;
4209 /* Setup Diagnostic Handler*/
4210 llvm_ctx
= LLVMGetModuleContext(M
);
4212 LLVMContextSetDiagnosticHandler(llvm_ctx
, ac_diagnostic_handler
,
4216 if (!radv_compile_to_elf(ac_llvm
, M
, pelf_buffer
, pelf_size
))
4221 static void ac_compile_llvm_module(struct ac_llvm_compiler
*ac_llvm
,
4222 LLVMModuleRef llvm_module
,
4223 struct radv_shader_binary
**rbinary
,
4224 gl_shader_stage stage
,
4226 const struct radv_nir_compiler_options
*options
)
4228 char *elf_buffer
= NULL
;
4229 size_t elf_size
= 0;
4230 char *llvm_ir_string
= NULL
;
4232 if (options
->dump_shader
) {
4233 fprintf(stderr
, "%s LLVM IR:\n\n", name
);
4234 ac_dump_module(llvm_module
);
4235 fprintf(stderr
, "\n");
4238 if (options
->record_ir
) {
4239 char *llvm_ir
= LLVMPrintModuleToString(llvm_module
);
4240 llvm_ir_string
= strdup(llvm_ir
);
4241 LLVMDisposeMessage(llvm_ir
);
4244 int v
= radv_llvm_compile(llvm_module
, &elf_buffer
, &elf_size
, ac_llvm
);
4246 fprintf(stderr
, "compile failed\n");
4249 LLVMContextRef ctx
= LLVMGetModuleContext(llvm_module
);
4250 LLVMDisposeModule(llvm_module
);
4251 LLVMContextDispose(ctx
);
4253 size_t llvm_ir_size
= llvm_ir_string
? strlen(llvm_ir_string
) : 0;
4254 size_t alloc_size
= sizeof(struct radv_shader_binary_rtld
) + elf_size
+ llvm_ir_size
+ 1;
4255 struct radv_shader_binary_rtld
*rbin
= calloc(1, alloc_size
);
4256 memcpy(rbin
->data
, elf_buffer
, elf_size
);
4258 memcpy(rbin
->data
+ elf_size
, llvm_ir_string
, llvm_ir_size
+ 1);
4260 rbin
->base
.type
= RADV_BINARY_TYPE_RTLD
;
4261 rbin
->base
.stage
= stage
;
4262 rbin
->base
.total_size
= alloc_size
;
4263 rbin
->elf_size
= elf_size
;
4264 rbin
->llvm_ir_size
= llvm_ir_size
;
4265 *rbinary
= &rbin
->base
;
4267 free(llvm_ir_string
);
4272 radv_compile_nir_shader(struct ac_llvm_compiler
*ac_llvm
,
4273 struct radv_shader_binary
**rbinary
,
4274 const struct radv_shader_args
*args
,
4275 struct nir_shader
*const *nir
,
4279 LLVMModuleRef llvm_module
;
4281 llvm_module
= ac_translate_nir_to_llvm(ac_llvm
, nir
, nir_count
, args
);
4283 ac_compile_llvm_module(ac_llvm
, llvm_module
, rbinary
,
4284 nir
[nir_count
- 1]->info
.stage
,
4285 radv_get_shader_name(args
->shader_info
,
4286 nir
[nir_count
- 1]->info
.stage
),
4289 /* Determine the ES type (VS or TES) for the GS on GFX9. */
4290 if (args
->options
->chip_class
>= GFX9
) {
4291 if (nir_count
== 2 &&
4292 nir
[1]->info
.stage
== MESA_SHADER_GEOMETRY
) {
4293 args
->shader_info
->gs
.es_type
= nir
[0]->info
.stage
;
4299 ac_gs_copy_shader_emit(struct radv_shader_context
*ctx
)
4301 LLVMValueRef vtx_offset
=
4302 LLVMBuildMul(ctx
->ac
.builder
, ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.vertex_id
),
4303 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
4304 LLVMValueRef stream_id
;
4306 /* Fetch the vertex stream ID. */
4307 if (!ctx
->args
->options
->use_ngg_streamout
&&
4308 ctx
->args
->shader_info
->so
.num_outputs
) {
4310 ac_unpack_param(&ctx
->ac
,
4311 ac_get_arg(&ctx
->ac
,
4312 ctx
->args
->streamout_config
),
4315 stream_id
= ctx
->ac
.i32_0
;
4318 LLVMBasicBlockRef end_bb
;
4319 LLVMValueRef switch_inst
;
4321 end_bb
= LLVMAppendBasicBlockInContext(ctx
->ac
.context
,
4322 ctx
->main_function
, "end");
4323 switch_inst
= LLVMBuildSwitch(ctx
->ac
.builder
, stream_id
, end_bb
, 4);
4325 for (unsigned stream
= 0; stream
< 4; stream
++) {
4326 unsigned num_components
=
4327 ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
];
4328 LLVMBasicBlockRef bb
;
4331 if (stream
> 0 && !num_components
)
4334 if (stream
> 0 && !ctx
->args
->shader_info
->so
.num_outputs
)
4337 bb
= LLVMInsertBasicBlockInContext(ctx
->ac
.context
, end_bb
, "out");
4338 LLVMAddCase(switch_inst
, LLVMConstInt(ctx
->ac
.i32
, stream
, 0), bb
);
4339 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, bb
);
4342 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
4343 unsigned output_usage_mask
=
4344 ctx
->args
->shader_info
->gs
.output_usage_mask
[i
];
4345 unsigned output_stream
=
4346 ctx
->args
->shader_info
->gs
.output_streams
[i
];
4347 int length
= util_last_bit(output_usage_mask
);
4349 if (!(ctx
->output_mask
& (1ull << i
)) ||
4350 output_stream
!= stream
)
4353 for (unsigned j
= 0; j
< length
; j
++) {
4354 LLVMValueRef value
, soffset
;
4356 if (!(output_usage_mask
& (1 << j
)))
4359 soffset
= LLVMConstInt(ctx
->ac
.i32
,
4361 ctx
->shader
->info
.gs
.vertices_out
* 16 * 4, false);
4365 value
= ac_build_buffer_load(&ctx
->ac
,
4368 vtx_offset
, soffset
,
4369 0, ac_glc
| ac_slc
, true, false);
4371 LLVMTypeRef type
= LLVMGetAllocatedType(ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
4372 if (ac_get_type_size(type
) == 2) {
4373 value
= LLVMBuildBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
4374 value
= LLVMBuildTrunc(ctx
->ac
.builder
, value
, ctx
->ac
.i16
, "");
4377 LLVMBuildStore(ctx
->ac
.builder
,
4378 ac_to_float(&ctx
->ac
, value
), ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
4382 if (!ctx
->args
->options
->use_ngg_streamout
&&
4383 ctx
->args
->shader_info
->so
.num_outputs
)
4384 radv_emit_streamout(ctx
, stream
);
4387 handle_vs_outputs_post(ctx
, false, true,
4388 &ctx
->args
->shader_info
->vs
.outinfo
);
4391 LLVMBuildBr(ctx
->ac
.builder
, end_bb
);
4394 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, end_bb
);
4398 radv_compile_gs_copy_shader(struct ac_llvm_compiler
*ac_llvm
,
4399 struct nir_shader
*geom_shader
,
4400 struct radv_shader_binary
**rbinary
,
4401 const struct radv_shader_args
*args
)
4403 struct radv_shader_context ctx
= {0};
4406 assert(args
->is_gs_copy_shader
);
4408 ac_llvm_context_init(&ctx
.ac
, ac_llvm
, args
->options
->chip_class
,
4409 args
->options
->family
, AC_FLOAT_MODE_DEFAULT
, 64, 64);
4410 ctx
.context
= ctx
.ac
.context
;
4412 ctx
.stage
= MESA_SHADER_VERTEX
;
4413 ctx
.shader
= geom_shader
;
4415 create_function(&ctx
, MESA_SHADER_VERTEX
, false);
4417 ac_setup_rings(&ctx
);
4419 nir_foreach_variable(variable
, &geom_shader
->outputs
) {
4420 scan_shader_output_decl(&ctx
, variable
, geom_shader
, MESA_SHADER_VERTEX
);
4421 ac_handle_shader_output_decl(&ctx
.ac
, &ctx
.abi
, geom_shader
,
4422 variable
, MESA_SHADER_VERTEX
);
4425 ac_gs_copy_shader_emit(&ctx
);
4427 LLVMBuildRetVoid(ctx
.ac
.builder
);
4429 ac_llvm_finalize_module(&ctx
, ac_llvm
->passmgr
, args
->options
);
4431 ac_compile_llvm_module(ac_llvm
, ctx
.ac
.module
, rbinary
,
4432 MESA_SHADER_VERTEX
, "GS Copy Shader", args
->options
);
4433 (*rbinary
)->is_gs_copy_shader
= true;
4438 llvm_compile_shader(struct radv_device
*device
,
4439 unsigned shader_count
,
4440 struct nir_shader
*const *shaders
,
4441 struct radv_shader_binary
**binary
,
4442 struct radv_shader_args
*args
)
4444 enum ac_target_machine_options tm_options
= 0;
4445 struct ac_llvm_compiler ac_llvm
;
4446 bool thread_compiler
;
4448 tm_options
|= AC_TM_SUPPORTS_SPILL
;
4449 if (args
->options
->check_ir
)
4450 tm_options
|= AC_TM_CHECK_IR
;
4451 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_LOAD_STORE_OPT
)
4452 tm_options
|= AC_TM_NO_LOAD_STORE_OPT
;
4454 thread_compiler
= !(device
->instance
->debug_flags
& RADV_DEBUG_NOTHREADLLVM
);
4456 radv_init_llvm_compiler(&ac_llvm
, thread_compiler
,
4457 args
->options
->family
, tm_options
,
4458 args
->shader_info
->wave_size
);
4460 if (args
->is_gs_copy_shader
) {
4461 radv_compile_gs_copy_shader(&ac_llvm
, *shaders
, binary
, args
);
4463 radv_compile_nir_shader(&ac_llvm
, binary
, args
,
4464 shaders
, shader_count
);
4467 radv_destroy_llvm_compiler(&ac_llvm
, thread_compiler
);