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85128ed07981fd2473d85621b3da3f1b2c312103
[mesa.git] / src / amd / vulkan / radv_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "radv_shader_helper.h"
31 #include "radv_shader_args.h"
32 #include "radv_debug.h"
33 #include "nir/nir.h"
34
35 #include "sid.h"
36 #include "ac_binary.h"
37 #include "ac_llvm_util.h"
38 #include "ac_llvm_build.h"
39 #include "ac_shader_abi.h"
40 #include "ac_shader_util.h"
41 #include "ac_exp_param.h"
42
43 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
44
45 struct radv_shader_context {
46 struct ac_llvm_context ac;
47 const struct nir_shader *shader;
48 struct ac_shader_abi abi;
49 const struct radv_shader_args *args;
50
51 gl_shader_stage stage;
52
53 unsigned max_workgroup_size;
54 LLVMContextRef context;
55 LLVMValueRef main_function;
56
57 LLVMValueRef descriptor_sets[MAX_SETS];
58
59 LLVMValueRef ring_offsets;
60
61 LLVMValueRef rel_auto_id;
62
63 LLVMValueRef gs_wave_id;
64 LLVMValueRef gs_vtx_offset[6];
65
66 LLVMValueRef esgs_ring;
67 LLVMValueRef gsvs_ring[4];
68 LLVMValueRef hs_ring_tess_offchip;
69 LLVMValueRef hs_ring_tess_factor;
70
71 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
72
73 uint64_t output_mask;
74
75 LLVMValueRef gs_next_vertex[4];
76 LLVMValueRef gs_curprim_verts[4];
77 LLVMValueRef gs_generated_prims[4];
78 LLVMValueRef gs_ngg_emit;
79 LLVMValueRef gs_ngg_scratch;
80
81 uint32_t tcs_num_inputs;
82 uint32_t tcs_num_patches;
83
84 LLVMValueRef vertexptr; /* GFX10 only */
85 };
86
87 struct radv_shader_output_values {
88 LLVMValueRef values[4];
89 unsigned slot_name;
90 unsigned slot_index;
91 unsigned usage_mask;
92 };
93
94 static inline struct radv_shader_context *
95 radv_shader_context_from_abi(struct ac_shader_abi *abi)
96 {
97 struct radv_shader_context *ctx = NULL;
98 return container_of(abi, ctx, abi);
99 }
100
101 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
102 {
103 switch (ctx->stage) {
104 case MESA_SHADER_TESS_CTRL:
105 return ac_unpack_param(&ctx->ac,
106 ac_get_arg(&ctx->ac, ctx->args->ac.tcs_rel_ids),
107 0, 8);
108 case MESA_SHADER_TESS_EVAL:
109 return ac_get_arg(&ctx->ac, ctx->args->tes_rel_patch_id);
110 break;
111 default:
112 unreachable("Illegal stage");
113 }
114 }
115
116 /* Tessellation shaders pass outputs to the next shader using LDS.
117 *
118 * LS outputs = TCS inputs
119 * TCS outputs = TES inputs
120 *
121 * The LDS layout is:
122 * - TCS inputs for patch 0
123 * - TCS inputs for patch 1
124 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
125 * - ...
126 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
127 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
128 * - TCS outputs for patch 1
129 * - Per-patch TCS outputs for patch 1
130 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
131 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
132 * - ...
133 *
134 * All three shaders VS(LS), TCS, TES share the same LDS space.
135 */
136 static LLVMValueRef
137 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
138 {
139 assert(ctx->stage == MESA_SHADER_TESS_CTRL);
140 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
141 uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * input_vertex_size;
142
143 input_patch_size /= 4;
144 return LLVMConstInt(ctx->ac.i32, input_patch_size, false);
145 }
146
147 static LLVMValueRef
148 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
149 {
150 uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
151 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->args->shader_info->tcs.patch_outputs_written);
152 uint32_t output_vertex_size = num_tcs_outputs * 16;
153 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
154 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
155 output_patch_size /= 4;
156 return LLVMConstInt(ctx->ac.i32, output_patch_size, false);
157 }
158
159 static LLVMValueRef
160 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
161 {
162 uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
163 uint32_t output_vertex_size = num_tcs_outputs * 16;
164 output_vertex_size /= 4;
165 return LLVMConstInt(ctx->ac.i32, output_vertex_size, false);
166 }
167
168 static LLVMValueRef
169 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
170 {
171 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
172 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
173 uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * input_vertex_size;
174 uint32_t output_patch0_offset = input_patch_size;
175 unsigned num_patches = ctx->tcs_num_patches;
176
177 output_patch0_offset *= num_patches;
178 output_patch0_offset /= 4;
179 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
180 }
181
182 static LLVMValueRef
183 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
184 {
185 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
186 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
187 uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * input_vertex_size;
188 uint32_t output_patch0_offset = input_patch_size;
189
190 uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
191 uint32_t output_vertex_size = num_tcs_outputs * 16;
192 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
193 unsigned num_patches = ctx->tcs_num_patches;
194
195 output_patch0_offset *= num_patches;
196 output_patch0_offset += pervertex_output_patch_size;
197 output_patch0_offset /= 4;
198 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
199 }
200
201 static LLVMValueRef
202 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
203 {
204 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
205 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
206
207 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
208 }
209
210 static LLVMValueRef
211 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
212 {
213 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
214 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
215 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
216
217 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
218 patch0_offset);
219 }
220
221 static LLVMValueRef
222 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
223 {
224 LLVMValueRef patch0_patch_data_offset =
225 get_tcs_out_patch0_patch_data_offset(ctx);
226 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
227 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
228
229 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
230 patch0_patch_data_offset);
231 }
232
233 static LLVMValueRef
234 create_llvm_function(struct ac_llvm_context *ctx, LLVMModuleRef module,
235 LLVMBuilderRef builder,
236 const struct ac_shader_args *args,
237 enum ac_llvm_calling_convention convention,
238 unsigned max_workgroup_size,
239 const struct radv_nir_compiler_options *options)
240 {
241 LLVMValueRef main_function =
242 ac_build_main(args, ctx, convention, "main", ctx->voidt, module);
243
244 if (options->address32_hi) {
245 ac_llvm_add_target_dep_function_attr(main_function,
246 "amdgpu-32bit-address-high-bits",
247 options->address32_hi);
248 }
249
250 ac_llvm_set_workgroup_size(main_function, max_workgroup_size);
251
252 return main_function;
253 }
254
255 static void
256 load_descriptor_sets(struct radv_shader_context *ctx)
257 {
258 uint32_t mask = ctx->args->shader_info->desc_set_used_mask;
259 if (ctx->args->shader_info->need_indirect_descriptor_sets) {
260 LLVMValueRef desc_sets =
261 ac_get_arg(&ctx->ac, ctx->args->descriptor_sets[0]);
262 while (mask) {
263 int i = u_bit_scan(&mask);
264
265 ctx->descriptor_sets[i] =
266 ac_build_load_to_sgpr(&ctx->ac, desc_sets,
267 LLVMConstInt(ctx->ac.i32, i, false));
268
269 }
270 } else {
271 while (mask) {
272 int i = u_bit_scan(&mask);
273
274 ctx->descriptor_sets[i] =
275 ac_get_arg(&ctx->ac, ctx->args->descriptor_sets[i]);
276 }
277 }
278 }
279
280 static enum ac_llvm_calling_convention
281 get_llvm_calling_convention(LLVMValueRef func, gl_shader_stage stage)
282 {
283 switch (stage) {
284 case MESA_SHADER_VERTEX:
285 case MESA_SHADER_TESS_EVAL:
286 return AC_LLVM_AMDGPU_VS;
287 break;
288 case MESA_SHADER_GEOMETRY:
289 return AC_LLVM_AMDGPU_GS;
290 break;
291 case MESA_SHADER_TESS_CTRL:
292 return AC_LLVM_AMDGPU_HS;
293 break;
294 case MESA_SHADER_FRAGMENT:
295 return AC_LLVM_AMDGPU_PS;
296 break;
297 case MESA_SHADER_COMPUTE:
298 return AC_LLVM_AMDGPU_CS;
299 break;
300 default:
301 unreachable("Unhandle shader type");
302 }
303 }
304
305 /* Returns whether the stage is a stage that can be directly before the GS */
306 static bool is_pre_gs_stage(gl_shader_stage stage)
307 {
308 return stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL;
309 }
310
311 static void create_function(struct radv_shader_context *ctx,
312 gl_shader_stage stage,
313 bool has_previous_stage)
314 {
315 if (ctx->ac.chip_class >= GFX10) {
316 if (is_pre_gs_stage(stage) && ctx->args->options->key.vs_common_out.as_ngg) {
317 /* On GFX10, VS is merged into GS for NGG. */
318 stage = MESA_SHADER_GEOMETRY;
319 has_previous_stage = true;
320 }
321 }
322
323 ctx->main_function = create_llvm_function(
324 &ctx->ac, ctx->ac.module, ctx->ac.builder, &ctx->args->ac,
325 get_llvm_calling_convention(ctx->main_function, stage),
326 ctx->max_workgroup_size,
327 ctx->args->options);
328
329 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
330 LLVMPointerType(ctx->ac.i8, AC_ADDR_SPACE_CONST),
331 NULL, 0, AC_FUNC_ATTR_READNONE);
332 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
333 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
334
335 load_descriptor_sets(ctx);
336
337 if (stage == MESA_SHADER_TESS_CTRL ||
338 (stage == MESA_SHADER_VERTEX && ctx->args->options->key.vs_common_out.as_ls) ||
339 /* GFX9 has the ESGS ring buffer in LDS. */
340 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
341 ac_declare_lds_as_pointer(&ctx->ac);
342 }
343
344 }
345
346
347 static LLVMValueRef
348 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
349 unsigned desc_set, unsigned binding)
350 {
351 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
352 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
353 struct radv_pipeline_layout *pipeline_layout = ctx->args->options->layout;
354 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
355 unsigned base_offset = layout->binding[binding].offset;
356 LLVMValueRef offset, stride;
357
358 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
359 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
360 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
361 layout->binding[binding].dynamic_offset_offset;
362 desc_ptr = ac_get_arg(&ctx->ac, ctx->args->ac.push_constants);
363 base_offset = pipeline_layout->push_constant_size + 16 * idx;
364 stride = LLVMConstInt(ctx->ac.i32, 16, false);
365 } else
366 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
367
368 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
369
370 if (layout->binding[binding].type != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
371 offset = ac_build_imad(&ctx->ac, index, stride, offset);
372 }
373
374 desc_ptr = LLVMBuildGEP(ctx->ac.builder, desc_ptr, &offset, 1, "");
375 desc_ptr = ac_cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
376 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
377
378 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
379 uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
380 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
381 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
382 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
383
384 if (ctx->ac.chip_class >= GFX10) {
385 desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
386 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
387 S_008F0C_RESOURCE_LEVEL(1);
388 } else {
389 desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
390 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
391 }
392
393 LLVMValueRef desc_components[4] = {
394 LLVMBuildPtrToInt(ctx->ac.builder, desc_ptr, ctx->ac.intptr, ""),
395 LLVMConstInt(ctx->ac.i32, S_008F04_BASE_ADDRESS_HI(ctx->args->options->address32_hi), false),
396 /* High limit to support variable sizes. */
397 LLVMConstInt(ctx->ac.i32, 0xffffffff, false),
398 LLVMConstInt(ctx->ac.i32, desc_type, false),
399 };
400
401 return ac_build_gather_values(&ctx->ac, desc_components, 4);
402 }
403
404 return desc_ptr;
405 }
406
407
408 /* The offchip buffer layout for TCS->TES is
409 *
410 * - attribute 0 of patch 0 vertex 0
411 * - attribute 0 of patch 0 vertex 1
412 * - attribute 0 of patch 0 vertex 2
413 * ...
414 * - attribute 0 of patch 1 vertex 0
415 * - attribute 0 of patch 1 vertex 1
416 * ...
417 * - attribute 1 of patch 0 vertex 0
418 * - attribute 1 of patch 0 vertex 1
419 * ...
420 * - per patch attribute 0 of patch 0
421 * - per patch attribute 0 of patch 1
422 * ...
423 *
424 * Note that every attribute has 4 components.
425 */
426 static LLVMValueRef get_non_vertex_index_offset(struct radv_shader_context *ctx)
427 {
428 uint32_t num_patches = ctx->tcs_num_patches;
429 uint32_t num_tcs_outputs;
430 if (ctx->stage == MESA_SHADER_TESS_CTRL)
431 num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
432 else
433 num_tcs_outputs = ctx->args->options->key.tes.tcs_num_outputs;
434
435 uint32_t output_vertex_size = num_tcs_outputs * 16;
436 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
437
438 return LLVMConstInt(ctx->ac.i32, pervertex_output_patch_size * num_patches, false);
439 }
440
441 static LLVMValueRef calc_param_stride(struct radv_shader_context *ctx,
442 LLVMValueRef vertex_index)
443 {
444 LLVMValueRef param_stride;
445 if (vertex_index)
446 param_stride = LLVMConstInt(ctx->ac.i32, ctx->shader->info.tess.tcs_vertices_out * ctx->tcs_num_patches, false);
447 else
448 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_num_patches, false);
449 return param_stride;
450 }
451
452 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
453 LLVMValueRef vertex_index,
454 LLVMValueRef param_index)
455 {
456 LLVMValueRef base_addr;
457 LLVMValueRef param_stride, constant16;
458 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
459 LLVMValueRef vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->shader->info.tess.tcs_vertices_out, false);
460 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
461 param_stride = calc_param_stride(ctx, vertex_index);
462 if (vertex_index) {
463 base_addr = ac_build_imad(&ctx->ac, rel_patch_id,
464 vertices_per_patch, vertex_index);
465 } else {
466 base_addr = rel_patch_id;
467 }
468
469 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
470 LLVMBuildMul(ctx->ac.builder, param_index,
471 param_stride, ""), "");
472
473 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
474
475 if (!vertex_index) {
476 LLVMValueRef patch_data_offset = get_non_vertex_index_offset(ctx);
477
478 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
479 patch_data_offset, "");
480 }
481 return base_addr;
482 }
483
484 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
485 unsigned param,
486 unsigned const_index,
487 bool is_compact,
488 LLVMValueRef vertex_index,
489 LLVMValueRef indir_index)
490 {
491 LLVMValueRef param_index;
492
493 if (indir_index)
494 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
495 indir_index, "");
496 else {
497 if (const_index && !is_compact)
498 param += const_index;
499 param_index = LLVMConstInt(ctx->ac.i32, param, false);
500 }
501 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
502 }
503
504 static LLVMValueRef
505 get_dw_address(struct radv_shader_context *ctx,
506 LLVMValueRef dw_addr,
507 unsigned param,
508 unsigned const_index,
509 bool compact_const_index,
510 LLVMValueRef vertex_index,
511 LLVMValueRef stride,
512 LLVMValueRef indir_index)
513
514 {
515
516 if (vertex_index) {
517 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
518 LLVMBuildMul(ctx->ac.builder,
519 vertex_index,
520 stride, ""), "");
521 }
522
523 if (indir_index)
524 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
525 LLVMBuildMul(ctx->ac.builder, indir_index,
526 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
527 else if (const_index && !compact_const_index)
528 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
529 LLVMConstInt(ctx->ac.i32, const_index * 4, false), "");
530
531 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
532 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
533
534 if (const_index && compact_const_index)
535 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
536 LLVMConstInt(ctx->ac.i32, const_index, false), "");
537 return dw_addr;
538 }
539
540 static LLVMValueRef
541 load_tcs_varyings(struct ac_shader_abi *abi,
542 LLVMTypeRef type,
543 LLVMValueRef vertex_index,
544 LLVMValueRef indir_index,
545 unsigned const_index,
546 unsigned location,
547 unsigned driver_location,
548 unsigned component,
549 unsigned num_components,
550 bool is_patch,
551 bool is_compact,
552 bool load_input)
553 {
554 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
555 LLVMValueRef dw_addr, stride;
556 LLVMValueRef value[4], result;
557 unsigned param = shader_io_get_unique_index(location);
558
559 if (load_input) {
560 uint32_t input_vertex_size = (ctx->tcs_num_inputs * 16) / 4;
561 stride = LLVMConstInt(ctx->ac.i32, input_vertex_size, false);
562 dw_addr = get_tcs_in_current_patch_offset(ctx);
563 } else {
564 if (!is_patch) {
565 stride = get_tcs_out_vertex_stride(ctx);
566 dw_addr = get_tcs_out_current_patch_offset(ctx);
567 } else {
568 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
569 stride = NULL;
570 }
571 }
572
573 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
574 indir_index);
575
576 for (unsigned i = 0; i < num_components + component; i++) {
577 value[i] = ac_lds_load(&ctx->ac, dw_addr);
578 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
579 ctx->ac.i32_1, "");
580 }
581 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
582 return result;
583 }
584
585 static void
586 store_tcs_output(struct ac_shader_abi *abi,
587 const nir_variable *var,
588 LLVMValueRef vertex_index,
589 LLVMValueRef param_index,
590 unsigned const_index,
591 LLVMValueRef src,
592 unsigned writemask)
593 {
594 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
595 const unsigned location = var->data.location;
596 unsigned component = var->data.location_frac;
597 const bool is_patch = var->data.patch;
598 const bool is_compact = var->data.compact;
599 LLVMValueRef dw_addr;
600 LLVMValueRef stride = NULL;
601 LLVMValueRef buf_addr = NULL;
602 LLVMValueRef oc_lds = ac_get_arg(&ctx->ac, ctx->args->oc_lds);
603 unsigned param;
604 bool store_lds = true;
605
606 if (is_patch) {
607 if (!(ctx->shader->info.patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
608 store_lds = false;
609 } else {
610 if (!(ctx->shader->info.outputs_read & (1ULL << location)))
611 store_lds = false;
612 }
613
614 param = shader_io_get_unique_index(location);
615 if ((location == VARYING_SLOT_CLIP_DIST0 || location == VARYING_SLOT_CLIP_DIST1) && is_compact) {
616 const_index += component;
617 component = 0;
618
619 if (const_index >= 4) {
620 const_index -= 4;
621 param++;
622 }
623 }
624
625 if (!is_patch) {
626 stride = get_tcs_out_vertex_stride(ctx);
627 dw_addr = get_tcs_out_current_patch_offset(ctx);
628 } else {
629 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
630 }
631
632 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
633 param_index);
634 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
635 vertex_index, param_index);
636
637 bool is_tess_factor = false;
638 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
639 location == VARYING_SLOT_TESS_LEVEL_OUTER)
640 is_tess_factor = true;
641
642 unsigned base = is_compact ? const_index : 0;
643 for (unsigned chan = 0; chan < 8; chan++) {
644 if (!(writemask & (1 << chan)))
645 continue;
646 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
647 value = ac_to_integer(&ctx->ac, value);
648 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
649
650 if (store_lds || is_tess_factor) {
651 LLVMValueRef dw_addr_chan =
652 LLVMBuildAdd(ctx->ac.builder, dw_addr,
653 LLVMConstInt(ctx->ac.i32, chan, false), "");
654 ac_lds_store(&ctx->ac, dw_addr_chan, value);
655 }
656
657 if (!is_tess_factor && writemask != 0xF)
658 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
659 buf_addr, oc_lds,
660 4 * (base + chan), ac_glc);
661 }
662
663 if (writemask == 0xF) {
664 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
665 buf_addr, oc_lds,
666 (base * 4), ac_glc);
667 }
668 }
669
670 static LLVMValueRef
671 load_tes_input(struct ac_shader_abi *abi,
672 LLVMTypeRef type,
673 LLVMValueRef vertex_index,
674 LLVMValueRef param_index,
675 unsigned const_index,
676 unsigned location,
677 unsigned driver_location,
678 unsigned component,
679 unsigned num_components,
680 bool is_patch,
681 bool is_compact,
682 bool load_input)
683 {
684 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
685 LLVMValueRef buf_addr;
686 LLVMValueRef result;
687 LLVMValueRef oc_lds = ac_get_arg(&ctx->ac, ctx->args->oc_lds);
688 unsigned param = shader_io_get_unique_index(location);
689
690 if ((location == VARYING_SLOT_CLIP_DIST0 || location == VARYING_SLOT_CLIP_DIST1) && is_compact) {
691 const_index += component;
692 component = 0;
693 if (const_index >= 4) {
694 const_index -= 4;
695 param++;
696 }
697 }
698
699 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
700 is_compact, vertex_index, param_index);
701
702 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
703 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
704
705 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
706 buf_addr, oc_lds, is_compact ? (4 * const_index) : 0, ac_glc, true, false);
707 result = ac_trim_vector(&ctx->ac, result, num_components);
708 return result;
709 }
710
711 static LLVMValueRef
712 radv_emit_fetch_64bit(struct radv_shader_context *ctx,
713 LLVMTypeRef type, LLVMValueRef a, LLVMValueRef b)
714 {
715 LLVMValueRef values[2] = {
716 ac_to_integer(&ctx->ac, a),
717 ac_to_integer(&ctx->ac, b),
718 };
719 LLVMValueRef result = ac_build_gather_values(&ctx->ac, values, 2);
720 return LLVMBuildBitCast(ctx->ac.builder, result, type, "");
721 }
722
723 static LLVMValueRef
724 load_gs_input(struct ac_shader_abi *abi,
725 unsigned location,
726 unsigned driver_location,
727 unsigned component,
728 unsigned num_components,
729 unsigned vertex_index,
730 unsigned const_index,
731 LLVMTypeRef type)
732 {
733 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
734 LLVMValueRef vtx_offset;
735 unsigned param, vtx_offset_param;
736 LLVMValueRef value[4], result;
737
738 vtx_offset_param = vertex_index;
739 assert(vtx_offset_param < 6);
740 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
741 LLVMConstInt(ctx->ac.i32, 4, false), "");
742
743 param = shader_io_get_unique_index(location);
744
745 for (unsigned i = component; i < num_components + component; i++) {
746 if (ctx->ac.chip_class >= GFX9) {
747 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
748 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
749 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
750 value[i] = ac_lds_load(&ctx->ac, dw_addr);
751
752 if (ac_get_type_size(type) == 8) {
753 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
754 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index + 1, 0), "");
755 LLVMValueRef tmp = ac_lds_load(&ctx->ac, dw_addr);
756
757 value[i] = radv_emit_fetch_64bit(ctx, type, value[i], tmp);
758 }
759 } else {
760 LLVMValueRef soffset =
761 LLVMConstInt(ctx->ac.i32,
762 (param * 4 + i + const_index) * 256,
763 false);
764
765 value[i] = ac_build_buffer_load(&ctx->ac,
766 ctx->esgs_ring, 1,
767 ctx->ac.i32_0,
768 vtx_offset, soffset,
769 0, ac_glc, true, false);
770
771 if (ac_get_type_size(type) == 8) {
772 soffset = LLVMConstInt(ctx->ac.i32,
773 (param * 4 + i + const_index + 1) * 256,
774 false);
775
776 LLVMValueRef tmp =
777 ac_build_buffer_load(&ctx->ac,
778 ctx->esgs_ring, 1,
779 ctx->ac.i32_0,
780 vtx_offset, soffset,
781 0, ac_glc, true, false);
782
783 value[i] = radv_emit_fetch_64bit(ctx, type, value[i], tmp);
784 }
785 }
786
787 if (ac_get_type_size(type) == 2) {
788 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], ctx->ac.i32, "");
789 value[i] = LLVMBuildTrunc(ctx->ac.builder, value[i], ctx->ac.i16, "");
790 }
791 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], type, "");
792 }
793 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
794 result = ac_to_integer(&ctx->ac, result);
795 return result;
796 }
797
798 static uint32_t
799 radv_get_sample_pos_offset(uint32_t num_samples)
800 {
801 uint32_t sample_pos_offset = 0;
802
803 switch (num_samples) {
804 case 2:
805 sample_pos_offset = 1;
806 break;
807 case 4:
808 sample_pos_offset = 3;
809 break;
810 case 8:
811 sample_pos_offset = 7;
812 break;
813 default:
814 break;
815 }
816 return sample_pos_offset;
817 }
818
819 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
820 LLVMValueRef sample_id)
821 {
822 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
823
824 LLVMValueRef result;
825 LLVMValueRef index = LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false);
826 LLVMValueRef ptr = LLVMBuildGEP(ctx->ac.builder, ctx->ring_offsets, &index, 1, "");
827
828 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
829 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
830
831 uint32_t sample_pos_offset =
832 radv_get_sample_pos_offset(ctx->args->options->key.fs.num_samples);
833
834 sample_id =
835 LLVMBuildAdd(ctx->ac.builder, sample_id,
836 LLVMConstInt(ctx->ac.i32, sample_pos_offset, false), "");
837 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
838
839 return result;
840 }
841
842
843 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
844 {
845 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
846 uint8_t log2_ps_iter_samples;
847
848 if (ctx->args->shader_info->ps.force_persample) {
849 log2_ps_iter_samples =
850 util_logbase2(ctx->args->options->key.fs.num_samples);
851 } else {
852 log2_ps_iter_samples = ctx->args->options->key.fs.log2_ps_iter_samples;
853 }
854
855 /* The bit pattern matches that used by fixed function fragment
856 * processing. */
857 static const uint16_t ps_iter_masks[] = {
858 0xffff, /* not used */
859 0x5555,
860 0x1111,
861 0x0101,
862 0x0001,
863 };
864 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
865
866 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
867
868 LLVMValueRef result, sample_id;
869 sample_id = ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->ac.ancillary), 8, 4);
870 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
871 result = LLVMBuildAnd(ctx->ac.builder, sample_id,
872 ac_get_arg(&ctx->ac, ctx->args->ac.sample_coverage), "");
873 return result;
874 }
875
876
877 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context *ctx,
878 unsigned stream,
879 LLVMValueRef vertexidx,
880 LLVMValueRef *addrs);
881
882 static void
883 visit_emit_vertex_with_counter(struct ac_shader_abi *abi, unsigned stream,
884 LLVMValueRef vertexidx, LLVMValueRef *addrs)
885 {
886 unsigned offset = 0;
887 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
888
889 if (ctx->args->options->key.vs_common_out.as_ngg) {
890 gfx10_ngg_gs_emit_vertex(ctx, stream, vertexidx, addrs);
891 return;
892 }
893
894 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
895 unsigned output_usage_mask =
896 ctx->args->shader_info->gs.output_usage_mask[i];
897 uint8_t output_stream =
898 ctx->args->shader_info->gs.output_streams[i];
899 LLVMValueRef *out_ptr = &addrs[i * 4];
900 int length = util_last_bit(output_usage_mask);
901
902 if (!(ctx->output_mask & (1ull << i)) ||
903 output_stream != stream)
904 continue;
905
906 for (unsigned j = 0; j < length; j++) {
907 if (!(output_usage_mask & (1 << j)))
908 continue;
909
910 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
911 out_ptr[j], "");
912 LLVMValueRef voffset =
913 LLVMConstInt(ctx->ac.i32, offset *
914 ctx->shader->info.gs.vertices_out, false);
915
916 offset++;
917
918 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, vertexidx, "");
919 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
920
921 out_val = ac_to_integer(&ctx->ac, out_val);
922 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
923
924 ac_build_buffer_store_dword(&ctx->ac,
925 ctx->gsvs_ring[stream],
926 out_val, 1,
927 voffset,
928 ac_get_arg(&ctx->ac,
929 ctx->args->gs2vs_offset),
930 0, ac_glc | ac_slc | ac_swizzled);
931 }
932 }
933
934 ac_build_sendmsg(&ctx->ac,
935 AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
936 ctx->gs_wave_id);
937 }
938
939 static void
940 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
941 {
942 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
943
944 if (ctx->args->options->key.vs_common_out.as_ngg) {
945 LLVMBuildStore(ctx->ac.builder, ctx->ac.i32_0, ctx->gs_curprim_verts[stream]);
946 return;
947 }
948
949 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
950 }
951
952 static LLVMValueRef
953 load_tess_coord(struct ac_shader_abi *abi)
954 {
955 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
956
957 LLVMValueRef coord[4] = {
958 ac_get_arg(&ctx->ac, ctx->args->tes_u),
959 ac_get_arg(&ctx->ac, ctx->args->tes_v),
960 ctx->ac.f32_0,
961 ctx->ac.f32_0,
962 };
963
964 if (ctx->shader->info.tess.primitive_mode == GL_TRIANGLES)
965 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
966 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
967
968 return ac_build_gather_values(&ctx->ac, coord, 3);
969 }
970
971 static LLVMValueRef
972 load_patch_vertices_in(struct ac_shader_abi *abi)
973 {
974 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
975 return LLVMConstInt(ctx->ac.i32, ctx->args->options->key.tcs.input_vertices, false);
976 }
977
978
979 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
980 {
981 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
982 return ac_get_arg(&ctx->ac, ctx->args->ac.base_vertex);
983 }
984
985 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
986 LLVMValueRef buffer_ptr, bool write)
987 {
988 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
989 LLVMValueRef result;
990
991 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
992
993 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
994 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
995
996 return result;
997 }
998
999 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
1000 {
1001 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1002 LLVMValueRef result;
1003
1004 if (LLVMGetTypeKind(LLVMTypeOf(buffer_ptr)) != LLVMPointerTypeKind) {
1005 /* Do not load the descriptor for inlined uniform blocks. */
1006 return buffer_ptr;
1007 }
1008
1009 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1010
1011 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1012 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1013
1014 return result;
1015 }
1016
1017 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
1018 unsigned descriptor_set,
1019 unsigned base_index,
1020 unsigned constant_index,
1021 LLVMValueRef index,
1022 enum ac_descriptor_type desc_type,
1023 bool image, bool write,
1024 bool bindless)
1025 {
1026 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1027 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
1028 struct radv_descriptor_set_layout *layout = ctx->args->options->layout->set[descriptor_set].layout;
1029 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
1030 unsigned offset = binding->offset;
1031 unsigned stride = binding->size;
1032 unsigned type_size;
1033 LLVMBuilderRef builder = ctx->ac.builder;
1034 LLVMTypeRef type;
1035
1036 assert(base_index < layout->binding_count);
1037
1038 switch (desc_type) {
1039 case AC_DESC_IMAGE:
1040 type = ctx->ac.v8i32;
1041 type_size = 32;
1042 break;
1043 case AC_DESC_FMASK:
1044 type = ctx->ac.v8i32;
1045 offset += 32;
1046 type_size = 32;
1047 break;
1048 case AC_DESC_SAMPLER:
1049 type = ctx->ac.v4i32;
1050 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER) {
1051 offset += radv_combined_image_descriptor_sampler_offset(binding);
1052 }
1053
1054 type_size = 16;
1055 break;
1056 case AC_DESC_BUFFER:
1057 type = ctx->ac.v4i32;
1058 type_size = 16;
1059 break;
1060 case AC_DESC_PLANE_0:
1061 case AC_DESC_PLANE_1:
1062 case AC_DESC_PLANE_2:
1063 type = ctx->ac.v8i32;
1064 type_size = 32;
1065 offset += 32 * (desc_type - AC_DESC_PLANE_0);
1066 break;
1067 default:
1068 unreachable("invalid desc_type\n");
1069 }
1070
1071 offset += constant_index * stride;
1072
1073 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
1074 (!index || binding->immutable_samplers_equal)) {
1075 if (binding->immutable_samplers_equal)
1076 constant_index = 0;
1077
1078 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
1079
1080 LLVMValueRef constants[] = {
1081 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
1082 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
1083 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
1084 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
1085 };
1086 return ac_build_gather_values(&ctx->ac, constants, 4);
1087 }
1088
1089 assert(stride % type_size == 0);
1090
1091 LLVMValueRef adjusted_index = index;
1092 if (!adjusted_index)
1093 adjusted_index = ctx->ac.i32_0;
1094
1095 adjusted_index = LLVMBuildMul(builder, adjusted_index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
1096
1097 LLVMValueRef val_offset = LLVMConstInt(ctx->ac.i32, offset, 0);
1098 list = LLVMBuildGEP(builder, list, &val_offset, 1, "");
1099 list = LLVMBuildPointerCast(builder, list,
1100 ac_array_in_const32_addr_space(type), "");
1101
1102 LLVMValueRef descriptor = ac_build_load_to_sgpr(&ctx->ac, list, adjusted_index);
1103
1104 /* 3 plane formats always have same size and format for plane 1 & 2, so
1105 * use the tail from plane 1 so that we can store only the first 16 bytes
1106 * of the last plane. */
1107 if (desc_type == AC_DESC_PLANE_2) {
1108 LLVMValueRef descriptor2 = radv_get_sampler_desc(abi, descriptor_set, base_index, constant_index, index, AC_DESC_PLANE_1,image, write, bindless);
1109
1110 LLVMValueRef components[8];
1111 for (unsigned i = 0; i < 4; ++i)
1112 components[i] = ac_llvm_extract_elem(&ctx->ac, descriptor, i);
1113
1114 for (unsigned i = 4; i < 8; ++i)
1115 components[i] = ac_llvm_extract_elem(&ctx->ac, descriptor2, i);
1116 descriptor = ac_build_gather_values(&ctx->ac, components, 8);
1117 }
1118
1119 return descriptor;
1120 }
1121
1122 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
1123 * so we may need to fix it up. */
1124 static LLVMValueRef
1125 adjust_vertex_fetch_alpha(struct radv_shader_context *ctx,
1126 unsigned adjustment,
1127 LLVMValueRef alpha)
1128 {
1129 if (adjustment == RADV_ALPHA_ADJUST_NONE)
1130 return alpha;
1131
1132 LLVMValueRef c30 = LLVMConstInt(ctx->ac.i32, 30, 0);
1133
1134 alpha = LLVMBuildBitCast(ctx->ac.builder, alpha, ctx->ac.f32, "");
1135
1136 if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
1137 alpha = LLVMBuildFPToUI(ctx->ac.builder, alpha, ctx->ac.i32, "");
1138 else
1139 alpha = ac_to_integer(&ctx->ac, alpha);
1140
1141 /* For the integer-like cases, do a natural sign extension.
1142 *
1143 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
1144 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
1145 * exponent.
1146 */
1147 alpha = LLVMBuildShl(ctx->ac.builder, alpha,
1148 adjustment == RADV_ALPHA_ADJUST_SNORM ?
1149 LLVMConstInt(ctx->ac.i32, 7, 0) : c30, "");
1150 alpha = LLVMBuildAShr(ctx->ac.builder, alpha, c30, "");
1151
1152 /* Convert back to the right type. */
1153 if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
1154 LLVMValueRef clamp;
1155 LLVMValueRef neg_one = LLVMConstReal(ctx->ac.f32, -1.0);
1156 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1157 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, alpha, neg_one, "");
1158 alpha = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, alpha, "");
1159 } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
1160 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1161 }
1162
1163 return LLVMBuildBitCast(ctx->ac.builder, alpha, ctx->ac.i32, "");
1164 }
1165
1166 static LLVMValueRef
1167 radv_fixup_vertex_input_fetches(struct radv_shader_context *ctx,
1168 LLVMValueRef value,
1169 unsigned num_channels,
1170 bool is_float)
1171 {
1172 LLVMValueRef zero = is_float ? ctx->ac.f32_0 : ctx->ac.i32_0;
1173 LLVMValueRef one = is_float ? ctx->ac.f32_1 : ctx->ac.i32_1;
1174 LLVMValueRef chan[4];
1175
1176 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMVectorTypeKind) {
1177 unsigned vec_size = LLVMGetVectorSize(LLVMTypeOf(value));
1178
1179 if (num_channels == 4 && num_channels == vec_size)
1180 return value;
1181
1182 num_channels = MIN2(num_channels, vec_size);
1183
1184 for (unsigned i = 0; i < num_channels; i++)
1185 chan[i] = ac_llvm_extract_elem(&ctx->ac, value, i);
1186 } else {
1187 assert(num_channels == 1);
1188 chan[0] = value;
1189 }
1190
1191 for (unsigned i = num_channels; i < 4; i++) {
1192 chan[i] = i == 3 ? one : zero;
1193 chan[i] = ac_to_integer(&ctx->ac, chan[i]);
1194 }
1195
1196 return ac_build_gather_values(&ctx->ac, chan, 4);
1197 }
1198
1199 static void
1200 handle_vs_input_decl(struct radv_shader_context *ctx,
1201 struct nir_variable *variable)
1202 {
1203 LLVMValueRef t_list_ptr = ac_get_arg(&ctx->ac, ctx->args->vertex_buffers);
1204 LLVMValueRef t_offset;
1205 LLVMValueRef t_list;
1206 LLVMValueRef input;
1207 LLVMValueRef buffer_index;
1208 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
1209 uint8_t input_usage_mask =
1210 ctx->args->shader_info->vs.input_usage_mask[variable->data.location];
1211 unsigned num_input_channels = util_last_bit(input_usage_mask);
1212
1213 variable->data.driver_location = variable->data.location * 4;
1214
1215 enum glsl_base_type type = glsl_get_base_type(variable->type);
1216 for (unsigned i = 0; i < attrib_count; ++i) {
1217 LLVMValueRef output[4];
1218 unsigned attrib_index = variable->data.location + i - VERT_ATTRIB_GENERIC0;
1219 unsigned attrib_format = ctx->args->options->key.vs.vertex_attribute_formats[attrib_index];
1220 unsigned data_format = attrib_format & 0x0f;
1221 unsigned num_format = (attrib_format >> 4) & 0x07;
1222 bool is_float = num_format != V_008F0C_BUF_NUM_FORMAT_UINT &&
1223 num_format != V_008F0C_BUF_NUM_FORMAT_SINT;
1224
1225 if (ctx->args->options->key.vs.instance_rate_inputs & (1u << attrib_index)) {
1226 uint32_t divisor = ctx->args->options->key.vs.instance_rate_divisors[attrib_index];
1227
1228 if (divisor) {
1229 buffer_index = ctx->abi.instance_id;
1230
1231 if (divisor != 1) {
1232 buffer_index = LLVMBuildUDiv(ctx->ac.builder, buffer_index,
1233 LLVMConstInt(ctx->ac.i32, divisor, 0), "");
1234 }
1235 } else {
1236 buffer_index = ctx->ac.i32_0;
1237 }
1238
1239 buffer_index = LLVMBuildAdd(ctx->ac.builder,
1240 ac_get_arg(&ctx->ac,
1241 ctx->args->ac.start_instance),\
1242 buffer_index, "");
1243 } else {
1244 buffer_index = LLVMBuildAdd(ctx->ac.builder,
1245 ctx->abi.vertex_id,
1246 ac_get_arg(&ctx->ac,
1247 ctx->args->ac.base_vertex), "");
1248 }
1249
1250 const struct ac_data_format_info *vtx_info = ac_get_data_format_info(data_format);
1251
1252 /* Adjust the number of channels to load based on the vertex
1253 * attribute format.
1254 */
1255 unsigned num_channels = MIN2(num_input_channels, vtx_info->num_channels);
1256 unsigned attrib_binding = ctx->args->options->key.vs.vertex_attribute_bindings[attrib_index];
1257 unsigned attrib_offset = ctx->args->options->key.vs.vertex_attribute_offsets[attrib_index];
1258 unsigned attrib_stride = ctx->args->options->key.vs.vertex_attribute_strides[attrib_index];
1259
1260 if (ctx->args->options->key.vs.post_shuffle & (1 << attrib_index)) {
1261 /* Always load, at least, 3 channels for formats that
1262 * need to be shuffled because X<->Z.
1263 */
1264 num_channels = MAX2(num_channels, 3);
1265 }
1266
1267 t_offset = LLVMConstInt(ctx->ac.i32, attrib_binding, false);
1268 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
1269
1270 /* Perform per-channel vertex fetch operations if unaligned
1271 * access are detected. Only GFX6 and GFX10 are affected.
1272 */
1273 bool unaligned_vertex_fetches = false;
1274 if ((ctx->ac.chip_class == GFX6 || ctx->ac.chip_class == GFX10) &&
1275 vtx_info->chan_format != data_format &&
1276 ((attrib_offset % vtx_info->element_size) ||
1277 (attrib_stride % vtx_info->element_size)))
1278 unaligned_vertex_fetches = true;
1279
1280 if (unaligned_vertex_fetches) {
1281 unsigned chan_format = vtx_info->chan_format;
1282 LLVMValueRef values[4];
1283
1284 assert(ctx->ac.chip_class == GFX6 ||
1285 ctx->ac.chip_class == GFX10);
1286
1287 for (unsigned chan = 0; chan < num_channels; chan++) {
1288 unsigned chan_offset = attrib_offset + chan * vtx_info->chan_byte_size;
1289 LLVMValueRef chan_index = buffer_index;
1290
1291 if (attrib_stride != 0 && chan_offset > attrib_stride) {
1292 LLVMValueRef buffer_offset =
1293 LLVMConstInt(ctx->ac.i32,
1294 chan_offset / attrib_stride, false);
1295
1296 chan_index = LLVMBuildAdd(ctx->ac.builder,
1297 buffer_index,
1298 buffer_offset, "");
1299
1300 chan_offset = chan_offset % attrib_stride;
1301 }
1302
1303 values[chan] = ac_build_struct_tbuffer_load(&ctx->ac, t_list,
1304 chan_index,
1305 LLVMConstInt(ctx->ac.i32, chan_offset, false),
1306 ctx->ac.i32_0, ctx->ac.i32_0, 1,
1307 chan_format, num_format, 0, true);
1308 }
1309
1310 input = ac_build_gather_values(&ctx->ac, values, num_channels);
1311 } else {
1312 if (attrib_stride != 0 && attrib_offset > attrib_stride) {
1313 LLVMValueRef buffer_offset =
1314 LLVMConstInt(ctx->ac.i32,
1315 attrib_offset / attrib_stride, false);
1316
1317 buffer_index = LLVMBuildAdd(ctx->ac.builder,
1318 buffer_index,
1319 buffer_offset, "");
1320
1321 attrib_offset = attrib_offset % attrib_stride;
1322 }
1323
1324 input = ac_build_struct_tbuffer_load(&ctx->ac, t_list,
1325 buffer_index,
1326 LLVMConstInt(ctx->ac.i32, attrib_offset, false),
1327 ctx->ac.i32_0, ctx->ac.i32_0,
1328 num_channels,
1329 data_format, num_format, 0, true);
1330 }
1331
1332 if (ctx->args->options->key.vs.post_shuffle & (1 << attrib_index)) {
1333 LLVMValueRef c[4];
1334 c[0] = ac_llvm_extract_elem(&ctx->ac, input, 2);
1335 c[1] = ac_llvm_extract_elem(&ctx->ac, input, 1);
1336 c[2] = ac_llvm_extract_elem(&ctx->ac, input, 0);
1337 c[3] = ac_llvm_extract_elem(&ctx->ac, input, 3);
1338
1339 input = ac_build_gather_values(&ctx->ac, c, 4);
1340 }
1341
1342 input = radv_fixup_vertex_input_fetches(ctx, input, num_channels,
1343 is_float);
1344
1345 for (unsigned chan = 0; chan < 4; chan++) {
1346 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
1347 output[chan] = LLVMBuildExtractElement(ctx->ac.builder, input, llvm_chan, "");
1348 if (type == GLSL_TYPE_FLOAT16) {
1349 output[chan] = LLVMBuildBitCast(ctx->ac.builder, output[chan], ctx->ac.f32, "");
1350 output[chan] = LLVMBuildFPTrunc(ctx->ac.builder, output[chan], ctx->ac.f16, "");
1351 }
1352 }
1353
1354 unsigned alpha_adjust = (ctx->args->options->key.vs.alpha_adjust >> (attrib_index * 2)) & 3;
1355 output[3] = adjust_vertex_fetch_alpha(ctx, alpha_adjust, output[3]);
1356
1357 for (unsigned chan = 0; chan < 4; chan++) {
1358 output[chan] = ac_to_integer(&ctx->ac, output[chan]);
1359 if (type == GLSL_TYPE_UINT16 || type == GLSL_TYPE_INT16)
1360 output[chan] = LLVMBuildTrunc(ctx->ac.builder, output[chan], ctx->ac.i16, "");
1361
1362 ctx->inputs[ac_llvm_reg_index_soa(variable->data.location + i, chan)] = output[chan];
1363 }
1364 }
1365 }
1366
1367 static void
1368 handle_vs_inputs(struct radv_shader_context *ctx,
1369 struct nir_shader *nir) {
1370 nir_foreach_variable(variable, &nir->inputs)
1371 handle_vs_input_decl(ctx, variable);
1372 }
1373
1374 static void
1375 prepare_interp_optimize(struct radv_shader_context *ctx,
1376 struct nir_shader *nir)
1377 {
1378 bool uses_center = false;
1379 bool uses_centroid = false;
1380 nir_foreach_variable(variable, &nir->inputs) {
1381 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
1382 variable->data.sample)
1383 continue;
1384
1385 if (variable->data.centroid)
1386 uses_centroid = true;
1387 else
1388 uses_center = true;
1389 }
1390
1391 ctx->abi.persp_centroid = ac_get_arg(&ctx->ac, ctx->args->ac.persp_centroid);
1392 ctx->abi.linear_centroid = ac_get_arg(&ctx->ac, ctx->args->ac.linear_centroid);
1393
1394 if (uses_center && uses_centroid) {
1395 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT,
1396 ac_get_arg(&ctx->ac, ctx->args->ac.prim_mask),
1397 ctx->ac.i32_0, "");
1398 ctx->abi.persp_centroid =
1399 LLVMBuildSelect(ctx->ac.builder, sel,
1400 ac_get_arg(&ctx->ac, ctx->args->ac.persp_center),
1401 ctx->abi.persp_centroid, "");
1402 ctx->abi.linear_centroid =
1403 LLVMBuildSelect(ctx->ac.builder, sel,
1404 ac_get_arg(&ctx->ac, ctx->args->ac.linear_center),
1405 ctx->abi.linear_centroid, "");
1406 }
1407 }
1408
1409 static void
1410 scan_shader_output_decl(struct radv_shader_context *ctx,
1411 struct nir_variable *variable,
1412 struct nir_shader *shader,
1413 gl_shader_stage stage)
1414 {
1415 int idx = variable->data.location + variable->data.index;
1416 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
1417 uint64_t mask_attribs;
1418
1419 variable->data.driver_location = idx * 4;
1420
1421 /* tess ctrl has it's own load/store paths for outputs */
1422 if (stage == MESA_SHADER_TESS_CTRL)
1423 return;
1424
1425 if (variable->data.compact) {
1426 unsigned component_count = variable->data.location_frac +
1427 glsl_get_length(variable->type);
1428 attrib_count = (component_count + 3) / 4;
1429 }
1430
1431 mask_attribs = ((1ull << attrib_count) - 1) << idx;
1432
1433 ctx->output_mask |= mask_attribs;
1434 }
1435
1436
1437 /* Initialize arguments for the shader export intrinsic */
1438 static void
1439 si_llvm_init_export_args(struct radv_shader_context *ctx,
1440 LLVMValueRef *values,
1441 unsigned enabled_channels,
1442 unsigned target,
1443 struct ac_export_args *args)
1444 {
1445 /* Specify the channels that are enabled. */
1446 args->enabled_channels = enabled_channels;
1447
1448 /* Specify whether the EXEC mask represents the valid mask */
1449 args->valid_mask = 0;
1450
1451 /* Specify whether this is the last export */
1452 args->done = 0;
1453
1454 /* Specify the target we are exporting */
1455 args->target = target;
1456
1457 args->compr = false;
1458 args->out[0] = LLVMGetUndef(ctx->ac.f32);
1459 args->out[1] = LLVMGetUndef(ctx->ac.f32);
1460 args->out[2] = LLVMGetUndef(ctx->ac.f32);
1461 args->out[3] = LLVMGetUndef(ctx->ac.f32);
1462
1463 if (!values)
1464 return;
1465
1466 bool is_16bit = ac_get_type_size(LLVMTypeOf(values[0])) == 2;
1467 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1468 unsigned index = target - V_008DFC_SQ_EXP_MRT;
1469 unsigned col_format = (ctx->args->options->key.fs.col_format >> (4 * index)) & 0xf;
1470 bool is_int8 = (ctx->args->options->key.fs.is_int8 >> index) & 1;
1471 bool is_int10 = (ctx->args->options->key.fs.is_int10 >> index) & 1;
1472 unsigned chan;
1473
1474 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
1475 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
1476 unsigned bits, bool hi) = NULL;
1477
1478 switch(col_format) {
1479 case V_028714_SPI_SHADER_ZERO:
1480 args->enabled_channels = 0; /* writemask */
1481 args->target = V_008DFC_SQ_EXP_NULL;
1482 break;
1483
1484 case V_028714_SPI_SHADER_32_R:
1485 args->enabled_channels = 1;
1486 args->out[0] = values[0];
1487 break;
1488
1489 case V_028714_SPI_SHADER_32_GR:
1490 args->enabled_channels = 0x3;
1491 args->out[0] = values[0];
1492 args->out[1] = values[1];
1493 break;
1494
1495 case V_028714_SPI_SHADER_32_AR:
1496 if (ctx->ac.chip_class >= GFX10) {
1497 args->enabled_channels = 0x3;
1498 args->out[0] = values[0];
1499 args->out[1] = values[3];
1500 } else {
1501 args->enabled_channels = 0x9;
1502 args->out[0] = values[0];
1503 args->out[3] = values[3];
1504 }
1505 break;
1506
1507 case V_028714_SPI_SHADER_FP16_ABGR:
1508 args->enabled_channels = 0x5;
1509 packf = ac_build_cvt_pkrtz_f16;
1510 if (is_16bit) {
1511 for (unsigned chan = 0; chan < 4; chan++)
1512 values[chan] = LLVMBuildFPExt(ctx->ac.builder,
1513 values[chan],
1514 ctx->ac.f32, "");
1515 }
1516 break;
1517
1518 case V_028714_SPI_SHADER_UNORM16_ABGR:
1519 args->enabled_channels = 0x5;
1520 packf = ac_build_cvt_pknorm_u16;
1521 break;
1522
1523 case V_028714_SPI_SHADER_SNORM16_ABGR:
1524 args->enabled_channels = 0x5;
1525 packf = ac_build_cvt_pknorm_i16;
1526 break;
1527
1528 case V_028714_SPI_SHADER_UINT16_ABGR:
1529 args->enabled_channels = 0x5;
1530 packi = ac_build_cvt_pk_u16;
1531 if (is_16bit) {
1532 for (unsigned chan = 0; chan < 4; chan++)
1533 values[chan] = LLVMBuildZExt(ctx->ac.builder,
1534 ac_to_integer(&ctx->ac, values[chan]),
1535 ctx->ac.i32, "");
1536 }
1537 break;
1538
1539 case V_028714_SPI_SHADER_SINT16_ABGR:
1540 args->enabled_channels = 0x5;
1541 packi = ac_build_cvt_pk_i16;
1542 if (is_16bit) {
1543 for (unsigned chan = 0; chan < 4; chan++)
1544 values[chan] = LLVMBuildSExt(ctx->ac.builder,
1545 ac_to_integer(&ctx->ac, values[chan]),
1546 ctx->ac.i32, "");
1547 }
1548 break;
1549
1550 default:
1551 case V_028714_SPI_SHADER_32_ABGR:
1552 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
1553 break;
1554 }
1555
1556 /* Pack f16 or norm_i16/u16. */
1557 if (packf) {
1558 for (chan = 0; chan < 2; chan++) {
1559 LLVMValueRef pack_args[2] = {
1560 values[2 * chan],
1561 values[2 * chan + 1]
1562 };
1563 LLVMValueRef packed;
1564
1565 packed = packf(&ctx->ac, pack_args);
1566 args->out[chan] = ac_to_float(&ctx->ac, packed);
1567 }
1568 args->compr = 1; /* COMPR flag */
1569 }
1570
1571 /* Pack i16/u16. */
1572 if (packi) {
1573 for (chan = 0; chan < 2; chan++) {
1574 LLVMValueRef pack_args[2] = {
1575 ac_to_integer(&ctx->ac, values[2 * chan]),
1576 ac_to_integer(&ctx->ac, values[2 * chan + 1])
1577 };
1578 LLVMValueRef packed;
1579
1580 packed = packi(&ctx->ac, pack_args,
1581 is_int8 ? 8 : is_int10 ? 10 : 16,
1582 chan == 1);
1583 args->out[chan] = ac_to_float(&ctx->ac, packed);
1584 }
1585 args->compr = 1; /* COMPR flag */
1586 }
1587 return;
1588 }
1589
1590 if (is_16bit) {
1591 for (unsigned chan = 0; chan < 4; chan++) {
1592 values[chan] = LLVMBuildBitCast(ctx->ac.builder, values[chan], ctx->ac.i16, "");
1593 args->out[chan] = LLVMBuildZExt(ctx->ac.builder, values[chan], ctx->ac.i32, "");
1594 }
1595 } else
1596 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
1597
1598 for (unsigned i = 0; i < 4; ++i)
1599 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
1600 }
1601
1602 static void
1603 radv_export_param(struct radv_shader_context *ctx, unsigned index,
1604 LLVMValueRef *values, unsigned enabled_channels)
1605 {
1606 struct ac_export_args args;
1607
1608 si_llvm_init_export_args(ctx, values, enabled_channels,
1609 V_008DFC_SQ_EXP_PARAM + index, &args);
1610 ac_build_export(&ctx->ac, &args);
1611 }
1612
1613 static LLVMValueRef
1614 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
1615 {
1616 LLVMValueRef output = ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
1617 return LLVMBuildLoad(ctx->ac.builder, output, "");
1618 }
1619
1620 static void
1621 radv_emit_stream_output(struct radv_shader_context *ctx,
1622 LLVMValueRef const *so_buffers,
1623 LLVMValueRef const *so_write_offsets,
1624 const struct radv_stream_output *output,
1625 struct radv_shader_output_values *shader_out)
1626 {
1627 unsigned num_comps = util_bitcount(output->component_mask);
1628 unsigned buf = output->buffer;
1629 unsigned offset = output->offset;
1630 unsigned start;
1631 LLVMValueRef out[4];
1632
1633 assert(num_comps && num_comps <= 4);
1634 if (!num_comps || num_comps > 4)
1635 return;
1636
1637 /* Get the first component. */
1638 start = ffs(output->component_mask) - 1;
1639
1640 /* Load the output as int. */
1641 for (int i = 0; i < num_comps; i++) {
1642 out[i] = ac_to_integer(&ctx->ac, shader_out->values[start + i]);
1643 }
1644
1645 /* Pack the output. */
1646 LLVMValueRef vdata = NULL;
1647
1648 switch (num_comps) {
1649 case 1: /* as i32 */
1650 vdata = out[0];
1651 break;
1652 case 2: /* as v2i32 */
1653 case 3: /* as v4i32 (aligned to 4) */
1654 out[3] = LLVMGetUndef(ctx->ac.i32);
1655 /* fall through */
1656 case 4: /* as v4i32 */
1657 vdata = ac_build_gather_values(&ctx->ac, out,
1658 !ac_has_vec3_support(ctx->ac.chip_class, false) ?
1659 util_next_power_of_two(num_comps) :
1660 num_comps);
1661 break;
1662 }
1663
1664 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf],
1665 vdata, num_comps, so_write_offsets[buf],
1666 ctx->ac.i32_0, offset,
1667 ac_glc | ac_slc);
1668 }
1669
1670 static void
1671 radv_emit_streamout(struct radv_shader_context *ctx, unsigned stream)
1672 {
1673 int i;
1674
1675 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1676 assert(ctx->args->streamout_config.used);
1677 LLVMValueRef so_vtx_count =
1678 ac_build_bfe(&ctx->ac,
1679 ac_get_arg(&ctx->ac, ctx->args->streamout_config),
1680 LLVMConstInt(ctx->ac.i32, 16, false),
1681 LLVMConstInt(ctx->ac.i32, 7, false), false);
1682
1683 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
1684
1685 /* can_emit = tid < so_vtx_count; */
1686 LLVMValueRef can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
1687 tid, so_vtx_count, "");
1688
1689 /* Emit the streamout code conditionally. This actually avoids
1690 * out-of-bounds buffer access. The hw tells us via the SGPR
1691 * (so_vtx_count) which threads are allowed to emit streamout data.
1692 */
1693 ac_build_ifcc(&ctx->ac, can_emit, 6501);
1694 {
1695 /* The buffer offset is computed as follows:
1696 * ByteOffset = streamout_offset[buffer_id]*4 +
1697 * (streamout_write_index + thread_id)*stride[buffer_id] +
1698 * attrib_offset
1699 */
1700 LLVMValueRef so_write_index =
1701 ac_get_arg(&ctx->ac, ctx->args->streamout_write_idx);
1702
1703 /* Compute (streamout_write_index + thread_id). */
1704 so_write_index =
1705 LLVMBuildAdd(ctx->ac.builder, so_write_index, tid, "");
1706
1707 /* Load the descriptor and compute the write offset for each
1708 * enabled buffer.
1709 */
1710 LLVMValueRef so_write_offset[4] = {};
1711 LLVMValueRef so_buffers[4] = {};
1712 LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac, ctx->args->streamout_buffers);
1713
1714 for (i = 0; i < 4; i++) {
1715 uint16_t stride = ctx->args->shader_info->so.strides[i];
1716
1717 if (!stride)
1718 continue;
1719
1720 LLVMValueRef offset =
1721 LLVMConstInt(ctx->ac.i32, i, false);
1722
1723 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac,
1724 buf_ptr, offset);
1725
1726 LLVMValueRef so_offset =
1727 ac_get_arg(&ctx->ac, ctx->args->streamout_offset[i]);
1728
1729 so_offset = LLVMBuildMul(ctx->ac.builder, so_offset,
1730 LLVMConstInt(ctx->ac.i32, 4, false), "");
1731
1732 so_write_offset[i] =
1733 ac_build_imad(&ctx->ac, so_write_index,
1734 LLVMConstInt(ctx->ac.i32,
1735 stride * 4, false),
1736 so_offset);
1737 }
1738
1739 /* Write streamout data. */
1740 for (i = 0; i < ctx->args->shader_info->so.num_outputs; i++) {
1741 struct radv_shader_output_values shader_out = {};
1742 struct radv_stream_output *output =
1743 &ctx->args->shader_info->so.outputs[i];
1744
1745 if (stream != output->stream)
1746 continue;
1747
1748 for (int j = 0; j < 4; j++) {
1749 shader_out.values[j] =
1750 radv_load_output(ctx, output->location, j);
1751 }
1752
1753 radv_emit_stream_output(ctx, so_buffers,so_write_offset,
1754 output, &shader_out);
1755 }
1756 }
1757 ac_build_endif(&ctx->ac, 6501);
1758 }
1759
1760 static void
1761 radv_build_param_exports(struct radv_shader_context *ctx,
1762 struct radv_shader_output_values *outputs,
1763 unsigned noutput,
1764 struct radv_vs_output_info *outinfo,
1765 bool export_clip_dists)
1766 {
1767 unsigned param_count = 0;
1768
1769 for (unsigned i = 0; i < noutput; i++) {
1770 unsigned slot_name = outputs[i].slot_name;
1771 unsigned usage_mask = outputs[i].usage_mask;
1772
1773 if (slot_name != VARYING_SLOT_LAYER &&
1774 slot_name != VARYING_SLOT_PRIMITIVE_ID &&
1775 slot_name != VARYING_SLOT_VIEWPORT &&
1776 slot_name != VARYING_SLOT_CLIP_DIST0 &&
1777 slot_name != VARYING_SLOT_CLIP_DIST1 &&
1778 slot_name < VARYING_SLOT_VAR0)
1779 continue;
1780
1781 if ((slot_name == VARYING_SLOT_CLIP_DIST0 ||
1782 slot_name == VARYING_SLOT_CLIP_DIST1) && !export_clip_dists)
1783 continue;
1784
1785 radv_export_param(ctx, param_count, outputs[i].values, usage_mask);
1786
1787 assert(i < ARRAY_SIZE(outinfo->vs_output_param_offset));
1788 outinfo->vs_output_param_offset[slot_name] = param_count++;
1789 }
1790
1791 outinfo->param_exports = param_count;
1792 }
1793
1794 /* Generate export instructions for hardware VS shader stage or NGG GS stage
1795 * (position and parameter data only).
1796 */
1797 static void
1798 radv_llvm_export_vs(struct radv_shader_context *ctx,
1799 struct radv_shader_output_values *outputs,
1800 unsigned noutput,
1801 struct radv_vs_output_info *outinfo,
1802 bool export_clip_dists)
1803 {
1804 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_value = NULL;
1805 struct ac_export_args pos_args[4] = {};
1806 unsigned pos_idx, index;
1807 int i;
1808
1809 /* Build position exports */
1810 for (i = 0; i < noutput; i++) {
1811 switch (outputs[i].slot_name) {
1812 case VARYING_SLOT_POS:
1813 si_llvm_init_export_args(ctx, outputs[i].values, 0xf,
1814 V_008DFC_SQ_EXP_POS, &pos_args[0]);
1815 break;
1816 case VARYING_SLOT_PSIZ:
1817 psize_value = outputs[i].values[0];
1818 break;
1819 case VARYING_SLOT_LAYER:
1820 layer_value = outputs[i].values[0];
1821 break;
1822 case VARYING_SLOT_VIEWPORT:
1823 viewport_value = outputs[i].values[0];
1824 break;
1825 case VARYING_SLOT_CLIP_DIST0:
1826 case VARYING_SLOT_CLIP_DIST1:
1827 index = 2 + outputs[i].slot_index;
1828 si_llvm_init_export_args(ctx, outputs[i].values, 0xf,
1829 V_008DFC_SQ_EXP_POS + index,
1830 &pos_args[index]);
1831 break;
1832 default:
1833 break;
1834 }
1835 }
1836
1837 /* We need to add the position output manually if it's missing. */
1838 if (!pos_args[0].out[0]) {
1839 pos_args[0].enabled_channels = 0xf; /* writemask */
1840 pos_args[0].valid_mask = 0; /* EXEC mask */
1841 pos_args[0].done = 0; /* last export? */
1842 pos_args[0].target = V_008DFC_SQ_EXP_POS;
1843 pos_args[0].compr = 0; /* COMPR flag */
1844 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
1845 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
1846 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
1847 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
1848 }
1849
1850 if (outinfo->writes_pointsize ||
1851 outinfo->writes_layer ||
1852 outinfo->writes_viewport_index) {
1853 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
1854 (outinfo->writes_layer == true ? 4 : 0));
1855 pos_args[1].valid_mask = 0;
1856 pos_args[1].done = 0;
1857 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
1858 pos_args[1].compr = 0;
1859 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
1860 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
1861 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
1862 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
1863
1864 if (outinfo->writes_pointsize == true)
1865 pos_args[1].out[0] = psize_value;
1866 if (outinfo->writes_layer == true)
1867 pos_args[1].out[2] = layer_value;
1868 if (outinfo->writes_viewport_index == true) {
1869 if (ctx->args->options->chip_class >= GFX9) {
1870 /* GFX9 has the layer in out.z[10:0] and the viewport
1871 * index in out.z[19:16].
1872 */
1873 LLVMValueRef v = viewport_value;
1874 v = ac_to_integer(&ctx->ac, v);
1875 v = LLVMBuildShl(ctx->ac.builder, v,
1876 LLVMConstInt(ctx->ac.i32, 16, false),
1877 "");
1878 v = LLVMBuildOr(ctx->ac.builder, v,
1879 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
1880
1881 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
1882 pos_args[1].enabled_channels |= 1 << 2;
1883 } else {
1884 pos_args[1].out[3] = viewport_value;
1885 pos_args[1].enabled_channels |= 1 << 3;
1886 }
1887 }
1888 }
1889
1890 for (i = 0; i < 4; i++) {
1891 if (pos_args[i].out[0])
1892 outinfo->pos_exports++;
1893 }
1894
1895 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
1896 * Setting valid_mask=1 prevents it and has no other effect.
1897 */
1898 if (ctx->ac.family == CHIP_NAVI10 ||
1899 ctx->ac.family == CHIP_NAVI12 ||
1900 ctx->ac.family == CHIP_NAVI14)
1901 pos_args[0].valid_mask = 1;
1902
1903 pos_idx = 0;
1904 for (i = 0; i < 4; i++) {
1905 if (!pos_args[i].out[0])
1906 continue;
1907
1908 /* Specify the target we are exporting */
1909 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
1910
1911 if (pos_idx == outinfo->pos_exports)
1912 /* Specify that this is the last export */
1913 pos_args[i].done = 1;
1914
1915 ac_build_export(&ctx->ac, &pos_args[i]);
1916 }
1917
1918 /* Build parameter exports */
1919 radv_build_param_exports(ctx, outputs, noutput, outinfo, export_clip_dists);
1920 }
1921
1922 static void
1923 handle_vs_outputs_post(struct radv_shader_context *ctx,
1924 bool export_prim_id,
1925 bool export_clip_dists,
1926 struct radv_vs_output_info *outinfo)
1927 {
1928 struct radv_shader_output_values *outputs;
1929 unsigned noutput = 0;
1930
1931 if (ctx->args->options->key.has_multiview_view_index) {
1932 LLVMValueRef* tmp_out = &ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
1933 if(!*tmp_out) {
1934 for(unsigned i = 0; i < 4; ++i)
1935 ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
1936 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
1937 }
1938
1939 LLVMValueRef view_index = ac_get_arg(&ctx->ac, ctx->args->ac.view_index);
1940 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, view_index), *tmp_out);
1941 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
1942 }
1943
1944 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
1945 sizeof(outinfo->vs_output_param_offset));
1946 outinfo->pos_exports = 0;
1947
1948 if (!ctx->args->options->use_ngg_streamout &&
1949 ctx->args->shader_info->so.num_outputs &&
1950 !ctx->args->is_gs_copy_shader) {
1951 /* The GS copy shader emission already emits streamout. */
1952 radv_emit_streamout(ctx, 0);
1953 }
1954
1955 /* Allocate a temporary array for the output values. */
1956 unsigned num_outputs = util_bitcount64(ctx->output_mask) + export_prim_id;
1957 outputs = malloc(num_outputs * sizeof(outputs[0]));
1958
1959 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
1960 if (!(ctx->output_mask & (1ull << i)))
1961 continue;
1962
1963 outputs[noutput].slot_name = i;
1964 outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
1965
1966 if (ctx->stage == MESA_SHADER_VERTEX &&
1967 !ctx->args->is_gs_copy_shader) {
1968 outputs[noutput].usage_mask =
1969 ctx->args->shader_info->vs.output_usage_mask[i];
1970 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
1971 outputs[noutput].usage_mask =
1972 ctx->args->shader_info->tes.output_usage_mask[i];
1973 } else {
1974 assert(ctx->args->is_gs_copy_shader);
1975 outputs[noutput].usage_mask =
1976 ctx->args->shader_info->gs.output_usage_mask[i];
1977 }
1978
1979 for (unsigned j = 0; j < 4; j++) {
1980 outputs[noutput].values[j] =
1981 ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
1982 }
1983
1984 noutput++;
1985 }
1986
1987 /* Export PrimitiveID. */
1988 if (export_prim_id) {
1989 outputs[noutput].slot_name = VARYING_SLOT_PRIMITIVE_ID;
1990 outputs[noutput].slot_index = 0;
1991 outputs[noutput].usage_mask = 0x1;
1992 outputs[noutput].values[0] =
1993 ac_get_arg(&ctx->ac, ctx->args->vs_prim_id);
1994 for (unsigned j = 1; j < 4; j++)
1995 outputs[noutput].values[j] = ctx->ac.f32_0;
1996 noutput++;
1997 }
1998
1999 radv_llvm_export_vs(ctx, outputs, noutput, outinfo, export_clip_dists);
2000
2001 free(outputs);
2002 }
2003
2004 static void
2005 handle_es_outputs_post(struct radv_shader_context *ctx,
2006 struct radv_es_output_info *outinfo)
2007 {
2008 int j;
2009 LLVMValueRef lds_base = NULL;
2010
2011 if (ctx->ac.chip_class >= GFX9) {
2012 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
2013 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
2014 LLVMValueRef wave_idx =
2015 ac_unpack_param(&ctx->ac,
2016 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 24, 4);
2017 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
2018 LLVMBuildMul(ctx->ac.builder, wave_idx,
2019 LLVMConstInt(ctx->ac.i32,
2020 ctx->ac.wave_size, false), ""), "");
2021 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
2022 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
2023 }
2024
2025 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2026 LLVMValueRef dw_addr = NULL;
2027 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2028 unsigned output_usage_mask;
2029 int param_index;
2030
2031 if (!(ctx->output_mask & (1ull << i)))
2032 continue;
2033
2034 if (ctx->stage == MESA_SHADER_VERTEX) {
2035 output_usage_mask =
2036 ctx->args->shader_info->vs.output_usage_mask[i];
2037 } else {
2038 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2039 output_usage_mask =
2040 ctx->args->shader_info->tes.output_usage_mask[i];
2041 }
2042
2043 param_index = shader_io_get_unique_index(i);
2044
2045 if (lds_base) {
2046 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2047 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
2048 "");
2049 }
2050
2051 for (j = 0; j < 4; j++) {
2052 if (!(output_usage_mask & (1 << j)))
2053 continue;
2054
2055 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2056 out_val = ac_to_integer(&ctx->ac, out_val);
2057 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
2058
2059 if (ctx->ac.chip_class >= GFX9) {
2060 LLVMValueRef dw_addr_offset =
2061 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2062 LLVMConstInt(ctx->ac.i32,
2063 j, false), "");
2064
2065 ac_lds_store(&ctx->ac, dw_addr_offset, out_val);
2066 } else {
2067 ac_build_buffer_store_dword(&ctx->ac,
2068 ctx->esgs_ring,
2069 out_val, 1,
2070 NULL,
2071 ac_get_arg(&ctx->ac, ctx->args->es2gs_offset),
2072 (4 * param_index + j) * 4,
2073 ac_glc | ac_slc | ac_swizzled);
2074 }
2075 }
2076 }
2077 }
2078
2079 static void
2080 handle_ls_outputs_post(struct radv_shader_context *ctx)
2081 {
2082 LLVMValueRef vertex_id = ctx->rel_auto_id;
2083 uint32_t num_tcs_inputs = util_last_bit64(ctx->args->shader_info->vs.ls_outputs_written);
2084 LLVMValueRef vertex_dw_stride = LLVMConstInt(ctx->ac.i32, num_tcs_inputs * 4, false);
2085 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
2086 vertex_dw_stride, "");
2087
2088 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2089 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2090
2091 if (!(ctx->output_mask & (1ull << i)))
2092 continue;
2093
2094 int param = shader_io_get_unique_index(i);
2095 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
2096 LLVMConstInt(ctx->ac.i32, param * 4, false),
2097 "");
2098 for (unsigned j = 0; j < 4; j++) {
2099 LLVMValueRef value = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2100 value = ac_to_integer(&ctx->ac, value);
2101 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
2102 ac_lds_store(&ctx->ac, dw_addr, value);
2103 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2104 }
2105 }
2106 }
2107
2108 static LLVMValueRef get_wave_id_in_tg(struct radv_shader_context *ctx)
2109 {
2110 return ac_unpack_param(&ctx->ac,
2111 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 24, 4);
2112 }
2113
2114 static LLVMValueRef get_tgsize(struct radv_shader_context *ctx)
2115 {
2116 return ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 28, 4);
2117 }
2118
2119 static LLVMValueRef get_thread_id_in_tg(struct radv_shader_context *ctx)
2120 {
2121 LLVMBuilderRef builder = ctx->ac.builder;
2122 LLVMValueRef tmp;
2123 tmp = LLVMBuildMul(builder, get_wave_id_in_tg(ctx),
2124 LLVMConstInt(ctx->ac.i32, ctx->ac.wave_size, false), "");
2125 return LLVMBuildAdd(builder, tmp, ac_get_thread_id(&ctx->ac), "");
2126 }
2127
2128 static LLVMValueRef ngg_get_vtx_cnt(struct radv_shader_context *ctx)
2129 {
2130 return ac_build_bfe(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_tg_info),
2131 LLVMConstInt(ctx->ac.i32, 12, false),
2132 LLVMConstInt(ctx->ac.i32, 9, false),
2133 false);
2134 }
2135
2136 static LLVMValueRef ngg_get_prim_cnt(struct radv_shader_context *ctx)
2137 {
2138 return ac_build_bfe(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_tg_info),
2139 LLVMConstInt(ctx->ac.i32, 22, false),
2140 LLVMConstInt(ctx->ac.i32, 9, false),
2141 false);
2142 }
2143
2144 static LLVMValueRef ngg_get_ordered_id(struct radv_shader_context *ctx)
2145 {
2146 return ac_build_bfe(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_tg_info),
2147 ctx->ac.i32_0,
2148 LLVMConstInt(ctx->ac.i32, 12, false),
2149 false);
2150 }
2151
2152 static LLVMValueRef
2153 ngg_gs_get_vertex_storage(struct radv_shader_context *ctx)
2154 {
2155 unsigned num_outputs = util_bitcount64(ctx->output_mask);
2156
2157 if (ctx->args->options->key.has_multiview_view_index)
2158 num_outputs++;
2159
2160 LLVMTypeRef elements[2] = {
2161 LLVMArrayType(ctx->ac.i32, 4 * num_outputs),
2162 LLVMArrayType(ctx->ac.i8, 4),
2163 };
2164 LLVMTypeRef type = LLVMStructTypeInContext(ctx->ac.context, elements, 2, false);
2165 type = LLVMPointerType(LLVMArrayType(type, 0), AC_ADDR_SPACE_LDS);
2166 return LLVMBuildBitCast(ctx->ac.builder, ctx->gs_ngg_emit, type, "");
2167 }
2168
2169 /**
2170 * Return a pointer to the LDS storage reserved for the N'th vertex, where N
2171 * is in emit order; that is:
2172 * - during the epilogue, N is the threadidx (relative to the entire threadgroup)
2173 * - during vertex emit, i.e. while the API GS shader invocation is running,
2174 * N = threadidx * gs_max_out_vertices + emitidx
2175 *
2176 * Goals of the LDS memory layout:
2177 * 1. Eliminate bank conflicts on write for geometry shaders that have all emits
2178 * in uniform control flow
2179 * 2. Eliminate bank conflicts on read for export if, additionally, there is no
2180 * culling
2181 * 3. Agnostic to the number of waves (since we don't know it before compiling)
2182 * 4. Allow coalescing of LDS instructions (ds_write_b128 etc.)
2183 * 5. Avoid wasting memory.
2184 *
2185 * We use an AoS layout due to point 4 (this also helps point 3). In an AoS
2186 * layout, elimination of bank conflicts requires that each vertex occupy an
2187 * odd number of dwords. We use the additional dword to store the output stream
2188 * index as well as a flag to indicate whether this vertex ends a primitive
2189 * for rasterization.
2190 *
2191 * Swizzling is required to satisfy points 1 and 2 simultaneously.
2192 *
2193 * Vertices are stored in export order (gsthread * gs_max_out_vertices + emitidx).
2194 * Indices are swizzled in groups of 32, which ensures point 1 without
2195 * disturbing point 2.
2196 *
2197 * \return an LDS pointer to type {[N x i32], [4 x i8]}
2198 */
2199 static LLVMValueRef
2200 ngg_gs_vertex_ptr(struct radv_shader_context *ctx, LLVMValueRef vertexidx)
2201 {
2202 LLVMBuilderRef builder = ctx->ac.builder;
2203 LLVMValueRef storage = ngg_gs_get_vertex_storage(ctx);
2204
2205 /* gs_max_out_vertices = 2^(write_stride_2exp) * some odd number */
2206 unsigned write_stride_2exp = ffs(ctx->shader->info.gs.vertices_out) - 1;
2207 if (write_stride_2exp) {
2208 LLVMValueRef row =
2209 LLVMBuildLShr(builder, vertexidx,
2210 LLVMConstInt(ctx->ac.i32, 5, false), "");
2211 LLVMValueRef swizzle =
2212 LLVMBuildAnd(builder, row,
2213 LLVMConstInt(ctx->ac.i32, (1u << write_stride_2exp) - 1,
2214 false), "");
2215 vertexidx = LLVMBuildXor(builder, vertexidx, swizzle, "");
2216 }
2217
2218 return ac_build_gep0(&ctx->ac, storage, vertexidx);
2219 }
2220
2221 static LLVMValueRef
2222 ngg_gs_emit_vertex_ptr(struct radv_shader_context *ctx, LLVMValueRef gsthread,
2223 LLVMValueRef emitidx)
2224 {
2225 LLVMBuilderRef builder = ctx->ac.builder;
2226 LLVMValueRef tmp;
2227
2228 tmp = LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false);
2229 tmp = LLVMBuildMul(builder, tmp, gsthread, "");
2230 const LLVMValueRef vertexidx = LLVMBuildAdd(builder, tmp, emitidx, "");
2231 return ngg_gs_vertex_ptr(ctx, vertexidx);
2232 }
2233
2234 static LLVMValueRef
2235 ngg_gs_get_emit_output_ptr(struct radv_shader_context *ctx, LLVMValueRef vertexptr,
2236 unsigned out_idx)
2237 {
2238 LLVMValueRef gep_idx[3] = {
2239 ctx->ac.i32_0, /* implied C-style array */
2240 ctx->ac.i32_0, /* first struct entry */
2241 LLVMConstInt(ctx->ac.i32, out_idx, false),
2242 };
2243 return LLVMBuildGEP(ctx->ac.builder, vertexptr, gep_idx, 3, "");
2244 }
2245
2246 static LLVMValueRef
2247 ngg_gs_get_emit_primflag_ptr(struct radv_shader_context *ctx, LLVMValueRef vertexptr,
2248 unsigned stream)
2249 {
2250 LLVMValueRef gep_idx[3] = {
2251 ctx->ac.i32_0, /* implied C-style array */
2252 ctx->ac.i32_1, /* second struct entry */
2253 LLVMConstInt(ctx->ac.i32, stream, false),
2254 };
2255 return LLVMBuildGEP(ctx->ac.builder, vertexptr, gep_idx, 3, "");
2256 }
2257
2258 static struct radv_stream_output *
2259 radv_get_stream_output_by_loc(struct radv_streamout_info *so, unsigned location)
2260 {
2261 for (unsigned i = 0; i < so->num_outputs; ++i) {
2262 if (so->outputs[i].location == location)
2263 return &so->outputs[i];
2264 }
2265
2266 return NULL;
2267 }
2268
2269 static void build_streamout_vertex(struct radv_shader_context *ctx,
2270 LLVMValueRef *so_buffer, LLVMValueRef *wg_offset_dw,
2271 unsigned stream, LLVMValueRef offset_vtx,
2272 LLVMValueRef vertexptr)
2273 {
2274 struct radv_streamout_info *so = &ctx->args->shader_info->so;
2275 LLVMBuilderRef builder = ctx->ac.builder;
2276 LLVMValueRef offset[4] = {};
2277 LLVMValueRef tmp;
2278
2279 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2280 if (!wg_offset_dw[buffer])
2281 continue;
2282
2283 tmp = LLVMBuildMul(builder, offset_vtx,
2284 LLVMConstInt(ctx->ac.i32, so->strides[buffer], false), "");
2285 tmp = LLVMBuildAdd(builder, wg_offset_dw[buffer], tmp, "");
2286 offset[buffer] = LLVMBuildShl(builder, tmp, LLVMConstInt(ctx->ac.i32, 2, false), "");
2287 }
2288
2289 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2290 struct radv_shader_output_values outputs[AC_LLVM_MAX_OUTPUTS];
2291 unsigned noutput = 0;
2292 unsigned out_idx = 0;
2293
2294 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2295 unsigned output_usage_mask =
2296 ctx->args->shader_info->gs.output_usage_mask[i];
2297 uint8_t output_stream =
2298 output_stream = ctx->args->shader_info->gs.output_streams[i];
2299
2300 if (!(ctx->output_mask & (1ull << i)) ||
2301 output_stream != stream)
2302 continue;
2303
2304 outputs[noutput].slot_name = i;
2305 outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
2306 outputs[noutput].usage_mask = output_usage_mask;
2307
2308 int length = util_last_bit(output_usage_mask);
2309
2310 for (unsigned j = 0; j < length; j++, out_idx++) {
2311 if (!(output_usage_mask & (1 << j)))
2312 continue;
2313
2314 tmp = ac_build_gep0(&ctx->ac, vertexptr,
2315 LLVMConstInt(ctx->ac.i32, out_idx, false));
2316 outputs[noutput].values[j] = LLVMBuildLoad(builder, tmp, "");
2317 }
2318
2319 for (unsigned j = length; j < 4; j++)
2320 outputs[noutput].values[j] = LLVMGetUndef(ctx->ac.f32);
2321
2322 noutput++;
2323 }
2324
2325 for (unsigned i = 0; i < noutput; i++) {
2326 struct radv_stream_output *output =
2327 radv_get_stream_output_by_loc(so, outputs[i].slot_name);
2328
2329 if (!output ||
2330 output->stream != stream)
2331 continue;
2332
2333 struct radv_shader_output_values out = {};
2334
2335 for (unsigned j = 0; j < 4; j++) {
2336 out.values[j] = outputs[i].values[j];
2337 }
2338
2339 radv_emit_stream_output(ctx, so_buffer, offset, output, &out);
2340 }
2341 } else {
2342 for (unsigned i = 0; i < so->num_outputs; ++i) {
2343 struct radv_stream_output *output =
2344 &ctx->args->shader_info->so.outputs[i];
2345
2346 if (stream != output->stream)
2347 continue;
2348
2349 struct radv_shader_output_values out = {};
2350
2351 for (unsigned comp = 0; comp < 4; comp++) {
2352 if (!(output->component_mask & (1 << comp)))
2353 continue;
2354
2355 tmp = ac_build_gep0(&ctx->ac, vertexptr,
2356 LLVMConstInt(ctx->ac.i32, 4 * i + comp, false));
2357 out.values[comp] = LLVMBuildLoad(builder, tmp, "");
2358 }
2359
2360 radv_emit_stream_output(ctx, so_buffer, offset, output, &out);
2361 }
2362 }
2363 }
2364
2365 struct ngg_streamout {
2366 LLVMValueRef num_vertices;
2367
2368 /* per-thread data */
2369 LLVMValueRef prim_enable[4]; /* i1 per stream */
2370 LLVMValueRef vertices[3]; /* [N x i32] addrspace(LDS)* */
2371
2372 /* Output */
2373 LLVMValueRef emit[4]; /* per-stream emitted primitives (only valid for used streams) */
2374 };
2375
2376 /**
2377 * Build streamout logic.
2378 *
2379 * Implies a barrier.
2380 *
2381 * Writes number of emitted primitives to gs_ngg_scratch[4:7].
2382 *
2383 * Clobbers gs_ngg_scratch[8:].
2384 */
2385 static void build_streamout(struct radv_shader_context *ctx,
2386 struct ngg_streamout *nggso)
2387 {
2388 struct radv_streamout_info *so = &ctx->args->shader_info->so;
2389 LLVMBuilderRef builder = ctx->ac.builder;
2390 LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac, ctx->args->streamout_buffers);
2391 LLVMValueRef tid = get_thread_id_in_tg(ctx);
2392 LLVMValueRef cond, tmp, tmp2;
2393 LLVMValueRef i32_2 = LLVMConstInt(ctx->ac.i32, 2, false);
2394 LLVMValueRef i32_4 = LLVMConstInt(ctx->ac.i32, 4, false);
2395 LLVMValueRef i32_8 = LLVMConstInt(ctx->ac.i32, 8, false);
2396 LLVMValueRef so_buffer[4] = {};
2397 unsigned max_num_vertices = 1 + (nggso->vertices[1] ? 1 : 0) +
2398 (nggso->vertices[2] ? 1 : 0);
2399 LLVMValueRef prim_stride_dw[4] = {};
2400 LLVMValueRef prim_stride_dw_vgpr = LLVMGetUndef(ctx->ac.i32);
2401 int stream_for_buffer[4] = { -1, -1, -1, -1 };
2402 unsigned bufmask_for_stream[4] = {};
2403 bool isgs = ctx->stage == MESA_SHADER_GEOMETRY;
2404 unsigned scratch_emit_base = isgs ? 4 : 0;
2405 LLVMValueRef scratch_emit_basev = isgs ? i32_4 : ctx->ac.i32_0;
2406 unsigned scratch_offset_base = isgs ? 8 : 4;
2407 LLVMValueRef scratch_offset_basev = isgs ? i32_8 : i32_4;
2408
2409 ac_llvm_add_target_dep_function_attr(ctx->main_function,
2410 "amdgpu-gds-size", 256);
2411
2412 /* Determine the mapping of streamout buffers to vertex streams. */
2413 for (unsigned i = 0; i < so->num_outputs; ++i) {
2414 unsigned buf = so->outputs[i].buffer;
2415 unsigned stream = so->outputs[i].stream;
2416 assert(stream_for_buffer[buf] < 0 || stream_for_buffer[buf] == stream);
2417 stream_for_buffer[buf] = stream;
2418 bufmask_for_stream[stream] |= 1 << buf;
2419 }
2420
2421 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2422 if (stream_for_buffer[buffer] == -1)
2423 continue;
2424
2425 assert(so->strides[buffer]);
2426
2427 LLVMValueRef stride_for_buffer =
2428 LLVMConstInt(ctx->ac.i32, so->strides[buffer], false);
2429 prim_stride_dw[buffer] =
2430 LLVMBuildMul(builder, stride_for_buffer,
2431 nggso->num_vertices, "");
2432 prim_stride_dw_vgpr = ac_build_writelane(
2433 &ctx->ac, prim_stride_dw_vgpr, prim_stride_dw[buffer],
2434 LLVMConstInt(ctx->ac.i32, buffer, false));
2435
2436 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, buffer, false);
2437 so_buffer[buffer] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr,
2438 offset);
2439 }
2440
2441 cond = LLVMBuildICmp(builder, LLVMIntEQ, get_wave_id_in_tg(ctx), ctx->ac.i32_0, "");
2442 ac_build_ifcc(&ctx->ac, cond, 5200);
2443 {
2444 LLVMTypeRef gdsptr = LLVMPointerType(ctx->ac.i32, AC_ADDR_SPACE_GDS);
2445 LLVMValueRef gdsbase = LLVMBuildIntToPtr(builder, ctx->ac.i32_0, gdsptr, "");
2446
2447 /* Advance the streamout offsets in GDS. */
2448 LLVMValueRef offsets_vgpr = ac_build_alloca_undef(&ctx->ac, ctx->ac.i32, "");
2449 LLVMValueRef generated_by_stream_vgpr = ac_build_alloca_undef(&ctx->ac, ctx->ac.i32, "");
2450
2451 cond = LLVMBuildICmp(builder, LLVMIntULT, ac_get_thread_id(&ctx->ac), i32_4, "");
2452 ac_build_ifcc(&ctx->ac, cond, 5210);
2453 {
2454 /* Fetch the number of generated primitives and store
2455 * it in GDS for later use.
2456 */
2457 if (isgs) {
2458 tmp = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tid);
2459 tmp = LLVMBuildLoad(builder, tmp, "");
2460 } else {
2461 tmp = ac_build_writelane(&ctx->ac, ctx->ac.i32_0,
2462 ngg_get_prim_cnt(ctx), ctx->ac.i32_0);
2463 }
2464 LLVMBuildStore(builder, tmp, generated_by_stream_vgpr);
2465
2466 unsigned swizzle[4];
2467 int unused_stream = -1;
2468 for (unsigned stream = 0; stream < 4; ++stream) {
2469 if (!ctx->args->shader_info->gs.num_stream_output_components[stream]) {
2470 unused_stream = stream;
2471 break;
2472 }
2473 }
2474 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2475 if (stream_for_buffer[buffer] >= 0) {
2476 swizzle[buffer] = stream_for_buffer[buffer];
2477 } else {
2478 assert(unused_stream >= 0);
2479 swizzle[buffer] = unused_stream;
2480 }
2481 }
2482
2483 tmp = ac_build_quad_swizzle(&ctx->ac, tmp,
2484 swizzle[0], swizzle[1], swizzle[2], swizzle[3]);
2485 tmp = LLVMBuildMul(builder, tmp, prim_stride_dw_vgpr, "");
2486
2487 LLVMValueRef args[] = {
2488 LLVMBuildIntToPtr(builder, ngg_get_ordered_id(ctx), gdsptr, ""),
2489 tmp,
2490 ctx->ac.i32_0, // ordering
2491 ctx->ac.i32_0, // scope
2492 ctx->ac.i1false, // isVolatile
2493 LLVMConstInt(ctx->ac.i32, 4 << 24, false), // OA index
2494 ctx->ac.i1true, // wave release
2495 ctx->ac.i1true, // wave done
2496 };
2497
2498 tmp = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.ds.ordered.add",
2499 ctx->ac.i32, args, ARRAY_SIZE(args), 0);
2500
2501 /* Keep offsets in a VGPR for quick retrieval via readlane by
2502 * the first wave for bounds checking, and also store in LDS
2503 * for retrieval by all waves later. */
2504 LLVMBuildStore(builder, tmp, offsets_vgpr);
2505
2506 tmp2 = LLVMBuildAdd(builder, ac_get_thread_id(&ctx->ac),
2507 scratch_offset_basev, "");
2508 tmp2 = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tmp2);
2509 LLVMBuildStore(builder, tmp, tmp2);
2510 }
2511 ac_build_endif(&ctx->ac, 5210);
2512
2513 /* Determine the max emit per buffer. This is done via the SALU, in part
2514 * because LLVM can't generate divide-by-multiply if we try to do this
2515 * via VALU with one lane per buffer.
2516 */
2517 LLVMValueRef max_emit[4] = {};
2518 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2519 if (stream_for_buffer[buffer] == -1)
2520 continue;
2521
2522 /* Compute the streamout buffer size in DWORD. */
2523 LLVMValueRef bufsize_dw =
2524 LLVMBuildLShr(builder,
2525 LLVMBuildExtractElement(builder, so_buffer[buffer], i32_2, ""),
2526 i32_2, "");
2527
2528 /* Load the streamout buffer offset from GDS. */
2529 tmp = LLVMBuildLoad(builder, offsets_vgpr, "");
2530 LLVMValueRef offset_dw =
2531 ac_build_readlane(&ctx->ac, tmp,
2532 LLVMConstInt(ctx->ac.i32, buffer, false));
2533
2534 /* Compute the remaining size to emit. */
2535 LLVMValueRef remaining_dw =
2536 LLVMBuildSub(builder, bufsize_dw, offset_dw, "");
2537 tmp = LLVMBuildUDiv(builder, remaining_dw,
2538 prim_stride_dw[buffer], "");
2539
2540 cond = LLVMBuildICmp(builder, LLVMIntULT,
2541 bufsize_dw, offset_dw, "");
2542 max_emit[buffer] = LLVMBuildSelect(builder, cond,
2543 ctx->ac.i32_0, tmp, "");
2544 }
2545
2546 /* Determine the number of emitted primitives per stream and fixup the
2547 * GDS counter if necessary.
2548 *
2549 * This is complicated by the fact that a single stream can emit to
2550 * multiple buffers (but luckily not vice versa).
2551 */
2552 LLVMValueRef emit_vgpr = ctx->ac.i32_0;
2553
2554 for (unsigned stream = 0; stream < 4; ++stream) {
2555 if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
2556 continue;
2557
2558 /* Load the number of generated primitives from GDS and
2559 * determine that number for the given stream.
2560 */
2561 tmp = LLVMBuildLoad(builder, generated_by_stream_vgpr, "");
2562 LLVMValueRef generated =
2563 ac_build_readlane(&ctx->ac, tmp,
2564 LLVMConstInt(ctx->ac.i32, stream, false));
2565
2566
2567 /* Compute the number of emitted primitives. */
2568 LLVMValueRef emit = generated;
2569 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2570 if (stream_for_buffer[buffer] == stream)
2571 emit = ac_build_umin(&ctx->ac, emit, max_emit[buffer]);
2572 }
2573
2574 /* Store the number of emitted primitives for that
2575 * stream.
2576 */
2577 emit_vgpr = ac_build_writelane(&ctx->ac, emit_vgpr, emit,
2578 LLVMConstInt(ctx->ac.i32, stream, false));
2579
2580 /* Fixup the offset using a plain GDS atomic if we overflowed. */
2581 cond = LLVMBuildICmp(builder, LLVMIntULT, emit, generated, "");
2582 ac_build_ifcc(&ctx->ac, cond, 5221); /* scalar branch */
2583 tmp = LLVMBuildLShr(builder,
2584 LLVMConstInt(ctx->ac.i32, bufmask_for_stream[stream], false),
2585 ac_get_thread_id(&ctx->ac), "");
2586 tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
2587 ac_build_ifcc(&ctx->ac, tmp, 5222);
2588 {
2589 tmp = LLVMBuildSub(builder, generated, emit, "");
2590 tmp = LLVMBuildMul(builder, tmp, prim_stride_dw_vgpr, "");
2591 tmp2 = LLVMBuildGEP(builder, gdsbase, &tid, 1, "");
2592 LLVMBuildAtomicRMW(builder, LLVMAtomicRMWBinOpSub, tmp2, tmp,
2593 LLVMAtomicOrderingMonotonic, false);
2594 }
2595 ac_build_endif(&ctx->ac, 5222);
2596 ac_build_endif(&ctx->ac, 5221);
2597 }
2598
2599 /* Store the number of emitted primitives to LDS for later use. */
2600 cond = LLVMBuildICmp(builder, LLVMIntULT, ac_get_thread_id(&ctx->ac), i32_4, "");
2601 ac_build_ifcc(&ctx->ac, cond, 5225);
2602 {
2603 tmp = LLVMBuildAdd(builder, ac_get_thread_id(&ctx->ac),
2604 scratch_emit_basev, "");
2605 tmp = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tmp);
2606 LLVMBuildStore(builder, emit_vgpr, tmp);
2607 }
2608 ac_build_endif(&ctx->ac, 5225);
2609 }
2610 ac_build_endif(&ctx->ac, 5200);
2611
2612 /* Determine the workgroup-relative per-thread / primitive offset into
2613 * the streamout buffers */
2614 struct ac_wg_scan primemit_scan[4] = {};
2615
2616 if (isgs) {
2617 for (unsigned stream = 0; stream < 4; ++stream) {
2618 if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
2619 continue;
2620
2621 primemit_scan[stream].enable_exclusive = true;
2622 primemit_scan[stream].op = nir_op_iadd;
2623 primemit_scan[stream].src = nggso->prim_enable[stream];
2624 primemit_scan[stream].scratch =
2625 ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch,
2626 LLVMConstInt(ctx->ac.i32, 12 + 8 * stream, false));
2627 primemit_scan[stream].waveidx = get_wave_id_in_tg(ctx);
2628 primemit_scan[stream].numwaves = get_tgsize(ctx);
2629 primemit_scan[stream].maxwaves = 8;
2630 ac_build_wg_scan_top(&ctx->ac, &primemit_scan[stream]);
2631 }
2632 }
2633
2634 ac_build_s_barrier(&ctx->ac);
2635
2636 /* Fetch the per-buffer offsets and per-stream emit counts in all waves. */
2637 LLVMValueRef wgoffset_dw[4] = {};
2638
2639 {
2640 LLVMValueRef scratch_vgpr;
2641
2642 tmp = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, ac_get_thread_id(&ctx->ac));
2643 scratch_vgpr = LLVMBuildLoad(builder, tmp, "");
2644
2645 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2646 if (stream_for_buffer[buffer] >= 0) {
2647 wgoffset_dw[buffer] = ac_build_readlane(
2648 &ctx->ac, scratch_vgpr,
2649 LLVMConstInt(ctx->ac.i32, scratch_offset_base + buffer, false));
2650 }
2651 }
2652
2653 for (unsigned stream = 0; stream < 4; ++stream) {
2654 if (ctx->args->shader_info->gs.num_stream_output_components[stream]) {
2655 nggso->emit[stream] = ac_build_readlane(
2656 &ctx->ac, scratch_vgpr,
2657 LLVMConstInt(ctx->ac.i32, scratch_emit_base + stream, false));
2658 }
2659 }
2660 }
2661
2662 /* Write out primitive data */
2663 for (unsigned stream = 0; stream < 4; ++stream) {
2664 if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
2665 continue;
2666
2667 if (isgs) {
2668 ac_build_wg_scan_bottom(&ctx->ac, &primemit_scan[stream]);
2669 } else {
2670 primemit_scan[stream].result_exclusive = tid;
2671 }
2672
2673 cond = LLVMBuildICmp(builder, LLVMIntULT,
2674 primemit_scan[stream].result_exclusive,
2675 nggso->emit[stream], "");
2676 cond = LLVMBuildAnd(builder, cond, nggso->prim_enable[stream], "");
2677 ac_build_ifcc(&ctx->ac, cond, 5240);
2678 {
2679 LLVMValueRef offset_vtx =
2680 LLVMBuildMul(builder, primemit_scan[stream].result_exclusive,
2681 nggso->num_vertices, "");
2682
2683 for (unsigned i = 0; i < max_num_vertices; ++i) {
2684 cond = LLVMBuildICmp(builder, LLVMIntULT,
2685 LLVMConstInt(ctx->ac.i32, i, false),
2686 nggso->num_vertices, "");
2687 ac_build_ifcc(&ctx->ac, cond, 5241);
2688 build_streamout_vertex(ctx, so_buffer, wgoffset_dw,
2689 stream, offset_vtx, nggso->vertices[i]);
2690 ac_build_endif(&ctx->ac, 5241);
2691 offset_vtx = LLVMBuildAdd(builder, offset_vtx, ctx->ac.i32_1, "");
2692 }
2693 }
2694 ac_build_endif(&ctx->ac, 5240);
2695 }
2696 }
2697
2698 static unsigned ngg_nogs_vertex_size(struct radv_shader_context *ctx)
2699 {
2700 unsigned lds_vertex_size = 0;
2701
2702 if (ctx->args->shader_info->so.num_outputs)
2703 lds_vertex_size = 4 * ctx->args->shader_info->so.num_outputs + 1;
2704
2705 return lds_vertex_size;
2706 }
2707
2708 /**
2709 * Returns an `[N x i32] addrspace(LDS)*` pointing at contiguous LDS storage
2710 * for the vertex outputs.
2711 */
2712 static LLVMValueRef ngg_nogs_vertex_ptr(struct radv_shader_context *ctx,
2713 LLVMValueRef vtxid)
2714 {
2715 /* The extra dword is used to avoid LDS bank conflicts. */
2716 unsigned vertex_size = ngg_nogs_vertex_size(ctx);
2717 LLVMTypeRef ai32 = LLVMArrayType(ctx->ac.i32, vertex_size);
2718 LLVMTypeRef pai32 = LLVMPointerType(ai32, AC_ADDR_SPACE_LDS);
2719 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, ctx->esgs_ring, pai32, "");
2720 return LLVMBuildGEP(ctx->ac.builder, tmp, &vtxid, 1, "");
2721 }
2722
2723 static void
2724 handle_ngg_outputs_post_1(struct radv_shader_context *ctx)
2725 {
2726 struct radv_streamout_info *so = &ctx->args->shader_info->so;
2727 LLVMBuilderRef builder = ctx->ac.builder;
2728 LLVMValueRef vertex_ptr = NULL;
2729 LLVMValueRef tmp, tmp2;
2730
2731 assert((ctx->stage == MESA_SHADER_VERTEX ||
2732 ctx->stage == MESA_SHADER_TESS_EVAL) && !ctx->args->is_gs_copy_shader);
2733
2734 if (!ctx->args->shader_info->so.num_outputs)
2735 return;
2736
2737 vertex_ptr = ngg_nogs_vertex_ptr(ctx, get_thread_id_in_tg(ctx));
2738
2739 for (unsigned i = 0; i < so->num_outputs; ++i) {
2740 struct radv_stream_output *output =
2741 &ctx->args->shader_info->so.outputs[i];
2742
2743 unsigned loc = output->location;
2744
2745 for (unsigned comp = 0; comp < 4; comp++) {
2746 if (!(output->component_mask & (1 << comp)))
2747 continue;
2748
2749 tmp = ac_build_gep0(&ctx->ac, vertex_ptr,
2750 LLVMConstInt(ctx->ac.i32, 4 * i + comp, false));
2751 tmp2 = LLVMBuildLoad(builder,
2752 ctx->abi.outputs[4 * loc + comp], "");
2753 tmp2 = ac_to_integer(&ctx->ac, tmp2);
2754 LLVMBuildStore(builder, tmp2, tmp);
2755 }
2756 }
2757 }
2758
2759 static void
2760 handle_ngg_outputs_post_2(struct radv_shader_context *ctx)
2761 {
2762 LLVMBuilderRef builder = ctx->ac.builder;
2763 LLVMValueRef tmp;
2764
2765 assert((ctx->stage == MESA_SHADER_VERTEX ||
2766 ctx->stage == MESA_SHADER_TESS_EVAL) && !ctx->args->is_gs_copy_shader);
2767
2768 LLVMValueRef prims_in_wave = ac_unpack_param(&ctx->ac,
2769 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 8, 8);
2770 LLVMValueRef vtx_in_wave = ac_unpack_param(&ctx->ac,
2771 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 0, 8);
2772 LLVMValueRef is_gs_thread = LLVMBuildICmp(builder, LLVMIntULT,
2773 ac_get_thread_id(&ctx->ac), prims_in_wave, "");
2774 LLVMValueRef is_es_thread = LLVMBuildICmp(builder, LLVMIntULT,
2775 ac_get_thread_id(&ctx->ac), vtx_in_wave, "");
2776 LLVMValueRef vtxindex[] = {
2777 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[0]), 0, 16),
2778 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[0]), 16, 16),
2779 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[2]), 0, 16),
2780 };
2781
2782 /* Determine the number of vertices per primitive. */
2783 unsigned num_vertices;
2784 LLVMValueRef num_vertices_val;
2785
2786 if (ctx->stage == MESA_SHADER_VERTEX) {
2787 LLVMValueRef outprim_val =
2788 LLVMConstInt(ctx->ac.i32,
2789 ctx->args->options->key.vs.outprim, false);
2790 num_vertices_val = LLVMBuildAdd(builder, outprim_val,
2791 ctx->ac.i32_1, "");
2792 num_vertices = 3; /* TODO: optimize for points & lines */
2793 } else {
2794 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2795
2796 if (ctx->shader->info.tess.point_mode)
2797 num_vertices = 1;
2798 else if (ctx->shader->info.tess.primitive_mode == GL_ISOLINES)
2799 num_vertices = 2;
2800 else
2801 num_vertices = 3;
2802
2803 num_vertices_val = LLVMConstInt(ctx->ac.i32, num_vertices, false);
2804 }
2805
2806 /* Streamout */
2807 if (ctx->args->shader_info->so.num_outputs) {
2808 struct ngg_streamout nggso = {};
2809
2810 nggso.num_vertices = num_vertices_val;
2811 nggso.prim_enable[0] = is_gs_thread;
2812
2813 for (unsigned i = 0; i < num_vertices; ++i)
2814 nggso.vertices[i] = ngg_nogs_vertex_ptr(ctx, vtxindex[i]);
2815
2816 build_streamout(ctx, &nggso);
2817 }
2818
2819 /* Copy Primitive IDs from GS threads to the LDS address corresponding
2820 * to the ES thread of the provoking vertex.
2821 */
2822 if (ctx->stage == MESA_SHADER_VERTEX &&
2823 ctx->args->options->key.vs_common_out.export_prim_id) {
2824 if (ctx->args->shader_info->so.num_outputs)
2825 ac_build_s_barrier(&ctx->ac);
2826
2827 ac_build_ifcc(&ctx->ac, is_gs_thread, 5400);
2828 /* Extract the PROVOKING_VTX_INDEX field. */
2829 LLVMValueRef provoking_vtx_in_prim =
2830 LLVMConstInt(ctx->ac.i32, 0, false);
2831
2832 /* provoking_vtx_index = vtxindex[provoking_vtx_in_prim]; */
2833 LLVMValueRef indices = ac_build_gather_values(&ctx->ac, vtxindex, 3);
2834 LLVMValueRef provoking_vtx_index =
2835 LLVMBuildExtractElement(builder, indices, provoking_vtx_in_prim, "");
2836
2837 LLVMBuildStore(builder, ac_get_arg(&ctx->ac, ctx->args->ac.gs_prim_id),
2838 ac_build_gep0(&ctx->ac, ctx->esgs_ring, provoking_vtx_index));
2839 ac_build_endif(&ctx->ac, 5400);
2840 }
2841
2842 /* TODO: primitive culling */
2843
2844 ac_build_sendmsg_gs_alloc_req(&ctx->ac, get_wave_id_in_tg(ctx),
2845 ngg_get_vtx_cnt(ctx), ngg_get_prim_cnt(ctx));
2846
2847 /* TODO: streamout queries */
2848 /* Export primitive data to the index buffer.
2849 *
2850 * For the first version, we will always build up all three indices
2851 * independent of the primitive type. The additional garbage data
2852 * shouldn't hurt.
2853 *
2854 * TODO: culling depends on the primitive type, so can have some
2855 * interaction here.
2856 */
2857 ac_build_ifcc(&ctx->ac, is_gs_thread, 6001);
2858 {
2859 struct ac_ngg_prim prim = {};
2860
2861 if (ctx->args->options->key.vs_common_out.as_ngg_passthrough) {
2862 prim.passthrough = ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[0]);
2863 } else {
2864 prim.num_vertices = num_vertices;
2865 prim.isnull = ctx->ac.i1false;
2866 memcpy(prim.index, vtxindex, sizeof(vtxindex[0]) * 3);
2867
2868 for (unsigned i = 0; i < num_vertices; ++i) {
2869 tmp = LLVMBuildLShr(builder,
2870 ac_get_arg(&ctx->ac, ctx->args->ac.gs_invocation_id),
2871 LLVMConstInt(ctx->ac.i32, 8 + i, false), "");
2872 prim.edgeflag[i] = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
2873 }
2874 }
2875
2876 ac_build_export_prim(&ctx->ac, &prim);
2877 }
2878 ac_build_endif(&ctx->ac, 6001);
2879
2880 /* Export per-vertex data (positions and parameters). */
2881 ac_build_ifcc(&ctx->ac, is_es_thread, 6002);
2882 {
2883 struct radv_vs_output_info *outinfo =
2884 ctx->stage == MESA_SHADER_TESS_EVAL ?
2885 &ctx->args->shader_info->tes.outinfo : &ctx->args->shader_info->vs.outinfo;
2886
2887 /* Exporting the primitive ID is handled below. */
2888 /* TODO: use the new VS export path */
2889 handle_vs_outputs_post(ctx, false,
2890 ctx->args->options->key.vs_common_out.export_clip_dists,
2891 outinfo);
2892
2893 if (ctx->args->options->key.vs_common_out.export_prim_id) {
2894 unsigned param_count = outinfo->param_exports;
2895 LLVMValueRef values[4];
2896
2897 if (ctx->stage == MESA_SHADER_VERTEX) {
2898 /* Wait for GS stores to finish. */
2899 ac_build_s_barrier(&ctx->ac);
2900
2901 tmp = ac_build_gep0(&ctx->ac, ctx->esgs_ring,
2902 get_thread_id_in_tg(ctx));
2903 values[0] = LLVMBuildLoad(builder, tmp, "");
2904 } else {
2905 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2906 values[0] = ac_get_arg(&ctx->ac, ctx->args->ac.tes_patch_id);
2907 }
2908
2909 values[0] = ac_to_float(&ctx->ac, values[0]);
2910 for (unsigned j = 1; j < 4; j++)
2911 values[j] = ctx->ac.f32_0;
2912
2913 radv_export_param(ctx, param_count, values, 0x1);
2914
2915 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
2916 outinfo->param_exports = param_count;
2917 }
2918 }
2919 ac_build_endif(&ctx->ac, 6002);
2920 }
2921
2922 static void gfx10_ngg_gs_emit_prologue(struct radv_shader_context *ctx)
2923 {
2924 /* Zero out the part of LDS scratch that is used to accumulate the
2925 * per-stream generated primitive count.
2926 */
2927 LLVMBuilderRef builder = ctx->ac.builder;
2928 LLVMValueRef scratchptr = ctx->gs_ngg_scratch;
2929 LLVMValueRef tid = get_thread_id_in_tg(ctx);
2930 LLVMBasicBlockRef merge_block;
2931 LLVMValueRef cond;
2932
2933 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
2934 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
2935 merge_block = LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
2936
2937 cond = LLVMBuildICmp(builder, LLVMIntULT, tid, LLVMConstInt(ctx->ac.i32, 4, false), "");
2938 LLVMBuildCondBr(ctx->ac.builder, cond, then_block, merge_block);
2939 LLVMPositionBuilderAtEnd(ctx->ac.builder, then_block);
2940
2941 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, scratchptr, tid);
2942 LLVMBuildStore(builder, ctx->ac.i32_0, ptr);
2943
2944 LLVMBuildBr(ctx->ac.builder, merge_block);
2945 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
2946
2947 ac_build_s_barrier(&ctx->ac);
2948 }
2949
2950 static void gfx10_ngg_gs_emit_epilogue_1(struct radv_shader_context *ctx)
2951 {
2952 LLVMBuilderRef builder = ctx->ac.builder;
2953 LLVMValueRef i8_0 = LLVMConstInt(ctx->ac.i8, 0, false);
2954 LLVMValueRef tmp;
2955
2956 /* Zero out remaining (non-emitted) primitive flags.
2957 *
2958 * Note: Alternatively, we could pass the relevant gs_next_vertex to
2959 * the emit threads via LDS. This is likely worse in the expected
2960 * typical case where each GS thread emits the full set of
2961 * vertices.
2962 */
2963 for (unsigned stream = 0; stream < 4; ++stream) {
2964 unsigned num_components;
2965
2966 num_components =
2967 ctx->args->shader_info->gs.num_stream_output_components[stream];
2968 if (!num_components)
2969 continue;
2970
2971 const LLVMValueRef gsthread = get_thread_id_in_tg(ctx);
2972
2973 ac_build_bgnloop(&ctx->ac, 5100);
2974
2975 const LLVMValueRef vertexidx =
2976 LLVMBuildLoad(builder, ctx->gs_next_vertex[stream], "");
2977 tmp = LLVMBuildICmp(builder, LLVMIntUGE, vertexidx,
2978 LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false), "");
2979 ac_build_ifcc(&ctx->ac, tmp, 5101);
2980 ac_build_break(&ctx->ac);
2981 ac_build_endif(&ctx->ac, 5101);
2982
2983 tmp = LLVMBuildAdd(builder, vertexidx, ctx->ac.i32_1, "");
2984 LLVMBuildStore(builder, tmp, ctx->gs_next_vertex[stream]);
2985
2986 tmp = ngg_gs_emit_vertex_ptr(ctx, gsthread, vertexidx);
2987 LLVMBuildStore(builder, i8_0,
2988 ngg_gs_get_emit_primflag_ptr(ctx, tmp, stream));
2989
2990 ac_build_endloop(&ctx->ac, 5100);
2991 }
2992
2993 /* Accumulate generated primitives counts across the entire threadgroup. */
2994 for (unsigned stream = 0; stream < 4; ++stream) {
2995 unsigned num_components;
2996
2997 num_components =
2998 ctx->args->shader_info->gs.num_stream_output_components[stream];
2999 if (!num_components)
3000 continue;
3001
3002 LLVMValueRef numprims =
3003 LLVMBuildLoad(builder, ctx->gs_generated_prims[stream], "");
3004 numprims = ac_build_reduce(&ctx->ac, numprims, nir_op_iadd, ctx->ac.wave_size);
3005
3006 tmp = LLVMBuildICmp(builder, LLVMIntEQ, ac_get_thread_id(&ctx->ac), ctx->ac.i32_0, "");
3007 ac_build_ifcc(&ctx->ac, tmp, 5105);
3008 {
3009 LLVMBuildAtomicRMW(builder, LLVMAtomicRMWBinOpAdd,
3010 ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch,
3011 LLVMConstInt(ctx->ac.i32, stream, false)),
3012 numprims, LLVMAtomicOrderingMonotonic, false);
3013 }
3014 ac_build_endif(&ctx->ac, 5105);
3015 }
3016 }
3017
3018 static void gfx10_ngg_gs_emit_epilogue_2(struct radv_shader_context *ctx)
3019 {
3020 const unsigned verts_per_prim = si_conv_gl_prim_to_vertices(ctx->shader->info.gs.output_primitive);
3021 LLVMBuilderRef builder = ctx->ac.builder;
3022 LLVMValueRef tmp, tmp2;
3023
3024 ac_build_s_barrier(&ctx->ac);
3025
3026 const LLVMValueRef tid = get_thread_id_in_tg(ctx);
3027 LLVMValueRef num_emit_threads = ngg_get_prim_cnt(ctx);
3028
3029 /* Streamout */
3030 if (ctx->args->shader_info->so.num_outputs) {
3031 struct ngg_streamout nggso = {};
3032
3033 nggso.num_vertices = LLVMConstInt(ctx->ac.i32, verts_per_prim, false);
3034
3035 LLVMValueRef vertexptr = ngg_gs_vertex_ptr(ctx, tid);
3036 for (unsigned stream = 0; stream < 4; ++stream) {
3037 if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
3038 continue;
3039
3040 tmp = LLVMBuildLoad(builder,
3041 ngg_gs_get_emit_primflag_ptr(ctx, vertexptr, stream), "");
3042 tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3043 tmp2 = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
3044 nggso.prim_enable[stream] = LLVMBuildAnd(builder, tmp, tmp2, "");
3045 }
3046
3047 for (unsigned i = 0; i < verts_per_prim; ++i) {
3048 tmp = LLVMBuildSub(builder, tid,
3049 LLVMConstInt(ctx->ac.i32, verts_per_prim - i - 1, false), "");
3050 tmp = ngg_gs_vertex_ptr(ctx, tmp);
3051 nggso.vertices[i] = ac_build_gep0(&ctx->ac, tmp, ctx->ac.i32_0);
3052 }
3053
3054 build_streamout(ctx, &nggso);
3055 }
3056
3057 /* Write shader query data. */
3058 tmp = ac_get_arg(&ctx->ac, ctx->args->ngg_gs_state);
3059 tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3060 ac_build_ifcc(&ctx->ac, tmp, 5109);
3061 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid,
3062 LLVMConstInt(ctx->ac.i32, 4, false), "");
3063 ac_build_ifcc(&ctx->ac, tmp, 5110);
3064 {
3065 tmp = LLVMBuildLoad(builder, ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tid), "");
3066
3067 ac_llvm_add_target_dep_function_attr(ctx->main_function,
3068 "amdgpu-gds-size", 256);
3069
3070 LLVMTypeRef gdsptr = LLVMPointerType(ctx->ac.i32, AC_ADDR_SPACE_GDS);
3071 LLVMValueRef gdsbase = LLVMBuildIntToPtr(builder, ctx->ac.i32_0, gdsptr, "");
3072
3073 const char *sync_scope = LLVM_VERSION_MAJOR >= 9 ? "workgroup-one-as" : "workgroup";
3074
3075 /* Use a plain GDS atomic to accumulate the number of generated
3076 * primitives.
3077 */
3078 ac_build_atomic_rmw(&ctx->ac, LLVMAtomicRMWBinOpAdd, gdsbase,
3079 tmp, sync_scope);
3080 }
3081 ac_build_endif(&ctx->ac, 5110);
3082 ac_build_endif(&ctx->ac, 5109);
3083
3084 /* TODO: culling */
3085
3086 /* Determine vertex liveness. */
3087 LLVMValueRef vertliveptr = ac_build_alloca(&ctx->ac, ctx->ac.i1, "vertexlive");
3088
3089 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
3090 ac_build_ifcc(&ctx->ac, tmp, 5120);
3091 {
3092 for (unsigned i = 0; i < verts_per_prim; ++i) {
3093 const LLVMValueRef primidx =
3094 LLVMBuildAdd(builder, tid,
3095 LLVMConstInt(ctx->ac.i32, i, false), "");
3096
3097 if (i > 0) {
3098 tmp = LLVMBuildICmp(builder, LLVMIntULT, primidx, num_emit_threads, "");
3099 ac_build_ifcc(&ctx->ac, tmp, 5121 + i);
3100 }
3101
3102 /* Load primitive liveness */
3103 tmp = ngg_gs_vertex_ptr(ctx, primidx);
3104 tmp = LLVMBuildLoad(builder,
3105 ngg_gs_get_emit_primflag_ptr(ctx, tmp, 0), "");
3106 const LLVMValueRef primlive =
3107 LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3108
3109 tmp = LLVMBuildLoad(builder, vertliveptr, "");
3110 tmp = LLVMBuildOr(builder, tmp, primlive, ""),
3111 LLVMBuildStore(builder, tmp, vertliveptr);
3112
3113 if (i > 0)
3114 ac_build_endif(&ctx->ac, 5121 + i);
3115 }
3116 }
3117 ac_build_endif(&ctx->ac, 5120);
3118
3119 /* Inclusive scan addition across the current wave. */
3120 LLVMValueRef vertlive = LLVMBuildLoad(builder, vertliveptr, "");
3121 struct ac_wg_scan vertlive_scan = {};
3122 vertlive_scan.op = nir_op_iadd;
3123 vertlive_scan.enable_reduce = true;
3124 vertlive_scan.enable_exclusive = true;
3125 vertlive_scan.src = vertlive;
3126 vertlive_scan.scratch = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, ctx->ac.i32_0);
3127 vertlive_scan.waveidx = get_wave_id_in_tg(ctx);
3128 vertlive_scan.numwaves = get_tgsize(ctx);
3129 vertlive_scan.maxwaves = 8;
3130
3131 ac_build_wg_scan(&ctx->ac, &vertlive_scan);
3132
3133 /* Skip all exports (including index exports) when possible. At least on
3134 * early gfx10 revisions this is also to avoid hangs.
3135 */
3136 LLVMValueRef have_exports =
3137 LLVMBuildICmp(builder, LLVMIntNE, vertlive_scan.result_reduce, ctx->ac.i32_0, "");
3138 num_emit_threads =
3139 LLVMBuildSelect(builder, have_exports, num_emit_threads, ctx->ac.i32_0, "");
3140
3141 /* Allocate export space. Send this message as early as possible, to
3142 * hide the latency of the SQ <-> SPI roundtrip.
3143 *
3144 * Note: We could consider compacting primitives for export as well.
3145 * PA processes 1 non-null prim / clock, but it fetches 4 DW of
3146 * prim data per clock and skips null primitives at no additional
3147 * cost. So compacting primitives can only be beneficial when
3148 * there are 4 or more contiguous null primitives in the export
3149 * (in the common case of single-dword prim exports).
3150 */
3151 ac_build_sendmsg_gs_alloc_req(&ctx->ac, get_wave_id_in_tg(ctx),
3152 vertlive_scan.result_reduce, num_emit_threads);
3153
3154 /* Setup the reverse vertex compaction permutation. We re-use stream 1
3155 * of the primitive liveness flags, relying on the fact that each
3156 * threadgroup can have at most 256 threads. */
3157 ac_build_ifcc(&ctx->ac, vertlive, 5130);
3158 {
3159 tmp = ngg_gs_vertex_ptr(ctx, vertlive_scan.result_exclusive);
3160 tmp2 = LLVMBuildTrunc(builder, tid, ctx->ac.i8, "");
3161 LLVMBuildStore(builder, tmp2,
3162 ngg_gs_get_emit_primflag_ptr(ctx, tmp, 1));
3163 }
3164 ac_build_endif(&ctx->ac, 5130);
3165
3166 ac_build_s_barrier(&ctx->ac);
3167
3168 /* Export primitive data */
3169 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
3170 ac_build_ifcc(&ctx->ac, tmp, 5140);
3171 {
3172 LLVMValueRef flags;
3173 struct ac_ngg_prim prim = {};
3174 prim.num_vertices = verts_per_prim;
3175
3176 tmp = ngg_gs_vertex_ptr(ctx, tid);
3177 flags = LLVMBuildLoad(builder,
3178 ngg_gs_get_emit_primflag_ptr(ctx, tmp, 0), "");
3179 prim.isnull = LLVMBuildNot(builder, LLVMBuildTrunc(builder, flags, ctx->ac.i1, ""), "");
3180
3181 for (unsigned i = 0; i < verts_per_prim; ++i) {
3182 prim.index[i] = LLVMBuildSub(builder, vertlive_scan.result_exclusive,
3183 LLVMConstInt(ctx->ac.i32, verts_per_prim - i - 1, false), "");
3184 prim.edgeflag[i] = ctx->ac.i1false;
3185 }
3186
3187 /* Geometry shaders output triangle strips, but NGG expects
3188 * triangles. We need to change the vertex order for odd
3189 * triangles to get correct front/back facing by swapping 2
3190 * vertex indices, but we also have to keep the provoking
3191 * vertex in the same place.
3192 */
3193 if (verts_per_prim == 3) {
3194 LLVMValueRef is_odd = LLVMBuildLShr(builder, flags, ctx->ac.i8_1, "");
3195 is_odd = LLVMBuildTrunc(builder, is_odd, ctx->ac.i1, "");
3196
3197 struct ac_ngg_prim in = prim;
3198 prim.index[0] = in.index[0];
3199 prim.index[1] = LLVMBuildSelect(builder, is_odd,
3200 in.index[2], in.index[1], "");
3201 prim.index[2] = LLVMBuildSelect(builder, is_odd,
3202 in.index[1], in.index[2], "");
3203 }
3204
3205 ac_build_export_prim(&ctx->ac, &prim);
3206 }
3207 ac_build_endif(&ctx->ac, 5140);
3208
3209 /* Export position and parameter data */
3210 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, vertlive_scan.result_reduce, "");
3211 ac_build_ifcc(&ctx->ac, tmp, 5145);
3212 {
3213 struct radv_vs_output_info *outinfo = &ctx->args->shader_info->vs.outinfo;
3214 bool export_view_index = ctx->args->options->key.has_multiview_view_index;
3215 struct radv_shader_output_values *outputs;
3216 unsigned noutput = 0;
3217
3218 /* Allocate a temporary array for the output values. */
3219 unsigned num_outputs = util_bitcount64(ctx->output_mask) + export_view_index;
3220 outputs = calloc(num_outputs, sizeof(outputs[0]));
3221
3222 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
3223 sizeof(outinfo->vs_output_param_offset));
3224 outinfo->pos_exports = 0;
3225
3226 tmp = ngg_gs_vertex_ptr(ctx, tid);
3227 tmp = LLVMBuildLoad(builder,
3228 ngg_gs_get_emit_primflag_ptr(ctx, tmp, 1), "");
3229 tmp = LLVMBuildZExt(builder, tmp, ctx->ac.i32, "");
3230 const LLVMValueRef vertexptr = ngg_gs_vertex_ptr(ctx, tmp);
3231
3232 unsigned out_idx = 0;
3233 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3234 unsigned output_usage_mask =
3235 ctx->args->shader_info->gs.output_usage_mask[i];
3236 int length = util_last_bit(output_usage_mask);
3237
3238 if (!(ctx->output_mask & (1ull << i)))
3239 continue;
3240
3241 outputs[noutput].slot_name = i;
3242 outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
3243 outputs[noutput].usage_mask = output_usage_mask;
3244
3245 for (unsigned j = 0; j < length; j++, out_idx++) {
3246 if (!(output_usage_mask & (1 << j)))
3247 continue;
3248
3249 tmp = ngg_gs_get_emit_output_ptr(ctx, vertexptr, out_idx);
3250 tmp = LLVMBuildLoad(builder, tmp, "");
3251
3252 LLVMTypeRef type = LLVMGetAllocatedType(ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
3253 if (ac_get_type_size(type) == 2) {
3254 tmp = ac_to_integer(&ctx->ac, tmp);
3255 tmp = LLVMBuildTrunc(ctx->ac.builder, tmp, ctx->ac.i16, "");
3256 }
3257
3258 outputs[noutput].values[j] = ac_to_float(&ctx->ac, tmp);
3259 }
3260
3261 for (unsigned j = length; j < 4; j++)
3262 outputs[noutput].values[j] = LLVMGetUndef(ctx->ac.f32);
3263
3264 noutput++;
3265 }
3266
3267 /* Export ViewIndex. */
3268 if (export_view_index) {
3269 outputs[noutput].slot_name = VARYING_SLOT_LAYER;
3270 outputs[noutput].slot_index = 0;
3271 outputs[noutput].usage_mask = 0x1;
3272 outputs[noutput].values[0] =
3273 ac_to_float(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->ac.view_index));
3274 for (unsigned j = 1; j < 4; j++)
3275 outputs[noutput].values[j] = ctx->ac.f32_0;
3276 noutput++;
3277 }
3278
3279 radv_llvm_export_vs(ctx, outputs, noutput, outinfo,
3280 ctx->args->options->key.vs_common_out.export_clip_dists);
3281 FREE(outputs);
3282 }
3283 ac_build_endif(&ctx->ac, 5145);
3284 }
3285
3286 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context *ctx,
3287 unsigned stream,
3288 LLVMValueRef vertexidx,
3289 LLVMValueRef *addrs)
3290 {
3291 LLVMBuilderRef builder = ctx->ac.builder;
3292 LLVMValueRef tmp;
3293
3294 const LLVMValueRef vertexptr =
3295 ngg_gs_emit_vertex_ptr(ctx, get_thread_id_in_tg(ctx), vertexidx);
3296 unsigned out_idx = 0;
3297 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3298 unsigned output_usage_mask =
3299 ctx->args->shader_info->gs.output_usage_mask[i];
3300 uint8_t output_stream =
3301 ctx->args->shader_info->gs.output_streams[i];
3302 LLVMValueRef *out_ptr = &addrs[i * 4];
3303 int length = util_last_bit(output_usage_mask);
3304
3305 if (!(ctx->output_mask & (1ull << i)) ||
3306 output_stream != stream)
3307 continue;
3308
3309 for (unsigned j = 0; j < length; j++, out_idx++) {
3310 if (!(output_usage_mask & (1 << j)))
3311 continue;
3312
3313 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
3314 out_ptr[j], "");
3315 out_val = ac_to_integer(&ctx->ac, out_val);
3316 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
3317
3318 LLVMBuildStore(builder, out_val,
3319 ngg_gs_get_emit_output_ptr(ctx, vertexptr, out_idx));
3320 }
3321 }
3322 assert(out_idx * 4 <= ctx->args->shader_info->gs.gsvs_vertex_size);
3323
3324 /* Store the current number of emitted vertices to zero out remaining
3325 * primitive flags in case the geometry shader doesn't emit the maximum
3326 * number of vertices.
3327 */
3328 tmp = LLVMBuildAdd(builder, vertexidx, ctx->ac.i32_1, "");
3329 LLVMBuildStore(builder, tmp, ctx->gs_next_vertex[stream]);
3330
3331 /* Determine and store whether this vertex completed a primitive. */
3332 const LLVMValueRef curverts = LLVMBuildLoad(builder, ctx->gs_curprim_verts[stream], "");
3333
3334 tmp = LLVMConstInt(ctx->ac.i32, si_conv_gl_prim_to_vertices(ctx->shader->info.gs.output_primitive) - 1, false);
3335 const LLVMValueRef iscompleteprim =
3336 LLVMBuildICmp(builder, LLVMIntUGE, curverts, tmp, "");
3337
3338 /* Since the geometry shader emits triangle strips, we need to
3339 * track which primitive is odd and swap vertex indices to get
3340 * the correct vertex order.
3341 */
3342 LLVMValueRef is_odd = ctx->ac.i1false;
3343 if (stream == 0 &&
3344 si_conv_gl_prim_to_vertices(ctx->shader->info.gs.output_primitive) == 3) {
3345 tmp = LLVMBuildAnd(builder, curverts, ctx->ac.i32_1, "");
3346 is_odd = LLVMBuildICmp(builder, LLVMIntEQ, tmp, ctx->ac.i32_1, "");
3347 }
3348
3349 tmp = LLVMBuildAdd(builder, curverts, ctx->ac.i32_1, "");
3350 LLVMBuildStore(builder, tmp, ctx->gs_curprim_verts[stream]);
3351
3352 /* The per-vertex primitive flag encoding:
3353 * bit 0: whether this vertex finishes a primitive
3354 * bit 1: whether the primitive is odd (if we are emitting triangle strips)
3355 */
3356 tmp = LLVMBuildZExt(builder, iscompleteprim, ctx->ac.i8, "");
3357 tmp = LLVMBuildOr(builder, tmp,
3358 LLVMBuildShl(builder,
3359 LLVMBuildZExt(builder, is_odd, ctx->ac.i8, ""),
3360 ctx->ac.i8_1, ""), "");
3361 LLVMBuildStore(builder, tmp,
3362 ngg_gs_get_emit_primflag_ptr(ctx, vertexptr, stream));
3363
3364 tmp = LLVMBuildLoad(builder, ctx->gs_generated_prims[stream], "");
3365 tmp = LLVMBuildAdd(builder, tmp, LLVMBuildZExt(builder, iscompleteprim, ctx->ac.i32, ""), "");
3366 LLVMBuildStore(builder, tmp, ctx->gs_generated_prims[stream]);
3367 }
3368
3369 static void
3370 write_tess_factors(struct radv_shader_context *ctx)
3371 {
3372 unsigned stride, outer_comps, inner_comps;
3373 LLVMValueRef tcs_rel_ids = ac_get_arg(&ctx->ac, ctx->args->ac.tcs_rel_ids);
3374 LLVMValueRef invocation_id = ac_unpack_param(&ctx->ac, tcs_rel_ids, 8, 5);
3375 LLVMValueRef rel_patch_id = ac_unpack_param(&ctx->ac, tcs_rel_ids, 0, 8);
3376 unsigned tess_inner_index = 0, tess_outer_index;
3377 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
3378 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
3379 int i;
3380 ac_emit_barrier(&ctx->ac, ctx->stage);
3381
3382 switch (ctx->args->options->key.tcs.primitive_mode) {
3383 case GL_ISOLINES:
3384 stride = 2;
3385 outer_comps = 2;
3386 inner_comps = 0;
3387 break;
3388 case GL_TRIANGLES:
3389 stride = 4;
3390 outer_comps = 3;
3391 inner_comps = 1;
3392 break;
3393 case GL_QUADS:
3394 stride = 6;
3395 outer_comps = 4;
3396 inner_comps = 2;
3397 break;
3398 default:
3399 return;
3400 }
3401
3402 ac_build_ifcc(&ctx->ac,
3403 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3404 invocation_id, ctx->ac.i32_0, ""), 6503);
3405
3406 lds_base = get_tcs_out_current_patch_data_offset(ctx);
3407
3408 if (inner_comps) {
3409 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
3410 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
3411 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
3412 }
3413
3414 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
3415 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
3416 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
3417
3418 for (i = 0; i < 4; i++) {
3419 inner[i] = LLVMGetUndef(ctx->ac.i32);
3420 outer[i] = LLVMGetUndef(ctx->ac.i32);
3421 }
3422
3423 // LINES reversal
3424 if (ctx->args->options->key.tcs.primitive_mode == GL_ISOLINES) {
3425 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
3426 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
3427 ctx->ac.i32_1, "");
3428 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
3429 } else {
3430 for (i = 0; i < outer_comps; i++) {
3431 outer[i] = out[i] =
3432 ac_lds_load(&ctx->ac, lds_outer);
3433 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
3434 ctx->ac.i32_1, "");
3435 }
3436 for (i = 0; i < inner_comps; i++) {
3437 inner[i] = out[outer_comps+i] =
3438 ac_lds_load(&ctx->ac, lds_inner);
3439 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
3440 ctx->ac.i32_1, "");
3441 }
3442 }
3443
3444 /* Convert the outputs to vectors for stores. */
3445 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
3446 vec1 = NULL;
3447
3448 if (stride > 4)
3449 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
3450
3451
3452 buffer = ctx->hs_ring_tess_factor;
3453 tf_base = ac_get_arg(&ctx->ac, ctx->args->tess_factor_offset);
3454 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
3455 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
3456 unsigned tf_offset = 0;
3457
3458 if (ctx->ac.chip_class <= GFX8) {
3459 ac_build_ifcc(&ctx->ac,
3460 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3461 rel_patch_id, ctx->ac.i32_0, ""), 6504);
3462
3463 /* Store the dynamic HS control word. */
3464 ac_build_buffer_store_dword(&ctx->ac, buffer,
3465 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
3466 1, ctx->ac.i32_0, tf_base,
3467 0, ac_glc);
3468 tf_offset += 4;
3469
3470 ac_build_endif(&ctx->ac, 6504);
3471 }
3472
3473 /* Store the tessellation factors. */
3474 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
3475 MIN2(stride, 4), byteoffset, tf_base,
3476 tf_offset, ac_glc);
3477 if (vec1)
3478 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
3479 stride - 4, byteoffset, tf_base,
3480 16 + tf_offset, ac_glc);
3481
3482 //store to offchip for TES to read - only if TES reads them
3483 if (ctx->args->options->key.tcs.tes_reads_tess_factors) {
3484 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
3485 LLVMValueRef tf_inner_offset;
3486 unsigned param_outer, param_inner;
3487
3488 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
3489 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
3490 LLVMConstInt(ctx->ac.i32, param_outer, 0));
3491
3492 outer_vec = ac_build_gather_values(&ctx->ac, outer,
3493 util_next_power_of_two(outer_comps));
3494
3495 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
3496 outer_comps, tf_outer_offset,
3497 ac_get_arg(&ctx->ac, ctx->args->oc_lds),
3498 0, ac_glc);
3499 if (inner_comps) {
3500 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
3501 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
3502 LLVMConstInt(ctx->ac.i32, param_inner, 0));
3503
3504 inner_vec = inner_comps == 1 ? inner[0] :
3505 ac_build_gather_values(&ctx->ac, inner, inner_comps);
3506 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
3507 inner_comps, tf_inner_offset,
3508 ac_get_arg(&ctx->ac, ctx->args->oc_lds),
3509 0, ac_glc);
3510 }
3511 }
3512
3513 ac_build_endif(&ctx->ac, 6503);
3514 }
3515
3516 static void
3517 handle_tcs_outputs_post(struct radv_shader_context *ctx)
3518 {
3519 write_tess_factors(ctx);
3520 }
3521
3522 static bool
3523 si_export_mrt_color(struct radv_shader_context *ctx,
3524 LLVMValueRef *color, unsigned index,
3525 struct ac_export_args *args)
3526 {
3527 /* Export */
3528 si_llvm_init_export_args(ctx, color, 0xf,
3529 V_008DFC_SQ_EXP_MRT + index, args);
3530 if (!args->enabled_channels)
3531 return false; /* unnecessary NULL export */
3532
3533 return true;
3534 }
3535
3536 static void
3537 radv_export_mrt_z(struct radv_shader_context *ctx,
3538 LLVMValueRef depth, LLVMValueRef stencil,
3539 LLVMValueRef samplemask)
3540 {
3541 struct ac_export_args args;
3542
3543 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3544
3545 ac_build_export(&ctx->ac, &args);
3546 }
3547
3548 static void
3549 handle_fs_outputs_post(struct radv_shader_context *ctx)
3550 {
3551 unsigned index = 0;
3552 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3553 struct ac_export_args color_args[8];
3554
3555 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3556 LLVMValueRef values[4];
3557
3558 if (!(ctx->output_mask & (1ull << i)))
3559 continue;
3560
3561 if (i < FRAG_RESULT_DATA0)
3562 continue;
3563
3564 for (unsigned j = 0; j < 4; j++)
3565 values[j] = ac_to_float(&ctx->ac,
3566 radv_load_output(ctx, i, j));
3567
3568 bool ret = si_export_mrt_color(ctx, values,
3569 i - FRAG_RESULT_DATA0,
3570 &color_args[index]);
3571 if (ret)
3572 index++;
3573 }
3574
3575 /* Process depth, stencil, samplemask. */
3576 if (ctx->args->shader_info->ps.writes_z) {
3577 depth = ac_to_float(&ctx->ac,
3578 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
3579 }
3580 if (ctx->args->shader_info->ps.writes_stencil) {
3581 stencil = ac_to_float(&ctx->ac,
3582 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
3583 }
3584 if (ctx->args->shader_info->ps.writes_sample_mask) {
3585 samplemask = ac_to_float(&ctx->ac,
3586 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
3587 }
3588
3589 /* Set the DONE bit on last non-null color export only if Z isn't
3590 * exported.
3591 */
3592 if (index > 0 &&
3593 !ctx->args->shader_info->ps.writes_z &&
3594 !ctx->args->shader_info->ps.writes_stencil &&
3595 !ctx->args->shader_info->ps.writes_sample_mask) {
3596 unsigned last = index - 1;
3597
3598 color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */
3599 color_args[last].done = 1; /* DONE bit */
3600 }
3601
3602 /* Export PS outputs. */
3603 for (unsigned i = 0; i < index; i++)
3604 ac_build_export(&ctx->ac, &color_args[i]);
3605
3606 if (depth || stencil || samplemask)
3607 radv_export_mrt_z(ctx, depth, stencil, samplemask);
3608 else if (!index)
3609 ac_build_export_null(&ctx->ac);
3610 }
3611
3612 static void
3613 emit_gs_epilogue(struct radv_shader_context *ctx)
3614 {
3615 if (ctx->args->options->key.vs_common_out.as_ngg) {
3616 gfx10_ngg_gs_emit_epilogue_1(ctx);
3617 return;
3618 }
3619
3620 if (ctx->ac.chip_class >= GFX10)
3621 LLVMBuildFence(ctx->ac.builder, LLVMAtomicOrderingRelease, false, "");
3622
3623 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
3624 }
3625
3626 static void
3627 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
3628 LLVMValueRef *addrs)
3629 {
3630 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3631
3632 switch (ctx->stage) {
3633 case MESA_SHADER_VERTEX:
3634 if (ctx->args->options->key.vs_common_out.as_ls)
3635 handle_ls_outputs_post(ctx);
3636 else if (ctx->args->options->key.vs_common_out.as_es)
3637 handle_es_outputs_post(ctx, &ctx->args->shader_info->vs.es_info);
3638 else if (ctx->args->options->key.vs_common_out.as_ngg)
3639 handle_ngg_outputs_post_1(ctx);
3640 else
3641 handle_vs_outputs_post(ctx, ctx->args->options->key.vs_common_out.export_prim_id,
3642 ctx->args->options->key.vs_common_out.export_clip_dists,
3643 &ctx->args->shader_info->vs.outinfo);
3644 break;
3645 case MESA_SHADER_FRAGMENT:
3646 handle_fs_outputs_post(ctx);
3647 break;
3648 case MESA_SHADER_GEOMETRY:
3649 emit_gs_epilogue(ctx);
3650 break;
3651 case MESA_SHADER_TESS_CTRL:
3652 handle_tcs_outputs_post(ctx);
3653 break;
3654 case MESA_SHADER_TESS_EVAL:
3655 if (ctx->args->options->key.vs_common_out.as_es)
3656 handle_es_outputs_post(ctx, &ctx->args->shader_info->tes.es_info);
3657 else if (ctx->args->options->key.vs_common_out.as_ngg)
3658 handle_ngg_outputs_post_1(ctx);
3659 else
3660 handle_vs_outputs_post(ctx, ctx->args->options->key.vs_common_out.export_prim_id,
3661 ctx->args->options->key.vs_common_out.export_clip_dists,
3662 &ctx->args->shader_info->tes.outinfo);
3663 break;
3664 default:
3665 break;
3666 }
3667 }
3668
3669 static void ac_llvm_finalize_module(struct radv_shader_context *ctx,
3670 LLVMPassManagerRef passmgr,
3671 const struct radv_nir_compiler_options *options)
3672 {
3673 LLVMRunPassManager(passmgr, ctx->ac.module);
3674 LLVMDisposeBuilder(ctx->ac.builder);
3675
3676 ac_llvm_context_dispose(&ctx->ac);
3677 }
3678
3679 static void
3680 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
3681 {
3682 struct radv_vs_output_info *outinfo;
3683
3684 switch (ctx->stage) {
3685 case MESA_SHADER_FRAGMENT:
3686 case MESA_SHADER_COMPUTE:
3687 case MESA_SHADER_TESS_CTRL:
3688 case MESA_SHADER_GEOMETRY:
3689 return;
3690 case MESA_SHADER_VERTEX:
3691 if (ctx->args->options->key.vs_common_out.as_ls ||
3692 ctx->args->options->key.vs_common_out.as_es)
3693 return;
3694 outinfo = &ctx->args->shader_info->vs.outinfo;
3695 break;
3696 case MESA_SHADER_TESS_EVAL:
3697 if (ctx->args->options->key.vs_common_out.as_es)
3698 return;
3699 outinfo = &ctx->args->shader_info->tes.outinfo;
3700 break;
3701 default:
3702 unreachable("Unhandled shader type");
3703 }
3704
3705 ac_optimize_vs_outputs(&ctx->ac,
3706 ctx->main_function,
3707 outinfo->vs_output_param_offset,
3708 VARYING_SLOT_MAX,
3709 &outinfo->param_exports);
3710 }
3711
3712 static void
3713 ac_setup_rings(struct radv_shader_context *ctx)
3714 {
3715 if (ctx->args->options->chip_class <= GFX8 &&
3716 (ctx->stage == MESA_SHADER_GEOMETRY ||
3717 ctx->args->options->key.vs_common_out.as_es || ctx->args->options->key.vs_common_out.as_es)) {
3718 unsigned ring = ctx->stage == MESA_SHADER_GEOMETRY ? RING_ESGS_GS
3719 : RING_ESGS_VS;
3720 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, ring, false);
3721
3722 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac,
3723 ctx->ring_offsets,
3724 offset);
3725 }
3726
3727 if (ctx->args->is_gs_copy_shader) {
3728 ctx->gsvs_ring[0] =
3729 ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets,
3730 LLVMConstInt(ctx->ac.i32,
3731 RING_GSVS_VS, false));
3732 }
3733
3734 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3735 /* The conceptual layout of the GSVS ring is
3736 * v0c0 .. vLv0 v0c1 .. vLc1 ..
3737 * but the real memory layout is swizzled across
3738 * threads:
3739 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
3740 * t16v0c0 ..
3741 * Override the buffer descriptor accordingly.
3742 */
3743 LLVMTypeRef v2i64 = LLVMVectorType(ctx->ac.i64, 2);
3744 uint64_t stream_offset = 0;
3745 unsigned num_records = ctx->ac.wave_size;
3746 LLVMValueRef base_ring;
3747
3748 base_ring =
3749 ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets,
3750 LLVMConstInt(ctx->ac.i32,
3751 RING_GSVS_GS, false));
3752
3753 for (unsigned stream = 0; stream < 4; stream++) {
3754 unsigned num_components, stride;
3755 LLVMValueRef ring, tmp;
3756
3757 num_components =
3758 ctx->args->shader_info->gs.num_stream_output_components[stream];
3759
3760 if (!num_components)
3761 continue;
3762
3763 stride = 4 * num_components * ctx->shader->info.gs.vertices_out;
3764
3765 /* Limit on the stride field for <= GFX7. */
3766 assert(stride < (1 << 14));
3767
3768 ring = LLVMBuildBitCast(ctx->ac.builder,
3769 base_ring, v2i64, "");
3770 tmp = LLVMBuildExtractElement(ctx->ac.builder,
3771 ring, ctx->ac.i32_0, "");
3772 tmp = LLVMBuildAdd(ctx->ac.builder, tmp,
3773 LLVMConstInt(ctx->ac.i64,
3774 stream_offset, 0), "");
3775 ring = LLVMBuildInsertElement(ctx->ac.builder,
3776 ring, tmp, ctx->ac.i32_0, "");
3777
3778 stream_offset += stride * ctx->ac.wave_size;
3779
3780 ring = LLVMBuildBitCast(ctx->ac.builder, ring,
3781 ctx->ac.v4i32, "");
3782
3783 tmp = LLVMBuildExtractElement(ctx->ac.builder, ring,
3784 ctx->ac.i32_1, "");
3785 tmp = LLVMBuildOr(ctx->ac.builder, tmp,
3786 LLVMConstInt(ctx->ac.i32,
3787 S_008F04_STRIDE(stride), false), "");
3788 ring = LLVMBuildInsertElement(ctx->ac.builder, ring, tmp,
3789 ctx->ac.i32_1, "");
3790
3791 ring = LLVMBuildInsertElement(ctx->ac.builder, ring,
3792 LLVMConstInt(ctx->ac.i32,
3793 num_records, false),
3794 LLVMConstInt(ctx->ac.i32, 2, false), "");
3795
3796 ctx->gsvs_ring[stream] = ring;
3797 }
3798 }
3799
3800 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3801 ctx->stage == MESA_SHADER_TESS_EVAL) {
3802 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
3803 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
3804 }
3805 }
3806
3807 unsigned
3808 radv_nir_get_max_workgroup_size(enum chip_class chip_class,
3809 gl_shader_stage stage,
3810 const struct nir_shader *nir)
3811 {
3812 const unsigned backup_sizes[] = {chip_class >= GFX9 ? 128 : 64, 1, 1};
3813 unsigned sizes[3];
3814 for (unsigned i = 0; i < 3; i++)
3815 sizes[i] = nir ? nir->info.cs.local_size[i] : backup_sizes[i];
3816 return radv_get_max_workgroup_size(chip_class, stage, sizes);
3817 }
3818
3819 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
3820 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
3821 {
3822 LLVMValueRef count =
3823 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 8, 8);
3824 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
3825 ctx->ac.i32_0, "");
3826 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty,
3827 ac_get_arg(&ctx->ac, ctx->args->rel_auto_id),
3828 ctx->abi.instance_id, "");
3829 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty,
3830 ac_get_arg(&ctx->ac, ctx->args->ac.tcs_rel_ids),
3831 ctx->rel_auto_id,
3832 "");
3833 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty,
3834 ac_get_arg(&ctx->ac, ctx->args->ac.tcs_patch_id),
3835 ctx->abi.vertex_id, "");
3836 }
3837
3838 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx, bool merged)
3839 {
3840 if (merged) {
3841 for(int i = 5; i >= 0; --i) {
3842 ctx->gs_vtx_offset[i] =
3843 ac_unpack_param(&ctx->ac,
3844 ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[i & ~1]),
3845 (i & 1) * 16, 16);
3846 }
3847
3848 ctx->gs_wave_id = ac_unpack_param(&ctx->ac,
3849 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info),
3850 16, 8);
3851 } else {
3852 for (int i = 0; i < 6; i++)
3853 ctx->gs_vtx_offset[i] = ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[i]);
3854 ctx->gs_wave_id = ac_get_arg(&ctx->ac, ctx->args->gs_wave_id);
3855 }
3856 }
3857
3858 /* Ensure that the esgs ring is declared.
3859 *
3860 * We declare it with 64KB alignment as a hint that the
3861 * pointer value will always be 0.
3862 */
3863 static void declare_esgs_ring(struct radv_shader_context *ctx)
3864 {
3865 if (ctx->esgs_ring)
3866 return;
3867
3868 assert(!LLVMGetNamedGlobal(ctx->ac.module, "esgs_ring"));
3869
3870 ctx->esgs_ring = LLVMAddGlobalInAddressSpace(
3871 ctx->ac.module, LLVMArrayType(ctx->ac.i32, 0),
3872 "esgs_ring",
3873 AC_ADDR_SPACE_LDS);
3874 LLVMSetLinkage(ctx->esgs_ring, LLVMExternalLinkage);
3875 LLVMSetAlignment(ctx->esgs_ring, 64 * 1024);
3876 }
3877
3878 static
3879 LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
3880 struct nir_shader *const *shaders,
3881 int shader_count,
3882 const struct radv_shader_args *args)
3883 {
3884 struct radv_shader_context ctx = {0};
3885 ctx.args = args;
3886
3887 enum ac_float_mode float_mode = AC_FLOAT_MODE_DEFAULT;
3888
3889 if (args->shader_info->float_controls_mode & FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32) {
3890 float_mode = AC_FLOAT_MODE_DENORM_FLUSH_TO_ZERO;
3891 }
3892
3893 ac_llvm_context_init(&ctx.ac, ac_llvm, args->options->chip_class,
3894 args->options->family, float_mode,
3895 args->shader_info->wave_size,
3896 args->shader_info->ballot_bit_size);
3897 ctx.context = ctx.ac.context;
3898
3899 ctx.max_workgroup_size = 0;
3900 for (int i = 0; i < shader_count; ++i) {
3901 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
3902 radv_nir_get_max_workgroup_size(args->options->chip_class,
3903 shaders[i]->info.stage,
3904 shaders[i]));
3905 }
3906
3907 if (ctx.ac.chip_class >= GFX10) {
3908 if (is_pre_gs_stage(shaders[0]->info.stage) &&
3909 args->options->key.vs_common_out.as_ngg) {
3910 ctx.max_workgroup_size = 128;
3911 }
3912 }
3913
3914 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2);
3915
3916 ctx.abi.inputs = &ctx.inputs[0];
3917 ctx.abi.emit_outputs = handle_shader_outputs_post;
3918 ctx.abi.emit_vertex_with_counter = visit_emit_vertex_with_counter;
3919 ctx.abi.load_ubo = radv_load_ubo;
3920 ctx.abi.load_ssbo = radv_load_ssbo;
3921 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
3922 ctx.abi.load_resource = radv_load_resource;
3923 ctx.abi.clamp_shadow_reference = false;
3924 ctx.abi.robust_buffer_access = args->options->robust_buffer_access;
3925
3926 bool is_ngg = is_pre_gs_stage(shaders[0]->info.stage) && args->options->key.vs_common_out.as_ngg;
3927 if (shader_count >= 2 || is_ngg)
3928 ac_init_exec_full_mask(&ctx.ac);
3929
3930 if (args->ac.vertex_id.used)
3931 ctx.abi.vertex_id = ac_get_arg(&ctx.ac, args->ac.vertex_id);
3932 if (args->rel_auto_id.used)
3933 ctx.rel_auto_id = ac_get_arg(&ctx.ac, args->rel_auto_id);
3934 if (args->ac.instance_id.used)
3935 ctx.abi.instance_id = ac_get_arg(&ctx.ac, args->ac.instance_id);
3936
3937 if (args->options->has_ls_vgpr_init_bug &&
3938 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
3939 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
3940
3941 if (is_ngg) {
3942 /* Declare scratch space base for streamout and vertex
3943 * compaction. Whether space is actually allocated is
3944 * determined during linking / PM4 creation.
3945 *
3946 * Add an extra dword per vertex to ensure an odd stride, which
3947 * avoids bank conflicts for SoA accesses.
3948 */
3949 if (!args->options->key.vs_common_out.as_ngg_passthrough)
3950 declare_esgs_ring(&ctx);
3951
3952 /* This is really only needed when streamout and / or vertex
3953 * compaction is enabled.
3954 */
3955 if (args->shader_info->so.num_outputs) {
3956 LLVMTypeRef asi32 = LLVMArrayType(ctx.ac.i32, 8);
3957 ctx.gs_ngg_scratch = LLVMAddGlobalInAddressSpace(ctx.ac.module,
3958 asi32, "ngg_scratch", AC_ADDR_SPACE_LDS);
3959 LLVMSetInitializer(ctx.gs_ngg_scratch, LLVMGetUndef(asi32));
3960 LLVMSetAlignment(ctx.gs_ngg_scratch, 4);
3961 }
3962 }
3963
3964 for(int i = 0; i < shader_count; ++i) {
3965 ctx.stage = shaders[i]->info.stage;
3966 ctx.shader = shaders[i];
3967 ctx.output_mask = 0;
3968
3969 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3970 for (int i = 0; i < 4; i++) {
3971 ctx.gs_next_vertex[i] =
3972 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
3973 }
3974 if (args->options->key.vs_common_out.as_ngg) {
3975 for (unsigned i = 0; i < 4; ++i) {
3976 ctx.gs_curprim_verts[i] =
3977 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
3978 ctx.gs_generated_prims[i] =
3979 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
3980 }
3981
3982 unsigned scratch_size = 8;
3983 if (args->shader_info->so.num_outputs)
3984 scratch_size = 44;
3985
3986 LLVMTypeRef ai32 = LLVMArrayType(ctx.ac.i32, scratch_size);
3987 ctx.gs_ngg_scratch =
3988 LLVMAddGlobalInAddressSpace(ctx.ac.module,
3989 ai32, "ngg_scratch", AC_ADDR_SPACE_LDS);
3990 LLVMSetInitializer(ctx.gs_ngg_scratch, LLVMGetUndef(ai32));
3991 LLVMSetAlignment(ctx.gs_ngg_scratch, 4);
3992
3993 ctx.gs_ngg_emit = LLVMAddGlobalInAddressSpace(ctx.ac.module,
3994 LLVMArrayType(ctx.ac.i32, 0), "ngg_emit", AC_ADDR_SPACE_LDS);
3995 LLVMSetLinkage(ctx.gs_ngg_emit, LLVMExternalLinkage);
3996 LLVMSetAlignment(ctx.gs_ngg_emit, 4);
3997 }
3998
3999 ctx.abi.load_inputs = load_gs_input;
4000 ctx.abi.emit_primitive = visit_end_primitive;
4001 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
4002 ctx.abi.load_tess_varyings = load_tcs_varyings;
4003 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
4004 ctx.abi.store_tcs_outputs = store_tcs_output;
4005 if (shader_count == 1)
4006 ctx.tcs_num_inputs = args->options->key.tcs.num_inputs;
4007 else
4008 ctx.tcs_num_inputs = util_last_bit64(args->shader_info->vs.ls_outputs_written);
4009 ctx.tcs_num_patches =
4010 get_tcs_num_patches(
4011 ctx.args->options->key.tcs.input_vertices,
4012 ctx.shader->info.tess.tcs_vertices_out,
4013 ctx.tcs_num_inputs,
4014 ctx.args->shader_info->tcs.outputs_written,
4015 ctx.args->shader_info->tcs.patch_outputs_written,
4016 ctx.args->options->tess_offchip_block_dw_size,
4017 ctx.args->options->chip_class,
4018 ctx.args->options->family);
4019 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
4020 ctx.abi.load_tess_varyings = load_tes_input;
4021 ctx.abi.load_tess_coord = load_tess_coord;
4022 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
4023 ctx.tcs_num_patches = args->options->key.tes.num_patches;
4024 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
4025 ctx.abi.load_base_vertex = radv_load_base_vertex;
4026 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
4027 ctx.abi.load_sample_position = load_sample_position;
4028 ctx.abi.load_sample_mask_in = load_sample_mask_in;
4029 }
4030
4031 if (shaders[i]->info.stage == MESA_SHADER_VERTEX &&
4032 args->options->key.vs_common_out.as_ngg &&
4033 args->options->key.vs_common_out.export_prim_id) {
4034 declare_esgs_ring(&ctx);
4035 }
4036
4037 bool nested_barrier = false;
4038
4039 if (i) {
4040 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
4041 args->options->key.vs_common_out.as_ngg) {
4042 gfx10_ngg_gs_emit_prologue(&ctx);
4043 nested_barrier = false;
4044 } else {
4045 nested_barrier = true;
4046 }
4047 }
4048
4049 if (nested_barrier) {
4050 /* Execute a barrier before the second shader in
4051 * a merged shader.
4052 *
4053 * Execute the barrier inside the conditional block,
4054 * so that empty waves can jump directly to s_endpgm,
4055 * which will also signal the barrier.
4056 *
4057 * This is possible in gfx9, because an empty wave
4058 * for the second shader does not participate in
4059 * the epilogue. With NGG, empty waves may still
4060 * be required to export data (e.g. GS output vertices),
4061 * so we cannot let them exit early.
4062 *
4063 * If the shader is TCS and the TCS epilog is present
4064 * and contains a barrier, it will wait there and then
4065 * reach s_endpgm.
4066 */
4067 ac_emit_barrier(&ctx.ac, ctx.stage);
4068 }
4069
4070 nir_foreach_variable(variable, &shaders[i]->outputs)
4071 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
4072
4073 ac_setup_rings(&ctx);
4074
4075 LLVMBasicBlockRef merge_block = NULL;
4076 if (shader_count >= 2 || is_ngg) {
4077 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
4078 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
4079 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
4080
4081 LLVMValueRef count =
4082 ac_unpack_param(&ctx.ac,
4083 ac_get_arg(&ctx.ac, args->merged_wave_info),
4084 8 * i, 8);
4085 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
4086 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
4087 thread_id, count, "");
4088 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
4089
4090 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
4091 }
4092
4093 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
4094 prepare_interp_optimize(&ctx, shaders[i]);
4095 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
4096 handle_vs_inputs(&ctx, shaders[i]);
4097 else if(shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
4098 prepare_gs_input_vgprs(&ctx, shader_count >= 2);
4099
4100 ac_nir_translate(&ctx.ac, &ctx.abi, &args->ac, shaders[i]);
4101
4102 if (shader_count >= 2 || is_ngg) {
4103 LLVMBuildBr(ctx.ac.builder, merge_block);
4104 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
4105 }
4106
4107 /* This needs to be outside the if wrapping the shader body, as sometimes
4108 * the HW generates waves with 0 es/vs threads. */
4109 if (is_pre_gs_stage(shaders[i]->info.stage) &&
4110 args->options->key.vs_common_out.as_ngg &&
4111 i == shader_count - 1) {
4112 handle_ngg_outputs_post_2(&ctx);
4113 } else if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
4114 args->options->key.vs_common_out.as_ngg) {
4115 gfx10_ngg_gs_emit_epilogue_2(&ctx);
4116 }
4117
4118 if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
4119 args->shader_info->tcs.num_patches = ctx.tcs_num_patches;
4120 args->shader_info->tcs.lds_size =
4121 calculate_tess_lds_size(
4122 ctx.args->options->key.tcs.input_vertices,
4123 ctx.shader->info.tess.tcs_vertices_out,
4124 ctx.tcs_num_inputs,
4125 ctx.tcs_num_patches,
4126 ctx.args->shader_info->tcs.outputs_written,
4127 ctx.args->shader_info->tcs.patch_outputs_written);
4128 }
4129 }
4130
4131 LLVMBuildRetVoid(ctx.ac.builder);
4132
4133 if (args->options->dump_preoptir) {
4134 fprintf(stderr, "%s LLVM IR:\n\n",
4135 radv_get_shader_name(args->shader_info,
4136 shaders[shader_count - 1]->info.stage));
4137 ac_dump_module(ctx.ac.module);
4138 fprintf(stderr, "\n");
4139 }
4140
4141 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, args->options);
4142
4143 if (shader_count == 1)
4144 ac_nir_eliminate_const_vs_outputs(&ctx);
4145
4146 if (args->options->dump_shader) {
4147 args->shader_info->private_mem_vgprs =
4148 ac_count_scratch_private_memory(ctx.main_function);
4149 }
4150
4151 return ctx.ac.module;
4152 }
4153
4154 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
4155 {
4156 unsigned *retval = (unsigned *)context;
4157 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
4158 char *description = LLVMGetDiagInfoDescription(di);
4159
4160 if (severity == LLVMDSError) {
4161 *retval = 1;
4162 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
4163 description);
4164 }
4165
4166 LLVMDisposeMessage(description);
4167 }
4168
4169 static unsigned radv_llvm_compile(LLVMModuleRef M,
4170 char **pelf_buffer, size_t *pelf_size,
4171 struct ac_llvm_compiler *ac_llvm)
4172 {
4173 unsigned retval = 0;
4174 LLVMContextRef llvm_ctx;
4175
4176 /* Setup Diagnostic Handler*/
4177 llvm_ctx = LLVMGetModuleContext(M);
4178
4179 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
4180 &retval);
4181
4182 /* Compile IR*/
4183 if (!radv_compile_to_elf(ac_llvm, M, pelf_buffer, pelf_size))
4184 retval = 1;
4185 return retval;
4186 }
4187
4188 static void ac_compile_llvm_module(struct ac_llvm_compiler *ac_llvm,
4189 LLVMModuleRef llvm_module,
4190 struct radv_shader_binary **rbinary,
4191 gl_shader_stage stage,
4192 const char *name,
4193 const struct radv_nir_compiler_options *options)
4194 {
4195 char *elf_buffer = NULL;
4196 size_t elf_size = 0;
4197 char *llvm_ir_string = NULL;
4198
4199 if (options->dump_shader) {
4200 fprintf(stderr, "%s LLVM IR:\n\n", name);
4201 ac_dump_module(llvm_module);
4202 fprintf(stderr, "\n");
4203 }
4204
4205 if (options->record_ir) {
4206 char *llvm_ir = LLVMPrintModuleToString(llvm_module);
4207 llvm_ir_string = strdup(llvm_ir);
4208 LLVMDisposeMessage(llvm_ir);
4209 }
4210
4211 int v = radv_llvm_compile(llvm_module, &elf_buffer, &elf_size, ac_llvm);
4212 if (v) {
4213 fprintf(stderr, "compile failed\n");
4214 }
4215
4216 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
4217 LLVMDisposeModule(llvm_module);
4218 LLVMContextDispose(ctx);
4219
4220 size_t llvm_ir_size = llvm_ir_string ? strlen(llvm_ir_string) : 0;
4221 size_t alloc_size = sizeof(struct radv_shader_binary_rtld) + elf_size + llvm_ir_size + 1;
4222 struct radv_shader_binary_rtld *rbin = calloc(1, alloc_size);
4223 memcpy(rbin->data, elf_buffer, elf_size);
4224 if (llvm_ir_string)
4225 memcpy(rbin->data + elf_size, llvm_ir_string, llvm_ir_size + 1);
4226
4227 rbin->base.type = RADV_BINARY_TYPE_RTLD;
4228 rbin->base.stage = stage;
4229 rbin->base.total_size = alloc_size;
4230 rbin->elf_size = elf_size;
4231 rbin->llvm_ir_size = llvm_ir_size;
4232 *rbinary = &rbin->base;
4233
4234 free(llvm_ir_string);
4235 free(elf_buffer);
4236 }
4237
4238 static void
4239 radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
4240 struct radv_shader_binary **rbinary,
4241 const struct radv_shader_args *args,
4242 struct nir_shader *const *nir,
4243 int nir_count)
4244 {
4245
4246 LLVMModuleRef llvm_module;
4247
4248 llvm_module = ac_translate_nir_to_llvm(ac_llvm, nir, nir_count, args);
4249
4250 ac_compile_llvm_module(ac_llvm, llvm_module, rbinary,
4251 nir[nir_count - 1]->info.stage,
4252 radv_get_shader_name(args->shader_info,
4253 nir[nir_count - 1]->info.stage),
4254 args->options);
4255
4256 /* Determine the ES type (VS or TES) for the GS on GFX9. */
4257 if (args->options->chip_class >= GFX9) {
4258 if (nir_count == 2 &&
4259 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
4260 args->shader_info->gs.es_type = nir[0]->info.stage;
4261 }
4262 }
4263 }
4264
4265 static void
4266 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
4267 {
4268 LLVMValueRef vtx_offset =
4269 LLVMBuildMul(ctx->ac.builder, ac_get_arg(&ctx->ac, ctx->args->ac.vertex_id),
4270 LLVMConstInt(ctx->ac.i32, 4, false), "");
4271 LLVMValueRef stream_id;
4272
4273 /* Fetch the vertex stream ID. */
4274 if (!ctx->args->options->use_ngg_streamout &&
4275 ctx->args->shader_info->so.num_outputs) {
4276 stream_id =
4277 ac_unpack_param(&ctx->ac,
4278 ac_get_arg(&ctx->ac,
4279 ctx->args->streamout_config),
4280 24, 2);
4281 } else {
4282 stream_id = ctx->ac.i32_0;
4283 }
4284
4285 LLVMBasicBlockRef end_bb;
4286 LLVMValueRef switch_inst;
4287
4288 end_bb = LLVMAppendBasicBlockInContext(ctx->ac.context,
4289 ctx->main_function, "end");
4290 switch_inst = LLVMBuildSwitch(ctx->ac.builder, stream_id, end_bb, 4);
4291
4292 for (unsigned stream = 0; stream < 4; stream++) {
4293 unsigned num_components =
4294 ctx->args->shader_info->gs.num_stream_output_components[stream];
4295 LLVMBasicBlockRef bb;
4296 unsigned offset;
4297
4298 if (stream > 0 && !num_components)
4299 continue;
4300
4301 if (stream > 0 && !ctx->args->shader_info->so.num_outputs)
4302 continue;
4303
4304 bb = LLVMInsertBasicBlockInContext(ctx->ac.context, end_bb, "out");
4305 LLVMAddCase(switch_inst, LLVMConstInt(ctx->ac.i32, stream, 0), bb);
4306 LLVMPositionBuilderAtEnd(ctx->ac.builder, bb);
4307
4308 offset = 0;
4309 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
4310 unsigned output_usage_mask =
4311 ctx->args->shader_info->gs.output_usage_mask[i];
4312 unsigned output_stream =
4313 ctx->args->shader_info->gs.output_streams[i];
4314 int length = util_last_bit(output_usage_mask);
4315
4316 if (!(ctx->output_mask & (1ull << i)) ||
4317 output_stream != stream)
4318 continue;
4319
4320 for (unsigned j = 0; j < length; j++) {
4321 LLVMValueRef value, soffset;
4322
4323 if (!(output_usage_mask & (1 << j)))
4324 continue;
4325
4326 soffset = LLVMConstInt(ctx->ac.i32,
4327 offset *
4328 ctx->shader->info.gs.vertices_out * 16 * 4, false);
4329
4330 offset++;
4331
4332 value = ac_build_buffer_load(&ctx->ac,
4333 ctx->gsvs_ring[0],
4334 1, ctx->ac.i32_0,
4335 vtx_offset, soffset,
4336 0, ac_glc | ac_slc, true, false);
4337
4338 LLVMTypeRef type = LLVMGetAllocatedType(ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
4339 if (ac_get_type_size(type) == 2) {
4340 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
4341 value = LLVMBuildTrunc(ctx->ac.builder, value, ctx->ac.i16, "");
4342 }
4343
4344 LLVMBuildStore(ctx->ac.builder,
4345 ac_to_float(&ctx->ac, value), ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
4346 }
4347 }
4348
4349 if (!ctx->args->options->use_ngg_streamout &&
4350 ctx->args->shader_info->so.num_outputs)
4351 radv_emit_streamout(ctx, stream);
4352
4353 if (stream == 0) {
4354 handle_vs_outputs_post(ctx, false, true,
4355 &ctx->args->shader_info->vs.outinfo);
4356 }
4357
4358 LLVMBuildBr(ctx->ac.builder, end_bb);
4359 }
4360
4361 LLVMPositionBuilderAtEnd(ctx->ac.builder, end_bb);
4362 }
4363
4364 static void
4365 radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
4366 struct nir_shader *geom_shader,
4367 struct radv_shader_binary **rbinary,
4368 const struct radv_shader_args *args)
4369 {
4370 struct radv_shader_context ctx = {0};
4371 ctx.args = args;
4372
4373 assert(args->is_gs_copy_shader);
4374
4375 ac_llvm_context_init(&ctx.ac, ac_llvm, args->options->chip_class,
4376 args->options->family, AC_FLOAT_MODE_DEFAULT, 64, 64);
4377 ctx.context = ctx.ac.context;
4378
4379 ctx.stage = MESA_SHADER_VERTEX;
4380 ctx.shader = geom_shader;
4381
4382 create_function(&ctx, MESA_SHADER_VERTEX, false);
4383
4384 ac_setup_rings(&ctx);
4385
4386 nir_foreach_variable(variable, &geom_shader->outputs) {
4387 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
4388 ac_handle_shader_output_decl(&ctx.ac, &ctx.abi, geom_shader,
4389 variable, MESA_SHADER_VERTEX);
4390 }
4391
4392 ac_gs_copy_shader_emit(&ctx);
4393
4394 LLVMBuildRetVoid(ctx.ac.builder);
4395
4396 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, args->options);
4397
4398 ac_compile_llvm_module(ac_llvm, ctx.ac.module, rbinary,
4399 MESA_SHADER_VERTEX, "GS Copy Shader", args->options);
4400 (*rbinary)->is_gs_copy_shader = true;
4401
4402 }
4403
4404 void
4405 llvm_compile_shader(struct radv_device *device,
4406 unsigned shader_count,
4407 struct nir_shader *const *shaders,
4408 struct radv_shader_binary **binary,
4409 struct radv_shader_args *args)
4410 {
4411 enum ac_target_machine_options tm_options = 0;
4412 struct ac_llvm_compiler ac_llvm;
4413 bool thread_compiler;
4414
4415 tm_options |= AC_TM_SUPPORTS_SPILL;
4416 if (args->options->check_ir)
4417 tm_options |= AC_TM_CHECK_IR;
4418 if (device->instance->debug_flags & RADV_DEBUG_NO_LOAD_STORE_OPT)
4419 tm_options |= AC_TM_NO_LOAD_STORE_OPT;
4420
4421 thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM);
4422
4423 radv_init_llvm_compiler(&ac_llvm, thread_compiler,
4424 args->options->family, tm_options,
4425 args->shader_info->wave_size);
4426
4427 if (args->is_gs_copy_shader) {
4428 radv_compile_gs_copy_shader(&ac_llvm, *shaders, binary, args);
4429 } else {
4430 radv_compile_nir_shader(&ac_llvm, binary, args,
4431 shaders, shader_count);
4432 }
4433
4434 radv_destroy_llvm_compiler(&ac_llvm, thread_compiler);
4435 }