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radv/gfx10: use the component mask when storing/loading NGG stream outputs
[mesa.git] / src / amd / vulkan / radv_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "radv_shader_helper.h"
31 #include "nir/nir.h"
32
33 #include <llvm-c/Core.h>
34 #include <llvm-c/TargetMachine.h>
35 #include <llvm-c/Transforms/Scalar.h>
36 #include <llvm-c/Transforms/Utils.h>
37
38 #include "sid.h"
39 #include "ac_binary.h"
40 #include "ac_llvm_util.h"
41 #include "ac_llvm_build.h"
42 #include "ac_shader_abi.h"
43 #include "ac_shader_util.h"
44 #include "ac_exp_param.h"
45
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47
48 struct radv_shader_context {
49 struct ac_llvm_context ac;
50 const struct radv_nir_compiler_options *options;
51 struct radv_shader_info *shader_info;
52 const struct nir_shader *shader;
53 struct ac_shader_abi abi;
54
55 unsigned max_workgroup_size;
56 LLVMContextRef context;
57 LLVMValueRef main_function;
58
59 LLVMValueRef descriptor_sets[MAX_SETS];
60 LLVMValueRef ring_offsets;
61
62 LLVMValueRef vertex_buffers;
63 LLVMValueRef rel_auto_id;
64 LLVMValueRef vs_prim_id;
65 LLVMValueRef es2gs_offset;
66
67 LLVMValueRef oc_lds;
68 LLVMValueRef merged_wave_info;
69 LLVMValueRef tess_factor_offset;
70 LLVMValueRef tes_rel_patch_id;
71 LLVMValueRef tes_u;
72 LLVMValueRef tes_v;
73
74 /* HW GS */
75 /* On gfx10:
76 * - bits 0..10: ordered_wave_id
77 * - bits 12..20: number of vertices in group
78 * - bits 22..30: number of primitives in group
79 */
80 LLVMValueRef gs_tg_info;
81 LLVMValueRef gs2vs_offset;
82 LLVMValueRef gs_wave_id;
83 LLVMValueRef gs_vtx_offset[6];
84
85 LLVMValueRef esgs_ring;
86 LLVMValueRef gsvs_ring[4];
87 LLVMValueRef hs_ring_tess_offchip;
88 LLVMValueRef hs_ring_tess_factor;
89
90 /* Streamout */
91 LLVMValueRef streamout_buffers;
92 LLVMValueRef streamout_write_idx;
93 LLVMValueRef streamout_config;
94 LLVMValueRef streamout_offset[4];
95
96 gl_shader_stage stage;
97
98 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
99
100 uint64_t output_mask;
101
102 bool is_gs_copy_shader;
103 LLVMValueRef gs_next_vertex[4];
104 LLVMValueRef gs_curprim_verts[4];
105 LLVMValueRef gs_generated_prims[4];
106 LLVMValueRef gs_ngg_emit;
107 LLVMValueRef gs_ngg_scratch;
108
109 uint32_t tcs_num_inputs;
110 uint32_t tcs_num_patches;
111
112 LLVMValueRef vertexptr; /* GFX10 only */
113 };
114
115 struct radv_shader_output_values {
116 LLVMValueRef values[4];
117 unsigned slot_name;
118 unsigned slot_index;
119 unsigned usage_mask;
120 };
121
122 enum radeon_llvm_calling_convention {
123 RADEON_LLVM_AMDGPU_VS = 87,
124 RADEON_LLVM_AMDGPU_GS = 88,
125 RADEON_LLVM_AMDGPU_PS = 89,
126 RADEON_LLVM_AMDGPU_CS = 90,
127 RADEON_LLVM_AMDGPU_HS = 93,
128 };
129
130 static inline struct radv_shader_context *
131 radv_shader_context_from_abi(struct ac_shader_abi *abi)
132 {
133 struct radv_shader_context *ctx = NULL;
134 return container_of(abi, ctx, abi);
135 }
136
137 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
138 {
139 switch (ctx->stage) {
140 case MESA_SHADER_TESS_CTRL:
141 return ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
142 case MESA_SHADER_TESS_EVAL:
143 return ctx->tes_rel_patch_id;
144 break;
145 default:
146 unreachable("Illegal stage");
147 }
148 }
149
150 static unsigned
151 get_tcs_num_patches(struct radv_shader_context *ctx)
152 {
153 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
154 unsigned num_tcs_output_cp = ctx->shader->info.tess.tcs_vertices_out;
155 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
156 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
157 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->tcs.outputs_written);
158 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->tcs.patch_outputs_written);
159 uint32_t output_vertex_size = num_tcs_outputs * 16;
160 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
161 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
162 unsigned num_patches;
163 unsigned hardware_lds_size;
164
165 /* Ensure that we only need one wave per SIMD so we don't need to check
166 * resource usage. Also ensures that the number of tcs in and out
167 * vertices per threadgroup are at most 256.
168 */
169 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
170 /* Make sure that the data fits in LDS. This assumes the shaders only
171 * use LDS for the inputs and outputs.
172 */
173 hardware_lds_size = 32768;
174
175 /* Looks like STONEY hangs if we use more than 32 KiB LDS in a single
176 * threadgroup, even though there is more than 32 KiB LDS.
177 *
178 * Test: dEQP-VK.tessellation.shader_input_output.barrier
179 */
180 if (ctx->options->chip_class >= GFX7 && ctx->options->family != CHIP_STONEY)
181 hardware_lds_size = 65536;
182
183 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
184 /* Make sure the output data fits in the offchip buffer */
185 num_patches = MIN2(num_patches, (ctx->options->tess_offchip_block_dw_size * 4) / output_patch_size);
186 /* Not necessary for correctness, but improves performance. The
187 * specific value is taken from the proprietary driver.
188 */
189 num_patches = MIN2(num_patches, 40);
190
191 /* GFX6 bug workaround - limit LS-HS threadgroups to only one wave. */
192 if (ctx->options->chip_class == GFX6) {
193 unsigned one_wave = ctx->options->wave_size / MAX2(num_tcs_input_cp, num_tcs_output_cp);
194 num_patches = MIN2(num_patches, one_wave);
195 }
196 return num_patches;
197 }
198
199 static unsigned
200 calculate_tess_lds_size(struct radv_shader_context *ctx)
201 {
202 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
203 unsigned num_tcs_output_cp;
204 unsigned num_tcs_outputs, num_tcs_patch_outputs;
205 unsigned input_vertex_size, output_vertex_size;
206 unsigned input_patch_size, output_patch_size;
207 unsigned pervertex_output_patch_size;
208 unsigned output_patch0_offset;
209 unsigned num_patches;
210 unsigned lds_size;
211
212 num_tcs_output_cp = ctx->shader->info.tess.tcs_vertices_out;
213 num_tcs_outputs = util_last_bit64(ctx->shader_info->tcs.outputs_written);
214 num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->tcs.patch_outputs_written);
215
216 input_vertex_size = ctx->tcs_num_inputs * 16;
217 output_vertex_size = num_tcs_outputs * 16;
218
219 input_patch_size = num_tcs_input_cp * input_vertex_size;
220
221 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
222 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
223
224 num_patches = ctx->tcs_num_patches;
225 output_patch0_offset = input_patch_size * num_patches;
226
227 lds_size = output_patch0_offset + output_patch_size * num_patches;
228 return lds_size;
229 }
230
231 /* Tessellation shaders pass outputs to the next shader using LDS.
232 *
233 * LS outputs = TCS inputs
234 * TCS outputs = TES inputs
235 *
236 * The LDS layout is:
237 * - TCS inputs for patch 0
238 * - TCS inputs for patch 1
239 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
240 * - ...
241 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
242 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
243 * - TCS outputs for patch 1
244 * - Per-patch TCS outputs for patch 1
245 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
246 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
247 * - ...
248 *
249 * All three shaders VS(LS), TCS, TES share the same LDS space.
250 */
251 static LLVMValueRef
252 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
253 {
254 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
255 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
256 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
257
258 input_patch_size /= 4;
259 return LLVMConstInt(ctx->ac.i32, input_patch_size, false);
260 }
261
262 static LLVMValueRef
263 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
264 {
265 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->tcs.outputs_written);
266 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->tcs.patch_outputs_written);
267 uint32_t output_vertex_size = num_tcs_outputs * 16;
268 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
269 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
270 output_patch_size /= 4;
271 return LLVMConstInt(ctx->ac.i32, output_patch_size, false);
272 }
273
274 static LLVMValueRef
275 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
276 {
277 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->tcs.outputs_written);
278 uint32_t output_vertex_size = num_tcs_outputs * 16;
279 output_vertex_size /= 4;
280 return LLVMConstInt(ctx->ac.i32, output_vertex_size, false);
281 }
282
283 static LLVMValueRef
284 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
285 {
286 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
287 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
288 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
289 uint32_t output_patch0_offset = input_patch_size;
290 unsigned num_patches = ctx->tcs_num_patches;
291
292 output_patch0_offset *= num_patches;
293 output_patch0_offset /= 4;
294 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
295 }
296
297 static LLVMValueRef
298 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
299 {
300 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
301 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
302 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
303 uint32_t output_patch0_offset = input_patch_size;
304
305 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->tcs.outputs_written);
306 uint32_t output_vertex_size = num_tcs_outputs * 16;
307 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
308 unsigned num_patches = ctx->tcs_num_patches;
309
310 output_patch0_offset *= num_patches;
311 output_patch0_offset += pervertex_output_patch_size;
312 output_patch0_offset /= 4;
313 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
314 }
315
316 static LLVMValueRef
317 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
318 {
319 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
320 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
321
322 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
323 }
324
325 static LLVMValueRef
326 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
327 {
328 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
329 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
330 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
331
332 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
333 patch0_offset);
334 }
335
336 static LLVMValueRef
337 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
338 {
339 LLVMValueRef patch0_patch_data_offset =
340 get_tcs_out_patch0_patch_data_offset(ctx);
341 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
342 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
343
344 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
345 patch0_patch_data_offset);
346 }
347
348 #define MAX_ARGS 64
349 struct arg_info {
350 LLVMTypeRef types[MAX_ARGS];
351 LLVMValueRef *assign[MAX_ARGS];
352 uint8_t count;
353 uint8_t sgpr_count;
354 uint8_t num_sgprs_used;
355 uint8_t num_vgprs_used;
356 };
357
358 enum ac_arg_regfile {
359 ARG_SGPR,
360 ARG_VGPR,
361 };
362
363 static void
364 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
365 LLVMValueRef *param_ptr)
366 {
367 assert(info->count < MAX_ARGS);
368
369 info->assign[info->count] = param_ptr;
370 info->types[info->count] = type;
371 info->count++;
372
373 if (regfile == ARG_SGPR) {
374 info->num_sgprs_used += ac_get_type_size(type) / 4;
375 info->sgpr_count++;
376 } else {
377 assert(regfile == ARG_VGPR);
378 info->num_vgprs_used += ac_get_type_size(type) / 4;
379 }
380 }
381
382 static void assign_arguments(LLVMValueRef main_function,
383 struct arg_info *info)
384 {
385 unsigned i;
386 for (i = 0; i < info->count; i++) {
387 if (info->assign[i])
388 *info->assign[i] = LLVMGetParam(main_function, i);
389 }
390 }
391
392 static LLVMValueRef
393 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
394 LLVMBuilderRef builder, LLVMTypeRef *return_types,
395 unsigned num_return_elems,
396 struct arg_info *args,
397 unsigned max_workgroup_size,
398 const struct radv_nir_compiler_options *options)
399 {
400 LLVMTypeRef main_function_type, ret_type;
401 LLVMBasicBlockRef main_function_body;
402
403 if (num_return_elems)
404 ret_type = LLVMStructTypeInContext(ctx, return_types,
405 num_return_elems, true);
406 else
407 ret_type = LLVMVoidTypeInContext(ctx);
408
409 /* Setup the function */
410 main_function_type =
411 LLVMFunctionType(ret_type, args->types, args->count, 0);
412 LLVMValueRef main_function =
413 LLVMAddFunction(module, "main", main_function_type);
414 main_function_body =
415 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
416 LLVMPositionBuilderAtEnd(builder, main_function_body);
417
418 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
419 for (unsigned i = 0; i < args->sgpr_count; ++i) {
420 LLVMValueRef P = LLVMGetParam(main_function, i);
421
422 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
423
424 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
425 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
426 ac_add_attr_dereferenceable(P, UINT64_MAX);
427 }
428 }
429
430 if (options->address32_hi) {
431 ac_llvm_add_target_dep_function_attr(main_function,
432 "amdgpu-32bit-address-high-bits",
433 options->address32_hi);
434 }
435
436 ac_llvm_set_workgroup_size(main_function, max_workgroup_size);
437
438 if (options->unsafe_math) {
439 /* These were copied from some LLVM test. */
440 LLVMAddTargetDependentFunctionAttr(main_function,
441 "less-precise-fpmad",
442 "true");
443 LLVMAddTargetDependentFunctionAttr(main_function,
444 "no-infs-fp-math",
445 "true");
446 LLVMAddTargetDependentFunctionAttr(main_function,
447 "no-nans-fp-math",
448 "true");
449 LLVMAddTargetDependentFunctionAttr(main_function,
450 "unsafe-fp-math",
451 "true");
452 LLVMAddTargetDependentFunctionAttr(main_function,
453 "no-signed-zeros-fp-math",
454 "true");
455 }
456 return main_function;
457 }
458
459
460 static void
461 set_loc(struct radv_userdata_info *ud_info, uint8_t *sgpr_idx,
462 uint8_t num_sgprs)
463 {
464 ud_info->sgpr_idx = *sgpr_idx;
465 ud_info->num_sgprs = num_sgprs;
466 *sgpr_idx += num_sgprs;
467 }
468
469 static void
470 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
471 uint8_t num_sgprs)
472 {
473 struct radv_userdata_info *ud_info =
474 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
475 assert(ud_info);
476
477 set_loc(ud_info, sgpr_idx, num_sgprs);
478 }
479
480 static void
481 set_loc_shader_ptr(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx)
482 {
483 bool use_32bit_pointers = idx != AC_UD_SCRATCH_RING_OFFSETS;
484
485 set_loc_shader(ctx, idx, sgpr_idx, use_32bit_pointers ? 1 : 2);
486 }
487
488 static void
489 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx)
490 {
491 struct radv_userdata_locations *locs =
492 &ctx->shader_info->user_sgprs_locs;
493 struct radv_userdata_info *ud_info = &locs->descriptor_sets[idx];
494 assert(ud_info);
495
496 set_loc(ud_info, sgpr_idx, 1);
497
498 locs->descriptor_sets_enabled |= 1 << idx;
499 }
500
501 struct user_sgpr_info {
502 bool need_ring_offsets;
503 bool indirect_all_descriptor_sets;
504 uint8_t remaining_sgprs;
505 };
506
507 static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
508 gl_shader_stage stage)
509 {
510 switch (stage) {
511 case MESA_SHADER_VERTEX:
512 if (ctx->shader_info->needs_multiview_view_index ||
513 (!ctx->options->key.vs_common_out.as_es && !ctx->options->key.vs_common_out.as_ls && ctx->options->key.has_multiview_view_index))
514 return true;
515 break;
516 case MESA_SHADER_TESS_EVAL:
517 if (ctx->shader_info->needs_multiview_view_index || (!ctx->options->key.vs_common_out.as_es && ctx->options->key.has_multiview_view_index))
518 return true;
519 break;
520 case MESA_SHADER_GEOMETRY:
521 case MESA_SHADER_TESS_CTRL:
522 if (ctx->shader_info->needs_multiview_view_index)
523 return true;
524 break;
525 default:
526 break;
527 }
528 return false;
529 }
530
531 static uint8_t
532 count_vs_user_sgprs(struct radv_shader_context *ctx)
533 {
534 uint8_t count = 0;
535
536 if (ctx->shader_info->vs.has_vertex_buffers)
537 count++;
538 count += ctx->shader_info->vs.needs_draw_id ? 3 : 2;
539
540 return count;
541 }
542
543 static void allocate_inline_push_consts(struct radv_shader_context *ctx,
544 struct user_sgpr_info *user_sgpr_info)
545 {
546 uint8_t remaining_sgprs = user_sgpr_info->remaining_sgprs;
547
548 /* Only supported if shaders use push constants. */
549 if (ctx->shader_info->min_push_constant_used == UINT8_MAX)
550 return;
551
552 /* Only supported if shaders don't have indirect push constants. */
553 if (ctx->shader_info->has_indirect_push_constants)
554 return;
555
556 /* Only supported for 32-bit push constants. */
557 if (!ctx->shader_info->has_only_32bit_push_constants)
558 return;
559
560 uint8_t num_push_consts =
561 (ctx->shader_info->max_push_constant_used -
562 ctx->shader_info->min_push_constant_used) / 4;
563
564 /* Check if the number of user SGPRs is large enough. */
565 if (num_push_consts < remaining_sgprs) {
566 ctx->shader_info->num_inline_push_consts = num_push_consts;
567 } else {
568 ctx->shader_info->num_inline_push_consts = remaining_sgprs;
569 }
570
571 /* Clamp to the maximum number of allowed inlined push constants. */
572 if (ctx->shader_info->num_inline_push_consts > AC_MAX_INLINE_PUSH_CONSTS)
573 ctx->shader_info->num_inline_push_consts = AC_MAX_INLINE_PUSH_CONSTS;
574
575 if (ctx->shader_info->num_inline_push_consts == num_push_consts &&
576 !ctx->shader_info->loads_dynamic_offsets) {
577 /* Disable the default push constants path if all constants are
578 * inlined and if shaders don't use dynamic descriptors.
579 */
580 ctx->shader_info->loads_push_constants = false;
581 }
582
583 ctx->shader_info->base_inline_push_consts =
584 ctx->shader_info->min_push_constant_used / 4;
585 }
586
587 static void allocate_user_sgprs(struct radv_shader_context *ctx,
588 gl_shader_stage stage,
589 bool has_previous_stage,
590 gl_shader_stage previous_stage,
591 bool needs_view_index,
592 struct user_sgpr_info *user_sgpr_info)
593 {
594 uint8_t user_sgpr_count = 0;
595
596 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
597
598 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
599 if (stage == MESA_SHADER_GEOMETRY ||
600 stage == MESA_SHADER_VERTEX ||
601 stage == MESA_SHADER_TESS_CTRL ||
602 stage == MESA_SHADER_TESS_EVAL ||
603 ctx->is_gs_copy_shader)
604 user_sgpr_info->need_ring_offsets = true;
605
606 if (stage == MESA_SHADER_FRAGMENT &&
607 ctx->shader_info->ps.needs_sample_positions)
608 user_sgpr_info->need_ring_offsets = true;
609
610 /* 2 user sgprs will nearly always be allocated for scratch/rings */
611 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
612 user_sgpr_count += 2;
613 }
614
615 switch (stage) {
616 case MESA_SHADER_COMPUTE:
617 if (ctx->shader_info->cs.uses_grid_size)
618 user_sgpr_count += 3;
619 break;
620 case MESA_SHADER_FRAGMENT:
621 user_sgpr_count += ctx->shader_info->ps.needs_sample_positions;
622 break;
623 case MESA_SHADER_VERTEX:
624 if (!ctx->is_gs_copy_shader)
625 user_sgpr_count += count_vs_user_sgprs(ctx);
626 break;
627 case MESA_SHADER_TESS_CTRL:
628 if (has_previous_stage) {
629 if (previous_stage == MESA_SHADER_VERTEX)
630 user_sgpr_count += count_vs_user_sgprs(ctx);
631 }
632 break;
633 case MESA_SHADER_TESS_EVAL:
634 break;
635 case MESA_SHADER_GEOMETRY:
636 if (has_previous_stage) {
637 if (previous_stage == MESA_SHADER_VERTEX) {
638 user_sgpr_count += count_vs_user_sgprs(ctx);
639 }
640 }
641 break;
642 default:
643 break;
644 }
645
646 if (needs_view_index)
647 user_sgpr_count++;
648
649 if (ctx->shader_info->loads_push_constants)
650 user_sgpr_count++;
651
652 if (ctx->shader_info->so.num_outputs)
653 user_sgpr_count++;
654
655 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 && stage != MESA_SHADER_COMPUTE ? 32 : 16;
656 uint32_t remaining_sgprs = available_sgprs - user_sgpr_count;
657 uint32_t num_desc_set =
658 util_bitcount(ctx->shader_info->desc_set_used_mask);
659
660 if (remaining_sgprs < num_desc_set) {
661 user_sgpr_info->indirect_all_descriptor_sets = true;
662 user_sgpr_info->remaining_sgprs = remaining_sgprs - 1;
663 } else {
664 user_sgpr_info->remaining_sgprs = remaining_sgprs - num_desc_set;
665 }
666
667 allocate_inline_push_consts(ctx, user_sgpr_info);
668 }
669
670 static void
671 declare_global_input_sgprs(struct radv_shader_context *ctx,
672 const struct user_sgpr_info *user_sgpr_info,
673 struct arg_info *args,
674 LLVMValueRef *desc_sets)
675 {
676 LLVMTypeRef type = ac_array_in_const32_addr_space(ctx->ac.i8);
677
678 /* 1 for each descriptor set */
679 if (!user_sgpr_info->indirect_all_descriptor_sets) {
680 uint32_t mask = ctx->shader_info->desc_set_used_mask;
681
682 while (mask) {
683 int i = u_bit_scan(&mask);
684
685 add_arg(args, ARG_SGPR, type, &ctx->descriptor_sets[i]);
686 }
687 } else {
688 add_arg(args, ARG_SGPR, ac_array_in_const32_addr_space(type),
689 desc_sets);
690 }
691
692 if (ctx->shader_info->loads_push_constants) {
693 /* 1 for push constants and dynamic descriptors */
694 add_arg(args, ARG_SGPR, type, &ctx->abi.push_constants);
695 }
696
697 for (unsigned i = 0; i < ctx->shader_info->num_inline_push_consts; i++) {
698 add_arg(args, ARG_SGPR, ctx->ac.i32,
699 &ctx->abi.inline_push_consts[i]);
700 }
701 ctx->abi.num_inline_push_consts = ctx->shader_info->num_inline_push_consts;
702 ctx->abi.base_inline_push_consts = ctx->shader_info->base_inline_push_consts;
703
704 if (ctx->shader_info->so.num_outputs) {
705 add_arg(args, ARG_SGPR,
706 ac_array_in_const32_addr_space(ctx->ac.v4i32),
707 &ctx->streamout_buffers);
708 }
709 }
710
711 static void
712 declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
713 gl_shader_stage stage,
714 bool has_previous_stage,
715 gl_shader_stage previous_stage,
716 struct arg_info *args)
717 {
718 if (!ctx->is_gs_copy_shader &&
719 (stage == MESA_SHADER_VERTEX ||
720 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
721 if (ctx->shader_info->vs.has_vertex_buffers) {
722 add_arg(args, ARG_SGPR,
723 ac_array_in_const32_addr_space(ctx->ac.v4i32),
724 &ctx->vertex_buffers);
725 }
726 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
727 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
728 if (ctx->shader_info->vs.needs_draw_id) {
729 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
730 }
731 }
732 }
733
734 static void
735 declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
736 {
737 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
738 if (!ctx->is_gs_copy_shader) {
739 if (ctx->options->key.vs_common_out.as_ls) {
740 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
741 if (ctx->ac.chip_class >= GFX10) {
742 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* user vgpr */
743 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
744 } else {
745 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
746 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
747 }
748 } else {
749 if (ctx->ac.chip_class >= GFX10) {
750 if (ctx->options->key.vs_common_out.as_ngg) {
751 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* user vgpr */
752 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* user vgpr */
753 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
754 } else {
755 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
756 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
757 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
758 }
759 } else {
760 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
761 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
762 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
763 }
764 }
765 }
766 }
767
768 static void
769 declare_streamout_sgprs(struct radv_shader_context *ctx, gl_shader_stage stage,
770 struct arg_info *args)
771 {
772 int i;
773
774 if (ctx->options->use_ngg_streamout)
775 return;
776
777 /* Streamout SGPRs. */
778 if (ctx->shader_info->so.num_outputs) {
779 assert(stage == MESA_SHADER_VERTEX ||
780 stage == MESA_SHADER_TESS_EVAL);
781
782 if (stage != MESA_SHADER_TESS_EVAL) {
783 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->streamout_config);
784 } else {
785 args->assign[args->count - 1] = &ctx->streamout_config;
786 args->types[args->count - 1] = ctx->ac.i32;
787 }
788
789 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->streamout_write_idx);
790 }
791
792 /* A streamout buffer offset is loaded if the stride is non-zero. */
793 for (i = 0; i < 4; i++) {
794 if (!ctx->shader_info->so.strides[i])
795 continue;
796
797 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->streamout_offset[i]);
798 }
799 }
800
801 static void
802 declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
803 {
804 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
805 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
806 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
807 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
808 }
809
810 static void
811 set_global_input_locs(struct radv_shader_context *ctx,
812 const struct user_sgpr_info *user_sgpr_info,
813 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
814 {
815 uint32_t mask = ctx->shader_info->desc_set_used_mask;
816
817 if (!user_sgpr_info->indirect_all_descriptor_sets) {
818 while (mask) {
819 int i = u_bit_scan(&mask);
820
821 set_loc_desc(ctx, i, user_sgpr_idx);
822 }
823 } else {
824 set_loc_shader_ptr(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
825 user_sgpr_idx);
826
827 while (mask) {
828 int i = u_bit_scan(&mask);
829
830 ctx->descriptor_sets[i] =
831 ac_build_load_to_sgpr(&ctx->ac, desc_sets,
832 LLVMConstInt(ctx->ac.i32, i, false));
833
834 }
835
836 ctx->shader_info->need_indirect_descriptor_sets = true;
837 }
838
839 if (ctx->shader_info->loads_push_constants) {
840 set_loc_shader_ptr(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx);
841 }
842
843 if (ctx->shader_info->num_inline_push_consts) {
844 set_loc_shader(ctx, AC_UD_INLINE_PUSH_CONSTANTS, user_sgpr_idx,
845 ctx->shader_info->num_inline_push_consts);
846 }
847
848 if (ctx->streamout_buffers) {
849 set_loc_shader_ptr(ctx, AC_UD_STREAMOUT_BUFFERS,
850 user_sgpr_idx);
851 }
852 }
853
854 static void
855 set_vs_specific_input_locs(struct radv_shader_context *ctx,
856 gl_shader_stage stage, bool has_previous_stage,
857 gl_shader_stage previous_stage,
858 uint8_t *user_sgpr_idx)
859 {
860 if (!ctx->is_gs_copy_shader &&
861 (stage == MESA_SHADER_VERTEX ||
862 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
863 if (ctx->shader_info->vs.has_vertex_buffers) {
864 set_loc_shader_ptr(ctx, AC_UD_VS_VERTEX_BUFFERS,
865 user_sgpr_idx);
866 }
867
868 unsigned vs_num = 2;
869 if (ctx->shader_info->vs.needs_draw_id)
870 vs_num++;
871
872 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
873 user_sgpr_idx, vs_num);
874 }
875 }
876
877 static void set_llvm_calling_convention(LLVMValueRef func,
878 gl_shader_stage stage)
879 {
880 enum radeon_llvm_calling_convention calling_conv;
881
882 switch (stage) {
883 case MESA_SHADER_VERTEX:
884 case MESA_SHADER_TESS_EVAL:
885 calling_conv = RADEON_LLVM_AMDGPU_VS;
886 break;
887 case MESA_SHADER_GEOMETRY:
888 calling_conv = RADEON_LLVM_AMDGPU_GS;
889 break;
890 case MESA_SHADER_TESS_CTRL:
891 calling_conv = RADEON_LLVM_AMDGPU_HS;
892 break;
893 case MESA_SHADER_FRAGMENT:
894 calling_conv = RADEON_LLVM_AMDGPU_PS;
895 break;
896 case MESA_SHADER_COMPUTE:
897 calling_conv = RADEON_LLVM_AMDGPU_CS;
898 break;
899 default:
900 unreachable("Unhandle shader type");
901 }
902
903 LLVMSetFunctionCallConv(func, calling_conv);
904 }
905
906 /* Returns whether the stage is a stage that can be directly before the GS */
907 static bool is_pre_gs_stage(gl_shader_stage stage)
908 {
909 return stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL;
910 }
911
912 static void create_function(struct radv_shader_context *ctx,
913 gl_shader_stage stage,
914 bool has_previous_stage,
915 gl_shader_stage previous_stage)
916 {
917 uint8_t user_sgpr_idx;
918 struct user_sgpr_info user_sgpr_info;
919 struct arg_info args = {};
920 LLVMValueRef desc_sets;
921 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
922
923 if (ctx->ac.chip_class >= GFX10) {
924 if (is_pre_gs_stage(stage) && ctx->options->key.vs_common_out.as_ngg) {
925 /* On GFX10, VS is merged into GS for NGG. */
926 previous_stage = stage;
927 stage = MESA_SHADER_GEOMETRY;
928 has_previous_stage = true;
929 }
930 }
931
932 allocate_user_sgprs(ctx, stage, has_previous_stage,
933 previous_stage, needs_view_index, &user_sgpr_info);
934
935 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
936 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
937 &ctx->ring_offsets);
938 }
939
940 switch (stage) {
941 case MESA_SHADER_COMPUTE:
942 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
943 &desc_sets);
944
945 if (ctx->shader_info->cs.uses_grid_size) {
946 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
947 &ctx->abi.num_work_groups);
948 }
949
950 for (int i = 0; i < 3; i++) {
951 ctx->abi.workgroup_ids[i] = NULL;
952 if (ctx->shader_info->cs.uses_block_id[i]) {
953 add_arg(&args, ARG_SGPR, ctx->ac.i32,
954 &ctx->abi.workgroup_ids[i]);
955 }
956 }
957
958 if (ctx->shader_info->cs.uses_local_invocation_idx)
959 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
960 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
961 &ctx->abi.local_invocation_ids);
962 break;
963 case MESA_SHADER_VERTEX:
964 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
965 &desc_sets);
966
967 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
968 previous_stage, &args);
969
970 if (needs_view_index)
971 add_arg(&args, ARG_SGPR, ctx->ac.i32,
972 &ctx->abi.view_index);
973 if (ctx->options->key.vs_common_out.as_es) {
974 add_arg(&args, ARG_SGPR, ctx->ac.i32,
975 &ctx->es2gs_offset);
976 } else if (ctx->options->key.vs_common_out.as_ls) {
977 /* no extra parameters */
978 } else {
979 declare_streamout_sgprs(ctx, stage, &args);
980 }
981
982 declare_vs_input_vgprs(ctx, &args);
983 break;
984 case MESA_SHADER_TESS_CTRL:
985 if (has_previous_stage) {
986 // First 6 system regs
987 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
988 add_arg(&args, ARG_SGPR, ctx->ac.i32,
989 &ctx->merged_wave_info);
990 add_arg(&args, ARG_SGPR, ctx->ac.i32,
991 &ctx->tess_factor_offset);
992
993 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
994 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
995 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
996
997 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
998 &desc_sets);
999
1000 declare_vs_specific_input_sgprs(ctx, stage,
1001 has_previous_stage,
1002 previous_stage, &args);
1003
1004 if (needs_view_index)
1005 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1006 &ctx->abi.view_index);
1007
1008 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1009 &ctx->abi.tcs_patch_id);
1010 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1011 &ctx->abi.tcs_rel_ids);
1012
1013 declare_vs_input_vgprs(ctx, &args);
1014 } else {
1015 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
1016 &desc_sets);
1017
1018 if (needs_view_index)
1019 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1020 &ctx->abi.view_index);
1021
1022 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1023 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1024 &ctx->tess_factor_offset);
1025 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1026 &ctx->abi.tcs_patch_id);
1027 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1028 &ctx->abi.tcs_rel_ids);
1029 }
1030 break;
1031 case MESA_SHADER_TESS_EVAL:
1032 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
1033 &desc_sets);
1034
1035 if (needs_view_index)
1036 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1037 &ctx->abi.view_index);
1038
1039 if (ctx->options->key.vs_common_out.as_es) {
1040 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1041 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
1042 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1043 &ctx->es2gs_offset);
1044 } else {
1045 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
1046 declare_streamout_sgprs(ctx, stage, &args);
1047 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1048 }
1049 declare_tes_input_vgprs(ctx, &args);
1050 break;
1051 case MESA_SHADER_GEOMETRY:
1052 if (has_previous_stage) {
1053 // First 6 system regs
1054 if (ctx->options->key.vs_common_out.as_ngg) {
1055 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1056 &ctx->gs_tg_info);
1057 } else {
1058 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1059 &ctx->gs2vs_offset);
1060 }
1061
1062 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1063 &ctx->merged_wave_info);
1064 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1065
1066 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
1067 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
1068 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
1069
1070 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
1071 &desc_sets);
1072
1073 if (previous_stage != MESA_SHADER_TESS_EVAL) {
1074 declare_vs_specific_input_sgprs(ctx, stage,
1075 has_previous_stage,
1076 previous_stage,
1077 &args);
1078 }
1079
1080 if (needs_view_index)
1081 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1082 &ctx->abi.view_index);
1083
1084 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1085 &ctx->gs_vtx_offset[0]);
1086 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1087 &ctx->gs_vtx_offset[2]);
1088 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1089 &ctx->abi.gs_prim_id);
1090 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1091 &ctx->abi.gs_invocation_id);
1092 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1093 &ctx->gs_vtx_offset[4]);
1094
1095 if (previous_stage == MESA_SHADER_VERTEX) {
1096 declare_vs_input_vgprs(ctx, &args);
1097 } else {
1098 declare_tes_input_vgprs(ctx, &args);
1099 }
1100 } else {
1101 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
1102 &desc_sets);
1103
1104 if (needs_view_index)
1105 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1106 &ctx->abi.view_index);
1107
1108 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
1109 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
1110 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1111 &ctx->gs_vtx_offset[0]);
1112 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1113 &ctx->gs_vtx_offset[1]);
1114 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1115 &ctx->abi.gs_prim_id);
1116 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1117 &ctx->gs_vtx_offset[2]);
1118 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1119 &ctx->gs_vtx_offset[3]);
1120 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1121 &ctx->gs_vtx_offset[4]);
1122 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1123 &ctx->gs_vtx_offset[5]);
1124 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1125 &ctx->abi.gs_invocation_id);
1126 }
1127 break;
1128 case MESA_SHADER_FRAGMENT:
1129 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
1130 &desc_sets);
1131
1132 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
1133 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->abi.persp_sample);
1134 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->abi.persp_center);
1135 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->abi.persp_centroid);
1136 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1137 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->abi.linear_sample);
1138 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->abi.linear_center);
1139 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->abi.linear_centroid);
1140 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1141 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1142 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1143 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1144 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1145 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1146 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1147 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1148 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1149 break;
1150 default:
1151 unreachable("Shader stage not implemented");
1152 }
1153
1154 ctx->main_function = create_llvm_function(
1155 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
1156 ctx->max_workgroup_size, ctx->options);
1157 set_llvm_calling_convention(ctx->main_function, stage);
1158
1159
1160 ctx->shader_info->num_input_vgprs = 0;
1161 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1162
1163 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1164
1165 if (ctx->stage != MESA_SHADER_FRAGMENT)
1166 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1167
1168 assign_arguments(ctx->main_function, &args);
1169
1170 user_sgpr_idx = 0;
1171
1172 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1173 set_loc_shader_ptr(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1174 &user_sgpr_idx);
1175 if (ctx->options->supports_spill) {
1176 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1177 LLVMPointerType(ctx->ac.i8, AC_ADDR_SPACE_CONST),
1178 NULL, 0, AC_FUNC_ATTR_READNONE);
1179 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1180 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1181 }
1182 }
1183
1184 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1185 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1186 if (has_previous_stage)
1187 user_sgpr_idx = 0;
1188
1189 set_global_input_locs(ctx, &user_sgpr_info, desc_sets, &user_sgpr_idx);
1190
1191 switch (stage) {
1192 case MESA_SHADER_COMPUTE:
1193 if (ctx->shader_info->cs.uses_grid_size) {
1194 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1195 &user_sgpr_idx, 3);
1196 }
1197 break;
1198 case MESA_SHADER_VERTEX:
1199 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1200 previous_stage, &user_sgpr_idx);
1201 if (ctx->abi.view_index)
1202 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1203 break;
1204 case MESA_SHADER_TESS_CTRL:
1205 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1206 previous_stage, &user_sgpr_idx);
1207 if (ctx->abi.view_index)
1208 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1209 break;
1210 case MESA_SHADER_TESS_EVAL:
1211 if (ctx->abi.view_index)
1212 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1213 break;
1214 case MESA_SHADER_GEOMETRY:
1215 if (has_previous_stage) {
1216 if (previous_stage == MESA_SHADER_VERTEX)
1217 set_vs_specific_input_locs(ctx, stage,
1218 has_previous_stage,
1219 previous_stage,
1220 &user_sgpr_idx);
1221 }
1222 if (ctx->abi.view_index)
1223 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1224 break;
1225 case MESA_SHADER_FRAGMENT:
1226 break;
1227 default:
1228 unreachable("Shader stage not implemented");
1229 }
1230
1231 if (stage == MESA_SHADER_TESS_CTRL ||
1232 (stage == MESA_SHADER_VERTEX && ctx->options->key.vs_common_out.as_ls) ||
1233 /* GFX9 has the ESGS ring buffer in LDS. */
1234 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
1235 ac_declare_lds_as_pointer(&ctx->ac);
1236 }
1237
1238 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1239 }
1240
1241
1242 static LLVMValueRef
1243 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
1244 unsigned desc_set, unsigned binding)
1245 {
1246 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1247 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1248 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
1249 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
1250 unsigned base_offset = layout->binding[binding].offset;
1251 LLVMValueRef offset, stride;
1252
1253 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1254 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1255 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
1256 layout->binding[binding].dynamic_offset_offset;
1257 desc_ptr = ctx->abi.push_constants;
1258 base_offset = pipeline_layout->push_constant_size + 16 * idx;
1259 stride = LLVMConstInt(ctx->ac.i32, 16, false);
1260 } else
1261 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
1262
1263 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
1264
1265 if (layout->binding[binding].type != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
1266 offset = ac_build_imad(&ctx->ac, index, stride, offset);
1267 }
1268
1269 desc_ptr = LLVMBuildGEP(ctx->ac.builder, desc_ptr, &offset, 1, "");
1270 desc_ptr = ac_cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
1271 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1272
1273 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
1274 uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1275 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1276 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1277 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
1278
1279 if (ctx->ac.chip_class >= GFX10) {
1280 desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
1281 S_008F0C_OOB_SELECT(3) |
1282 S_008F0C_RESOURCE_LEVEL(1);
1283 } else {
1284 desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1285 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1286 }
1287
1288 LLVMValueRef desc_components[4] = {
1289 LLVMBuildPtrToInt(ctx->ac.builder, desc_ptr, ctx->ac.intptr, ""),
1290 LLVMConstInt(ctx->ac.i32, S_008F04_BASE_ADDRESS_HI(ctx->options->address32_hi), false),
1291 /* High limit to support variable sizes. */
1292 LLVMConstInt(ctx->ac.i32, 0xffffffff, false),
1293 LLVMConstInt(ctx->ac.i32, desc_type, false),
1294 };
1295
1296 return ac_build_gather_values(&ctx->ac, desc_components, 4);
1297 }
1298
1299 return desc_ptr;
1300 }
1301
1302
1303 /* The offchip buffer layout for TCS->TES is
1304 *
1305 * - attribute 0 of patch 0 vertex 0
1306 * - attribute 0 of patch 0 vertex 1
1307 * - attribute 0 of patch 0 vertex 2
1308 * ...
1309 * - attribute 0 of patch 1 vertex 0
1310 * - attribute 0 of patch 1 vertex 1
1311 * ...
1312 * - attribute 1 of patch 0 vertex 0
1313 * - attribute 1 of patch 0 vertex 1
1314 * ...
1315 * - per patch attribute 0 of patch 0
1316 * - per patch attribute 0 of patch 1
1317 * ...
1318 *
1319 * Note that every attribute has 4 components.
1320 */
1321 static LLVMValueRef get_non_vertex_index_offset(struct radv_shader_context *ctx)
1322 {
1323 uint32_t num_patches = ctx->tcs_num_patches;
1324 uint32_t num_tcs_outputs;
1325 if (ctx->stage == MESA_SHADER_TESS_CTRL)
1326 num_tcs_outputs = util_last_bit64(ctx->shader_info->tcs.outputs_written);
1327 else
1328 num_tcs_outputs = ctx->options->key.tes.tcs_num_outputs;
1329
1330 uint32_t output_vertex_size = num_tcs_outputs * 16;
1331 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
1332
1333 return LLVMConstInt(ctx->ac.i32, pervertex_output_patch_size * num_patches, false);
1334 }
1335
1336 static LLVMValueRef calc_param_stride(struct radv_shader_context *ctx,
1337 LLVMValueRef vertex_index)
1338 {
1339 LLVMValueRef param_stride;
1340 if (vertex_index)
1341 param_stride = LLVMConstInt(ctx->ac.i32, ctx->shader->info.tess.tcs_vertices_out * ctx->tcs_num_patches, false);
1342 else
1343 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_num_patches, false);
1344 return param_stride;
1345 }
1346
1347 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
1348 LLVMValueRef vertex_index,
1349 LLVMValueRef param_index)
1350 {
1351 LLVMValueRef base_addr;
1352 LLVMValueRef param_stride, constant16;
1353 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
1354 LLVMValueRef vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->shader->info.tess.tcs_vertices_out, false);
1355 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
1356 param_stride = calc_param_stride(ctx, vertex_index);
1357 if (vertex_index) {
1358 base_addr = ac_build_imad(&ctx->ac, rel_patch_id,
1359 vertices_per_patch, vertex_index);
1360 } else {
1361 base_addr = rel_patch_id;
1362 }
1363
1364 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1365 LLVMBuildMul(ctx->ac.builder, param_index,
1366 param_stride, ""), "");
1367
1368 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
1369
1370 if (!vertex_index) {
1371 LLVMValueRef patch_data_offset = get_non_vertex_index_offset(ctx);
1372
1373 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1374 patch_data_offset, "");
1375 }
1376 return base_addr;
1377 }
1378
1379 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
1380 unsigned param,
1381 unsigned const_index,
1382 bool is_compact,
1383 LLVMValueRef vertex_index,
1384 LLVMValueRef indir_index)
1385 {
1386 LLVMValueRef param_index;
1387
1388 if (indir_index)
1389 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
1390 indir_index, "");
1391 else {
1392 if (const_index && !is_compact)
1393 param += const_index;
1394 param_index = LLVMConstInt(ctx->ac.i32, param, false);
1395 }
1396 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
1397 }
1398
1399 static LLVMValueRef
1400 get_dw_address(struct radv_shader_context *ctx,
1401 LLVMValueRef dw_addr,
1402 unsigned param,
1403 unsigned const_index,
1404 bool compact_const_index,
1405 LLVMValueRef vertex_index,
1406 LLVMValueRef stride,
1407 LLVMValueRef indir_index)
1408
1409 {
1410
1411 if (vertex_index) {
1412 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1413 LLVMBuildMul(ctx->ac.builder,
1414 vertex_index,
1415 stride, ""), "");
1416 }
1417
1418 if (indir_index)
1419 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1420 LLVMBuildMul(ctx->ac.builder, indir_index,
1421 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
1422 else if (const_index && !compact_const_index)
1423 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1424 LLVMConstInt(ctx->ac.i32, const_index * 4, false), "");
1425
1426 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1427 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
1428
1429 if (const_index && compact_const_index)
1430 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1431 LLVMConstInt(ctx->ac.i32, const_index, false), "");
1432 return dw_addr;
1433 }
1434
1435 static LLVMValueRef
1436 load_tcs_varyings(struct ac_shader_abi *abi,
1437 LLVMTypeRef type,
1438 LLVMValueRef vertex_index,
1439 LLVMValueRef indir_index,
1440 unsigned const_index,
1441 unsigned location,
1442 unsigned driver_location,
1443 unsigned component,
1444 unsigned num_components,
1445 bool is_patch,
1446 bool is_compact,
1447 bool load_input)
1448 {
1449 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1450 LLVMValueRef dw_addr, stride;
1451 LLVMValueRef value[4], result;
1452 unsigned param = shader_io_get_unique_index(location);
1453
1454 if (load_input) {
1455 uint32_t input_vertex_size = (ctx->tcs_num_inputs * 16) / 4;
1456 stride = LLVMConstInt(ctx->ac.i32, input_vertex_size, false);
1457 dw_addr = get_tcs_in_current_patch_offset(ctx);
1458 } else {
1459 if (!is_patch) {
1460 stride = get_tcs_out_vertex_stride(ctx);
1461 dw_addr = get_tcs_out_current_patch_offset(ctx);
1462 } else {
1463 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1464 stride = NULL;
1465 }
1466 }
1467
1468 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1469 indir_index);
1470
1471 for (unsigned i = 0; i < num_components + component; i++) {
1472 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1473 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1474 ctx->ac.i32_1, "");
1475 }
1476 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1477 return result;
1478 }
1479
1480 static void
1481 store_tcs_output(struct ac_shader_abi *abi,
1482 const nir_variable *var,
1483 LLVMValueRef vertex_index,
1484 LLVMValueRef param_index,
1485 unsigned const_index,
1486 LLVMValueRef src,
1487 unsigned writemask)
1488 {
1489 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1490 const unsigned location = var->data.location;
1491 unsigned component = var->data.location_frac;
1492 const bool is_patch = var->data.patch;
1493 const bool is_compact = var->data.compact;
1494 LLVMValueRef dw_addr;
1495 LLVMValueRef stride = NULL;
1496 LLVMValueRef buf_addr = NULL;
1497 unsigned param;
1498 bool store_lds = true;
1499
1500 if (is_patch) {
1501 if (!(ctx->shader->info.patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
1502 store_lds = false;
1503 } else {
1504 if (!(ctx->shader->info.outputs_read & (1ULL << location)))
1505 store_lds = false;
1506 }
1507
1508 param = shader_io_get_unique_index(location);
1509 if ((location == VARYING_SLOT_CLIP_DIST0 || location == VARYING_SLOT_CLIP_DIST1) && is_compact) {
1510 const_index += component;
1511 component = 0;
1512
1513 if (const_index >= 4) {
1514 const_index -= 4;
1515 param++;
1516 }
1517 }
1518
1519 if (!is_patch) {
1520 stride = get_tcs_out_vertex_stride(ctx);
1521 dw_addr = get_tcs_out_current_patch_offset(ctx);
1522 } else {
1523 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1524 }
1525
1526 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1527 param_index);
1528 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
1529 vertex_index, param_index);
1530
1531 bool is_tess_factor = false;
1532 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
1533 location == VARYING_SLOT_TESS_LEVEL_OUTER)
1534 is_tess_factor = true;
1535
1536 unsigned base = is_compact ? const_index : 0;
1537 for (unsigned chan = 0; chan < 8; chan++) {
1538 if (!(writemask & (1 << chan)))
1539 continue;
1540 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1541 value = ac_to_integer(&ctx->ac, value);
1542 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
1543
1544 if (store_lds || is_tess_factor) {
1545 LLVMValueRef dw_addr_chan =
1546 LLVMBuildAdd(ctx->ac.builder, dw_addr,
1547 LLVMConstInt(ctx->ac.i32, chan, false), "");
1548 ac_lds_store(&ctx->ac, dw_addr_chan, value);
1549 }
1550
1551 if (!is_tess_factor && writemask != 0xF)
1552 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
1553 buf_addr, ctx->oc_lds,
1554 4 * (base + chan), ac_glc, false);
1555 }
1556
1557 if (writemask == 0xF) {
1558 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
1559 buf_addr, ctx->oc_lds,
1560 (base * 4), ac_glc, false);
1561 }
1562 }
1563
1564 static LLVMValueRef
1565 load_tes_input(struct ac_shader_abi *abi,
1566 LLVMTypeRef type,
1567 LLVMValueRef vertex_index,
1568 LLVMValueRef param_index,
1569 unsigned const_index,
1570 unsigned location,
1571 unsigned driver_location,
1572 unsigned component,
1573 unsigned num_components,
1574 bool is_patch,
1575 bool is_compact,
1576 bool load_input)
1577 {
1578 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1579 LLVMValueRef buf_addr;
1580 LLVMValueRef result;
1581 unsigned param = shader_io_get_unique_index(location);
1582
1583 if ((location == VARYING_SLOT_CLIP_DIST0 || location == VARYING_SLOT_CLIP_DIST1) && is_compact) {
1584 const_index += component;
1585 component = 0;
1586 if (const_index >= 4) {
1587 const_index -= 4;
1588 param++;
1589 }
1590 }
1591
1592 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
1593 is_compact, vertex_index, param_index);
1594
1595 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
1596 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
1597
1598 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
1599 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, ac_glc, true, false);
1600 result = ac_trim_vector(&ctx->ac, result, num_components);
1601 return result;
1602 }
1603
1604 static LLVMValueRef
1605 radv_emit_fetch_64bit(struct radv_shader_context *ctx,
1606 LLVMTypeRef type, LLVMValueRef a, LLVMValueRef b)
1607 {
1608 LLVMValueRef values[2] = {
1609 ac_to_integer(&ctx->ac, a),
1610 ac_to_integer(&ctx->ac, b),
1611 };
1612 LLVMValueRef result = ac_build_gather_values(&ctx->ac, values, 2);
1613 return LLVMBuildBitCast(ctx->ac.builder, result, type, "");
1614 }
1615
1616 static LLVMValueRef
1617 load_gs_input(struct ac_shader_abi *abi,
1618 unsigned location,
1619 unsigned driver_location,
1620 unsigned component,
1621 unsigned num_components,
1622 unsigned vertex_index,
1623 unsigned const_index,
1624 LLVMTypeRef type)
1625 {
1626 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1627 LLVMValueRef vtx_offset;
1628 unsigned param, vtx_offset_param;
1629 LLVMValueRef value[4], result;
1630
1631 vtx_offset_param = vertex_index;
1632 assert(vtx_offset_param < 6);
1633 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
1634 LLVMConstInt(ctx->ac.i32, 4, false), "");
1635
1636 param = shader_io_get_unique_index(location);
1637
1638 for (unsigned i = component; i < num_components + component; i++) {
1639 if (ctx->ac.chip_class >= GFX9) {
1640 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
1641 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1642 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
1643 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1644
1645 if (ac_get_type_size(type) == 8) {
1646 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1647 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index + 1, 0), "");
1648 LLVMValueRef tmp = ac_lds_load(&ctx->ac, dw_addr);
1649
1650 value[i] = radv_emit_fetch_64bit(ctx, type, value[i], tmp);
1651 }
1652 } else {
1653 LLVMValueRef soffset =
1654 LLVMConstInt(ctx->ac.i32,
1655 (param * 4 + i + const_index) * 256,
1656 false);
1657
1658 value[i] = ac_build_buffer_load(&ctx->ac,
1659 ctx->esgs_ring, 1,
1660 ctx->ac.i32_0,
1661 vtx_offset, soffset,
1662 0, ac_glc, true, false);
1663
1664 if (ac_get_type_size(type) == 8) {
1665 soffset = LLVMConstInt(ctx->ac.i32,
1666 (param * 4 + i + const_index + 1) * 256,
1667 false);
1668
1669 LLVMValueRef tmp =
1670 ac_build_buffer_load(&ctx->ac,
1671 ctx->esgs_ring, 1,
1672 ctx->ac.i32_0,
1673 vtx_offset, soffset,
1674 0, ac_glc, true, false);
1675
1676 value[i] = radv_emit_fetch_64bit(ctx, type, value[i], tmp);
1677 }
1678 }
1679
1680 if (ac_get_type_size(type) == 2) {
1681 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], ctx->ac.i32, "");
1682 value[i] = LLVMBuildTrunc(ctx->ac.builder, value[i], ctx->ac.i16, "");
1683 }
1684 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], type, "");
1685 }
1686 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1687 result = ac_to_integer(&ctx->ac, result);
1688 return result;
1689 }
1690
1691
1692 static void radv_emit_kill(struct ac_shader_abi *abi, LLVMValueRef visible)
1693 {
1694 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1695 ac_build_kill_if_false(&ctx->ac, visible);
1696 }
1697
1698 static uint32_t
1699 radv_get_sample_pos_offset(uint32_t num_samples)
1700 {
1701 uint32_t sample_pos_offset = 0;
1702
1703 switch (num_samples) {
1704 case 2:
1705 sample_pos_offset = 1;
1706 break;
1707 case 4:
1708 sample_pos_offset = 3;
1709 break;
1710 case 8:
1711 sample_pos_offset = 7;
1712 break;
1713 default:
1714 break;
1715 }
1716 return sample_pos_offset;
1717 }
1718
1719 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
1720 LLVMValueRef sample_id)
1721 {
1722 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1723
1724 LLVMValueRef result;
1725 LLVMValueRef index = LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false);
1726 LLVMValueRef ptr = LLVMBuildGEP(ctx->ac.builder, ctx->ring_offsets, &index, 1, "");
1727
1728 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
1729 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
1730
1731 uint32_t sample_pos_offset =
1732 radv_get_sample_pos_offset(ctx->options->key.fs.num_samples);
1733
1734 sample_id =
1735 LLVMBuildAdd(ctx->ac.builder, sample_id,
1736 LLVMConstInt(ctx->ac.i32, sample_pos_offset, false), "");
1737 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
1738
1739 return result;
1740 }
1741
1742
1743 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1744 {
1745 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1746 uint8_t log2_ps_iter_samples;
1747
1748 if (ctx->shader_info->ps.force_persample) {
1749 log2_ps_iter_samples =
1750 util_logbase2(ctx->options->key.fs.num_samples);
1751 } else {
1752 log2_ps_iter_samples = ctx->options->key.fs.log2_ps_iter_samples;
1753 }
1754
1755 /* The bit pattern matches that used by fixed function fragment
1756 * processing. */
1757 static const uint16_t ps_iter_masks[] = {
1758 0xffff, /* not used */
1759 0x5555,
1760 0x1111,
1761 0x0101,
1762 0x0001,
1763 };
1764 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
1765
1766 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
1767
1768 LLVMValueRef result, sample_id;
1769 sample_id = ac_unpack_param(&ctx->ac, abi->ancillary, 8, 4);
1770 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
1771 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
1772 return result;
1773 }
1774
1775
1776 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context *ctx,
1777 unsigned stream,
1778 LLVMValueRef *addrs);
1779
1780 static void
1781 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
1782 {
1783 LLVMValueRef gs_next_vertex;
1784 LLVMValueRef can_emit;
1785 unsigned offset = 0;
1786 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1787
1788 if (ctx->options->key.vs_common_out.as_ngg) {
1789 gfx10_ngg_gs_emit_vertex(ctx, stream, addrs);
1790 return;
1791 }
1792
1793 /* Write vertex attribute values to GSVS ring */
1794 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
1795 ctx->gs_next_vertex[stream],
1796 "");
1797
1798 /* If this thread has already emitted the declared maximum number of
1799 * vertices, don't emit any more: excessive vertex emissions are not
1800 * supposed to have any effect.
1801 */
1802 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
1803 LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false), "");
1804
1805 bool use_kill = !ctx->shader_info->gs.writes_memory;
1806 if (use_kill)
1807 ac_build_kill_if_false(&ctx->ac, can_emit);
1808 else
1809 ac_build_ifcc(&ctx->ac, can_emit, 6505);
1810
1811 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
1812 unsigned output_usage_mask =
1813 ctx->shader_info->gs.output_usage_mask[i];
1814 uint8_t output_stream =
1815 ctx->shader_info->gs.output_streams[i];
1816 LLVMValueRef *out_ptr = &addrs[i * 4];
1817 int length = util_last_bit(output_usage_mask);
1818
1819 if (!(ctx->output_mask & (1ull << i)) ||
1820 output_stream != stream)
1821 continue;
1822
1823 for (unsigned j = 0; j < length; j++) {
1824 if (!(output_usage_mask & (1 << j)))
1825 continue;
1826
1827 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
1828 out_ptr[j], "");
1829 LLVMValueRef voffset =
1830 LLVMConstInt(ctx->ac.i32, offset *
1831 ctx->shader->info.gs.vertices_out, false);
1832
1833 offset++;
1834
1835 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
1836 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
1837
1838 out_val = ac_to_integer(&ctx->ac, out_val);
1839 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
1840
1841 ac_build_buffer_store_dword(&ctx->ac,
1842 ctx->gsvs_ring[stream],
1843 out_val, 1,
1844 voffset, ctx->gs2vs_offset, 0,
1845 ac_glc | ac_slc, true);
1846 }
1847 }
1848
1849 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
1850 ctx->ac.i32_1, "");
1851 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
1852
1853 ac_build_sendmsg(&ctx->ac,
1854 AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
1855 ctx->gs_wave_id);
1856
1857 if (!use_kill)
1858 ac_build_endif(&ctx->ac, 6505);
1859 }
1860
1861 static void
1862 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
1863 {
1864 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1865
1866 if (ctx->options->key.vs_common_out.as_ngg) {
1867 LLVMBuildStore(ctx->ac.builder, ctx->ac.i32_0, ctx->gs_curprim_verts[stream]);
1868 return;
1869 }
1870
1871 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
1872 }
1873
1874 static LLVMValueRef
1875 load_tess_coord(struct ac_shader_abi *abi)
1876 {
1877 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1878
1879 LLVMValueRef coord[4] = {
1880 ctx->tes_u,
1881 ctx->tes_v,
1882 ctx->ac.f32_0,
1883 ctx->ac.f32_0,
1884 };
1885
1886 if (ctx->shader->info.tess.primitive_mode == GL_TRIANGLES)
1887 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1888 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
1889
1890 return ac_build_gather_values(&ctx->ac, coord, 3);
1891 }
1892
1893 static LLVMValueRef
1894 load_patch_vertices_in(struct ac_shader_abi *abi)
1895 {
1896 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1897 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
1898 }
1899
1900
1901 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
1902 {
1903 return abi->base_vertex;
1904 }
1905
1906 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
1907 LLVMValueRef buffer_ptr, bool write)
1908 {
1909 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1910 LLVMValueRef result;
1911
1912 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1913
1914 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1915 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1916
1917 return result;
1918 }
1919
1920 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
1921 {
1922 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1923 LLVMValueRef result;
1924
1925 if (LLVMGetTypeKind(LLVMTypeOf(buffer_ptr)) != LLVMPointerTypeKind) {
1926 /* Do not load the descriptor for inlined uniform blocks. */
1927 return buffer_ptr;
1928 }
1929
1930 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1931
1932 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1933 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1934
1935 return result;
1936 }
1937
1938 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
1939 unsigned descriptor_set,
1940 unsigned base_index,
1941 unsigned constant_index,
1942 LLVMValueRef index,
1943 enum ac_descriptor_type desc_type,
1944 bool image, bool write,
1945 bool bindless)
1946 {
1947 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1948 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
1949 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
1950 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
1951 unsigned offset = binding->offset;
1952 unsigned stride = binding->size;
1953 unsigned type_size;
1954 LLVMBuilderRef builder = ctx->ac.builder;
1955 LLVMTypeRef type;
1956
1957 assert(base_index < layout->binding_count);
1958
1959 switch (desc_type) {
1960 case AC_DESC_IMAGE:
1961 type = ctx->ac.v8i32;
1962 type_size = 32;
1963 break;
1964 case AC_DESC_FMASK:
1965 type = ctx->ac.v8i32;
1966 offset += 32;
1967 type_size = 32;
1968 break;
1969 case AC_DESC_SAMPLER:
1970 type = ctx->ac.v4i32;
1971 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER) {
1972 offset += radv_combined_image_descriptor_sampler_offset(binding);
1973 }
1974
1975 type_size = 16;
1976 break;
1977 case AC_DESC_BUFFER:
1978 type = ctx->ac.v4i32;
1979 type_size = 16;
1980 break;
1981 case AC_DESC_PLANE_0:
1982 case AC_DESC_PLANE_1:
1983 case AC_DESC_PLANE_2:
1984 type = ctx->ac.v8i32;
1985 type_size = 32;
1986 offset += 32 * (desc_type - AC_DESC_PLANE_0);
1987 break;
1988 default:
1989 unreachable("invalid desc_type\n");
1990 }
1991
1992 offset += constant_index * stride;
1993
1994 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
1995 (!index || binding->immutable_samplers_equal)) {
1996 if (binding->immutable_samplers_equal)
1997 constant_index = 0;
1998
1999 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
2000
2001 LLVMValueRef constants[] = {
2002 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
2003 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
2004 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
2005 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
2006 };
2007 return ac_build_gather_values(&ctx->ac, constants, 4);
2008 }
2009
2010 assert(stride % type_size == 0);
2011
2012 LLVMValueRef adjusted_index = index;
2013 if (!adjusted_index)
2014 adjusted_index = ctx->ac.i32_0;
2015
2016 adjusted_index = LLVMBuildMul(builder, adjusted_index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
2017
2018 LLVMValueRef val_offset = LLVMConstInt(ctx->ac.i32, offset, 0);
2019 list = LLVMBuildGEP(builder, list, &val_offset, 1, "");
2020 list = LLVMBuildPointerCast(builder, list,
2021 ac_array_in_const32_addr_space(type), "");
2022
2023 LLVMValueRef descriptor = ac_build_load_to_sgpr(&ctx->ac, list, adjusted_index);
2024
2025 /* 3 plane formats always have same size and format for plane 1 & 2, so
2026 * use the tail from plane 1 so that we can store only the first 16 bytes
2027 * of the last plane. */
2028 if (desc_type == AC_DESC_PLANE_2) {
2029 LLVMValueRef descriptor2 = radv_get_sampler_desc(abi, descriptor_set, base_index, constant_index, index, AC_DESC_PLANE_1,image, write, bindless);
2030
2031 LLVMValueRef components[8];
2032 for (unsigned i = 0; i < 4; ++i)
2033 components[i] = ac_llvm_extract_elem(&ctx->ac, descriptor, i);
2034
2035 for (unsigned i = 4; i < 8; ++i)
2036 components[i] = ac_llvm_extract_elem(&ctx->ac, descriptor2, i);
2037 descriptor = ac_build_gather_values(&ctx->ac, components, 8);
2038 }
2039
2040 return descriptor;
2041 }
2042
2043 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
2044 * so we may need to fix it up. */
2045 static LLVMValueRef
2046 adjust_vertex_fetch_alpha(struct radv_shader_context *ctx,
2047 unsigned adjustment,
2048 LLVMValueRef alpha)
2049 {
2050 if (adjustment == RADV_ALPHA_ADJUST_NONE)
2051 return alpha;
2052
2053 LLVMValueRef c30 = LLVMConstInt(ctx->ac.i32, 30, 0);
2054
2055 alpha = LLVMBuildBitCast(ctx->ac.builder, alpha, ctx->ac.f32, "");
2056
2057 if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
2058 alpha = LLVMBuildFPToUI(ctx->ac.builder, alpha, ctx->ac.i32, "");
2059 else
2060 alpha = ac_to_integer(&ctx->ac, alpha);
2061
2062 /* For the integer-like cases, do a natural sign extension.
2063 *
2064 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
2065 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
2066 * exponent.
2067 */
2068 alpha = LLVMBuildShl(ctx->ac.builder, alpha,
2069 adjustment == RADV_ALPHA_ADJUST_SNORM ?
2070 LLVMConstInt(ctx->ac.i32, 7, 0) : c30, "");
2071 alpha = LLVMBuildAShr(ctx->ac.builder, alpha, c30, "");
2072
2073 /* Convert back to the right type. */
2074 if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
2075 LLVMValueRef clamp;
2076 LLVMValueRef neg_one = LLVMConstReal(ctx->ac.f32, -1.0);
2077 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
2078 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, alpha, neg_one, "");
2079 alpha = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, alpha, "");
2080 } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
2081 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
2082 }
2083
2084 return LLVMBuildBitCast(ctx->ac.builder, alpha, ctx->ac.i32, "");
2085 }
2086
2087 static unsigned
2088 get_num_channels_from_data_format(unsigned data_format)
2089 {
2090 switch (data_format) {
2091 case V_008F0C_BUF_DATA_FORMAT_8:
2092 case V_008F0C_BUF_DATA_FORMAT_16:
2093 case V_008F0C_BUF_DATA_FORMAT_32:
2094 return 1;
2095 case V_008F0C_BUF_DATA_FORMAT_8_8:
2096 case V_008F0C_BUF_DATA_FORMAT_16_16:
2097 case V_008F0C_BUF_DATA_FORMAT_32_32:
2098 return 2;
2099 case V_008F0C_BUF_DATA_FORMAT_10_11_11:
2100 case V_008F0C_BUF_DATA_FORMAT_11_11_10:
2101 case V_008F0C_BUF_DATA_FORMAT_32_32_32:
2102 return 3;
2103 case V_008F0C_BUF_DATA_FORMAT_8_8_8_8:
2104 case V_008F0C_BUF_DATA_FORMAT_10_10_10_2:
2105 case V_008F0C_BUF_DATA_FORMAT_2_10_10_10:
2106 case V_008F0C_BUF_DATA_FORMAT_16_16_16_16:
2107 case V_008F0C_BUF_DATA_FORMAT_32_32_32_32:
2108 return 4;
2109 default:
2110 break;
2111 }
2112
2113 return 4;
2114 }
2115
2116 static LLVMValueRef
2117 radv_fixup_vertex_input_fetches(struct radv_shader_context *ctx,
2118 LLVMValueRef value,
2119 unsigned num_channels,
2120 bool is_float)
2121 {
2122 LLVMValueRef zero = is_float ? ctx->ac.f32_0 : ctx->ac.i32_0;
2123 LLVMValueRef one = is_float ? ctx->ac.f32_1 : ctx->ac.i32_1;
2124 LLVMValueRef chan[4];
2125
2126 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMVectorTypeKind) {
2127 unsigned vec_size = LLVMGetVectorSize(LLVMTypeOf(value));
2128
2129 if (num_channels == 4 && num_channels == vec_size)
2130 return value;
2131
2132 num_channels = MIN2(num_channels, vec_size);
2133
2134 for (unsigned i = 0; i < num_channels; i++)
2135 chan[i] = ac_llvm_extract_elem(&ctx->ac, value, i);
2136 } else {
2137 if (num_channels) {
2138 assert(num_channels == 1);
2139 chan[0] = value;
2140 }
2141 }
2142
2143 for (unsigned i = num_channels; i < 4; i++) {
2144 chan[i] = i == 3 ? one : zero;
2145 chan[i] = ac_to_integer(&ctx->ac, chan[i]);
2146 }
2147
2148 return ac_build_gather_values(&ctx->ac, chan, 4);
2149 }
2150
2151 static void
2152 handle_vs_input_decl(struct radv_shader_context *ctx,
2153 struct nir_variable *variable)
2154 {
2155 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
2156 LLVMValueRef t_offset;
2157 LLVMValueRef t_list;
2158 LLVMValueRef input;
2159 LLVMValueRef buffer_index;
2160 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
2161 uint8_t input_usage_mask =
2162 ctx->shader_info->vs.input_usage_mask[variable->data.location];
2163 unsigned num_input_channels = util_last_bit(input_usage_mask);
2164
2165 variable->data.driver_location = variable->data.location * 4;
2166
2167 enum glsl_base_type type = glsl_get_base_type(variable->type);
2168 for (unsigned i = 0; i < attrib_count; ++i) {
2169 LLVMValueRef output[4];
2170 unsigned attrib_index = variable->data.location + i - VERT_ATTRIB_GENERIC0;
2171 unsigned attrib_format = ctx->options->key.vs.vertex_attribute_formats[attrib_index];
2172 unsigned data_format = attrib_format & 0x0f;
2173 unsigned num_format = (attrib_format >> 4) & 0x07;
2174 bool is_float = num_format != V_008F0C_BUF_NUM_FORMAT_UINT &&
2175 num_format != V_008F0C_BUF_NUM_FORMAT_SINT;
2176
2177 if (ctx->options->key.vs.instance_rate_inputs & (1u << attrib_index)) {
2178 uint32_t divisor = ctx->options->key.vs.instance_rate_divisors[attrib_index];
2179
2180 if (divisor) {
2181 buffer_index = ctx->abi.instance_id;
2182
2183 if (divisor != 1) {
2184 buffer_index = LLVMBuildUDiv(ctx->ac.builder, buffer_index,
2185 LLVMConstInt(ctx->ac.i32, divisor, 0), "");
2186 }
2187 } else {
2188 buffer_index = ctx->ac.i32_0;
2189 }
2190
2191 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.start_instance, buffer_index, "");
2192 } else
2193 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
2194 ctx->abi.base_vertex, "");
2195
2196 /* Adjust the number of channels to load based on the vertex
2197 * attribute format.
2198 */
2199 unsigned num_format_channels = get_num_channels_from_data_format(data_format);
2200 unsigned num_channels = MIN2(num_input_channels, num_format_channels);
2201 unsigned attrib_binding = ctx->options->key.vs.vertex_attribute_bindings[attrib_index];
2202 unsigned attrib_offset = ctx->options->key.vs.vertex_attribute_offsets[attrib_index];
2203 unsigned attrib_stride = ctx->options->key.vs.vertex_attribute_strides[attrib_index];
2204
2205 if (ctx->options->key.vs.post_shuffle & (1 << attrib_index)) {
2206 /* Always load, at least, 3 channels for formats that
2207 * need to be shuffled because X<->Z.
2208 */
2209 num_channels = MAX2(num_channels, 3);
2210 }
2211
2212 if (attrib_stride != 0 && attrib_offset > attrib_stride) {
2213 LLVMValueRef buffer_offset =
2214 LLVMConstInt(ctx->ac.i32,
2215 attrib_offset / attrib_stride, false);
2216
2217 buffer_index = LLVMBuildAdd(ctx->ac.builder,
2218 buffer_index,
2219 buffer_offset, "");
2220
2221 attrib_offset = attrib_offset % attrib_stride;
2222 }
2223
2224 t_offset = LLVMConstInt(ctx->ac.i32, attrib_binding, false);
2225 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
2226
2227 input = ac_build_struct_tbuffer_load(&ctx->ac, t_list,
2228 buffer_index,
2229 LLVMConstInt(ctx->ac.i32, attrib_offset, false),
2230 ctx->ac.i32_0, ctx->ac.i32_0,
2231 num_channels,
2232 data_format, num_format, 0, true);
2233
2234 if (ctx->options->key.vs.post_shuffle & (1 << attrib_index)) {
2235 LLVMValueRef c[4];
2236 c[0] = ac_llvm_extract_elem(&ctx->ac, input, 2);
2237 c[1] = ac_llvm_extract_elem(&ctx->ac, input, 1);
2238 c[2] = ac_llvm_extract_elem(&ctx->ac, input, 0);
2239 c[3] = ac_llvm_extract_elem(&ctx->ac, input, 3);
2240
2241 input = ac_build_gather_values(&ctx->ac, c, 4);
2242 }
2243
2244 input = radv_fixup_vertex_input_fetches(ctx, input, num_channels,
2245 is_float);
2246
2247 for (unsigned chan = 0; chan < 4; chan++) {
2248 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
2249 output[chan] = LLVMBuildExtractElement(ctx->ac.builder, input, llvm_chan, "");
2250 if (type == GLSL_TYPE_FLOAT16) {
2251 output[chan] = LLVMBuildBitCast(ctx->ac.builder, output[chan], ctx->ac.f32, "");
2252 output[chan] = LLVMBuildFPTrunc(ctx->ac.builder, output[chan], ctx->ac.f16, "");
2253 }
2254 }
2255
2256 unsigned alpha_adjust = (ctx->options->key.vs.alpha_adjust >> (attrib_index * 2)) & 3;
2257 output[3] = adjust_vertex_fetch_alpha(ctx, alpha_adjust, output[3]);
2258
2259 for (unsigned chan = 0; chan < 4; chan++) {
2260 output[chan] = ac_to_integer(&ctx->ac, output[chan]);
2261 if (type == GLSL_TYPE_UINT16 || type == GLSL_TYPE_INT16)
2262 output[chan] = LLVMBuildTrunc(ctx->ac.builder, output[chan], ctx->ac.i16, "");
2263
2264 ctx->inputs[ac_llvm_reg_index_soa(variable->data.location + i, chan)] = output[chan];
2265 }
2266 }
2267 }
2268
2269 static void
2270 handle_vs_inputs(struct radv_shader_context *ctx,
2271 struct nir_shader *nir) {
2272 nir_foreach_variable(variable, &nir->inputs)
2273 handle_vs_input_decl(ctx, variable);
2274 }
2275
2276 static void
2277 prepare_interp_optimize(struct radv_shader_context *ctx,
2278 struct nir_shader *nir)
2279 {
2280 bool uses_center = false;
2281 bool uses_centroid = false;
2282 nir_foreach_variable(variable, &nir->inputs) {
2283 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
2284 variable->data.sample)
2285 continue;
2286
2287 if (variable->data.centroid)
2288 uses_centroid = true;
2289 else
2290 uses_center = true;
2291 }
2292
2293 if (uses_center && uses_centroid) {
2294 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
2295 ctx->abi.persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->abi.persp_center, ctx->abi.persp_centroid, "");
2296 ctx->abi.linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->abi.linear_center, ctx->abi.linear_centroid, "");
2297 }
2298 }
2299
2300 static void
2301 scan_shader_output_decl(struct radv_shader_context *ctx,
2302 struct nir_variable *variable,
2303 struct nir_shader *shader,
2304 gl_shader_stage stage)
2305 {
2306 int idx = variable->data.location + variable->data.index;
2307 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
2308 uint64_t mask_attribs;
2309
2310 variable->data.driver_location = idx * 4;
2311
2312 /* tess ctrl has it's own load/store paths for outputs */
2313 if (stage == MESA_SHADER_TESS_CTRL)
2314 return;
2315
2316 if (variable->data.compact) {
2317 unsigned component_count = variable->data.location_frac +
2318 glsl_get_length(variable->type);
2319 attrib_count = (component_count + 3) / 4;
2320 }
2321
2322 mask_attribs = ((1ull << attrib_count) - 1) << idx;
2323
2324 ctx->output_mask |= mask_attribs;
2325 }
2326
2327
2328 /* Initialize arguments for the shader export intrinsic */
2329 static void
2330 si_llvm_init_export_args(struct radv_shader_context *ctx,
2331 LLVMValueRef *values,
2332 unsigned enabled_channels,
2333 unsigned target,
2334 struct ac_export_args *args)
2335 {
2336 /* Specify the channels that are enabled. */
2337 args->enabled_channels = enabled_channels;
2338
2339 /* Specify whether the EXEC mask represents the valid mask */
2340 args->valid_mask = 0;
2341
2342 /* Specify whether this is the last export */
2343 args->done = 0;
2344
2345 /* Specify the target we are exporting */
2346 args->target = target;
2347
2348 args->compr = false;
2349 args->out[0] = LLVMGetUndef(ctx->ac.f32);
2350 args->out[1] = LLVMGetUndef(ctx->ac.f32);
2351 args->out[2] = LLVMGetUndef(ctx->ac.f32);
2352 args->out[3] = LLVMGetUndef(ctx->ac.f32);
2353
2354 if (!values)
2355 return;
2356
2357 bool is_16bit = ac_get_type_size(LLVMTypeOf(values[0])) == 2;
2358 if (ctx->stage == MESA_SHADER_FRAGMENT) {
2359 unsigned index = target - V_008DFC_SQ_EXP_MRT;
2360 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
2361 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
2362 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
2363 unsigned chan;
2364
2365 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2366 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2367 unsigned bits, bool hi) = NULL;
2368
2369 switch(col_format) {
2370 case V_028714_SPI_SHADER_ZERO:
2371 args->enabled_channels = 0; /* writemask */
2372 args->target = V_008DFC_SQ_EXP_NULL;
2373 break;
2374
2375 case V_028714_SPI_SHADER_32_R:
2376 args->enabled_channels = 1;
2377 args->out[0] = values[0];
2378 break;
2379
2380 case V_028714_SPI_SHADER_32_GR:
2381 args->enabled_channels = 0x3;
2382 args->out[0] = values[0];
2383 args->out[1] = values[1];
2384 break;
2385
2386 case V_028714_SPI_SHADER_32_AR:
2387 if (ctx->ac.chip_class >= GFX10) {
2388 args->enabled_channels = 0x3;
2389 args->out[0] = values[0];
2390 args->out[1] = values[3];
2391 } else {
2392 args->enabled_channels = 0x9;
2393 args->out[0] = values[0];
2394 args->out[3] = values[3];
2395 }
2396 break;
2397
2398 case V_028714_SPI_SHADER_FP16_ABGR:
2399 args->enabled_channels = 0x5;
2400 packf = ac_build_cvt_pkrtz_f16;
2401 if (is_16bit) {
2402 for (unsigned chan = 0; chan < 4; chan++)
2403 values[chan] = LLVMBuildFPExt(ctx->ac.builder,
2404 values[chan],
2405 ctx->ac.f32, "");
2406 }
2407 break;
2408
2409 case V_028714_SPI_SHADER_UNORM16_ABGR:
2410 args->enabled_channels = 0x5;
2411 packf = ac_build_cvt_pknorm_u16;
2412 break;
2413
2414 case V_028714_SPI_SHADER_SNORM16_ABGR:
2415 args->enabled_channels = 0x5;
2416 packf = ac_build_cvt_pknorm_i16;
2417 break;
2418
2419 case V_028714_SPI_SHADER_UINT16_ABGR:
2420 args->enabled_channels = 0x5;
2421 packi = ac_build_cvt_pk_u16;
2422 if (is_16bit) {
2423 for (unsigned chan = 0; chan < 4; chan++)
2424 values[chan] = LLVMBuildZExt(ctx->ac.builder,
2425 ac_to_integer(&ctx->ac, values[chan]),
2426 ctx->ac.i32, "");
2427 }
2428 break;
2429
2430 case V_028714_SPI_SHADER_SINT16_ABGR:
2431 args->enabled_channels = 0x5;
2432 packi = ac_build_cvt_pk_i16;
2433 if (is_16bit) {
2434 for (unsigned chan = 0; chan < 4; chan++)
2435 values[chan] = LLVMBuildSExt(ctx->ac.builder,
2436 ac_to_integer(&ctx->ac, values[chan]),
2437 ctx->ac.i32, "");
2438 }
2439 break;
2440
2441 default:
2442 case V_028714_SPI_SHADER_32_ABGR:
2443 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2444 break;
2445 }
2446
2447 /* Pack f16 or norm_i16/u16. */
2448 if (packf) {
2449 for (chan = 0; chan < 2; chan++) {
2450 LLVMValueRef pack_args[2] = {
2451 values[2 * chan],
2452 values[2 * chan + 1]
2453 };
2454 LLVMValueRef packed;
2455
2456 packed = packf(&ctx->ac, pack_args);
2457 args->out[chan] = ac_to_float(&ctx->ac, packed);
2458 }
2459 args->compr = 1; /* COMPR flag */
2460 }
2461
2462 /* Pack i16/u16. */
2463 if (packi) {
2464 for (chan = 0; chan < 2; chan++) {
2465 LLVMValueRef pack_args[2] = {
2466 ac_to_integer(&ctx->ac, values[2 * chan]),
2467 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2468 };
2469 LLVMValueRef packed;
2470
2471 packed = packi(&ctx->ac, pack_args,
2472 is_int8 ? 8 : is_int10 ? 10 : 16,
2473 chan == 1);
2474 args->out[chan] = ac_to_float(&ctx->ac, packed);
2475 }
2476 args->compr = 1; /* COMPR flag */
2477 }
2478 return;
2479 }
2480
2481 if (is_16bit) {
2482 for (unsigned chan = 0; chan < 4; chan++) {
2483 values[chan] = LLVMBuildBitCast(ctx->ac.builder, values[chan], ctx->ac.i16, "");
2484 args->out[chan] = LLVMBuildZExt(ctx->ac.builder, values[chan], ctx->ac.i32, "");
2485 }
2486 } else
2487 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2488
2489 for (unsigned i = 0; i < 4; ++i)
2490 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
2491 }
2492
2493 static void
2494 radv_export_param(struct radv_shader_context *ctx, unsigned index,
2495 LLVMValueRef *values, unsigned enabled_channels)
2496 {
2497 struct ac_export_args args;
2498
2499 si_llvm_init_export_args(ctx, values, enabled_channels,
2500 V_008DFC_SQ_EXP_PARAM + index, &args);
2501 ac_build_export(&ctx->ac, &args);
2502 }
2503
2504 static LLVMValueRef
2505 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
2506 {
2507 LLVMValueRef output = ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
2508 return LLVMBuildLoad(ctx->ac.builder, output, "");
2509 }
2510
2511 static void
2512 radv_emit_stream_output(struct radv_shader_context *ctx,
2513 LLVMValueRef const *so_buffers,
2514 LLVMValueRef const *so_write_offsets,
2515 const struct radv_stream_output *output,
2516 struct radv_shader_output_values *shader_out)
2517 {
2518 unsigned num_comps = util_bitcount(output->component_mask);
2519 unsigned buf = output->buffer;
2520 unsigned offset = output->offset;
2521 unsigned start;
2522 LLVMValueRef out[4];
2523
2524 assert(num_comps && num_comps <= 4);
2525 if (!num_comps || num_comps > 4)
2526 return;
2527
2528 /* Get the first component. */
2529 start = ffs(output->component_mask) - 1;
2530
2531 /* Load the output as int. */
2532 for (int i = 0; i < num_comps; i++) {
2533 out[i] = ac_to_integer(&ctx->ac, shader_out->values[start + i]);
2534 }
2535
2536 /* Pack the output. */
2537 LLVMValueRef vdata = NULL;
2538
2539 switch (num_comps) {
2540 case 1: /* as i32 */
2541 vdata = out[0];
2542 break;
2543 case 2: /* as v2i32 */
2544 case 3: /* as v4i32 (aligned to 4) */
2545 out[3] = LLVMGetUndef(ctx->ac.i32);
2546 /* fall through */
2547 case 4: /* as v4i32 */
2548 vdata = ac_build_gather_values(&ctx->ac, out,
2549 !ac_has_vec3_support(ctx->ac.chip_class, false) ?
2550 util_next_power_of_two(num_comps) :
2551 num_comps);
2552 break;
2553 }
2554
2555 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf],
2556 vdata, num_comps, so_write_offsets[buf],
2557 ctx->ac.i32_0, offset,
2558 ac_glc | ac_slc, false);
2559 }
2560
2561 static void
2562 radv_emit_streamout(struct radv_shader_context *ctx, unsigned stream)
2563 {
2564 int i;
2565
2566 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2567 assert(ctx->streamout_config);
2568 LLVMValueRef so_vtx_count =
2569 ac_build_bfe(&ctx->ac, ctx->streamout_config,
2570 LLVMConstInt(ctx->ac.i32, 16, false),
2571 LLVMConstInt(ctx->ac.i32, 7, false), false);
2572
2573 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2574
2575 /* can_emit = tid < so_vtx_count; */
2576 LLVMValueRef can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
2577 tid, so_vtx_count, "");
2578
2579 /* Emit the streamout code conditionally. This actually avoids
2580 * out-of-bounds buffer access. The hw tells us via the SGPR
2581 * (so_vtx_count) which threads are allowed to emit streamout data.
2582 */
2583 ac_build_ifcc(&ctx->ac, can_emit, 6501);
2584 {
2585 /* The buffer offset is computed as follows:
2586 * ByteOffset = streamout_offset[buffer_id]*4 +
2587 * (streamout_write_index + thread_id)*stride[buffer_id] +
2588 * attrib_offset
2589 */
2590 LLVMValueRef so_write_index = ctx->streamout_write_idx;
2591
2592 /* Compute (streamout_write_index + thread_id). */
2593 so_write_index =
2594 LLVMBuildAdd(ctx->ac.builder, so_write_index, tid, "");
2595
2596 /* Load the descriptor and compute the write offset for each
2597 * enabled buffer.
2598 */
2599 LLVMValueRef so_write_offset[4] = {};
2600 LLVMValueRef so_buffers[4] = {};
2601 LLVMValueRef buf_ptr = ctx->streamout_buffers;
2602
2603 for (i = 0; i < 4; i++) {
2604 uint16_t stride = ctx->shader_info->so.strides[i];
2605
2606 if (!stride)
2607 continue;
2608
2609 LLVMValueRef offset =
2610 LLVMConstInt(ctx->ac.i32, i, false);
2611
2612 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac,
2613 buf_ptr, offset);
2614
2615 LLVMValueRef so_offset = ctx->streamout_offset[i];
2616
2617 so_offset = LLVMBuildMul(ctx->ac.builder, so_offset,
2618 LLVMConstInt(ctx->ac.i32, 4, false), "");
2619
2620 so_write_offset[i] =
2621 ac_build_imad(&ctx->ac, so_write_index,
2622 LLVMConstInt(ctx->ac.i32,
2623 stride * 4, false),
2624 so_offset);
2625 }
2626
2627 /* Write streamout data. */
2628 for (i = 0; i < ctx->shader_info->so.num_outputs; i++) {
2629 struct radv_shader_output_values shader_out = {};
2630 struct radv_stream_output *output =
2631 &ctx->shader_info->so.outputs[i];
2632
2633 if (stream != output->stream)
2634 continue;
2635
2636 for (int j = 0; j < 4; j++) {
2637 shader_out.values[j] =
2638 radv_load_output(ctx, output->location, j);
2639 }
2640
2641 radv_emit_stream_output(ctx, so_buffers,so_write_offset,
2642 output, &shader_out);
2643 }
2644 }
2645 ac_build_endif(&ctx->ac, 6501);
2646 }
2647
2648 static void
2649 radv_build_param_exports(struct radv_shader_context *ctx,
2650 struct radv_shader_output_values *outputs,
2651 unsigned noutput,
2652 struct radv_vs_output_info *outinfo,
2653 bool export_clip_dists)
2654 {
2655 unsigned param_count = 0;
2656
2657 for (unsigned i = 0; i < noutput; i++) {
2658 unsigned slot_name = outputs[i].slot_name;
2659 unsigned usage_mask = outputs[i].usage_mask;
2660
2661 if (slot_name != VARYING_SLOT_LAYER &&
2662 slot_name != VARYING_SLOT_PRIMITIVE_ID &&
2663 slot_name != VARYING_SLOT_CLIP_DIST0 &&
2664 slot_name != VARYING_SLOT_CLIP_DIST1 &&
2665 slot_name < VARYING_SLOT_VAR0)
2666 continue;
2667
2668 if ((slot_name == VARYING_SLOT_CLIP_DIST0 ||
2669 slot_name == VARYING_SLOT_CLIP_DIST1) && !export_clip_dists)
2670 continue;
2671
2672 radv_export_param(ctx, param_count, outputs[i].values, usage_mask);
2673
2674 assert(i < ARRAY_SIZE(outinfo->vs_output_param_offset));
2675 outinfo->vs_output_param_offset[slot_name] = param_count++;
2676 }
2677
2678 outinfo->param_exports = param_count;
2679 }
2680
2681 /* Generate export instructions for hardware VS shader stage or NGG GS stage
2682 * (position and parameter data only).
2683 */
2684 static void
2685 radv_llvm_export_vs(struct radv_shader_context *ctx,
2686 struct radv_shader_output_values *outputs,
2687 unsigned noutput,
2688 struct radv_vs_output_info *outinfo,
2689 bool export_clip_dists)
2690 {
2691 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_value = NULL;
2692 struct ac_export_args pos_args[4] = {};
2693 unsigned pos_idx, index;
2694 int i;
2695
2696 /* Build position exports */
2697 for (i = 0; i < noutput; i++) {
2698 switch (outputs[i].slot_name) {
2699 case VARYING_SLOT_POS:
2700 si_llvm_init_export_args(ctx, outputs[i].values, 0xf,
2701 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2702 break;
2703 case VARYING_SLOT_PSIZ:
2704 psize_value = outputs[i].values[0];
2705 break;
2706 case VARYING_SLOT_LAYER:
2707 layer_value = outputs[i].values[0];
2708 break;
2709 case VARYING_SLOT_VIEWPORT:
2710 viewport_value = outputs[i].values[0];
2711 break;
2712 case VARYING_SLOT_CLIP_DIST0:
2713 case VARYING_SLOT_CLIP_DIST1:
2714 index = 2 + outputs[i].slot_index;
2715 si_llvm_init_export_args(ctx, outputs[i].values, 0xf,
2716 V_008DFC_SQ_EXP_POS + index,
2717 &pos_args[index]);
2718 break;
2719 default:
2720 break;
2721 }
2722 }
2723
2724 /* We need to add the position output manually if it's missing. */
2725 if (!pos_args[0].out[0]) {
2726 pos_args[0].enabled_channels = 0xf; /* writemask */
2727 pos_args[0].valid_mask = 0; /* EXEC mask */
2728 pos_args[0].done = 0; /* last export? */
2729 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2730 pos_args[0].compr = 0; /* COMPR flag */
2731 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
2732 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
2733 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
2734 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
2735 }
2736
2737 if (outinfo->writes_pointsize ||
2738 outinfo->writes_layer ||
2739 outinfo->writes_viewport_index) {
2740 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
2741 (outinfo->writes_layer == true ? 4 : 0));
2742 pos_args[1].valid_mask = 0;
2743 pos_args[1].done = 0;
2744 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2745 pos_args[1].compr = 0;
2746 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2747 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2748 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2749 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2750
2751 if (outinfo->writes_pointsize == true)
2752 pos_args[1].out[0] = psize_value;
2753 if (outinfo->writes_layer == true)
2754 pos_args[1].out[2] = layer_value;
2755 if (outinfo->writes_viewport_index == true) {
2756 if (ctx->options->chip_class >= GFX9) {
2757 /* GFX9 has the layer in out.z[10:0] and the viewport
2758 * index in out.z[19:16].
2759 */
2760 LLVMValueRef v = viewport_value;
2761 v = ac_to_integer(&ctx->ac, v);
2762 v = LLVMBuildShl(ctx->ac.builder, v,
2763 LLVMConstInt(ctx->ac.i32, 16, false),
2764 "");
2765 v = LLVMBuildOr(ctx->ac.builder, v,
2766 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2767
2768 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2769 pos_args[1].enabled_channels |= 1 << 2;
2770 } else {
2771 pos_args[1].out[3] = viewport_value;
2772 pos_args[1].enabled_channels |= 1 << 3;
2773 }
2774 }
2775 }
2776
2777 for (i = 0; i < 4; i++) {
2778 if (pos_args[i].out[0])
2779 outinfo->pos_exports++;
2780 }
2781
2782 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
2783 * Setting valid_mask=1 prevents it and has no other effect.
2784 */
2785 if (ctx->ac.family == CHIP_NAVI10 ||
2786 ctx->ac.family == CHIP_NAVI12 ||
2787 ctx->ac.family == CHIP_NAVI14)
2788 pos_args[0].valid_mask = 1;
2789
2790 pos_idx = 0;
2791 for (i = 0; i < 4; i++) {
2792 if (!pos_args[i].out[0])
2793 continue;
2794
2795 /* Specify the target we are exporting */
2796 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2797
2798 if (pos_idx == outinfo->pos_exports)
2799 /* Specify that this is the last export */
2800 pos_args[i].done = 1;
2801
2802 ac_build_export(&ctx->ac, &pos_args[i]);
2803 }
2804
2805 /* Build parameter exports */
2806 radv_build_param_exports(ctx, outputs, noutput, outinfo, export_clip_dists);
2807 }
2808
2809 static void
2810 handle_vs_outputs_post(struct radv_shader_context *ctx,
2811 bool export_prim_id,
2812 bool export_clip_dists,
2813 struct radv_vs_output_info *outinfo)
2814 {
2815 struct radv_shader_output_values *outputs;
2816 unsigned noutput = 0;
2817
2818 if (ctx->options->key.has_multiview_view_index) {
2819 LLVMValueRef* tmp_out = &ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2820 if(!*tmp_out) {
2821 for(unsigned i = 0; i < 4; ++i)
2822 ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
2823 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
2824 }
2825
2826 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
2827 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
2828 }
2829
2830 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
2831 sizeof(outinfo->vs_output_param_offset));
2832 outinfo->pos_exports = 0;
2833
2834 if (!ctx->options->use_ngg_streamout &&
2835 ctx->shader_info->so.num_outputs &&
2836 !ctx->is_gs_copy_shader) {
2837 /* The GS copy shader emission already emits streamout. */
2838 radv_emit_streamout(ctx, 0);
2839 }
2840
2841 /* Allocate a temporary array for the output values. */
2842 unsigned num_outputs = util_bitcount64(ctx->output_mask) + export_prim_id;
2843 outputs = malloc(num_outputs * sizeof(outputs[0]));
2844
2845 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2846 if (!(ctx->output_mask & (1ull << i)))
2847 continue;
2848
2849 outputs[noutput].slot_name = i;
2850 outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
2851
2852 if (ctx->stage == MESA_SHADER_VERTEX &&
2853 !ctx->is_gs_copy_shader) {
2854 outputs[noutput].usage_mask =
2855 ctx->shader_info->vs.output_usage_mask[i];
2856 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
2857 outputs[noutput].usage_mask =
2858 ctx->shader_info->tes.output_usage_mask[i];
2859 } else {
2860 assert(ctx->is_gs_copy_shader);
2861 outputs[noutput].usage_mask =
2862 ctx->shader_info->gs.output_usage_mask[i];
2863 }
2864
2865 for (unsigned j = 0; j < 4; j++) {
2866 outputs[noutput].values[j] =
2867 ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2868 }
2869
2870 noutput++;
2871 }
2872
2873 /* Export PrimitiveID. */
2874 if (export_prim_id) {
2875 outputs[noutput].slot_name = VARYING_SLOT_PRIMITIVE_ID;
2876 outputs[noutput].slot_index = 0;
2877 outputs[noutput].usage_mask = 0x1;
2878 outputs[noutput].values[0] = ctx->vs_prim_id;
2879 for (unsigned j = 1; j < 4; j++)
2880 outputs[noutput].values[j] = ctx->ac.f32_0;
2881 noutput++;
2882 }
2883
2884 radv_llvm_export_vs(ctx, outputs, noutput, outinfo, export_clip_dists);
2885
2886 free(outputs);
2887 }
2888
2889 static void
2890 handle_es_outputs_post(struct radv_shader_context *ctx,
2891 struct radv_es_output_info *outinfo)
2892 {
2893 int j;
2894 LLVMValueRef lds_base = NULL;
2895
2896 if (ctx->ac.chip_class >= GFX9) {
2897 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
2898 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
2899 LLVMValueRef wave_idx = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 24, 4);
2900 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
2901 LLVMBuildMul(ctx->ac.builder, wave_idx,
2902 LLVMConstInt(ctx->ac.i32,
2903 ctx->ac.wave_size, false), ""), "");
2904 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
2905 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
2906 }
2907
2908 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2909 LLVMValueRef dw_addr = NULL;
2910 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2911 unsigned output_usage_mask;
2912 int param_index;
2913
2914 if (!(ctx->output_mask & (1ull << i)))
2915 continue;
2916
2917 if (ctx->stage == MESA_SHADER_VERTEX) {
2918 output_usage_mask =
2919 ctx->shader_info->vs.output_usage_mask[i];
2920 } else {
2921 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2922 output_usage_mask =
2923 ctx->shader_info->tes.output_usage_mask[i];
2924 }
2925
2926 param_index = shader_io_get_unique_index(i);
2927
2928 if (lds_base) {
2929 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2930 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
2931 "");
2932 }
2933
2934 for (j = 0; j < 4; j++) {
2935 if (!(output_usage_mask & (1 << j)))
2936 continue;
2937
2938 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2939 out_val = ac_to_integer(&ctx->ac, out_val);
2940 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
2941
2942 if (ctx->ac.chip_class >= GFX9) {
2943 LLVMValueRef dw_addr_offset =
2944 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2945 LLVMConstInt(ctx->ac.i32,
2946 j, false), "");
2947
2948 ac_lds_store(&ctx->ac, dw_addr_offset, out_val);
2949 } else {
2950 ac_build_buffer_store_dword(&ctx->ac,
2951 ctx->esgs_ring,
2952 out_val, 1,
2953 NULL, ctx->es2gs_offset,
2954 (4 * param_index + j) * 4,
2955 ac_glc | ac_slc, true);
2956 }
2957 }
2958 }
2959 }
2960
2961 static void
2962 handle_ls_outputs_post(struct radv_shader_context *ctx)
2963 {
2964 LLVMValueRef vertex_id = ctx->rel_auto_id;
2965 uint32_t num_tcs_inputs = util_last_bit64(ctx->shader_info->vs.ls_outputs_written);
2966 LLVMValueRef vertex_dw_stride = LLVMConstInt(ctx->ac.i32, num_tcs_inputs * 4, false);
2967 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
2968 vertex_dw_stride, "");
2969
2970 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2971 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2972
2973 if (!(ctx->output_mask & (1ull << i)))
2974 continue;
2975
2976 int param = shader_io_get_unique_index(i);
2977 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
2978 LLVMConstInt(ctx->ac.i32, param * 4, false),
2979 "");
2980 for (unsigned j = 0; j < 4; j++) {
2981 LLVMValueRef value = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2982 value = ac_to_integer(&ctx->ac, value);
2983 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
2984 ac_lds_store(&ctx->ac, dw_addr, value);
2985 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2986 }
2987 }
2988 }
2989
2990 static LLVMValueRef get_wave_id_in_tg(struct radv_shader_context *ctx)
2991 {
2992 return ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 24, 4);
2993 }
2994
2995 static LLVMValueRef get_tgsize(struct radv_shader_context *ctx)
2996 {
2997 return ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 28, 4);
2998 }
2999
3000 static LLVMValueRef get_thread_id_in_tg(struct radv_shader_context *ctx)
3001 {
3002 LLVMBuilderRef builder = ctx->ac.builder;
3003 LLVMValueRef tmp;
3004 tmp = LLVMBuildMul(builder, get_wave_id_in_tg(ctx),
3005 LLVMConstInt(ctx->ac.i32, ctx->ac.wave_size, false), "");
3006 return LLVMBuildAdd(builder, tmp, ac_get_thread_id(&ctx->ac), "");
3007 }
3008
3009 static LLVMValueRef ngg_get_vtx_cnt(struct radv_shader_context *ctx)
3010 {
3011 return ac_build_bfe(&ctx->ac, ctx->gs_tg_info,
3012 LLVMConstInt(ctx->ac.i32, 12, false),
3013 LLVMConstInt(ctx->ac.i32, 9, false),
3014 false);
3015 }
3016
3017 static LLVMValueRef ngg_get_prim_cnt(struct radv_shader_context *ctx)
3018 {
3019 return ac_build_bfe(&ctx->ac, ctx->gs_tg_info,
3020 LLVMConstInt(ctx->ac.i32, 22, false),
3021 LLVMConstInt(ctx->ac.i32, 9, false),
3022 false);
3023 }
3024
3025 static LLVMValueRef ngg_get_ordered_id(struct radv_shader_context *ctx)
3026 {
3027 return ac_build_bfe(&ctx->ac, ctx->gs_tg_info,
3028 ctx->ac.i32_0,
3029 LLVMConstInt(ctx->ac.i32, 11, false),
3030 false);
3031 }
3032
3033 static LLVMValueRef
3034 ngg_gs_get_vertex_storage(struct radv_shader_context *ctx)
3035 {
3036 unsigned num_outputs = util_bitcount64(ctx->output_mask);
3037
3038 if (ctx->options->key.has_multiview_view_index)
3039 num_outputs++;
3040
3041 LLVMTypeRef elements[2] = {
3042 LLVMArrayType(ctx->ac.i32, 4 * num_outputs),
3043 LLVMArrayType(ctx->ac.i8, 4),
3044 };
3045 LLVMTypeRef type = LLVMStructTypeInContext(ctx->ac.context, elements, 2, false);
3046 type = LLVMPointerType(LLVMArrayType(type, 0), AC_ADDR_SPACE_LDS);
3047 return LLVMBuildBitCast(ctx->ac.builder, ctx->gs_ngg_emit, type, "");
3048 }
3049
3050 /**
3051 * Return a pointer to the LDS storage reserved for the N'th vertex, where N
3052 * is in emit order; that is:
3053 * - during the epilogue, N is the threadidx (relative to the entire threadgroup)
3054 * - during vertex emit, i.e. while the API GS shader invocation is running,
3055 * N = threadidx * gs_max_out_vertices + emitidx
3056 *
3057 * Goals of the LDS memory layout:
3058 * 1. Eliminate bank conflicts on write for geometry shaders that have all emits
3059 * in uniform control flow
3060 * 2. Eliminate bank conflicts on read for export if, additionally, there is no
3061 * culling
3062 * 3. Agnostic to the number of waves (since we don't know it before compiling)
3063 * 4. Allow coalescing of LDS instructions (ds_write_b128 etc.)
3064 * 5. Avoid wasting memory.
3065 *
3066 * We use an AoS layout due to point 4 (this also helps point 3). In an AoS
3067 * layout, elimination of bank conflicts requires that each vertex occupy an
3068 * odd number of dwords. We use the additional dword to store the output stream
3069 * index as well as a flag to indicate whether this vertex ends a primitive
3070 * for rasterization.
3071 *
3072 * Swizzling is required to satisfy points 1 and 2 simultaneously.
3073 *
3074 * Vertices are stored in export order (gsthread * gs_max_out_vertices + emitidx).
3075 * Indices are swizzled in groups of 32, which ensures point 1 without
3076 * disturbing point 2.
3077 *
3078 * \return an LDS pointer to type {[N x i32], [4 x i8]}
3079 */
3080 static LLVMValueRef
3081 ngg_gs_vertex_ptr(struct radv_shader_context *ctx, LLVMValueRef vertexidx)
3082 {
3083 LLVMBuilderRef builder = ctx->ac.builder;
3084 LLVMValueRef storage = ngg_gs_get_vertex_storage(ctx);
3085
3086 /* gs_max_out_vertices = 2^(write_stride_2exp) * some odd number */
3087 unsigned write_stride_2exp = ffs(ctx->shader->info.gs.vertices_out) - 1;
3088 if (write_stride_2exp) {
3089 LLVMValueRef row =
3090 LLVMBuildLShr(builder, vertexidx,
3091 LLVMConstInt(ctx->ac.i32, 5, false), "");
3092 LLVMValueRef swizzle =
3093 LLVMBuildAnd(builder, row,
3094 LLVMConstInt(ctx->ac.i32, (1u << write_stride_2exp) - 1,
3095 false), "");
3096 vertexidx = LLVMBuildXor(builder, vertexidx, swizzle, "");
3097 }
3098
3099 return ac_build_gep0(&ctx->ac, storage, vertexidx);
3100 }
3101
3102 static LLVMValueRef
3103 ngg_gs_emit_vertex_ptr(struct radv_shader_context *ctx, LLVMValueRef gsthread,
3104 LLVMValueRef emitidx)
3105 {
3106 LLVMBuilderRef builder = ctx->ac.builder;
3107 LLVMValueRef tmp;
3108
3109 tmp = LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false);
3110 tmp = LLVMBuildMul(builder, tmp, gsthread, "");
3111 const LLVMValueRef vertexidx = LLVMBuildAdd(builder, tmp, emitidx, "");
3112 return ngg_gs_vertex_ptr(ctx, vertexidx);
3113 }
3114
3115 /* Send GS Alloc Req message from the first wave of the group to SPI.
3116 * Message payload is:
3117 * - bits 0..10: vertices in group
3118 * - bits 12..22: primitives in group
3119 */
3120 static void build_sendmsg_gs_alloc_req(struct radv_shader_context *ctx,
3121 LLVMValueRef vtx_cnt,
3122 LLVMValueRef prim_cnt)
3123 {
3124 LLVMBuilderRef builder = ctx->ac.builder;
3125 LLVMValueRef tmp;
3126
3127 tmp = LLVMBuildICmp(builder, LLVMIntEQ, get_wave_id_in_tg(ctx), ctx->ac.i32_0, "");
3128 ac_build_ifcc(&ctx->ac, tmp, 5020);
3129
3130 tmp = LLVMBuildShl(builder, prim_cnt, LLVMConstInt(ctx->ac.i32, 12, false),"");
3131 tmp = LLVMBuildOr(builder, tmp, vtx_cnt, "");
3132 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_ALLOC_REQ, tmp);
3133
3134 ac_build_endif(&ctx->ac, 5020);
3135 }
3136
3137 struct ngg_prim {
3138 unsigned num_vertices;
3139 LLVMValueRef isnull;
3140 LLVMValueRef index[3];
3141 LLVMValueRef edgeflag[3];
3142 };
3143
3144 static void build_export_prim(struct radv_shader_context *ctx,
3145 const struct ngg_prim *prim)
3146 {
3147 LLVMBuilderRef builder = ctx->ac.builder;
3148 struct ac_export_args args;
3149 LLVMValueRef tmp;
3150
3151 tmp = LLVMBuildZExt(builder, prim->isnull, ctx->ac.i32, "");
3152 args.out[0] = LLVMBuildShl(builder, tmp, LLVMConstInt(ctx->ac.i32, 31, false), "");
3153
3154 for (unsigned i = 0; i < prim->num_vertices; ++i) {
3155 tmp = LLVMBuildShl(builder, prim->index[i],
3156 LLVMConstInt(ctx->ac.i32, 10 * i, false), "");
3157 args.out[0] = LLVMBuildOr(builder, args.out[0], tmp, "");
3158 tmp = LLVMBuildZExt(builder, prim->edgeflag[i], ctx->ac.i32, "");
3159 tmp = LLVMBuildShl(builder, tmp,
3160 LLVMConstInt(ctx->ac.i32, 10 * i + 9, false), "");
3161 args.out[0] = LLVMBuildOr(builder, args.out[0], tmp, "");
3162 }
3163
3164 args.out[0] = LLVMBuildBitCast(builder, args.out[0], ctx->ac.f32, "");
3165 args.out[1] = LLVMGetUndef(ctx->ac.f32);
3166 args.out[2] = LLVMGetUndef(ctx->ac.f32);
3167 args.out[3] = LLVMGetUndef(ctx->ac.f32);
3168
3169 args.target = V_008DFC_SQ_EXP_PRIM;
3170 args.enabled_channels = 1;
3171 args.done = true;
3172 args.valid_mask = false;
3173 args.compr = false;
3174
3175 ac_build_export(&ctx->ac, &args);
3176 }
3177
3178 static void build_streamout_vertex(struct radv_shader_context *ctx,
3179 LLVMValueRef *so_buffer, LLVMValueRef *wg_offset_dw,
3180 unsigned stream, LLVMValueRef offset_vtx,
3181 LLVMValueRef vertexptr)
3182 {
3183 struct radv_streamout_info *so = &ctx->shader_info->so;
3184 LLVMBuilderRef builder = ctx->ac.builder;
3185 LLVMValueRef offset[4] = {};
3186 LLVMValueRef tmp;
3187
3188 for (unsigned buffer = 0; buffer < 4; ++buffer) {
3189 if (!wg_offset_dw[buffer])
3190 continue;
3191
3192 tmp = LLVMBuildMul(builder, offset_vtx,
3193 LLVMConstInt(ctx->ac.i32, so->strides[buffer], false), "");
3194 tmp = LLVMBuildAdd(builder, wg_offset_dw[buffer], tmp, "");
3195 offset[buffer] = LLVMBuildShl(builder, tmp, LLVMConstInt(ctx->ac.i32, 2, false), "");
3196 }
3197
3198 for (unsigned i = 0; i < so->num_outputs; ++i) {
3199 struct radv_stream_output *output =
3200 &ctx->shader_info->so.outputs[i];
3201
3202 if (stream != output->stream)
3203 continue;
3204
3205 struct radv_shader_output_values out = {};
3206
3207 for (unsigned comp = 0; comp < 4; comp++) {
3208 if (!(output->component_mask & (1 << comp)))
3209 continue;
3210
3211 tmp = ac_build_gep0(&ctx->ac, vertexptr,
3212 LLVMConstInt(ctx->ac.i32, 4 * i + comp, false));
3213 out.values[comp] = LLVMBuildLoad(builder, tmp, "");
3214 }
3215
3216 radv_emit_stream_output(ctx, so_buffer, offset, output, &out);
3217 }
3218 }
3219
3220 struct ngg_streamout {
3221 LLVMValueRef num_vertices;
3222
3223 /* per-thread data */
3224 LLVMValueRef prim_enable[4]; /* i1 per stream */
3225 LLVMValueRef vertices[3]; /* [N x i32] addrspace(LDS)* */
3226
3227 /* Output */
3228 LLVMValueRef emit[4]; /* per-stream emitted primitives (only valid for used streams) */
3229 };
3230
3231 /**
3232 * Build streamout logic.
3233 *
3234 * Implies a barrier.
3235 *
3236 * Writes number of emitted primitives to gs_ngg_scratch[4:7].
3237 *
3238 * Clobbers gs_ngg_scratch[8:].
3239 */
3240 static void build_streamout(struct radv_shader_context *ctx,
3241 struct ngg_streamout *nggso)
3242 {
3243 struct radv_streamout_info *so = &ctx->shader_info->so;
3244 LLVMBuilderRef builder = ctx->ac.builder;
3245 LLVMValueRef buf_ptr = ctx->streamout_buffers;
3246 LLVMValueRef tid = get_thread_id_in_tg(ctx);
3247 LLVMValueRef cond, tmp, tmp2;
3248 LLVMValueRef i32_2 = LLVMConstInt(ctx->ac.i32, 2, false);
3249 LLVMValueRef i32_4 = LLVMConstInt(ctx->ac.i32, 4, false);
3250 LLVMValueRef i32_8 = LLVMConstInt(ctx->ac.i32, 8, false);
3251 LLVMValueRef so_buffer[4] = {};
3252 unsigned max_num_vertices = 1 + (nggso->vertices[1] ? 1 : 0) +
3253 (nggso->vertices[2] ? 1 : 0);
3254 LLVMValueRef prim_stride_dw[4] = {};
3255 LLVMValueRef prim_stride_dw_vgpr = LLVMGetUndef(ctx->ac.i32);
3256 int stream_for_buffer[4] = { -1, -1, -1, -1 };
3257 unsigned bufmask_for_stream[4] = {};
3258 bool isgs = ctx->stage == MESA_SHADER_GEOMETRY;
3259 unsigned scratch_emit_base = isgs ? 4 : 0;
3260 LLVMValueRef scratch_emit_basev = isgs ? i32_4 : ctx->ac.i32_0;
3261 unsigned scratch_offset_base = isgs ? 8 : 4;
3262 LLVMValueRef scratch_offset_basev = isgs ? i32_8 : i32_4;
3263
3264 ac_llvm_add_target_dep_function_attr(ctx->main_function,
3265 "amdgpu-gds-size", 256);
3266
3267 /* Determine the mapping of streamout buffers to vertex streams. */
3268 for (unsigned i = 0; i < so->num_outputs; ++i) {
3269 unsigned buf = so->outputs[i].buffer;
3270 unsigned stream = so->outputs[i].stream;
3271 assert(stream_for_buffer[buf] < 0 || stream_for_buffer[buf] == stream);
3272 stream_for_buffer[buf] = stream;
3273 bufmask_for_stream[stream] |= 1 << buf;
3274 }
3275
3276 for (unsigned buffer = 0; buffer < 4; ++buffer) {
3277 if (stream_for_buffer[buffer] == -1)
3278 continue;
3279
3280 assert(so->strides[buffer]);
3281
3282 LLVMValueRef stride_for_buffer =
3283 LLVMConstInt(ctx->ac.i32, so->strides[buffer], false);
3284 prim_stride_dw[buffer] =
3285 LLVMBuildMul(builder, stride_for_buffer,
3286 nggso->num_vertices, "");
3287 prim_stride_dw_vgpr = ac_build_writelane(
3288 &ctx->ac, prim_stride_dw_vgpr, prim_stride_dw[buffer],
3289 LLVMConstInt(ctx->ac.i32, buffer, false));
3290
3291 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, buffer, false);
3292 so_buffer[buffer] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr,
3293 offset);
3294 }
3295
3296 cond = LLVMBuildICmp(builder, LLVMIntEQ, get_wave_id_in_tg(ctx), ctx->ac.i32_0, "");
3297 ac_build_ifcc(&ctx->ac, cond, 5200);
3298 {
3299 LLVMTypeRef gdsptr = LLVMPointerType(ctx->ac.i32, AC_ADDR_SPACE_GDS);
3300 LLVMValueRef gdsbase = LLVMBuildIntToPtr(builder, ctx->ac.i32_0, gdsptr, "");
3301
3302 /* Advance the streamout offsets in GDS. */
3303 LLVMValueRef offsets_vgpr = ac_build_alloca_undef(&ctx->ac, ctx->ac.i32, "");
3304 LLVMValueRef generated_by_stream_vgpr = ac_build_alloca_undef(&ctx->ac, ctx->ac.i32, "");
3305
3306 cond = LLVMBuildICmp(builder, LLVMIntULT, ac_get_thread_id(&ctx->ac), i32_4, "");
3307 ac_build_ifcc(&ctx->ac, cond, 5210);
3308 {
3309 /* Fetch the number of generated primitives and store
3310 * it in GDS for later use.
3311 */
3312 if (isgs) {
3313 tmp = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tid);
3314 tmp = LLVMBuildLoad(builder, tmp, "");
3315 } else {
3316 tmp = ac_build_writelane(&ctx->ac, ctx->ac.i32_0,
3317 ngg_get_prim_cnt(ctx), ctx->ac.i32_0);
3318 }
3319 LLVMBuildStore(builder, tmp, generated_by_stream_vgpr);
3320
3321 unsigned swizzle[4];
3322 int unused_stream = -1;
3323 for (unsigned stream = 0; stream < 4; ++stream) {
3324 if (!ctx->shader_info->gs.num_stream_output_components[stream]) {
3325 unused_stream = stream;
3326 break;
3327 }
3328 }
3329 for (unsigned buffer = 0; buffer < 4; ++buffer) {
3330 if (stream_for_buffer[buffer] >= 0) {
3331 swizzle[buffer] = stream_for_buffer[buffer];
3332 } else {
3333 assert(unused_stream >= 0);
3334 swizzle[buffer] = unused_stream;
3335 }
3336 }
3337
3338 tmp = ac_build_quad_swizzle(&ctx->ac, tmp,
3339 swizzle[0], swizzle[1], swizzle[2], swizzle[3]);
3340 tmp = LLVMBuildMul(builder, tmp, prim_stride_dw_vgpr, "");
3341
3342 LLVMValueRef args[] = {
3343 LLVMBuildIntToPtr(builder, ngg_get_ordered_id(ctx), gdsptr, ""),
3344 tmp,
3345 ctx->ac.i32_0, // ordering
3346 ctx->ac.i32_0, // scope
3347 ctx->ac.i1false, // isVolatile
3348 LLVMConstInt(ctx->ac.i32, 4 << 24, false), // OA index
3349 ctx->ac.i1true, // wave release
3350 ctx->ac.i1true, // wave done
3351 };
3352
3353 tmp = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.ds.ordered.add",
3354 ctx->ac.i32, args, ARRAY_SIZE(args), 0);
3355
3356 /* Keep offsets in a VGPR for quick retrieval via readlane by
3357 * the first wave for bounds checking, and also store in LDS
3358 * for retrieval by all waves later. */
3359 LLVMBuildStore(builder, tmp, offsets_vgpr);
3360
3361 tmp2 = LLVMBuildAdd(builder, ac_get_thread_id(&ctx->ac),
3362 scratch_offset_basev, "");
3363 tmp2 = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tmp2);
3364 LLVMBuildStore(builder, tmp, tmp2);
3365 }
3366 ac_build_endif(&ctx->ac, 5210);
3367
3368 /* Determine the max emit per buffer. This is done via the SALU, in part
3369 * because LLVM can't generate divide-by-multiply if we try to do this
3370 * via VALU with one lane per buffer.
3371 */
3372 LLVMValueRef max_emit[4] = {};
3373 for (unsigned buffer = 0; buffer < 4; ++buffer) {
3374 if (stream_for_buffer[buffer] == -1)
3375 continue;
3376
3377 /* Compute the streamout buffer size in DWORD. */
3378 LLVMValueRef bufsize_dw =
3379 LLVMBuildLShr(builder,
3380 LLVMBuildExtractElement(builder, so_buffer[buffer], i32_2, ""),
3381 i32_2, "");
3382
3383 /* Load the streamout buffer offset from GDS. */
3384 tmp = LLVMBuildLoad(builder, offsets_vgpr, "");
3385 LLVMValueRef offset_dw =
3386 ac_build_readlane(&ctx->ac, tmp,
3387 LLVMConstInt(ctx->ac.i32, buffer, false));
3388
3389 /* Compute the remaining size to emit. */
3390 LLVMValueRef remaining_dw =
3391 LLVMBuildSub(builder, bufsize_dw, offset_dw, "");
3392 tmp = LLVMBuildUDiv(builder, remaining_dw,
3393 prim_stride_dw[buffer], "");
3394
3395 cond = LLVMBuildICmp(builder, LLVMIntULT,
3396 bufsize_dw, offset_dw, "");
3397 max_emit[buffer] = LLVMBuildSelect(builder, cond,
3398 ctx->ac.i32_0, tmp, "");
3399 }
3400
3401 /* Determine the number of emitted primitives per stream and fixup the
3402 * GDS counter if necessary.
3403 *
3404 * This is complicated by the fact that a single stream can emit to
3405 * multiple buffers (but luckily not vice versa).
3406 */
3407 LLVMValueRef emit_vgpr = ctx->ac.i32_0;
3408
3409 for (unsigned stream = 0; stream < 4; ++stream) {
3410 if (!ctx->shader_info->gs.num_stream_output_components[stream])
3411 continue;
3412
3413 /* Load the number of generated primitives from GDS and
3414 * determine that number for the given stream.
3415 */
3416 tmp = LLVMBuildLoad(builder, generated_by_stream_vgpr, "");
3417 LLVMValueRef generated =
3418 ac_build_readlane(&ctx->ac, tmp,
3419 LLVMConstInt(ctx->ac.i32, stream, false));
3420
3421
3422 /* Compute the number of emitted primitives. */
3423 LLVMValueRef emit = generated;
3424 for (unsigned buffer = 0; buffer < 4; ++buffer) {
3425 if (stream_for_buffer[buffer] == stream)
3426 emit = ac_build_umin(&ctx->ac, emit, max_emit[buffer]);
3427 }
3428
3429 /* Store the number of emitted primitives for that
3430 * stream.
3431 */
3432 emit_vgpr = ac_build_writelane(&ctx->ac, emit_vgpr, emit,
3433 LLVMConstInt(ctx->ac.i32, stream, false));
3434
3435 /* Fixup the offset using a plain GDS atomic if we overflowed. */
3436 cond = LLVMBuildICmp(builder, LLVMIntULT, emit, generated, "");
3437 ac_build_ifcc(&ctx->ac, cond, 5221); /* scalar branch */
3438 tmp = LLVMBuildLShr(builder,
3439 LLVMConstInt(ctx->ac.i32, bufmask_for_stream[stream], false),
3440 ac_get_thread_id(&ctx->ac), "");
3441 tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3442 ac_build_ifcc(&ctx->ac, tmp, 5222);
3443 {
3444 tmp = LLVMBuildSub(builder, generated, emit, "");
3445 tmp = LLVMBuildMul(builder, tmp, prim_stride_dw_vgpr, "");
3446 tmp2 = LLVMBuildGEP(builder, gdsbase, &tid, 1, "");
3447 LLVMBuildAtomicRMW(builder, LLVMAtomicRMWBinOpSub, tmp2, tmp,
3448 LLVMAtomicOrderingMonotonic, false);
3449 }
3450 ac_build_endif(&ctx->ac, 5222);
3451 ac_build_endif(&ctx->ac, 5221);
3452 }
3453
3454 /* Store the number of emitted primitives to LDS for later use. */
3455 cond = LLVMBuildICmp(builder, LLVMIntULT, ac_get_thread_id(&ctx->ac), i32_4, "");
3456 ac_build_ifcc(&ctx->ac, cond, 5225);
3457 {
3458 tmp = LLVMBuildAdd(builder, ac_get_thread_id(&ctx->ac),
3459 scratch_emit_basev, "");
3460 tmp = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tmp);
3461 LLVMBuildStore(builder, emit_vgpr, tmp);
3462 }
3463 ac_build_endif(&ctx->ac, 5225);
3464 }
3465 ac_build_endif(&ctx->ac, 5200);
3466
3467 /* Determine the workgroup-relative per-thread / primitive offset into
3468 * the streamout buffers */
3469 struct ac_wg_scan primemit_scan[4] = {};
3470
3471 if (isgs) {
3472 for (unsigned stream = 0; stream < 4; ++stream) {
3473 if (!ctx->shader_info->gs.num_stream_output_components[stream])
3474 continue;
3475
3476 primemit_scan[stream].enable_exclusive = true;
3477 primemit_scan[stream].op = nir_op_iadd;
3478 primemit_scan[stream].src = nggso->prim_enable[stream];
3479 primemit_scan[stream].scratch =
3480 ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch,
3481 LLVMConstInt(ctx->ac.i32, 12 + 8 * stream, false));
3482 primemit_scan[stream].waveidx = get_wave_id_in_tg(ctx);
3483 primemit_scan[stream].numwaves = get_tgsize(ctx);
3484 primemit_scan[stream].maxwaves = 8;
3485 ac_build_wg_scan_top(&ctx->ac, &primemit_scan[stream]);
3486 }
3487 }
3488
3489 ac_build_s_barrier(&ctx->ac);
3490
3491 /* Fetch the per-buffer offsets and per-stream emit counts in all waves. */
3492 LLVMValueRef wgoffset_dw[4] = {};
3493
3494 {
3495 LLVMValueRef scratch_vgpr;
3496
3497 tmp = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, ac_get_thread_id(&ctx->ac));
3498 scratch_vgpr = LLVMBuildLoad(builder, tmp, "");
3499
3500 for (unsigned buffer = 0; buffer < 4; ++buffer) {
3501 if (stream_for_buffer[buffer] >= 0) {
3502 wgoffset_dw[buffer] = ac_build_readlane(
3503 &ctx->ac, scratch_vgpr,
3504 LLVMConstInt(ctx->ac.i32, scratch_offset_base + buffer, false));
3505 }
3506 }
3507
3508 for (unsigned stream = 0; stream < 4; ++stream) {
3509 if (ctx->shader_info->gs.num_stream_output_components[stream]) {
3510 nggso->emit[stream] = ac_build_readlane(
3511 &ctx->ac, scratch_vgpr,
3512 LLVMConstInt(ctx->ac.i32, scratch_emit_base + stream, false));
3513 }
3514 }
3515 }
3516
3517 /* Write out primitive data */
3518 for (unsigned stream = 0; stream < 4; ++stream) {
3519 if (!ctx->shader_info->gs.num_stream_output_components[stream])
3520 continue;
3521
3522 if (isgs) {
3523 ac_build_wg_scan_bottom(&ctx->ac, &primemit_scan[stream]);
3524 } else {
3525 primemit_scan[stream].result_exclusive = tid;
3526 }
3527
3528 cond = LLVMBuildICmp(builder, LLVMIntULT,
3529 primemit_scan[stream].result_exclusive,
3530 nggso->emit[stream], "");
3531 cond = LLVMBuildAnd(builder, cond, nggso->prim_enable[stream], "");
3532 ac_build_ifcc(&ctx->ac, cond, 5240);
3533 {
3534 LLVMValueRef offset_vtx =
3535 LLVMBuildMul(builder, primemit_scan[stream].result_exclusive,
3536 nggso->num_vertices, "");
3537
3538 for (unsigned i = 0; i < max_num_vertices; ++i) {
3539 cond = LLVMBuildICmp(builder, LLVMIntULT,
3540 LLVMConstInt(ctx->ac.i32, i, false),
3541 nggso->num_vertices, "");
3542 ac_build_ifcc(&ctx->ac, cond, 5241);
3543 build_streamout_vertex(ctx, so_buffer, wgoffset_dw,
3544 stream, offset_vtx, nggso->vertices[i]);
3545 ac_build_endif(&ctx->ac, 5241);
3546 offset_vtx = LLVMBuildAdd(builder, offset_vtx, ctx->ac.i32_1, "");
3547 }
3548 }
3549 ac_build_endif(&ctx->ac, 5240);
3550 }
3551 }
3552
3553 static unsigned ngg_nogs_vertex_size(struct radv_shader_context *ctx)
3554 {
3555 unsigned lds_vertex_size = 0;
3556
3557 if (ctx->shader_info->so.num_outputs)
3558 lds_vertex_size = 4 * ctx->shader_info->so.num_outputs + 1;
3559
3560 return lds_vertex_size;
3561 }
3562
3563 /**
3564 * Returns an `[N x i32] addrspace(LDS)*` pointing at contiguous LDS storage
3565 * for the vertex outputs.
3566 */
3567 static LLVMValueRef ngg_nogs_vertex_ptr(struct radv_shader_context *ctx,
3568 LLVMValueRef vtxid)
3569 {
3570 /* The extra dword is used to avoid LDS bank conflicts. */
3571 unsigned vertex_size = ngg_nogs_vertex_size(ctx);
3572 LLVMTypeRef ai32 = LLVMArrayType(ctx->ac.i32, vertex_size);
3573 LLVMTypeRef pai32 = LLVMPointerType(ai32, AC_ADDR_SPACE_LDS);
3574 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, ctx->esgs_ring, pai32, "");
3575 return LLVMBuildGEP(ctx->ac.builder, tmp, &vtxid, 1, "");
3576 }
3577
3578 static void
3579 handle_ngg_outputs_post_1(struct radv_shader_context *ctx)
3580 {
3581 struct radv_streamout_info *so = &ctx->shader_info->so;
3582 LLVMBuilderRef builder = ctx->ac.builder;
3583 LLVMValueRef vertex_ptr = NULL;
3584 LLVMValueRef tmp, tmp2;
3585
3586 assert((ctx->stage == MESA_SHADER_VERTEX ||
3587 ctx->stage == MESA_SHADER_TESS_EVAL) && !ctx->is_gs_copy_shader);
3588
3589 if (!ctx->shader_info->so.num_outputs)
3590 return;
3591
3592 vertex_ptr = ngg_nogs_vertex_ptr(ctx, get_thread_id_in_tg(ctx));
3593
3594 for (unsigned i = 0; i < so->num_outputs; ++i) {
3595 struct radv_stream_output *output =
3596 &ctx->shader_info->so.outputs[i];
3597
3598 unsigned loc = output->location;
3599
3600 for (unsigned comp = 0; comp < 4; comp++) {
3601 if (!(output->component_mask & (1 << comp)))
3602 continue;
3603
3604 tmp = ac_build_gep0(&ctx->ac, vertex_ptr,
3605 LLVMConstInt(ctx->ac.i32, 4 * i + comp, false));
3606 tmp2 = LLVMBuildLoad(builder,
3607 ctx->abi.outputs[4 * loc + comp], "");
3608 tmp2 = ac_to_integer(&ctx->ac, tmp2);
3609 LLVMBuildStore(builder, tmp2, tmp);
3610 }
3611 }
3612 }
3613
3614 static void
3615 handle_ngg_outputs_post_2(struct radv_shader_context *ctx)
3616 {
3617 LLVMBuilderRef builder = ctx->ac.builder;
3618 LLVMValueRef tmp;
3619
3620 assert((ctx->stage == MESA_SHADER_VERTEX ||
3621 ctx->stage == MESA_SHADER_TESS_EVAL) && !ctx->is_gs_copy_shader);
3622
3623 LLVMValueRef prims_in_wave = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 8, 8);
3624 LLVMValueRef vtx_in_wave = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 0, 8);
3625 LLVMValueRef is_gs_thread = LLVMBuildICmp(builder, LLVMIntULT,
3626 ac_get_thread_id(&ctx->ac), prims_in_wave, "");
3627 LLVMValueRef is_es_thread = LLVMBuildICmp(builder, LLVMIntULT,
3628 ac_get_thread_id(&ctx->ac), vtx_in_wave, "");
3629 LLVMValueRef vtxindex[] = {
3630 ac_unpack_param(&ctx->ac, ctx->gs_vtx_offset[0], 0, 16),
3631 ac_unpack_param(&ctx->ac, ctx->gs_vtx_offset[0], 16, 16),
3632 ac_unpack_param(&ctx->ac, ctx->gs_vtx_offset[2], 0, 16),
3633 };
3634
3635 /* Determine the number of vertices per primitive. */
3636 unsigned num_vertices;
3637 LLVMValueRef num_vertices_val;
3638
3639 if (ctx->stage == MESA_SHADER_VERTEX) {
3640 num_vertices_val = LLVMConstInt(ctx->ac.i32, 1, false);
3641 num_vertices = 3; /* TODO: optimize for points & lines */
3642 } else {
3643 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
3644
3645 if (ctx->shader->info.tess.point_mode)
3646 num_vertices = 1;
3647 else if (ctx->shader->info.tess.primitive_mode == GL_ISOLINES)
3648 num_vertices = 2;
3649 else
3650 num_vertices = 3;
3651
3652 num_vertices_val = LLVMConstInt(ctx->ac.i32, num_vertices, false);
3653 }
3654
3655 /* Streamout */
3656 if (ctx->shader_info->so.num_outputs) {
3657 struct ngg_streamout nggso = {};
3658
3659 nggso.num_vertices = num_vertices_val;
3660 nggso.prim_enable[0] = is_gs_thread;
3661
3662 for (unsigned i = 0; i < num_vertices; ++i)
3663 nggso.vertices[i] = ngg_nogs_vertex_ptr(ctx, vtxindex[i]);
3664
3665 build_streamout(ctx, &nggso);
3666 }
3667
3668 /* Copy Primitive IDs from GS threads to the LDS address corresponding
3669 * to the ES thread of the provoking vertex.
3670 */
3671 if (ctx->stage == MESA_SHADER_VERTEX &&
3672 ctx->options->key.vs_common_out.export_prim_id) {
3673 if (ctx->shader_info->so.num_outputs)
3674 ac_build_s_barrier(&ctx->ac);
3675
3676 ac_build_ifcc(&ctx->ac, is_gs_thread, 5400);
3677 /* Extract the PROVOKING_VTX_INDEX field. */
3678 LLVMValueRef provoking_vtx_in_prim =
3679 LLVMConstInt(ctx->ac.i32, 0, false);
3680
3681 /* provoking_vtx_index = vtxindex[provoking_vtx_in_prim]; */
3682 LLVMValueRef indices = ac_build_gather_values(&ctx->ac, vtxindex, 3);
3683 LLVMValueRef provoking_vtx_index =
3684 LLVMBuildExtractElement(builder, indices, provoking_vtx_in_prim, "");
3685
3686 LLVMBuildStore(builder, ctx->abi.gs_prim_id,
3687 ac_build_gep0(&ctx->ac, ctx->esgs_ring, provoking_vtx_index));
3688 ac_build_endif(&ctx->ac, 5400);
3689 }
3690
3691 /* TODO: primitive culling */
3692
3693 build_sendmsg_gs_alloc_req(ctx, ngg_get_vtx_cnt(ctx), ngg_get_prim_cnt(ctx));
3694
3695 /* TODO: streamout queries */
3696 /* Export primitive data to the index buffer. Format is:
3697 * - bits 0..8: index 0
3698 * - bit 9: edge flag 0
3699 * - bits 10..18: index 1
3700 * - bit 19: edge flag 1
3701 * - bits 20..28: index 2
3702 * - bit 29: edge flag 2
3703 * - bit 31: null primitive (skip)
3704 *
3705 * For the first version, we will always build up all three indices
3706 * independent of the primitive type. The additional garbage data
3707 * shouldn't hurt.
3708 *
3709 * TODO: culling depends on the primitive type, so can have some
3710 * interaction here.
3711 */
3712 ac_build_ifcc(&ctx->ac, is_gs_thread, 6001);
3713 {
3714 struct ngg_prim prim = {};
3715
3716 prim.num_vertices = num_vertices;
3717 prim.isnull = ctx->ac.i1false;
3718 memcpy(prim.index, vtxindex, sizeof(vtxindex[0]) * 3);
3719
3720 for (unsigned i = 0; i < num_vertices; ++i) {
3721 tmp = LLVMBuildLShr(builder, ctx->abi.gs_invocation_id,
3722 LLVMConstInt(ctx->ac.i32, 8 + i, false), "");
3723 prim.edgeflag[i] = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3724 }
3725
3726 build_export_prim(ctx, &prim);
3727 }
3728 ac_build_endif(&ctx->ac, 6001);
3729
3730 /* Export per-vertex data (positions and parameters). */
3731 ac_build_ifcc(&ctx->ac, is_es_thread, 6002);
3732 {
3733 struct radv_vs_output_info *outinfo =
3734 ctx->stage == MESA_SHADER_TESS_EVAL ? &ctx->shader_info->tes.outinfo : &ctx->shader_info->vs.outinfo;
3735
3736 /* Exporting the primitive ID is handled below. */
3737 /* TODO: use the new VS export path */
3738 handle_vs_outputs_post(ctx, false,
3739 ctx->options->key.vs_common_out.export_clip_dists,
3740 outinfo);
3741
3742 if (ctx->options->key.vs_common_out.export_prim_id) {
3743 unsigned param_count = outinfo->param_exports;
3744 LLVMValueRef values[4];
3745
3746 if (ctx->stage == MESA_SHADER_VERTEX) {
3747 /* Wait for GS stores to finish. */
3748 ac_build_s_barrier(&ctx->ac);
3749
3750 tmp = ac_build_gep0(&ctx->ac, ctx->esgs_ring,
3751 get_thread_id_in_tg(ctx));
3752 values[0] = LLVMBuildLoad(builder, tmp, "");
3753 } else {
3754 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
3755 values[0] = ctx->abi.tes_patch_id;
3756 }
3757
3758 values[0] = ac_to_float(&ctx->ac, values[0]);
3759 for (unsigned j = 1; j < 4; j++)
3760 values[j] = ctx->ac.f32_0;
3761
3762 radv_export_param(ctx, param_count, values, 0x1);
3763
3764 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
3765 outinfo->param_exports = param_count;
3766 }
3767 }
3768 ac_build_endif(&ctx->ac, 6002);
3769 }
3770
3771 static void gfx10_ngg_gs_emit_prologue(struct radv_shader_context *ctx)
3772 {
3773 /* Zero out the part of LDS scratch that is used to accumulate the
3774 * per-stream generated primitive count.
3775 */
3776 LLVMBuilderRef builder = ctx->ac.builder;
3777 LLVMValueRef scratchptr = ctx->gs_ngg_scratch;
3778 LLVMValueRef tid = get_thread_id_in_tg(ctx);
3779 LLVMBasicBlockRef merge_block;
3780 LLVMValueRef cond;
3781
3782 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
3783 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
3784 merge_block = LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
3785
3786 cond = LLVMBuildICmp(builder, LLVMIntULT, tid, LLVMConstInt(ctx->ac.i32, 4, false), "");
3787 LLVMBuildCondBr(ctx->ac.builder, cond, then_block, merge_block);
3788 LLVMPositionBuilderAtEnd(ctx->ac.builder, then_block);
3789
3790 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, scratchptr, tid);
3791 LLVMBuildStore(builder, ctx->ac.i32_0, ptr);
3792
3793 LLVMBuildBr(ctx->ac.builder, merge_block);
3794 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
3795
3796 ac_build_s_barrier(&ctx->ac);
3797 }
3798
3799 static void gfx10_ngg_gs_emit_epilogue_1(struct radv_shader_context *ctx)
3800 {
3801 LLVMBuilderRef builder = ctx->ac.builder;
3802 LLVMValueRef i8_0 = LLVMConstInt(ctx->ac.i8, 0, false);
3803 LLVMValueRef tmp;
3804
3805 /* Zero out remaining (non-emitted) primitive flags.
3806 *
3807 * Note: Alternatively, we could pass the relevant gs_next_vertex to
3808 * the emit threads via LDS. This is likely worse in the expected
3809 * typical case where each GS thread emits the full set of
3810 * vertices.
3811 */
3812 for (unsigned stream = 0; stream < 4; ++stream) {
3813 unsigned num_components;
3814
3815 num_components =
3816 ctx->shader_info->gs.num_stream_output_components[stream];
3817 if (!num_components)
3818 continue;
3819
3820 const LLVMValueRef gsthread = get_thread_id_in_tg(ctx);
3821
3822 ac_build_bgnloop(&ctx->ac, 5100);
3823
3824 const LLVMValueRef vertexidx =
3825 LLVMBuildLoad(builder, ctx->gs_next_vertex[stream], "");
3826 tmp = LLVMBuildICmp(builder, LLVMIntUGE, vertexidx,
3827 LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false), "");
3828 ac_build_ifcc(&ctx->ac, tmp, 5101);
3829 ac_build_break(&ctx->ac);
3830 ac_build_endif(&ctx->ac, 5101);
3831
3832 tmp = LLVMBuildAdd(builder, vertexidx, ctx->ac.i32_1, "");
3833 LLVMBuildStore(builder, tmp, ctx->gs_next_vertex[stream]);
3834
3835 tmp = ngg_gs_emit_vertex_ptr(ctx, gsthread, vertexidx);
3836 LLVMValueRef gep_idx[3] = {
3837 ctx->ac.i32_0, /* implied C-style array */
3838 ctx->ac.i32_1, /* second entry of struct */
3839 LLVMConstInt(ctx->ac.i32, stream, false),
3840 };
3841 tmp = LLVMBuildGEP(builder, tmp, gep_idx, 3, "");
3842 LLVMBuildStore(builder, i8_0, tmp);
3843
3844 ac_build_endloop(&ctx->ac, 5100);
3845 }
3846
3847 /* Accumulate generated primitives counts across the entire threadgroup. */
3848 for (unsigned stream = 0; stream < 4; ++stream) {
3849 unsigned num_components;
3850
3851 num_components =
3852 ctx->shader_info->gs.num_stream_output_components[stream];
3853 if (!num_components)
3854 continue;
3855
3856 LLVMValueRef numprims =
3857 LLVMBuildLoad(builder, ctx->gs_generated_prims[stream], "");
3858 numprims = ac_build_reduce(&ctx->ac, numprims, nir_op_iadd, ctx->ac.wave_size);
3859
3860 tmp = LLVMBuildICmp(builder, LLVMIntEQ, ac_get_thread_id(&ctx->ac), ctx->ac.i32_0, "");
3861 ac_build_ifcc(&ctx->ac, tmp, 5105);
3862 {
3863 LLVMBuildAtomicRMW(builder, LLVMAtomicRMWBinOpAdd,
3864 ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch,
3865 LLVMConstInt(ctx->ac.i32, stream, false)),
3866 numprims, LLVMAtomicOrderingMonotonic, false);
3867 }
3868 ac_build_endif(&ctx->ac, 5105);
3869 }
3870 }
3871
3872 static void gfx10_ngg_gs_emit_epilogue_2(struct radv_shader_context *ctx)
3873 {
3874 const unsigned verts_per_prim = si_conv_gl_prim_to_vertices(ctx->shader->info.gs.output_primitive);
3875 LLVMBuilderRef builder = ctx->ac.builder;
3876 LLVMValueRef tmp, tmp2;
3877
3878 ac_build_s_barrier(&ctx->ac);
3879
3880 const LLVMValueRef tid = get_thread_id_in_tg(ctx);
3881 LLVMValueRef num_emit_threads = ngg_get_prim_cnt(ctx);
3882
3883 /* Streamout */
3884 if (ctx->shader_info->so.num_outputs) {
3885 struct ngg_streamout nggso = {};
3886
3887 nggso.num_vertices = LLVMConstInt(ctx->ac.i32, verts_per_prim, false);
3888
3889 LLVMValueRef vertexptr = ngg_gs_vertex_ptr(ctx, tid);
3890 for (unsigned stream = 0; stream < 4; ++stream) {
3891 if (!ctx->shader_info->gs.num_stream_output_components[stream])
3892 continue;
3893
3894 LLVMValueRef gep_idx[3] = {
3895 ctx->ac.i32_0, /* implicit C-style array */
3896 ctx->ac.i32_1, /* second value of struct */
3897 LLVMConstInt(ctx->ac.i32, stream, false),
3898 };
3899 tmp = LLVMBuildGEP(builder, vertexptr, gep_idx, 3, "");
3900 tmp = LLVMBuildLoad(builder, tmp, "");
3901 tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3902 tmp2 = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
3903 nggso.prim_enable[stream] = LLVMBuildAnd(builder, tmp, tmp2, "");
3904 }
3905
3906 for (unsigned i = 0; i < verts_per_prim; ++i) {
3907 tmp = LLVMBuildSub(builder, tid,
3908 LLVMConstInt(ctx->ac.i32, verts_per_prim - i - 1, false), "");
3909 tmp = ngg_gs_vertex_ptr(ctx, tmp);
3910 nggso.vertices[i] = ac_build_gep0(&ctx->ac, tmp, ctx->ac.i32_0);
3911 }
3912
3913 build_streamout(ctx, &nggso);
3914 }
3915
3916 /* TODO: culling */
3917
3918 /* Determine vertex liveness. */
3919 LLVMValueRef vertliveptr = ac_build_alloca(&ctx->ac, ctx->ac.i1, "vertexlive");
3920
3921 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
3922 ac_build_ifcc(&ctx->ac, tmp, 5120);
3923 {
3924 for (unsigned i = 0; i < verts_per_prim; ++i) {
3925 const LLVMValueRef primidx =
3926 LLVMBuildAdd(builder, tid,
3927 LLVMConstInt(ctx->ac.i32, i, false), "");
3928
3929 if (i > 0) {
3930 tmp = LLVMBuildICmp(builder, LLVMIntULT, primidx, num_emit_threads, "");
3931 ac_build_ifcc(&ctx->ac, tmp, 5121 + i);
3932 }
3933
3934 /* Load primitive liveness */
3935 tmp = ngg_gs_vertex_ptr(ctx, primidx);
3936 LLVMValueRef gep_idx[3] = {
3937 ctx->ac.i32_0, /* implicit C-style array */
3938 ctx->ac.i32_1, /* second value of struct */
3939 ctx->ac.i32_0, /* stream 0 */
3940 };
3941 tmp = LLVMBuildGEP(builder, tmp, gep_idx, 3, "");
3942 tmp = LLVMBuildLoad(builder, tmp, "");
3943 const LLVMValueRef primlive =
3944 LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3945
3946 tmp = LLVMBuildLoad(builder, vertliveptr, "");
3947 tmp = LLVMBuildOr(builder, tmp, primlive, ""),
3948 LLVMBuildStore(builder, tmp, vertliveptr);
3949
3950 if (i > 0)
3951 ac_build_endif(&ctx->ac, 5121 + i);
3952 }
3953 }
3954 ac_build_endif(&ctx->ac, 5120);
3955
3956 /* Inclusive scan addition across the current wave. */
3957 LLVMValueRef vertlive = LLVMBuildLoad(builder, vertliveptr, "");
3958 struct ac_wg_scan vertlive_scan = {};
3959 vertlive_scan.op = nir_op_iadd;
3960 vertlive_scan.enable_reduce = true;
3961 vertlive_scan.enable_exclusive = true;
3962 vertlive_scan.src = vertlive;
3963 vertlive_scan.scratch = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, ctx->ac.i32_0);
3964 vertlive_scan.waveidx = get_wave_id_in_tg(ctx);
3965 vertlive_scan.numwaves = get_tgsize(ctx);
3966 vertlive_scan.maxwaves = 8;
3967
3968 ac_build_wg_scan(&ctx->ac, &vertlive_scan);
3969
3970 /* Skip all exports (including index exports) when possible. At least on
3971 * early gfx10 revisions this is also to avoid hangs.
3972 */
3973 LLVMValueRef have_exports =
3974 LLVMBuildICmp(builder, LLVMIntNE, vertlive_scan.result_reduce, ctx->ac.i32_0, "");
3975 num_emit_threads =
3976 LLVMBuildSelect(builder, have_exports, num_emit_threads, ctx->ac.i32_0, "");
3977
3978 /* Allocate export space. Send this message as early as possible, to
3979 * hide the latency of the SQ <-> SPI roundtrip.
3980 *
3981 * Note: We could consider compacting primitives for export as well.
3982 * PA processes 1 non-null prim / clock, but it fetches 4 DW of
3983 * prim data per clock and skips null primitives at no additional
3984 * cost. So compacting primitives can only be beneficial when
3985 * there are 4 or more contiguous null primitives in the export
3986 * (in the common case of single-dword prim exports).
3987 */
3988 build_sendmsg_gs_alloc_req(ctx, vertlive_scan.result_reduce, num_emit_threads);
3989
3990 /* Setup the reverse vertex compaction permutation. We re-use stream 1
3991 * of the primitive liveness flags, relying on the fact that each
3992 * threadgroup can have at most 256 threads. */
3993 ac_build_ifcc(&ctx->ac, vertlive, 5130);
3994 {
3995 tmp = ngg_gs_vertex_ptr(ctx, vertlive_scan.result_exclusive);
3996 LLVMValueRef gep_idx[3] = {
3997 ctx->ac.i32_0, /* implicit C-style array */
3998 ctx->ac.i32_1, /* second value of struct */
3999 ctx->ac.i32_1, /* stream 1 */
4000 };
4001 tmp = LLVMBuildGEP(builder, tmp, gep_idx, 3, "");
4002 tmp2 = LLVMBuildTrunc(builder, tid, ctx->ac.i8, "");
4003 LLVMBuildStore(builder, tmp2, tmp);
4004 }
4005 ac_build_endif(&ctx->ac, 5130);
4006
4007 ac_build_s_barrier(&ctx->ac);
4008
4009 /* Export primitive data */
4010 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
4011 ac_build_ifcc(&ctx->ac, tmp, 5140);
4012 {
4013 struct ngg_prim prim = {};
4014 prim.num_vertices = verts_per_prim;
4015
4016 tmp = ngg_gs_vertex_ptr(ctx, tid);
4017 LLVMValueRef gep_idx[3] = {
4018 ctx->ac.i32_0, /* implicit C-style array */
4019 ctx->ac.i32_1, /* second value of struct */
4020 ctx->ac.i32_0, /* primflag */
4021 };
4022 tmp = LLVMBuildGEP(builder, tmp, gep_idx, 3, "");
4023 tmp = LLVMBuildLoad(builder, tmp, "");
4024 prim.isnull = LLVMBuildICmp(builder, LLVMIntEQ, tmp,
4025 LLVMConstInt(ctx->ac.i8, 0, false), "");
4026
4027 for (unsigned i = 0; i < verts_per_prim; ++i) {
4028 prim.index[i] = LLVMBuildSub(builder, vertlive_scan.result_exclusive,
4029 LLVMConstInt(ctx->ac.i32, verts_per_prim - i - 1, false), "");
4030 prim.edgeflag[i] = ctx->ac.i1false;
4031 }
4032
4033 build_export_prim(ctx, &prim);
4034 }
4035 ac_build_endif(&ctx->ac, 5140);
4036
4037 /* Export position and parameter data */
4038 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, vertlive_scan.result_reduce, "");
4039 ac_build_ifcc(&ctx->ac, tmp, 5145);
4040 {
4041 struct radv_vs_output_info *outinfo = &ctx->shader_info->vs.outinfo;
4042 bool export_view_index = ctx->options->key.has_multiview_view_index;
4043 struct radv_shader_output_values *outputs;
4044 unsigned noutput = 0;
4045
4046 /* Allocate a temporary array for the output values. */
4047 unsigned num_outputs = util_bitcount64(ctx->output_mask) + export_view_index;
4048 outputs = calloc(num_outputs, sizeof(outputs[0]));
4049
4050 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
4051 sizeof(outinfo->vs_output_param_offset));
4052 outinfo->pos_exports = 0;
4053
4054 tmp = ngg_gs_vertex_ptr(ctx, tid);
4055 LLVMValueRef gep_idx[3] = {
4056 ctx->ac.i32_0, /* implicit C-style array */
4057 ctx->ac.i32_1, /* second value of struct */
4058 ctx->ac.i32_1, /* stream 1: source data index */
4059 };
4060 tmp = LLVMBuildGEP(builder, tmp, gep_idx, 3, "");
4061 tmp = LLVMBuildLoad(builder, tmp, "");
4062 tmp = LLVMBuildZExt(builder, tmp, ctx->ac.i32, "");
4063 const LLVMValueRef vertexptr = ngg_gs_vertex_ptr(ctx, tmp);
4064
4065 unsigned out_idx = 0;
4066 gep_idx[1] = ctx->ac.i32_0;
4067 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
4068 unsigned output_usage_mask =
4069 ctx->shader_info->gs.output_usage_mask[i];
4070 int length = util_last_bit(output_usage_mask);
4071
4072 if (!(ctx->output_mask & (1ull << i)))
4073 continue;
4074
4075 outputs[noutput].slot_name = i;
4076 outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
4077 outputs[noutput].usage_mask = output_usage_mask;
4078
4079 for (unsigned j = 0; j < length; j++, out_idx++) {
4080 if (!(output_usage_mask & (1 << j)))
4081 continue;
4082
4083 gep_idx[2] = LLVMConstInt(ctx->ac.i32, out_idx, false);
4084 tmp = LLVMBuildGEP(builder, vertexptr, gep_idx, 3, "");
4085 tmp = LLVMBuildLoad(builder, tmp, "");
4086
4087 LLVMTypeRef type = LLVMGetAllocatedType(ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
4088 if (ac_get_type_size(type) == 2) {
4089 tmp = ac_to_integer(&ctx->ac, tmp);
4090 tmp = LLVMBuildTrunc(ctx->ac.builder, tmp, ctx->ac.i16, "");
4091 }
4092
4093 outputs[noutput].values[j] = ac_to_float(&ctx->ac, tmp);
4094 }
4095
4096 for (unsigned j = length; j < 4; j++)
4097 outputs[noutput].values[j] = LLVMGetUndef(ctx->ac.f32);
4098
4099 noutput++;
4100 }
4101
4102 /* Export ViewIndex. */
4103 if (export_view_index) {
4104 outputs[noutput].slot_name = VARYING_SLOT_LAYER;
4105 outputs[noutput].slot_index = 0;
4106 outputs[noutput].usage_mask = 0x1;
4107 outputs[noutput].values[0] = ac_to_float(&ctx->ac, ctx->abi.view_index);
4108 for (unsigned j = 1; j < 4; j++)
4109 outputs[noutput].values[j] = ctx->ac.f32_0;
4110 noutput++;
4111 }
4112
4113 radv_llvm_export_vs(ctx, outputs, noutput, outinfo,
4114 ctx->options->key.vs_common_out.export_clip_dists);
4115 FREE(outputs);
4116 }
4117 ac_build_endif(&ctx->ac, 5145);
4118 }
4119
4120 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context *ctx,
4121 unsigned stream,
4122 LLVMValueRef *addrs)
4123 {
4124 LLVMBuilderRef builder = ctx->ac.builder;
4125 LLVMValueRef tmp;
4126 const LLVMValueRef vertexidx =
4127 LLVMBuildLoad(builder, ctx->gs_next_vertex[stream], "");
4128
4129 /* If this thread has already emitted the declared maximum number of
4130 * vertices, skip the write: excessive vertex emissions are not
4131 * supposed to have any effect.
4132 */
4133 const LLVMValueRef can_emit =
4134 LLVMBuildICmp(builder, LLVMIntULT, vertexidx,
4135 LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false), "");
4136 ac_build_ifcc(&ctx->ac, can_emit, 9001);
4137
4138 tmp = LLVMBuildAdd(builder, vertexidx, ctx->ac.i32_1, "");
4139 tmp = LLVMBuildSelect(builder, can_emit, tmp, vertexidx, "");
4140 LLVMBuildStore(builder, tmp, ctx->gs_next_vertex[stream]);
4141
4142 const LLVMValueRef vertexptr =
4143 ngg_gs_emit_vertex_ptr(ctx, get_thread_id_in_tg(ctx), vertexidx);
4144 unsigned out_idx = 0;
4145 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
4146 unsigned output_usage_mask =
4147 ctx->shader_info->gs.output_usage_mask[i];
4148 uint8_t output_stream =
4149 ctx->shader_info->gs.output_streams[i];
4150 LLVMValueRef *out_ptr = &addrs[i * 4];
4151 int length = util_last_bit(output_usage_mask);
4152
4153 if (!(ctx->output_mask & (1ull << i)) ||
4154 output_stream != stream)
4155 continue;
4156
4157 for (unsigned j = 0; j < length; j++, out_idx++) {
4158 if (!(output_usage_mask & (1 << j)))
4159 continue;
4160
4161 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
4162 out_ptr[j], "");
4163 LLVMValueRef gep_idx[3] = {
4164 ctx->ac.i32_0, /* implied C-style array */
4165 ctx->ac.i32_0, /* first entry of struct */
4166 LLVMConstInt(ctx->ac.i32, out_idx, false),
4167 };
4168 LLVMValueRef ptr = LLVMBuildGEP(builder, vertexptr, gep_idx, 3, "");
4169
4170 out_val = ac_to_integer(&ctx->ac, out_val);
4171 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
4172
4173 LLVMBuildStore(builder, out_val, ptr);
4174 }
4175 }
4176 assert(out_idx * 4 <= ctx->shader_info->gs.gsvs_vertex_size);
4177
4178 /* Determine and store whether this vertex completed a primitive. */
4179 const LLVMValueRef curverts = LLVMBuildLoad(builder, ctx->gs_curprim_verts[stream], "");
4180
4181 tmp = LLVMConstInt(ctx->ac.i32, si_conv_gl_prim_to_vertices(ctx->shader->info.gs.output_primitive) - 1, false);
4182 const LLVMValueRef iscompleteprim =
4183 LLVMBuildICmp(builder, LLVMIntUGE, curverts, tmp, "");
4184
4185 tmp = LLVMBuildAdd(builder, curverts, ctx->ac.i32_1, "");
4186 LLVMBuildStore(builder, tmp, ctx->gs_curprim_verts[stream]);
4187
4188 LLVMValueRef gep_idx[3] = {
4189 ctx->ac.i32_0, /* implied C-style array */
4190 ctx->ac.i32_1, /* second struct entry */
4191 LLVMConstInt(ctx->ac.i32, stream, false),
4192 };
4193 const LLVMValueRef primflagptr =
4194 LLVMBuildGEP(builder, vertexptr, gep_idx, 3, "");
4195
4196 tmp = LLVMBuildZExt(builder, iscompleteprim, ctx->ac.i8, "");
4197 LLVMBuildStore(builder, tmp, primflagptr);
4198
4199 tmp = LLVMBuildLoad(builder, ctx->gs_generated_prims[stream], "");
4200 tmp = LLVMBuildAdd(builder, tmp, LLVMBuildZExt(builder, iscompleteprim, ctx->ac.i32, ""), "");
4201 LLVMBuildStore(builder, tmp, ctx->gs_generated_prims[stream]);
4202
4203 ac_build_endif(&ctx->ac, 9001);
4204 }
4205
4206 static void
4207 write_tess_factors(struct radv_shader_context *ctx)
4208 {
4209 unsigned stride, outer_comps, inner_comps;
4210 LLVMValueRef invocation_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
4211 LLVMValueRef rel_patch_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
4212 unsigned tess_inner_index = 0, tess_outer_index;
4213 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
4214 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
4215 int i;
4216 ac_emit_barrier(&ctx->ac, ctx->stage);
4217
4218 switch (ctx->options->key.tcs.primitive_mode) {
4219 case GL_ISOLINES:
4220 stride = 2;
4221 outer_comps = 2;
4222 inner_comps = 0;
4223 break;
4224 case GL_TRIANGLES:
4225 stride = 4;
4226 outer_comps = 3;
4227 inner_comps = 1;
4228 break;
4229 case GL_QUADS:
4230 stride = 6;
4231 outer_comps = 4;
4232 inner_comps = 2;
4233 break;
4234 default:
4235 return;
4236 }
4237
4238 ac_build_ifcc(&ctx->ac,
4239 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
4240 invocation_id, ctx->ac.i32_0, ""), 6503);
4241
4242 lds_base = get_tcs_out_current_patch_data_offset(ctx);
4243
4244 if (inner_comps) {
4245 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
4246 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
4247 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
4248 }
4249
4250 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
4251 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
4252 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
4253
4254 for (i = 0; i < 4; i++) {
4255 inner[i] = LLVMGetUndef(ctx->ac.i32);
4256 outer[i] = LLVMGetUndef(ctx->ac.i32);
4257 }
4258
4259 // LINES reversal
4260 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
4261 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
4262 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
4263 ctx->ac.i32_1, "");
4264 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
4265 } else {
4266 for (i = 0; i < outer_comps; i++) {
4267 outer[i] = out[i] =
4268 ac_lds_load(&ctx->ac, lds_outer);
4269 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
4270 ctx->ac.i32_1, "");
4271 }
4272 for (i = 0; i < inner_comps; i++) {
4273 inner[i] = out[outer_comps+i] =
4274 ac_lds_load(&ctx->ac, lds_inner);
4275 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
4276 ctx->ac.i32_1, "");
4277 }
4278 }
4279
4280 /* Convert the outputs to vectors for stores. */
4281 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
4282 vec1 = NULL;
4283
4284 if (stride > 4)
4285 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
4286
4287
4288 buffer = ctx->hs_ring_tess_factor;
4289 tf_base = ctx->tess_factor_offset;
4290 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
4291 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
4292 unsigned tf_offset = 0;
4293
4294 if (ctx->options->chip_class <= GFX8) {
4295 ac_build_ifcc(&ctx->ac,
4296 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
4297 rel_patch_id, ctx->ac.i32_0, ""), 6504);
4298
4299 /* Store the dynamic HS control word. */
4300 ac_build_buffer_store_dword(&ctx->ac, buffer,
4301 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
4302 1, ctx->ac.i32_0, tf_base,
4303 0, ac_glc, false);
4304 tf_offset += 4;
4305
4306 ac_build_endif(&ctx->ac, 6504);
4307 }
4308
4309 /* Store the tessellation factors. */
4310 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
4311 MIN2(stride, 4), byteoffset, tf_base,
4312 tf_offset, ac_glc, false);
4313 if (vec1)
4314 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
4315 stride - 4, byteoffset, tf_base,
4316 16 + tf_offset, ac_glc, false);
4317
4318 //store to offchip for TES to read - only if TES reads them
4319 if (ctx->options->key.tcs.tes_reads_tess_factors) {
4320 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
4321 LLVMValueRef tf_inner_offset;
4322 unsigned param_outer, param_inner;
4323
4324 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
4325 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
4326 LLVMConstInt(ctx->ac.i32, param_outer, 0));
4327
4328 outer_vec = ac_build_gather_values(&ctx->ac, outer,
4329 util_next_power_of_two(outer_comps));
4330
4331 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
4332 outer_comps, tf_outer_offset,
4333 ctx->oc_lds, 0, ac_glc, false);
4334 if (inner_comps) {
4335 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
4336 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
4337 LLVMConstInt(ctx->ac.i32, param_inner, 0));
4338
4339 inner_vec = inner_comps == 1 ? inner[0] :
4340 ac_build_gather_values(&ctx->ac, inner, inner_comps);
4341 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
4342 inner_comps, tf_inner_offset,
4343 ctx->oc_lds, 0, ac_glc, false);
4344 }
4345 }
4346
4347 ac_build_endif(&ctx->ac, 6503);
4348 }
4349
4350 static void
4351 handle_tcs_outputs_post(struct radv_shader_context *ctx)
4352 {
4353 write_tess_factors(ctx);
4354 }
4355
4356 static bool
4357 si_export_mrt_color(struct radv_shader_context *ctx,
4358 LLVMValueRef *color, unsigned index,
4359 struct ac_export_args *args)
4360 {
4361 /* Export */
4362 si_llvm_init_export_args(ctx, color, 0xf,
4363 V_008DFC_SQ_EXP_MRT + index, args);
4364 if (!args->enabled_channels)
4365 return false; /* unnecessary NULL export */
4366
4367 return true;
4368 }
4369
4370 static void
4371 radv_export_mrt_z(struct radv_shader_context *ctx,
4372 LLVMValueRef depth, LLVMValueRef stencil,
4373 LLVMValueRef samplemask)
4374 {
4375 struct ac_export_args args;
4376
4377 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
4378
4379 ac_build_export(&ctx->ac, &args);
4380 }
4381
4382 static void
4383 handle_fs_outputs_post(struct radv_shader_context *ctx)
4384 {
4385 unsigned index = 0;
4386 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
4387 struct ac_export_args color_args[8];
4388
4389 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
4390 LLVMValueRef values[4];
4391
4392 if (!(ctx->output_mask & (1ull << i)))
4393 continue;
4394
4395 if (i < FRAG_RESULT_DATA0)
4396 continue;
4397
4398 for (unsigned j = 0; j < 4; j++)
4399 values[j] = ac_to_float(&ctx->ac,
4400 radv_load_output(ctx, i, j));
4401
4402 bool ret = si_export_mrt_color(ctx, values,
4403 i - FRAG_RESULT_DATA0,
4404 &color_args[index]);
4405 if (ret)
4406 index++;
4407 }
4408
4409 /* Process depth, stencil, samplemask. */
4410 if (ctx->shader_info->ps.writes_z) {
4411 depth = ac_to_float(&ctx->ac,
4412 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
4413 }
4414 if (ctx->shader_info->ps.writes_stencil) {
4415 stencil = ac_to_float(&ctx->ac,
4416 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
4417 }
4418 if (ctx->shader_info->ps.writes_sample_mask) {
4419 samplemask = ac_to_float(&ctx->ac,
4420 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
4421 }
4422
4423 /* Set the DONE bit on last non-null color export only if Z isn't
4424 * exported.
4425 */
4426 if (index > 0 &&
4427 !ctx->shader_info->ps.writes_z &&
4428 !ctx->shader_info->ps.writes_stencil &&
4429 !ctx->shader_info->ps.writes_sample_mask) {
4430 unsigned last = index - 1;
4431
4432 color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */
4433 color_args[last].done = 1; /* DONE bit */
4434 }
4435
4436 /* Export PS outputs. */
4437 for (unsigned i = 0; i < index; i++)
4438 ac_build_export(&ctx->ac, &color_args[i]);
4439
4440 if (depth || stencil || samplemask)
4441 radv_export_mrt_z(ctx, depth, stencil, samplemask);
4442 else if (!index)
4443 ac_build_export_null(&ctx->ac);
4444 }
4445
4446 static void
4447 emit_gs_epilogue(struct radv_shader_context *ctx)
4448 {
4449 if (ctx->options->key.vs_common_out.as_ngg) {
4450 gfx10_ngg_gs_emit_epilogue_1(ctx);
4451 return;
4452 }
4453
4454 if (ctx->ac.chip_class >= GFX10)
4455 LLVMBuildFence(ctx->ac.builder, LLVMAtomicOrderingRelease, false, "");
4456
4457 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
4458 }
4459
4460 static void
4461 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
4462 LLVMValueRef *addrs)
4463 {
4464 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4465
4466 switch (ctx->stage) {
4467 case MESA_SHADER_VERTEX:
4468 if (ctx->options->key.vs_common_out.as_ls)
4469 handle_ls_outputs_post(ctx);
4470 else if (ctx->options->key.vs_common_out.as_es)
4471 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
4472 else if (ctx->options->key.vs_common_out.as_ngg)
4473 handle_ngg_outputs_post_1(ctx);
4474 else
4475 handle_vs_outputs_post(ctx, ctx->options->key.vs_common_out.export_prim_id,
4476 ctx->options->key.vs_common_out.export_clip_dists,
4477 &ctx->shader_info->vs.outinfo);
4478 break;
4479 case MESA_SHADER_FRAGMENT:
4480 handle_fs_outputs_post(ctx);
4481 break;
4482 case MESA_SHADER_GEOMETRY:
4483 emit_gs_epilogue(ctx);
4484 break;
4485 case MESA_SHADER_TESS_CTRL:
4486 handle_tcs_outputs_post(ctx);
4487 break;
4488 case MESA_SHADER_TESS_EVAL:
4489 if (ctx->options->key.vs_common_out.as_es)
4490 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
4491 else if (ctx->options->key.vs_common_out.as_ngg)
4492 handle_ngg_outputs_post_1(ctx);
4493 else
4494 handle_vs_outputs_post(ctx, ctx->options->key.vs_common_out.export_prim_id,
4495 ctx->options->key.vs_common_out.export_clip_dists,
4496 &ctx->shader_info->tes.outinfo);
4497 break;
4498 default:
4499 break;
4500 }
4501 }
4502
4503 static void ac_llvm_finalize_module(struct radv_shader_context *ctx,
4504 LLVMPassManagerRef passmgr,
4505 const struct radv_nir_compiler_options *options)
4506 {
4507 LLVMRunPassManager(passmgr, ctx->ac.module);
4508 LLVMDisposeBuilder(ctx->ac.builder);
4509
4510 ac_llvm_context_dispose(&ctx->ac);
4511 }
4512
4513 static void
4514 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
4515 {
4516 struct radv_vs_output_info *outinfo;
4517
4518 switch (ctx->stage) {
4519 case MESA_SHADER_FRAGMENT:
4520 case MESA_SHADER_COMPUTE:
4521 case MESA_SHADER_TESS_CTRL:
4522 case MESA_SHADER_GEOMETRY:
4523 return;
4524 case MESA_SHADER_VERTEX:
4525 if (ctx->options->key.vs_common_out.as_ls ||
4526 ctx->options->key.vs_common_out.as_es)
4527 return;
4528 outinfo = &ctx->shader_info->vs.outinfo;
4529 break;
4530 case MESA_SHADER_TESS_EVAL:
4531 if (ctx->options->key.vs_common_out.as_es)
4532 return;
4533 outinfo = &ctx->shader_info->tes.outinfo;
4534 break;
4535 default:
4536 unreachable("Unhandled shader type");
4537 }
4538
4539 ac_optimize_vs_outputs(&ctx->ac,
4540 ctx->main_function,
4541 outinfo->vs_output_param_offset,
4542 VARYING_SLOT_MAX,
4543 &outinfo->param_exports);
4544 }
4545
4546 static void
4547 ac_setup_rings(struct radv_shader_context *ctx)
4548 {
4549 if (ctx->options->chip_class <= GFX8 &&
4550 (ctx->stage == MESA_SHADER_GEOMETRY ||
4551 ctx->options->key.vs_common_out.as_es || ctx->options->key.vs_common_out.as_es)) {
4552 unsigned ring = ctx->stage == MESA_SHADER_GEOMETRY ? RING_ESGS_GS
4553 : RING_ESGS_VS;
4554 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, ring, false);
4555
4556 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac,
4557 ctx->ring_offsets,
4558 offset);
4559 }
4560
4561 if (ctx->is_gs_copy_shader) {
4562 ctx->gsvs_ring[0] =
4563 ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets,
4564 LLVMConstInt(ctx->ac.i32,
4565 RING_GSVS_VS, false));
4566 }
4567
4568 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4569 /* The conceptual layout of the GSVS ring is
4570 * v0c0 .. vLv0 v0c1 .. vLc1 ..
4571 * but the real memory layout is swizzled across
4572 * threads:
4573 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
4574 * t16v0c0 ..
4575 * Override the buffer descriptor accordingly.
4576 */
4577 LLVMTypeRef v2i64 = LLVMVectorType(ctx->ac.i64, 2);
4578 uint64_t stream_offset = 0;
4579 unsigned num_records = ctx->ac.wave_size;
4580 LLVMValueRef base_ring;
4581
4582 base_ring =
4583 ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets,
4584 LLVMConstInt(ctx->ac.i32,
4585 RING_GSVS_GS, false));
4586
4587 for (unsigned stream = 0; stream < 4; stream++) {
4588 unsigned num_components, stride;
4589 LLVMValueRef ring, tmp;
4590
4591 num_components =
4592 ctx->shader_info->gs.num_stream_output_components[stream];
4593
4594 if (!num_components)
4595 continue;
4596
4597 stride = 4 * num_components * ctx->shader->info.gs.vertices_out;
4598
4599 /* Limit on the stride field for <= GFX7. */
4600 assert(stride < (1 << 14));
4601
4602 ring = LLVMBuildBitCast(ctx->ac.builder,
4603 base_ring, v2i64, "");
4604 tmp = LLVMBuildExtractElement(ctx->ac.builder,
4605 ring, ctx->ac.i32_0, "");
4606 tmp = LLVMBuildAdd(ctx->ac.builder, tmp,
4607 LLVMConstInt(ctx->ac.i64,
4608 stream_offset, 0), "");
4609 ring = LLVMBuildInsertElement(ctx->ac.builder,
4610 ring, tmp, ctx->ac.i32_0, "");
4611
4612 stream_offset += stride * ctx->ac.wave_size;
4613
4614 ring = LLVMBuildBitCast(ctx->ac.builder, ring,
4615 ctx->ac.v4i32, "");
4616
4617 tmp = LLVMBuildExtractElement(ctx->ac.builder, ring,
4618 ctx->ac.i32_1, "");
4619 tmp = LLVMBuildOr(ctx->ac.builder, tmp,
4620 LLVMConstInt(ctx->ac.i32,
4621 S_008F04_STRIDE(stride), false), "");
4622 ring = LLVMBuildInsertElement(ctx->ac.builder, ring, tmp,
4623 ctx->ac.i32_1, "");
4624
4625 ring = LLVMBuildInsertElement(ctx->ac.builder, ring,
4626 LLVMConstInt(ctx->ac.i32,
4627 num_records, false),
4628 LLVMConstInt(ctx->ac.i32, 2, false), "");
4629
4630 ctx->gsvs_ring[stream] = ring;
4631 }
4632 }
4633
4634 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
4635 ctx->stage == MESA_SHADER_TESS_EVAL) {
4636 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
4637 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
4638 }
4639 }
4640
4641 unsigned
4642 radv_nir_get_max_workgroup_size(enum chip_class chip_class,
4643 gl_shader_stage stage,
4644 const struct nir_shader *nir)
4645 {
4646 const unsigned backup_sizes[] = {chip_class >= GFX9 ? 128 : 64, 1, 1};
4647 return radv_get_max_workgroup_size(chip_class, stage, nir ? nir->info.cs.local_size : backup_sizes);
4648 }
4649
4650 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
4651 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
4652 {
4653 LLVMValueRef count = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 8, 8);
4654 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
4655 ctx->ac.i32_0, "");
4656 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
4657 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
4658 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
4659 }
4660
4661 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
4662 {
4663 for(int i = 5; i >= 0; --i) {
4664 ctx->gs_vtx_offset[i] = ac_unpack_param(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
4665 (i & 1) * 16, 16);
4666 }
4667
4668 ctx->gs_wave_id = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 16, 8);
4669 }
4670
4671 /* Ensure that the esgs ring is declared.
4672 *
4673 * We declare it with 64KB alignment as a hint that the
4674 * pointer value will always be 0.
4675 */
4676 static void declare_esgs_ring(struct radv_shader_context *ctx)
4677 {
4678 if (ctx->esgs_ring)
4679 return;
4680
4681 assert(!LLVMGetNamedGlobal(ctx->ac.module, "esgs_ring"));
4682
4683 ctx->esgs_ring = LLVMAddGlobalInAddressSpace(
4684 ctx->ac.module, LLVMArrayType(ctx->ac.i32, 0),
4685 "esgs_ring",
4686 AC_ADDR_SPACE_LDS);
4687 LLVMSetLinkage(ctx->esgs_ring, LLVMExternalLinkage);
4688 LLVMSetAlignment(ctx->esgs_ring, 64 * 1024);
4689 }
4690
4691 static
4692 LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
4693 struct nir_shader *const *shaders,
4694 int shader_count,
4695 struct radv_shader_info *shader_info,
4696 const struct radv_nir_compiler_options *options)
4697 {
4698 struct radv_shader_context ctx = {0};
4699 unsigned i;
4700 ctx.options = options;
4701 ctx.shader_info = shader_info;
4702
4703 enum ac_float_mode float_mode =
4704 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
4705 AC_FLOAT_MODE_DEFAULT;
4706
4707 ac_llvm_context_init(&ctx.ac, ac_llvm, options->chip_class,
4708 options->family, float_mode, options->wave_size, 64);
4709 ctx.context = ctx.ac.context;
4710
4711 for (i = 0; i < MAX_SETS; i++)
4712 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
4713 for (i = 0; i < AC_UD_MAX_UD; i++)
4714 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
4715
4716 ctx.max_workgroup_size = 0;
4717 for (int i = 0; i < shader_count; ++i) {
4718 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
4719 radv_nir_get_max_workgroup_size(ctx.options->chip_class,
4720 shaders[i]->info.stage,
4721 shaders[i]));
4722 }
4723
4724 if (ctx.ac.chip_class >= GFX10) {
4725 if (is_pre_gs_stage(shaders[0]->info.stage) &&
4726 options->key.vs_common_out.as_ngg) {
4727 ctx.max_workgroup_size = 128;
4728 }
4729 }
4730
4731 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
4732 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
4733
4734 ctx.abi.inputs = &ctx.inputs[0];
4735 ctx.abi.emit_outputs = handle_shader_outputs_post;
4736 ctx.abi.emit_vertex = visit_emit_vertex;
4737 ctx.abi.load_ubo = radv_load_ubo;
4738 ctx.abi.load_ssbo = radv_load_ssbo;
4739 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
4740 ctx.abi.load_resource = radv_load_resource;
4741 ctx.abi.clamp_shadow_reference = false;
4742 ctx.abi.robust_buffer_access = options->robust_buffer_access;
4743
4744 bool is_ngg = is_pre_gs_stage(shaders[0]->info.stage) && ctx.options->key.vs_common_out.as_ngg;
4745 if (shader_count >= 2 || is_ngg)
4746 ac_init_exec_full_mask(&ctx.ac);
4747
4748 if (options->has_ls_vgpr_init_bug &&
4749 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
4750 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
4751
4752 if (shaders[shader_count - 1]->info.stage != MESA_SHADER_GEOMETRY &&
4753 (ctx.options->key.vs_common_out.as_ngg &&
4754 !ctx.options->key.vs_common_out.as_es)) {
4755 /* Unconditionally declare scratch space base for streamout and
4756 * vertex compaction. Whether space is actually allocated is
4757 * determined during linking / PM4 creation.
4758 *
4759 * Add an extra dword per vertex to ensure an odd stride, which
4760 * avoids bank conflicts for SoA accesses.
4761 */
4762 declare_esgs_ring(&ctx);
4763
4764 /* This is really only needed when streamout and / or vertex
4765 * compaction is enabled.
4766 */
4767 LLVMTypeRef asi32 = LLVMArrayType(ctx.ac.i32, 8);
4768 ctx.gs_ngg_scratch = LLVMAddGlobalInAddressSpace(ctx.ac.module,
4769 asi32, "ngg_scratch", AC_ADDR_SPACE_LDS);
4770 LLVMSetInitializer(ctx.gs_ngg_scratch, LLVMGetUndef(asi32));
4771 LLVMSetAlignment(ctx.gs_ngg_scratch, 4);
4772 }
4773
4774 for(int i = 0; i < shader_count; ++i) {
4775 ctx.stage = shaders[i]->info.stage;
4776 ctx.shader = shaders[i];
4777 ctx.output_mask = 0;
4778
4779 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
4780 for (int i = 0; i < 4; i++) {
4781 ctx.gs_next_vertex[i] =
4782 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
4783 }
4784 if (ctx.options->key.vs_common_out.as_ngg) {
4785 for (unsigned i = 0; i < 4; ++i) {
4786 ctx.gs_curprim_verts[i] =
4787 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
4788 ctx.gs_generated_prims[i] =
4789 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
4790 }
4791
4792 unsigned scratch_size = 8;
4793 if (ctx.shader_info->so.num_outputs)
4794 scratch_size = 44;
4795
4796 LLVMTypeRef ai32 = LLVMArrayType(ctx.ac.i32, scratch_size);
4797 ctx.gs_ngg_scratch =
4798 LLVMAddGlobalInAddressSpace(ctx.ac.module,
4799 ai32, "ngg_scratch", AC_ADDR_SPACE_LDS);
4800 LLVMSetInitializer(ctx.gs_ngg_scratch, LLVMGetUndef(ai32));
4801 LLVMSetAlignment(ctx.gs_ngg_scratch, 4);
4802
4803 ctx.gs_ngg_emit = LLVMAddGlobalInAddressSpace(ctx.ac.module,
4804 LLVMArrayType(ctx.ac.i32, 0), "ngg_emit", AC_ADDR_SPACE_LDS);
4805 LLVMSetLinkage(ctx.gs_ngg_emit, LLVMExternalLinkage);
4806 LLVMSetAlignment(ctx.gs_ngg_emit, 4);
4807 }
4808
4809 ctx.abi.load_inputs = load_gs_input;
4810 ctx.abi.emit_primitive = visit_end_primitive;
4811 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
4812 ctx.abi.load_tess_varyings = load_tcs_varyings;
4813 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
4814 ctx.abi.store_tcs_outputs = store_tcs_output;
4815 if (shader_count == 1)
4816 ctx.tcs_num_inputs = ctx.options->key.tcs.num_inputs;
4817 else
4818 ctx.tcs_num_inputs = util_last_bit64(shader_info->vs.ls_outputs_written);
4819 ctx.tcs_num_patches = get_tcs_num_patches(&ctx);
4820 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
4821 ctx.abi.load_tess_varyings = load_tes_input;
4822 ctx.abi.load_tess_coord = load_tess_coord;
4823 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
4824 ctx.tcs_num_patches = ctx.options->key.tes.num_patches;
4825 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
4826 ctx.abi.load_base_vertex = radv_load_base_vertex;
4827 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
4828 ctx.abi.load_sample_position = load_sample_position;
4829 ctx.abi.load_sample_mask_in = load_sample_mask_in;
4830 ctx.abi.emit_kill = radv_emit_kill;
4831 }
4832
4833 if (shaders[i]->info.stage == MESA_SHADER_VERTEX &&
4834 ctx.options->key.vs_common_out.as_ngg &&
4835 ctx.options->key.vs_common_out.export_prim_id) {
4836 declare_esgs_ring(&ctx);
4837 }
4838
4839 bool nested_barrier = false;
4840
4841 if (i) {
4842 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
4843 ctx.options->key.vs_common_out.as_ngg) {
4844 gfx10_ngg_gs_emit_prologue(&ctx);
4845 nested_barrier = false;
4846 } else {
4847 nested_barrier = true;
4848 }
4849 }
4850
4851 if (nested_barrier) {
4852 /* Execute a barrier before the second shader in
4853 * a merged shader.
4854 *
4855 * Execute the barrier inside the conditional block,
4856 * so that empty waves can jump directly to s_endpgm,
4857 * which will also signal the barrier.
4858 *
4859 * This is possible in gfx9, because an empty wave
4860 * for the second shader does not participate in
4861 * the epilogue. With NGG, empty waves may still
4862 * be required to export data (e.g. GS output vertices),
4863 * so we cannot let them exit early.
4864 *
4865 * If the shader is TCS and the TCS epilog is present
4866 * and contains a barrier, it will wait there and then
4867 * reach s_endpgm.
4868 */
4869 ac_emit_barrier(&ctx.ac, ctx.stage);
4870 }
4871
4872 nir_foreach_variable(variable, &shaders[i]->outputs)
4873 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
4874
4875 ac_setup_rings(&ctx);
4876
4877 LLVMBasicBlockRef merge_block;
4878 if (shader_count >= 2 || is_ngg) {
4879 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
4880 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
4881 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
4882
4883 LLVMValueRef count = ac_unpack_param(&ctx.ac, ctx.merged_wave_info, 8 * i, 8);
4884 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
4885 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
4886 thread_id, count, "");
4887 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
4888
4889 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
4890 }
4891
4892 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
4893 prepare_interp_optimize(&ctx, shaders[i]);
4894 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
4895 handle_vs_inputs(&ctx, shaders[i]);
4896 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
4897 prepare_gs_input_vgprs(&ctx);
4898
4899 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
4900
4901 if (shader_count >= 2 || is_ngg) {
4902 LLVMBuildBr(ctx.ac.builder, merge_block);
4903 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
4904 }
4905
4906 /* This needs to be outside the if wrapping the shader body, as sometimes
4907 * the HW generates waves with 0 es/vs threads. */
4908 if (is_pre_gs_stage(shaders[i]->info.stage) &&
4909 ctx.options->key.vs_common_out.as_ngg &&
4910 i == shader_count - 1) {
4911 handle_ngg_outputs_post_2(&ctx);
4912 } else if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
4913 ctx.options->key.vs_common_out.as_ngg) {
4914 gfx10_ngg_gs_emit_epilogue_2(&ctx);
4915 }
4916
4917 if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
4918 shader_info->tcs.num_patches = ctx.tcs_num_patches;
4919 shader_info->tcs.lds_size = calculate_tess_lds_size(&ctx);
4920 }
4921 }
4922
4923 LLVMBuildRetVoid(ctx.ac.builder);
4924
4925 if (options->dump_preoptir) {
4926 fprintf(stderr, "%s LLVM IR:\n\n",
4927 radv_get_shader_name(shader_info,
4928 shaders[shader_count - 1]->info.stage));
4929 ac_dump_module(ctx.ac.module);
4930 fprintf(stderr, "\n");
4931 }
4932
4933 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, options);
4934
4935 if (shader_count == 1)
4936 ac_nir_eliminate_const_vs_outputs(&ctx);
4937
4938 if (options->dump_shader) {
4939 ctx.shader_info->private_mem_vgprs =
4940 ac_count_scratch_private_memory(ctx.main_function);
4941 }
4942
4943 return ctx.ac.module;
4944 }
4945
4946 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
4947 {
4948 unsigned *retval = (unsigned *)context;
4949 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
4950 char *description = LLVMGetDiagInfoDescription(di);
4951
4952 if (severity == LLVMDSError) {
4953 *retval = 1;
4954 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
4955 description);
4956 }
4957
4958 LLVMDisposeMessage(description);
4959 }
4960
4961 static unsigned radv_llvm_compile(LLVMModuleRef M,
4962 char **pelf_buffer, size_t *pelf_size,
4963 struct ac_llvm_compiler *ac_llvm)
4964 {
4965 unsigned retval = 0;
4966 LLVMContextRef llvm_ctx;
4967
4968 /* Setup Diagnostic Handler*/
4969 llvm_ctx = LLVMGetModuleContext(M);
4970
4971 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
4972 &retval);
4973
4974 /* Compile IR*/
4975 if (!radv_compile_to_elf(ac_llvm, M, pelf_buffer, pelf_size))
4976 retval = 1;
4977 return retval;
4978 }
4979
4980 static void ac_compile_llvm_module(struct ac_llvm_compiler *ac_llvm,
4981 LLVMModuleRef llvm_module,
4982 struct radv_shader_binary **rbinary,
4983 gl_shader_stage stage,
4984 const char *name,
4985 const struct radv_nir_compiler_options *options)
4986 {
4987 char *elf_buffer = NULL;
4988 size_t elf_size = 0;
4989 char *llvm_ir_string = NULL;
4990
4991 if (options->dump_shader) {
4992 fprintf(stderr, "%s LLVM IR:\n\n", name);
4993 ac_dump_module(llvm_module);
4994 fprintf(stderr, "\n");
4995 }
4996
4997 if (options->record_ir) {
4998 char *llvm_ir = LLVMPrintModuleToString(llvm_module);
4999 llvm_ir_string = strdup(llvm_ir);
5000 LLVMDisposeMessage(llvm_ir);
5001 }
5002
5003 int v = radv_llvm_compile(llvm_module, &elf_buffer, &elf_size, ac_llvm);
5004 if (v) {
5005 fprintf(stderr, "compile failed\n");
5006 }
5007
5008 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
5009 LLVMDisposeModule(llvm_module);
5010 LLVMContextDispose(ctx);
5011
5012 size_t llvm_ir_size = llvm_ir_string ? strlen(llvm_ir_string) : 0;
5013 size_t alloc_size = sizeof(struct radv_shader_binary_rtld) + elf_size + llvm_ir_size + 1;
5014 struct radv_shader_binary_rtld *rbin = calloc(1, alloc_size);
5015 memcpy(rbin->data, elf_buffer, elf_size);
5016 if (llvm_ir_string)
5017 memcpy(rbin->data + elf_size, llvm_ir_string, llvm_ir_size + 1);
5018
5019 rbin->base.type = RADV_BINARY_TYPE_RTLD;
5020 rbin->base.stage = stage;
5021 rbin->base.total_size = alloc_size;
5022 rbin->elf_size = elf_size;
5023 rbin->llvm_ir_size = llvm_ir_size;
5024 *rbinary = &rbin->base;
5025
5026 free(llvm_ir_string);
5027 free(elf_buffer);
5028 }
5029
5030 void
5031 radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
5032 struct radv_shader_binary **rbinary,
5033 struct radv_shader_info *shader_info,
5034 struct nir_shader *const *nir,
5035 int nir_count,
5036 const struct radv_nir_compiler_options *options)
5037 {
5038
5039 LLVMModuleRef llvm_module;
5040
5041 llvm_module = ac_translate_nir_to_llvm(ac_llvm, nir, nir_count, shader_info,
5042 options);
5043
5044 ac_compile_llvm_module(ac_llvm, llvm_module, rbinary,
5045 nir[nir_count - 1]->info.stage,
5046 radv_get_shader_name(shader_info,
5047 nir[nir_count - 1]->info.stage),
5048 options);
5049
5050 /* Determine the ES type (VS or TES) for the GS on GFX9. */
5051 if (options->chip_class >= GFX9) {
5052 if (nir_count == 2 &&
5053 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
5054 shader_info->gs.es_type = nir[0]->info.stage;
5055 }
5056 }
5057 shader_info->wave_size = options->wave_size;
5058 }
5059
5060 static void
5061 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
5062 {
5063 LLVMValueRef vtx_offset =
5064 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
5065 LLVMConstInt(ctx->ac.i32, 4, false), "");
5066 LLVMValueRef stream_id;
5067
5068 /* Fetch the vertex stream ID. */
5069 if (!ctx->options->use_ngg_streamout &&
5070 ctx->shader_info->so.num_outputs) {
5071 stream_id =
5072 ac_unpack_param(&ctx->ac, ctx->streamout_config, 24, 2);
5073 } else {
5074 stream_id = ctx->ac.i32_0;
5075 }
5076
5077 LLVMBasicBlockRef end_bb;
5078 LLVMValueRef switch_inst;
5079
5080 end_bb = LLVMAppendBasicBlockInContext(ctx->ac.context,
5081 ctx->main_function, "end");
5082 switch_inst = LLVMBuildSwitch(ctx->ac.builder, stream_id, end_bb, 4);
5083
5084 for (unsigned stream = 0; stream < 4; stream++) {
5085 unsigned num_components =
5086 ctx->shader_info->gs.num_stream_output_components[stream];
5087 LLVMBasicBlockRef bb;
5088 unsigned offset;
5089
5090 if (stream > 0 && !num_components)
5091 continue;
5092
5093 if (stream > 0 && !ctx->shader_info->so.num_outputs)
5094 continue;
5095
5096 bb = LLVMInsertBasicBlockInContext(ctx->ac.context, end_bb, "out");
5097 LLVMAddCase(switch_inst, LLVMConstInt(ctx->ac.i32, stream, 0), bb);
5098 LLVMPositionBuilderAtEnd(ctx->ac.builder, bb);
5099
5100 offset = 0;
5101 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
5102 unsigned output_usage_mask =
5103 ctx->shader_info->gs.output_usage_mask[i];
5104 unsigned output_stream =
5105 ctx->shader_info->gs.output_streams[i];
5106 int length = util_last_bit(output_usage_mask);
5107
5108 if (!(ctx->output_mask & (1ull << i)) ||
5109 output_stream != stream)
5110 continue;
5111
5112 for (unsigned j = 0; j < length; j++) {
5113 LLVMValueRef value, soffset;
5114
5115 if (!(output_usage_mask & (1 << j)))
5116 continue;
5117
5118 soffset = LLVMConstInt(ctx->ac.i32,
5119 offset *
5120 ctx->shader->info.gs.vertices_out * 16 * 4, false);
5121
5122 offset++;
5123
5124 value = ac_build_buffer_load(&ctx->ac,
5125 ctx->gsvs_ring[0],
5126 1, ctx->ac.i32_0,
5127 vtx_offset, soffset,
5128 0, ac_glc | ac_slc, true, false);
5129
5130 LLVMTypeRef type = LLVMGetAllocatedType(ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
5131 if (ac_get_type_size(type) == 2) {
5132 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
5133 value = LLVMBuildTrunc(ctx->ac.builder, value, ctx->ac.i16, "");
5134 }
5135
5136 LLVMBuildStore(ctx->ac.builder,
5137 ac_to_float(&ctx->ac, value), ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
5138 }
5139 }
5140
5141 if (!ctx->options->use_ngg_streamout &&
5142 ctx->shader_info->so.num_outputs)
5143 radv_emit_streamout(ctx, stream);
5144
5145 if (stream == 0) {
5146 handle_vs_outputs_post(ctx, false, true,
5147 &ctx->shader_info->vs.outinfo);
5148 }
5149
5150 LLVMBuildBr(ctx->ac.builder, end_bb);
5151 }
5152
5153 LLVMPositionBuilderAtEnd(ctx->ac.builder, end_bb);
5154 }
5155
5156 void
5157 radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
5158 struct nir_shader *geom_shader,
5159 struct radv_shader_binary **rbinary,
5160 struct radv_shader_info *shader_info,
5161 const struct radv_nir_compiler_options *options)
5162 {
5163 struct radv_shader_context ctx = {0};
5164 ctx.options = options;
5165 ctx.shader_info = shader_info;
5166
5167 enum ac_float_mode float_mode =
5168 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
5169 AC_FLOAT_MODE_DEFAULT;
5170
5171 ac_llvm_context_init(&ctx.ac, ac_llvm, options->chip_class,
5172 options->family, float_mode, 64, 64);
5173 ctx.context = ctx.ac.context;
5174
5175 ctx.is_gs_copy_shader = true;
5176 ctx.stage = MESA_SHADER_VERTEX;
5177 ctx.shader = geom_shader;
5178
5179 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
5180
5181 ac_setup_rings(&ctx);
5182
5183 nir_foreach_variable(variable, &geom_shader->outputs) {
5184 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
5185 ac_handle_shader_output_decl(&ctx.ac, &ctx.abi, geom_shader,
5186 variable, MESA_SHADER_VERTEX);
5187 }
5188
5189 ac_gs_copy_shader_emit(&ctx);
5190
5191 LLVMBuildRetVoid(ctx.ac.builder);
5192
5193 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, options);
5194
5195 ac_compile_llvm_module(ac_llvm, ctx.ac.module, rbinary,
5196 MESA_SHADER_VERTEX, "GS Copy Shader", options);
5197 (*rbinary)->is_gs_copy_shader = true;
5198
5199 }