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radv: remove unnecessary LLVM includes
[mesa.git] / src / amd / vulkan / radv_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "radv_shader_helper.h"
31 #include "radv_shader_args.h"
32 #include "nir/nir.h"
33
34 #include "sid.h"
35 #include "ac_binary.h"
36 #include "ac_llvm_util.h"
37 #include "ac_llvm_build.h"
38 #include "ac_shader_abi.h"
39 #include "ac_shader_util.h"
40 #include "ac_exp_param.h"
41
42 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
43
44 struct radv_shader_context {
45 struct ac_llvm_context ac;
46 const struct nir_shader *shader;
47 struct ac_shader_abi abi;
48 const struct radv_shader_args *args;
49
50 gl_shader_stage stage;
51
52 unsigned max_workgroup_size;
53 LLVMContextRef context;
54 LLVMValueRef main_function;
55
56 LLVMValueRef descriptor_sets[MAX_SETS];
57
58 LLVMValueRef ring_offsets;
59
60 LLVMValueRef rel_auto_id;
61
62 LLVMValueRef gs_wave_id;
63 LLVMValueRef gs_vtx_offset[6];
64
65 LLVMValueRef esgs_ring;
66 LLVMValueRef gsvs_ring[4];
67 LLVMValueRef hs_ring_tess_offchip;
68 LLVMValueRef hs_ring_tess_factor;
69
70 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
71
72 uint64_t output_mask;
73
74 LLVMValueRef gs_next_vertex[4];
75 LLVMValueRef gs_curprim_verts[4];
76 LLVMValueRef gs_generated_prims[4];
77 LLVMValueRef gs_ngg_emit;
78 LLVMValueRef gs_ngg_scratch;
79
80 uint32_t tcs_num_inputs;
81 uint32_t tcs_num_patches;
82
83 LLVMValueRef vertexptr; /* GFX10 only */
84 };
85
86 struct radv_shader_output_values {
87 LLVMValueRef values[4];
88 unsigned slot_name;
89 unsigned slot_index;
90 unsigned usage_mask;
91 };
92
93 static inline struct radv_shader_context *
94 radv_shader_context_from_abi(struct ac_shader_abi *abi)
95 {
96 struct radv_shader_context *ctx = NULL;
97 return container_of(abi, ctx, abi);
98 }
99
100 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
101 {
102 switch (ctx->stage) {
103 case MESA_SHADER_TESS_CTRL:
104 return ac_unpack_param(&ctx->ac,
105 ac_get_arg(&ctx->ac, ctx->args->ac.tcs_rel_ids),
106 0, 8);
107 case MESA_SHADER_TESS_EVAL:
108 return ac_get_arg(&ctx->ac, ctx->args->tes_rel_patch_id);
109 break;
110 default:
111 unreachable("Illegal stage");
112 }
113 }
114
115 /* Tessellation shaders pass outputs to the next shader using LDS.
116 *
117 * LS outputs = TCS inputs
118 * TCS outputs = TES inputs
119 *
120 * The LDS layout is:
121 * - TCS inputs for patch 0
122 * - TCS inputs for patch 1
123 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
124 * - ...
125 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
126 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
127 * - TCS outputs for patch 1
128 * - Per-patch TCS outputs for patch 1
129 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
130 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
131 * - ...
132 *
133 * All three shaders VS(LS), TCS, TES share the same LDS space.
134 */
135 static LLVMValueRef
136 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
137 {
138 assert(ctx->stage == MESA_SHADER_TESS_CTRL);
139 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
140 uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * input_vertex_size;
141
142 input_patch_size /= 4;
143 return LLVMConstInt(ctx->ac.i32, input_patch_size, false);
144 }
145
146 static LLVMValueRef
147 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
148 {
149 uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
150 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->args->shader_info->tcs.patch_outputs_written);
151 uint32_t output_vertex_size = num_tcs_outputs * 16;
152 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
153 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
154 output_patch_size /= 4;
155 return LLVMConstInt(ctx->ac.i32, output_patch_size, false);
156 }
157
158 static LLVMValueRef
159 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
160 {
161 uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
162 uint32_t output_vertex_size = num_tcs_outputs * 16;
163 output_vertex_size /= 4;
164 return LLVMConstInt(ctx->ac.i32, output_vertex_size, false);
165 }
166
167 static LLVMValueRef
168 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
169 {
170 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
171 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
172 uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * input_vertex_size;
173 uint32_t output_patch0_offset = input_patch_size;
174 unsigned num_patches = ctx->tcs_num_patches;
175
176 output_patch0_offset *= num_patches;
177 output_patch0_offset /= 4;
178 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
179 }
180
181 static LLVMValueRef
182 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
183 {
184 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
185 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
186 uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * input_vertex_size;
187 uint32_t output_patch0_offset = input_patch_size;
188
189 uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
190 uint32_t output_vertex_size = num_tcs_outputs * 16;
191 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
192 unsigned num_patches = ctx->tcs_num_patches;
193
194 output_patch0_offset *= num_patches;
195 output_patch0_offset += pervertex_output_patch_size;
196 output_patch0_offset /= 4;
197 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
198 }
199
200 static LLVMValueRef
201 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
202 {
203 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
204 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
205
206 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
207 }
208
209 static LLVMValueRef
210 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
211 {
212 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
213 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
214 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
215
216 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
217 patch0_offset);
218 }
219
220 static LLVMValueRef
221 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
222 {
223 LLVMValueRef patch0_patch_data_offset =
224 get_tcs_out_patch0_patch_data_offset(ctx);
225 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
226 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
227
228 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
229 patch0_patch_data_offset);
230 }
231
232 static LLVMValueRef
233 create_llvm_function(struct ac_llvm_context *ctx, LLVMModuleRef module,
234 LLVMBuilderRef builder,
235 const struct ac_shader_args *args,
236 enum ac_llvm_calling_convention convention,
237 unsigned max_workgroup_size,
238 const struct radv_nir_compiler_options *options)
239 {
240 LLVMValueRef main_function =
241 ac_build_main(args, ctx, convention, "main", ctx->voidt, module);
242
243 if (options->address32_hi) {
244 ac_llvm_add_target_dep_function_attr(main_function,
245 "amdgpu-32bit-address-high-bits",
246 options->address32_hi);
247 }
248
249 ac_llvm_set_workgroup_size(main_function, max_workgroup_size);
250
251 return main_function;
252 }
253
254 static void
255 load_descriptor_sets(struct radv_shader_context *ctx)
256 {
257 uint32_t mask = ctx->args->shader_info->desc_set_used_mask;
258 if (ctx->args->shader_info->need_indirect_descriptor_sets) {
259 LLVMValueRef desc_sets =
260 ac_get_arg(&ctx->ac, ctx->args->descriptor_sets[0]);
261 while (mask) {
262 int i = u_bit_scan(&mask);
263
264 ctx->descriptor_sets[i] =
265 ac_build_load_to_sgpr(&ctx->ac, desc_sets,
266 LLVMConstInt(ctx->ac.i32, i, false));
267
268 }
269 } else {
270 while (mask) {
271 int i = u_bit_scan(&mask);
272
273 ctx->descriptor_sets[i] =
274 ac_get_arg(&ctx->ac, ctx->args->descriptor_sets[i]);
275 }
276 }
277 }
278
279 static enum ac_llvm_calling_convention
280 get_llvm_calling_convention(LLVMValueRef func, gl_shader_stage stage)
281 {
282 switch (stage) {
283 case MESA_SHADER_VERTEX:
284 case MESA_SHADER_TESS_EVAL:
285 return AC_LLVM_AMDGPU_VS;
286 break;
287 case MESA_SHADER_GEOMETRY:
288 return AC_LLVM_AMDGPU_GS;
289 break;
290 case MESA_SHADER_TESS_CTRL:
291 return AC_LLVM_AMDGPU_HS;
292 break;
293 case MESA_SHADER_FRAGMENT:
294 return AC_LLVM_AMDGPU_PS;
295 break;
296 case MESA_SHADER_COMPUTE:
297 return AC_LLVM_AMDGPU_CS;
298 break;
299 default:
300 unreachable("Unhandle shader type");
301 }
302 }
303
304 /* Returns whether the stage is a stage that can be directly before the GS */
305 static bool is_pre_gs_stage(gl_shader_stage stage)
306 {
307 return stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL;
308 }
309
310 static void create_function(struct radv_shader_context *ctx,
311 gl_shader_stage stage,
312 bool has_previous_stage)
313 {
314 if (ctx->ac.chip_class >= GFX10) {
315 if (is_pre_gs_stage(stage) && ctx->args->options->key.vs_common_out.as_ngg) {
316 /* On GFX10, VS is merged into GS for NGG. */
317 stage = MESA_SHADER_GEOMETRY;
318 has_previous_stage = true;
319 }
320 }
321
322 ctx->main_function = create_llvm_function(
323 &ctx->ac, ctx->ac.module, ctx->ac.builder, &ctx->args->ac,
324 get_llvm_calling_convention(ctx->main_function, stage),
325 ctx->max_workgroup_size,
326 ctx->args->options);
327
328 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
329 LLVMPointerType(ctx->ac.i8, AC_ADDR_SPACE_CONST),
330 NULL, 0, AC_FUNC_ATTR_READNONE);
331 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
332 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
333
334 load_descriptor_sets(ctx);
335
336 if (stage == MESA_SHADER_TESS_CTRL ||
337 (stage == MESA_SHADER_VERTEX && ctx->args->options->key.vs_common_out.as_ls) ||
338 /* GFX9 has the ESGS ring buffer in LDS. */
339 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
340 ac_declare_lds_as_pointer(&ctx->ac);
341 }
342
343 }
344
345
346 static LLVMValueRef
347 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
348 unsigned desc_set, unsigned binding)
349 {
350 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
351 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
352 struct radv_pipeline_layout *pipeline_layout = ctx->args->options->layout;
353 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
354 unsigned base_offset = layout->binding[binding].offset;
355 LLVMValueRef offset, stride;
356
357 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
358 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
359 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
360 layout->binding[binding].dynamic_offset_offset;
361 desc_ptr = ac_get_arg(&ctx->ac, ctx->args->ac.push_constants);
362 base_offset = pipeline_layout->push_constant_size + 16 * idx;
363 stride = LLVMConstInt(ctx->ac.i32, 16, false);
364 } else
365 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
366
367 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
368
369 if (layout->binding[binding].type != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
370 offset = ac_build_imad(&ctx->ac, index, stride, offset);
371 }
372
373 desc_ptr = LLVMBuildGEP(ctx->ac.builder, desc_ptr, &offset, 1, "");
374 desc_ptr = ac_cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
375 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
376
377 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
378 uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
379 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
380 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
381 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
382
383 if (ctx->ac.chip_class >= GFX10) {
384 desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
385 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
386 S_008F0C_RESOURCE_LEVEL(1);
387 } else {
388 desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
389 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
390 }
391
392 LLVMValueRef desc_components[4] = {
393 LLVMBuildPtrToInt(ctx->ac.builder, desc_ptr, ctx->ac.intptr, ""),
394 LLVMConstInt(ctx->ac.i32, S_008F04_BASE_ADDRESS_HI(ctx->args->options->address32_hi), false),
395 /* High limit to support variable sizes. */
396 LLVMConstInt(ctx->ac.i32, 0xffffffff, false),
397 LLVMConstInt(ctx->ac.i32, desc_type, false),
398 };
399
400 return ac_build_gather_values(&ctx->ac, desc_components, 4);
401 }
402
403 return desc_ptr;
404 }
405
406
407 /* The offchip buffer layout for TCS->TES is
408 *
409 * - attribute 0 of patch 0 vertex 0
410 * - attribute 0 of patch 0 vertex 1
411 * - attribute 0 of patch 0 vertex 2
412 * ...
413 * - attribute 0 of patch 1 vertex 0
414 * - attribute 0 of patch 1 vertex 1
415 * ...
416 * - attribute 1 of patch 0 vertex 0
417 * - attribute 1 of patch 0 vertex 1
418 * ...
419 * - per patch attribute 0 of patch 0
420 * - per patch attribute 0 of patch 1
421 * ...
422 *
423 * Note that every attribute has 4 components.
424 */
425 static LLVMValueRef get_non_vertex_index_offset(struct radv_shader_context *ctx)
426 {
427 uint32_t num_patches = ctx->tcs_num_patches;
428 uint32_t num_tcs_outputs;
429 if (ctx->stage == MESA_SHADER_TESS_CTRL)
430 num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
431 else
432 num_tcs_outputs = ctx->args->options->key.tes.tcs_num_outputs;
433
434 uint32_t output_vertex_size = num_tcs_outputs * 16;
435 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
436
437 return LLVMConstInt(ctx->ac.i32, pervertex_output_patch_size * num_patches, false);
438 }
439
440 static LLVMValueRef calc_param_stride(struct radv_shader_context *ctx,
441 LLVMValueRef vertex_index)
442 {
443 LLVMValueRef param_stride;
444 if (vertex_index)
445 param_stride = LLVMConstInt(ctx->ac.i32, ctx->shader->info.tess.tcs_vertices_out * ctx->tcs_num_patches, false);
446 else
447 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_num_patches, false);
448 return param_stride;
449 }
450
451 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
452 LLVMValueRef vertex_index,
453 LLVMValueRef param_index)
454 {
455 LLVMValueRef base_addr;
456 LLVMValueRef param_stride, constant16;
457 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
458 LLVMValueRef vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->shader->info.tess.tcs_vertices_out, false);
459 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
460 param_stride = calc_param_stride(ctx, vertex_index);
461 if (vertex_index) {
462 base_addr = ac_build_imad(&ctx->ac, rel_patch_id,
463 vertices_per_patch, vertex_index);
464 } else {
465 base_addr = rel_patch_id;
466 }
467
468 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
469 LLVMBuildMul(ctx->ac.builder, param_index,
470 param_stride, ""), "");
471
472 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
473
474 if (!vertex_index) {
475 LLVMValueRef patch_data_offset = get_non_vertex_index_offset(ctx);
476
477 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
478 patch_data_offset, "");
479 }
480 return base_addr;
481 }
482
483 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
484 unsigned param,
485 unsigned const_index,
486 bool is_compact,
487 LLVMValueRef vertex_index,
488 LLVMValueRef indir_index)
489 {
490 LLVMValueRef param_index;
491
492 if (indir_index)
493 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
494 indir_index, "");
495 else {
496 if (const_index && !is_compact)
497 param += const_index;
498 param_index = LLVMConstInt(ctx->ac.i32, param, false);
499 }
500 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
501 }
502
503 static LLVMValueRef
504 get_dw_address(struct radv_shader_context *ctx,
505 LLVMValueRef dw_addr,
506 unsigned param,
507 unsigned const_index,
508 bool compact_const_index,
509 LLVMValueRef vertex_index,
510 LLVMValueRef stride,
511 LLVMValueRef indir_index)
512
513 {
514
515 if (vertex_index) {
516 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
517 LLVMBuildMul(ctx->ac.builder,
518 vertex_index,
519 stride, ""), "");
520 }
521
522 if (indir_index)
523 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
524 LLVMBuildMul(ctx->ac.builder, indir_index,
525 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
526 else if (const_index && !compact_const_index)
527 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
528 LLVMConstInt(ctx->ac.i32, const_index * 4, false), "");
529
530 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
531 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
532
533 if (const_index && compact_const_index)
534 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
535 LLVMConstInt(ctx->ac.i32, const_index, false), "");
536 return dw_addr;
537 }
538
539 static LLVMValueRef
540 load_tcs_varyings(struct ac_shader_abi *abi,
541 LLVMTypeRef type,
542 LLVMValueRef vertex_index,
543 LLVMValueRef indir_index,
544 unsigned const_index,
545 unsigned location,
546 unsigned driver_location,
547 unsigned component,
548 unsigned num_components,
549 bool is_patch,
550 bool is_compact,
551 bool load_input)
552 {
553 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
554 LLVMValueRef dw_addr, stride;
555 LLVMValueRef value[4], result;
556 unsigned param = shader_io_get_unique_index(location);
557
558 if (load_input) {
559 uint32_t input_vertex_size = (ctx->tcs_num_inputs * 16) / 4;
560 stride = LLVMConstInt(ctx->ac.i32, input_vertex_size, false);
561 dw_addr = get_tcs_in_current_patch_offset(ctx);
562 } else {
563 if (!is_patch) {
564 stride = get_tcs_out_vertex_stride(ctx);
565 dw_addr = get_tcs_out_current_patch_offset(ctx);
566 } else {
567 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
568 stride = NULL;
569 }
570 }
571
572 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
573 indir_index);
574
575 for (unsigned i = 0; i < num_components + component; i++) {
576 value[i] = ac_lds_load(&ctx->ac, dw_addr);
577 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
578 ctx->ac.i32_1, "");
579 }
580 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
581 return result;
582 }
583
584 static void
585 store_tcs_output(struct ac_shader_abi *abi,
586 const nir_variable *var,
587 LLVMValueRef vertex_index,
588 LLVMValueRef param_index,
589 unsigned const_index,
590 LLVMValueRef src,
591 unsigned writemask)
592 {
593 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
594 const unsigned location = var->data.location;
595 unsigned component = var->data.location_frac;
596 const bool is_patch = var->data.patch;
597 const bool is_compact = var->data.compact;
598 LLVMValueRef dw_addr;
599 LLVMValueRef stride = NULL;
600 LLVMValueRef buf_addr = NULL;
601 LLVMValueRef oc_lds = ac_get_arg(&ctx->ac, ctx->args->oc_lds);
602 unsigned param;
603 bool store_lds = true;
604
605 if (is_patch) {
606 if (!(ctx->shader->info.patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
607 store_lds = false;
608 } else {
609 if (!(ctx->shader->info.outputs_read & (1ULL << location)))
610 store_lds = false;
611 }
612
613 param = shader_io_get_unique_index(location);
614 if ((location == VARYING_SLOT_CLIP_DIST0 || location == VARYING_SLOT_CLIP_DIST1) && is_compact) {
615 const_index += component;
616 component = 0;
617
618 if (const_index >= 4) {
619 const_index -= 4;
620 param++;
621 }
622 }
623
624 if (!is_patch) {
625 stride = get_tcs_out_vertex_stride(ctx);
626 dw_addr = get_tcs_out_current_patch_offset(ctx);
627 } else {
628 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
629 }
630
631 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
632 param_index);
633 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
634 vertex_index, param_index);
635
636 bool is_tess_factor = false;
637 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
638 location == VARYING_SLOT_TESS_LEVEL_OUTER)
639 is_tess_factor = true;
640
641 unsigned base = is_compact ? const_index : 0;
642 for (unsigned chan = 0; chan < 8; chan++) {
643 if (!(writemask & (1 << chan)))
644 continue;
645 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
646 value = ac_to_integer(&ctx->ac, value);
647 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
648
649 if (store_lds || is_tess_factor) {
650 LLVMValueRef dw_addr_chan =
651 LLVMBuildAdd(ctx->ac.builder, dw_addr,
652 LLVMConstInt(ctx->ac.i32, chan, false), "");
653 ac_lds_store(&ctx->ac, dw_addr_chan, value);
654 }
655
656 if (!is_tess_factor && writemask != 0xF)
657 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
658 buf_addr, oc_lds,
659 4 * (base + chan), ac_glc);
660 }
661
662 if (writemask == 0xF) {
663 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
664 buf_addr, oc_lds,
665 (base * 4), ac_glc);
666 }
667 }
668
669 static LLVMValueRef
670 load_tes_input(struct ac_shader_abi *abi,
671 LLVMTypeRef type,
672 LLVMValueRef vertex_index,
673 LLVMValueRef param_index,
674 unsigned const_index,
675 unsigned location,
676 unsigned driver_location,
677 unsigned component,
678 unsigned num_components,
679 bool is_patch,
680 bool is_compact,
681 bool load_input)
682 {
683 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
684 LLVMValueRef buf_addr;
685 LLVMValueRef result;
686 LLVMValueRef oc_lds = ac_get_arg(&ctx->ac, ctx->args->oc_lds);
687 unsigned param = shader_io_get_unique_index(location);
688
689 if ((location == VARYING_SLOT_CLIP_DIST0 || location == VARYING_SLOT_CLIP_DIST1) && is_compact) {
690 const_index += component;
691 component = 0;
692 if (const_index >= 4) {
693 const_index -= 4;
694 param++;
695 }
696 }
697
698 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
699 is_compact, vertex_index, param_index);
700
701 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
702 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
703
704 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
705 buf_addr, oc_lds, is_compact ? (4 * const_index) : 0, ac_glc, true, false);
706 result = ac_trim_vector(&ctx->ac, result, num_components);
707 return result;
708 }
709
710 static LLVMValueRef
711 radv_emit_fetch_64bit(struct radv_shader_context *ctx,
712 LLVMTypeRef type, LLVMValueRef a, LLVMValueRef b)
713 {
714 LLVMValueRef values[2] = {
715 ac_to_integer(&ctx->ac, a),
716 ac_to_integer(&ctx->ac, b),
717 };
718 LLVMValueRef result = ac_build_gather_values(&ctx->ac, values, 2);
719 return LLVMBuildBitCast(ctx->ac.builder, result, type, "");
720 }
721
722 static LLVMValueRef
723 load_gs_input(struct ac_shader_abi *abi,
724 unsigned location,
725 unsigned driver_location,
726 unsigned component,
727 unsigned num_components,
728 unsigned vertex_index,
729 unsigned const_index,
730 LLVMTypeRef type)
731 {
732 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
733 LLVMValueRef vtx_offset;
734 unsigned param, vtx_offset_param;
735 LLVMValueRef value[4], result;
736
737 vtx_offset_param = vertex_index;
738 assert(vtx_offset_param < 6);
739 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
740 LLVMConstInt(ctx->ac.i32, 4, false), "");
741
742 param = shader_io_get_unique_index(location);
743
744 for (unsigned i = component; i < num_components + component; i++) {
745 if (ctx->ac.chip_class >= GFX9) {
746 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
747 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
748 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
749 value[i] = ac_lds_load(&ctx->ac, dw_addr);
750
751 if (ac_get_type_size(type) == 8) {
752 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
753 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index + 1, 0), "");
754 LLVMValueRef tmp = ac_lds_load(&ctx->ac, dw_addr);
755
756 value[i] = radv_emit_fetch_64bit(ctx, type, value[i], tmp);
757 }
758 } else {
759 LLVMValueRef soffset =
760 LLVMConstInt(ctx->ac.i32,
761 (param * 4 + i + const_index) * 256,
762 false);
763
764 value[i] = ac_build_buffer_load(&ctx->ac,
765 ctx->esgs_ring, 1,
766 ctx->ac.i32_0,
767 vtx_offset, soffset,
768 0, ac_glc, true, false);
769
770 if (ac_get_type_size(type) == 8) {
771 soffset = LLVMConstInt(ctx->ac.i32,
772 (param * 4 + i + const_index + 1) * 256,
773 false);
774
775 LLVMValueRef tmp =
776 ac_build_buffer_load(&ctx->ac,
777 ctx->esgs_ring, 1,
778 ctx->ac.i32_0,
779 vtx_offset, soffset,
780 0, ac_glc, true, false);
781
782 value[i] = radv_emit_fetch_64bit(ctx, type, value[i], tmp);
783 }
784 }
785
786 if (ac_get_type_size(type) == 2) {
787 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], ctx->ac.i32, "");
788 value[i] = LLVMBuildTrunc(ctx->ac.builder, value[i], ctx->ac.i16, "");
789 }
790 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], type, "");
791 }
792 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
793 result = ac_to_integer(&ctx->ac, result);
794 return result;
795 }
796
797 static uint32_t
798 radv_get_sample_pos_offset(uint32_t num_samples)
799 {
800 uint32_t sample_pos_offset = 0;
801
802 switch (num_samples) {
803 case 2:
804 sample_pos_offset = 1;
805 break;
806 case 4:
807 sample_pos_offset = 3;
808 break;
809 case 8:
810 sample_pos_offset = 7;
811 break;
812 default:
813 break;
814 }
815 return sample_pos_offset;
816 }
817
818 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
819 LLVMValueRef sample_id)
820 {
821 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
822
823 LLVMValueRef result;
824 LLVMValueRef index = LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false);
825 LLVMValueRef ptr = LLVMBuildGEP(ctx->ac.builder, ctx->ring_offsets, &index, 1, "");
826
827 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
828 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
829
830 uint32_t sample_pos_offset =
831 radv_get_sample_pos_offset(ctx->args->options->key.fs.num_samples);
832
833 sample_id =
834 LLVMBuildAdd(ctx->ac.builder, sample_id,
835 LLVMConstInt(ctx->ac.i32, sample_pos_offset, false), "");
836 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
837
838 return result;
839 }
840
841
842 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
843 {
844 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
845 uint8_t log2_ps_iter_samples;
846
847 if (ctx->args->shader_info->ps.force_persample) {
848 log2_ps_iter_samples =
849 util_logbase2(ctx->args->options->key.fs.num_samples);
850 } else {
851 log2_ps_iter_samples = ctx->args->options->key.fs.log2_ps_iter_samples;
852 }
853
854 /* The bit pattern matches that used by fixed function fragment
855 * processing. */
856 static const uint16_t ps_iter_masks[] = {
857 0xffff, /* not used */
858 0x5555,
859 0x1111,
860 0x0101,
861 0x0001,
862 };
863 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
864
865 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
866
867 LLVMValueRef result, sample_id;
868 sample_id = ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->ac.ancillary), 8, 4);
869 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
870 result = LLVMBuildAnd(ctx->ac.builder, sample_id,
871 ac_get_arg(&ctx->ac, ctx->args->ac.sample_coverage), "");
872 return result;
873 }
874
875
876 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context *ctx,
877 unsigned stream,
878 LLVMValueRef *addrs);
879
880 static void
881 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
882 {
883 LLVMValueRef gs_next_vertex;
884 LLVMValueRef can_emit;
885 unsigned offset = 0;
886 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
887
888 if (ctx->args->options->key.vs_common_out.as_ngg) {
889 gfx10_ngg_gs_emit_vertex(ctx, stream, addrs);
890 return;
891 }
892
893 /* Write vertex attribute values to GSVS ring */
894 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
895 ctx->gs_next_vertex[stream],
896 "");
897
898 /* If this thread has already emitted the declared maximum number of
899 * vertices, don't emit any more: excessive vertex emissions are not
900 * supposed to have any effect.
901 */
902 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
903 LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false), "");
904
905 bool use_kill = !ctx->args->shader_info->gs.writes_memory;
906 if (use_kill)
907 ac_build_kill_if_false(&ctx->ac, can_emit);
908 else
909 ac_build_ifcc(&ctx->ac, can_emit, 6505);
910
911 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
912 unsigned output_usage_mask =
913 ctx->args->shader_info->gs.output_usage_mask[i];
914 uint8_t output_stream =
915 ctx->args->shader_info->gs.output_streams[i];
916 LLVMValueRef *out_ptr = &addrs[i * 4];
917 int length = util_last_bit(output_usage_mask);
918
919 if (!(ctx->output_mask & (1ull << i)) ||
920 output_stream != stream)
921 continue;
922
923 for (unsigned j = 0; j < length; j++) {
924 if (!(output_usage_mask & (1 << j)))
925 continue;
926
927 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
928 out_ptr[j], "");
929 LLVMValueRef voffset =
930 LLVMConstInt(ctx->ac.i32, offset *
931 ctx->shader->info.gs.vertices_out, false);
932
933 offset++;
934
935 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
936 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
937
938 out_val = ac_to_integer(&ctx->ac, out_val);
939 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
940
941 ac_build_buffer_store_dword(&ctx->ac,
942 ctx->gsvs_ring[stream],
943 out_val, 1,
944 voffset,
945 ac_get_arg(&ctx->ac,
946 ctx->args->gs2vs_offset),
947 0, ac_glc | ac_slc | ac_swizzled);
948 }
949 }
950
951 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
952 ctx->ac.i32_1, "");
953 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
954
955 ac_build_sendmsg(&ctx->ac,
956 AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
957 ctx->gs_wave_id);
958
959 if (!use_kill)
960 ac_build_endif(&ctx->ac, 6505);
961 }
962
963 static void
964 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
965 {
966 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
967
968 if (ctx->args->options->key.vs_common_out.as_ngg) {
969 LLVMBuildStore(ctx->ac.builder, ctx->ac.i32_0, ctx->gs_curprim_verts[stream]);
970 return;
971 }
972
973 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
974 }
975
976 static LLVMValueRef
977 load_tess_coord(struct ac_shader_abi *abi)
978 {
979 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
980
981 LLVMValueRef coord[4] = {
982 ac_get_arg(&ctx->ac, ctx->args->tes_u),
983 ac_get_arg(&ctx->ac, ctx->args->tes_v),
984 ctx->ac.f32_0,
985 ctx->ac.f32_0,
986 };
987
988 if (ctx->shader->info.tess.primitive_mode == GL_TRIANGLES)
989 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
990 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
991
992 return ac_build_gather_values(&ctx->ac, coord, 3);
993 }
994
995 static LLVMValueRef
996 load_patch_vertices_in(struct ac_shader_abi *abi)
997 {
998 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
999 return LLVMConstInt(ctx->ac.i32, ctx->args->options->key.tcs.input_vertices, false);
1000 }
1001
1002
1003 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
1004 {
1005 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1006 return ac_get_arg(&ctx->ac, ctx->args->ac.base_vertex);
1007 }
1008
1009 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
1010 LLVMValueRef buffer_ptr, bool write)
1011 {
1012 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1013 LLVMValueRef result;
1014
1015 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1016
1017 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1018 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1019
1020 return result;
1021 }
1022
1023 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
1024 {
1025 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1026 LLVMValueRef result;
1027
1028 if (LLVMGetTypeKind(LLVMTypeOf(buffer_ptr)) != LLVMPointerTypeKind) {
1029 /* Do not load the descriptor for inlined uniform blocks. */
1030 return buffer_ptr;
1031 }
1032
1033 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1034
1035 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1036 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1037
1038 return result;
1039 }
1040
1041 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
1042 unsigned descriptor_set,
1043 unsigned base_index,
1044 unsigned constant_index,
1045 LLVMValueRef index,
1046 enum ac_descriptor_type desc_type,
1047 bool image, bool write,
1048 bool bindless)
1049 {
1050 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1051 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
1052 struct radv_descriptor_set_layout *layout = ctx->args->options->layout->set[descriptor_set].layout;
1053 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
1054 unsigned offset = binding->offset;
1055 unsigned stride = binding->size;
1056 unsigned type_size;
1057 LLVMBuilderRef builder = ctx->ac.builder;
1058 LLVMTypeRef type;
1059
1060 assert(base_index < layout->binding_count);
1061
1062 switch (desc_type) {
1063 case AC_DESC_IMAGE:
1064 type = ctx->ac.v8i32;
1065 type_size = 32;
1066 break;
1067 case AC_DESC_FMASK:
1068 type = ctx->ac.v8i32;
1069 offset += 32;
1070 type_size = 32;
1071 break;
1072 case AC_DESC_SAMPLER:
1073 type = ctx->ac.v4i32;
1074 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER) {
1075 offset += radv_combined_image_descriptor_sampler_offset(binding);
1076 }
1077
1078 type_size = 16;
1079 break;
1080 case AC_DESC_BUFFER:
1081 type = ctx->ac.v4i32;
1082 type_size = 16;
1083 break;
1084 case AC_DESC_PLANE_0:
1085 case AC_DESC_PLANE_1:
1086 case AC_DESC_PLANE_2:
1087 type = ctx->ac.v8i32;
1088 type_size = 32;
1089 offset += 32 * (desc_type - AC_DESC_PLANE_0);
1090 break;
1091 default:
1092 unreachable("invalid desc_type\n");
1093 }
1094
1095 offset += constant_index * stride;
1096
1097 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
1098 (!index || binding->immutable_samplers_equal)) {
1099 if (binding->immutable_samplers_equal)
1100 constant_index = 0;
1101
1102 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
1103
1104 LLVMValueRef constants[] = {
1105 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
1106 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
1107 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
1108 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
1109 };
1110 return ac_build_gather_values(&ctx->ac, constants, 4);
1111 }
1112
1113 assert(stride % type_size == 0);
1114
1115 LLVMValueRef adjusted_index = index;
1116 if (!adjusted_index)
1117 adjusted_index = ctx->ac.i32_0;
1118
1119 adjusted_index = LLVMBuildMul(builder, adjusted_index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
1120
1121 LLVMValueRef val_offset = LLVMConstInt(ctx->ac.i32, offset, 0);
1122 list = LLVMBuildGEP(builder, list, &val_offset, 1, "");
1123 list = LLVMBuildPointerCast(builder, list,
1124 ac_array_in_const32_addr_space(type), "");
1125
1126 LLVMValueRef descriptor = ac_build_load_to_sgpr(&ctx->ac, list, adjusted_index);
1127
1128 /* 3 plane formats always have same size and format for plane 1 & 2, so
1129 * use the tail from plane 1 so that we can store only the first 16 bytes
1130 * of the last plane. */
1131 if (desc_type == AC_DESC_PLANE_2) {
1132 LLVMValueRef descriptor2 = radv_get_sampler_desc(abi, descriptor_set, base_index, constant_index, index, AC_DESC_PLANE_1,image, write, bindless);
1133
1134 LLVMValueRef components[8];
1135 for (unsigned i = 0; i < 4; ++i)
1136 components[i] = ac_llvm_extract_elem(&ctx->ac, descriptor, i);
1137
1138 for (unsigned i = 4; i < 8; ++i)
1139 components[i] = ac_llvm_extract_elem(&ctx->ac, descriptor2, i);
1140 descriptor = ac_build_gather_values(&ctx->ac, components, 8);
1141 }
1142
1143 return descriptor;
1144 }
1145
1146 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
1147 * so we may need to fix it up. */
1148 static LLVMValueRef
1149 adjust_vertex_fetch_alpha(struct radv_shader_context *ctx,
1150 unsigned adjustment,
1151 LLVMValueRef alpha)
1152 {
1153 if (adjustment == RADV_ALPHA_ADJUST_NONE)
1154 return alpha;
1155
1156 LLVMValueRef c30 = LLVMConstInt(ctx->ac.i32, 30, 0);
1157
1158 alpha = LLVMBuildBitCast(ctx->ac.builder, alpha, ctx->ac.f32, "");
1159
1160 if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
1161 alpha = LLVMBuildFPToUI(ctx->ac.builder, alpha, ctx->ac.i32, "");
1162 else
1163 alpha = ac_to_integer(&ctx->ac, alpha);
1164
1165 /* For the integer-like cases, do a natural sign extension.
1166 *
1167 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
1168 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
1169 * exponent.
1170 */
1171 alpha = LLVMBuildShl(ctx->ac.builder, alpha,
1172 adjustment == RADV_ALPHA_ADJUST_SNORM ?
1173 LLVMConstInt(ctx->ac.i32, 7, 0) : c30, "");
1174 alpha = LLVMBuildAShr(ctx->ac.builder, alpha, c30, "");
1175
1176 /* Convert back to the right type. */
1177 if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
1178 LLVMValueRef clamp;
1179 LLVMValueRef neg_one = LLVMConstReal(ctx->ac.f32, -1.0);
1180 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1181 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, alpha, neg_one, "");
1182 alpha = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, alpha, "");
1183 } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
1184 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1185 }
1186
1187 return LLVMBuildBitCast(ctx->ac.builder, alpha, ctx->ac.i32, "");
1188 }
1189
1190 static LLVMValueRef
1191 radv_fixup_vertex_input_fetches(struct radv_shader_context *ctx,
1192 LLVMValueRef value,
1193 unsigned num_channels,
1194 bool is_float)
1195 {
1196 LLVMValueRef zero = is_float ? ctx->ac.f32_0 : ctx->ac.i32_0;
1197 LLVMValueRef one = is_float ? ctx->ac.f32_1 : ctx->ac.i32_1;
1198 LLVMValueRef chan[4];
1199
1200 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMVectorTypeKind) {
1201 unsigned vec_size = LLVMGetVectorSize(LLVMTypeOf(value));
1202
1203 if (num_channels == 4 && num_channels == vec_size)
1204 return value;
1205
1206 num_channels = MIN2(num_channels, vec_size);
1207
1208 for (unsigned i = 0; i < num_channels; i++)
1209 chan[i] = ac_llvm_extract_elem(&ctx->ac, value, i);
1210 } else {
1211 assert(num_channels == 1);
1212 chan[0] = value;
1213 }
1214
1215 for (unsigned i = num_channels; i < 4; i++) {
1216 chan[i] = i == 3 ? one : zero;
1217 chan[i] = ac_to_integer(&ctx->ac, chan[i]);
1218 }
1219
1220 return ac_build_gather_values(&ctx->ac, chan, 4);
1221 }
1222
1223 static void
1224 handle_vs_input_decl(struct radv_shader_context *ctx,
1225 struct nir_variable *variable)
1226 {
1227 LLVMValueRef t_list_ptr = ac_get_arg(&ctx->ac, ctx->args->vertex_buffers);
1228 LLVMValueRef t_offset;
1229 LLVMValueRef t_list;
1230 LLVMValueRef input;
1231 LLVMValueRef buffer_index;
1232 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
1233 uint8_t input_usage_mask =
1234 ctx->args->shader_info->vs.input_usage_mask[variable->data.location];
1235 unsigned num_input_channels = util_last_bit(input_usage_mask);
1236
1237 variable->data.driver_location = variable->data.location * 4;
1238
1239 enum glsl_base_type type = glsl_get_base_type(variable->type);
1240 for (unsigned i = 0; i < attrib_count; ++i) {
1241 LLVMValueRef output[4];
1242 unsigned attrib_index = variable->data.location + i - VERT_ATTRIB_GENERIC0;
1243 unsigned attrib_format = ctx->args->options->key.vs.vertex_attribute_formats[attrib_index];
1244 unsigned data_format = attrib_format & 0x0f;
1245 unsigned num_format = (attrib_format >> 4) & 0x07;
1246 bool is_float = num_format != V_008F0C_BUF_NUM_FORMAT_UINT &&
1247 num_format != V_008F0C_BUF_NUM_FORMAT_SINT;
1248
1249 if (ctx->args->options->key.vs.instance_rate_inputs & (1u << attrib_index)) {
1250 uint32_t divisor = ctx->args->options->key.vs.instance_rate_divisors[attrib_index];
1251
1252 if (divisor) {
1253 buffer_index = ctx->abi.instance_id;
1254
1255 if (divisor != 1) {
1256 buffer_index = LLVMBuildUDiv(ctx->ac.builder, buffer_index,
1257 LLVMConstInt(ctx->ac.i32, divisor, 0), "");
1258 }
1259 } else {
1260 buffer_index = ctx->ac.i32_0;
1261 }
1262
1263 buffer_index = LLVMBuildAdd(ctx->ac.builder,
1264 ac_get_arg(&ctx->ac,
1265 ctx->args->ac.start_instance),\
1266 buffer_index, "");
1267 } else {
1268 buffer_index = LLVMBuildAdd(ctx->ac.builder,
1269 ctx->abi.vertex_id,
1270 ac_get_arg(&ctx->ac,
1271 ctx->args->ac.base_vertex), "");
1272 }
1273
1274 const struct ac_data_format_info *vtx_info = ac_get_data_format_info(data_format);
1275
1276 /* Adjust the number of channels to load based on the vertex
1277 * attribute format.
1278 */
1279 unsigned num_channels = MIN2(num_input_channels, vtx_info->num_channels);
1280 unsigned attrib_binding = ctx->args->options->key.vs.vertex_attribute_bindings[attrib_index];
1281 unsigned attrib_offset = ctx->args->options->key.vs.vertex_attribute_offsets[attrib_index];
1282 unsigned attrib_stride = ctx->args->options->key.vs.vertex_attribute_strides[attrib_index];
1283
1284 if (ctx->args->options->key.vs.post_shuffle & (1 << attrib_index)) {
1285 /* Always load, at least, 3 channels for formats that
1286 * need to be shuffled because X<->Z.
1287 */
1288 num_channels = MAX2(num_channels, 3);
1289 }
1290
1291 t_offset = LLVMConstInt(ctx->ac.i32, attrib_binding, false);
1292 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
1293
1294 /* Perform per-channel vertex fetch operations if unaligned
1295 * access are detected. Only GFX6 and GFX10 are affected.
1296 */
1297 bool unaligned_vertex_fetches = false;
1298 if ((ctx->ac.chip_class == GFX6 || ctx->ac.chip_class == GFX10) &&
1299 vtx_info->chan_format != data_format &&
1300 ((attrib_offset % vtx_info->element_size) ||
1301 (attrib_stride % vtx_info->element_size)))
1302 unaligned_vertex_fetches = true;
1303
1304 if (unaligned_vertex_fetches) {
1305 unsigned chan_format = vtx_info->chan_format;
1306 LLVMValueRef values[4];
1307
1308 assert(ctx->ac.chip_class == GFX6 ||
1309 ctx->ac.chip_class == GFX10);
1310
1311 for (unsigned chan = 0; chan < num_channels; chan++) {
1312 unsigned chan_offset = attrib_offset + chan * vtx_info->chan_byte_size;
1313 LLVMValueRef chan_index = buffer_index;
1314
1315 if (attrib_stride != 0 && chan_offset > attrib_stride) {
1316 LLVMValueRef buffer_offset =
1317 LLVMConstInt(ctx->ac.i32,
1318 chan_offset / attrib_stride, false);
1319
1320 chan_index = LLVMBuildAdd(ctx->ac.builder,
1321 buffer_index,
1322 buffer_offset, "");
1323
1324 chan_offset = chan_offset % attrib_stride;
1325 }
1326
1327 values[chan] = ac_build_struct_tbuffer_load(&ctx->ac, t_list,
1328 chan_index,
1329 LLVMConstInt(ctx->ac.i32, chan_offset, false),
1330 ctx->ac.i32_0, ctx->ac.i32_0, 1,
1331 chan_format, num_format, 0, true);
1332 }
1333
1334 input = ac_build_gather_values(&ctx->ac, values, num_channels);
1335 } else {
1336 if (attrib_stride != 0 && attrib_offset > attrib_stride) {
1337 LLVMValueRef buffer_offset =
1338 LLVMConstInt(ctx->ac.i32,
1339 attrib_offset / attrib_stride, false);
1340
1341 buffer_index = LLVMBuildAdd(ctx->ac.builder,
1342 buffer_index,
1343 buffer_offset, "");
1344
1345 attrib_offset = attrib_offset % attrib_stride;
1346 }
1347
1348 input = ac_build_struct_tbuffer_load(&ctx->ac, t_list,
1349 buffer_index,
1350 LLVMConstInt(ctx->ac.i32, attrib_offset, false),
1351 ctx->ac.i32_0, ctx->ac.i32_0,
1352 num_channels,
1353 data_format, num_format, 0, true);
1354 }
1355
1356 if (ctx->args->options->key.vs.post_shuffle & (1 << attrib_index)) {
1357 LLVMValueRef c[4];
1358 c[0] = ac_llvm_extract_elem(&ctx->ac, input, 2);
1359 c[1] = ac_llvm_extract_elem(&ctx->ac, input, 1);
1360 c[2] = ac_llvm_extract_elem(&ctx->ac, input, 0);
1361 c[3] = ac_llvm_extract_elem(&ctx->ac, input, 3);
1362
1363 input = ac_build_gather_values(&ctx->ac, c, 4);
1364 }
1365
1366 input = radv_fixup_vertex_input_fetches(ctx, input, num_channels,
1367 is_float);
1368
1369 for (unsigned chan = 0; chan < 4; chan++) {
1370 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
1371 output[chan] = LLVMBuildExtractElement(ctx->ac.builder, input, llvm_chan, "");
1372 if (type == GLSL_TYPE_FLOAT16) {
1373 output[chan] = LLVMBuildBitCast(ctx->ac.builder, output[chan], ctx->ac.f32, "");
1374 output[chan] = LLVMBuildFPTrunc(ctx->ac.builder, output[chan], ctx->ac.f16, "");
1375 }
1376 }
1377
1378 unsigned alpha_adjust = (ctx->args->options->key.vs.alpha_adjust >> (attrib_index * 2)) & 3;
1379 output[3] = adjust_vertex_fetch_alpha(ctx, alpha_adjust, output[3]);
1380
1381 for (unsigned chan = 0; chan < 4; chan++) {
1382 output[chan] = ac_to_integer(&ctx->ac, output[chan]);
1383 if (type == GLSL_TYPE_UINT16 || type == GLSL_TYPE_INT16)
1384 output[chan] = LLVMBuildTrunc(ctx->ac.builder, output[chan], ctx->ac.i16, "");
1385
1386 ctx->inputs[ac_llvm_reg_index_soa(variable->data.location + i, chan)] = output[chan];
1387 }
1388 }
1389 }
1390
1391 static void
1392 handle_vs_inputs(struct radv_shader_context *ctx,
1393 struct nir_shader *nir) {
1394 nir_foreach_variable(variable, &nir->inputs)
1395 handle_vs_input_decl(ctx, variable);
1396 }
1397
1398 static void
1399 prepare_interp_optimize(struct radv_shader_context *ctx,
1400 struct nir_shader *nir)
1401 {
1402 bool uses_center = false;
1403 bool uses_centroid = false;
1404 nir_foreach_variable(variable, &nir->inputs) {
1405 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
1406 variable->data.sample)
1407 continue;
1408
1409 if (variable->data.centroid)
1410 uses_centroid = true;
1411 else
1412 uses_center = true;
1413 }
1414
1415 ctx->abi.persp_centroid = ac_get_arg(&ctx->ac, ctx->args->ac.persp_centroid);
1416 ctx->abi.linear_centroid = ac_get_arg(&ctx->ac, ctx->args->ac.linear_centroid);
1417
1418 if (uses_center && uses_centroid) {
1419 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT,
1420 ac_get_arg(&ctx->ac, ctx->args->ac.prim_mask),
1421 ctx->ac.i32_0, "");
1422 ctx->abi.persp_centroid =
1423 LLVMBuildSelect(ctx->ac.builder, sel,
1424 ac_get_arg(&ctx->ac, ctx->args->ac.persp_center),
1425 ctx->abi.persp_centroid, "");
1426 ctx->abi.linear_centroid =
1427 LLVMBuildSelect(ctx->ac.builder, sel,
1428 ac_get_arg(&ctx->ac, ctx->args->ac.linear_center),
1429 ctx->abi.linear_centroid, "");
1430 }
1431 }
1432
1433 static void
1434 scan_shader_output_decl(struct radv_shader_context *ctx,
1435 struct nir_variable *variable,
1436 struct nir_shader *shader,
1437 gl_shader_stage stage)
1438 {
1439 int idx = variable->data.location + variable->data.index;
1440 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
1441 uint64_t mask_attribs;
1442
1443 variable->data.driver_location = idx * 4;
1444
1445 /* tess ctrl has it's own load/store paths for outputs */
1446 if (stage == MESA_SHADER_TESS_CTRL)
1447 return;
1448
1449 if (variable->data.compact) {
1450 unsigned component_count = variable->data.location_frac +
1451 glsl_get_length(variable->type);
1452 attrib_count = (component_count + 3) / 4;
1453 }
1454
1455 mask_attribs = ((1ull << attrib_count) - 1) << idx;
1456
1457 ctx->output_mask |= mask_attribs;
1458 }
1459
1460
1461 /* Initialize arguments for the shader export intrinsic */
1462 static void
1463 si_llvm_init_export_args(struct radv_shader_context *ctx,
1464 LLVMValueRef *values,
1465 unsigned enabled_channels,
1466 unsigned target,
1467 struct ac_export_args *args)
1468 {
1469 /* Specify the channels that are enabled. */
1470 args->enabled_channels = enabled_channels;
1471
1472 /* Specify whether the EXEC mask represents the valid mask */
1473 args->valid_mask = 0;
1474
1475 /* Specify whether this is the last export */
1476 args->done = 0;
1477
1478 /* Specify the target we are exporting */
1479 args->target = target;
1480
1481 args->compr = false;
1482 args->out[0] = LLVMGetUndef(ctx->ac.f32);
1483 args->out[1] = LLVMGetUndef(ctx->ac.f32);
1484 args->out[2] = LLVMGetUndef(ctx->ac.f32);
1485 args->out[3] = LLVMGetUndef(ctx->ac.f32);
1486
1487 if (!values)
1488 return;
1489
1490 bool is_16bit = ac_get_type_size(LLVMTypeOf(values[0])) == 2;
1491 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1492 unsigned index = target - V_008DFC_SQ_EXP_MRT;
1493 unsigned col_format = (ctx->args->options->key.fs.col_format >> (4 * index)) & 0xf;
1494 bool is_int8 = (ctx->args->options->key.fs.is_int8 >> index) & 1;
1495 bool is_int10 = (ctx->args->options->key.fs.is_int10 >> index) & 1;
1496 unsigned chan;
1497
1498 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
1499 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
1500 unsigned bits, bool hi) = NULL;
1501
1502 switch(col_format) {
1503 case V_028714_SPI_SHADER_ZERO:
1504 args->enabled_channels = 0; /* writemask */
1505 args->target = V_008DFC_SQ_EXP_NULL;
1506 break;
1507
1508 case V_028714_SPI_SHADER_32_R:
1509 args->enabled_channels = 1;
1510 args->out[0] = values[0];
1511 break;
1512
1513 case V_028714_SPI_SHADER_32_GR:
1514 args->enabled_channels = 0x3;
1515 args->out[0] = values[0];
1516 args->out[1] = values[1];
1517 break;
1518
1519 case V_028714_SPI_SHADER_32_AR:
1520 if (ctx->ac.chip_class >= GFX10) {
1521 args->enabled_channels = 0x3;
1522 args->out[0] = values[0];
1523 args->out[1] = values[3];
1524 } else {
1525 args->enabled_channels = 0x9;
1526 args->out[0] = values[0];
1527 args->out[3] = values[3];
1528 }
1529 break;
1530
1531 case V_028714_SPI_SHADER_FP16_ABGR:
1532 args->enabled_channels = 0x5;
1533 packf = ac_build_cvt_pkrtz_f16;
1534 if (is_16bit) {
1535 for (unsigned chan = 0; chan < 4; chan++)
1536 values[chan] = LLVMBuildFPExt(ctx->ac.builder,
1537 values[chan],
1538 ctx->ac.f32, "");
1539 }
1540 break;
1541
1542 case V_028714_SPI_SHADER_UNORM16_ABGR:
1543 args->enabled_channels = 0x5;
1544 packf = ac_build_cvt_pknorm_u16;
1545 break;
1546
1547 case V_028714_SPI_SHADER_SNORM16_ABGR:
1548 args->enabled_channels = 0x5;
1549 packf = ac_build_cvt_pknorm_i16;
1550 break;
1551
1552 case V_028714_SPI_SHADER_UINT16_ABGR:
1553 args->enabled_channels = 0x5;
1554 packi = ac_build_cvt_pk_u16;
1555 if (is_16bit) {
1556 for (unsigned chan = 0; chan < 4; chan++)
1557 values[chan] = LLVMBuildZExt(ctx->ac.builder,
1558 ac_to_integer(&ctx->ac, values[chan]),
1559 ctx->ac.i32, "");
1560 }
1561 break;
1562
1563 case V_028714_SPI_SHADER_SINT16_ABGR:
1564 args->enabled_channels = 0x5;
1565 packi = ac_build_cvt_pk_i16;
1566 if (is_16bit) {
1567 for (unsigned chan = 0; chan < 4; chan++)
1568 values[chan] = LLVMBuildSExt(ctx->ac.builder,
1569 ac_to_integer(&ctx->ac, values[chan]),
1570 ctx->ac.i32, "");
1571 }
1572 break;
1573
1574 default:
1575 case V_028714_SPI_SHADER_32_ABGR:
1576 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
1577 break;
1578 }
1579
1580 /* Pack f16 or norm_i16/u16. */
1581 if (packf) {
1582 for (chan = 0; chan < 2; chan++) {
1583 LLVMValueRef pack_args[2] = {
1584 values[2 * chan],
1585 values[2 * chan + 1]
1586 };
1587 LLVMValueRef packed;
1588
1589 packed = packf(&ctx->ac, pack_args);
1590 args->out[chan] = ac_to_float(&ctx->ac, packed);
1591 }
1592 args->compr = 1; /* COMPR flag */
1593 }
1594
1595 /* Pack i16/u16. */
1596 if (packi) {
1597 for (chan = 0; chan < 2; chan++) {
1598 LLVMValueRef pack_args[2] = {
1599 ac_to_integer(&ctx->ac, values[2 * chan]),
1600 ac_to_integer(&ctx->ac, values[2 * chan + 1])
1601 };
1602 LLVMValueRef packed;
1603
1604 packed = packi(&ctx->ac, pack_args,
1605 is_int8 ? 8 : is_int10 ? 10 : 16,
1606 chan == 1);
1607 args->out[chan] = ac_to_float(&ctx->ac, packed);
1608 }
1609 args->compr = 1; /* COMPR flag */
1610 }
1611 return;
1612 }
1613
1614 if (is_16bit) {
1615 for (unsigned chan = 0; chan < 4; chan++) {
1616 values[chan] = LLVMBuildBitCast(ctx->ac.builder, values[chan], ctx->ac.i16, "");
1617 args->out[chan] = LLVMBuildZExt(ctx->ac.builder, values[chan], ctx->ac.i32, "");
1618 }
1619 } else
1620 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
1621
1622 for (unsigned i = 0; i < 4; ++i)
1623 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
1624 }
1625
1626 static void
1627 radv_export_param(struct radv_shader_context *ctx, unsigned index,
1628 LLVMValueRef *values, unsigned enabled_channels)
1629 {
1630 struct ac_export_args args;
1631
1632 si_llvm_init_export_args(ctx, values, enabled_channels,
1633 V_008DFC_SQ_EXP_PARAM + index, &args);
1634 ac_build_export(&ctx->ac, &args);
1635 }
1636
1637 static LLVMValueRef
1638 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
1639 {
1640 LLVMValueRef output = ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
1641 return LLVMBuildLoad(ctx->ac.builder, output, "");
1642 }
1643
1644 static void
1645 radv_emit_stream_output(struct radv_shader_context *ctx,
1646 LLVMValueRef const *so_buffers,
1647 LLVMValueRef const *so_write_offsets,
1648 const struct radv_stream_output *output,
1649 struct radv_shader_output_values *shader_out)
1650 {
1651 unsigned num_comps = util_bitcount(output->component_mask);
1652 unsigned buf = output->buffer;
1653 unsigned offset = output->offset;
1654 unsigned start;
1655 LLVMValueRef out[4];
1656
1657 assert(num_comps && num_comps <= 4);
1658 if (!num_comps || num_comps > 4)
1659 return;
1660
1661 /* Get the first component. */
1662 start = ffs(output->component_mask) - 1;
1663
1664 /* Load the output as int. */
1665 for (int i = 0; i < num_comps; i++) {
1666 out[i] = ac_to_integer(&ctx->ac, shader_out->values[start + i]);
1667 }
1668
1669 /* Pack the output. */
1670 LLVMValueRef vdata = NULL;
1671
1672 switch (num_comps) {
1673 case 1: /* as i32 */
1674 vdata = out[0];
1675 break;
1676 case 2: /* as v2i32 */
1677 case 3: /* as v4i32 (aligned to 4) */
1678 out[3] = LLVMGetUndef(ctx->ac.i32);
1679 /* fall through */
1680 case 4: /* as v4i32 */
1681 vdata = ac_build_gather_values(&ctx->ac, out,
1682 !ac_has_vec3_support(ctx->ac.chip_class, false) ?
1683 util_next_power_of_two(num_comps) :
1684 num_comps);
1685 break;
1686 }
1687
1688 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf],
1689 vdata, num_comps, so_write_offsets[buf],
1690 ctx->ac.i32_0, offset,
1691 ac_glc | ac_slc);
1692 }
1693
1694 static void
1695 radv_emit_streamout(struct radv_shader_context *ctx, unsigned stream)
1696 {
1697 int i;
1698
1699 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1700 assert(ctx->args->streamout_config.used);
1701 LLVMValueRef so_vtx_count =
1702 ac_build_bfe(&ctx->ac,
1703 ac_get_arg(&ctx->ac, ctx->args->streamout_config),
1704 LLVMConstInt(ctx->ac.i32, 16, false),
1705 LLVMConstInt(ctx->ac.i32, 7, false), false);
1706
1707 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
1708
1709 /* can_emit = tid < so_vtx_count; */
1710 LLVMValueRef can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
1711 tid, so_vtx_count, "");
1712
1713 /* Emit the streamout code conditionally. This actually avoids
1714 * out-of-bounds buffer access. The hw tells us via the SGPR
1715 * (so_vtx_count) which threads are allowed to emit streamout data.
1716 */
1717 ac_build_ifcc(&ctx->ac, can_emit, 6501);
1718 {
1719 /* The buffer offset is computed as follows:
1720 * ByteOffset = streamout_offset[buffer_id]*4 +
1721 * (streamout_write_index + thread_id)*stride[buffer_id] +
1722 * attrib_offset
1723 */
1724 LLVMValueRef so_write_index =
1725 ac_get_arg(&ctx->ac, ctx->args->streamout_write_idx);
1726
1727 /* Compute (streamout_write_index + thread_id). */
1728 so_write_index =
1729 LLVMBuildAdd(ctx->ac.builder, so_write_index, tid, "");
1730
1731 /* Load the descriptor and compute the write offset for each
1732 * enabled buffer.
1733 */
1734 LLVMValueRef so_write_offset[4] = {};
1735 LLVMValueRef so_buffers[4] = {};
1736 LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac, ctx->args->streamout_buffers);
1737
1738 for (i = 0; i < 4; i++) {
1739 uint16_t stride = ctx->args->shader_info->so.strides[i];
1740
1741 if (!stride)
1742 continue;
1743
1744 LLVMValueRef offset =
1745 LLVMConstInt(ctx->ac.i32, i, false);
1746
1747 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac,
1748 buf_ptr, offset);
1749
1750 LLVMValueRef so_offset =
1751 ac_get_arg(&ctx->ac, ctx->args->streamout_offset[i]);
1752
1753 so_offset = LLVMBuildMul(ctx->ac.builder, so_offset,
1754 LLVMConstInt(ctx->ac.i32, 4, false), "");
1755
1756 so_write_offset[i] =
1757 ac_build_imad(&ctx->ac, so_write_index,
1758 LLVMConstInt(ctx->ac.i32,
1759 stride * 4, false),
1760 so_offset);
1761 }
1762
1763 /* Write streamout data. */
1764 for (i = 0; i < ctx->args->shader_info->so.num_outputs; i++) {
1765 struct radv_shader_output_values shader_out = {};
1766 struct radv_stream_output *output =
1767 &ctx->args->shader_info->so.outputs[i];
1768
1769 if (stream != output->stream)
1770 continue;
1771
1772 for (int j = 0; j < 4; j++) {
1773 shader_out.values[j] =
1774 radv_load_output(ctx, output->location, j);
1775 }
1776
1777 radv_emit_stream_output(ctx, so_buffers,so_write_offset,
1778 output, &shader_out);
1779 }
1780 }
1781 ac_build_endif(&ctx->ac, 6501);
1782 }
1783
1784 static void
1785 radv_build_param_exports(struct radv_shader_context *ctx,
1786 struct radv_shader_output_values *outputs,
1787 unsigned noutput,
1788 struct radv_vs_output_info *outinfo,
1789 bool export_clip_dists)
1790 {
1791 unsigned param_count = 0;
1792
1793 for (unsigned i = 0; i < noutput; i++) {
1794 unsigned slot_name = outputs[i].slot_name;
1795 unsigned usage_mask = outputs[i].usage_mask;
1796
1797 if (slot_name != VARYING_SLOT_LAYER &&
1798 slot_name != VARYING_SLOT_PRIMITIVE_ID &&
1799 slot_name != VARYING_SLOT_CLIP_DIST0 &&
1800 slot_name != VARYING_SLOT_CLIP_DIST1 &&
1801 slot_name < VARYING_SLOT_VAR0)
1802 continue;
1803
1804 if ((slot_name == VARYING_SLOT_CLIP_DIST0 ||
1805 slot_name == VARYING_SLOT_CLIP_DIST1) && !export_clip_dists)
1806 continue;
1807
1808 radv_export_param(ctx, param_count, outputs[i].values, usage_mask);
1809
1810 assert(i < ARRAY_SIZE(outinfo->vs_output_param_offset));
1811 outinfo->vs_output_param_offset[slot_name] = param_count++;
1812 }
1813
1814 outinfo->param_exports = param_count;
1815 }
1816
1817 /* Generate export instructions for hardware VS shader stage or NGG GS stage
1818 * (position and parameter data only).
1819 */
1820 static void
1821 radv_llvm_export_vs(struct radv_shader_context *ctx,
1822 struct radv_shader_output_values *outputs,
1823 unsigned noutput,
1824 struct radv_vs_output_info *outinfo,
1825 bool export_clip_dists)
1826 {
1827 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_value = NULL;
1828 struct ac_export_args pos_args[4] = {};
1829 unsigned pos_idx, index;
1830 int i;
1831
1832 /* Build position exports */
1833 for (i = 0; i < noutput; i++) {
1834 switch (outputs[i].slot_name) {
1835 case VARYING_SLOT_POS:
1836 si_llvm_init_export_args(ctx, outputs[i].values, 0xf,
1837 V_008DFC_SQ_EXP_POS, &pos_args[0]);
1838 break;
1839 case VARYING_SLOT_PSIZ:
1840 psize_value = outputs[i].values[0];
1841 break;
1842 case VARYING_SLOT_LAYER:
1843 layer_value = outputs[i].values[0];
1844 break;
1845 case VARYING_SLOT_VIEWPORT:
1846 viewport_value = outputs[i].values[0];
1847 break;
1848 case VARYING_SLOT_CLIP_DIST0:
1849 case VARYING_SLOT_CLIP_DIST1:
1850 index = 2 + outputs[i].slot_index;
1851 si_llvm_init_export_args(ctx, outputs[i].values, 0xf,
1852 V_008DFC_SQ_EXP_POS + index,
1853 &pos_args[index]);
1854 break;
1855 default:
1856 break;
1857 }
1858 }
1859
1860 /* We need to add the position output manually if it's missing. */
1861 if (!pos_args[0].out[0]) {
1862 pos_args[0].enabled_channels = 0xf; /* writemask */
1863 pos_args[0].valid_mask = 0; /* EXEC mask */
1864 pos_args[0].done = 0; /* last export? */
1865 pos_args[0].target = V_008DFC_SQ_EXP_POS;
1866 pos_args[0].compr = 0; /* COMPR flag */
1867 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
1868 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
1869 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
1870 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
1871 }
1872
1873 if (outinfo->writes_pointsize ||
1874 outinfo->writes_layer ||
1875 outinfo->writes_viewport_index) {
1876 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
1877 (outinfo->writes_layer == true ? 4 : 0));
1878 pos_args[1].valid_mask = 0;
1879 pos_args[1].done = 0;
1880 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
1881 pos_args[1].compr = 0;
1882 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
1883 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
1884 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
1885 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
1886
1887 if (outinfo->writes_pointsize == true)
1888 pos_args[1].out[0] = psize_value;
1889 if (outinfo->writes_layer == true)
1890 pos_args[1].out[2] = layer_value;
1891 if (outinfo->writes_viewport_index == true) {
1892 if (ctx->args->options->chip_class >= GFX9) {
1893 /* GFX9 has the layer in out.z[10:0] and the viewport
1894 * index in out.z[19:16].
1895 */
1896 LLVMValueRef v = viewport_value;
1897 v = ac_to_integer(&ctx->ac, v);
1898 v = LLVMBuildShl(ctx->ac.builder, v,
1899 LLVMConstInt(ctx->ac.i32, 16, false),
1900 "");
1901 v = LLVMBuildOr(ctx->ac.builder, v,
1902 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
1903
1904 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
1905 pos_args[1].enabled_channels |= 1 << 2;
1906 } else {
1907 pos_args[1].out[3] = viewport_value;
1908 pos_args[1].enabled_channels |= 1 << 3;
1909 }
1910 }
1911 }
1912
1913 for (i = 0; i < 4; i++) {
1914 if (pos_args[i].out[0])
1915 outinfo->pos_exports++;
1916 }
1917
1918 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
1919 * Setting valid_mask=1 prevents it and has no other effect.
1920 */
1921 if (ctx->ac.family == CHIP_NAVI10 ||
1922 ctx->ac.family == CHIP_NAVI12 ||
1923 ctx->ac.family == CHIP_NAVI14)
1924 pos_args[0].valid_mask = 1;
1925
1926 pos_idx = 0;
1927 for (i = 0; i < 4; i++) {
1928 if (!pos_args[i].out[0])
1929 continue;
1930
1931 /* Specify the target we are exporting */
1932 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
1933
1934 if (pos_idx == outinfo->pos_exports)
1935 /* Specify that this is the last export */
1936 pos_args[i].done = 1;
1937
1938 ac_build_export(&ctx->ac, &pos_args[i]);
1939 }
1940
1941 /* Build parameter exports */
1942 radv_build_param_exports(ctx, outputs, noutput, outinfo, export_clip_dists);
1943 }
1944
1945 static void
1946 handle_vs_outputs_post(struct radv_shader_context *ctx,
1947 bool export_prim_id,
1948 bool export_clip_dists,
1949 struct radv_vs_output_info *outinfo)
1950 {
1951 struct radv_shader_output_values *outputs;
1952 unsigned noutput = 0;
1953
1954 if (ctx->args->options->key.has_multiview_view_index) {
1955 LLVMValueRef* tmp_out = &ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
1956 if(!*tmp_out) {
1957 for(unsigned i = 0; i < 4; ++i)
1958 ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
1959 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
1960 }
1961
1962 LLVMValueRef view_index = ac_get_arg(&ctx->ac, ctx->args->ac.view_index);
1963 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, view_index), *tmp_out);
1964 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
1965 }
1966
1967 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
1968 sizeof(outinfo->vs_output_param_offset));
1969 outinfo->pos_exports = 0;
1970
1971 if (!ctx->args->options->use_ngg_streamout &&
1972 ctx->args->shader_info->so.num_outputs &&
1973 !ctx->args->is_gs_copy_shader) {
1974 /* The GS copy shader emission already emits streamout. */
1975 radv_emit_streamout(ctx, 0);
1976 }
1977
1978 /* Allocate a temporary array for the output values. */
1979 unsigned num_outputs = util_bitcount64(ctx->output_mask) + export_prim_id;
1980 outputs = malloc(num_outputs * sizeof(outputs[0]));
1981
1982 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
1983 if (!(ctx->output_mask & (1ull << i)))
1984 continue;
1985
1986 outputs[noutput].slot_name = i;
1987 outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
1988
1989 if (ctx->stage == MESA_SHADER_VERTEX &&
1990 !ctx->args->is_gs_copy_shader) {
1991 outputs[noutput].usage_mask =
1992 ctx->args->shader_info->vs.output_usage_mask[i];
1993 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
1994 outputs[noutput].usage_mask =
1995 ctx->args->shader_info->tes.output_usage_mask[i];
1996 } else {
1997 assert(ctx->args->is_gs_copy_shader);
1998 outputs[noutput].usage_mask =
1999 ctx->args->shader_info->gs.output_usage_mask[i];
2000 }
2001
2002 for (unsigned j = 0; j < 4; j++) {
2003 outputs[noutput].values[j] =
2004 ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2005 }
2006
2007 noutput++;
2008 }
2009
2010 /* Export PrimitiveID. */
2011 if (export_prim_id) {
2012 outputs[noutput].slot_name = VARYING_SLOT_PRIMITIVE_ID;
2013 outputs[noutput].slot_index = 0;
2014 outputs[noutput].usage_mask = 0x1;
2015 outputs[noutput].values[0] =
2016 ac_get_arg(&ctx->ac, ctx->args->vs_prim_id);
2017 for (unsigned j = 1; j < 4; j++)
2018 outputs[noutput].values[j] = ctx->ac.f32_0;
2019 noutput++;
2020 }
2021
2022 radv_llvm_export_vs(ctx, outputs, noutput, outinfo, export_clip_dists);
2023
2024 free(outputs);
2025 }
2026
2027 static void
2028 handle_es_outputs_post(struct radv_shader_context *ctx,
2029 struct radv_es_output_info *outinfo)
2030 {
2031 int j;
2032 LLVMValueRef lds_base = NULL;
2033
2034 if (ctx->ac.chip_class >= GFX9) {
2035 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
2036 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
2037 LLVMValueRef wave_idx =
2038 ac_unpack_param(&ctx->ac,
2039 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 24, 4);
2040 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
2041 LLVMBuildMul(ctx->ac.builder, wave_idx,
2042 LLVMConstInt(ctx->ac.i32,
2043 ctx->ac.wave_size, false), ""), "");
2044 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
2045 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
2046 }
2047
2048 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2049 LLVMValueRef dw_addr = NULL;
2050 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2051 unsigned output_usage_mask;
2052 int param_index;
2053
2054 if (!(ctx->output_mask & (1ull << i)))
2055 continue;
2056
2057 if (ctx->stage == MESA_SHADER_VERTEX) {
2058 output_usage_mask =
2059 ctx->args->shader_info->vs.output_usage_mask[i];
2060 } else {
2061 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2062 output_usage_mask =
2063 ctx->args->shader_info->tes.output_usage_mask[i];
2064 }
2065
2066 param_index = shader_io_get_unique_index(i);
2067
2068 if (lds_base) {
2069 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2070 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
2071 "");
2072 }
2073
2074 for (j = 0; j < 4; j++) {
2075 if (!(output_usage_mask & (1 << j)))
2076 continue;
2077
2078 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2079 out_val = ac_to_integer(&ctx->ac, out_val);
2080 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
2081
2082 if (ctx->ac.chip_class >= GFX9) {
2083 LLVMValueRef dw_addr_offset =
2084 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2085 LLVMConstInt(ctx->ac.i32,
2086 j, false), "");
2087
2088 ac_lds_store(&ctx->ac, dw_addr_offset, out_val);
2089 } else {
2090 ac_build_buffer_store_dword(&ctx->ac,
2091 ctx->esgs_ring,
2092 out_val, 1,
2093 NULL,
2094 ac_get_arg(&ctx->ac, ctx->args->es2gs_offset),
2095 (4 * param_index + j) * 4,
2096 ac_glc | ac_slc | ac_swizzled);
2097 }
2098 }
2099 }
2100 }
2101
2102 static void
2103 handle_ls_outputs_post(struct radv_shader_context *ctx)
2104 {
2105 LLVMValueRef vertex_id = ctx->rel_auto_id;
2106 uint32_t num_tcs_inputs = util_last_bit64(ctx->args->shader_info->vs.ls_outputs_written);
2107 LLVMValueRef vertex_dw_stride = LLVMConstInt(ctx->ac.i32, num_tcs_inputs * 4, false);
2108 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
2109 vertex_dw_stride, "");
2110
2111 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2112 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2113
2114 if (!(ctx->output_mask & (1ull << i)))
2115 continue;
2116
2117 int param = shader_io_get_unique_index(i);
2118 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
2119 LLVMConstInt(ctx->ac.i32, param * 4, false),
2120 "");
2121 for (unsigned j = 0; j < 4; j++) {
2122 LLVMValueRef value = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2123 value = ac_to_integer(&ctx->ac, value);
2124 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
2125 ac_lds_store(&ctx->ac, dw_addr, value);
2126 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2127 }
2128 }
2129 }
2130
2131 static LLVMValueRef get_wave_id_in_tg(struct radv_shader_context *ctx)
2132 {
2133 return ac_unpack_param(&ctx->ac,
2134 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 24, 4);
2135 }
2136
2137 static LLVMValueRef get_tgsize(struct radv_shader_context *ctx)
2138 {
2139 return ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 28, 4);
2140 }
2141
2142 static LLVMValueRef get_thread_id_in_tg(struct radv_shader_context *ctx)
2143 {
2144 LLVMBuilderRef builder = ctx->ac.builder;
2145 LLVMValueRef tmp;
2146 tmp = LLVMBuildMul(builder, get_wave_id_in_tg(ctx),
2147 LLVMConstInt(ctx->ac.i32, ctx->ac.wave_size, false), "");
2148 return LLVMBuildAdd(builder, tmp, ac_get_thread_id(&ctx->ac), "");
2149 }
2150
2151 static LLVMValueRef ngg_get_vtx_cnt(struct radv_shader_context *ctx)
2152 {
2153 return ac_build_bfe(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_tg_info),
2154 LLVMConstInt(ctx->ac.i32, 12, false),
2155 LLVMConstInt(ctx->ac.i32, 9, false),
2156 false);
2157 }
2158
2159 static LLVMValueRef ngg_get_prim_cnt(struct radv_shader_context *ctx)
2160 {
2161 return ac_build_bfe(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_tg_info),
2162 LLVMConstInt(ctx->ac.i32, 22, false),
2163 LLVMConstInt(ctx->ac.i32, 9, false),
2164 false);
2165 }
2166
2167 static LLVMValueRef ngg_get_ordered_id(struct radv_shader_context *ctx)
2168 {
2169 return ac_build_bfe(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_tg_info),
2170 ctx->ac.i32_0,
2171 LLVMConstInt(ctx->ac.i32, 12, false),
2172 false);
2173 }
2174
2175 static LLVMValueRef
2176 ngg_gs_get_vertex_storage(struct radv_shader_context *ctx)
2177 {
2178 unsigned num_outputs = util_bitcount64(ctx->output_mask);
2179
2180 if (ctx->args->options->key.has_multiview_view_index)
2181 num_outputs++;
2182
2183 LLVMTypeRef elements[2] = {
2184 LLVMArrayType(ctx->ac.i32, 4 * num_outputs),
2185 LLVMArrayType(ctx->ac.i8, 4),
2186 };
2187 LLVMTypeRef type = LLVMStructTypeInContext(ctx->ac.context, elements, 2, false);
2188 type = LLVMPointerType(LLVMArrayType(type, 0), AC_ADDR_SPACE_LDS);
2189 return LLVMBuildBitCast(ctx->ac.builder, ctx->gs_ngg_emit, type, "");
2190 }
2191
2192 /**
2193 * Return a pointer to the LDS storage reserved for the N'th vertex, where N
2194 * is in emit order; that is:
2195 * - during the epilogue, N is the threadidx (relative to the entire threadgroup)
2196 * - during vertex emit, i.e. while the API GS shader invocation is running,
2197 * N = threadidx * gs_max_out_vertices + emitidx
2198 *
2199 * Goals of the LDS memory layout:
2200 * 1. Eliminate bank conflicts on write for geometry shaders that have all emits
2201 * in uniform control flow
2202 * 2. Eliminate bank conflicts on read for export if, additionally, there is no
2203 * culling
2204 * 3. Agnostic to the number of waves (since we don't know it before compiling)
2205 * 4. Allow coalescing of LDS instructions (ds_write_b128 etc.)
2206 * 5. Avoid wasting memory.
2207 *
2208 * We use an AoS layout due to point 4 (this also helps point 3). In an AoS
2209 * layout, elimination of bank conflicts requires that each vertex occupy an
2210 * odd number of dwords. We use the additional dword to store the output stream
2211 * index as well as a flag to indicate whether this vertex ends a primitive
2212 * for rasterization.
2213 *
2214 * Swizzling is required to satisfy points 1 and 2 simultaneously.
2215 *
2216 * Vertices are stored in export order (gsthread * gs_max_out_vertices + emitidx).
2217 * Indices are swizzled in groups of 32, which ensures point 1 without
2218 * disturbing point 2.
2219 *
2220 * \return an LDS pointer to type {[N x i32], [4 x i8]}
2221 */
2222 static LLVMValueRef
2223 ngg_gs_vertex_ptr(struct radv_shader_context *ctx, LLVMValueRef vertexidx)
2224 {
2225 LLVMBuilderRef builder = ctx->ac.builder;
2226 LLVMValueRef storage = ngg_gs_get_vertex_storage(ctx);
2227
2228 /* gs_max_out_vertices = 2^(write_stride_2exp) * some odd number */
2229 unsigned write_stride_2exp = ffs(ctx->shader->info.gs.vertices_out) - 1;
2230 if (write_stride_2exp) {
2231 LLVMValueRef row =
2232 LLVMBuildLShr(builder, vertexidx,
2233 LLVMConstInt(ctx->ac.i32, 5, false), "");
2234 LLVMValueRef swizzle =
2235 LLVMBuildAnd(builder, row,
2236 LLVMConstInt(ctx->ac.i32, (1u << write_stride_2exp) - 1,
2237 false), "");
2238 vertexidx = LLVMBuildXor(builder, vertexidx, swizzle, "");
2239 }
2240
2241 return ac_build_gep0(&ctx->ac, storage, vertexidx);
2242 }
2243
2244 static LLVMValueRef
2245 ngg_gs_emit_vertex_ptr(struct radv_shader_context *ctx, LLVMValueRef gsthread,
2246 LLVMValueRef emitidx)
2247 {
2248 LLVMBuilderRef builder = ctx->ac.builder;
2249 LLVMValueRef tmp;
2250
2251 tmp = LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false);
2252 tmp = LLVMBuildMul(builder, tmp, gsthread, "");
2253 const LLVMValueRef vertexidx = LLVMBuildAdd(builder, tmp, emitidx, "");
2254 return ngg_gs_vertex_ptr(ctx, vertexidx);
2255 }
2256
2257 static LLVMValueRef
2258 ngg_gs_get_emit_output_ptr(struct radv_shader_context *ctx, LLVMValueRef vertexptr,
2259 unsigned out_idx)
2260 {
2261 LLVMValueRef gep_idx[3] = {
2262 ctx->ac.i32_0, /* implied C-style array */
2263 ctx->ac.i32_0, /* first struct entry */
2264 LLVMConstInt(ctx->ac.i32, out_idx, false),
2265 };
2266 return LLVMBuildGEP(ctx->ac.builder, vertexptr, gep_idx, 3, "");
2267 }
2268
2269 static LLVMValueRef
2270 ngg_gs_get_emit_primflag_ptr(struct radv_shader_context *ctx, LLVMValueRef vertexptr,
2271 unsigned stream)
2272 {
2273 LLVMValueRef gep_idx[3] = {
2274 ctx->ac.i32_0, /* implied C-style array */
2275 ctx->ac.i32_1, /* second struct entry */
2276 LLVMConstInt(ctx->ac.i32, stream, false),
2277 };
2278 return LLVMBuildGEP(ctx->ac.builder, vertexptr, gep_idx, 3, "");
2279 }
2280
2281 static struct radv_stream_output *
2282 radv_get_stream_output_by_loc(struct radv_streamout_info *so, unsigned location)
2283 {
2284 for (unsigned i = 0; i < so->num_outputs; ++i) {
2285 if (so->outputs[i].location == location)
2286 return &so->outputs[i];
2287 }
2288
2289 return NULL;
2290 }
2291
2292 static void build_streamout_vertex(struct radv_shader_context *ctx,
2293 LLVMValueRef *so_buffer, LLVMValueRef *wg_offset_dw,
2294 unsigned stream, LLVMValueRef offset_vtx,
2295 LLVMValueRef vertexptr)
2296 {
2297 struct radv_streamout_info *so = &ctx->args->shader_info->so;
2298 LLVMBuilderRef builder = ctx->ac.builder;
2299 LLVMValueRef offset[4] = {};
2300 LLVMValueRef tmp;
2301
2302 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2303 if (!wg_offset_dw[buffer])
2304 continue;
2305
2306 tmp = LLVMBuildMul(builder, offset_vtx,
2307 LLVMConstInt(ctx->ac.i32, so->strides[buffer], false), "");
2308 tmp = LLVMBuildAdd(builder, wg_offset_dw[buffer], tmp, "");
2309 offset[buffer] = LLVMBuildShl(builder, tmp, LLVMConstInt(ctx->ac.i32, 2, false), "");
2310 }
2311
2312 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2313 struct radv_shader_output_values outputs[AC_LLVM_MAX_OUTPUTS];
2314 unsigned noutput = 0;
2315 unsigned out_idx = 0;
2316
2317 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2318 unsigned output_usage_mask =
2319 ctx->args->shader_info->gs.output_usage_mask[i];
2320 uint8_t output_stream =
2321 output_stream = ctx->args->shader_info->gs.output_streams[i];
2322
2323 if (!(ctx->output_mask & (1ull << i)) ||
2324 output_stream != stream)
2325 continue;
2326
2327 outputs[noutput].slot_name = i;
2328 outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
2329 outputs[noutput].usage_mask = output_usage_mask;
2330
2331 int length = util_last_bit(output_usage_mask);
2332
2333 for (unsigned j = 0; j < length; j++, out_idx++) {
2334 if (!(output_usage_mask & (1 << j)))
2335 continue;
2336
2337 tmp = ac_build_gep0(&ctx->ac, vertexptr,
2338 LLVMConstInt(ctx->ac.i32, out_idx, false));
2339 outputs[noutput].values[j] = LLVMBuildLoad(builder, tmp, "");
2340 }
2341
2342 for (unsigned j = length; j < 4; j++)
2343 outputs[noutput].values[j] = LLVMGetUndef(ctx->ac.f32);
2344
2345 noutput++;
2346 }
2347
2348 for (unsigned i = 0; i < noutput; i++) {
2349 struct radv_stream_output *output =
2350 radv_get_stream_output_by_loc(so, outputs[i].slot_name);
2351
2352 if (!output ||
2353 output->stream != stream)
2354 continue;
2355
2356 struct radv_shader_output_values out = {};
2357
2358 for (unsigned j = 0; j < 4; j++) {
2359 out.values[j] = outputs[i].values[j];
2360 }
2361
2362 radv_emit_stream_output(ctx, so_buffer, offset, output, &out);
2363 }
2364 } else {
2365 for (unsigned i = 0; i < so->num_outputs; ++i) {
2366 struct radv_stream_output *output =
2367 &ctx->args->shader_info->so.outputs[i];
2368
2369 if (stream != output->stream)
2370 continue;
2371
2372 struct radv_shader_output_values out = {};
2373
2374 for (unsigned comp = 0; comp < 4; comp++) {
2375 if (!(output->component_mask & (1 << comp)))
2376 continue;
2377
2378 tmp = ac_build_gep0(&ctx->ac, vertexptr,
2379 LLVMConstInt(ctx->ac.i32, 4 * i + comp, false));
2380 out.values[comp] = LLVMBuildLoad(builder, tmp, "");
2381 }
2382
2383 radv_emit_stream_output(ctx, so_buffer, offset, output, &out);
2384 }
2385 }
2386 }
2387
2388 struct ngg_streamout {
2389 LLVMValueRef num_vertices;
2390
2391 /* per-thread data */
2392 LLVMValueRef prim_enable[4]; /* i1 per stream */
2393 LLVMValueRef vertices[3]; /* [N x i32] addrspace(LDS)* */
2394
2395 /* Output */
2396 LLVMValueRef emit[4]; /* per-stream emitted primitives (only valid for used streams) */
2397 };
2398
2399 /**
2400 * Build streamout logic.
2401 *
2402 * Implies a barrier.
2403 *
2404 * Writes number of emitted primitives to gs_ngg_scratch[4:7].
2405 *
2406 * Clobbers gs_ngg_scratch[8:].
2407 */
2408 static void build_streamout(struct radv_shader_context *ctx,
2409 struct ngg_streamout *nggso)
2410 {
2411 struct radv_streamout_info *so = &ctx->args->shader_info->so;
2412 LLVMBuilderRef builder = ctx->ac.builder;
2413 LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac, ctx->args->streamout_buffers);
2414 LLVMValueRef tid = get_thread_id_in_tg(ctx);
2415 LLVMValueRef cond, tmp, tmp2;
2416 LLVMValueRef i32_2 = LLVMConstInt(ctx->ac.i32, 2, false);
2417 LLVMValueRef i32_4 = LLVMConstInt(ctx->ac.i32, 4, false);
2418 LLVMValueRef i32_8 = LLVMConstInt(ctx->ac.i32, 8, false);
2419 LLVMValueRef so_buffer[4] = {};
2420 unsigned max_num_vertices = 1 + (nggso->vertices[1] ? 1 : 0) +
2421 (nggso->vertices[2] ? 1 : 0);
2422 LLVMValueRef prim_stride_dw[4] = {};
2423 LLVMValueRef prim_stride_dw_vgpr = LLVMGetUndef(ctx->ac.i32);
2424 int stream_for_buffer[4] = { -1, -1, -1, -1 };
2425 unsigned bufmask_for_stream[4] = {};
2426 bool isgs = ctx->stage == MESA_SHADER_GEOMETRY;
2427 unsigned scratch_emit_base = isgs ? 4 : 0;
2428 LLVMValueRef scratch_emit_basev = isgs ? i32_4 : ctx->ac.i32_0;
2429 unsigned scratch_offset_base = isgs ? 8 : 4;
2430 LLVMValueRef scratch_offset_basev = isgs ? i32_8 : i32_4;
2431
2432 ac_llvm_add_target_dep_function_attr(ctx->main_function,
2433 "amdgpu-gds-size", 256);
2434
2435 /* Determine the mapping of streamout buffers to vertex streams. */
2436 for (unsigned i = 0; i < so->num_outputs; ++i) {
2437 unsigned buf = so->outputs[i].buffer;
2438 unsigned stream = so->outputs[i].stream;
2439 assert(stream_for_buffer[buf] < 0 || stream_for_buffer[buf] == stream);
2440 stream_for_buffer[buf] = stream;
2441 bufmask_for_stream[stream] |= 1 << buf;
2442 }
2443
2444 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2445 if (stream_for_buffer[buffer] == -1)
2446 continue;
2447
2448 assert(so->strides[buffer]);
2449
2450 LLVMValueRef stride_for_buffer =
2451 LLVMConstInt(ctx->ac.i32, so->strides[buffer], false);
2452 prim_stride_dw[buffer] =
2453 LLVMBuildMul(builder, stride_for_buffer,
2454 nggso->num_vertices, "");
2455 prim_stride_dw_vgpr = ac_build_writelane(
2456 &ctx->ac, prim_stride_dw_vgpr, prim_stride_dw[buffer],
2457 LLVMConstInt(ctx->ac.i32, buffer, false));
2458
2459 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, buffer, false);
2460 so_buffer[buffer] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr,
2461 offset);
2462 }
2463
2464 cond = LLVMBuildICmp(builder, LLVMIntEQ, get_wave_id_in_tg(ctx), ctx->ac.i32_0, "");
2465 ac_build_ifcc(&ctx->ac, cond, 5200);
2466 {
2467 LLVMTypeRef gdsptr = LLVMPointerType(ctx->ac.i32, AC_ADDR_SPACE_GDS);
2468 LLVMValueRef gdsbase = LLVMBuildIntToPtr(builder, ctx->ac.i32_0, gdsptr, "");
2469
2470 /* Advance the streamout offsets in GDS. */
2471 LLVMValueRef offsets_vgpr = ac_build_alloca_undef(&ctx->ac, ctx->ac.i32, "");
2472 LLVMValueRef generated_by_stream_vgpr = ac_build_alloca_undef(&ctx->ac, ctx->ac.i32, "");
2473
2474 cond = LLVMBuildICmp(builder, LLVMIntULT, ac_get_thread_id(&ctx->ac), i32_4, "");
2475 ac_build_ifcc(&ctx->ac, cond, 5210);
2476 {
2477 /* Fetch the number of generated primitives and store
2478 * it in GDS for later use.
2479 */
2480 if (isgs) {
2481 tmp = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tid);
2482 tmp = LLVMBuildLoad(builder, tmp, "");
2483 } else {
2484 tmp = ac_build_writelane(&ctx->ac, ctx->ac.i32_0,
2485 ngg_get_prim_cnt(ctx), ctx->ac.i32_0);
2486 }
2487 LLVMBuildStore(builder, tmp, generated_by_stream_vgpr);
2488
2489 unsigned swizzle[4];
2490 int unused_stream = -1;
2491 for (unsigned stream = 0; stream < 4; ++stream) {
2492 if (!ctx->args->shader_info->gs.num_stream_output_components[stream]) {
2493 unused_stream = stream;
2494 break;
2495 }
2496 }
2497 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2498 if (stream_for_buffer[buffer] >= 0) {
2499 swizzle[buffer] = stream_for_buffer[buffer];
2500 } else {
2501 assert(unused_stream >= 0);
2502 swizzle[buffer] = unused_stream;
2503 }
2504 }
2505
2506 tmp = ac_build_quad_swizzle(&ctx->ac, tmp,
2507 swizzle[0], swizzle[1], swizzle[2], swizzle[3]);
2508 tmp = LLVMBuildMul(builder, tmp, prim_stride_dw_vgpr, "");
2509
2510 LLVMValueRef args[] = {
2511 LLVMBuildIntToPtr(builder, ngg_get_ordered_id(ctx), gdsptr, ""),
2512 tmp,
2513 ctx->ac.i32_0, // ordering
2514 ctx->ac.i32_0, // scope
2515 ctx->ac.i1false, // isVolatile
2516 LLVMConstInt(ctx->ac.i32, 4 << 24, false), // OA index
2517 ctx->ac.i1true, // wave release
2518 ctx->ac.i1true, // wave done
2519 };
2520
2521 tmp = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.ds.ordered.add",
2522 ctx->ac.i32, args, ARRAY_SIZE(args), 0);
2523
2524 /* Keep offsets in a VGPR for quick retrieval via readlane by
2525 * the first wave for bounds checking, and also store in LDS
2526 * for retrieval by all waves later. */
2527 LLVMBuildStore(builder, tmp, offsets_vgpr);
2528
2529 tmp2 = LLVMBuildAdd(builder, ac_get_thread_id(&ctx->ac),
2530 scratch_offset_basev, "");
2531 tmp2 = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tmp2);
2532 LLVMBuildStore(builder, tmp, tmp2);
2533 }
2534 ac_build_endif(&ctx->ac, 5210);
2535
2536 /* Determine the max emit per buffer. This is done via the SALU, in part
2537 * because LLVM can't generate divide-by-multiply if we try to do this
2538 * via VALU with one lane per buffer.
2539 */
2540 LLVMValueRef max_emit[4] = {};
2541 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2542 if (stream_for_buffer[buffer] == -1)
2543 continue;
2544
2545 /* Compute the streamout buffer size in DWORD. */
2546 LLVMValueRef bufsize_dw =
2547 LLVMBuildLShr(builder,
2548 LLVMBuildExtractElement(builder, so_buffer[buffer], i32_2, ""),
2549 i32_2, "");
2550
2551 /* Load the streamout buffer offset from GDS. */
2552 tmp = LLVMBuildLoad(builder, offsets_vgpr, "");
2553 LLVMValueRef offset_dw =
2554 ac_build_readlane(&ctx->ac, tmp,
2555 LLVMConstInt(ctx->ac.i32, buffer, false));
2556
2557 /* Compute the remaining size to emit. */
2558 LLVMValueRef remaining_dw =
2559 LLVMBuildSub(builder, bufsize_dw, offset_dw, "");
2560 tmp = LLVMBuildUDiv(builder, remaining_dw,
2561 prim_stride_dw[buffer], "");
2562
2563 cond = LLVMBuildICmp(builder, LLVMIntULT,
2564 bufsize_dw, offset_dw, "");
2565 max_emit[buffer] = LLVMBuildSelect(builder, cond,
2566 ctx->ac.i32_0, tmp, "");
2567 }
2568
2569 /* Determine the number of emitted primitives per stream and fixup the
2570 * GDS counter if necessary.
2571 *
2572 * This is complicated by the fact that a single stream can emit to
2573 * multiple buffers (but luckily not vice versa).
2574 */
2575 LLVMValueRef emit_vgpr = ctx->ac.i32_0;
2576
2577 for (unsigned stream = 0; stream < 4; ++stream) {
2578 if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
2579 continue;
2580
2581 /* Load the number of generated primitives from GDS and
2582 * determine that number for the given stream.
2583 */
2584 tmp = LLVMBuildLoad(builder, generated_by_stream_vgpr, "");
2585 LLVMValueRef generated =
2586 ac_build_readlane(&ctx->ac, tmp,
2587 LLVMConstInt(ctx->ac.i32, stream, false));
2588
2589
2590 /* Compute the number of emitted primitives. */
2591 LLVMValueRef emit = generated;
2592 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2593 if (stream_for_buffer[buffer] == stream)
2594 emit = ac_build_umin(&ctx->ac, emit, max_emit[buffer]);
2595 }
2596
2597 /* Store the number of emitted primitives for that
2598 * stream.
2599 */
2600 emit_vgpr = ac_build_writelane(&ctx->ac, emit_vgpr, emit,
2601 LLVMConstInt(ctx->ac.i32, stream, false));
2602
2603 /* Fixup the offset using a plain GDS atomic if we overflowed. */
2604 cond = LLVMBuildICmp(builder, LLVMIntULT, emit, generated, "");
2605 ac_build_ifcc(&ctx->ac, cond, 5221); /* scalar branch */
2606 tmp = LLVMBuildLShr(builder,
2607 LLVMConstInt(ctx->ac.i32, bufmask_for_stream[stream], false),
2608 ac_get_thread_id(&ctx->ac), "");
2609 tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
2610 ac_build_ifcc(&ctx->ac, tmp, 5222);
2611 {
2612 tmp = LLVMBuildSub(builder, generated, emit, "");
2613 tmp = LLVMBuildMul(builder, tmp, prim_stride_dw_vgpr, "");
2614 tmp2 = LLVMBuildGEP(builder, gdsbase, &tid, 1, "");
2615 LLVMBuildAtomicRMW(builder, LLVMAtomicRMWBinOpSub, tmp2, tmp,
2616 LLVMAtomicOrderingMonotonic, false);
2617 }
2618 ac_build_endif(&ctx->ac, 5222);
2619 ac_build_endif(&ctx->ac, 5221);
2620 }
2621
2622 /* Store the number of emitted primitives to LDS for later use. */
2623 cond = LLVMBuildICmp(builder, LLVMIntULT, ac_get_thread_id(&ctx->ac), i32_4, "");
2624 ac_build_ifcc(&ctx->ac, cond, 5225);
2625 {
2626 tmp = LLVMBuildAdd(builder, ac_get_thread_id(&ctx->ac),
2627 scratch_emit_basev, "");
2628 tmp = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tmp);
2629 LLVMBuildStore(builder, emit_vgpr, tmp);
2630 }
2631 ac_build_endif(&ctx->ac, 5225);
2632 }
2633 ac_build_endif(&ctx->ac, 5200);
2634
2635 /* Determine the workgroup-relative per-thread / primitive offset into
2636 * the streamout buffers */
2637 struct ac_wg_scan primemit_scan[4] = {};
2638
2639 if (isgs) {
2640 for (unsigned stream = 0; stream < 4; ++stream) {
2641 if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
2642 continue;
2643
2644 primemit_scan[stream].enable_exclusive = true;
2645 primemit_scan[stream].op = nir_op_iadd;
2646 primemit_scan[stream].src = nggso->prim_enable[stream];
2647 primemit_scan[stream].scratch =
2648 ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch,
2649 LLVMConstInt(ctx->ac.i32, 12 + 8 * stream, false));
2650 primemit_scan[stream].waveidx = get_wave_id_in_tg(ctx);
2651 primemit_scan[stream].numwaves = get_tgsize(ctx);
2652 primemit_scan[stream].maxwaves = 8;
2653 ac_build_wg_scan_top(&ctx->ac, &primemit_scan[stream]);
2654 }
2655 }
2656
2657 ac_build_s_barrier(&ctx->ac);
2658
2659 /* Fetch the per-buffer offsets and per-stream emit counts in all waves. */
2660 LLVMValueRef wgoffset_dw[4] = {};
2661
2662 {
2663 LLVMValueRef scratch_vgpr;
2664
2665 tmp = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, ac_get_thread_id(&ctx->ac));
2666 scratch_vgpr = LLVMBuildLoad(builder, tmp, "");
2667
2668 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2669 if (stream_for_buffer[buffer] >= 0) {
2670 wgoffset_dw[buffer] = ac_build_readlane(
2671 &ctx->ac, scratch_vgpr,
2672 LLVMConstInt(ctx->ac.i32, scratch_offset_base + buffer, false));
2673 }
2674 }
2675
2676 for (unsigned stream = 0; stream < 4; ++stream) {
2677 if (ctx->args->shader_info->gs.num_stream_output_components[stream]) {
2678 nggso->emit[stream] = ac_build_readlane(
2679 &ctx->ac, scratch_vgpr,
2680 LLVMConstInt(ctx->ac.i32, scratch_emit_base + stream, false));
2681 }
2682 }
2683 }
2684
2685 /* Write out primitive data */
2686 for (unsigned stream = 0; stream < 4; ++stream) {
2687 if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
2688 continue;
2689
2690 if (isgs) {
2691 ac_build_wg_scan_bottom(&ctx->ac, &primemit_scan[stream]);
2692 } else {
2693 primemit_scan[stream].result_exclusive = tid;
2694 }
2695
2696 cond = LLVMBuildICmp(builder, LLVMIntULT,
2697 primemit_scan[stream].result_exclusive,
2698 nggso->emit[stream], "");
2699 cond = LLVMBuildAnd(builder, cond, nggso->prim_enable[stream], "");
2700 ac_build_ifcc(&ctx->ac, cond, 5240);
2701 {
2702 LLVMValueRef offset_vtx =
2703 LLVMBuildMul(builder, primemit_scan[stream].result_exclusive,
2704 nggso->num_vertices, "");
2705
2706 for (unsigned i = 0; i < max_num_vertices; ++i) {
2707 cond = LLVMBuildICmp(builder, LLVMIntULT,
2708 LLVMConstInt(ctx->ac.i32, i, false),
2709 nggso->num_vertices, "");
2710 ac_build_ifcc(&ctx->ac, cond, 5241);
2711 build_streamout_vertex(ctx, so_buffer, wgoffset_dw,
2712 stream, offset_vtx, nggso->vertices[i]);
2713 ac_build_endif(&ctx->ac, 5241);
2714 offset_vtx = LLVMBuildAdd(builder, offset_vtx, ctx->ac.i32_1, "");
2715 }
2716 }
2717 ac_build_endif(&ctx->ac, 5240);
2718 }
2719 }
2720
2721 static unsigned ngg_nogs_vertex_size(struct radv_shader_context *ctx)
2722 {
2723 unsigned lds_vertex_size = 0;
2724
2725 if (ctx->args->shader_info->so.num_outputs)
2726 lds_vertex_size = 4 * ctx->args->shader_info->so.num_outputs + 1;
2727
2728 return lds_vertex_size;
2729 }
2730
2731 /**
2732 * Returns an `[N x i32] addrspace(LDS)*` pointing at contiguous LDS storage
2733 * for the vertex outputs.
2734 */
2735 static LLVMValueRef ngg_nogs_vertex_ptr(struct radv_shader_context *ctx,
2736 LLVMValueRef vtxid)
2737 {
2738 /* The extra dword is used to avoid LDS bank conflicts. */
2739 unsigned vertex_size = ngg_nogs_vertex_size(ctx);
2740 LLVMTypeRef ai32 = LLVMArrayType(ctx->ac.i32, vertex_size);
2741 LLVMTypeRef pai32 = LLVMPointerType(ai32, AC_ADDR_SPACE_LDS);
2742 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, ctx->esgs_ring, pai32, "");
2743 return LLVMBuildGEP(ctx->ac.builder, tmp, &vtxid, 1, "");
2744 }
2745
2746 static void
2747 handle_ngg_outputs_post_1(struct radv_shader_context *ctx)
2748 {
2749 struct radv_streamout_info *so = &ctx->args->shader_info->so;
2750 LLVMBuilderRef builder = ctx->ac.builder;
2751 LLVMValueRef vertex_ptr = NULL;
2752 LLVMValueRef tmp, tmp2;
2753
2754 assert((ctx->stage == MESA_SHADER_VERTEX ||
2755 ctx->stage == MESA_SHADER_TESS_EVAL) && !ctx->args->is_gs_copy_shader);
2756
2757 if (!ctx->args->shader_info->so.num_outputs)
2758 return;
2759
2760 vertex_ptr = ngg_nogs_vertex_ptr(ctx, get_thread_id_in_tg(ctx));
2761
2762 for (unsigned i = 0; i < so->num_outputs; ++i) {
2763 struct radv_stream_output *output =
2764 &ctx->args->shader_info->so.outputs[i];
2765
2766 unsigned loc = output->location;
2767
2768 for (unsigned comp = 0; comp < 4; comp++) {
2769 if (!(output->component_mask & (1 << comp)))
2770 continue;
2771
2772 tmp = ac_build_gep0(&ctx->ac, vertex_ptr,
2773 LLVMConstInt(ctx->ac.i32, 4 * i + comp, false));
2774 tmp2 = LLVMBuildLoad(builder,
2775 ctx->abi.outputs[4 * loc + comp], "");
2776 tmp2 = ac_to_integer(&ctx->ac, tmp2);
2777 LLVMBuildStore(builder, tmp2, tmp);
2778 }
2779 }
2780 }
2781
2782 static void
2783 handle_ngg_outputs_post_2(struct radv_shader_context *ctx)
2784 {
2785 LLVMBuilderRef builder = ctx->ac.builder;
2786 LLVMValueRef tmp;
2787
2788 assert((ctx->stage == MESA_SHADER_VERTEX ||
2789 ctx->stage == MESA_SHADER_TESS_EVAL) && !ctx->args->is_gs_copy_shader);
2790
2791 LLVMValueRef prims_in_wave = ac_unpack_param(&ctx->ac,
2792 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 8, 8);
2793 LLVMValueRef vtx_in_wave = ac_unpack_param(&ctx->ac,
2794 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 0, 8);
2795 LLVMValueRef is_gs_thread = LLVMBuildICmp(builder, LLVMIntULT,
2796 ac_get_thread_id(&ctx->ac), prims_in_wave, "");
2797 LLVMValueRef is_es_thread = LLVMBuildICmp(builder, LLVMIntULT,
2798 ac_get_thread_id(&ctx->ac), vtx_in_wave, "");
2799 LLVMValueRef vtxindex[] = {
2800 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[0]), 0, 16),
2801 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[0]), 16, 16),
2802 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[2]), 0, 16),
2803 };
2804
2805 /* Determine the number of vertices per primitive. */
2806 unsigned num_vertices;
2807 LLVMValueRef num_vertices_val;
2808
2809 if (ctx->stage == MESA_SHADER_VERTEX) {
2810 LLVMValueRef outprim_val =
2811 LLVMConstInt(ctx->ac.i32,
2812 ctx->args->options->key.vs.outprim, false);
2813 num_vertices_val = LLVMBuildAdd(builder, outprim_val,
2814 ctx->ac.i32_1, "");
2815 num_vertices = 3; /* TODO: optimize for points & lines */
2816 } else {
2817 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2818
2819 if (ctx->shader->info.tess.point_mode)
2820 num_vertices = 1;
2821 else if (ctx->shader->info.tess.primitive_mode == GL_ISOLINES)
2822 num_vertices = 2;
2823 else
2824 num_vertices = 3;
2825
2826 num_vertices_val = LLVMConstInt(ctx->ac.i32, num_vertices, false);
2827 }
2828
2829 /* Streamout */
2830 if (ctx->args->shader_info->so.num_outputs) {
2831 struct ngg_streamout nggso = {};
2832
2833 nggso.num_vertices = num_vertices_val;
2834 nggso.prim_enable[0] = is_gs_thread;
2835
2836 for (unsigned i = 0; i < num_vertices; ++i)
2837 nggso.vertices[i] = ngg_nogs_vertex_ptr(ctx, vtxindex[i]);
2838
2839 build_streamout(ctx, &nggso);
2840 }
2841
2842 /* Copy Primitive IDs from GS threads to the LDS address corresponding
2843 * to the ES thread of the provoking vertex.
2844 */
2845 if (ctx->stage == MESA_SHADER_VERTEX &&
2846 ctx->args->options->key.vs_common_out.export_prim_id) {
2847 if (ctx->args->shader_info->so.num_outputs)
2848 ac_build_s_barrier(&ctx->ac);
2849
2850 ac_build_ifcc(&ctx->ac, is_gs_thread, 5400);
2851 /* Extract the PROVOKING_VTX_INDEX field. */
2852 LLVMValueRef provoking_vtx_in_prim =
2853 LLVMConstInt(ctx->ac.i32, 0, false);
2854
2855 /* provoking_vtx_index = vtxindex[provoking_vtx_in_prim]; */
2856 LLVMValueRef indices = ac_build_gather_values(&ctx->ac, vtxindex, 3);
2857 LLVMValueRef provoking_vtx_index =
2858 LLVMBuildExtractElement(builder, indices, provoking_vtx_in_prim, "");
2859
2860 LLVMBuildStore(builder, ac_get_arg(&ctx->ac, ctx->args->ac.gs_prim_id),
2861 ac_build_gep0(&ctx->ac, ctx->esgs_ring, provoking_vtx_index));
2862 ac_build_endif(&ctx->ac, 5400);
2863 }
2864
2865 /* TODO: primitive culling */
2866
2867 ac_build_sendmsg_gs_alloc_req(&ctx->ac, get_wave_id_in_tg(ctx),
2868 ngg_get_vtx_cnt(ctx), ngg_get_prim_cnt(ctx));
2869
2870 /* TODO: streamout queries */
2871 /* Export primitive data to the index buffer.
2872 *
2873 * For the first version, we will always build up all three indices
2874 * independent of the primitive type. The additional garbage data
2875 * shouldn't hurt.
2876 *
2877 * TODO: culling depends on the primitive type, so can have some
2878 * interaction here.
2879 */
2880 ac_build_ifcc(&ctx->ac, is_gs_thread, 6001);
2881 {
2882 struct ac_ngg_prim prim = {};
2883
2884 if (ctx->args->options->key.vs_common_out.as_ngg_passthrough) {
2885 prim.passthrough = ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[0]);
2886 } else {
2887 prim.num_vertices = num_vertices;
2888 prim.isnull = ctx->ac.i1false;
2889 memcpy(prim.index, vtxindex, sizeof(vtxindex[0]) * 3);
2890
2891 for (unsigned i = 0; i < num_vertices; ++i) {
2892 tmp = LLVMBuildLShr(builder,
2893 ac_get_arg(&ctx->ac, ctx->args->ac.gs_invocation_id),
2894 LLVMConstInt(ctx->ac.i32, 8 + i, false), "");
2895 prim.edgeflag[i] = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
2896 }
2897 }
2898
2899 ac_build_export_prim(&ctx->ac, &prim);
2900 }
2901 ac_build_endif(&ctx->ac, 6001);
2902
2903 /* Export per-vertex data (positions and parameters). */
2904 ac_build_ifcc(&ctx->ac, is_es_thread, 6002);
2905 {
2906 struct radv_vs_output_info *outinfo =
2907 ctx->stage == MESA_SHADER_TESS_EVAL ?
2908 &ctx->args->shader_info->tes.outinfo : &ctx->args->shader_info->vs.outinfo;
2909
2910 /* Exporting the primitive ID is handled below. */
2911 /* TODO: use the new VS export path */
2912 handle_vs_outputs_post(ctx, false,
2913 ctx->args->options->key.vs_common_out.export_clip_dists,
2914 outinfo);
2915
2916 if (ctx->args->options->key.vs_common_out.export_prim_id) {
2917 unsigned param_count = outinfo->param_exports;
2918 LLVMValueRef values[4];
2919
2920 if (ctx->stage == MESA_SHADER_VERTEX) {
2921 /* Wait for GS stores to finish. */
2922 ac_build_s_barrier(&ctx->ac);
2923
2924 tmp = ac_build_gep0(&ctx->ac, ctx->esgs_ring,
2925 get_thread_id_in_tg(ctx));
2926 values[0] = LLVMBuildLoad(builder, tmp, "");
2927 } else {
2928 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2929 values[0] = ac_get_arg(&ctx->ac, ctx->args->ac.tes_patch_id);
2930 }
2931
2932 values[0] = ac_to_float(&ctx->ac, values[0]);
2933 for (unsigned j = 1; j < 4; j++)
2934 values[j] = ctx->ac.f32_0;
2935
2936 radv_export_param(ctx, param_count, values, 0x1);
2937
2938 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
2939 outinfo->param_exports = param_count;
2940 }
2941 }
2942 ac_build_endif(&ctx->ac, 6002);
2943 }
2944
2945 static void gfx10_ngg_gs_emit_prologue(struct radv_shader_context *ctx)
2946 {
2947 /* Zero out the part of LDS scratch that is used to accumulate the
2948 * per-stream generated primitive count.
2949 */
2950 LLVMBuilderRef builder = ctx->ac.builder;
2951 LLVMValueRef scratchptr = ctx->gs_ngg_scratch;
2952 LLVMValueRef tid = get_thread_id_in_tg(ctx);
2953 LLVMBasicBlockRef merge_block;
2954 LLVMValueRef cond;
2955
2956 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
2957 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
2958 merge_block = LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
2959
2960 cond = LLVMBuildICmp(builder, LLVMIntULT, tid, LLVMConstInt(ctx->ac.i32, 4, false), "");
2961 LLVMBuildCondBr(ctx->ac.builder, cond, then_block, merge_block);
2962 LLVMPositionBuilderAtEnd(ctx->ac.builder, then_block);
2963
2964 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, scratchptr, tid);
2965 LLVMBuildStore(builder, ctx->ac.i32_0, ptr);
2966
2967 LLVMBuildBr(ctx->ac.builder, merge_block);
2968 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
2969
2970 ac_build_s_barrier(&ctx->ac);
2971 }
2972
2973 static void gfx10_ngg_gs_emit_epilogue_1(struct radv_shader_context *ctx)
2974 {
2975 LLVMBuilderRef builder = ctx->ac.builder;
2976 LLVMValueRef i8_0 = LLVMConstInt(ctx->ac.i8, 0, false);
2977 LLVMValueRef tmp;
2978
2979 /* Zero out remaining (non-emitted) primitive flags.
2980 *
2981 * Note: Alternatively, we could pass the relevant gs_next_vertex to
2982 * the emit threads via LDS. This is likely worse in the expected
2983 * typical case where each GS thread emits the full set of
2984 * vertices.
2985 */
2986 for (unsigned stream = 0; stream < 4; ++stream) {
2987 unsigned num_components;
2988
2989 num_components =
2990 ctx->args->shader_info->gs.num_stream_output_components[stream];
2991 if (!num_components)
2992 continue;
2993
2994 const LLVMValueRef gsthread = get_thread_id_in_tg(ctx);
2995
2996 ac_build_bgnloop(&ctx->ac, 5100);
2997
2998 const LLVMValueRef vertexidx =
2999 LLVMBuildLoad(builder, ctx->gs_next_vertex[stream], "");
3000 tmp = LLVMBuildICmp(builder, LLVMIntUGE, vertexidx,
3001 LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false), "");
3002 ac_build_ifcc(&ctx->ac, tmp, 5101);
3003 ac_build_break(&ctx->ac);
3004 ac_build_endif(&ctx->ac, 5101);
3005
3006 tmp = LLVMBuildAdd(builder, vertexidx, ctx->ac.i32_1, "");
3007 LLVMBuildStore(builder, tmp, ctx->gs_next_vertex[stream]);
3008
3009 tmp = ngg_gs_emit_vertex_ptr(ctx, gsthread, vertexidx);
3010 LLVMBuildStore(builder, i8_0,
3011 ngg_gs_get_emit_primflag_ptr(ctx, tmp, stream));
3012
3013 ac_build_endloop(&ctx->ac, 5100);
3014 }
3015
3016 /* Accumulate generated primitives counts across the entire threadgroup. */
3017 for (unsigned stream = 0; stream < 4; ++stream) {
3018 unsigned num_components;
3019
3020 num_components =
3021 ctx->args->shader_info->gs.num_stream_output_components[stream];
3022 if (!num_components)
3023 continue;
3024
3025 LLVMValueRef numprims =
3026 LLVMBuildLoad(builder, ctx->gs_generated_prims[stream], "");
3027 numprims = ac_build_reduce(&ctx->ac, numprims, nir_op_iadd, ctx->ac.wave_size);
3028
3029 tmp = LLVMBuildICmp(builder, LLVMIntEQ, ac_get_thread_id(&ctx->ac), ctx->ac.i32_0, "");
3030 ac_build_ifcc(&ctx->ac, tmp, 5105);
3031 {
3032 LLVMBuildAtomicRMW(builder, LLVMAtomicRMWBinOpAdd,
3033 ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch,
3034 LLVMConstInt(ctx->ac.i32, stream, false)),
3035 numprims, LLVMAtomicOrderingMonotonic, false);
3036 }
3037 ac_build_endif(&ctx->ac, 5105);
3038 }
3039 }
3040
3041 static void gfx10_ngg_gs_emit_epilogue_2(struct radv_shader_context *ctx)
3042 {
3043 const unsigned verts_per_prim = si_conv_gl_prim_to_vertices(ctx->shader->info.gs.output_primitive);
3044 LLVMBuilderRef builder = ctx->ac.builder;
3045 LLVMValueRef tmp, tmp2;
3046
3047 ac_build_s_barrier(&ctx->ac);
3048
3049 const LLVMValueRef tid = get_thread_id_in_tg(ctx);
3050 LLVMValueRef num_emit_threads = ngg_get_prim_cnt(ctx);
3051
3052 /* Streamout */
3053 if (ctx->args->shader_info->so.num_outputs) {
3054 struct ngg_streamout nggso = {};
3055
3056 nggso.num_vertices = LLVMConstInt(ctx->ac.i32, verts_per_prim, false);
3057
3058 LLVMValueRef vertexptr = ngg_gs_vertex_ptr(ctx, tid);
3059 for (unsigned stream = 0; stream < 4; ++stream) {
3060 if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
3061 continue;
3062
3063 tmp = LLVMBuildLoad(builder,
3064 ngg_gs_get_emit_primflag_ptr(ctx, vertexptr, stream), "");
3065 tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3066 tmp2 = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
3067 nggso.prim_enable[stream] = LLVMBuildAnd(builder, tmp, tmp2, "");
3068 }
3069
3070 for (unsigned i = 0; i < verts_per_prim; ++i) {
3071 tmp = LLVMBuildSub(builder, tid,
3072 LLVMConstInt(ctx->ac.i32, verts_per_prim - i - 1, false), "");
3073 tmp = ngg_gs_vertex_ptr(ctx, tmp);
3074 nggso.vertices[i] = ac_build_gep0(&ctx->ac, tmp, ctx->ac.i32_0);
3075 }
3076
3077 build_streamout(ctx, &nggso);
3078 }
3079
3080 /* Write shader query data. */
3081 tmp = ac_get_arg(&ctx->ac, ctx->args->ngg_gs_state);
3082 tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3083 ac_build_ifcc(&ctx->ac, tmp, 5109);
3084 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid,
3085 LLVMConstInt(ctx->ac.i32, 4, false), "");
3086 ac_build_ifcc(&ctx->ac, tmp, 5110);
3087 {
3088 tmp = LLVMBuildLoad(builder, ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tid), "");
3089
3090 ac_llvm_add_target_dep_function_attr(ctx->main_function,
3091 "amdgpu-gds-size", 256);
3092
3093 LLVMTypeRef gdsptr = LLVMPointerType(ctx->ac.i32, AC_ADDR_SPACE_GDS);
3094 LLVMValueRef gdsbase = LLVMBuildIntToPtr(builder, ctx->ac.i32_0, gdsptr, "");
3095
3096 const char *sync_scope = LLVM_VERSION_MAJOR >= 9 ? "workgroup-one-as" : "workgroup";
3097
3098 /* Use a plain GDS atomic to accumulate the number of generated
3099 * primitives.
3100 */
3101 ac_build_atomic_rmw(&ctx->ac, LLVMAtomicRMWBinOpAdd, gdsbase,
3102 tmp, sync_scope);
3103 }
3104 ac_build_endif(&ctx->ac, 5110);
3105 ac_build_endif(&ctx->ac, 5109);
3106
3107 /* TODO: culling */
3108
3109 /* Determine vertex liveness. */
3110 LLVMValueRef vertliveptr = ac_build_alloca(&ctx->ac, ctx->ac.i1, "vertexlive");
3111
3112 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
3113 ac_build_ifcc(&ctx->ac, tmp, 5120);
3114 {
3115 for (unsigned i = 0; i < verts_per_prim; ++i) {
3116 const LLVMValueRef primidx =
3117 LLVMBuildAdd(builder, tid,
3118 LLVMConstInt(ctx->ac.i32, i, false), "");
3119
3120 if (i > 0) {
3121 tmp = LLVMBuildICmp(builder, LLVMIntULT, primidx, num_emit_threads, "");
3122 ac_build_ifcc(&ctx->ac, tmp, 5121 + i);
3123 }
3124
3125 /* Load primitive liveness */
3126 tmp = ngg_gs_vertex_ptr(ctx, primidx);
3127 tmp = LLVMBuildLoad(builder,
3128 ngg_gs_get_emit_primflag_ptr(ctx, tmp, 0), "");
3129 const LLVMValueRef primlive =
3130 LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3131
3132 tmp = LLVMBuildLoad(builder, vertliveptr, "");
3133 tmp = LLVMBuildOr(builder, tmp, primlive, ""),
3134 LLVMBuildStore(builder, tmp, vertliveptr);
3135
3136 if (i > 0)
3137 ac_build_endif(&ctx->ac, 5121 + i);
3138 }
3139 }
3140 ac_build_endif(&ctx->ac, 5120);
3141
3142 /* Inclusive scan addition across the current wave. */
3143 LLVMValueRef vertlive = LLVMBuildLoad(builder, vertliveptr, "");
3144 struct ac_wg_scan vertlive_scan = {};
3145 vertlive_scan.op = nir_op_iadd;
3146 vertlive_scan.enable_reduce = true;
3147 vertlive_scan.enable_exclusive = true;
3148 vertlive_scan.src = vertlive;
3149 vertlive_scan.scratch = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, ctx->ac.i32_0);
3150 vertlive_scan.waveidx = get_wave_id_in_tg(ctx);
3151 vertlive_scan.numwaves = get_tgsize(ctx);
3152 vertlive_scan.maxwaves = 8;
3153
3154 ac_build_wg_scan(&ctx->ac, &vertlive_scan);
3155
3156 /* Skip all exports (including index exports) when possible. At least on
3157 * early gfx10 revisions this is also to avoid hangs.
3158 */
3159 LLVMValueRef have_exports =
3160 LLVMBuildICmp(builder, LLVMIntNE, vertlive_scan.result_reduce, ctx->ac.i32_0, "");
3161 num_emit_threads =
3162 LLVMBuildSelect(builder, have_exports, num_emit_threads, ctx->ac.i32_0, "");
3163
3164 /* Allocate export space. Send this message as early as possible, to
3165 * hide the latency of the SQ <-> SPI roundtrip.
3166 *
3167 * Note: We could consider compacting primitives for export as well.
3168 * PA processes 1 non-null prim / clock, but it fetches 4 DW of
3169 * prim data per clock and skips null primitives at no additional
3170 * cost. So compacting primitives can only be beneficial when
3171 * there are 4 or more contiguous null primitives in the export
3172 * (in the common case of single-dword prim exports).
3173 */
3174 ac_build_sendmsg_gs_alloc_req(&ctx->ac, get_wave_id_in_tg(ctx),
3175 vertlive_scan.result_reduce, num_emit_threads);
3176
3177 /* Setup the reverse vertex compaction permutation. We re-use stream 1
3178 * of the primitive liveness flags, relying on the fact that each
3179 * threadgroup can have at most 256 threads. */
3180 ac_build_ifcc(&ctx->ac, vertlive, 5130);
3181 {
3182 tmp = ngg_gs_vertex_ptr(ctx, vertlive_scan.result_exclusive);
3183 tmp2 = LLVMBuildTrunc(builder, tid, ctx->ac.i8, "");
3184 LLVMBuildStore(builder, tmp2,
3185 ngg_gs_get_emit_primflag_ptr(ctx, tmp, 1));
3186 }
3187 ac_build_endif(&ctx->ac, 5130);
3188
3189 ac_build_s_barrier(&ctx->ac);
3190
3191 /* Export primitive data */
3192 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
3193 ac_build_ifcc(&ctx->ac, tmp, 5140);
3194 {
3195 LLVMValueRef flags;
3196 struct ac_ngg_prim prim = {};
3197 prim.num_vertices = verts_per_prim;
3198
3199 tmp = ngg_gs_vertex_ptr(ctx, tid);
3200 flags = LLVMBuildLoad(builder,
3201 ngg_gs_get_emit_primflag_ptr(ctx, tmp, 0), "");
3202 prim.isnull = LLVMBuildNot(builder, LLVMBuildTrunc(builder, flags, ctx->ac.i1, ""), "");
3203
3204 for (unsigned i = 0; i < verts_per_prim; ++i) {
3205 prim.index[i] = LLVMBuildSub(builder, vertlive_scan.result_exclusive,
3206 LLVMConstInt(ctx->ac.i32, verts_per_prim - i - 1, false), "");
3207 prim.edgeflag[i] = ctx->ac.i1false;
3208 }
3209
3210 /* Geometry shaders output triangle strips, but NGG expects
3211 * triangles. We need to change the vertex order for odd
3212 * triangles to get correct front/back facing by swapping 2
3213 * vertex indices, but we also have to keep the provoking
3214 * vertex in the same place.
3215 */
3216 if (verts_per_prim == 3) {
3217 LLVMValueRef is_odd = LLVMBuildLShr(builder, flags, ctx->ac.i8_1, "");
3218 is_odd = LLVMBuildTrunc(builder, is_odd, ctx->ac.i1, "");
3219
3220 struct ac_ngg_prim in = prim;
3221 prim.index[0] = in.index[0];
3222 prim.index[1] = LLVMBuildSelect(builder, is_odd,
3223 in.index[2], in.index[1], "");
3224 prim.index[2] = LLVMBuildSelect(builder, is_odd,
3225 in.index[1], in.index[2], "");
3226 }
3227
3228 ac_build_export_prim(&ctx->ac, &prim);
3229 }
3230 ac_build_endif(&ctx->ac, 5140);
3231
3232 /* Export position and parameter data */
3233 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, vertlive_scan.result_reduce, "");
3234 ac_build_ifcc(&ctx->ac, tmp, 5145);
3235 {
3236 struct radv_vs_output_info *outinfo = &ctx->args->shader_info->vs.outinfo;
3237 bool export_view_index = ctx->args->options->key.has_multiview_view_index;
3238 struct radv_shader_output_values *outputs;
3239 unsigned noutput = 0;
3240
3241 /* Allocate a temporary array for the output values. */
3242 unsigned num_outputs = util_bitcount64(ctx->output_mask) + export_view_index;
3243 outputs = calloc(num_outputs, sizeof(outputs[0]));
3244
3245 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
3246 sizeof(outinfo->vs_output_param_offset));
3247 outinfo->pos_exports = 0;
3248
3249 tmp = ngg_gs_vertex_ptr(ctx, tid);
3250 tmp = LLVMBuildLoad(builder,
3251 ngg_gs_get_emit_primflag_ptr(ctx, tmp, 1), "");
3252 tmp = LLVMBuildZExt(builder, tmp, ctx->ac.i32, "");
3253 const LLVMValueRef vertexptr = ngg_gs_vertex_ptr(ctx, tmp);
3254
3255 unsigned out_idx = 0;
3256 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3257 unsigned output_usage_mask =
3258 ctx->args->shader_info->gs.output_usage_mask[i];
3259 int length = util_last_bit(output_usage_mask);
3260
3261 if (!(ctx->output_mask & (1ull << i)))
3262 continue;
3263
3264 outputs[noutput].slot_name = i;
3265 outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
3266 outputs[noutput].usage_mask = output_usage_mask;
3267
3268 for (unsigned j = 0; j < length; j++, out_idx++) {
3269 if (!(output_usage_mask & (1 << j)))
3270 continue;
3271
3272 tmp = ngg_gs_get_emit_output_ptr(ctx, vertexptr, out_idx);
3273 tmp = LLVMBuildLoad(builder, tmp, "");
3274
3275 LLVMTypeRef type = LLVMGetAllocatedType(ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
3276 if (ac_get_type_size(type) == 2) {
3277 tmp = ac_to_integer(&ctx->ac, tmp);
3278 tmp = LLVMBuildTrunc(ctx->ac.builder, tmp, ctx->ac.i16, "");
3279 }
3280
3281 outputs[noutput].values[j] = ac_to_float(&ctx->ac, tmp);
3282 }
3283
3284 for (unsigned j = length; j < 4; j++)
3285 outputs[noutput].values[j] = LLVMGetUndef(ctx->ac.f32);
3286
3287 noutput++;
3288 }
3289
3290 /* Export ViewIndex. */
3291 if (export_view_index) {
3292 outputs[noutput].slot_name = VARYING_SLOT_LAYER;
3293 outputs[noutput].slot_index = 0;
3294 outputs[noutput].usage_mask = 0x1;
3295 outputs[noutput].values[0] =
3296 ac_to_float(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->ac.view_index));
3297 for (unsigned j = 1; j < 4; j++)
3298 outputs[noutput].values[j] = ctx->ac.f32_0;
3299 noutput++;
3300 }
3301
3302 radv_llvm_export_vs(ctx, outputs, noutput, outinfo,
3303 ctx->args->options->key.vs_common_out.export_clip_dists);
3304 FREE(outputs);
3305 }
3306 ac_build_endif(&ctx->ac, 5145);
3307 }
3308
3309 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context *ctx,
3310 unsigned stream,
3311 LLVMValueRef *addrs)
3312 {
3313 LLVMBuilderRef builder = ctx->ac.builder;
3314 LLVMValueRef tmp;
3315 const LLVMValueRef vertexidx =
3316 LLVMBuildLoad(builder, ctx->gs_next_vertex[stream], "");
3317
3318 /* If this thread has already emitted the declared maximum number of
3319 * vertices, skip the write: excessive vertex emissions are not
3320 * supposed to have any effect.
3321 */
3322 const LLVMValueRef can_emit =
3323 LLVMBuildICmp(builder, LLVMIntULT, vertexidx,
3324 LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false), "");
3325 ac_build_ifcc(&ctx->ac, can_emit, 9001);
3326
3327 tmp = LLVMBuildAdd(builder, vertexidx, ctx->ac.i32_1, "");
3328 tmp = LLVMBuildSelect(builder, can_emit, tmp, vertexidx, "");
3329 LLVMBuildStore(builder, tmp, ctx->gs_next_vertex[stream]);
3330
3331 const LLVMValueRef vertexptr =
3332 ngg_gs_emit_vertex_ptr(ctx, get_thread_id_in_tg(ctx), vertexidx);
3333 unsigned out_idx = 0;
3334 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3335 unsigned output_usage_mask =
3336 ctx->args->shader_info->gs.output_usage_mask[i];
3337 uint8_t output_stream =
3338 ctx->args->shader_info->gs.output_streams[i];
3339 LLVMValueRef *out_ptr = &addrs[i * 4];
3340 int length = util_last_bit(output_usage_mask);
3341
3342 if (!(ctx->output_mask & (1ull << i)) ||
3343 output_stream != stream)
3344 continue;
3345
3346 for (unsigned j = 0; j < length; j++, out_idx++) {
3347 if (!(output_usage_mask & (1 << j)))
3348 continue;
3349
3350 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
3351 out_ptr[j], "");
3352 out_val = ac_to_integer(&ctx->ac, out_val);
3353 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
3354
3355 LLVMBuildStore(builder, out_val,
3356 ngg_gs_get_emit_output_ptr(ctx, vertexptr, out_idx));
3357 }
3358 }
3359 assert(out_idx * 4 <= ctx->args->shader_info->gs.gsvs_vertex_size);
3360
3361 /* Determine and store whether this vertex completed a primitive. */
3362 const LLVMValueRef curverts = LLVMBuildLoad(builder, ctx->gs_curprim_verts[stream], "");
3363
3364 tmp = LLVMConstInt(ctx->ac.i32, si_conv_gl_prim_to_vertices(ctx->shader->info.gs.output_primitive) - 1, false);
3365 const LLVMValueRef iscompleteprim =
3366 LLVMBuildICmp(builder, LLVMIntUGE, curverts, tmp, "");
3367
3368 /* Since the geometry shader emits triangle strips, we need to
3369 * track which primitive is odd and swap vertex indices to get
3370 * the correct vertex order.
3371 */
3372 LLVMValueRef is_odd = ctx->ac.i1false;
3373 if (stream == 0 &&
3374 si_conv_gl_prim_to_vertices(ctx->shader->info.gs.output_primitive) == 3) {
3375 tmp = LLVMBuildAnd(builder, curverts, ctx->ac.i32_1, "");
3376 is_odd = LLVMBuildICmp(builder, LLVMIntEQ, tmp, ctx->ac.i32_1, "");
3377 }
3378
3379 tmp = LLVMBuildAdd(builder, curverts, ctx->ac.i32_1, "");
3380 LLVMBuildStore(builder, tmp, ctx->gs_curprim_verts[stream]);
3381
3382 /* The per-vertex primitive flag encoding:
3383 * bit 0: whether this vertex finishes a primitive
3384 * bit 1: whether the primitive is odd (if we are emitting triangle strips)
3385 */
3386 tmp = LLVMBuildZExt(builder, iscompleteprim, ctx->ac.i8, "");
3387 tmp = LLVMBuildOr(builder, tmp,
3388 LLVMBuildShl(builder,
3389 LLVMBuildZExt(builder, is_odd, ctx->ac.i8, ""),
3390 ctx->ac.i8_1, ""), "");
3391 LLVMBuildStore(builder, tmp,
3392 ngg_gs_get_emit_primflag_ptr(ctx, vertexptr, stream));
3393
3394 tmp = LLVMBuildLoad(builder, ctx->gs_generated_prims[stream], "");
3395 tmp = LLVMBuildAdd(builder, tmp, LLVMBuildZExt(builder, iscompleteprim, ctx->ac.i32, ""), "");
3396 LLVMBuildStore(builder, tmp, ctx->gs_generated_prims[stream]);
3397
3398 ac_build_endif(&ctx->ac, 9001);
3399 }
3400
3401 static void
3402 write_tess_factors(struct radv_shader_context *ctx)
3403 {
3404 unsigned stride, outer_comps, inner_comps;
3405 LLVMValueRef tcs_rel_ids = ac_get_arg(&ctx->ac, ctx->args->ac.tcs_rel_ids);
3406 LLVMValueRef invocation_id = ac_unpack_param(&ctx->ac, tcs_rel_ids, 8, 5);
3407 LLVMValueRef rel_patch_id = ac_unpack_param(&ctx->ac, tcs_rel_ids, 0, 8);
3408 unsigned tess_inner_index = 0, tess_outer_index;
3409 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
3410 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
3411 int i;
3412 ac_emit_barrier(&ctx->ac, ctx->stage);
3413
3414 switch (ctx->args->options->key.tcs.primitive_mode) {
3415 case GL_ISOLINES:
3416 stride = 2;
3417 outer_comps = 2;
3418 inner_comps = 0;
3419 break;
3420 case GL_TRIANGLES:
3421 stride = 4;
3422 outer_comps = 3;
3423 inner_comps = 1;
3424 break;
3425 case GL_QUADS:
3426 stride = 6;
3427 outer_comps = 4;
3428 inner_comps = 2;
3429 break;
3430 default:
3431 return;
3432 }
3433
3434 ac_build_ifcc(&ctx->ac,
3435 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3436 invocation_id, ctx->ac.i32_0, ""), 6503);
3437
3438 lds_base = get_tcs_out_current_patch_data_offset(ctx);
3439
3440 if (inner_comps) {
3441 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
3442 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
3443 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
3444 }
3445
3446 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
3447 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
3448 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
3449
3450 for (i = 0; i < 4; i++) {
3451 inner[i] = LLVMGetUndef(ctx->ac.i32);
3452 outer[i] = LLVMGetUndef(ctx->ac.i32);
3453 }
3454
3455 // LINES reversal
3456 if (ctx->args->options->key.tcs.primitive_mode == GL_ISOLINES) {
3457 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
3458 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
3459 ctx->ac.i32_1, "");
3460 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
3461 } else {
3462 for (i = 0; i < outer_comps; i++) {
3463 outer[i] = out[i] =
3464 ac_lds_load(&ctx->ac, lds_outer);
3465 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
3466 ctx->ac.i32_1, "");
3467 }
3468 for (i = 0; i < inner_comps; i++) {
3469 inner[i] = out[outer_comps+i] =
3470 ac_lds_load(&ctx->ac, lds_inner);
3471 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
3472 ctx->ac.i32_1, "");
3473 }
3474 }
3475
3476 /* Convert the outputs to vectors for stores. */
3477 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
3478 vec1 = NULL;
3479
3480 if (stride > 4)
3481 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
3482
3483
3484 buffer = ctx->hs_ring_tess_factor;
3485 tf_base = ac_get_arg(&ctx->ac, ctx->args->tess_factor_offset);
3486 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
3487 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
3488 unsigned tf_offset = 0;
3489
3490 if (ctx->ac.chip_class <= GFX8) {
3491 ac_build_ifcc(&ctx->ac,
3492 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3493 rel_patch_id, ctx->ac.i32_0, ""), 6504);
3494
3495 /* Store the dynamic HS control word. */
3496 ac_build_buffer_store_dword(&ctx->ac, buffer,
3497 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
3498 1, ctx->ac.i32_0, tf_base,
3499 0, ac_glc);
3500 tf_offset += 4;
3501
3502 ac_build_endif(&ctx->ac, 6504);
3503 }
3504
3505 /* Store the tessellation factors. */
3506 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
3507 MIN2(stride, 4), byteoffset, tf_base,
3508 tf_offset, ac_glc);
3509 if (vec1)
3510 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
3511 stride - 4, byteoffset, tf_base,
3512 16 + tf_offset, ac_glc);
3513
3514 //store to offchip for TES to read - only if TES reads them
3515 if (ctx->args->options->key.tcs.tes_reads_tess_factors) {
3516 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
3517 LLVMValueRef tf_inner_offset;
3518 unsigned param_outer, param_inner;
3519
3520 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
3521 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
3522 LLVMConstInt(ctx->ac.i32, param_outer, 0));
3523
3524 outer_vec = ac_build_gather_values(&ctx->ac, outer,
3525 util_next_power_of_two(outer_comps));
3526
3527 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
3528 outer_comps, tf_outer_offset,
3529 ac_get_arg(&ctx->ac, ctx->args->oc_lds),
3530 0, ac_glc);
3531 if (inner_comps) {
3532 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
3533 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
3534 LLVMConstInt(ctx->ac.i32, param_inner, 0));
3535
3536 inner_vec = inner_comps == 1 ? inner[0] :
3537 ac_build_gather_values(&ctx->ac, inner, inner_comps);
3538 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
3539 inner_comps, tf_inner_offset,
3540 ac_get_arg(&ctx->ac, ctx->args->oc_lds),
3541 0, ac_glc);
3542 }
3543 }
3544
3545 ac_build_endif(&ctx->ac, 6503);
3546 }
3547
3548 static void
3549 handle_tcs_outputs_post(struct radv_shader_context *ctx)
3550 {
3551 write_tess_factors(ctx);
3552 }
3553
3554 static bool
3555 si_export_mrt_color(struct radv_shader_context *ctx,
3556 LLVMValueRef *color, unsigned index,
3557 struct ac_export_args *args)
3558 {
3559 /* Export */
3560 si_llvm_init_export_args(ctx, color, 0xf,
3561 V_008DFC_SQ_EXP_MRT + index, args);
3562 if (!args->enabled_channels)
3563 return false; /* unnecessary NULL export */
3564
3565 return true;
3566 }
3567
3568 static void
3569 radv_export_mrt_z(struct radv_shader_context *ctx,
3570 LLVMValueRef depth, LLVMValueRef stencil,
3571 LLVMValueRef samplemask)
3572 {
3573 struct ac_export_args args;
3574
3575 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3576
3577 ac_build_export(&ctx->ac, &args);
3578 }
3579
3580 static void
3581 handle_fs_outputs_post(struct radv_shader_context *ctx)
3582 {
3583 unsigned index = 0;
3584 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3585 struct ac_export_args color_args[8];
3586
3587 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3588 LLVMValueRef values[4];
3589
3590 if (!(ctx->output_mask & (1ull << i)))
3591 continue;
3592
3593 if (i < FRAG_RESULT_DATA0)
3594 continue;
3595
3596 for (unsigned j = 0; j < 4; j++)
3597 values[j] = ac_to_float(&ctx->ac,
3598 radv_load_output(ctx, i, j));
3599
3600 bool ret = si_export_mrt_color(ctx, values,
3601 i - FRAG_RESULT_DATA0,
3602 &color_args[index]);
3603 if (ret)
3604 index++;
3605 }
3606
3607 /* Process depth, stencil, samplemask. */
3608 if (ctx->args->shader_info->ps.writes_z) {
3609 depth = ac_to_float(&ctx->ac,
3610 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
3611 }
3612 if (ctx->args->shader_info->ps.writes_stencil) {
3613 stencil = ac_to_float(&ctx->ac,
3614 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
3615 }
3616 if (ctx->args->shader_info->ps.writes_sample_mask) {
3617 samplemask = ac_to_float(&ctx->ac,
3618 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
3619 }
3620
3621 /* Set the DONE bit on last non-null color export only if Z isn't
3622 * exported.
3623 */
3624 if (index > 0 &&
3625 !ctx->args->shader_info->ps.writes_z &&
3626 !ctx->args->shader_info->ps.writes_stencil &&
3627 !ctx->args->shader_info->ps.writes_sample_mask) {
3628 unsigned last = index - 1;
3629
3630 color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */
3631 color_args[last].done = 1; /* DONE bit */
3632 }
3633
3634 /* Export PS outputs. */
3635 for (unsigned i = 0; i < index; i++)
3636 ac_build_export(&ctx->ac, &color_args[i]);
3637
3638 if (depth || stencil || samplemask)
3639 radv_export_mrt_z(ctx, depth, stencil, samplemask);
3640 else if (!index)
3641 ac_build_export_null(&ctx->ac);
3642 }
3643
3644 static void
3645 emit_gs_epilogue(struct radv_shader_context *ctx)
3646 {
3647 if (ctx->args->options->key.vs_common_out.as_ngg) {
3648 gfx10_ngg_gs_emit_epilogue_1(ctx);
3649 return;
3650 }
3651
3652 if (ctx->ac.chip_class >= GFX10)
3653 LLVMBuildFence(ctx->ac.builder, LLVMAtomicOrderingRelease, false, "");
3654
3655 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
3656 }
3657
3658 static void
3659 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
3660 LLVMValueRef *addrs)
3661 {
3662 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3663
3664 switch (ctx->stage) {
3665 case MESA_SHADER_VERTEX:
3666 if (ctx->args->options->key.vs_common_out.as_ls)
3667 handle_ls_outputs_post(ctx);
3668 else if (ctx->args->options->key.vs_common_out.as_es)
3669 handle_es_outputs_post(ctx, &ctx->args->shader_info->vs.es_info);
3670 else if (ctx->args->options->key.vs_common_out.as_ngg)
3671 handle_ngg_outputs_post_1(ctx);
3672 else
3673 handle_vs_outputs_post(ctx, ctx->args->options->key.vs_common_out.export_prim_id,
3674 ctx->args->options->key.vs_common_out.export_clip_dists,
3675 &ctx->args->shader_info->vs.outinfo);
3676 break;
3677 case MESA_SHADER_FRAGMENT:
3678 handle_fs_outputs_post(ctx);
3679 break;
3680 case MESA_SHADER_GEOMETRY:
3681 emit_gs_epilogue(ctx);
3682 break;
3683 case MESA_SHADER_TESS_CTRL:
3684 handle_tcs_outputs_post(ctx);
3685 break;
3686 case MESA_SHADER_TESS_EVAL:
3687 if (ctx->args->options->key.vs_common_out.as_es)
3688 handle_es_outputs_post(ctx, &ctx->args->shader_info->tes.es_info);
3689 else if (ctx->args->options->key.vs_common_out.as_ngg)
3690 handle_ngg_outputs_post_1(ctx);
3691 else
3692 handle_vs_outputs_post(ctx, ctx->args->options->key.vs_common_out.export_prim_id,
3693 ctx->args->options->key.vs_common_out.export_clip_dists,
3694 &ctx->args->shader_info->tes.outinfo);
3695 break;
3696 default:
3697 break;
3698 }
3699 }
3700
3701 static void ac_llvm_finalize_module(struct radv_shader_context *ctx,
3702 LLVMPassManagerRef passmgr,
3703 const struct radv_nir_compiler_options *options)
3704 {
3705 LLVMRunPassManager(passmgr, ctx->ac.module);
3706 LLVMDisposeBuilder(ctx->ac.builder);
3707
3708 ac_llvm_context_dispose(&ctx->ac);
3709 }
3710
3711 static void
3712 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
3713 {
3714 struct radv_vs_output_info *outinfo;
3715
3716 switch (ctx->stage) {
3717 case MESA_SHADER_FRAGMENT:
3718 case MESA_SHADER_COMPUTE:
3719 case MESA_SHADER_TESS_CTRL:
3720 case MESA_SHADER_GEOMETRY:
3721 return;
3722 case MESA_SHADER_VERTEX:
3723 if (ctx->args->options->key.vs_common_out.as_ls ||
3724 ctx->args->options->key.vs_common_out.as_es)
3725 return;
3726 outinfo = &ctx->args->shader_info->vs.outinfo;
3727 break;
3728 case MESA_SHADER_TESS_EVAL:
3729 if (ctx->args->options->key.vs_common_out.as_es)
3730 return;
3731 outinfo = &ctx->args->shader_info->tes.outinfo;
3732 break;
3733 default:
3734 unreachable("Unhandled shader type");
3735 }
3736
3737 ac_optimize_vs_outputs(&ctx->ac,
3738 ctx->main_function,
3739 outinfo->vs_output_param_offset,
3740 VARYING_SLOT_MAX,
3741 &outinfo->param_exports);
3742 }
3743
3744 static void
3745 ac_setup_rings(struct radv_shader_context *ctx)
3746 {
3747 if (ctx->args->options->chip_class <= GFX8 &&
3748 (ctx->stage == MESA_SHADER_GEOMETRY ||
3749 ctx->args->options->key.vs_common_out.as_es || ctx->args->options->key.vs_common_out.as_es)) {
3750 unsigned ring = ctx->stage == MESA_SHADER_GEOMETRY ? RING_ESGS_GS
3751 : RING_ESGS_VS;
3752 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, ring, false);
3753
3754 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac,
3755 ctx->ring_offsets,
3756 offset);
3757 }
3758
3759 if (ctx->args->is_gs_copy_shader) {
3760 ctx->gsvs_ring[0] =
3761 ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets,
3762 LLVMConstInt(ctx->ac.i32,
3763 RING_GSVS_VS, false));
3764 }
3765
3766 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3767 /* The conceptual layout of the GSVS ring is
3768 * v0c0 .. vLv0 v0c1 .. vLc1 ..
3769 * but the real memory layout is swizzled across
3770 * threads:
3771 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
3772 * t16v0c0 ..
3773 * Override the buffer descriptor accordingly.
3774 */
3775 LLVMTypeRef v2i64 = LLVMVectorType(ctx->ac.i64, 2);
3776 uint64_t stream_offset = 0;
3777 unsigned num_records = ctx->ac.wave_size;
3778 LLVMValueRef base_ring;
3779
3780 base_ring =
3781 ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets,
3782 LLVMConstInt(ctx->ac.i32,
3783 RING_GSVS_GS, false));
3784
3785 for (unsigned stream = 0; stream < 4; stream++) {
3786 unsigned num_components, stride;
3787 LLVMValueRef ring, tmp;
3788
3789 num_components =
3790 ctx->args->shader_info->gs.num_stream_output_components[stream];
3791
3792 if (!num_components)
3793 continue;
3794
3795 stride = 4 * num_components * ctx->shader->info.gs.vertices_out;
3796
3797 /* Limit on the stride field for <= GFX7. */
3798 assert(stride < (1 << 14));
3799
3800 ring = LLVMBuildBitCast(ctx->ac.builder,
3801 base_ring, v2i64, "");
3802 tmp = LLVMBuildExtractElement(ctx->ac.builder,
3803 ring, ctx->ac.i32_0, "");
3804 tmp = LLVMBuildAdd(ctx->ac.builder, tmp,
3805 LLVMConstInt(ctx->ac.i64,
3806 stream_offset, 0), "");
3807 ring = LLVMBuildInsertElement(ctx->ac.builder,
3808 ring, tmp, ctx->ac.i32_0, "");
3809
3810 stream_offset += stride * ctx->ac.wave_size;
3811
3812 ring = LLVMBuildBitCast(ctx->ac.builder, ring,
3813 ctx->ac.v4i32, "");
3814
3815 tmp = LLVMBuildExtractElement(ctx->ac.builder, ring,
3816 ctx->ac.i32_1, "");
3817 tmp = LLVMBuildOr(ctx->ac.builder, tmp,
3818 LLVMConstInt(ctx->ac.i32,
3819 S_008F04_STRIDE(stride), false), "");
3820 ring = LLVMBuildInsertElement(ctx->ac.builder, ring, tmp,
3821 ctx->ac.i32_1, "");
3822
3823 ring = LLVMBuildInsertElement(ctx->ac.builder, ring,
3824 LLVMConstInt(ctx->ac.i32,
3825 num_records, false),
3826 LLVMConstInt(ctx->ac.i32, 2, false), "");
3827
3828 ctx->gsvs_ring[stream] = ring;
3829 }
3830 }
3831
3832 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3833 ctx->stage == MESA_SHADER_TESS_EVAL) {
3834 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
3835 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
3836 }
3837 }
3838
3839 unsigned
3840 radv_nir_get_max_workgroup_size(enum chip_class chip_class,
3841 gl_shader_stage stage,
3842 const struct nir_shader *nir)
3843 {
3844 const unsigned backup_sizes[] = {chip_class >= GFX9 ? 128 : 64, 1, 1};
3845 unsigned sizes[3];
3846 for (unsigned i = 0; i < 3; i++)
3847 sizes[i] = nir ? nir->info.cs.local_size[i] : backup_sizes[i];
3848 return radv_get_max_workgroup_size(chip_class, stage, sizes);
3849 }
3850
3851 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
3852 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
3853 {
3854 LLVMValueRef count =
3855 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 8, 8);
3856 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
3857 ctx->ac.i32_0, "");
3858 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty,
3859 ac_get_arg(&ctx->ac, ctx->args->rel_auto_id),
3860 ctx->abi.instance_id, "");
3861 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty,
3862 ac_get_arg(&ctx->ac, ctx->args->ac.tcs_rel_ids),
3863 ctx->rel_auto_id,
3864 "");
3865 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty,
3866 ac_get_arg(&ctx->ac, ctx->args->ac.tcs_patch_id),
3867 ctx->abi.vertex_id, "");
3868 }
3869
3870 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx, bool merged)
3871 {
3872 if (merged) {
3873 for(int i = 5; i >= 0; --i) {
3874 ctx->gs_vtx_offset[i] =
3875 ac_unpack_param(&ctx->ac,
3876 ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[i & ~1]),
3877 (i & 1) * 16, 16);
3878 }
3879
3880 ctx->gs_wave_id = ac_unpack_param(&ctx->ac,
3881 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info),
3882 16, 8);
3883 } else {
3884 for (int i = 0; i < 6; i++)
3885 ctx->gs_vtx_offset[i] = ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[i]);
3886 ctx->gs_wave_id = ac_get_arg(&ctx->ac, ctx->args->gs_wave_id);
3887 }
3888 }
3889
3890 /* Ensure that the esgs ring is declared.
3891 *
3892 * We declare it with 64KB alignment as a hint that the
3893 * pointer value will always be 0.
3894 */
3895 static void declare_esgs_ring(struct radv_shader_context *ctx)
3896 {
3897 if (ctx->esgs_ring)
3898 return;
3899
3900 assert(!LLVMGetNamedGlobal(ctx->ac.module, "esgs_ring"));
3901
3902 ctx->esgs_ring = LLVMAddGlobalInAddressSpace(
3903 ctx->ac.module, LLVMArrayType(ctx->ac.i32, 0),
3904 "esgs_ring",
3905 AC_ADDR_SPACE_LDS);
3906 LLVMSetLinkage(ctx->esgs_ring, LLVMExternalLinkage);
3907 LLVMSetAlignment(ctx->esgs_ring, 64 * 1024);
3908 }
3909
3910 static
3911 LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
3912 struct nir_shader *const *shaders,
3913 int shader_count,
3914 const struct radv_shader_args *args)
3915 {
3916 struct radv_shader_context ctx = {0};
3917 ctx.args = args;
3918
3919 enum ac_float_mode float_mode = AC_FLOAT_MODE_DEFAULT;
3920
3921 if (args->shader_info->float_controls_mode & FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32) {
3922 float_mode = AC_FLOAT_MODE_DENORM_FLUSH_TO_ZERO;
3923 }
3924
3925 ac_llvm_context_init(&ctx.ac, ac_llvm, args->options->chip_class,
3926 args->options->family, float_mode,
3927 args->shader_info->wave_size, 64);
3928 ctx.context = ctx.ac.context;
3929
3930 ctx.max_workgroup_size = 0;
3931 for (int i = 0; i < shader_count; ++i) {
3932 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
3933 radv_nir_get_max_workgroup_size(args->options->chip_class,
3934 shaders[i]->info.stage,
3935 shaders[i]));
3936 }
3937
3938 if (ctx.ac.chip_class >= GFX10) {
3939 if (is_pre_gs_stage(shaders[0]->info.stage) &&
3940 args->options->key.vs_common_out.as_ngg) {
3941 ctx.max_workgroup_size = 128;
3942 }
3943 }
3944
3945 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2);
3946
3947 ctx.abi.inputs = &ctx.inputs[0];
3948 ctx.abi.emit_outputs = handle_shader_outputs_post;
3949 ctx.abi.emit_vertex = visit_emit_vertex;
3950 ctx.abi.load_ubo = radv_load_ubo;
3951 ctx.abi.load_ssbo = radv_load_ssbo;
3952 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
3953 ctx.abi.load_resource = radv_load_resource;
3954 ctx.abi.clamp_shadow_reference = false;
3955 ctx.abi.robust_buffer_access = args->options->robust_buffer_access;
3956
3957 bool is_ngg = is_pre_gs_stage(shaders[0]->info.stage) && args->options->key.vs_common_out.as_ngg;
3958 if (shader_count >= 2 || is_ngg)
3959 ac_init_exec_full_mask(&ctx.ac);
3960
3961 if (args->ac.vertex_id.used)
3962 ctx.abi.vertex_id = ac_get_arg(&ctx.ac, args->ac.vertex_id);
3963 if (args->rel_auto_id.used)
3964 ctx.rel_auto_id = ac_get_arg(&ctx.ac, args->rel_auto_id);
3965 if (args->ac.instance_id.used)
3966 ctx.abi.instance_id = ac_get_arg(&ctx.ac, args->ac.instance_id);
3967
3968 if (args->options->has_ls_vgpr_init_bug &&
3969 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
3970 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
3971
3972 if (is_ngg) {
3973 /* Declare scratch space base for streamout and vertex
3974 * compaction. Whether space is actually allocated is
3975 * determined during linking / PM4 creation.
3976 *
3977 * Add an extra dword per vertex to ensure an odd stride, which
3978 * avoids bank conflicts for SoA accesses.
3979 */
3980 if (!args->options->key.vs_common_out.as_ngg_passthrough)
3981 declare_esgs_ring(&ctx);
3982
3983 /* This is really only needed when streamout and / or vertex
3984 * compaction is enabled.
3985 */
3986 if (args->shader_info->so.num_outputs) {
3987 LLVMTypeRef asi32 = LLVMArrayType(ctx.ac.i32, 8);
3988 ctx.gs_ngg_scratch = LLVMAddGlobalInAddressSpace(ctx.ac.module,
3989 asi32, "ngg_scratch", AC_ADDR_SPACE_LDS);
3990 LLVMSetInitializer(ctx.gs_ngg_scratch, LLVMGetUndef(asi32));
3991 LLVMSetAlignment(ctx.gs_ngg_scratch, 4);
3992 }
3993 }
3994
3995 for(int i = 0; i < shader_count; ++i) {
3996 ctx.stage = shaders[i]->info.stage;
3997 ctx.shader = shaders[i];
3998 ctx.output_mask = 0;
3999
4000 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
4001 for (int i = 0; i < 4; i++) {
4002 ctx.gs_next_vertex[i] =
4003 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
4004 }
4005 if (args->options->key.vs_common_out.as_ngg) {
4006 for (unsigned i = 0; i < 4; ++i) {
4007 ctx.gs_curprim_verts[i] =
4008 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
4009 ctx.gs_generated_prims[i] =
4010 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
4011 }
4012
4013 unsigned scratch_size = 8;
4014 if (args->shader_info->so.num_outputs)
4015 scratch_size = 44;
4016
4017 LLVMTypeRef ai32 = LLVMArrayType(ctx.ac.i32, scratch_size);
4018 ctx.gs_ngg_scratch =
4019 LLVMAddGlobalInAddressSpace(ctx.ac.module,
4020 ai32, "ngg_scratch", AC_ADDR_SPACE_LDS);
4021 LLVMSetInitializer(ctx.gs_ngg_scratch, LLVMGetUndef(ai32));
4022 LLVMSetAlignment(ctx.gs_ngg_scratch, 4);
4023
4024 ctx.gs_ngg_emit = LLVMAddGlobalInAddressSpace(ctx.ac.module,
4025 LLVMArrayType(ctx.ac.i32, 0), "ngg_emit", AC_ADDR_SPACE_LDS);
4026 LLVMSetLinkage(ctx.gs_ngg_emit, LLVMExternalLinkage);
4027 LLVMSetAlignment(ctx.gs_ngg_emit, 4);
4028 }
4029
4030 ctx.abi.load_inputs = load_gs_input;
4031 ctx.abi.emit_primitive = visit_end_primitive;
4032 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
4033 ctx.abi.load_tess_varyings = load_tcs_varyings;
4034 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
4035 ctx.abi.store_tcs_outputs = store_tcs_output;
4036 if (shader_count == 1)
4037 ctx.tcs_num_inputs = args->options->key.tcs.num_inputs;
4038 else
4039 ctx.tcs_num_inputs = util_last_bit64(args->shader_info->vs.ls_outputs_written);
4040 ctx.tcs_num_patches =
4041 get_tcs_num_patches(
4042 ctx.args->options->key.tcs.input_vertices,
4043 ctx.shader->info.tess.tcs_vertices_out,
4044 ctx.tcs_num_inputs,
4045 ctx.args->shader_info->tcs.outputs_written,
4046 ctx.args->shader_info->tcs.patch_outputs_written,
4047 ctx.args->options->tess_offchip_block_dw_size,
4048 ctx.args->options->chip_class,
4049 ctx.args->options->family);
4050 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
4051 ctx.abi.load_tess_varyings = load_tes_input;
4052 ctx.abi.load_tess_coord = load_tess_coord;
4053 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
4054 ctx.tcs_num_patches = args->options->key.tes.num_patches;
4055 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
4056 ctx.abi.load_base_vertex = radv_load_base_vertex;
4057 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
4058 ctx.abi.load_sample_position = load_sample_position;
4059 ctx.abi.load_sample_mask_in = load_sample_mask_in;
4060 }
4061
4062 if (shaders[i]->info.stage == MESA_SHADER_VERTEX &&
4063 args->options->key.vs_common_out.as_ngg &&
4064 args->options->key.vs_common_out.export_prim_id) {
4065 declare_esgs_ring(&ctx);
4066 }
4067
4068 bool nested_barrier = false;
4069
4070 if (i) {
4071 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
4072 args->options->key.vs_common_out.as_ngg) {
4073 gfx10_ngg_gs_emit_prologue(&ctx);
4074 nested_barrier = false;
4075 } else {
4076 nested_barrier = true;
4077 }
4078 }
4079
4080 if (nested_barrier) {
4081 /* Execute a barrier before the second shader in
4082 * a merged shader.
4083 *
4084 * Execute the barrier inside the conditional block,
4085 * so that empty waves can jump directly to s_endpgm,
4086 * which will also signal the barrier.
4087 *
4088 * This is possible in gfx9, because an empty wave
4089 * for the second shader does not participate in
4090 * the epilogue. With NGG, empty waves may still
4091 * be required to export data (e.g. GS output vertices),
4092 * so we cannot let them exit early.
4093 *
4094 * If the shader is TCS and the TCS epilog is present
4095 * and contains a barrier, it will wait there and then
4096 * reach s_endpgm.
4097 */
4098 ac_emit_barrier(&ctx.ac, ctx.stage);
4099 }
4100
4101 nir_foreach_variable(variable, &shaders[i]->outputs)
4102 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
4103
4104 ac_setup_rings(&ctx);
4105
4106 LLVMBasicBlockRef merge_block = NULL;
4107 if (shader_count >= 2 || is_ngg) {
4108 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
4109 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
4110 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
4111
4112 LLVMValueRef count =
4113 ac_unpack_param(&ctx.ac,
4114 ac_get_arg(&ctx.ac, args->merged_wave_info),
4115 8 * i, 8);
4116 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
4117 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
4118 thread_id, count, "");
4119 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
4120
4121 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
4122 }
4123
4124 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
4125 prepare_interp_optimize(&ctx, shaders[i]);
4126 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
4127 handle_vs_inputs(&ctx, shaders[i]);
4128 else if(shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
4129 prepare_gs_input_vgprs(&ctx, shader_count >= 2);
4130
4131 ac_nir_translate(&ctx.ac, &ctx.abi, &args->ac, shaders[i]);
4132
4133 if (shader_count >= 2 || is_ngg) {
4134 LLVMBuildBr(ctx.ac.builder, merge_block);
4135 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
4136 }
4137
4138 /* This needs to be outside the if wrapping the shader body, as sometimes
4139 * the HW generates waves with 0 es/vs threads. */
4140 if (is_pre_gs_stage(shaders[i]->info.stage) &&
4141 args->options->key.vs_common_out.as_ngg &&
4142 i == shader_count - 1) {
4143 handle_ngg_outputs_post_2(&ctx);
4144 } else if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
4145 args->options->key.vs_common_out.as_ngg) {
4146 gfx10_ngg_gs_emit_epilogue_2(&ctx);
4147 }
4148
4149 if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
4150 args->shader_info->tcs.num_patches = ctx.tcs_num_patches;
4151 args->shader_info->tcs.lds_size =
4152 calculate_tess_lds_size(
4153 ctx.args->options->key.tcs.input_vertices,
4154 ctx.shader->info.tess.tcs_vertices_out,
4155 ctx.tcs_num_inputs,
4156 ctx.tcs_num_patches,
4157 ctx.args->shader_info->tcs.outputs_written,
4158 ctx.args->shader_info->tcs.patch_outputs_written);
4159 }
4160 }
4161
4162 LLVMBuildRetVoid(ctx.ac.builder);
4163
4164 if (args->options->dump_preoptir) {
4165 fprintf(stderr, "%s LLVM IR:\n\n",
4166 radv_get_shader_name(args->shader_info,
4167 shaders[shader_count - 1]->info.stage));
4168 ac_dump_module(ctx.ac.module);
4169 fprintf(stderr, "\n");
4170 }
4171
4172 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, args->options);
4173
4174 if (shader_count == 1)
4175 ac_nir_eliminate_const_vs_outputs(&ctx);
4176
4177 if (args->options->dump_shader) {
4178 args->shader_info->private_mem_vgprs =
4179 ac_count_scratch_private_memory(ctx.main_function);
4180 }
4181
4182 return ctx.ac.module;
4183 }
4184
4185 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
4186 {
4187 unsigned *retval = (unsigned *)context;
4188 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
4189 char *description = LLVMGetDiagInfoDescription(di);
4190
4191 if (severity == LLVMDSError) {
4192 *retval = 1;
4193 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
4194 description);
4195 }
4196
4197 LLVMDisposeMessage(description);
4198 }
4199
4200 static unsigned radv_llvm_compile(LLVMModuleRef M,
4201 char **pelf_buffer, size_t *pelf_size,
4202 struct ac_llvm_compiler *ac_llvm)
4203 {
4204 unsigned retval = 0;
4205 LLVMContextRef llvm_ctx;
4206
4207 /* Setup Diagnostic Handler*/
4208 llvm_ctx = LLVMGetModuleContext(M);
4209
4210 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
4211 &retval);
4212
4213 /* Compile IR*/
4214 if (!radv_compile_to_elf(ac_llvm, M, pelf_buffer, pelf_size))
4215 retval = 1;
4216 return retval;
4217 }
4218
4219 static void ac_compile_llvm_module(struct ac_llvm_compiler *ac_llvm,
4220 LLVMModuleRef llvm_module,
4221 struct radv_shader_binary **rbinary,
4222 gl_shader_stage stage,
4223 const char *name,
4224 const struct radv_nir_compiler_options *options)
4225 {
4226 char *elf_buffer = NULL;
4227 size_t elf_size = 0;
4228 char *llvm_ir_string = NULL;
4229
4230 if (options->dump_shader) {
4231 fprintf(stderr, "%s LLVM IR:\n\n", name);
4232 ac_dump_module(llvm_module);
4233 fprintf(stderr, "\n");
4234 }
4235
4236 if (options->record_ir) {
4237 char *llvm_ir = LLVMPrintModuleToString(llvm_module);
4238 llvm_ir_string = strdup(llvm_ir);
4239 LLVMDisposeMessage(llvm_ir);
4240 }
4241
4242 int v = radv_llvm_compile(llvm_module, &elf_buffer, &elf_size, ac_llvm);
4243 if (v) {
4244 fprintf(stderr, "compile failed\n");
4245 }
4246
4247 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
4248 LLVMDisposeModule(llvm_module);
4249 LLVMContextDispose(ctx);
4250
4251 size_t llvm_ir_size = llvm_ir_string ? strlen(llvm_ir_string) : 0;
4252 size_t alloc_size = sizeof(struct radv_shader_binary_rtld) + elf_size + llvm_ir_size + 1;
4253 struct radv_shader_binary_rtld *rbin = calloc(1, alloc_size);
4254 memcpy(rbin->data, elf_buffer, elf_size);
4255 if (llvm_ir_string)
4256 memcpy(rbin->data + elf_size, llvm_ir_string, llvm_ir_size + 1);
4257
4258 rbin->base.type = RADV_BINARY_TYPE_RTLD;
4259 rbin->base.stage = stage;
4260 rbin->base.total_size = alloc_size;
4261 rbin->elf_size = elf_size;
4262 rbin->llvm_ir_size = llvm_ir_size;
4263 *rbinary = &rbin->base;
4264
4265 free(llvm_ir_string);
4266 free(elf_buffer);
4267 }
4268
4269 void
4270 radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
4271 struct radv_shader_binary **rbinary,
4272 const struct radv_shader_args *args,
4273 struct nir_shader *const *nir,
4274 int nir_count)
4275 {
4276
4277 LLVMModuleRef llvm_module;
4278
4279 llvm_module = ac_translate_nir_to_llvm(ac_llvm, nir, nir_count, args);
4280
4281 ac_compile_llvm_module(ac_llvm, llvm_module, rbinary,
4282 nir[nir_count - 1]->info.stage,
4283 radv_get_shader_name(args->shader_info,
4284 nir[nir_count - 1]->info.stage),
4285 args->options);
4286
4287 /* Determine the ES type (VS or TES) for the GS on GFX9. */
4288 if (args->options->chip_class >= GFX9) {
4289 if (nir_count == 2 &&
4290 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
4291 args->shader_info->gs.es_type = nir[0]->info.stage;
4292 }
4293 }
4294 }
4295
4296 static void
4297 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
4298 {
4299 LLVMValueRef vtx_offset =
4300 LLVMBuildMul(ctx->ac.builder, ac_get_arg(&ctx->ac, ctx->args->ac.vertex_id),
4301 LLVMConstInt(ctx->ac.i32, 4, false), "");
4302 LLVMValueRef stream_id;
4303
4304 /* Fetch the vertex stream ID. */
4305 if (!ctx->args->options->use_ngg_streamout &&
4306 ctx->args->shader_info->so.num_outputs) {
4307 stream_id =
4308 ac_unpack_param(&ctx->ac,
4309 ac_get_arg(&ctx->ac,
4310 ctx->args->streamout_config),
4311 24, 2);
4312 } else {
4313 stream_id = ctx->ac.i32_0;
4314 }
4315
4316 LLVMBasicBlockRef end_bb;
4317 LLVMValueRef switch_inst;
4318
4319 end_bb = LLVMAppendBasicBlockInContext(ctx->ac.context,
4320 ctx->main_function, "end");
4321 switch_inst = LLVMBuildSwitch(ctx->ac.builder, stream_id, end_bb, 4);
4322
4323 for (unsigned stream = 0; stream < 4; stream++) {
4324 unsigned num_components =
4325 ctx->args->shader_info->gs.num_stream_output_components[stream];
4326 LLVMBasicBlockRef bb;
4327 unsigned offset;
4328
4329 if (stream > 0 && !num_components)
4330 continue;
4331
4332 if (stream > 0 && !ctx->args->shader_info->so.num_outputs)
4333 continue;
4334
4335 bb = LLVMInsertBasicBlockInContext(ctx->ac.context, end_bb, "out");
4336 LLVMAddCase(switch_inst, LLVMConstInt(ctx->ac.i32, stream, 0), bb);
4337 LLVMPositionBuilderAtEnd(ctx->ac.builder, bb);
4338
4339 offset = 0;
4340 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
4341 unsigned output_usage_mask =
4342 ctx->args->shader_info->gs.output_usage_mask[i];
4343 unsigned output_stream =
4344 ctx->args->shader_info->gs.output_streams[i];
4345 int length = util_last_bit(output_usage_mask);
4346
4347 if (!(ctx->output_mask & (1ull << i)) ||
4348 output_stream != stream)
4349 continue;
4350
4351 for (unsigned j = 0; j < length; j++) {
4352 LLVMValueRef value, soffset;
4353
4354 if (!(output_usage_mask & (1 << j)))
4355 continue;
4356
4357 soffset = LLVMConstInt(ctx->ac.i32,
4358 offset *
4359 ctx->shader->info.gs.vertices_out * 16 * 4, false);
4360
4361 offset++;
4362
4363 value = ac_build_buffer_load(&ctx->ac,
4364 ctx->gsvs_ring[0],
4365 1, ctx->ac.i32_0,
4366 vtx_offset, soffset,
4367 0, ac_glc | ac_slc, true, false);
4368
4369 LLVMTypeRef type = LLVMGetAllocatedType(ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
4370 if (ac_get_type_size(type) == 2) {
4371 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
4372 value = LLVMBuildTrunc(ctx->ac.builder, value, ctx->ac.i16, "");
4373 }
4374
4375 LLVMBuildStore(ctx->ac.builder,
4376 ac_to_float(&ctx->ac, value), ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
4377 }
4378 }
4379
4380 if (!ctx->args->options->use_ngg_streamout &&
4381 ctx->args->shader_info->so.num_outputs)
4382 radv_emit_streamout(ctx, stream);
4383
4384 if (stream == 0) {
4385 handle_vs_outputs_post(ctx, false, true,
4386 &ctx->args->shader_info->vs.outinfo);
4387 }
4388
4389 LLVMBuildBr(ctx->ac.builder, end_bb);
4390 }
4391
4392 LLVMPositionBuilderAtEnd(ctx->ac.builder, end_bb);
4393 }
4394
4395 void
4396 radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
4397 struct nir_shader *geom_shader,
4398 struct radv_shader_binary **rbinary,
4399 const struct radv_shader_args *args)
4400 {
4401 struct radv_shader_context ctx = {0};
4402 ctx.args = args;
4403
4404 assert(args->is_gs_copy_shader);
4405
4406 ac_llvm_context_init(&ctx.ac, ac_llvm, args->options->chip_class,
4407 args->options->family, AC_FLOAT_MODE_DEFAULT, 64, 64);
4408 ctx.context = ctx.ac.context;
4409
4410 ctx.stage = MESA_SHADER_VERTEX;
4411 ctx.shader = geom_shader;
4412
4413 create_function(&ctx, MESA_SHADER_VERTEX, false);
4414
4415 ac_setup_rings(&ctx);
4416
4417 nir_foreach_variable(variable, &geom_shader->outputs) {
4418 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
4419 ac_handle_shader_output_decl(&ctx.ac, &ctx.abi, geom_shader,
4420 variable, MESA_SHADER_VERTEX);
4421 }
4422
4423 ac_gs_copy_shader_emit(&ctx);
4424
4425 LLVMBuildRetVoid(ctx.ac.builder);
4426
4427 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, args->options);
4428
4429 ac_compile_llvm_module(ac_llvm, ctx.ac.module, rbinary,
4430 MESA_SHADER_VERTEX, "GS Copy Shader", args->options);
4431 (*rbinary)->is_gs_copy_shader = true;
4432
4433 }