2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "radv_shader_helper.h"
33 #include <llvm-c/Core.h>
34 #include <llvm-c/TargetMachine.h>
35 #include <llvm-c/Transforms/Scalar.h>
36 #include <llvm-c/Transforms/Utils.h>
39 #include "ac_binary.h"
40 #include "ac_llvm_util.h"
41 #include "ac_llvm_build.h"
42 #include "ac_shader_abi.h"
43 #include "ac_shader_util.h"
44 #include "ac_exp_param.h"
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
48 struct radv_shader_context
{
49 struct ac_llvm_context ac
;
50 const struct radv_nir_compiler_options
*options
;
51 struct radv_shader_info
*shader_info
;
52 const struct nir_shader
*shader
;
53 struct ac_shader_abi abi
;
55 unsigned max_workgroup_size
;
56 LLVMContextRef context
;
57 LLVMValueRef main_function
;
59 LLVMValueRef descriptor_sets
[MAX_SETS
];
60 LLVMValueRef ring_offsets
;
62 LLVMValueRef vertex_buffers
;
63 LLVMValueRef rel_auto_id
;
64 LLVMValueRef vs_prim_id
;
65 LLVMValueRef es2gs_offset
;
68 LLVMValueRef merged_wave_info
;
69 LLVMValueRef tess_factor_offset
;
70 LLVMValueRef tes_rel_patch_id
;
76 * - bits 0..10: ordered_wave_id
77 * - bits 12..20: number of vertices in group
78 * - bits 22..30: number of primitives in group
80 LLVMValueRef gs_tg_info
;
81 LLVMValueRef gs2vs_offset
;
82 LLVMValueRef gs_wave_id
;
83 LLVMValueRef gs_vtx_offset
[6];
85 LLVMValueRef esgs_ring
;
86 LLVMValueRef gsvs_ring
[4];
87 LLVMValueRef hs_ring_tess_offchip
;
88 LLVMValueRef hs_ring_tess_factor
;
91 LLVMValueRef streamout_buffers
;
92 LLVMValueRef streamout_write_idx
;
93 LLVMValueRef streamout_config
;
94 LLVMValueRef streamout_offset
[4];
96 gl_shader_stage stage
;
98 LLVMValueRef inputs
[RADEON_LLVM_MAX_INPUTS
* 4];
100 uint64_t output_mask
;
102 bool is_gs_copy_shader
;
103 LLVMValueRef gs_next_vertex
[4];
104 LLVMValueRef gs_curprim_verts
[4];
105 LLVMValueRef gs_generated_prims
[4];
106 LLVMValueRef gs_ngg_emit
;
107 LLVMValueRef gs_ngg_scratch
;
109 uint32_t tcs_num_inputs
;
110 uint32_t tcs_num_patches
;
112 LLVMValueRef vertexptr
; /* GFX10 only */
115 struct radv_shader_output_values
{
116 LLVMValueRef values
[4];
122 enum radeon_llvm_calling_convention
{
123 RADEON_LLVM_AMDGPU_VS
= 87,
124 RADEON_LLVM_AMDGPU_GS
= 88,
125 RADEON_LLVM_AMDGPU_PS
= 89,
126 RADEON_LLVM_AMDGPU_CS
= 90,
127 RADEON_LLVM_AMDGPU_HS
= 93,
130 static inline struct radv_shader_context
*
131 radv_shader_context_from_abi(struct ac_shader_abi
*abi
)
133 struct radv_shader_context
*ctx
= NULL
;
134 return container_of(abi
, ctx
, abi
);
137 static LLVMValueRef
get_rel_patch_id(struct radv_shader_context
*ctx
)
139 switch (ctx
->stage
) {
140 case MESA_SHADER_TESS_CTRL
:
141 return ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
142 case MESA_SHADER_TESS_EVAL
:
143 return ctx
->tes_rel_patch_id
;
146 unreachable("Illegal stage");
151 get_tcs_num_patches(struct radv_shader_context
*ctx
)
153 unsigned num_tcs_input_cp
= ctx
->options
->key
.tcs
.input_vertices
;
154 unsigned num_tcs_output_cp
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
155 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
156 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
157 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->tcs
.outputs_written
);
158 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->tcs
.patch_outputs_written
);
159 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
160 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
161 uint32_t output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
162 unsigned num_patches
;
163 unsigned hardware_lds_size
;
165 /* Ensure that we only need one wave per SIMD so we don't need to check
166 * resource usage. Also ensures that the number of tcs in and out
167 * vertices per threadgroup are at most 256.
169 num_patches
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
) * 4;
170 /* Make sure that the data fits in LDS. This assumes the shaders only
171 * use LDS for the inputs and outputs.
173 hardware_lds_size
= 32768;
175 /* Looks like STONEY hangs if we use more than 32 KiB LDS in a single
176 * threadgroup, even though there is more than 32 KiB LDS.
178 * Test: dEQP-VK.tessellation.shader_input_output.barrier
180 if (ctx
->options
->chip_class
>= GFX7
&& ctx
->options
->family
!= CHIP_STONEY
)
181 hardware_lds_size
= 65536;
183 num_patches
= MIN2(num_patches
, hardware_lds_size
/ (input_patch_size
+ output_patch_size
));
184 /* Make sure the output data fits in the offchip buffer */
185 num_patches
= MIN2(num_patches
, (ctx
->options
->tess_offchip_block_dw_size
* 4) / output_patch_size
);
186 /* Not necessary for correctness, but improves performance. The
187 * specific value is taken from the proprietary driver.
189 num_patches
= MIN2(num_patches
, 40);
191 /* GFX6 bug workaround - limit LS-HS threadgroups to only one wave. */
192 if (ctx
->options
->chip_class
== GFX6
) {
193 unsigned one_wave
= ctx
->options
->wave_size
/ MAX2(num_tcs_input_cp
, num_tcs_output_cp
);
194 num_patches
= MIN2(num_patches
, one_wave
);
200 calculate_tess_lds_size(struct radv_shader_context
*ctx
)
202 unsigned num_tcs_input_cp
= ctx
->options
->key
.tcs
.input_vertices
;
203 unsigned num_tcs_output_cp
;
204 unsigned num_tcs_outputs
, num_tcs_patch_outputs
;
205 unsigned input_vertex_size
, output_vertex_size
;
206 unsigned input_patch_size
, output_patch_size
;
207 unsigned pervertex_output_patch_size
;
208 unsigned output_patch0_offset
;
209 unsigned num_patches
;
212 num_tcs_output_cp
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
213 num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->tcs
.outputs_written
);
214 num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->tcs
.patch_outputs_written
);
216 input_vertex_size
= ctx
->tcs_num_inputs
* 16;
217 output_vertex_size
= num_tcs_outputs
* 16;
219 input_patch_size
= num_tcs_input_cp
* input_vertex_size
;
221 pervertex_output_patch_size
= num_tcs_output_cp
* output_vertex_size
;
222 output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
224 num_patches
= ctx
->tcs_num_patches
;
225 output_patch0_offset
= input_patch_size
* num_patches
;
227 lds_size
= output_patch0_offset
+ output_patch_size
* num_patches
;
231 /* Tessellation shaders pass outputs to the next shader using LDS.
233 * LS outputs = TCS inputs
234 * TCS outputs = TES inputs
237 * - TCS inputs for patch 0
238 * - TCS inputs for patch 1
239 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
241 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
242 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
243 * - TCS outputs for patch 1
244 * - Per-patch TCS outputs for patch 1
245 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
246 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
249 * All three shaders VS(LS), TCS, TES share the same LDS space.
252 get_tcs_in_patch_stride(struct radv_shader_context
*ctx
)
254 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
255 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
256 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
258 input_patch_size
/= 4;
259 return LLVMConstInt(ctx
->ac
.i32
, input_patch_size
, false);
263 get_tcs_out_patch_stride(struct radv_shader_context
*ctx
)
265 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->tcs
.outputs_written
);
266 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->tcs
.patch_outputs_written
);
267 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
268 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
269 uint32_t output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
270 output_patch_size
/= 4;
271 return LLVMConstInt(ctx
->ac
.i32
, output_patch_size
, false);
275 get_tcs_out_vertex_stride(struct radv_shader_context
*ctx
)
277 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->tcs
.outputs_written
);
278 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
279 output_vertex_size
/= 4;
280 return LLVMConstInt(ctx
->ac
.i32
, output_vertex_size
, false);
284 get_tcs_out_patch0_offset(struct radv_shader_context
*ctx
)
286 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
287 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
288 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
289 uint32_t output_patch0_offset
= input_patch_size
;
290 unsigned num_patches
= ctx
->tcs_num_patches
;
292 output_patch0_offset
*= num_patches
;
293 output_patch0_offset
/= 4;
294 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
298 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context
*ctx
)
300 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
301 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
302 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
303 uint32_t output_patch0_offset
= input_patch_size
;
305 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->tcs
.outputs_written
);
306 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
307 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
308 unsigned num_patches
= ctx
->tcs_num_patches
;
310 output_patch0_offset
*= num_patches
;
311 output_patch0_offset
+= pervertex_output_patch_size
;
312 output_patch0_offset
/= 4;
313 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
317 get_tcs_in_current_patch_offset(struct radv_shader_context
*ctx
)
319 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
320 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
322 return LLVMBuildMul(ctx
->ac
.builder
, patch_stride
, rel_patch_id
, "");
326 get_tcs_out_current_patch_offset(struct radv_shader_context
*ctx
)
328 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
329 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
330 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
332 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
,
337 get_tcs_out_current_patch_data_offset(struct radv_shader_context
*ctx
)
339 LLVMValueRef patch0_patch_data_offset
=
340 get_tcs_out_patch0_patch_data_offset(ctx
);
341 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
342 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
344 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
,
345 patch0_patch_data_offset
);
350 LLVMTypeRef types
[MAX_ARGS
];
351 LLVMValueRef
*assign
[MAX_ARGS
];
354 uint8_t num_sgprs_used
;
355 uint8_t num_vgprs_used
;
358 enum ac_arg_regfile
{
364 add_arg(struct arg_info
*info
, enum ac_arg_regfile regfile
, LLVMTypeRef type
,
365 LLVMValueRef
*param_ptr
)
367 assert(info
->count
< MAX_ARGS
);
369 info
->assign
[info
->count
] = param_ptr
;
370 info
->types
[info
->count
] = type
;
373 if (regfile
== ARG_SGPR
) {
374 info
->num_sgprs_used
+= ac_get_type_size(type
) / 4;
377 assert(regfile
== ARG_VGPR
);
378 info
->num_vgprs_used
+= ac_get_type_size(type
) / 4;
382 static void assign_arguments(LLVMValueRef main_function
,
383 struct arg_info
*info
)
386 for (i
= 0; i
< info
->count
; i
++) {
388 *info
->assign
[i
] = LLVMGetParam(main_function
, i
);
393 create_llvm_function(LLVMContextRef ctx
, LLVMModuleRef module
,
394 LLVMBuilderRef builder
, LLVMTypeRef
*return_types
,
395 unsigned num_return_elems
,
396 struct arg_info
*args
,
397 unsigned max_workgroup_size
,
398 const struct radv_nir_compiler_options
*options
)
400 LLVMTypeRef main_function_type
, ret_type
;
401 LLVMBasicBlockRef main_function_body
;
403 if (num_return_elems
)
404 ret_type
= LLVMStructTypeInContext(ctx
, return_types
,
405 num_return_elems
, true);
407 ret_type
= LLVMVoidTypeInContext(ctx
);
409 /* Setup the function */
411 LLVMFunctionType(ret_type
, args
->types
, args
->count
, 0);
412 LLVMValueRef main_function
=
413 LLVMAddFunction(module
, "main", main_function_type
);
415 LLVMAppendBasicBlockInContext(ctx
, main_function
, "main_body");
416 LLVMPositionBuilderAtEnd(builder
, main_function_body
);
418 LLVMSetFunctionCallConv(main_function
, RADEON_LLVM_AMDGPU_CS
);
419 for (unsigned i
= 0; i
< args
->sgpr_count
; ++i
) {
420 LLVMValueRef P
= LLVMGetParam(main_function
, i
);
422 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_INREG
);
424 if (LLVMGetTypeKind(LLVMTypeOf(P
)) == LLVMPointerTypeKind
) {
425 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_NOALIAS
);
426 ac_add_attr_dereferenceable(P
, UINT64_MAX
);
430 if (options
->address32_hi
) {
431 ac_llvm_add_target_dep_function_attr(main_function
,
432 "amdgpu-32bit-address-high-bits",
433 options
->address32_hi
);
436 ac_llvm_set_workgroup_size(main_function
, max_workgroup_size
);
438 if (options
->unsafe_math
) {
439 /* These were copied from some LLVM test. */
440 LLVMAddTargetDependentFunctionAttr(main_function
,
441 "less-precise-fpmad",
443 LLVMAddTargetDependentFunctionAttr(main_function
,
446 LLVMAddTargetDependentFunctionAttr(main_function
,
449 LLVMAddTargetDependentFunctionAttr(main_function
,
452 LLVMAddTargetDependentFunctionAttr(main_function
,
453 "no-signed-zeros-fp-math",
456 return main_function
;
461 set_loc(struct radv_userdata_info
*ud_info
, uint8_t *sgpr_idx
,
464 ud_info
->sgpr_idx
= *sgpr_idx
;
465 ud_info
->num_sgprs
= num_sgprs
;
466 *sgpr_idx
+= num_sgprs
;
470 set_loc_shader(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
,
473 struct radv_userdata_info
*ud_info
=
474 &ctx
->shader_info
->user_sgprs_locs
.shader_data
[idx
];
477 set_loc(ud_info
, sgpr_idx
, num_sgprs
);
481 set_loc_shader_ptr(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
)
483 bool use_32bit_pointers
= idx
!= AC_UD_SCRATCH_RING_OFFSETS
;
485 set_loc_shader(ctx
, idx
, sgpr_idx
, use_32bit_pointers
? 1 : 2);
489 set_loc_desc(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
)
491 struct radv_userdata_locations
*locs
=
492 &ctx
->shader_info
->user_sgprs_locs
;
493 struct radv_userdata_info
*ud_info
= &locs
->descriptor_sets
[idx
];
496 set_loc(ud_info
, sgpr_idx
, 1);
498 locs
->descriptor_sets_enabled
|= 1 << idx
;
501 struct user_sgpr_info
{
502 bool need_ring_offsets
;
503 bool indirect_all_descriptor_sets
;
504 uint8_t remaining_sgprs
;
507 static bool needs_view_index_sgpr(struct radv_shader_context
*ctx
,
508 gl_shader_stage stage
)
511 case MESA_SHADER_VERTEX
:
512 if (ctx
->shader_info
->needs_multiview_view_index
||
513 (!ctx
->options
->key
.vs_common_out
.as_es
&& !ctx
->options
->key
.vs_common_out
.as_ls
&& ctx
->options
->key
.has_multiview_view_index
))
516 case MESA_SHADER_TESS_EVAL
:
517 if (ctx
->shader_info
->needs_multiview_view_index
|| (!ctx
->options
->key
.vs_common_out
.as_es
&& ctx
->options
->key
.has_multiview_view_index
))
520 case MESA_SHADER_GEOMETRY
:
521 case MESA_SHADER_TESS_CTRL
:
522 if (ctx
->shader_info
->needs_multiview_view_index
)
532 count_vs_user_sgprs(struct radv_shader_context
*ctx
)
536 if (ctx
->shader_info
->vs
.has_vertex_buffers
)
538 count
+= ctx
->shader_info
->vs
.needs_draw_id
? 3 : 2;
543 static void allocate_inline_push_consts(struct radv_shader_context
*ctx
,
544 struct user_sgpr_info
*user_sgpr_info
)
546 uint8_t remaining_sgprs
= user_sgpr_info
->remaining_sgprs
;
548 /* Only supported if shaders use push constants. */
549 if (ctx
->shader_info
->min_push_constant_used
== UINT8_MAX
)
552 /* Only supported if shaders don't have indirect push constants. */
553 if (ctx
->shader_info
->has_indirect_push_constants
)
556 /* Only supported for 32-bit push constants. */
557 if (!ctx
->shader_info
->has_only_32bit_push_constants
)
560 uint8_t num_push_consts
=
561 (ctx
->shader_info
->max_push_constant_used
-
562 ctx
->shader_info
->min_push_constant_used
) / 4;
564 /* Check if the number of user SGPRs is large enough. */
565 if (num_push_consts
< remaining_sgprs
) {
566 ctx
->shader_info
->num_inline_push_consts
= num_push_consts
;
568 ctx
->shader_info
->num_inline_push_consts
= remaining_sgprs
;
571 /* Clamp to the maximum number of allowed inlined push constants. */
572 if (ctx
->shader_info
->num_inline_push_consts
> AC_MAX_INLINE_PUSH_CONSTS
)
573 ctx
->shader_info
->num_inline_push_consts
= AC_MAX_INLINE_PUSH_CONSTS
;
575 if (ctx
->shader_info
->num_inline_push_consts
== num_push_consts
&&
576 !ctx
->shader_info
->loads_dynamic_offsets
) {
577 /* Disable the default push constants path if all constants are
578 * inlined and if shaders don't use dynamic descriptors.
580 ctx
->shader_info
->loads_push_constants
= false;
583 ctx
->shader_info
->base_inline_push_consts
=
584 ctx
->shader_info
->min_push_constant_used
/ 4;
587 static void allocate_user_sgprs(struct radv_shader_context
*ctx
,
588 gl_shader_stage stage
,
589 bool has_previous_stage
,
590 gl_shader_stage previous_stage
,
591 bool needs_view_index
,
592 struct user_sgpr_info
*user_sgpr_info
)
594 uint8_t user_sgpr_count
= 0;
596 memset(user_sgpr_info
, 0, sizeof(struct user_sgpr_info
));
598 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
599 if (stage
== MESA_SHADER_GEOMETRY
||
600 stage
== MESA_SHADER_VERTEX
||
601 stage
== MESA_SHADER_TESS_CTRL
||
602 stage
== MESA_SHADER_TESS_EVAL
||
603 ctx
->is_gs_copy_shader
)
604 user_sgpr_info
->need_ring_offsets
= true;
606 if (stage
== MESA_SHADER_FRAGMENT
&&
607 ctx
->shader_info
->ps
.needs_sample_positions
)
608 user_sgpr_info
->need_ring_offsets
= true;
610 /* 2 user sgprs will nearly always be allocated for scratch/rings */
611 if (ctx
->options
->supports_spill
|| user_sgpr_info
->need_ring_offsets
) {
612 user_sgpr_count
+= 2;
616 case MESA_SHADER_COMPUTE
:
617 if (ctx
->shader_info
->cs
.uses_grid_size
)
618 user_sgpr_count
+= 3;
620 case MESA_SHADER_FRAGMENT
:
621 user_sgpr_count
+= ctx
->shader_info
->ps
.needs_sample_positions
;
623 case MESA_SHADER_VERTEX
:
624 if (!ctx
->is_gs_copy_shader
)
625 user_sgpr_count
+= count_vs_user_sgprs(ctx
);
627 case MESA_SHADER_TESS_CTRL
:
628 if (has_previous_stage
) {
629 if (previous_stage
== MESA_SHADER_VERTEX
)
630 user_sgpr_count
+= count_vs_user_sgprs(ctx
);
633 case MESA_SHADER_TESS_EVAL
:
635 case MESA_SHADER_GEOMETRY
:
636 if (has_previous_stage
) {
637 if (previous_stage
== MESA_SHADER_VERTEX
) {
638 user_sgpr_count
+= count_vs_user_sgprs(ctx
);
646 if (needs_view_index
)
649 if (ctx
->shader_info
->loads_push_constants
)
652 if (ctx
->streamout_buffers
)
655 uint32_t available_sgprs
= ctx
->options
->chip_class
>= GFX9
&& stage
!= MESA_SHADER_COMPUTE
? 32 : 16;
656 uint32_t remaining_sgprs
= available_sgprs
- user_sgpr_count
;
657 uint32_t num_desc_set
=
658 util_bitcount(ctx
->shader_info
->desc_set_used_mask
);
660 if (remaining_sgprs
< num_desc_set
) {
661 user_sgpr_info
->indirect_all_descriptor_sets
= true;
662 user_sgpr_info
->remaining_sgprs
= remaining_sgprs
- 1;
664 user_sgpr_info
->remaining_sgprs
= remaining_sgprs
- num_desc_set
;
667 allocate_inline_push_consts(ctx
, user_sgpr_info
);
671 declare_global_input_sgprs(struct radv_shader_context
*ctx
,
672 const struct user_sgpr_info
*user_sgpr_info
,
673 struct arg_info
*args
,
674 LLVMValueRef
*desc_sets
)
676 LLVMTypeRef type
= ac_array_in_const32_addr_space(ctx
->ac
.i8
);
678 /* 1 for each descriptor set */
679 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
680 uint32_t mask
= ctx
->shader_info
->desc_set_used_mask
;
683 int i
= u_bit_scan(&mask
);
685 add_arg(args
, ARG_SGPR
, type
, &ctx
->descriptor_sets
[i
]);
688 add_arg(args
, ARG_SGPR
, ac_array_in_const32_addr_space(type
),
692 if (ctx
->shader_info
->loads_push_constants
) {
693 /* 1 for push constants and dynamic descriptors */
694 add_arg(args
, ARG_SGPR
, type
, &ctx
->abi
.push_constants
);
697 for (unsigned i
= 0; i
< ctx
->shader_info
->num_inline_push_consts
; i
++) {
698 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
,
699 &ctx
->abi
.inline_push_consts
[i
]);
701 ctx
->abi
.num_inline_push_consts
= ctx
->shader_info
->num_inline_push_consts
;
702 ctx
->abi
.base_inline_push_consts
= ctx
->shader_info
->base_inline_push_consts
;
704 if (ctx
->shader_info
->so
.num_outputs
) {
705 add_arg(args
, ARG_SGPR
,
706 ac_array_in_const32_addr_space(ctx
->ac
.v4i32
),
707 &ctx
->streamout_buffers
);
712 declare_vs_specific_input_sgprs(struct radv_shader_context
*ctx
,
713 gl_shader_stage stage
,
714 bool has_previous_stage
,
715 gl_shader_stage previous_stage
,
716 struct arg_info
*args
)
718 if (!ctx
->is_gs_copy_shader
&&
719 (stage
== MESA_SHADER_VERTEX
||
720 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
721 if (ctx
->shader_info
->vs
.has_vertex_buffers
) {
722 add_arg(args
, ARG_SGPR
,
723 ac_array_in_const32_addr_space(ctx
->ac
.v4i32
),
724 &ctx
->vertex_buffers
);
726 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.base_vertex
);
727 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.start_instance
);
728 if (ctx
->shader_info
->vs
.needs_draw_id
) {
729 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.draw_id
);
735 declare_vs_input_vgprs(struct radv_shader_context
*ctx
, struct arg_info
*args
)
737 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.vertex_id
);
738 if (!ctx
->is_gs_copy_shader
) {
739 if (ctx
->options
->key
.vs_common_out
.as_ls
) {
740 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->rel_auto_id
);
741 if (ctx
->ac
.chip_class
>= GFX10
) {
742 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* user vgpr */
743 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
745 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
746 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* unused */
749 if (ctx
->ac
.chip_class
>= GFX10
) {
750 if (ctx
->options
->key
.vs_common_out
.as_ngg
) {
751 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* user vgpr */
752 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* user vgpr */
753 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
755 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* unused */
756 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->vs_prim_id
);
757 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
760 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
761 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->vs_prim_id
);
762 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* unused */
769 declare_streamout_sgprs(struct radv_shader_context
*ctx
, gl_shader_stage stage
,
770 struct arg_info
*args
)
774 /* Streamout SGPRs. */
775 if (ctx
->shader_info
->so
.num_outputs
) {
776 assert(stage
== MESA_SHADER_VERTEX
||
777 stage
== MESA_SHADER_TESS_EVAL
);
779 if (stage
!= MESA_SHADER_TESS_EVAL
) {
780 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->streamout_config
);
782 args
->assign
[args
->count
- 1] = &ctx
->streamout_config
;
783 args
->types
[args
->count
- 1] = ctx
->ac
.i32
;
786 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->streamout_write_idx
);
789 /* A streamout buffer offset is loaded if the stride is non-zero. */
790 for (i
= 0; i
< 4; i
++) {
791 if (!ctx
->shader_info
->so
.strides
[i
])
794 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->streamout_offset
[i
]);
799 declare_tes_input_vgprs(struct radv_shader_context
*ctx
, struct arg_info
*args
)
801 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_u
);
802 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_v
);
803 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->tes_rel_patch_id
);
804 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.tes_patch_id
);
808 set_global_input_locs(struct radv_shader_context
*ctx
,
809 const struct user_sgpr_info
*user_sgpr_info
,
810 LLVMValueRef desc_sets
, uint8_t *user_sgpr_idx
)
812 uint32_t mask
= ctx
->shader_info
->desc_set_used_mask
;
814 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
816 int i
= u_bit_scan(&mask
);
818 set_loc_desc(ctx
, i
, user_sgpr_idx
);
821 set_loc_shader_ptr(ctx
, AC_UD_INDIRECT_DESCRIPTOR_SETS
,
825 int i
= u_bit_scan(&mask
);
827 ctx
->descriptor_sets
[i
] =
828 ac_build_load_to_sgpr(&ctx
->ac
, desc_sets
,
829 LLVMConstInt(ctx
->ac
.i32
, i
, false));
833 ctx
->shader_info
->need_indirect_descriptor_sets
= true;
836 if (ctx
->shader_info
->loads_push_constants
) {
837 set_loc_shader_ptr(ctx
, AC_UD_PUSH_CONSTANTS
, user_sgpr_idx
);
840 if (ctx
->shader_info
->num_inline_push_consts
) {
841 set_loc_shader(ctx
, AC_UD_INLINE_PUSH_CONSTANTS
, user_sgpr_idx
,
842 ctx
->shader_info
->num_inline_push_consts
);
845 if (ctx
->streamout_buffers
) {
846 set_loc_shader_ptr(ctx
, AC_UD_STREAMOUT_BUFFERS
,
852 set_vs_specific_input_locs(struct radv_shader_context
*ctx
,
853 gl_shader_stage stage
, bool has_previous_stage
,
854 gl_shader_stage previous_stage
,
855 uint8_t *user_sgpr_idx
)
857 if (!ctx
->is_gs_copy_shader
&&
858 (stage
== MESA_SHADER_VERTEX
||
859 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
860 if (ctx
->shader_info
->vs
.has_vertex_buffers
) {
861 set_loc_shader_ptr(ctx
, AC_UD_VS_VERTEX_BUFFERS
,
866 if (ctx
->shader_info
->vs
.needs_draw_id
)
869 set_loc_shader(ctx
, AC_UD_VS_BASE_VERTEX_START_INSTANCE
,
870 user_sgpr_idx
, vs_num
);
874 static void set_llvm_calling_convention(LLVMValueRef func
,
875 gl_shader_stage stage
)
877 enum radeon_llvm_calling_convention calling_conv
;
880 case MESA_SHADER_VERTEX
:
881 case MESA_SHADER_TESS_EVAL
:
882 calling_conv
= RADEON_LLVM_AMDGPU_VS
;
884 case MESA_SHADER_GEOMETRY
:
885 calling_conv
= RADEON_LLVM_AMDGPU_GS
;
887 case MESA_SHADER_TESS_CTRL
:
888 calling_conv
= RADEON_LLVM_AMDGPU_HS
;
890 case MESA_SHADER_FRAGMENT
:
891 calling_conv
= RADEON_LLVM_AMDGPU_PS
;
893 case MESA_SHADER_COMPUTE
:
894 calling_conv
= RADEON_LLVM_AMDGPU_CS
;
897 unreachable("Unhandle shader type");
900 LLVMSetFunctionCallConv(func
, calling_conv
);
903 /* Returns whether the stage is a stage that can be directly before the GS */
904 static bool is_pre_gs_stage(gl_shader_stage stage
)
906 return stage
== MESA_SHADER_VERTEX
|| stage
== MESA_SHADER_TESS_EVAL
;
909 static void create_function(struct radv_shader_context
*ctx
,
910 gl_shader_stage stage
,
911 bool has_previous_stage
,
912 gl_shader_stage previous_stage
)
914 uint8_t user_sgpr_idx
;
915 struct user_sgpr_info user_sgpr_info
;
916 struct arg_info args
= {};
917 LLVMValueRef desc_sets
;
918 bool needs_view_index
= needs_view_index_sgpr(ctx
, stage
);
920 if (ctx
->ac
.chip_class
>= GFX10
) {
921 if (is_pre_gs_stage(stage
) && ctx
->options
->key
.vs_common_out
.as_ngg
) {
922 /* On GFX10, VS is merged into GS for NGG. */
923 previous_stage
= stage
;
924 stage
= MESA_SHADER_GEOMETRY
;
925 has_previous_stage
= true;
929 allocate_user_sgprs(ctx
, stage
, has_previous_stage
,
930 previous_stage
, needs_view_index
, &user_sgpr_info
);
932 if (user_sgpr_info
.need_ring_offsets
&& !ctx
->options
->supports_spill
) {
933 add_arg(&args
, ARG_SGPR
, ac_array_in_const_addr_space(ctx
->ac
.v4i32
),
938 case MESA_SHADER_COMPUTE
:
939 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
942 if (ctx
->shader_info
->cs
.uses_grid_size
) {
943 add_arg(&args
, ARG_SGPR
, ctx
->ac
.v3i32
,
944 &ctx
->abi
.num_work_groups
);
947 for (int i
= 0; i
< 3; i
++) {
948 ctx
->abi
.workgroup_ids
[i
] = NULL
;
949 if (ctx
->shader_info
->cs
.uses_block_id
[i
]) {
950 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
951 &ctx
->abi
.workgroup_ids
[i
]);
955 if (ctx
->shader_info
->cs
.uses_local_invocation_idx
)
956 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.tg_size
);
957 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
,
958 &ctx
->abi
.local_invocation_ids
);
960 case MESA_SHADER_VERTEX
:
961 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
964 declare_vs_specific_input_sgprs(ctx
, stage
, has_previous_stage
,
965 previous_stage
, &args
);
967 if (needs_view_index
)
968 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
969 &ctx
->abi
.view_index
);
970 if (ctx
->options
->key
.vs_common_out
.as_es
) {
971 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
973 } else if (ctx
->options
->key
.vs_common_out
.as_ls
) {
974 /* no extra parameters */
976 declare_streamout_sgprs(ctx
, stage
, &args
);
979 declare_vs_input_vgprs(ctx
, &args
);
981 case MESA_SHADER_TESS_CTRL
:
982 if (has_previous_stage
) {
983 // First 6 system regs
984 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
985 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
986 &ctx
->merged_wave_info
);
987 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
988 &ctx
->tess_factor_offset
);
990 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
991 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
992 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
994 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
997 declare_vs_specific_input_sgprs(ctx
, stage
,
999 previous_stage
, &args
);
1001 if (needs_view_index
)
1002 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1003 &ctx
->abi
.view_index
);
1005 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1006 &ctx
->abi
.tcs_patch_id
);
1007 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1008 &ctx
->abi
.tcs_rel_ids
);
1010 declare_vs_input_vgprs(ctx
, &args
);
1012 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1015 if (needs_view_index
)
1016 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1017 &ctx
->abi
.view_index
);
1019 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1020 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1021 &ctx
->tess_factor_offset
);
1022 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1023 &ctx
->abi
.tcs_patch_id
);
1024 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1025 &ctx
->abi
.tcs_rel_ids
);
1028 case MESA_SHADER_TESS_EVAL
:
1029 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1032 if (needs_view_index
)
1033 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1034 &ctx
->abi
.view_index
);
1036 if (ctx
->options
->key
.vs_common_out
.as_es
) {
1037 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1038 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
1039 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1040 &ctx
->es2gs_offset
);
1042 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
1043 declare_streamout_sgprs(ctx
, stage
, &args
);
1044 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1046 declare_tes_input_vgprs(ctx
, &args
);
1048 case MESA_SHADER_GEOMETRY
:
1049 if (has_previous_stage
) {
1050 // First 6 system regs
1051 if (ctx
->options
->key
.vs_common_out
.as_ngg
) {
1052 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1055 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1056 &ctx
->gs2vs_offset
);
1059 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1060 &ctx
->merged_wave_info
);
1061 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1063 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
1064 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1065 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1067 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1070 if (previous_stage
!= MESA_SHADER_TESS_EVAL
) {
1071 declare_vs_specific_input_sgprs(ctx
, stage
,
1077 if (needs_view_index
)
1078 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1079 &ctx
->abi
.view_index
);
1081 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1082 &ctx
->gs_vtx_offset
[0]);
1083 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1084 &ctx
->gs_vtx_offset
[2]);
1085 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1086 &ctx
->abi
.gs_prim_id
);
1087 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1088 &ctx
->abi
.gs_invocation_id
);
1089 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1090 &ctx
->gs_vtx_offset
[4]);
1092 if (previous_stage
== MESA_SHADER_VERTEX
) {
1093 declare_vs_input_vgprs(ctx
, &args
);
1095 declare_tes_input_vgprs(ctx
, &args
);
1098 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1101 if (needs_view_index
)
1102 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1103 &ctx
->abi
.view_index
);
1105 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs2vs_offset
);
1106 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs_wave_id
);
1107 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1108 &ctx
->gs_vtx_offset
[0]);
1109 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1110 &ctx
->gs_vtx_offset
[1]);
1111 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1112 &ctx
->abi
.gs_prim_id
);
1113 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1114 &ctx
->gs_vtx_offset
[2]);
1115 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1116 &ctx
->gs_vtx_offset
[3]);
1117 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1118 &ctx
->gs_vtx_offset
[4]);
1119 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1120 &ctx
->gs_vtx_offset
[5]);
1121 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1122 &ctx
->abi
.gs_invocation_id
);
1125 case MESA_SHADER_FRAGMENT
:
1126 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1129 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.prim_mask
);
1130 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->abi
.persp_sample
);
1131 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->abi
.persp_center
);
1132 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->abi
.persp_centroid
);
1133 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
, NULL
); /* persp pull model */
1134 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->abi
.linear_sample
);
1135 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->abi
.linear_center
);
1136 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->abi
.linear_centroid
);
1137 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, NULL
); /* line stipple tex */
1138 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[0]);
1139 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[1]);
1140 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[2]);
1141 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[3]);
1142 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.front_face
);
1143 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.ancillary
);
1144 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.sample_coverage
);
1145 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* fixed pt */
1148 unreachable("Shader stage not implemented");
1151 ctx
->main_function
= create_llvm_function(
1152 ctx
->context
, ctx
->ac
.module
, ctx
->ac
.builder
, NULL
, 0, &args
,
1153 ctx
->max_workgroup_size
, ctx
->options
);
1154 set_llvm_calling_convention(ctx
->main_function
, stage
);
1157 ctx
->shader_info
->num_input_vgprs
= 0;
1158 ctx
->shader_info
->num_input_sgprs
= ctx
->options
->supports_spill
? 2 : 0;
1160 ctx
->shader_info
->num_input_sgprs
+= args
.num_sgprs_used
;
1162 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
1163 ctx
->shader_info
->num_input_vgprs
= args
.num_vgprs_used
;
1165 assign_arguments(ctx
->main_function
, &args
);
1169 if (ctx
->options
->supports_spill
|| user_sgpr_info
.need_ring_offsets
) {
1170 set_loc_shader_ptr(ctx
, AC_UD_SCRATCH_RING_OFFSETS
,
1172 if (ctx
->options
->supports_spill
) {
1173 ctx
->ring_offsets
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.implicit.buffer.ptr",
1174 LLVMPointerType(ctx
->ac
.i8
, AC_ADDR_SPACE_CONST
),
1175 NULL
, 0, AC_FUNC_ATTR_READNONE
);
1176 ctx
->ring_offsets
= LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->ring_offsets
,
1177 ac_array_in_const_addr_space(ctx
->ac
.v4i32
), "");
1181 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1182 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1183 if (has_previous_stage
)
1186 set_global_input_locs(ctx
, &user_sgpr_info
, desc_sets
, &user_sgpr_idx
);
1189 case MESA_SHADER_COMPUTE
:
1190 if (ctx
->shader_info
->cs
.uses_grid_size
) {
1191 set_loc_shader(ctx
, AC_UD_CS_GRID_SIZE
,
1195 case MESA_SHADER_VERTEX
:
1196 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1197 previous_stage
, &user_sgpr_idx
);
1198 if (ctx
->abi
.view_index
)
1199 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1201 case MESA_SHADER_TESS_CTRL
:
1202 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1203 previous_stage
, &user_sgpr_idx
);
1204 if (ctx
->abi
.view_index
)
1205 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1207 case MESA_SHADER_TESS_EVAL
:
1208 if (ctx
->abi
.view_index
)
1209 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1211 case MESA_SHADER_GEOMETRY
:
1212 if (has_previous_stage
) {
1213 if (previous_stage
== MESA_SHADER_VERTEX
)
1214 set_vs_specific_input_locs(ctx
, stage
,
1219 if (ctx
->abi
.view_index
)
1220 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1222 case MESA_SHADER_FRAGMENT
:
1225 unreachable("Shader stage not implemented");
1228 if (stage
== MESA_SHADER_TESS_CTRL
||
1229 (stage
== MESA_SHADER_VERTEX
&& ctx
->options
->key
.vs_common_out
.as_ls
) ||
1230 /* GFX9 has the ESGS ring buffer in LDS. */
1231 (stage
== MESA_SHADER_GEOMETRY
&& has_previous_stage
)) {
1232 ac_declare_lds_as_pointer(&ctx
->ac
);
1235 ctx
->shader_info
->num_user_sgprs
= user_sgpr_idx
;
1240 radv_load_resource(struct ac_shader_abi
*abi
, LLVMValueRef index
,
1241 unsigned desc_set
, unsigned binding
)
1243 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1244 LLVMValueRef desc_ptr
= ctx
->descriptor_sets
[desc_set
];
1245 struct radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
1246 struct radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
1247 unsigned base_offset
= layout
->binding
[binding
].offset
;
1248 LLVMValueRef offset
, stride
;
1250 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
1251 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
1252 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+
1253 layout
->binding
[binding
].dynamic_offset_offset
;
1254 desc_ptr
= ctx
->abi
.push_constants
;
1255 base_offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
1256 stride
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
1258 stride
= LLVMConstInt(ctx
->ac
.i32
, layout
->binding
[binding
].size
, false);
1260 offset
= LLVMConstInt(ctx
->ac
.i32
, base_offset
, false);
1262 if (layout
->binding
[binding
].type
!= VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
1263 offset
= ac_build_imad(&ctx
->ac
, index
, stride
, offset
);
1266 desc_ptr
= LLVMBuildGEP(ctx
->ac
.builder
, desc_ptr
, &offset
, 1, "");
1267 desc_ptr
= ac_cast_ptr(&ctx
->ac
, desc_ptr
, ctx
->ac
.v4i32
);
1268 LLVMSetMetadata(desc_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1270 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
1271 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1272 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1273 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1274 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
1276 if (ctx
->ac
.chip_class
>= GFX10
) {
1277 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
1278 S_008F0C_OOB_SELECT(3) |
1279 S_008F0C_RESOURCE_LEVEL(1);
1281 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1282 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1285 LLVMValueRef desc_components
[4] = {
1286 LLVMBuildPtrToInt(ctx
->ac
.builder
, desc_ptr
, ctx
->ac
.intptr
, ""),
1287 LLVMConstInt(ctx
->ac
.i32
, S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
), false),
1288 /* High limit to support variable sizes. */
1289 LLVMConstInt(ctx
->ac
.i32
, 0xffffffff, false),
1290 LLVMConstInt(ctx
->ac
.i32
, desc_type
, false),
1293 return ac_build_gather_values(&ctx
->ac
, desc_components
, 4);
1300 /* The offchip buffer layout for TCS->TES is
1302 * - attribute 0 of patch 0 vertex 0
1303 * - attribute 0 of patch 0 vertex 1
1304 * - attribute 0 of patch 0 vertex 2
1306 * - attribute 0 of patch 1 vertex 0
1307 * - attribute 0 of patch 1 vertex 1
1309 * - attribute 1 of patch 0 vertex 0
1310 * - attribute 1 of patch 0 vertex 1
1312 * - per patch attribute 0 of patch 0
1313 * - per patch attribute 0 of patch 1
1316 * Note that every attribute has 4 components.
1318 static LLVMValueRef
get_non_vertex_index_offset(struct radv_shader_context
*ctx
)
1320 uint32_t num_patches
= ctx
->tcs_num_patches
;
1321 uint32_t num_tcs_outputs
;
1322 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
1323 num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->tcs
.outputs_written
);
1325 num_tcs_outputs
= ctx
->options
->key
.tes
.tcs_num_outputs
;
1327 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
1328 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
1330 return LLVMConstInt(ctx
->ac
.i32
, pervertex_output_patch_size
* num_patches
, false);
1333 static LLVMValueRef
calc_param_stride(struct radv_shader_context
*ctx
,
1334 LLVMValueRef vertex_index
)
1336 LLVMValueRef param_stride
;
1338 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.tess
.tcs_vertices_out
* ctx
->tcs_num_patches
, false);
1340 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_num_patches
, false);
1341 return param_stride
;
1344 static LLVMValueRef
get_tcs_tes_buffer_address(struct radv_shader_context
*ctx
,
1345 LLVMValueRef vertex_index
,
1346 LLVMValueRef param_index
)
1348 LLVMValueRef base_addr
;
1349 LLVMValueRef param_stride
, constant16
;
1350 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
1351 LLVMValueRef vertices_per_patch
= LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.tess
.tcs_vertices_out
, false);
1352 constant16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
1353 param_stride
= calc_param_stride(ctx
, vertex_index
);
1355 base_addr
= ac_build_imad(&ctx
->ac
, rel_patch_id
,
1356 vertices_per_patch
, vertex_index
);
1358 base_addr
= rel_patch_id
;
1361 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
1362 LLVMBuildMul(ctx
->ac
.builder
, param_index
,
1363 param_stride
, ""), "");
1365 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, base_addr
, constant16
, "");
1367 if (!vertex_index
) {
1368 LLVMValueRef patch_data_offset
= get_non_vertex_index_offset(ctx
);
1370 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
1371 patch_data_offset
, "");
1376 static LLVMValueRef
get_tcs_tes_buffer_address_params(struct radv_shader_context
*ctx
,
1378 unsigned const_index
,
1380 LLVMValueRef vertex_index
,
1381 LLVMValueRef indir_index
)
1383 LLVMValueRef param_index
;
1386 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, param
, false),
1389 if (const_index
&& !is_compact
)
1390 param
+= const_index
;
1391 param_index
= LLVMConstInt(ctx
->ac
.i32
, param
, false);
1393 return get_tcs_tes_buffer_address(ctx
, vertex_index
, param_index
);
1397 get_dw_address(struct radv_shader_context
*ctx
,
1398 LLVMValueRef dw_addr
,
1400 unsigned const_index
,
1401 bool compact_const_index
,
1402 LLVMValueRef vertex_index
,
1403 LLVMValueRef stride
,
1404 LLVMValueRef indir_index
)
1409 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1410 LLVMBuildMul(ctx
->ac
.builder
,
1416 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1417 LLVMBuildMul(ctx
->ac
.builder
, indir_index
,
1418 LLVMConstInt(ctx
->ac
.i32
, 4, false), ""), "");
1419 else if (const_index
&& !compact_const_index
)
1420 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1421 LLVMConstInt(ctx
->ac
.i32
, const_index
* 4, false), "");
1423 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1424 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false), "");
1426 if (const_index
&& compact_const_index
)
1427 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1428 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
1433 load_tcs_varyings(struct ac_shader_abi
*abi
,
1435 LLVMValueRef vertex_index
,
1436 LLVMValueRef indir_index
,
1437 unsigned const_index
,
1439 unsigned driver_location
,
1441 unsigned num_components
,
1446 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1447 LLVMValueRef dw_addr
, stride
;
1448 LLVMValueRef value
[4], result
;
1449 unsigned param
= shader_io_get_unique_index(location
);
1452 uint32_t input_vertex_size
= (ctx
->tcs_num_inputs
* 16) / 4;
1453 stride
= LLVMConstInt(ctx
->ac
.i32
, input_vertex_size
, false);
1454 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
1457 stride
= get_tcs_out_vertex_stride(ctx
);
1458 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1460 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1465 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
1468 for (unsigned i
= 0; i
< num_components
+ component
; i
++) {
1469 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
1470 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1473 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1478 store_tcs_output(struct ac_shader_abi
*abi
,
1479 const nir_variable
*var
,
1480 LLVMValueRef vertex_index
,
1481 LLVMValueRef param_index
,
1482 unsigned const_index
,
1486 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1487 const unsigned location
= var
->data
.location
;
1488 unsigned component
= var
->data
.location_frac
;
1489 const bool is_patch
= var
->data
.patch
;
1490 const bool is_compact
= var
->data
.compact
;
1491 LLVMValueRef dw_addr
;
1492 LLVMValueRef stride
= NULL
;
1493 LLVMValueRef buf_addr
= NULL
;
1495 bool store_lds
= true;
1498 if (!(ctx
->shader
->info
.patch_outputs_read
& (1U << (location
- VARYING_SLOT_PATCH0
))))
1501 if (!(ctx
->shader
->info
.outputs_read
& (1ULL << location
)))
1505 param
= shader_io_get_unique_index(location
);
1506 if ((location
== VARYING_SLOT_CLIP_DIST0
|| location
== VARYING_SLOT_CLIP_DIST1
) && is_compact
) {
1507 const_index
+= component
;
1510 if (const_index
>= 4) {
1517 stride
= get_tcs_out_vertex_stride(ctx
);
1518 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1520 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1523 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
1525 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
, is_compact
,
1526 vertex_index
, param_index
);
1528 bool is_tess_factor
= false;
1529 if (location
== VARYING_SLOT_TESS_LEVEL_INNER
||
1530 location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
1531 is_tess_factor
= true;
1533 unsigned base
= is_compact
? const_index
: 0;
1534 for (unsigned chan
= 0; chan
< 8; chan
++) {
1535 if (!(writemask
& (1 << chan
)))
1537 LLVMValueRef value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- component
);
1538 value
= ac_to_integer(&ctx
->ac
, value
);
1539 value
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
1541 if (store_lds
|| is_tess_factor
) {
1542 LLVMValueRef dw_addr_chan
=
1543 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1544 LLVMConstInt(ctx
->ac
.i32
, chan
, false), "");
1545 ac_lds_store(&ctx
->ac
, dw_addr_chan
, value
);
1548 if (!is_tess_factor
&& writemask
!= 0xF)
1549 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, value
, 1,
1550 buf_addr
, ctx
->oc_lds
,
1551 4 * (base
+ chan
), ac_glc
, false);
1554 if (writemask
== 0xF) {
1555 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, src
, 4,
1556 buf_addr
, ctx
->oc_lds
,
1557 (base
* 4), ac_glc
, false);
1562 load_tes_input(struct ac_shader_abi
*abi
,
1564 LLVMValueRef vertex_index
,
1565 LLVMValueRef param_index
,
1566 unsigned const_index
,
1568 unsigned driver_location
,
1570 unsigned num_components
,
1575 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1576 LLVMValueRef buf_addr
;
1577 LLVMValueRef result
;
1578 unsigned param
= shader_io_get_unique_index(location
);
1580 if ((location
== VARYING_SLOT_CLIP_DIST0
|| location
== VARYING_SLOT_CLIP_DIST1
) && is_compact
) {
1581 const_index
+= component
;
1583 if (const_index
>= 4) {
1589 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
,
1590 is_compact
, vertex_index
, param_index
);
1592 LLVMValueRef comp_offset
= LLVMConstInt(ctx
->ac
.i32
, component
* 4, false);
1593 buf_addr
= LLVMBuildAdd(ctx
->ac
.builder
, buf_addr
, comp_offset
, "");
1595 result
= ac_build_buffer_load(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, num_components
, NULL
,
1596 buf_addr
, ctx
->oc_lds
, is_compact
? (4 * const_index
) : 0, ac_glc
, true, false);
1597 result
= ac_trim_vector(&ctx
->ac
, result
, num_components
);
1602 load_gs_input(struct ac_shader_abi
*abi
,
1604 unsigned driver_location
,
1606 unsigned num_components
,
1607 unsigned vertex_index
,
1608 unsigned const_index
,
1611 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1612 LLVMValueRef vtx_offset
;
1613 unsigned param
, vtx_offset_param
;
1614 LLVMValueRef value
[4], result
;
1616 vtx_offset_param
= vertex_index
;
1617 assert(vtx_offset_param
< 6);
1618 vtx_offset
= LLVMBuildMul(ctx
->ac
.builder
, ctx
->gs_vtx_offset
[vtx_offset_param
],
1619 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
1621 param
= shader_io_get_unique_index(location
);
1623 for (unsigned i
= component
; i
< num_components
+ component
; i
++) {
1624 if (ctx
->ac
.chip_class
>= GFX9
) {
1625 LLVMValueRef dw_addr
= ctx
->gs_vtx_offset
[vtx_offset_param
];
1626 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1627 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
, 0), "");
1628 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
1630 LLVMValueRef soffset
=
1631 LLVMConstInt(ctx
->ac
.i32
,
1632 (param
* 4 + i
+ const_index
) * 256,
1635 value
[i
] = ac_build_buffer_load(&ctx
->ac
,
1638 vtx_offset
, soffset
,
1639 0, ac_glc
, true, false);
1642 if (ac_get_type_size(type
) == 2) {
1643 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
], ctx
->ac
.i32
, "");
1644 value
[i
] = LLVMBuildTrunc(ctx
->ac
.builder
, value
[i
], ctx
->ac
.i16
, "");
1646 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
], type
, "");
1648 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1649 result
= ac_to_integer(&ctx
->ac
, result
);
1654 static void radv_emit_kill(struct ac_shader_abi
*abi
, LLVMValueRef visible
)
1656 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1657 ac_build_kill_if_false(&ctx
->ac
, visible
);
1661 radv_get_sample_pos_offset(uint32_t num_samples
)
1663 uint32_t sample_pos_offset
= 0;
1665 switch (num_samples
) {
1667 sample_pos_offset
= 1;
1670 sample_pos_offset
= 3;
1673 sample_pos_offset
= 7;
1678 return sample_pos_offset
;
1681 static LLVMValueRef
load_sample_position(struct ac_shader_abi
*abi
,
1682 LLVMValueRef sample_id
)
1684 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1686 LLVMValueRef result
;
1687 LLVMValueRef index
= LLVMConstInt(ctx
->ac
.i32
, RING_PS_SAMPLE_POSITIONS
, false);
1688 LLVMValueRef ptr
= LLVMBuildGEP(ctx
->ac
.builder
, ctx
->ring_offsets
, &index
, 1, "");
1690 ptr
= LLVMBuildBitCast(ctx
->ac
.builder
, ptr
,
1691 ac_array_in_const_addr_space(ctx
->ac
.v2f32
), "");
1693 uint32_t sample_pos_offset
=
1694 radv_get_sample_pos_offset(ctx
->options
->key
.fs
.num_samples
);
1697 LLVMBuildAdd(ctx
->ac
.builder
, sample_id
,
1698 LLVMConstInt(ctx
->ac
.i32
, sample_pos_offset
, false), "");
1699 result
= ac_build_load_invariant(&ctx
->ac
, ptr
, sample_id
);
1705 static LLVMValueRef
load_sample_mask_in(struct ac_shader_abi
*abi
)
1707 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1708 uint8_t log2_ps_iter_samples
;
1710 if (ctx
->shader_info
->ps
.force_persample
) {
1711 log2_ps_iter_samples
=
1712 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
1714 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
1717 /* The bit pattern matches that used by fixed function fragment
1719 static const uint16_t ps_iter_masks
[] = {
1720 0xffff, /* not used */
1726 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
1728 uint32_t ps_iter_mask
= ps_iter_masks
[log2_ps_iter_samples
];
1730 LLVMValueRef result
, sample_id
;
1731 sample_id
= ac_unpack_param(&ctx
->ac
, abi
->ancillary
, 8, 4);
1732 sample_id
= LLVMBuildShl(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, ps_iter_mask
, false), sample_id
, "");
1733 result
= LLVMBuildAnd(ctx
->ac
.builder
, sample_id
, abi
->sample_coverage
, "");
1738 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context
*ctx
,
1740 LLVMValueRef
*addrs
);
1743 visit_emit_vertex(struct ac_shader_abi
*abi
, unsigned stream
, LLVMValueRef
*addrs
)
1745 LLVMValueRef gs_next_vertex
;
1746 LLVMValueRef can_emit
;
1747 unsigned offset
= 0;
1748 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1750 if (ctx
->options
->key
.vs_common_out
.as_ngg
) {
1751 gfx10_ngg_gs_emit_vertex(ctx
, stream
, addrs
);
1755 /* Write vertex attribute values to GSVS ring */
1756 gs_next_vertex
= LLVMBuildLoad(ctx
->ac
.builder
,
1757 ctx
->gs_next_vertex
[stream
],
1760 /* If this thread has already emitted the declared maximum number of
1761 * vertices, kill it: excessive vertex emissions are not supposed to
1762 * have any effect, and GS threads have no externally observable
1763 * effects other than emitting vertices.
1765 can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
, gs_next_vertex
,
1766 LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.gs
.vertices_out
, false), "");
1767 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
1769 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
1770 unsigned output_usage_mask
=
1771 ctx
->shader_info
->gs
.output_usage_mask
[i
];
1772 uint8_t output_stream
=
1773 ctx
->shader_info
->gs
.output_streams
[i
];
1774 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
1775 int length
= util_last_bit(output_usage_mask
);
1777 if (!(ctx
->output_mask
& (1ull << i
)) ||
1778 output_stream
!= stream
)
1781 for (unsigned j
= 0; j
< length
; j
++) {
1782 if (!(output_usage_mask
& (1 << j
)))
1785 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
,
1787 LLVMValueRef voffset
=
1788 LLVMConstInt(ctx
->ac
.i32
, offset
*
1789 ctx
->shader
->info
.gs
.vertices_out
, false);
1793 voffset
= LLVMBuildAdd(ctx
->ac
.builder
, voffset
, gs_next_vertex
, "");
1794 voffset
= LLVMBuildMul(ctx
->ac
.builder
, voffset
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
1796 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
1797 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
1799 ac_build_buffer_store_dword(&ctx
->ac
,
1800 ctx
->gsvs_ring
[stream
],
1802 voffset
, ctx
->gs2vs_offset
, 0,
1803 ac_glc
| ac_slc
, true);
1807 gs_next_vertex
= LLVMBuildAdd(ctx
->ac
.builder
, gs_next_vertex
,
1809 LLVMBuildStore(ctx
->ac
.builder
, gs_next_vertex
, ctx
->gs_next_vertex
[stream
]);
1811 ac_build_sendmsg(&ctx
->ac
,
1812 AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (stream
<< 8),
1817 visit_end_primitive(struct ac_shader_abi
*abi
, unsigned stream
)
1819 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1821 if (ctx
->options
->key
.vs_common_out
.as_ngg
) {
1822 LLVMBuildStore(ctx
->ac
.builder
, ctx
->ac
.i32_0
, ctx
->gs_curprim_verts
[stream
]);
1826 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (stream
<< 8), ctx
->gs_wave_id
);
1830 load_tess_coord(struct ac_shader_abi
*abi
)
1832 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1834 LLVMValueRef coord
[4] = {
1841 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
)
1842 coord
[2] = LLVMBuildFSub(ctx
->ac
.builder
, ctx
->ac
.f32_1
,
1843 LLVMBuildFAdd(ctx
->ac
.builder
, coord
[0], coord
[1], ""), "");
1845 return ac_build_gather_values(&ctx
->ac
, coord
, 3);
1849 load_patch_vertices_in(struct ac_shader_abi
*abi
)
1851 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1852 return LLVMConstInt(ctx
->ac
.i32
, ctx
->options
->key
.tcs
.input_vertices
, false);
1856 static LLVMValueRef
radv_load_base_vertex(struct ac_shader_abi
*abi
)
1858 return abi
->base_vertex
;
1861 static LLVMValueRef
radv_load_ssbo(struct ac_shader_abi
*abi
,
1862 LLVMValueRef buffer_ptr
, bool write
)
1864 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1865 LLVMValueRef result
;
1867 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1869 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
1870 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
1875 static LLVMValueRef
radv_load_ubo(struct ac_shader_abi
*abi
, LLVMValueRef buffer_ptr
)
1877 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1878 LLVMValueRef result
;
1880 if (LLVMGetTypeKind(LLVMTypeOf(buffer_ptr
)) != LLVMPointerTypeKind
) {
1881 /* Do not load the descriptor for inlined uniform blocks. */
1885 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1887 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
1888 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
1893 static LLVMValueRef
radv_get_sampler_desc(struct ac_shader_abi
*abi
,
1894 unsigned descriptor_set
,
1895 unsigned base_index
,
1896 unsigned constant_index
,
1898 enum ac_descriptor_type desc_type
,
1899 bool image
, bool write
,
1902 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1903 LLVMValueRef list
= ctx
->descriptor_sets
[descriptor_set
];
1904 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
1905 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
1906 unsigned offset
= binding
->offset
;
1907 unsigned stride
= binding
->size
;
1909 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1912 assert(base_index
< layout
->binding_count
);
1914 switch (desc_type
) {
1916 type
= ctx
->ac
.v8i32
;
1920 type
= ctx
->ac
.v8i32
;
1924 case AC_DESC_SAMPLER
:
1925 type
= ctx
->ac
.v4i32
;
1926 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
) {
1927 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
1932 case AC_DESC_BUFFER
:
1933 type
= ctx
->ac
.v4i32
;
1936 case AC_DESC_PLANE_0
:
1937 case AC_DESC_PLANE_1
:
1938 case AC_DESC_PLANE_2
:
1939 type
= ctx
->ac
.v8i32
;
1941 offset
+= 32 * (desc_type
- AC_DESC_PLANE_0
);
1944 unreachable("invalid desc_type\n");
1947 offset
+= constant_index
* stride
;
1949 if (desc_type
== AC_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
1950 (!index
|| binding
->immutable_samplers_equal
)) {
1951 if (binding
->immutable_samplers_equal
)
1954 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
1956 LLVMValueRef constants
[] = {
1957 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 0], 0),
1958 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 1], 0),
1959 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 2], 0),
1960 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 3], 0),
1962 return ac_build_gather_values(&ctx
->ac
, constants
, 4);
1965 assert(stride
% type_size
== 0);
1967 LLVMValueRef adjusted_index
= index
;
1968 if (!adjusted_index
)
1969 adjusted_index
= ctx
->ac
.i32_0
;
1971 adjusted_index
= LLVMBuildMul(builder
, adjusted_index
, LLVMConstInt(ctx
->ac
.i32
, stride
/ type_size
, 0), "");
1973 LLVMValueRef val_offset
= LLVMConstInt(ctx
->ac
.i32
, offset
, 0);
1974 list
= LLVMBuildGEP(builder
, list
, &val_offset
, 1, "");
1975 list
= LLVMBuildPointerCast(builder
, list
,
1976 ac_array_in_const32_addr_space(type
), "");
1978 LLVMValueRef descriptor
= ac_build_load_to_sgpr(&ctx
->ac
, list
, adjusted_index
);
1980 /* 3 plane formats always have same size and format for plane 1 & 2, so
1981 * use the tail from plane 1 so that we can store only the first 16 bytes
1982 * of the last plane. */
1983 if (desc_type
== AC_DESC_PLANE_2
) {
1984 LLVMValueRef descriptor2
= radv_get_sampler_desc(abi
, descriptor_set
, base_index
, constant_index
, index
, AC_DESC_PLANE_1
,image
, write
, bindless
);
1986 LLVMValueRef components
[8];
1987 for (unsigned i
= 0; i
< 4; ++i
)
1988 components
[i
] = ac_llvm_extract_elem(&ctx
->ac
, descriptor
, i
);
1990 for (unsigned i
= 4; i
< 8; ++i
)
1991 components
[i
] = ac_llvm_extract_elem(&ctx
->ac
, descriptor2
, i
);
1992 descriptor
= ac_build_gather_values(&ctx
->ac
, components
, 8);
1998 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
1999 * so we may need to fix it up. */
2001 adjust_vertex_fetch_alpha(struct radv_shader_context
*ctx
,
2002 unsigned adjustment
,
2005 if (adjustment
== RADV_ALPHA_ADJUST_NONE
)
2008 LLVMValueRef c30
= LLVMConstInt(ctx
->ac
.i32
, 30, 0);
2010 alpha
= LLVMBuildBitCast(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
2012 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
2013 alpha
= LLVMBuildFPToUI(ctx
->ac
.builder
, alpha
, ctx
->ac
.i32
, "");
2015 alpha
= ac_to_integer(&ctx
->ac
, alpha
);
2017 /* For the integer-like cases, do a natural sign extension.
2019 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
2020 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
2023 alpha
= LLVMBuildShl(ctx
->ac
.builder
, alpha
,
2024 adjustment
== RADV_ALPHA_ADJUST_SNORM
?
2025 LLVMConstInt(ctx
->ac
.i32
, 7, 0) : c30
, "");
2026 alpha
= LLVMBuildAShr(ctx
->ac
.builder
, alpha
, c30
, "");
2028 /* Convert back to the right type. */
2029 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
2031 LLVMValueRef neg_one
= LLVMConstReal(ctx
->ac
.f32
, -1.0);
2032 alpha
= LLVMBuildSIToFP(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
2033 clamp
= LLVMBuildFCmp(ctx
->ac
.builder
, LLVMRealULT
, alpha
, neg_one
, "");
2034 alpha
= LLVMBuildSelect(ctx
->ac
.builder
, clamp
, neg_one
, alpha
, "");
2035 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
2036 alpha
= LLVMBuildSIToFP(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
2039 return LLVMBuildBitCast(ctx
->ac
.builder
, alpha
, ctx
->ac
.i32
, "");
2043 get_num_channels_from_data_format(unsigned data_format
)
2045 switch (data_format
) {
2046 case V_008F0C_BUF_DATA_FORMAT_8
:
2047 case V_008F0C_BUF_DATA_FORMAT_16
:
2048 case V_008F0C_BUF_DATA_FORMAT_32
:
2050 case V_008F0C_BUF_DATA_FORMAT_8_8
:
2051 case V_008F0C_BUF_DATA_FORMAT_16_16
:
2052 case V_008F0C_BUF_DATA_FORMAT_32_32
:
2054 case V_008F0C_BUF_DATA_FORMAT_10_11_11
:
2055 case V_008F0C_BUF_DATA_FORMAT_11_11_10
:
2056 case V_008F0C_BUF_DATA_FORMAT_32_32_32
:
2058 case V_008F0C_BUF_DATA_FORMAT_8_8_8_8
:
2059 case V_008F0C_BUF_DATA_FORMAT_10_10_10_2
:
2060 case V_008F0C_BUF_DATA_FORMAT_2_10_10_10
:
2061 case V_008F0C_BUF_DATA_FORMAT_16_16_16_16
:
2062 case V_008F0C_BUF_DATA_FORMAT_32_32_32_32
:
2072 radv_fixup_vertex_input_fetches(struct radv_shader_context
*ctx
,
2074 unsigned num_channels
,
2077 LLVMValueRef zero
= is_float
? ctx
->ac
.f32_0
: ctx
->ac
.i32_0
;
2078 LLVMValueRef one
= is_float
? ctx
->ac
.f32_1
: ctx
->ac
.i32_1
;
2079 LLVMValueRef chan
[4];
2081 if (LLVMGetTypeKind(LLVMTypeOf(value
)) == LLVMVectorTypeKind
) {
2082 unsigned vec_size
= LLVMGetVectorSize(LLVMTypeOf(value
));
2084 if (num_channels
== 4 && num_channels
== vec_size
)
2087 num_channels
= MIN2(num_channels
, vec_size
);
2089 for (unsigned i
= 0; i
< num_channels
; i
++)
2090 chan
[i
] = ac_llvm_extract_elem(&ctx
->ac
, value
, i
);
2093 assert(num_channels
== 1);
2098 for (unsigned i
= num_channels
; i
< 4; i
++) {
2099 chan
[i
] = i
== 3 ? one
: zero
;
2100 chan
[i
] = ac_to_integer(&ctx
->ac
, chan
[i
]);
2103 return ac_build_gather_values(&ctx
->ac
, chan
, 4);
2107 handle_vs_input_decl(struct radv_shader_context
*ctx
,
2108 struct nir_variable
*variable
)
2110 LLVMValueRef t_list_ptr
= ctx
->vertex_buffers
;
2111 LLVMValueRef t_offset
;
2112 LLVMValueRef t_list
;
2114 LLVMValueRef buffer_index
;
2115 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, true);
2116 uint8_t input_usage_mask
=
2117 ctx
->shader_info
->vs
.input_usage_mask
[variable
->data
.location
];
2118 unsigned num_input_channels
= util_last_bit(input_usage_mask
);
2120 variable
->data
.driver_location
= variable
->data
.location
* 4;
2122 enum glsl_base_type type
= glsl_get_base_type(variable
->type
);
2123 for (unsigned i
= 0; i
< attrib_count
; ++i
) {
2124 LLVMValueRef output
[4];
2125 unsigned attrib_index
= variable
->data
.location
+ i
- VERT_ATTRIB_GENERIC0
;
2126 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[attrib_index
];
2127 unsigned data_format
= attrib_format
& 0x0f;
2128 unsigned num_format
= (attrib_format
>> 4) & 0x07;
2129 bool is_float
= num_format
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
2130 num_format
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
2132 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << attrib_index
)) {
2133 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[attrib_index
];
2136 buffer_index
= ctx
->abi
.instance_id
;
2139 buffer_index
= LLVMBuildUDiv(ctx
->ac
.builder
, buffer_index
,
2140 LLVMConstInt(ctx
->ac
.i32
, divisor
, 0), "");
2143 buffer_index
= ctx
->ac
.i32_0
;
2146 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
, ctx
->abi
.start_instance
, buffer_index
, "");
2148 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
, ctx
->abi
.vertex_id
,
2149 ctx
->abi
.base_vertex
, "");
2151 /* Adjust the number of channels to load based on the vertex
2154 unsigned num_format_channels
= get_num_channels_from_data_format(data_format
);
2155 unsigned num_channels
= MIN2(num_input_channels
, num_format_channels
);
2156 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[attrib_index
];
2157 unsigned attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[attrib_index
];
2158 unsigned attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[attrib_index
];
2160 if (ctx
->options
->key
.vs
.post_shuffle
& (1 << attrib_index
)) {
2161 /* Always load, at least, 3 channels for formats that
2162 * need to be shuffled because X<->Z.
2164 num_channels
= MAX2(num_channels
, 3);
2167 if (attrib_stride
!= 0 && attrib_offset
> attrib_stride
) {
2168 LLVMValueRef buffer_offset
=
2169 LLVMConstInt(ctx
->ac
.i32
,
2170 attrib_offset
/ attrib_stride
, false);
2172 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
,
2176 attrib_offset
= attrib_offset
% attrib_stride
;
2179 t_offset
= LLVMConstInt(ctx
->ac
.i32
, attrib_binding
, false);
2180 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
2182 input
= ac_build_struct_tbuffer_load(&ctx
->ac
, t_list
,
2184 LLVMConstInt(ctx
->ac
.i32
, attrib_offset
, false),
2185 ctx
->ac
.i32_0
, ctx
->ac
.i32_0
,
2187 data_format
, num_format
, 0, true);
2189 if (ctx
->options
->key
.vs
.post_shuffle
& (1 << attrib_index
)) {
2191 c
[0] = ac_llvm_extract_elem(&ctx
->ac
, input
, 2);
2192 c
[1] = ac_llvm_extract_elem(&ctx
->ac
, input
, 1);
2193 c
[2] = ac_llvm_extract_elem(&ctx
->ac
, input
, 0);
2194 c
[3] = ac_llvm_extract_elem(&ctx
->ac
, input
, 3);
2196 input
= ac_build_gather_values(&ctx
->ac
, c
, 4);
2199 input
= radv_fixup_vertex_input_fetches(ctx
, input
, num_channels
,
2202 for (unsigned chan
= 0; chan
< 4; chan
++) {
2203 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
2204 output
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
, input
, llvm_chan
, "");
2205 if (type
== GLSL_TYPE_FLOAT16
) {
2206 output
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.f32
, "");
2207 output
[chan
] = LLVMBuildFPTrunc(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.f16
, "");
2211 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (attrib_index
* 2)) & 3;
2212 output
[3] = adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, output
[3]);
2214 for (unsigned chan
= 0; chan
< 4; chan
++) {
2215 output
[chan
] = ac_to_integer(&ctx
->ac
, output
[chan
]);
2216 if (type
== GLSL_TYPE_UINT16
|| type
== GLSL_TYPE_INT16
)
2217 output
[chan
] = LLVMBuildTrunc(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.i16
, "");
2219 ctx
->inputs
[ac_llvm_reg_index_soa(variable
->data
.location
+ i
, chan
)] = output
[chan
];
2225 handle_vs_inputs(struct radv_shader_context
*ctx
,
2226 struct nir_shader
*nir
) {
2227 nir_foreach_variable(variable
, &nir
->inputs
)
2228 handle_vs_input_decl(ctx
, variable
);
2232 prepare_interp_optimize(struct radv_shader_context
*ctx
,
2233 struct nir_shader
*nir
)
2235 bool uses_center
= false;
2236 bool uses_centroid
= false;
2237 nir_foreach_variable(variable
, &nir
->inputs
) {
2238 if (glsl_get_base_type(glsl_without_array(variable
->type
)) != GLSL_TYPE_FLOAT
||
2239 variable
->data
.sample
)
2242 if (variable
->data
.centroid
)
2243 uses_centroid
= true;
2248 if (uses_center
&& uses_centroid
) {
2249 LLVMValueRef sel
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntSLT
, ctx
->abi
.prim_mask
, ctx
->ac
.i32_0
, "");
2250 ctx
->abi
.persp_centroid
= LLVMBuildSelect(ctx
->ac
.builder
, sel
, ctx
->abi
.persp_center
, ctx
->abi
.persp_centroid
, "");
2251 ctx
->abi
.linear_centroid
= LLVMBuildSelect(ctx
->ac
.builder
, sel
, ctx
->abi
.linear_center
, ctx
->abi
.linear_centroid
, "");
2256 scan_shader_output_decl(struct radv_shader_context
*ctx
,
2257 struct nir_variable
*variable
,
2258 struct nir_shader
*shader
,
2259 gl_shader_stage stage
)
2261 int idx
= variable
->data
.location
+ variable
->data
.index
;
2262 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
2263 uint64_t mask_attribs
;
2265 variable
->data
.driver_location
= idx
* 4;
2267 /* tess ctrl has it's own load/store paths for outputs */
2268 if (stage
== MESA_SHADER_TESS_CTRL
)
2271 if (variable
->data
.compact
) {
2272 unsigned component_count
= variable
->data
.location_frac
+
2273 glsl_get_length(variable
->type
);
2274 attrib_count
= (component_count
+ 3) / 4;
2277 mask_attribs
= ((1ull << attrib_count
) - 1) << idx
;
2279 ctx
->output_mask
|= mask_attribs
;
2283 /* Initialize arguments for the shader export intrinsic */
2285 si_llvm_init_export_args(struct radv_shader_context
*ctx
,
2286 LLVMValueRef
*values
,
2287 unsigned enabled_channels
,
2289 struct ac_export_args
*args
)
2291 /* Specify the channels that are enabled. */
2292 args
->enabled_channels
= enabled_channels
;
2294 /* Specify whether the EXEC mask represents the valid mask */
2295 args
->valid_mask
= 0;
2297 /* Specify whether this is the last export */
2300 /* Specify the target we are exporting */
2301 args
->target
= target
;
2303 args
->compr
= false;
2304 args
->out
[0] = LLVMGetUndef(ctx
->ac
.f32
);
2305 args
->out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
2306 args
->out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
2307 args
->out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
2312 bool is_16bit
= ac_get_type_size(LLVMTypeOf(values
[0])) == 2;
2313 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
2314 unsigned index
= target
- V_008DFC_SQ_EXP_MRT
;
2315 unsigned col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * index
)) & 0xf;
2316 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> index
) & 1;
2317 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> index
) & 1;
2320 LLVMValueRef (*packf
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2]) = NULL
;
2321 LLVMValueRef (*packi
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2],
2322 unsigned bits
, bool hi
) = NULL
;
2324 switch(col_format
) {
2325 case V_028714_SPI_SHADER_ZERO
:
2326 args
->enabled_channels
= 0; /* writemask */
2327 args
->target
= V_008DFC_SQ_EXP_NULL
;
2330 case V_028714_SPI_SHADER_32_R
:
2331 args
->enabled_channels
= 1;
2332 args
->out
[0] = values
[0];
2335 case V_028714_SPI_SHADER_32_GR
:
2336 args
->enabled_channels
= 0x3;
2337 args
->out
[0] = values
[0];
2338 args
->out
[1] = values
[1];
2341 case V_028714_SPI_SHADER_32_AR
:
2342 if (ctx
->ac
.chip_class
>= GFX10
) {
2343 args
->enabled_channels
= 0x3;
2344 args
->out
[0] = values
[0];
2345 args
->out
[1] = values
[3];
2347 args
->enabled_channels
= 0x9;
2348 args
->out
[0] = values
[0];
2349 args
->out
[3] = values
[3];
2353 case V_028714_SPI_SHADER_FP16_ABGR
:
2354 args
->enabled_channels
= 0x5;
2355 packf
= ac_build_cvt_pkrtz_f16
;
2357 for (unsigned chan
= 0; chan
< 4; chan
++)
2358 values
[chan
] = LLVMBuildFPExt(ctx
->ac
.builder
,
2364 case V_028714_SPI_SHADER_UNORM16_ABGR
:
2365 args
->enabled_channels
= 0x5;
2366 packf
= ac_build_cvt_pknorm_u16
;
2369 case V_028714_SPI_SHADER_SNORM16_ABGR
:
2370 args
->enabled_channels
= 0x5;
2371 packf
= ac_build_cvt_pknorm_i16
;
2374 case V_028714_SPI_SHADER_UINT16_ABGR
:
2375 args
->enabled_channels
= 0x5;
2376 packi
= ac_build_cvt_pk_u16
;
2378 for (unsigned chan
= 0; chan
< 4; chan
++)
2379 values
[chan
] = LLVMBuildZExt(ctx
->ac
.builder
,
2380 ac_to_integer(&ctx
->ac
, values
[chan
]),
2385 case V_028714_SPI_SHADER_SINT16_ABGR
:
2386 args
->enabled_channels
= 0x5;
2387 packi
= ac_build_cvt_pk_i16
;
2389 for (unsigned chan
= 0; chan
< 4; chan
++)
2390 values
[chan
] = LLVMBuildSExt(ctx
->ac
.builder
,
2391 ac_to_integer(&ctx
->ac
, values
[chan
]),
2397 case V_028714_SPI_SHADER_32_ABGR
:
2398 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
2402 /* Pack f16 or norm_i16/u16. */
2404 for (chan
= 0; chan
< 2; chan
++) {
2405 LLVMValueRef pack_args
[2] = {
2407 values
[2 * chan
+ 1]
2409 LLVMValueRef packed
;
2411 packed
= packf(&ctx
->ac
, pack_args
);
2412 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2414 args
->compr
= 1; /* COMPR flag */
2419 for (chan
= 0; chan
< 2; chan
++) {
2420 LLVMValueRef pack_args
[2] = {
2421 ac_to_integer(&ctx
->ac
, values
[2 * chan
]),
2422 ac_to_integer(&ctx
->ac
, values
[2 * chan
+ 1])
2424 LLVMValueRef packed
;
2426 packed
= packi(&ctx
->ac
, pack_args
,
2427 is_int8
? 8 : is_int10
? 10 : 16,
2429 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2431 args
->compr
= 1; /* COMPR flag */
2437 for (unsigned chan
= 0; chan
< 4; chan
++) {
2438 values
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, values
[chan
], ctx
->ac
.i16
, "");
2439 args
->out
[chan
] = LLVMBuildZExt(ctx
->ac
.builder
, values
[chan
], ctx
->ac
.i32
, "");
2442 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
2444 for (unsigned i
= 0; i
< 4; ++i
)
2445 args
->out
[i
] = ac_to_float(&ctx
->ac
, args
->out
[i
]);
2449 radv_export_param(struct radv_shader_context
*ctx
, unsigned index
,
2450 LLVMValueRef
*values
, unsigned enabled_channels
)
2452 struct ac_export_args args
;
2454 si_llvm_init_export_args(ctx
, values
, enabled_channels
,
2455 V_008DFC_SQ_EXP_PARAM
+ index
, &args
);
2456 ac_build_export(&ctx
->ac
, &args
);
2460 radv_load_output(struct radv_shader_context
*ctx
, unsigned index
, unsigned chan
)
2462 LLVMValueRef output
= ctx
->abi
.outputs
[ac_llvm_reg_index_soa(index
, chan
)];
2463 return LLVMBuildLoad(ctx
->ac
.builder
, output
, "");
2467 radv_emit_stream_output(struct radv_shader_context
*ctx
,
2468 LLVMValueRef
const *so_buffers
,
2469 LLVMValueRef
const *so_write_offsets
,
2470 const struct radv_stream_output
*output
,
2471 struct radv_shader_output_values
*shader_out
)
2473 unsigned num_comps
= util_bitcount(output
->component_mask
);
2474 unsigned buf
= output
->buffer
;
2475 unsigned offset
= output
->offset
;
2477 LLVMValueRef out
[4];
2479 assert(num_comps
&& num_comps
<= 4);
2480 if (!num_comps
|| num_comps
> 4)
2483 /* Get the first component. */
2484 start
= ffs(output
->component_mask
) - 1;
2486 /* Load the output as int. */
2487 for (int i
= 0; i
< num_comps
; i
++) {
2488 out
[i
] = ac_to_integer(&ctx
->ac
, shader_out
->values
[start
+ i
]);
2491 /* Pack the output. */
2492 LLVMValueRef vdata
= NULL
;
2494 switch (num_comps
) {
2495 case 1: /* as i32 */
2498 case 2: /* as v2i32 */
2499 case 3: /* as v4i32 (aligned to 4) */
2500 out
[3] = LLVMGetUndef(ctx
->ac
.i32
);
2502 case 4: /* as v4i32 */
2503 vdata
= ac_build_gather_values(&ctx
->ac
, out
,
2504 !ac_has_vec3_support(ctx
->ac
.chip_class
, false) ?
2505 util_next_power_of_two(num_comps
) :
2510 ac_build_buffer_store_dword(&ctx
->ac
, so_buffers
[buf
],
2511 vdata
, num_comps
, so_write_offsets
[buf
],
2512 ctx
->ac
.i32_0
, offset
,
2513 ac_glc
| ac_slc
, false);
2517 radv_emit_streamout(struct radv_shader_context
*ctx
, unsigned stream
)
2521 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2522 assert(ctx
->streamout_config
);
2523 LLVMValueRef so_vtx_count
=
2524 ac_build_bfe(&ctx
->ac
, ctx
->streamout_config
,
2525 LLVMConstInt(ctx
->ac
.i32
, 16, false),
2526 LLVMConstInt(ctx
->ac
.i32
, 7, false), false);
2528 LLVMValueRef tid
= ac_get_thread_id(&ctx
->ac
);
2530 /* can_emit = tid < so_vtx_count; */
2531 LLVMValueRef can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
,
2532 tid
, so_vtx_count
, "");
2534 /* Emit the streamout code conditionally. This actually avoids
2535 * out-of-bounds buffer access. The hw tells us via the SGPR
2536 * (so_vtx_count) which threads are allowed to emit streamout data.
2538 ac_build_ifcc(&ctx
->ac
, can_emit
, 6501);
2540 /* The buffer offset is computed as follows:
2541 * ByteOffset = streamout_offset[buffer_id]*4 +
2542 * (streamout_write_index + thread_id)*stride[buffer_id] +
2545 LLVMValueRef so_write_index
= ctx
->streamout_write_idx
;
2547 /* Compute (streamout_write_index + thread_id). */
2549 LLVMBuildAdd(ctx
->ac
.builder
, so_write_index
, tid
, "");
2551 /* Load the descriptor and compute the write offset for each
2554 LLVMValueRef so_write_offset
[4] = {};
2555 LLVMValueRef so_buffers
[4] = {};
2556 LLVMValueRef buf_ptr
= ctx
->streamout_buffers
;
2558 for (i
= 0; i
< 4; i
++) {
2559 uint16_t stride
= ctx
->shader_info
->so
.strides
[i
];
2564 LLVMValueRef offset
=
2565 LLVMConstInt(ctx
->ac
.i32
, i
, false);
2567 so_buffers
[i
] = ac_build_load_to_sgpr(&ctx
->ac
,
2570 LLVMValueRef so_offset
= ctx
->streamout_offset
[i
];
2572 so_offset
= LLVMBuildMul(ctx
->ac
.builder
, so_offset
,
2573 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
2575 so_write_offset
[i
] =
2576 ac_build_imad(&ctx
->ac
, so_write_index
,
2577 LLVMConstInt(ctx
->ac
.i32
,
2582 /* Write streamout data. */
2583 for (i
= 0; i
< ctx
->shader_info
->so
.num_outputs
; i
++) {
2584 struct radv_shader_output_values shader_out
= {};
2585 struct radv_stream_output
*output
=
2586 &ctx
->shader_info
->so
.outputs
[i
];
2588 if (stream
!= output
->stream
)
2591 for (int j
= 0; j
< 4; j
++) {
2592 shader_out
.values
[j
] =
2593 radv_load_output(ctx
, output
->location
, j
);
2596 radv_emit_stream_output(ctx
, so_buffers
,so_write_offset
,
2597 output
, &shader_out
);
2600 ac_build_endif(&ctx
->ac
, 6501);
2604 radv_build_param_exports(struct radv_shader_context
*ctx
,
2605 struct radv_shader_output_values
*outputs
,
2607 struct radv_vs_output_info
*outinfo
,
2608 bool export_clip_dists
)
2610 unsigned param_count
= 0;
2612 for (unsigned i
= 0; i
< noutput
; i
++) {
2613 unsigned slot_name
= outputs
[i
].slot_name
;
2614 unsigned usage_mask
= outputs
[i
].usage_mask
;
2616 if (slot_name
!= VARYING_SLOT_LAYER
&&
2617 slot_name
!= VARYING_SLOT_PRIMITIVE_ID
&&
2618 slot_name
!= VARYING_SLOT_CLIP_DIST0
&&
2619 slot_name
!= VARYING_SLOT_CLIP_DIST1
&&
2620 slot_name
< VARYING_SLOT_VAR0
)
2623 if ((slot_name
== VARYING_SLOT_CLIP_DIST0
||
2624 slot_name
== VARYING_SLOT_CLIP_DIST1
) && !export_clip_dists
)
2627 radv_export_param(ctx
, param_count
, outputs
[i
].values
, usage_mask
);
2629 assert(i
< ARRAY_SIZE(outinfo
->vs_output_param_offset
));
2630 outinfo
->vs_output_param_offset
[slot_name
] = param_count
++;
2633 outinfo
->param_exports
= param_count
;
2636 /* Generate export instructions for hardware VS shader stage or NGG GS stage
2637 * (position and parameter data only).
2640 radv_llvm_export_vs(struct radv_shader_context
*ctx
,
2641 struct radv_shader_output_values
*outputs
,
2643 struct radv_vs_output_info
*outinfo
,
2644 bool export_clip_dists
)
2646 LLVMValueRef psize_value
= NULL
, layer_value
= NULL
, viewport_value
= NULL
;
2647 struct ac_export_args pos_args
[4] = {};
2648 unsigned pos_idx
, index
;
2651 /* Build position exports */
2652 for (i
= 0; i
< noutput
; i
++) {
2653 switch (outputs
[i
].slot_name
) {
2654 case VARYING_SLOT_POS
:
2655 si_llvm_init_export_args(ctx
, outputs
[i
].values
, 0xf,
2656 V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
2658 case VARYING_SLOT_PSIZ
:
2659 psize_value
= outputs
[i
].values
[0];
2661 case VARYING_SLOT_LAYER
:
2662 layer_value
= outputs
[i
].values
[0];
2664 case VARYING_SLOT_VIEWPORT
:
2665 viewport_value
= outputs
[i
].values
[0];
2667 case VARYING_SLOT_CLIP_DIST0
:
2668 case VARYING_SLOT_CLIP_DIST1
:
2669 index
= 2 + outputs
[i
].slot_index
;
2670 si_llvm_init_export_args(ctx
, outputs
[i
].values
, 0xf,
2671 V_008DFC_SQ_EXP_POS
+ index
,
2679 /* We need to add the position output manually if it's missing. */
2680 if (!pos_args
[0].out
[0]) {
2681 pos_args
[0].enabled_channels
= 0xf; /* writemask */
2682 pos_args
[0].valid_mask
= 0; /* EXEC mask */
2683 pos_args
[0].done
= 0; /* last export? */
2684 pos_args
[0].target
= V_008DFC_SQ_EXP_POS
;
2685 pos_args
[0].compr
= 0; /* COMPR flag */
2686 pos_args
[0].out
[0] = ctx
->ac
.f32_0
; /* X */
2687 pos_args
[0].out
[1] = ctx
->ac
.f32_0
; /* Y */
2688 pos_args
[0].out
[2] = ctx
->ac
.f32_0
; /* Z */
2689 pos_args
[0].out
[3] = ctx
->ac
.f32_1
; /* W */
2692 if (outinfo
->writes_pointsize
||
2693 outinfo
->writes_layer
||
2694 outinfo
->writes_viewport_index
) {
2695 pos_args
[1].enabled_channels
= ((outinfo
->writes_pointsize
== true ? 1 : 0) |
2696 (outinfo
->writes_layer
== true ? 4 : 0));
2697 pos_args
[1].valid_mask
= 0;
2698 pos_args
[1].done
= 0;
2699 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
2700 pos_args
[1].compr
= 0;
2701 pos_args
[1].out
[0] = ctx
->ac
.f32_0
; /* X */
2702 pos_args
[1].out
[1] = ctx
->ac
.f32_0
; /* Y */
2703 pos_args
[1].out
[2] = ctx
->ac
.f32_0
; /* Z */
2704 pos_args
[1].out
[3] = ctx
->ac
.f32_0
; /* W */
2706 if (outinfo
->writes_pointsize
== true)
2707 pos_args
[1].out
[0] = psize_value
;
2708 if (outinfo
->writes_layer
== true)
2709 pos_args
[1].out
[2] = layer_value
;
2710 if (outinfo
->writes_viewport_index
== true) {
2711 if (ctx
->options
->chip_class
>= GFX9
) {
2712 /* GFX9 has the layer in out.z[10:0] and the viewport
2713 * index in out.z[19:16].
2715 LLVMValueRef v
= viewport_value
;
2716 v
= ac_to_integer(&ctx
->ac
, v
);
2717 v
= LLVMBuildShl(ctx
->ac
.builder
, v
,
2718 LLVMConstInt(ctx
->ac
.i32
, 16, false),
2720 v
= LLVMBuildOr(ctx
->ac
.builder
, v
,
2721 ac_to_integer(&ctx
->ac
, pos_args
[1].out
[2]), "");
2723 pos_args
[1].out
[2] = ac_to_float(&ctx
->ac
, v
);
2724 pos_args
[1].enabled_channels
|= 1 << 2;
2726 pos_args
[1].out
[3] = viewport_value
;
2727 pos_args
[1].enabled_channels
|= 1 << 3;
2732 for (i
= 0; i
< 4; i
++) {
2733 if (pos_args
[i
].out
[0])
2734 outinfo
->pos_exports
++;
2737 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
2738 * Setting valid_mask=1 prevents it and has no other effect.
2740 if (ctx
->ac
.family
== CHIP_NAVI10
||
2741 ctx
->ac
.family
== CHIP_NAVI12
||
2742 ctx
->ac
.family
== CHIP_NAVI14
)
2743 pos_args
[0].valid_mask
= 1;
2746 for (i
= 0; i
< 4; i
++) {
2747 if (!pos_args
[i
].out
[0])
2750 /* Specify the target we are exporting */
2751 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
2753 if (pos_idx
== outinfo
->pos_exports
)
2754 /* Specify that this is the last export */
2755 pos_args
[i
].done
= 1;
2757 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
2760 /* Build parameter exports */
2761 radv_build_param_exports(ctx
, outputs
, noutput
, outinfo
, export_clip_dists
);
2765 handle_vs_outputs_post(struct radv_shader_context
*ctx
,
2766 bool export_prim_id
,
2767 bool export_clip_dists
,
2768 struct radv_vs_output_info
*outinfo
)
2770 struct radv_shader_output_values
*outputs
;
2771 unsigned noutput
= 0;
2773 if (ctx
->options
->key
.has_multiview_view_index
) {
2774 LLVMValueRef
* tmp_out
= &ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
2776 for(unsigned i
= 0; i
< 4; ++i
)
2777 ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, i
)] =
2778 ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
2781 LLVMBuildStore(ctx
->ac
.builder
, ac_to_float(&ctx
->ac
, ctx
->abi
.view_index
), *tmp_out
);
2782 ctx
->output_mask
|= 1ull << VARYING_SLOT_LAYER
;
2785 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
2786 sizeof(outinfo
->vs_output_param_offset
));
2787 outinfo
->pos_exports
= 0;
2789 if (ctx
->shader_info
->so
.num_outputs
&&
2790 !ctx
->is_gs_copy_shader
) {
2791 /* The GS copy shader emission already emits streamout. */
2792 radv_emit_streamout(ctx
, 0);
2795 /* Allocate a temporary array for the output values. */
2796 unsigned num_outputs
= util_bitcount64(ctx
->output_mask
) + export_prim_id
;
2797 outputs
= malloc(num_outputs
* sizeof(outputs
[0]));
2799 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2800 if (!(ctx
->output_mask
& (1ull << i
)))
2803 outputs
[noutput
].slot_name
= i
;
2804 outputs
[noutput
].slot_index
= i
== VARYING_SLOT_CLIP_DIST1
;
2806 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
2807 !ctx
->is_gs_copy_shader
) {
2808 outputs
[noutput
].usage_mask
=
2809 ctx
->shader_info
->vs
.output_usage_mask
[i
];
2810 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
2811 outputs
[noutput
].usage_mask
=
2812 ctx
->shader_info
->tes
.output_usage_mask
[i
];
2814 assert(ctx
->is_gs_copy_shader
);
2815 outputs
[noutput
].usage_mask
=
2816 ctx
->shader_info
->gs
.output_usage_mask
[i
];
2819 for (unsigned j
= 0; j
< 4; j
++) {
2820 outputs
[noutput
].values
[j
] =
2821 ac_to_float(&ctx
->ac
, radv_load_output(ctx
, i
, j
));
2827 /* Export PrimitiveID. */
2828 if (export_prim_id
) {
2829 outputs
[noutput
].slot_name
= VARYING_SLOT_PRIMITIVE_ID
;
2830 outputs
[noutput
].slot_index
= 0;
2831 outputs
[noutput
].usage_mask
= 0x1;
2832 outputs
[noutput
].values
[0] = ctx
->vs_prim_id
;
2833 for (unsigned j
= 1; j
< 4; j
++)
2834 outputs
[noutput
].values
[j
] = ctx
->ac
.f32_0
;
2838 radv_llvm_export_vs(ctx
, outputs
, noutput
, outinfo
, export_clip_dists
);
2844 handle_es_outputs_post(struct radv_shader_context
*ctx
,
2845 struct radv_es_output_info
*outinfo
)
2848 uint64_t max_output_written
= 0;
2849 LLVMValueRef lds_base
= NULL
;
2851 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2854 if (!(ctx
->output_mask
& (1ull << i
)))
2857 param_index
= shader_io_get_unique_index(i
);
2859 max_output_written
= MAX2(param_index
, max_output_written
);
2862 outinfo
->esgs_itemsize
= (max_output_written
+ 1) * 16;
2864 if (ctx
->ac
.chip_class
>= GFX9
) {
2865 unsigned itemsize_dw
= outinfo
->esgs_itemsize
/ 4;
2866 LLVMValueRef vertex_idx
= ac_get_thread_id(&ctx
->ac
);
2867 LLVMValueRef wave_idx
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 24, 4);
2868 vertex_idx
= LLVMBuildOr(ctx
->ac
.builder
, vertex_idx
,
2869 LLVMBuildMul(ctx
->ac
.builder
, wave_idx
,
2870 LLVMConstInt(ctx
->ac
.i32
,
2871 ctx
->ac
.wave_size
, false), ""), "");
2872 lds_base
= LLVMBuildMul(ctx
->ac
.builder
, vertex_idx
,
2873 LLVMConstInt(ctx
->ac
.i32
, itemsize_dw
, 0), "");
2876 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2877 LLVMValueRef dw_addr
= NULL
;
2878 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
2879 unsigned output_usage_mask
;
2882 if (!(ctx
->output_mask
& (1ull << i
)))
2885 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2887 ctx
->shader_info
->vs
.output_usage_mask
[i
];
2889 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
2891 ctx
->shader_info
->tes
.output_usage_mask
[i
];
2894 param_index
= shader_io_get_unique_index(i
);
2897 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
2898 LLVMConstInt(ctx
->ac
.i32
, param_index
* 4, false),
2902 for (j
= 0; j
< 4; j
++) {
2903 if (!(output_usage_mask
& (1 << j
)))
2906 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
2907 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
2908 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
2910 if (ctx
->ac
.chip_class
>= GFX9
) {
2911 LLVMValueRef dw_addr_offset
=
2912 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2913 LLVMConstInt(ctx
->ac
.i32
,
2916 ac_lds_store(&ctx
->ac
, dw_addr_offset
, out_val
);
2918 ac_build_buffer_store_dword(&ctx
->ac
,
2921 NULL
, ctx
->es2gs_offset
,
2922 (4 * param_index
+ j
) * 4,
2923 ac_glc
| ac_slc
, true);
2930 handle_ls_outputs_post(struct radv_shader_context
*ctx
)
2932 LLVMValueRef vertex_id
= ctx
->rel_auto_id
;
2933 uint32_t num_tcs_inputs
= util_last_bit64(ctx
->shader_info
->vs
.ls_outputs_written
);
2934 LLVMValueRef vertex_dw_stride
= LLVMConstInt(ctx
->ac
.i32
, num_tcs_inputs
* 4, false);
2935 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->ac
.builder
, vertex_id
,
2936 vertex_dw_stride
, "");
2938 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2939 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
2941 if (!(ctx
->output_mask
& (1ull << i
)))
2944 int param
= shader_io_get_unique_index(i
);
2945 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_dw_addr
,
2946 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false),
2948 for (unsigned j
= 0; j
< 4; j
++) {
2949 LLVMValueRef value
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
2950 value
= ac_to_integer(&ctx
->ac
, value
);
2951 value
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
2952 ac_lds_store(&ctx
->ac
, dw_addr
, value
);
2953 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
, ctx
->ac
.i32_1
, "");
2958 static LLVMValueRef
get_wave_id_in_tg(struct radv_shader_context
*ctx
)
2960 return ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 24, 4);
2963 static LLVMValueRef
get_tgsize(struct radv_shader_context
*ctx
)
2965 return ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 28, 4);
2968 static LLVMValueRef
get_thread_id_in_tg(struct radv_shader_context
*ctx
)
2970 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2972 tmp
= LLVMBuildMul(builder
, get_wave_id_in_tg(ctx
),
2973 LLVMConstInt(ctx
->ac
.i32
, ctx
->ac
.wave_size
, false), "");
2974 return LLVMBuildAdd(builder
, tmp
, ac_get_thread_id(&ctx
->ac
), "");
2977 static LLVMValueRef
ngg_get_vtx_cnt(struct radv_shader_context
*ctx
)
2979 return ac_build_bfe(&ctx
->ac
, ctx
->gs_tg_info
,
2980 LLVMConstInt(ctx
->ac
.i32
, 12, false),
2981 LLVMConstInt(ctx
->ac
.i32
, 9, false),
2985 static LLVMValueRef
ngg_get_prim_cnt(struct radv_shader_context
*ctx
)
2987 return ac_build_bfe(&ctx
->ac
, ctx
->gs_tg_info
,
2988 LLVMConstInt(ctx
->ac
.i32
, 22, false),
2989 LLVMConstInt(ctx
->ac
.i32
, 9, false),
2994 ngg_gs_get_vertex_storage(struct radv_shader_context
*ctx
)
2996 unsigned num_outputs
= util_bitcount64(ctx
->output_mask
);
2998 LLVMTypeRef elements
[2] = {
2999 LLVMArrayType(ctx
->ac
.i32
, 4 * num_outputs
),
3000 LLVMArrayType(ctx
->ac
.i8
, 4),
3002 LLVMTypeRef type
= LLVMStructTypeInContext(ctx
->ac
.context
, elements
, 2, false);
3003 type
= LLVMPointerType(LLVMArrayType(type
, 0), AC_ADDR_SPACE_LDS
);
3004 return LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->gs_ngg_emit
, type
, "");
3008 * Return a pointer to the LDS storage reserved for the N'th vertex, where N
3009 * is in emit order; that is:
3010 * - during the epilogue, N is the threadidx (relative to the entire threadgroup)
3011 * - during vertex emit, i.e. while the API GS shader invocation is running,
3012 * N = threadidx * gs_max_out_vertices + emitidx
3014 * Goals of the LDS memory layout:
3015 * 1. Eliminate bank conflicts on write for geometry shaders that have all emits
3016 * in uniform control flow
3017 * 2. Eliminate bank conflicts on read for export if, additionally, there is no
3019 * 3. Agnostic to the number of waves (since we don't know it before compiling)
3020 * 4. Allow coalescing of LDS instructions (ds_write_b128 etc.)
3021 * 5. Avoid wasting memory.
3023 * We use an AoS layout due to point 4 (this also helps point 3). In an AoS
3024 * layout, elimination of bank conflicts requires that each vertex occupy an
3025 * odd number of dwords. We use the additional dword to store the output stream
3026 * index as well as a flag to indicate whether this vertex ends a primitive
3027 * for rasterization.
3029 * Swizzling is required to satisfy points 1 and 2 simultaneously.
3031 * Vertices are stored in export order (gsthread * gs_max_out_vertices + emitidx).
3032 * Indices are swizzled in groups of 32, which ensures point 1 without
3033 * disturbing point 2.
3035 * \return an LDS pointer to type {[N x i32], [4 x i8]}
3038 ngg_gs_vertex_ptr(struct radv_shader_context
*ctx
, LLVMValueRef vertexidx
)
3040 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3041 LLVMValueRef storage
= ngg_gs_get_vertex_storage(ctx
);
3043 /* gs_max_out_vertices = 2^(write_stride_2exp) * some odd number */
3044 unsigned write_stride_2exp
= ffs(ctx
->shader
->info
.gs
.vertices_out
) - 1;
3045 if (write_stride_2exp
) {
3047 LLVMBuildLShr(builder
, vertexidx
,
3048 LLVMConstInt(ctx
->ac
.i32
, 5, false), "");
3049 LLVMValueRef swizzle
=
3050 LLVMBuildAnd(builder
, row
,
3051 LLVMConstInt(ctx
->ac
.i32
, (1u << write_stride_2exp
) - 1,
3053 vertexidx
= LLVMBuildXor(builder
, vertexidx
, swizzle
, "");
3056 return ac_build_gep0(&ctx
->ac
, storage
, vertexidx
);
3060 ngg_gs_emit_vertex_ptr(struct radv_shader_context
*ctx
, LLVMValueRef gsthread
,
3061 LLVMValueRef emitidx
)
3063 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3066 tmp
= LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.gs
.vertices_out
, false);
3067 tmp
= LLVMBuildMul(builder
, tmp
, gsthread
, "");
3068 const LLVMValueRef vertexidx
= LLVMBuildAdd(builder
, tmp
, emitidx
, "");
3069 return ngg_gs_vertex_ptr(ctx
, vertexidx
);
3072 /* Send GS Alloc Req message from the first wave of the group to SPI.
3073 * Message payload is:
3074 * - bits 0..10: vertices in group
3075 * - bits 12..22: primitives in group
3077 static void build_sendmsg_gs_alloc_req(struct radv_shader_context
*ctx
,
3078 LLVMValueRef vtx_cnt
,
3079 LLVMValueRef prim_cnt
)
3081 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3084 tmp
= LLVMBuildICmp(builder
, LLVMIntEQ
, get_wave_id_in_tg(ctx
), ctx
->ac
.i32_0
, "");
3085 ac_build_ifcc(&ctx
->ac
, tmp
, 5020);
3087 tmp
= LLVMBuildShl(builder
, prim_cnt
, LLVMConstInt(ctx
->ac
.i32
, 12, false),"");
3088 tmp
= LLVMBuildOr(builder
, tmp
, vtx_cnt
, "");
3089 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_ALLOC_REQ
, tmp
);
3091 ac_build_endif(&ctx
->ac
, 5020);
3095 unsigned num_vertices
;
3096 LLVMValueRef isnull
;
3097 LLVMValueRef index
[3];
3098 LLVMValueRef edgeflag
[3];
3101 static void build_export_prim(struct radv_shader_context
*ctx
,
3102 const struct ngg_prim
*prim
)
3104 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3105 struct ac_export_args args
;
3108 tmp
= LLVMBuildZExt(builder
, prim
->isnull
, ctx
->ac
.i32
, "");
3109 args
.out
[0] = LLVMBuildShl(builder
, tmp
, LLVMConstInt(ctx
->ac
.i32
, 31, false), "");
3111 for (unsigned i
= 0; i
< prim
->num_vertices
; ++i
) {
3112 tmp
= LLVMBuildShl(builder
, prim
->index
[i
],
3113 LLVMConstInt(ctx
->ac
.i32
, 10 * i
, false), "");
3114 args
.out
[0] = LLVMBuildOr(builder
, args
.out
[0], tmp
, "");
3115 tmp
= LLVMBuildZExt(builder
, prim
->edgeflag
[i
], ctx
->ac
.i32
, "");
3116 tmp
= LLVMBuildShl(builder
, tmp
,
3117 LLVMConstInt(ctx
->ac
.i32
, 10 * i
+ 9, false), "");
3118 args
.out
[0] = LLVMBuildOr(builder
, args
.out
[0], tmp
, "");
3121 args
.out
[0] = LLVMBuildBitCast(builder
, args
.out
[0], ctx
->ac
.f32
, "");
3122 args
.out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
3123 args
.out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
3124 args
.out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
3126 args
.target
= V_008DFC_SQ_EXP_PRIM
;
3127 args
.enabled_channels
= 1;
3129 args
.valid_mask
= false;
3132 ac_build_export(&ctx
->ac
, &args
);
3136 handle_ngg_outputs_post(struct radv_shader_context
*ctx
)
3138 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3139 unsigned num_vertices
= 3;
3142 assert((ctx
->stage
== MESA_SHADER_VERTEX
||
3143 ctx
->stage
== MESA_SHADER_TESS_EVAL
) && !ctx
->is_gs_copy_shader
);
3145 LLVMValueRef prims_in_wave
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 8, 8);
3146 LLVMValueRef vtx_in_wave
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 0, 8);
3147 LLVMValueRef is_gs_thread
= LLVMBuildICmp(builder
, LLVMIntULT
,
3148 ac_get_thread_id(&ctx
->ac
), prims_in_wave
, "");
3149 LLVMValueRef is_es_thread
= LLVMBuildICmp(builder
, LLVMIntULT
,
3150 ac_get_thread_id(&ctx
->ac
), vtx_in_wave
, "");
3151 LLVMValueRef vtxindex
[] = {
3152 ac_unpack_param(&ctx
->ac
, ctx
->gs_vtx_offset
[0], 0, 16),
3153 ac_unpack_param(&ctx
->ac
, ctx
->gs_vtx_offset
[0], 16, 16),
3154 ac_unpack_param(&ctx
->ac
, ctx
->gs_vtx_offset
[2], 0, 16),
3157 /* TODO: streamout */
3159 /* Copy Primitive IDs from GS threads to the LDS address corresponding
3160 * to the ES thread of the provoking vertex.
3162 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
3163 ctx
->options
->key
.vs_common_out
.export_prim_id
) {
3164 /* TODO: streamout */
3166 ac_build_ifcc(&ctx
->ac
, is_gs_thread
, 5400);
3167 /* Extract the PROVOKING_VTX_INDEX field. */
3168 LLVMValueRef provoking_vtx_in_prim
=
3169 LLVMConstInt(ctx
->ac
.i32
, 0, false);
3171 /* provoking_vtx_index = vtxindex[provoking_vtx_in_prim]; */
3172 LLVMValueRef indices
= ac_build_gather_values(&ctx
->ac
, vtxindex
, 3);
3173 LLVMValueRef provoking_vtx_index
=
3174 LLVMBuildExtractElement(builder
, indices
, provoking_vtx_in_prim
, "");
3176 LLVMBuildStore(builder
, ctx
->abi
.gs_prim_id
,
3177 ac_build_gep0(&ctx
->ac
, ctx
->esgs_ring
, provoking_vtx_index
));
3178 ac_build_endif(&ctx
->ac
, 5400);
3181 /* TODO: primitive culling */
3183 build_sendmsg_gs_alloc_req(ctx
, ngg_get_vtx_cnt(ctx
), ngg_get_prim_cnt(ctx
));
3185 /* TODO: streamout queries */
3186 /* Export primitive data to the index buffer. Format is:
3187 * - bits 0..8: index 0
3188 * - bit 9: edge flag 0
3189 * - bits 10..18: index 1
3190 * - bit 19: edge flag 1
3191 * - bits 20..28: index 2
3192 * - bit 29: edge flag 2
3193 * - bit 31: null primitive (skip)
3195 * For the first version, we will always build up all three indices
3196 * independent of the primitive type. The additional garbage data
3199 * TODO: culling depends on the primitive type, so can have some
3202 ac_build_ifcc(&ctx
->ac
, is_gs_thread
, 6001);
3204 struct ngg_prim prim
= {};
3206 prim
.num_vertices
= num_vertices
;
3207 prim
.isnull
= ctx
->ac
.i1false
;
3208 memcpy(prim
.index
, vtxindex
, sizeof(vtxindex
[0]) * 3);
3210 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
3211 tmp
= LLVMBuildLShr(builder
, ctx
->abi
.gs_invocation_id
,
3212 LLVMConstInt(ctx
->ac
.i32
, 8 + i
, false), "");
3213 prim
.edgeflag
[i
] = LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
3216 build_export_prim(ctx
, &prim
);
3218 ac_build_endif(&ctx
->ac
, 6001);
3220 /* Export per-vertex data (positions and parameters). */
3221 ac_build_ifcc(&ctx
->ac
, is_es_thread
, 6002);
3223 struct radv_vs_output_info
*outinfo
=
3224 ctx
->stage
== MESA_SHADER_TESS_EVAL
? &ctx
->shader_info
->tes
.outinfo
: &ctx
->shader_info
->vs
.outinfo
;
3226 /* Exporting the primitive ID is handled below. */
3227 /* TODO: use the new VS export path */
3228 handle_vs_outputs_post(ctx
, false,
3229 ctx
->options
->key
.vs_common_out
.export_clip_dists
,
3232 if (ctx
->options
->key
.vs_common_out
.export_prim_id
) {
3233 unsigned param_count
= outinfo
->param_exports
;
3234 LLVMValueRef values
[4];
3236 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
3237 /* Wait for GS stores to finish. */
3238 ac_build_s_barrier(&ctx
->ac
);
3240 tmp
= ac_build_gep0(&ctx
->ac
, ctx
->esgs_ring
,
3241 get_thread_id_in_tg(ctx
));
3242 values
[0] = LLVMBuildLoad(builder
, tmp
, "");
3244 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
3245 values
[0] = ctx
->abi
.tes_patch_id
;
3248 values
[0] = ac_to_float(&ctx
->ac
, values
[0]);
3249 for (unsigned j
= 1; j
< 4; j
++)
3250 values
[j
] = ctx
->ac
.f32_0
;
3252 radv_export_param(ctx
, param_count
, values
, 0x1);
3254 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
++;
3255 outinfo
->param_exports
= param_count
;
3258 ac_build_endif(&ctx
->ac
, 6002);
3261 static void gfx10_ngg_gs_emit_prologue(struct radv_shader_context
*ctx
)
3263 /* Zero out the part of LDS scratch that is used to accumulate the
3264 * per-stream generated primitive count.
3266 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3267 LLVMValueRef scratchptr
= ctx
->gs_ngg_scratch
;
3268 LLVMValueRef tid
= get_thread_id_in_tg(ctx
);
3269 LLVMBasicBlockRef merge_block
;
3272 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
->ac
.builder
));
3273 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
3274 merge_block
= LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
3276 cond
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
3277 LLVMBuildCondBr(ctx
->ac
.builder
, cond
, then_block
, merge_block
);
3278 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, then_block
);
3280 LLVMValueRef ptr
= ac_build_gep0(&ctx
->ac
, scratchptr
, tid
);
3281 LLVMBuildStore(builder
, ctx
->ac
.i32_0
, ptr
);
3283 LLVMBuildBr(ctx
->ac
.builder
, merge_block
);
3284 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, merge_block
);
3286 ac_build_s_barrier(&ctx
->ac
);
3289 static void gfx10_ngg_gs_emit_epilogue_1(struct radv_shader_context
*ctx
)
3291 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3292 LLVMValueRef i8_0
= LLVMConstInt(ctx
->ac
.i8
, 0, false);
3295 /* Zero out remaining (non-emitted) primitive flags.
3297 * Note: Alternatively, we could pass the relevant gs_next_vertex to
3298 * the emit threads via LDS. This is likely worse in the expected
3299 * typical case where each GS thread emits the full set of
3302 for (unsigned stream
= 0; stream
< 4; ++stream
) {
3303 unsigned num_components
;
3306 ctx
->shader_info
->gs
.num_stream_output_components
[stream
];
3307 if (!num_components
)
3310 const LLVMValueRef gsthread
= get_thread_id_in_tg(ctx
);
3312 ac_build_bgnloop(&ctx
->ac
, 5100);
3314 const LLVMValueRef vertexidx
=
3315 LLVMBuildLoad(builder
, ctx
->gs_next_vertex
[stream
], "");
3316 tmp
= LLVMBuildICmp(builder
, LLVMIntUGE
, vertexidx
,
3317 LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.gs
.vertices_out
, false), "");
3318 ac_build_ifcc(&ctx
->ac
, tmp
, 5101);
3319 ac_build_break(&ctx
->ac
);
3320 ac_build_endif(&ctx
->ac
, 5101);
3322 tmp
= LLVMBuildAdd(builder
, vertexidx
, ctx
->ac
.i32_1
, "");
3323 LLVMBuildStore(builder
, tmp
, ctx
->gs_next_vertex
[stream
]);
3325 tmp
= ngg_gs_emit_vertex_ptr(ctx
, gsthread
, vertexidx
);
3326 LLVMValueRef gep_idx
[3] = {
3327 ctx
->ac
.i32_0
, /* implied C-style array */
3328 ctx
->ac
.i32_1
, /* second entry of struct */
3329 LLVMConstInt(ctx
->ac
.i32
, stream
, false),
3331 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3332 LLVMBuildStore(builder
, i8_0
, tmp
);
3334 ac_build_endloop(&ctx
->ac
, 5100);
3338 static void gfx10_ngg_gs_emit_epilogue_2(struct radv_shader_context
*ctx
)
3340 const unsigned verts_per_prim
= si_conv_gl_prim_to_vertices(ctx
->shader
->info
.gs
.output_primitive
);
3341 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3342 LLVMValueRef tmp
, tmp2
;
3344 ac_build_s_barrier(&ctx
->ac
);
3346 const LLVMValueRef tid
= get_thread_id_in_tg(ctx
);
3347 LLVMValueRef num_emit_threads
= ngg_get_prim_cnt(ctx
);
3349 /* TODO: streamout */
3353 /* Determine vertex liveness. */
3354 LLVMValueRef vertliveptr
= ac_build_alloca(&ctx
->ac
, ctx
->ac
.i1
, "vertexlive");
3356 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, num_emit_threads
, "");
3357 ac_build_ifcc(&ctx
->ac
, tmp
, 5120);
3359 for (unsigned i
= 0; i
< verts_per_prim
; ++i
) {
3360 const LLVMValueRef primidx
=
3361 LLVMBuildAdd(builder
, tid
,
3362 LLVMConstInt(ctx
->ac
.i32
, i
, false), "");
3365 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, primidx
, num_emit_threads
, "");
3366 ac_build_ifcc(&ctx
->ac
, tmp
, 5121 + i
);
3369 /* Load primitive liveness */
3370 tmp
= ngg_gs_vertex_ptr(ctx
, primidx
);
3371 LLVMValueRef gep_idx
[3] = {
3372 ctx
->ac
.i32_0
, /* implicit C-style array */
3373 ctx
->ac
.i32_1
, /* second value of struct */
3374 ctx
->ac
.i32_0
, /* stream 0 */
3376 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3377 tmp
= LLVMBuildLoad(builder
, tmp
, "");
3378 const LLVMValueRef primlive
=
3379 LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
3381 tmp
= LLVMBuildLoad(builder
, vertliveptr
, "");
3382 tmp
= LLVMBuildOr(builder
, tmp
, primlive
, ""),
3383 LLVMBuildStore(builder
, tmp
, vertliveptr
);
3386 ac_build_endif(&ctx
->ac
, 5121 + i
);
3389 ac_build_endif(&ctx
->ac
, 5120);
3391 /* Inclusive scan addition across the current wave. */
3392 LLVMValueRef vertlive
= LLVMBuildLoad(builder
, vertliveptr
, "");
3393 struct ac_wg_scan vertlive_scan
= {};
3394 vertlive_scan
.op
= nir_op_iadd
;
3395 vertlive_scan
.enable_reduce
= true;
3396 vertlive_scan
.enable_exclusive
= true;
3397 vertlive_scan
.src
= vertlive
;
3398 vertlive_scan
.scratch
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, ctx
->ac
.i32_0
);
3399 vertlive_scan
.waveidx
= get_wave_id_in_tg(ctx
);
3400 vertlive_scan
.numwaves
= get_tgsize(ctx
);
3401 vertlive_scan
.maxwaves
= 8;
3403 ac_build_wg_scan(&ctx
->ac
, &vertlive_scan
);
3405 /* Skip all exports (including index exports) when possible. At least on
3406 * early gfx10 revisions this is also to avoid hangs.
3408 LLVMValueRef have_exports
=
3409 LLVMBuildICmp(builder
, LLVMIntNE
, vertlive_scan
.result_reduce
, ctx
->ac
.i32_0
, "");
3411 LLVMBuildSelect(builder
, have_exports
, num_emit_threads
, ctx
->ac
.i32_0
, "");
3413 /* Allocate export space. Send this message as early as possible, to
3414 * hide the latency of the SQ <-> SPI roundtrip.
3416 * Note: We could consider compacting primitives for export as well.
3417 * PA processes 1 non-null prim / clock, but it fetches 4 DW of
3418 * prim data per clock and skips null primitives at no additional
3419 * cost. So compacting primitives can only be beneficial when
3420 * there are 4 or more contiguous null primitives in the export
3421 * (in the common case of single-dword prim exports).
3423 build_sendmsg_gs_alloc_req(ctx
, vertlive_scan
.result_reduce
, num_emit_threads
);
3425 /* Setup the reverse vertex compaction permutation. We re-use stream 1
3426 * of the primitive liveness flags, relying on the fact that each
3427 * threadgroup can have at most 256 threads. */
3428 ac_build_ifcc(&ctx
->ac
, vertlive
, 5130);
3430 tmp
= ngg_gs_vertex_ptr(ctx
, vertlive_scan
.result_exclusive
);
3431 LLVMValueRef gep_idx
[3] = {
3432 ctx
->ac
.i32_0
, /* implicit C-style array */
3433 ctx
->ac
.i32_1
, /* second value of struct */
3434 ctx
->ac
.i32_1
, /* stream 1 */
3436 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3437 tmp2
= LLVMBuildTrunc(builder
, tid
, ctx
->ac
.i8
, "");
3438 LLVMBuildStore(builder
, tmp2
, tmp
);
3440 ac_build_endif(&ctx
->ac
, 5130);
3442 ac_build_s_barrier(&ctx
->ac
);
3444 /* Export primitive data */
3445 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, num_emit_threads
, "");
3446 ac_build_ifcc(&ctx
->ac
, tmp
, 5140);
3448 struct ngg_prim prim
= {};
3449 prim
.num_vertices
= verts_per_prim
;
3451 tmp
= ngg_gs_vertex_ptr(ctx
, tid
);
3452 LLVMValueRef gep_idx
[3] = {
3453 ctx
->ac
.i32_0
, /* implicit C-style array */
3454 ctx
->ac
.i32_1
, /* second value of struct */
3455 ctx
->ac
.i32_0
, /* primflag */
3457 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3458 tmp
= LLVMBuildLoad(builder
, tmp
, "");
3459 prim
.isnull
= LLVMBuildICmp(builder
, LLVMIntEQ
, tmp
,
3460 LLVMConstInt(ctx
->ac
.i8
, 0, false), "");
3462 for (unsigned i
= 0; i
< verts_per_prim
; ++i
) {
3463 prim
.index
[i
] = LLVMBuildSub(builder
, vertlive_scan
.result_exclusive
,
3464 LLVMConstInt(ctx
->ac
.i32
, verts_per_prim
- i
- 1, false), "");
3465 prim
.edgeflag
[i
] = ctx
->ac
.i1false
;
3468 build_export_prim(ctx
, &prim
);
3470 ac_build_endif(&ctx
->ac
, 5140);
3472 /* Export position and parameter data */
3473 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, vertlive_scan
.result_reduce
, "");
3474 ac_build_ifcc(&ctx
->ac
, tmp
, 5145);
3476 struct radv_vs_output_info
*outinfo
= &ctx
->shader_info
->vs
.outinfo
;
3477 bool export_view_index
= ctx
->options
->key
.has_multiview_view_index
;
3478 struct radv_shader_output_values
*outputs
;
3479 unsigned noutput
= 0;
3481 /* Allocate a temporary array for the output values. */
3482 unsigned num_outputs
= util_bitcount64(ctx
->output_mask
) + export_view_index
;
3483 outputs
= calloc(num_outputs
, sizeof(outputs
[0]));
3485 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
3486 sizeof(outinfo
->vs_output_param_offset
));
3487 outinfo
->pos_exports
= 0;
3489 tmp
= ngg_gs_vertex_ptr(ctx
, tid
);
3490 LLVMValueRef gep_idx
[3] = {
3491 ctx
->ac
.i32_0
, /* implicit C-style array */
3492 ctx
->ac
.i32_1
, /* second value of struct */
3493 ctx
->ac
.i32_1
, /* stream 1: source data index */
3495 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3496 tmp
= LLVMBuildLoad(builder
, tmp
, "");
3497 tmp
= LLVMBuildZExt(builder
, tmp
, ctx
->ac
.i32
, "");
3498 const LLVMValueRef vertexptr
= ngg_gs_vertex_ptr(ctx
, tmp
);
3500 unsigned out_idx
= 0;
3501 gep_idx
[1] = ctx
->ac
.i32_0
;
3502 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3503 if (!(ctx
->output_mask
& (1ull << i
)))
3506 outputs
[noutput
].slot_name
= i
;
3507 outputs
[noutput
].slot_index
= i
== VARYING_SLOT_CLIP_DIST1
;
3509 outputs
[noutput
].usage_mask
= ctx
->shader_info
->gs
.output_usage_mask
[i
];
3510 int length
= util_last_bit(outputs
[noutput
].usage_mask
);
3512 for (unsigned j
= 0; j
< length
; j
++, out_idx
++) {
3513 gep_idx
[2] = LLVMConstInt(ctx
->ac
.i32
, out_idx
, false);
3514 tmp
= LLVMBuildGEP(builder
, vertexptr
, gep_idx
, 3, "");
3515 tmp
= LLVMBuildLoad(builder
, tmp
, "");
3517 LLVMTypeRef type
= LLVMGetAllocatedType(ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
3518 if (ac_get_type_size(type
) == 2) {
3519 tmp
= ac_to_integer(&ctx
->ac
, tmp
);
3520 tmp
= LLVMBuildTrunc(ctx
->ac
.builder
, tmp
, ctx
->ac
.i16
, "");
3523 outputs
[noutput
].values
[j
] = ac_to_float(&ctx
->ac
, tmp
);
3526 for (unsigned j
= length
; j
< 4; j
++)
3527 outputs
[noutput
].values
[j
] = LLVMGetUndef(ctx
->ac
.f32
);
3532 /* Export ViewIndex. */
3533 if (export_view_index
) {
3534 outputs
[noutput
].slot_name
= VARYING_SLOT_LAYER
;
3535 outputs
[noutput
].slot_index
= 0;
3536 outputs
[noutput
].usage_mask
= 0x1;
3537 outputs
[noutput
].values
[0] = ac_to_float(&ctx
->ac
, ctx
->abi
.view_index
);
3538 for (unsigned j
= 1; j
< 4; j
++)
3539 outputs
[noutput
].values
[j
] = ctx
->ac
.f32_0
;
3543 radv_llvm_export_vs(ctx
, outputs
, noutput
, outinfo
,
3544 ctx
->options
->key
.vs_common_out
.export_clip_dists
);
3547 ac_build_endif(&ctx
->ac
, 5145);
3550 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context
*ctx
,
3552 LLVMValueRef
*addrs
)
3554 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3556 const LLVMValueRef vertexidx
=
3557 LLVMBuildLoad(builder
, ctx
->gs_next_vertex
[stream
], "");
3559 /* If this thread has already emitted the declared maximum number of
3560 * vertices, skip the write: excessive vertex emissions are not
3561 * supposed to have any effect.
3563 const LLVMValueRef can_emit
=
3564 LLVMBuildICmp(builder
, LLVMIntULT
, vertexidx
,
3565 LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.gs
.vertices_out
, false), "");
3566 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
3568 tmp
= LLVMBuildAdd(builder
, vertexidx
, ctx
->ac
.i32_1
, "");
3569 tmp
= LLVMBuildSelect(builder
, can_emit
, tmp
, vertexidx
, "");
3570 LLVMBuildStore(builder
, tmp
, ctx
->gs_next_vertex
[stream
]);
3572 const LLVMValueRef vertexptr
=
3573 ngg_gs_emit_vertex_ptr(ctx
, get_thread_id_in_tg(ctx
), vertexidx
);
3574 unsigned out_idx
= 0;
3575 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3576 unsigned output_usage_mask
=
3577 ctx
->shader_info
->gs
.output_usage_mask
[i
];
3578 uint8_t output_stream
=
3579 ctx
->shader_info
->gs
.output_streams
[i
];
3580 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
3581 int length
= util_last_bit(output_usage_mask
);
3583 if (!(ctx
->output_mask
& (1ull << i
)) ||
3584 output_stream
!= stream
)
3587 for (unsigned j
= 0; j
< length
; j
++, out_idx
++) {
3588 if (!(output_usage_mask
& (1 << j
)))
3591 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
,
3593 LLVMValueRef gep_idx
[3] = {
3594 ctx
->ac
.i32_0
, /* implied C-style array */
3595 ctx
->ac
.i32_0
, /* first entry of struct */
3596 LLVMConstInt(ctx
->ac
.i32
, out_idx
, false),
3598 LLVMValueRef ptr
= LLVMBuildGEP(builder
, vertexptr
, gep_idx
, 3, "");
3600 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
3601 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
3603 LLVMBuildStore(builder
, out_val
, ptr
);
3606 assert(out_idx
* 4 <= ctx
->shader_info
->gs
.gsvs_vertex_size
);
3608 /* Determine and store whether this vertex completed a primitive. */
3609 const LLVMValueRef curverts
= LLVMBuildLoad(builder
, ctx
->gs_curprim_verts
[stream
], "");
3611 tmp
= LLVMConstInt(ctx
->ac
.i32
, si_conv_gl_prim_to_vertices(ctx
->shader
->info
.gs
.output_primitive
) - 1, false);
3612 const LLVMValueRef iscompleteprim
=
3613 LLVMBuildICmp(builder
, LLVMIntUGE
, curverts
, tmp
, "");
3615 tmp
= LLVMBuildAdd(builder
, curverts
, ctx
->ac
.i32_1
, "");
3616 LLVMBuildStore(builder
, tmp
, ctx
->gs_curprim_verts
[stream
]);
3618 LLVMValueRef gep_idx
[3] = {
3619 ctx
->ac
.i32_0
, /* implied C-style array */
3620 ctx
->ac
.i32_1
, /* second struct entry */
3621 LLVMConstInt(ctx
->ac
.i32
, stream
, false),
3623 const LLVMValueRef primflagptr
=
3624 LLVMBuildGEP(builder
, vertexptr
, gep_idx
, 3, "");
3626 tmp
= LLVMBuildZExt(builder
, iscompleteprim
, ctx
->ac
.i8
, "");
3627 LLVMBuildStore(builder
, tmp
, primflagptr
);
3629 tmp
= LLVMBuildLoad(builder
, ctx
->gs_generated_prims
[stream
], "");
3630 tmp
= LLVMBuildAdd(builder
, tmp
, LLVMBuildZExt(builder
, iscompleteprim
, ctx
->ac
.i32
, ""), "");
3631 LLVMBuildStore(builder
, tmp
, ctx
->gs_generated_prims
[stream
]);
3635 write_tess_factors(struct radv_shader_context
*ctx
)
3637 unsigned stride
, outer_comps
, inner_comps
;
3638 LLVMValueRef invocation_id
= ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 8, 5);
3639 LLVMValueRef rel_patch_id
= ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
3640 unsigned tess_inner_index
= 0, tess_outer_index
;
3641 LLVMValueRef lds_base
, lds_inner
= NULL
, lds_outer
, byteoffset
, buffer
;
3642 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
3644 ac_emit_barrier(&ctx
->ac
, ctx
->stage
);
3646 switch (ctx
->options
->key
.tcs
.primitive_mode
) {
3666 ac_build_ifcc(&ctx
->ac
,
3667 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3668 invocation_id
, ctx
->ac
.i32_0
, ""), 6503);
3670 lds_base
= get_tcs_out_current_patch_data_offset(ctx
);
3673 tess_inner_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
3674 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3675 LLVMConstInt(ctx
->ac
.i32
, tess_inner_index
* 4, false), "");
3678 tess_outer_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
3679 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3680 LLVMConstInt(ctx
->ac
.i32
, tess_outer_index
* 4, false), "");
3682 for (i
= 0; i
< 4; i
++) {
3683 inner
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
3684 outer
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
3688 if (ctx
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
3689 outer
[0] = out
[1] = ac_lds_load(&ctx
->ac
, lds_outer
);
3690 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
3692 outer
[1] = out
[0] = ac_lds_load(&ctx
->ac
, lds_outer
);
3694 for (i
= 0; i
< outer_comps
; i
++) {
3696 ac_lds_load(&ctx
->ac
, lds_outer
);
3697 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
3700 for (i
= 0; i
< inner_comps
; i
++) {
3701 inner
[i
] = out
[outer_comps
+i
] =
3702 ac_lds_load(&ctx
->ac
, lds_inner
);
3703 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_inner
,
3708 /* Convert the outputs to vectors for stores. */
3709 vec0
= ac_build_gather_values(&ctx
->ac
, out
, MIN2(stride
, 4));
3713 vec1
= ac_build_gather_values(&ctx
->ac
, out
+ 4, stride
- 4);
3716 buffer
= ctx
->hs_ring_tess_factor
;
3717 tf_base
= ctx
->tess_factor_offset
;
3718 byteoffset
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
3719 LLVMConstInt(ctx
->ac
.i32
, 4 * stride
, false), "");
3720 unsigned tf_offset
= 0;
3722 if (ctx
->options
->chip_class
<= GFX8
) {
3723 ac_build_ifcc(&ctx
->ac
,
3724 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3725 rel_patch_id
, ctx
->ac
.i32_0
, ""), 6504);
3727 /* Store the dynamic HS control word. */
3728 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
3729 LLVMConstInt(ctx
->ac
.i32
, 0x80000000, false),
3730 1, ctx
->ac
.i32_0
, tf_base
,
3734 ac_build_endif(&ctx
->ac
, 6504);
3737 /* Store the tessellation factors. */
3738 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
3739 MIN2(stride
, 4), byteoffset
, tf_base
,
3740 tf_offset
, ac_glc
, false);
3742 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
3743 stride
- 4, byteoffset
, tf_base
,
3744 16 + tf_offset
, ac_glc
, false);
3746 //store to offchip for TES to read - only if TES reads them
3747 if (ctx
->options
->key
.tcs
.tes_reads_tess_factors
) {
3748 LLVMValueRef inner_vec
, outer_vec
, tf_outer_offset
;
3749 LLVMValueRef tf_inner_offset
;
3750 unsigned param_outer
, param_inner
;
3752 param_outer
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
3753 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
3754 LLVMConstInt(ctx
->ac
.i32
, param_outer
, 0));
3756 outer_vec
= ac_build_gather_values(&ctx
->ac
, outer
,
3757 util_next_power_of_two(outer_comps
));
3759 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, outer_vec
,
3760 outer_comps
, tf_outer_offset
,
3761 ctx
->oc_lds
, 0, ac_glc
, false);
3763 param_inner
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
3764 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
3765 LLVMConstInt(ctx
->ac
.i32
, param_inner
, 0));
3767 inner_vec
= inner_comps
== 1 ? inner
[0] :
3768 ac_build_gather_values(&ctx
->ac
, inner
, inner_comps
);
3769 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, inner_vec
,
3770 inner_comps
, tf_inner_offset
,
3771 ctx
->oc_lds
, 0, ac_glc
, false);
3775 ac_build_endif(&ctx
->ac
, 6503);
3779 handle_tcs_outputs_post(struct radv_shader_context
*ctx
)
3781 write_tess_factors(ctx
);
3785 si_export_mrt_color(struct radv_shader_context
*ctx
,
3786 LLVMValueRef
*color
, unsigned index
,
3787 struct ac_export_args
*args
)
3790 si_llvm_init_export_args(ctx
, color
, 0xf,
3791 V_008DFC_SQ_EXP_MRT
+ index
, args
);
3792 if (!args
->enabled_channels
)
3793 return false; /* unnecessary NULL export */
3799 radv_export_mrt_z(struct radv_shader_context
*ctx
,
3800 LLVMValueRef depth
, LLVMValueRef stencil
,
3801 LLVMValueRef samplemask
)
3803 struct ac_export_args args
;
3805 ac_export_mrt_z(&ctx
->ac
, depth
, stencil
, samplemask
, &args
);
3807 ac_build_export(&ctx
->ac
, &args
);
3811 handle_fs_outputs_post(struct radv_shader_context
*ctx
)
3814 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
3815 struct ac_export_args color_args
[8];
3817 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3818 LLVMValueRef values
[4];
3820 if (!(ctx
->output_mask
& (1ull << i
)))
3823 if (i
< FRAG_RESULT_DATA0
)
3826 for (unsigned j
= 0; j
< 4; j
++)
3827 values
[j
] = ac_to_float(&ctx
->ac
,
3828 radv_load_output(ctx
, i
, j
));
3830 bool ret
= si_export_mrt_color(ctx
, values
,
3831 i
- FRAG_RESULT_DATA0
,
3832 &color_args
[index
]);
3837 /* Process depth, stencil, samplemask. */
3838 if (ctx
->shader_info
->ps
.writes_z
) {
3839 depth
= ac_to_float(&ctx
->ac
,
3840 radv_load_output(ctx
, FRAG_RESULT_DEPTH
, 0));
3842 if (ctx
->shader_info
->ps
.writes_stencil
) {
3843 stencil
= ac_to_float(&ctx
->ac
,
3844 radv_load_output(ctx
, FRAG_RESULT_STENCIL
, 0));
3846 if (ctx
->shader_info
->ps
.writes_sample_mask
) {
3847 samplemask
= ac_to_float(&ctx
->ac
,
3848 radv_load_output(ctx
, FRAG_RESULT_SAMPLE_MASK
, 0));
3851 /* Set the DONE bit on last non-null color export only if Z isn't
3855 !ctx
->shader_info
->ps
.writes_z
&&
3856 !ctx
->shader_info
->ps
.writes_stencil
&&
3857 !ctx
->shader_info
->ps
.writes_sample_mask
) {
3858 unsigned last
= index
- 1;
3860 color_args
[last
].valid_mask
= 1; /* whether the EXEC mask is valid */
3861 color_args
[last
].done
= 1; /* DONE bit */
3864 /* Export PS outputs. */
3865 for (unsigned i
= 0; i
< index
; i
++)
3866 ac_build_export(&ctx
->ac
, &color_args
[i
]);
3868 if (depth
|| stencil
|| samplemask
)
3869 radv_export_mrt_z(ctx
, depth
, stencil
, samplemask
);
3871 ac_build_export_null(&ctx
->ac
);
3875 emit_gs_epilogue(struct radv_shader_context
*ctx
)
3877 if (ctx
->options
->key
.vs_common_out
.as_ngg
) {
3878 gfx10_ngg_gs_emit_epilogue_1(ctx
);
3882 if (ctx
->ac
.chip_class
>= GFX10
)
3883 LLVMBuildFence(ctx
->ac
.builder
, LLVMAtomicOrderingRelease
, false, "");
3885 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
, ctx
->gs_wave_id
);
3889 handle_shader_outputs_post(struct ac_shader_abi
*abi
, unsigned max_outputs
,
3890 LLVMValueRef
*addrs
)
3892 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
3894 switch (ctx
->stage
) {
3895 case MESA_SHADER_VERTEX
:
3896 if (ctx
->options
->key
.vs_common_out
.as_ls
)
3897 handle_ls_outputs_post(ctx
);
3898 else if (ctx
->options
->key
.vs_common_out
.as_es
)
3899 handle_es_outputs_post(ctx
, &ctx
->shader_info
->vs
.es_info
);
3900 else if (ctx
->options
->key
.vs_common_out
.as_ngg
)
3901 break; /* handled outside of the shader body */
3903 handle_vs_outputs_post(ctx
, ctx
->options
->key
.vs_common_out
.export_prim_id
,
3904 ctx
->options
->key
.vs_common_out
.export_clip_dists
,
3905 &ctx
->shader_info
->vs
.outinfo
);
3907 case MESA_SHADER_FRAGMENT
:
3908 handle_fs_outputs_post(ctx
);
3910 case MESA_SHADER_GEOMETRY
:
3911 emit_gs_epilogue(ctx
);
3913 case MESA_SHADER_TESS_CTRL
:
3914 handle_tcs_outputs_post(ctx
);
3916 case MESA_SHADER_TESS_EVAL
:
3917 if (ctx
->options
->key
.vs_common_out
.as_es
)
3918 handle_es_outputs_post(ctx
, &ctx
->shader_info
->tes
.es_info
);
3919 else if (ctx
->options
->key
.vs_common_out
.as_ngg
)
3920 break; /* handled outside of the shader body */
3922 handle_vs_outputs_post(ctx
, ctx
->options
->key
.vs_common_out
.export_prim_id
,
3923 ctx
->options
->key
.vs_common_out
.export_clip_dists
,
3924 &ctx
->shader_info
->tes
.outinfo
);
3931 static void ac_llvm_finalize_module(struct radv_shader_context
*ctx
,
3932 LLVMPassManagerRef passmgr
,
3933 const struct radv_nir_compiler_options
*options
)
3935 LLVMRunPassManager(passmgr
, ctx
->ac
.module
);
3936 LLVMDisposeBuilder(ctx
->ac
.builder
);
3938 ac_llvm_context_dispose(&ctx
->ac
);
3942 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context
*ctx
)
3944 struct radv_vs_output_info
*outinfo
;
3946 switch (ctx
->stage
) {
3947 case MESA_SHADER_FRAGMENT
:
3948 case MESA_SHADER_COMPUTE
:
3949 case MESA_SHADER_TESS_CTRL
:
3950 case MESA_SHADER_GEOMETRY
:
3952 case MESA_SHADER_VERTEX
:
3953 if (ctx
->options
->key
.vs_common_out
.as_ls
||
3954 ctx
->options
->key
.vs_common_out
.as_es
)
3956 outinfo
= &ctx
->shader_info
->vs
.outinfo
;
3958 case MESA_SHADER_TESS_EVAL
:
3959 if (ctx
->options
->key
.vs_common_out
.as_es
)
3961 outinfo
= &ctx
->shader_info
->tes
.outinfo
;
3964 unreachable("Unhandled shader type");
3967 ac_optimize_vs_outputs(&ctx
->ac
,
3969 outinfo
->vs_output_param_offset
,
3971 &outinfo
->param_exports
);
3975 ac_setup_rings(struct radv_shader_context
*ctx
)
3977 if (ctx
->options
->chip_class
<= GFX8
&&
3978 (ctx
->stage
== MESA_SHADER_GEOMETRY
||
3979 ctx
->options
->key
.vs_common_out
.as_es
|| ctx
->options
->key
.vs_common_out
.as_es
)) {
3980 unsigned ring
= ctx
->stage
== MESA_SHADER_GEOMETRY
? RING_ESGS_GS
3982 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, ring
, false);
3984 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
,
3989 if (ctx
->is_gs_copy_shader
) {
3991 ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
,
3992 LLVMConstInt(ctx
->ac
.i32
,
3993 RING_GSVS_VS
, false));
3996 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
3997 /* The conceptual layout of the GSVS ring is
3998 * v0c0 .. vLv0 v0c1 .. vLc1 ..
3999 * but the real memory layout is swizzled across
4001 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
4003 * Override the buffer descriptor accordingly.
4005 LLVMTypeRef v2i64
= LLVMVectorType(ctx
->ac
.i64
, 2);
4006 uint64_t stream_offset
= 0;
4007 unsigned num_records
= ctx
->ac
.wave_size
;
4008 LLVMValueRef base_ring
;
4011 ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
,
4012 LLVMConstInt(ctx
->ac
.i32
,
4013 RING_GSVS_GS
, false));
4015 for (unsigned stream
= 0; stream
< 4; stream
++) {
4016 unsigned num_components
, stride
;
4017 LLVMValueRef ring
, tmp
;
4020 ctx
->shader_info
->gs
.num_stream_output_components
[stream
];
4022 if (!num_components
)
4025 stride
= 4 * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
4027 /* Limit on the stride field for <= GFX7. */
4028 assert(stride
< (1 << 14));
4030 ring
= LLVMBuildBitCast(ctx
->ac
.builder
,
4031 base_ring
, v2i64
, "");
4032 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
,
4033 ring
, ctx
->ac
.i32_0
, "");
4034 tmp
= LLVMBuildAdd(ctx
->ac
.builder
, tmp
,
4035 LLVMConstInt(ctx
->ac
.i64
,
4036 stream_offset
, 0), "");
4037 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
,
4038 ring
, tmp
, ctx
->ac
.i32_0
, "");
4040 stream_offset
+= stride
* ctx
->ac
.wave_size
;
4042 ring
= LLVMBuildBitCast(ctx
->ac
.builder
, ring
,
4045 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
, ring
,
4047 tmp
= LLVMBuildOr(ctx
->ac
.builder
, tmp
,
4048 LLVMConstInt(ctx
->ac
.i32
,
4049 S_008F04_STRIDE(stride
), false), "");
4050 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ring
, tmp
,
4053 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ring
,
4054 LLVMConstInt(ctx
->ac
.i32
,
4055 num_records
, false),
4056 LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
4058 ctx
->gsvs_ring
[stream
] = ring
;
4062 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
4063 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
4064 ctx
->hs_ring_tess_offchip
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_OFFCHIP
, false));
4065 ctx
->hs_ring_tess_factor
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_FACTOR
, false));
4070 radv_nir_get_max_workgroup_size(enum chip_class chip_class
,
4071 gl_shader_stage stage
,
4072 const struct nir_shader
*nir
)
4074 const unsigned backup_sizes
[] = {chip_class
>= GFX9
? 128 : 64, 1, 1};
4075 return radv_get_max_workgroup_size(chip_class
, stage
, nir
? nir
->info
.cs
.local_size
: backup_sizes
);
4078 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
4079 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context
*ctx
)
4081 LLVMValueRef count
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 8, 8);
4082 LLVMValueRef hs_empty
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, count
,
4084 ctx
->abi
.instance_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->rel_auto_id
, ctx
->abi
.instance_id
, "");
4085 ctx
->rel_auto_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_rel_ids
, ctx
->rel_auto_id
, "");
4086 ctx
->abi
.vertex_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_patch_id
, ctx
->abi
.vertex_id
, "");
4089 static void prepare_gs_input_vgprs(struct radv_shader_context
*ctx
)
4091 for(int i
= 5; i
>= 0; --i
) {
4092 ctx
->gs_vtx_offset
[i
] = ac_unpack_param(&ctx
->ac
, ctx
->gs_vtx_offset
[i
& ~1],
4096 ctx
->gs_wave_id
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 16, 8);
4099 /* Ensure that the esgs ring is declared.
4101 * We declare it with 64KB alignment as a hint that the
4102 * pointer value will always be 0.
4104 static void declare_esgs_ring(struct radv_shader_context
*ctx
)
4109 assert(!LLVMGetNamedGlobal(ctx
->ac
.module
, "esgs_ring"));
4111 ctx
->esgs_ring
= LLVMAddGlobalInAddressSpace(
4112 ctx
->ac
.module
, LLVMArrayType(ctx
->ac
.i32
, 0),
4115 LLVMSetLinkage(ctx
->esgs_ring
, LLVMExternalLinkage
);
4116 LLVMSetAlignment(ctx
->esgs_ring
, 64 * 1024);
4120 LLVMModuleRef
ac_translate_nir_to_llvm(struct ac_llvm_compiler
*ac_llvm
,
4121 struct nir_shader
*const *shaders
,
4123 struct radv_shader_info
*shader_info
,
4124 const struct radv_nir_compiler_options
*options
)
4126 struct radv_shader_context ctx
= {0};
4128 ctx
.options
= options
;
4129 ctx
.shader_info
= shader_info
;
4131 enum ac_float_mode float_mode
=
4132 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
4133 AC_FLOAT_MODE_DEFAULT
;
4135 ac_llvm_context_init(&ctx
.ac
, ac_llvm
, options
->chip_class
,
4136 options
->family
, float_mode
, options
->wave_size
, 64);
4137 ctx
.context
= ctx
.ac
.context
;
4139 radv_nir_shader_info_init(shader_info
);
4141 for(int i
= 0; i
< shader_count
; ++i
)
4142 radv_nir_shader_info_pass(shaders
[i
], options
, shader_info
);
4144 for (i
= 0; i
< MAX_SETS
; i
++)
4145 shader_info
->user_sgprs_locs
.descriptor_sets
[i
].sgpr_idx
= -1;
4146 for (i
= 0; i
< AC_UD_MAX_UD
; i
++)
4147 shader_info
->user_sgprs_locs
.shader_data
[i
].sgpr_idx
= -1;
4149 ctx
.max_workgroup_size
= 0;
4150 for (int i
= 0; i
< shader_count
; ++i
) {
4151 ctx
.max_workgroup_size
= MAX2(ctx
.max_workgroup_size
,
4152 radv_nir_get_max_workgroup_size(ctx
.options
->chip_class
,
4153 shaders
[i
]->info
.stage
,
4157 if (ctx
.ac
.chip_class
>= GFX10
) {
4158 if (is_pre_gs_stage(shaders
[0]->info
.stage
) &&
4159 options
->key
.vs_common_out
.as_ngg
) {
4160 ctx
.max_workgroup_size
= 128;
4164 create_function(&ctx
, shaders
[shader_count
- 1]->info
.stage
, shader_count
>= 2,
4165 shader_count
>= 2 ? shaders
[shader_count
- 2]->info
.stage
: MESA_SHADER_VERTEX
);
4167 ctx
.abi
.inputs
= &ctx
.inputs
[0];
4168 ctx
.abi
.emit_outputs
= handle_shader_outputs_post
;
4169 ctx
.abi
.emit_vertex
= visit_emit_vertex
;
4170 ctx
.abi
.load_ubo
= radv_load_ubo
;
4171 ctx
.abi
.load_ssbo
= radv_load_ssbo
;
4172 ctx
.abi
.load_sampler_desc
= radv_get_sampler_desc
;
4173 ctx
.abi
.load_resource
= radv_load_resource
;
4174 ctx
.abi
.clamp_shadow_reference
= false;
4175 ctx
.abi
.robust_buffer_access
= options
->robust_buffer_access
;
4177 bool is_ngg
= is_pre_gs_stage(shaders
[0]->info
.stage
) && ctx
.options
->key
.vs_common_out
.as_ngg
;
4178 if (shader_count
>= 2 || is_ngg
)
4179 ac_init_exec_full_mask(&ctx
.ac
);
4181 if (options
->has_ls_vgpr_init_bug
&&
4182 shaders
[shader_count
- 1]->info
.stage
== MESA_SHADER_TESS_CTRL
)
4183 ac_nir_fixup_ls_hs_input_vgprs(&ctx
);
4185 for(int i
= 0; i
< shader_count
; ++i
) {
4186 ctx
.stage
= shaders
[i
]->info
.stage
;
4187 ctx
.shader
= shaders
[i
];
4188 ctx
.output_mask
= 0;
4190 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
4191 for (int i
= 0; i
< 4; i
++) {
4192 ctx
.gs_next_vertex
[i
] =
4193 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
4195 if (ctx
.options
->key
.vs_common_out
.as_ngg
) {
4196 for (unsigned i
= 0; i
< 4; ++i
) {
4197 ctx
.gs_curprim_verts
[i
] =
4198 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
4199 ctx
.gs_generated_prims
[i
] =
4200 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
4203 /* TODO: streamout */
4205 LLVMTypeRef ai32
= LLVMArrayType(ctx
.ac
.i32
, 8);
4206 ctx
.gs_ngg_scratch
=
4207 LLVMAddGlobalInAddressSpace(ctx
.ac
.module
,
4208 ai32
, "ngg_scratch", AC_ADDR_SPACE_LDS
);
4209 LLVMSetInitializer(ctx
.gs_ngg_scratch
, LLVMGetUndef(ai32
));
4210 LLVMSetAlignment(ctx
.gs_ngg_scratch
, 4);
4212 ctx
.gs_ngg_emit
= LLVMBuildIntToPtr(ctx
.ac
.builder
, ctx
.ac
.i32_0
,
4213 LLVMPointerType(LLVMArrayType(ctx
.ac
.i32
, 0), AC_ADDR_SPACE_LDS
),
4217 ctx
.abi
.load_inputs
= load_gs_input
;
4218 ctx
.abi
.emit_primitive
= visit_end_primitive
;
4219 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4220 ctx
.abi
.load_tess_varyings
= load_tcs_varyings
;
4221 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
4222 ctx
.abi
.store_tcs_outputs
= store_tcs_output
;
4223 if (shader_count
== 1)
4224 ctx
.tcs_num_inputs
= ctx
.options
->key
.tcs
.num_inputs
;
4226 ctx
.tcs_num_inputs
= util_last_bit64(shader_info
->vs
.ls_outputs_written
);
4227 ctx
.tcs_num_patches
= get_tcs_num_patches(&ctx
);
4228 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4229 ctx
.abi
.load_tess_varyings
= load_tes_input
;
4230 ctx
.abi
.load_tess_coord
= load_tess_coord
;
4231 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
4232 ctx
.tcs_num_patches
= ctx
.options
->key
.tes
.num_patches
;
4233 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
) {
4234 ctx
.abi
.load_base_vertex
= radv_load_base_vertex
;
4235 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
) {
4236 ctx
.abi
.load_sample_position
= load_sample_position
;
4237 ctx
.abi
.load_sample_mask_in
= load_sample_mask_in
;
4238 ctx
.abi
.emit_kill
= radv_emit_kill
;
4241 if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
&&
4242 ctx
.options
->key
.vs_common_out
.as_ngg
&&
4243 ctx
.options
->key
.vs_common_out
.export_prim_id
) {
4244 declare_esgs_ring(&ctx
);
4247 bool nested_barrier
= false;
4250 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
&&
4251 ctx
.options
->key
.vs_common_out
.as_ngg
) {
4252 gfx10_ngg_gs_emit_prologue(&ctx
);
4253 nested_barrier
= false;
4255 nested_barrier
= true;
4259 if (nested_barrier
) {
4260 /* Execute a barrier before the second shader in
4263 * Execute the barrier inside the conditional block,
4264 * so that empty waves can jump directly to s_endpgm,
4265 * which will also signal the barrier.
4267 * This is possible in gfx9, because an empty wave
4268 * for the second shader does not participate in
4269 * the epilogue. With NGG, empty waves may still
4270 * be required to export data (e.g. GS output vertices),
4271 * so we cannot let them exit early.
4273 * If the shader is TCS and the TCS epilog is present
4274 * and contains a barrier, it will wait there and then
4277 ac_emit_barrier(&ctx
.ac
, ctx
.stage
);
4280 nir_foreach_variable(variable
, &shaders
[i
]->outputs
)
4281 scan_shader_output_decl(&ctx
, variable
, shaders
[i
], shaders
[i
]->info
.stage
);
4283 ac_setup_rings(&ctx
);
4285 LLVMBasicBlockRef merge_block
;
4286 if (shader_count
>= 2 || is_ngg
) {
4287 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
4288 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
4289 merge_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
4291 LLVMValueRef count
= ac_unpack_param(&ctx
.ac
, ctx
.merged_wave_info
, 8 * i
, 8);
4292 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
.ac
);
4293 LLVMValueRef cond
= LLVMBuildICmp(ctx
.ac
.builder
, LLVMIntULT
,
4294 thread_id
, count
, "");
4295 LLVMBuildCondBr(ctx
.ac
.builder
, cond
, then_block
, merge_block
);
4297 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, then_block
);
4300 if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
)
4301 prepare_interp_optimize(&ctx
, shaders
[i
]);
4302 else if(shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
)
4303 handle_vs_inputs(&ctx
, shaders
[i
]);
4304 else if(shader_count
>= 2 && shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
)
4305 prepare_gs_input_vgprs(&ctx
);
4307 ac_nir_translate(&ctx
.ac
, &ctx
.abi
, shaders
[i
]);
4309 if (shader_count
>= 2 || is_ngg
) {
4310 LLVMBuildBr(ctx
.ac
.builder
, merge_block
);
4311 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, merge_block
);
4314 /* This needs to be outside the if wrapping the shader body, as sometimes
4315 * the HW generates waves with 0 es/vs threads. */
4316 if (is_pre_gs_stage(shaders
[i
]->info
.stage
) &&
4317 ctx
.options
->key
.vs_common_out
.as_ngg
&&
4318 i
== shader_count
- 1) {
4319 handle_ngg_outputs_post(&ctx
);
4320 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
&&
4321 ctx
.options
->key
.vs_common_out
.as_ngg
) {
4322 gfx10_ngg_gs_emit_epilogue_2(&ctx
);
4325 if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4326 shader_info
->tcs
.num_patches
= ctx
.tcs_num_patches
;
4327 shader_info
->tcs
.lds_size
= calculate_tess_lds_size(&ctx
);
4331 LLVMBuildRetVoid(ctx
.ac
.builder
);
4333 if (options
->dump_preoptir
) {
4334 fprintf(stderr
, "%s LLVM IR:\n\n",
4335 radv_get_shader_name(shader_info
,
4336 shaders
[shader_count
- 1]->info
.stage
));
4337 ac_dump_module(ctx
.ac
.module
);
4338 fprintf(stderr
, "\n");
4341 ac_llvm_finalize_module(&ctx
, ac_llvm
->passmgr
, options
);
4343 if (shader_count
== 1)
4344 ac_nir_eliminate_const_vs_outputs(&ctx
);
4346 if (options
->dump_shader
) {
4347 ctx
.shader_info
->private_mem_vgprs
=
4348 ac_count_scratch_private_memory(ctx
.main_function
);
4351 return ctx
.ac
.module
;
4354 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di
, void *context
)
4356 unsigned *retval
= (unsigned *)context
;
4357 LLVMDiagnosticSeverity severity
= LLVMGetDiagInfoSeverity(di
);
4358 char *description
= LLVMGetDiagInfoDescription(di
);
4360 if (severity
== LLVMDSError
) {
4362 fprintf(stderr
, "LLVM triggered Diagnostic Handler: %s\n",
4366 LLVMDisposeMessage(description
);
4369 static unsigned radv_llvm_compile(LLVMModuleRef M
,
4370 char **pelf_buffer
, size_t *pelf_size
,
4371 struct ac_llvm_compiler
*ac_llvm
)
4373 unsigned retval
= 0;
4374 LLVMContextRef llvm_ctx
;
4376 /* Setup Diagnostic Handler*/
4377 llvm_ctx
= LLVMGetModuleContext(M
);
4379 LLVMContextSetDiagnosticHandler(llvm_ctx
, ac_diagnostic_handler
,
4383 if (!radv_compile_to_elf(ac_llvm
, M
, pelf_buffer
, pelf_size
))
4388 static void ac_compile_llvm_module(struct ac_llvm_compiler
*ac_llvm
,
4389 LLVMModuleRef llvm_module
,
4390 struct radv_shader_binary
**rbinary
,
4391 gl_shader_stage stage
,
4393 const struct radv_nir_compiler_options
*options
)
4395 char *elf_buffer
= NULL
;
4396 size_t elf_size
= 0;
4397 char *llvm_ir_string
= NULL
;
4399 if (options
->dump_shader
) {
4400 fprintf(stderr
, "%s LLVM IR:\n\n", name
);
4401 ac_dump_module(llvm_module
);
4402 fprintf(stderr
, "\n");
4405 if (options
->record_llvm_ir
) {
4406 char *llvm_ir
= LLVMPrintModuleToString(llvm_module
);
4407 llvm_ir_string
= strdup(llvm_ir
);
4408 LLVMDisposeMessage(llvm_ir
);
4411 int v
= radv_llvm_compile(llvm_module
, &elf_buffer
, &elf_size
, ac_llvm
);
4413 fprintf(stderr
, "compile failed\n");
4416 LLVMContextRef ctx
= LLVMGetModuleContext(llvm_module
);
4417 LLVMDisposeModule(llvm_module
);
4418 LLVMContextDispose(ctx
);
4420 size_t llvm_ir_size
= llvm_ir_string
? strlen(llvm_ir_string
) : 0;
4421 size_t alloc_size
= sizeof(struct radv_shader_binary_rtld
) + elf_size
+ llvm_ir_size
+ 1;
4422 struct radv_shader_binary_rtld
*rbin
= calloc(1, alloc_size
);
4423 memcpy(rbin
->data
, elf_buffer
, elf_size
);
4425 memcpy(rbin
->data
+ elf_size
, llvm_ir_string
, llvm_ir_size
+ 1);
4427 rbin
->base
.type
= RADV_BINARY_TYPE_RTLD
;
4428 rbin
->base
.stage
= stage
;
4429 rbin
->base
.total_size
= alloc_size
;
4430 rbin
->elf_size
= elf_size
;
4431 rbin
->llvm_ir_size
= llvm_ir_size
;
4432 *rbinary
= &rbin
->base
;
4434 free(llvm_ir_string
);
4439 radv_compile_nir_shader(struct ac_llvm_compiler
*ac_llvm
,
4440 struct radv_shader_binary
**rbinary
,
4441 struct radv_shader_info
*shader_info
,
4442 struct nir_shader
*const *nir
,
4444 const struct radv_nir_compiler_options
*options
)
4447 LLVMModuleRef llvm_module
;
4449 llvm_module
= ac_translate_nir_to_llvm(ac_llvm
, nir
, nir_count
, shader_info
,
4452 ac_compile_llvm_module(ac_llvm
, llvm_module
, rbinary
,
4453 nir
[nir_count
- 1]->info
.stage
,
4454 radv_get_shader_name(shader_info
,
4455 nir
[nir_count
- 1]->info
.stage
),
4458 /* Determine the ES type (VS or TES) for the GS on GFX9. */
4459 if (options
->chip_class
>= GFX9
) {
4460 if (nir_count
== 2 &&
4461 nir
[1]->info
.stage
== MESA_SHADER_GEOMETRY
) {
4462 shader_info
->gs
.es_type
= nir
[0]->info
.stage
;
4465 shader_info
->wave_size
= options
->wave_size
;
4469 ac_gs_copy_shader_emit(struct radv_shader_context
*ctx
)
4471 LLVMValueRef vtx_offset
=
4472 LLVMBuildMul(ctx
->ac
.builder
, ctx
->abi
.vertex_id
,
4473 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
4474 LLVMValueRef stream_id
;
4476 /* Fetch the vertex stream ID. */
4477 if (ctx
->shader_info
->so
.num_outputs
) {
4479 ac_unpack_param(&ctx
->ac
, ctx
->streamout_config
, 24, 2);
4481 stream_id
= ctx
->ac
.i32_0
;
4484 LLVMBasicBlockRef end_bb
;
4485 LLVMValueRef switch_inst
;
4487 end_bb
= LLVMAppendBasicBlockInContext(ctx
->ac
.context
,
4488 ctx
->main_function
, "end");
4489 switch_inst
= LLVMBuildSwitch(ctx
->ac
.builder
, stream_id
, end_bb
, 4);
4491 for (unsigned stream
= 0; stream
< 4; stream
++) {
4492 unsigned num_components
=
4493 ctx
->shader_info
->gs
.num_stream_output_components
[stream
];
4494 LLVMBasicBlockRef bb
;
4497 if (!num_components
)
4500 if (stream
> 0 && !ctx
->shader_info
->so
.num_outputs
)
4503 bb
= LLVMInsertBasicBlockInContext(ctx
->ac
.context
, end_bb
, "out");
4504 LLVMAddCase(switch_inst
, LLVMConstInt(ctx
->ac
.i32
, stream
, 0), bb
);
4505 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, bb
);
4508 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
4509 unsigned output_usage_mask
=
4510 ctx
->shader_info
->gs
.output_usage_mask
[i
];
4511 unsigned output_stream
=
4512 ctx
->shader_info
->gs
.output_streams
[i
];
4513 int length
= util_last_bit(output_usage_mask
);
4515 if (!(ctx
->output_mask
& (1ull << i
)) ||
4516 output_stream
!= stream
)
4519 for (unsigned j
= 0; j
< length
; j
++) {
4520 LLVMValueRef value
, soffset
;
4522 if (!(output_usage_mask
& (1 << j
)))
4525 soffset
= LLVMConstInt(ctx
->ac
.i32
,
4527 ctx
->shader
->info
.gs
.vertices_out
* 16 * 4, false);
4531 value
= ac_build_buffer_load(&ctx
->ac
,
4534 vtx_offset
, soffset
,
4535 0, ac_glc
| ac_slc
, true, false);
4537 LLVMTypeRef type
= LLVMGetAllocatedType(ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
4538 if (ac_get_type_size(type
) == 2) {
4539 value
= LLVMBuildBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
4540 value
= LLVMBuildTrunc(ctx
->ac
.builder
, value
, ctx
->ac
.i16
, "");
4543 LLVMBuildStore(ctx
->ac
.builder
,
4544 ac_to_float(&ctx
->ac
, value
), ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
4548 if (ctx
->shader_info
->so
.num_outputs
)
4549 radv_emit_streamout(ctx
, stream
);
4552 handle_vs_outputs_post(ctx
, false, true,
4553 &ctx
->shader_info
->vs
.outinfo
);
4556 LLVMBuildBr(ctx
->ac
.builder
, end_bb
);
4559 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, end_bb
);
4563 radv_compile_gs_copy_shader(struct ac_llvm_compiler
*ac_llvm
,
4564 struct nir_shader
*geom_shader
,
4565 struct radv_shader_binary
**rbinary
,
4566 struct radv_shader_info
*shader_info
,
4567 const struct radv_nir_compiler_options
*options
)
4569 struct radv_shader_context ctx
= {0};
4570 ctx
.options
= options
;
4571 ctx
.shader_info
= shader_info
;
4573 enum ac_float_mode float_mode
=
4574 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
4575 AC_FLOAT_MODE_DEFAULT
;
4577 ac_llvm_context_init(&ctx
.ac
, ac_llvm
, options
->chip_class
,
4578 options
->family
, float_mode
, 64, 64);
4579 ctx
.context
= ctx
.ac
.context
;
4581 ctx
.is_gs_copy_shader
= true;
4582 ctx
.stage
= MESA_SHADER_VERTEX
;
4583 ctx
.shader
= geom_shader
;
4585 radv_nir_shader_info_pass(geom_shader
, options
, shader_info
);
4587 create_function(&ctx
, MESA_SHADER_VERTEX
, false, MESA_SHADER_VERTEX
);
4589 ac_setup_rings(&ctx
);
4591 nir_foreach_variable(variable
, &geom_shader
->outputs
) {
4592 scan_shader_output_decl(&ctx
, variable
, geom_shader
, MESA_SHADER_VERTEX
);
4593 ac_handle_shader_output_decl(&ctx
.ac
, &ctx
.abi
, geom_shader
,
4594 variable
, MESA_SHADER_VERTEX
);
4597 ac_gs_copy_shader_emit(&ctx
);
4599 LLVMBuildRetVoid(ctx
.ac
.builder
);
4601 ac_llvm_finalize_module(&ctx
, ac_llvm
->passmgr
, options
);
4603 ac_compile_llvm_module(ac_llvm
, ctx
.ac
.module
, rbinary
,
4604 MESA_SHADER_VERTEX
, "GS Copy Shader", options
);
4605 (*rbinary
)->is_gs_copy_shader
= true;