2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "radv_shader_helper.h"
33 #include <llvm-c/Core.h>
34 #include <llvm-c/TargetMachine.h>
35 #include <llvm-c/Transforms/Scalar.h>
36 #include <llvm-c/Transforms/Utils.h>
39 #include "ac_binary.h"
40 #include "ac_llvm_util.h"
41 #include "ac_llvm_build.h"
42 #include "ac_shader_abi.h"
43 #include "ac_shader_util.h"
44 #include "ac_exp_param.h"
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
48 struct radv_shader_context
{
49 struct ac_llvm_context ac
;
50 const struct radv_nir_compiler_options
*options
;
51 struct radv_shader_variant_info
*shader_info
;
52 struct ac_shader_abi abi
;
54 unsigned max_workgroup_size
;
55 LLVMContextRef context
;
56 LLVMValueRef main_function
;
58 LLVMValueRef descriptor_sets
[MAX_SETS
];
59 LLVMValueRef ring_offsets
;
61 LLVMValueRef vertex_buffers
;
62 LLVMValueRef rel_auto_id
;
63 LLVMValueRef vs_prim_id
;
64 LLVMValueRef es2gs_offset
;
67 LLVMValueRef merged_wave_info
;
68 LLVMValueRef tess_factor_offset
;
69 LLVMValueRef tes_rel_patch_id
;
75 * - bits 0..10: ordered_wave_id
76 * - bits 12..20: number of vertices in group
77 * - bits 22..30: number of primitives in group
79 LLVMValueRef gs_tg_info
;
80 LLVMValueRef gs2vs_offset
;
81 LLVMValueRef gs_wave_id
;
82 LLVMValueRef gs_vtx_offset
[6];
84 LLVMValueRef esgs_ring
;
85 LLVMValueRef gsvs_ring
[4];
86 LLVMValueRef hs_ring_tess_offchip
;
87 LLVMValueRef hs_ring_tess_factor
;
90 LLVMValueRef streamout_buffers
;
91 LLVMValueRef streamout_write_idx
;
92 LLVMValueRef streamout_config
;
93 LLVMValueRef streamout_offset
[4];
95 gl_shader_stage stage
;
97 LLVMValueRef inputs
[RADEON_LLVM_MAX_INPUTS
* 4];
98 uint64_t float16_shaded_mask
;
101 uint64_t output_mask
;
103 bool is_gs_copy_shader
;
104 LLVMValueRef gs_next_vertex
[4];
105 LLVMValueRef gs_curprim_verts
[4];
106 LLVMValueRef gs_generated_prims
[4];
107 LLVMValueRef gs_ngg_emit
;
108 LLVMValueRef gs_ngg_scratch
;
109 unsigned gs_max_out_vertices
;
110 unsigned gs_output_prim
;
112 unsigned tes_primitive_mode
;
114 uint32_t tcs_patch_outputs_read
;
115 uint64_t tcs_outputs_read
;
116 uint32_t tcs_vertices_per_patch
;
117 uint32_t tcs_num_inputs
;
118 uint32_t tcs_num_patches
;
119 uint32_t max_gsvs_emit_size
;
120 uint32_t gsvs_vertex_size
;
122 LLVMValueRef vertexptr
; /* GFX10 only */
125 struct radv_shader_output_values
{
126 LLVMValueRef values
[4];
132 enum radeon_llvm_calling_convention
{
133 RADEON_LLVM_AMDGPU_VS
= 87,
134 RADEON_LLVM_AMDGPU_GS
= 88,
135 RADEON_LLVM_AMDGPU_PS
= 89,
136 RADEON_LLVM_AMDGPU_CS
= 90,
137 RADEON_LLVM_AMDGPU_HS
= 93,
140 static inline struct radv_shader_context
*
141 radv_shader_context_from_abi(struct ac_shader_abi
*abi
)
143 struct radv_shader_context
*ctx
= NULL
;
144 return container_of(abi
, ctx
, abi
);
147 struct ac_build_if_state
149 struct radv_shader_context
*ctx
;
150 LLVMValueRef condition
;
151 LLVMBasicBlockRef entry_block
;
152 LLVMBasicBlockRef true_block
;
153 LLVMBasicBlockRef false_block
;
154 LLVMBasicBlockRef merge_block
;
157 static LLVMBasicBlockRef
158 ac_build_insert_new_block(struct radv_shader_context
*ctx
, const char *name
)
160 LLVMBasicBlockRef current_block
;
161 LLVMBasicBlockRef next_block
;
162 LLVMBasicBlockRef new_block
;
164 /* get current basic block */
165 current_block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
167 /* chqeck if there's another block after this one */
168 next_block
= LLVMGetNextBasicBlock(current_block
);
170 /* insert the new block before the next block */
171 new_block
= LLVMInsertBasicBlockInContext(ctx
->context
, next_block
, name
);
174 /* append new block after current block */
175 LLVMValueRef function
= LLVMGetBasicBlockParent(current_block
);
176 new_block
= LLVMAppendBasicBlockInContext(ctx
->context
, function
, name
);
182 ac_nir_build_if(struct ac_build_if_state
*ifthen
,
183 struct radv_shader_context
*ctx
,
184 LLVMValueRef condition
)
186 LLVMBasicBlockRef block
= LLVMGetInsertBlock(ctx
->ac
.builder
);
188 memset(ifthen
, 0, sizeof *ifthen
);
190 ifthen
->condition
= condition
;
191 ifthen
->entry_block
= block
;
193 /* create endif/merge basic block for the phi functions */
194 ifthen
->merge_block
= ac_build_insert_new_block(ctx
, "endif-block");
196 /* create/insert true_block before merge_block */
198 LLVMInsertBasicBlockInContext(ctx
->context
,
202 /* successive code goes into the true block */
203 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, ifthen
->true_block
);
210 ac_nir_build_endif(struct ac_build_if_state
*ifthen
)
212 LLVMBuilderRef builder
= ifthen
->ctx
->ac
.builder
;
214 /* Insert branch to the merge block from current block */
215 LLVMBuildBr(builder
, ifthen
->merge_block
);
218 * Now patch in the various branch instructions.
221 /* Insert the conditional branch instruction at the end of entry_block */
222 LLVMPositionBuilderAtEnd(builder
, ifthen
->entry_block
);
223 if (ifthen
->false_block
) {
224 /* we have an else clause */
225 LLVMBuildCondBr(builder
, ifthen
->condition
,
226 ifthen
->true_block
, ifthen
->false_block
);
230 LLVMBuildCondBr(builder
, ifthen
->condition
,
231 ifthen
->true_block
, ifthen
->merge_block
);
234 /* Resume building code at end of the ifthen->merge_block */
235 LLVMPositionBuilderAtEnd(builder
, ifthen
->merge_block
);
239 static LLVMValueRef
get_rel_patch_id(struct radv_shader_context
*ctx
)
241 switch (ctx
->stage
) {
242 case MESA_SHADER_TESS_CTRL
:
243 return ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
244 case MESA_SHADER_TESS_EVAL
:
245 return ctx
->tes_rel_patch_id
;
248 unreachable("Illegal stage");
253 get_tcs_num_patches(struct radv_shader_context
*ctx
)
255 unsigned num_tcs_input_cp
= ctx
->options
->key
.tcs
.input_vertices
;
256 unsigned num_tcs_output_cp
= ctx
->tcs_vertices_per_patch
;
257 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
258 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
259 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
260 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.patch_outputs_written
);
261 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
262 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
263 uint32_t output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
264 unsigned num_patches
;
265 unsigned hardware_lds_size
;
267 /* Ensure that we only need one wave per SIMD so we don't need to check
268 * resource usage. Also ensures that the number of tcs in and out
269 * vertices per threadgroup are at most 256.
271 num_patches
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
) * 4;
272 /* Make sure that the data fits in LDS. This assumes the shaders only
273 * use LDS for the inputs and outputs.
275 hardware_lds_size
= 32768;
277 /* Looks like STONEY hangs if we use more than 32 KiB LDS in a single
278 * threadgroup, even though there is more than 32 KiB LDS.
280 * Test: dEQP-VK.tessellation.shader_input_output.barrier
282 if (ctx
->options
->chip_class
>= GFX7
&& ctx
->options
->family
!= CHIP_STONEY
)
283 hardware_lds_size
= 65536;
285 num_patches
= MIN2(num_patches
, hardware_lds_size
/ (input_patch_size
+ output_patch_size
));
286 /* Make sure the output data fits in the offchip buffer */
287 num_patches
= MIN2(num_patches
, (ctx
->options
->tess_offchip_block_dw_size
* 4) / output_patch_size
);
288 /* Not necessary for correctness, but improves performance. The
289 * specific value is taken from the proprietary driver.
291 num_patches
= MIN2(num_patches
, 40);
293 /* GFX6 bug workaround - limit LS-HS threadgroups to only one wave. */
294 if (ctx
->options
->chip_class
== GFX6
) {
295 unsigned one_wave
= ctx
->options
->wave_size
/ MAX2(num_tcs_input_cp
, num_tcs_output_cp
);
296 num_patches
= MIN2(num_patches
, one_wave
);
302 calculate_tess_lds_size(struct radv_shader_context
*ctx
)
304 unsigned num_tcs_input_cp
= ctx
->options
->key
.tcs
.input_vertices
;
305 unsigned num_tcs_output_cp
;
306 unsigned num_tcs_outputs
, num_tcs_patch_outputs
;
307 unsigned input_vertex_size
, output_vertex_size
;
308 unsigned input_patch_size
, output_patch_size
;
309 unsigned pervertex_output_patch_size
;
310 unsigned output_patch0_offset
;
311 unsigned num_patches
;
314 num_tcs_output_cp
= ctx
->tcs_vertices_per_patch
;
315 num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
316 num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.patch_outputs_written
);
318 input_vertex_size
= ctx
->tcs_num_inputs
* 16;
319 output_vertex_size
= num_tcs_outputs
* 16;
321 input_patch_size
= num_tcs_input_cp
* input_vertex_size
;
323 pervertex_output_patch_size
= num_tcs_output_cp
* output_vertex_size
;
324 output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
326 num_patches
= ctx
->tcs_num_patches
;
327 output_patch0_offset
= input_patch_size
* num_patches
;
329 lds_size
= output_patch0_offset
+ output_patch_size
* num_patches
;
333 /* Tessellation shaders pass outputs to the next shader using LDS.
335 * LS outputs = TCS inputs
336 * TCS outputs = TES inputs
339 * - TCS inputs for patch 0
340 * - TCS inputs for patch 1
341 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
343 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
344 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
345 * - TCS outputs for patch 1
346 * - Per-patch TCS outputs for patch 1
347 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
348 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
351 * All three shaders VS(LS), TCS, TES share the same LDS space.
354 get_tcs_in_patch_stride(struct radv_shader_context
*ctx
)
356 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
357 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
358 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
360 input_patch_size
/= 4;
361 return LLVMConstInt(ctx
->ac
.i32
, input_patch_size
, false);
365 get_tcs_out_patch_stride(struct radv_shader_context
*ctx
)
367 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
368 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.patch_outputs_written
);
369 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
370 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
371 uint32_t output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
372 output_patch_size
/= 4;
373 return LLVMConstInt(ctx
->ac
.i32
, output_patch_size
, false);
377 get_tcs_out_vertex_stride(struct radv_shader_context
*ctx
)
379 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
380 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
381 output_vertex_size
/= 4;
382 return LLVMConstInt(ctx
->ac
.i32
, output_vertex_size
, false);
386 get_tcs_out_patch0_offset(struct radv_shader_context
*ctx
)
388 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
389 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
390 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
391 uint32_t output_patch0_offset
= input_patch_size
;
392 unsigned num_patches
= ctx
->tcs_num_patches
;
394 output_patch0_offset
*= num_patches
;
395 output_patch0_offset
/= 4;
396 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
400 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context
*ctx
)
402 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
403 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
404 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
405 uint32_t output_patch0_offset
= input_patch_size
;
407 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
408 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
409 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
410 unsigned num_patches
= ctx
->tcs_num_patches
;
412 output_patch0_offset
*= num_patches
;
413 output_patch0_offset
+= pervertex_output_patch_size
;
414 output_patch0_offset
/= 4;
415 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
419 get_tcs_in_current_patch_offset(struct radv_shader_context
*ctx
)
421 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
422 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
424 return LLVMBuildMul(ctx
->ac
.builder
, patch_stride
, rel_patch_id
, "");
428 get_tcs_out_current_patch_offset(struct radv_shader_context
*ctx
)
430 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
431 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
432 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
434 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
,
439 get_tcs_out_current_patch_data_offset(struct radv_shader_context
*ctx
)
441 LLVMValueRef patch0_patch_data_offset
=
442 get_tcs_out_patch0_patch_data_offset(ctx
);
443 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
444 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
446 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
,
447 patch0_patch_data_offset
);
452 LLVMTypeRef types
[MAX_ARGS
];
453 LLVMValueRef
*assign
[MAX_ARGS
];
456 uint8_t num_sgprs_used
;
457 uint8_t num_vgprs_used
;
460 enum ac_arg_regfile
{
466 add_arg(struct arg_info
*info
, enum ac_arg_regfile regfile
, LLVMTypeRef type
,
467 LLVMValueRef
*param_ptr
)
469 assert(info
->count
< MAX_ARGS
);
471 info
->assign
[info
->count
] = param_ptr
;
472 info
->types
[info
->count
] = type
;
475 if (regfile
== ARG_SGPR
) {
476 info
->num_sgprs_used
+= ac_get_type_size(type
) / 4;
479 assert(regfile
== ARG_VGPR
);
480 info
->num_vgprs_used
+= ac_get_type_size(type
) / 4;
484 static void assign_arguments(LLVMValueRef main_function
,
485 struct arg_info
*info
)
488 for (i
= 0; i
< info
->count
; i
++) {
490 *info
->assign
[i
] = LLVMGetParam(main_function
, i
);
495 create_llvm_function(LLVMContextRef ctx
, LLVMModuleRef module
,
496 LLVMBuilderRef builder
, LLVMTypeRef
*return_types
,
497 unsigned num_return_elems
,
498 struct arg_info
*args
,
499 unsigned max_workgroup_size
,
500 const struct radv_nir_compiler_options
*options
)
502 LLVMTypeRef main_function_type
, ret_type
;
503 LLVMBasicBlockRef main_function_body
;
505 if (num_return_elems
)
506 ret_type
= LLVMStructTypeInContext(ctx
, return_types
,
507 num_return_elems
, true);
509 ret_type
= LLVMVoidTypeInContext(ctx
);
511 /* Setup the function */
513 LLVMFunctionType(ret_type
, args
->types
, args
->count
, 0);
514 LLVMValueRef main_function
=
515 LLVMAddFunction(module
, "main", main_function_type
);
517 LLVMAppendBasicBlockInContext(ctx
, main_function
, "main_body");
518 LLVMPositionBuilderAtEnd(builder
, main_function_body
);
520 LLVMSetFunctionCallConv(main_function
, RADEON_LLVM_AMDGPU_CS
);
521 for (unsigned i
= 0; i
< args
->sgpr_count
; ++i
) {
522 LLVMValueRef P
= LLVMGetParam(main_function
, i
);
524 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_INREG
);
526 if (LLVMGetTypeKind(LLVMTypeOf(P
)) == LLVMPointerTypeKind
) {
527 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_NOALIAS
);
528 ac_add_attr_dereferenceable(P
, UINT64_MAX
);
532 if (options
->address32_hi
) {
533 ac_llvm_add_target_dep_function_attr(main_function
,
534 "amdgpu-32bit-address-high-bits",
535 options
->address32_hi
);
538 ac_llvm_set_workgroup_size(main_function
, max_workgroup_size
);
540 if (options
->unsafe_math
) {
541 /* These were copied from some LLVM test. */
542 LLVMAddTargetDependentFunctionAttr(main_function
,
543 "less-precise-fpmad",
545 LLVMAddTargetDependentFunctionAttr(main_function
,
548 LLVMAddTargetDependentFunctionAttr(main_function
,
551 LLVMAddTargetDependentFunctionAttr(main_function
,
554 LLVMAddTargetDependentFunctionAttr(main_function
,
555 "no-signed-zeros-fp-math",
558 return main_function
;
563 set_loc(struct radv_userdata_info
*ud_info
, uint8_t *sgpr_idx
,
566 ud_info
->sgpr_idx
= *sgpr_idx
;
567 ud_info
->num_sgprs
= num_sgprs
;
568 *sgpr_idx
+= num_sgprs
;
572 set_loc_shader(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
,
575 struct radv_userdata_info
*ud_info
=
576 &ctx
->shader_info
->user_sgprs_locs
.shader_data
[idx
];
579 set_loc(ud_info
, sgpr_idx
, num_sgprs
);
583 set_loc_shader_ptr(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
)
585 bool use_32bit_pointers
= idx
!= AC_UD_SCRATCH_RING_OFFSETS
;
587 set_loc_shader(ctx
, idx
, sgpr_idx
, use_32bit_pointers
? 1 : 2);
591 set_loc_desc(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
)
593 struct radv_userdata_locations
*locs
=
594 &ctx
->shader_info
->user_sgprs_locs
;
595 struct radv_userdata_info
*ud_info
= &locs
->descriptor_sets
[idx
];
598 set_loc(ud_info
, sgpr_idx
, 1);
600 locs
->descriptor_sets_enabled
|= 1 << idx
;
603 struct user_sgpr_info
{
604 bool need_ring_offsets
;
605 bool indirect_all_descriptor_sets
;
606 uint8_t remaining_sgprs
;
609 static bool needs_view_index_sgpr(struct radv_shader_context
*ctx
,
610 gl_shader_stage stage
)
613 case MESA_SHADER_VERTEX
:
614 if (ctx
->shader_info
->info
.needs_multiview_view_index
||
615 (!ctx
->options
->key
.vs_common_out
.as_es
&& !ctx
->options
->key
.vs_common_out
.as_ls
&& ctx
->options
->key
.has_multiview_view_index
))
618 case MESA_SHADER_TESS_EVAL
:
619 if (ctx
->shader_info
->info
.needs_multiview_view_index
|| (!ctx
->options
->key
.vs_common_out
.as_es
&& ctx
->options
->key
.has_multiview_view_index
))
622 case MESA_SHADER_GEOMETRY
:
623 case MESA_SHADER_TESS_CTRL
:
624 if (ctx
->shader_info
->info
.needs_multiview_view_index
)
634 count_vs_user_sgprs(struct radv_shader_context
*ctx
)
638 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
)
640 count
+= ctx
->shader_info
->info
.vs
.needs_draw_id
? 3 : 2;
645 static void allocate_inline_push_consts(struct radv_shader_context
*ctx
,
646 struct user_sgpr_info
*user_sgpr_info
)
648 uint8_t remaining_sgprs
= user_sgpr_info
->remaining_sgprs
;
650 /* Only supported if shaders use push constants. */
651 if (ctx
->shader_info
->info
.min_push_constant_used
== UINT8_MAX
)
654 /* Only supported if shaders don't have indirect push constants. */
655 if (ctx
->shader_info
->info
.has_indirect_push_constants
)
658 /* Only supported for 32-bit push constants. */
659 if (!ctx
->shader_info
->info
.has_only_32bit_push_constants
)
662 uint8_t num_push_consts
=
663 (ctx
->shader_info
->info
.max_push_constant_used
-
664 ctx
->shader_info
->info
.min_push_constant_used
) / 4;
666 /* Check if the number of user SGPRs is large enough. */
667 if (num_push_consts
< remaining_sgprs
) {
668 ctx
->shader_info
->info
.num_inline_push_consts
= num_push_consts
;
670 ctx
->shader_info
->info
.num_inline_push_consts
= remaining_sgprs
;
673 /* Clamp to the maximum number of allowed inlined push constants. */
674 if (ctx
->shader_info
->info
.num_inline_push_consts
> AC_MAX_INLINE_PUSH_CONSTS
)
675 ctx
->shader_info
->info
.num_inline_push_consts
= AC_MAX_INLINE_PUSH_CONSTS
;
677 if (ctx
->shader_info
->info
.num_inline_push_consts
== num_push_consts
&&
678 !ctx
->shader_info
->info
.loads_dynamic_offsets
) {
679 /* Disable the default push constants path if all constants are
680 * inlined and if shaders don't use dynamic descriptors.
682 ctx
->shader_info
->info
.loads_push_constants
= false;
685 ctx
->shader_info
->info
.base_inline_push_consts
=
686 ctx
->shader_info
->info
.min_push_constant_used
/ 4;
689 static void allocate_user_sgprs(struct radv_shader_context
*ctx
,
690 gl_shader_stage stage
,
691 bool has_previous_stage
,
692 gl_shader_stage previous_stage
,
693 bool needs_view_index
,
694 struct user_sgpr_info
*user_sgpr_info
)
696 uint8_t user_sgpr_count
= 0;
698 memset(user_sgpr_info
, 0, sizeof(struct user_sgpr_info
));
700 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
701 if (stage
== MESA_SHADER_GEOMETRY
||
702 stage
== MESA_SHADER_VERTEX
||
703 stage
== MESA_SHADER_TESS_CTRL
||
704 stage
== MESA_SHADER_TESS_EVAL
||
705 ctx
->is_gs_copy_shader
)
706 user_sgpr_info
->need_ring_offsets
= true;
708 if (stage
== MESA_SHADER_FRAGMENT
&&
709 ctx
->shader_info
->info
.ps
.needs_sample_positions
)
710 user_sgpr_info
->need_ring_offsets
= true;
712 /* 2 user sgprs will nearly always be allocated for scratch/rings */
713 if (ctx
->options
->supports_spill
|| user_sgpr_info
->need_ring_offsets
) {
714 user_sgpr_count
+= 2;
718 case MESA_SHADER_COMPUTE
:
719 if (ctx
->shader_info
->info
.cs
.uses_grid_size
)
720 user_sgpr_count
+= 3;
722 case MESA_SHADER_FRAGMENT
:
723 user_sgpr_count
+= ctx
->shader_info
->info
.ps
.needs_sample_positions
;
725 case MESA_SHADER_VERTEX
:
726 if (!ctx
->is_gs_copy_shader
)
727 user_sgpr_count
+= count_vs_user_sgprs(ctx
);
729 case MESA_SHADER_TESS_CTRL
:
730 if (has_previous_stage
) {
731 if (previous_stage
== MESA_SHADER_VERTEX
)
732 user_sgpr_count
+= count_vs_user_sgprs(ctx
);
735 case MESA_SHADER_TESS_EVAL
:
737 case MESA_SHADER_GEOMETRY
:
738 if (has_previous_stage
) {
739 if (previous_stage
== MESA_SHADER_VERTEX
) {
740 user_sgpr_count
+= count_vs_user_sgprs(ctx
);
748 if (needs_view_index
)
751 if (ctx
->shader_info
->info
.loads_push_constants
)
754 if (ctx
->streamout_buffers
)
757 uint32_t available_sgprs
= ctx
->options
->chip_class
>= GFX9
&& stage
!= MESA_SHADER_COMPUTE
? 32 : 16;
758 uint32_t remaining_sgprs
= available_sgprs
- user_sgpr_count
;
759 uint32_t num_desc_set
=
760 util_bitcount(ctx
->shader_info
->info
.desc_set_used_mask
);
762 if (remaining_sgprs
< num_desc_set
) {
763 user_sgpr_info
->indirect_all_descriptor_sets
= true;
764 user_sgpr_info
->remaining_sgprs
= remaining_sgprs
- 1;
766 user_sgpr_info
->remaining_sgprs
= remaining_sgprs
- num_desc_set
;
769 allocate_inline_push_consts(ctx
, user_sgpr_info
);
773 declare_global_input_sgprs(struct radv_shader_context
*ctx
,
774 const struct user_sgpr_info
*user_sgpr_info
,
775 struct arg_info
*args
,
776 LLVMValueRef
*desc_sets
)
778 LLVMTypeRef type
= ac_array_in_const32_addr_space(ctx
->ac
.i8
);
780 /* 1 for each descriptor set */
781 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
782 uint32_t mask
= ctx
->shader_info
->info
.desc_set_used_mask
;
785 int i
= u_bit_scan(&mask
);
787 add_arg(args
, ARG_SGPR
, type
, &ctx
->descriptor_sets
[i
]);
790 add_arg(args
, ARG_SGPR
, ac_array_in_const32_addr_space(type
),
794 if (ctx
->shader_info
->info
.loads_push_constants
) {
795 /* 1 for push constants and dynamic descriptors */
796 add_arg(args
, ARG_SGPR
, type
, &ctx
->abi
.push_constants
);
799 for (unsigned i
= 0; i
< ctx
->shader_info
->info
.num_inline_push_consts
; i
++) {
800 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
,
801 &ctx
->abi
.inline_push_consts
[i
]);
803 ctx
->abi
.num_inline_push_consts
= ctx
->shader_info
->info
.num_inline_push_consts
;
804 ctx
->abi
.base_inline_push_consts
= ctx
->shader_info
->info
.base_inline_push_consts
;
806 if (ctx
->shader_info
->info
.so
.num_outputs
) {
807 add_arg(args
, ARG_SGPR
,
808 ac_array_in_const32_addr_space(ctx
->ac
.v4i32
),
809 &ctx
->streamout_buffers
);
814 declare_vs_specific_input_sgprs(struct radv_shader_context
*ctx
,
815 gl_shader_stage stage
,
816 bool has_previous_stage
,
817 gl_shader_stage previous_stage
,
818 struct arg_info
*args
)
820 if (!ctx
->is_gs_copy_shader
&&
821 (stage
== MESA_SHADER_VERTEX
||
822 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
823 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
824 add_arg(args
, ARG_SGPR
,
825 ac_array_in_const32_addr_space(ctx
->ac
.v4i32
),
826 &ctx
->vertex_buffers
);
828 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.base_vertex
);
829 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.start_instance
);
830 if (ctx
->shader_info
->info
.vs
.needs_draw_id
) {
831 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.draw_id
);
837 declare_vs_input_vgprs(struct radv_shader_context
*ctx
, struct arg_info
*args
)
839 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.vertex_id
);
840 if (!ctx
->is_gs_copy_shader
) {
841 if (ctx
->options
->key
.vs_common_out
.as_ls
) {
842 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->rel_auto_id
);
843 if (ctx
->ac
.chip_class
>= GFX10
) {
844 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* user vgpr */
845 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
847 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
848 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* unused */
851 if (ctx
->ac
.chip_class
>= GFX10
) {
852 if (ctx
->options
->key
.vs_common_out
.as_ngg
) {
853 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* user vgpr */
854 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* user vgpr */
855 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
857 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* unused */
858 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->vs_prim_id
);
859 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
862 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
863 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->vs_prim_id
);
864 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* unused */
871 declare_streamout_sgprs(struct radv_shader_context
*ctx
, gl_shader_stage stage
,
872 struct arg_info
*args
)
876 /* Streamout SGPRs. */
877 if (ctx
->shader_info
->info
.so
.num_outputs
) {
878 assert(stage
== MESA_SHADER_VERTEX
||
879 stage
== MESA_SHADER_TESS_EVAL
);
881 if (stage
!= MESA_SHADER_TESS_EVAL
) {
882 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->streamout_config
);
884 args
->assign
[args
->count
- 1] = &ctx
->streamout_config
;
885 args
->types
[args
->count
- 1] = ctx
->ac
.i32
;
888 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->streamout_write_idx
);
891 /* A streamout buffer offset is loaded if the stride is non-zero. */
892 for (i
= 0; i
< 4; i
++) {
893 if (!ctx
->shader_info
->info
.so
.strides
[i
])
896 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->streamout_offset
[i
]);
901 declare_tes_input_vgprs(struct radv_shader_context
*ctx
, struct arg_info
*args
)
903 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_u
);
904 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_v
);
905 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->tes_rel_patch_id
);
906 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.tes_patch_id
);
910 set_global_input_locs(struct radv_shader_context
*ctx
,
911 const struct user_sgpr_info
*user_sgpr_info
,
912 LLVMValueRef desc_sets
, uint8_t *user_sgpr_idx
)
914 uint32_t mask
= ctx
->shader_info
->info
.desc_set_used_mask
;
916 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
918 int i
= u_bit_scan(&mask
);
920 set_loc_desc(ctx
, i
, user_sgpr_idx
);
923 set_loc_shader_ptr(ctx
, AC_UD_INDIRECT_DESCRIPTOR_SETS
,
927 int i
= u_bit_scan(&mask
);
929 ctx
->descriptor_sets
[i
] =
930 ac_build_load_to_sgpr(&ctx
->ac
, desc_sets
,
931 LLVMConstInt(ctx
->ac
.i32
, i
, false));
935 ctx
->shader_info
->need_indirect_descriptor_sets
= true;
938 if (ctx
->shader_info
->info
.loads_push_constants
) {
939 set_loc_shader_ptr(ctx
, AC_UD_PUSH_CONSTANTS
, user_sgpr_idx
);
942 if (ctx
->shader_info
->info
.num_inline_push_consts
) {
943 set_loc_shader(ctx
, AC_UD_INLINE_PUSH_CONSTANTS
, user_sgpr_idx
,
944 ctx
->shader_info
->info
.num_inline_push_consts
);
947 if (ctx
->streamout_buffers
) {
948 set_loc_shader_ptr(ctx
, AC_UD_STREAMOUT_BUFFERS
,
954 set_vs_specific_input_locs(struct radv_shader_context
*ctx
,
955 gl_shader_stage stage
, bool has_previous_stage
,
956 gl_shader_stage previous_stage
,
957 uint8_t *user_sgpr_idx
)
959 if (!ctx
->is_gs_copy_shader
&&
960 (stage
== MESA_SHADER_VERTEX
||
961 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
962 if (ctx
->shader_info
->info
.vs
.has_vertex_buffers
) {
963 set_loc_shader_ptr(ctx
, AC_UD_VS_VERTEX_BUFFERS
,
968 if (ctx
->shader_info
->info
.vs
.needs_draw_id
)
971 set_loc_shader(ctx
, AC_UD_VS_BASE_VERTEX_START_INSTANCE
,
972 user_sgpr_idx
, vs_num
);
976 static void set_llvm_calling_convention(LLVMValueRef func
,
977 gl_shader_stage stage
)
979 enum radeon_llvm_calling_convention calling_conv
;
982 case MESA_SHADER_VERTEX
:
983 case MESA_SHADER_TESS_EVAL
:
984 calling_conv
= RADEON_LLVM_AMDGPU_VS
;
986 case MESA_SHADER_GEOMETRY
:
987 calling_conv
= RADEON_LLVM_AMDGPU_GS
;
989 case MESA_SHADER_TESS_CTRL
:
990 calling_conv
= RADEON_LLVM_AMDGPU_HS
;
992 case MESA_SHADER_FRAGMENT
:
993 calling_conv
= RADEON_LLVM_AMDGPU_PS
;
995 case MESA_SHADER_COMPUTE
:
996 calling_conv
= RADEON_LLVM_AMDGPU_CS
;
999 unreachable("Unhandle shader type");
1002 LLVMSetFunctionCallConv(func
, calling_conv
);
1005 /* Returns whether the stage is a stage that can be directly before the GS */
1006 static bool is_pre_gs_stage(gl_shader_stage stage
)
1008 return stage
== MESA_SHADER_VERTEX
|| stage
== MESA_SHADER_TESS_EVAL
;
1011 static void create_function(struct radv_shader_context
*ctx
,
1012 gl_shader_stage stage
,
1013 bool has_previous_stage
,
1014 gl_shader_stage previous_stage
)
1016 uint8_t user_sgpr_idx
;
1017 struct user_sgpr_info user_sgpr_info
;
1018 struct arg_info args
= {};
1019 LLVMValueRef desc_sets
;
1020 bool needs_view_index
= needs_view_index_sgpr(ctx
, stage
);
1022 if (ctx
->ac
.chip_class
>= GFX10
) {
1023 if (is_pre_gs_stage(stage
) && ctx
->options
->key
.vs_common_out
.as_ngg
) {
1024 /* On GFX10, VS is merged into GS for NGG. */
1025 previous_stage
= stage
;
1026 stage
= MESA_SHADER_GEOMETRY
;
1027 has_previous_stage
= true;
1031 allocate_user_sgprs(ctx
, stage
, has_previous_stage
,
1032 previous_stage
, needs_view_index
, &user_sgpr_info
);
1034 if (user_sgpr_info
.need_ring_offsets
&& !ctx
->options
->supports_spill
) {
1035 add_arg(&args
, ARG_SGPR
, ac_array_in_const_addr_space(ctx
->ac
.v4i32
),
1036 &ctx
->ring_offsets
);
1040 case MESA_SHADER_COMPUTE
:
1041 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1044 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
1045 add_arg(&args
, ARG_SGPR
, ctx
->ac
.v3i32
,
1046 &ctx
->abi
.num_work_groups
);
1049 for (int i
= 0; i
< 3; i
++) {
1050 ctx
->abi
.workgroup_ids
[i
] = NULL
;
1051 if (ctx
->shader_info
->info
.cs
.uses_block_id
[i
]) {
1052 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1053 &ctx
->abi
.workgroup_ids
[i
]);
1057 if (ctx
->shader_info
->info
.cs
.uses_local_invocation_idx
)
1058 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.tg_size
);
1059 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
,
1060 &ctx
->abi
.local_invocation_ids
);
1062 case MESA_SHADER_VERTEX
:
1063 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1066 declare_vs_specific_input_sgprs(ctx
, stage
, has_previous_stage
,
1067 previous_stage
, &args
);
1069 if (needs_view_index
)
1070 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1071 &ctx
->abi
.view_index
);
1072 if (ctx
->options
->key
.vs_common_out
.as_es
) {
1073 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1074 &ctx
->es2gs_offset
);
1075 } else if (ctx
->options
->key
.vs_common_out
.as_ls
) {
1076 /* no extra parameters */
1078 declare_streamout_sgprs(ctx
, stage
, &args
);
1081 declare_vs_input_vgprs(ctx
, &args
);
1083 case MESA_SHADER_TESS_CTRL
:
1084 if (has_previous_stage
) {
1085 // First 6 system regs
1086 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1087 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1088 &ctx
->merged_wave_info
);
1089 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1090 &ctx
->tess_factor_offset
);
1092 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
1093 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1094 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1096 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1099 declare_vs_specific_input_sgprs(ctx
, stage
,
1101 previous_stage
, &args
);
1103 if (needs_view_index
)
1104 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1105 &ctx
->abi
.view_index
);
1107 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1108 &ctx
->abi
.tcs_patch_id
);
1109 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1110 &ctx
->abi
.tcs_rel_ids
);
1112 declare_vs_input_vgprs(ctx
, &args
);
1114 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1117 if (needs_view_index
)
1118 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1119 &ctx
->abi
.view_index
);
1121 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1122 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1123 &ctx
->tess_factor_offset
);
1124 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1125 &ctx
->abi
.tcs_patch_id
);
1126 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1127 &ctx
->abi
.tcs_rel_ids
);
1130 case MESA_SHADER_TESS_EVAL
:
1131 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1134 if (needs_view_index
)
1135 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1136 &ctx
->abi
.view_index
);
1138 if (ctx
->options
->key
.vs_common_out
.as_es
) {
1139 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1140 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
1141 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1142 &ctx
->es2gs_offset
);
1144 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
1145 declare_streamout_sgprs(ctx
, stage
, &args
);
1146 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1148 declare_tes_input_vgprs(ctx
, &args
);
1150 case MESA_SHADER_GEOMETRY
:
1151 if (has_previous_stage
) {
1152 // First 6 system regs
1153 if (ctx
->options
->key
.vs_common_out
.as_ngg
) {
1154 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1157 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1158 &ctx
->gs2vs_offset
);
1161 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1162 &ctx
->merged_wave_info
);
1163 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1165 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
1166 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1167 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1169 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1172 if (previous_stage
!= MESA_SHADER_TESS_EVAL
) {
1173 declare_vs_specific_input_sgprs(ctx
, stage
,
1179 if (needs_view_index
)
1180 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1181 &ctx
->abi
.view_index
);
1183 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1184 &ctx
->gs_vtx_offset
[0]);
1185 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1186 &ctx
->gs_vtx_offset
[2]);
1187 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1188 &ctx
->abi
.gs_prim_id
);
1189 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1190 &ctx
->abi
.gs_invocation_id
);
1191 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1192 &ctx
->gs_vtx_offset
[4]);
1194 if (previous_stage
== MESA_SHADER_VERTEX
) {
1195 declare_vs_input_vgprs(ctx
, &args
);
1197 declare_tes_input_vgprs(ctx
, &args
);
1200 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1203 if (needs_view_index
)
1204 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1205 &ctx
->abi
.view_index
);
1207 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs2vs_offset
);
1208 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs_wave_id
);
1209 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1210 &ctx
->gs_vtx_offset
[0]);
1211 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1212 &ctx
->gs_vtx_offset
[1]);
1213 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1214 &ctx
->abi
.gs_prim_id
);
1215 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1216 &ctx
->gs_vtx_offset
[2]);
1217 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1218 &ctx
->gs_vtx_offset
[3]);
1219 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1220 &ctx
->gs_vtx_offset
[4]);
1221 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1222 &ctx
->gs_vtx_offset
[5]);
1223 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1224 &ctx
->abi
.gs_invocation_id
);
1227 case MESA_SHADER_FRAGMENT
:
1228 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1231 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.prim_mask
);
1232 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->abi
.persp_sample
);
1233 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->abi
.persp_center
);
1234 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->abi
.persp_centroid
);
1235 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
, NULL
); /* persp pull model */
1236 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->abi
.linear_sample
);
1237 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->abi
.linear_center
);
1238 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->abi
.linear_centroid
);
1239 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, NULL
); /* line stipple tex */
1240 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[0]);
1241 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[1]);
1242 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[2]);
1243 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[3]);
1244 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.front_face
);
1245 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.ancillary
);
1246 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.sample_coverage
);
1247 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* fixed pt */
1250 unreachable("Shader stage not implemented");
1253 ctx
->main_function
= create_llvm_function(
1254 ctx
->context
, ctx
->ac
.module
, ctx
->ac
.builder
, NULL
, 0, &args
,
1255 ctx
->max_workgroup_size
, ctx
->options
);
1256 set_llvm_calling_convention(ctx
->main_function
, stage
);
1259 ctx
->shader_info
->num_input_vgprs
= 0;
1260 ctx
->shader_info
->num_input_sgprs
= ctx
->options
->supports_spill
? 2 : 0;
1262 ctx
->shader_info
->num_input_sgprs
+= args
.num_sgprs_used
;
1264 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
1265 ctx
->shader_info
->num_input_vgprs
= args
.num_vgprs_used
;
1267 assign_arguments(ctx
->main_function
, &args
);
1271 if (ctx
->options
->supports_spill
|| user_sgpr_info
.need_ring_offsets
) {
1272 set_loc_shader_ptr(ctx
, AC_UD_SCRATCH_RING_OFFSETS
,
1274 if (ctx
->options
->supports_spill
) {
1275 ctx
->ring_offsets
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.implicit.buffer.ptr",
1276 LLVMPointerType(ctx
->ac
.i8
, AC_ADDR_SPACE_CONST
),
1277 NULL
, 0, AC_FUNC_ATTR_READNONE
);
1278 ctx
->ring_offsets
= LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->ring_offsets
,
1279 ac_array_in_const_addr_space(ctx
->ac
.v4i32
), "");
1283 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1284 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1285 if (has_previous_stage
)
1288 set_global_input_locs(ctx
, &user_sgpr_info
, desc_sets
, &user_sgpr_idx
);
1291 case MESA_SHADER_COMPUTE
:
1292 if (ctx
->shader_info
->info
.cs
.uses_grid_size
) {
1293 set_loc_shader(ctx
, AC_UD_CS_GRID_SIZE
,
1297 case MESA_SHADER_VERTEX
:
1298 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1299 previous_stage
, &user_sgpr_idx
);
1300 if (ctx
->abi
.view_index
)
1301 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1303 case MESA_SHADER_TESS_CTRL
:
1304 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1305 previous_stage
, &user_sgpr_idx
);
1306 if (ctx
->abi
.view_index
)
1307 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1309 case MESA_SHADER_TESS_EVAL
:
1310 if (ctx
->abi
.view_index
)
1311 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1313 case MESA_SHADER_GEOMETRY
:
1314 if (has_previous_stage
) {
1315 if (previous_stage
== MESA_SHADER_VERTEX
)
1316 set_vs_specific_input_locs(ctx
, stage
,
1321 if (ctx
->abi
.view_index
)
1322 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1324 case MESA_SHADER_FRAGMENT
:
1327 unreachable("Shader stage not implemented");
1330 if (stage
== MESA_SHADER_TESS_CTRL
||
1331 (stage
== MESA_SHADER_VERTEX
&& ctx
->options
->key
.vs_common_out
.as_ls
) ||
1332 /* GFX9 has the ESGS ring buffer in LDS. */
1333 (stage
== MESA_SHADER_GEOMETRY
&& has_previous_stage
)) {
1334 ac_declare_lds_as_pointer(&ctx
->ac
);
1337 ctx
->shader_info
->num_user_sgprs
= user_sgpr_idx
;
1342 radv_load_resource(struct ac_shader_abi
*abi
, LLVMValueRef index
,
1343 unsigned desc_set
, unsigned binding
)
1345 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1346 LLVMValueRef desc_ptr
= ctx
->descriptor_sets
[desc_set
];
1347 struct radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
1348 struct radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
1349 unsigned base_offset
= layout
->binding
[binding
].offset
;
1350 LLVMValueRef offset
, stride
;
1352 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
1353 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
1354 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+
1355 layout
->binding
[binding
].dynamic_offset_offset
;
1356 desc_ptr
= ctx
->abi
.push_constants
;
1357 base_offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
1358 stride
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
1360 stride
= LLVMConstInt(ctx
->ac
.i32
, layout
->binding
[binding
].size
, false);
1362 offset
= LLVMConstInt(ctx
->ac
.i32
, base_offset
, false);
1364 if (layout
->binding
[binding
].type
!= VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
1365 offset
= ac_build_imad(&ctx
->ac
, index
, stride
, offset
);
1368 desc_ptr
= LLVMBuildGEP(ctx
->ac
.builder
, desc_ptr
, &offset
, 1, "");
1369 desc_ptr
= ac_cast_ptr(&ctx
->ac
, desc_ptr
, ctx
->ac
.v4i32
);
1370 LLVMSetMetadata(desc_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1372 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
1373 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1374 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1375 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1376 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
1378 if (ctx
->ac
.chip_class
>= GFX10
) {
1379 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
1380 S_008F0C_OOB_SELECT(3) |
1381 S_008F0C_RESOURCE_LEVEL(1);
1383 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1384 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1387 LLVMValueRef desc_components
[4] = {
1388 LLVMBuildPtrToInt(ctx
->ac
.builder
, desc_ptr
, ctx
->ac
.intptr
, ""),
1389 LLVMConstInt(ctx
->ac
.i32
, S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
), false),
1390 /* High limit to support variable sizes. */
1391 LLVMConstInt(ctx
->ac
.i32
, 0xffffffff, false),
1392 LLVMConstInt(ctx
->ac
.i32
, desc_type
, false),
1395 return ac_build_gather_values(&ctx
->ac
, desc_components
, 4);
1402 /* The offchip buffer layout for TCS->TES is
1404 * - attribute 0 of patch 0 vertex 0
1405 * - attribute 0 of patch 0 vertex 1
1406 * - attribute 0 of patch 0 vertex 2
1408 * - attribute 0 of patch 1 vertex 0
1409 * - attribute 0 of patch 1 vertex 1
1411 * - attribute 1 of patch 0 vertex 0
1412 * - attribute 1 of patch 0 vertex 1
1414 * - per patch attribute 0 of patch 0
1415 * - per patch attribute 0 of patch 1
1418 * Note that every attribute has 4 components.
1420 static LLVMValueRef
get_non_vertex_index_offset(struct radv_shader_context
*ctx
)
1422 uint32_t num_patches
= ctx
->tcs_num_patches
;
1423 uint32_t num_tcs_outputs
;
1424 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
1425 num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->info
.tcs
.outputs_written
);
1427 num_tcs_outputs
= ctx
->options
->key
.tes
.tcs_num_outputs
;
1429 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
1430 uint32_t pervertex_output_patch_size
= ctx
->tcs_vertices_per_patch
* output_vertex_size
;
1432 return LLVMConstInt(ctx
->ac
.i32
, pervertex_output_patch_size
* num_patches
, false);
1435 static LLVMValueRef
calc_param_stride(struct radv_shader_context
*ctx
,
1436 LLVMValueRef vertex_index
)
1438 LLVMValueRef param_stride
;
1440 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_vertices_per_patch
* ctx
->tcs_num_patches
, false);
1442 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_num_patches
, false);
1443 return param_stride
;
1446 static LLVMValueRef
get_tcs_tes_buffer_address(struct radv_shader_context
*ctx
,
1447 LLVMValueRef vertex_index
,
1448 LLVMValueRef param_index
)
1450 LLVMValueRef base_addr
;
1451 LLVMValueRef param_stride
, constant16
;
1452 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
1453 LLVMValueRef vertices_per_patch
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_vertices_per_patch
, false);
1454 constant16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
1455 param_stride
= calc_param_stride(ctx
, vertex_index
);
1457 base_addr
= ac_build_imad(&ctx
->ac
, rel_patch_id
,
1458 vertices_per_patch
, vertex_index
);
1460 base_addr
= rel_patch_id
;
1463 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
1464 LLVMBuildMul(ctx
->ac
.builder
, param_index
,
1465 param_stride
, ""), "");
1467 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, base_addr
, constant16
, "");
1469 if (!vertex_index
) {
1470 LLVMValueRef patch_data_offset
= get_non_vertex_index_offset(ctx
);
1472 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
1473 patch_data_offset
, "");
1478 static LLVMValueRef
get_tcs_tes_buffer_address_params(struct radv_shader_context
*ctx
,
1480 unsigned const_index
,
1482 LLVMValueRef vertex_index
,
1483 LLVMValueRef indir_index
)
1485 LLVMValueRef param_index
;
1488 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, param
, false),
1491 if (const_index
&& !is_compact
)
1492 param
+= const_index
;
1493 param_index
= LLVMConstInt(ctx
->ac
.i32
, param
, false);
1495 return get_tcs_tes_buffer_address(ctx
, vertex_index
, param_index
);
1499 get_dw_address(struct radv_shader_context
*ctx
,
1500 LLVMValueRef dw_addr
,
1502 unsigned const_index
,
1503 bool compact_const_index
,
1504 LLVMValueRef vertex_index
,
1505 LLVMValueRef stride
,
1506 LLVMValueRef indir_index
)
1511 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1512 LLVMBuildMul(ctx
->ac
.builder
,
1518 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1519 LLVMBuildMul(ctx
->ac
.builder
, indir_index
,
1520 LLVMConstInt(ctx
->ac
.i32
, 4, false), ""), "");
1521 else if (const_index
&& !compact_const_index
)
1522 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1523 LLVMConstInt(ctx
->ac
.i32
, const_index
* 4, false), "");
1525 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1526 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false), "");
1528 if (const_index
&& compact_const_index
)
1529 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1530 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
1535 load_tcs_varyings(struct ac_shader_abi
*abi
,
1537 LLVMValueRef vertex_index
,
1538 LLVMValueRef indir_index
,
1539 unsigned const_index
,
1541 unsigned driver_location
,
1543 unsigned num_components
,
1548 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1549 LLVMValueRef dw_addr
, stride
;
1550 LLVMValueRef value
[4], result
;
1551 unsigned param
= shader_io_get_unique_index(location
);
1554 uint32_t input_vertex_size
= (ctx
->tcs_num_inputs
* 16) / 4;
1555 stride
= LLVMConstInt(ctx
->ac
.i32
, input_vertex_size
, false);
1556 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
1559 stride
= get_tcs_out_vertex_stride(ctx
);
1560 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1562 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1567 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
1570 for (unsigned i
= 0; i
< num_components
+ component
; i
++) {
1571 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
1572 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1575 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1580 store_tcs_output(struct ac_shader_abi
*abi
,
1581 const nir_variable
*var
,
1582 LLVMValueRef vertex_index
,
1583 LLVMValueRef param_index
,
1584 unsigned const_index
,
1588 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1589 const unsigned location
= var
->data
.location
;
1590 unsigned component
= var
->data
.location_frac
;
1591 const bool is_patch
= var
->data
.patch
;
1592 const bool is_compact
= var
->data
.compact
;
1593 LLVMValueRef dw_addr
;
1594 LLVMValueRef stride
= NULL
;
1595 LLVMValueRef buf_addr
= NULL
;
1597 bool store_lds
= true;
1600 if (!(ctx
->tcs_patch_outputs_read
& (1U << (location
- VARYING_SLOT_PATCH0
))))
1603 if (!(ctx
->tcs_outputs_read
& (1ULL << location
)))
1607 param
= shader_io_get_unique_index(location
);
1608 if ((location
== VARYING_SLOT_CLIP_DIST0
|| location
== VARYING_SLOT_CLIP_DIST1
) && is_compact
) {
1609 const_index
+= component
;
1612 if (const_index
>= 4) {
1619 stride
= get_tcs_out_vertex_stride(ctx
);
1620 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1622 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1625 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
1627 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
, is_compact
,
1628 vertex_index
, param_index
);
1630 bool is_tess_factor
= false;
1631 if (location
== VARYING_SLOT_TESS_LEVEL_INNER
||
1632 location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
1633 is_tess_factor
= true;
1635 unsigned base
= is_compact
? const_index
: 0;
1636 for (unsigned chan
= 0; chan
< 8; chan
++) {
1637 if (!(writemask
& (1 << chan
)))
1639 LLVMValueRef value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- component
);
1640 value
= ac_to_integer(&ctx
->ac
, value
);
1641 value
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
1643 if (store_lds
|| is_tess_factor
) {
1644 LLVMValueRef dw_addr_chan
=
1645 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1646 LLVMConstInt(ctx
->ac
.i32
, chan
, false), "");
1647 ac_lds_store(&ctx
->ac
, dw_addr_chan
, value
);
1650 if (!is_tess_factor
&& writemask
!= 0xF)
1651 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, value
, 1,
1652 buf_addr
, ctx
->oc_lds
,
1653 4 * (base
+ chan
), ac_glc
, false);
1656 if (writemask
== 0xF) {
1657 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, src
, 4,
1658 buf_addr
, ctx
->oc_lds
,
1659 (base
* 4), ac_glc
, false);
1664 load_tes_input(struct ac_shader_abi
*abi
,
1666 LLVMValueRef vertex_index
,
1667 LLVMValueRef param_index
,
1668 unsigned const_index
,
1670 unsigned driver_location
,
1672 unsigned num_components
,
1677 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1678 LLVMValueRef buf_addr
;
1679 LLVMValueRef result
;
1680 unsigned param
= shader_io_get_unique_index(location
);
1682 if ((location
== VARYING_SLOT_CLIP_DIST0
|| location
== VARYING_SLOT_CLIP_DIST1
) && is_compact
) {
1683 const_index
+= component
;
1685 if (const_index
>= 4) {
1691 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
,
1692 is_compact
, vertex_index
, param_index
);
1694 LLVMValueRef comp_offset
= LLVMConstInt(ctx
->ac
.i32
, component
* 4, false);
1695 buf_addr
= LLVMBuildAdd(ctx
->ac
.builder
, buf_addr
, comp_offset
, "");
1697 result
= ac_build_buffer_load(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, num_components
, NULL
,
1698 buf_addr
, ctx
->oc_lds
, is_compact
? (4 * const_index
) : 0, ac_glc
, true, false);
1699 result
= ac_trim_vector(&ctx
->ac
, result
, num_components
);
1704 load_gs_input(struct ac_shader_abi
*abi
,
1706 unsigned driver_location
,
1708 unsigned num_components
,
1709 unsigned vertex_index
,
1710 unsigned const_index
,
1713 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1714 LLVMValueRef vtx_offset
;
1715 unsigned param
, vtx_offset_param
;
1716 LLVMValueRef value
[4], result
;
1718 vtx_offset_param
= vertex_index
;
1719 assert(vtx_offset_param
< 6);
1720 vtx_offset
= LLVMBuildMul(ctx
->ac
.builder
, ctx
->gs_vtx_offset
[vtx_offset_param
],
1721 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
1723 param
= shader_io_get_unique_index(location
);
1725 for (unsigned i
= component
; i
< num_components
+ component
; i
++) {
1726 if (ctx
->ac
.chip_class
>= GFX9
) {
1727 LLVMValueRef dw_addr
= ctx
->gs_vtx_offset
[vtx_offset_param
];
1728 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1729 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
, 0), "");
1730 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
1732 LLVMValueRef soffset
=
1733 LLVMConstInt(ctx
->ac
.i32
,
1734 (param
* 4 + i
+ const_index
) * 256,
1737 value
[i
] = ac_build_buffer_load(&ctx
->ac
,
1740 vtx_offset
, soffset
,
1741 0, ac_glc
, true, false);
1744 if (ac_get_type_size(type
) == 2) {
1745 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
], ctx
->ac
.i32
, "");
1746 value
[i
] = LLVMBuildTrunc(ctx
->ac
.builder
, value
[i
], ctx
->ac
.i16
, "");
1748 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
], type
, "");
1750 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1751 result
= ac_to_integer(&ctx
->ac
, result
);
1756 static void radv_emit_kill(struct ac_shader_abi
*abi
, LLVMValueRef visible
)
1758 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1759 ac_build_kill_if_false(&ctx
->ac
, visible
);
1762 static LLVMValueRef
lookup_interp_param(struct ac_shader_abi
*abi
,
1763 enum glsl_interp_mode interp
, unsigned location
)
1765 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1768 case INTERP_MODE_FLAT
:
1771 case INTERP_MODE_SMOOTH
:
1772 case INTERP_MODE_NONE
:
1773 if (location
== INTERP_CENTER
)
1774 return ctx
->abi
.persp_center
;
1775 else if (location
== INTERP_CENTROID
)
1776 return ctx
->abi
.persp_centroid
;
1777 else if (location
== INTERP_SAMPLE
)
1778 return ctx
->abi
.persp_sample
;
1780 case INTERP_MODE_NOPERSPECTIVE
:
1781 if (location
== INTERP_CENTER
)
1782 return ctx
->abi
.linear_center
;
1783 else if (location
== INTERP_CENTROID
)
1784 return ctx
->abi
.linear_centroid
;
1785 else if (location
== INTERP_SAMPLE
)
1786 return ctx
->abi
.linear_sample
;
1793 radv_get_sample_pos_offset(uint32_t num_samples
)
1795 uint32_t sample_pos_offset
= 0;
1797 switch (num_samples
) {
1799 sample_pos_offset
= 1;
1802 sample_pos_offset
= 3;
1805 sample_pos_offset
= 7;
1810 return sample_pos_offset
;
1813 static LLVMValueRef
load_sample_position(struct ac_shader_abi
*abi
,
1814 LLVMValueRef sample_id
)
1816 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1818 LLVMValueRef result
;
1819 LLVMValueRef index
= LLVMConstInt(ctx
->ac
.i32
, RING_PS_SAMPLE_POSITIONS
, false);
1820 LLVMValueRef ptr
= LLVMBuildGEP(ctx
->ac
.builder
, ctx
->ring_offsets
, &index
, 1, "");
1822 ptr
= LLVMBuildBitCast(ctx
->ac
.builder
, ptr
,
1823 ac_array_in_const_addr_space(ctx
->ac
.v2f32
), "");
1825 uint32_t sample_pos_offset
=
1826 radv_get_sample_pos_offset(ctx
->options
->key
.fs
.num_samples
);
1829 LLVMBuildAdd(ctx
->ac
.builder
, sample_id
,
1830 LLVMConstInt(ctx
->ac
.i32
, sample_pos_offset
, false), "");
1831 result
= ac_build_load_invariant(&ctx
->ac
, ptr
, sample_id
);
1837 static LLVMValueRef
load_sample_mask_in(struct ac_shader_abi
*abi
)
1839 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1840 uint8_t log2_ps_iter_samples
;
1842 if (ctx
->shader_info
->info
.ps
.force_persample
) {
1843 log2_ps_iter_samples
=
1844 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
1846 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
1849 /* The bit pattern matches that used by fixed function fragment
1851 static const uint16_t ps_iter_masks
[] = {
1852 0xffff, /* not used */
1858 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
1860 uint32_t ps_iter_mask
= ps_iter_masks
[log2_ps_iter_samples
];
1862 LLVMValueRef result
, sample_id
;
1863 sample_id
= ac_unpack_param(&ctx
->ac
, abi
->ancillary
, 8, 4);
1864 sample_id
= LLVMBuildShl(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, ps_iter_mask
, false), sample_id
, "");
1865 result
= LLVMBuildAnd(ctx
->ac
.builder
, sample_id
, abi
->sample_coverage
, "");
1870 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context
*ctx
,
1872 LLVMValueRef
*addrs
);
1875 visit_emit_vertex(struct ac_shader_abi
*abi
, unsigned stream
, LLVMValueRef
*addrs
)
1877 LLVMValueRef gs_next_vertex
;
1878 LLVMValueRef can_emit
;
1879 unsigned offset
= 0;
1880 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1882 if (ctx
->options
->key
.vs_common_out
.as_ngg
) {
1883 gfx10_ngg_gs_emit_vertex(ctx
, stream
, addrs
);
1887 /* Write vertex attribute values to GSVS ring */
1888 gs_next_vertex
= LLVMBuildLoad(ctx
->ac
.builder
,
1889 ctx
->gs_next_vertex
[stream
],
1892 /* If this thread has already emitted the declared maximum number of
1893 * vertices, kill it: excessive vertex emissions are not supposed to
1894 * have any effect, and GS threads have no externally observable
1895 * effects other than emitting vertices.
1897 can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
, gs_next_vertex
,
1898 LLVMConstInt(ctx
->ac
.i32
, ctx
->gs_max_out_vertices
, false), "");
1899 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
1901 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
1902 unsigned output_usage_mask
=
1903 ctx
->shader_info
->info
.gs
.output_usage_mask
[i
];
1904 uint8_t output_stream
=
1905 ctx
->shader_info
->info
.gs
.output_streams
[i
];
1906 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
1907 int length
= util_last_bit(output_usage_mask
);
1909 if (!(ctx
->output_mask
& (1ull << i
)) ||
1910 output_stream
!= stream
)
1913 for (unsigned j
= 0; j
< length
; j
++) {
1914 if (!(output_usage_mask
& (1 << j
)))
1917 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
,
1919 LLVMValueRef voffset
=
1920 LLVMConstInt(ctx
->ac
.i32
, offset
*
1921 ctx
->gs_max_out_vertices
, false);
1925 voffset
= LLVMBuildAdd(ctx
->ac
.builder
, voffset
, gs_next_vertex
, "");
1926 voffset
= LLVMBuildMul(ctx
->ac
.builder
, voffset
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
1928 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
1929 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
1931 ac_build_buffer_store_dword(&ctx
->ac
,
1932 ctx
->gsvs_ring
[stream
],
1934 voffset
, ctx
->gs2vs_offset
, 0,
1935 ac_glc
| ac_slc
, true);
1939 gs_next_vertex
= LLVMBuildAdd(ctx
->ac
.builder
, gs_next_vertex
,
1941 LLVMBuildStore(ctx
->ac
.builder
, gs_next_vertex
, ctx
->gs_next_vertex
[stream
]);
1943 ac_build_sendmsg(&ctx
->ac
,
1944 AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (stream
<< 8),
1949 visit_end_primitive(struct ac_shader_abi
*abi
, unsigned stream
)
1951 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1953 if (ctx
->options
->key
.vs_common_out
.as_ngg
) {
1954 LLVMBuildStore(ctx
->ac
.builder
, ctx
->ac
.i32_0
, ctx
->gs_curprim_verts
[stream
]);
1958 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (stream
<< 8), ctx
->gs_wave_id
);
1962 load_tess_coord(struct ac_shader_abi
*abi
)
1964 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1966 LLVMValueRef coord
[4] = {
1973 if (ctx
->tes_primitive_mode
== GL_TRIANGLES
)
1974 coord
[2] = LLVMBuildFSub(ctx
->ac
.builder
, ctx
->ac
.f32_1
,
1975 LLVMBuildFAdd(ctx
->ac
.builder
, coord
[0], coord
[1], ""), "");
1977 return ac_build_gather_values(&ctx
->ac
, coord
, 3);
1981 load_patch_vertices_in(struct ac_shader_abi
*abi
)
1983 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1984 return LLVMConstInt(ctx
->ac
.i32
, ctx
->options
->key
.tcs
.input_vertices
, false);
1988 static LLVMValueRef
radv_load_base_vertex(struct ac_shader_abi
*abi
)
1990 return abi
->base_vertex
;
1993 static LLVMValueRef
radv_load_ssbo(struct ac_shader_abi
*abi
,
1994 LLVMValueRef buffer_ptr
, bool write
)
1996 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1997 LLVMValueRef result
;
1999 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
2001 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
2002 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
2007 static LLVMValueRef
radv_load_ubo(struct ac_shader_abi
*abi
, LLVMValueRef buffer_ptr
)
2009 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
2010 LLVMValueRef result
;
2012 if (LLVMGetTypeKind(LLVMTypeOf(buffer_ptr
)) != LLVMPointerTypeKind
) {
2013 /* Do not load the descriptor for inlined uniform blocks. */
2017 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
2019 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
2020 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
2025 static LLVMValueRef
radv_get_sampler_desc(struct ac_shader_abi
*abi
,
2026 unsigned descriptor_set
,
2027 unsigned base_index
,
2028 unsigned constant_index
,
2030 enum ac_descriptor_type desc_type
,
2031 bool image
, bool write
,
2034 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
2035 LLVMValueRef list
= ctx
->descriptor_sets
[descriptor_set
];
2036 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
2037 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
2038 unsigned offset
= binding
->offset
;
2039 unsigned stride
= binding
->size
;
2041 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2044 assert(base_index
< layout
->binding_count
);
2046 switch (desc_type
) {
2048 type
= ctx
->ac
.v8i32
;
2052 type
= ctx
->ac
.v8i32
;
2056 case AC_DESC_SAMPLER
:
2057 type
= ctx
->ac
.v4i32
;
2058 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
) {
2059 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
2064 case AC_DESC_BUFFER
:
2065 type
= ctx
->ac
.v4i32
;
2068 case AC_DESC_PLANE_0
:
2069 case AC_DESC_PLANE_1
:
2070 case AC_DESC_PLANE_2
:
2071 type
= ctx
->ac
.v8i32
;
2073 offset
+= 32 * (desc_type
- AC_DESC_PLANE_0
);
2076 unreachable("invalid desc_type\n");
2079 offset
+= constant_index
* stride
;
2081 if (desc_type
== AC_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
2082 (!index
|| binding
->immutable_samplers_equal
)) {
2083 if (binding
->immutable_samplers_equal
)
2086 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
2088 LLVMValueRef constants
[] = {
2089 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 0], 0),
2090 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 1], 0),
2091 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 2], 0),
2092 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 3], 0),
2094 return ac_build_gather_values(&ctx
->ac
, constants
, 4);
2097 assert(stride
% type_size
== 0);
2099 LLVMValueRef adjusted_index
= index
;
2100 if (!adjusted_index
)
2101 adjusted_index
= ctx
->ac
.i32_0
;
2103 adjusted_index
= LLVMBuildMul(builder
, adjusted_index
, LLVMConstInt(ctx
->ac
.i32
, stride
/ type_size
, 0), "");
2105 LLVMValueRef val_offset
= LLVMConstInt(ctx
->ac
.i32
, offset
, 0);
2106 list
= LLVMBuildGEP(builder
, list
, &val_offset
, 1, "");
2107 list
= LLVMBuildPointerCast(builder
, list
,
2108 ac_array_in_const32_addr_space(type
), "");
2110 LLVMValueRef descriptor
= ac_build_load_to_sgpr(&ctx
->ac
, list
, adjusted_index
);
2112 /* 3 plane formats always have same size and format for plane 1 & 2, so
2113 * use the tail from plane 1 so that we can store only the first 16 bytes
2114 * of the last plane. */
2115 if (desc_type
== AC_DESC_PLANE_2
) {
2116 LLVMValueRef descriptor2
= radv_get_sampler_desc(abi
, descriptor_set
, base_index
, constant_index
, index
, AC_DESC_PLANE_1
,image
, write
, bindless
);
2118 LLVMValueRef components
[8];
2119 for (unsigned i
= 0; i
< 4; ++i
)
2120 components
[i
] = ac_llvm_extract_elem(&ctx
->ac
, descriptor
, i
);
2122 for (unsigned i
= 4; i
< 8; ++i
)
2123 components
[i
] = ac_llvm_extract_elem(&ctx
->ac
, descriptor2
, i
);
2124 descriptor
= ac_build_gather_values(&ctx
->ac
, components
, 8);
2130 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
2131 * so we may need to fix it up. */
2133 adjust_vertex_fetch_alpha(struct radv_shader_context
*ctx
,
2134 unsigned adjustment
,
2137 if (adjustment
== RADV_ALPHA_ADJUST_NONE
)
2140 LLVMValueRef c30
= LLVMConstInt(ctx
->ac
.i32
, 30, 0);
2142 alpha
= LLVMBuildBitCast(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
2144 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
2145 alpha
= LLVMBuildFPToUI(ctx
->ac
.builder
, alpha
, ctx
->ac
.i32
, "");
2147 alpha
= ac_to_integer(&ctx
->ac
, alpha
);
2149 /* For the integer-like cases, do a natural sign extension.
2151 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
2152 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
2155 alpha
= LLVMBuildShl(ctx
->ac
.builder
, alpha
,
2156 adjustment
== RADV_ALPHA_ADJUST_SNORM
?
2157 LLVMConstInt(ctx
->ac
.i32
, 7, 0) : c30
, "");
2158 alpha
= LLVMBuildAShr(ctx
->ac
.builder
, alpha
, c30
, "");
2160 /* Convert back to the right type. */
2161 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
2163 LLVMValueRef neg_one
= LLVMConstReal(ctx
->ac
.f32
, -1.0);
2164 alpha
= LLVMBuildSIToFP(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
2165 clamp
= LLVMBuildFCmp(ctx
->ac
.builder
, LLVMRealULT
, alpha
, neg_one
, "");
2166 alpha
= LLVMBuildSelect(ctx
->ac
.builder
, clamp
, neg_one
, alpha
, "");
2167 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
2168 alpha
= LLVMBuildSIToFP(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
2171 return LLVMBuildBitCast(ctx
->ac
.builder
, alpha
, ctx
->ac
.i32
, "");
2175 get_num_channels_from_data_format(unsigned data_format
)
2177 switch (data_format
) {
2178 case V_008F0C_BUF_DATA_FORMAT_8
:
2179 case V_008F0C_BUF_DATA_FORMAT_16
:
2180 case V_008F0C_BUF_DATA_FORMAT_32
:
2182 case V_008F0C_BUF_DATA_FORMAT_8_8
:
2183 case V_008F0C_BUF_DATA_FORMAT_16_16
:
2184 case V_008F0C_BUF_DATA_FORMAT_32_32
:
2186 case V_008F0C_BUF_DATA_FORMAT_10_11_11
:
2187 case V_008F0C_BUF_DATA_FORMAT_11_11_10
:
2188 case V_008F0C_BUF_DATA_FORMAT_32_32_32
:
2190 case V_008F0C_BUF_DATA_FORMAT_8_8_8_8
:
2191 case V_008F0C_BUF_DATA_FORMAT_10_10_10_2
:
2192 case V_008F0C_BUF_DATA_FORMAT_2_10_10_10
:
2193 case V_008F0C_BUF_DATA_FORMAT_16_16_16_16
:
2194 case V_008F0C_BUF_DATA_FORMAT_32_32_32_32
:
2204 radv_fixup_vertex_input_fetches(struct radv_shader_context
*ctx
,
2206 unsigned num_channels
,
2209 LLVMValueRef zero
= is_float
? ctx
->ac
.f32_0
: ctx
->ac
.i32_0
;
2210 LLVMValueRef one
= is_float
? ctx
->ac
.f32_1
: ctx
->ac
.i32_1
;
2211 LLVMValueRef chan
[4];
2213 if (LLVMGetTypeKind(LLVMTypeOf(value
)) == LLVMVectorTypeKind
) {
2214 unsigned vec_size
= LLVMGetVectorSize(LLVMTypeOf(value
));
2216 if (num_channels
== 4 && num_channels
== vec_size
)
2219 num_channels
= MIN2(num_channels
, vec_size
);
2221 for (unsigned i
= 0; i
< num_channels
; i
++)
2222 chan
[i
] = ac_llvm_extract_elem(&ctx
->ac
, value
, i
);
2225 assert(num_channels
== 1);
2230 for (unsigned i
= num_channels
; i
< 4; i
++) {
2231 chan
[i
] = i
== 3 ? one
: zero
;
2232 chan
[i
] = ac_to_integer(&ctx
->ac
, chan
[i
]);
2235 return ac_build_gather_values(&ctx
->ac
, chan
, 4);
2239 handle_vs_input_decl(struct radv_shader_context
*ctx
,
2240 struct nir_variable
*variable
)
2242 LLVMValueRef t_list_ptr
= ctx
->vertex_buffers
;
2243 LLVMValueRef t_offset
;
2244 LLVMValueRef t_list
;
2246 LLVMValueRef buffer_index
;
2247 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, true);
2248 uint8_t input_usage_mask
=
2249 ctx
->shader_info
->info
.vs
.input_usage_mask
[variable
->data
.location
];
2250 unsigned num_input_channels
= util_last_bit(input_usage_mask
);
2252 variable
->data
.driver_location
= variable
->data
.location
* 4;
2254 enum glsl_base_type type
= glsl_get_base_type(variable
->type
);
2255 for (unsigned i
= 0; i
< attrib_count
; ++i
) {
2256 LLVMValueRef output
[4];
2257 unsigned attrib_index
= variable
->data
.location
+ i
- VERT_ATTRIB_GENERIC0
;
2258 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[attrib_index
];
2259 unsigned data_format
= attrib_format
& 0x0f;
2260 unsigned num_format
= (attrib_format
>> 4) & 0x07;
2261 bool is_float
= num_format
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
2262 num_format
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
2264 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << attrib_index
)) {
2265 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[attrib_index
];
2268 buffer_index
= ctx
->abi
.instance_id
;
2271 buffer_index
= LLVMBuildUDiv(ctx
->ac
.builder
, buffer_index
,
2272 LLVMConstInt(ctx
->ac
.i32
, divisor
, 0), "");
2275 buffer_index
= ctx
->ac
.i32_0
;
2278 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
, ctx
->abi
.start_instance
, buffer_index
, "");
2280 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
, ctx
->abi
.vertex_id
,
2281 ctx
->abi
.base_vertex
, "");
2283 /* Adjust the number of channels to load based on the vertex
2286 unsigned num_format_channels
= get_num_channels_from_data_format(data_format
);
2287 unsigned num_channels
= MIN2(num_input_channels
, num_format_channels
);
2288 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[attrib_index
];
2289 unsigned attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[attrib_index
];
2290 unsigned attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[attrib_index
];
2292 if (ctx
->options
->key
.vs
.post_shuffle
& (1 << attrib_index
)) {
2293 /* Always load, at least, 3 channels for formats that
2294 * need to be shuffled because X<->Z.
2296 num_channels
= MAX2(num_channels
, 3);
2299 if (attrib_stride
!= 0 && attrib_offset
> attrib_stride
) {
2300 LLVMValueRef buffer_offset
=
2301 LLVMConstInt(ctx
->ac
.i32
,
2302 attrib_offset
/ attrib_stride
, false);
2304 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
,
2308 attrib_offset
= attrib_offset
% attrib_stride
;
2311 t_offset
= LLVMConstInt(ctx
->ac
.i32
, attrib_binding
, false);
2312 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
2314 input
= ac_build_struct_tbuffer_load(&ctx
->ac
, t_list
,
2316 LLVMConstInt(ctx
->ac
.i32
, attrib_offset
, false),
2317 ctx
->ac
.i32_0
, ctx
->ac
.i32_0
,
2319 data_format
, num_format
, 0, true);
2321 if (ctx
->options
->key
.vs
.post_shuffle
& (1 << attrib_index
)) {
2323 c
[0] = ac_llvm_extract_elem(&ctx
->ac
, input
, 2);
2324 c
[1] = ac_llvm_extract_elem(&ctx
->ac
, input
, 1);
2325 c
[2] = ac_llvm_extract_elem(&ctx
->ac
, input
, 0);
2326 c
[3] = ac_llvm_extract_elem(&ctx
->ac
, input
, 3);
2328 input
= ac_build_gather_values(&ctx
->ac
, c
, 4);
2331 input
= radv_fixup_vertex_input_fetches(ctx
, input
, num_channels
,
2334 for (unsigned chan
= 0; chan
< 4; chan
++) {
2335 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
2336 output
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
, input
, llvm_chan
, "");
2337 if (type
== GLSL_TYPE_FLOAT16
) {
2338 output
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.f32
, "");
2339 output
[chan
] = LLVMBuildFPTrunc(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.f16
, "");
2343 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (attrib_index
* 2)) & 3;
2344 output
[3] = adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, output
[3]);
2346 for (unsigned chan
= 0; chan
< 4; chan
++) {
2347 output
[chan
] = ac_to_integer(&ctx
->ac
, output
[chan
]);
2348 if (type
== GLSL_TYPE_UINT16
|| type
== GLSL_TYPE_INT16
)
2349 output
[chan
] = LLVMBuildTrunc(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.i16
, "");
2351 ctx
->inputs
[ac_llvm_reg_index_soa(variable
->data
.location
+ i
, chan
)] = output
[chan
];
2357 handle_vs_inputs(struct radv_shader_context
*ctx
,
2358 struct nir_shader
*nir
) {
2359 nir_foreach_variable(variable
, &nir
->inputs
)
2360 handle_vs_input_decl(ctx
, variable
);
2364 prepare_interp_optimize(struct radv_shader_context
*ctx
,
2365 struct nir_shader
*nir
)
2367 bool uses_center
= false;
2368 bool uses_centroid
= false;
2369 nir_foreach_variable(variable
, &nir
->inputs
) {
2370 if (glsl_get_base_type(glsl_without_array(variable
->type
)) != GLSL_TYPE_FLOAT
||
2371 variable
->data
.sample
)
2374 if (variable
->data
.centroid
)
2375 uses_centroid
= true;
2380 if (uses_center
&& uses_centroid
) {
2381 LLVMValueRef sel
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntSLT
, ctx
->abi
.prim_mask
, ctx
->ac
.i32_0
, "");
2382 ctx
->abi
.persp_centroid
= LLVMBuildSelect(ctx
->ac
.builder
, sel
, ctx
->abi
.persp_center
, ctx
->abi
.persp_centroid
, "");
2383 ctx
->abi
.linear_centroid
= LLVMBuildSelect(ctx
->ac
.builder
, sel
, ctx
->abi
.linear_center
, ctx
->abi
.linear_centroid
, "");
2388 scan_shader_output_decl(struct radv_shader_context
*ctx
,
2389 struct nir_variable
*variable
,
2390 struct nir_shader
*shader
,
2391 gl_shader_stage stage
)
2393 int idx
= variable
->data
.location
+ variable
->data
.index
;
2394 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
2395 uint64_t mask_attribs
;
2397 variable
->data
.driver_location
= idx
* 4;
2399 /* tess ctrl has it's own load/store paths for outputs */
2400 if (stage
== MESA_SHADER_TESS_CTRL
)
2403 if (variable
->data
.compact
) {
2404 unsigned component_count
= variable
->data
.location_frac
+
2405 glsl_get_length(variable
->type
);
2406 attrib_count
= (component_count
+ 3) / 4;
2409 mask_attribs
= ((1ull << attrib_count
) - 1) << idx
;
2410 if (stage
== MESA_SHADER_VERTEX
||
2411 stage
== MESA_SHADER_TESS_EVAL
||
2412 stage
== MESA_SHADER_GEOMETRY
) {
2413 if (idx
== VARYING_SLOT_CLIP_DIST0
) {
2414 if (stage
== MESA_SHADER_VERTEX
) {
2415 ctx
->shader_info
->vs
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
2416 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
2417 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
<<= shader
->info
.clip_distance_array_size
;
2419 if (stage
== MESA_SHADER_TESS_EVAL
) {
2420 ctx
->shader_info
->tes
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
2421 ctx
->shader_info
->tes
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
2422 ctx
->shader_info
->tes
.outinfo
.cull_dist_mask
<<= shader
->info
.clip_distance_array_size
;
2424 if (stage
== MESA_SHADER_GEOMETRY
) {
2425 ctx
->shader_info
->vs
.outinfo
.clip_dist_mask
= (1 << shader
->info
.clip_distance_array_size
) - 1;
2426 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
= (1 << shader
->info
.cull_distance_array_size
) - 1;
2427 ctx
->shader_info
->vs
.outinfo
.cull_dist_mask
<<= shader
->info
.clip_distance_array_size
;
2432 ctx
->output_mask
|= mask_attribs
;
2436 /* Initialize arguments for the shader export intrinsic */
2438 si_llvm_init_export_args(struct radv_shader_context
*ctx
,
2439 LLVMValueRef
*values
,
2440 unsigned enabled_channels
,
2442 struct ac_export_args
*args
)
2444 /* Specify the channels that are enabled. */
2445 args
->enabled_channels
= enabled_channels
;
2447 /* Specify whether the EXEC mask represents the valid mask */
2448 args
->valid_mask
= 0;
2450 /* Specify whether this is the last export */
2453 /* Specify the target we are exporting */
2454 args
->target
= target
;
2456 args
->compr
= false;
2457 args
->out
[0] = LLVMGetUndef(ctx
->ac
.f32
);
2458 args
->out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
2459 args
->out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
2460 args
->out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
2465 bool is_16bit
= ac_get_type_size(LLVMTypeOf(values
[0])) == 2;
2466 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
2467 unsigned index
= target
- V_008DFC_SQ_EXP_MRT
;
2468 unsigned col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * index
)) & 0xf;
2469 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> index
) & 1;
2470 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> index
) & 1;
2473 LLVMValueRef (*packf
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2]) = NULL
;
2474 LLVMValueRef (*packi
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2],
2475 unsigned bits
, bool hi
) = NULL
;
2477 switch(col_format
) {
2478 case V_028714_SPI_SHADER_ZERO
:
2479 args
->enabled_channels
= 0; /* writemask */
2480 args
->target
= V_008DFC_SQ_EXP_NULL
;
2483 case V_028714_SPI_SHADER_32_R
:
2484 args
->enabled_channels
= 1;
2485 args
->out
[0] = values
[0];
2488 case V_028714_SPI_SHADER_32_GR
:
2489 args
->enabled_channels
= 0x3;
2490 args
->out
[0] = values
[0];
2491 args
->out
[1] = values
[1];
2494 case V_028714_SPI_SHADER_32_AR
:
2495 if (ctx
->ac
.chip_class
>= GFX10
) {
2496 args
->enabled_channels
= 0x3;
2497 args
->out
[0] = values
[0];
2498 args
->out
[1] = values
[3];
2500 args
->enabled_channels
= 0x9;
2501 args
->out
[0] = values
[0];
2502 args
->out
[3] = values
[3];
2506 case V_028714_SPI_SHADER_FP16_ABGR
:
2507 args
->enabled_channels
= 0x5;
2508 packf
= ac_build_cvt_pkrtz_f16
;
2510 for (unsigned chan
= 0; chan
< 4; chan
++)
2511 values
[chan
] = LLVMBuildFPExt(ctx
->ac
.builder
,
2517 case V_028714_SPI_SHADER_UNORM16_ABGR
:
2518 args
->enabled_channels
= 0x5;
2519 packf
= ac_build_cvt_pknorm_u16
;
2522 case V_028714_SPI_SHADER_SNORM16_ABGR
:
2523 args
->enabled_channels
= 0x5;
2524 packf
= ac_build_cvt_pknorm_i16
;
2527 case V_028714_SPI_SHADER_UINT16_ABGR
:
2528 args
->enabled_channels
= 0x5;
2529 packi
= ac_build_cvt_pk_u16
;
2531 for (unsigned chan
= 0; chan
< 4; chan
++)
2532 values
[chan
] = LLVMBuildZExt(ctx
->ac
.builder
,
2533 ac_to_integer(&ctx
->ac
, values
[chan
]),
2538 case V_028714_SPI_SHADER_SINT16_ABGR
:
2539 args
->enabled_channels
= 0x5;
2540 packi
= ac_build_cvt_pk_i16
;
2542 for (unsigned chan
= 0; chan
< 4; chan
++)
2543 values
[chan
] = LLVMBuildSExt(ctx
->ac
.builder
,
2544 ac_to_integer(&ctx
->ac
, values
[chan
]),
2550 case V_028714_SPI_SHADER_32_ABGR
:
2551 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
2555 /* Pack f16 or norm_i16/u16. */
2557 for (chan
= 0; chan
< 2; chan
++) {
2558 LLVMValueRef pack_args
[2] = {
2560 values
[2 * chan
+ 1]
2562 LLVMValueRef packed
;
2564 packed
= packf(&ctx
->ac
, pack_args
);
2565 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2567 args
->compr
= 1; /* COMPR flag */
2572 for (chan
= 0; chan
< 2; chan
++) {
2573 LLVMValueRef pack_args
[2] = {
2574 ac_to_integer(&ctx
->ac
, values
[2 * chan
]),
2575 ac_to_integer(&ctx
->ac
, values
[2 * chan
+ 1])
2577 LLVMValueRef packed
;
2579 packed
= packi(&ctx
->ac
, pack_args
,
2580 is_int8
? 8 : is_int10
? 10 : 16,
2582 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2584 args
->compr
= 1; /* COMPR flag */
2590 for (unsigned chan
= 0; chan
< 4; chan
++) {
2591 values
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, values
[chan
], ctx
->ac
.i16
, "");
2592 args
->out
[chan
] = LLVMBuildZExt(ctx
->ac
.builder
, values
[chan
], ctx
->ac
.i32
, "");
2595 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
2597 for (unsigned i
= 0; i
< 4; ++i
)
2598 args
->out
[i
] = ac_to_float(&ctx
->ac
, args
->out
[i
]);
2602 radv_export_param(struct radv_shader_context
*ctx
, unsigned index
,
2603 LLVMValueRef
*values
, unsigned enabled_channels
)
2605 struct ac_export_args args
;
2607 si_llvm_init_export_args(ctx
, values
, enabled_channels
,
2608 V_008DFC_SQ_EXP_PARAM
+ index
, &args
);
2609 ac_build_export(&ctx
->ac
, &args
);
2613 radv_load_output(struct radv_shader_context
*ctx
, unsigned index
, unsigned chan
)
2615 LLVMValueRef output
= ctx
->abi
.outputs
[ac_llvm_reg_index_soa(index
, chan
)];
2616 return LLVMBuildLoad(ctx
->ac
.builder
, output
, "");
2620 radv_emit_stream_output(struct radv_shader_context
*ctx
,
2621 LLVMValueRef
const *so_buffers
,
2622 LLVMValueRef
const *so_write_offsets
,
2623 const struct radv_stream_output
*output
,
2624 struct radv_shader_output_values
*shader_out
)
2626 unsigned num_comps
= util_bitcount(output
->component_mask
);
2627 unsigned buf
= output
->buffer
;
2628 unsigned offset
= output
->offset
;
2630 LLVMValueRef out
[4];
2632 assert(num_comps
&& num_comps
<= 4);
2633 if (!num_comps
|| num_comps
> 4)
2636 /* Get the first component. */
2637 start
= ffs(output
->component_mask
) - 1;
2639 /* Load the output as int. */
2640 for (int i
= 0; i
< num_comps
; i
++) {
2641 out
[i
] = ac_to_integer(&ctx
->ac
, shader_out
->values
[start
+ i
]);
2644 /* Pack the output. */
2645 LLVMValueRef vdata
= NULL
;
2647 switch (num_comps
) {
2648 case 1: /* as i32 */
2651 case 2: /* as v2i32 */
2652 case 3: /* as v4i32 (aligned to 4) */
2653 out
[3] = LLVMGetUndef(ctx
->ac
.i32
);
2655 case 4: /* as v4i32 */
2656 vdata
= ac_build_gather_values(&ctx
->ac
, out
,
2657 !ac_has_vec3_support(ctx
->ac
.chip_class
, false) ?
2658 util_next_power_of_two(num_comps
) :
2663 ac_build_buffer_store_dword(&ctx
->ac
, so_buffers
[buf
],
2664 vdata
, num_comps
, so_write_offsets
[buf
],
2665 ctx
->ac
.i32_0
, offset
,
2666 ac_glc
| ac_slc
, false);
2670 radv_emit_streamout(struct radv_shader_context
*ctx
, unsigned stream
)
2672 struct ac_build_if_state if_ctx
;
2675 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2676 assert(ctx
->streamout_config
);
2677 LLVMValueRef so_vtx_count
=
2678 ac_build_bfe(&ctx
->ac
, ctx
->streamout_config
,
2679 LLVMConstInt(ctx
->ac
.i32
, 16, false),
2680 LLVMConstInt(ctx
->ac
.i32
, 7, false), false);
2682 LLVMValueRef tid
= ac_get_thread_id(&ctx
->ac
);
2684 /* can_emit = tid < so_vtx_count; */
2685 LLVMValueRef can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
,
2686 tid
, so_vtx_count
, "");
2688 /* Emit the streamout code conditionally. This actually avoids
2689 * out-of-bounds buffer access. The hw tells us via the SGPR
2690 * (so_vtx_count) which threads are allowed to emit streamout data.
2692 ac_nir_build_if(&if_ctx
, ctx
, can_emit
);
2694 /* The buffer offset is computed as follows:
2695 * ByteOffset = streamout_offset[buffer_id]*4 +
2696 * (streamout_write_index + thread_id)*stride[buffer_id] +
2699 LLVMValueRef so_write_index
= ctx
->streamout_write_idx
;
2701 /* Compute (streamout_write_index + thread_id). */
2703 LLVMBuildAdd(ctx
->ac
.builder
, so_write_index
, tid
, "");
2705 /* Load the descriptor and compute the write offset for each
2708 LLVMValueRef so_write_offset
[4] = {};
2709 LLVMValueRef so_buffers
[4] = {};
2710 LLVMValueRef buf_ptr
= ctx
->streamout_buffers
;
2712 for (i
= 0; i
< 4; i
++) {
2713 uint16_t stride
= ctx
->shader_info
->info
.so
.strides
[i
];
2718 LLVMValueRef offset
=
2719 LLVMConstInt(ctx
->ac
.i32
, i
, false);
2721 so_buffers
[i
] = ac_build_load_to_sgpr(&ctx
->ac
,
2724 LLVMValueRef so_offset
= ctx
->streamout_offset
[i
];
2726 so_offset
= LLVMBuildMul(ctx
->ac
.builder
, so_offset
,
2727 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
2729 so_write_offset
[i
] =
2730 ac_build_imad(&ctx
->ac
, so_write_index
,
2731 LLVMConstInt(ctx
->ac
.i32
,
2736 /* Write streamout data. */
2737 for (i
= 0; i
< ctx
->shader_info
->info
.so
.num_outputs
; i
++) {
2738 struct radv_shader_output_values shader_out
= {};
2739 struct radv_stream_output
*output
=
2740 &ctx
->shader_info
->info
.so
.outputs
[i
];
2742 if (stream
!= output
->stream
)
2745 for (int j
= 0; j
< 4; j
++) {
2746 shader_out
.values
[j
] =
2747 radv_load_output(ctx
, output
->location
, j
);
2750 radv_emit_stream_output(ctx
, so_buffers
,so_write_offset
,
2751 output
, &shader_out
);
2754 ac_nir_build_endif(&if_ctx
);
2758 radv_build_param_exports(struct radv_shader_context
*ctx
,
2759 struct radv_shader_output_values
*outputs
,
2761 struct radv_vs_output_info
*outinfo
,
2762 bool export_clip_dists
)
2764 unsigned param_count
= 0;
2766 for (unsigned i
= 0; i
< noutput
; i
++) {
2767 unsigned slot_name
= outputs
[i
].slot_name
;
2768 unsigned usage_mask
= outputs
[i
].usage_mask
;
2770 if (slot_name
!= VARYING_SLOT_LAYER
&&
2771 slot_name
!= VARYING_SLOT_PRIMITIVE_ID
&&
2772 slot_name
!= VARYING_SLOT_CLIP_DIST0
&&
2773 slot_name
!= VARYING_SLOT_CLIP_DIST1
&&
2774 slot_name
< VARYING_SLOT_VAR0
)
2777 if ((slot_name
== VARYING_SLOT_CLIP_DIST0
||
2778 slot_name
== VARYING_SLOT_CLIP_DIST1
) && !export_clip_dists
)
2781 radv_export_param(ctx
, param_count
, outputs
[i
].values
, usage_mask
);
2783 assert(i
< ARRAY_SIZE(outinfo
->vs_output_param_offset
));
2784 outinfo
->vs_output_param_offset
[slot_name
] = param_count
++;
2787 outinfo
->param_exports
= param_count
;
2790 /* Generate export instructions for hardware VS shader stage or NGG GS stage
2791 * (position and parameter data only).
2794 radv_llvm_export_vs(struct radv_shader_context
*ctx
,
2795 struct radv_shader_output_values
*outputs
,
2797 struct radv_vs_output_info
*outinfo
,
2798 bool export_clip_dists
)
2800 LLVMValueRef psize_value
= NULL
, layer_value
= NULL
, viewport_value
= NULL
;
2801 struct ac_export_args pos_args
[4] = {};
2802 unsigned pos_idx
, index
;
2805 /* Build position exports */
2806 for (i
= 0; i
< noutput
; i
++) {
2807 switch (outputs
[i
].slot_name
) {
2808 case VARYING_SLOT_POS
:
2809 si_llvm_init_export_args(ctx
, outputs
[i
].values
, 0xf,
2810 V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
2812 case VARYING_SLOT_PSIZ
:
2813 psize_value
= outputs
[i
].values
[0];
2815 case VARYING_SLOT_LAYER
:
2816 layer_value
= outputs
[i
].values
[0];
2818 case VARYING_SLOT_VIEWPORT
:
2819 viewport_value
= outputs
[i
].values
[0];
2821 case VARYING_SLOT_CLIP_DIST0
:
2822 case VARYING_SLOT_CLIP_DIST1
:
2823 index
= 2 + outputs
[i
].slot_index
;
2824 si_llvm_init_export_args(ctx
, outputs
[i
].values
, 0xf,
2825 V_008DFC_SQ_EXP_POS
+ index
,
2833 /* We need to add the position output manually if it's missing. */
2834 if (!pos_args
[0].out
[0]) {
2835 pos_args
[0].enabled_channels
= 0xf; /* writemask */
2836 pos_args
[0].valid_mask
= 0; /* EXEC mask */
2837 pos_args
[0].done
= 0; /* last export? */
2838 pos_args
[0].target
= V_008DFC_SQ_EXP_POS
;
2839 pos_args
[0].compr
= 0; /* COMPR flag */
2840 pos_args
[0].out
[0] = ctx
->ac
.f32_0
; /* X */
2841 pos_args
[0].out
[1] = ctx
->ac
.f32_0
; /* Y */
2842 pos_args
[0].out
[2] = ctx
->ac
.f32_0
; /* Z */
2843 pos_args
[0].out
[3] = ctx
->ac
.f32_1
; /* W */
2846 if (outinfo
->writes_pointsize
||
2847 outinfo
->writes_layer
||
2848 outinfo
->writes_viewport_index
) {
2849 pos_args
[1].enabled_channels
= ((outinfo
->writes_pointsize
== true ? 1 : 0) |
2850 (outinfo
->writes_layer
== true ? 4 : 0));
2851 pos_args
[1].valid_mask
= 0;
2852 pos_args
[1].done
= 0;
2853 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
2854 pos_args
[1].compr
= 0;
2855 pos_args
[1].out
[0] = ctx
->ac
.f32_0
; /* X */
2856 pos_args
[1].out
[1] = ctx
->ac
.f32_0
; /* Y */
2857 pos_args
[1].out
[2] = ctx
->ac
.f32_0
; /* Z */
2858 pos_args
[1].out
[3] = ctx
->ac
.f32_0
; /* W */
2860 if (outinfo
->writes_pointsize
== true)
2861 pos_args
[1].out
[0] = psize_value
;
2862 if (outinfo
->writes_layer
== true)
2863 pos_args
[1].out
[2] = layer_value
;
2864 if (outinfo
->writes_viewport_index
== true) {
2865 if (ctx
->options
->chip_class
>= GFX9
) {
2866 /* GFX9 has the layer in out.z[10:0] and the viewport
2867 * index in out.z[19:16].
2869 LLVMValueRef v
= viewport_value
;
2870 v
= ac_to_integer(&ctx
->ac
, v
);
2871 v
= LLVMBuildShl(ctx
->ac
.builder
, v
,
2872 LLVMConstInt(ctx
->ac
.i32
, 16, false),
2874 v
= LLVMBuildOr(ctx
->ac
.builder
, v
,
2875 ac_to_integer(&ctx
->ac
, pos_args
[1].out
[2]), "");
2877 pos_args
[1].out
[2] = ac_to_float(&ctx
->ac
, v
);
2878 pos_args
[1].enabled_channels
|= 1 << 2;
2880 pos_args
[1].out
[3] = viewport_value
;
2881 pos_args
[1].enabled_channels
|= 1 << 3;
2886 for (i
= 0; i
< 4; i
++) {
2887 if (pos_args
[i
].out
[0])
2888 outinfo
->pos_exports
++;
2891 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
2892 * Setting valid_mask=1 prevents it and has no other effect.
2894 if (ctx
->ac
.family
== CHIP_NAVI10
||
2895 ctx
->ac
.family
== CHIP_NAVI12
||
2896 ctx
->ac
.family
== CHIP_NAVI14
)
2897 pos_args
[0].valid_mask
= 1;
2900 for (i
= 0; i
< 4; i
++) {
2901 if (!pos_args
[i
].out
[0])
2904 /* Specify the target we are exporting */
2905 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
2907 if (pos_idx
== outinfo
->pos_exports
)
2908 /* Specify that this is the last export */
2909 pos_args
[i
].done
= 1;
2911 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
2914 /* Build parameter exports */
2915 radv_build_param_exports(ctx
, outputs
, noutput
, outinfo
, export_clip_dists
);
2919 handle_vs_outputs_post(struct radv_shader_context
*ctx
,
2920 bool export_prim_id
,
2921 bool export_clip_dists
,
2922 struct radv_vs_output_info
*outinfo
)
2924 struct radv_shader_output_values
*outputs
;
2925 unsigned noutput
= 0;
2927 if (ctx
->options
->key
.has_multiview_view_index
) {
2928 LLVMValueRef
* tmp_out
= &ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
2930 for(unsigned i
= 0; i
< 4; ++i
)
2931 ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, i
)] =
2932 ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
2935 LLVMBuildStore(ctx
->ac
.builder
, ac_to_float(&ctx
->ac
, ctx
->abi
.view_index
), *tmp_out
);
2936 ctx
->output_mask
|= 1ull << VARYING_SLOT_LAYER
;
2939 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
2940 sizeof(outinfo
->vs_output_param_offset
));
2941 outinfo
->pos_exports
= 0;
2943 if (ctx
->output_mask
& (1ull << VARYING_SLOT_PSIZ
)) {
2944 outinfo
->writes_pointsize
= true;
2947 if (ctx
->output_mask
& (1ull << VARYING_SLOT_LAYER
)) {
2948 outinfo
->writes_layer
= true;
2951 if (ctx
->output_mask
& (1ull << VARYING_SLOT_VIEWPORT
)) {
2952 outinfo
->writes_viewport_index
= true;
2955 if (ctx
->shader_info
->info
.so
.num_outputs
&&
2956 !ctx
->is_gs_copy_shader
) {
2957 /* The GS copy shader emission already emits streamout. */
2958 radv_emit_streamout(ctx
, 0);
2961 /* Allocate a temporary array for the output values. */
2962 unsigned num_outputs
= util_bitcount64(ctx
->output_mask
) + export_prim_id
;
2963 outputs
= malloc(num_outputs
* sizeof(outputs
[0]));
2965 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2966 if (!(ctx
->output_mask
& (1ull << i
)))
2969 outputs
[noutput
].slot_name
= i
;
2970 outputs
[noutput
].slot_index
= i
== VARYING_SLOT_CLIP_DIST1
;
2972 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
2973 !ctx
->is_gs_copy_shader
) {
2974 outputs
[noutput
].usage_mask
=
2975 ctx
->shader_info
->info
.vs
.output_usage_mask
[i
];
2976 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
2977 outputs
[noutput
].usage_mask
=
2978 ctx
->shader_info
->info
.tes
.output_usage_mask
[i
];
2980 assert(ctx
->is_gs_copy_shader
);
2981 outputs
[noutput
].usage_mask
=
2982 ctx
->shader_info
->info
.gs
.output_usage_mask
[i
];
2985 for (unsigned j
= 0; j
< 4; j
++) {
2986 outputs
[noutput
].values
[j
] =
2987 ac_to_float(&ctx
->ac
, radv_load_output(ctx
, i
, j
));
2993 /* Export PrimitiveID. */
2994 if (export_prim_id
) {
2995 outinfo
->export_prim_id
= true;
2997 outputs
[noutput
].slot_name
= VARYING_SLOT_PRIMITIVE_ID
;
2998 outputs
[noutput
].slot_index
= 0;
2999 outputs
[noutput
].usage_mask
= 0x1;
3000 outputs
[noutput
].values
[0] = ctx
->vs_prim_id
;
3001 for (unsigned j
= 1; j
< 4; j
++)
3002 outputs
[noutput
].values
[j
] = ctx
->ac
.f32_0
;
3006 radv_llvm_export_vs(ctx
, outputs
, noutput
, outinfo
, export_clip_dists
);
3012 handle_es_outputs_post(struct radv_shader_context
*ctx
,
3013 struct radv_es_output_info
*outinfo
)
3016 uint64_t max_output_written
= 0;
3017 LLVMValueRef lds_base
= NULL
;
3019 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3022 if (!(ctx
->output_mask
& (1ull << i
)))
3025 param_index
= shader_io_get_unique_index(i
);
3027 max_output_written
= MAX2(param_index
, max_output_written
);
3030 outinfo
->esgs_itemsize
= (max_output_written
+ 1) * 16;
3032 if (ctx
->ac
.chip_class
>= GFX9
) {
3033 unsigned itemsize_dw
= outinfo
->esgs_itemsize
/ 4;
3034 LLVMValueRef vertex_idx
= ac_get_thread_id(&ctx
->ac
);
3035 LLVMValueRef wave_idx
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 24, 4);
3036 vertex_idx
= LLVMBuildOr(ctx
->ac
.builder
, vertex_idx
,
3037 LLVMBuildMul(ctx
->ac
.builder
, wave_idx
,
3038 LLVMConstInt(ctx
->ac
.i32
,
3039 ctx
->ac
.wave_size
, false), ""), "");
3040 lds_base
= LLVMBuildMul(ctx
->ac
.builder
, vertex_idx
,
3041 LLVMConstInt(ctx
->ac
.i32
, itemsize_dw
, 0), "");
3044 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3045 LLVMValueRef dw_addr
= NULL
;
3046 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
3047 unsigned output_usage_mask
;
3050 if (!(ctx
->output_mask
& (1ull << i
)))
3053 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
3055 ctx
->shader_info
->info
.vs
.output_usage_mask
[i
];
3057 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
3059 ctx
->shader_info
->info
.tes
.output_usage_mask
[i
];
3062 param_index
= shader_io_get_unique_index(i
);
3065 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3066 LLVMConstInt(ctx
->ac
.i32
, param_index
* 4, false),
3070 for (j
= 0; j
< 4; j
++) {
3071 if (!(output_usage_mask
& (1 << j
)))
3074 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
3075 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
3076 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
3078 if (ctx
->ac
.chip_class
>= GFX9
) {
3079 LLVMValueRef dw_addr_offset
=
3080 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
3081 LLVMConstInt(ctx
->ac
.i32
,
3084 ac_lds_store(&ctx
->ac
, dw_addr_offset
, out_val
);
3086 ac_build_buffer_store_dword(&ctx
->ac
,
3089 NULL
, ctx
->es2gs_offset
,
3090 (4 * param_index
+ j
) * 4,
3091 ac_glc
| ac_slc
, true);
3098 handle_ls_outputs_post(struct radv_shader_context
*ctx
)
3100 LLVMValueRef vertex_id
= ctx
->rel_auto_id
;
3101 uint32_t num_tcs_inputs
= util_last_bit64(ctx
->shader_info
->info
.vs
.ls_outputs_written
);
3102 LLVMValueRef vertex_dw_stride
= LLVMConstInt(ctx
->ac
.i32
, num_tcs_inputs
* 4, false);
3103 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->ac
.builder
, vertex_id
,
3104 vertex_dw_stride
, "");
3106 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3107 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
3109 if (!(ctx
->output_mask
& (1ull << i
)))
3112 int param
= shader_io_get_unique_index(i
);
3113 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_dw_addr
,
3114 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false),
3116 for (unsigned j
= 0; j
< 4; j
++) {
3117 LLVMValueRef value
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
3118 value
= ac_to_integer(&ctx
->ac
, value
);
3119 value
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
3120 ac_lds_store(&ctx
->ac
, dw_addr
, value
);
3121 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
, ctx
->ac
.i32_1
, "");
3126 static LLVMValueRef
get_wave_id_in_tg(struct radv_shader_context
*ctx
)
3128 return ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 24, 4);
3131 static LLVMValueRef
get_tgsize(struct radv_shader_context
*ctx
)
3133 return ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 28, 4);
3136 static LLVMValueRef
get_thread_id_in_tg(struct radv_shader_context
*ctx
)
3138 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3140 tmp
= LLVMBuildMul(builder
, get_wave_id_in_tg(ctx
),
3141 LLVMConstInt(ctx
->ac
.i32
, ctx
->ac
.wave_size
, false), "");
3142 return LLVMBuildAdd(builder
, tmp
, ac_get_thread_id(&ctx
->ac
), "");
3145 static LLVMValueRef
ngg_get_vtx_cnt(struct radv_shader_context
*ctx
)
3147 return ac_build_bfe(&ctx
->ac
, ctx
->gs_tg_info
,
3148 LLVMConstInt(ctx
->ac
.i32
, 12, false),
3149 LLVMConstInt(ctx
->ac
.i32
, 9, false),
3153 static LLVMValueRef
ngg_get_prim_cnt(struct radv_shader_context
*ctx
)
3155 return ac_build_bfe(&ctx
->ac
, ctx
->gs_tg_info
,
3156 LLVMConstInt(ctx
->ac
.i32
, 22, false),
3157 LLVMConstInt(ctx
->ac
.i32
, 9, false),
3162 ngg_gs_get_vertex_storage(struct radv_shader_context
*ctx
)
3164 unsigned num_outputs
= util_bitcount64(ctx
->output_mask
);
3166 LLVMTypeRef elements
[2] = {
3167 LLVMArrayType(ctx
->ac
.i32
, 4 * num_outputs
),
3168 LLVMArrayType(ctx
->ac
.i8
, 4),
3170 LLVMTypeRef type
= LLVMStructTypeInContext(ctx
->ac
.context
, elements
, 2, false);
3171 type
= LLVMPointerType(LLVMArrayType(type
, 0), AC_ADDR_SPACE_LDS
);
3172 return LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->gs_ngg_emit
, type
, "");
3176 * Return a pointer to the LDS storage reserved for the N'th vertex, where N
3177 * is in emit order; that is:
3178 * - during the epilogue, N is the threadidx (relative to the entire threadgroup)
3179 * - during vertex emit, i.e. while the API GS shader invocation is running,
3180 * N = threadidx * gs_max_out_vertices + emitidx
3182 * Goals of the LDS memory layout:
3183 * 1. Eliminate bank conflicts on write for geometry shaders that have all emits
3184 * in uniform control flow
3185 * 2. Eliminate bank conflicts on read for export if, additionally, there is no
3187 * 3. Agnostic to the number of waves (since we don't know it before compiling)
3188 * 4. Allow coalescing of LDS instructions (ds_write_b128 etc.)
3189 * 5. Avoid wasting memory.
3191 * We use an AoS layout due to point 4 (this also helps point 3). In an AoS
3192 * layout, elimination of bank conflicts requires that each vertex occupy an
3193 * odd number of dwords. We use the additional dword to store the output stream
3194 * index as well as a flag to indicate whether this vertex ends a primitive
3195 * for rasterization.
3197 * Swizzling is required to satisfy points 1 and 2 simultaneously.
3199 * Vertices are stored in export order (gsthread * gs_max_out_vertices + emitidx).
3200 * Indices are swizzled in groups of 32, which ensures point 1 without
3201 * disturbing point 2.
3203 * \return an LDS pointer to type {[N x i32], [4 x i8]}
3206 ngg_gs_vertex_ptr(struct radv_shader_context
*ctx
, LLVMValueRef vertexidx
)
3208 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3209 LLVMValueRef storage
= ngg_gs_get_vertex_storage(ctx
);
3211 /* gs_max_out_vertices = 2^(write_stride_2exp) * some odd number */
3212 unsigned write_stride_2exp
= ffs(ctx
->gs_max_out_vertices
) - 1;
3213 if (write_stride_2exp
) {
3215 LLVMBuildLShr(builder
, vertexidx
,
3216 LLVMConstInt(ctx
->ac
.i32
, 5, false), "");
3217 LLVMValueRef swizzle
=
3218 LLVMBuildAnd(builder
, row
,
3219 LLVMConstInt(ctx
->ac
.i32
, (1u << write_stride_2exp
) - 1,
3221 vertexidx
= LLVMBuildXor(builder
, vertexidx
, swizzle
, "");
3224 return ac_build_gep0(&ctx
->ac
, storage
, vertexidx
);
3228 ngg_gs_emit_vertex_ptr(struct radv_shader_context
*ctx
, LLVMValueRef gsthread
,
3229 LLVMValueRef emitidx
)
3231 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3234 tmp
= LLVMConstInt(ctx
->ac
.i32
, ctx
->gs_max_out_vertices
, false);
3235 tmp
= LLVMBuildMul(builder
, tmp
, gsthread
, "");
3236 const LLVMValueRef vertexidx
= LLVMBuildAdd(builder
, tmp
, emitidx
, "");
3237 return ngg_gs_vertex_ptr(ctx
, vertexidx
);
3240 /* Send GS Alloc Req message from the first wave of the group to SPI.
3241 * Message payload is:
3242 * - bits 0..10: vertices in group
3243 * - bits 12..22: primitives in group
3245 static void build_sendmsg_gs_alloc_req(struct radv_shader_context
*ctx
,
3246 LLVMValueRef vtx_cnt
,
3247 LLVMValueRef prim_cnt
)
3249 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3252 tmp
= LLVMBuildICmp(builder
, LLVMIntEQ
, get_wave_id_in_tg(ctx
), ctx
->ac
.i32_0
, "");
3253 ac_build_ifcc(&ctx
->ac
, tmp
, 5020);
3255 tmp
= LLVMBuildShl(builder
, prim_cnt
, LLVMConstInt(ctx
->ac
.i32
, 12, false),"");
3256 tmp
= LLVMBuildOr(builder
, tmp
, vtx_cnt
, "");
3257 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_ALLOC_REQ
, tmp
);
3259 ac_build_endif(&ctx
->ac
, 5020);
3263 unsigned num_vertices
;
3264 LLVMValueRef isnull
;
3265 LLVMValueRef index
[3];
3266 LLVMValueRef edgeflag
[3];
3269 static void build_export_prim(struct radv_shader_context
*ctx
,
3270 const struct ngg_prim
*prim
)
3272 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3273 struct ac_export_args args
;
3276 tmp
= LLVMBuildZExt(builder
, prim
->isnull
, ctx
->ac
.i32
, "");
3277 args
.out
[0] = LLVMBuildShl(builder
, tmp
, LLVMConstInt(ctx
->ac
.i32
, 31, false), "");
3279 for (unsigned i
= 0; i
< prim
->num_vertices
; ++i
) {
3280 tmp
= LLVMBuildShl(builder
, prim
->index
[i
],
3281 LLVMConstInt(ctx
->ac
.i32
, 10 * i
, false), "");
3282 args
.out
[0] = LLVMBuildOr(builder
, args
.out
[0], tmp
, "");
3283 tmp
= LLVMBuildZExt(builder
, prim
->edgeflag
[i
], ctx
->ac
.i32
, "");
3284 tmp
= LLVMBuildShl(builder
, tmp
,
3285 LLVMConstInt(ctx
->ac
.i32
, 10 * i
+ 9, false), "");
3286 args
.out
[0] = LLVMBuildOr(builder
, args
.out
[0], tmp
, "");
3289 args
.out
[0] = LLVMBuildBitCast(builder
, args
.out
[0], ctx
->ac
.f32
, "");
3290 args
.out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
3291 args
.out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
3292 args
.out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
3294 args
.target
= V_008DFC_SQ_EXP_PRIM
;
3295 args
.enabled_channels
= 1;
3297 args
.valid_mask
= false;
3300 ac_build_export(&ctx
->ac
, &args
);
3304 handle_ngg_outputs_post(struct radv_shader_context
*ctx
)
3306 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3307 struct ac_build_if_state if_state
;
3308 unsigned num_vertices
= 3;
3311 assert((ctx
->stage
== MESA_SHADER_VERTEX
||
3312 ctx
->stage
== MESA_SHADER_TESS_EVAL
) && !ctx
->is_gs_copy_shader
);
3314 LLVMValueRef prims_in_wave
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 8, 8);
3315 LLVMValueRef vtx_in_wave
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 0, 8);
3316 LLVMValueRef is_gs_thread
= LLVMBuildICmp(builder
, LLVMIntULT
,
3317 ac_get_thread_id(&ctx
->ac
), prims_in_wave
, "");
3318 LLVMValueRef is_es_thread
= LLVMBuildICmp(builder
, LLVMIntULT
,
3319 ac_get_thread_id(&ctx
->ac
), vtx_in_wave
, "");
3320 LLVMValueRef vtxindex
[] = {
3321 ac_unpack_param(&ctx
->ac
, ctx
->gs_vtx_offset
[0], 0, 16),
3322 ac_unpack_param(&ctx
->ac
, ctx
->gs_vtx_offset
[0], 16, 16),
3323 ac_unpack_param(&ctx
->ac
, ctx
->gs_vtx_offset
[2], 0, 16),
3326 /* TODO: streamout */
3328 /* Copy Primitive IDs from GS threads to the LDS address corresponding
3329 * to the ES thread of the provoking vertex.
3331 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
3332 ctx
->options
->key
.vs_common_out
.export_prim_id
) {
3333 /* TODO: streamout */
3335 ac_build_ifcc(&ctx
->ac
, is_gs_thread
, 5400);
3336 /* Extract the PROVOKING_VTX_INDEX field. */
3337 LLVMValueRef provoking_vtx_in_prim
=
3338 LLVMConstInt(ctx
->ac
.i32
, 0, false);
3340 /* provoking_vtx_index = vtxindex[provoking_vtx_in_prim]; */
3341 LLVMValueRef indices
= ac_build_gather_values(&ctx
->ac
, vtxindex
, 3);
3342 LLVMValueRef provoking_vtx_index
=
3343 LLVMBuildExtractElement(builder
, indices
, provoking_vtx_in_prim
, "");
3345 LLVMBuildStore(builder
, ctx
->abi
.gs_prim_id
,
3346 ac_build_gep0(&ctx
->ac
, ctx
->esgs_ring
, provoking_vtx_index
));
3347 ac_build_endif(&ctx
->ac
, 5400);
3350 /* TODO: primitive culling */
3352 build_sendmsg_gs_alloc_req(ctx
, ngg_get_vtx_cnt(ctx
), ngg_get_prim_cnt(ctx
));
3354 /* TODO: streamout queries */
3355 /* Export primitive data to the index buffer. Format is:
3356 * - bits 0..8: index 0
3357 * - bit 9: edge flag 0
3358 * - bits 10..18: index 1
3359 * - bit 19: edge flag 1
3360 * - bits 20..28: index 2
3361 * - bit 29: edge flag 2
3362 * - bit 31: null primitive (skip)
3364 * For the first version, we will always build up all three indices
3365 * independent of the primitive type. The additional garbage data
3368 * TODO: culling depends on the primitive type, so can have some
3371 ac_nir_build_if(&if_state
, ctx
, is_gs_thread
);
3373 struct ngg_prim prim
= {};
3375 prim
.num_vertices
= num_vertices
;
3376 prim
.isnull
= ctx
->ac
.i1false
;
3377 memcpy(prim
.index
, vtxindex
, sizeof(vtxindex
[0]) * 3);
3379 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
3380 tmp
= LLVMBuildLShr(builder
, ctx
->abi
.gs_invocation_id
,
3381 LLVMConstInt(ctx
->ac
.i32
, 8 + i
, false), "");
3382 prim
.edgeflag
[i
] = LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
3385 build_export_prim(ctx
, &prim
);
3387 ac_nir_build_endif(&if_state
);
3389 /* Export per-vertex data (positions and parameters). */
3390 ac_nir_build_if(&if_state
, ctx
, is_es_thread
);
3392 struct radv_vs_output_info
*outinfo
=
3393 ctx
->stage
== MESA_SHADER_TESS_EVAL
? &ctx
->shader_info
->tes
.outinfo
: &ctx
->shader_info
->vs
.outinfo
;
3395 /* Exporting the primitive ID is handled below. */
3396 /* TODO: use the new VS export path */
3397 handle_vs_outputs_post(ctx
, false,
3398 ctx
->options
->key
.vs_common_out
.export_clip_dists
,
3401 if (ctx
->options
->key
.vs_common_out
.export_prim_id
) {
3402 unsigned param_count
= outinfo
->param_exports
;
3403 LLVMValueRef values
[4];
3405 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
3406 /* Wait for GS stores to finish. */
3407 ac_build_s_barrier(&ctx
->ac
);
3409 tmp
= ac_build_gep0(&ctx
->ac
, ctx
->esgs_ring
,
3410 get_thread_id_in_tg(ctx
));
3411 values
[0] = LLVMBuildLoad(builder
, tmp
, "");
3413 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
3414 values
[0] = ctx
->abi
.tes_patch_id
;
3417 values
[0] = ac_to_float(&ctx
->ac
, values
[0]);
3418 for (unsigned j
= 1; j
< 4; j
++)
3419 values
[j
] = ctx
->ac
.f32_0
;
3421 radv_export_param(ctx
, param_count
, values
, 0x1);
3423 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
++;
3424 outinfo
->export_prim_id
= true;
3425 outinfo
->param_exports
= param_count
;
3428 ac_nir_build_endif(&if_state
);
3431 static void gfx10_ngg_gs_emit_prologue(struct radv_shader_context
*ctx
)
3433 /* Zero out the part of LDS scratch that is used to accumulate the
3434 * per-stream generated primitive count.
3436 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3437 LLVMValueRef scratchptr
= ctx
->gs_ngg_scratch
;
3438 LLVMValueRef tid
= get_thread_id_in_tg(ctx
);
3439 LLVMBasicBlockRef merge_block
;
3442 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
->ac
.builder
));
3443 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
3444 merge_block
= LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
3446 cond
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
3447 LLVMBuildCondBr(ctx
->ac
.builder
, cond
, then_block
, merge_block
);
3448 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, then_block
);
3450 LLVMValueRef ptr
= ac_build_gep0(&ctx
->ac
, scratchptr
, tid
);
3451 LLVMBuildStore(builder
, ctx
->ac
.i32_0
, ptr
);
3453 LLVMBuildBr(ctx
->ac
.builder
, merge_block
);
3454 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, merge_block
);
3456 ac_build_s_barrier(&ctx
->ac
);
3459 static void gfx10_ngg_gs_emit_epilogue_1(struct radv_shader_context
*ctx
)
3461 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3462 LLVMValueRef i8_0
= LLVMConstInt(ctx
->ac
.i8
, 0, false);
3465 /* Zero out remaining (non-emitted) primitive flags.
3467 * Note: Alternatively, we could pass the relevant gs_next_vertex to
3468 * the emit threads via LDS. This is likely worse in the expected
3469 * typical case where each GS thread emits the full set of
3472 for (unsigned stream
= 0; stream
< 4; ++stream
) {
3473 unsigned num_components
;
3476 ctx
->shader_info
->info
.gs
.num_stream_output_components
[stream
];
3477 if (!num_components
)
3480 const LLVMValueRef gsthread
= get_thread_id_in_tg(ctx
);
3482 ac_build_bgnloop(&ctx
->ac
, 5100);
3484 const LLVMValueRef vertexidx
=
3485 LLVMBuildLoad(builder
, ctx
->gs_next_vertex
[stream
], "");
3486 tmp
= LLVMBuildICmp(builder
, LLVMIntUGE
, vertexidx
,
3487 LLVMConstInt(ctx
->ac
.i32
, ctx
->gs_max_out_vertices
, false), "");
3488 ac_build_ifcc(&ctx
->ac
, tmp
, 5101);
3489 ac_build_break(&ctx
->ac
);
3490 ac_build_endif(&ctx
->ac
, 5101);
3492 tmp
= LLVMBuildAdd(builder
, vertexidx
, ctx
->ac
.i32_1
, "");
3493 LLVMBuildStore(builder
, tmp
, ctx
->gs_next_vertex
[stream
]);
3495 tmp
= ngg_gs_emit_vertex_ptr(ctx
, gsthread
, vertexidx
);
3496 LLVMValueRef gep_idx
[3] = {
3497 ctx
->ac
.i32_0
, /* implied C-style array */
3498 ctx
->ac
.i32_1
, /* second entry of struct */
3499 LLVMConstInt(ctx
->ac
.i32
, stream
, false),
3501 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3502 LLVMBuildStore(builder
, i8_0
, tmp
);
3504 ac_build_endloop(&ctx
->ac
, 5100);
3508 static void gfx10_ngg_gs_emit_epilogue_2(struct radv_shader_context
*ctx
)
3510 const unsigned verts_per_prim
= si_conv_gl_prim_to_vertices(ctx
->gs_output_prim
);
3511 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3512 LLVMValueRef tmp
, tmp2
;
3514 ac_build_s_barrier(&ctx
->ac
);
3516 const LLVMValueRef tid
= get_thread_id_in_tg(ctx
);
3517 LLVMValueRef num_emit_threads
= ngg_get_prim_cnt(ctx
);
3519 /* TODO: streamout */
3523 /* Determine vertex liveness. */
3524 LLVMValueRef vertliveptr
= ac_build_alloca(&ctx
->ac
, ctx
->ac
.i1
, "vertexlive");
3526 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, num_emit_threads
, "");
3527 ac_build_ifcc(&ctx
->ac
, tmp
, 5120);
3529 for (unsigned i
= 0; i
< verts_per_prim
; ++i
) {
3530 const LLVMValueRef primidx
=
3531 LLVMBuildAdd(builder
, tid
,
3532 LLVMConstInt(ctx
->ac
.i32
, i
, false), "");
3535 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, primidx
, num_emit_threads
, "");
3536 ac_build_ifcc(&ctx
->ac
, tmp
, 5121 + i
);
3539 /* Load primitive liveness */
3540 tmp
= ngg_gs_vertex_ptr(ctx
, primidx
);
3541 LLVMValueRef gep_idx
[3] = {
3542 ctx
->ac
.i32_0
, /* implicit C-style array */
3543 ctx
->ac
.i32_1
, /* second value of struct */
3544 ctx
->ac
.i32_0
, /* stream 0 */
3546 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3547 tmp
= LLVMBuildLoad(builder
, tmp
, "");
3548 const LLVMValueRef primlive
=
3549 LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
3551 tmp
= LLVMBuildLoad(builder
, vertliveptr
, "");
3552 tmp
= LLVMBuildOr(builder
, tmp
, primlive
, ""),
3553 LLVMBuildStore(builder
, tmp
, vertliveptr
);
3556 ac_build_endif(&ctx
->ac
, 5121 + i
);
3559 ac_build_endif(&ctx
->ac
, 5120);
3561 /* Inclusive scan addition across the current wave. */
3562 LLVMValueRef vertlive
= LLVMBuildLoad(builder
, vertliveptr
, "");
3563 struct ac_wg_scan vertlive_scan
= {};
3564 vertlive_scan
.op
= nir_op_iadd
;
3565 vertlive_scan
.enable_reduce
= true;
3566 vertlive_scan
.enable_exclusive
= true;
3567 vertlive_scan
.src
= vertlive
;
3568 vertlive_scan
.scratch
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, ctx
->ac
.i32_0
);
3569 vertlive_scan
.waveidx
= get_wave_id_in_tg(ctx
);
3570 vertlive_scan
.numwaves
= get_tgsize(ctx
);
3571 vertlive_scan
.maxwaves
= 8;
3573 ac_build_wg_scan(&ctx
->ac
, &vertlive_scan
);
3575 /* Skip all exports (including index exports) when possible. At least on
3576 * early gfx10 revisions this is also to avoid hangs.
3578 LLVMValueRef have_exports
=
3579 LLVMBuildICmp(builder
, LLVMIntNE
, vertlive_scan
.result_reduce
, ctx
->ac
.i32_0
, "");
3581 LLVMBuildSelect(builder
, have_exports
, num_emit_threads
, ctx
->ac
.i32_0
, "");
3583 /* Allocate export space. Send this message as early as possible, to
3584 * hide the latency of the SQ <-> SPI roundtrip.
3586 * Note: We could consider compacting primitives for export as well.
3587 * PA processes 1 non-null prim / clock, but it fetches 4 DW of
3588 * prim data per clock and skips null primitives at no additional
3589 * cost. So compacting primitives can only be beneficial when
3590 * there are 4 or more contiguous null primitives in the export
3591 * (in the common case of single-dword prim exports).
3593 build_sendmsg_gs_alloc_req(ctx
, vertlive_scan
.result_reduce
, num_emit_threads
);
3595 /* Setup the reverse vertex compaction permutation. We re-use stream 1
3596 * of the primitive liveness flags, relying on the fact that each
3597 * threadgroup can have at most 256 threads. */
3598 ac_build_ifcc(&ctx
->ac
, vertlive
, 5130);
3600 tmp
= ngg_gs_vertex_ptr(ctx
, vertlive_scan
.result_exclusive
);
3601 LLVMValueRef gep_idx
[3] = {
3602 ctx
->ac
.i32_0
, /* implicit C-style array */
3603 ctx
->ac
.i32_1
, /* second value of struct */
3604 ctx
->ac
.i32_1
, /* stream 1 */
3606 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3607 tmp2
= LLVMBuildTrunc(builder
, tid
, ctx
->ac
.i8
, "");
3608 LLVMBuildStore(builder
, tmp2
, tmp
);
3610 ac_build_endif(&ctx
->ac
, 5130);
3612 ac_build_s_barrier(&ctx
->ac
);
3614 /* Export primitive data */
3615 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, num_emit_threads
, "");
3616 ac_build_ifcc(&ctx
->ac
, tmp
, 5140);
3618 struct ngg_prim prim
= {};
3619 prim
.num_vertices
= verts_per_prim
;
3621 tmp
= ngg_gs_vertex_ptr(ctx
, tid
);
3622 LLVMValueRef gep_idx
[3] = {
3623 ctx
->ac
.i32_0
, /* implicit C-style array */
3624 ctx
->ac
.i32_1
, /* second value of struct */
3625 ctx
->ac
.i32_0
, /* primflag */
3627 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3628 tmp
= LLVMBuildLoad(builder
, tmp
, "");
3629 prim
.isnull
= LLVMBuildICmp(builder
, LLVMIntEQ
, tmp
,
3630 LLVMConstInt(ctx
->ac
.i8
, 0, false), "");
3632 for (unsigned i
= 0; i
< verts_per_prim
; ++i
) {
3633 prim
.index
[i
] = LLVMBuildSub(builder
, vertlive_scan
.result_exclusive
,
3634 LLVMConstInt(ctx
->ac
.i32
, verts_per_prim
- i
- 1, false), "");
3635 prim
.edgeflag
[i
] = ctx
->ac
.i1false
;
3638 build_export_prim(ctx
, &prim
);
3640 ac_build_endif(&ctx
->ac
, 5140);
3642 /* Export position and parameter data */
3643 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, vertlive_scan
.result_reduce
, "");
3644 ac_build_ifcc(&ctx
->ac
, tmp
, 5145);
3646 struct radv_vs_output_info
*outinfo
= &ctx
->shader_info
->vs
.outinfo
;
3647 bool export_view_index
= ctx
->options
->key
.has_multiview_view_index
;
3648 struct radv_shader_output_values
*outputs
;
3649 unsigned noutput
= 0;
3651 /* Allocate a temporary array for the output values. */
3652 unsigned num_outputs
= util_bitcount64(ctx
->output_mask
) + export_view_index
;
3653 outputs
= calloc(num_outputs
, sizeof(outputs
[0]));
3655 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
3656 sizeof(outinfo
->vs_output_param_offset
));
3657 outinfo
->pos_exports
= 0;
3659 tmp
= ngg_gs_vertex_ptr(ctx
, tid
);
3660 LLVMValueRef gep_idx
[3] = {
3661 ctx
->ac
.i32_0
, /* implicit C-style array */
3662 ctx
->ac
.i32_1
, /* second value of struct */
3663 ctx
->ac
.i32_1
, /* stream 1: source data index */
3665 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3666 tmp
= LLVMBuildLoad(builder
, tmp
, "");
3667 tmp
= LLVMBuildZExt(builder
, tmp
, ctx
->ac
.i32
, "");
3668 const LLVMValueRef vertexptr
= ngg_gs_vertex_ptr(ctx
, tmp
);
3670 if (ctx
->output_mask
& (1ull << VARYING_SLOT_PSIZ
)) {
3671 outinfo
->writes_pointsize
= true;
3674 if (ctx
->output_mask
& (1ull << VARYING_SLOT_LAYER
)) {
3675 outinfo
->writes_layer
= true;
3678 if (ctx
->output_mask
& (1ull << VARYING_SLOT_VIEWPORT
)) {
3679 outinfo
->writes_viewport_index
= true;
3682 unsigned out_idx
= 0;
3683 gep_idx
[1] = ctx
->ac
.i32_0
;
3684 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3685 if (!(ctx
->output_mask
& (1ull << i
)))
3688 outputs
[noutput
].slot_name
= i
;
3689 outputs
[noutput
].slot_index
= i
== VARYING_SLOT_CLIP_DIST1
;
3691 outputs
[noutput
].usage_mask
= ctx
->shader_info
->info
.gs
.output_usage_mask
[i
];
3692 int length
= util_last_bit(outputs
[noutput
].usage_mask
);
3694 for (unsigned j
= 0; j
< length
; j
++, out_idx
++) {
3695 gep_idx
[2] = LLVMConstInt(ctx
->ac
.i32
, out_idx
, false);
3696 tmp
= LLVMBuildGEP(builder
, vertexptr
, gep_idx
, 3, "");
3697 tmp
= LLVMBuildLoad(builder
, tmp
, "");
3699 LLVMTypeRef type
= LLVMGetAllocatedType(ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
3700 if (ac_get_type_size(type
) == 2) {
3701 tmp
= ac_to_integer(&ctx
->ac
, tmp
);
3702 tmp
= LLVMBuildTrunc(ctx
->ac
.builder
, tmp
, ctx
->ac
.i16
, "");
3705 outputs
[noutput
].values
[j
] = ac_to_float(&ctx
->ac
, tmp
);
3708 for (unsigned j
= length
; j
< 4; j
++)
3709 outputs
[noutput
].values
[j
] = LLVMGetUndef(ctx
->ac
.f32
);
3714 /* Export ViewIndex. */
3715 if (export_view_index
) {
3716 outinfo
->writes_layer
= true;
3718 outputs
[noutput
].slot_name
= VARYING_SLOT_LAYER
;
3719 outputs
[noutput
].slot_index
= 0;
3720 outputs
[noutput
].usage_mask
= 0x1;
3721 outputs
[noutput
].values
[0] = ac_to_float(&ctx
->ac
, ctx
->abi
.view_index
);
3722 for (unsigned j
= 1; j
< 4; j
++)
3723 outputs
[noutput
].values
[j
] = ctx
->ac
.f32_0
;
3727 radv_llvm_export_vs(ctx
, outputs
, noutput
, outinfo
,
3728 ctx
->options
->key
.vs_common_out
.export_clip_dists
);
3731 ac_build_endif(&ctx
->ac
, 5145);
3734 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context
*ctx
,
3736 LLVMValueRef
*addrs
)
3738 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3740 const LLVMValueRef vertexidx
=
3741 LLVMBuildLoad(builder
, ctx
->gs_next_vertex
[stream
], "");
3743 /* If this thread has already emitted the declared maximum number of
3744 * vertices, skip the write: excessive vertex emissions are not
3745 * supposed to have any effect.
3747 const LLVMValueRef can_emit
=
3748 LLVMBuildICmp(builder
, LLVMIntULT
, vertexidx
,
3749 LLVMConstInt(ctx
->ac
.i32
, ctx
->gs_max_out_vertices
, false), "");
3750 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
3752 tmp
= LLVMBuildAdd(builder
, vertexidx
, ctx
->ac
.i32_1
, "");
3753 tmp
= LLVMBuildSelect(builder
, can_emit
, tmp
, vertexidx
, "");
3754 LLVMBuildStore(builder
, tmp
, ctx
->gs_next_vertex
[stream
]);
3756 const LLVMValueRef vertexptr
=
3757 ngg_gs_emit_vertex_ptr(ctx
, get_thread_id_in_tg(ctx
), vertexidx
);
3758 unsigned out_idx
= 0;
3759 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3760 unsigned output_usage_mask
=
3761 ctx
->shader_info
->info
.gs
.output_usage_mask
[i
];
3762 uint8_t output_stream
=
3763 ctx
->shader_info
->info
.gs
.output_streams
[i
];
3764 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
3765 int length
= util_last_bit(output_usage_mask
);
3767 if (!(ctx
->output_mask
& (1ull << i
)) ||
3768 output_stream
!= stream
)
3771 for (unsigned j
= 0; j
< length
; j
++, out_idx
++) {
3772 if (!(output_usage_mask
& (1 << j
)))
3775 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
,
3777 LLVMValueRef gep_idx
[3] = {
3778 ctx
->ac
.i32_0
, /* implied C-style array */
3779 ctx
->ac
.i32_0
, /* first entry of struct */
3780 LLVMConstInt(ctx
->ac
.i32
, out_idx
, false),
3782 LLVMValueRef ptr
= LLVMBuildGEP(builder
, vertexptr
, gep_idx
, 3, "");
3784 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
3785 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
3787 LLVMBuildStore(builder
, out_val
, ptr
);
3790 assert(out_idx
* 4 <= ctx
->gsvs_vertex_size
);
3792 /* Determine and store whether this vertex completed a primitive. */
3793 const LLVMValueRef curverts
= LLVMBuildLoad(builder
, ctx
->gs_curprim_verts
[stream
], "");
3795 tmp
= LLVMConstInt(ctx
->ac
.i32
, si_conv_gl_prim_to_vertices(ctx
->gs_output_prim
) - 1, false);
3796 const LLVMValueRef iscompleteprim
=
3797 LLVMBuildICmp(builder
, LLVMIntUGE
, curverts
, tmp
, "");
3799 tmp
= LLVMBuildAdd(builder
, curverts
, ctx
->ac
.i32_1
, "");
3800 LLVMBuildStore(builder
, tmp
, ctx
->gs_curprim_verts
[stream
]);
3802 LLVMValueRef gep_idx
[3] = {
3803 ctx
->ac
.i32_0
, /* implied C-style array */
3804 ctx
->ac
.i32_1
, /* second struct entry */
3805 LLVMConstInt(ctx
->ac
.i32
, stream
, false),
3807 const LLVMValueRef primflagptr
=
3808 LLVMBuildGEP(builder
, vertexptr
, gep_idx
, 3, "");
3810 tmp
= LLVMBuildZExt(builder
, iscompleteprim
, ctx
->ac
.i8
, "");
3811 LLVMBuildStore(builder
, tmp
, primflagptr
);
3813 tmp
= LLVMBuildLoad(builder
, ctx
->gs_generated_prims
[stream
], "");
3814 tmp
= LLVMBuildAdd(builder
, tmp
, LLVMBuildZExt(builder
, iscompleteprim
, ctx
->ac
.i32
, ""), "");
3815 LLVMBuildStore(builder
, tmp
, ctx
->gs_generated_prims
[stream
]);
3819 write_tess_factors(struct radv_shader_context
*ctx
)
3821 unsigned stride
, outer_comps
, inner_comps
;
3822 struct ac_build_if_state if_ctx
, inner_if_ctx
;
3823 LLVMValueRef invocation_id
= ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 8, 5);
3824 LLVMValueRef rel_patch_id
= ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
3825 unsigned tess_inner_index
= 0, tess_outer_index
;
3826 LLVMValueRef lds_base
, lds_inner
= NULL
, lds_outer
, byteoffset
, buffer
;
3827 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
3829 ac_emit_barrier(&ctx
->ac
, ctx
->stage
);
3831 switch (ctx
->options
->key
.tcs
.primitive_mode
) {
3851 ac_nir_build_if(&if_ctx
, ctx
,
3852 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3853 invocation_id
, ctx
->ac
.i32_0
, ""));
3855 lds_base
= get_tcs_out_current_patch_data_offset(ctx
);
3858 tess_inner_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
3859 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3860 LLVMConstInt(ctx
->ac
.i32
, tess_inner_index
* 4, false), "");
3863 tess_outer_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
3864 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3865 LLVMConstInt(ctx
->ac
.i32
, tess_outer_index
* 4, false), "");
3867 for (i
= 0; i
< 4; i
++) {
3868 inner
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
3869 outer
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
3873 if (ctx
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
3874 outer
[0] = out
[1] = ac_lds_load(&ctx
->ac
, lds_outer
);
3875 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
3877 outer
[1] = out
[0] = ac_lds_load(&ctx
->ac
, lds_outer
);
3879 for (i
= 0; i
< outer_comps
; i
++) {
3881 ac_lds_load(&ctx
->ac
, lds_outer
);
3882 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
3885 for (i
= 0; i
< inner_comps
; i
++) {
3886 inner
[i
] = out
[outer_comps
+i
] =
3887 ac_lds_load(&ctx
->ac
, lds_inner
);
3888 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_inner
,
3893 /* Convert the outputs to vectors for stores. */
3894 vec0
= ac_build_gather_values(&ctx
->ac
, out
, MIN2(stride
, 4));
3898 vec1
= ac_build_gather_values(&ctx
->ac
, out
+ 4, stride
- 4);
3901 buffer
= ctx
->hs_ring_tess_factor
;
3902 tf_base
= ctx
->tess_factor_offset
;
3903 byteoffset
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
3904 LLVMConstInt(ctx
->ac
.i32
, 4 * stride
, false), "");
3905 unsigned tf_offset
= 0;
3907 if (ctx
->options
->chip_class
<= GFX8
) {
3908 ac_nir_build_if(&inner_if_ctx
, ctx
,
3909 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3910 rel_patch_id
, ctx
->ac
.i32_0
, ""));
3912 /* Store the dynamic HS control word. */
3913 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
3914 LLVMConstInt(ctx
->ac
.i32
, 0x80000000, false),
3915 1, ctx
->ac
.i32_0
, tf_base
,
3919 ac_nir_build_endif(&inner_if_ctx
);
3922 /* Store the tessellation factors. */
3923 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
3924 MIN2(stride
, 4), byteoffset
, tf_base
,
3925 tf_offset
, ac_glc
, false);
3927 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
3928 stride
- 4, byteoffset
, tf_base
,
3929 16 + tf_offset
, ac_glc
, false);
3931 //store to offchip for TES to read - only if TES reads them
3932 if (ctx
->options
->key
.tcs
.tes_reads_tess_factors
) {
3933 LLVMValueRef inner_vec
, outer_vec
, tf_outer_offset
;
3934 LLVMValueRef tf_inner_offset
;
3935 unsigned param_outer
, param_inner
;
3937 param_outer
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
3938 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
3939 LLVMConstInt(ctx
->ac
.i32
, param_outer
, 0));
3941 outer_vec
= ac_build_gather_values(&ctx
->ac
, outer
,
3942 util_next_power_of_two(outer_comps
));
3944 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, outer_vec
,
3945 outer_comps
, tf_outer_offset
,
3946 ctx
->oc_lds
, 0, ac_glc
, false);
3948 param_inner
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
3949 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
3950 LLVMConstInt(ctx
->ac
.i32
, param_inner
, 0));
3952 inner_vec
= inner_comps
== 1 ? inner
[0] :
3953 ac_build_gather_values(&ctx
->ac
, inner
, inner_comps
);
3954 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, inner_vec
,
3955 inner_comps
, tf_inner_offset
,
3956 ctx
->oc_lds
, 0, ac_glc
, false);
3959 ac_nir_build_endif(&if_ctx
);
3963 handle_tcs_outputs_post(struct radv_shader_context
*ctx
)
3965 write_tess_factors(ctx
);
3969 si_export_mrt_color(struct radv_shader_context
*ctx
,
3970 LLVMValueRef
*color
, unsigned index
,
3971 struct ac_export_args
*args
)
3974 si_llvm_init_export_args(ctx
, color
, 0xf,
3975 V_008DFC_SQ_EXP_MRT
+ index
, args
);
3976 if (!args
->enabled_channels
)
3977 return false; /* unnecessary NULL export */
3983 radv_export_mrt_z(struct radv_shader_context
*ctx
,
3984 LLVMValueRef depth
, LLVMValueRef stencil
,
3985 LLVMValueRef samplemask
)
3987 struct ac_export_args args
;
3989 ac_export_mrt_z(&ctx
->ac
, depth
, stencil
, samplemask
, &args
);
3991 ac_build_export(&ctx
->ac
, &args
);
3995 handle_fs_outputs_post(struct radv_shader_context
*ctx
)
3998 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
3999 struct ac_export_args color_args
[8];
4001 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
4002 LLVMValueRef values
[4];
4004 if (!(ctx
->output_mask
& (1ull << i
)))
4007 if (i
< FRAG_RESULT_DATA0
)
4010 for (unsigned j
= 0; j
< 4; j
++)
4011 values
[j
] = ac_to_float(&ctx
->ac
,
4012 radv_load_output(ctx
, i
, j
));
4014 bool ret
= si_export_mrt_color(ctx
, values
,
4015 i
- FRAG_RESULT_DATA0
,
4016 &color_args
[index
]);
4021 /* Process depth, stencil, samplemask. */
4022 if (ctx
->shader_info
->info
.ps
.writes_z
) {
4023 depth
= ac_to_float(&ctx
->ac
,
4024 radv_load_output(ctx
, FRAG_RESULT_DEPTH
, 0));
4026 if (ctx
->shader_info
->info
.ps
.writes_stencil
) {
4027 stencil
= ac_to_float(&ctx
->ac
,
4028 radv_load_output(ctx
, FRAG_RESULT_STENCIL
, 0));
4030 if (ctx
->shader_info
->info
.ps
.writes_sample_mask
) {
4031 samplemask
= ac_to_float(&ctx
->ac
,
4032 radv_load_output(ctx
, FRAG_RESULT_SAMPLE_MASK
, 0));
4035 /* Set the DONE bit on last non-null color export only if Z isn't
4039 !ctx
->shader_info
->info
.ps
.writes_z
&&
4040 !ctx
->shader_info
->info
.ps
.writes_stencil
&&
4041 !ctx
->shader_info
->info
.ps
.writes_sample_mask
) {
4042 unsigned last
= index
- 1;
4044 color_args
[last
].valid_mask
= 1; /* whether the EXEC mask is valid */
4045 color_args
[last
].done
= 1; /* DONE bit */
4048 /* Export PS outputs. */
4049 for (unsigned i
= 0; i
< index
; i
++)
4050 ac_build_export(&ctx
->ac
, &color_args
[i
]);
4052 if (depth
|| stencil
|| samplemask
)
4053 radv_export_mrt_z(ctx
, depth
, stencil
, samplemask
);
4055 ac_build_export_null(&ctx
->ac
);
4059 emit_gs_epilogue(struct radv_shader_context
*ctx
)
4061 if (ctx
->options
->key
.vs_common_out
.as_ngg
) {
4062 gfx10_ngg_gs_emit_epilogue_1(ctx
);
4066 if (ctx
->ac
.chip_class
>= GFX10
)
4067 LLVMBuildFence(ctx
->ac
.builder
, LLVMAtomicOrderingRelease
, false, "");
4069 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
, ctx
->gs_wave_id
);
4073 handle_shader_outputs_post(struct ac_shader_abi
*abi
, unsigned max_outputs
,
4074 LLVMValueRef
*addrs
)
4076 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4078 switch (ctx
->stage
) {
4079 case MESA_SHADER_VERTEX
:
4080 if (ctx
->options
->key
.vs_common_out
.as_ls
)
4081 handle_ls_outputs_post(ctx
);
4082 else if (ctx
->options
->key
.vs_common_out
.as_es
)
4083 handle_es_outputs_post(ctx
, &ctx
->shader_info
->vs
.es_info
);
4084 else if (ctx
->options
->key
.vs_common_out
.as_ngg
)
4085 break; /* handled outside of the shader body */
4087 handle_vs_outputs_post(ctx
, ctx
->options
->key
.vs_common_out
.export_prim_id
,
4088 ctx
->options
->key
.vs_common_out
.export_clip_dists
,
4089 &ctx
->shader_info
->vs
.outinfo
);
4091 case MESA_SHADER_FRAGMENT
:
4092 handle_fs_outputs_post(ctx
);
4094 case MESA_SHADER_GEOMETRY
:
4095 emit_gs_epilogue(ctx
);
4097 case MESA_SHADER_TESS_CTRL
:
4098 handle_tcs_outputs_post(ctx
);
4100 case MESA_SHADER_TESS_EVAL
:
4101 if (ctx
->options
->key
.vs_common_out
.as_es
)
4102 handle_es_outputs_post(ctx
, &ctx
->shader_info
->tes
.es_info
);
4103 else if (ctx
->options
->key
.vs_common_out
.as_ngg
)
4104 break; /* handled outside of the shader body */
4106 handle_vs_outputs_post(ctx
, ctx
->options
->key
.vs_common_out
.export_prim_id
,
4107 ctx
->options
->key
.vs_common_out
.export_clip_dists
,
4108 &ctx
->shader_info
->tes
.outinfo
);
4115 static void ac_llvm_finalize_module(struct radv_shader_context
*ctx
,
4116 LLVMPassManagerRef passmgr
,
4117 const struct radv_nir_compiler_options
*options
)
4119 LLVMRunPassManager(passmgr
, ctx
->ac
.module
);
4120 LLVMDisposeBuilder(ctx
->ac
.builder
);
4122 ac_llvm_context_dispose(&ctx
->ac
);
4126 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context
*ctx
)
4128 struct radv_vs_output_info
*outinfo
;
4130 switch (ctx
->stage
) {
4131 case MESA_SHADER_FRAGMENT
:
4132 case MESA_SHADER_COMPUTE
:
4133 case MESA_SHADER_TESS_CTRL
:
4134 case MESA_SHADER_GEOMETRY
:
4136 case MESA_SHADER_VERTEX
:
4137 if (ctx
->options
->key
.vs_common_out
.as_ls
||
4138 ctx
->options
->key
.vs_common_out
.as_es
)
4140 outinfo
= &ctx
->shader_info
->vs
.outinfo
;
4142 case MESA_SHADER_TESS_EVAL
:
4143 if (ctx
->options
->key
.vs_common_out
.as_es
)
4145 outinfo
= &ctx
->shader_info
->tes
.outinfo
;
4148 unreachable("Unhandled shader type");
4151 ac_optimize_vs_outputs(&ctx
->ac
,
4153 outinfo
->vs_output_param_offset
,
4155 &outinfo
->param_exports
);
4159 ac_setup_rings(struct radv_shader_context
*ctx
)
4161 if (ctx
->options
->chip_class
<= GFX8
&&
4162 (ctx
->stage
== MESA_SHADER_GEOMETRY
||
4163 ctx
->options
->key
.vs_common_out
.as_es
|| ctx
->options
->key
.vs_common_out
.as_es
)) {
4164 unsigned ring
= ctx
->stage
== MESA_SHADER_GEOMETRY
? RING_ESGS_GS
4166 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, ring
, false);
4168 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
,
4173 if (ctx
->is_gs_copy_shader
) {
4175 ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
,
4176 LLVMConstInt(ctx
->ac
.i32
,
4177 RING_GSVS_VS
, false));
4180 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
4181 /* The conceptual layout of the GSVS ring is
4182 * v0c0 .. vLv0 v0c1 .. vLc1 ..
4183 * but the real memory layout is swizzled across
4185 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
4187 * Override the buffer descriptor accordingly.
4189 LLVMTypeRef v2i64
= LLVMVectorType(ctx
->ac
.i64
, 2);
4190 uint64_t stream_offset
= 0;
4191 unsigned num_records
= ctx
->ac
.wave_size
;
4192 LLVMValueRef base_ring
;
4195 ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
,
4196 LLVMConstInt(ctx
->ac
.i32
,
4197 RING_GSVS_GS
, false));
4199 for (unsigned stream
= 0; stream
< 4; stream
++) {
4200 unsigned num_components
, stride
;
4201 LLVMValueRef ring
, tmp
;
4204 ctx
->shader_info
->info
.gs
.num_stream_output_components
[stream
];
4206 if (!num_components
)
4209 stride
= 4 * num_components
* ctx
->gs_max_out_vertices
;
4211 /* Limit on the stride field for <= GFX7. */
4212 assert(stride
< (1 << 14));
4214 ring
= LLVMBuildBitCast(ctx
->ac
.builder
,
4215 base_ring
, v2i64
, "");
4216 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
,
4217 ring
, ctx
->ac
.i32_0
, "");
4218 tmp
= LLVMBuildAdd(ctx
->ac
.builder
, tmp
,
4219 LLVMConstInt(ctx
->ac
.i64
,
4220 stream_offset
, 0), "");
4221 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
,
4222 ring
, tmp
, ctx
->ac
.i32_0
, "");
4224 stream_offset
+= stride
* ctx
->ac
.wave_size
;
4226 ring
= LLVMBuildBitCast(ctx
->ac
.builder
, ring
,
4229 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
, ring
,
4231 tmp
= LLVMBuildOr(ctx
->ac
.builder
, tmp
,
4232 LLVMConstInt(ctx
->ac
.i32
,
4233 S_008F04_STRIDE(stride
), false), "");
4234 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ring
, tmp
,
4237 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ring
,
4238 LLVMConstInt(ctx
->ac
.i32
,
4239 num_records
, false),
4240 LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
4242 ctx
->gsvs_ring
[stream
] = ring
;
4246 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
4247 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
4248 ctx
->hs_ring_tess_offchip
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_OFFCHIP
, false));
4249 ctx
->hs_ring_tess_factor
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_FACTOR
, false));
4254 radv_nir_get_max_workgroup_size(enum chip_class chip_class
,
4255 gl_shader_stage stage
,
4256 const struct nir_shader
*nir
)
4258 const unsigned backup_sizes
[] = {chip_class
>= GFX9
? 128 : 64, 1, 1};
4259 return radv_get_max_workgroup_size(chip_class
, stage
, nir
? nir
->info
.cs
.local_size
: backup_sizes
);
4262 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
4263 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context
*ctx
)
4265 LLVMValueRef count
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 8, 8);
4266 LLVMValueRef hs_empty
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, count
,
4268 ctx
->abi
.instance_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->rel_auto_id
, ctx
->abi
.instance_id
, "");
4269 ctx
->rel_auto_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_rel_ids
, ctx
->rel_auto_id
, "");
4270 ctx
->abi
.vertex_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_patch_id
, ctx
->abi
.vertex_id
, "");
4273 static void prepare_gs_input_vgprs(struct radv_shader_context
*ctx
)
4275 for(int i
= 5; i
>= 0; --i
) {
4276 ctx
->gs_vtx_offset
[i
] = ac_unpack_param(&ctx
->ac
, ctx
->gs_vtx_offset
[i
& ~1],
4280 ctx
->gs_wave_id
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 16, 8);
4283 /* Ensure that the esgs ring is declared.
4285 * We declare it with 64KB alignment as a hint that the
4286 * pointer value will always be 0.
4288 static void declare_esgs_ring(struct radv_shader_context
*ctx
)
4293 assert(!LLVMGetNamedGlobal(ctx
->ac
.module
, "esgs_ring"));
4295 ctx
->esgs_ring
= LLVMAddGlobalInAddressSpace(
4296 ctx
->ac
.module
, LLVMArrayType(ctx
->ac
.i32
, 0),
4299 LLVMSetLinkage(ctx
->esgs_ring
, LLVMExternalLinkage
);
4300 LLVMSetAlignment(ctx
->esgs_ring
, 64 * 1024);
4304 LLVMModuleRef
ac_translate_nir_to_llvm(struct ac_llvm_compiler
*ac_llvm
,
4305 struct nir_shader
*const *shaders
,
4307 struct radv_shader_variant_info
*shader_info
,
4308 const struct radv_nir_compiler_options
*options
)
4310 struct radv_shader_context ctx
= {0};
4312 ctx
.options
= options
;
4313 ctx
.shader_info
= shader_info
;
4315 enum ac_float_mode float_mode
=
4316 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
4317 AC_FLOAT_MODE_DEFAULT
;
4319 ac_llvm_context_init(&ctx
.ac
, ac_llvm
, options
->chip_class
,
4320 options
->family
, float_mode
, options
->wave_size
,
4321 options
->wave_size
);
4322 ctx
.context
= ctx
.ac
.context
;
4324 radv_nir_shader_info_init(&shader_info
->info
);
4326 for(int i
= 0; i
< shader_count
; ++i
)
4327 radv_nir_shader_info_pass(shaders
[i
], options
, &shader_info
->info
);
4329 for (i
= 0; i
< MAX_SETS
; i
++)
4330 shader_info
->user_sgprs_locs
.descriptor_sets
[i
].sgpr_idx
= -1;
4331 for (i
= 0; i
< AC_UD_MAX_UD
; i
++)
4332 shader_info
->user_sgprs_locs
.shader_data
[i
].sgpr_idx
= -1;
4334 ctx
.max_workgroup_size
= 0;
4335 for (int i
= 0; i
< shader_count
; ++i
) {
4336 ctx
.max_workgroup_size
= MAX2(ctx
.max_workgroup_size
,
4337 radv_nir_get_max_workgroup_size(ctx
.options
->chip_class
,
4338 shaders
[i
]->info
.stage
,
4342 if (ctx
.ac
.chip_class
>= GFX10
) {
4343 if (is_pre_gs_stage(shaders
[0]->info
.stage
) &&
4344 options
->key
.vs_common_out
.as_ngg
) {
4345 ctx
.max_workgroup_size
= 128;
4349 create_function(&ctx
, shaders
[shader_count
- 1]->info
.stage
, shader_count
>= 2,
4350 shader_count
>= 2 ? shaders
[shader_count
- 2]->info
.stage
: MESA_SHADER_VERTEX
);
4352 ctx
.abi
.inputs
= &ctx
.inputs
[0];
4353 ctx
.abi
.emit_outputs
= handle_shader_outputs_post
;
4354 ctx
.abi
.emit_vertex
= visit_emit_vertex
;
4355 ctx
.abi
.load_ubo
= radv_load_ubo
;
4356 ctx
.abi
.load_ssbo
= radv_load_ssbo
;
4357 ctx
.abi
.load_sampler_desc
= radv_get_sampler_desc
;
4358 ctx
.abi
.load_resource
= radv_load_resource
;
4359 ctx
.abi
.clamp_shadow_reference
= false;
4360 ctx
.abi
.robust_buffer_access
= options
->robust_buffer_access
;
4362 bool is_ngg
= is_pre_gs_stage(shaders
[0]->info
.stage
) && ctx
.options
->key
.vs_common_out
.as_ngg
;
4363 if (shader_count
>= 2 || is_ngg
)
4364 ac_init_exec_full_mask(&ctx
.ac
);
4366 if (options
->has_ls_vgpr_init_bug
&&
4367 shaders
[shader_count
- 1]->info
.stage
== MESA_SHADER_TESS_CTRL
)
4368 ac_nir_fixup_ls_hs_input_vgprs(&ctx
);
4370 for(int i
= 0; i
< shader_count
; ++i
) {
4371 ctx
.stage
= shaders
[i
]->info
.stage
;
4372 ctx
.output_mask
= 0;
4374 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
4375 for (int i
= 0; i
< 4; i
++) {
4376 ctx
.gs_next_vertex
[i
] =
4377 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
4379 if (ctx
.options
->key
.vs_common_out
.as_ngg
) {
4380 for (unsigned i
= 0; i
< 4; ++i
) {
4381 ctx
.gs_curprim_verts
[i
] =
4382 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
4383 ctx
.gs_generated_prims
[i
] =
4384 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
4387 /* TODO: streamout */
4389 LLVMTypeRef ai32
= LLVMArrayType(ctx
.ac
.i32
, 8);
4390 ctx
.gs_ngg_scratch
=
4391 LLVMAddGlobalInAddressSpace(ctx
.ac
.module
,
4392 ai32
, "ngg_scratch", AC_ADDR_SPACE_LDS
);
4393 LLVMSetInitializer(ctx
.gs_ngg_scratch
, LLVMGetUndef(ai32
));
4394 LLVMSetAlignment(ctx
.gs_ngg_scratch
, 4);
4396 ctx
.gs_ngg_emit
= LLVMBuildIntToPtr(ctx
.ac
.builder
, ctx
.ac
.i32_0
,
4397 LLVMPointerType(LLVMArrayType(ctx
.ac
.i32
, 0), AC_ADDR_SPACE_LDS
),
4401 ctx
.gs_max_out_vertices
= shaders
[i
]->info
.gs
.vertices_out
;
4402 ctx
.gs_output_prim
= shaders
[i
]->info
.gs
.output_primitive
;
4403 ctx
.abi
.load_inputs
= load_gs_input
;
4404 ctx
.abi
.emit_primitive
= visit_end_primitive
;
4405 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4406 ctx
.tcs_outputs_read
= shaders
[i
]->info
.outputs_read
;
4407 ctx
.tcs_patch_outputs_read
= shaders
[i
]->info
.patch_outputs_read
;
4408 ctx
.abi
.load_tess_varyings
= load_tcs_varyings
;
4409 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
4410 ctx
.abi
.store_tcs_outputs
= store_tcs_output
;
4411 ctx
.tcs_vertices_per_patch
= shaders
[i
]->info
.tess
.tcs_vertices_out
;
4412 if (shader_count
== 1)
4413 ctx
.tcs_num_inputs
= ctx
.options
->key
.tcs
.num_inputs
;
4415 ctx
.tcs_num_inputs
= util_last_bit64(shader_info
->info
.vs
.ls_outputs_written
);
4416 ctx
.tcs_num_patches
= get_tcs_num_patches(&ctx
);
4417 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4418 ctx
.tes_primitive_mode
= shaders
[i
]->info
.tess
.primitive_mode
;
4419 ctx
.abi
.load_tess_varyings
= load_tes_input
;
4420 ctx
.abi
.load_tess_coord
= load_tess_coord
;
4421 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
4422 ctx
.tcs_vertices_per_patch
= shaders
[i
]->info
.tess
.tcs_vertices_out
;
4423 ctx
.tcs_num_patches
= ctx
.options
->key
.tes
.num_patches
;
4424 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
) {
4425 ctx
.abi
.load_base_vertex
= radv_load_base_vertex
;
4426 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
) {
4427 shader_info
->fs
.can_discard
= shaders
[i
]->info
.fs
.uses_discard
;
4428 ctx
.abi
.lookup_interp_param
= lookup_interp_param
;
4429 ctx
.abi
.load_sample_position
= load_sample_position
;
4430 ctx
.abi
.load_sample_mask_in
= load_sample_mask_in
;
4431 ctx
.abi
.emit_kill
= radv_emit_kill
;
4434 if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
&&
4435 ctx
.options
->key
.vs_common_out
.as_ngg
&&
4436 ctx
.options
->key
.vs_common_out
.export_prim_id
) {
4437 declare_esgs_ring(&ctx
);
4440 bool nested_barrier
= false;
4443 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
&&
4444 ctx
.options
->key
.vs_common_out
.as_ngg
) {
4445 gfx10_ngg_gs_emit_prologue(&ctx
);
4446 nested_barrier
= false;
4448 nested_barrier
= true;
4452 if (nested_barrier
) {
4453 /* Execute a barrier before the second shader in
4456 * Execute the barrier inside the conditional block,
4457 * so that empty waves can jump directly to s_endpgm,
4458 * which will also signal the barrier.
4460 * This is possible in gfx9, because an empty wave
4461 * for the second shader does not participate in
4462 * the epilogue. With NGG, empty waves may still
4463 * be required to export data (e.g. GS output vertices),
4464 * so we cannot let them exit early.
4466 * If the shader is TCS and the TCS epilog is present
4467 * and contains a barrier, it will wait there and then
4470 ac_emit_barrier(&ctx
.ac
, ctx
.stage
);
4473 nir_foreach_variable(variable
, &shaders
[i
]->outputs
)
4474 scan_shader_output_decl(&ctx
, variable
, shaders
[i
], shaders
[i
]->info
.stage
);
4476 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
4477 unsigned addclip
= shaders
[i
]->info
.clip_distance_array_size
+
4478 shaders
[i
]->info
.cull_distance_array_size
> 4;
4479 ctx
.gsvs_vertex_size
= (util_bitcount64(ctx
.output_mask
) + addclip
) * 16;
4480 ctx
.max_gsvs_emit_size
= ctx
.gsvs_vertex_size
*
4481 shaders
[i
]->info
.gs
.vertices_out
;
4484 ac_setup_rings(&ctx
);
4486 LLVMBasicBlockRef merge_block
;
4487 if (shader_count
>= 2 || is_ngg
) {
4488 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
4489 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
4490 merge_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
4492 LLVMValueRef count
= ac_unpack_param(&ctx
.ac
, ctx
.merged_wave_info
, 8 * i
, 8);
4493 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
.ac
);
4494 LLVMValueRef cond
= LLVMBuildICmp(ctx
.ac
.builder
, LLVMIntULT
,
4495 thread_id
, count
, "");
4496 LLVMBuildCondBr(ctx
.ac
.builder
, cond
, then_block
, merge_block
);
4498 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, then_block
);
4501 if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
)
4502 prepare_interp_optimize(&ctx
, shaders
[i
]);
4503 else if(shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
)
4504 handle_vs_inputs(&ctx
, shaders
[i
]);
4505 else if(shader_count
>= 2 && shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
)
4506 prepare_gs_input_vgprs(&ctx
);
4508 ac_nir_translate(&ctx
.ac
, &ctx
.abi
, shaders
[i
]);
4510 if (shader_count
>= 2 || is_ngg
) {
4511 LLVMBuildBr(ctx
.ac
.builder
, merge_block
);
4512 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, merge_block
);
4515 /* This needs to be outside the if wrapping the shader body, as sometimes
4516 * the HW generates waves with 0 es/vs threads. */
4517 if (is_pre_gs_stage(shaders
[i
]->info
.stage
) &&
4518 ctx
.options
->key
.vs_common_out
.as_ngg
&&
4519 i
== shader_count
- 1) {
4520 handle_ngg_outputs_post(&ctx
);
4521 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
&&
4522 ctx
.options
->key
.vs_common_out
.as_ngg
) {
4523 gfx10_ngg_gs_emit_epilogue_2(&ctx
);
4526 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
4527 shader_info
->gs
.gsvs_vertex_size
= ctx
.gsvs_vertex_size
;
4528 shader_info
->gs
.max_gsvs_emit_size
= ctx
.max_gsvs_emit_size
;
4529 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4530 shader_info
->tcs
.num_patches
= ctx
.tcs_num_patches
;
4531 shader_info
->tcs
.lds_size
= calculate_tess_lds_size(&ctx
);
4535 LLVMBuildRetVoid(ctx
.ac
.builder
);
4537 if (options
->dump_preoptir
) {
4538 fprintf(stderr
, "%s LLVM IR:\n\n",
4539 radv_get_shader_name(shader_info
,
4540 shaders
[shader_count
- 1]->info
.stage
));
4541 ac_dump_module(ctx
.ac
.module
);
4542 fprintf(stderr
, "\n");
4545 ac_llvm_finalize_module(&ctx
, ac_llvm
->passmgr
, options
);
4547 if (shader_count
== 1)
4548 ac_nir_eliminate_const_vs_outputs(&ctx
);
4550 if (options
->dump_shader
) {
4551 ctx
.shader_info
->private_mem_vgprs
=
4552 ac_count_scratch_private_memory(ctx
.main_function
);
4555 return ctx
.ac
.module
;
4558 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di
, void *context
)
4560 unsigned *retval
= (unsigned *)context
;
4561 LLVMDiagnosticSeverity severity
= LLVMGetDiagInfoSeverity(di
);
4562 char *description
= LLVMGetDiagInfoDescription(di
);
4564 if (severity
== LLVMDSError
) {
4566 fprintf(stderr
, "LLVM triggered Diagnostic Handler: %s\n",
4570 LLVMDisposeMessage(description
);
4573 static unsigned radv_llvm_compile(LLVMModuleRef M
,
4574 char **pelf_buffer
, size_t *pelf_size
,
4575 struct ac_llvm_compiler
*ac_llvm
)
4577 unsigned retval
= 0;
4578 LLVMContextRef llvm_ctx
;
4580 /* Setup Diagnostic Handler*/
4581 llvm_ctx
= LLVMGetModuleContext(M
);
4583 LLVMContextSetDiagnosticHandler(llvm_ctx
, ac_diagnostic_handler
,
4587 if (!radv_compile_to_elf(ac_llvm
, M
, pelf_buffer
, pelf_size
))
4592 static void ac_compile_llvm_module(struct ac_llvm_compiler
*ac_llvm
,
4593 LLVMModuleRef llvm_module
,
4594 struct radv_shader_binary
**rbinary
,
4595 struct radv_shader_variant_info
*shader_info
,
4596 gl_shader_stage stage
,
4598 const struct radv_nir_compiler_options
*options
)
4600 char *elf_buffer
= NULL
;
4601 size_t elf_size
= 0;
4602 char *llvm_ir_string
= NULL
;
4604 if (options
->dump_shader
) {
4605 fprintf(stderr
, "%s LLVM IR:\n\n", name
);
4606 ac_dump_module(llvm_module
);
4607 fprintf(stderr
, "\n");
4610 if (options
->record_llvm_ir
) {
4611 char *llvm_ir
= LLVMPrintModuleToString(llvm_module
);
4612 llvm_ir_string
= strdup(llvm_ir
);
4613 LLVMDisposeMessage(llvm_ir
);
4616 int v
= radv_llvm_compile(llvm_module
, &elf_buffer
, &elf_size
, ac_llvm
);
4618 fprintf(stderr
, "compile failed\n");
4621 LLVMContextRef ctx
= LLVMGetModuleContext(llvm_module
);
4622 LLVMDisposeModule(llvm_module
);
4623 LLVMContextDispose(ctx
);
4625 size_t llvm_ir_size
= llvm_ir_string
? strlen(llvm_ir_string
) : 0;
4626 size_t alloc_size
= sizeof(struct radv_shader_binary_rtld
) + elf_size
+ llvm_ir_size
+ 1;
4627 struct radv_shader_binary_rtld
*rbin
= calloc(1, alloc_size
);
4628 memcpy(rbin
->data
, elf_buffer
, elf_size
);
4630 memcpy(rbin
->data
+ elf_size
, llvm_ir_string
, llvm_ir_size
+ 1);
4632 rbin
->base
.type
= RADV_BINARY_TYPE_RTLD
;
4633 rbin
->base
.stage
= stage
;
4634 rbin
->base
.total_size
= alloc_size
;
4635 rbin
->elf_size
= elf_size
;
4636 rbin
->llvm_ir_size
= llvm_ir_size
;
4637 *rbinary
= &rbin
->base
;
4639 free(llvm_ir_string
);
4644 ac_fill_shader_info(struct radv_shader_variant_info
*shader_info
, struct nir_shader
*nir
, const struct radv_nir_compiler_options
*options
)
4646 switch (nir
->info
.stage
) {
4647 case MESA_SHADER_COMPUTE
:
4648 for (int i
= 0; i
< 3; ++i
)
4649 shader_info
->cs
.block_size
[i
] = nir
->info
.cs
.local_size
[i
];
4651 case MESA_SHADER_FRAGMENT
:
4652 shader_info
->fs
.early_fragment_test
= nir
->info
.fs
.early_fragment_tests
;
4653 shader_info
->fs
.post_depth_coverage
= nir
->info
.fs
.post_depth_coverage
;
4655 case MESA_SHADER_GEOMETRY
:
4656 shader_info
->gs
.vertices_in
= nir
->info
.gs
.vertices_in
;
4657 shader_info
->gs
.vertices_out
= nir
->info
.gs
.vertices_out
;
4658 shader_info
->gs
.output_prim
= nir
->info
.gs
.output_primitive
;
4659 shader_info
->gs
.invocations
= nir
->info
.gs
.invocations
;
4661 case MESA_SHADER_TESS_EVAL
:
4662 shader_info
->tes
.primitive_mode
= nir
->info
.tess
.primitive_mode
;
4663 shader_info
->tes
.spacing
= nir
->info
.tess
.spacing
;
4664 shader_info
->tes
.ccw
= nir
->info
.tess
.ccw
;
4665 shader_info
->tes
.point_mode
= nir
->info
.tess
.point_mode
;
4666 shader_info
->tes
.as_es
= options
->key
.vs_common_out
.as_es
;
4667 shader_info
->tes
.export_prim_id
= options
->key
.vs_common_out
.export_prim_id
;
4668 shader_info
->is_ngg
= options
->key
.vs_common_out
.as_ngg
;
4670 case MESA_SHADER_TESS_CTRL
:
4671 shader_info
->tcs
.tcs_vertices_out
= nir
->info
.tess
.tcs_vertices_out
;
4673 case MESA_SHADER_VERTEX
:
4674 shader_info
->vs
.as_es
= options
->key
.vs_common_out
.as_es
;
4675 shader_info
->vs
.as_ls
= options
->key
.vs_common_out
.as_ls
;
4676 shader_info
->vs
.export_prim_id
= options
->key
.vs_common_out
.export_prim_id
;
4677 shader_info
->is_ngg
= options
->key
.vs_common_out
.as_ngg
;
4685 radv_compile_nir_shader(struct ac_llvm_compiler
*ac_llvm
,
4686 struct radv_shader_binary
**rbinary
,
4687 struct radv_shader_variant_info
*shader_info
,
4688 struct nir_shader
*const *nir
,
4690 const struct radv_nir_compiler_options
*options
)
4693 LLVMModuleRef llvm_module
;
4695 llvm_module
= ac_translate_nir_to_llvm(ac_llvm
, nir
, nir_count
, shader_info
,
4698 ac_compile_llvm_module(ac_llvm
, llvm_module
, rbinary
, shader_info
,
4699 nir
[nir_count
- 1]->info
.stage
,
4700 radv_get_shader_name(shader_info
,
4701 nir
[nir_count
- 1]->info
.stage
),
4704 for (int i
= 0; i
< nir_count
; ++i
)
4705 ac_fill_shader_info(shader_info
, nir
[i
], options
);
4707 /* Determine the ES type (VS or TES) for the GS on GFX9. */
4708 if (options
->chip_class
>= GFX9
) {
4709 if (nir_count
== 2 &&
4710 nir
[1]->info
.stage
== MESA_SHADER_GEOMETRY
) {
4711 shader_info
->gs
.es_type
= nir
[0]->info
.stage
;
4714 shader_info
->info
.wave_size
= options
->wave_size
;
4718 ac_gs_copy_shader_emit(struct radv_shader_context
*ctx
)
4720 LLVMValueRef vtx_offset
=
4721 LLVMBuildMul(ctx
->ac
.builder
, ctx
->abi
.vertex_id
,
4722 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
4723 LLVMValueRef stream_id
;
4725 /* Fetch the vertex stream ID. */
4726 if (ctx
->shader_info
->info
.so
.num_outputs
) {
4728 ac_unpack_param(&ctx
->ac
, ctx
->streamout_config
, 24, 2);
4730 stream_id
= ctx
->ac
.i32_0
;
4733 LLVMBasicBlockRef end_bb
;
4734 LLVMValueRef switch_inst
;
4736 end_bb
= LLVMAppendBasicBlockInContext(ctx
->ac
.context
,
4737 ctx
->main_function
, "end");
4738 switch_inst
= LLVMBuildSwitch(ctx
->ac
.builder
, stream_id
, end_bb
, 4);
4740 for (unsigned stream
= 0; stream
< 4; stream
++) {
4741 unsigned num_components
=
4742 ctx
->shader_info
->info
.gs
.num_stream_output_components
[stream
];
4743 LLVMBasicBlockRef bb
;
4746 if (!num_components
)
4749 if (stream
> 0 && !ctx
->shader_info
->info
.so
.num_outputs
)
4752 bb
= LLVMInsertBasicBlockInContext(ctx
->ac
.context
, end_bb
, "out");
4753 LLVMAddCase(switch_inst
, LLVMConstInt(ctx
->ac
.i32
, stream
, 0), bb
);
4754 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, bb
);
4757 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
4758 unsigned output_usage_mask
=
4759 ctx
->shader_info
->info
.gs
.output_usage_mask
[i
];
4760 unsigned output_stream
=
4761 ctx
->shader_info
->info
.gs
.output_streams
[i
];
4762 int length
= util_last_bit(output_usage_mask
);
4764 if (!(ctx
->output_mask
& (1ull << i
)) ||
4765 output_stream
!= stream
)
4768 for (unsigned j
= 0; j
< length
; j
++) {
4769 LLVMValueRef value
, soffset
;
4771 if (!(output_usage_mask
& (1 << j
)))
4774 soffset
= LLVMConstInt(ctx
->ac
.i32
,
4776 ctx
->gs_max_out_vertices
* 16 * 4, false);
4780 value
= ac_build_buffer_load(&ctx
->ac
,
4783 vtx_offset
, soffset
,
4784 0, ac_glc
| ac_slc
, true, false);
4786 LLVMTypeRef type
= LLVMGetAllocatedType(ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
4787 if (ac_get_type_size(type
) == 2) {
4788 value
= LLVMBuildBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
4789 value
= LLVMBuildTrunc(ctx
->ac
.builder
, value
, ctx
->ac
.i16
, "");
4792 LLVMBuildStore(ctx
->ac
.builder
,
4793 ac_to_float(&ctx
->ac
, value
), ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
4797 if (ctx
->shader_info
->info
.so
.num_outputs
)
4798 radv_emit_streamout(ctx
, stream
);
4801 handle_vs_outputs_post(ctx
, false, true,
4802 &ctx
->shader_info
->vs
.outinfo
);
4805 LLVMBuildBr(ctx
->ac
.builder
, end_bb
);
4808 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, end_bb
);
4812 radv_compile_gs_copy_shader(struct ac_llvm_compiler
*ac_llvm
,
4813 struct nir_shader
*geom_shader
,
4814 struct radv_shader_binary
**rbinary
,
4815 struct radv_shader_variant_info
*shader_info
,
4816 const struct radv_nir_compiler_options
*options
)
4818 struct radv_shader_context ctx
= {0};
4819 ctx
.options
= options
;
4820 ctx
.shader_info
= shader_info
;
4822 enum ac_float_mode float_mode
=
4823 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
4824 AC_FLOAT_MODE_DEFAULT
;
4826 ac_llvm_context_init(&ctx
.ac
, ac_llvm
, options
->chip_class
,
4827 options
->family
, float_mode
, 64, 64);
4828 ctx
.context
= ctx
.ac
.context
;
4830 ctx
.is_gs_copy_shader
= true;
4831 ctx
.stage
= MESA_SHADER_VERTEX
;
4833 radv_nir_shader_info_pass(geom_shader
, options
, &shader_info
->info
);
4835 create_function(&ctx
, MESA_SHADER_VERTEX
, false, MESA_SHADER_VERTEX
);
4837 ctx
.gs_max_out_vertices
= geom_shader
->info
.gs
.vertices_out
;
4838 ac_setup_rings(&ctx
);
4840 nir_foreach_variable(variable
, &geom_shader
->outputs
) {
4841 scan_shader_output_decl(&ctx
, variable
, geom_shader
, MESA_SHADER_VERTEX
);
4842 ac_handle_shader_output_decl(&ctx
.ac
, &ctx
.abi
, geom_shader
,
4843 variable
, MESA_SHADER_VERTEX
);
4846 ac_gs_copy_shader_emit(&ctx
);
4848 LLVMBuildRetVoid(ctx
.ac
.builder
);
4850 ac_llvm_finalize_module(&ctx
, ac_llvm
->passmgr
, options
);
4852 ac_compile_llvm_module(ac_llvm
, ctx
.ac
.module
, rbinary
, shader_info
,
4853 MESA_SHADER_VERTEX
, "GS Copy Shader", options
);
4854 (*rbinary
)->is_gs_copy_shader
= true;