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radv/gfx10: account for the subpass view for the NGG GS storage
[mesa.git] / src / amd / vulkan / radv_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "radv_shader_helper.h"
31 #include "nir/nir.h"
32
33 #include <llvm-c/Core.h>
34 #include <llvm-c/TargetMachine.h>
35 #include <llvm-c/Transforms/Scalar.h>
36 #include <llvm-c/Transforms/Utils.h>
37
38 #include "sid.h"
39 #include "ac_binary.h"
40 #include "ac_llvm_util.h"
41 #include "ac_llvm_build.h"
42 #include "ac_shader_abi.h"
43 #include "ac_shader_util.h"
44 #include "ac_exp_param.h"
45
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47
48 struct radv_shader_context {
49 struct ac_llvm_context ac;
50 const struct radv_nir_compiler_options *options;
51 struct radv_shader_info *shader_info;
52 const struct nir_shader *shader;
53 struct ac_shader_abi abi;
54
55 unsigned max_workgroup_size;
56 LLVMContextRef context;
57 LLVMValueRef main_function;
58
59 LLVMValueRef descriptor_sets[MAX_SETS];
60 LLVMValueRef ring_offsets;
61
62 LLVMValueRef vertex_buffers;
63 LLVMValueRef rel_auto_id;
64 LLVMValueRef vs_prim_id;
65 LLVMValueRef es2gs_offset;
66
67 LLVMValueRef oc_lds;
68 LLVMValueRef merged_wave_info;
69 LLVMValueRef tess_factor_offset;
70 LLVMValueRef tes_rel_patch_id;
71 LLVMValueRef tes_u;
72 LLVMValueRef tes_v;
73
74 /* HW GS */
75 /* On gfx10:
76 * - bits 0..10: ordered_wave_id
77 * - bits 12..20: number of vertices in group
78 * - bits 22..30: number of primitives in group
79 */
80 LLVMValueRef gs_tg_info;
81 LLVMValueRef gs2vs_offset;
82 LLVMValueRef gs_wave_id;
83 LLVMValueRef gs_vtx_offset[6];
84
85 LLVMValueRef esgs_ring;
86 LLVMValueRef gsvs_ring[4];
87 LLVMValueRef hs_ring_tess_offchip;
88 LLVMValueRef hs_ring_tess_factor;
89
90 /* Streamout */
91 LLVMValueRef streamout_buffers;
92 LLVMValueRef streamout_write_idx;
93 LLVMValueRef streamout_config;
94 LLVMValueRef streamout_offset[4];
95
96 gl_shader_stage stage;
97
98 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
99
100 uint64_t output_mask;
101
102 bool is_gs_copy_shader;
103 LLVMValueRef gs_next_vertex[4];
104 LLVMValueRef gs_curprim_verts[4];
105 LLVMValueRef gs_generated_prims[4];
106 LLVMValueRef gs_ngg_emit;
107 LLVMValueRef gs_ngg_scratch;
108
109 uint32_t tcs_num_inputs;
110 uint32_t tcs_num_patches;
111
112 LLVMValueRef vertexptr; /* GFX10 only */
113 };
114
115 struct radv_shader_output_values {
116 LLVMValueRef values[4];
117 unsigned slot_name;
118 unsigned slot_index;
119 unsigned usage_mask;
120 };
121
122 enum radeon_llvm_calling_convention {
123 RADEON_LLVM_AMDGPU_VS = 87,
124 RADEON_LLVM_AMDGPU_GS = 88,
125 RADEON_LLVM_AMDGPU_PS = 89,
126 RADEON_LLVM_AMDGPU_CS = 90,
127 RADEON_LLVM_AMDGPU_HS = 93,
128 };
129
130 static inline struct radv_shader_context *
131 radv_shader_context_from_abi(struct ac_shader_abi *abi)
132 {
133 struct radv_shader_context *ctx = NULL;
134 return container_of(abi, ctx, abi);
135 }
136
137 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
138 {
139 switch (ctx->stage) {
140 case MESA_SHADER_TESS_CTRL:
141 return ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
142 case MESA_SHADER_TESS_EVAL:
143 return ctx->tes_rel_patch_id;
144 break;
145 default:
146 unreachable("Illegal stage");
147 }
148 }
149
150 static unsigned
151 get_tcs_num_patches(struct radv_shader_context *ctx)
152 {
153 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
154 unsigned num_tcs_output_cp = ctx->shader->info.tess.tcs_vertices_out;
155 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
156 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
157 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->tcs.outputs_written);
158 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->tcs.patch_outputs_written);
159 uint32_t output_vertex_size = num_tcs_outputs * 16;
160 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
161 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
162 unsigned num_patches;
163 unsigned hardware_lds_size;
164
165 /* Ensure that we only need one wave per SIMD so we don't need to check
166 * resource usage. Also ensures that the number of tcs in and out
167 * vertices per threadgroup are at most 256.
168 */
169 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
170 /* Make sure that the data fits in LDS. This assumes the shaders only
171 * use LDS for the inputs and outputs.
172 */
173 hardware_lds_size = 32768;
174
175 /* Looks like STONEY hangs if we use more than 32 KiB LDS in a single
176 * threadgroup, even though there is more than 32 KiB LDS.
177 *
178 * Test: dEQP-VK.tessellation.shader_input_output.barrier
179 */
180 if (ctx->options->chip_class >= GFX7 && ctx->options->family != CHIP_STONEY)
181 hardware_lds_size = 65536;
182
183 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
184 /* Make sure the output data fits in the offchip buffer */
185 num_patches = MIN2(num_patches, (ctx->options->tess_offchip_block_dw_size * 4) / output_patch_size);
186 /* Not necessary for correctness, but improves performance. The
187 * specific value is taken from the proprietary driver.
188 */
189 num_patches = MIN2(num_patches, 40);
190
191 /* GFX6 bug workaround - limit LS-HS threadgroups to only one wave. */
192 if (ctx->options->chip_class == GFX6) {
193 unsigned one_wave = ctx->options->wave_size / MAX2(num_tcs_input_cp, num_tcs_output_cp);
194 num_patches = MIN2(num_patches, one_wave);
195 }
196 return num_patches;
197 }
198
199 static unsigned
200 calculate_tess_lds_size(struct radv_shader_context *ctx)
201 {
202 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
203 unsigned num_tcs_output_cp;
204 unsigned num_tcs_outputs, num_tcs_patch_outputs;
205 unsigned input_vertex_size, output_vertex_size;
206 unsigned input_patch_size, output_patch_size;
207 unsigned pervertex_output_patch_size;
208 unsigned output_patch0_offset;
209 unsigned num_patches;
210 unsigned lds_size;
211
212 num_tcs_output_cp = ctx->shader->info.tess.tcs_vertices_out;
213 num_tcs_outputs = util_last_bit64(ctx->shader_info->tcs.outputs_written);
214 num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->tcs.patch_outputs_written);
215
216 input_vertex_size = ctx->tcs_num_inputs * 16;
217 output_vertex_size = num_tcs_outputs * 16;
218
219 input_patch_size = num_tcs_input_cp * input_vertex_size;
220
221 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
222 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
223
224 num_patches = ctx->tcs_num_patches;
225 output_patch0_offset = input_patch_size * num_patches;
226
227 lds_size = output_patch0_offset + output_patch_size * num_patches;
228 return lds_size;
229 }
230
231 /* Tessellation shaders pass outputs to the next shader using LDS.
232 *
233 * LS outputs = TCS inputs
234 * TCS outputs = TES inputs
235 *
236 * The LDS layout is:
237 * - TCS inputs for patch 0
238 * - TCS inputs for patch 1
239 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
240 * - ...
241 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
242 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
243 * - TCS outputs for patch 1
244 * - Per-patch TCS outputs for patch 1
245 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
246 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
247 * - ...
248 *
249 * All three shaders VS(LS), TCS, TES share the same LDS space.
250 */
251 static LLVMValueRef
252 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
253 {
254 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
255 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
256 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
257
258 input_patch_size /= 4;
259 return LLVMConstInt(ctx->ac.i32, input_patch_size, false);
260 }
261
262 static LLVMValueRef
263 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
264 {
265 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->tcs.outputs_written);
266 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->tcs.patch_outputs_written);
267 uint32_t output_vertex_size = num_tcs_outputs * 16;
268 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
269 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
270 output_patch_size /= 4;
271 return LLVMConstInt(ctx->ac.i32, output_patch_size, false);
272 }
273
274 static LLVMValueRef
275 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
276 {
277 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->tcs.outputs_written);
278 uint32_t output_vertex_size = num_tcs_outputs * 16;
279 output_vertex_size /= 4;
280 return LLVMConstInt(ctx->ac.i32, output_vertex_size, false);
281 }
282
283 static LLVMValueRef
284 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
285 {
286 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
287 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
288 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
289 uint32_t output_patch0_offset = input_patch_size;
290 unsigned num_patches = ctx->tcs_num_patches;
291
292 output_patch0_offset *= num_patches;
293 output_patch0_offset /= 4;
294 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
295 }
296
297 static LLVMValueRef
298 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
299 {
300 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
301 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
302 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
303 uint32_t output_patch0_offset = input_patch_size;
304
305 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->tcs.outputs_written);
306 uint32_t output_vertex_size = num_tcs_outputs * 16;
307 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
308 unsigned num_patches = ctx->tcs_num_patches;
309
310 output_patch0_offset *= num_patches;
311 output_patch0_offset += pervertex_output_patch_size;
312 output_patch0_offset /= 4;
313 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
314 }
315
316 static LLVMValueRef
317 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
318 {
319 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
320 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
321
322 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
323 }
324
325 static LLVMValueRef
326 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
327 {
328 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
329 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
330 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
331
332 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
333 patch0_offset);
334 }
335
336 static LLVMValueRef
337 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
338 {
339 LLVMValueRef patch0_patch_data_offset =
340 get_tcs_out_patch0_patch_data_offset(ctx);
341 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
342 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
343
344 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
345 patch0_patch_data_offset);
346 }
347
348 #define MAX_ARGS 64
349 struct arg_info {
350 LLVMTypeRef types[MAX_ARGS];
351 LLVMValueRef *assign[MAX_ARGS];
352 uint8_t count;
353 uint8_t sgpr_count;
354 uint8_t num_sgprs_used;
355 uint8_t num_vgprs_used;
356 };
357
358 enum ac_arg_regfile {
359 ARG_SGPR,
360 ARG_VGPR,
361 };
362
363 static void
364 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
365 LLVMValueRef *param_ptr)
366 {
367 assert(info->count < MAX_ARGS);
368
369 info->assign[info->count] = param_ptr;
370 info->types[info->count] = type;
371 info->count++;
372
373 if (regfile == ARG_SGPR) {
374 info->num_sgprs_used += ac_get_type_size(type) / 4;
375 info->sgpr_count++;
376 } else {
377 assert(regfile == ARG_VGPR);
378 info->num_vgprs_used += ac_get_type_size(type) / 4;
379 }
380 }
381
382 static void assign_arguments(LLVMValueRef main_function,
383 struct arg_info *info)
384 {
385 unsigned i;
386 for (i = 0; i < info->count; i++) {
387 if (info->assign[i])
388 *info->assign[i] = LLVMGetParam(main_function, i);
389 }
390 }
391
392 static LLVMValueRef
393 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
394 LLVMBuilderRef builder, LLVMTypeRef *return_types,
395 unsigned num_return_elems,
396 struct arg_info *args,
397 unsigned max_workgroup_size,
398 const struct radv_nir_compiler_options *options)
399 {
400 LLVMTypeRef main_function_type, ret_type;
401 LLVMBasicBlockRef main_function_body;
402
403 if (num_return_elems)
404 ret_type = LLVMStructTypeInContext(ctx, return_types,
405 num_return_elems, true);
406 else
407 ret_type = LLVMVoidTypeInContext(ctx);
408
409 /* Setup the function */
410 main_function_type =
411 LLVMFunctionType(ret_type, args->types, args->count, 0);
412 LLVMValueRef main_function =
413 LLVMAddFunction(module, "main", main_function_type);
414 main_function_body =
415 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
416 LLVMPositionBuilderAtEnd(builder, main_function_body);
417
418 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
419 for (unsigned i = 0; i < args->sgpr_count; ++i) {
420 LLVMValueRef P = LLVMGetParam(main_function, i);
421
422 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
423
424 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
425 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
426 ac_add_attr_dereferenceable(P, UINT64_MAX);
427 }
428 }
429
430 if (options->address32_hi) {
431 ac_llvm_add_target_dep_function_attr(main_function,
432 "amdgpu-32bit-address-high-bits",
433 options->address32_hi);
434 }
435
436 ac_llvm_set_workgroup_size(main_function, max_workgroup_size);
437
438 if (options->unsafe_math) {
439 /* These were copied from some LLVM test. */
440 LLVMAddTargetDependentFunctionAttr(main_function,
441 "less-precise-fpmad",
442 "true");
443 LLVMAddTargetDependentFunctionAttr(main_function,
444 "no-infs-fp-math",
445 "true");
446 LLVMAddTargetDependentFunctionAttr(main_function,
447 "no-nans-fp-math",
448 "true");
449 LLVMAddTargetDependentFunctionAttr(main_function,
450 "unsafe-fp-math",
451 "true");
452 LLVMAddTargetDependentFunctionAttr(main_function,
453 "no-signed-zeros-fp-math",
454 "true");
455 }
456 return main_function;
457 }
458
459
460 static void
461 set_loc(struct radv_userdata_info *ud_info, uint8_t *sgpr_idx,
462 uint8_t num_sgprs)
463 {
464 ud_info->sgpr_idx = *sgpr_idx;
465 ud_info->num_sgprs = num_sgprs;
466 *sgpr_idx += num_sgprs;
467 }
468
469 static void
470 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
471 uint8_t num_sgprs)
472 {
473 struct radv_userdata_info *ud_info =
474 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
475 assert(ud_info);
476
477 set_loc(ud_info, sgpr_idx, num_sgprs);
478 }
479
480 static void
481 set_loc_shader_ptr(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx)
482 {
483 bool use_32bit_pointers = idx != AC_UD_SCRATCH_RING_OFFSETS;
484
485 set_loc_shader(ctx, idx, sgpr_idx, use_32bit_pointers ? 1 : 2);
486 }
487
488 static void
489 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx)
490 {
491 struct radv_userdata_locations *locs =
492 &ctx->shader_info->user_sgprs_locs;
493 struct radv_userdata_info *ud_info = &locs->descriptor_sets[idx];
494 assert(ud_info);
495
496 set_loc(ud_info, sgpr_idx, 1);
497
498 locs->descriptor_sets_enabled |= 1 << idx;
499 }
500
501 struct user_sgpr_info {
502 bool need_ring_offsets;
503 bool indirect_all_descriptor_sets;
504 uint8_t remaining_sgprs;
505 };
506
507 static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
508 gl_shader_stage stage)
509 {
510 switch (stage) {
511 case MESA_SHADER_VERTEX:
512 if (ctx->shader_info->needs_multiview_view_index ||
513 (!ctx->options->key.vs_common_out.as_es && !ctx->options->key.vs_common_out.as_ls && ctx->options->key.has_multiview_view_index))
514 return true;
515 break;
516 case MESA_SHADER_TESS_EVAL:
517 if (ctx->shader_info->needs_multiview_view_index || (!ctx->options->key.vs_common_out.as_es && ctx->options->key.has_multiview_view_index))
518 return true;
519 break;
520 case MESA_SHADER_GEOMETRY:
521 case MESA_SHADER_TESS_CTRL:
522 if (ctx->shader_info->needs_multiview_view_index)
523 return true;
524 break;
525 default:
526 break;
527 }
528 return false;
529 }
530
531 static uint8_t
532 count_vs_user_sgprs(struct radv_shader_context *ctx)
533 {
534 uint8_t count = 0;
535
536 if (ctx->shader_info->vs.has_vertex_buffers)
537 count++;
538 count += ctx->shader_info->vs.needs_draw_id ? 3 : 2;
539
540 return count;
541 }
542
543 static void allocate_inline_push_consts(struct radv_shader_context *ctx,
544 struct user_sgpr_info *user_sgpr_info)
545 {
546 uint8_t remaining_sgprs = user_sgpr_info->remaining_sgprs;
547
548 /* Only supported if shaders use push constants. */
549 if (ctx->shader_info->min_push_constant_used == UINT8_MAX)
550 return;
551
552 /* Only supported if shaders don't have indirect push constants. */
553 if (ctx->shader_info->has_indirect_push_constants)
554 return;
555
556 /* Only supported for 32-bit push constants. */
557 if (!ctx->shader_info->has_only_32bit_push_constants)
558 return;
559
560 uint8_t num_push_consts =
561 (ctx->shader_info->max_push_constant_used -
562 ctx->shader_info->min_push_constant_used) / 4;
563
564 /* Check if the number of user SGPRs is large enough. */
565 if (num_push_consts < remaining_sgprs) {
566 ctx->shader_info->num_inline_push_consts = num_push_consts;
567 } else {
568 ctx->shader_info->num_inline_push_consts = remaining_sgprs;
569 }
570
571 /* Clamp to the maximum number of allowed inlined push constants. */
572 if (ctx->shader_info->num_inline_push_consts > AC_MAX_INLINE_PUSH_CONSTS)
573 ctx->shader_info->num_inline_push_consts = AC_MAX_INLINE_PUSH_CONSTS;
574
575 if (ctx->shader_info->num_inline_push_consts == num_push_consts &&
576 !ctx->shader_info->loads_dynamic_offsets) {
577 /* Disable the default push constants path if all constants are
578 * inlined and if shaders don't use dynamic descriptors.
579 */
580 ctx->shader_info->loads_push_constants = false;
581 }
582
583 ctx->shader_info->base_inline_push_consts =
584 ctx->shader_info->min_push_constant_used / 4;
585 }
586
587 static void allocate_user_sgprs(struct radv_shader_context *ctx,
588 gl_shader_stage stage,
589 bool has_previous_stage,
590 gl_shader_stage previous_stage,
591 bool needs_view_index,
592 struct user_sgpr_info *user_sgpr_info)
593 {
594 uint8_t user_sgpr_count = 0;
595
596 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
597
598 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
599 if (stage == MESA_SHADER_GEOMETRY ||
600 stage == MESA_SHADER_VERTEX ||
601 stage == MESA_SHADER_TESS_CTRL ||
602 stage == MESA_SHADER_TESS_EVAL ||
603 ctx->is_gs_copy_shader)
604 user_sgpr_info->need_ring_offsets = true;
605
606 if (stage == MESA_SHADER_FRAGMENT &&
607 ctx->shader_info->ps.needs_sample_positions)
608 user_sgpr_info->need_ring_offsets = true;
609
610 /* 2 user sgprs will nearly always be allocated for scratch/rings */
611 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
612 user_sgpr_count += 2;
613 }
614
615 switch (stage) {
616 case MESA_SHADER_COMPUTE:
617 if (ctx->shader_info->cs.uses_grid_size)
618 user_sgpr_count += 3;
619 break;
620 case MESA_SHADER_FRAGMENT:
621 user_sgpr_count += ctx->shader_info->ps.needs_sample_positions;
622 break;
623 case MESA_SHADER_VERTEX:
624 if (!ctx->is_gs_copy_shader)
625 user_sgpr_count += count_vs_user_sgprs(ctx);
626 break;
627 case MESA_SHADER_TESS_CTRL:
628 if (has_previous_stage) {
629 if (previous_stage == MESA_SHADER_VERTEX)
630 user_sgpr_count += count_vs_user_sgprs(ctx);
631 }
632 break;
633 case MESA_SHADER_TESS_EVAL:
634 break;
635 case MESA_SHADER_GEOMETRY:
636 if (has_previous_stage) {
637 if (previous_stage == MESA_SHADER_VERTEX) {
638 user_sgpr_count += count_vs_user_sgprs(ctx);
639 }
640 }
641 break;
642 default:
643 break;
644 }
645
646 if (needs_view_index)
647 user_sgpr_count++;
648
649 if (ctx->shader_info->loads_push_constants)
650 user_sgpr_count++;
651
652 if (ctx->streamout_buffers)
653 user_sgpr_count++;
654
655 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 && stage != MESA_SHADER_COMPUTE ? 32 : 16;
656 uint32_t remaining_sgprs = available_sgprs - user_sgpr_count;
657 uint32_t num_desc_set =
658 util_bitcount(ctx->shader_info->desc_set_used_mask);
659
660 if (remaining_sgprs < num_desc_set) {
661 user_sgpr_info->indirect_all_descriptor_sets = true;
662 user_sgpr_info->remaining_sgprs = remaining_sgprs - 1;
663 } else {
664 user_sgpr_info->remaining_sgprs = remaining_sgprs - num_desc_set;
665 }
666
667 allocate_inline_push_consts(ctx, user_sgpr_info);
668 }
669
670 static void
671 declare_global_input_sgprs(struct radv_shader_context *ctx,
672 const struct user_sgpr_info *user_sgpr_info,
673 struct arg_info *args,
674 LLVMValueRef *desc_sets)
675 {
676 LLVMTypeRef type = ac_array_in_const32_addr_space(ctx->ac.i8);
677
678 /* 1 for each descriptor set */
679 if (!user_sgpr_info->indirect_all_descriptor_sets) {
680 uint32_t mask = ctx->shader_info->desc_set_used_mask;
681
682 while (mask) {
683 int i = u_bit_scan(&mask);
684
685 add_arg(args, ARG_SGPR, type, &ctx->descriptor_sets[i]);
686 }
687 } else {
688 add_arg(args, ARG_SGPR, ac_array_in_const32_addr_space(type),
689 desc_sets);
690 }
691
692 if (ctx->shader_info->loads_push_constants) {
693 /* 1 for push constants and dynamic descriptors */
694 add_arg(args, ARG_SGPR, type, &ctx->abi.push_constants);
695 }
696
697 for (unsigned i = 0; i < ctx->shader_info->num_inline_push_consts; i++) {
698 add_arg(args, ARG_SGPR, ctx->ac.i32,
699 &ctx->abi.inline_push_consts[i]);
700 }
701 ctx->abi.num_inline_push_consts = ctx->shader_info->num_inline_push_consts;
702 ctx->abi.base_inline_push_consts = ctx->shader_info->base_inline_push_consts;
703
704 if (ctx->shader_info->so.num_outputs) {
705 add_arg(args, ARG_SGPR,
706 ac_array_in_const32_addr_space(ctx->ac.v4i32),
707 &ctx->streamout_buffers);
708 }
709 }
710
711 static void
712 declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
713 gl_shader_stage stage,
714 bool has_previous_stage,
715 gl_shader_stage previous_stage,
716 struct arg_info *args)
717 {
718 if (!ctx->is_gs_copy_shader &&
719 (stage == MESA_SHADER_VERTEX ||
720 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
721 if (ctx->shader_info->vs.has_vertex_buffers) {
722 add_arg(args, ARG_SGPR,
723 ac_array_in_const32_addr_space(ctx->ac.v4i32),
724 &ctx->vertex_buffers);
725 }
726 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
727 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
728 if (ctx->shader_info->vs.needs_draw_id) {
729 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
730 }
731 }
732 }
733
734 static void
735 declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
736 {
737 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
738 if (!ctx->is_gs_copy_shader) {
739 if (ctx->options->key.vs_common_out.as_ls) {
740 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
741 if (ctx->ac.chip_class >= GFX10) {
742 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* user vgpr */
743 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
744 } else {
745 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
746 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
747 }
748 } else {
749 if (ctx->ac.chip_class >= GFX10) {
750 if (ctx->options->key.vs_common_out.as_ngg) {
751 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* user vgpr */
752 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* user vgpr */
753 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
754 } else {
755 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
756 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
757 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
758 }
759 } else {
760 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
761 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
762 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
763 }
764 }
765 }
766 }
767
768 static void
769 declare_streamout_sgprs(struct radv_shader_context *ctx, gl_shader_stage stage,
770 struct arg_info *args)
771 {
772 int i;
773
774 /* Streamout SGPRs. */
775 if (ctx->shader_info->so.num_outputs) {
776 assert(stage == MESA_SHADER_VERTEX ||
777 stage == MESA_SHADER_TESS_EVAL);
778
779 if (stage != MESA_SHADER_TESS_EVAL) {
780 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->streamout_config);
781 } else {
782 args->assign[args->count - 1] = &ctx->streamout_config;
783 args->types[args->count - 1] = ctx->ac.i32;
784 }
785
786 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->streamout_write_idx);
787 }
788
789 /* A streamout buffer offset is loaded if the stride is non-zero. */
790 for (i = 0; i < 4; i++) {
791 if (!ctx->shader_info->so.strides[i])
792 continue;
793
794 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->streamout_offset[i]);
795 }
796 }
797
798 static void
799 declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
800 {
801 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
802 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
803 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
804 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
805 }
806
807 static void
808 set_global_input_locs(struct radv_shader_context *ctx,
809 const struct user_sgpr_info *user_sgpr_info,
810 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
811 {
812 uint32_t mask = ctx->shader_info->desc_set_used_mask;
813
814 if (!user_sgpr_info->indirect_all_descriptor_sets) {
815 while (mask) {
816 int i = u_bit_scan(&mask);
817
818 set_loc_desc(ctx, i, user_sgpr_idx);
819 }
820 } else {
821 set_loc_shader_ptr(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
822 user_sgpr_idx);
823
824 while (mask) {
825 int i = u_bit_scan(&mask);
826
827 ctx->descriptor_sets[i] =
828 ac_build_load_to_sgpr(&ctx->ac, desc_sets,
829 LLVMConstInt(ctx->ac.i32, i, false));
830
831 }
832
833 ctx->shader_info->need_indirect_descriptor_sets = true;
834 }
835
836 if (ctx->shader_info->loads_push_constants) {
837 set_loc_shader_ptr(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx);
838 }
839
840 if (ctx->shader_info->num_inline_push_consts) {
841 set_loc_shader(ctx, AC_UD_INLINE_PUSH_CONSTANTS, user_sgpr_idx,
842 ctx->shader_info->num_inline_push_consts);
843 }
844
845 if (ctx->streamout_buffers) {
846 set_loc_shader_ptr(ctx, AC_UD_STREAMOUT_BUFFERS,
847 user_sgpr_idx);
848 }
849 }
850
851 static void
852 set_vs_specific_input_locs(struct radv_shader_context *ctx,
853 gl_shader_stage stage, bool has_previous_stage,
854 gl_shader_stage previous_stage,
855 uint8_t *user_sgpr_idx)
856 {
857 if (!ctx->is_gs_copy_shader &&
858 (stage == MESA_SHADER_VERTEX ||
859 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
860 if (ctx->shader_info->vs.has_vertex_buffers) {
861 set_loc_shader_ptr(ctx, AC_UD_VS_VERTEX_BUFFERS,
862 user_sgpr_idx);
863 }
864
865 unsigned vs_num = 2;
866 if (ctx->shader_info->vs.needs_draw_id)
867 vs_num++;
868
869 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
870 user_sgpr_idx, vs_num);
871 }
872 }
873
874 static void set_llvm_calling_convention(LLVMValueRef func,
875 gl_shader_stage stage)
876 {
877 enum radeon_llvm_calling_convention calling_conv;
878
879 switch (stage) {
880 case MESA_SHADER_VERTEX:
881 case MESA_SHADER_TESS_EVAL:
882 calling_conv = RADEON_LLVM_AMDGPU_VS;
883 break;
884 case MESA_SHADER_GEOMETRY:
885 calling_conv = RADEON_LLVM_AMDGPU_GS;
886 break;
887 case MESA_SHADER_TESS_CTRL:
888 calling_conv = RADEON_LLVM_AMDGPU_HS;
889 break;
890 case MESA_SHADER_FRAGMENT:
891 calling_conv = RADEON_LLVM_AMDGPU_PS;
892 break;
893 case MESA_SHADER_COMPUTE:
894 calling_conv = RADEON_LLVM_AMDGPU_CS;
895 break;
896 default:
897 unreachable("Unhandle shader type");
898 }
899
900 LLVMSetFunctionCallConv(func, calling_conv);
901 }
902
903 /* Returns whether the stage is a stage that can be directly before the GS */
904 static bool is_pre_gs_stage(gl_shader_stage stage)
905 {
906 return stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL;
907 }
908
909 static void create_function(struct radv_shader_context *ctx,
910 gl_shader_stage stage,
911 bool has_previous_stage,
912 gl_shader_stage previous_stage)
913 {
914 uint8_t user_sgpr_idx;
915 struct user_sgpr_info user_sgpr_info;
916 struct arg_info args = {};
917 LLVMValueRef desc_sets;
918 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
919
920 if (ctx->ac.chip_class >= GFX10) {
921 if (is_pre_gs_stage(stage) && ctx->options->key.vs_common_out.as_ngg) {
922 /* On GFX10, VS is merged into GS for NGG. */
923 previous_stage = stage;
924 stage = MESA_SHADER_GEOMETRY;
925 has_previous_stage = true;
926 }
927 }
928
929 allocate_user_sgprs(ctx, stage, has_previous_stage,
930 previous_stage, needs_view_index, &user_sgpr_info);
931
932 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
933 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
934 &ctx->ring_offsets);
935 }
936
937 switch (stage) {
938 case MESA_SHADER_COMPUTE:
939 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
940 &desc_sets);
941
942 if (ctx->shader_info->cs.uses_grid_size) {
943 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
944 &ctx->abi.num_work_groups);
945 }
946
947 for (int i = 0; i < 3; i++) {
948 ctx->abi.workgroup_ids[i] = NULL;
949 if (ctx->shader_info->cs.uses_block_id[i]) {
950 add_arg(&args, ARG_SGPR, ctx->ac.i32,
951 &ctx->abi.workgroup_ids[i]);
952 }
953 }
954
955 if (ctx->shader_info->cs.uses_local_invocation_idx)
956 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
957 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
958 &ctx->abi.local_invocation_ids);
959 break;
960 case MESA_SHADER_VERTEX:
961 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
962 &desc_sets);
963
964 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
965 previous_stage, &args);
966
967 if (needs_view_index)
968 add_arg(&args, ARG_SGPR, ctx->ac.i32,
969 &ctx->abi.view_index);
970 if (ctx->options->key.vs_common_out.as_es) {
971 add_arg(&args, ARG_SGPR, ctx->ac.i32,
972 &ctx->es2gs_offset);
973 } else if (ctx->options->key.vs_common_out.as_ls) {
974 /* no extra parameters */
975 } else {
976 declare_streamout_sgprs(ctx, stage, &args);
977 }
978
979 declare_vs_input_vgprs(ctx, &args);
980 break;
981 case MESA_SHADER_TESS_CTRL:
982 if (has_previous_stage) {
983 // First 6 system regs
984 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
985 add_arg(&args, ARG_SGPR, ctx->ac.i32,
986 &ctx->merged_wave_info);
987 add_arg(&args, ARG_SGPR, ctx->ac.i32,
988 &ctx->tess_factor_offset);
989
990 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
991 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
992 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
993
994 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
995 &desc_sets);
996
997 declare_vs_specific_input_sgprs(ctx, stage,
998 has_previous_stage,
999 previous_stage, &args);
1000
1001 if (needs_view_index)
1002 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1003 &ctx->abi.view_index);
1004
1005 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1006 &ctx->abi.tcs_patch_id);
1007 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1008 &ctx->abi.tcs_rel_ids);
1009
1010 declare_vs_input_vgprs(ctx, &args);
1011 } else {
1012 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
1013 &desc_sets);
1014
1015 if (needs_view_index)
1016 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1017 &ctx->abi.view_index);
1018
1019 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1020 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1021 &ctx->tess_factor_offset);
1022 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1023 &ctx->abi.tcs_patch_id);
1024 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1025 &ctx->abi.tcs_rel_ids);
1026 }
1027 break;
1028 case MESA_SHADER_TESS_EVAL:
1029 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
1030 &desc_sets);
1031
1032 if (needs_view_index)
1033 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1034 &ctx->abi.view_index);
1035
1036 if (ctx->options->key.vs_common_out.as_es) {
1037 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1038 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
1039 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1040 &ctx->es2gs_offset);
1041 } else {
1042 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
1043 declare_streamout_sgprs(ctx, stage, &args);
1044 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1045 }
1046 declare_tes_input_vgprs(ctx, &args);
1047 break;
1048 case MESA_SHADER_GEOMETRY:
1049 if (has_previous_stage) {
1050 // First 6 system regs
1051 if (ctx->options->key.vs_common_out.as_ngg) {
1052 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1053 &ctx->gs_tg_info);
1054 } else {
1055 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1056 &ctx->gs2vs_offset);
1057 }
1058
1059 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1060 &ctx->merged_wave_info);
1061 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1062
1063 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
1064 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
1065 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
1066
1067 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
1068 &desc_sets);
1069
1070 if (previous_stage != MESA_SHADER_TESS_EVAL) {
1071 declare_vs_specific_input_sgprs(ctx, stage,
1072 has_previous_stage,
1073 previous_stage,
1074 &args);
1075 }
1076
1077 if (needs_view_index)
1078 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1079 &ctx->abi.view_index);
1080
1081 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1082 &ctx->gs_vtx_offset[0]);
1083 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1084 &ctx->gs_vtx_offset[2]);
1085 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1086 &ctx->abi.gs_prim_id);
1087 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1088 &ctx->abi.gs_invocation_id);
1089 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1090 &ctx->gs_vtx_offset[4]);
1091
1092 if (previous_stage == MESA_SHADER_VERTEX) {
1093 declare_vs_input_vgprs(ctx, &args);
1094 } else {
1095 declare_tes_input_vgprs(ctx, &args);
1096 }
1097 } else {
1098 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
1099 &desc_sets);
1100
1101 if (needs_view_index)
1102 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1103 &ctx->abi.view_index);
1104
1105 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
1106 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
1107 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1108 &ctx->gs_vtx_offset[0]);
1109 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1110 &ctx->gs_vtx_offset[1]);
1111 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1112 &ctx->abi.gs_prim_id);
1113 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1114 &ctx->gs_vtx_offset[2]);
1115 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1116 &ctx->gs_vtx_offset[3]);
1117 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1118 &ctx->gs_vtx_offset[4]);
1119 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1120 &ctx->gs_vtx_offset[5]);
1121 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1122 &ctx->abi.gs_invocation_id);
1123 }
1124 break;
1125 case MESA_SHADER_FRAGMENT:
1126 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
1127 &desc_sets);
1128
1129 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
1130 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->abi.persp_sample);
1131 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->abi.persp_center);
1132 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->abi.persp_centroid);
1133 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1134 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->abi.linear_sample);
1135 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->abi.linear_center);
1136 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->abi.linear_centroid);
1137 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1138 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1139 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1140 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1141 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1142 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1143 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1144 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1145 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1146 break;
1147 default:
1148 unreachable("Shader stage not implemented");
1149 }
1150
1151 ctx->main_function = create_llvm_function(
1152 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
1153 ctx->max_workgroup_size, ctx->options);
1154 set_llvm_calling_convention(ctx->main_function, stage);
1155
1156
1157 ctx->shader_info->num_input_vgprs = 0;
1158 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1159
1160 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1161
1162 if (ctx->stage != MESA_SHADER_FRAGMENT)
1163 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1164
1165 assign_arguments(ctx->main_function, &args);
1166
1167 user_sgpr_idx = 0;
1168
1169 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1170 set_loc_shader_ptr(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1171 &user_sgpr_idx);
1172 if (ctx->options->supports_spill) {
1173 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1174 LLVMPointerType(ctx->ac.i8, AC_ADDR_SPACE_CONST),
1175 NULL, 0, AC_FUNC_ATTR_READNONE);
1176 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1177 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1178 }
1179 }
1180
1181 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1182 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1183 if (has_previous_stage)
1184 user_sgpr_idx = 0;
1185
1186 set_global_input_locs(ctx, &user_sgpr_info, desc_sets, &user_sgpr_idx);
1187
1188 switch (stage) {
1189 case MESA_SHADER_COMPUTE:
1190 if (ctx->shader_info->cs.uses_grid_size) {
1191 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1192 &user_sgpr_idx, 3);
1193 }
1194 break;
1195 case MESA_SHADER_VERTEX:
1196 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1197 previous_stage, &user_sgpr_idx);
1198 if (ctx->abi.view_index)
1199 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1200 break;
1201 case MESA_SHADER_TESS_CTRL:
1202 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1203 previous_stage, &user_sgpr_idx);
1204 if (ctx->abi.view_index)
1205 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1206 break;
1207 case MESA_SHADER_TESS_EVAL:
1208 if (ctx->abi.view_index)
1209 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1210 break;
1211 case MESA_SHADER_GEOMETRY:
1212 if (has_previous_stage) {
1213 if (previous_stage == MESA_SHADER_VERTEX)
1214 set_vs_specific_input_locs(ctx, stage,
1215 has_previous_stage,
1216 previous_stage,
1217 &user_sgpr_idx);
1218 }
1219 if (ctx->abi.view_index)
1220 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1221 break;
1222 case MESA_SHADER_FRAGMENT:
1223 break;
1224 default:
1225 unreachable("Shader stage not implemented");
1226 }
1227
1228 if (stage == MESA_SHADER_TESS_CTRL ||
1229 (stage == MESA_SHADER_VERTEX && ctx->options->key.vs_common_out.as_ls) ||
1230 /* GFX9 has the ESGS ring buffer in LDS. */
1231 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
1232 ac_declare_lds_as_pointer(&ctx->ac);
1233 }
1234
1235 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1236 }
1237
1238
1239 static LLVMValueRef
1240 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
1241 unsigned desc_set, unsigned binding)
1242 {
1243 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1244 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1245 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
1246 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
1247 unsigned base_offset = layout->binding[binding].offset;
1248 LLVMValueRef offset, stride;
1249
1250 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1251 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1252 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
1253 layout->binding[binding].dynamic_offset_offset;
1254 desc_ptr = ctx->abi.push_constants;
1255 base_offset = pipeline_layout->push_constant_size + 16 * idx;
1256 stride = LLVMConstInt(ctx->ac.i32, 16, false);
1257 } else
1258 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
1259
1260 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
1261
1262 if (layout->binding[binding].type != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
1263 offset = ac_build_imad(&ctx->ac, index, stride, offset);
1264 }
1265
1266 desc_ptr = LLVMBuildGEP(ctx->ac.builder, desc_ptr, &offset, 1, "");
1267 desc_ptr = ac_cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
1268 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1269
1270 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
1271 uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1272 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1273 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1274 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
1275
1276 if (ctx->ac.chip_class >= GFX10) {
1277 desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
1278 S_008F0C_OOB_SELECT(3) |
1279 S_008F0C_RESOURCE_LEVEL(1);
1280 } else {
1281 desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1282 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1283 }
1284
1285 LLVMValueRef desc_components[4] = {
1286 LLVMBuildPtrToInt(ctx->ac.builder, desc_ptr, ctx->ac.intptr, ""),
1287 LLVMConstInt(ctx->ac.i32, S_008F04_BASE_ADDRESS_HI(ctx->options->address32_hi), false),
1288 /* High limit to support variable sizes. */
1289 LLVMConstInt(ctx->ac.i32, 0xffffffff, false),
1290 LLVMConstInt(ctx->ac.i32, desc_type, false),
1291 };
1292
1293 return ac_build_gather_values(&ctx->ac, desc_components, 4);
1294 }
1295
1296 return desc_ptr;
1297 }
1298
1299
1300 /* The offchip buffer layout for TCS->TES is
1301 *
1302 * - attribute 0 of patch 0 vertex 0
1303 * - attribute 0 of patch 0 vertex 1
1304 * - attribute 0 of patch 0 vertex 2
1305 * ...
1306 * - attribute 0 of patch 1 vertex 0
1307 * - attribute 0 of patch 1 vertex 1
1308 * ...
1309 * - attribute 1 of patch 0 vertex 0
1310 * - attribute 1 of patch 0 vertex 1
1311 * ...
1312 * - per patch attribute 0 of patch 0
1313 * - per patch attribute 0 of patch 1
1314 * ...
1315 *
1316 * Note that every attribute has 4 components.
1317 */
1318 static LLVMValueRef get_non_vertex_index_offset(struct radv_shader_context *ctx)
1319 {
1320 uint32_t num_patches = ctx->tcs_num_patches;
1321 uint32_t num_tcs_outputs;
1322 if (ctx->stage == MESA_SHADER_TESS_CTRL)
1323 num_tcs_outputs = util_last_bit64(ctx->shader_info->tcs.outputs_written);
1324 else
1325 num_tcs_outputs = ctx->options->key.tes.tcs_num_outputs;
1326
1327 uint32_t output_vertex_size = num_tcs_outputs * 16;
1328 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
1329
1330 return LLVMConstInt(ctx->ac.i32, pervertex_output_patch_size * num_patches, false);
1331 }
1332
1333 static LLVMValueRef calc_param_stride(struct radv_shader_context *ctx,
1334 LLVMValueRef vertex_index)
1335 {
1336 LLVMValueRef param_stride;
1337 if (vertex_index)
1338 param_stride = LLVMConstInt(ctx->ac.i32, ctx->shader->info.tess.tcs_vertices_out * ctx->tcs_num_patches, false);
1339 else
1340 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_num_patches, false);
1341 return param_stride;
1342 }
1343
1344 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
1345 LLVMValueRef vertex_index,
1346 LLVMValueRef param_index)
1347 {
1348 LLVMValueRef base_addr;
1349 LLVMValueRef param_stride, constant16;
1350 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
1351 LLVMValueRef vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->shader->info.tess.tcs_vertices_out, false);
1352 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
1353 param_stride = calc_param_stride(ctx, vertex_index);
1354 if (vertex_index) {
1355 base_addr = ac_build_imad(&ctx->ac, rel_patch_id,
1356 vertices_per_patch, vertex_index);
1357 } else {
1358 base_addr = rel_patch_id;
1359 }
1360
1361 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1362 LLVMBuildMul(ctx->ac.builder, param_index,
1363 param_stride, ""), "");
1364
1365 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
1366
1367 if (!vertex_index) {
1368 LLVMValueRef patch_data_offset = get_non_vertex_index_offset(ctx);
1369
1370 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1371 patch_data_offset, "");
1372 }
1373 return base_addr;
1374 }
1375
1376 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
1377 unsigned param,
1378 unsigned const_index,
1379 bool is_compact,
1380 LLVMValueRef vertex_index,
1381 LLVMValueRef indir_index)
1382 {
1383 LLVMValueRef param_index;
1384
1385 if (indir_index)
1386 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
1387 indir_index, "");
1388 else {
1389 if (const_index && !is_compact)
1390 param += const_index;
1391 param_index = LLVMConstInt(ctx->ac.i32, param, false);
1392 }
1393 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
1394 }
1395
1396 static LLVMValueRef
1397 get_dw_address(struct radv_shader_context *ctx,
1398 LLVMValueRef dw_addr,
1399 unsigned param,
1400 unsigned const_index,
1401 bool compact_const_index,
1402 LLVMValueRef vertex_index,
1403 LLVMValueRef stride,
1404 LLVMValueRef indir_index)
1405
1406 {
1407
1408 if (vertex_index) {
1409 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1410 LLVMBuildMul(ctx->ac.builder,
1411 vertex_index,
1412 stride, ""), "");
1413 }
1414
1415 if (indir_index)
1416 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1417 LLVMBuildMul(ctx->ac.builder, indir_index,
1418 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
1419 else if (const_index && !compact_const_index)
1420 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1421 LLVMConstInt(ctx->ac.i32, const_index * 4, false), "");
1422
1423 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1424 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
1425
1426 if (const_index && compact_const_index)
1427 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1428 LLVMConstInt(ctx->ac.i32, const_index, false), "");
1429 return dw_addr;
1430 }
1431
1432 static LLVMValueRef
1433 load_tcs_varyings(struct ac_shader_abi *abi,
1434 LLVMTypeRef type,
1435 LLVMValueRef vertex_index,
1436 LLVMValueRef indir_index,
1437 unsigned const_index,
1438 unsigned location,
1439 unsigned driver_location,
1440 unsigned component,
1441 unsigned num_components,
1442 bool is_patch,
1443 bool is_compact,
1444 bool load_input)
1445 {
1446 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1447 LLVMValueRef dw_addr, stride;
1448 LLVMValueRef value[4], result;
1449 unsigned param = shader_io_get_unique_index(location);
1450
1451 if (load_input) {
1452 uint32_t input_vertex_size = (ctx->tcs_num_inputs * 16) / 4;
1453 stride = LLVMConstInt(ctx->ac.i32, input_vertex_size, false);
1454 dw_addr = get_tcs_in_current_patch_offset(ctx);
1455 } else {
1456 if (!is_patch) {
1457 stride = get_tcs_out_vertex_stride(ctx);
1458 dw_addr = get_tcs_out_current_patch_offset(ctx);
1459 } else {
1460 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1461 stride = NULL;
1462 }
1463 }
1464
1465 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1466 indir_index);
1467
1468 for (unsigned i = 0; i < num_components + component; i++) {
1469 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1470 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1471 ctx->ac.i32_1, "");
1472 }
1473 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1474 return result;
1475 }
1476
1477 static void
1478 store_tcs_output(struct ac_shader_abi *abi,
1479 const nir_variable *var,
1480 LLVMValueRef vertex_index,
1481 LLVMValueRef param_index,
1482 unsigned const_index,
1483 LLVMValueRef src,
1484 unsigned writemask)
1485 {
1486 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1487 const unsigned location = var->data.location;
1488 unsigned component = var->data.location_frac;
1489 const bool is_patch = var->data.patch;
1490 const bool is_compact = var->data.compact;
1491 LLVMValueRef dw_addr;
1492 LLVMValueRef stride = NULL;
1493 LLVMValueRef buf_addr = NULL;
1494 unsigned param;
1495 bool store_lds = true;
1496
1497 if (is_patch) {
1498 if (!(ctx->shader->info.patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
1499 store_lds = false;
1500 } else {
1501 if (!(ctx->shader->info.outputs_read & (1ULL << location)))
1502 store_lds = false;
1503 }
1504
1505 param = shader_io_get_unique_index(location);
1506 if ((location == VARYING_SLOT_CLIP_DIST0 || location == VARYING_SLOT_CLIP_DIST1) && is_compact) {
1507 const_index += component;
1508 component = 0;
1509
1510 if (const_index >= 4) {
1511 const_index -= 4;
1512 param++;
1513 }
1514 }
1515
1516 if (!is_patch) {
1517 stride = get_tcs_out_vertex_stride(ctx);
1518 dw_addr = get_tcs_out_current_patch_offset(ctx);
1519 } else {
1520 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1521 }
1522
1523 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1524 param_index);
1525 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
1526 vertex_index, param_index);
1527
1528 bool is_tess_factor = false;
1529 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
1530 location == VARYING_SLOT_TESS_LEVEL_OUTER)
1531 is_tess_factor = true;
1532
1533 unsigned base = is_compact ? const_index : 0;
1534 for (unsigned chan = 0; chan < 8; chan++) {
1535 if (!(writemask & (1 << chan)))
1536 continue;
1537 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1538 value = ac_to_integer(&ctx->ac, value);
1539 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
1540
1541 if (store_lds || is_tess_factor) {
1542 LLVMValueRef dw_addr_chan =
1543 LLVMBuildAdd(ctx->ac.builder, dw_addr,
1544 LLVMConstInt(ctx->ac.i32, chan, false), "");
1545 ac_lds_store(&ctx->ac, dw_addr_chan, value);
1546 }
1547
1548 if (!is_tess_factor && writemask != 0xF)
1549 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
1550 buf_addr, ctx->oc_lds,
1551 4 * (base + chan), ac_glc, false);
1552 }
1553
1554 if (writemask == 0xF) {
1555 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
1556 buf_addr, ctx->oc_lds,
1557 (base * 4), ac_glc, false);
1558 }
1559 }
1560
1561 static LLVMValueRef
1562 load_tes_input(struct ac_shader_abi *abi,
1563 LLVMTypeRef type,
1564 LLVMValueRef vertex_index,
1565 LLVMValueRef param_index,
1566 unsigned const_index,
1567 unsigned location,
1568 unsigned driver_location,
1569 unsigned component,
1570 unsigned num_components,
1571 bool is_patch,
1572 bool is_compact,
1573 bool load_input)
1574 {
1575 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1576 LLVMValueRef buf_addr;
1577 LLVMValueRef result;
1578 unsigned param = shader_io_get_unique_index(location);
1579
1580 if ((location == VARYING_SLOT_CLIP_DIST0 || location == VARYING_SLOT_CLIP_DIST1) && is_compact) {
1581 const_index += component;
1582 component = 0;
1583 if (const_index >= 4) {
1584 const_index -= 4;
1585 param++;
1586 }
1587 }
1588
1589 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
1590 is_compact, vertex_index, param_index);
1591
1592 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
1593 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
1594
1595 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
1596 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, ac_glc, true, false);
1597 result = ac_trim_vector(&ctx->ac, result, num_components);
1598 return result;
1599 }
1600
1601 static LLVMValueRef
1602 load_gs_input(struct ac_shader_abi *abi,
1603 unsigned location,
1604 unsigned driver_location,
1605 unsigned component,
1606 unsigned num_components,
1607 unsigned vertex_index,
1608 unsigned const_index,
1609 LLVMTypeRef type)
1610 {
1611 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1612 LLVMValueRef vtx_offset;
1613 unsigned param, vtx_offset_param;
1614 LLVMValueRef value[4], result;
1615
1616 vtx_offset_param = vertex_index;
1617 assert(vtx_offset_param < 6);
1618 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
1619 LLVMConstInt(ctx->ac.i32, 4, false), "");
1620
1621 param = shader_io_get_unique_index(location);
1622
1623 for (unsigned i = component; i < num_components + component; i++) {
1624 if (ctx->ac.chip_class >= GFX9) {
1625 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
1626 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1627 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
1628 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1629 } else {
1630 LLVMValueRef soffset =
1631 LLVMConstInt(ctx->ac.i32,
1632 (param * 4 + i + const_index) * 256,
1633 false);
1634
1635 value[i] = ac_build_buffer_load(&ctx->ac,
1636 ctx->esgs_ring, 1,
1637 ctx->ac.i32_0,
1638 vtx_offset, soffset,
1639 0, ac_glc, true, false);
1640 }
1641
1642 if (ac_get_type_size(type) == 2) {
1643 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], ctx->ac.i32, "");
1644 value[i] = LLVMBuildTrunc(ctx->ac.builder, value[i], ctx->ac.i16, "");
1645 }
1646 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], type, "");
1647 }
1648 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1649 result = ac_to_integer(&ctx->ac, result);
1650 return result;
1651 }
1652
1653
1654 static void radv_emit_kill(struct ac_shader_abi *abi, LLVMValueRef visible)
1655 {
1656 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1657 ac_build_kill_if_false(&ctx->ac, visible);
1658 }
1659
1660 static uint32_t
1661 radv_get_sample_pos_offset(uint32_t num_samples)
1662 {
1663 uint32_t sample_pos_offset = 0;
1664
1665 switch (num_samples) {
1666 case 2:
1667 sample_pos_offset = 1;
1668 break;
1669 case 4:
1670 sample_pos_offset = 3;
1671 break;
1672 case 8:
1673 sample_pos_offset = 7;
1674 break;
1675 default:
1676 break;
1677 }
1678 return sample_pos_offset;
1679 }
1680
1681 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
1682 LLVMValueRef sample_id)
1683 {
1684 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1685
1686 LLVMValueRef result;
1687 LLVMValueRef index = LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false);
1688 LLVMValueRef ptr = LLVMBuildGEP(ctx->ac.builder, ctx->ring_offsets, &index, 1, "");
1689
1690 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
1691 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
1692
1693 uint32_t sample_pos_offset =
1694 radv_get_sample_pos_offset(ctx->options->key.fs.num_samples);
1695
1696 sample_id =
1697 LLVMBuildAdd(ctx->ac.builder, sample_id,
1698 LLVMConstInt(ctx->ac.i32, sample_pos_offset, false), "");
1699 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
1700
1701 return result;
1702 }
1703
1704
1705 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1706 {
1707 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1708 uint8_t log2_ps_iter_samples;
1709
1710 if (ctx->shader_info->ps.force_persample) {
1711 log2_ps_iter_samples =
1712 util_logbase2(ctx->options->key.fs.num_samples);
1713 } else {
1714 log2_ps_iter_samples = ctx->options->key.fs.log2_ps_iter_samples;
1715 }
1716
1717 /* The bit pattern matches that used by fixed function fragment
1718 * processing. */
1719 static const uint16_t ps_iter_masks[] = {
1720 0xffff, /* not used */
1721 0x5555,
1722 0x1111,
1723 0x0101,
1724 0x0001,
1725 };
1726 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
1727
1728 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
1729
1730 LLVMValueRef result, sample_id;
1731 sample_id = ac_unpack_param(&ctx->ac, abi->ancillary, 8, 4);
1732 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
1733 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
1734 return result;
1735 }
1736
1737
1738 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context *ctx,
1739 unsigned stream,
1740 LLVMValueRef *addrs);
1741
1742 static void
1743 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
1744 {
1745 LLVMValueRef gs_next_vertex;
1746 LLVMValueRef can_emit;
1747 unsigned offset = 0;
1748 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1749
1750 if (ctx->options->key.vs_common_out.as_ngg) {
1751 gfx10_ngg_gs_emit_vertex(ctx, stream, addrs);
1752 return;
1753 }
1754
1755 /* Write vertex attribute values to GSVS ring */
1756 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
1757 ctx->gs_next_vertex[stream],
1758 "");
1759
1760 /* If this thread has already emitted the declared maximum number of
1761 * vertices, kill it: excessive vertex emissions are not supposed to
1762 * have any effect, and GS threads have no externally observable
1763 * effects other than emitting vertices.
1764 */
1765 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
1766 LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false), "");
1767 ac_build_kill_if_false(&ctx->ac, can_emit);
1768
1769 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
1770 unsigned output_usage_mask =
1771 ctx->shader_info->gs.output_usage_mask[i];
1772 uint8_t output_stream =
1773 ctx->shader_info->gs.output_streams[i];
1774 LLVMValueRef *out_ptr = &addrs[i * 4];
1775 int length = util_last_bit(output_usage_mask);
1776
1777 if (!(ctx->output_mask & (1ull << i)) ||
1778 output_stream != stream)
1779 continue;
1780
1781 for (unsigned j = 0; j < length; j++) {
1782 if (!(output_usage_mask & (1 << j)))
1783 continue;
1784
1785 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
1786 out_ptr[j], "");
1787 LLVMValueRef voffset =
1788 LLVMConstInt(ctx->ac.i32, offset *
1789 ctx->shader->info.gs.vertices_out, false);
1790
1791 offset++;
1792
1793 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
1794 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
1795
1796 out_val = ac_to_integer(&ctx->ac, out_val);
1797 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
1798
1799 ac_build_buffer_store_dword(&ctx->ac,
1800 ctx->gsvs_ring[stream],
1801 out_val, 1,
1802 voffset, ctx->gs2vs_offset, 0,
1803 ac_glc | ac_slc, true);
1804 }
1805 }
1806
1807 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
1808 ctx->ac.i32_1, "");
1809 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
1810
1811 ac_build_sendmsg(&ctx->ac,
1812 AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
1813 ctx->gs_wave_id);
1814 }
1815
1816 static void
1817 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
1818 {
1819 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1820
1821 if (ctx->options->key.vs_common_out.as_ngg) {
1822 LLVMBuildStore(ctx->ac.builder, ctx->ac.i32_0, ctx->gs_curprim_verts[stream]);
1823 return;
1824 }
1825
1826 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
1827 }
1828
1829 static LLVMValueRef
1830 load_tess_coord(struct ac_shader_abi *abi)
1831 {
1832 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1833
1834 LLVMValueRef coord[4] = {
1835 ctx->tes_u,
1836 ctx->tes_v,
1837 ctx->ac.f32_0,
1838 ctx->ac.f32_0,
1839 };
1840
1841 if (ctx->shader->info.tess.primitive_mode == GL_TRIANGLES)
1842 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1843 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
1844
1845 return ac_build_gather_values(&ctx->ac, coord, 3);
1846 }
1847
1848 static LLVMValueRef
1849 load_patch_vertices_in(struct ac_shader_abi *abi)
1850 {
1851 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1852 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
1853 }
1854
1855
1856 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
1857 {
1858 return abi->base_vertex;
1859 }
1860
1861 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
1862 LLVMValueRef buffer_ptr, bool write)
1863 {
1864 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1865 LLVMValueRef result;
1866
1867 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1868
1869 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1870 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1871
1872 return result;
1873 }
1874
1875 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
1876 {
1877 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1878 LLVMValueRef result;
1879
1880 if (LLVMGetTypeKind(LLVMTypeOf(buffer_ptr)) != LLVMPointerTypeKind) {
1881 /* Do not load the descriptor for inlined uniform blocks. */
1882 return buffer_ptr;
1883 }
1884
1885 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1886
1887 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1888 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1889
1890 return result;
1891 }
1892
1893 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
1894 unsigned descriptor_set,
1895 unsigned base_index,
1896 unsigned constant_index,
1897 LLVMValueRef index,
1898 enum ac_descriptor_type desc_type,
1899 bool image, bool write,
1900 bool bindless)
1901 {
1902 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1903 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
1904 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
1905 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
1906 unsigned offset = binding->offset;
1907 unsigned stride = binding->size;
1908 unsigned type_size;
1909 LLVMBuilderRef builder = ctx->ac.builder;
1910 LLVMTypeRef type;
1911
1912 assert(base_index < layout->binding_count);
1913
1914 switch (desc_type) {
1915 case AC_DESC_IMAGE:
1916 type = ctx->ac.v8i32;
1917 type_size = 32;
1918 break;
1919 case AC_DESC_FMASK:
1920 type = ctx->ac.v8i32;
1921 offset += 32;
1922 type_size = 32;
1923 break;
1924 case AC_DESC_SAMPLER:
1925 type = ctx->ac.v4i32;
1926 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER) {
1927 offset += radv_combined_image_descriptor_sampler_offset(binding);
1928 }
1929
1930 type_size = 16;
1931 break;
1932 case AC_DESC_BUFFER:
1933 type = ctx->ac.v4i32;
1934 type_size = 16;
1935 break;
1936 case AC_DESC_PLANE_0:
1937 case AC_DESC_PLANE_1:
1938 case AC_DESC_PLANE_2:
1939 type = ctx->ac.v8i32;
1940 type_size = 32;
1941 offset += 32 * (desc_type - AC_DESC_PLANE_0);
1942 break;
1943 default:
1944 unreachable("invalid desc_type\n");
1945 }
1946
1947 offset += constant_index * stride;
1948
1949 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
1950 (!index || binding->immutable_samplers_equal)) {
1951 if (binding->immutable_samplers_equal)
1952 constant_index = 0;
1953
1954 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
1955
1956 LLVMValueRef constants[] = {
1957 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
1958 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
1959 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
1960 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
1961 };
1962 return ac_build_gather_values(&ctx->ac, constants, 4);
1963 }
1964
1965 assert(stride % type_size == 0);
1966
1967 LLVMValueRef adjusted_index = index;
1968 if (!adjusted_index)
1969 adjusted_index = ctx->ac.i32_0;
1970
1971 adjusted_index = LLVMBuildMul(builder, adjusted_index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
1972
1973 LLVMValueRef val_offset = LLVMConstInt(ctx->ac.i32, offset, 0);
1974 list = LLVMBuildGEP(builder, list, &val_offset, 1, "");
1975 list = LLVMBuildPointerCast(builder, list,
1976 ac_array_in_const32_addr_space(type), "");
1977
1978 LLVMValueRef descriptor = ac_build_load_to_sgpr(&ctx->ac, list, adjusted_index);
1979
1980 /* 3 plane formats always have same size and format for plane 1 & 2, so
1981 * use the tail from plane 1 so that we can store only the first 16 bytes
1982 * of the last plane. */
1983 if (desc_type == AC_DESC_PLANE_2) {
1984 LLVMValueRef descriptor2 = radv_get_sampler_desc(abi, descriptor_set, base_index, constant_index, index, AC_DESC_PLANE_1,image, write, bindless);
1985
1986 LLVMValueRef components[8];
1987 for (unsigned i = 0; i < 4; ++i)
1988 components[i] = ac_llvm_extract_elem(&ctx->ac, descriptor, i);
1989
1990 for (unsigned i = 4; i < 8; ++i)
1991 components[i] = ac_llvm_extract_elem(&ctx->ac, descriptor2, i);
1992 descriptor = ac_build_gather_values(&ctx->ac, components, 8);
1993 }
1994
1995 return descriptor;
1996 }
1997
1998 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
1999 * so we may need to fix it up. */
2000 static LLVMValueRef
2001 adjust_vertex_fetch_alpha(struct radv_shader_context *ctx,
2002 unsigned adjustment,
2003 LLVMValueRef alpha)
2004 {
2005 if (adjustment == RADV_ALPHA_ADJUST_NONE)
2006 return alpha;
2007
2008 LLVMValueRef c30 = LLVMConstInt(ctx->ac.i32, 30, 0);
2009
2010 alpha = LLVMBuildBitCast(ctx->ac.builder, alpha, ctx->ac.f32, "");
2011
2012 if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
2013 alpha = LLVMBuildFPToUI(ctx->ac.builder, alpha, ctx->ac.i32, "");
2014 else
2015 alpha = ac_to_integer(&ctx->ac, alpha);
2016
2017 /* For the integer-like cases, do a natural sign extension.
2018 *
2019 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
2020 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
2021 * exponent.
2022 */
2023 alpha = LLVMBuildShl(ctx->ac.builder, alpha,
2024 adjustment == RADV_ALPHA_ADJUST_SNORM ?
2025 LLVMConstInt(ctx->ac.i32, 7, 0) : c30, "");
2026 alpha = LLVMBuildAShr(ctx->ac.builder, alpha, c30, "");
2027
2028 /* Convert back to the right type. */
2029 if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
2030 LLVMValueRef clamp;
2031 LLVMValueRef neg_one = LLVMConstReal(ctx->ac.f32, -1.0);
2032 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
2033 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, alpha, neg_one, "");
2034 alpha = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, alpha, "");
2035 } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
2036 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
2037 }
2038
2039 return LLVMBuildBitCast(ctx->ac.builder, alpha, ctx->ac.i32, "");
2040 }
2041
2042 static unsigned
2043 get_num_channels_from_data_format(unsigned data_format)
2044 {
2045 switch (data_format) {
2046 case V_008F0C_BUF_DATA_FORMAT_8:
2047 case V_008F0C_BUF_DATA_FORMAT_16:
2048 case V_008F0C_BUF_DATA_FORMAT_32:
2049 return 1;
2050 case V_008F0C_BUF_DATA_FORMAT_8_8:
2051 case V_008F0C_BUF_DATA_FORMAT_16_16:
2052 case V_008F0C_BUF_DATA_FORMAT_32_32:
2053 return 2;
2054 case V_008F0C_BUF_DATA_FORMAT_10_11_11:
2055 case V_008F0C_BUF_DATA_FORMAT_11_11_10:
2056 case V_008F0C_BUF_DATA_FORMAT_32_32_32:
2057 return 3;
2058 case V_008F0C_BUF_DATA_FORMAT_8_8_8_8:
2059 case V_008F0C_BUF_DATA_FORMAT_10_10_10_2:
2060 case V_008F0C_BUF_DATA_FORMAT_2_10_10_10:
2061 case V_008F0C_BUF_DATA_FORMAT_16_16_16_16:
2062 case V_008F0C_BUF_DATA_FORMAT_32_32_32_32:
2063 return 4;
2064 default:
2065 break;
2066 }
2067
2068 return 4;
2069 }
2070
2071 static LLVMValueRef
2072 radv_fixup_vertex_input_fetches(struct radv_shader_context *ctx,
2073 LLVMValueRef value,
2074 unsigned num_channels,
2075 bool is_float)
2076 {
2077 LLVMValueRef zero = is_float ? ctx->ac.f32_0 : ctx->ac.i32_0;
2078 LLVMValueRef one = is_float ? ctx->ac.f32_1 : ctx->ac.i32_1;
2079 LLVMValueRef chan[4];
2080
2081 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMVectorTypeKind) {
2082 unsigned vec_size = LLVMGetVectorSize(LLVMTypeOf(value));
2083
2084 if (num_channels == 4 && num_channels == vec_size)
2085 return value;
2086
2087 num_channels = MIN2(num_channels, vec_size);
2088
2089 for (unsigned i = 0; i < num_channels; i++)
2090 chan[i] = ac_llvm_extract_elem(&ctx->ac, value, i);
2091 } else {
2092 if (num_channels) {
2093 assert(num_channels == 1);
2094 chan[0] = value;
2095 }
2096 }
2097
2098 for (unsigned i = num_channels; i < 4; i++) {
2099 chan[i] = i == 3 ? one : zero;
2100 chan[i] = ac_to_integer(&ctx->ac, chan[i]);
2101 }
2102
2103 return ac_build_gather_values(&ctx->ac, chan, 4);
2104 }
2105
2106 static void
2107 handle_vs_input_decl(struct radv_shader_context *ctx,
2108 struct nir_variable *variable)
2109 {
2110 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
2111 LLVMValueRef t_offset;
2112 LLVMValueRef t_list;
2113 LLVMValueRef input;
2114 LLVMValueRef buffer_index;
2115 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
2116 uint8_t input_usage_mask =
2117 ctx->shader_info->vs.input_usage_mask[variable->data.location];
2118 unsigned num_input_channels = util_last_bit(input_usage_mask);
2119
2120 variable->data.driver_location = variable->data.location * 4;
2121
2122 enum glsl_base_type type = glsl_get_base_type(variable->type);
2123 for (unsigned i = 0; i < attrib_count; ++i) {
2124 LLVMValueRef output[4];
2125 unsigned attrib_index = variable->data.location + i - VERT_ATTRIB_GENERIC0;
2126 unsigned attrib_format = ctx->options->key.vs.vertex_attribute_formats[attrib_index];
2127 unsigned data_format = attrib_format & 0x0f;
2128 unsigned num_format = (attrib_format >> 4) & 0x07;
2129 bool is_float = num_format != V_008F0C_BUF_NUM_FORMAT_UINT &&
2130 num_format != V_008F0C_BUF_NUM_FORMAT_SINT;
2131
2132 if (ctx->options->key.vs.instance_rate_inputs & (1u << attrib_index)) {
2133 uint32_t divisor = ctx->options->key.vs.instance_rate_divisors[attrib_index];
2134
2135 if (divisor) {
2136 buffer_index = ctx->abi.instance_id;
2137
2138 if (divisor != 1) {
2139 buffer_index = LLVMBuildUDiv(ctx->ac.builder, buffer_index,
2140 LLVMConstInt(ctx->ac.i32, divisor, 0), "");
2141 }
2142 } else {
2143 buffer_index = ctx->ac.i32_0;
2144 }
2145
2146 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.start_instance, buffer_index, "");
2147 } else
2148 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
2149 ctx->abi.base_vertex, "");
2150
2151 /* Adjust the number of channels to load based on the vertex
2152 * attribute format.
2153 */
2154 unsigned num_format_channels = get_num_channels_from_data_format(data_format);
2155 unsigned num_channels = MIN2(num_input_channels, num_format_channels);
2156 unsigned attrib_binding = ctx->options->key.vs.vertex_attribute_bindings[attrib_index];
2157 unsigned attrib_offset = ctx->options->key.vs.vertex_attribute_offsets[attrib_index];
2158 unsigned attrib_stride = ctx->options->key.vs.vertex_attribute_strides[attrib_index];
2159
2160 if (ctx->options->key.vs.post_shuffle & (1 << attrib_index)) {
2161 /* Always load, at least, 3 channels for formats that
2162 * need to be shuffled because X<->Z.
2163 */
2164 num_channels = MAX2(num_channels, 3);
2165 }
2166
2167 if (attrib_stride != 0 && attrib_offset > attrib_stride) {
2168 LLVMValueRef buffer_offset =
2169 LLVMConstInt(ctx->ac.i32,
2170 attrib_offset / attrib_stride, false);
2171
2172 buffer_index = LLVMBuildAdd(ctx->ac.builder,
2173 buffer_index,
2174 buffer_offset, "");
2175
2176 attrib_offset = attrib_offset % attrib_stride;
2177 }
2178
2179 t_offset = LLVMConstInt(ctx->ac.i32, attrib_binding, false);
2180 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
2181
2182 input = ac_build_struct_tbuffer_load(&ctx->ac, t_list,
2183 buffer_index,
2184 LLVMConstInt(ctx->ac.i32, attrib_offset, false),
2185 ctx->ac.i32_0, ctx->ac.i32_0,
2186 num_channels,
2187 data_format, num_format, 0, true);
2188
2189 if (ctx->options->key.vs.post_shuffle & (1 << attrib_index)) {
2190 LLVMValueRef c[4];
2191 c[0] = ac_llvm_extract_elem(&ctx->ac, input, 2);
2192 c[1] = ac_llvm_extract_elem(&ctx->ac, input, 1);
2193 c[2] = ac_llvm_extract_elem(&ctx->ac, input, 0);
2194 c[3] = ac_llvm_extract_elem(&ctx->ac, input, 3);
2195
2196 input = ac_build_gather_values(&ctx->ac, c, 4);
2197 }
2198
2199 input = radv_fixup_vertex_input_fetches(ctx, input, num_channels,
2200 is_float);
2201
2202 for (unsigned chan = 0; chan < 4; chan++) {
2203 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
2204 output[chan] = LLVMBuildExtractElement(ctx->ac.builder, input, llvm_chan, "");
2205 if (type == GLSL_TYPE_FLOAT16) {
2206 output[chan] = LLVMBuildBitCast(ctx->ac.builder, output[chan], ctx->ac.f32, "");
2207 output[chan] = LLVMBuildFPTrunc(ctx->ac.builder, output[chan], ctx->ac.f16, "");
2208 }
2209 }
2210
2211 unsigned alpha_adjust = (ctx->options->key.vs.alpha_adjust >> (attrib_index * 2)) & 3;
2212 output[3] = adjust_vertex_fetch_alpha(ctx, alpha_adjust, output[3]);
2213
2214 for (unsigned chan = 0; chan < 4; chan++) {
2215 output[chan] = ac_to_integer(&ctx->ac, output[chan]);
2216 if (type == GLSL_TYPE_UINT16 || type == GLSL_TYPE_INT16)
2217 output[chan] = LLVMBuildTrunc(ctx->ac.builder, output[chan], ctx->ac.i16, "");
2218
2219 ctx->inputs[ac_llvm_reg_index_soa(variable->data.location + i, chan)] = output[chan];
2220 }
2221 }
2222 }
2223
2224 static void
2225 handle_vs_inputs(struct radv_shader_context *ctx,
2226 struct nir_shader *nir) {
2227 nir_foreach_variable(variable, &nir->inputs)
2228 handle_vs_input_decl(ctx, variable);
2229 }
2230
2231 static void
2232 prepare_interp_optimize(struct radv_shader_context *ctx,
2233 struct nir_shader *nir)
2234 {
2235 bool uses_center = false;
2236 bool uses_centroid = false;
2237 nir_foreach_variable(variable, &nir->inputs) {
2238 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
2239 variable->data.sample)
2240 continue;
2241
2242 if (variable->data.centroid)
2243 uses_centroid = true;
2244 else
2245 uses_center = true;
2246 }
2247
2248 if (uses_center && uses_centroid) {
2249 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
2250 ctx->abi.persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->abi.persp_center, ctx->abi.persp_centroid, "");
2251 ctx->abi.linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->abi.linear_center, ctx->abi.linear_centroid, "");
2252 }
2253 }
2254
2255 static void
2256 scan_shader_output_decl(struct radv_shader_context *ctx,
2257 struct nir_variable *variable,
2258 struct nir_shader *shader,
2259 gl_shader_stage stage)
2260 {
2261 int idx = variable->data.location + variable->data.index;
2262 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
2263 uint64_t mask_attribs;
2264
2265 variable->data.driver_location = idx * 4;
2266
2267 /* tess ctrl has it's own load/store paths for outputs */
2268 if (stage == MESA_SHADER_TESS_CTRL)
2269 return;
2270
2271 if (variable->data.compact) {
2272 unsigned component_count = variable->data.location_frac +
2273 glsl_get_length(variable->type);
2274 attrib_count = (component_count + 3) / 4;
2275 }
2276
2277 mask_attribs = ((1ull << attrib_count) - 1) << idx;
2278
2279 ctx->output_mask |= mask_attribs;
2280 }
2281
2282
2283 /* Initialize arguments for the shader export intrinsic */
2284 static void
2285 si_llvm_init_export_args(struct radv_shader_context *ctx,
2286 LLVMValueRef *values,
2287 unsigned enabled_channels,
2288 unsigned target,
2289 struct ac_export_args *args)
2290 {
2291 /* Specify the channels that are enabled. */
2292 args->enabled_channels = enabled_channels;
2293
2294 /* Specify whether the EXEC mask represents the valid mask */
2295 args->valid_mask = 0;
2296
2297 /* Specify whether this is the last export */
2298 args->done = 0;
2299
2300 /* Specify the target we are exporting */
2301 args->target = target;
2302
2303 args->compr = false;
2304 args->out[0] = LLVMGetUndef(ctx->ac.f32);
2305 args->out[1] = LLVMGetUndef(ctx->ac.f32);
2306 args->out[2] = LLVMGetUndef(ctx->ac.f32);
2307 args->out[3] = LLVMGetUndef(ctx->ac.f32);
2308
2309 if (!values)
2310 return;
2311
2312 bool is_16bit = ac_get_type_size(LLVMTypeOf(values[0])) == 2;
2313 if (ctx->stage == MESA_SHADER_FRAGMENT) {
2314 unsigned index = target - V_008DFC_SQ_EXP_MRT;
2315 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
2316 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
2317 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
2318 unsigned chan;
2319
2320 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2321 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2322 unsigned bits, bool hi) = NULL;
2323
2324 switch(col_format) {
2325 case V_028714_SPI_SHADER_ZERO:
2326 args->enabled_channels = 0; /* writemask */
2327 args->target = V_008DFC_SQ_EXP_NULL;
2328 break;
2329
2330 case V_028714_SPI_SHADER_32_R:
2331 args->enabled_channels = 1;
2332 args->out[0] = values[0];
2333 break;
2334
2335 case V_028714_SPI_SHADER_32_GR:
2336 args->enabled_channels = 0x3;
2337 args->out[0] = values[0];
2338 args->out[1] = values[1];
2339 break;
2340
2341 case V_028714_SPI_SHADER_32_AR:
2342 if (ctx->ac.chip_class >= GFX10) {
2343 args->enabled_channels = 0x3;
2344 args->out[0] = values[0];
2345 args->out[1] = values[3];
2346 } else {
2347 args->enabled_channels = 0x9;
2348 args->out[0] = values[0];
2349 args->out[3] = values[3];
2350 }
2351 break;
2352
2353 case V_028714_SPI_SHADER_FP16_ABGR:
2354 args->enabled_channels = 0x5;
2355 packf = ac_build_cvt_pkrtz_f16;
2356 if (is_16bit) {
2357 for (unsigned chan = 0; chan < 4; chan++)
2358 values[chan] = LLVMBuildFPExt(ctx->ac.builder,
2359 values[chan],
2360 ctx->ac.f32, "");
2361 }
2362 break;
2363
2364 case V_028714_SPI_SHADER_UNORM16_ABGR:
2365 args->enabled_channels = 0x5;
2366 packf = ac_build_cvt_pknorm_u16;
2367 break;
2368
2369 case V_028714_SPI_SHADER_SNORM16_ABGR:
2370 args->enabled_channels = 0x5;
2371 packf = ac_build_cvt_pknorm_i16;
2372 break;
2373
2374 case V_028714_SPI_SHADER_UINT16_ABGR:
2375 args->enabled_channels = 0x5;
2376 packi = ac_build_cvt_pk_u16;
2377 if (is_16bit) {
2378 for (unsigned chan = 0; chan < 4; chan++)
2379 values[chan] = LLVMBuildZExt(ctx->ac.builder,
2380 ac_to_integer(&ctx->ac, values[chan]),
2381 ctx->ac.i32, "");
2382 }
2383 break;
2384
2385 case V_028714_SPI_SHADER_SINT16_ABGR:
2386 args->enabled_channels = 0x5;
2387 packi = ac_build_cvt_pk_i16;
2388 if (is_16bit) {
2389 for (unsigned chan = 0; chan < 4; chan++)
2390 values[chan] = LLVMBuildSExt(ctx->ac.builder,
2391 ac_to_integer(&ctx->ac, values[chan]),
2392 ctx->ac.i32, "");
2393 }
2394 break;
2395
2396 default:
2397 case V_028714_SPI_SHADER_32_ABGR:
2398 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2399 break;
2400 }
2401
2402 /* Pack f16 or norm_i16/u16. */
2403 if (packf) {
2404 for (chan = 0; chan < 2; chan++) {
2405 LLVMValueRef pack_args[2] = {
2406 values[2 * chan],
2407 values[2 * chan + 1]
2408 };
2409 LLVMValueRef packed;
2410
2411 packed = packf(&ctx->ac, pack_args);
2412 args->out[chan] = ac_to_float(&ctx->ac, packed);
2413 }
2414 args->compr = 1; /* COMPR flag */
2415 }
2416
2417 /* Pack i16/u16. */
2418 if (packi) {
2419 for (chan = 0; chan < 2; chan++) {
2420 LLVMValueRef pack_args[2] = {
2421 ac_to_integer(&ctx->ac, values[2 * chan]),
2422 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2423 };
2424 LLVMValueRef packed;
2425
2426 packed = packi(&ctx->ac, pack_args,
2427 is_int8 ? 8 : is_int10 ? 10 : 16,
2428 chan == 1);
2429 args->out[chan] = ac_to_float(&ctx->ac, packed);
2430 }
2431 args->compr = 1; /* COMPR flag */
2432 }
2433 return;
2434 }
2435
2436 if (is_16bit) {
2437 for (unsigned chan = 0; chan < 4; chan++) {
2438 values[chan] = LLVMBuildBitCast(ctx->ac.builder, values[chan], ctx->ac.i16, "");
2439 args->out[chan] = LLVMBuildZExt(ctx->ac.builder, values[chan], ctx->ac.i32, "");
2440 }
2441 } else
2442 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2443
2444 for (unsigned i = 0; i < 4; ++i)
2445 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
2446 }
2447
2448 static void
2449 radv_export_param(struct radv_shader_context *ctx, unsigned index,
2450 LLVMValueRef *values, unsigned enabled_channels)
2451 {
2452 struct ac_export_args args;
2453
2454 si_llvm_init_export_args(ctx, values, enabled_channels,
2455 V_008DFC_SQ_EXP_PARAM + index, &args);
2456 ac_build_export(&ctx->ac, &args);
2457 }
2458
2459 static LLVMValueRef
2460 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
2461 {
2462 LLVMValueRef output = ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
2463 return LLVMBuildLoad(ctx->ac.builder, output, "");
2464 }
2465
2466 static void
2467 radv_emit_stream_output(struct radv_shader_context *ctx,
2468 LLVMValueRef const *so_buffers,
2469 LLVMValueRef const *so_write_offsets,
2470 const struct radv_stream_output *output,
2471 struct radv_shader_output_values *shader_out)
2472 {
2473 unsigned num_comps = util_bitcount(output->component_mask);
2474 unsigned buf = output->buffer;
2475 unsigned offset = output->offset;
2476 unsigned start;
2477 LLVMValueRef out[4];
2478
2479 assert(num_comps && num_comps <= 4);
2480 if (!num_comps || num_comps > 4)
2481 return;
2482
2483 /* Get the first component. */
2484 start = ffs(output->component_mask) - 1;
2485
2486 /* Load the output as int. */
2487 for (int i = 0; i < num_comps; i++) {
2488 out[i] = ac_to_integer(&ctx->ac, shader_out->values[start + i]);
2489 }
2490
2491 /* Pack the output. */
2492 LLVMValueRef vdata = NULL;
2493
2494 switch (num_comps) {
2495 case 1: /* as i32 */
2496 vdata = out[0];
2497 break;
2498 case 2: /* as v2i32 */
2499 case 3: /* as v4i32 (aligned to 4) */
2500 out[3] = LLVMGetUndef(ctx->ac.i32);
2501 /* fall through */
2502 case 4: /* as v4i32 */
2503 vdata = ac_build_gather_values(&ctx->ac, out,
2504 !ac_has_vec3_support(ctx->ac.chip_class, false) ?
2505 util_next_power_of_two(num_comps) :
2506 num_comps);
2507 break;
2508 }
2509
2510 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf],
2511 vdata, num_comps, so_write_offsets[buf],
2512 ctx->ac.i32_0, offset,
2513 ac_glc | ac_slc, false);
2514 }
2515
2516 static void
2517 radv_emit_streamout(struct radv_shader_context *ctx, unsigned stream)
2518 {
2519 int i;
2520
2521 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2522 assert(ctx->streamout_config);
2523 LLVMValueRef so_vtx_count =
2524 ac_build_bfe(&ctx->ac, ctx->streamout_config,
2525 LLVMConstInt(ctx->ac.i32, 16, false),
2526 LLVMConstInt(ctx->ac.i32, 7, false), false);
2527
2528 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2529
2530 /* can_emit = tid < so_vtx_count; */
2531 LLVMValueRef can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
2532 tid, so_vtx_count, "");
2533
2534 /* Emit the streamout code conditionally. This actually avoids
2535 * out-of-bounds buffer access. The hw tells us via the SGPR
2536 * (so_vtx_count) which threads are allowed to emit streamout data.
2537 */
2538 ac_build_ifcc(&ctx->ac, can_emit, 6501);
2539 {
2540 /* The buffer offset is computed as follows:
2541 * ByteOffset = streamout_offset[buffer_id]*4 +
2542 * (streamout_write_index + thread_id)*stride[buffer_id] +
2543 * attrib_offset
2544 */
2545 LLVMValueRef so_write_index = ctx->streamout_write_idx;
2546
2547 /* Compute (streamout_write_index + thread_id). */
2548 so_write_index =
2549 LLVMBuildAdd(ctx->ac.builder, so_write_index, tid, "");
2550
2551 /* Load the descriptor and compute the write offset for each
2552 * enabled buffer.
2553 */
2554 LLVMValueRef so_write_offset[4] = {};
2555 LLVMValueRef so_buffers[4] = {};
2556 LLVMValueRef buf_ptr = ctx->streamout_buffers;
2557
2558 for (i = 0; i < 4; i++) {
2559 uint16_t stride = ctx->shader_info->so.strides[i];
2560
2561 if (!stride)
2562 continue;
2563
2564 LLVMValueRef offset =
2565 LLVMConstInt(ctx->ac.i32, i, false);
2566
2567 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac,
2568 buf_ptr, offset);
2569
2570 LLVMValueRef so_offset = ctx->streamout_offset[i];
2571
2572 so_offset = LLVMBuildMul(ctx->ac.builder, so_offset,
2573 LLVMConstInt(ctx->ac.i32, 4, false), "");
2574
2575 so_write_offset[i] =
2576 ac_build_imad(&ctx->ac, so_write_index,
2577 LLVMConstInt(ctx->ac.i32,
2578 stride * 4, false),
2579 so_offset);
2580 }
2581
2582 /* Write streamout data. */
2583 for (i = 0; i < ctx->shader_info->so.num_outputs; i++) {
2584 struct radv_shader_output_values shader_out = {};
2585 struct radv_stream_output *output =
2586 &ctx->shader_info->so.outputs[i];
2587
2588 if (stream != output->stream)
2589 continue;
2590
2591 for (int j = 0; j < 4; j++) {
2592 shader_out.values[j] =
2593 radv_load_output(ctx, output->location, j);
2594 }
2595
2596 radv_emit_stream_output(ctx, so_buffers,so_write_offset,
2597 output, &shader_out);
2598 }
2599 }
2600 ac_build_endif(&ctx->ac, 6501);
2601 }
2602
2603 static void
2604 radv_build_param_exports(struct radv_shader_context *ctx,
2605 struct radv_shader_output_values *outputs,
2606 unsigned noutput,
2607 struct radv_vs_output_info *outinfo,
2608 bool export_clip_dists)
2609 {
2610 unsigned param_count = 0;
2611
2612 for (unsigned i = 0; i < noutput; i++) {
2613 unsigned slot_name = outputs[i].slot_name;
2614 unsigned usage_mask = outputs[i].usage_mask;
2615
2616 if (slot_name != VARYING_SLOT_LAYER &&
2617 slot_name != VARYING_SLOT_PRIMITIVE_ID &&
2618 slot_name != VARYING_SLOT_CLIP_DIST0 &&
2619 slot_name != VARYING_SLOT_CLIP_DIST1 &&
2620 slot_name < VARYING_SLOT_VAR0)
2621 continue;
2622
2623 if ((slot_name == VARYING_SLOT_CLIP_DIST0 ||
2624 slot_name == VARYING_SLOT_CLIP_DIST1) && !export_clip_dists)
2625 continue;
2626
2627 radv_export_param(ctx, param_count, outputs[i].values, usage_mask);
2628
2629 assert(i < ARRAY_SIZE(outinfo->vs_output_param_offset));
2630 outinfo->vs_output_param_offset[slot_name] = param_count++;
2631 }
2632
2633 outinfo->param_exports = param_count;
2634 }
2635
2636 /* Generate export instructions for hardware VS shader stage or NGG GS stage
2637 * (position and parameter data only).
2638 */
2639 static void
2640 radv_llvm_export_vs(struct radv_shader_context *ctx,
2641 struct radv_shader_output_values *outputs,
2642 unsigned noutput,
2643 struct radv_vs_output_info *outinfo,
2644 bool export_clip_dists)
2645 {
2646 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_value = NULL;
2647 struct ac_export_args pos_args[4] = {};
2648 unsigned pos_idx, index;
2649 int i;
2650
2651 /* Build position exports */
2652 for (i = 0; i < noutput; i++) {
2653 switch (outputs[i].slot_name) {
2654 case VARYING_SLOT_POS:
2655 si_llvm_init_export_args(ctx, outputs[i].values, 0xf,
2656 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2657 break;
2658 case VARYING_SLOT_PSIZ:
2659 psize_value = outputs[i].values[0];
2660 break;
2661 case VARYING_SLOT_LAYER:
2662 layer_value = outputs[i].values[0];
2663 break;
2664 case VARYING_SLOT_VIEWPORT:
2665 viewport_value = outputs[i].values[0];
2666 break;
2667 case VARYING_SLOT_CLIP_DIST0:
2668 case VARYING_SLOT_CLIP_DIST1:
2669 index = 2 + outputs[i].slot_index;
2670 si_llvm_init_export_args(ctx, outputs[i].values, 0xf,
2671 V_008DFC_SQ_EXP_POS + index,
2672 &pos_args[index]);
2673 break;
2674 default:
2675 break;
2676 }
2677 }
2678
2679 /* We need to add the position output manually if it's missing. */
2680 if (!pos_args[0].out[0]) {
2681 pos_args[0].enabled_channels = 0xf; /* writemask */
2682 pos_args[0].valid_mask = 0; /* EXEC mask */
2683 pos_args[0].done = 0; /* last export? */
2684 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2685 pos_args[0].compr = 0; /* COMPR flag */
2686 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
2687 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
2688 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
2689 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
2690 }
2691
2692 if (outinfo->writes_pointsize ||
2693 outinfo->writes_layer ||
2694 outinfo->writes_viewport_index) {
2695 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
2696 (outinfo->writes_layer == true ? 4 : 0));
2697 pos_args[1].valid_mask = 0;
2698 pos_args[1].done = 0;
2699 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2700 pos_args[1].compr = 0;
2701 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2702 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2703 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2704 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2705
2706 if (outinfo->writes_pointsize == true)
2707 pos_args[1].out[0] = psize_value;
2708 if (outinfo->writes_layer == true)
2709 pos_args[1].out[2] = layer_value;
2710 if (outinfo->writes_viewport_index == true) {
2711 if (ctx->options->chip_class >= GFX9) {
2712 /* GFX9 has the layer in out.z[10:0] and the viewport
2713 * index in out.z[19:16].
2714 */
2715 LLVMValueRef v = viewport_value;
2716 v = ac_to_integer(&ctx->ac, v);
2717 v = LLVMBuildShl(ctx->ac.builder, v,
2718 LLVMConstInt(ctx->ac.i32, 16, false),
2719 "");
2720 v = LLVMBuildOr(ctx->ac.builder, v,
2721 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2722
2723 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2724 pos_args[1].enabled_channels |= 1 << 2;
2725 } else {
2726 pos_args[1].out[3] = viewport_value;
2727 pos_args[1].enabled_channels |= 1 << 3;
2728 }
2729 }
2730 }
2731
2732 for (i = 0; i < 4; i++) {
2733 if (pos_args[i].out[0])
2734 outinfo->pos_exports++;
2735 }
2736
2737 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
2738 * Setting valid_mask=1 prevents it and has no other effect.
2739 */
2740 if (ctx->ac.family == CHIP_NAVI10 ||
2741 ctx->ac.family == CHIP_NAVI12 ||
2742 ctx->ac.family == CHIP_NAVI14)
2743 pos_args[0].valid_mask = 1;
2744
2745 pos_idx = 0;
2746 for (i = 0; i < 4; i++) {
2747 if (!pos_args[i].out[0])
2748 continue;
2749
2750 /* Specify the target we are exporting */
2751 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2752
2753 if (pos_idx == outinfo->pos_exports)
2754 /* Specify that this is the last export */
2755 pos_args[i].done = 1;
2756
2757 ac_build_export(&ctx->ac, &pos_args[i]);
2758 }
2759
2760 /* Build parameter exports */
2761 radv_build_param_exports(ctx, outputs, noutput, outinfo, export_clip_dists);
2762 }
2763
2764 static void
2765 handle_vs_outputs_post(struct radv_shader_context *ctx,
2766 bool export_prim_id,
2767 bool export_clip_dists,
2768 struct radv_vs_output_info *outinfo)
2769 {
2770 struct radv_shader_output_values *outputs;
2771 unsigned noutput = 0;
2772
2773 if (ctx->options->key.has_multiview_view_index) {
2774 LLVMValueRef* tmp_out = &ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2775 if(!*tmp_out) {
2776 for(unsigned i = 0; i < 4; ++i)
2777 ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
2778 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
2779 }
2780
2781 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
2782 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
2783 }
2784
2785 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
2786 sizeof(outinfo->vs_output_param_offset));
2787 outinfo->pos_exports = 0;
2788
2789 if (ctx->shader_info->so.num_outputs &&
2790 !ctx->is_gs_copy_shader) {
2791 /* The GS copy shader emission already emits streamout. */
2792 radv_emit_streamout(ctx, 0);
2793 }
2794
2795 /* Allocate a temporary array for the output values. */
2796 unsigned num_outputs = util_bitcount64(ctx->output_mask) + export_prim_id;
2797 outputs = malloc(num_outputs * sizeof(outputs[0]));
2798
2799 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2800 if (!(ctx->output_mask & (1ull << i)))
2801 continue;
2802
2803 outputs[noutput].slot_name = i;
2804 outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
2805
2806 if (ctx->stage == MESA_SHADER_VERTEX &&
2807 !ctx->is_gs_copy_shader) {
2808 outputs[noutput].usage_mask =
2809 ctx->shader_info->vs.output_usage_mask[i];
2810 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
2811 outputs[noutput].usage_mask =
2812 ctx->shader_info->tes.output_usage_mask[i];
2813 } else {
2814 assert(ctx->is_gs_copy_shader);
2815 outputs[noutput].usage_mask =
2816 ctx->shader_info->gs.output_usage_mask[i];
2817 }
2818
2819 for (unsigned j = 0; j < 4; j++) {
2820 outputs[noutput].values[j] =
2821 ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2822 }
2823
2824 noutput++;
2825 }
2826
2827 /* Export PrimitiveID. */
2828 if (export_prim_id) {
2829 outputs[noutput].slot_name = VARYING_SLOT_PRIMITIVE_ID;
2830 outputs[noutput].slot_index = 0;
2831 outputs[noutput].usage_mask = 0x1;
2832 outputs[noutput].values[0] = ctx->vs_prim_id;
2833 for (unsigned j = 1; j < 4; j++)
2834 outputs[noutput].values[j] = ctx->ac.f32_0;
2835 noutput++;
2836 }
2837
2838 radv_llvm_export_vs(ctx, outputs, noutput, outinfo, export_clip_dists);
2839
2840 free(outputs);
2841 }
2842
2843 static void
2844 handle_es_outputs_post(struct radv_shader_context *ctx,
2845 struct radv_es_output_info *outinfo)
2846 {
2847 int j;
2848 LLVMValueRef lds_base = NULL;
2849
2850 if (ctx->ac.chip_class >= GFX9) {
2851 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
2852 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
2853 LLVMValueRef wave_idx = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 24, 4);
2854 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
2855 LLVMBuildMul(ctx->ac.builder, wave_idx,
2856 LLVMConstInt(ctx->ac.i32,
2857 ctx->ac.wave_size, false), ""), "");
2858 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
2859 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
2860 }
2861
2862 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2863 LLVMValueRef dw_addr = NULL;
2864 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2865 unsigned output_usage_mask;
2866 int param_index;
2867
2868 if (!(ctx->output_mask & (1ull << i)))
2869 continue;
2870
2871 if (ctx->stage == MESA_SHADER_VERTEX) {
2872 output_usage_mask =
2873 ctx->shader_info->vs.output_usage_mask[i];
2874 } else {
2875 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2876 output_usage_mask =
2877 ctx->shader_info->tes.output_usage_mask[i];
2878 }
2879
2880 param_index = shader_io_get_unique_index(i);
2881
2882 if (lds_base) {
2883 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2884 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
2885 "");
2886 }
2887
2888 for (j = 0; j < 4; j++) {
2889 if (!(output_usage_mask & (1 << j)))
2890 continue;
2891
2892 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2893 out_val = ac_to_integer(&ctx->ac, out_val);
2894 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
2895
2896 if (ctx->ac.chip_class >= GFX9) {
2897 LLVMValueRef dw_addr_offset =
2898 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2899 LLVMConstInt(ctx->ac.i32,
2900 j, false), "");
2901
2902 ac_lds_store(&ctx->ac, dw_addr_offset, out_val);
2903 } else {
2904 ac_build_buffer_store_dword(&ctx->ac,
2905 ctx->esgs_ring,
2906 out_val, 1,
2907 NULL, ctx->es2gs_offset,
2908 (4 * param_index + j) * 4,
2909 ac_glc | ac_slc, true);
2910 }
2911 }
2912 }
2913 }
2914
2915 static void
2916 handle_ls_outputs_post(struct radv_shader_context *ctx)
2917 {
2918 LLVMValueRef vertex_id = ctx->rel_auto_id;
2919 uint32_t num_tcs_inputs = util_last_bit64(ctx->shader_info->vs.ls_outputs_written);
2920 LLVMValueRef vertex_dw_stride = LLVMConstInt(ctx->ac.i32, num_tcs_inputs * 4, false);
2921 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
2922 vertex_dw_stride, "");
2923
2924 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2925 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2926
2927 if (!(ctx->output_mask & (1ull << i)))
2928 continue;
2929
2930 int param = shader_io_get_unique_index(i);
2931 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
2932 LLVMConstInt(ctx->ac.i32, param * 4, false),
2933 "");
2934 for (unsigned j = 0; j < 4; j++) {
2935 LLVMValueRef value = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2936 value = ac_to_integer(&ctx->ac, value);
2937 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
2938 ac_lds_store(&ctx->ac, dw_addr, value);
2939 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2940 }
2941 }
2942 }
2943
2944 static LLVMValueRef get_wave_id_in_tg(struct radv_shader_context *ctx)
2945 {
2946 return ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 24, 4);
2947 }
2948
2949 static LLVMValueRef get_tgsize(struct radv_shader_context *ctx)
2950 {
2951 return ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 28, 4);
2952 }
2953
2954 static LLVMValueRef get_thread_id_in_tg(struct radv_shader_context *ctx)
2955 {
2956 LLVMBuilderRef builder = ctx->ac.builder;
2957 LLVMValueRef tmp;
2958 tmp = LLVMBuildMul(builder, get_wave_id_in_tg(ctx),
2959 LLVMConstInt(ctx->ac.i32, ctx->ac.wave_size, false), "");
2960 return LLVMBuildAdd(builder, tmp, ac_get_thread_id(&ctx->ac), "");
2961 }
2962
2963 static LLVMValueRef ngg_get_vtx_cnt(struct radv_shader_context *ctx)
2964 {
2965 return ac_build_bfe(&ctx->ac, ctx->gs_tg_info,
2966 LLVMConstInt(ctx->ac.i32, 12, false),
2967 LLVMConstInt(ctx->ac.i32, 9, false),
2968 false);
2969 }
2970
2971 static LLVMValueRef ngg_get_prim_cnt(struct radv_shader_context *ctx)
2972 {
2973 return ac_build_bfe(&ctx->ac, ctx->gs_tg_info,
2974 LLVMConstInt(ctx->ac.i32, 22, false),
2975 LLVMConstInt(ctx->ac.i32, 9, false),
2976 false);
2977 }
2978
2979 static LLVMValueRef
2980 ngg_gs_get_vertex_storage(struct radv_shader_context *ctx)
2981 {
2982 unsigned num_outputs = util_bitcount64(ctx->output_mask);
2983
2984 if (ctx->options->key.has_multiview_view_index)
2985 num_outputs++;
2986
2987 LLVMTypeRef elements[2] = {
2988 LLVMArrayType(ctx->ac.i32, 4 * num_outputs),
2989 LLVMArrayType(ctx->ac.i8, 4),
2990 };
2991 LLVMTypeRef type = LLVMStructTypeInContext(ctx->ac.context, elements, 2, false);
2992 type = LLVMPointerType(LLVMArrayType(type, 0), AC_ADDR_SPACE_LDS);
2993 return LLVMBuildBitCast(ctx->ac.builder, ctx->gs_ngg_emit, type, "");
2994 }
2995
2996 /**
2997 * Return a pointer to the LDS storage reserved for the N'th vertex, where N
2998 * is in emit order; that is:
2999 * - during the epilogue, N is the threadidx (relative to the entire threadgroup)
3000 * - during vertex emit, i.e. while the API GS shader invocation is running,
3001 * N = threadidx * gs_max_out_vertices + emitidx
3002 *
3003 * Goals of the LDS memory layout:
3004 * 1. Eliminate bank conflicts on write for geometry shaders that have all emits
3005 * in uniform control flow
3006 * 2. Eliminate bank conflicts on read for export if, additionally, there is no
3007 * culling
3008 * 3. Agnostic to the number of waves (since we don't know it before compiling)
3009 * 4. Allow coalescing of LDS instructions (ds_write_b128 etc.)
3010 * 5. Avoid wasting memory.
3011 *
3012 * We use an AoS layout due to point 4 (this also helps point 3). In an AoS
3013 * layout, elimination of bank conflicts requires that each vertex occupy an
3014 * odd number of dwords. We use the additional dword to store the output stream
3015 * index as well as a flag to indicate whether this vertex ends a primitive
3016 * for rasterization.
3017 *
3018 * Swizzling is required to satisfy points 1 and 2 simultaneously.
3019 *
3020 * Vertices are stored in export order (gsthread * gs_max_out_vertices + emitidx).
3021 * Indices are swizzled in groups of 32, which ensures point 1 without
3022 * disturbing point 2.
3023 *
3024 * \return an LDS pointer to type {[N x i32], [4 x i8]}
3025 */
3026 static LLVMValueRef
3027 ngg_gs_vertex_ptr(struct radv_shader_context *ctx, LLVMValueRef vertexidx)
3028 {
3029 LLVMBuilderRef builder = ctx->ac.builder;
3030 LLVMValueRef storage = ngg_gs_get_vertex_storage(ctx);
3031
3032 /* gs_max_out_vertices = 2^(write_stride_2exp) * some odd number */
3033 unsigned write_stride_2exp = ffs(ctx->shader->info.gs.vertices_out) - 1;
3034 if (write_stride_2exp) {
3035 LLVMValueRef row =
3036 LLVMBuildLShr(builder, vertexidx,
3037 LLVMConstInt(ctx->ac.i32, 5, false), "");
3038 LLVMValueRef swizzle =
3039 LLVMBuildAnd(builder, row,
3040 LLVMConstInt(ctx->ac.i32, (1u << write_stride_2exp) - 1,
3041 false), "");
3042 vertexidx = LLVMBuildXor(builder, vertexidx, swizzle, "");
3043 }
3044
3045 return ac_build_gep0(&ctx->ac, storage, vertexidx);
3046 }
3047
3048 static LLVMValueRef
3049 ngg_gs_emit_vertex_ptr(struct radv_shader_context *ctx, LLVMValueRef gsthread,
3050 LLVMValueRef emitidx)
3051 {
3052 LLVMBuilderRef builder = ctx->ac.builder;
3053 LLVMValueRef tmp;
3054
3055 tmp = LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false);
3056 tmp = LLVMBuildMul(builder, tmp, gsthread, "");
3057 const LLVMValueRef vertexidx = LLVMBuildAdd(builder, tmp, emitidx, "");
3058 return ngg_gs_vertex_ptr(ctx, vertexidx);
3059 }
3060
3061 /* Send GS Alloc Req message from the first wave of the group to SPI.
3062 * Message payload is:
3063 * - bits 0..10: vertices in group
3064 * - bits 12..22: primitives in group
3065 */
3066 static void build_sendmsg_gs_alloc_req(struct radv_shader_context *ctx,
3067 LLVMValueRef vtx_cnt,
3068 LLVMValueRef prim_cnt)
3069 {
3070 LLVMBuilderRef builder = ctx->ac.builder;
3071 LLVMValueRef tmp;
3072
3073 tmp = LLVMBuildICmp(builder, LLVMIntEQ, get_wave_id_in_tg(ctx), ctx->ac.i32_0, "");
3074 ac_build_ifcc(&ctx->ac, tmp, 5020);
3075
3076 tmp = LLVMBuildShl(builder, prim_cnt, LLVMConstInt(ctx->ac.i32, 12, false),"");
3077 tmp = LLVMBuildOr(builder, tmp, vtx_cnt, "");
3078 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_ALLOC_REQ, tmp);
3079
3080 ac_build_endif(&ctx->ac, 5020);
3081 }
3082
3083 struct ngg_prim {
3084 unsigned num_vertices;
3085 LLVMValueRef isnull;
3086 LLVMValueRef index[3];
3087 LLVMValueRef edgeflag[3];
3088 };
3089
3090 static void build_export_prim(struct radv_shader_context *ctx,
3091 const struct ngg_prim *prim)
3092 {
3093 LLVMBuilderRef builder = ctx->ac.builder;
3094 struct ac_export_args args;
3095 LLVMValueRef tmp;
3096
3097 tmp = LLVMBuildZExt(builder, prim->isnull, ctx->ac.i32, "");
3098 args.out[0] = LLVMBuildShl(builder, tmp, LLVMConstInt(ctx->ac.i32, 31, false), "");
3099
3100 for (unsigned i = 0; i < prim->num_vertices; ++i) {
3101 tmp = LLVMBuildShl(builder, prim->index[i],
3102 LLVMConstInt(ctx->ac.i32, 10 * i, false), "");
3103 args.out[0] = LLVMBuildOr(builder, args.out[0], tmp, "");
3104 tmp = LLVMBuildZExt(builder, prim->edgeflag[i], ctx->ac.i32, "");
3105 tmp = LLVMBuildShl(builder, tmp,
3106 LLVMConstInt(ctx->ac.i32, 10 * i + 9, false), "");
3107 args.out[0] = LLVMBuildOr(builder, args.out[0], tmp, "");
3108 }
3109
3110 args.out[0] = LLVMBuildBitCast(builder, args.out[0], ctx->ac.f32, "");
3111 args.out[1] = LLVMGetUndef(ctx->ac.f32);
3112 args.out[2] = LLVMGetUndef(ctx->ac.f32);
3113 args.out[3] = LLVMGetUndef(ctx->ac.f32);
3114
3115 args.target = V_008DFC_SQ_EXP_PRIM;
3116 args.enabled_channels = 1;
3117 args.done = true;
3118 args.valid_mask = false;
3119 args.compr = false;
3120
3121 ac_build_export(&ctx->ac, &args);
3122 }
3123
3124 static void
3125 handle_ngg_outputs_post(struct radv_shader_context *ctx)
3126 {
3127 LLVMBuilderRef builder = ctx->ac.builder;
3128 unsigned num_vertices = 3;
3129 LLVMValueRef tmp;
3130
3131 assert((ctx->stage == MESA_SHADER_VERTEX ||
3132 ctx->stage == MESA_SHADER_TESS_EVAL) && !ctx->is_gs_copy_shader);
3133
3134 LLVMValueRef prims_in_wave = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 8, 8);
3135 LLVMValueRef vtx_in_wave = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 0, 8);
3136 LLVMValueRef is_gs_thread = LLVMBuildICmp(builder, LLVMIntULT,
3137 ac_get_thread_id(&ctx->ac), prims_in_wave, "");
3138 LLVMValueRef is_es_thread = LLVMBuildICmp(builder, LLVMIntULT,
3139 ac_get_thread_id(&ctx->ac), vtx_in_wave, "");
3140 LLVMValueRef vtxindex[] = {
3141 ac_unpack_param(&ctx->ac, ctx->gs_vtx_offset[0], 0, 16),
3142 ac_unpack_param(&ctx->ac, ctx->gs_vtx_offset[0], 16, 16),
3143 ac_unpack_param(&ctx->ac, ctx->gs_vtx_offset[2], 0, 16),
3144 };
3145
3146 /* TODO: streamout */
3147
3148 /* Copy Primitive IDs from GS threads to the LDS address corresponding
3149 * to the ES thread of the provoking vertex.
3150 */
3151 if (ctx->stage == MESA_SHADER_VERTEX &&
3152 ctx->options->key.vs_common_out.export_prim_id) {
3153 /* TODO: streamout */
3154
3155 ac_build_ifcc(&ctx->ac, is_gs_thread, 5400);
3156 /* Extract the PROVOKING_VTX_INDEX field. */
3157 LLVMValueRef provoking_vtx_in_prim =
3158 LLVMConstInt(ctx->ac.i32, 0, false);
3159
3160 /* provoking_vtx_index = vtxindex[provoking_vtx_in_prim]; */
3161 LLVMValueRef indices = ac_build_gather_values(&ctx->ac, vtxindex, 3);
3162 LLVMValueRef provoking_vtx_index =
3163 LLVMBuildExtractElement(builder, indices, provoking_vtx_in_prim, "");
3164
3165 LLVMBuildStore(builder, ctx->abi.gs_prim_id,
3166 ac_build_gep0(&ctx->ac, ctx->esgs_ring, provoking_vtx_index));
3167 ac_build_endif(&ctx->ac, 5400);
3168 }
3169
3170 /* TODO: primitive culling */
3171
3172 build_sendmsg_gs_alloc_req(ctx, ngg_get_vtx_cnt(ctx), ngg_get_prim_cnt(ctx));
3173
3174 /* TODO: streamout queries */
3175 /* Export primitive data to the index buffer. Format is:
3176 * - bits 0..8: index 0
3177 * - bit 9: edge flag 0
3178 * - bits 10..18: index 1
3179 * - bit 19: edge flag 1
3180 * - bits 20..28: index 2
3181 * - bit 29: edge flag 2
3182 * - bit 31: null primitive (skip)
3183 *
3184 * For the first version, we will always build up all three indices
3185 * independent of the primitive type. The additional garbage data
3186 * shouldn't hurt.
3187 *
3188 * TODO: culling depends on the primitive type, so can have some
3189 * interaction here.
3190 */
3191 ac_build_ifcc(&ctx->ac, is_gs_thread, 6001);
3192 {
3193 struct ngg_prim prim = {};
3194
3195 prim.num_vertices = num_vertices;
3196 prim.isnull = ctx->ac.i1false;
3197 memcpy(prim.index, vtxindex, sizeof(vtxindex[0]) * 3);
3198
3199 for (unsigned i = 0; i < num_vertices; ++i) {
3200 tmp = LLVMBuildLShr(builder, ctx->abi.gs_invocation_id,
3201 LLVMConstInt(ctx->ac.i32, 8 + i, false), "");
3202 prim.edgeflag[i] = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3203 }
3204
3205 build_export_prim(ctx, &prim);
3206 }
3207 ac_build_endif(&ctx->ac, 6001);
3208
3209 /* Export per-vertex data (positions and parameters). */
3210 ac_build_ifcc(&ctx->ac, is_es_thread, 6002);
3211 {
3212 struct radv_vs_output_info *outinfo =
3213 ctx->stage == MESA_SHADER_TESS_EVAL ? &ctx->shader_info->tes.outinfo : &ctx->shader_info->vs.outinfo;
3214
3215 /* Exporting the primitive ID is handled below. */
3216 /* TODO: use the new VS export path */
3217 handle_vs_outputs_post(ctx, false,
3218 ctx->options->key.vs_common_out.export_clip_dists,
3219 outinfo);
3220
3221 if (ctx->options->key.vs_common_out.export_prim_id) {
3222 unsigned param_count = outinfo->param_exports;
3223 LLVMValueRef values[4];
3224
3225 if (ctx->stage == MESA_SHADER_VERTEX) {
3226 /* Wait for GS stores to finish. */
3227 ac_build_s_barrier(&ctx->ac);
3228
3229 tmp = ac_build_gep0(&ctx->ac, ctx->esgs_ring,
3230 get_thread_id_in_tg(ctx));
3231 values[0] = LLVMBuildLoad(builder, tmp, "");
3232 } else {
3233 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
3234 values[0] = ctx->abi.tes_patch_id;
3235 }
3236
3237 values[0] = ac_to_float(&ctx->ac, values[0]);
3238 for (unsigned j = 1; j < 4; j++)
3239 values[j] = ctx->ac.f32_0;
3240
3241 radv_export_param(ctx, param_count, values, 0x1);
3242
3243 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
3244 outinfo->param_exports = param_count;
3245 }
3246 }
3247 ac_build_endif(&ctx->ac, 6002);
3248 }
3249
3250 static void gfx10_ngg_gs_emit_prologue(struct radv_shader_context *ctx)
3251 {
3252 /* Zero out the part of LDS scratch that is used to accumulate the
3253 * per-stream generated primitive count.
3254 */
3255 LLVMBuilderRef builder = ctx->ac.builder;
3256 LLVMValueRef scratchptr = ctx->gs_ngg_scratch;
3257 LLVMValueRef tid = get_thread_id_in_tg(ctx);
3258 LLVMBasicBlockRef merge_block;
3259 LLVMValueRef cond;
3260
3261 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
3262 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
3263 merge_block = LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
3264
3265 cond = LLVMBuildICmp(builder, LLVMIntULT, tid, LLVMConstInt(ctx->ac.i32, 4, false), "");
3266 LLVMBuildCondBr(ctx->ac.builder, cond, then_block, merge_block);
3267 LLVMPositionBuilderAtEnd(ctx->ac.builder, then_block);
3268
3269 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, scratchptr, tid);
3270 LLVMBuildStore(builder, ctx->ac.i32_0, ptr);
3271
3272 LLVMBuildBr(ctx->ac.builder, merge_block);
3273 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
3274
3275 ac_build_s_barrier(&ctx->ac);
3276 }
3277
3278 static void gfx10_ngg_gs_emit_epilogue_1(struct radv_shader_context *ctx)
3279 {
3280 LLVMBuilderRef builder = ctx->ac.builder;
3281 LLVMValueRef i8_0 = LLVMConstInt(ctx->ac.i8, 0, false);
3282 LLVMValueRef tmp;
3283
3284 /* Zero out remaining (non-emitted) primitive flags.
3285 *
3286 * Note: Alternatively, we could pass the relevant gs_next_vertex to
3287 * the emit threads via LDS. This is likely worse in the expected
3288 * typical case where each GS thread emits the full set of
3289 * vertices.
3290 */
3291 for (unsigned stream = 0; stream < 4; ++stream) {
3292 unsigned num_components;
3293
3294 num_components =
3295 ctx->shader_info->gs.num_stream_output_components[stream];
3296 if (!num_components)
3297 continue;
3298
3299 const LLVMValueRef gsthread = get_thread_id_in_tg(ctx);
3300
3301 ac_build_bgnloop(&ctx->ac, 5100);
3302
3303 const LLVMValueRef vertexidx =
3304 LLVMBuildLoad(builder, ctx->gs_next_vertex[stream], "");
3305 tmp = LLVMBuildICmp(builder, LLVMIntUGE, vertexidx,
3306 LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false), "");
3307 ac_build_ifcc(&ctx->ac, tmp, 5101);
3308 ac_build_break(&ctx->ac);
3309 ac_build_endif(&ctx->ac, 5101);
3310
3311 tmp = LLVMBuildAdd(builder, vertexidx, ctx->ac.i32_1, "");
3312 LLVMBuildStore(builder, tmp, ctx->gs_next_vertex[stream]);
3313
3314 tmp = ngg_gs_emit_vertex_ptr(ctx, gsthread, vertexidx);
3315 LLVMValueRef gep_idx[3] = {
3316 ctx->ac.i32_0, /* implied C-style array */
3317 ctx->ac.i32_1, /* second entry of struct */
3318 LLVMConstInt(ctx->ac.i32, stream, false),
3319 };
3320 tmp = LLVMBuildGEP(builder, tmp, gep_idx, 3, "");
3321 LLVMBuildStore(builder, i8_0, tmp);
3322
3323 ac_build_endloop(&ctx->ac, 5100);
3324 }
3325 }
3326
3327 static void gfx10_ngg_gs_emit_epilogue_2(struct radv_shader_context *ctx)
3328 {
3329 const unsigned verts_per_prim = si_conv_gl_prim_to_vertices(ctx->shader->info.gs.output_primitive);
3330 LLVMBuilderRef builder = ctx->ac.builder;
3331 LLVMValueRef tmp, tmp2;
3332
3333 ac_build_s_barrier(&ctx->ac);
3334
3335 const LLVMValueRef tid = get_thread_id_in_tg(ctx);
3336 LLVMValueRef num_emit_threads = ngg_get_prim_cnt(ctx);
3337
3338 /* TODO: streamout */
3339
3340 /* TODO: culling */
3341
3342 /* Determine vertex liveness. */
3343 LLVMValueRef vertliveptr = ac_build_alloca(&ctx->ac, ctx->ac.i1, "vertexlive");
3344
3345 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
3346 ac_build_ifcc(&ctx->ac, tmp, 5120);
3347 {
3348 for (unsigned i = 0; i < verts_per_prim; ++i) {
3349 const LLVMValueRef primidx =
3350 LLVMBuildAdd(builder, tid,
3351 LLVMConstInt(ctx->ac.i32, i, false), "");
3352
3353 if (i > 0) {
3354 tmp = LLVMBuildICmp(builder, LLVMIntULT, primidx, num_emit_threads, "");
3355 ac_build_ifcc(&ctx->ac, tmp, 5121 + i);
3356 }
3357
3358 /* Load primitive liveness */
3359 tmp = ngg_gs_vertex_ptr(ctx, primidx);
3360 LLVMValueRef gep_idx[3] = {
3361 ctx->ac.i32_0, /* implicit C-style array */
3362 ctx->ac.i32_1, /* second value of struct */
3363 ctx->ac.i32_0, /* stream 0 */
3364 };
3365 tmp = LLVMBuildGEP(builder, tmp, gep_idx, 3, "");
3366 tmp = LLVMBuildLoad(builder, tmp, "");
3367 const LLVMValueRef primlive =
3368 LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3369
3370 tmp = LLVMBuildLoad(builder, vertliveptr, "");
3371 tmp = LLVMBuildOr(builder, tmp, primlive, ""),
3372 LLVMBuildStore(builder, tmp, vertliveptr);
3373
3374 if (i > 0)
3375 ac_build_endif(&ctx->ac, 5121 + i);
3376 }
3377 }
3378 ac_build_endif(&ctx->ac, 5120);
3379
3380 /* Inclusive scan addition across the current wave. */
3381 LLVMValueRef vertlive = LLVMBuildLoad(builder, vertliveptr, "");
3382 struct ac_wg_scan vertlive_scan = {};
3383 vertlive_scan.op = nir_op_iadd;
3384 vertlive_scan.enable_reduce = true;
3385 vertlive_scan.enable_exclusive = true;
3386 vertlive_scan.src = vertlive;
3387 vertlive_scan.scratch = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, ctx->ac.i32_0);
3388 vertlive_scan.waveidx = get_wave_id_in_tg(ctx);
3389 vertlive_scan.numwaves = get_tgsize(ctx);
3390 vertlive_scan.maxwaves = 8;
3391
3392 ac_build_wg_scan(&ctx->ac, &vertlive_scan);
3393
3394 /* Skip all exports (including index exports) when possible. At least on
3395 * early gfx10 revisions this is also to avoid hangs.
3396 */
3397 LLVMValueRef have_exports =
3398 LLVMBuildICmp(builder, LLVMIntNE, vertlive_scan.result_reduce, ctx->ac.i32_0, "");
3399 num_emit_threads =
3400 LLVMBuildSelect(builder, have_exports, num_emit_threads, ctx->ac.i32_0, "");
3401
3402 /* Allocate export space. Send this message as early as possible, to
3403 * hide the latency of the SQ <-> SPI roundtrip.
3404 *
3405 * Note: We could consider compacting primitives for export as well.
3406 * PA processes 1 non-null prim / clock, but it fetches 4 DW of
3407 * prim data per clock and skips null primitives at no additional
3408 * cost. So compacting primitives can only be beneficial when
3409 * there are 4 or more contiguous null primitives in the export
3410 * (in the common case of single-dword prim exports).
3411 */
3412 build_sendmsg_gs_alloc_req(ctx, vertlive_scan.result_reduce, num_emit_threads);
3413
3414 /* Setup the reverse vertex compaction permutation. We re-use stream 1
3415 * of the primitive liveness flags, relying on the fact that each
3416 * threadgroup can have at most 256 threads. */
3417 ac_build_ifcc(&ctx->ac, vertlive, 5130);
3418 {
3419 tmp = ngg_gs_vertex_ptr(ctx, vertlive_scan.result_exclusive);
3420 LLVMValueRef gep_idx[3] = {
3421 ctx->ac.i32_0, /* implicit C-style array */
3422 ctx->ac.i32_1, /* second value of struct */
3423 ctx->ac.i32_1, /* stream 1 */
3424 };
3425 tmp = LLVMBuildGEP(builder, tmp, gep_idx, 3, "");
3426 tmp2 = LLVMBuildTrunc(builder, tid, ctx->ac.i8, "");
3427 LLVMBuildStore(builder, tmp2, tmp);
3428 }
3429 ac_build_endif(&ctx->ac, 5130);
3430
3431 ac_build_s_barrier(&ctx->ac);
3432
3433 /* Export primitive data */
3434 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
3435 ac_build_ifcc(&ctx->ac, tmp, 5140);
3436 {
3437 struct ngg_prim prim = {};
3438 prim.num_vertices = verts_per_prim;
3439
3440 tmp = ngg_gs_vertex_ptr(ctx, tid);
3441 LLVMValueRef gep_idx[3] = {
3442 ctx->ac.i32_0, /* implicit C-style array */
3443 ctx->ac.i32_1, /* second value of struct */
3444 ctx->ac.i32_0, /* primflag */
3445 };
3446 tmp = LLVMBuildGEP(builder, tmp, gep_idx, 3, "");
3447 tmp = LLVMBuildLoad(builder, tmp, "");
3448 prim.isnull = LLVMBuildICmp(builder, LLVMIntEQ, tmp,
3449 LLVMConstInt(ctx->ac.i8, 0, false), "");
3450
3451 for (unsigned i = 0; i < verts_per_prim; ++i) {
3452 prim.index[i] = LLVMBuildSub(builder, vertlive_scan.result_exclusive,
3453 LLVMConstInt(ctx->ac.i32, verts_per_prim - i - 1, false), "");
3454 prim.edgeflag[i] = ctx->ac.i1false;
3455 }
3456
3457 build_export_prim(ctx, &prim);
3458 }
3459 ac_build_endif(&ctx->ac, 5140);
3460
3461 /* Export position and parameter data */
3462 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, vertlive_scan.result_reduce, "");
3463 ac_build_ifcc(&ctx->ac, tmp, 5145);
3464 {
3465 struct radv_vs_output_info *outinfo = &ctx->shader_info->vs.outinfo;
3466 bool export_view_index = ctx->options->key.has_multiview_view_index;
3467 struct radv_shader_output_values *outputs;
3468 unsigned noutput = 0;
3469
3470 /* Allocate a temporary array for the output values. */
3471 unsigned num_outputs = util_bitcount64(ctx->output_mask) + export_view_index;
3472 outputs = calloc(num_outputs, sizeof(outputs[0]));
3473
3474 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
3475 sizeof(outinfo->vs_output_param_offset));
3476 outinfo->pos_exports = 0;
3477
3478 tmp = ngg_gs_vertex_ptr(ctx, tid);
3479 LLVMValueRef gep_idx[3] = {
3480 ctx->ac.i32_0, /* implicit C-style array */
3481 ctx->ac.i32_1, /* second value of struct */
3482 ctx->ac.i32_1, /* stream 1: source data index */
3483 };
3484 tmp = LLVMBuildGEP(builder, tmp, gep_idx, 3, "");
3485 tmp = LLVMBuildLoad(builder, tmp, "");
3486 tmp = LLVMBuildZExt(builder, tmp, ctx->ac.i32, "");
3487 const LLVMValueRef vertexptr = ngg_gs_vertex_ptr(ctx, tmp);
3488
3489 unsigned out_idx = 0;
3490 gep_idx[1] = ctx->ac.i32_0;
3491 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3492 if (!(ctx->output_mask & (1ull << i)))
3493 continue;
3494
3495 outputs[noutput].slot_name = i;
3496 outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
3497
3498 outputs[noutput].usage_mask = ctx->shader_info->gs.output_usage_mask[i];
3499 int length = util_last_bit(outputs[noutput].usage_mask);
3500
3501 for (unsigned j = 0; j < length; j++, out_idx++) {
3502 gep_idx[2] = LLVMConstInt(ctx->ac.i32, out_idx, false);
3503 tmp = LLVMBuildGEP(builder, vertexptr, gep_idx, 3, "");
3504 tmp = LLVMBuildLoad(builder, tmp, "");
3505
3506 LLVMTypeRef type = LLVMGetAllocatedType(ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
3507 if (ac_get_type_size(type) == 2) {
3508 tmp = ac_to_integer(&ctx->ac, tmp);
3509 tmp = LLVMBuildTrunc(ctx->ac.builder, tmp, ctx->ac.i16, "");
3510 }
3511
3512 outputs[noutput].values[j] = ac_to_float(&ctx->ac, tmp);
3513 }
3514
3515 for (unsigned j = length; j < 4; j++)
3516 outputs[noutput].values[j] = LLVMGetUndef(ctx->ac.f32);
3517
3518 noutput++;
3519 }
3520
3521 /* Export ViewIndex. */
3522 if (export_view_index) {
3523 outputs[noutput].slot_name = VARYING_SLOT_LAYER;
3524 outputs[noutput].slot_index = 0;
3525 outputs[noutput].usage_mask = 0x1;
3526 outputs[noutput].values[0] = ac_to_float(&ctx->ac, ctx->abi.view_index);
3527 for (unsigned j = 1; j < 4; j++)
3528 outputs[noutput].values[j] = ctx->ac.f32_0;
3529 noutput++;
3530 }
3531
3532 radv_llvm_export_vs(ctx, outputs, noutput, outinfo,
3533 ctx->options->key.vs_common_out.export_clip_dists);
3534 FREE(outputs);
3535 }
3536 ac_build_endif(&ctx->ac, 5145);
3537 }
3538
3539 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context *ctx,
3540 unsigned stream,
3541 LLVMValueRef *addrs)
3542 {
3543 LLVMBuilderRef builder = ctx->ac.builder;
3544 LLVMValueRef tmp;
3545 const LLVMValueRef vertexidx =
3546 LLVMBuildLoad(builder, ctx->gs_next_vertex[stream], "");
3547
3548 /* If this thread has already emitted the declared maximum number of
3549 * vertices, skip the write: excessive vertex emissions are not
3550 * supposed to have any effect.
3551 */
3552 const LLVMValueRef can_emit =
3553 LLVMBuildICmp(builder, LLVMIntULT, vertexidx,
3554 LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false), "");
3555 ac_build_kill_if_false(&ctx->ac, can_emit);
3556
3557 tmp = LLVMBuildAdd(builder, vertexidx, ctx->ac.i32_1, "");
3558 tmp = LLVMBuildSelect(builder, can_emit, tmp, vertexidx, "");
3559 LLVMBuildStore(builder, tmp, ctx->gs_next_vertex[stream]);
3560
3561 const LLVMValueRef vertexptr =
3562 ngg_gs_emit_vertex_ptr(ctx, get_thread_id_in_tg(ctx), vertexidx);
3563 unsigned out_idx = 0;
3564 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3565 unsigned output_usage_mask =
3566 ctx->shader_info->gs.output_usage_mask[i];
3567 uint8_t output_stream =
3568 ctx->shader_info->gs.output_streams[i];
3569 LLVMValueRef *out_ptr = &addrs[i * 4];
3570 int length = util_last_bit(output_usage_mask);
3571
3572 if (!(ctx->output_mask & (1ull << i)) ||
3573 output_stream != stream)
3574 continue;
3575
3576 for (unsigned j = 0; j < length; j++, out_idx++) {
3577 if (!(output_usage_mask & (1 << j)))
3578 continue;
3579
3580 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
3581 out_ptr[j], "");
3582 LLVMValueRef gep_idx[3] = {
3583 ctx->ac.i32_0, /* implied C-style array */
3584 ctx->ac.i32_0, /* first entry of struct */
3585 LLVMConstInt(ctx->ac.i32, out_idx, false),
3586 };
3587 LLVMValueRef ptr = LLVMBuildGEP(builder, vertexptr, gep_idx, 3, "");
3588
3589 out_val = ac_to_integer(&ctx->ac, out_val);
3590 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
3591
3592 LLVMBuildStore(builder, out_val, ptr);
3593 }
3594 }
3595 assert(out_idx * 4 <= ctx->shader_info->gs.gsvs_vertex_size);
3596
3597 /* Determine and store whether this vertex completed a primitive. */
3598 const LLVMValueRef curverts = LLVMBuildLoad(builder, ctx->gs_curprim_verts[stream], "");
3599
3600 tmp = LLVMConstInt(ctx->ac.i32, si_conv_gl_prim_to_vertices(ctx->shader->info.gs.output_primitive) - 1, false);
3601 const LLVMValueRef iscompleteprim =
3602 LLVMBuildICmp(builder, LLVMIntUGE, curverts, tmp, "");
3603
3604 tmp = LLVMBuildAdd(builder, curverts, ctx->ac.i32_1, "");
3605 LLVMBuildStore(builder, tmp, ctx->gs_curprim_verts[stream]);
3606
3607 LLVMValueRef gep_idx[3] = {
3608 ctx->ac.i32_0, /* implied C-style array */
3609 ctx->ac.i32_1, /* second struct entry */
3610 LLVMConstInt(ctx->ac.i32, stream, false),
3611 };
3612 const LLVMValueRef primflagptr =
3613 LLVMBuildGEP(builder, vertexptr, gep_idx, 3, "");
3614
3615 tmp = LLVMBuildZExt(builder, iscompleteprim, ctx->ac.i8, "");
3616 LLVMBuildStore(builder, tmp, primflagptr);
3617
3618 tmp = LLVMBuildLoad(builder, ctx->gs_generated_prims[stream], "");
3619 tmp = LLVMBuildAdd(builder, tmp, LLVMBuildZExt(builder, iscompleteprim, ctx->ac.i32, ""), "");
3620 LLVMBuildStore(builder, tmp, ctx->gs_generated_prims[stream]);
3621 }
3622
3623 static void
3624 write_tess_factors(struct radv_shader_context *ctx)
3625 {
3626 unsigned stride, outer_comps, inner_comps;
3627 LLVMValueRef invocation_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
3628 LLVMValueRef rel_patch_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
3629 unsigned tess_inner_index = 0, tess_outer_index;
3630 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
3631 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
3632 int i;
3633 ac_emit_barrier(&ctx->ac, ctx->stage);
3634
3635 switch (ctx->options->key.tcs.primitive_mode) {
3636 case GL_ISOLINES:
3637 stride = 2;
3638 outer_comps = 2;
3639 inner_comps = 0;
3640 break;
3641 case GL_TRIANGLES:
3642 stride = 4;
3643 outer_comps = 3;
3644 inner_comps = 1;
3645 break;
3646 case GL_QUADS:
3647 stride = 6;
3648 outer_comps = 4;
3649 inner_comps = 2;
3650 break;
3651 default:
3652 return;
3653 }
3654
3655 ac_build_ifcc(&ctx->ac,
3656 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3657 invocation_id, ctx->ac.i32_0, ""), 6503);
3658
3659 lds_base = get_tcs_out_current_patch_data_offset(ctx);
3660
3661 if (inner_comps) {
3662 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
3663 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
3664 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
3665 }
3666
3667 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
3668 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
3669 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
3670
3671 for (i = 0; i < 4; i++) {
3672 inner[i] = LLVMGetUndef(ctx->ac.i32);
3673 outer[i] = LLVMGetUndef(ctx->ac.i32);
3674 }
3675
3676 // LINES reversal
3677 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
3678 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
3679 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
3680 ctx->ac.i32_1, "");
3681 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
3682 } else {
3683 for (i = 0; i < outer_comps; i++) {
3684 outer[i] = out[i] =
3685 ac_lds_load(&ctx->ac, lds_outer);
3686 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
3687 ctx->ac.i32_1, "");
3688 }
3689 for (i = 0; i < inner_comps; i++) {
3690 inner[i] = out[outer_comps+i] =
3691 ac_lds_load(&ctx->ac, lds_inner);
3692 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
3693 ctx->ac.i32_1, "");
3694 }
3695 }
3696
3697 /* Convert the outputs to vectors for stores. */
3698 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
3699 vec1 = NULL;
3700
3701 if (stride > 4)
3702 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
3703
3704
3705 buffer = ctx->hs_ring_tess_factor;
3706 tf_base = ctx->tess_factor_offset;
3707 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
3708 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
3709 unsigned tf_offset = 0;
3710
3711 if (ctx->options->chip_class <= GFX8) {
3712 ac_build_ifcc(&ctx->ac,
3713 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3714 rel_patch_id, ctx->ac.i32_0, ""), 6504);
3715
3716 /* Store the dynamic HS control word. */
3717 ac_build_buffer_store_dword(&ctx->ac, buffer,
3718 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
3719 1, ctx->ac.i32_0, tf_base,
3720 0, ac_glc, false);
3721 tf_offset += 4;
3722
3723 ac_build_endif(&ctx->ac, 6504);
3724 }
3725
3726 /* Store the tessellation factors. */
3727 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
3728 MIN2(stride, 4), byteoffset, tf_base,
3729 tf_offset, ac_glc, false);
3730 if (vec1)
3731 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
3732 stride - 4, byteoffset, tf_base,
3733 16 + tf_offset, ac_glc, false);
3734
3735 //store to offchip for TES to read - only if TES reads them
3736 if (ctx->options->key.tcs.tes_reads_tess_factors) {
3737 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
3738 LLVMValueRef tf_inner_offset;
3739 unsigned param_outer, param_inner;
3740
3741 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
3742 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
3743 LLVMConstInt(ctx->ac.i32, param_outer, 0));
3744
3745 outer_vec = ac_build_gather_values(&ctx->ac, outer,
3746 util_next_power_of_two(outer_comps));
3747
3748 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
3749 outer_comps, tf_outer_offset,
3750 ctx->oc_lds, 0, ac_glc, false);
3751 if (inner_comps) {
3752 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
3753 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
3754 LLVMConstInt(ctx->ac.i32, param_inner, 0));
3755
3756 inner_vec = inner_comps == 1 ? inner[0] :
3757 ac_build_gather_values(&ctx->ac, inner, inner_comps);
3758 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
3759 inner_comps, tf_inner_offset,
3760 ctx->oc_lds, 0, ac_glc, false);
3761 }
3762 }
3763
3764 ac_build_endif(&ctx->ac, 6503);
3765 }
3766
3767 static void
3768 handle_tcs_outputs_post(struct radv_shader_context *ctx)
3769 {
3770 write_tess_factors(ctx);
3771 }
3772
3773 static bool
3774 si_export_mrt_color(struct radv_shader_context *ctx,
3775 LLVMValueRef *color, unsigned index,
3776 struct ac_export_args *args)
3777 {
3778 /* Export */
3779 si_llvm_init_export_args(ctx, color, 0xf,
3780 V_008DFC_SQ_EXP_MRT + index, args);
3781 if (!args->enabled_channels)
3782 return false; /* unnecessary NULL export */
3783
3784 return true;
3785 }
3786
3787 static void
3788 radv_export_mrt_z(struct radv_shader_context *ctx,
3789 LLVMValueRef depth, LLVMValueRef stencil,
3790 LLVMValueRef samplemask)
3791 {
3792 struct ac_export_args args;
3793
3794 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3795
3796 ac_build_export(&ctx->ac, &args);
3797 }
3798
3799 static void
3800 handle_fs_outputs_post(struct radv_shader_context *ctx)
3801 {
3802 unsigned index = 0;
3803 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3804 struct ac_export_args color_args[8];
3805
3806 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3807 LLVMValueRef values[4];
3808
3809 if (!(ctx->output_mask & (1ull << i)))
3810 continue;
3811
3812 if (i < FRAG_RESULT_DATA0)
3813 continue;
3814
3815 for (unsigned j = 0; j < 4; j++)
3816 values[j] = ac_to_float(&ctx->ac,
3817 radv_load_output(ctx, i, j));
3818
3819 bool ret = si_export_mrt_color(ctx, values,
3820 i - FRAG_RESULT_DATA0,
3821 &color_args[index]);
3822 if (ret)
3823 index++;
3824 }
3825
3826 /* Process depth, stencil, samplemask. */
3827 if (ctx->shader_info->ps.writes_z) {
3828 depth = ac_to_float(&ctx->ac,
3829 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
3830 }
3831 if (ctx->shader_info->ps.writes_stencil) {
3832 stencil = ac_to_float(&ctx->ac,
3833 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
3834 }
3835 if (ctx->shader_info->ps.writes_sample_mask) {
3836 samplemask = ac_to_float(&ctx->ac,
3837 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
3838 }
3839
3840 /* Set the DONE bit on last non-null color export only if Z isn't
3841 * exported.
3842 */
3843 if (index > 0 &&
3844 !ctx->shader_info->ps.writes_z &&
3845 !ctx->shader_info->ps.writes_stencil &&
3846 !ctx->shader_info->ps.writes_sample_mask) {
3847 unsigned last = index - 1;
3848
3849 color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */
3850 color_args[last].done = 1; /* DONE bit */
3851 }
3852
3853 /* Export PS outputs. */
3854 for (unsigned i = 0; i < index; i++)
3855 ac_build_export(&ctx->ac, &color_args[i]);
3856
3857 if (depth || stencil || samplemask)
3858 radv_export_mrt_z(ctx, depth, stencil, samplemask);
3859 else if (!index)
3860 ac_build_export_null(&ctx->ac);
3861 }
3862
3863 static void
3864 emit_gs_epilogue(struct radv_shader_context *ctx)
3865 {
3866 if (ctx->options->key.vs_common_out.as_ngg) {
3867 gfx10_ngg_gs_emit_epilogue_1(ctx);
3868 return;
3869 }
3870
3871 if (ctx->ac.chip_class >= GFX10)
3872 LLVMBuildFence(ctx->ac.builder, LLVMAtomicOrderingRelease, false, "");
3873
3874 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
3875 }
3876
3877 static void
3878 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
3879 LLVMValueRef *addrs)
3880 {
3881 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3882
3883 switch (ctx->stage) {
3884 case MESA_SHADER_VERTEX:
3885 if (ctx->options->key.vs_common_out.as_ls)
3886 handle_ls_outputs_post(ctx);
3887 else if (ctx->options->key.vs_common_out.as_es)
3888 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
3889 else if (ctx->options->key.vs_common_out.as_ngg)
3890 break; /* handled outside of the shader body */
3891 else
3892 handle_vs_outputs_post(ctx, ctx->options->key.vs_common_out.export_prim_id,
3893 ctx->options->key.vs_common_out.export_clip_dists,
3894 &ctx->shader_info->vs.outinfo);
3895 break;
3896 case MESA_SHADER_FRAGMENT:
3897 handle_fs_outputs_post(ctx);
3898 break;
3899 case MESA_SHADER_GEOMETRY:
3900 emit_gs_epilogue(ctx);
3901 break;
3902 case MESA_SHADER_TESS_CTRL:
3903 handle_tcs_outputs_post(ctx);
3904 break;
3905 case MESA_SHADER_TESS_EVAL:
3906 if (ctx->options->key.vs_common_out.as_es)
3907 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
3908 else if (ctx->options->key.vs_common_out.as_ngg)
3909 break; /* handled outside of the shader body */
3910 else
3911 handle_vs_outputs_post(ctx, ctx->options->key.vs_common_out.export_prim_id,
3912 ctx->options->key.vs_common_out.export_clip_dists,
3913 &ctx->shader_info->tes.outinfo);
3914 break;
3915 default:
3916 break;
3917 }
3918 }
3919
3920 static void ac_llvm_finalize_module(struct radv_shader_context *ctx,
3921 LLVMPassManagerRef passmgr,
3922 const struct radv_nir_compiler_options *options)
3923 {
3924 LLVMRunPassManager(passmgr, ctx->ac.module);
3925 LLVMDisposeBuilder(ctx->ac.builder);
3926
3927 ac_llvm_context_dispose(&ctx->ac);
3928 }
3929
3930 static void
3931 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
3932 {
3933 struct radv_vs_output_info *outinfo;
3934
3935 switch (ctx->stage) {
3936 case MESA_SHADER_FRAGMENT:
3937 case MESA_SHADER_COMPUTE:
3938 case MESA_SHADER_TESS_CTRL:
3939 case MESA_SHADER_GEOMETRY:
3940 return;
3941 case MESA_SHADER_VERTEX:
3942 if (ctx->options->key.vs_common_out.as_ls ||
3943 ctx->options->key.vs_common_out.as_es)
3944 return;
3945 outinfo = &ctx->shader_info->vs.outinfo;
3946 break;
3947 case MESA_SHADER_TESS_EVAL:
3948 if (ctx->options->key.vs_common_out.as_es)
3949 return;
3950 outinfo = &ctx->shader_info->tes.outinfo;
3951 break;
3952 default:
3953 unreachable("Unhandled shader type");
3954 }
3955
3956 ac_optimize_vs_outputs(&ctx->ac,
3957 ctx->main_function,
3958 outinfo->vs_output_param_offset,
3959 VARYING_SLOT_MAX,
3960 &outinfo->param_exports);
3961 }
3962
3963 static void
3964 ac_setup_rings(struct radv_shader_context *ctx)
3965 {
3966 if (ctx->options->chip_class <= GFX8 &&
3967 (ctx->stage == MESA_SHADER_GEOMETRY ||
3968 ctx->options->key.vs_common_out.as_es || ctx->options->key.vs_common_out.as_es)) {
3969 unsigned ring = ctx->stage == MESA_SHADER_GEOMETRY ? RING_ESGS_GS
3970 : RING_ESGS_VS;
3971 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, ring, false);
3972
3973 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac,
3974 ctx->ring_offsets,
3975 offset);
3976 }
3977
3978 if (ctx->is_gs_copy_shader) {
3979 ctx->gsvs_ring[0] =
3980 ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets,
3981 LLVMConstInt(ctx->ac.i32,
3982 RING_GSVS_VS, false));
3983 }
3984
3985 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3986 /* The conceptual layout of the GSVS ring is
3987 * v0c0 .. vLv0 v0c1 .. vLc1 ..
3988 * but the real memory layout is swizzled across
3989 * threads:
3990 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
3991 * t16v0c0 ..
3992 * Override the buffer descriptor accordingly.
3993 */
3994 LLVMTypeRef v2i64 = LLVMVectorType(ctx->ac.i64, 2);
3995 uint64_t stream_offset = 0;
3996 unsigned num_records = ctx->ac.wave_size;
3997 LLVMValueRef base_ring;
3998
3999 base_ring =
4000 ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets,
4001 LLVMConstInt(ctx->ac.i32,
4002 RING_GSVS_GS, false));
4003
4004 for (unsigned stream = 0; stream < 4; stream++) {
4005 unsigned num_components, stride;
4006 LLVMValueRef ring, tmp;
4007
4008 num_components =
4009 ctx->shader_info->gs.num_stream_output_components[stream];
4010
4011 if (!num_components)
4012 continue;
4013
4014 stride = 4 * num_components * ctx->shader->info.gs.vertices_out;
4015
4016 /* Limit on the stride field for <= GFX7. */
4017 assert(stride < (1 << 14));
4018
4019 ring = LLVMBuildBitCast(ctx->ac.builder,
4020 base_ring, v2i64, "");
4021 tmp = LLVMBuildExtractElement(ctx->ac.builder,
4022 ring, ctx->ac.i32_0, "");
4023 tmp = LLVMBuildAdd(ctx->ac.builder, tmp,
4024 LLVMConstInt(ctx->ac.i64,
4025 stream_offset, 0), "");
4026 ring = LLVMBuildInsertElement(ctx->ac.builder,
4027 ring, tmp, ctx->ac.i32_0, "");
4028
4029 stream_offset += stride * ctx->ac.wave_size;
4030
4031 ring = LLVMBuildBitCast(ctx->ac.builder, ring,
4032 ctx->ac.v4i32, "");
4033
4034 tmp = LLVMBuildExtractElement(ctx->ac.builder, ring,
4035 ctx->ac.i32_1, "");
4036 tmp = LLVMBuildOr(ctx->ac.builder, tmp,
4037 LLVMConstInt(ctx->ac.i32,
4038 S_008F04_STRIDE(stride), false), "");
4039 ring = LLVMBuildInsertElement(ctx->ac.builder, ring, tmp,
4040 ctx->ac.i32_1, "");
4041
4042 ring = LLVMBuildInsertElement(ctx->ac.builder, ring,
4043 LLVMConstInt(ctx->ac.i32,
4044 num_records, false),
4045 LLVMConstInt(ctx->ac.i32, 2, false), "");
4046
4047 ctx->gsvs_ring[stream] = ring;
4048 }
4049 }
4050
4051 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
4052 ctx->stage == MESA_SHADER_TESS_EVAL) {
4053 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
4054 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
4055 }
4056 }
4057
4058 unsigned
4059 radv_nir_get_max_workgroup_size(enum chip_class chip_class,
4060 gl_shader_stage stage,
4061 const struct nir_shader *nir)
4062 {
4063 const unsigned backup_sizes[] = {chip_class >= GFX9 ? 128 : 64, 1, 1};
4064 return radv_get_max_workgroup_size(chip_class, stage, nir ? nir->info.cs.local_size : backup_sizes);
4065 }
4066
4067 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
4068 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
4069 {
4070 LLVMValueRef count = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 8, 8);
4071 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
4072 ctx->ac.i32_0, "");
4073 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
4074 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
4075 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
4076 }
4077
4078 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
4079 {
4080 for(int i = 5; i >= 0; --i) {
4081 ctx->gs_vtx_offset[i] = ac_unpack_param(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
4082 (i & 1) * 16, 16);
4083 }
4084
4085 ctx->gs_wave_id = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 16, 8);
4086 }
4087
4088 /* Ensure that the esgs ring is declared.
4089 *
4090 * We declare it with 64KB alignment as a hint that the
4091 * pointer value will always be 0.
4092 */
4093 static void declare_esgs_ring(struct radv_shader_context *ctx)
4094 {
4095 if (ctx->esgs_ring)
4096 return;
4097
4098 assert(!LLVMGetNamedGlobal(ctx->ac.module, "esgs_ring"));
4099
4100 ctx->esgs_ring = LLVMAddGlobalInAddressSpace(
4101 ctx->ac.module, LLVMArrayType(ctx->ac.i32, 0),
4102 "esgs_ring",
4103 AC_ADDR_SPACE_LDS);
4104 LLVMSetLinkage(ctx->esgs_ring, LLVMExternalLinkage);
4105 LLVMSetAlignment(ctx->esgs_ring, 64 * 1024);
4106 }
4107
4108 static
4109 LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
4110 struct nir_shader *const *shaders,
4111 int shader_count,
4112 struct radv_shader_info *shader_info,
4113 const struct radv_nir_compiler_options *options)
4114 {
4115 struct radv_shader_context ctx = {0};
4116 unsigned i;
4117 ctx.options = options;
4118 ctx.shader_info = shader_info;
4119
4120 enum ac_float_mode float_mode =
4121 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
4122 AC_FLOAT_MODE_DEFAULT;
4123
4124 ac_llvm_context_init(&ctx.ac, ac_llvm, options->chip_class,
4125 options->family, float_mode, options->wave_size, 64);
4126 ctx.context = ctx.ac.context;
4127
4128 radv_nir_shader_info_init(shader_info);
4129
4130 for(int i = 0; i < shader_count; ++i)
4131 radv_nir_shader_info_pass(shaders[i], options, shader_info);
4132
4133 for (i = 0; i < MAX_SETS; i++)
4134 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
4135 for (i = 0; i < AC_UD_MAX_UD; i++)
4136 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
4137
4138 ctx.max_workgroup_size = 0;
4139 for (int i = 0; i < shader_count; ++i) {
4140 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
4141 radv_nir_get_max_workgroup_size(ctx.options->chip_class,
4142 shaders[i]->info.stage,
4143 shaders[i]));
4144 }
4145
4146 if (ctx.ac.chip_class >= GFX10) {
4147 if (is_pre_gs_stage(shaders[0]->info.stage) &&
4148 options->key.vs_common_out.as_ngg) {
4149 ctx.max_workgroup_size = 128;
4150 }
4151 }
4152
4153 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
4154 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
4155
4156 ctx.abi.inputs = &ctx.inputs[0];
4157 ctx.abi.emit_outputs = handle_shader_outputs_post;
4158 ctx.abi.emit_vertex = visit_emit_vertex;
4159 ctx.abi.load_ubo = radv_load_ubo;
4160 ctx.abi.load_ssbo = radv_load_ssbo;
4161 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
4162 ctx.abi.load_resource = radv_load_resource;
4163 ctx.abi.clamp_shadow_reference = false;
4164 ctx.abi.robust_buffer_access = options->robust_buffer_access;
4165
4166 bool is_ngg = is_pre_gs_stage(shaders[0]->info.stage) && ctx.options->key.vs_common_out.as_ngg;
4167 if (shader_count >= 2 || is_ngg)
4168 ac_init_exec_full_mask(&ctx.ac);
4169
4170 if (options->has_ls_vgpr_init_bug &&
4171 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
4172 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
4173
4174 for(int i = 0; i < shader_count; ++i) {
4175 ctx.stage = shaders[i]->info.stage;
4176 ctx.shader = shaders[i];
4177 ctx.output_mask = 0;
4178
4179 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
4180 for (int i = 0; i < 4; i++) {
4181 ctx.gs_next_vertex[i] =
4182 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
4183 }
4184 if (ctx.options->key.vs_common_out.as_ngg) {
4185 for (unsigned i = 0; i < 4; ++i) {
4186 ctx.gs_curprim_verts[i] =
4187 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
4188 ctx.gs_generated_prims[i] =
4189 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
4190 }
4191
4192 /* TODO: streamout */
4193
4194 LLVMTypeRef ai32 = LLVMArrayType(ctx.ac.i32, 8);
4195 ctx.gs_ngg_scratch =
4196 LLVMAddGlobalInAddressSpace(ctx.ac.module,
4197 ai32, "ngg_scratch", AC_ADDR_SPACE_LDS);
4198 LLVMSetInitializer(ctx.gs_ngg_scratch, LLVMGetUndef(ai32));
4199 LLVMSetAlignment(ctx.gs_ngg_scratch, 4);
4200
4201 ctx.gs_ngg_emit = LLVMBuildIntToPtr(ctx.ac.builder, ctx.ac.i32_0,
4202 LLVMPointerType(LLVMArrayType(ctx.ac.i32, 0), AC_ADDR_SPACE_LDS),
4203 "ngg_emit");
4204 }
4205
4206 ctx.abi.load_inputs = load_gs_input;
4207 ctx.abi.emit_primitive = visit_end_primitive;
4208 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
4209 ctx.abi.load_tess_varyings = load_tcs_varyings;
4210 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
4211 ctx.abi.store_tcs_outputs = store_tcs_output;
4212 if (shader_count == 1)
4213 ctx.tcs_num_inputs = ctx.options->key.tcs.num_inputs;
4214 else
4215 ctx.tcs_num_inputs = util_last_bit64(shader_info->vs.ls_outputs_written);
4216 ctx.tcs_num_patches = get_tcs_num_patches(&ctx);
4217 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
4218 ctx.abi.load_tess_varyings = load_tes_input;
4219 ctx.abi.load_tess_coord = load_tess_coord;
4220 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
4221 ctx.tcs_num_patches = ctx.options->key.tes.num_patches;
4222 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
4223 ctx.abi.load_base_vertex = radv_load_base_vertex;
4224 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
4225 ctx.abi.load_sample_position = load_sample_position;
4226 ctx.abi.load_sample_mask_in = load_sample_mask_in;
4227 ctx.abi.emit_kill = radv_emit_kill;
4228 }
4229
4230 if (shaders[i]->info.stage == MESA_SHADER_VERTEX &&
4231 ctx.options->key.vs_common_out.as_ngg &&
4232 ctx.options->key.vs_common_out.export_prim_id) {
4233 declare_esgs_ring(&ctx);
4234 }
4235
4236 bool nested_barrier = false;
4237
4238 if (i) {
4239 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
4240 ctx.options->key.vs_common_out.as_ngg) {
4241 gfx10_ngg_gs_emit_prologue(&ctx);
4242 nested_barrier = false;
4243 } else {
4244 nested_barrier = true;
4245 }
4246 }
4247
4248 if (nested_barrier) {
4249 /* Execute a barrier before the second shader in
4250 * a merged shader.
4251 *
4252 * Execute the barrier inside the conditional block,
4253 * so that empty waves can jump directly to s_endpgm,
4254 * which will also signal the barrier.
4255 *
4256 * This is possible in gfx9, because an empty wave
4257 * for the second shader does not participate in
4258 * the epilogue. With NGG, empty waves may still
4259 * be required to export data (e.g. GS output vertices),
4260 * so we cannot let them exit early.
4261 *
4262 * If the shader is TCS and the TCS epilog is present
4263 * and contains a barrier, it will wait there and then
4264 * reach s_endpgm.
4265 */
4266 ac_emit_barrier(&ctx.ac, ctx.stage);
4267 }
4268
4269 nir_foreach_variable(variable, &shaders[i]->outputs)
4270 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
4271
4272 ac_setup_rings(&ctx);
4273
4274 LLVMBasicBlockRef merge_block;
4275 if (shader_count >= 2 || is_ngg) {
4276 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
4277 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
4278 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
4279
4280 LLVMValueRef count = ac_unpack_param(&ctx.ac, ctx.merged_wave_info, 8 * i, 8);
4281 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
4282 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
4283 thread_id, count, "");
4284 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
4285
4286 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
4287 }
4288
4289 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
4290 prepare_interp_optimize(&ctx, shaders[i]);
4291 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
4292 handle_vs_inputs(&ctx, shaders[i]);
4293 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
4294 prepare_gs_input_vgprs(&ctx);
4295
4296 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
4297
4298 if (shader_count >= 2 || is_ngg) {
4299 LLVMBuildBr(ctx.ac.builder, merge_block);
4300 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
4301 }
4302
4303 /* This needs to be outside the if wrapping the shader body, as sometimes
4304 * the HW generates waves with 0 es/vs threads. */
4305 if (is_pre_gs_stage(shaders[i]->info.stage) &&
4306 ctx.options->key.vs_common_out.as_ngg &&
4307 i == shader_count - 1) {
4308 handle_ngg_outputs_post(&ctx);
4309 } else if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
4310 ctx.options->key.vs_common_out.as_ngg) {
4311 gfx10_ngg_gs_emit_epilogue_2(&ctx);
4312 }
4313
4314 if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
4315 shader_info->tcs.num_patches = ctx.tcs_num_patches;
4316 shader_info->tcs.lds_size = calculate_tess_lds_size(&ctx);
4317 }
4318 }
4319
4320 LLVMBuildRetVoid(ctx.ac.builder);
4321
4322 if (options->dump_preoptir) {
4323 fprintf(stderr, "%s LLVM IR:\n\n",
4324 radv_get_shader_name(shader_info,
4325 shaders[shader_count - 1]->info.stage));
4326 ac_dump_module(ctx.ac.module);
4327 fprintf(stderr, "\n");
4328 }
4329
4330 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, options);
4331
4332 if (shader_count == 1)
4333 ac_nir_eliminate_const_vs_outputs(&ctx);
4334
4335 if (options->dump_shader) {
4336 ctx.shader_info->private_mem_vgprs =
4337 ac_count_scratch_private_memory(ctx.main_function);
4338 }
4339
4340 return ctx.ac.module;
4341 }
4342
4343 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
4344 {
4345 unsigned *retval = (unsigned *)context;
4346 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
4347 char *description = LLVMGetDiagInfoDescription(di);
4348
4349 if (severity == LLVMDSError) {
4350 *retval = 1;
4351 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
4352 description);
4353 }
4354
4355 LLVMDisposeMessage(description);
4356 }
4357
4358 static unsigned radv_llvm_compile(LLVMModuleRef M,
4359 char **pelf_buffer, size_t *pelf_size,
4360 struct ac_llvm_compiler *ac_llvm)
4361 {
4362 unsigned retval = 0;
4363 LLVMContextRef llvm_ctx;
4364
4365 /* Setup Diagnostic Handler*/
4366 llvm_ctx = LLVMGetModuleContext(M);
4367
4368 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
4369 &retval);
4370
4371 /* Compile IR*/
4372 if (!radv_compile_to_elf(ac_llvm, M, pelf_buffer, pelf_size))
4373 retval = 1;
4374 return retval;
4375 }
4376
4377 static void ac_compile_llvm_module(struct ac_llvm_compiler *ac_llvm,
4378 LLVMModuleRef llvm_module,
4379 struct radv_shader_binary **rbinary,
4380 gl_shader_stage stage,
4381 const char *name,
4382 const struct radv_nir_compiler_options *options)
4383 {
4384 char *elf_buffer = NULL;
4385 size_t elf_size = 0;
4386 char *llvm_ir_string = NULL;
4387
4388 if (options->dump_shader) {
4389 fprintf(stderr, "%s LLVM IR:\n\n", name);
4390 ac_dump_module(llvm_module);
4391 fprintf(stderr, "\n");
4392 }
4393
4394 if (options->record_llvm_ir) {
4395 char *llvm_ir = LLVMPrintModuleToString(llvm_module);
4396 llvm_ir_string = strdup(llvm_ir);
4397 LLVMDisposeMessage(llvm_ir);
4398 }
4399
4400 int v = radv_llvm_compile(llvm_module, &elf_buffer, &elf_size, ac_llvm);
4401 if (v) {
4402 fprintf(stderr, "compile failed\n");
4403 }
4404
4405 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
4406 LLVMDisposeModule(llvm_module);
4407 LLVMContextDispose(ctx);
4408
4409 size_t llvm_ir_size = llvm_ir_string ? strlen(llvm_ir_string) : 0;
4410 size_t alloc_size = sizeof(struct radv_shader_binary_rtld) + elf_size + llvm_ir_size + 1;
4411 struct radv_shader_binary_rtld *rbin = calloc(1, alloc_size);
4412 memcpy(rbin->data, elf_buffer, elf_size);
4413 if (llvm_ir_string)
4414 memcpy(rbin->data + elf_size, llvm_ir_string, llvm_ir_size + 1);
4415
4416 rbin->base.type = RADV_BINARY_TYPE_RTLD;
4417 rbin->base.stage = stage;
4418 rbin->base.total_size = alloc_size;
4419 rbin->elf_size = elf_size;
4420 rbin->llvm_ir_size = llvm_ir_size;
4421 *rbinary = &rbin->base;
4422
4423 free(llvm_ir_string);
4424 free(elf_buffer);
4425 }
4426
4427 void
4428 radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
4429 struct radv_shader_binary **rbinary,
4430 struct radv_shader_info *shader_info,
4431 struct nir_shader *const *nir,
4432 int nir_count,
4433 const struct radv_nir_compiler_options *options)
4434 {
4435
4436 LLVMModuleRef llvm_module;
4437
4438 llvm_module = ac_translate_nir_to_llvm(ac_llvm, nir, nir_count, shader_info,
4439 options);
4440
4441 ac_compile_llvm_module(ac_llvm, llvm_module, rbinary,
4442 nir[nir_count - 1]->info.stage,
4443 radv_get_shader_name(shader_info,
4444 nir[nir_count - 1]->info.stage),
4445 options);
4446
4447 /* Determine the ES type (VS or TES) for the GS on GFX9. */
4448 if (options->chip_class >= GFX9) {
4449 if (nir_count == 2 &&
4450 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
4451 shader_info->gs.es_type = nir[0]->info.stage;
4452 }
4453 }
4454 shader_info->wave_size = options->wave_size;
4455 }
4456
4457 static void
4458 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
4459 {
4460 LLVMValueRef vtx_offset =
4461 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
4462 LLVMConstInt(ctx->ac.i32, 4, false), "");
4463 LLVMValueRef stream_id;
4464
4465 /* Fetch the vertex stream ID. */
4466 if (ctx->shader_info->so.num_outputs) {
4467 stream_id =
4468 ac_unpack_param(&ctx->ac, ctx->streamout_config, 24, 2);
4469 } else {
4470 stream_id = ctx->ac.i32_0;
4471 }
4472
4473 LLVMBasicBlockRef end_bb;
4474 LLVMValueRef switch_inst;
4475
4476 end_bb = LLVMAppendBasicBlockInContext(ctx->ac.context,
4477 ctx->main_function, "end");
4478 switch_inst = LLVMBuildSwitch(ctx->ac.builder, stream_id, end_bb, 4);
4479
4480 for (unsigned stream = 0; stream < 4; stream++) {
4481 unsigned num_components =
4482 ctx->shader_info->gs.num_stream_output_components[stream];
4483 LLVMBasicBlockRef bb;
4484 unsigned offset;
4485
4486 if (!num_components)
4487 continue;
4488
4489 if (stream > 0 && !ctx->shader_info->so.num_outputs)
4490 continue;
4491
4492 bb = LLVMInsertBasicBlockInContext(ctx->ac.context, end_bb, "out");
4493 LLVMAddCase(switch_inst, LLVMConstInt(ctx->ac.i32, stream, 0), bb);
4494 LLVMPositionBuilderAtEnd(ctx->ac.builder, bb);
4495
4496 offset = 0;
4497 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
4498 unsigned output_usage_mask =
4499 ctx->shader_info->gs.output_usage_mask[i];
4500 unsigned output_stream =
4501 ctx->shader_info->gs.output_streams[i];
4502 int length = util_last_bit(output_usage_mask);
4503
4504 if (!(ctx->output_mask & (1ull << i)) ||
4505 output_stream != stream)
4506 continue;
4507
4508 for (unsigned j = 0; j < length; j++) {
4509 LLVMValueRef value, soffset;
4510
4511 if (!(output_usage_mask & (1 << j)))
4512 continue;
4513
4514 soffset = LLVMConstInt(ctx->ac.i32,
4515 offset *
4516 ctx->shader->info.gs.vertices_out * 16 * 4, false);
4517
4518 offset++;
4519
4520 value = ac_build_buffer_load(&ctx->ac,
4521 ctx->gsvs_ring[0],
4522 1, ctx->ac.i32_0,
4523 vtx_offset, soffset,
4524 0, ac_glc | ac_slc, true, false);
4525
4526 LLVMTypeRef type = LLVMGetAllocatedType(ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
4527 if (ac_get_type_size(type) == 2) {
4528 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
4529 value = LLVMBuildTrunc(ctx->ac.builder, value, ctx->ac.i16, "");
4530 }
4531
4532 LLVMBuildStore(ctx->ac.builder,
4533 ac_to_float(&ctx->ac, value), ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
4534 }
4535 }
4536
4537 if (ctx->shader_info->so.num_outputs)
4538 radv_emit_streamout(ctx, stream);
4539
4540 if (stream == 0) {
4541 handle_vs_outputs_post(ctx, false, true,
4542 &ctx->shader_info->vs.outinfo);
4543 }
4544
4545 LLVMBuildBr(ctx->ac.builder, end_bb);
4546 }
4547
4548 LLVMPositionBuilderAtEnd(ctx->ac.builder, end_bb);
4549 }
4550
4551 void
4552 radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
4553 struct nir_shader *geom_shader,
4554 struct radv_shader_binary **rbinary,
4555 struct radv_shader_info *shader_info,
4556 const struct radv_nir_compiler_options *options)
4557 {
4558 struct radv_shader_context ctx = {0};
4559 ctx.options = options;
4560 ctx.shader_info = shader_info;
4561
4562 enum ac_float_mode float_mode =
4563 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
4564 AC_FLOAT_MODE_DEFAULT;
4565
4566 ac_llvm_context_init(&ctx.ac, ac_llvm, options->chip_class,
4567 options->family, float_mode, 64, 64);
4568 ctx.context = ctx.ac.context;
4569
4570 ctx.is_gs_copy_shader = true;
4571 ctx.stage = MESA_SHADER_VERTEX;
4572 ctx.shader = geom_shader;
4573
4574 radv_nir_shader_info_pass(geom_shader, options, shader_info);
4575
4576 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
4577
4578 ac_setup_rings(&ctx);
4579
4580 nir_foreach_variable(variable, &geom_shader->outputs) {
4581 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
4582 ac_handle_shader_output_decl(&ctx.ac, &ctx.abi, geom_shader,
4583 variable, MESA_SHADER_VERTEX);
4584 }
4585
4586 ac_gs_copy_shader_emit(&ctx);
4587
4588 LLVMBuildRetVoid(ctx.ac.builder);
4589
4590 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, options);
4591
4592 ac_compile_llvm_module(ac_llvm, ctx.ac.module, rbinary,
4593 MESA_SHADER_VERTEX, "GS Copy Shader", options);
4594 (*rbinary)->is_gs_copy_shader = true;
4595
4596 }