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radv: align the LDS size in calculate_tess_lds_size()
[mesa.git] / src / amd / vulkan / radv_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "radv_shader_helper.h"
31 #include "radv_shader_args.h"
32 #include "radv_debug.h"
33 #include "nir/nir.h"
34
35 #include "sid.h"
36 #include "ac_binary.h"
37 #include "ac_llvm_util.h"
38 #include "ac_llvm_build.h"
39 #include "ac_shader_abi.h"
40 #include "ac_shader_util.h"
41 #include "ac_exp_param.h"
42
43 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
44
45 struct radv_shader_context {
46 struct ac_llvm_context ac;
47 const struct nir_shader *shader;
48 struct ac_shader_abi abi;
49 const struct radv_shader_args *args;
50
51 gl_shader_stage stage;
52
53 unsigned max_workgroup_size;
54 LLVMContextRef context;
55 LLVMValueRef main_function;
56
57 LLVMValueRef descriptor_sets[MAX_SETS];
58
59 LLVMValueRef ring_offsets;
60
61 LLVMValueRef rel_auto_id;
62
63 LLVMValueRef gs_wave_id;
64 LLVMValueRef gs_vtx_offset[6];
65
66 LLVMValueRef esgs_ring;
67 LLVMValueRef gsvs_ring[4];
68 LLVMValueRef hs_ring_tess_offchip;
69 LLVMValueRef hs_ring_tess_factor;
70
71 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
72
73 uint64_t output_mask;
74
75 LLVMValueRef gs_next_vertex[4];
76 LLVMValueRef gs_curprim_verts[4];
77 LLVMValueRef gs_generated_prims[4];
78 LLVMValueRef gs_ngg_emit;
79 LLVMValueRef gs_ngg_scratch;
80
81 uint32_t tcs_num_inputs;
82 uint32_t tcs_num_patches;
83
84 LLVMValueRef vertexptr; /* GFX10 only */
85 };
86
87 struct radv_shader_output_values {
88 LLVMValueRef values[4];
89 unsigned slot_name;
90 unsigned slot_index;
91 unsigned usage_mask;
92 };
93
94 static inline struct radv_shader_context *
95 radv_shader_context_from_abi(struct ac_shader_abi *abi)
96 {
97 struct radv_shader_context *ctx = NULL;
98 return container_of(abi, ctx, abi);
99 }
100
101 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
102 {
103 switch (ctx->stage) {
104 case MESA_SHADER_TESS_CTRL:
105 return ac_unpack_param(&ctx->ac,
106 ac_get_arg(&ctx->ac, ctx->args->ac.tcs_rel_ids),
107 0, 8);
108 case MESA_SHADER_TESS_EVAL:
109 return ac_get_arg(&ctx->ac, ctx->args->tes_rel_patch_id);
110 break;
111 default:
112 unreachable("Illegal stage");
113 }
114 }
115
116 /* Tessellation shaders pass outputs to the next shader using LDS.
117 *
118 * LS outputs = TCS inputs
119 * TCS outputs = TES inputs
120 *
121 * The LDS layout is:
122 * - TCS inputs for patch 0
123 * - TCS inputs for patch 1
124 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
125 * - ...
126 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
127 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
128 * - TCS outputs for patch 1
129 * - Per-patch TCS outputs for patch 1
130 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
131 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
132 * - ...
133 *
134 * All three shaders VS(LS), TCS, TES share the same LDS space.
135 */
136 static LLVMValueRef
137 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
138 {
139 assert(ctx->stage == MESA_SHADER_TESS_CTRL);
140 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
141 uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * input_vertex_size;
142
143 input_patch_size /= 4;
144 return LLVMConstInt(ctx->ac.i32, input_patch_size, false);
145 }
146
147 static LLVMValueRef
148 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
149 {
150 uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
151 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->args->shader_info->tcs.patch_outputs_written);
152 uint32_t output_vertex_size = num_tcs_outputs * 16;
153 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
154 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
155 output_patch_size /= 4;
156 return LLVMConstInt(ctx->ac.i32, output_patch_size, false);
157 }
158
159 static LLVMValueRef
160 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
161 {
162 uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
163 uint32_t output_vertex_size = num_tcs_outputs * 16;
164 output_vertex_size /= 4;
165 return LLVMConstInt(ctx->ac.i32, output_vertex_size, false);
166 }
167
168 static LLVMValueRef
169 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
170 {
171 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
172 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
173 uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * input_vertex_size;
174 uint32_t output_patch0_offset = input_patch_size;
175 unsigned num_patches = ctx->tcs_num_patches;
176
177 output_patch0_offset *= num_patches;
178 output_patch0_offset /= 4;
179 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
180 }
181
182 static LLVMValueRef
183 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
184 {
185 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
186 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
187 uint32_t input_patch_size = ctx->args->options->key.tcs.input_vertices * input_vertex_size;
188 uint32_t output_patch0_offset = input_patch_size;
189
190 uint32_t num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
191 uint32_t output_vertex_size = num_tcs_outputs * 16;
192 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
193 unsigned num_patches = ctx->tcs_num_patches;
194
195 output_patch0_offset *= num_patches;
196 output_patch0_offset += pervertex_output_patch_size;
197 output_patch0_offset /= 4;
198 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
199 }
200
201 static LLVMValueRef
202 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
203 {
204 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
205 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
206
207 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
208 }
209
210 static LLVMValueRef
211 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
212 {
213 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
214 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
215 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
216
217 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
218 patch0_offset);
219 }
220
221 static LLVMValueRef
222 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
223 {
224 LLVMValueRef patch0_patch_data_offset =
225 get_tcs_out_patch0_patch_data_offset(ctx);
226 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
227 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
228
229 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
230 patch0_patch_data_offset);
231 }
232
233 static LLVMValueRef
234 create_llvm_function(struct ac_llvm_context *ctx, LLVMModuleRef module,
235 LLVMBuilderRef builder,
236 const struct ac_shader_args *args,
237 enum ac_llvm_calling_convention convention,
238 unsigned max_workgroup_size,
239 const struct radv_nir_compiler_options *options)
240 {
241 LLVMValueRef main_function =
242 ac_build_main(args, ctx, convention, "main", ctx->voidt, module);
243
244 if (options->address32_hi) {
245 ac_llvm_add_target_dep_function_attr(main_function,
246 "amdgpu-32bit-address-high-bits",
247 options->address32_hi);
248 }
249
250 ac_llvm_set_workgroup_size(main_function, max_workgroup_size);
251
252 return main_function;
253 }
254
255 static void
256 load_descriptor_sets(struct radv_shader_context *ctx)
257 {
258 uint32_t mask = ctx->args->shader_info->desc_set_used_mask;
259 if (ctx->args->shader_info->need_indirect_descriptor_sets) {
260 LLVMValueRef desc_sets =
261 ac_get_arg(&ctx->ac, ctx->args->descriptor_sets[0]);
262 while (mask) {
263 int i = u_bit_scan(&mask);
264
265 ctx->descriptor_sets[i] =
266 ac_build_load_to_sgpr(&ctx->ac, desc_sets,
267 LLVMConstInt(ctx->ac.i32, i, false));
268
269 }
270 } else {
271 while (mask) {
272 int i = u_bit_scan(&mask);
273
274 ctx->descriptor_sets[i] =
275 ac_get_arg(&ctx->ac, ctx->args->descriptor_sets[i]);
276 }
277 }
278 }
279
280 static enum ac_llvm_calling_convention
281 get_llvm_calling_convention(LLVMValueRef func, gl_shader_stage stage)
282 {
283 switch (stage) {
284 case MESA_SHADER_VERTEX:
285 case MESA_SHADER_TESS_EVAL:
286 return AC_LLVM_AMDGPU_VS;
287 break;
288 case MESA_SHADER_GEOMETRY:
289 return AC_LLVM_AMDGPU_GS;
290 break;
291 case MESA_SHADER_TESS_CTRL:
292 return AC_LLVM_AMDGPU_HS;
293 break;
294 case MESA_SHADER_FRAGMENT:
295 return AC_LLVM_AMDGPU_PS;
296 break;
297 case MESA_SHADER_COMPUTE:
298 return AC_LLVM_AMDGPU_CS;
299 break;
300 default:
301 unreachable("Unhandle shader type");
302 }
303 }
304
305 /* Returns whether the stage is a stage that can be directly before the GS */
306 static bool is_pre_gs_stage(gl_shader_stage stage)
307 {
308 return stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL;
309 }
310
311 static void create_function(struct radv_shader_context *ctx,
312 gl_shader_stage stage,
313 bool has_previous_stage)
314 {
315 if (ctx->ac.chip_class >= GFX10) {
316 if (is_pre_gs_stage(stage) && ctx->args->options->key.vs_common_out.as_ngg) {
317 /* On GFX10, VS is merged into GS for NGG. */
318 stage = MESA_SHADER_GEOMETRY;
319 has_previous_stage = true;
320 }
321 }
322
323 ctx->main_function = create_llvm_function(
324 &ctx->ac, ctx->ac.module, ctx->ac.builder, &ctx->args->ac,
325 get_llvm_calling_convention(ctx->main_function, stage),
326 ctx->max_workgroup_size,
327 ctx->args->options);
328
329 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
330 LLVMPointerType(ctx->ac.i8, AC_ADDR_SPACE_CONST),
331 NULL, 0, AC_FUNC_ATTR_READNONE);
332 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
333 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
334
335 load_descriptor_sets(ctx);
336
337 if (stage == MESA_SHADER_TESS_CTRL ||
338 (stage == MESA_SHADER_VERTEX && ctx->args->options->key.vs_common_out.as_ls) ||
339 /* GFX9 has the ESGS ring buffer in LDS. */
340 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
341 ac_declare_lds_as_pointer(&ctx->ac);
342 }
343
344 }
345
346
347 static LLVMValueRef
348 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
349 unsigned desc_set, unsigned binding)
350 {
351 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
352 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
353 struct radv_pipeline_layout *pipeline_layout = ctx->args->options->layout;
354 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
355 unsigned base_offset = layout->binding[binding].offset;
356 LLVMValueRef offset, stride;
357
358 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
359 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
360 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
361 layout->binding[binding].dynamic_offset_offset;
362 desc_ptr = ac_get_arg(&ctx->ac, ctx->args->ac.push_constants);
363 base_offset = pipeline_layout->push_constant_size + 16 * idx;
364 stride = LLVMConstInt(ctx->ac.i32, 16, false);
365 } else
366 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
367
368 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
369
370 if (layout->binding[binding].type != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
371 offset = ac_build_imad(&ctx->ac, index, stride, offset);
372 }
373
374 desc_ptr = LLVMBuildGEP(ctx->ac.builder, desc_ptr, &offset, 1, "");
375 desc_ptr = ac_cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
376 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
377
378 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
379 uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
380 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
381 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
382 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
383
384 if (ctx->ac.chip_class >= GFX10) {
385 desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
386 S_008F0C_OOB_SELECT(V_008F0C_OOB_SELECT_RAW) |
387 S_008F0C_RESOURCE_LEVEL(1);
388 } else {
389 desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
390 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
391 }
392
393 LLVMValueRef desc_components[4] = {
394 LLVMBuildPtrToInt(ctx->ac.builder, desc_ptr, ctx->ac.intptr, ""),
395 LLVMConstInt(ctx->ac.i32, S_008F04_BASE_ADDRESS_HI(ctx->args->options->address32_hi), false),
396 /* High limit to support variable sizes. */
397 LLVMConstInt(ctx->ac.i32, 0xffffffff, false),
398 LLVMConstInt(ctx->ac.i32, desc_type, false),
399 };
400
401 return ac_build_gather_values(&ctx->ac, desc_components, 4);
402 }
403
404 return desc_ptr;
405 }
406
407
408 /* The offchip buffer layout for TCS->TES is
409 *
410 * - attribute 0 of patch 0 vertex 0
411 * - attribute 0 of patch 0 vertex 1
412 * - attribute 0 of patch 0 vertex 2
413 * ...
414 * - attribute 0 of patch 1 vertex 0
415 * - attribute 0 of patch 1 vertex 1
416 * ...
417 * - attribute 1 of patch 0 vertex 0
418 * - attribute 1 of patch 0 vertex 1
419 * ...
420 * - per patch attribute 0 of patch 0
421 * - per patch attribute 0 of patch 1
422 * ...
423 *
424 * Note that every attribute has 4 components.
425 */
426 static LLVMValueRef get_non_vertex_index_offset(struct radv_shader_context *ctx)
427 {
428 uint32_t num_patches = ctx->tcs_num_patches;
429 uint32_t num_tcs_outputs;
430 if (ctx->stage == MESA_SHADER_TESS_CTRL)
431 num_tcs_outputs = util_last_bit64(ctx->args->shader_info->tcs.outputs_written);
432 else
433 num_tcs_outputs = ctx->args->options->key.tes.tcs_num_outputs;
434
435 uint32_t output_vertex_size = num_tcs_outputs * 16;
436 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
437
438 return LLVMConstInt(ctx->ac.i32, pervertex_output_patch_size * num_patches, false);
439 }
440
441 static LLVMValueRef calc_param_stride(struct radv_shader_context *ctx,
442 LLVMValueRef vertex_index)
443 {
444 LLVMValueRef param_stride;
445 if (vertex_index)
446 param_stride = LLVMConstInt(ctx->ac.i32, ctx->shader->info.tess.tcs_vertices_out * ctx->tcs_num_patches, false);
447 else
448 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_num_patches, false);
449 return param_stride;
450 }
451
452 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
453 LLVMValueRef vertex_index,
454 LLVMValueRef param_index)
455 {
456 LLVMValueRef base_addr;
457 LLVMValueRef param_stride, constant16;
458 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
459 LLVMValueRef vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->shader->info.tess.tcs_vertices_out, false);
460 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
461 param_stride = calc_param_stride(ctx, vertex_index);
462 if (vertex_index) {
463 base_addr = ac_build_imad(&ctx->ac, rel_patch_id,
464 vertices_per_patch, vertex_index);
465 } else {
466 base_addr = rel_patch_id;
467 }
468
469 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
470 LLVMBuildMul(ctx->ac.builder, param_index,
471 param_stride, ""), "");
472
473 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
474
475 if (!vertex_index) {
476 LLVMValueRef patch_data_offset = get_non_vertex_index_offset(ctx);
477
478 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
479 patch_data_offset, "");
480 }
481 return base_addr;
482 }
483
484 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
485 unsigned param,
486 unsigned const_index,
487 bool is_compact,
488 LLVMValueRef vertex_index,
489 LLVMValueRef indir_index)
490 {
491 LLVMValueRef param_index;
492
493 if (indir_index)
494 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
495 indir_index, "");
496 else {
497 if (const_index && !is_compact)
498 param += const_index;
499 param_index = LLVMConstInt(ctx->ac.i32, param, false);
500 }
501 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
502 }
503
504 static LLVMValueRef
505 get_dw_address(struct radv_shader_context *ctx,
506 LLVMValueRef dw_addr,
507 unsigned param,
508 unsigned const_index,
509 bool compact_const_index,
510 LLVMValueRef vertex_index,
511 LLVMValueRef stride,
512 LLVMValueRef indir_index)
513
514 {
515
516 if (vertex_index) {
517 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
518 LLVMBuildMul(ctx->ac.builder,
519 vertex_index,
520 stride, ""), "");
521 }
522
523 if (indir_index)
524 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
525 LLVMBuildMul(ctx->ac.builder, indir_index,
526 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
527 else if (const_index && !compact_const_index)
528 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
529 LLVMConstInt(ctx->ac.i32, const_index * 4, false), "");
530
531 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
532 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
533
534 if (const_index && compact_const_index)
535 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
536 LLVMConstInt(ctx->ac.i32, const_index, false), "");
537 return dw_addr;
538 }
539
540 static LLVMValueRef
541 load_tcs_varyings(struct ac_shader_abi *abi,
542 LLVMTypeRef type,
543 LLVMValueRef vertex_index,
544 LLVMValueRef indir_index,
545 unsigned const_index,
546 unsigned location,
547 unsigned driver_location,
548 unsigned component,
549 unsigned num_components,
550 bool is_patch,
551 bool is_compact,
552 bool load_input)
553 {
554 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
555 LLVMValueRef dw_addr, stride;
556 LLVMValueRef value[4], result;
557 unsigned param = shader_io_get_unique_index(location);
558
559 if (load_input) {
560 uint32_t input_vertex_size = (ctx->tcs_num_inputs * 16) / 4;
561 stride = LLVMConstInt(ctx->ac.i32, input_vertex_size, false);
562 dw_addr = get_tcs_in_current_patch_offset(ctx);
563 } else {
564 if (!is_patch) {
565 stride = get_tcs_out_vertex_stride(ctx);
566 dw_addr = get_tcs_out_current_patch_offset(ctx);
567 } else {
568 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
569 stride = NULL;
570 }
571 }
572
573 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
574 indir_index);
575
576 for (unsigned i = 0; i < num_components + component; i++) {
577 value[i] = ac_lds_load(&ctx->ac, dw_addr);
578 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
579 ctx->ac.i32_1, "");
580 }
581 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
582 return result;
583 }
584
585 static void
586 store_tcs_output(struct ac_shader_abi *abi,
587 const nir_variable *var,
588 LLVMValueRef vertex_index,
589 LLVMValueRef param_index,
590 unsigned const_index,
591 LLVMValueRef src,
592 unsigned writemask)
593 {
594 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
595 const unsigned location = var->data.location;
596 unsigned component = var->data.location_frac;
597 const bool is_patch = var->data.patch;
598 const bool is_compact = var->data.compact;
599 LLVMValueRef dw_addr;
600 LLVMValueRef stride = NULL;
601 LLVMValueRef buf_addr = NULL;
602 LLVMValueRef oc_lds = ac_get_arg(&ctx->ac, ctx->args->oc_lds);
603 unsigned param;
604 bool store_lds = true;
605
606 if (is_patch) {
607 if (!(ctx->shader->info.patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
608 store_lds = false;
609 } else {
610 if (!(ctx->shader->info.outputs_read & (1ULL << location)))
611 store_lds = false;
612 }
613
614 param = shader_io_get_unique_index(location);
615 if ((location == VARYING_SLOT_CLIP_DIST0 || location == VARYING_SLOT_CLIP_DIST1) && is_compact) {
616 const_index += component;
617 component = 0;
618
619 if (const_index >= 4) {
620 const_index -= 4;
621 param++;
622 }
623 }
624
625 if (!is_patch) {
626 stride = get_tcs_out_vertex_stride(ctx);
627 dw_addr = get_tcs_out_current_patch_offset(ctx);
628 } else {
629 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
630 }
631
632 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
633 param_index);
634 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
635 vertex_index, param_index);
636
637 bool is_tess_factor = false;
638 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
639 location == VARYING_SLOT_TESS_LEVEL_OUTER)
640 is_tess_factor = true;
641
642 unsigned base = is_compact ? const_index : 0;
643 for (unsigned chan = 0; chan < 8; chan++) {
644 if (!(writemask & (1 << chan)))
645 continue;
646 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
647 value = ac_to_integer(&ctx->ac, value);
648 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
649
650 if (store_lds || is_tess_factor) {
651 LLVMValueRef dw_addr_chan =
652 LLVMBuildAdd(ctx->ac.builder, dw_addr,
653 LLVMConstInt(ctx->ac.i32, chan, false), "");
654 ac_lds_store(&ctx->ac, dw_addr_chan, value);
655 }
656
657 if (!is_tess_factor && writemask != 0xF)
658 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
659 buf_addr, oc_lds,
660 4 * (base + chan), ac_glc);
661 }
662
663 if (writemask == 0xF) {
664 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
665 buf_addr, oc_lds,
666 (base * 4), ac_glc);
667 }
668 }
669
670 static LLVMValueRef
671 load_tes_input(struct ac_shader_abi *abi,
672 LLVMTypeRef type,
673 LLVMValueRef vertex_index,
674 LLVMValueRef param_index,
675 unsigned const_index,
676 unsigned location,
677 unsigned driver_location,
678 unsigned component,
679 unsigned num_components,
680 bool is_patch,
681 bool is_compact,
682 bool load_input)
683 {
684 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
685 LLVMValueRef buf_addr;
686 LLVMValueRef result;
687 LLVMValueRef oc_lds = ac_get_arg(&ctx->ac, ctx->args->oc_lds);
688 unsigned param = shader_io_get_unique_index(location);
689
690 if ((location == VARYING_SLOT_CLIP_DIST0 || location == VARYING_SLOT_CLIP_DIST1) && is_compact) {
691 const_index += component;
692 component = 0;
693 if (const_index >= 4) {
694 const_index -= 4;
695 param++;
696 }
697 }
698
699 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
700 is_compact, vertex_index, param_index);
701
702 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
703 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
704
705 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
706 buf_addr, oc_lds, is_compact ? (4 * const_index) : 0, ac_glc, true, false);
707 result = ac_trim_vector(&ctx->ac, result, num_components);
708 return result;
709 }
710
711 static LLVMValueRef
712 radv_emit_fetch_64bit(struct radv_shader_context *ctx,
713 LLVMTypeRef type, LLVMValueRef a, LLVMValueRef b)
714 {
715 LLVMValueRef values[2] = {
716 ac_to_integer(&ctx->ac, a),
717 ac_to_integer(&ctx->ac, b),
718 };
719 LLVMValueRef result = ac_build_gather_values(&ctx->ac, values, 2);
720 return LLVMBuildBitCast(ctx->ac.builder, result, type, "");
721 }
722
723 static LLVMValueRef
724 load_gs_input(struct ac_shader_abi *abi,
725 unsigned location,
726 unsigned driver_location,
727 unsigned component,
728 unsigned num_components,
729 unsigned vertex_index,
730 unsigned const_index,
731 LLVMTypeRef type)
732 {
733 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
734 LLVMValueRef vtx_offset;
735 unsigned param, vtx_offset_param;
736 LLVMValueRef value[4], result;
737
738 vtx_offset_param = vertex_index;
739 assert(vtx_offset_param < 6);
740 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
741 LLVMConstInt(ctx->ac.i32, 4, false), "");
742
743 param = shader_io_get_unique_index(location);
744
745 for (unsigned i = component; i < num_components + component; i++) {
746 if (ctx->ac.chip_class >= GFX9) {
747 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
748 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
749 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
750 value[i] = ac_lds_load(&ctx->ac, dw_addr);
751
752 if (ac_get_type_size(type) == 8) {
753 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
754 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index + 1, 0), "");
755 LLVMValueRef tmp = ac_lds_load(&ctx->ac, dw_addr);
756
757 value[i] = radv_emit_fetch_64bit(ctx, type, value[i], tmp);
758 }
759 } else {
760 LLVMValueRef soffset =
761 LLVMConstInt(ctx->ac.i32,
762 (param * 4 + i + const_index) * 256,
763 false);
764
765 value[i] = ac_build_buffer_load(&ctx->ac,
766 ctx->esgs_ring, 1,
767 ctx->ac.i32_0,
768 vtx_offset, soffset,
769 0, ac_glc, true, false);
770
771 if (ac_get_type_size(type) == 8) {
772 soffset = LLVMConstInt(ctx->ac.i32,
773 (param * 4 + i + const_index + 1) * 256,
774 false);
775
776 LLVMValueRef tmp =
777 ac_build_buffer_load(&ctx->ac,
778 ctx->esgs_ring, 1,
779 ctx->ac.i32_0,
780 vtx_offset, soffset,
781 0, ac_glc, true, false);
782
783 value[i] = radv_emit_fetch_64bit(ctx, type, value[i], tmp);
784 }
785 }
786
787 if (ac_get_type_size(type) == 2) {
788 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], ctx->ac.i32, "");
789 value[i] = LLVMBuildTrunc(ctx->ac.builder, value[i], ctx->ac.i16, "");
790 }
791 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], type, "");
792 }
793 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
794 result = ac_to_integer(&ctx->ac, result);
795 return result;
796 }
797
798 static uint32_t
799 radv_get_sample_pos_offset(uint32_t num_samples)
800 {
801 uint32_t sample_pos_offset = 0;
802
803 switch (num_samples) {
804 case 2:
805 sample_pos_offset = 1;
806 break;
807 case 4:
808 sample_pos_offset = 3;
809 break;
810 case 8:
811 sample_pos_offset = 7;
812 break;
813 default:
814 break;
815 }
816 return sample_pos_offset;
817 }
818
819 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
820 LLVMValueRef sample_id)
821 {
822 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
823
824 LLVMValueRef result;
825 LLVMValueRef index = LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false);
826 LLVMValueRef ptr = LLVMBuildGEP(ctx->ac.builder, ctx->ring_offsets, &index, 1, "");
827
828 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
829 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
830
831 uint32_t sample_pos_offset =
832 radv_get_sample_pos_offset(ctx->args->options->key.fs.num_samples);
833
834 sample_id =
835 LLVMBuildAdd(ctx->ac.builder, sample_id,
836 LLVMConstInt(ctx->ac.i32, sample_pos_offset, false), "");
837 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
838
839 return result;
840 }
841
842
843 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
844 {
845 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
846 uint8_t log2_ps_iter_samples;
847
848 if (ctx->args->shader_info->ps.force_persample) {
849 log2_ps_iter_samples =
850 util_logbase2(ctx->args->options->key.fs.num_samples);
851 } else {
852 log2_ps_iter_samples = ctx->args->options->key.fs.log2_ps_iter_samples;
853 }
854
855 /* The bit pattern matches that used by fixed function fragment
856 * processing. */
857 static const uint16_t ps_iter_masks[] = {
858 0xffff, /* not used */
859 0x5555,
860 0x1111,
861 0x0101,
862 0x0001,
863 };
864 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
865
866 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
867
868 LLVMValueRef result, sample_id;
869 sample_id = ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->ac.ancillary), 8, 4);
870 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
871 result = LLVMBuildAnd(ctx->ac.builder, sample_id,
872 ac_get_arg(&ctx->ac, ctx->args->ac.sample_coverage), "");
873 return result;
874 }
875
876
877 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context *ctx,
878 unsigned stream,
879 LLVMValueRef vertexidx,
880 LLVMValueRef *addrs);
881
882 static void
883 visit_emit_vertex_with_counter(struct ac_shader_abi *abi, unsigned stream,
884 LLVMValueRef vertexidx, LLVMValueRef *addrs)
885 {
886 unsigned offset = 0;
887 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
888
889 if (ctx->args->options->key.vs_common_out.as_ngg) {
890 gfx10_ngg_gs_emit_vertex(ctx, stream, vertexidx, addrs);
891 return;
892 }
893
894 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
895 unsigned output_usage_mask =
896 ctx->args->shader_info->gs.output_usage_mask[i];
897 uint8_t output_stream =
898 ctx->args->shader_info->gs.output_streams[i];
899 LLVMValueRef *out_ptr = &addrs[i * 4];
900 int length = util_last_bit(output_usage_mask);
901
902 if (!(ctx->output_mask & (1ull << i)) ||
903 output_stream != stream)
904 continue;
905
906 for (unsigned j = 0; j < length; j++) {
907 if (!(output_usage_mask & (1 << j)))
908 continue;
909
910 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
911 out_ptr[j], "");
912 LLVMValueRef voffset =
913 LLVMConstInt(ctx->ac.i32, offset *
914 ctx->shader->info.gs.vertices_out, false);
915
916 offset++;
917
918 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, vertexidx, "");
919 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
920
921 out_val = ac_to_integer(&ctx->ac, out_val);
922 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
923
924 ac_build_buffer_store_dword(&ctx->ac,
925 ctx->gsvs_ring[stream],
926 out_val, 1,
927 voffset,
928 ac_get_arg(&ctx->ac,
929 ctx->args->gs2vs_offset),
930 0, ac_glc | ac_slc | ac_swizzled);
931 }
932 }
933
934 ac_build_sendmsg(&ctx->ac,
935 AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
936 ctx->gs_wave_id);
937 }
938
939 static void
940 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
941 {
942 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
943
944 if (ctx->args->options->key.vs_common_out.as_ngg) {
945 LLVMBuildStore(ctx->ac.builder, ctx->ac.i32_0, ctx->gs_curprim_verts[stream]);
946 return;
947 }
948
949 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
950 }
951
952 static LLVMValueRef
953 load_tess_coord(struct ac_shader_abi *abi)
954 {
955 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
956
957 LLVMValueRef coord[4] = {
958 ac_get_arg(&ctx->ac, ctx->args->tes_u),
959 ac_get_arg(&ctx->ac, ctx->args->tes_v),
960 ctx->ac.f32_0,
961 ctx->ac.f32_0,
962 };
963
964 if (ctx->shader->info.tess.primitive_mode == GL_TRIANGLES)
965 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
966 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
967
968 return ac_build_gather_values(&ctx->ac, coord, 3);
969 }
970
971 static LLVMValueRef
972 load_patch_vertices_in(struct ac_shader_abi *abi)
973 {
974 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
975 return LLVMConstInt(ctx->ac.i32, ctx->args->options->key.tcs.input_vertices, false);
976 }
977
978
979 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
980 {
981 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
982 return ac_get_arg(&ctx->ac, ctx->args->ac.base_vertex);
983 }
984
985 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
986 LLVMValueRef buffer_ptr, bool write)
987 {
988 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
989 LLVMValueRef result;
990
991 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
992
993 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
994 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
995
996 return result;
997 }
998
999 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
1000 {
1001 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1002 LLVMValueRef result;
1003
1004 if (LLVMGetTypeKind(LLVMTypeOf(buffer_ptr)) != LLVMPointerTypeKind) {
1005 /* Do not load the descriptor for inlined uniform blocks. */
1006 return buffer_ptr;
1007 }
1008
1009 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1010
1011 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1012 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1013
1014 return result;
1015 }
1016
1017 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
1018 unsigned descriptor_set,
1019 unsigned base_index,
1020 unsigned constant_index,
1021 LLVMValueRef index,
1022 enum ac_descriptor_type desc_type,
1023 bool image, bool write,
1024 bool bindless)
1025 {
1026 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1027 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
1028 struct radv_descriptor_set_layout *layout = ctx->args->options->layout->set[descriptor_set].layout;
1029 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
1030 unsigned offset = binding->offset;
1031 unsigned stride = binding->size;
1032 unsigned type_size;
1033 LLVMBuilderRef builder = ctx->ac.builder;
1034 LLVMTypeRef type;
1035
1036 assert(base_index < layout->binding_count);
1037
1038 switch (desc_type) {
1039 case AC_DESC_IMAGE:
1040 type = ctx->ac.v8i32;
1041 type_size = 32;
1042 break;
1043 case AC_DESC_FMASK:
1044 type = ctx->ac.v8i32;
1045 offset += 32;
1046 type_size = 32;
1047 break;
1048 case AC_DESC_SAMPLER:
1049 type = ctx->ac.v4i32;
1050 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER) {
1051 offset += radv_combined_image_descriptor_sampler_offset(binding);
1052 }
1053
1054 type_size = 16;
1055 break;
1056 case AC_DESC_BUFFER:
1057 type = ctx->ac.v4i32;
1058 type_size = 16;
1059 break;
1060 case AC_DESC_PLANE_0:
1061 case AC_DESC_PLANE_1:
1062 case AC_DESC_PLANE_2:
1063 type = ctx->ac.v8i32;
1064 type_size = 32;
1065 offset += 32 * (desc_type - AC_DESC_PLANE_0);
1066 break;
1067 default:
1068 unreachable("invalid desc_type\n");
1069 }
1070
1071 offset += constant_index * stride;
1072
1073 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
1074 (!index || binding->immutable_samplers_equal)) {
1075 if (binding->immutable_samplers_equal)
1076 constant_index = 0;
1077
1078 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
1079
1080 LLVMValueRef constants[] = {
1081 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
1082 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
1083 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
1084 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
1085 };
1086 return ac_build_gather_values(&ctx->ac, constants, 4);
1087 }
1088
1089 assert(stride % type_size == 0);
1090
1091 LLVMValueRef adjusted_index = index;
1092 if (!adjusted_index)
1093 adjusted_index = ctx->ac.i32_0;
1094
1095 adjusted_index = LLVMBuildMul(builder, adjusted_index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
1096
1097 LLVMValueRef val_offset = LLVMConstInt(ctx->ac.i32, offset, 0);
1098 list = LLVMBuildGEP(builder, list, &val_offset, 1, "");
1099 list = LLVMBuildPointerCast(builder, list,
1100 ac_array_in_const32_addr_space(type), "");
1101
1102 LLVMValueRef descriptor = ac_build_load_to_sgpr(&ctx->ac, list, adjusted_index);
1103
1104 /* 3 plane formats always have same size and format for plane 1 & 2, so
1105 * use the tail from plane 1 so that we can store only the first 16 bytes
1106 * of the last plane. */
1107 if (desc_type == AC_DESC_PLANE_2) {
1108 LLVMValueRef descriptor2 = radv_get_sampler_desc(abi, descriptor_set, base_index, constant_index, index, AC_DESC_PLANE_1,image, write, bindless);
1109
1110 LLVMValueRef components[8];
1111 for (unsigned i = 0; i < 4; ++i)
1112 components[i] = ac_llvm_extract_elem(&ctx->ac, descriptor, i);
1113
1114 for (unsigned i = 4; i < 8; ++i)
1115 components[i] = ac_llvm_extract_elem(&ctx->ac, descriptor2, i);
1116 descriptor = ac_build_gather_values(&ctx->ac, components, 8);
1117 }
1118
1119 return descriptor;
1120 }
1121
1122 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
1123 * so we may need to fix it up. */
1124 static LLVMValueRef
1125 adjust_vertex_fetch_alpha(struct radv_shader_context *ctx,
1126 unsigned adjustment,
1127 LLVMValueRef alpha)
1128 {
1129 if (adjustment == RADV_ALPHA_ADJUST_NONE)
1130 return alpha;
1131
1132 LLVMValueRef c30 = LLVMConstInt(ctx->ac.i32, 30, 0);
1133
1134 alpha = LLVMBuildBitCast(ctx->ac.builder, alpha, ctx->ac.f32, "");
1135
1136 if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
1137 alpha = LLVMBuildFPToUI(ctx->ac.builder, alpha, ctx->ac.i32, "");
1138 else
1139 alpha = ac_to_integer(&ctx->ac, alpha);
1140
1141 /* For the integer-like cases, do a natural sign extension.
1142 *
1143 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
1144 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
1145 * exponent.
1146 */
1147 alpha = LLVMBuildShl(ctx->ac.builder, alpha,
1148 adjustment == RADV_ALPHA_ADJUST_SNORM ?
1149 LLVMConstInt(ctx->ac.i32, 7, 0) : c30, "");
1150 alpha = LLVMBuildAShr(ctx->ac.builder, alpha, c30, "");
1151
1152 /* Convert back to the right type. */
1153 if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
1154 LLVMValueRef clamp;
1155 LLVMValueRef neg_one = LLVMConstReal(ctx->ac.f32, -1.0);
1156 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1157 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, alpha, neg_one, "");
1158 alpha = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, alpha, "");
1159 } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
1160 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
1161 }
1162
1163 return LLVMBuildBitCast(ctx->ac.builder, alpha, ctx->ac.i32, "");
1164 }
1165
1166 static LLVMValueRef
1167 radv_fixup_vertex_input_fetches(struct radv_shader_context *ctx,
1168 LLVMValueRef value,
1169 unsigned num_channels,
1170 bool is_float)
1171 {
1172 LLVMValueRef zero = is_float ? ctx->ac.f32_0 : ctx->ac.i32_0;
1173 LLVMValueRef one = is_float ? ctx->ac.f32_1 : ctx->ac.i32_1;
1174 LLVMValueRef chan[4];
1175
1176 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMVectorTypeKind) {
1177 unsigned vec_size = LLVMGetVectorSize(LLVMTypeOf(value));
1178
1179 if (num_channels == 4 && num_channels == vec_size)
1180 return value;
1181
1182 num_channels = MIN2(num_channels, vec_size);
1183
1184 for (unsigned i = 0; i < num_channels; i++)
1185 chan[i] = ac_llvm_extract_elem(&ctx->ac, value, i);
1186 } else {
1187 assert(num_channels == 1);
1188 chan[0] = value;
1189 }
1190
1191 for (unsigned i = num_channels; i < 4; i++) {
1192 chan[i] = i == 3 ? one : zero;
1193 chan[i] = ac_to_integer(&ctx->ac, chan[i]);
1194 }
1195
1196 return ac_build_gather_values(&ctx->ac, chan, 4);
1197 }
1198
1199 static void
1200 handle_vs_input_decl(struct radv_shader_context *ctx,
1201 struct nir_variable *variable)
1202 {
1203 LLVMValueRef t_list_ptr = ac_get_arg(&ctx->ac, ctx->args->vertex_buffers);
1204 LLVMValueRef t_offset;
1205 LLVMValueRef t_list;
1206 LLVMValueRef input;
1207 LLVMValueRef buffer_index;
1208 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
1209 uint8_t input_usage_mask =
1210 ctx->args->shader_info->vs.input_usage_mask[variable->data.location];
1211 unsigned num_input_channels = util_last_bit(input_usage_mask);
1212
1213 variable->data.driver_location = variable->data.location * 4;
1214
1215 enum glsl_base_type type = glsl_get_base_type(variable->type);
1216 for (unsigned i = 0; i < attrib_count; ++i) {
1217 LLVMValueRef output[4];
1218 unsigned attrib_index = variable->data.location + i - VERT_ATTRIB_GENERIC0;
1219 unsigned attrib_format = ctx->args->options->key.vs.vertex_attribute_formats[attrib_index];
1220 unsigned data_format = attrib_format & 0x0f;
1221 unsigned num_format = (attrib_format >> 4) & 0x07;
1222 bool is_float = num_format != V_008F0C_BUF_NUM_FORMAT_UINT &&
1223 num_format != V_008F0C_BUF_NUM_FORMAT_SINT;
1224
1225 if (ctx->args->options->key.vs.instance_rate_inputs & (1u << attrib_index)) {
1226 uint32_t divisor = ctx->args->options->key.vs.instance_rate_divisors[attrib_index];
1227
1228 if (divisor) {
1229 buffer_index = ctx->abi.instance_id;
1230
1231 if (divisor != 1) {
1232 buffer_index = LLVMBuildUDiv(ctx->ac.builder, buffer_index,
1233 LLVMConstInt(ctx->ac.i32, divisor, 0), "");
1234 }
1235 } else {
1236 buffer_index = ctx->ac.i32_0;
1237 }
1238
1239 buffer_index = LLVMBuildAdd(ctx->ac.builder,
1240 ac_get_arg(&ctx->ac,
1241 ctx->args->ac.start_instance),\
1242 buffer_index, "");
1243 } else {
1244 buffer_index = LLVMBuildAdd(ctx->ac.builder,
1245 ctx->abi.vertex_id,
1246 ac_get_arg(&ctx->ac,
1247 ctx->args->ac.base_vertex), "");
1248 }
1249
1250 const struct ac_data_format_info *vtx_info = ac_get_data_format_info(data_format);
1251
1252 /* Adjust the number of channels to load based on the vertex
1253 * attribute format.
1254 */
1255 unsigned num_channels = MIN2(num_input_channels, vtx_info->num_channels);
1256 unsigned attrib_binding = ctx->args->options->key.vs.vertex_attribute_bindings[attrib_index];
1257 unsigned attrib_offset = ctx->args->options->key.vs.vertex_attribute_offsets[attrib_index];
1258 unsigned attrib_stride = ctx->args->options->key.vs.vertex_attribute_strides[attrib_index];
1259
1260 if (ctx->args->options->key.vs.post_shuffle & (1 << attrib_index)) {
1261 /* Always load, at least, 3 channels for formats that
1262 * need to be shuffled because X<->Z.
1263 */
1264 num_channels = MAX2(num_channels, 3);
1265 }
1266
1267 t_offset = LLVMConstInt(ctx->ac.i32, attrib_binding, false);
1268 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
1269
1270 /* Perform per-channel vertex fetch operations if unaligned
1271 * access are detected. Only GFX6 and GFX10 are affected.
1272 */
1273 bool unaligned_vertex_fetches = false;
1274 if ((ctx->ac.chip_class == GFX6 || ctx->ac.chip_class >= GFX10) &&
1275 vtx_info->chan_format != data_format &&
1276 ((attrib_offset % vtx_info->element_size) ||
1277 (attrib_stride % vtx_info->element_size)))
1278 unaligned_vertex_fetches = true;
1279
1280 if (unaligned_vertex_fetches) {
1281 unsigned chan_format = vtx_info->chan_format;
1282 LLVMValueRef values[4];
1283
1284 assert(ctx->ac.chip_class == GFX6 ||
1285 ctx->ac.chip_class >= GFX10);
1286
1287 for (unsigned chan = 0; chan < num_channels; chan++) {
1288 unsigned chan_offset = attrib_offset + chan * vtx_info->chan_byte_size;
1289 LLVMValueRef chan_index = buffer_index;
1290
1291 if (attrib_stride != 0 && chan_offset > attrib_stride) {
1292 LLVMValueRef buffer_offset =
1293 LLVMConstInt(ctx->ac.i32,
1294 chan_offset / attrib_stride, false);
1295
1296 chan_index = LLVMBuildAdd(ctx->ac.builder,
1297 buffer_index,
1298 buffer_offset, "");
1299
1300 chan_offset = chan_offset % attrib_stride;
1301 }
1302
1303 values[chan] = ac_build_struct_tbuffer_load(&ctx->ac, t_list,
1304 chan_index,
1305 LLVMConstInt(ctx->ac.i32, chan_offset, false),
1306 ctx->ac.i32_0, ctx->ac.i32_0, 1,
1307 chan_format, num_format, 0, true);
1308 }
1309
1310 input = ac_build_gather_values(&ctx->ac, values, num_channels);
1311 } else {
1312 if (attrib_stride != 0 && attrib_offset > attrib_stride) {
1313 LLVMValueRef buffer_offset =
1314 LLVMConstInt(ctx->ac.i32,
1315 attrib_offset / attrib_stride, false);
1316
1317 buffer_index = LLVMBuildAdd(ctx->ac.builder,
1318 buffer_index,
1319 buffer_offset, "");
1320
1321 attrib_offset = attrib_offset % attrib_stride;
1322 }
1323
1324 input = ac_build_struct_tbuffer_load(&ctx->ac, t_list,
1325 buffer_index,
1326 LLVMConstInt(ctx->ac.i32, attrib_offset, false),
1327 ctx->ac.i32_0, ctx->ac.i32_0,
1328 num_channels,
1329 data_format, num_format, 0, true);
1330 }
1331
1332 if (ctx->args->options->key.vs.post_shuffle & (1 << attrib_index)) {
1333 LLVMValueRef c[4];
1334 c[0] = ac_llvm_extract_elem(&ctx->ac, input, 2);
1335 c[1] = ac_llvm_extract_elem(&ctx->ac, input, 1);
1336 c[2] = ac_llvm_extract_elem(&ctx->ac, input, 0);
1337 c[3] = ac_llvm_extract_elem(&ctx->ac, input, 3);
1338
1339 input = ac_build_gather_values(&ctx->ac, c, 4);
1340 }
1341
1342 input = radv_fixup_vertex_input_fetches(ctx, input, num_channels,
1343 is_float);
1344
1345 for (unsigned chan = 0; chan < 4; chan++) {
1346 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
1347 output[chan] = LLVMBuildExtractElement(ctx->ac.builder, input, llvm_chan, "");
1348 if (type == GLSL_TYPE_FLOAT16) {
1349 output[chan] = LLVMBuildBitCast(ctx->ac.builder, output[chan], ctx->ac.f32, "");
1350 output[chan] = LLVMBuildFPTrunc(ctx->ac.builder, output[chan], ctx->ac.f16, "");
1351 }
1352 }
1353
1354 unsigned alpha_adjust = (ctx->args->options->key.vs.alpha_adjust >> (attrib_index * 2)) & 3;
1355 output[3] = adjust_vertex_fetch_alpha(ctx, alpha_adjust, output[3]);
1356
1357 for (unsigned chan = 0; chan < 4; chan++) {
1358 output[chan] = ac_to_integer(&ctx->ac, output[chan]);
1359 if (type == GLSL_TYPE_UINT16 || type == GLSL_TYPE_INT16)
1360 output[chan] = LLVMBuildTrunc(ctx->ac.builder, output[chan], ctx->ac.i16, "");
1361
1362 ctx->inputs[ac_llvm_reg_index_soa(variable->data.location + i, chan)] = output[chan];
1363 }
1364 }
1365 }
1366
1367 static void
1368 handle_vs_inputs(struct radv_shader_context *ctx,
1369 struct nir_shader *nir) {
1370 nir_foreach_variable(variable, &nir->inputs)
1371 handle_vs_input_decl(ctx, variable);
1372 }
1373
1374 static void
1375 prepare_interp_optimize(struct radv_shader_context *ctx,
1376 struct nir_shader *nir)
1377 {
1378 bool uses_center = false;
1379 bool uses_centroid = false;
1380 nir_foreach_variable(variable, &nir->inputs) {
1381 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
1382 variable->data.sample)
1383 continue;
1384
1385 if (variable->data.centroid)
1386 uses_centroid = true;
1387 else
1388 uses_center = true;
1389 }
1390
1391 ctx->abi.persp_centroid = ac_get_arg(&ctx->ac, ctx->args->ac.persp_centroid);
1392 ctx->abi.linear_centroid = ac_get_arg(&ctx->ac, ctx->args->ac.linear_centroid);
1393
1394 if (uses_center && uses_centroid) {
1395 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT,
1396 ac_get_arg(&ctx->ac, ctx->args->ac.prim_mask),
1397 ctx->ac.i32_0, "");
1398 ctx->abi.persp_centroid =
1399 LLVMBuildSelect(ctx->ac.builder, sel,
1400 ac_get_arg(&ctx->ac, ctx->args->ac.persp_center),
1401 ctx->abi.persp_centroid, "");
1402 ctx->abi.linear_centroid =
1403 LLVMBuildSelect(ctx->ac.builder, sel,
1404 ac_get_arg(&ctx->ac, ctx->args->ac.linear_center),
1405 ctx->abi.linear_centroid, "");
1406 }
1407 }
1408
1409 static void
1410 scan_shader_output_decl(struct radv_shader_context *ctx,
1411 struct nir_variable *variable,
1412 struct nir_shader *shader,
1413 gl_shader_stage stage)
1414 {
1415 int idx = variable->data.location + variable->data.index;
1416 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
1417 uint64_t mask_attribs;
1418
1419 variable->data.driver_location = idx * 4;
1420
1421 /* tess ctrl has it's own load/store paths for outputs */
1422 if (stage == MESA_SHADER_TESS_CTRL)
1423 return;
1424
1425 if (variable->data.compact) {
1426 unsigned component_count = variable->data.location_frac +
1427 glsl_get_length(variable->type);
1428 attrib_count = (component_count + 3) / 4;
1429 }
1430
1431 mask_attribs = ((1ull << attrib_count) - 1) << idx;
1432
1433 ctx->output_mask |= mask_attribs;
1434 }
1435
1436
1437 /* Initialize arguments for the shader export intrinsic */
1438 static void
1439 si_llvm_init_export_args(struct radv_shader_context *ctx,
1440 LLVMValueRef *values,
1441 unsigned enabled_channels,
1442 unsigned target,
1443 struct ac_export_args *args)
1444 {
1445 /* Specify the channels that are enabled. */
1446 args->enabled_channels = enabled_channels;
1447
1448 /* Specify whether the EXEC mask represents the valid mask */
1449 args->valid_mask = 0;
1450
1451 /* Specify whether this is the last export */
1452 args->done = 0;
1453
1454 /* Specify the target we are exporting */
1455 args->target = target;
1456
1457 args->compr = false;
1458 args->out[0] = LLVMGetUndef(ctx->ac.f32);
1459 args->out[1] = LLVMGetUndef(ctx->ac.f32);
1460 args->out[2] = LLVMGetUndef(ctx->ac.f32);
1461 args->out[3] = LLVMGetUndef(ctx->ac.f32);
1462
1463 if (!values)
1464 return;
1465
1466 bool is_16bit = ac_get_type_size(LLVMTypeOf(values[0])) == 2;
1467 if (ctx->stage == MESA_SHADER_FRAGMENT) {
1468 unsigned index = target - V_008DFC_SQ_EXP_MRT;
1469 unsigned col_format = (ctx->args->options->key.fs.col_format >> (4 * index)) & 0xf;
1470 bool is_int8 = (ctx->args->options->key.fs.is_int8 >> index) & 1;
1471 bool is_int10 = (ctx->args->options->key.fs.is_int10 >> index) & 1;
1472 unsigned chan;
1473
1474 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
1475 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
1476 unsigned bits, bool hi) = NULL;
1477
1478 switch(col_format) {
1479 case V_028714_SPI_SHADER_ZERO:
1480 args->enabled_channels = 0; /* writemask */
1481 args->target = V_008DFC_SQ_EXP_NULL;
1482 break;
1483
1484 case V_028714_SPI_SHADER_32_R:
1485 args->enabled_channels = 1;
1486 args->out[0] = values[0];
1487 break;
1488
1489 case V_028714_SPI_SHADER_32_GR:
1490 args->enabled_channels = 0x3;
1491 args->out[0] = values[0];
1492 args->out[1] = values[1];
1493 break;
1494
1495 case V_028714_SPI_SHADER_32_AR:
1496 if (ctx->ac.chip_class >= GFX10) {
1497 args->enabled_channels = 0x3;
1498 args->out[0] = values[0];
1499 args->out[1] = values[3];
1500 } else {
1501 args->enabled_channels = 0x9;
1502 args->out[0] = values[0];
1503 args->out[3] = values[3];
1504 }
1505 break;
1506
1507 case V_028714_SPI_SHADER_FP16_ABGR:
1508 args->enabled_channels = 0x5;
1509 packf = ac_build_cvt_pkrtz_f16;
1510 if (is_16bit) {
1511 for (unsigned chan = 0; chan < 4; chan++)
1512 values[chan] = LLVMBuildFPExt(ctx->ac.builder,
1513 values[chan],
1514 ctx->ac.f32, "");
1515 }
1516 break;
1517
1518 case V_028714_SPI_SHADER_UNORM16_ABGR:
1519 args->enabled_channels = 0x5;
1520 packf = ac_build_cvt_pknorm_u16;
1521 break;
1522
1523 case V_028714_SPI_SHADER_SNORM16_ABGR:
1524 args->enabled_channels = 0x5;
1525 packf = ac_build_cvt_pknorm_i16;
1526 break;
1527
1528 case V_028714_SPI_SHADER_UINT16_ABGR:
1529 args->enabled_channels = 0x5;
1530 packi = ac_build_cvt_pk_u16;
1531 if (is_16bit) {
1532 for (unsigned chan = 0; chan < 4; chan++)
1533 values[chan] = LLVMBuildZExt(ctx->ac.builder,
1534 ac_to_integer(&ctx->ac, values[chan]),
1535 ctx->ac.i32, "");
1536 }
1537 break;
1538
1539 case V_028714_SPI_SHADER_SINT16_ABGR:
1540 args->enabled_channels = 0x5;
1541 packi = ac_build_cvt_pk_i16;
1542 if (is_16bit) {
1543 for (unsigned chan = 0; chan < 4; chan++)
1544 values[chan] = LLVMBuildSExt(ctx->ac.builder,
1545 ac_to_integer(&ctx->ac, values[chan]),
1546 ctx->ac.i32, "");
1547 }
1548 break;
1549
1550 default:
1551 case V_028714_SPI_SHADER_32_ABGR:
1552 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
1553 break;
1554 }
1555
1556 /* Replace NaN by zero (only 32-bit) to fix game bugs if
1557 * requested.
1558 */
1559 if (ctx->args->options->enable_mrt_output_nan_fixup &&
1560 !is_16bit &&
1561 (col_format == V_028714_SPI_SHADER_32_R ||
1562 col_format == V_028714_SPI_SHADER_32_GR ||
1563 col_format == V_028714_SPI_SHADER_32_AR ||
1564 col_format == V_028714_SPI_SHADER_32_ABGR ||
1565 col_format == V_028714_SPI_SHADER_FP16_ABGR)) {
1566 for (unsigned i = 0; i < 4; i++) {
1567 LLVMValueRef args[2] = {
1568 values[i],
1569 LLVMConstInt(ctx->ac.i32, S_NAN | Q_NAN, false)
1570 };
1571 LLVMValueRef isnan =
1572 ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.class.f32", ctx->ac.i1,
1573 args, 2, AC_FUNC_ATTR_READNONE);
1574 values[i] = LLVMBuildSelect(ctx->ac.builder, isnan,
1575 ctx->ac.f32_0,
1576 values[i], "");
1577 }
1578 }
1579
1580 /* Pack f16 or norm_i16/u16. */
1581 if (packf) {
1582 for (chan = 0; chan < 2; chan++) {
1583 LLVMValueRef pack_args[2] = {
1584 values[2 * chan],
1585 values[2 * chan + 1]
1586 };
1587 LLVMValueRef packed;
1588
1589 packed = packf(&ctx->ac, pack_args);
1590 args->out[chan] = ac_to_float(&ctx->ac, packed);
1591 }
1592 args->compr = 1; /* COMPR flag */
1593 }
1594
1595 /* Pack i16/u16. */
1596 if (packi) {
1597 for (chan = 0; chan < 2; chan++) {
1598 LLVMValueRef pack_args[2] = {
1599 ac_to_integer(&ctx->ac, values[2 * chan]),
1600 ac_to_integer(&ctx->ac, values[2 * chan + 1])
1601 };
1602 LLVMValueRef packed;
1603
1604 packed = packi(&ctx->ac, pack_args,
1605 is_int8 ? 8 : is_int10 ? 10 : 16,
1606 chan == 1);
1607 args->out[chan] = ac_to_float(&ctx->ac, packed);
1608 }
1609 args->compr = 1; /* COMPR flag */
1610 }
1611 return;
1612 }
1613
1614 if (is_16bit) {
1615 for (unsigned chan = 0; chan < 4; chan++) {
1616 values[chan] = LLVMBuildBitCast(ctx->ac.builder, values[chan], ctx->ac.i16, "");
1617 args->out[chan] = LLVMBuildZExt(ctx->ac.builder, values[chan], ctx->ac.i32, "");
1618 }
1619 } else
1620 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
1621
1622 for (unsigned i = 0; i < 4; ++i)
1623 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
1624 }
1625
1626 static void
1627 radv_export_param(struct radv_shader_context *ctx, unsigned index,
1628 LLVMValueRef *values, unsigned enabled_channels)
1629 {
1630 struct ac_export_args args;
1631
1632 si_llvm_init_export_args(ctx, values, enabled_channels,
1633 V_008DFC_SQ_EXP_PARAM + index, &args);
1634 ac_build_export(&ctx->ac, &args);
1635 }
1636
1637 static LLVMValueRef
1638 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
1639 {
1640 LLVMValueRef output = ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
1641 return LLVMBuildLoad(ctx->ac.builder, output, "");
1642 }
1643
1644 static void
1645 radv_emit_stream_output(struct radv_shader_context *ctx,
1646 LLVMValueRef const *so_buffers,
1647 LLVMValueRef const *so_write_offsets,
1648 const struct radv_stream_output *output,
1649 struct radv_shader_output_values *shader_out)
1650 {
1651 unsigned num_comps = util_bitcount(output->component_mask);
1652 unsigned buf = output->buffer;
1653 unsigned offset = output->offset;
1654 unsigned start;
1655 LLVMValueRef out[4];
1656
1657 assert(num_comps && num_comps <= 4);
1658 if (!num_comps || num_comps > 4)
1659 return;
1660
1661 /* Get the first component. */
1662 start = ffs(output->component_mask) - 1;
1663
1664 /* Load the output as int. */
1665 for (int i = 0; i < num_comps; i++) {
1666 out[i] = ac_to_integer(&ctx->ac, shader_out->values[start + i]);
1667 }
1668
1669 /* Pack the output. */
1670 LLVMValueRef vdata = NULL;
1671
1672 switch (num_comps) {
1673 case 1: /* as i32 */
1674 vdata = out[0];
1675 break;
1676 case 2: /* as v2i32 */
1677 case 3: /* as v4i32 (aligned to 4) */
1678 out[3] = LLVMGetUndef(ctx->ac.i32);
1679 /* fall through */
1680 case 4: /* as v4i32 */
1681 vdata = ac_build_gather_values(&ctx->ac, out,
1682 !ac_has_vec3_support(ctx->ac.chip_class, false) ?
1683 util_next_power_of_two(num_comps) :
1684 num_comps);
1685 break;
1686 }
1687
1688 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf],
1689 vdata, num_comps, so_write_offsets[buf],
1690 ctx->ac.i32_0, offset,
1691 ac_glc | ac_slc);
1692 }
1693
1694 static void
1695 radv_emit_streamout(struct radv_shader_context *ctx, unsigned stream)
1696 {
1697 int i;
1698
1699 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1700 assert(ctx->args->streamout_config.used);
1701 LLVMValueRef so_vtx_count =
1702 ac_build_bfe(&ctx->ac,
1703 ac_get_arg(&ctx->ac, ctx->args->streamout_config),
1704 LLVMConstInt(ctx->ac.i32, 16, false),
1705 LLVMConstInt(ctx->ac.i32, 7, false), false);
1706
1707 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
1708
1709 /* can_emit = tid < so_vtx_count; */
1710 LLVMValueRef can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
1711 tid, so_vtx_count, "");
1712
1713 /* Emit the streamout code conditionally. This actually avoids
1714 * out-of-bounds buffer access. The hw tells us via the SGPR
1715 * (so_vtx_count) which threads are allowed to emit streamout data.
1716 */
1717 ac_build_ifcc(&ctx->ac, can_emit, 6501);
1718 {
1719 /* The buffer offset is computed as follows:
1720 * ByteOffset = streamout_offset[buffer_id]*4 +
1721 * (streamout_write_index + thread_id)*stride[buffer_id] +
1722 * attrib_offset
1723 */
1724 LLVMValueRef so_write_index =
1725 ac_get_arg(&ctx->ac, ctx->args->streamout_write_idx);
1726
1727 /* Compute (streamout_write_index + thread_id). */
1728 so_write_index =
1729 LLVMBuildAdd(ctx->ac.builder, so_write_index, tid, "");
1730
1731 /* Load the descriptor and compute the write offset for each
1732 * enabled buffer.
1733 */
1734 LLVMValueRef so_write_offset[4] = {};
1735 LLVMValueRef so_buffers[4] = {};
1736 LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac, ctx->args->streamout_buffers);
1737
1738 for (i = 0; i < 4; i++) {
1739 uint16_t stride = ctx->args->shader_info->so.strides[i];
1740
1741 if (!stride)
1742 continue;
1743
1744 LLVMValueRef offset =
1745 LLVMConstInt(ctx->ac.i32, i, false);
1746
1747 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac,
1748 buf_ptr, offset);
1749
1750 LLVMValueRef so_offset =
1751 ac_get_arg(&ctx->ac, ctx->args->streamout_offset[i]);
1752
1753 so_offset = LLVMBuildMul(ctx->ac.builder, so_offset,
1754 LLVMConstInt(ctx->ac.i32, 4, false), "");
1755
1756 so_write_offset[i] =
1757 ac_build_imad(&ctx->ac, so_write_index,
1758 LLVMConstInt(ctx->ac.i32,
1759 stride * 4, false),
1760 so_offset);
1761 }
1762
1763 /* Write streamout data. */
1764 for (i = 0; i < ctx->args->shader_info->so.num_outputs; i++) {
1765 struct radv_shader_output_values shader_out = {};
1766 struct radv_stream_output *output =
1767 &ctx->args->shader_info->so.outputs[i];
1768
1769 if (stream != output->stream)
1770 continue;
1771
1772 for (int j = 0; j < 4; j++) {
1773 shader_out.values[j] =
1774 radv_load_output(ctx, output->location, j);
1775 }
1776
1777 radv_emit_stream_output(ctx, so_buffers,so_write_offset,
1778 output, &shader_out);
1779 }
1780 }
1781 ac_build_endif(&ctx->ac, 6501);
1782 }
1783
1784 static void
1785 radv_build_param_exports(struct radv_shader_context *ctx,
1786 struct radv_shader_output_values *outputs,
1787 unsigned noutput,
1788 struct radv_vs_output_info *outinfo,
1789 bool export_clip_dists)
1790 {
1791 unsigned param_count = 0;
1792
1793 for (unsigned i = 0; i < noutput; i++) {
1794 unsigned slot_name = outputs[i].slot_name;
1795 unsigned usage_mask = outputs[i].usage_mask;
1796
1797 if (slot_name != VARYING_SLOT_LAYER &&
1798 slot_name != VARYING_SLOT_PRIMITIVE_ID &&
1799 slot_name != VARYING_SLOT_VIEWPORT &&
1800 slot_name != VARYING_SLOT_CLIP_DIST0 &&
1801 slot_name != VARYING_SLOT_CLIP_DIST1 &&
1802 slot_name < VARYING_SLOT_VAR0)
1803 continue;
1804
1805 if ((slot_name == VARYING_SLOT_CLIP_DIST0 ||
1806 slot_name == VARYING_SLOT_CLIP_DIST1) && !export_clip_dists)
1807 continue;
1808
1809 radv_export_param(ctx, param_count, outputs[i].values, usage_mask);
1810
1811 assert(i < ARRAY_SIZE(outinfo->vs_output_param_offset));
1812 outinfo->vs_output_param_offset[slot_name] = param_count++;
1813 }
1814
1815 outinfo->param_exports = param_count;
1816 }
1817
1818 /* Generate export instructions for hardware VS shader stage or NGG GS stage
1819 * (position and parameter data only).
1820 */
1821 static void
1822 radv_llvm_export_vs(struct radv_shader_context *ctx,
1823 struct radv_shader_output_values *outputs,
1824 unsigned noutput,
1825 struct radv_vs_output_info *outinfo,
1826 bool export_clip_dists)
1827 {
1828 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_value = NULL;
1829 struct ac_export_args pos_args[4] = {};
1830 unsigned pos_idx, index;
1831 int i;
1832
1833 /* Build position exports */
1834 for (i = 0; i < noutput; i++) {
1835 switch (outputs[i].slot_name) {
1836 case VARYING_SLOT_POS:
1837 si_llvm_init_export_args(ctx, outputs[i].values, 0xf,
1838 V_008DFC_SQ_EXP_POS, &pos_args[0]);
1839 break;
1840 case VARYING_SLOT_PSIZ:
1841 psize_value = outputs[i].values[0];
1842 break;
1843 case VARYING_SLOT_LAYER:
1844 layer_value = outputs[i].values[0];
1845 break;
1846 case VARYING_SLOT_VIEWPORT:
1847 viewport_value = outputs[i].values[0];
1848 break;
1849 case VARYING_SLOT_CLIP_DIST0:
1850 case VARYING_SLOT_CLIP_DIST1:
1851 index = 2 + outputs[i].slot_index;
1852 si_llvm_init_export_args(ctx, outputs[i].values, 0xf,
1853 V_008DFC_SQ_EXP_POS + index,
1854 &pos_args[index]);
1855 break;
1856 default:
1857 break;
1858 }
1859 }
1860
1861 /* We need to add the position output manually if it's missing. */
1862 if (!pos_args[0].out[0]) {
1863 pos_args[0].enabled_channels = 0xf; /* writemask */
1864 pos_args[0].valid_mask = 0; /* EXEC mask */
1865 pos_args[0].done = 0; /* last export? */
1866 pos_args[0].target = V_008DFC_SQ_EXP_POS;
1867 pos_args[0].compr = 0; /* COMPR flag */
1868 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
1869 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
1870 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
1871 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
1872 }
1873
1874 if (outinfo->writes_pointsize ||
1875 outinfo->writes_layer ||
1876 outinfo->writes_viewport_index) {
1877 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
1878 (outinfo->writes_layer == true ? 4 : 0));
1879 pos_args[1].valid_mask = 0;
1880 pos_args[1].done = 0;
1881 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
1882 pos_args[1].compr = 0;
1883 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
1884 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
1885 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
1886 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
1887
1888 if (outinfo->writes_pointsize == true)
1889 pos_args[1].out[0] = psize_value;
1890 if (outinfo->writes_layer == true)
1891 pos_args[1].out[2] = layer_value;
1892 if (outinfo->writes_viewport_index == true) {
1893 if (ctx->args->options->chip_class >= GFX9) {
1894 /* GFX9 has the layer in out.z[10:0] and the viewport
1895 * index in out.z[19:16].
1896 */
1897 LLVMValueRef v = viewport_value;
1898 v = ac_to_integer(&ctx->ac, v);
1899 v = LLVMBuildShl(ctx->ac.builder, v,
1900 LLVMConstInt(ctx->ac.i32, 16, false),
1901 "");
1902 v = LLVMBuildOr(ctx->ac.builder, v,
1903 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
1904
1905 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
1906 pos_args[1].enabled_channels |= 1 << 2;
1907 } else {
1908 pos_args[1].out[3] = viewport_value;
1909 pos_args[1].enabled_channels |= 1 << 3;
1910 }
1911 }
1912 }
1913
1914 for (i = 0; i < 4; i++) {
1915 if (pos_args[i].out[0])
1916 outinfo->pos_exports++;
1917 }
1918
1919 /* GFX10 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
1920 * Setting valid_mask=1 prevents it and has no other effect.
1921 */
1922 if (ctx->ac.chip_class == GFX10)
1923 pos_args[0].valid_mask = 1;
1924
1925 pos_idx = 0;
1926 for (i = 0; i < 4; i++) {
1927 if (!pos_args[i].out[0])
1928 continue;
1929
1930 /* Specify the target we are exporting */
1931 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
1932
1933 if (pos_idx == outinfo->pos_exports)
1934 /* Specify that this is the last export */
1935 pos_args[i].done = 1;
1936
1937 ac_build_export(&ctx->ac, &pos_args[i]);
1938 }
1939
1940 /* Build parameter exports */
1941 radv_build_param_exports(ctx, outputs, noutput, outinfo, export_clip_dists);
1942 }
1943
1944 static void
1945 handle_vs_outputs_post(struct radv_shader_context *ctx,
1946 bool export_prim_id,
1947 bool export_clip_dists,
1948 struct radv_vs_output_info *outinfo)
1949 {
1950 struct radv_shader_output_values *outputs;
1951 unsigned noutput = 0;
1952
1953 if (ctx->args->options->key.has_multiview_view_index) {
1954 LLVMValueRef* tmp_out = &ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
1955 if(!*tmp_out) {
1956 for(unsigned i = 0; i < 4; ++i)
1957 ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
1958 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
1959 }
1960
1961 LLVMValueRef view_index = ac_get_arg(&ctx->ac, ctx->args->ac.view_index);
1962 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, view_index), *tmp_out);
1963 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
1964 }
1965
1966 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
1967 sizeof(outinfo->vs_output_param_offset));
1968 outinfo->pos_exports = 0;
1969
1970 if (!ctx->args->options->use_ngg_streamout &&
1971 ctx->args->shader_info->so.num_outputs &&
1972 !ctx->args->is_gs_copy_shader) {
1973 /* The GS copy shader emission already emits streamout. */
1974 radv_emit_streamout(ctx, 0);
1975 }
1976
1977 /* Allocate a temporary array for the output values. */
1978 unsigned num_outputs = util_bitcount64(ctx->output_mask) + export_prim_id;
1979 outputs = malloc(num_outputs * sizeof(outputs[0]));
1980
1981 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
1982 if (!(ctx->output_mask & (1ull << i)))
1983 continue;
1984
1985 outputs[noutput].slot_name = i;
1986 outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
1987
1988 if (ctx->stage == MESA_SHADER_VERTEX &&
1989 !ctx->args->is_gs_copy_shader) {
1990 outputs[noutput].usage_mask =
1991 ctx->args->shader_info->vs.output_usage_mask[i];
1992 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
1993 outputs[noutput].usage_mask =
1994 ctx->args->shader_info->tes.output_usage_mask[i];
1995 } else {
1996 assert(ctx->args->is_gs_copy_shader);
1997 outputs[noutput].usage_mask =
1998 ctx->args->shader_info->gs.output_usage_mask[i];
1999 }
2000
2001 for (unsigned j = 0; j < 4; j++) {
2002 outputs[noutput].values[j] =
2003 ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2004 }
2005
2006 noutput++;
2007 }
2008
2009 /* Export PrimitiveID. */
2010 if (export_prim_id) {
2011 outputs[noutput].slot_name = VARYING_SLOT_PRIMITIVE_ID;
2012 outputs[noutput].slot_index = 0;
2013 outputs[noutput].usage_mask = 0x1;
2014 outputs[noutput].values[0] =
2015 ac_get_arg(&ctx->ac, ctx->args->vs_prim_id);
2016 for (unsigned j = 1; j < 4; j++)
2017 outputs[noutput].values[j] = ctx->ac.f32_0;
2018 noutput++;
2019 }
2020
2021 radv_llvm_export_vs(ctx, outputs, noutput, outinfo, export_clip_dists);
2022
2023 free(outputs);
2024 }
2025
2026 static void
2027 handle_es_outputs_post(struct radv_shader_context *ctx,
2028 struct radv_es_output_info *outinfo)
2029 {
2030 int j;
2031 LLVMValueRef lds_base = NULL;
2032
2033 if (ctx->ac.chip_class >= GFX9) {
2034 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
2035 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
2036 LLVMValueRef wave_idx =
2037 ac_unpack_param(&ctx->ac,
2038 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 24, 4);
2039 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
2040 LLVMBuildMul(ctx->ac.builder, wave_idx,
2041 LLVMConstInt(ctx->ac.i32,
2042 ctx->ac.wave_size, false), ""), "");
2043 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
2044 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
2045 }
2046
2047 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2048 LLVMValueRef dw_addr = NULL;
2049 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2050 unsigned output_usage_mask;
2051 int param_index;
2052
2053 if (!(ctx->output_mask & (1ull << i)))
2054 continue;
2055
2056 if (ctx->stage == MESA_SHADER_VERTEX) {
2057 output_usage_mask =
2058 ctx->args->shader_info->vs.output_usage_mask[i];
2059 } else {
2060 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2061 output_usage_mask =
2062 ctx->args->shader_info->tes.output_usage_mask[i];
2063 }
2064
2065 param_index = shader_io_get_unique_index(i);
2066
2067 if (lds_base) {
2068 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2069 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
2070 "");
2071 }
2072
2073 for (j = 0; j < 4; j++) {
2074 if (!(output_usage_mask & (1 << j)))
2075 continue;
2076
2077 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2078 out_val = ac_to_integer(&ctx->ac, out_val);
2079 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
2080
2081 if (ctx->ac.chip_class >= GFX9) {
2082 LLVMValueRef dw_addr_offset =
2083 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2084 LLVMConstInt(ctx->ac.i32,
2085 j, false), "");
2086
2087 ac_lds_store(&ctx->ac, dw_addr_offset, out_val);
2088 } else {
2089 ac_build_buffer_store_dword(&ctx->ac,
2090 ctx->esgs_ring,
2091 out_val, 1,
2092 NULL,
2093 ac_get_arg(&ctx->ac, ctx->args->es2gs_offset),
2094 (4 * param_index + j) * 4,
2095 ac_glc | ac_slc | ac_swizzled);
2096 }
2097 }
2098 }
2099 }
2100
2101 static void
2102 handle_ls_outputs_post(struct radv_shader_context *ctx)
2103 {
2104 LLVMValueRef vertex_id = ctx->rel_auto_id;
2105 uint32_t num_tcs_inputs = util_last_bit64(ctx->args->shader_info->vs.ls_outputs_written);
2106 LLVMValueRef vertex_dw_stride = LLVMConstInt(ctx->ac.i32, num_tcs_inputs * 4, false);
2107 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
2108 vertex_dw_stride, "");
2109
2110 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2111 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2112
2113 if (!(ctx->output_mask & (1ull << i)))
2114 continue;
2115
2116 int param = shader_io_get_unique_index(i);
2117 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
2118 LLVMConstInt(ctx->ac.i32, param * 4, false),
2119 "");
2120 for (unsigned j = 0; j < 4; j++) {
2121 LLVMValueRef value = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2122 value = ac_to_integer(&ctx->ac, value);
2123 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
2124 ac_lds_store(&ctx->ac, dw_addr, value);
2125 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2126 }
2127 }
2128 }
2129
2130 static LLVMValueRef get_wave_id_in_tg(struct radv_shader_context *ctx)
2131 {
2132 return ac_unpack_param(&ctx->ac,
2133 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 24, 4);
2134 }
2135
2136 static LLVMValueRef get_tgsize(struct radv_shader_context *ctx)
2137 {
2138 return ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 28, 4);
2139 }
2140
2141 static LLVMValueRef get_thread_id_in_tg(struct radv_shader_context *ctx)
2142 {
2143 LLVMBuilderRef builder = ctx->ac.builder;
2144 LLVMValueRef tmp;
2145 tmp = LLVMBuildMul(builder, get_wave_id_in_tg(ctx),
2146 LLVMConstInt(ctx->ac.i32, ctx->ac.wave_size, false), "");
2147 return LLVMBuildAdd(builder, tmp, ac_get_thread_id(&ctx->ac), "");
2148 }
2149
2150 static LLVMValueRef ngg_get_vtx_cnt(struct radv_shader_context *ctx)
2151 {
2152 return ac_build_bfe(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_tg_info),
2153 LLVMConstInt(ctx->ac.i32, 12, false),
2154 LLVMConstInt(ctx->ac.i32, 9, false),
2155 false);
2156 }
2157
2158 static LLVMValueRef ngg_get_prim_cnt(struct radv_shader_context *ctx)
2159 {
2160 return ac_build_bfe(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_tg_info),
2161 LLVMConstInt(ctx->ac.i32, 22, false),
2162 LLVMConstInt(ctx->ac.i32, 9, false),
2163 false);
2164 }
2165
2166 static LLVMValueRef ngg_get_ordered_id(struct radv_shader_context *ctx)
2167 {
2168 return ac_build_bfe(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_tg_info),
2169 ctx->ac.i32_0,
2170 LLVMConstInt(ctx->ac.i32, 12, false),
2171 false);
2172 }
2173
2174 static LLVMValueRef
2175 ngg_gs_get_vertex_storage(struct radv_shader_context *ctx)
2176 {
2177 unsigned num_outputs = util_bitcount64(ctx->output_mask);
2178
2179 if (ctx->args->options->key.has_multiview_view_index)
2180 num_outputs++;
2181
2182 LLVMTypeRef elements[2] = {
2183 LLVMArrayType(ctx->ac.i32, 4 * num_outputs),
2184 LLVMArrayType(ctx->ac.i8, 4),
2185 };
2186 LLVMTypeRef type = LLVMStructTypeInContext(ctx->ac.context, elements, 2, false);
2187 type = LLVMPointerType(LLVMArrayType(type, 0), AC_ADDR_SPACE_LDS);
2188 return LLVMBuildBitCast(ctx->ac.builder, ctx->gs_ngg_emit, type, "");
2189 }
2190
2191 /**
2192 * Return a pointer to the LDS storage reserved for the N'th vertex, where N
2193 * is in emit order; that is:
2194 * - during the epilogue, N is the threadidx (relative to the entire threadgroup)
2195 * - during vertex emit, i.e. while the API GS shader invocation is running,
2196 * N = threadidx * gs_max_out_vertices + emitidx
2197 *
2198 * Goals of the LDS memory layout:
2199 * 1. Eliminate bank conflicts on write for geometry shaders that have all emits
2200 * in uniform control flow
2201 * 2. Eliminate bank conflicts on read for export if, additionally, there is no
2202 * culling
2203 * 3. Agnostic to the number of waves (since we don't know it before compiling)
2204 * 4. Allow coalescing of LDS instructions (ds_write_b128 etc.)
2205 * 5. Avoid wasting memory.
2206 *
2207 * We use an AoS layout due to point 4 (this also helps point 3). In an AoS
2208 * layout, elimination of bank conflicts requires that each vertex occupy an
2209 * odd number of dwords. We use the additional dword to store the output stream
2210 * index as well as a flag to indicate whether this vertex ends a primitive
2211 * for rasterization.
2212 *
2213 * Swizzling is required to satisfy points 1 and 2 simultaneously.
2214 *
2215 * Vertices are stored in export order (gsthread * gs_max_out_vertices + emitidx).
2216 * Indices are swizzled in groups of 32, which ensures point 1 without
2217 * disturbing point 2.
2218 *
2219 * \return an LDS pointer to type {[N x i32], [4 x i8]}
2220 */
2221 static LLVMValueRef
2222 ngg_gs_vertex_ptr(struct radv_shader_context *ctx, LLVMValueRef vertexidx)
2223 {
2224 LLVMBuilderRef builder = ctx->ac.builder;
2225 LLVMValueRef storage = ngg_gs_get_vertex_storage(ctx);
2226
2227 /* gs_max_out_vertices = 2^(write_stride_2exp) * some odd number */
2228 unsigned write_stride_2exp = ffs(ctx->shader->info.gs.vertices_out) - 1;
2229 if (write_stride_2exp) {
2230 LLVMValueRef row =
2231 LLVMBuildLShr(builder, vertexidx,
2232 LLVMConstInt(ctx->ac.i32, 5, false), "");
2233 LLVMValueRef swizzle =
2234 LLVMBuildAnd(builder, row,
2235 LLVMConstInt(ctx->ac.i32, (1u << write_stride_2exp) - 1,
2236 false), "");
2237 vertexidx = LLVMBuildXor(builder, vertexidx, swizzle, "");
2238 }
2239
2240 return ac_build_gep0(&ctx->ac, storage, vertexidx);
2241 }
2242
2243 static LLVMValueRef
2244 ngg_gs_emit_vertex_ptr(struct radv_shader_context *ctx, LLVMValueRef gsthread,
2245 LLVMValueRef emitidx)
2246 {
2247 LLVMBuilderRef builder = ctx->ac.builder;
2248 LLVMValueRef tmp;
2249
2250 tmp = LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false);
2251 tmp = LLVMBuildMul(builder, tmp, gsthread, "");
2252 const LLVMValueRef vertexidx = LLVMBuildAdd(builder, tmp, emitidx, "");
2253 return ngg_gs_vertex_ptr(ctx, vertexidx);
2254 }
2255
2256 static LLVMValueRef
2257 ngg_gs_get_emit_output_ptr(struct radv_shader_context *ctx, LLVMValueRef vertexptr,
2258 unsigned out_idx)
2259 {
2260 LLVMValueRef gep_idx[3] = {
2261 ctx->ac.i32_0, /* implied C-style array */
2262 ctx->ac.i32_0, /* first struct entry */
2263 LLVMConstInt(ctx->ac.i32, out_idx, false),
2264 };
2265 return LLVMBuildGEP(ctx->ac.builder, vertexptr, gep_idx, 3, "");
2266 }
2267
2268 static LLVMValueRef
2269 ngg_gs_get_emit_primflag_ptr(struct radv_shader_context *ctx, LLVMValueRef vertexptr,
2270 unsigned stream)
2271 {
2272 LLVMValueRef gep_idx[3] = {
2273 ctx->ac.i32_0, /* implied C-style array */
2274 ctx->ac.i32_1, /* second struct entry */
2275 LLVMConstInt(ctx->ac.i32, stream, false),
2276 };
2277 return LLVMBuildGEP(ctx->ac.builder, vertexptr, gep_idx, 3, "");
2278 }
2279
2280 static struct radv_stream_output *
2281 radv_get_stream_output_by_loc(struct radv_streamout_info *so, unsigned location)
2282 {
2283 for (unsigned i = 0; i < so->num_outputs; ++i) {
2284 if (so->outputs[i].location == location)
2285 return &so->outputs[i];
2286 }
2287
2288 return NULL;
2289 }
2290
2291 static void build_streamout_vertex(struct radv_shader_context *ctx,
2292 LLVMValueRef *so_buffer, LLVMValueRef *wg_offset_dw,
2293 unsigned stream, LLVMValueRef offset_vtx,
2294 LLVMValueRef vertexptr)
2295 {
2296 struct radv_streamout_info *so = &ctx->args->shader_info->so;
2297 LLVMBuilderRef builder = ctx->ac.builder;
2298 LLVMValueRef offset[4] = {};
2299 LLVMValueRef tmp;
2300
2301 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2302 if (!wg_offset_dw[buffer])
2303 continue;
2304
2305 tmp = LLVMBuildMul(builder, offset_vtx,
2306 LLVMConstInt(ctx->ac.i32, so->strides[buffer], false), "");
2307 tmp = LLVMBuildAdd(builder, wg_offset_dw[buffer], tmp, "");
2308 offset[buffer] = LLVMBuildShl(builder, tmp, LLVMConstInt(ctx->ac.i32, 2, false), "");
2309 }
2310
2311 if (ctx->stage == MESA_SHADER_GEOMETRY) {
2312 struct radv_shader_output_values outputs[AC_LLVM_MAX_OUTPUTS];
2313 unsigned noutput = 0;
2314 unsigned out_idx = 0;
2315
2316 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2317 unsigned output_usage_mask =
2318 ctx->args->shader_info->gs.output_usage_mask[i];
2319 uint8_t output_stream = ctx->args->shader_info->gs.output_streams[i];
2320
2321 if (!(ctx->output_mask & (1ull << i)) ||
2322 output_stream != stream)
2323 continue;
2324
2325 outputs[noutput].slot_name = i;
2326 outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
2327 outputs[noutput].usage_mask = output_usage_mask;
2328
2329 int length = util_last_bit(output_usage_mask);
2330
2331 for (unsigned j = 0; j < length; j++, out_idx++) {
2332 if (!(output_usage_mask & (1 << j)))
2333 continue;
2334
2335 tmp = ac_build_gep0(&ctx->ac, vertexptr,
2336 LLVMConstInt(ctx->ac.i32, out_idx, false));
2337 outputs[noutput].values[j] = LLVMBuildLoad(builder, tmp, "");
2338 }
2339
2340 for (unsigned j = length; j < 4; j++)
2341 outputs[noutput].values[j] = LLVMGetUndef(ctx->ac.f32);
2342
2343 noutput++;
2344 }
2345
2346 for (unsigned i = 0; i < noutput; i++) {
2347 struct radv_stream_output *output =
2348 radv_get_stream_output_by_loc(so, outputs[i].slot_name);
2349
2350 if (!output ||
2351 output->stream != stream)
2352 continue;
2353
2354 struct radv_shader_output_values out = {};
2355
2356 for (unsigned j = 0; j < 4; j++) {
2357 out.values[j] = outputs[i].values[j];
2358 }
2359
2360 radv_emit_stream_output(ctx, so_buffer, offset, output, &out);
2361 }
2362 } else {
2363 for (unsigned i = 0; i < so->num_outputs; ++i) {
2364 struct radv_stream_output *output =
2365 &ctx->args->shader_info->so.outputs[i];
2366
2367 if (stream != output->stream)
2368 continue;
2369
2370 struct radv_shader_output_values out = {};
2371
2372 for (unsigned comp = 0; comp < 4; comp++) {
2373 if (!(output->component_mask & (1 << comp)))
2374 continue;
2375
2376 tmp = ac_build_gep0(&ctx->ac, vertexptr,
2377 LLVMConstInt(ctx->ac.i32, 4 * i + comp, false));
2378 out.values[comp] = LLVMBuildLoad(builder, tmp, "");
2379 }
2380
2381 radv_emit_stream_output(ctx, so_buffer, offset, output, &out);
2382 }
2383 }
2384 }
2385
2386 struct ngg_streamout {
2387 LLVMValueRef num_vertices;
2388
2389 /* per-thread data */
2390 LLVMValueRef prim_enable[4]; /* i1 per stream */
2391 LLVMValueRef vertices[3]; /* [N x i32] addrspace(LDS)* */
2392
2393 /* Output */
2394 LLVMValueRef emit[4]; /* per-stream emitted primitives (only valid for used streams) */
2395 };
2396
2397 /**
2398 * Build streamout logic.
2399 *
2400 * Implies a barrier.
2401 *
2402 * Writes number of emitted primitives to gs_ngg_scratch[4:7].
2403 *
2404 * Clobbers gs_ngg_scratch[8:].
2405 */
2406 static void build_streamout(struct radv_shader_context *ctx,
2407 struct ngg_streamout *nggso)
2408 {
2409 struct radv_streamout_info *so = &ctx->args->shader_info->so;
2410 LLVMBuilderRef builder = ctx->ac.builder;
2411 LLVMValueRef buf_ptr = ac_get_arg(&ctx->ac, ctx->args->streamout_buffers);
2412 LLVMValueRef tid = get_thread_id_in_tg(ctx);
2413 LLVMValueRef cond, tmp, tmp2;
2414 LLVMValueRef i32_2 = LLVMConstInt(ctx->ac.i32, 2, false);
2415 LLVMValueRef i32_4 = LLVMConstInt(ctx->ac.i32, 4, false);
2416 LLVMValueRef i32_8 = LLVMConstInt(ctx->ac.i32, 8, false);
2417 LLVMValueRef so_buffer[4] = {};
2418 unsigned max_num_vertices = 1 + (nggso->vertices[1] ? 1 : 0) +
2419 (nggso->vertices[2] ? 1 : 0);
2420 LLVMValueRef prim_stride_dw[4] = {};
2421 LLVMValueRef prim_stride_dw_vgpr = LLVMGetUndef(ctx->ac.i32);
2422 int stream_for_buffer[4] = { -1, -1, -1, -1 };
2423 unsigned bufmask_for_stream[4] = {};
2424 bool isgs = ctx->stage == MESA_SHADER_GEOMETRY;
2425 unsigned scratch_emit_base = isgs ? 4 : 0;
2426 LLVMValueRef scratch_emit_basev = isgs ? i32_4 : ctx->ac.i32_0;
2427 unsigned scratch_offset_base = isgs ? 8 : 4;
2428 LLVMValueRef scratch_offset_basev = isgs ? i32_8 : i32_4;
2429
2430 ac_llvm_add_target_dep_function_attr(ctx->main_function,
2431 "amdgpu-gds-size", 256);
2432
2433 /* Determine the mapping of streamout buffers to vertex streams. */
2434 for (unsigned i = 0; i < so->num_outputs; ++i) {
2435 unsigned buf = so->outputs[i].buffer;
2436 unsigned stream = so->outputs[i].stream;
2437 assert(stream_for_buffer[buf] < 0 || stream_for_buffer[buf] == stream);
2438 stream_for_buffer[buf] = stream;
2439 bufmask_for_stream[stream] |= 1 << buf;
2440 }
2441
2442 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2443 if (stream_for_buffer[buffer] == -1)
2444 continue;
2445
2446 assert(so->strides[buffer]);
2447
2448 LLVMValueRef stride_for_buffer =
2449 LLVMConstInt(ctx->ac.i32, so->strides[buffer], false);
2450 prim_stride_dw[buffer] =
2451 LLVMBuildMul(builder, stride_for_buffer,
2452 nggso->num_vertices, "");
2453 prim_stride_dw_vgpr = ac_build_writelane(
2454 &ctx->ac, prim_stride_dw_vgpr, prim_stride_dw[buffer],
2455 LLVMConstInt(ctx->ac.i32, buffer, false));
2456
2457 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, buffer, false);
2458 so_buffer[buffer] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr,
2459 offset);
2460 }
2461
2462 cond = LLVMBuildICmp(builder, LLVMIntEQ, get_wave_id_in_tg(ctx), ctx->ac.i32_0, "");
2463 ac_build_ifcc(&ctx->ac, cond, 5200);
2464 {
2465 LLVMTypeRef gdsptr = LLVMPointerType(ctx->ac.i32, AC_ADDR_SPACE_GDS);
2466 LLVMValueRef gdsbase = LLVMBuildIntToPtr(builder, ctx->ac.i32_0, gdsptr, "");
2467
2468 /* Advance the streamout offsets in GDS. */
2469 LLVMValueRef offsets_vgpr = ac_build_alloca_undef(&ctx->ac, ctx->ac.i32, "");
2470 LLVMValueRef generated_by_stream_vgpr = ac_build_alloca_undef(&ctx->ac, ctx->ac.i32, "");
2471
2472 cond = LLVMBuildICmp(builder, LLVMIntULT, ac_get_thread_id(&ctx->ac), i32_4, "");
2473 ac_build_ifcc(&ctx->ac, cond, 5210);
2474 {
2475 /* Fetch the number of generated primitives and store
2476 * it in GDS for later use.
2477 */
2478 if (isgs) {
2479 tmp = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tid);
2480 tmp = LLVMBuildLoad(builder, tmp, "");
2481 } else {
2482 tmp = ac_build_writelane(&ctx->ac, ctx->ac.i32_0,
2483 ngg_get_prim_cnt(ctx), ctx->ac.i32_0);
2484 }
2485 LLVMBuildStore(builder, tmp, generated_by_stream_vgpr);
2486
2487 unsigned swizzle[4];
2488 int unused_stream = -1;
2489 for (unsigned stream = 0; stream < 4; ++stream) {
2490 if (!ctx->args->shader_info->gs.num_stream_output_components[stream]) {
2491 unused_stream = stream;
2492 break;
2493 }
2494 }
2495 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2496 if (stream_for_buffer[buffer] >= 0) {
2497 swizzle[buffer] = stream_for_buffer[buffer];
2498 } else {
2499 assert(unused_stream >= 0);
2500 swizzle[buffer] = unused_stream;
2501 }
2502 }
2503
2504 tmp = ac_build_quad_swizzle(&ctx->ac, tmp,
2505 swizzle[0], swizzle[1], swizzle[2], swizzle[3]);
2506 tmp = LLVMBuildMul(builder, tmp, prim_stride_dw_vgpr, "");
2507
2508 LLVMValueRef args[] = {
2509 LLVMBuildIntToPtr(builder, ngg_get_ordered_id(ctx), gdsptr, ""),
2510 tmp,
2511 ctx->ac.i32_0, // ordering
2512 ctx->ac.i32_0, // scope
2513 ctx->ac.i1false, // isVolatile
2514 LLVMConstInt(ctx->ac.i32, 4 << 24, false), // OA index
2515 ctx->ac.i1true, // wave release
2516 ctx->ac.i1true, // wave done
2517 };
2518
2519 tmp = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.ds.ordered.add",
2520 ctx->ac.i32, args, ARRAY_SIZE(args), 0);
2521
2522 /* Keep offsets in a VGPR for quick retrieval via readlane by
2523 * the first wave for bounds checking, and also store in LDS
2524 * for retrieval by all waves later. */
2525 LLVMBuildStore(builder, tmp, offsets_vgpr);
2526
2527 tmp2 = LLVMBuildAdd(builder, ac_get_thread_id(&ctx->ac),
2528 scratch_offset_basev, "");
2529 tmp2 = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tmp2);
2530 LLVMBuildStore(builder, tmp, tmp2);
2531 }
2532 ac_build_endif(&ctx->ac, 5210);
2533
2534 /* Determine the max emit per buffer. This is done via the SALU, in part
2535 * because LLVM can't generate divide-by-multiply if we try to do this
2536 * via VALU with one lane per buffer.
2537 */
2538 LLVMValueRef max_emit[4] = {};
2539 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2540 if (stream_for_buffer[buffer] == -1)
2541 continue;
2542
2543 /* Compute the streamout buffer size in DWORD. */
2544 LLVMValueRef bufsize_dw =
2545 LLVMBuildLShr(builder,
2546 LLVMBuildExtractElement(builder, so_buffer[buffer], i32_2, ""),
2547 i32_2, "");
2548
2549 /* Load the streamout buffer offset from GDS. */
2550 tmp = LLVMBuildLoad(builder, offsets_vgpr, "");
2551 LLVMValueRef offset_dw =
2552 ac_build_readlane(&ctx->ac, tmp,
2553 LLVMConstInt(ctx->ac.i32, buffer, false));
2554
2555 /* Compute the remaining size to emit. */
2556 LLVMValueRef remaining_dw =
2557 LLVMBuildSub(builder, bufsize_dw, offset_dw, "");
2558 tmp = LLVMBuildUDiv(builder, remaining_dw,
2559 prim_stride_dw[buffer], "");
2560
2561 cond = LLVMBuildICmp(builder, LLVMIntULT,
2562 bufsize_dw, offset_dw, "");
2563 max_emit[buffer] = LLVMBuildSelect(builder, cond,
2564 ctx->ac.i32_0, tmp, "");
2565 }
2566
2567 /* Determine the number of emitted primitives per stream and fixup the
2568 * GDS counter if necessary.
2569 *
2570 * This is complicated by the fact that a single stream can emit to
2571 * multiple buffers (but luckily not vice versa).
2572 */
2573 LLVMValueRef emit_vgpr = ctx->ac.i32_0;
2574
2575 for (unsigned stream = 0; stream < 4; ++stream) {
2576 if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
2577 continue;
2578
2579 /* Load the number of generated primitives from GDS and
2580 * determine that number for the given stream.
2581 */
2582 tmp = LLVMBuildLoad(builder, generated_by_stream_vgpr, "");
2583 LLVMValueRef generated =
2584 ac_build_readlane(&ctx->ac, tmp,
2585 LLVMConstInt(ctx->ac.i32, stream, false));
2586
2587
2588 /* Compute the number of emitted primitives. */
2589 LLVMValueRef emit = generated;
2590 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2591 if (stream_for_buffer[buffer] == stream)
2592 emit = ac_build_umin(&ctx->ac, emit, max_emit[buffer]);
2593 }
2594
2595 /* Store the number of emitted primitives for that
2596 * stream.
2597 */
2598 emit_vgpr = ac_build_writelane(&ctx->ac, emit_vgpr, emit,
2599 LLVMConstInt(ctx->ac.i32, stream, false));
2600
2601 /* Fixup the offset using a plain GDS atomic if we overflowed. */
2602 cond = LLVMBuildICmp(builder, LLVMIntULT, emit, generated, "");
2603 ac_build_ifcc(&ctx->ac, cond, 5221); /* scalar branch */
2604 tmp = LLVMBuildLShr(builder,
2605 LLVMConstInt(ctx->ac.i32, bufmask_for_stream[stream], false),
2606 ac_get_thread_id(&ctx->ac), "");
2607 tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
2608 ac_build_ifcc(&ctx->ac, tmp, 5222);
2609 {
2610 tmp = LLVMBuildSub(builder, generated, emit, "");
2611 tmp = LLVMBuildMul(builder, tmp, prim_stride_dw_vgpr, "");
2612 tmp2 = LLVMBuildGEP(builder, gdsbase, &tid, 1, "");
2613 LLVMBuildAtomicRMW(builder, LLVMAtomicRMWBinOpSub, tmp2, tmp,
2614 LLVMAtomicOrderingMonotonic, false);
2615 }
2616 ac_build_endif(&ctx->ac, 5222);
2617 ac_build_endif(&ctx->ac, 5221);
2618 }
2619
2620 /* Store the number of emitted primitives to LDS for later use. */
2621 cond = LLVMBuildICmp(builder, LLVMIntULT, ac_get_thread_id(&ctx->ac), i32_4, "");
2622 ac_build_ifcc(&ctx->ac, cond, 5225);
2623 {
2624 tmp = LLVMBuildAdd(builder, ac_get_thread_id(&ctx->ac),
2625 scratch_emit_basev, "");
2626 tmp = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tmp);
2627 LLVMBuildStore(builder, emit_vgpr, tmp);
2628 }
2629 ac_build_endif(&ctx->ac, 5225);
2630 }
2631 ac_build_endif(&ctx->ac, 5200);
2632
2633 /* Determine the workgroup-relative per-thread / primitive offset into
2634 * the streamout buffers */
2635 struct ac_wg_scan primemit_scan[4] = {};
2636
2637 if (isgs) {
2638 for (unsigned stream = 0; stream < 4; ++stream) {
2639 if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
2640 continue;
2641
2642 primemit_scan[stream].enable_exclusive = true;
2643 primemit_scan[stream].op = nir_op_iadd;
2644 primemit_scan[stream].src = nggso->prim_enable[stream];
2645 primemit_scan[stream].scratch =
2646 ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch,
2647 LLVMConstInt(ctx->ac.i32, 12 + 8 * stream, false));
2648 primemit_scan[stream].waveidx = get_wave_id_in_tg(ctx);
2649 primemit_scan[stream].numwaves = get_tgsize(ctx);
2650 primemit_scan[stream].maxwaves = 8;
2651 ac_build_wg_scan_top(&ctx->ac, &primemit_scan[stream]);
2652 }
2653 }
2654
2655 ac_build_s_barrier(&ctx->ac);
2656
2657 /* Fetch the per-buffer offsets and per-stream emit counts in all waves. */
2658 LLVMValueRef wgoffset_dw[4] = {};
2659
2660 {
2661 LLVMValueRef scratch_vgpr;
2662
2663 tmp = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, ac_get_thread_id(&ctx->ac));
2664 scratch_vgpr = LLVMBuildLoad(builder, tmp, "");
2665
2666 for (unsigned buffer = 0; buffer < 4; ++buffer) {
2667 if (stream_for_buffer[buffer] >= 0) {
2668 wgoffset_dw[buffer] = ac_build_readlane(
2669 &ctx->ac, scratch_vgpr,
2670 LLVMConstInt(ctx->ac.i32, scratch_offset_base + buffer, false));
2671 }
2672 }
2673
2674 for (unsigned stream = 0; stream < 4; ++stream) {
2675 if (ctx->args->shader_info->gs.num_stream_output_components[stream]) {
2676 nggso->emit[stream] = ac_build_readlane(
2677 &ctx->ac, scratch_vgpr,
2678 LLVMConstInt(ctx->ac.i32, scratch_emit_base + stream, false));
2679 }
2680 }
2681 }
2682
2683 /* Write out primitive data */
2684 for (unsigned stream = 0; stream < 4; ++stream) {
2685 if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
2686 continue;
2687
2688 if (isgs) {
2689 ac_build_wg_scan_bottom(&ctx->ac, &primemit_scan[stream]);
2690 } else {
2691 primemit_scan[stream].result_exclusive = tid;
2692 }
2693
2694 cond = LLVMBuildICmp(builder, LLVMIntULT,
2695 primemit_scan[stream].result_exclusive,
2696 nggso->emit[stream], "");
2697 cond = LLVMBuildAnd(builder, cond, nggso->prim_enable[stream], "");
2698 ac_build_ifcc(&ctx->ac, cond, 5240);
2699 {
2700 LLVMValueRef offset_vtx =
2701 LLVMBuildMul(builder, primemit_scan[stream].result_exclusive,
2702 nggso->num_vertices, "");
2703
2704 for (unsigned i = 0; i < max_num_vertices; ++i) {
2705 cond = LLVMBuildICmp(builder, LLVMIntULT,
2706 LLVMConstInt(ctx->ac.i32, i, false),
2707 nggso->num_vertices, "");
2708 ac_build_ifcc(&ctx->ac, cond, 5241);
2709 build_streamout_vertex(ctx, so_buffer, wgoffset_dw,
2710 stream, offset_vtx, nggso->vertices[i]);
2711 ac_build_endif(&ctx->ac, 5241);
2712 offset_vtx = LLVMBuildAdd(builder, offset_vtx, ctx->ac.i32_1, "");
2713 }
2714 }
2715 ac_build_endif(&ctx->ac, 5240);
2716 }
2717 }
2718
2719 static unsigned ngg_nogs_vertex_size(struct radv_shader_context *ctx)
2720 {
2721 unsigned lds_vertex_size = 0;
2722
2723 if (ctx->args->shader_info->so.num_outputs)
2724 lds_vertex_size = 4 * ctx->args->shader_info->so.num_outputs + 1;
2725
2726 return lds_vertex_size;
2727 }
2728
2729 /**
2730 * Returns an `[N x i32] addrspace(LDS)*` pointing at contiguous LDS storage
2731 * for the vertex outputs.
2732 */
2733 static LLVMValueRef ngg_nogs_vertex_ptr(struct radv_shader_context *ctx,
2734 LLVMValueRef vtxid)
2735 {
2736 /* The extra dword is used to avoid LDS bank conflicts. */
2737 unsigned vertex_size = ngg_nogs_vertex_size(ctx);
2738 LLVMTypeRef ai32 = LLVMArrayType(ctx->ac.i32, vertex_size);
2739 LLVMTypeRef pai32 = LLVMPointerType(ai32, AC_ADDR_SPACE_LDS);
2740 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, ctx->esgs_ring, pai32, "");
2741 return LLVMBuildGEP(ctx->ac.builder, tmp, &vtxid, 1, "");
2742 }
2743
2744 static void
2745 handle_ngg_outputs_post_1(struct radv_shader_context *ctx)
2746 {
2747 struct radv_streamout_info *so = &ctx->args->shader_info->so;
2748 LLVMBuilderRef builder = ctx->ac.builder;
2749 LLVMValueRef vertex_ptr = NULL;
2750 LLVMValueRef tmp, tmp2;
2751
2752 assert((ctx->stage == MESA_SHADER_VERTEX ||
2753 ctx->stage == MESA_SHADER_TESS_EVAL) && !ctx->args->is_gs_copy_shader);
2754
2755 if (!ctx->args->shader_info->so.num_outputs)
2756 return;
2757
2758 vertex_ptr = ngg_nogs_vertex_ptr(ctx, get_thread_id_in_tg(ctx));
2759
2760 for (unsigned i = 0; i < so->num_outputs; ++i) {
2761 struct radv_stream_output *output =
2762 &ctx->args->shader_info->so.outputs[i];
2763
2764 unsigned loc = output->location;
2765
2766 for (unsigned comp = 0; comp < 4; comp++) {
2767 if (!(output->component_mask & (1 << comp)))
2768 continue;
2769
2770 tmp = ac_build_gep0(&ctx->ac, vertex_ptr,
2771 LLVMConstInt(ctx->ac.i32, 4 * i + comp, false));
2772 tmp2 = LLVMBuildLoad(builder,
2773 ctx->abi.outputs[4 * loc + comp], "");
2774 tmp2 = ac_to_integer(&ctx->ac, tmp2);
2775 LLVMBuildStore(builder, tmp2, tmp);
2776 }
2777 }
2778 }
2779
2780 static void
2781 handle_ngg_outputs_post_2(struct radv_shader_context *ctx)
2782 {
2783 LLVMBuilderRef builder = ctx->ac.builder;
2784 LLVMValueRef tmp;
2785
2786 assert((ctx->stage == MESA_SHADER_VERTEX ||
2787 ctx->stage == MESA_SHADER_TESS_EVAL) && !ctx->args->is_gs_copy_shader);
2788
2789 LLVMValueRef prims_in_wave = ac_unpack_param(&ctx->ac,
2790 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 8, 8);
2791 LLVMValueRef vtx_in_wave = ac_unpack_param(&ctx->ac,
2792 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 0, 8);
2793 LLVMValueRef is_gs_thread = LLVMBuildICmp(builder, LLVMIntULT,
2794 ac_get_thread_id(&ctx->ac), prims_in_wave, "");
2795 LLVMValueRef is_es_thread = LLVMBuildICmp(builder, LLVMIntULT,
2796 ac_get_thread_id(&ctx->ac), vtx_in_wave, "");
2797 LLVMValueRef vtxindex[] = {
2798 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[0]), 0, 16),
2799 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[0]), 16, 16),
2800 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[2]), 0, 16),
2801 };
2802
2803 /* Determine the number of vertices per primitive. */
2804 unsigned num_vertices;
2805 LLVMValueRef num_vertices_val;
2806
2807 if (ctx->stage == MESA_SHADER_VERTEX) {
2808 LLVMValueRef outprim_val =
2809 LLVMConstInt(ctx->ac.i32,
2810 ctx->args->options->key.vs.outprim, false);
2811 num_vertices_val = LLVMBuildAdd(builder, outprim_val,
2812 ctx->ac.i32_1, "");
2813 num_vertices = 3; /* TODO: optimize for points & lines */
2814 } else {
2815 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2816
2817 if (ctx->shader->info.tess.point_mode)
2818 num_vertices = 1;
2819 else if (ctx->shader->info.tess.primitive_mode == GL_ISOLINES)
2820 num_vertices = 2;
2821 else
2822 num_vertices = 3;
2823
2824 num_vertices_val = LLVMConstInt(ctx->ac.i32, num_vertices, false);
2825 }
2826
2827 /* Streamout */
2828 if (ctx->args->shader_info->so.num_outputs) {
2829 struct ngg_streamout nggso = {};
2830
2831 nggso.num_vertices = num_vertices_val;
2832 nggso.prim_enable[0] = is_gs_thread;
2833
2834 for (unsigned i = 0; i < num_vertices; ++i)
2835 nggso.vertices[i] = ngg_nogs_vertex_ptr(ctx, vtxindex[i]);
2836
2837 build_streamout(ctx, &nggso);
2838 }
2839
2840 /* Copy Primitive IDs from GS threads to the LDS address corresponding
2841 * to the ES thread of the provoking vertex.
2842 */
2843 if (ctx->stage == MESA_SHADER_VERTEX &&
2844 ctx->args->options->key.vs_common_out.export_prim_id) {
2845 if (ctx->args->shader_info->so.num_outputs)
2846 ac_build_s_barrier(&ctx->ac);
2847
2848 ac_build_ifcc(&ctx->ac, is_gs_thread, 5400);
2849 /* Extract the PROVOKING_VTX_INDEX field. */
2850 LLVMValueRef provoking_vtx_in_prim =
2851 LLVMConstInt(ctx->ac.i32, 0, false);
2852
2853 /* provoking_vtx_index = vtxindex[provoking_vtx_in_prim]; */
2854 LLVMValueRef indices = ac_build_gather_values(&ctx->ac, vtxindex, 3);
2855 LLVMValueRef provoking_vtx_index =
2856 LLVMBuildExtractElement(builder, indices, provoking_vtx_in_prim, "");
2857
2858 LLVMBuildStore(builder, ac_get_arg(&ctx->ac, ctx->args->ac.gs_prim_id),
2859 ac_build_gep0(&ctx->ac, ctx->esgs_ring, provoking_vtx_index));
2860 ac_build_endif(&ctx->ac, 5400);
2861 }
2862
2863 /* TODO: primitive culling */
2864
2865 ac_build_sendmsg_gs_alloc_req(&ctx->ac, get_wave_id_in_tg(ctx),
2866 ngg_get_vtx_cnt(ctx), ngg_get_prim_cnt(ctx));
2867
2868 /* TODO: streamout queries */
2869 /* Export primitive data to the index buffer.
2870 *
2871 * For the first version, we will always build up all three indices
2872 * independent of the primitive type. The additional garbage data
2873 * shouldn't hurt.
2874 *
2875 * TODO: culling depends on the primitive type, so can have some
2876 * interaction here.
2877 */
2878 ac_build_ifcc(&ctx->ac, is_gs_thread, 6001);
2879 {
2880 struct ac_ngg_prim prim = {};
2881
2882 if (ctx->args->options->key.vs_common_out.as_ngg_passthrough) {
2883 prim.passthrough = ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[0]);
2884 } else {
2885 prim.num_vertices = num_vertices;
2886 prim.isnull = ctx->ac.i1false;
2887 memcpy(prim.index, vtxindex, sizeof(vtxindex[0]) * 3);
2888
2889 for (unsigned i = 0; i < num_vertices; ++i) {
2890 tmp = LLVMBuildLShr(builder,
2891 ac_get_arg(&ctx->ac, ctx->args->ac.gs_invocation_id),
2892 LLVMConstInt(ctx->ac.i32, 8 + i, false), "");
2893 prim.edgeflag[i] = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
2894 }
2895 }
2896
2897 ac_build_export_prim(&ctx->ac, &prim);
2898 }
2899 ac_build_endif(&ctx->ac, 6001);
2900
2901 /* Export per-vertex data (positions and parameters). */
2902 ac_build_ifcc(&ctx->ac, is_es_thread, 6002);
2903 {
2904 struct radv_vs_output_info *outinfo =
2905 ctx->stage == MESA_SHADER_TESS_EVAL ?
2906 &ctx->args->shader_info->tes.outinfo : &ctx->args->shader_info->vs.outinfo;
2907
2908 /* Exporting the primitive ID is handled below. */
2909 /* TODO: use the new VS export path */
2910 handle_vs_outputs_post(ctx, false,
2911 ctx->args->options->key.vs_common_out.export_clip_dists,
2912 outinfo);
2913
2914 if (ctx->args->options->key.vs_common_out.export_prim_id) {
2915 unsigned param_count = outinfo->param_exports;
2916 LLVMValueRef values[4];
2917
2918 if (ctx->stage == MESA_SHADER_VERTEX) {
2919 /* Wait for GS stores to finish. */
2920 ac_build_s_barrier(&ctx->ac);
2921
2922 tmp = ac_build_gep0(&ctx->ac, ctx->esgs_ring,
2923 get_thread_id_in_tg(ctx));
2924 values[0] = LLVMBuildLoad(builder, tmp, "");
2925 } else {
2926 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2927 values[0] = ac_get_arg(&ctx->ac, ctx->args->ac.tes_patch_id);
2928 }
2929
2930 values[0] = ac_to_float(&ctx->ac, values[0]);
2931 for (unsigned j = 1; j < 4; j++)
2932 values[j] = ctx->ac.f32_0;
2933
2934 radv_export_param(ctx, param_count, values, 0x1);
2935
2936 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
2937 outinfo->param_exports = param_count;
2938 }
2939 }
2940 ac_build_endif(&ctx->ac, 6002);
2941 }
2942
2943 static void gfx10_ngg_gs_emit_prologue(struct radv_shader_context *ctx)
2944 {
2945 /* Zero out the part of LDS scratch that is used to accumulate the
2946 * per-stream generated primitive count.
2947 */
2948 LLVMBuilderRef builder = ctx->ac.builder;
2949 LLVMValueRef scratchptr = ctx->gs_ngg_scratch;
2950 LLVMValueRef tid = get_thread_id_in_tg(ctx);
2951 LLVMBasicBlockRef merge_block;
2952 LLVMValueRef cond;
2953
2954 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
2955 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
2956 merge_block = LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
2957
2958 cond = LLVMBuildICmp(builder, LLVMIntULT, tid, LLVMConstInt(ctx->ac.i32, 4, false), "");
2959 LLVMBuildCondBr(ctx->ac.builder, cond, then_block, merge_block);
2960 LLVMPositionBuilderAtEnd(ctx->ac.builder, then_block);
2961
2962 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, scratchptr, tid);
2963 LLVMBuildStore(builder, ctx->ac.i32_0, ptr);
2964
2965 LLVMBuildBr(ctx->ac.builder, merge_block);
2966 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
2967
2968 ac_build_s_barrier(&ctx->ac);
2969 }
2970
2971 static void gfx10_ngg_gs_emit_epilogue_1(struct radv_shader_context *ctx)
2972 {
2973 LLVMBuilderRef builder = ctx->ac.builder;
2974 LLVMValueRef i8_0 = LLVMConstInt(ctx->ac.i8, 0, false);
2975 LLVMValueRef tmp;
2976
2977 /* Zero out remaining (non-emitted) primitive flags.
2978 *
2979 * Note: Alternatively, we could pass the relevant gs_next_vertex to
2980 * the emit threads via LDS. This is likely worse in the expected
2981 * typical case where each GS thread emits the full set of
2982 * vertices.
2983 */
2984 for (unsigned stream = 0; stream < 4; ++stream) {
2985 unsigned num_components;
2986
2987 num_components =
2988 ctx->args->shader_info->gs.num_stream_output_components[stream];
2989 if (!num_components)
2990 continue;
2991
2992 const LLVMValueRef gsthread = get_thread_id_in_tg(ctx);
2993
2994 ac_build_bgnloop(&ctx->ac, 5100);
2995
2996 const LLVMValueRef vertexidx =
2997 LLVMBuildLoad(builder, ctx->gs_next_vertex[stream], "");
2998 tmp = LLVMBuildICmp(builder, LLVMIntUGE, vertexidx,
2999 LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false), "");
3000 ac_build_ifcc(&ctx->ac, tmp, 5101);
3001 ac_build_break(&ctx->ac);
3002 ac_build_endif(&ctx->ac, 5101);
3003
3004 tmp = LLVMBuildAdd(builder, vertexidx, ctx->ac.i32_1, "");
3005 LLVMBuildStore(builder, tmp, ctx->gs_next_vertex[stream]);
3006
3007 tmp = ngg_gs_emit_vertex_ptr(ctx, gsthread, vertexidx);
3008 LLVMBuildStore(builder, i8_0,
3009 ngg_gs_get_emit_primflag_ptr(ctx, tmp, stream));
3010
3011 ac_build_endloop(&ctx->ac, 5100);
3012 }
3013
3014 /* Accumulate generated primitives counts across the entire threadgroup. */
3015 for (unsigned stream = 0; stream < 4; ++stream) {
3016 unsigned num_components;
3017
3018 num_components =
3019 ctx->args->shader_info->gs.num_stream_output_components[stream];
3020 if (!num_components)
3021 continue;
3022
3023 LLVMValueRef numprims =
3024 LLVMBuildLoad(builder, ctx->gs_generated_prims[stream], "");
3025 numprims = ac_build_reduce(&ctx->ac, numprims, nir_op_iadd, ctx->ac.wave_size);
3026
3027 tmp = LLVMBuildICmp(builder, LLVMIntEQ, ac_get_thread_id(&ctx->ac), ctx->ac.i32_0, "");
3028 ac_build_ifcc(&ctx->ac, tmp, 5105);
3029 {
3030 LLVMBuildAtomicRMW(builder, LLVMAtomicRMWBinOpAdd,
3031 ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch,
3032 LLVMConstInt(ctx->ac.i32, stream, false)),
3033 numprims, LLVMAtomicOrderingMonotonic, false);
3034 }
3035 ac_build_endif(&ctx->ac, 5105);
3036 }
3037 }
3038
3039 static void gfx10_ngg_gs_emit_epilogue_2(struct radv_shader_context *ctx)
3040 {
3041 const unsigned verts_per_prim = si_conv_gl_prim_to_vertices(ctx->shader->info.gs.output_primitive);
3042 LLVMBuilderRef builder = ctx->ac.builder;
3043 LLVMValueRef tmp, tmp2;
3044
3045 ac_build_s_barrier(&ctx->ac);
3046
3047 const LLVMValueRef tid = get_thread_id_in_tg(ctx);
3048 LLVMValueRef num_emit_threads = ngg_get_prim_cnt(ctx);
3049
3050 /* Streamout */
3051 if (ctx->args->shader_info->so.num_outputs) {
3052 struct ngg_streamout nggso = {};
3053
3054 nggso.num_vertices = LLVMConstInt(ctx->ac.i32, verts_per_prim, false);
3055
3056 LLVMValueRef vertexptr = ngg_gs_vertex_ptr(ctx, tid);
3057 for (unsigned stream = 0; stream < 4; ++stream) {
3058 if (!ctx->args->shader_info->gs.num_stream_output_components[stream])
3059 continue;
3060
3061 tmp = LLVMBuildLoad(builder,
3062 ngg_gs_get_emit_primflag_ptr(ctx, vertexptr, stream), "");
3063 tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3064 tmp2 = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
3065 nggso.prim_enable[stream] = LLVMBuildAnd(builder, tmp, tmp2, "");
3066 }
3067
3068 for (unsigned i = 0; i < verts_per_prim; ++i) {
3069 tmp = LLVMBuildSub(builder, tid,
3070 LLVMConstInt(ctx->ac.i32, verts_per_prim - i - 1, false), "");
3071 tmp = ngg_gs_vertex_ptr(ctx, tmp);
3072 nggso.vertices[i] = ac_build_gep0(&ctx->ac, tmp, ctx->ac.i32_0);
3073 }
3074
3075 build_streamout(ctx, &nggso);
3076 }
3077
3078 /* Write shader query data. */
3079 tmp = ac_get_arg(&ctx->ac, ctx->args->ngg_gs_state);
3080 tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3081 ac_build_ifcc(&ctx->ac, tmp, 5109);
3082 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid,
3083 LLVMConstInt(ctx->ac.i32, 4, false), "");
3084 ac_build_ifcc(&ctx->ac, tmp, 5110);
3085 {
3086 tmp = LLVMBuildLoad(builder, ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tid), "");
3087
3088 ac_llvm_add_target_dep_function_attr(ctx->main_function,
3089 "amdgpu-gds-size", 256);
3090
3091 LLVMTypeRef gdsptr = LLVMPointerType(ctx->ac.i32, AC_ADDR_SPACE_GDS);
3092 LLVMValueRef gdsbase = LLVMBuildIntToPtr(builder, ctx->ac.i32_0, gdsptr, "");
3093
3094 const char *sync_scope = LLVM_VERSION_MAJOR >= 9 ? "workgroup-one-as" : "workgroup";
3095
3096 /* Use a plain GDS atomic to accumulate the number of generated
3097 * primitives.
3098 */
3099 ac_build_atomic_rmw(&ctx->ac, LLVMAtomicRMWBinOpAdd, gdsbase,
3100 tmp, sync_scope);
3101 }
3102 ac_build_endif(&ctx->ac, 5110);
3103 ac_build_endif(&ctx->ac, 5109);
3104
3105 /* TODO: culling */
3106
3107 /* Determine vertex liveness. */
3108 LLVMValueRef vertliveptr = ac_build_alloca(&ctx->ac, ctx->ac.i1, "vertexlive");
3109
3110 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
3111 ac_build_ifcc(&ctx->ac, tmp, 5120);
3112 {
3113 for (unsigned i = 0; i < verts_per_prim; ++i) {
3114 const LLVMValueRef primidx =
3115 LLVMBuildAdd(builder, tid,
3116 LLVMConstInt(ctx->ac.i32, i, false), "");
3117
3118 if (i > 0) {
3119 tmp = LLVMBuildICmp(builder, LLVMIntULT, primidx, num_emit_threads, "");
3120 ac_build_ifcc(&ctx->ac, tmp, 5121 + i);
3121 }
3122
3123 /* Load primitive liveness */
3124 tmp = ngg_gs_vertex_ptr(ctx, primidx);
3125 tmp = LLVMBuildLoad(builder,
3126 ngg_gs_get_emit_primflag_ptr(ctx, tmp, 0), "");
3127 const LLVMValueRef primlive =
3128 LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3129
3130 tmp = LLVMBuildLoad(builder, vertliveptr, "");
3131 tmp = LLVMBuildOr(builder, tmp, primlive, ""),
3132 LLVMBuildStore(builder, tmp, vertliveptr);
3133
3134 if (i > 0)
3135 ac_build_endif(&ctx->ac, 5121 + i);
3136 }
3137 }
3138 ac_build_endif(&ctx->ac, 5120);
3139
3140 /* Inclusive scan addition across the current wave. */
3141 LLVMValueRef vertlive = LLVMBuildLoad(builder, vertliveptr, "");
3142 struct ac_wg_scan vertlive_scan = {};
3143 vertlive_scan.op = nir_op_iadd;
3144 vertlive_scan.enable_reduce = true;
3145 vertlive_scan.enable_exclusive = true;
3146 vertlive_scan.src = vertlive;
3147 vertlive_scan.scratch = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, ctx->ac.i32_0);
3148 vertlive_scan.waveidx = get_wave_id_in_tg(ctx);
3149 vertlive_scan.numwaves = get_tgsize(ctx);
3150 vertlive_scan.maxwaves = 8;
3151
3152 ac_build_wg_scan(&ctx->ac, &vertlive_scan);
3153
3154 /* Skip all exports (including index exports) when possible. At least on
3155 * early gfx10 revisions this is also to avoid hangs.
3156 */
3157 LLVMValueRef have_exports =
3158 LLVMBuildICmp(builder, LLVMIntNE, vertlive_scan.result_reduce, ctx->ac.i32_0, "");
3159 num_emit_threads =
3160 LLVMBuildSelect(builder, have_exports, num_emit_threads, ctx->ac.i32_0, "");
3161
3162 /* Allocate export space. Send this message as early as possible, to
3163 * hide the latency of the SQ <-> SPI roundtrip.
3164 *
3165 * Note: We could consider compacting primitives for export as well.
3166 * PA processes 1 non-null prim / clock, but it fetches 4 DW of
3167 * prim data per clock and skips null primitives at no additional
3168 * cost. So compacting primitives can only be beneficial when
3169 * there are 4 or more contiguous null primitives in the export
3170 * (in the common case of single-dword prim exports).
3171 */
3172 ac_build_sendmsg_gs_alloc_req(&ctx->ac, get_wave_id_in_tg(ctx),
3173 vertlive_scan.result_reduce, num_emit_threads);
3174
3175 /* Setup the reverse vertex compaction permutation. We re-use stream 1
3176 * of the primitive liveness flags, relying on the fact that each
3177 * threadgroup can have at most 256 threads. */
3178 ac_build_ifcc(&ctx->ac, vertlive, 5130);
3179 {
3180 tmp = ngg_gs_vertex_ptr(ctx, vertlive_scan.result_exclusive);
3181 tmp2 = LLVMBuildTrunc(builder, tid, ctx->ac.i8, "");
3182 LLVMBuildStore(builder, tmp2,
3183 ngg_gs_get_emit_primflag_ptr(ctx, tmp, 1));
3184 }
3185 ac_build_endif(&ctx->ac, 5130);
3186
3187 ac_build_s_barrier(&ctx->ac);
3188
3189 /* Export primitive data */
3190 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
3191 ac_build_ifcc(&ctx->ac, tmp, 5140);
3192 {
3193 LLVMValueRef flags;
3194 struct ac_ngg_prim prim = {};
3195 prim.num_vertices = verts_per_prim;
3196
3197 tmp = ngg_gs_vertex_ptr(ctx, tid);
3198 flags = LLVMBuildLoad(builder,
3199 ngg_gs_get_emit_primflag_ptr(ctx, tmp, 0), "");
3200 prim.isnull = LLVMBuildNot(builder, LLVMBuildTrunc(builder, flags, ctx->ac.i1, ""), "");
3201
3202 for (unsigned i = 0; i < verts_per_prim; ++i) {
3203 prim.index[i] = LLVMBuildSub(builder, vertlive_scan.result_exclusive,
3204 LLVMConstInt(ctx->ac.i32, verts_per_prim - i - 1, false), "");
3205 prim.edgeflag[i] = ctx->ac.i1false;
3206 }
3207
3208 /* Geometry shaders output triangle strips, but NGG expects
3209 * triangles. We need to change the vertex order for odd
3210 * triangles to get correct front/back facing by swapping 2
3211 * vertex indices, but we also have to keep the provoking
3212 * vertex in the same place.
3213 */
3214 if (verts_per_prim == 3) {
3215 LLVMValueRef is_odd = LLVMBuildLShr(builder, flags, ctx->ac.i8_1, "");
3216 is_odd = LLVMBuildTrunc(builder, is_odd, ctx->ac.i1, "");
3217
3218 struct ac_ngg_prim in = prim;
3219 prim.index[0] = in.index[0];
3220 prim.index[1] = LLVMBuildSelect(builder, is_odd,
3221 in.index[2], in.index[1], "");
3222 prim.index[2] = LLVMBuildSelect(builder, is_odd,
3223 in.index[1], in.index[2], "");
3224 }
3225
3226 ac_build_export_prim(&ctx->ac, &prim);
3227 }
3228 ac_build_endif(&ctx->ac, 5140);
3229
3230 /* Export position and parameter data */
3231 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, vertlive_scan.result_reduce, "");
3232 ac_build_ifcc(&ctx->ac, tmp, 5145);
3233 {
3234 struct radv_vs_output_info *outinfo = &ctx->args->shader_info->vs.outinfo;
3235 bool export_view_index = ctx->args->options->key.has_multiview_view_index;
3236 struct radv_shader_output_values *outputs;
3237 unsigned noutput = 0;
3238
3239 /* Allocate a temporary array for the output values. */
3240 unsigned num_outputs = util_bitcount64(ctx->output_mask) + export_view_index;
3241 outputs = calloc(num_outputs, sizeof(outputs[0]));
3242
3243 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
3244 sizeof(outinfo->vs_output_param_offset));
3245 outinfo->pos_exports = 0;
3246
3247 tmp = ngg_gs_vertex_ptr(ctx, tid);
3248 tmp = LLVMBuildLoad(builder,
3249 ngg_gs_get_emit_primflag_ptr(ctx, tmp, 1), "");
3250 tmp = LLVMBuildZExt(builder, tmp, ctx->ac.i32, "");
3251 const LLVMValueRef vertexptr = ngg_gs_vertex_ptr(ctx, tmp);
3252
3253 unsigned out_idx = 0;
3254 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3255 unsigned output_usage_mask =
3256 ctx->args->shader_info->gs.output_usage_mask[i];
3257 int length = util_last_bit(output_usage_mask);
3258
3259 if (!(ctx->output_mask & (1ull << i)))
3260 continue;
3261
3262 outputs[noutput].slot_name = i;
3263 outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
3264 outputs[noutput].usage_mask = output_usage_mask;
3265
3266 for (unsigned j = 0; j < length; j++, out_idx++) {
3267 if (!(output_usage_mask & (1 << j)))
3268 continue;
3269
3270 tmp = ngg_gs_get_emit_output_ptr(ctx, vertexptr, out_idx);
3271 tmp = LLVMBuildLoad(builder, tmp, "");
3272
3273 LLVMTypeRef type = LLVMGetAllocatedType(ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
3274 if (ac_get_type_size(type) == 2) {
3275 tmp = ac_to_integer(&ctx->ac, tmp);
3276 tmp = LLVMBuildTrunc(ctx->ac.builder, tmp, ctx->ac.i16, "");
3277 }
3278
3279 outputs[noutput].values[j] = ac_to_float(&ctx->ac, tmp);
3280 }
3281
3282 for (unsigned j = length; j < 4; j++)
3283 outputs[noutput].values[j] = LLVMGetUndef(ctx->ac.f32);
3284
3285 noutput++;
3286 }
3287
3288 /* Export ViewIndex. */
3289 if (export_view_index) {
3290 outputs[noutput].slot_name = VARYING_SLOT_LAYER;
3291 outputs[noutput].slot_index = 0;
3292 outputs[noutput].usage_mask = 0x1;
3293 outputs[noutput].values[0] =
3294 ac_to_float(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->ac.view_index));
3295 for (unsigned j = 1; j < 4; j++)
3296 outputs[noutput].values[j] = ctx->ac.f32_0;
3297 noutput++;
3298 }
3299
3300 radv_llvm_export_vs(ctx, outputs, noutput, outinfo,
3301 ctx->args->options->key.vs_common_out.export_clip_dists);
3302 FREE(outputs);
3303 }
3304 ac_build_endif(&ctx->ac, 5145);
3305 }
3306
3307 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context *ctx,
3308 unsigned stream,
3309 LLVMValueRef vertexidx,
3310 LLVMValueRef *addrs)
3311 {
3312 LLVMBuilderRef builder = ctx->ac.builder;
3313 LLVMValueRef tmp;
3314
3315 const LLVMValueRef vertexptr =
3316 ngg_gs_emit_vertex_ptr(ctx, get_thread_id_in_tg(ctx), vertexidx);
3317 unsigned out_idx = 0;
3318 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3319 unsigned output_usage_mask =
3320 ctx->args->shader_info->gs.output_usage_mask[i];
3321 uint8_t output_stream =
3322 ctx->args->shader_info->gs.output_streams[i];
3323 LLVMValueRef *out_ptr = &addrs[i * 4];
3324 int length = util_last_bit(output_usage_mask);
3325
3326 if (!(ctx->output_mask & (1ull << i)) ||
3327 output_stream != stream)
3328 continue;
3329
3330 for (unsigned j = 0; j < length; j++, out_idx++) {
3331 if (!(output_usage_mask & (1 << j)))
3332 continue;
3333
3334 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
3335 out_ptr[j], "");
3336 out_val = ac_to_integer(&ctx->ac, out_val);
3337 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
3338
3339 LLVMBuildStore(builder, out_val,
3340 ngg_gs_get_emit_output_ptr(ctx, vertexptr, out_idx));
3341 }
3342 }
3343 assert(out_idx * 4 <= ctx->args->shader_info->gs.gsvs_vertex_size);
3344
3345 /* Store the current number of emitted vertices to zero out remaining
3346 * primitive flags in case the geometry shader doesn't emit the maximum
3347 * number of vertices.
3348 */
3349 tmp = LLVMBuildAdd(builder, vertexidx, ctx->ac.i32_1, "");
3350 LLVMBuildStore(builder, tmp, ctx->gs_next_vertex[stream]);
3351
3352 /* Determine and store whether this vertex completed a primitive. */
3353 const LLVMValueRef curverts = LLVMBuildLoad(builder, ctx->gs_curprim_verts[stream], "");
3354
3355 tmp = LLVMConstInt(ctx->ac.i32, si_conv_gl_prim_to_vertices(ctx->shader->info.gs.output_primitive) - 1, false);
3356 const LLVMValueRef iscompleteprim =
3357 LLVMBuildICmp(builder, LLVMIntUGE, curverts, tmp, "");
3358
3359 /* Since the geometry shader emits triangle strips, we need to
3360 * track which primitive is odd and swap vertex indices to get
3361 * the correct vertex order.
3362 */
3363 LLVMValueRef is_odd = ctx->ac.i1false;
3364 if (stream == 0 &&
3365 si_conv_gl_prim_to_vertices(ctx->shader->info.gs.output_primitive) == 3) {
3366 tmp = LLVMBuildAnd(builder, curverts, ctx->ac.i32_1, "");
3367 is_odd = LLVMBuildICmp(builder, LLVMIntEQ, tmp, ctx->ac.i32_1, "");
3368 }
3369
3370 tmp = LLVMBuildAdd(builder, curverts, ctx->ac.i32_1, "");
3371 LLVMBuildStore(builder, tmp, ctx->gs_curprim_verts[stream]);
3372
3373 /* The per-vertex primitive flag encoding:
3374 * bit 0: whether this vertex finishes a primitive
3375 * bit 1: whether the primitive is odd (if we are emitting triangle strips)
3376 */
3377 tmp = LLVMBuildZExt(builder, iscompleteprim, ctx->ac.i8, "");
3378 tmp = LLVMBuildOr(builder, tmp,
3379 LLVMBuildShl(builder,
3380 LLVMBuildZExt(builder, is_odd, ctx->ac.i8, ""),
3381 ctx->ac.i8_1, ""), "");
3382 LLVMBuildStore(builder, tmp,
3383 ngg_gs_get_emit_primflag_ptr(ctx, vertexptr, stream));
3384
3385 tmp = LLVMBuildLoad(builder, ctx->gs_generated_prims[stream], "");
3386 tmp = LLVMBuildAdd(builder, tmp, LLVMBuildZExt(builder, iscompleteprim, ctx->ac.i32, ""), "");
3387 LLVMBuildStore(builder, tmp, ctx->gs_generated_prims[stream]);
3388 }
3389
3390 static void
3391 write_tess_factors(struct radv_shader_context *ctx)
3392 {
3393 unsigned stride, outer_comps, inner_comps;
3394 LLVMValueRef tcs_rel_ids = ac_get_arg(&ctx->ac, ctx->args->ac.tcs_rel_ids);
3395 LLVMValueRef invocation_id = ac_unpack_param(&ctx->ac, tcs_rel_ids, 8, 5);
3396 LLVMValueRef rel_patch_id = ac_unpack_param(&ctx->ac, tcs_rel_ids, 0, 8);
3397 unsigned tess_inner_index = 0, tess_outer_index;
3398 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
3399 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
3400 int i;
3401 ac_emit_barrier(&ctx->ac, ctx->stage);
3402
3403 switch (ctx->args->options->key.tcs.primitive_mode) {
3404 case GL_ISOLINES:
3405 stride = 2;
3406 outer_comps = 2;
3407 inner_comps = 0;
3408 break;
3409 case GL_TRIANGLES:
3410 stride = 4;
3411 outer_comps = 3;
3412 inner_comps = 1;
3413 break;
3414 case GL_QUADS:
3415 stride = 6;
3416 outer_comps = 4;
3417 inner_comps = 2;
3418 break;
3419 default:
3420 return;
3421 }
3422
3423 ac_build_ifcc(&ctx->ac,
3424 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3425 invocation_id, ctx->ac.i32_0, ""), 6503);
3426
3427 lds_base = get_tcs_out_current_patch_data_offset(ctx);
3428
3429 if (inner_comps) {
3430 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
3431 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
3432 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
3433 }
3434
3435 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
3436 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
3437 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
3438
3439 for (i = 0; i < 4; i++) {
3440 inner[i] = LLVMGetUndef(ctx->ac.i32);
3441 outer[i] = LLVMGetUndef(ctx->ac.i32);
3442 }
3443
3444 // LINES reversal
3445 if (ctx->args->options->key.tcs.primitive_mode == GL_ISOLINES) {
3446 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
3447 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
3448 ctx->ac.i32_1, "");
3449 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
3450 } else {
3451 for (i = 0; i < outer_comps; i++) {
3452 outer[i] = out[i] =
3453 ac_lds_load(&ctx->ac, lds_outer);
3454 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
3455 ctx->ac.i32_1, "");
3456 }
3457 for (i = 0; i < inner_comps; i++) {
3458 inner[i] = out[outer_comps+i] =
3459 ac_lds_load(&ctx->ac, lds_inner);
3460 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
3461 ctx->ac.i32_1, "");
3462 }
3463 }
3464
3465 /* Convert the outputs to vectors for stores. */
3466 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
3467 vec1 = NULL;
3468
3469 if (stride > 4)
3470 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
3471
3472
3473 buffer = ctx->hs_ring_tess_factor;
3474 tf_base = ac_get_arg(&ctx->ac, ctx->args->tess_factor_offset);
3475 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
3476 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
3477 unsigned tf_offset = 0;
3478
3479 if (ctx->ac.chip_class <= GFX8) {
3480 ac_build_ifcc(&ctx->ac,
3481 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
3482 rel_patch_id, ctx->ac.i32_0, ""), 6504);
3483
3484 /* Store the dynamic HS control word. */
3485 ac_build_buffer_store_dword(&ctx->ac, buffer,
3486 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
3487 1, ctx->ac.i32_0, tf_base,
3488 0, ac_glc);
3489 tf_offset += 4;
3490
3491 ac_build_endif(&ctx->ac, 6504);
3492 }
3493
3494 /* Store the tessellation factors. */
3495 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
3496 MIN2(stride, 4), byteoffset, tf_base,
3497 tf_offset, ac_glc);
3498 if (vec1)
3499 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
3500 stride - 4, byteoffset, tf_base,
3501 16 + tf_offset, ac_glc);
3502
3503 //store to offchip for TES to read - only if TES reads them
3504 if (ctx->args->options->key.tcs.tes_reads_tess_factors) {
3505 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
3506 LLVMValueRef tf_inner_offset;
3507 unsigned param_outer, param_inner;
3508
3509 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
3510 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
3511 LLVMConstInt(ctx->ac.i32, param_outer, 0));
3512
3513 outer_vec = ac_build_gather_values(&ctx->ac, outer,
3514 util_next_power_of_two(outer_comps));
3515
3516 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
3517 outer_comps, tf_outer_offset,
3518 ac_get_arg(&ctx->ac, ctx->args->oc_lds),
3519 0, ac_glc);
3520 if (inner_comps) {
3521 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
3522 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
3523 LLVMConstInt(ctx->ac.i32, param_inner, 0));
3524
3525 inner_vec = inner_comps == 1 ? inner[0] :
3526 ac_build_gather_values(&ctx->ac, inner, inner_comps);
3527 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
3528 inner_comps, tf_inner_offset,
3529 ac_get_arg(&ctx->ac, ctx->args->oc_lds),
3530 0, ac_glc);
3531 }
3532 }
3533
3534 ac_build_endif(&ctx->ac, 6503);
3535 }
3536
3537 static void
3538 handle_tcs_outputs_post(struct radv_shader_context *ctx)
3539 {
3540 write_tess_factors(ctx);
3541 }
3542
3543 static bool
3544 si_export_mrt_color(struct radv_shader_context *ctx,
3545 LLVMValueRef *color, unsigned index,
3546 struct ac_export_args *args)
3547 {
3548 /* Export */
3549 si_llvm_init_export_args(ctx, color, 0xf,
3550 V_008DFC_SQ_EXP_MRT + index, args);
3551 if (!args->enabled_channels)
3552 return false; /* unnecessary NULL export */
3553
3554 return true;
3555 }
3556
3557 static void
3558 radv_export_mrt_z(struct radv_shader_context *ctx,
3559 LLVMValueRef depth, LLVMValueRef stencil,
3560 LLVMValueRef samplemask)
3561 {
3562 struct ac_export_args args;
3563
3564 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
3565
3566 ac_build_export(&ctx->ac, &args);
3567 }
3568
3569 static void
3570 handle_fs_outputs_post(struct radv_shader_context *ctx)
3571 {
3572 unsigned index = 0;
3573 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
3574 struct ac_export_args color_args[8];
3575
3576 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3577 LLVMValueRef values[4];
3578
3579 if (!(ctx->output_mask & (1ull << i)))
3580 continue;
3581
3582 if (i < FRAG_RESULT_DATA0)
3583 continue;
3584
3585 for (unsigned j = 0; j < 4; j++)
3586 values[j] = ac_to_float(&ctx->ac,
3587 radv_load_output(ctx, i, j));
3588
3589 bool ret = si_export_mrt_color(ctx, values,
3590 i - FRAG_RESULT_DATA0,
3591 &color_args[index]);
3592 if (ret)
3593 index++;
3594 }
3595
3596 /* Process depth, stencil, samplemask. */
3597 if (ctx->args->shader_info->ps.writes_z) {
3598 depth = ac_to_float(&ctx->ac,
3599 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
3600 }
3601 if (ctx->args->shader_info->ps.writes_stencil) {
3602 stencil = ac_to_float(&ctx->ac,
3603 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
3604 }
3605 if (ctx->args->shader_info->ps.writes_sample_mask) {
3606 samplemask = ac_to_float(&ctx->ac,
3607 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
3608 }
3609
3610 /* Set the DONE bit on last non-null color export only if Z isn't
3611 * exported.
3612 */
3613 if (index > 0 &&
3614 !ctx->args->shader_info->ps.writes_z &&
3615 !ctx->args->shader_info->ps.writes_stencil &&
3616 !ctx->args->shader_info->ps.writes_sample_mask) {
3617 unsigned last = index - 1;
3618
3619 color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */
3620 color_args[last].done = 1; /* DONE bit */
3621 }
3622
3623 /* Export PS outputs. */
3624 for (unsigned i = 0; i < index; i++)
3625 ac_build_export(&ctx->ac, &color_args[i]);
3626
3627 if (depth || stencil || samplemask)
3628 radv_export_mrt_z(ctx, depth, stencil, samplemask);
3629 else if (!index)
3630 ac_build_export_null(&ctx->ac);
3631 }
3632
3633 static void
3634 emit_gs_epilogue(struct radv_shader_context *ctx)
3635 {
3636 if (ctx->args->options->key.vs_common_out.as_ngg) {
3637 gfx10_ngg_gs_emit_epilogue_1(ctx);
3638 return;
3639 }
3640
3641 if (ctx->ac.chip_class >= GFX10)
3642 LLVMBuildFence(ctx->ac.builder, LLVMAtomicOrderingRelease, false, "");
3643
3644 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
3645 }
3646
3647 static void
3648 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
3649 LLVMValueRef *addrs)
3650 {
3651 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
3652
3653 switch (ctx->stage) {
3654 case MESA_SHADER_VERTEX:
3655 if (ctx->args->options->key.vs_common_out.as_ls)
3656 handle_ls_outputs_post(ctx);
3657 else if (ctx->args->options->key.vs_common_out.as_es)
3658 handle_es_outputs_post(ctx, &ctx->args->shader_info->vs.es_info);
3659 else if (ctx->args->options->key.vs_common_out.as_ngg)
3660 handle_ngg_outputs_post_1(ctx);
3661 else
3662 handle_vs_outputs_post(ctx, ctx->args->options->key.vs_common_out.export_prim_id,
3663 ctx->args->options->key.vs_common_out.export_clip_dists,
3664 &ctx->args->shader_info->vs.outinfo);
3665 break;
3666 case MESA_SHADER_FRAGMENT:
3667 handle_fs_outputs_post(ctx);
3668 break;
3669 case MESA_SHADER_GEOMETRY:
3670 emit_gs_epilogue(ctx);
3671 break;
3672 case MESA_SHADER_TESS_CTRL:
3673 handle_tcs_outputs_post(ctx);
3674 break;
3675 case MESA_SHADER_TESS_EVAL:
3676 if (ctx->args->options->key.vs_common_out.as_es)
3677 handle_es_outputs_post(ctx, &ctx->args->shader_info->tes.es_info);
3678 else if (ctx->args->options->key.vs_common_out.as_ngg)
3679 handle_ngg_outputs_post_1(ctx);
3680 else
3681 handle_vs_outputs_post(ctx, ctx->args->options->key.vs_common_out.export_prim_id,
3682 ctx->args->options->key.vs_common_out.export_clip_dists,
3683 &ctx->args->shader_info->tes.outinfo);
3684 break;
3685 default:
3686 break;
3687 }
3688 }
3689
3690 static void ac_llvm_finalize_module(struct radv_shader_context *ctx,
3691 LLVMPassManagerRef passmgr,
3692 const struct radv_nir_compiler_options *options)
3693 {
3694 LLVMRunPassManager(passmgr, ctx->ac.module);
3695 LLVMDisposeBuilder(ctx->ac.builder);
3696
3697 ac_llvm_context_dispose(&ctx->ac);
3698 }
3699
3700 static void
3701 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
3702 {
3703 struct radv_vs_output_info *outinfo;
3704
3705 switch (ctx->stage) {
3706 case MESA_SHADER_FRAGMENT:
3707 case MESA_SHADER_COMPUTE:
3708 case MESA_SHADER_TESS_CTRL:
3709 case MESA_SHADER_GEOMETRY:
3710 return;
3711 case MESA_SHADER_VERTEX:
3712 if (ctx->args->options->key.vs_common_out.as_ls ||
3713 ctx->args->options->key.vs_common_out.as_es)
3714 return;
3715 outinfo = &ctx->args->shader_info->vs.outinfo;
3716 break;
3717 case MESA_SHADER_TESS_EVAL:
3718 if (ctx->args->options->key.vs_common_out.as_es)
3719 return;
3720 outinfo = &ctx->args->shader_info->tes.outinfo;
3721 break;
3722 default:
3723 unreachable("Unhandled shader type");
3724 }
3725
3726 ac_optimize_vs_outputs(&ctx->ac,
3727 ctx->main_function,
3728 outinfo->vs_output_param_offset,
3729 VARYING_SLOT_MAX, 0,
3730 &outinfo->param_exports);
3731 }
3732
3733 static void
3734 ac_setup_rings(struct radv_shader_context *ctx)
3735 {
3736 if (ctx->args->options->chip_class <= GFX8 &&
3737 (ctx->stage == MESA_SHADER_GEOMETRY ||
3738 ctx->args->options->key.vs_common_out.as_es)) {
3739 unsigned ring = ctx->stage == MESA_SHADER_GEOMETRY ? RING_ESGS_GS
3740 : RING_ESGS_VS;
3741 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, ring, false);
3742
3743 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac,
3744 ctx->ring_offsets,
3745 offset);
3746 }
3747
3748 if (ctx->args->is_gs_copy_shader) {
3749 ctx->gsvs_ring[0] =
3750 ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets,
3751 LLVMConstInt(ctx->ac.i32,
3752 RING_GSVS_VS, false));
3753 }
3754
3755 if (ctx->stage == MESA_SHADER_GEOMETRY) {
3756 /* The conceptual layout of the GSVS ring is
3757 * v0c0 .. vLv0 v0c1 .. vLc1 ..
3758 * but the real memory layout is swizzled across
3759 * threads:
3760 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
3761 * t16v0c0 ..
3762 * Override the buffer descriptor accordingly.
3763 */
3764 LLVMTypeRef v2i64 = LLVMVectorType(ctx->ac.i64, 2);
3765 uint64_t stream_offset = 0;
3766 unsigned num_records = ctx->ac.wave_size;
3767 LLVMValueRef base_ring;
3768
3769 base_ring =
3770 ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets,
3771 LLVMConstInt(ctx->ac.i32,
3772 RING_GSVS_GS, false));
3773
3774 for (unsigned stream = 0; stream < 4; stream++) {
3775 unsigned num_components, stride;
3776 LLVMValueRef ring, tmp;
3777
3778 num_components =
3779 ctx->args->shader_info->gs.num_stream_output_components[stream];
3780
3781 if (!num_components)
3782 continue;
3783
3784 stride = 4 * num_components * ctx->shader->info.gs.vertices_out;
3785
3786 /* Limit on the stride field for <= GFX7. */
3787 assert(stride < (1 << 14));
3788
3789 ring = LLVMBuildBitCast(ctx->ac.builder,
3790 base_ring, v2i64, "");
3791 tmp = LLVMBuildExtractElement(ctx->ac.builder,
3792 ring, ctx->ac.i32_0, "");
3793 tmp = LLVMBuildAdd(ctx->ac.builder, tmp,
3794 LLVMConstInt(ctx->ac.i64,
3795 stream_offset, 0), "");
3796 ring = LLVMBuildInsertElement(ctx->ac.builder,
3797 ring, tmp, ctx->ac.i32_0, "");
3798
3799 stream_offset += stride * ctx->ac.wave_size;
3800
3801 ring = LLVMBuildBitCast(ctx->ac.builder, ring,
3802 ctx->ac.v4i32, "");
3803
3804 tmp = LLVMBuildExtractElement(ctx->ac.builder, ring,
3805 ctx->ac.i32_1, "");
3806 tmp = LLVMBuildOr(ctx->ac.builder, tmp,
3807 LLVMConstInt(ctx->ac.i32,
3808 S_008F04_STRIDE(stride), false), "");
3809 ring = LLVMBuildInsertElement(ctx->ac.builder, ring, tmp,
3810 ctx->ac.i32_1, "");
3811
3812 ring = LLVMBuildInsertElement(ctx->ac.builder, ring,
3813 LLVMConstInt(ctx->ac.i32,
3814 num_records, false),
3815 LLVMConstInt(ctx->ac.i32, 2, false), "");
3816
3817 ctx->gsvs_ring[stream] = ring;
3818 }
3819 }
3820
3821 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
3822 ctx->stage == MESA_SHADER_TESS_EVAL) {
3823 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
3824 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
3825 }
3826 }
3827
3828 unsigned
3829 radv_nir_get_max_workgroup_size(enum chip_class chip_class,
3830 gl_shader_stage stage,
3831 const struct nir_shader *nir)
3832 {
3833 const unsigned backup_sizes[] = {chip_class >= GFX9 ? 128 : 64, 1, 1};
3834 unsigned sizes[3];
3835 for (unsigned i = 0; i < 3; i++)
3836 sizes[i] = nir ? nir->info.cs.local_size[i] : backup_sizes[i];
3837 return radv_get_max_workgroup_size(chip_class, stage, sizes);
3838 }
3839
3840 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
3841 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
3842 {
3843 LLVMValueRef count =
3844 ac_unpack_param(&ctx->ac, ac_get_arg(&ctx->ac, ctx->args->merged_wave_info), 8, 8);
3845 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
3846 ctx->ac.i32_0, "");
3847 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty,
3848 ac_get_arg(&ctx->ac, ctx->args->rel_auto_id),
3849 ctx->abi.instance_id, "");
3850 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty,
3851 ac_get_arg(&ctx->ac, ctx->args->ac.tcs_rel_ids),
3852 ctx->rel_auto_id,
3853 "");
3854 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty,
3855 ac_get_arg(&ctx->ac, ctx->args->ac.tcs_patch_id),
3856 ctx->abi.vertex_id, "");
3857 }
3858
3859 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx, bool merged)
3860 {
3861 if (merged) {
3862 for(int i = 5; i >= 0; --i) {
3863 ctx->gs_vtx_offset[i] =
3864 ac_unpack_param(&ctx->ac,
3865 ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[i & ~1]),
3866 (i & 1) * 16, 16);
3867 }
3868
3869 ctx->gs_wave_id = ac_unpack_param(&ctx->ac,
3870 ac_get_arg(&ctx->ac, ctx->args->merged_wave_info),
3871 16, 8);
3872 } else {
3873 for (int i = 0; i < 6; i++)
3874 ctx->gs_vtx_offset[i] = ac_get_arg(&ctx->ac, ctx->args->gs_vtx_offset[i]);
3875 ctx->gs_wave_id = ac_get_arg(&ctx->ac, ctx->args->gs_wave_id);
3876 }
3877 }
3878
3879 /* Ensure that the esgs ring is declared.
3880 *
3881 * We declare it with 64KB alignment as a hint that the
3882 * pointer value will always be 0.
3883 */
3884 static void declare_esgs_ring(struct radv_shader_context *ctx)
3885 {
3886 if (ctx->esgs_ring)
3887 return;
3888
3889 assert(!LLVMGetNamedGlobal(ctx->ac.module, "esgs_ring"));
3890
3891 ctx->esgs_ring = LLVMAddGlobalInAddressSpace(
3892 ctx->ac.module, LLVMArrayType(ctx->ac.i32, 0),
3893 "esgs_ring",
3894 AC_ADDR_SPACE_LDS);
3895 LLVMSetLinkage(ctx->esgs_ring, LLVMExternalLinkage);
3896 LLVMSetAlignment(ctx->esgs_ring, 64 * 1024);
3897 }
3898
3899 static
3900 LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
3901 struct nir_shader *const *shaders,
3902 int shader_count,
3903 const struct radv_shader_args *args)
3904 {
3905 struct radv_shader_context ctx = {0};
3906 ctx.args = args;
3907
3908 enum ac_float_mode float_mode = AC_FLOAT_MODE_DEFAULT;
3909
3910 if (args->shader_info->float_controls_mode & FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32) {
3911 float_mode = AC_FLOAT_MODE_DENORM_FLUSH_TO_ZERO;
3912 }
3913
3914 ac_llvm_context_init(&ctx.ac, ac_llvm, args->options->chip_class,
3915 args->options->family, float_mode,
3916 args->shader_info->wave_size,
3917 args->shader_info->ballot_bit_size);
3918 ctx.context = ctx.ac.context;
3919
3920 ctx.max_workgroup_size = 0;
3921 for (int i = 0; i < shader_count; ++i) {
3922 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
3923 radv_nir_get_max_workgroup_size(args->options->chip_class,
3924 shaders[i]->info.stage,
3925 shaders[i]));
3926 }
3927
3928 if (ctx.ac.chip_class >= GFX10) {
3929 if (is_pre_gs_stage(shaders[0]->info.stage) &&
3930 args->options->key.vs_common_out.as_ngg) {
3931 ctx.max_workgroup_size = 128;
3932 }
3933 }
3934
3935 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2);
3936
3937 ctx.abi.inputs = &ctx.inputs[0];
3938 ctx.abi.emit_outputs = handle_shader_outputs_post;
3939 ctx.abi.emit_vertex_with_counter = visit_emit_vertex_with_counter;
3940 ctx.abi.load_ubo = radv_load_ubo;
3941 ctx.abi.load_ssbo = radv_load_ssbo;
3942 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
3943 ctx.abi.load_resource = radv_load_resource;
3944 ctx.abi.clamp_shadow_reference = false;
3945 ctx.abi.robust_buffer_access = args->options->robust_buffer_access;
3946
3947 bool is_ngg = is_pre_gs_stage(shaders[0]->info.stage) && args->options->key.vs_common_out.as_ngg;
3948 if (shader_count >= 2 || is_ngg)
3949 ac_init_exec_full_mask(&ctx.ac);
3950
3951 if (args->ac.vertex_id.used)
3952 ctx.abi.vertex_id = ac_get_arg(&ctx.ac, args->ac.vertex_id);
3953 if (args->rel_auto_id.used)
3954 ctx.rel_auto_id = ac_get_arg(&ctx.ac, args->rel_auto_id);
3955 if (args->ac.instance_id.used)
3956 ctx.abi.instance_id = ac_get_arg(&ctx.ac, args->ac.instance_id);
3957
3958 if (args->options->has_ls_vgpr_init_bug &&
3959 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
3960 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
3961
3962 if (is_ngg) {
3963 /* Declare scratch space base for streamout and vertex
3964 * compaction. Whether space is actually allocated is
3965 * determined during linking / PM4 creation.
3966 *
3967 * Add an extra dword per vertex to ensure an odd stride, which
3968 * avoids bank conflicts for SoA accesses.
3969 */
3970 if (!args->options->key.vs_common_out.as_ngg_passthrough)
3971 declare_esgs_ring(&ctx);
3972
3973 /* This is really only needed when streamout and / or vertex
3974 * compaction is enabled.
3975 */
3976 if (args->shader_info->so.num_outputs) {
3977 LLVMTypeRef asi32 = LLVMArrayType(ctx.ac.i32, 8);
3978 ctx.gs_ngg_scratch = LLVMAddGlobalInAddressSpace(ctx.ac.module,
3979 asi32, "ngg_scratch", AC_ADDR_SPACE_LDS);
3980 LLVMSetInitializer(ctx.gs_ngg_scratch, LLVMGetUndef(asi32));
3981 LLVMSetAlignment(ctx.gs_ngg_scratch, 4);
3982 }
3983 }
3984
3985 for(int i = 0; i < shader_count; ++i) {
3986 ctx.stage = shaders[i]->info.stage;
3987 ctx.shader = shaders[i];
3988 ctx.output_mask = 0;
3989
3990 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
3991 for (int i = 0; i < 4; i++) {
3992 ctx.gs_next_vertex[i] =
3993 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
3994 }
3995 if (args->options->key.vs_common_out.as_ngg) {
3996 for (unsigned i = 0; i < 4; ++i) {
3997 ctx.gs_curprim_verts[i] =
3998 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
3999 ctx.gs_generated_prims[i] =
4000 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
4001 }
4002
4003 unsigned scratch_size = 8;
4004 if (args->shader_info->so.num_outputs)
4005 scratch_size = 44;
4006
4007 LLVMTypeRef ai32 = LLVMArrayType(ctx.ac.i32, scratch_size);
4008 ctx.gs_ngg_scratch =
4009 LLVMAddGlobalInAddressSpace(ctx.ac.module,
4010 ai32, "ngg_scratch", AC_ADDR_SPACE_LDS);
4011 LLVMSetInitializer(ctx.gs_ngg_scratch, LLVMGetUndef(ai32));
4012 LLVMSetAlignment(ctx.gs_ngg_scratch, 4);
4013
4014 ctx.gs_ngg_emit = LLVMAddGlobalInAddressSpace(ctx.ac.module,
4015 LLVMArrayType(ctx.ac.i32, 0), "ngg_emit", AC_ADDR_SPACE_LDS);
4016 LLVMSetLinkage(ctx.gs_ngg_emit, LLVMExternalLinkage);
4017 LLVMSetAlignment(ctx.gs_ngg_emit, 4);
4018 }
4019
4020 ctx.abi.load_inputs = load_gs_input;
4021 ctx.abi.emit_primitive = visit_end_primitive;
4022 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
4023 ctx.abi.load_tess_varyings = load_tcs_varyings;
4024 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
4025 ctx.abi.store_tcs_outputs = store_tcs_output;
4026 if (shader_count == 1)
4027 ctx.tcs_num_inputs = args->options->key.tcs.num_inputs;
4028 else
4029 ctx.tcs_num_inputs = util_last_bit64(args->shader_info->vs.ls_outputs_written);
4030 unsigned tcs_num_outputs = util_last_bit64(ctx.args->shader_info->tcs.outputs_written);
4031 unsigned tcs_num_patch_outputs = util_last_bit64(ctx.args->shader_info->tcs.patch_outputs_written);
4032 ctx.tcs_num_patches =
4033 get_tcs_num_patches(
4034 ctx.args->options->key.tcs.input_vertices,
4035 ctx.shader->info.tess.tcs_vertices_out,
4036 ctx.tcs_num_inputs,
4037 tcs_num_outputs,
4038 tcs_num_patch_outputs,
4039 ctx.args->options->tess_offchip_block_dw_size,
4040 ctx.args->options->chip_class,
4041 ctx.args->options->family);
4042 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
4043 ctx.abi.load_tess_varyings = load_tes_input;
4044 ctx.abi.load_tess_coord = load_tess_coord;
4045 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
4046 ctx.tcs_num_patches = args->options->key.tes.num_patches;
4047 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
4048 ctx.abi.load_base_vertex = radv_load_base_vertex;
4049 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
4050 ctx.abi.load_sample_position = load_sample_position;
4051 ctx.abi.load_sample_mask_in = load_sample_mask_in;
4052 }
4053
4054 if (shaders[i]->info.stage == MESA_SHADER_VERTEX &&
4055 args->options->key.vs_common_out.as_ngg &&
4056 args->options->key.vs_common_out.export_prim_id) {
4057 declare_esgs_ring(&ctx);
4058 }
4059
4060 bool nested_barrier = false;
4061
4062 if (i) {
4063 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
4064 args->options->key.vs_common_out.as_ngg) {
4065 gfx10_ngg_gs_emit_prologue(&ctx);
4066 nested_barrier = false;
4067 } else {
4068 nested_barrier = true;
4069 }
4070 }
4071
4072 if (nested_barrier) {
4073 /* Execute a barrier before the second shader in
4074 * a merged shader.
4075 *
4076 * Execute the barrier inside the conditional block,
4077 * so that empty waves can jump directly to s_endpgm,
4078 * which will also signal the barrier.
4079 *
4080 * This is possible in gfx9, because an empty wave
4081 * for the second shader does not participate in
4082 * the epilogue. With NGG, empty waves may still
4083 * be required to export data (e.g. GS output vertices),
4084 * so we cannot let them exit early.
4085 *
4086 * If the shader is TCS and the TCS epilog is present
4087 * and contains a barrier, it will wait there and then
4088 * reach s_endpgm.
4089 */
4090 ac_emit_barrier(&ctx.ac, ctx.stage);
4091 }
4092
4093 nir_foreach_variable(variable, &shaders[i]->outputs)
4094 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
4095
4096 ac_setup_rings(&ctx);
4097
4098 LLVMBasicBlockRef merge_block = NULL;
4099 if (shader_count >= 2 || is_ngg) {
4100 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
4101 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
4102 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
4103
4104 LLVMValueRef count =
4105 ac_unpack_param(&ctx.ac,
4106 ac_get_arg(&ctx.ac, args->merged_wave_info),
4107 8 * i, 8);
4108 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
4109 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
4110 thread_id, count, "");
4111 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
4112
4113 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
4114 }
4115
4116 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
4117 prepare_interp_optimize(&ctx, shaders[i]);
4118 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
4119 handle_vs_inputs(&ctx, shaders[i]);
4120 else if(shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
4121 prepare_gs_input_vgprs(&ctx, shader_count >= 2);
4122
4123 ac_nir_translate(&ctx.ac, &ctx.abi, &args->ac, shaders[i]);
4124
4125 if (shader_count >= 2 || is_ngg) {
4126 LLVMBuildBr(ctx.ac.builder, merge_block);
4127 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
4128 }
4129
4130 /* This needs to be outside the if wrapping the shader body, as sometimes
4131 * the HW generates waves with 0 es/vs threads. */
4132 if (is_pre_gs_stage(shaders[i]->info.stage) &&
4133 args->options->key.vs_common_out.as_ngg &&
4134 i == shader_count - 1) {
4135 handle_ngg_outputs_post_2(&ctx);
4136 } else if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
4137 args->options->key.vs_common_out.as_ngg) {
4138 gfx10_ngg_gs_emit_epilogue_2(&ctx);
4139 }
4140
4141 if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
4142 unsigned tcs_num_outputs = util_last_bit64(ctx.args->shader_info->tcs.outputs_written);
4143 unsigned tcs_num_patch_outputs = util_last_bit64(ctx.args->shader_info->tcs.patch_outputs_written);
4144 args->shader_info->tcs.num_patches = ctx.tcs_num_patches;
4145 args->shader_info->tcs.num_lds_blocks =
4146 calculate_tess_lds_size(
4147 ctx.args->options->chip_class,
4148 ctx.args->options->key.tcs.input_vertices,
4149 ctx.shader->info.tess.tcs_vertices_out,
4150 ctx.tcs_num_inputs,
4151 ctx.tcs_num_patches,
4152 tcs_num_outputs,
4153 tcs_num_patch_outputs);
4154 }
4155 }
4156
4157 LLVMBuildRetVoid(ctx.ac.builder);
4158
4159 if (args->options->dump_preoptir) {
4160 fprintf(stderr, "%s LLVM IR:\n\n",
4161 radv_get_shader_name(args->shader_info,
4162 shaders[shader_count - 1]->info.stage));
4163 ac_dump_module(ctx.ac.module);
4164 fprintf(stderr, "\n");
4165 }
4166
4167 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, args->options);
4168
4169 if (shader_count == 1)
4170 ac_nir_eliminate_const_vs_outputs(&ctx);
4171
4172 if (args->options->dump_shader) {
4173 args->shader_info->private_mem_vgprs =
4174 ac_count_scratch_private_memory(ctx.main_function);
4175 }
4176
4177 return ctx.ac.module;
4178 }
4179
4180 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
4181 {
4182 unsigned *retval = (unsigned *)context;
4183 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
4184 char *description = LLVMGetDiagInfoDescription(di);
4185
4186 if (severity == LLVMDSError) {
4187 *retval = 1;
4188 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
4189 description);
4190 }
4191
4192 LLVMDisposeMessage(description);
4193 }
4194
4195 static unsigned radv_llvm_compile(LLVMModuleRef M,
4196 char **pelf_buffer, size_t *pelf_size,
4197 struct ac_llvm_compiler *ac_llvm)
4198 {
4199 unsigned retval = 0;
4200 LLVMContextRef llvm_ctx;
4201
4202 /* Setup Diagnostic Handler*/
4203 llvm_ctx = LLVMGetModuleContext(M);
4204
4205 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
4206 &retval);
4207
4208 /* Compile IR*/
4209 if (!radv_compile_to_elf(ac_llvm, M, pelf_buffer, pelf_size))
4210 retval = 1;
4211 return retval;
4212 }
4213
4214 static void ac_compile_llvm_module(struct ac_llvm_compiler *ac_llvm,
4215 LLVMModuleRef llvm_module,
4216 struct radv_shader_binary **rbinary,
4217 gl_shader_stage stage,
4218 const char *name,
4219 const struct radv_nir_compiler_options *options)
4220 {
4221 char *elf_buffer = NULL;
4222 size_t elf_size = 0;
4223 char *llvm_ir_string = NULL;
4224
4225 if (options->dump_shader) {
4226 fprintf(stderr, "%s LLVM IR:\n\n", name);
4227 ac_dump_module(llvm_module);
4228 fprintf(stderr, "\n");
4229 }
4230
4231 if (options->record_ir) {
4232 char *llvm_ir = LLVMPrintModuleToString(llvm_module);
4233 llvm_ir_string = strdup(llvm_ir);
4234 LLVMDisposeMessage(llvm_ir);
4235 }
4236
4237 int v = radv_llvm_compile(llvm_module, &elf_buffer, &elf_size, ac_llvm);
4238 if (v) {
4239 fprintf(stderr, "compile failed\n");
4240 }
4241
4242 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
4243 LLVMDisposeModule(llvm_module);
4244 LLVMContextDispose(ctx);
4245
4246 size_t llvm_ir_size = llvm_ir_string ? strlen(llvm_ir_string) : 0;
4247 size_t alloc_size = sizeof(struct radv_shader_binary_rtld) + elf_size + llvm_ir_size + 1;
4248 struct radv_shader_binary_rtld *rbin = calloc(1, alloc_size);
4249 memcpy(rbin->data, elf_buffer, elf_size);
4250 if (llvm_ir_string)
4251 memcpy(rbin->data + elf_size, llvm_ir_string, llvm_ir_size + 1);
4252
4253 rbin->base.type = RADV_BINARY_TYPE_RTLD;
4254 rbin->base.stage = stage;
4255 rbin->base.total_size = alloc_size;
4256 rbin->elf_size = elf_size;
4257 rbin->llvm_ir_size = llvm_ir_size;
4258 *rbinary = &rbin->base;
4259
4260 free(llvm_ir_string);
4261 free(elf_buffer);
4262 }
4263
4264 static void
4265 radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
4266 struct radv_shader_binary **rbinary,
4267 const struct radv_shader_args *args,
4268 struct nir_shader *const *nir,
4269 int nir_count)
4270 {
4271
4272 LLVMModuleRef llvm_module;
4273
4274 llvm_module = ac_translate_nir_to_llvm(ac_llvm, nir, nir_count, args);
4275
4276 ac_compile_llvm_module(ac_llvm, llvm_module, rbinary,
4277 nir[nir_count - 1]->info.stage,
4278 radv_get_shader_name(args->shader_info,
4279 nir[nir_count - 1]->info.stage),
4280 args->options);
4281
4282 /* Determine the ES type (VS or TES) for the GS on GFX9. */
4283 if (args->options->chip_class >= GFX9) {
4284 if (nir_count == 2 &&
4285 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
4286 args->shader_info->gs.es_type = nir[0]->info.stage;
4287 }
4288 }
4289 }
4290
4291 static void
4292 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
4293 {
4294 LLVMValueRef vtx_offset =
4295 LLVMBuildMul(ctx->ac.builder, ac_get_arg(&ctx->ac, ctx->args->ac.vertex_id),
4296 LLVMConstInt(ctx->ac.i32, 4, false), "");
4297 LLVMValueRef stream_id;
4298
4299 /* Fetch the vertex stream ID. */
4300 if (!ctx->args->options->use_ngg_streamout &&
4301 ctx->args->shader_info->so.num_outputs) {
4302 stream_id =
4303 ac_unpack_param(&ctx->ac,
4304 ac_get_arg(&ctx->ac,
4305 ctx->args->streamout_config),
4306 24, 2);
4307 } else {
4308 stream_id = ctx->ac.i32_0;
4309 }
4310
4311 LLVMBasicBlockRef end_bb;
4312 LLVMValueRef switch_inst;
4313
4314 end_bb = LLVMAppendBasicBlockInContext(ctx->ac.context,
4315 ctx->main_function, "end");
4316 switch_inst = LLVMBuildSwitch(ctx->ac.builder, stream_id, end_bb, 4);
4317
4318 for (unsigned stream = 0; stream < 4; stream++) {
4319 unsigned num_components =
4320 ctx->args->shader_info->gs.num_stream_output_components[stream];
4321 LLVMBasicBlockRef bb;
4322 unsigned offset;
4323
4324 if (stream > 0 && !num_components)
4325 continue;
4326
4327 if (stream > 0 && !ctx->args->shader_info->so.num_outputs)
4328 continue;
4329
4330 bb = LLVMInsertBasicBlockInContext(ctx->ac.context, end_bb, "out");
4331 LLVMAddCase(switch_inst, LLVMConstInt(ctx->ac.i32, stream, 0), bb);
4332 LLVMPositionBuilderAtEnd(ctx->ac.builder, bb);
4333
4334 offset = 0;
4335 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
4336 unsigned output_usage_mask =
4337 ctx->args->shader_info->gs.output_usage_mask[i];
4338 unsigned output_stream =
4339 ctx->args->shader_info->gs.output_streams[i];
4340 int length = util_last_bit(output_usage_mask);
4341
4342 if (!(ctx->output_mask & (1ull << i)) ||
4343 output_stream != stream)
4344 continue;
4345
4346 for (unsigned j = 0; j < length; j++) {
4347 LLVMValueRef value, soffset;
4348
4349 if (!(output_usage_mask & (1 << j)))
4350 continue;
4351
4352 soffset = LLVMConstInt(ctx->ac.i32,
4353 offset *
4354 ctx->shader->info.gs.vertices_out * 16 * 4, false);
4355
4356 offset++;
4357
4358 value = ac_build_buffer_load(&ctx->ac,
4359 ctx->gsvs_ring[0],
4360 1, ctx->ac.i32_0,
4361 vtx_offset, soffset,
4362 0, ac_glc | ac_slc, true, false);
4363
4364 LLVMTypeRef type = LLVMGetAllocatedType(ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
4365 if (ac_get_type_size(type) == 2) {
4366 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
4367 value = LLVMBuildTrunc(ctx->ac.builder, value, ctx->ac.i16, "");
4368 }
4369
4370 LLVMBuildStore(ctx->ac.builder,
4371 ac_to_float(&ctx->ac, value), ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
4372 }
4373 }
4374
4375 if (!ctx->args->options->use_ngg_streamout &&
4376 ctx->args->shader_info->so.num_outputs)
4377 radv_emit_streamout(ctx, stream);
4378
4379 if (stream == 0) {
4380 handle_vs_outputs_post(ctx, false, true,
4381 &ctx->args->shader_info->vs.outinfo);
4382 }
4383
4384 LLVMBuildBr(ctx->ac.builder, end_bb);
4385 }
4386
4387 LLVMPositionBuilderAtEnd(ctx->ac.builder, end_bb);
4388 }
4389
4390 static void
4391 radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
4392 struct nir_shader *geom_shader,
4393 struct radv_shader_binary **rbinary,
4394 const struct radv_shader_args *args)
4395 {
4396 struct radv_shader_context ctx = {0};
4397 ctx.args = args;
4398
4399 assert(args->is_gs_copy_shader);
4400
4401 ac_llvm_context_init(&ctx.ac, ac_llvm, args->options->chip_class,
4402 args->options->family, AC_FLOAT_MODE_DEFAULT, 64, 64);
4403 ctx.context = ctx.ac.context;
4404
4405 ctx.stage = MESA_SHADER_VERTEX;
4406 ctx.shader = geom_shader;
4407
4408 create_function(&ctx, MESA_SHADER_VERTEX, false);
4409
4410 ac_setup_rings(&ctx);
4411
4412 nir_foreach_variable(variable, &geom_shader->outputs) {
4413 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
4414 ac_handle_shader_output_decl(&ctx.ac, &ctx.abi, geom_shader,
4415 variable, MESA_SHADER_VERTEX);
4416 }
4417
4418 ac_gs_copy_shader_emit(&ctx);
4419
4420 LLVMBuildRetVoid(ctx.ac.builder);
4421
4422 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, args->options);
4423
4424 ac_compile_llvm_module(ac_llvm, ctx.ac.module, rbinary,
4425 MESA_SHADER_VERTEX, "GS Copy Shader", args->options);
4426 (*rbinary)->is_gs_copy_shader = true;
4427
4428 }
4429
4430 void
4431 llvm_compile_shader(struct radv_device *device,
4432 unsigned shader_count,
4433 struct nir_shader *const *shaders,
4434 struct radv_shader_binary **binary,
4435 struct radv_shader_args *args)
4436 {
4437 enum ac_target_machine_options tm_options = 0;
4438 struct ac_llvm_compiler ac_llvm;
4439 bool thread_compiler;
4440
4441 tm_options |= AC_TM_SUPPORTS_SPILL;
4442 if (args->options->check_ir)
4443 tm_options |= AC_TM_CHECK_IR;
4444
4445 thread_compiler = !(device->instance->debug_flags & RADV_DEBUG_NOTHREADLLVM);
4446
4447 radv_init_llvm_compiler(&ac_llvm, thread_compiler,
4448 args->options->family, tm_options,
4449 args->shader_info->wave_size);
4450
4451 if (args->is_gs_copy_shader) {
4452 radv_compile_gs_copy_shader(&ac_llvm, *shaders, binary, args);
4453 } else {
4454 radv_compile_nir_shader(&ac_llvm, binary, args,
4455 shaders, shader_count);
4456 }
4457
4458 radv_destroy_llvm_compiler(&ac_llvm, thread_compiler);
4459 }