2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "radv_shader_helper.h"
31 #include "radv_shader_args.h"
34 #include <llvm-c/Core.h>
35 #include <llvm-c/TargetMachine.h>
36 #include <llvm-c/Transforms/Scalar.h>
37 #include <llvm-c/Transforms/Utils.h>
40 #include "ac_binary.h"
41 #include "ac_llvm_util.h"
42 #include "ac_llvm_build.h"
43 #include "ac_shader_abi.h"
44 #include "ac_shader_util.h"
45 #include "ac_exp_param.h"
47 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
49 struct radv_shader_context
{
50 struct ac_llvm_context ac
;
51 const struct nir_shader
*shader
;
52 struct ac_shader_abi abi
;
53 const struct radv_shader_args
*args
;
55 gl_shader_stage stage
;
57 unsigned max_workgroup_size
;
58 LLVMContextRef context
;
59 LLVMValueRef main_function
;
61 LLVMValueRef descriptor_sets
[MAX_SETS
];
63 LLVMValueRef ring_offsets
;
65 LLVMValueRef rel_auto_id
;
67 LLVMValueRef gs_wave_id
;
68 LLVMValueRef gs_vtx_offset
[6];
70 LLVMValueRef esgs_ring
;
71 LLVMValueRef gsvs_ring
[4];
72 LLVMValueRef hs_ring_tess_offchip
;
73 LLVMValueRef hs_ring_tess_factor
;
75 LLVMValueRef inputs
[RADEON_LLVM_MAX_INPUTS
* 4];
79 LLVMValueRef gs_next_vertex
[4];
80 LLVMValueRef gs_curprim_verts
[4];
81 LLVMValueRef gs_generated_prims
[4];
82 LLVMValueRef gs_ngg_emit
;
83 LLVMValueRef gs_ngg_scratch
;
85 uint32_t tcs_num_inputs
;
86 uint32_t tcs_num_patches
;
88 LLVMValueRef vertexptr
; /* GFX10 only */
91 struct radv_shader_output_values
{
92 LLVMValueRef values
[4];
98 static inline struct radv_shader_context
*
99 radv_shader_context_from_abi(struct ac_shader_abi
*abi
)
101 struct radv_shader_context
*ctx
= NULL
;
102 return container_of(abi
, ctx
, abi
);
105 static LLVMValueRef
get_rel_patch_id(struct radv_shader_context
*ctx
)
107 switch (ctx
->stage
) {
108 case MESA_SHADER_TESS_CTRL
:
109 return ac_unpack_param(&ctx
->ac
,
110 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.tcs_rel_ids
),
112 case MESA_SHADER_TESS_EVAL
:
113 return ac_get_arg(&ctx
->ac
, ctx
->args
->tes_rel_patch_id
);
116 unreachable("Illegal stage");
121 get_tcs_num_patches(struct radv_shader_context
*ctx
)
123 unsigned num_tcs_input_cp
= ctx
->args
->options
->key
.tcs
.input_vertices
;
124 unsigned num_tcs_output_cp
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
125 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
126 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
127 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
128 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.patch_outputs_written
);
129 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
130 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
131 uint32_t output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
132 unsigned num_patches
;
133 unsigned hardware_lds_size
;
135 /* Ensure that we only need one wave per SIMD so we don't need to check
136 * resource usage. Also ensures that the number of tcs in and out
137 * vertices per threadgroup are at most 256.
139 num_patches
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
) * 4;
140 /* Make sure that the data fits in LDS. This assumes the shaders only
141 * use LDS for the inputs and outputs.
143 hardware_lds_size
= 32768;
145 /* Looks like STONEY hangs if we use more than 32 KiB LDS in a single
146 * threadgroup, even though there is more than 32 KiB LDS.
148 * Test: dEQP-VK.tessellation.shader_input_output.barrier
150 if (ctx
->args
->options
->chip_class
>= GFX7
&& ctx
->args
->options
->family
!= CHIP_STONEY
)
151 hardware_lds_size
= 65536;
153 num_patches
= MIN2(num_patches
, hardware_lds_size
/ (input_patch_size
+ output_patch_size
));
154 /* Make sure the output data fits in the offchip buffer */
155 num_patches
= MIN2(num_patches
, (ctx
->args
->options
->tess_offchip_block_dw_size
* 4) / output_patch_size
);
156 /* Not necessary for correctness, but improves performance. The
157 * specific value is taken from the proprietary driver.
159 num_patches
= MIN2(num_patches
, 40);
161 /* GFX6 bug workaround - limit LS-HS threadgroups to only one wave. */
162 if (ctx
->args
->options
->chip_class
== GFX6
) {
163 unsigned one_wave
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
);
164 num_patches
= MIN2(num_patches
, one_wave
);
170 calculate_tess_lds_size(struct radv_shader_context
*ctx
)
172 unsigned num_tcs_input_cp
= ctx
->args
->options
->key
.tcs
.input_vertices
;
173 unsigned num_tcs_output_cp
;
174 unsigned num_tcs_outputs
, num_tcs_patch_outputs
;
175 unsigned input_vertex_size
, output_vertex_size
;
176 unsigned input_patch_size
, output_patch_size
;
177 unsigned pervertex_output_patch_size
;
178 unsigned output_patch0_offset
;
179 unsigned num_patches
;
182 num_tcs_output_cp
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
183 num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
184 num_tcs_patch_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.patch_outputs_written
);
186 input_vertex_size
= ctx
->tcs_num_inputs
* 16;
187 output_vertex_size
= num_tcs_outputs
* 16;
189 input_patch_size
= num_tcs_input_cp
* input_vertex_size
;
191 pervertex_output_patch_size
= num_tcs_output_cp
* output_vertex_size
;
192 output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
194 num_patches
= ctx
->tcs_num_patches
;
195 output_patch0_offset
= input_patch_size
* num_patches
;
197 lds_size
= output_patch0_offset
+ output_patch_size
* num_patches
;
201 /* Tessellation shaders pass outputs to the next shader using LDS.
203 * LS outputs = TCS inputs
204 * TCS outputs = TES inputs
207 * - TCS inputs for patch 0
208 * - TCS inputs for patch 1
209 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
211 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
212 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
213 * - TCS outputs for patch 1
214 * - Per-patch TCS outputs for patch 1
215 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
216 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
219 * All three shaders VS(LS), TCS, TES share the same LDS space.
222 get_tcs_in_patch_stride(struct radv_shader_context
*ctx
)
224 assert(ctx
->stage
== MESA_SHADER_TESS_CTRL
);
225 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
226 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
228 input_patch_size
/= 4;
229 return LLVMConstInt(ctx
->ac
.i32
, input_patch_size
, false);
233 get_tcs_out_patch_stride(struct radv_shader_context
*ctx
)
235 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
236 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.patch_outputs_written
);
237 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
238 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
239 uint32_t output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
240 output_patch_size
/= 4;
241 return LLVMConstInt(ctx
->ac
.i32
, output_patch_size
, false);
245 get_tcs_out_vertex_stride(struct radv_shader_context
*ctx
)
247 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
248 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
249 output_vertex_size
/= 4;
250 return LLVMConstInt(ctx
->ac
.i32
, output_vertex_size
, false);
254 get_tcs_out_patch0_offset(struct radv_shader_context
*ctx
)
256 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
257 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
258 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
259 uint32_t output_patch0_offset
= input_patch_size
;
260 unsigned num_patches
= ctx
->tcs_num_patches
;
262 output_patch0_offset
*= num_patches
;
263 output_patch0_offset
/= 4;
264 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
268 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context
*ctx
)
270 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
271 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
272 uint32_t input_patch_size
= ctx
->args
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
273 uint32_t output_patch0_offset
= input_patch_size
;
275 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
276 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
277 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
278 unsigned num_patches
= ctx
->tcs_num_patches
;
280 output_patch0_offset
*= num_patches
;
281 output_patch0_offset
+= pervertex_output_patch_size
;
282 output_patch0_offset
/= 4;
283 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
287 get_tcs_in_current_patch_offset(struct radv_shader_context
*ctx
)
289 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
290 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
292 return LLVMBuildMul(ctx
->ac
.builder
, patch_stride
, rel_patch_id
, "");
296 get_tcs_out_current_patch_offset(struct radv_shader_context
*ctx
)
298 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
299 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
300 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
302 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
,
307 get_tcs_out_current_patch_data_offset(struct radv_shader_context
*ctx
)
309 LLVMValueRef patch0_patch_data_offset
=
310 get_tcs_out_patch0_patch_data_offset(ctx
);
311 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
312 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
314 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
,
315 patch0_patch_data_offset
);
319 create_llvm_function(struct ac_llvm_context
*ctx
, LLVMModuleRef module
,
320 LLVMBuilderRef builder
,
321 const struct ac_shader_args
*args
,
322 enum ac_llvm_calling_convention convention
,
323 unsigned max_workgroup_size
,
324 const struct radv_nir_compiler_options
*options
)
326 LLVMValueRef main_function
=
327 ac_build_main(args
, ctx
, convention
, "main", ctx
->voidt
, module
);
329 if (options
->address32_hi
) {
330 ac_llvm_add_target_dep_function_attr(main_function
,
331 "amdgpu-32bit-address-high-bits",
332 options
->address32_hi
);
335 ac_llvm_set_workgroup_size(main_function
, max_workgroup_size
);
337 return main_function
;
341 load_descriptor_sets(struct radv_shader_context
*ctx
)
343 uint32_t mask
= ctx
->args
->shader_info
->desc_set_used_mask
;
344 if (ctx
->args
->shader_info
->need_indirect_descriptor_sets
) {
345 LLVMValueRef desc_sets
=
346 ac_get_arg(&ctx
->ac
, ctx
->args
->descriptor_sets
[0]);
348 int i
= u_bit_scan(&mask
);
350 ctx
->descriptor_sets
[i
] =
351 ac_build_load_to_sgpr(&ctx
->ac
, desc_sets
,
352 LLVMConstInt(ctx
->ac
.i32
, i
, false));
357 int i
= u_bit_scan(&mask
);
359 ctx
->descriptor_sets
[i
] =
360 ac_get_arg(&ctx
->ac
, ctx
->args
->descriptor_sets
[i
]);
365 static enum ac_llvm_calling_convention
366 get_llvm_calling_convention(LLVMValueRef func
, gl_shader_stage stage
)
369 case MESA_SHADER_VERTEX
:
370 case MESA_SHADER_TESS_EVAL
:
371 return AC_LLVM_AMDGPU_VS
;
373 case MESA_SHADER_GEOMETRY
:
374 return AC_LLVM_AMDGPU_GS
;
376 case MESA_SHADER_TESS_CTRL
:
377 return AC_LLVM_AMDGPU_HS
;
379 case MESA_SHADER_FRAGMENT
:
380 return AC_LLVM_AMDGPU_PS
;
382 case MESA_SHADER_COMPUTE
:
383 return AC_LLVM_AMDGPU_CS
;
386 unreachable("Unhandle shader type");
390 /* Returns whether the stage is a stage that can be directly before the GS */
391 static bool is_pre_gs_stage(gl_shader_stage stage
)
393 return stage
== MESA_SHADER_VERTEX
|| stage
== MESA_SHADER_TESS_EVAL
;
396 static void create_function(struct radv_shader_context
*ctx
,
397 gl_shader_stage stage
,
398 bool has_previous_stage
)
400 if (ctx
->ac
.chip_class
>= GFX10
) {
401 if (is_pre_gs_stage(stage
) && ctx
->args
->options
->key
.vs_common_out
.as_ngg
) {
402 /* On GFX10, VS is merged into GS for NGG. */
403 stage
= MESA_SHADER_GEOMETRY
;
404 has_previous_stage
= true;
408 ctx
->main_function
= create_llvm_function(
409 &ctx
->ac
, ctx
->ac
.module
, ctx
->ac
.builder
, &ctx
->args
->ac
,
410 get_llvm_calling_convention(ctx
->main_function
, stage
),
411 ctx
->max_workgroup_size
,
414 ctx
->ring_offsets
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.implicit.buffer.ptr",
415 LLVMPointerType(ctx
->ac
.i8
, AC_ADDR_SPACE_CONST
),
416 NULL
, 0, AC_FUNC_ATTR_READNONE
);
417 ctx
->ring_offsets
= LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->ring_offsets
,
418 ac_array_in_const_addr_space(ctx
->ac
.v4i32
), "");
420 load_descriptor_sets(ctx
);
422 if (stage
== MESA_SHADER_TESS_CTRL
||
423 (stage
== MESA_SHADER_VERTEX
&& ctx
->args
->options
->key
.vs_common_out
.as_ls
) ||
424 /* GFX9 has the ESGS ring buffer in LDS. */
425 (stage
== MESA_SHADER_GEOMETRY
&& has_previous_stage
)) {
426 ac_declare_lds_as_pointer(&ctx
->ac
);
433 radv_load_resource(struct ac_shader_abi
*abi
, LLVMValueRef index
,
434 unsigned desc_set
, unsigned binding
)
436 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
437 LLVMValueRef desc_ptr
= ctx
->descriptor_sets
[desc_set
];
438 struct radv_pipeline_layout
*pipeline_layout
= ctx
->args
->options
->layout
;
439 struct radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
440 unsigned base_offset
= layout
->binding
[binding
].offset
;
441 LLVMValueRef offset
, stride
;
443 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
444 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
445 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+
446 layout
->binding
[binding
].dynamic_offset_offset
;
447 desc_ptr
= ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.push_constants
);
448 base_offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
449 stride
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
451 stride
= LLVMConstInt(ctx
->ac
.i32
, layout
->binding
[binding
].size
, false);
453 offset
= LLVMConstInt(ctx
->ac
.i32
, base_offset
, false);
455 if (layout
->binding
[binding
].type
!= VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
456 offset
= ac_build_imad(&ctx
->ac
, index
, stride
, offset
);
459 desc_ptr
= LLVMBuildGEP(ctx
->ac
.builder
, desc_ptr
, &offset
, 1, "");
460 desc_ptr
= ac_cast_ptr(&ctx
->ac
, desc_ptr
, ctx
->ac
.v4i32
);
461 LLVMSetMetadata(desc_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
463 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
464 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
465 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
466 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
467 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
469 if (ctx
->ac
.chip_class
>= GFX10
) {
470 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
471 S_008F0C_OOB_SELECT(3) |
472 S_008F0C_RESOURCE_LEVEL(1);
474 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
475 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
478 LLVMValueRef desc_components
[4] = {
479 LLVMBuildPtrToInt(ctx
->ac
.builder
, desc_ptr
, ctx
->ac
.intptr
, ""),
480 LLVMConstInt(ctx
->ac
.i32
, S_008F04_BASE_ADDRESS_HI(ctx
->args
->options
->address32_hi
), false),
481 /* High limit to support variable sizes. */
482 LLVMConstInt(ctx
->ac
.i32
, 0xffffffff, false),
483 LLVMConstInt(ctx
->ac
.i32
, desc_type
, false),
486 return ac_build_gather_values(&ctx
->ac
, desc_components
, 4);
493 /* The offchip buffer layout for TCS->TES is
495 * - attribute 0 of patch 0 vertex 0
496 * - attribute 0 of patch 0 vertex 1
497 * - attribute 0 of patch 0 vertex 2
499 * - attribute 0 of patch 1 vertex 0
500 * - attribute 0 of patch 1 vertex 1
502 * - attribute 1 of patch 0 vertex 0
503 * - attribute 1 of patch 0 vertex 1
505 * - per patch attribute 0 of patch 0
506 * - per patch attribute 0 of patch 1
509 * Note that every attribute has 4 components.
511 static LLVMValueRef
get_non_vertex_index_offset(struct radv_shader_context
*ctx
)
513 uint32_t num_patches
= ctx
->tcs_num_patches
;
514 uint32_t num_tcs_outputs
;
515 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
516 num_tcs_outputs
= util_last_bit64(ctx
->args
->shader_info
->tcs
.outputs_written
);
518 num_tcs_outputs
= ctx
->args
->options
->key
.tes
.tcs_num_outputs
;
520 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
521 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
523 return LLVMConstInt(ctx
->ac
.i32
, pervertex_output_patch_size
* num_patches
, false);
526 static LLVMValueRef
calc_param_stride(struct radv_shader_context
*ctx
,
527 LLVMValueRef vertex_index
)
529 LLVMValueRef param_stride
;
531 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.tess
.tcs_vertices_out
* ctx
->tcs_num_patches
, false);
533 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_num_patches
, false);
537 static LLVMValueRef
get_tcs_tes_buffer_address(struct radv_shader_context
*ctx
,
538 LLVMValueRef vertex_index
,
539 LLVMValueRef param_index
)
541 LLVMValueRef base_addr
;
542 LLVMValueRef param_stride
, constant16
;
543 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
544 LLVMValueRef vertices_per_patch
= LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.tess
.tcs_vertices_out
, false);
545 constant16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
546 param_stride
= calc_param_stride(ctx
, vertex_index
);
548 base_addr
= ac_build_imad(&ctx
->ac
, rel_patch_id
,
549 vertices_per_patch
, vertex_index
);
551 base_addr
= rel_patch_id
;
554 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
555 LLVMBuildMul(ctx
->ac
.builder
, param_index
,
556 param_stride
, ""), "");
558 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, base_addr
, constant16
, "");
561 LLVMValueRef patch_data_offset
= get_non_vertex_index_offset(ctx
);
563 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
564 patch_data_offset
, "");
569 static LLVMValueRef
get_tcs_tes_buffer_address_params(struct radv_shader_context
*ctx
,
571 unsigned const_index
,
573 LLVMValueRef vertex_index
,
574 LLVMValueRef indir_index
)
576 LLVMValueRef param_index
;
579 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, param
, false),
582 if (const_index
&& !is_compact
)
583 param
+= const_index
;
584 param_index
= LLVMConstInt(ctx
->ac
.i32
, param
, false);
586 return get_tcs_tes_buffer_address(ctx
, vertex_index
, param_index
);
590 get_dw_address(struct radv_shader_context
*ctx
,
591 LLVMValueRef dw_addr
,
593 unsigned const_index
,
594 bool compact_const_index
,
595 LLVMValueRef vertex_index
,
597 LLVMValueRef indir_index
)
602 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
603 LLVMBuildMul(ctx
->ac
.builder
,
609 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
610 LLVMBuildMul(ctx
->ac
.builder
, indir_index
,
611 LLVMConstInt(ctx
->ac
.i32
, 4, false), ""), "");
612 else if (const_index
&& !compact_const_index
)
613 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
614 LLVMConstInt(ctx
->ac
.i32
, const_index
* 4, false), "");
616 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
617 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false), "");
619 if (const_index
&& compact_const_index
)
620 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
621 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
626 load_tcs_varyings(struct ac_shader_abi
*abi
,
628 LLVMValueRef vertex_index
,
629 LLVMValueRef indir_index
,
630 unsigned const_index
,
632 unsigned driver_location
,
634 unsigned num_components
,
639 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
640 LLVMValueRef dw_addr
, stride
;
641 LLVMValueRef value
[4], result
;
642 unsigned param
= shader_io_get_unique_index(location
);
645 uint32_t input_vertex_size
= (ctx
->tcs_num_inputs
* 16) / 4;
646 stride
= LLVMConstInt(ctx
->ac
.i32
, input_vertex_size
, false);
647 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
650 stride
= get_tcs_out_vertex_stride(ctx
);
651 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
653 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
658 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
661 for (unsigned i
= 0; i
< num_components
+ component
; i
++) {
662 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
663 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
666 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
671 store_tcs_output(struct ac_shader_abi
*abi
,
672 const nir_variable
*var
,
673 LLVMValueRef vertex_index
,
674 LLVMValueRef param_index
,
675 unsigned const_index
,
679 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
680 const unsigned location
= var
->data
.location
;
681 unsigned component
= var
->data
.location_frac
;
682 const bool is_patch
= var
->data
.patch
;
683 const bool is_compact
= var
->data
.compact
;
684 LLVMValueRef dw_addr
;
685 LLVMValueRef stride
= NULL
;
686 LLVMValueRef buf_addr
= NULL
;
687 LLVMValueRef oc_lds
= ac_get_arg(&ctx
->ac
, ctx
->args
->oc_lds
);
689 bool store_lds
= true;
692 if (!(ctx
->shader
->info
.patch_outputs_read
& (1U << (location
- VARYING_SLOT_PATCH0
))))
695 if (!(ctx
->shader
->info
.outputs_read
& (1ULL << location
)))
699 param
= shader_io_get_unique_index(location
);
700 if ((location
== VARYING_SLOT_CLIP_DIST0
|| location
== VARYING_SLOT_CLIP_DIST1
) && is_compact
) {
701 const_index
+= component
;
704 if (const_index
>= 4) {
711 stride
= get_tcs_out_vertex_stride(ctx
);
712 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
714 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
717 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
719 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
, is_compact
,
720 vertex_index
, param_index
);
722 bool is_tess_factor
= false;
723 if (location
== VARYING_SLOT_TESS_LEVEL_INNER
||
724 location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
725 is_tess_factor
= true;
727 unsigned base
= is_compact
? const_index
: 0;
728 for (unsigned chan
= 0; chan
< 8; chan
++) {
729 if (!(writemask
& (1 << chan
)))
731 LLVMValueRef value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- component
);
732 value
= ac_to_integer(&ctx
->ac
, value
);
733 value
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
735 if (store_lds
|| is_tess_factor
) {
736 LLVMValueRef dw_addr_chan
=
737 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
738 LLVMConstInt(ctx
->ac
.i32
, chan
, false), "");
739 ac_lds_store(&ctx
->ac
, dw_addr_chan
, value
);
742 if (!is_tess_factor
&& writemask
!= 0xF)
743 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, value
, 1,
745 4 * (base
+ chan
), ac_glc
);
748 if (writemask
== 0xF) {
749 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, src
, 4,
756 load_tes_input(struct ac_shader_abi
*abi
,
758 LLVMValueRef vertex_index
,
759 LLVMValueRef param_index
,
760 unsigned const_index
,
762 unsigned driver_location
,
764 unsigned num_components
,
769 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
770 LLVMValueRef buf_addr
;
772 LLVMValueRef oc_lds
= ac_get_arg(&ctx
->ac
, ctx
->args
->oc_lds
);
773 unsigned param
= shader_io_get_unique_index(location
);
775 if ((location
== VARYING_SLOT_CLIP_DIST0
|| location
== VARYING_SLOT_CLIP_DIST1
) && is_compact
) {
776 const_index
+= component
;
778 if (const_index
>= 4) {
784 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
,
785 is_compact
, vertex_index
, param_index
);
787 LLVMValueRef comp_offset
= LLVMConstInt(ctx
->ac
.i32
, component
* 4, false);
788 buf_addr
= LLVMBuildAdd(ctx
->ac
.builder
, buf_addr
, comp_offset
, "");
790 result
= ac_build_buffer_load(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, num_components
, NULL
,
791 buf_addr
, oc_lds
, is_compact
? (4 * const_index
) : 0, ac_glc
, true, false);
792 result
= ac_trim_vector(&ctx
->ac
, result
, num_components
);
797 radv_emit_fetch_64bit(struct radv_shader_context
*ctx
,
798 LLVMTypeRef type
, LLVMValueRef a
, LLVMValueRef b
)
800 LLVMValueRef values
[2] = {
801 ac_to_integer(&ctx
->ac
, a
),
802 ac_to_integer(&ctx
->ac
, b
),
804 LLVMValueRef result
= ac_build_gather_values(&ctx
->ac
, values
, 2);
805 return LLVMBuildBitCast(ctx
->ac
.builder
, result
, type
, "");
809 load_gs_input(struct ac_shader_abi
*abi
,
811 unsigned driver_location
,
813 unsigned num_components
,
814 unsigned vertex_index
,
815 unsigned const_index
,
818 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
819 LLVMValueRef vtx_offset
;
820 unsigned param
, vtx_offset_param
;
821 LLVMValueRef value
[4], result
;
823 vtx_offset_param
= vertex_index
;
824 assert(vtx_offset_param
< 6);
825 vtx_offset
= LLVMBuildMul(ctx
->ac
.builder
, ctx
->gs_vtx_offset
[vtx_offset_param
],
826 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
828 param
= shader_io_get_unique_index(location
);
830 for (unsigned i
= component
; i
< num_components
+ component
; i
++) {
831 if (ctx
->ac
.chip_class
>= GFX9
) {
832 LLVMValueRef dw_addr
= ctx
->gs_vtx_offset
[vtx_offset_param
];
833 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
834 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
, 0), "");
835 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
837 if (ac_get_type_size(type
) == 8) {
838 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
839 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
+ 1, 0), "");
840 LLVMValueRef tmp
= ac_lds_load(&ctx
->ac
, dw_addr
);
842 value
[i
] = radv_emit_fetch_64bit(ctx
, type
, value
[i
], tmp
);
845 LLVMValueRef soffset
=
846 LLVMConstInt(ctx
->ac
.i32
,
847 (param
* 4 + i
+ const_index
) * 256,
850 value
[i
] = ac_build_buffer_load(&ctx
->ac
,
854 0, ac_glc
, true, false);
856 if (ac_get_type_size(type
) == 8) {
857 soffset
= LLVMConstInt(ctx
->ac
.i32
,
858 (param
* 4 + i
+ const_index
+ 1) * 256,
862 ac_build_buffer_load(&ctx
->ac
,
866 0, ac_glc
, true, false);
868 value
[i
] = radv_emit_fetch_64bit(ctx
, type
, value
[i
], tmp
);
872 if (ac_get_type_size(type
) == 2) {
873 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
], ctx
->ac
.i32
, "");
874 value
[i
] = LLVMBuildTrunc(ctx
->ac
.builder
, value
[i
], ctx
->ac
.i16
, "");
876 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
], type
, "");
878 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
879 result
= ac_to_integer(&ctx
->ac
, result
);
884 static void radv_emit_kill(struct ac_shader_abi
*abi
, LLVMValueRef visible
)
886 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
887 ac_build_kill_if_false(&ctx
->ac
, visible
);
891 radv_get_sample_pos_offset(uint32_t num_samples
)
893 uint32_t sample_pos_offset
= 0;
895 switch (num_samples
) {
897 sample_pos_offset
= 1;
900 sample_pos_offset
= 3;
903 sample_pos_offset
= 7;
908 return sample_pos_offset
;
911 static LLVMValueRef
load_sample_position(struct ac_shader_abi
*abi
,
912 LLVMValueRef sample_id
)
914 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
917 LLVMValueRef index
= LLVMConstInt(ctx
->ac
.i32
, RING_PS_SAMPLE_POSITIONS
, false);
918 LLVMValueRef ptr
= LLVMBuildGEP(ctx
->ac
.builder
, ctx
->ring_offsets
, &index
, 1, "");
920 ptr
= LLVMBuildBitCast(ctx
->ac
.builder
, ptr
,
921 ac_array_in_const_addr_space(ctx
->ac
.v2f32
), "");
923 uint32_t sample_pos_offset
=
924 radv_get_sample_pos_offset(ctx
->args
->options
->key
.fs
.num_samples
);
927 LLVMBuildAdd(ctx
->ac
.builder
, sample_id
,
928 LLVMConstInt(ctx
->ac
.i32
, sample_pos_offset
, false), "");
929 result
= ac_build_load_invariant(&ctx
->ac
, ptr
, sample_id
);
935 static LLVMValueRef
load_sample_mask_in(struct ac_shader_abi
*abi
)
937 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
938 uint8_t log2_ps_iter_samples
;
940 if (ctx
->args
->shader_info
->ps
.force_persample
) {
941 log2_ps_iter_samples
=
942 util_logbase2(ctx
->args
->options
->key
.fs
.num_samples
);
944 log2_ps_iter_samples
= ctx
->args
->options
->key
.fs
.log2_ps_iter_samples
;
947 /* The bit pattern matches that used by fixed function fragment
949 static const uint16_t ps_iter_masks
[] = {
950 0xffff, /* not used */
956 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
958 uint32_t ps_iter_mask
= ps_iter_masks
[log2_ps_iter_samples
];
960 LLVMValueRef result
, sample_id
;
961 sample_id
= ac_unpack_param(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.ancillary
), 8, 4);
962 sample_id
= LLVMBuildShl(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, ps_iter_mask
, false), sample_id
, "");
963 result
= LLVMBuildAnd(ctx
->ac
.builder
, sample_id
,
964 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.sample_coverage
), "");
969 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context
*ctx
,
971 LLVMValueRef
*addrs
);
974 visit_emit_vertex(struct ac_shader_abi
*abi
, unsigned stream
, LLVMValueRef
*addrs
)
976 LLVMValueRef gs_next_vertex
;
977 LLVMValueRef can_emit
;
979 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
981 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg
) {
982 gfx10_ngg_gs_emit_vertex(ctx
, stream
, addrs
);
986 /* Write vertex attribute values to GSVS ring */
987 gs_next_vertex
= LLVMBuildLoad(ctx
->ac
.builder
,
988 ctx
->gs_next_vertex
[stream
],
991 /* If this thread has already emitted the declared maximum number of
992 * vertices, don't emit any more: excessive vertex emissions are not
993 * supposed to have any effect.
995 can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
, gs_next_vertex
,
996 LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.gs
.vertices_out
, false), "");
998 bool use_kill
= !ctx
->args
->shader_info
->gs
.writes_memory
;
1000 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
1002 ac_build_ifcc(&ctx
->ac
, can_emit
, 6505);
1004 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
1005 unsigned output_usage_mask
=
1006 ctx
->args
->shader_info
->gs
.output_usage_mask
[i
];
1007 uint8_t output_stream
=
1008 ctx
->args
->shader_info
->gs
.output_streams
[i
];
1009 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
1010 int length
= util_last_bit(output_usage_mask
);
1012 if (!(ctx
->output_mask
& (1ull << i
)) ||
1013 output_stream
!= stream
)
1016 for (unsigned j
= 0; j
< length
; j
++) {
1017 if (!(output_usage_mask
& (1 << j
)))
1020 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
,
1022 LLVMValueRef voffset
=
1023 LLVMConstInt(ctx
->ac
.i32
, offset
*
1024 ctx
->shader
->info
.gs
.vertices_out
, false);
1028 voffset
= LLVMBuildAdd(ctx
->ac
.builder
, voffset
, gs_next_vertex
, "");
1029 voffset
= LLVMBuildMul(ctx
->ac
.builder
, voffset
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
1031 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
1032 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
1034 ac_build_buffer_store_dword(&ctx
->ac
,
1035 ctx
->gsvs_ring
[stream
],
1038 ac_get_arg(&ctx
->ac
,
1039 ctx
->args
->gs2vs_offset
),
1040 0, ac_glc
| ac_slc
| ac_swizzled
);
1044 gs_next_vertex
= LLVMBuildAdd(ctx
->ac
.builder
, gs_next_vertex
,
1046 LLVMBuildStore(ctx
->ac
.builder
, gs_next_vertex
, ctx
->gs_next_vertex
[stream
]);
1048 ac_build_sendmsg(&ctx
->ac
,
1049 AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (stream
<< 8),
1053 ac_build_endif(&ctx
->ac
, 6505);
1057 visit_end_primitive(struct ac_shader_abi
*abi
, unsigned stream
)
1059 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1061 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg
) {
1062 LLVMBuildStore(ctx
->ac
.builder
, ctx
->ac
.i32_0
, ctx
->gs_curprim_verts
[stream
]);
1066 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (stream
<< 8), ctx
->gs_wave_id
);
1070 load_tess_coord(struct ac_shader_abi
*abi
)
1072 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1074 LLVMValueRef coord
[4] = {
1075 ac_get_arg(&ctx
->ac
, ctx
->args
->tes_u
),
1076 ac_get_arg(&ctx
->ac
, ctx
->args
->tes_v
),
1081 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
)
1082 coord
[2] = LLVMBuildFSub(ctx
->ac
.builder
, ctx
->ac
.f32_1
,
1083 LLVMBuildFAdd(ctx
->ac
.builder
, coord
[0], coord
[1], ""), "");
1085 return ac_build_gather_values(&ctx
->ac
, coord
, 3);
1089 load_patch_vertices_in(struct ac_shader_abi
*abi
)
1091 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1092 return LLVMConstInt(ctx
->ac
.i32
, ctx
->args
->options
->key
.tcs
.input_vertices
, false);
1096 static LLVMValueRef
radv_load_base_vertex(struct ac_shader_abi
*abi
)
1098 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1099 return ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.base_vertex
);
1102 static LLVMValueRef
radv_load_ssbo(struct ac_shader_abi
*abi
,
1103 LLVMValueRef buffer_ptr
, bool write
)
1105 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1106 LLVMValueRef result
;
1108 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1110 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
1111 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
1116 static LLVMValueRef
radv_load_ubo(struct ac_shader_abi
*abi
, LLVMValueRef buffer_ptr
)
1118 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1119 LLVMValueRef result
;
1121 if (LLVMGetTypeKind(LLVMTypeOf(buffer_ptr
)) != LLVMPointerTypeKind
) {
1122 /* Do not load the descriptor for inlined uniform blocks. */
1126 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1128 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
1129 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
1134 static LLVMValueRef
radv_get_sampler_desc(struct ac_shader_abi
*abi
,
1135 unsigned descriptor_set
,
1136 unsigned base_index
,
1137 unsigned constant_index
,
1139 enum ac_descriptor_type desc_type
,
1140 bool image
, bool write
,
1143 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1144 LLVMValueRef list
= ctx
->descriptor_sets
[descriptor_set
];
1145 struct radv_descriptor_set_layout
*layout
= ctx
->args
->options
->layout
->set
[descriptor_set
].layout
;
1146 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
1147 unsigned offset
= binding
->offset
;
1148 unsigned stride
= binding
->size
;
1150 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1153 assert(base_index
< layout
->binding_count
);
1155 switch (desc_type
) {
1157 type
= ctx
->ac
.v8i32
;
1161 type
= ctx
->ac
.v8i32
;
1165 case AC_DESC_SAMPLER
:
1166 type
= ctx
->ac
.v4i32
;
1167 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
) {
1168 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
1173 case AC_DESC_BUFFER
:
1174 type
= ctx
->ac
.v4i32
;
1177 case AC_DESC_PLANE_0
:
1178 case AC_DESC_PLANE_1
:
1179 case AC_DESC_PLANE_2
:
1180 type
= ctx
->ac
.v8i32
;
1182 offset
+= 32 * (desc_type
- AC_DESC_PLANE_0
);
1185 unreachable("invalid desc_type\n");
1188 offset
+= constant_index
* stride
;
1190 if (desc_type
== AC_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
1191 (!index
|| binding
->immutable_samplers_equal
)) {
1192 if (binding
->immutable_samplers_equal
)
1195 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
1197 LLVMValueRef constants
[] = {
1198 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 0], 0),
1199 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 1], 0),
1200 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 2], 0),
1201 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 3], 0),
1203 return ac_build_gather_values(&ctx
->ac
, constants
, 4);
1206 assert(stride
% type_size
== 0);
1208 LLVMValueRef adjusted_index
= index
;
1209 if (!adjusted_index
)
1210 adjusted_index
= ctx
->ac
.i32_0
;
1212 adjusted_index
= LLVMBuildMul(builder
, adjusted_index
, LLVMConstInt(ctx
->ac
.i32
, stride
/ type_size
, 0), "");
1214 LLVMValueRef val_offset
= LLVMConstInt(ctx
->ac
.i32
, offset
, 0);
1215 list
= LLVMBuildGEP(builder
, list
, &val_offset
, 1, "");
1216 list
= LLVMBuildPointerCast(builder
, list
,
1217 ac_array_in_const32_addr_space(type
), "");
1219 LLVMValueRef descriptor
= ac_build_load_to_sgpr(&ctx
->ac
, list
, adjusted_index
);
1221 /* 3 plane formats always have same size and format for plane 1 & 2, so
1222 * use the tail from plane 1 so that we can store only the first 16 bytes
1223 * of the last plane. */
1224 if (desc_type
== AC_DESC_PLANE_2
) {
1225 LLVMValueRef descriptor2
= radv_get_sampler_desc(abi
, descriptor_set
, base_index
, constant_index
, index
, AC_DESC_PLANE_1
,image
, write
, bindless
);
1227 LLVMValueRef components
[8];
1228 for (unsigned i
= 0; i
< 4; ++i
)
1229 components
[i
] = ac_llvm_extract_elem(&ctx
->ac
, descriptor
, i
);
1231 for (unsigned i
= 4; i
< 8; ++i
)
1232 components
[i
] = ac_llvm_extract_elem(&ctx
->ac
, descriptor2
, i
);
1233 descriptor
= ac_build_gather_values(&ctx
->ac
, components
, 8);
1239 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
1240 * so we may need to fix it up. */
1242 adjust_vertex_fetch_alpha(struct radv_shader_context
*ctx
,
1243 unsigned adjustment
,
1246 if (adjustment
== RADV_ALPHA_ADJUST_NONE
)
1249 LLVMValueRef c30
= LLVMConstInt(ctx
->ac
.i32
, 30, 0);
1251 alpha
= LLVMBuildBitCast(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
1253 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
1254 alpha
= LLVMBuildFPToUI(ctx
->ac
.builder
, alpha
, ctx
->ac
.i32
, "");
1256 alpha
= ac_to_integer(&ctx
->ac
, alpha
);
1258 /* For the integer-like cases, do a natural sign extension.
1260 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
1261 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
1264 alpha
= LLVMBuildShl(ctx
->ac
.builder
, alpha
,
1265 adjustment
== RADV_ALPHA_ADJUST_SNORM
?
1266 LLVMConstInt(ctx
->ac
.i32
, 7, 0) : c30
, "");
1267 alpha
= LLVMBuildAShr(ctx
->ac
.builder
, alpha
, c30
, "");
1269 /* Convert back to the right type. */
1270 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
1272 LLVMValueRef neg_one
= LLVMConstReal(ctx
->ac
.f32
, -1.0);
1273 alpha
= LLVMBuildSIToFP(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
1274 clamp
= LLVMBuildFCmp(ctx
->ac
.builder
, LLVMRealULT
, alpha
, neg_one
, "");
1275 alpha
= LLVMBuildSelect(ctx
->ac
.builder
, clamp
, neg_one
, alpha
, "");
1276 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
1277 alpha
= LLVMBuildSIToFP(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
1280 return LLVMBuildBitCast(ctx
->ac
.builder
, alpha
, ctx
->ac
.i32
, "");
1284 get_num_channels_from_data_format(unsigned data_format
)
1286 switch (data_format
) {
1287 case V_008F0C_BUF_DATA_FORMAT_8
:
1288 case V_008F0C_BUF_DATA_FORMAT_16
:
1289 case V_008F0C_BUF_DATA_FORMAT_32
:
1291 case V_008F0C_BUF_DATA_FORMAT_8_8
:
1292 case V_008F0C_BUF_DATA_FORMAT_16_16
:
1293 case V_008F0C_BUF_DATA_FORMAT_32_32
:
1295 case V_008F0C_BUF_DATA_FORMAT_10_11_11
:
1296 case V_008F0C_BUF_DATA_FORMAT_11_11_10
:
1297 case V_008F0C_BUF_DATA_FORMAT_32_32_32
:
1299 case V_008F0C_BUF_DATA_FORMAT_8_8_8_8
:
1300 case V_008F0C_BUF_DATA_FORMAT_10_10_10_2
:
1301 case V_008F0C_BUF_DATA_FORMAT_2_10_10_10
:
1302 case V_008F0C_BUF_DATA_FORMAT_16_16_16_16
:
1303 case V_008F0C_BUF_DATA_FORMAT_32_32_32_32
:
1313 radv_fixup_vertex_input_fetches(struct radv_shader_context
*ctx
,
1315 unsigned num_channels
,
1318 LLVMValueRef zero
= is_float
? ctx
->ac
.f32_0
: ctx
->ac
.i32_0
;
1319 LLVMValueRef one
= is_float
? ctx
->ac
.f32_1
: ctx
->ac
.i32_1
;
1320 LLVMValueRef chan
[4];
1322 if (LLVMGetTypeKind(LLVMTypeOf(value
)) == LLVMVectorTypeKind
) {
1323 unsigned vec_size
= LLVMGetVectorSize(LLVMTypeOf(value
));
1325 if (num_channels
== 4 && num_channels
== vec_size
)
1328 num_channels
= MIN2(num_channels
, vec_size
);
1330 for (unsigned i
= 0; i
< num_channels
; i
++)
1331 chan
[i
] = ac_llvm_extract_elem(&ctx
->ac
, value
, i
);
1333 assert(num_channels
== 1);
1337 for (unsigned i
= num_channels
; i
< 4; i
++) {
1338 chan
[i
] = i
== 3 ? one
: zero
;
1339 chan
[i
] = ac_to_integer(&ctx
->ac
, chan
[i
]);
1342 return ac_build_gather_values(&ctx
->ac
, chan
, 4);
1346 handle_vs_input_decl(struct radv_shader_context
*ctx
,
1347 struct nir_variable
*variable
)
1349 LLVMValueRef t_list_ptr
= ac_get_arg(&ctx
->ac
, ctx
->args
->vertex_buffers
);
1350 LLVMValueRef t_offset
;
1351 LLVMValueRef t_list
;
1353 LLVMValueRef buffer_index
;
1354 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, true);
1355 uint8_t input_usage_mask
=
1356 ctx
->args
->shader_info
->vs
.input_usage_mask
[variable
->data
.location
];
1357 unsigned num_input_channels
= util_last_bit(input_usage_mask
);
1359 variable
->data
.driver_location
= variable
->data
.location
* 4;
1361 enum glsl_base_type type
= glsl_get_base_type(variable
->type
);
1362 for (unsigned i
= 0; i
< attrib_count
; ++i
) {
1363 LLVMValueRef output
[4];
1364 unsigned attrib_index
= variable
->data
.location
+ i
- VERT_ATTRIB_GENERIC0
;
1365 unsigned attrib_format
= ctx
->args
->options
->key
.vs
.vertex_attribute_formats
[attrib_index
];
1366 unsigned data_format
= attrib_format
& 0x0f;
1367 unsigned num_format
= (attrib_format
>> 4) & 0x07;
1368 bool is_float
= num_format
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
1369 num_format
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
1371 if (ctx
->args
->options
->key
.vs
.instance_rate_inputs
& (1u << attrib_index
)) {
1372 uint32_t divisor
= ctx
->args
->options
->key
.vs
.instance_rate_divisors
[attrib_index
];
1375 buffer_index
= ctx
->abi
.instance_id
;
1378 buffer_index
= LLVMBuildUDiv(ctx
->ac
.builder
, buffer_index
,
1379 LLVMConstInt(ctx
->ac
.i32
, divisor
, 0), "");
1382 buffer_index
= ctx
->ac
.i32_0
;
1385 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
,
1386 ac_get_arg(&ctx
->ac
,
1387 ctx
->args
->ac
.start_instance
),\
1390 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
,
1392 ac_get_arg(&ctx
->ac
,
1393 ctx
->args
->ac
.base_vertex
), "");
1396 /* Adjust the number of channels to load based on the vertex
1399 unsigned num_format_channels
= get_num_channels_from_data_format(data_format
);
1400 unsigned num_channels
= MIN2(num_input_channels
, num_format_channels
);
1401 unsigned attrib_binding
= ctx
->args
->options
->key
.vs
.vertex_attribute_bindings
[attrib_index
];
1402 unsigned attrib_offset
= ctx
->args
->options
->key
.vs
.vertex_attribute_offsets
[attrib_index
];
1403 unsigned attrib_stride
= ctx
->args
->options
->key
.vs
.vertex_attribute_strides
[attrib_index
];
1405 if (ctx
->args
->options
->key
.vs
.post_shuffle
& (1 << attrib_index
)) {
1406 /* Always load, at least, 3 channels for formats that
1407 * need to be shuffled because X<->Z.
1409 num_channels
= MAX2(num_channels
, 3);
1412 if (attrib_stride
!= 0 && attrib_offset
> attrib_stride
) {
1413 LLVMValueRef buffer_offset
=
1414 LLVMConstInt(ctx
->ac
.i32
,
1415 attrib_offset
/ attrib_stride
, false);
1417 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
,
1421 attrib_offset
= attrib_offset
% attrib_stride
;
1424 t_offset
= LLVMConstInt(ctx
->ac
.i32
, attrib_binding
, false);
1425 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
1427 input
= ac_build_struct_tbuffer_load(&ctx
->ac
, t_list
,
1429 LLVMConstInt(ctx
->ac
.i32
, attrib_offset
, false),
1430 ctx
->ac
.i32_0
, ctx
->ac
.i32_0
,
1432 data_format
, num_format
, 0, true);
1434 if (ctx
->args
->options
->key
.vs
.post_shuffle
& (1 << attrib_index
)) {
1436 c
[0] = ac_llvm_extract_elem(&ctx
->ac
, input
, 2);
1437 c
[1] = ac_llvm_extract_elem(&ctx
->ac
, input
, 1);
1438 c
[2] = ac_llvm_extract_elem(&ctx
->ac
, input
, 0);
1439 c
[3] = ac_llvm_extract_elem(&ctx
->ac
, input
, 3);
1441 input
= ac_build_gather_values(&ctx
->ac
, c
, 4);
1444 input
= radv_fixup_vertex_input_fetches(ctx
, input
, num_channels
,
1447 for (unsigned chan
= 0; chan
< 4; chan
++) {
1448 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
1449 output
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
, input
, llvm_chan
, "");
1450 if (type
== GLSL_TYPE_FLOAT16
) {
1451 output
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.f32
, "");
1452 output
[chan
] = LLVMBuildFPTrunc(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.f16
, "");
1456 unsigned alpha_adjust
= (ctx
->args
->options
->key
.vs
.alpha_adjust
>> (attrib_index
* 2)) & 3;
1457 output
[3] = adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, output
[3]);
1459 for (unsigned chan
= 0; chan
< 4; chan
++) {
1460 output
[chan
] = ac_to_integer(&ctx
->ac
, output
[chan
]);
1461 if (type
== GLSL_TYPE_UINT16
|| type
== GLSL_TYPE_INT16
)
1462 output
[chan
] = LLVMBuildTrunc(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.i16
, "");
1464 ctx
->inputs
[ac_llvm_reg_index_soa(variable
->data
.location
+ i
, chan
)] = output
[chan
];
1470 handle_vs_inputs(struct radv_shader_context
*ctx
,
1471 struct nir_shader
*nir
) {
1472 nir_foreach_variable(variable
, &nir
->inputs
)
1473 handle_vs_input_decl(ctx
, variable
);
1477 prepare_interp_optimize(struct radv_shader_context
*ctx
,
1478 struct nir_shader
*nir
)
1480 bool uses_center
= false;
1481 bool uses_centroid
= false;
1482 nir_foreach_variable(variable
, &nir
->inputs
) {
1483 if (glsl_get_base_type(glsl_without_array(variable
->type
)) != GLSL_TYPE_FLOAT
||
1484 variable
->data
.sample
)
1487 if (variable
->data
.centroid
)
1488 uses_centroid
= true;
1493 ctx
->abi
.persp_centroid
= ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.persp_centroid
);
1494 ctx
->abi
.linear_centroid
= ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.linear_centroid
);
1496 if (uses_center
&& uses_centroid
) {
1497 LLVMValueRef sel
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntSLT
,
1498 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.prim_mask
),
1500 ctx
->abi
.persp_centroid
=
1501 LLVMBuildSelect(ctx
->ac
.builder
, sel
,
1502 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.persp_center
),
1503 ctx
->abi
.persp_centroid
, "");
1504 ctx
->abi
.linear_centroid
=
1505 LLVMBuildSelect(ctx
->ac
.builder
, sel
,
1506 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.linear_center
),
1507 ctx
->abi
.linear_centroid
, "");
1512 scan_shader_output_decl(struct radv_shader_context
*ctx
,
1513 struct nir_variable
*variable
,
1514 struct nir_shader
*shader
,
1515 gl_shader_stage stage
)
1517 int idx
= variable
->data
.location
+ variable
->data
.index
;
1518 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
1519 uint64_t mask_attribs
;
1521 variable
->data
.driver_location
= idx
* 4;
1523 /* tess ctrl has it's own load/store paths for outputs */
1524 if (stage
== MESA_SHADER_TESS_CTRL
)
1527 if (variable
->data
.compact
) {
1528 unsigned component_count
= variable
->data
.location_frac
+
1529 glsl_get_length(variable
->type
);
1530 attrib_count
= (component_count
+ 3) / 4;
1533 mask_attribs
= ((1ull << attrib_count
) - 1) << idx
;
1535 ctx
->output_mask
|= mask_attribs
;
1539 /* Initialize arguments for the shader export intrinsic */
1541 si_llvm_init_export_args(struct radv_shader_context
*ctx
,
1542 LLVMValueRef
*values
,
1543 unsigned enabled_channels
,
1545 struct ac_export_args
*args
)
1547 /* Specify the channels that are enabled. */
1548 args
->enabled_channels
= enabled_channels
;
1550 /* Specify whether the EXEC mask represents the valid mask */
1551 args
->valid_mask
= 0;
1553 /* Specify whether this is the last export */
1556 /* Specify the target we are exporting */
1557 args
->target
= target
;
1559 args
->compr
= false;
1560 args
->out
[0] = LLVMGetUndef(ctx
->ac
.f32
);
1561 args
->out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
1562 args
->out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
1563 args
->out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
1568 bool is_16bit
= ac_get_type_size(LLVMTypeOf(values
[0])) == 2;
1569 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
1570 unsigned index
= target
- V_008DFC_SQ_EXP_MRT
;
1571 unsigned col_format
= (ctx
->args
->options
->key
.fs
.col_format
>> (4 * index
)) & 0xf;
1572 bool is_int8
= (ctx
->args
->options
->key
.fs
.is_int8
>> index
) & 1;
1573 bool is_int10
= (ctx
->args
->options
->key
.fs
.is_int10
>> index
) & 1;
1576 LLVMValueRef (*packf
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2]) = NULL
;
1577 LLVMValueRef (*packi
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2],
1578 unsigned bits
, bool hi
) = NULL
;
1580 switch(col_format
) {
1581 case V_028714_SPI_SHADER_ZERO
:
1582 args
->enabled_channels
= 0; /* writemask */
1583 args
->target
= V_008DFC_SQ_EXP_NULL
;
1586 case V_028714_SPI_SHADER_32_R
:
1587 args
->enabled_channels
= 1;
1588 args
->out
[0] = values
[0];
1591 case V_028714_SPI_SHADER_32_GR
:
1592 args
->enabled_channels
= 0x3;
1593 args
->out
[0] = values
[0];
1594 args
->out
[1] = values
[1];
1597 case V_028714_SPI_SHADER_32_AR
:
1598 if (ctx
->ac
.chip_class
>= GFX10
) {
1599 args
->enabled_channels
= 0x3;
1600 args
->out
[0] = values
[0];
1601 args
->out
[1] = values
[3];
1603 args
->enabled_channels
= 0x9;
1604 args
->out
[0] = values
[0];
1605 args
->out
[3] = values
[3];
1609 case V_028714_SPI_SHADER_FP16_ABGR
:
1610 args
->enabled_channels
= 0x5;
1611 packf
= ac_build_cvt_pkrtz_f16
;
1613 for (unsigned chan
= 0; chan
< 4; chan
++)
1614 values
[chan
] = LLVMBuildFPExt(ctx
->ac
.builder
,
1620 case V_028714_SPI_SHADER_UNORM16_ABGR
:
1621 args
->enabled_channels
= 0x5;
1622 packf
= ac_build_cvt_pknorm_u16
;
1625 case V_028714_SPI_SHADER_SNORM16_ABGR
:
1626 args
->enabled_channels
= 0x5;
1627 packf
= ac_build_cvt_pknorm_i16
;
1630 case V_028714_SPI_SHADER_UINT16_ABGR
:
1631 args
->enabled_channels
= 0x5;
1632 packi
= ac_build_cvt_pk_u16
;
1634 for (unsigned chan
= 0; chan
< 4; chan
++)
1635 values
[chan
] = LLVMBuildZExt(ctx
->ac
.builder
,
1636 ac_to_integer(&ctx
->ac
, values
[chan
]),
1641 case V_028714_SPI_SHADER_SINT16_ABGR
:
1642 args
->enabled_channels
= 0x5;
1643 packi
= ac_build_cvt_pk_i16
;
1645 for (unsigned chan
= 0; chan
< 4; chan
++)
1646 values
[chan
] = LLVMBuildSExt(ctx
->ac
.builder
,
1647 ac_to_integer(&ctx
->ac
, values
[chan
]),
1653 case V_028714_SPI_SHADER_32_ABGR
:
1654 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
1658 /* Pack f16 or norm_i16/u16. */
1660 for (chan
= 0; chan
< 2; chan
++) {
1661 LLVMValueRef pack_args
[2] = {
1663 values
[2 * chan
+ 1]
1665 LLVMValueRef packed
;
1667 packed
= packf(&ctx
->ac
, pack_args
);
1668 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
1670 args
->compr
= 1; /* COMPR flag */
1675 for (chan
= 0; chan
< 2; chan
++) {
1676 LLVMValueRef pack_args
[2] = {
1677 ac_to_integer(&ctx
->ac
, values
[2 * chan
]),
1678 ac_to_integer(&ctx
->ac
, values
[2 * chan
+ 1])
1680 LLVMValueRef packed
;
1682 packed
= packi(&ctx
->ac
, pack_args
,
1683 is_int8
? 8 : is_int10
? 10 : 16,
1685 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
1687 args
->compr
= 1; /* COMPR flag */
1693 for (unsigned chan
= 0; chan
< 4; chan
++) {
1694 values
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, values
[chan
], ctx
->ac
.i16
, "");
1695 args
->out
[chan
] = LLVMBuildZExt(ctx
->ac
.builder
, values
[chan
], ctx
->ac
.i32
, "");
1698 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
1700 for (unsigned i
= 0; i
< 4; ++i
)
1701 args
->out
[i
] = ac_to_float(&ctx
->ac
, args
->out
[i
]);
1705 radv_export_param(struct radv_shader_context
*ctx
, unsigned index
,
1706 LLVMValueRef
*values
, unsigned enabled_channels
)
1708 struct ac_export_args args
;
1710 si_llvm_init_export_args(ctx
, values
, enabled_channels
,
1711 V_008DFC_SQ_EXP_PARAM
+ index
, &args
);
1712 ac_build_export(&ctx
->ac
, &args
);
1716 radv_load_output(struct radv_shader_context
*ctx
, unsigned index
, unsigned chan
)
1718 LLVMValueRef output
= ctx
->abi
.outputs
[ac_llvm_reg_index_soa(index
, chan
)];
1719 return LLVMBuildLoad(ctx
->ac
.builder
, output
, "");
1723 radv_emit_stream_output(struct radv_shader_context
*ctx
,
1724 LLVMValueRef
const *so_buffers
,
1725 LLVMValueRef
const *so_write_offsets
,
1726 const struct radv_stream_output
*output
,
1727 struct radv_shader_output_values
*shader_out
)
1729 unsigned num_comps
= util_bitcount(output
->component_mask
);
1730 unsigned buf
= output
->buffer
;
1731 unsigned offset
= output
->offset
;
1733 LLVMValueRef out
[4];
1735 assert(num_comps
&& num_comps
<= 4);
1736 if (!num_comps
|| num_comps
> 4)
1739 /* Get the first component. */
1740 start
= ffs(output
->component_mask
) - 1;
1742 /* Load the output as int. */
1743 for (int i
= 0; i
< num_comps
; i
++) {
1744 out
[i
] = ac_to_integer(&ctx
->ac
, shader_out
->values
[start
+ i
]);
1747 /* Pack the output. */
1748 LLVMValueRef vdata
= NULL
;
1750 switch (num_comps
) {
1751 case 1: /* as i32 */
1754 case 2: /* as v2i32 */
1755 case 3: /* as v4i32 (aligned to 4) */
1756 out
[3] = LLVMGetUndef(ctx
->ac
.i32
);
1758 case 4: /* as v4i32 */
1759 vdata
= ac_build_gather_values(&ctx
->ac
, out
,
1760 !ac_has_vec3_support(ctx
->ac
.chip_class
, false) ?
1761 util_next_power_of_two(num_comps
) :
1766 ac_build_buffer_store_dword(&ctx
->ac
, so_buffers
[buf
],
1767 vdata
, num_comps
, so_write_offsets
[buf
],
1768 ctx
->ac
.i32_0
, offset
,
1773 radv_emit_streamout(struct radv_shader_context
*ctx
, unsigned stream
)
1777 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
1778 assert(ctx
->args
->streamout_config
.used
);
1779 LLVMValueRef so_vtx_count
=
1780 ac_build_bfe(&ctx
->ac
,
1781 ac_get_arg(&ctx
->ac
, ctx
->args
->streamout_config
),
1782 LLVMConstInt(ctx
->ac
.i32
, 16, false),
1783 LLVMConstInt(ctx
->ac
.i32
, 7, false), false);
1785 LLVMValueRef tid
= ac_get_thread_id(&ctx
->ac
);
1787 /* can_emit = tid < so_vtx_count; */
1788 LLVMValueRef can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
,
1789 tid
, so_vtx_count
, "");
1791 /* Emit the streamout code conditionally. This actually avoids
1792 * out-of-bounds buffer access. The hw tells us via the SGPR
1793 * (so_vtx_count) which threads are allowed to emit streamout data.
1795 ac_build_ifcc(&ctx
->ac
, can_emit
, 6501);
1797 /* The buffer offset is computed as follows:
1798 * ByteOffset = streamout_offset[buffer_id]*4 +
1799 * (streamout_write_index + thread_id)*stride[buffer_id] +
1802 LLVMValueRef so_write_index
=
1803 ac_get_arg(&ctx
->ac
, ctx
->args
->streamout_write_idx
);
1805 /* Compute (streamout_write_index + thread_id). */
1807 LLVMBuildAdd(ctx
->ac
.builder
, so_write_index
, tid
, "");
1809 /* Load the descriptor and compute the write offset for each
1812 LLVMValueRef so_write_offset
[4] = {};
1813 LLVMValueRef so_buffers
[4] = {};
1814 LLVMValueRef buf_ptr
= ac_get_arg(&ctx
->ac
, ctx
->args
->streamout_buffers
);
1816 for (i
= 0; i
< 4; i
++) {
1817 uint16_t stride
= ctx
->args
->shader_info
->so
.strides
[i
];
1822 LLVMValueRef offset
=
1823 LLVMConstInt(ctx
->ac
.i32
, i
, false);
1825 so_buffers
[i
] = ac_build_load_to_sgpr(&ctx
->ac
,
1828 LLVMValueRef so_offset
=
1829 ac_get_arg(&ctx
->ac
, ctx
->args
->streamout_offset
[i
]);
1831 so_offset
= LLVMBuildMul(ctx
->ac
.builder
, so_offset
,
1832 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
1834 so_write_offset
[i
] =
1835 ac_build_imad(&ctx
->ac
, so_write_index
,
1836 LLVMConstInt(ctx
->ac
.i32
,
1841 /* Write streamout data. */
1842 for (i
= 0; i
< ctx
->args
->shader_info
->so
.num_outputs
; i
++) {
1843 struct radv_shader_output_values shader_out
= {};
1844 struct radv_stream_output
*output
=
1845 &ctx
->args
->shader_info
->so
.outputs
[i
];
1847 if (stream
!= output
->stream
)
1850 for (int j
= 0; j
< 4; j
++) {
1851 shader_out
.values
[j
] =
1852 radv_load_output(ctx
, output
->location
, j
);
1855 radv_emit_stream_output(ctx
, so_buffers
,so_write_offset
,
1856 output
, &shader_out
);
1859 ac_build_endif(&ctx
->ac
, 6501);
1863 radv_build_param_exports(struct radv_shader_context
*ctx
,
1864 struct radv_shader_output_values
*outputs
,
1866 struct radv_vs_output_info
*outinfo
,
1867 bool export_clip_dists
)
1869 unsigned param_count
= 0;
1871 for (unsigned i
= 0; i
< noutput
; i
++) {
1872 unsigned slot_name
= outputs
[i
].slot_name
;
1873 unsigned usage_mask
= outputs
[i
].usage_mask
;
1875 if (slot_name
!= VARYING_SLOT_LAYER
&&
1876 slot_name
!= VARYING_SLOT_PRIMITIVE_ID
&&
1877 slot_name
!= VARYING_SLOT_CLIP_DIST0
&&
1878 slot_name
!= VARYING_SLOT_CLIP_DIST1
&&
1879 slot_name
< VARYING_SLOT_VAR0
)
1882 if ((slot_name
== VARYING_SLOT_CLIP_DIST0
||
1883 slot_name
== VARYING_SLOT_CLIP_DIST1
) && !export_clip_dists
)
1886 radv_export_param(ctx
, param_count
, outputs
[i
].values
, usage_mask
);
1888 assert(i
< ARRAY_SIZE(outinfo
->vs_output_param_offset
));
1889 outinfo
->vs_output_param_offset
[slot_name
] = param_count
++;
1892 outinfo
->param_exports
= param_count
;
1895 /* Generate export instructions for hardware VS shader stage or NGG GS stage
1896 * (position and parameter data only).
1899 radv_llvm_export_vs(struct radv_shader_context
*ctx
,
1900 struct radv_shader_output_values
*outputs
,
1902 struct radv_vs_output_info
*outinfo
,
1903 bool export_clip_dists
)
1905 LLVMValueRef psize_value
= NULL
, layer_value
= NULL
, viewport_value
= NULL
;
1906 struct ac_export_args pos_args
[4] = {};
1907 unsigned pos_idx
, index
;
1910 /* Build position exports */
1911 for (i
= 0; i
< noutput
; i
++) {
1912 switch (outputs
[i
].slot_name
) {
1913 case VARYING_SLOT_POS
:
1914 si_llvm_init_export_args(ctx
, outputs
[i
].values
, 0xf,
1915 V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
1917 case VARYING_SLOT_PSIZ
:
1918 psize_value
= outputs
[i
].values
[0];
1920 case VARYING_SLOT_LAYER
:
1921 layer_value
= outputs
[i
].values
[0];
1923 case VARYING_SLOT_VIEWPORT
:
1924 viewport_value
= outputs
[i
].values
[0];
1926 case VARYING_SLOT_CLIP_DIST0
:
1927 case VARYING_SLOT_CLIP_DIST1
:
1928 index
= 2 + outputs
[i
].slot_index
;
1929 si_llvm_init_export_args(ctx
, outputs
[i
].values
, 0xf,
1930 V_008DFC_SQ_EXP_POS
+ index
,
1938 /* We need to add the position output manually if it's missing. */
1939 if (!pos_args
[0].out
[0]) {
1940 pos_args
[0].enabled_channels
= 0xf; /* writemask */
1941 pos_args
[0].valid_mask
= 0; /* EXEC mask */
1942 pos_args
[0].done
= 0; /* last export? */
1943 pos_args
[0].target
= V_008DFC_SQ_EXP_POS
;
1944 pos_args
[0].compr
= 0; /* COMPR flag */
1945 pos_args
[0].out
[0] = ctx
->ac
.f32_0
; /* X */
1946 pos_args
[0].out
[1] = ctx
->ac
.f32_0
; /* Y */
1947 pos_args
[0].out
[2] = ctx
->ac
.f32_0
; /* Z */
1948 pos_args
[0].out
[3] = ctx
->ac
.f32_1
; /* W */
1951 if (outinfo
->writes_pointsize
||
1952 outinfo
->writes_layer
||
1953 outinfo
->writes_viewport_index
) {
1954 pos_args
[1].enabled_channels
= ((outinfo
->writes_pointsize
== true ? 1 : 0) |
1955 (outinfo
->writes_layer
== true ? 4 : 0));
1956 pos_args
[1].valid_mask
= 0;
1957 pos_args
[1].done
= 0;
1958 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
1959 pos_args
[1].compr
= 0;
1960 pos_args
[1].out
[0] = ctx
->ac
.f32_0
; /* X */
1961 pos_args
[1].out
[1] = ctx
->ac
.f32_0
; /* Y */
1962 pos_args
[1].out
[2] = ctx
->ac
.f32_0
; /* Z */
1963 pos_args
[1].out
[3] = ctx
->ac
.f32_0
; /* W */
1965 if (outinfo
->writes_pointsize
== true)
1966 pos_args
[1].out
[0] = psize_value
;
1967 if (outinfo
->writes_layer
== true)
1968 pos_args
[1].out
[2] = layer_value
;
1969 if (outinfo
->writes_viewport_index
== true) {
1970 if (ctx
->args
->options
->chip_class
>= GFX9
) {
1971 /* GFX9 has the layer in out.z[10:0] and the viewport
1972 * index in out.z[19:16].
1974 LLVMValueRef v
= viewport_value
;
1975 v
= ac_to_integer(&ctx
->ac
, v
);
1976 v
= LLVMBuildShl(ctx
->ac
.builder
, v
,
1977 LLVMConstInt(ctx
->ac
.i32
, 16, false),
1979 v
= LLVMBuildOr(ctx
->ac
.builder
, v
,
1980 ac_to_integer(&ctx
->ac
, pos_args
[1].out
[2]), "");
1982 pos_args
[1].out
[2] = ac_to_float(&ctx
->ac
, v
);
1983 pos_args
[1].enabled_channels
|= 1 << 2;
1985 pos_args
[1].out
[3] = viewport_value
;
1986 pos_args
[1].enabled_channels
|= 1 << 3;
1991 for (i
= 0; i
< 4; i
++) {
1992 if (pos_args
[i
].out
[0])
1993 outinfo
->pos_exports
++;
1996 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
1997 * Setting valid_mask=1 prevents it and has no other effect.
1999 if (ctx
->ac
.family
== CHIP_NAVI10
||
2000 ctx
->ac
.family
== CHIP_NAVI12
||
2001 ctx
->ac
.family
== CHIP_NAVI14
)
2002 pos_args
[0].valid_mask
= 1;
2005 for (i
= 0; i
< 4; i
++) {
2006 if (!pos_args
[i
].out
[0])
2009 /* Specify the target we are exporting */
2010 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
2012 if (pos_idx
== outinfo
->pos_exports
)
2013 /* Specify that this is the last export */
2014 pos_args
[i
].done
= 1;
2016 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
2019 /* Build parameter exports */
2020 radv_build_param_exports(ctx
, outputs
, noutput
, outinfo
, export_clip_dists
);
2024 handle_vs_outputs_post(struct radv_shader_context
*ctx
,
2025 bool export_prim_id
,
2026 bool export_clip_dists
,
2027 struct radv_vs_output_info
*outinfo
)
2029 struct radv_shader_output_values
*outputs
;
2030 unsigned noutput
= 0;
2032 if (ctx
->args
->options
->key
.has_multiview_view_index
) {
2033 LLVMValueRef
* tmp_out
= &ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
2035 for(unsigned i
= 0; i
< 4; ++i
)
2036 ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, i
)] =
2037 ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
2040 LLVMValueRef view_index
= ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.view_index
);
2041 LLVMBuildStore(ctx
->ac
.builder
, ac_to_float(&ctx
->ac
, view_index
), *tmp_out
);
2042 ctx
->output_mask
|= 1ull << VARYING_SLOT_LAYER
;
2045 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
2046 sizeof(outinfo
->vs_output_param_offset
));
2047 outinfo
->pos_exports
= 0;
2049 if (!ctx
->args
->options
->use_ngg_streamout
&&
2050 ctx
->args
->shader_info
->so
.num_outputs
&&
2051 !ctx
->args
->is_gs_copy_shader
) {
2052 /* The GS copy shader emission already emits streamout. */
2053 radv_emit_streamout(ctx
, 0);
2056 /* Allocate a temporary array for the output values. */
2057 unsigned num_outputs
= util_bitcount64(ctx
->output_mask
) + export_prim_id
;
2058 outputs
= malloc(num_outputs
* sizeof(outputs
[0]));
2060 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2061 if (!(ctx
->output_mask
& (1ull << i
)))
2064 outputs
[noutput
].slot_name
= i
;
2065 outputs
[noutput
].slot_index
= i
== VARYING_SLOT_CLIP_DIST1
;
2067 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
2068 !ctx
->args
->is_gs_copy_shader
) {
2069 outputs
[noutput
].usage_mask
=
2070 ctx
->args
->shader_info
->vs
.output_usage_mask
[i
];
2071 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
2072 outputs
[noutput
].usage_mask
=
2073 ctx
->args
->shader_info
->tes
.output_usage_mask
[i
];
2075 assert(ctx
->args
->is_gs_copy_shader
);
2076 outputs
[noutput
].usage_mask
=
2077 ctx
->args
->shader_info
->gs
.output_usage_mask
[i
];
2080 for (unsigned j
= 0; j
< 4; j
++) {
2081 outputs
[noutput
].values
[j
] =
2082 ac_to_float(&ctx
->ac
, radv_load_output(ctx
, i
, j
));
2088 /* Export PrimitiveID. */
2089 if (export_prim_id
) {
2090 outputs
[noutput
].slot_name
= VARYING_SLOT_PRIMITIVE_ID
;
2091 outputs
[noutput
].slot_index
= 0;
2092 outputs
[noutput
].usage_mask
= 0x1;
2093 outputs
[noutput
].values
[0] =
2094 ac_get_arg(&ctx
->ac
, ctx
->args
->vs_prim_id
);
2095 for (unsigned j
= 1; j
< 4; j
++)
2096 outputs
[noutput
].values
[j
] = ctx
->ac
.f32_0
;
2100 radv_llvm_export_vs(ctx
, outputs
, noutput
, outinfo
, export_clip_dists
);
2106 handle_es_outputs_post(struct radv_shader_context
*ctx
,
2107 struct radv_es_output_info
*outinfo
)
2110 LLVMValueRef lds_base
= NULL
;
2112 if (ctx
->ac
.chip_class
>= GFX9
) {
2113 unsigned itemsize_dw
= outinfo
->esgs_itemsize
/ 4;
2114 LLVMValueRef vertex_idx
= ac_get_thread_id(&ctx
->ac
);
2115 LLVMValueRef wave_idx
=
2116 ac_unpack_param(&ctx
->ac
,
2117 ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
), 24, 4);
2118 vertex_idx
= LLVMBuildOr(ctx
->ac
.builder
, vertex_idx
,
2119 LLVMBuildMul(ctx
->ac
.builder
, wave_idx
,
2120 LLVMConstInt(ctx
->ac
.i32
,
2121 ctx
->ac
.wave_size
, false), ""), "");
2122 lds_base
= LLVMBuildMul(ctx
->ac
.builder
, vertex_idx
,
2123 LLVMConstInt(ctx
->ac
.i32
, itemsize_dw
, 0), "");
2126 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2127 LLVMValueRef dw_addr
= NULL
;
2128 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
2129 unsigned output_usage_mask
;
2132 if (!(ctx
->output_mask
& (1ull << i
)))
2135 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2137 ctx
->args
->shader_info
->vs
.output_usage_mask
[i
];
2139 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
2141 ctx
->args
->shader_info
->tes
.output_usage_mask
[i
];
2144 param_index
= shader_io_get_unique_index(i
);
2147 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
2148 LLVMConstInt(ctx
->ac
.i32
, param_index
* 4, false),
2152 for (j
= 0; j
< 4; j
++) {
2153 if (!(output_usage_mask
& (1 << j
)))
2156 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
2157 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
2158 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
2160 if (ctx
->ac
.chip_class
>= GFX9
) {
2161 LLVMValueRef dw_addr_offset
=
2162 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2163 LLVMConstInt(ctx
->ac
.i32
,
2166 ac_lds_store(&ctx
->ac
, dw_addr_offset
, out_val
);
2168 ac_build_buffer_store_dword(&ctx
->ac
,
2172 ac_get_arg(&ctx
->ac
, ctx
->args
->es2gs_offset
),
2173 (4 * param_index
+ j
) * 4,
2174 ac_glc
| ac_slc
| ac_swizzled
);
2181 handle_ls_outputs_post(struct radv_shader_context
*ctx
)
2183 LLVMValueRef vertex_id
= ctx
->rel_auto_id
;
2184 uint32_t num_tcs_inputs
= util_last_bit64(ctx
->args
->shader_info
->vs
.ls_outputs_written
);
2185 LLVMValueRef vertex_dw_stride
= LLVMConstInt(ctx
->ac
.i32
, num_tcs_inputs
* 4, false);
2186 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->ac
.builder
, vertex_id
,
2187 vertex_dw_stride
, "");
2189 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2190 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
2192 if (!(ctx
->output_mask
& (1ull << i
)))
2195 int param
= shader_io_get_unique_index(i
);
2196 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_dw_addr
,
2197 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false),
2199 for (unsigned j
= 0; j
< 4; j
++) {
2200 LLVMValueRef value
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
2201 value
= ac_to_integer(&ctx
->ac
, value
);
2202 value
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
2203 ac_lds_store(&ctx
->ac
, dw_addr
, value
);
2204 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
, ctx
->ac
.i32_1
, "");
2209 static LLVMValueRef
get_wave_id_in_tg(struct radv_shader_context
*ctx
)
2211 return ac_unpack_param(&ctx
->ac
,
2212 ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
), 24, 4);
2215 static LLVMValueRef
get_tgsize(struct radv_shader_context
*ctx
)
2217 return ac_unpack_param(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
), 28, 4);
2220 static LLVMValueRef
get_thread_id_in_tg(struct radv_shader_context
*ctx
)
2222 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2224 tmp
= LLVMBuildMul(builder
, get_wave_id_in_tg(ctx
),
2225 LLVMConstInt(ctx
->ac
.i32
, ctx
->ac
.wave_size
, false), "");
2226 return LLVMBuildAdd(builder
, tmp
, ac_get_thread_id(&ctx
->ac
), "");
2229 static LLVMValueRef
ngg_get_vtx_cnt(struct radv_shader_context
*ctx
)
2231 return ac_build_bfe(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->gs_tg_info
),
2232 LLVMConstInt(ctx
->ac
.i32
, 12, false),
2233 LLVMConstInt(ctx
->ac
.i32
, 9, false),
2237 static LLVMValueRef
ngg_get_prim_cnt(struct radv_shader_context
*ctx
)
2239 return ac_build_bfe(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->gs_tg_info
),
2240 LLVMConstInt(ctx
->ac
.i32
, 22, false),
2241 LLVMConstInt(ctx
->ac
.i32
, 9, false),
2245 static LLVMValueRef
ngg_get_ordered_id(struct radv_shader_context
*ctx
)
2247 return ac_build_bfe(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->gs_tg_info
),
2249 LLVMConstInt(ctx
->ac
.i32
, 11, false),
2254 ngg_gs_get_vertex_storage(struct radv_shader_context
*ctx
)
2256 unsigned num_outputs
= util_bitcount64(ctx
->output_mask
);
2258 if (ctx
->args
->options
->key
.has_multiview_view_index
)
2261 LLVMTypeRef elements
[2] = {
2262 LLVMArrayType(ctx
->ac
.i32
, 4 * num_outputs
),
2263 LLVMArrayType(ctx
->ac
.i8
, 4),
2265 LLVMTypeRef type
= LLVMStructTypeInContext(ctx
->ac
.context
, elements
, 2, false);
2266 type
= LLVMPointerType(LLVMArrayType(type
, 0), AC_ADDR_SPACE_LDS
);
2267 return LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->gs_ngg_emit
, type
, "");
2271 * Return a pointer to the LDS storage reserved for the N'th vertex, where N
2272 * is in emit order; that is:
2273 * - during the epilogue, N is the threadidx (relative to the entire threadgroup)
2274 * - during vertex emit, i.e. while the API GS shader invocation is running,
2275 * N = threadidx * gs_max_out_vertices + emitidx
2277 * Goals of the LDS memory layout:
2278 * 1. Eliminate bank conflicts on write for geometry shaders that have all emits
2279 * in uniform control flow
2280 * 2. Eliminate bank conflicts on read for export if, additionally, there is no
2282 * 3. Agnostic to the number of waves (since we don't know it before compiling)
2283 * 4. Allow coalescing of LDS instructions (ds_write_b128 etc.)
2284 * 5. Avoid wasting memory.
2286 * We use an AoS layout due to point 4 (this also helps point 3). In an AoS
2287 * layout, elimination of bank conflicts requires that each vertex occupy an
2288 * odd number of dwords. We use the additional dword to store the output stream
2289 * index as well as a flag to indicate whether this vertex ends a primitive
2290 * for rasterization.
2292 * Swizzling is required to satisfy points 1 and 2 simultaneously.
2294 * Vertices are stored in export order (gsthread * gs_max_out_vertices + emitidx).
2295 * Indices are swizzled in groups of 32, which ensures point 1 without
2296 * disturbing point 2.
2298 * \return an LDS pointer to type {[N x i32], [4 x i8]}
2301 ngg_gs_vertex_ptr(struct radv_shader_context
*ctx
, LLVMValueRef vertexidx
)
2303 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2304 LLVMValueRef storage
= ngg_gs_get_vertex_storage(ctx
);
2306 /* gs_max_out_vertices = 2^(write_stride_2exp) * some odd number */
2307 unsigned write_stride_2exp
= ffs(ctx
->shader
->info
.gs
.vertices_out
) - 1;
2308 if (write_stride_2exp
) {
2310 LLVMBuildLShr(builder
, vertexidx
,
2311 LLVMConstInt(ctx
->ac
.i32
, 5, false), "");
2312 LLVMValueRef swizzle
=
2313 LLVMBuildAnd(builder
, row
,
2314 LLVMConstInt(ctx
->ac
.i32
, (1u << write_stride_2exp
) - 1,
2316 vertexidx
= LLVMBuildXor(builder
, vertexidx
, swizzle
, "");
2319 return ac_build_gep0(&ctx
->ac
, storage
, vertexidx
);
2323 ngg_gs_emit_vertex_ptr(struct radv_shader_context
*ctx
, LLVMValueRef gsthread
,
2324 LLVMValueRef emitidx
)
2326 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2329 tmp
= LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.gs
.vertices_out
, false);
2330 tmp
= LLVMBuildMul(builder
, tmp
, gsthread
, "");
2331 const LLVMValueRef vertexidx
= LLVMBuildAdd(builder
, tmp
, emitidx
, "");
2332 return ngg_gs_vertex_ptr(ctx
, vertexidx
);
2335 /* Send GS Alloc Req message from the first wave of the group to SPI.
2336 * Message payload is:
2337 * - bits 0..10: vertices in group
2338 * - bits 12..22: primitives in group
2340 static void build_sendmsg_gs_alloc_req(struct radv_shader_context
*ctx
,
2341 LLVMValueRef vtx_cnt
,
2342 LLVMValueRef prim_cnt
)
2344 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2347 tmp
= LLVMBuildICmp(builder
, LLVMIntEQ
, get_wave_id_in_tg(ctx
), ctx
->ac
.i32_0
, "");
2348 ac_build_ifcc(&ctx
->ac
, tmp
, 5020);
2350 tmp
= LLVMBuildShl(builder
, prim_cnt
, LLVMConstInt(ctx
->ac
.i32
, 12, false),"");
2351 tmp
= LLVMBuildOr(builder
, tmp
, vtx_cnt
, "");
2352 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_ALLOC_REQ
, tmp
);
2354 ac_build_endif(&ctx
->ac
, 5020);
2358 unsigned num_vertices
;
2359 LLVMValueRef isnull
;
2361 LLVMValueRef index
[3];
2362 LLVMValueRef edgeflag
[3];
2365 static void build_export_prim(struct radv_shader_context
*ctx
,
2366 const struct ngg_prim
*prim
)
2368 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2369 struct ac_export_args args
;
2370 LLVMValueRef vertices
[3];
2371 LLVMValueRef odd
, even
;
2374 tmp
= LLVMBuildZExt(builder
, prim
->isnull
, ctx
->ac
.i32
, "");
2375 args
.out
[0] = LLVMBuildShl(builder
, tmp
, LLVMConstInt(ctx
->ac
.i32
, 31, false), "");
2377 for (unsigned i
= 0; i
< prim
->num_vertices
; ++i
) {
2378 tmp
= LLVMBuildZExt(builder
, prim
->edgeflag
[i
], ctx
->ac
.i32
, "");
2379 tmp
= LLVMBuildShl(builder
, tmp
,
2380 LLVMConstInt(ctx
->ac
.i32
, 9, false), "");
2381 vertices
[i
] = LLVMBuildOr(builder
, prim
->index
[i
], tmp
, "");
2384 switch (prim
->num_vertices
) {
2386 args
.out
[0] = LLVMBuildOr(builder
, args
.out
[0], vertices
[0], "");
2389 tmp
= LLVMBuildShl(builder
, vertices
[1],
2390 LLVMConstInt(ctx
->ac
.i32
, 10, false), "");
2391 tmp
= LLVMBuildOr(builder
, args
.out
[0], tmp
, "");
2392 args
.out
[0] = LLVMBuildOr(builder
, tmp
, vertices
[0], "");
2395 /* Swap vertices if needed to follow drawing order. */
2396 tmp
= LLVMBuildShl(builder
, vertices
[2],
2397 LLVMConstInt(ctx
->ac
.i32
, 20, false), "");
2398 even
= LLVMBuildOr(builder
, args
.out
[0], tmp
, "");
2399 tmp
= LLVMBuildShl(builder
, vertices
[1],
2400 LLVMConstInt(ctx
->ac
.i32
, 10, false), "");
2401 even
= LLVMBuildOr(builder
, even
, tmp
, "");
2402 even
= LLVMBuildOr(builder
, even
, vertices
[0], "");
2404 tmp
= LLVMBuildShl(builder
, vertices
[1],
2405 LLVMConstInt(ctx
->ac
.i32
, 20, false), "");
2406 odd
= LLVMBuildOr(builder
, args
.out
[0], tmp
, "");
2407 tmp
= LLVMBuildShl(builder
, vertices
[2],
2408 LLVMConstInt(ctx
->ac
.i32
, 10, false), "");
2409 odd
= LLVMBuildOr(builder
, odd
, tmp
, "");
2410 odd
= LLVMBuildOr(builder
, odd
, vertices
[0], "");
2412 args
.out
[0] = LLVMBuildSelect(builder
, prim
->swap
, odd
, even
, "");
2415 unreachable("invalid number of vertices");
2418 args
.out
[0] = LLVMBuildBitCast(builder
, args
.out
[0], ctx
->ac
.f32
, "");
2419 args
.out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
2420 args
.out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
2421 args
.out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
2423 args
.target
= V_008DFC_SQ_EXP_PRIM
;
2424 args
.enabled_channels
= 1;
2426 args
.valid_mask
= false;
2429 ac_build_export(&ctx
->ac
, &args
);
2432 static struct radv_stream_output
*
2433 radv_get_stream_output_by_loc(struct radv_streamout_info
*so
, unsigned location
)
2435 for (unsigned i
= 0; i
< so
->num_outputs
; ++i
) {
2436 if (so
->outputs
[i
].location
== location
)
2437 return &so
->outputs
[i
];
2443 static void build_streamout_vertex(struct radv_shader_context
*ctx
,
2444 LLVMValueRef
*so_buffer
, LLVMValueRef
*wg_offset_dw
,
2445 unsigned stream
, LLVMValueRef offset_vtx
,
2446 LLVMValueRef vertexptr
)
2448 struct radv_streamout_info
*so
= &ctx
->args
->shader_info
->so
;
2449 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2450 LLVMValueRef offset
[4] = {};
2453 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
2454 if (!wg_offset_dw
[buffer
])
2457 tmp
= LLVMBuildMul(builder
, offset_vtx
,
2458 LLVMConstInt(ctx
->ac
.i32
, so
->strides
[buffer
], false), "");
2459 tmp
= LLVMBuildAdd(builder
, wg_offset_dw
[buffer
], tmp
, "");
2460 offset
[buffer
] = LLVMBuildShl(builder
, tmp
, LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
2463 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
2464 struct radv_shader_output_values outputs
[AC_LLVM_MAX_OUTPUTS
];
2465 unsigned noutput
= 0;
2466 unsigned out_idx
= 0;
2468 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2469 unsigned output_usage_mask
=
2470 ctx
->args
->shader_info
->gs
.output_usage_mask
[i
];
2471 uint8_t output_stream
=
2472 output_stream
= ctx
->args
->shader_info
->gs
.output_streams
[i
];
2474 if (!(ctx
->output_mask
& (1ull << i
)) ||
2475 output_stream
!= stream
)
2478 outputs
[noutput
].slot_name
= i
;
2479 outputs
[noutput
].slot_index
= i
== VARYING_SLOT_CLIP_DIST1
;
2480 outputs
[noutput
].usage_mask
= output_usage_mask
;
2482 int length
= util_last_bit(output_usage_mask
);
2484 for (unsigned j
= 0; j
< length
; j
++, out_idx
++) {
2485 if (!(output_usage_mask
& (1 << j
)))
2488 tmp
= ac_build_gep0(&ctx
->ac
, vertexptr
,
2489 LLVMConstInt(ctx
->ac
.i32
, out_idx
, false));
2490 outputs
[noutput
].values
[j
] = LLVMBuildLoad(builder
, tmp
, "");
2493 for (unsigned j
= length
; j
< 4; j
++)
2494 outputs
[noutput
].values
[j
] = LLVMGetUndef(ctx
->ac
.f32
);
2499 for (unsigned i
= 0; i
< noutput
; i
++) {
2500 struct radv_stream_output
*output
=
2501 radv_get_stream_output_by_loc(so
, outputs
[i
].slot_name
);
2504 output
->stream
!= stream
)
2507 struct radv_shader_output_values out
= {};
2509 for (unsigned j
= 0; j
< 4; j
++) {
2510 out
.values
[j
] = outputs
[i
].values
[j
];
2513 radv_emit_stream_output(ctx
, so_buffer
, offset
, output
, &out
);
2516 for (unsigned i
= 0; i
< so
->num_outputs
; ++i
) {
2517 struct radv_stream_output
*output
=
2518 &ctx
->args
->shader_info
->so
.outputs
[i
];
2520 if (stream
!= output
->stream
)
2523 struct radv_shader_output_values out
= {};
2525 for (unsigned comp
= 0; comp
< 4; comp
++) {
2526 if (!(output
->component_mask
& (1 << comp
)))
2529 tmp
= ac_build_gep0(&ctx
->ac
, vertexptr
,
2530 LLVMConstInt(ctx
->ac
.i32
, 4 * i
+ comp
, false));
2531 out
.values
[comp
] = LLVMBuildLoad(builder
, tmp
, "");
2534 radv_emit_stream_output(ctx
, so_buffer
, offset
, output
, &out
);
2539 struct ngg_streamout
{
2540 LLVMValueRef num_vertices
;
2542 /* per-thread data */
2543 LLVMValueRef prim_enable
[4]; /* i1 per stream */
2544 LLVMValueRef vertices
[3]; /* [N x i32] addrspace(LDS)* */
2547 LLVMValueRef emit
[4]; /* per-stream emitted primitives (only valid for used streams) */
2551 * Build streamout logic.
2553 * Implies a barrier.
2555 * Writes number of emitted primitives to gs_ngg_scratch[4:7].
2557 * Clobbers gs_ngg_scratch[8:].
2559 static void build_streamout(struct radv_shader_context
*ctx
,
2560 struct ngg_streamout
*nggso
)
2562 struct radv_streamout_info
*so
= &ctx
->args
->shader_info
->so
;
2563 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2564 LLVMValueRef buf_ptr
= ac_get_arg(&ctx
->ac
, ctx
->args
->streamout_buffers
);
2565 LLVMValueRef tid
= get_thread_id_in_tg(ctx
);
2566 LLVMValueRef cond
, tmp
, tmp2
;
2567 LLVMValueRef i32_2
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
2568 LLVMValueRef i32_4
= LLVMConstInt(ctx
->ac
.i32
, 4, false);
2569 LLVMValueRef i32_8
= LLVMConstInt(ctx
->ac
.i32
, 8, false);
2570 LLVMValueRef so_buffer
[4] = {};
2571 unsigned max_num_vertices
= 1 + (nggso
->vertices
[1] ? 1 : 0) +
2572 (nggso
->vertices
[2] ? 1 : 0);
2573 LLVMValueRef prim_stride_dw
[4] = {};
2574 LLVMValueRef prim_stride_dw_vgpr
= LLVMGetUndef(ctx
->ac
.i32
);
2575 int stream_for_buffer
[4] = { -1, -1, -1, -1 };
2576 unsigned bufmask_for_stream
[4] = {};
2577 bool isgs
= ctx
->stage
== MESA_SHADER_GEOMETRY
;
2578 unsigned scratch_emit_base
= isgs
? 4 : 0;
2579 LLVMValueRef scratch_emit_basev
= isgs
? i32_4
: ctx
->ac
.i32_0
;
2580 unsigned scratch_offset_base
= isgs
? 8 : 4;
2581 LLVMValueRef scratch_offset_basev
= isgs
? i32_8
: i32_4
;
2583 ac_llvm_add_target_dep_function_attr(ctx
->main_function
,
2584 "amdgpu-gds-size", 256);
2586 /* Determine the mapping of streamout buffers to vertex streams. */
2587 for (unsigned i
= 0; i
< so
->num_outputs
; ++i
) {
2588 unsigned buf
= so
->outputs
[i
].buffer
;
2589 unsigned stream
= so
->outputs
[i
].stream
;
2590 assert(stream_for_buffer
[buf
] < 0 || stream_for_buffer
[buf
] == stream
);
2591 stream_for_buffer
[buf
] = stream
;
2592 bufmask_for_stream
[stream
] |= 1 << buf
;
2595 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
2596 if (stream_for_buffer
[buffer
] == -1)
2599 assert(so
->strides
[buffer
]);
2601 LLVMValueRef stride_for_buffer
=
2602 LLVMConstInt(ctx
->ac
.i32
, so
->strides
[buffer
], false);
2603 prim_stride_dw
[buffer
] =
2604 LLVMBuildMul(builder
, stride_for_buffer
,
2605 nggso
->num_vertices
, "");
2606 prim_stride_dw_vgpr
= ac_build_writelane(
2607 &ctx
->ac
, prim_stride_dw_vgpr
, prim_stride_dw
[buffer
],
2608 LLVMConstInt(ctx
->ac
.i32
, buffer
, false));
2610 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, buffer
, false);
2611 so_buffer
[buffer
] = ac_build_load_to_sgpr(&ctx
->ac
, buf_ptr
,
2615 cond
= LLVMBuildICmp(builder
, LLVMIntEQ
, get_wave_id_in_tg(ctx
), ctx
->ac
.i32_0
, "");
2616 ac_build_ifcc(&ctx
->ac
, cond
, 5200);
2618 LLVMTypeRef gdsptr
= LLVMPointerType(ctx
->ac
.i32
, AC_ADDR_SPACE_GDS
);
2619 LLVMValueRef gdsbase
= LLVMBuildIntToPtr(builder
, ctx
->ac
.i32_0
, gdsptr
, "");
2621 /* Advance the streamout offsets in GDS. */
2622 LLVMValueRef offsets_vgpr
= ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.i32
, "");
2623 LLVMValueRef generated_by_stream_vgpr
= ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.i32
, "");
2625 cond
= LLVMBuildICmp(builder
, LLVMIntULT
, ac_get_thread_id(&ctx
->ac
), i32_4
, "");
2626 ac_build_ifcc(&ctx
->ac
, cond
, 5210);
2628 /* Fetch the number of generated primitives and store
2629 * it in GDS for later use.
2632 tmp
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, tid
);
2633 tmp
= LLVMBuildLoad(builder
, tmp
, "");
2635 tmp
= ac_build_writelane(&ctx
->ac
, ctx
->ac
.i32_0
,
2636 ngg_get_prim_cnt(ctx
), ctx
->ac
.i32_0
);
2638 LLVMBuildStore(builder
, tmp
, generated_by_stream_vgpr
);
2640 unsigned swizzle
[4];
2641 int unused_stream
= -1;
2642 for (unsigned stream
= 0; stream
< 4; ++stream
) {
2643 if (!ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
]) {
2644 unused_stream
= stream
;
2648 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
2649 if (stream_for_buffer
[buffer
] >= 0) {
2650 swizzle
[buffer
] = stream_for_buffer
[buffer
];
2652 assert(unused_stream
>= 0);
2653 swizzle
[buffer
] = unused_stream
;
2657 tmp
= ac_build_quad_swizzle(&ctx
->ac
, tmp
,
2658 swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
2659 tmp
= LLVMBuildMul(builder
, tmp
, prim_stride_dw_vgpr
, "");
2661 LLVMValueRef args
[] = {
2662 LLVMBuildIntToPtr(builder
, ngg_get_ordered_id(ctx
), gdsptr
, ""),
2664 ctx
->ac
.i32_0
, // ordering
2665 ctx
->ac
.i32_0
, // scope
2666 ctx
->ac
.i1false
, // isVolatile
2667 LLVMConstInt(ctx
->ac
.i32
, 4 << 24, false), // OA index
2668 ctx
->ac
.i1true
, // wave release
2669 ctx
->ac
.i1true
, // wave done
2672 tmp
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.ds.ordered.add",
2673 ctx
->ac
.i32
, args
, ARRAY_SIZE(args
), 0);
2675 /* Keep offsets in a VGPR for quick retrieval via readlane by
2676 * the first wave for bounds checking, and also store in LDS
2677 * for retrieval by all waves later. */
2678 LLVMBuildStore(builder
, tmp
, offsets_vgpr
);
2680 tmp2
= LLVMBuildAdd(builder
, ac_get_thread_id(&ctx
->ac
),
2681 scratch_offset_basev
, "");
2682 tmp2
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, tmp2
);
2683 LLVMBuildStore(builder
, tmp
, tmp2
);
2685 ac_build_endif(&ctx
->ac
, 5210);
2687 /* Determine the max emit per buffer. This is done via the SALU, in part
2688 * because LLVM can't generate divide-by-multiply if we try to do this
2689 * via VALU with one lane per buffer.
2691 LLVMValueRef max_emit
[4] = {};
2692 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
2693 if (stream_for_buffer
[buffer
] == -1)
2696 /* Compute the streamout buffer size in DWORD. */
2697 LLVMValueRef bufsize_dw
=
2698 LLVMBuildLShr(builder
,
2699 LLVMBuildExtractElement(builder
, so_buffer
[buffer
], i32_2
, ""),
2702 /* Load the streamout buffer offset from GDS. */
2703 tmp
= LLVMBuildLoad(builder
, offsets_vgpr
, "");
2704 LLVMValueRef offset_dw
=
2705 ac_build_readlane(&ctx
->ac
, tmp
,
2706 LLVMConstInt(ctx
->ac
.i32
, buffer
, false));
2708 /* Compute the remaining size to emit. */
2709 LLVMValueRef remaining_dw
=
2710 LLVMBuildSub(builder
, bufsize_dw
, offset_dw
, "");
2711 tmp
= LLVMBuildUDiv(builder
, remaining_dw
,
2712 prim_stride_dw
[buffer
], "");
2714 cond
= LLVMBuildICmp(builder
, LLVMIntULT
,
2715 bufsize_dw
, offset_dw
, "");
2716 max_emit
[buffer
] = LLVMBuildSelect(builder
, cond
,
2717 ctx
->ac
.i32_0
, tmp
, "");
2720 /* Determine the number of emitted primitives per stream and fixup the
2721 * GDS counter if necessary.
2723 * This is complicated by the fact that a single stream can emit to
2724 * multiple buffers (but luckily not vice versa).
2726 LLVMValueRef emit_vgpr
= ctx
->ac
.i32_0
;
2728 for (unsigned stream
= 0; stream
< 4; ++stream
) {
2729 if (!ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
])
2732 /* Load the number of generated primitives from GDS and
2733 * determine that number for the given stream.
2735 tmp
= LLVMBuildLoad(builder
, generated_by_stream_vgpr
, "");
2736 LLVMValueRef generated
=
2737 ac_build_readlane(&ctx
->ac
, tmp
,
2738 LLVMConstInt(ctx
->ac
.i32
, stream
, false));
2741 /* Compute the number of emitted primitives. */
2742 LLVMValueRef emit
= generated
;
2743 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
2744 if (stream_for_buffer
[buffer
] == stream
)
2745 emit
= ac_build_umin(&ctx
->ac
, emit
, max_emit
[buffer
]);
2748 /* Store the number of emitted primitives for that
2751 emit_vgpr
= ac_build_writelane(&ctx
->ac
, emit_vgpr
, emit
,
2752 LLVMConstInt(ctx
->ac
.i32
, stream
, false));
2754 /* Fixup the offset using a plain GDS atomic if we overflowed. */
2755 cond
= LLVMBuildICmp(builder
, LLVMIntULT
, emit
, generated
, "");
2756 ac_build_ifcc(&ctx
->ac
, cond
, 5221); /* scalar branch */
2757 tmp
= LLVMBuildLShr(builder
,
2758 LLVMConstInt(ctx
->ac
.i32
, bufmask_for_stream
[stream
], false),
2759 ac_get_thread_id(&ctx
->ac
), "");
2760 tmp
= LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
2761 ac_build_ifcc(&ctx
->ac
, tmp
, 5222);
2763 tmp
= LLVMBuildSub(builder
, generated
, emit
, "");
2764 tmp
= LLVMBuildMul(builder
, tmp
, prim_stride_dw_vgpr
, "");
2765 tmp2
= LLVMBuildGEP(builder
, gdsbase
, &tid
, 1, "");
2766 LLVMBuildAtomicRMW(builder
, LLVMAtomicRMWBinOpSub
, tmp2
, tmp
,
2767 LLVMAtomicOrderingMonotonic
, false);
2769 ac_build_endif(&ctx
->ac
, 5222);
2770 ac_build_endif(&ctx
->ac
, 5221);
2773 /* Store the number of emitted primitives to LDS for later use. */
2774 cond
= LLVMBuildICmp(builder
, LLVMIntULT
, ac_get_thread_id(&ctx
->ac
), i32_4
, "");
2775 ac_build_ifcc(&ctx
->ac
, cond
, 5225);
2777 tmp
= LLVMBuildAdd(builder
, ac_get_thread_id(&ctx
->ac
),
2778 scratch_emit_basev
, "");
2779 tmp
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, tmp
);
2780 LLVMBuildStore(builder
, emit_vgpr
, tmp
);
2782 ac_build_endif(&ctx
->ac
, 5225);
2784 ac_build_endif(&ctx
->ac
, 5200);
2786 /* Determine the workgroup-relative per-thread / primitive offset into
2787 * the streamout buffers */
2788 struct ac_wg_scan primemit_scan
[4] = {};
2791 for (unsigned stream
= 0; stream
< 4; ++stream
) {
2792 if (!ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
])
2795 primemit_scan
[stream
].enable_exclusive
= true;
2796 primemit_scan
[stream
].op
= nir_op_iadd
;
2797 primemit_scan
[stream
].src
= nggso
->prim_enable
[stream
];
2798 primemit_scan
[stream
].scratch
=
2799 ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
,
2800 LLVMConstInt(ctx
->ac
.i32
, 12 + 8 * stream
, false));
2801 primemit_scan
[stream
].waveidx
= get_wave_id_in_tg(ctx
);
2802 primemit_scan
[stream
].numwaves
= get_tgsize(ctx
);
2803 primemit_scan
[stream
].maxwaves
= 8;
2804 ac_build_wg_scan_top(&ctx
->ac
, &primemit_scan
[stream
]);
2808 ac_build_s_barrier(&ctx
->ac
);
2810 /* Fetch the per-buffer offsets and per-stream emit counts in all waves. */
2811 LLVMValueRef wgoffset_dw
[4] = {};
2814 LLVMValueRef scratch_vgpr
;
2816 tmp
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, ac_get_thread_id(&ctx
->ac
));
2817 scratch_vgpr
= LLVMBuildLoad(builder
, tmp
, "");
2819 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
2820 if (stream_for_buffer
[buffer
] >= 0) {
2821 wgoffset_dw
[buffer
] = ac_build_readlane(
2822 &ctx
->ac
, scratch_vgpr
,
2823 LLVMConstInt(ctx
->ac
.i32
, scratch_offset_base
+ buffer
, false));
2827 for (unsigned stream
= 0; stream
< 4; ++stream
) {
2828 if (ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
]) {
2829 nggso
->emit
[stream
] = ac_build_readlane(
2830 &ctx
->ac
, scratch_vgpr
,
2831 LLVMConstInt(ctx
->ac
.i32
, scratch_emit_base
+ stream
, false));
2836 /* Write out primitive data */
2837 for (unsigned stream
= 0; stream
< 4; ++stream
) {
2838 if (!ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
])
2842 ac_build_wg_scan_bottom(&ctx
->ac
, &primemit_scan
[stream
]);
2844 primemit_scan
[stream
].result_exclusive
= tid
;
2847 cond
= LLVMBuildICmp(builder
, LLVMIntULT
,
2848 primemit_scan
[stream
].result_exclusive
,
2849 nggso
->emit
[stream
], "");
2850 cond
= LLVMBuildAnd(builder
, cond
, nggso
->prim_enable
[stream
], "");
2851 ac_build_ifcc(&ctx
->ac
, cond
, 5240);
2853 LLVMValueRef offset_vtx
=
2854 LLVMBuildMul(builder
, primemit_scan
[stream
].result_exclusive
,
2855 nggso
->num_vertices
, "");
2857 for (unsigned i
= 0; i
< max_num_vertices
; ++i
) {
2858 cond
= LLVMBuildICmp(builder
, LLVMIntULT
,
2859 LLVMConstInt(ctx
->ac
.i32
, i
, false),
2860 nggso
->num_vertices
, "");
2861 ac_build_ifcc(&ctx
->ac
, cond
, 5241);
2862 build_streamout_vertex(ctx
, so_buffer
, wgoffset_dw
,
2863 stream
, offset_vtx
, nggso
->vertices
[i
]);
2864 ac_build_endif(&ctx
->ac
, 5241);
2865 offset_vtx
= LLVMBuildAdd(builder
, offset_vtx
, ctx
->ac
.i32_1
, "");
2868 ac_build_endif(&ctx
->ac
, 5240);
2872 static unsigned ngg_nogs_vertex_size(struct radv_shader_context
*ctx
)
2874 unsigned lds_vertex_size
= 0;
2876 if (ctx
->args
->shader_info
->so
.num_outputs
)
2877 lds_vertex_size
= 4 * ctx
->args
->shader_info
->so
.num_outputs
+ 1;
2879 return lds_vertex_size
;
2883 * Returns an `[N x i32] addrspace(LDS)*` pointing at contiguous LDS storage
2884 * for the vertex outputs.
2886 static LLVMValueRef
ngg_nogs_vertex_ptr(struct radv_shader_context
*ctx
,
2889 /* The extra dword is used to avoid LDS bank conflicts. */
2890 unsigned vertex_size
= ngg_nogs_vertex_size(ctx
);
2891 LLVMTypeRef ai32
= LLVMArrayType(ctx
->ac
.i32
, vertex_size
);
2892 LLVMTypeRef pai32
= LLVMPointerType(ai32
, AC_ADDR_SPACE_LDS
);
2893 LLVMValueRef tmp
= LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->esgs_ring
, pai32
, "");
2894 return LLVMBuildGEP(ctx
->ac
.builder
, tmp
, &vtxid
, 1, "");
2898 handle_ngg_outputs_post_1(struct radv_shader_context
*ctx
)
2900 struct radv_streamout_info
*so
= &ctx
->args
->shader_info
->so
;
2901 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2902 LLVMValueRef vertex_ptr
= NULL
;
2903 LLVMValueRef tmp
, tmp2
;
2905 assert((ctx
->stage
== MESA_SHADER_VERTEX
||
2906 ctx
->stage
== MESA_SHADER_TESS_EVAL
) && !ctx
->args
->is_gs_copy_shader
);
2908 if (!ctx
->args
->shader_info
->so
.num_outputs
)
2911 vertex_ptr
= ngg_nogs_vertex_ptr(ctx
, get_thread_id_in_tg(ctx
));
2913 for (unsigned i
= 0; i
< so
->num_outputs
; ++i
) {
2914 struct radv_stream_output
*output
=
2915 &ctx
->args
->shader_info
->so
.outputs
[i
];
2917 unsigned loc
= output
->location
;
2919 for (unsigned comp
= 0; comp
< 4; comp
++) {
2920 if (!(output
->component_mask
& (1 << comp
)))
2923 tmp
= ac_build_gep0(&ctx
->ac
, vertex_ptr
,
2924 LLVMConstInt(ctx
->ac
.i32
, 4 * i
+ comp
, false));
2925 tmp2
= LLVMBuildLoad(builder
,
2926 ctx
->abi
.outputs
[4 * loc
+ comp
], "");
2927 tmp2
= ac_to_integer(&ctx
->ac
, tmp2
);
2928 LLVMBuildStore(builder
, tmp2
, tmp
);
2934 handle_ngg_outputs_post_2(struct radv_shader_context
*ctx
)
2936 LLVMBuilderRef builder
= ctx
->ac
.builder
;
2939 assert((ctx
->stage
== MESA_SHADER_VERTEX
||
2940 ctx
->stage
== MESA_SHADER_TESS_EVAL
) && !ctx
->args
->is_gs_copy_shader
);
2942 LLVMValueRef prims_in_wave
= ac_unpack_param(&ctx
->ac
,
2943 ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
), 8, 8);
2944 LLVMValueRef vtx_in_wave
= ac_unpack_param(&ctx
->ac
,
2945 ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
), 0, 8);
2946 LLVMValueRef is_gs_thread
= LLVMBuildICmp(builder
, LLVMIntULT
,
2947 ac_get_thread_id(&ctx
->ac
), prims_in_wave
, "");
2948 LLVMValueRef is_es_thread
= LLVMBuildICmp(builder
, LLVMIntULT
,
2949 ac_get_thread_id(&ctx
->ac
), vtx_in_wave
, "");
2950 LLVMValueRef vtxindex
[] = {
2951 ac_unpack_param(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->gs_vtx_offset
[0]), 0, 16),
2952 ac_unpack_param(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->gs_vtx_offset
[0]), 16, 16),
2953 ac_unpack_param(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->gs_vtx_offset
[2]), 0, 16),
2956 /* Determine the number of vertices per primitive. */
2957 unsigned num_vertices
;
2958 LLVMValueRef num_vertices_val
;
2960 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2961 LLVMValueRef outprim_val
=
2962 LLVMConstInt(ctx
->ac
.i32
,
2963 ctx
->args
->options
->key
.vs
.outprim
, false);
2964 num_vertices_val
= LLVMBuildAdd(builder
, outprim_val
,
2966 num_vertices
= 3; /* TODO: optimize for points & lines */
2968 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
2970 if (ctx
->shader
->info
.tess
.point_mode
)
2972 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
2977 num_vertices_val
= LLVMConstInt(ctx
->ac
.i32
, num_vertices
, false);
2981 if (ctx
->args
->shader_info
->so
.num_outputs
) {
2982 struct ngg_streamout nggso
= {};
2984 nggso
.num_vertices
= num_vertices_val
;
2985 nggso
.prim_enable
[0] = is_gs_thread
;
2987 for (unsigned i
= 0; i
< num_vertices
; ++i
)
2988 nggso
.vertices
[i
] = ngg_nogs_vertex_ptr(ctx
, vtxindex
[i
]);
2990 build_streamout(ctx
, &nggso
);
2993 /* Copy Primitive IDs from GS threads to the LDS address corresponding
2994 * to the ES thread of the provoking vertex.
2996 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
2997 ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
2998 if (ctx
->args
->shader_info
->so
.num_outputs
)
2999 ac_build_s_barrier(&ctx
->ac
);
3001 ac_build_ifcc(&ctx
->ac
, is_gs_thread
, 5400);
3002 /* Extract the PROVOKING_VTX_INDEX field. */
3003 LLVMValueRef provoking_vtx_in_prim
=
3004 LLVMConstInt(ctx
->ac
.i32
, 0, false);
3006 /* provoking_vtx_index = vtxindex[provoking_vtx_in_prim]; */
3007 LLVMValueRef indices
= ac_build_gather_values(&ctx
->ac
, vtxindex
, 3);
3008 LLVMValueRef provoking_vtx_index
=
3009 LLVMBuildExtractElement(builder
, indices
, provoking_vtx_in_prim
, "");
3011 LLVMBuildStore(builder
, ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.gs_prim_id
),
3012 ac_build_gep0(&ctx
->ac
, ctx
->esgs_ring
, provoking_vtx_index
));
3013 ac_build_endif(&ctx
->ac
, 5400);
3016 /* TODO: primitive culling */
3018 build_sendmsg_gs_alloc_req(ctx
, ngg_get_vtx_cnt(ctx
), ngg_get_prim_cnt(ctx
));
3020 /* TODO: streamout queries */
3021 /* Export primitive data to the index buffer. Format is:
3022 * - bits 0..8: index 0
3023 * - bit 9: edge flag 0
3024 * - bits 10..18: index 1
3025 * - bit 19: edge flag 1
3026 * - bits 20..28: index 2
3027 * - bit 29: edge flag 2
3028 * - bit 31: null primitive (skip)
3030 * For the first version, we will always build up all three indices
3031 * independent of the primitive type. The additional garbage data
3034 * TODO: culling depends on the primitive type, so can have some
3037 ac_build_ifcc(&ctx
->ac
, is_gs_thread
, 6001);
3039 struct ngg_prim prim
= {};
3041 prim
.num_vertices
= num_vertices
;
3042 prim
.isnull
= ctx
->ac
.i1false
;
3043 prim
.swap
= ctx
->ac
.i1false
;
3044 memcpy(prim
.index
, vtxindex
, sizeof(vtxindex
[0]) * 3);
3046 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
3047 tmp
= LLVMBuildLShr(builder
,
3048 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.gs_invocation_id
),
3049 LLVMConstInt(ctx
->ac
.i32
, 8 + i
, false), "");
3050 prim
.edgeflag
[i
] = LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
3053 build_export_prim(ctx
, &prim
);
3055 ac_build_endif(&ctx
->ac
, 6001);
3057 /* Export per-vertex data (positions and parameters). */
3058 ac_build_ifcc(&ctx
->ac
, is_es_thread
, 6002);
3060 struct radv_vs_output_info
*outinfo
=
3061 ctx
->stage
== MESA_SHADER_TESS_EVAL
?
3062 &ctx
->args
->shader_info
->tes
.outinfo
: &ctx
->args
->shader_info
->vs
.outinfo
;
3064 /* Exporting the primitive ID is handled below. */
3065 /* TODO: use the new VS export path */
3066 handle_vs_outputs_post(ctx
, false,
3067 ctx
->args
->options
->key
.vs_common_out
.export_clip_dists
,
3070 if (ctx
->args
->options
->key
.vs_common_out
.export_prim_id
) {
3071 unsigned param_count
= outinfo
->param_exports
;
3072 LLVMValueRef values
[4];
3074 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
3075 /* Wait for GS stores to finish. */
3076 ac_build_s_barrier(&ctx
->ac
);
3078 tmp
= ac_build_gep0(&ctx
->ac
, ctx
->esgs_ring
,
3079 get_thread_id_in_tg(ctx
));
3080 values
[0] = LLVMBuildLoad(builder
, tmp
, "");
3082 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
3083 values
[0] = ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.tes_patch_id
);
3086 values
[0] = ac_to_float(&ctx
->ac
, values
[0]);
3087 for (unsigned j
= 1; j
< 4; j
++)
3088 values
[j
] = ctx
->ac
.f32_0
;
3090 radv_export_param(ctx
, param_count
, values
, 0x1);
3092 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
++;
3093 outinfo
->param_exports
= param_count
;
3096 ac_build_endif(&ctx
->ac
, 6002);
3099 static void gfx10_ngg_gs_emit_prologue(struct radv_shader_context
*ctx
)
3101 /* Zero out the part of LDS scratch that is used to accumulate the
3102 * per-stream generated primitive count.
3104 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3105 LLVMValueRef scratchptr
= ctx
->gs_ngg_scratch
;
3106 LLVMValueRef tid
= get_thread_id_in_tg(ctx
);
3107 LLVMBasicBlockRef merge_block
;
3110 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
->ac
.builder
));
3111 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
3112 merge_block
= LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
3114 cond
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
3115 LLVMBuildCondBr(ctx
->ac
.builder
, cond
, then_block
, merge_block
);
3116 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, then_block
);
3118 LLVMValueRef ptr
= ac_build_gep0(&ctx
->ac
, scratchptr
, tid
);
3119 LLVMBuildStore(builder
, ctx
->ac
.i32_0
, ptr
);
3121 LLVMBuildBr(ctx
->ac
.builder
, merge_block
);
3122 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, merge_block
);
3124 ac_build_s_barrier(&ctx
->ac
);
3127 static void gfx10_ngg_gs_emit_epilogue_1(struct radv_shader_context
*ctx
)
3129 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3130 LLVMValueRef i8_0
= LLVMConstInt(ctx
->ac
.i8
, 0, false);
3133 /* Zero out remaining (non-emitted) primitive flags.
3135 * Note: Alternatively, we could pass the relevant gs_next_vertex to
3136 * the emit threads via LDS. This is likely worse in the expected
3137 * typical case where each GS thread emits the full set of
3140 for (unsigned stream
= 0; stream
< 4; ++stream
) {
3141 unsigned num_components
;
3144 ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
];
3145 if (!num_components
)
3148 const LLVMValueRef gsthread
= get_thread_id_in_tg(ctx
);
3150 ac_build_bgnloop(&ctx
->ac
, 5100);
3152 const LLVMValueRef vertexidx
=
3153 LLVMBuildLoad(builder
, ctx
->gs_next_vertex
[stream
], "");
3154 tmp
= LLVMBuildICmp(builder
, LLVMIntUGE
, vertexidx
,
3155 LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.gs
.vertices_out
, false), "");
3156 ac_build_ifcc(&ctx
->ac
, tmp
, 5101);
3157 ac_build_break(&ctx
->ac
);
3158 ac_build_endif(&ctx
->ac
, 5101);
3160 tmp
= LLVMBuildAdd(builder
, vertexidx
, ctx
->ac
.i32_1
, "");
3161 LLVMBuildStore(builder
, tmp
, ctx
->gs_next_vertex
[stream
]);
3163 tmp
= ngg_gs_emit_vertex_ptr(ctx
, gsthread
, vertexidx
);
3164 LLVMValueRef gep_idx
[3] = {
3165 ctx
->ac
.i32_0
, /* implied C-style array */
3166 ctx
->ac
.i32_1
, /* second entry of struct */
3167 LLVMConstInt(ctx
->ac
.i32
, stream
, false),
3169 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3170 LLVMBuildStore(builder
, i8_0
, tmp
);
3172 ac_build_endloop(&ctx
->ac
, 5100);
3175 /* Accumulate generated primitives counts across the entire threadgroup. */
3176 for (unsigned stream
= 0; stream
< 4; ++stream
) {
3177 unsigned num_components
;
3180 ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
];
3181 if (!num_components
)
3184 LLVMValueRef numprims
=
3185 LLVMBuildLoad(builder
, ctx
->gs_generated_prims
[stream
], "");
3186 numprims
= ac_build_reduce(&ctx
->ac
, numprims
, nir_op_iadd
, ctx
->ac
.wave_size
);
3188 tmp
= LLVMBuildICmp(builder
, LLVMIntEQ
, ac_get_thread_id(&ctx
->ac
), ctx
->ac
.i32_0
, "");
3189 ac_build_ifcc(&ctx
->ac
, tmp
, 5105);
3191 LLVMBuildAtomicRMW(builder
, LLVMAtomicRMWBinOpAdd
,
3192 ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
,
3193 LLVMConstInt(ctx
->ac
.i32
, stream
, false)),
3194 numprims
, LLVMAtomicOrderingMonotonic
, false);
3196 ac_build_endif(&ctx
->ac
, 5105);
3200 static void gfx10_ngg_gs_emit_epilogue_2(struct radv_shader_context
*ctx
)
3202 const unsigned verts_per_prim
= si_conv_gl_prim_to_vertices(ctx
->shader
->info
.gs
.output_primitive
);
3203 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3204 LLVMValueRef tmp
, tmp2
;
3206 ac_build_s_barrier(&ctx
->ac
);
3208 const LLVMValueRef tid
= get_thread_id_in_tg(ctx
);
3209 LLVMValueRef num_emit_threads
= ngg_get_prim_cnt(ctx
);
3212 if (ctx
->args
->shader_info
->so
.num_outputs
) {
3213 struct ngg_streamout nggso
= {};
3215 nggso
.num_vertices
= LLVMConstInt(ctx
->ac
.i32
, verts_per_prim
, false);
3217 LLVMValueRef vertexptr
= ngg_gs_vertex_ptr(ctx
, tid
);
3218 for (unsigned stream
= 0; stream
< 4; ++stream
) {
3219 if (!ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
])
3222 LLVMValueRef gep_idx
[3] = {
3223 ctx
->ac
.i32_0
, /* implicit C-style array */
3224 ctx
->ac
.i32_1
, /* second value of struct */
3225 LLVMConstInt(ctx
->ac
.i32
, stream
, false),
3227 tmp
= LLVMBuildGEP(builder
, vertexptr
, gep_idx
, 3, "");
3228 tmp
= LLVMBuildLoad(builder
, tmp
, "");
3229 tmp
= LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
3230 tmp2
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, num_emit_threads
, "");
3231 nggso
.prim_enable
[stream
] = LLVMBuildAnd(builder
, tmp
, tmp2
, "");
3234 for (unsigned i
= 0; i
< verts_per_prim
; ++i
) {
3235 tmp
= LLVMBuildSub(builder
, tid
,
3236 LLVMConstInt(ctx
->ac
.i32
, verts_per_prim
- i
- 1, false), "");
3237 tmp
= ngg_gs_vertex_ptr(ctx
, tmp
);
3238 nggso
.vertices
[i
] = ac_build_gep0(&ctx
->ac
, tmp
, ctx
->ac
.i32_0
);
3241 build_streamout(ctx
, &nggso
);
3246 /* Determine vertex liveness. */
3247 LLVMValueRef vertliveptr
= ac_build_alloca(&ctx
->ac
, ctx
->ac
.i1
, "vertexlive");
3249 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, num_emit_threads
, "");
3250 ac_build_ifcc(&ctx
->ac
, tmp
, 5120);
3252 for (unsigned i
= 0; i
< verts_per_prim
; ++i
) {
3253 const LLVMValueRef primidx
=
3254 LLVMBuildAdd(builder
, tid
,
3255 LLVMConstInt(ctx
->ac
.i32
, i
, false), "");
3258 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, primidx
, num_emit_threads
, "");
3259 ac_build_ifcc(&ctx
->ac
, tmp
, 5121 + i
);
3262 /* Load primitive liveness */
3263 tmp
= ngg_gs_vertex_ptr(ctx
, primidx
);
3264 LLVMValueRef gep_idx
[3] = {
3265 ctx
->ac
.i32_0
, /* implicit C-style array */
3266 ctx
->ac
.i32_1
, /* second value of struct */
3267 ctx
->ac
.i32_0
, /* stream 0 */
3269 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3270 tmp
= LLVMBuildLoad(builder
, tmp
, "");
3271 const LLVMValueRef primlive
=
3272 LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
3274 tmp
= LLVMBuildLoad(builder
, vertliveptr
, "");
3275 tmp
= LLVMBuildOr(builder
, tmp
, primlive
, ""),
3276 LLVMBuildStore(builder
, tmp
, vertliveptr
);
3279 ac_build_endif(&ctx
->ac
, 5121 + i
);
3282 ac_build_endif(&ctx
->ac
, 5120);
3284 /* Inclusive scan addition across the current wave. */
3285 LLVMValueRef vertlive
= LLVMBuildLoad(builder
, vertliveptr
, "");
3286 struct ac_wg_scan vertlive_scan
= {};
3287 vertlive_scan
.op
= nir_op_iadd
;
3288 vertlive_scan
.enable_reduce
= true;
3289 vertlive_scan
.enable_exclusive
= true;
3290 vertlive_scan
.src
= vertlive
;
3291 vertlive_scan
.scratch
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, ctx
->ac
.i32_0
);
3292 vertlive_scan
.waveidx
= get_wave_id_in_tg(ctx
);
3293 vertlive_scan
.numwaves
= get_tgsize(ctx
);
3294 vertlive_scan
.maxwaves
= 8;
3296 ac_build_wg_scan(&ctx
->ac
, &vertlive_scan
);
3298 /* Skip all exports (including index exports) when possible. At least on
3299 * early gfx10 revisions this is also to avoid hangs.
3301 LLVMValueRef have_exports
=
3302 LLVMBuildICmp(builder
, LLVMIntNE
, vertlive_scan
.result_reduce
, ctx
->ac
.i32_0
, "");
3304 LLVMBuildSelect(builder
, have_exports
, num_emit_threads
, ctx
->ac
.i32_0
, "");
3306 /* Allocate export space. Send this message as early as possible, to
3307 * hide the latency of the SQ <-> SPI roundtrip.
3309 * Note: We could consider compacting primitives for export as well.
3310 * PA processes 1 non-null prim / clock, but it fetches 4 DW of
3311 * prim data per clock and skips null primitives at no additional
3312 * cost. So compacting primitives can only be beneficial when
3313 * there are 4 or more contiguous null primitives in the export
3314 * (in the common case of single-dword prim exports).
3316 build_sendmsg_gs_alloc_req(ctx
, vertlive_scan
.result_reduce
, num_emit_threads
);
3318 /* Setup the reverse vertex compaction permutation. We re-use stream 1
3319 * of the primitive liveness flags, relying on the fact that each
3320 * threadgroup can have at most 256 threads. */
3321 ac_build_ifcc(&ctx
->ac
, vertlive
, 5130);
3323 tmp
= ngg_gs_vertex_ptr(ctx
, vertlive_scan
.result_exclusive
);
3324 LLVMValueRef gep_idx
[3] = {
3325 ctx
->ac
.i32_0
, /* implicit C-style array */
3326 ctx
->ac
.i32_1
, /* second value of struct */
3327 ctx
->ac
.i32_1
, /* stream 1 */
3329 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3330 tmp2
= LLVMBuildTrunc(builder
, tid
, ctx
->ac
.i8
, "");
3331 LLVMBuildStore(builder
, tmp2
, tmp
);
3333 ac_build_endif(&ctx
->ac
, 5130);
3335 ac_build_s_barrier(&ctx
->ac
);
3337 /* Export primitive data */
3338 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, num_emit_threads
, "");
3339 ac_build_ifcc(&ctx
->ac
, tmp
, 5140);
3341 struct ngg_prim prim
= {};
3342 prim
.num_vertices
= verts_per_prim
;
3344 tmp
= ngg_gs_vertex_ptr(ctx
, tid
);
3345 LLVMValueRef gep_idx
[3] = {
3346 ctx
->ac
.i32_0
, /* implicit C-style array */
3347 ctx
->ac
.i32_1
, /* second value of struct */
3348 ctx
->ac
.i32_0
, /* primflag */
3350 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3351 tmp
= LLVMBuildLoad(builder
, tmp
, "");
3352 prim
.isnull
= LLVMBuildICmp(builder
, LLVMIntEQ
, tmp
,
3353 LLVMConstInt(ctx
->ac
.i8
, 0, false), "");
3354 prim
.swap
= LLVMBuildICmp(builder
, LLVMIntEQ
,
3355 LLVMBuildAnd(builder
, tid
, LLVMConstInt(ctx
->ac
.i32
, 1, false), ""),
3356 LLVMConstInt(ctx
->ac
.i32
, 1, false), "");
3358 for (unsigned i
= 0; i
< verts_per_prim
; ++i
) {
3359 prim
.index
[i
] = LLVMBuildSub(builder
, vertlive_scan
.result_exclusive
,
3360 LLVMConstInt(ctx
->ac
.i32
, verts_per_prim
- i
- 1, false), "");
3361 prim
.edgeflag
[i
] = ctx
->ac
.i1false
;
3364 build_export_prim(ctx
, &prim
);
3366 ac_build_endif(&ctx
->ac
, 5140);
3368 /* Export position and parameter data */
3369 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, vertlive_scan
.result_reduce
, "");
3370 ac_build_ifcc(&ctx
->ac
, tmp
, 5145);
3372 struct radv_vs_output_info
*outinfo
= &ctx
->args
->shader_info
->vs
.outinfo
;
3373 bool export_view_index
= ctx
->args
->options
->key
.has_multiview_view_index
;
3374 struct radv_shader_output_values
*outputs
;
3375 unsigned noutput
= 0;
3377 /* Allocate a temporary array for the output values. */
3378 unsigned num_outputs
= util_bitcount64(ctx
->output_mask
) + export_view_index
;
3379 outputs
= calloc(num_outputs
, sizeof(outputs
[0]));
3381 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
3382 sizeof(outinfo
->vs_output_param_offset
));
3383 outinfo
->pos_exports
= 0;
3385 tmp
= ngg_gs_vertex_ptr(ctx
, tid
);
3386 LLVMValueRef gep_idx
[3] = {
3387 ctx
->ac
.i32_0
, /* implicit C-style array */
3388 ctx
->ac
.i32_1
, /* second value of struct */
3389 ctx
->ac
.i32_1
, /* stream 1: source data index */
3391 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3392 tmp
= LLVMBuildLoad(builder
, tmp
, "");
3393 tmp
= LLVMBuildZExt(builder
, tmp
, ctx
->ac
.i32
, "");
3394 const LLVMValueRef vertexptr
= ngg_gs_vertex_ptr(ctx
, tmp
);
3396 unsigned out_idx
= 0;
3397 gep_idx
[1] = ctx
->ac
.i32_0
;
3398 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3399 unsigned output_usage_mask
=
3400 ctx
->args
->shader_info
->gs
.output_usage_mask
[i
];
3401 int length
= util_last_bit(output_usage_mask
);
3403 if (!(ctx
->output_mask
& (1ull << i
)))
3406 outputs
[noutput
].slot_name
= i
;
3407 outputs
[noutput
].slot_index
= i
== VARYING_SLOT_CLIP_DIST1
;
3408 outputs
[noutput
].usage_mask
= output_usage_mask
;
3410 for (unsigned j
= 0; j
< length
; j
++, out_idx
++) {
3411 if (!(output_usage_mask
& (1 << j
)))
3414 gep_idx
[2] = LLVMConstInt(ctx
->ac
.i32
, out_idx
, false);
3415 tmp
= LLVMBuildGEP(builder
, vertexptr
, gep_idx
, 3, "");
3416 tmp
= LLVMBuildLoad(builder
, tmp
, "");
3418 LLVMTypeRef type
= LLVMGetAllocatedType(ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
3419 if (ac_get_type_size(type
) == 2) {
3420 tmp
= ac_to_integer(&ctx
->ac
, tmp
);
3421 tmp
= LLVMBuildTrunc(ctx
->ac
.builder
, tmp
, ctx
->ac
.i16
, "");
3424 outputs
[noutput
].values
[j
] = ac_to_float(&ctx
->ac
, tmp
);
3427 for (unsigned j
= length
; j
< 4; j
++)
3428 outputs
[noutput
].values
[j
] = LLVMGetUndef(ctx
->ac
.f32
);
3433 /* Export ViewIndex. */
3434 if (export_view_index
) {
3435 outputs
[noutput
].slot_name
= VARYING_SLOT_LAYER
;
3436 outputs
[noutput
].slot_index
= 0;
3437 outputs
[noutput
].usage_mask
= 0x1;
3438 outputs
[noutput
].values
[0] =
3439 ac_to_float(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.view_index
));
3440 for (unsigned j
= 1; j
< 4; j
++)
3441 outputs
[noutput
].values
[j
] = ctx
->ac
.f32_0
;
3445 radv_llvm_export_vs(ctx
, outputs
, noutput
, outinfo
,
3446 ctx
->args
->options
->key
.vs_common_out
.export_clip_dists
);
3449 ac_build_endif(&ctx
->ac
, 5145);
3452 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context
*ctx
,
3454 LLVMValueRef
*addrs
)
3456 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3458 const LLVMValueRef vertexidx
=
3459 LLVMBuildLoad(builder
, ctx
->gs_next_vertex
[stream
], "");
3461 /* If this thread has already emitted the declared maximum number of
3462 * vertices, skip the write: excessive vertex emissions are not
3463 * supposed to have any effect.
3465 const LLVMValueRef can_emit
=
3466 LLVMBuildICmp(builder
, LLVMIntULT
, vertexidx
,
3467 LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.gs
.vertices_out
, false), "");
3468 ac_build_ifcc(&ctx
->ac
, can_emit
, 9001);
3470 tmp
= LLVMBuildAdd(builder
, vertexidx
, ctx
->ac
.i32_1
, "");
3471 tmp
= LLVMBuildSelect(builder
, can_emit
, tmp
, vertexidx
, "");
3472 LLVMBuildStore(builder
, tmp
, ctx
->gs_next_vertex
[stream
]);
3474 const LLVMValueRef vertexptr
=
3475 ngg_gs_emit_vertex_ptr(ctx
, get_thread_id_in_tg(ctx
), vertexidx
);
3476 unsigned out_idx
= 0;
3477 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3478 unsigned output_usage_mask
=
3479 ctx
->args
->shader_info
->gs
.output_usage_mask
[i
];
3480 uint8_t output_stream
=
3481 ctx
->args
->shader_info
->gs
.output_streams
[i
];
3482 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
3483 int length
= util_last_bit(output_usage_mask
);
3485 if (!(ctx
->output_mask
& (1ull << i
)) ||
3486 output_stream
!= stream
)
3489 for (unsigned j
= 0; j
< length
; j
++, out_idx
++) {
3490 if (!(output_usage_mask
& (1 << j
)))
3493 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
,
3495 LLVMValueRef gep_idx
[3] = {
3496 ctx
->ac
.i32_0
, /* implied C-style array */
3497 ctx
->ac
.i32_0
, /* first entry of struct */
3498 LLVMConstInt(ctx
->ac
.i32
, out_idx
, false),
3500 LLVMValueRef ptr
= LLVMBuildGEP(builder
, vertexptr
, gep_idx
, 3, "");
3502 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
3503 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
3505 LLVMBuildStore(builder
, out_val
, ptr
);
3508 assert(out_idx
* 4 <= ctx
->args
->shader_info
->gs
.gsvs_vertex_size
);
3510 /* Determine and store whether this vertex completed a primitive. */
3511 const LLVMValueRef curverts
= LLVMBuildLoad(builder
, ctx
->gs_curprim_verts
[stream
], "");
3513 tmp
= LLVMConstInt(ctx
->ac
.i32
, si_conv_gl_prim_to_vertices(ctx
->shader
->info
.gs
.output_primitive
) - 1, false);
3514 const LLVMValueRef iscompleteprim
=
3515 LLVMBuildICmp(builder
, LLVMIntUGE
, curverts
, tmp
, "");
3517 tmp
= LLVMBuildAdd(builder
, curverts
, ctx
->ac
.i32_1
, "");
3518 LLVMBuildStore(builder
, tmp
, ctx
->gs_curprim_verts
[stream
]);
3520 LLVMValueRef gep_idx
[3] = {
3521 ctx
->ac
.i32_0
, /* implied C-style array */
3522 ctx
->ac
.i32_1
, /* second struct entry */
3523 LLVMConstInt(ctx
->ac
.i32
, stream
, false),
3525 const LLVMValueRef primflagptr
=
3526 LLVMBuildGEP(builder
, vertexptr
, gep_idx
, 3, "");
3528 tmp
= LLVMBuildZExt(builder
, iscompleteprim
, ctx
->ac
.i8
, "");
3529 LLVMBuildStore(builder
, tmp
, primflagptr
);
3531 tmp
= LLVMBuildLoad(builder
, ctx
->gs_generated_prims
[stream
], "");
3532 tmp
= LLVMBuildAdd(builder
, tmp
, LLVMBuildZExt(builder
, iscompleteprim
, ctx
->ac
.i32
, ""), "");
3533 LLVMBuildStore(builder
, tmp
, ctx
->gs_generated_prims
[stream
]);
3535 ac_build_endif(&ctx
->ac
, 9001);
3539 write_tess_factors(struct radv_shader_context
*ctx
)
3541 unsigned stride
, outer_comps
, inner_comps
;
3542 LLVMValueRef tcs_rel_ids
= ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.tcs_rel_ids
);
3543 LLVMValueRef invocation_id
= ac_unpack_param(&ctx
->ac
, tcs_rel_ids
, 8, 5);
3544 LLVMValueRef rel_patch_id
= ac_unpack_param(&ctx
->ac
, tcs_rel_ids
, 0, 8);
3545 unsigned tess_inner_index
= 0, tess_outer_index
;
3546 LLVMValueRef lds_base
, lds_inner
= NULL
, lds_outer
, byteoffset
, buffer
;
3547 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
3549 ac_emit_barrier(&ctx
->ac
, ctx
->stage
);
3551 switch (ctx
->args
->options
->key
.tcs
.primitive_mode
) {
3571 ac_build_ifcc(&ctx
->ac
,
3572 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3573 invocation_id
, ctx
->ac
.i32_0
, ""), 6503);
3575 lds_base
= get_tcs_out_current_patch_data_offset(ctx
);
3578 tess_inner_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
3579 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3580 LLVMConstInt(ctx
->ac
.i32
, tess_inner_index
* 4, false), "");
3583 tess_outer_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
3584 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
3585 LLVMConstInt(ctx
->ac
.i32
, tess_outer_index
* 4, false), "");
3587 for (i
= 0; i
< 4; i
++) {
3588 inner
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
3589 outer
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
3593 if (ctx
->args
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
3594 outer
[0] = out
[1] = ac_lds_load(&ctx
->ac
, lds_outer
);
3595 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
3597 outer
[1] = out
[0] = ac_lds_load(&ctx
->ac
, lds_outer
);
3599 for (i
= 0; i
< outer_comps
; i
++) {
3601 ac_lds_load(&ctx
->ac
, lds_outer
);
3602 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
3605 for (i
= 0; i
< inner_comps
; i
++) {
3606 inner
[i
] = out
[outer_comps
+i
] =
3607 ac_lds_load(&ctx
->ac
, lds_inner
);
3608 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_inner
,
3613 /* Convert the outputs to vectors for stores. */
3614 vec0
= ac_build_gather_values(&ctx
->ac
, out
, MIN2(stride
, 4));
3618 vec1
= ac_build_gather_values(&ctx
->ac
, out
+ 4, stride
- 4);
3621 buffer
= ctx
->hs_ring_tess_factor
;
3622 tf_base
= ac_get_arg(&ctx
->ac
, ctx
->args
->tess_factor_offset
);
3623 byteoffset
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
3624 LLVMConstInt(ctx
->ac
.i32
, 4 * stride
, false), "");
3625 unsigned tf_offset
= 0;
3627 if (ctx
->ac
.chip_class
<= GFX8
) {
3628 ac_build_ifcc(&ctx
->ac
,
3629 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
3630 rel_patch_id
, ctx
->ac
.i32_0
, ""), 6504);
3632 /* Store the dynamic HS control word. */
3633 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
3634 LLVMConstInt(ctx
->ac
.i32
, 0x80000000, false),
3635 1, ctx
->ac
.i32_0
, tf_base
,
3639 ac_build_endif(&ctx
->ac
, 6504);
3642 /* Store the tessellation factors. */
3643 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
3644 MIN2(stride
, 4), byteoffset
, tf_base
,
3647 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
3648 stride
- 4, byteoffset
, tf_base
,
3649 16 + tf_offset
, ac_glc
);
3651 //store to offchip for TES to read - only if TES reads them
3652 if (ctx
->args
->options
->key
.tcs
.tes_reads_tess_factors
) {
3653 LLVMValueRef inner_vec
, outer_vec
, tf_outer_offset
;
3654 LLVMValueRef tf_inner_offset
;
3655 unsigned param_outer
, param_inner
;
3657 param_outer
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
3658 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
3659 LLVMConstInt(ctx
->ac
.i32
, param_outer
, 0));
3661 outer_vec
= ac_build_gather_values(&ctx
->ac
, outer
,
3662 util_next_power_of_two(outer_comps
));
3664 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, outer_vec
,
3665 outer_comps
, tf_outer_offset
,
3666 ac_get_arg(&ctx
->ac
, ctx
->args
->oc_lds
),
3669 param_inner
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
3670 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
3671 LLVMConstInt(ctx
->ac
.i32
, param_inner
, 0));
3673 inner_vec
= inner_comps
== 1 ? inner
[0] :
3674 ac_build_gather_values(&ctx
->ac
, inner
, inner_comps
);
3675 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, inner_vec
,
3676 inner_comps
, tf_inner_offset
,
3677 ac_get_arg(&ctx
->ac
, ctx
->args
->oc_lds
),
3682 ac_build_endif(&ctx
->ac
, 6503);
3686 handle_tcs_outputs_post(struct radv_shader_context
*ctx
)
3688 write_tess_factors(ctx
);
3692 si_export_mrt_color(struct radv_shader_context
*ctx
,
3693 LLVMValueRef
*color
, unsigned index
,
3694 struct ac_export_args
*args
)
3697 si_llvm_init_export_args(ctx
, color
, 0xf,
3698 V_008DFC_SQ_EXP_MRT
+ index
, args
);
3699 if (!args
->enabled_channels
)
3700 return false; /* unnecessary NULL export */
3706 radv_export_mrt_z(struct radv_shader_context
*ctx
,
3707 LLVMValueRef depth
, LLVMValueRef stencil
,
3708 LLVMValueRef samplemask
)
3710 struct ac_export_args args
;
3712 ac_export_mrt_z(&ctx
->ac
, depth
, stencil
, samplemask
, &args
);
3714 ac_build_export(&ctx
->ac
, &args
);
3718 handle_fs_outputs_post(struct radv_shader_context
*ctx
)
3721 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
3722 struct ac_export_args color_args
[8];
3724 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3725 LLVMValueRef values
[4];
3727 if (!(ctx
->output_mask
& (1ull << i
)))
3730 if (i
< FRAG_RESULT_DATA0
)
3733 for (unsigned j
= 0; j
< 4; j
++)
3734 values
[j
] = ac_to_float(&ctx
->ac
,
3735 radv_load_output(ctx
, i
, j
));
3737 bool ret
= si_export_mrt_color(ctx
, values
,
3738 i
- FRAG_RESULT_DATA0
,
3739 &color_args
[index
]);
3744 /* Process depth, stencil, samplemask. */
3745 if (ctx
->args
->shader_info
->ps
.writes_z
) {
3746 depth
= ac_to_float(&ctx
->ac
,
3747 radv_load_output(ctx
, FRAG_RESULT_DEPTH
, 0));
3749 if (ctx
->args
->shader_info
->ps
.writes_stencil
) {
3750 stencil
= ac_to_float(&ctx
->ac
,
3751 radv_load_output(ctx
, FRAG_RESULT_STENCIL
, 0));
3753 if (ctx
->args
->shader_info
->ps
.writes_sample_mask
) {
3754 samplemask
= ac_to_float(&ctx
->ac
,
3755 radv_load_output(ctx
, FRAG_RESULT_SAMPLE_MASK
, 0));
3758 /* Set the DONE bit on last non-null color export only if Z isn't
3762 !ctx
->args
->shader_info
->ps
.writes_z
&&
3763 !ctx
->args
->shader_info
->ps
.writes_stencil
&&
3764 !ctx
->args
->shader_info
->ps
.writes_sample_mask
) {
3765 unsigned last
= index
- 1;
3767 color_args
[last
].valid_mask
= 1; /* whether the EXEC mask is valid */
3768 color_args
[last
].done
= 1; /* DONE bit */
3771 /* Export PS outputs. */
3772 for (unsigned i
= 0; i
< index
; i
++)
3773 ac_build_export(&ctx
->ac
, &color_args
[i
]);
3775 if (depth
|| stencil
|| samplemask
)
3776 radv_export_mrt_z(ctx
, depth
, stencil
, samplemask
);
3778 ac_build_export_null(&ctx
->ac
);
3782 emit_gs_epilogue(struct radv_shader_context
*ctx
)
3784 if (ctx
->args
->options
->key
.vs_common_out
.as_ngg
) {
3785 gfx10_ngg_gs_emit_epilogue_1(ctx
);
3789 if (ctx
->ac
.chip_class
>= GFX10
)
3790 LLVMBuildFence(ctx
->ac
.builder
, LLVMAtomicOrderingRelease
, false, "");
3792 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
, ctx
->gs_wave_id
);
3796 handle_shader_outputs_post(struct ac_shader_abi
*abi
, unsigned max_outputs
,
3797 LLVMValueRef
*addrs
)
3799 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
3801 switch (ctx
->stage
) {
3802 case MESA_SHADER_VERTEX
:
3803 if (ctx
->args
->options
->key
.vs_common_out
.as_ls
)
3804 handle_ls_outputs_post(ctx
);
3805 else if (ctx
->args
->options
->key
.vs_common_out
.as_es
)
3806 handle_es_outputs_post(ctx
, &ctx
->args
->shader_info
->vs
.es_info
);
3807 else if (ctx
->args
->options
->key
.vs_common_out
.as_ngg
)
3808 handle_ngg_outputs_post_1(ctx
);
3810 handle_vs_outputs_post(ctx
, ctx
->args
->options
->key
.vs_common_out
.export_prim_id
,
3811 ctx
->args
->options
->key
.vs_common_out
.export_clip_dists
,
3812 &ctx
->args
->shader_info
->vs
.outinfo
);
3814 case MESA_SHADER_FRAGMENT
:
3815 handle_fs_outputs_post(ctx
);
3817 case MESA_SHADER_GEOMETRY
:
3818 emit_gs_epilogue(ctx
);
3820 case MESA_SHADER_TESS_CTRL
:
3821 handle_tcs_outputs_post(ctx
);
3823 case MESA_SHADER_TESS_EVAL
:
3824 if (ctx
->args
->options
->key
.vs_common_out
.as_es
)
3825 handle_es_outputs_post(ctx
, &ctx
->args
->shader_info
->tes
.es_info
);
3826 else if (ctx
->args
->options
->key
.vs_common_out
.as_ngg
)
3827 handle_ngg_outputs_post_1(ctx
);
3829 handle_vs_outputs_post(ctx
, ctx
->args
->options
->key
.vs_common_out
.export_prim_id
,
3830 ctx
->args
->options
->key
.vs_common_out
.export_clip_dists
,
3831 &ctx
->args
->shader_info
->tes
.outinfo
);
3838 static void ac_llvm_finalize_module(struct radv_shader_context
*ctx
,
3839 LLVMPassManagerRef passmgr
,
3840 const struct radv_nir_compiler_options
*options
)
3842 LLVMRunPassManager(passmgr
, ctx
->ac
.module
);
3843 LLVMDisposeBuilder(ctx
->ac
.builder
);
3845 ac_llvm_context_dispose(&ctx
->ac
);
3849 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context
*ctx
)
3851 struct radv_vs_output_info
*outinfo
;
3853 switch (ctx
->stage
) {
3854 case MESA_SHADER_FRAGMENT
:
3855 case MESA_SHADER_COMPUTE
:
3856 case MESA_SHADER_TESS_CTRL
:
3857 case MESA_SHADER_GEOMETRY
:
3859 case MESA_SHADER_VERTEX
:
3860 if (ctx
->args
->options
->key
.vs_common_out
.as_ls
||
3861 ctx
->args
->options
->key
.vs_common_out
.as_es
)
3863 outinfo
= &ctx
->args
->shader_info
->vs
.outinfo
;
3865 case MESA_SHADER_TESS_EVAL
:
3866 if (ctx
->args
->options
->key
.vs_common_out
.as_es
)
3868 outinfo
= &ctx
->args
->shader_info
->tes
.outinfo
;
3871 unreachable("Unhandled shader type");
3874 ac_optimize_vs_outputs(&ctx
->ac
,
3876 outinfo
->vs_output_param_offset
,
3878 &outinfo
->param_exports
);
3882 ac_setup_rings(struct radv_shader_context
*ctx
)
3884 if (ctx
->args
->options
->chip_class
<= GFX8
&&
3885 (ctx
->stage
== MESA_SHADER_GEOMETRY
||
3886 ctx
->args
->options
->key
.vs_common_out
.as_es
|| ctx
->args
->options
->key
.vs_common_out
.as_es
)) {
3887 unsigned ring
= ctx
->stage
== MESA_SHADER_GEOMETRY
? RING_ESGS_GS
3889 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, ring
, false);
3891 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
,
3896 if (ctx
->args
->is_gs_copy_shader
) {
3898 ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
,
3899 LLVMConstInt(ctx
->ac
.i32
,
3900 RING_GSVS_VS
, false));
3903 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
3904 /* The conceptual layout of the GSVS ring is
3905 * v0c0 .. vLv0 v0c1 .. vLc1 ..
3906 * but the real memory layout is swizzled across
3908 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
3910 * Override the buffer descriptor accordingly.
3912 LLVMTypeRef v2i64
= LLVMVectorType(ctx
->ac
.i64
, 2);
3913 uint64_t stream_offset
= 0;
3914 unsigned num_records
= ctx
->ac
.wave_size
;
3915 LLVMValueRef base_ring
;
3918 ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
,
3919 LLVMConstInt(ctx
->ac
.i32
,
3920 RING_GSVS_GS
, false));
3922 for (unsigned stream
= 0; stream
< 4; stream
++) {
3923 unsigned num_components
, stride
;
3924 LLVMValueRef ring
, tmp
;
3927 ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
];
3929 if (!num_components
)
3932 stride
= 4 * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
3934 /* Limit on the stride field for <= GFX7. */
3935 assert(stride
< (1 << 14));
3937 ring
= LLVMBuildBitCast(ctx
->ac
.builder
,
3938 base_ring
, v2i64
, "");
3939 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
,
3940 ring
, ctx
->ac
.i32_0
, "");
3941 tmp
= LLVMBuildAdd(ctx
->ac
.builder
, tmp
,
3942 LLVMConstInt(ctx
->ac
.i64
,
3943 stream_offset
, 0), "");
3944 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
,
3945 ring
, tmp
, ctx
->ac
.i32_0
, "");
3947 stream_offset
+= stride
* ctx
->ac
.wave_size
;
3949 ring
= LLVMBuildBitCast(ctx
->ac
.builder
, ring
,
3952 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
, ring
,
3954 tmp
= LLVMBuildOr(ctx
->ac
.builder
, tmp
,
3955 LLVMConstInt(ctx
->ac
.i32
,
3956 S_008F04_STRIDE(stride
), false), "");
3957 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ring
, tmp
,
3960 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ring
,
3961 LLVMConstInt(ctx
->ac
.i32
,
3962 num_records
, false),
3963 LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
3965 ctx
->gsvs_ring
[stream
] = ring
;
3969 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
3970 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
3971 ctx
->hs_ring_tess_offchip
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_OFFCHIP
, false));
3972 ctx
->hs_ring_tess_factor
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_FACTOR
, false));
3977 radv_nir_get_max_workgroup_size(enum chip_class chip_class
,
3978 gl_shader_stage stage
,
3979 const struct nir_shader
*nir
)
3981 const unsigned backup_sizes
[] = {chip_class
>= GFX9
? 128 : 64, 1, 1};
3983 for (unsigned i
= 0; i
< 3; i
++)
3984 sizes
[i
] = nir
? nir
->info
.cs
.local_size
[i
] : backup_sizes
[i
];
3985 return radv_get_max_workgroup_size(chip_class
, stage
, sizes
);
3988 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
3989 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context
*ctx
)
3991 LLVMValueRef count
=
3992 ac_unpack_param(&ctx
->ac
, ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
), 8, 8);
3993 LLVMValueRef hs_empty
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, count
,
3995 ctx
->abi
.instance_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
,
3996 ac_get_arg(&ctx
->ac
, ctx
->args
->rel_auto_id
),
3997 ctx
->abi
.instance_id
, "");
3998 ctx
->rel_auto_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
,
3999 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.tcs_rel_ids
),
4002 ctx
->abi
.vertex_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
,
4003 ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.tcs_patch_id
),
4004 ctx
->abi
.vertex_id
, "");
4007 static void prepare_gs_input_vgprs(struct radv_shader_context
*ctx
, bool merged
)
4010 for(int i
= 5; i
>= 0; --i
) {
4011 ctx
->gs_vtx_offset
[i
] =
4012 ac_unpack_param(&ctx
->ac
,
4013 ac_get_arg(&ctx
->ac
, ctx
->args
->gs_vtx_offset
[i
& ~1]),
4017 ctx
->gs_wave_id
= ac_unpack_param(&ctx
->ac
,
4018 ac_get_arg(&ctx
->ac
, ctx
->args
->merged_wave_info
),
4021 for (int i
= 0; i
< 6; i
++)
4022 ctx
->gs_vtx_offset
[i
] = ac_get_arg(&ctx
->ac
, ctx
->args
->gs_vtx_offset
[i
]);
4023 ctx
->gs_wave_id
= ac_get_arg(&ctx
->ac
, ctx
->args
->gs_wave_id
);
4027 /* Ensure that the esgs ring is declared.
4029 * We declare it with 64KB alignment as a hint that the
4030 * pointer value will always be 0.
4032 static void declare_esgs_ring(struct radv_shader_context
*ctx
)
4037 assert(!LLVMGetNamedGlobal(ctx
->ac
.module
, "esgs_ring"));
4039 ctx
->esgs_ring
= LLVMAddGlobalInAddressSpace(
4040 ctx
->ac
.module
, LLVMArrayType(ctx
->ac
.i32
, 0),
4043 LLVMSetLinkage(ctx
->esgs_ring
, LLVMExternalLinkage
);
4044 LLVMSetAlignment(ctx
->esgs_ring
, 64 * 1024);
4048 LLVMModuleRef
ac_translate_nir_to_llvm(struct ac_llvm_compiler
*ac_llvm
,
4049 struct nir_shader
*const *shaders
,
4051 const struct radv_shader_args
*args
)
4053 struct radv_shader_context ctx
= {0};
4056 enum ac_float_mode float_mode
= AC_FLOAT_MODE_DEFAULT
;
4058 if (args
->shader_info
->float_controls_mode
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
) {
4059 float_mode
= AC_FLOAT_MODE_DENORM_FLUSH_TO_ZERO
;
4062 ac_llvm_context_init(&ctx
.ac
, ac_llvm
, args
->options
->chip_class
,
4063 args
->options
->family
, float_mode
,
4064 args
->shader_info
->wave_size
, 64);
4065 ctx
.context
= ctx
.ac
.context
;
4067 ctx
.max_workgroup_size
= 0;
4068 for (int i
= 0; i
< shader_count
; ++i
) {
4069 ctx
.max_workgroup_size
= MAX2(ctx
.max_workgroup_size
,
4070 radv_nir_get_max_workgroup_size(args
->options
->chip_class
,
4071 shaders
[i
]->info
.stage
,
4075 if (ctx
.ac
.chip_class
>= GFX10
) {
4076 if (is_pre_gs_stage(shaders
[0]->info
.stage
) &&
4077 args
->options
->key
.vs_common_out
.as_ngg
) {
4078 ctx
.max_workgroup_size
= 128;
4082 create_function(&ctx
, shaders
[shader_count
- 1]->info
.stage
, shader_count
>= 2);
4084 ctx
.abi
.inputs
= &ctx
.inputs
[0];
4085 ctx
.abi
.emit_outputs
= handle_shader_outputs_post
;
4086 ctx
.abi
.emit_vertex
= visit_emit_vertex
;
4087 ctx
.abi
.load_ubo
= radv_load_ubo
;
4088 ctx
.abi
.load_ssbo
= radv_load_ssbo
;
4089 ctx
.abi
.load_sampler_desc
= radv_get_sampler_desc
;
4090 ctx
.abi
.load_resource
= radv_load_resource
;
4091 ctx
.abi
.clamp_shadow_reference
= false;
4092 ctx
.abi
.robust_buffer_access
= args
->options
->robust_buffer_access
;
4094 bool is_ngg
= is_pre_gs_stage(shaders
[0]->info
.stage
) && args
->options
->key
.vs_common_out
.as_ngg
;
4095 if (shader_count
>= 2 || is_ngg
)
4096 ac_init_exec_full_mask(&ctx
.ac
);
4098 if (args
->ac
.vertex_id
.used
)
4099 ctx
.abi
.vertex_id
= ac_get_arg(&ctx
.ac
, args
->ac
.vertex_id
);
4100 if (args
->rel_auto_id
.used
)
4101 ctx
.rel_auto_id
= ac_get_arg(&ctx
.ac
, args
->rel_auto_id
);
4102 if (args
->ac
.instance_id
.used
)
4103 ctx
.abi
.instance_id
= ac_get_arg(&ctx
.ac
, args
->ac
.instance_id
);
4105 if (args
->options
->has_ls_vgpr_init_bug
&&
4106 shaders
[shader_count
- 1]->info
.stage
== MESA_SHADER_TESS_CTRL
)
4107 ac_nir_fixup_ls_hs_input_vgprs(&ctx
);
4110 /* Declare scratch space base for streamout and vertex
4111 * compaction. Whether space is actually allocated is
4112 * determined during linking / PM4 creation.
4114 * Add an extra dword per vertex to ensure an odd stride, which
4115 * avoids bank conflicts for SoA accesses.
4117 declare_esgs_ring(&ctx
);
4119 /* This is really only needed when streamout and / or vertex
4120 * compaction is enabled.
4122 LLVMTypeRef asi32
= LLVMArrayType(ctx
.ac
.i32
, 8);
4123 ctx
.gs_ngg_scratch
= LLVMAddGlobalInAddressSpace(ctx
.ac
.module
,
4124 asi32
, "ngg_scratch", AC_ADDR_SPACE_LDS
);
4125 LLVMSetInitializer(ctx
.gs_ngg_scratch
, LLVMGetUndef(asi32
));
4126 LLVMSetAlignment(ctx
.gs_ngg_scratch
, 4);
4129 for(int i
= 0; i
< shader_count
; ++i
) {
4130 ctx
.stage
= shaders
[i
]->info
.stage
;
4131 ctx
.shader
= shaders
[i
];
4132 ctx
.output_mask
= 0;
4134 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
4135 for (int i
= 0; i
< 4; i
++) {
4136 ctx
.gs_next_vertex
[i
] =
4137 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
4139 if (args
->options
->key
.vs_common_out
.as_ngg
) {
4140 for (unsigned i
= 0; i
< 4; ++i
) {
4141 ctx
.gs_curprim_verts
[i
] =
4142 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
4143 ctx
.gs_generated_prims
[i
] =
4144 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
4147 unsigned scratch_size
= 8;
4148 if (args
->shader_info
->so
.num_outputs
)
4151 LLVMTypeRef ai32
= LLVMArrayType(ctx
.ac
.i32
, scratch_size
);
4152 ctx
.gs_ngg_scratch
=
4153 LLVMAddGlobalInAddressSpace(ctx
.ac
.module
,
4154 ai32
, "ngg_scratch", AC_ADDR_SPACE_LDS
);
4155 LLVMSetInitializer(ctx
.gs_ngg_scratch
, LLVMGetUndef(ai32
));
4156 LLVMSetAlignment(ctx
.gs_ngg_scratch
, 4);
4158 ctx
.gs_ngg_emit
= LLVMAddGlobalInAddressSpace(ctx
.ac
.module
,
4159 LLVMArrayType(ctx
.ac
.i32
, 0), "ngg_emit", AC_ADDR_SPACE_LDS
);
4160 LLVMSetLinkage(ctx
.gs_ngg_emit
, LLVMExternalLinkage
);
4161 LLVMSetAlignment(ctx
.gs_ngg_emit
, 4);
4164 ctx
.abi
.load_inputs
= load_gs_input
;
4165 ctx
.abi
.emit_primitive
= visit_end_primitive
;
4166 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4167 ctx
.abi
.load_tess_varyings
= load_tcs_varyings
;
4168 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
4169 ctx
.abi
.store_tcs_outputs
= store_tcs_output
;
4170 if (shader_count
== 1)
4171 ctx
.tcs_num_inputs
= args
->options
->key
.tcs
.num_inputs
;
4173 ctx
.tcs_num_inputs
= util_last_bit64(args
->shader_info
->vs
.ls_outputs_written
);
4174 ctx
.tcs_num_patches
= get_tcs_num_patches(&ctx
);
4175 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4176 ctx
.abi
.load_tess_varyings
= load_tes_input
;
4177 ctx
.abi
.load_tess_coord
= load_tess_coord
;
4178 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
4179 ctx
.tcs_num_patches
= args
->options
->key
.tes
.num_patches
;
4180 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
) {
4181 ctx
.abi
.load_base_vertex
= radv_load_base_vertex
;
4182 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
) {
4183 ctx
.abi
.load_sample_position
= load_sample_position
;
4184 ctx
.abi
.load_sample_mask_in
= load_sample_mask_in
;
4185 ctx
.abi
.emit_kill
= radv_emit_kill
;
4188 if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
&&
4189 args
->options
->key
.vs_common_out
.as_ngg
&&
4190 args
->options
->key
.vs_common_out
.export_prim_id
) {
4191 declare_esgs_ring(&ctx
);
4194 bool nested_barrier
= false;
4197 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
&&
4198 args
->options
->key
.vs_common_out
.as_ngg
) {
4199 gfx10_ngg_gs_emit_prologue(&ctx
);
4200 nested_barrier
= false;
4202 nested_barrier
= true;
4206 if (nested_barrier
) {
4207 /* Execute a barrier before the second shader in
4210 * Execute the barrier inside the conditional block,
4211 * so that empty waves can jump directly to s_endpgm,
4212 * which will also signal the barrier.
4214 * This is possible in gfx9, because an empty wave
4215 * for the second shader does not participate in
4216 * the epilogue. With NGG, empty waves may still
4217 * be required to export data (e.g. GS output vertices),
4218 * so we cannot let them exit early.
4220 * If the shader is TCS and the TCS epilog is present
4221 * and contains a barrier, it will wait there and then
4224 ac_emit_barrier(&ctx
.ac
, ctx
.stage
);
4227 nir_foreach_variable(variable
, &shaders
[i
]->outputs
)
4228 scan_shader_output_decl(&ctx
, variable
, shaders
[i
], shaders
[i
]->info
.stage
);
4230 ac_setup_rings(&ctx
);
4232 LLVMBasicBlockRef merge_block
;
4233 if (shader_count
>= 2 || is_ngg
) {
4234 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
4235 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
4236 merge_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
4238 LLVMValueRef count
=
4239 ac_unpack_param(&ctx
.ac
,
4240 ac_get_arg(&ctx
.ac
, args
->merged_wave_info
),
4242 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
.ac
);
4243 LLVMValueRef cond
= LLVMBuildICmp(ctx
.ac
.builder
, LLVMIntULT
,
4244 thread_id
, count
, "");
4245 LLVMBuildCondBr(ctx
.ac
.builder
, cond
, then_block
, merge_block
);
4247 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, then_block
);
4250 if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
)
4251 prepare_interp_optimize(&ctx
, shaders
[i
]);
4252 else if(shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
)
4253 handle_vs_inputs(&ctx
, shaders
[i
]);
4254 else if(shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
)
4255 prepare_gs_input_vgprs(&ctx
, shader_count
>= 2);
4257 ac_nir_translate(&ctx
.ac
, &ctx
.abi
, &args
->ac
, shaders
[i
]);
4259 if (shader_count
>= 2 || is_ngg
) {
4260 LLVMBuildBr(ctx
.ac
.builder
, merge_block
);
4261 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, merge_block
);
4264 /* This needs to be outside the if wrapping the shader body, as sometimes
4265 * the HW generates waves with 0 es/vs threads. */
4266 if (is_pre_gs_stage(shaders
[i
]->info
.stage
) &&
4267 args
->options
->key
.vs_common_out
.as_ngg
&&
4268 i
== shader_count
- 1) {
4269 handle_ngg_outputs_post_2(&ctx
);
4270 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
&&
4271 args
->options
->key
.vs_common_out
.as_ngg
) {
4272 gfx10_ngg_gs_emit_epilogue_2(&ctx
);
4275 if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4276 args
->shader_info
->tcs
.num_patches
= ctx
.tcs_num_patches
;
4277 args
->shader_info
->tcs
.lds_size
= calculate_tess_lds_size(&ctx
);
4281 LLVMBuildRetVoid(ctx
.ac
.builder
);
4283 if (args
->options
->dump_preoptir
) {
4284 fprintf(stderr
, "%s LLVM IR:\n\n",
4285 radv_get_shader_name(args
->shader_info
,
4286 shaders
[shader_count
- 1]->info
.stage
));
4287 ac_dump_module(ctx
.ac
.module
);
4288 fprintf(stderr
, "\n");
4291 ac_llvm_finalize_module(&ctx
, ac_llvm
->passmgr
, args
->options
);
4293 if (shader_count
== 1)
4294 ac_nir_eliminate_const_vs_outputs(&ctx
);
4296 if (args
->options
->dump_shader
) {
4297 args
->shader_info
->private_mem_vgprs
=
4298 ac_count_scratch_private_memory(ctx
.main_function
);
4301 return ctx
.ac
.module
;
4304 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di
, void *context
)
4306 unsigned *retval
= (unsigned *)context
;
4307 LLVMDiagnosticSeverity severity
= LLVMGetDiagInfoSeverity(di
);
4308 char *description
= LLVMGetDiagInfoDescription(di
);
4310 if (severity
== LLVMDSError
) {
4312 fprintf(stderr
, "LLVM triggered Diagnostic Handler: %s\n",
4316 LLVMDisposeMessage(description
);
4319 static unsigned radv_llvm_compile(LLVMModuleRef M
,
4320 char **pelf_buffer
, size_t *pelf_size
,
4321 struct ac_llvm_compiler
*ac_llvm
)
4323 unsigned retval
= 0;
4324 LLVMContextRef llvm_ctx
;
4326 /* Setup Diagnostic Handler*/
4327 llvm_ctx
= LLVMGetModuleContext(M
);
4329 LLVMContextSetDiagnosticHandler(llvm_ctx
, ac_diagnostic_handler
,
4333 if (!radv_compile_to_elf(ac_llvm
, M
, pelf_buffer
, pelf_size
))
4338 static void ac_compile_llvm_module(struct ac_llvm_compiler
*ac_llvm
,
4339 LLVMModuleRef llvm_module
,
4340 struct radv_shader_binary
**rbinary
,
4341 gl_shader_stage stage
,
4343 const struct radv_nir_compiler_options
*options
)
4345 char *elf_buffer
= NULL
;
4346 size_t elf_size
= 0;
4347 char *llvm_ir_string
= NULL
;
4349 if (options
->dump_shader
) {
4350 fprintf(stderr
, "%s LLVM IR:\n\n", name
);
4351 ac_dump_module(llvm_module
);
4352 fprintf(stderr
, "\n");
4355 if (options
->record_ir
) {
4356 char *llvm_ir
= LLVMPrintModuleToString(llvm_module
);
4357 llvm_ir_string
= strdup(llvm_ir
);
4358 LLVMDisposeMessage(llvm_ir
);
4361 int v
= radv_llvm_compile(llvm_module
, &elf_buffer
, &elf_size
, ac_llvm
);
4363 fprintf(stderr
, "compile failed\n");
4366 LLVMContextRef ctx
= LLVMGetModuleContext(llvm_module
);
4367 LLVMDisposeModule(llvm_module
);
4368 LLVMContextDispose(ctx
);
4370 size_t llvm_ir_size
= llvm_ir_string
? strlen(llvm_ir_string
) : 0;
4371 size_t alloc_size
= sizeof(struct radv_shader_binary_rtld
) + elf_size
+ llvm_ir_size
+ 1;
4372 struct radv_shader_binary_rtld
*rbin
= calloc(1, alloc_size
);
4373 memcpy(rbin
->data
, elf_buffer
, elf_size
);
4375 memcpy(rbin
->data
+ elf_size
, llvm_ir_string
, llvm_ir_size
+ 1);
4377 rbin
->base
.type
= RADV_BINARY_TYPE_RTLD
;
4378 rbin
->base
.stage
= stage
;
4379 rbin
->base
.total_size
= alloc_size
;
4380 rbin
->elf_size
= elf_size
;
4381 rbin
->llvm_ir_size
= llvm_ir_size
;
4382 *rbinary
= &rbin
->base
;
4384 free(llvm_ir_string
);
4389 radv_compile_nir_shader(struct ac_llvm_compiler
*ac_llvm
,
4390 struct radv_shader_binary
**rbinary
,
4391 const struct radv_shader_args
*args
,
4392 struct nir_shader
*const *nir
,
4396 LLVMModuleRef llvm_module
;
4398 llvm_module
= ac_translate_nir_to_llvm(ac_llvm
, nir
, nir_count
, args
);
4400 ac_compile_llvm_module(ac_llvm
, llvm_module
, rbinary
,
4401 nir
[nir_count
- 1]->info
.stage
,
4402 radv_get_shader_name(args
->shader_info
,
4403 nir
[nir_count
- 1]->info
.stage
),
4406 /* Determine the ES type (VS or TES) for the GS on GFX9. */
4407 if (args
->options
->chip_class
>= GFX9
) {
4408 if (nir_count
== 2 &&
4409 nir
[1]->info
.stage
== MESA_SHADER_GEOMETRY
) {
4410 args
->shader_info
->gs
.es_type
= nir
[0]->info
.stage
;
4416 ac_gs_copy_shader_emit(struct radv_shader_context
*ctx
)
4418 LLVMValueRef vtx_offset
=
4419 LLVMBuildMul(ctx
->ac
.builder
, ac_get_arg(&ctx
->ac
, ctx
->args
->ac
.vertex_id
),
4420 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
4421 LLVMValueRef stream_id
;
4423 /* Fetch the vertex stream ID. */
4424 if (!ctx
->args
->options
->use_ngg_streamout
&&
4425 ctx
->args
->shader_info
->so
.num_outputs
) {
4427 ac_unpack_param(&ctx
->ac
,
4428 ac_get_arg(&ctx
->ac
,
4429 ctx
->args
->streamout_config
),
4432 stream_id
= ctx
->ac
.i32_0
;
4435 LLVMBasicBlockRef end_bb
;
4436 LLVMValueRef switch_inst
;
4438 end_bb
= LLVMAppendBasicBlockInContext(ctx
->ac
.context
,
4439 ctx
->main_function
, "end");
4440 switch_inst
= LLVMBuildSwitch(ctx
->ac
.builder
, stream_id
, end_bb
, 4);
4442 for (unsigned stream
= 0; stream
< 4; stream
++) {
4443 unsigned num_components
=
4444 ctx
->args
->shader_info
->gs
.num_stream_output_components
[stream
];
4445 LLVMBasicBlockRef bb
;
4448 if (stream
> 0 && !num_components
)
4451 if (stream
> 0 && !ctx
->args
->shader_info
->so
.num_outputs
)
4454 bb
= LLVMInsertBasicBlockInContext(ctx
->ac
.context
, end_bb
, "out");
4455 LLVMAddCase(switch_inst
, LLVMConstInt(ctx
->ac
.i32
, stream
, 0), bb
);
4456 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, bb
);
4459 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
4460 unsigned output_usage_mask
=
4461 ctx
->args
->shader_info
->gs
.output_usage_mask
[i
];
4462 unsigned output_stream
=
4463 ctx
->args
->shader_info
->gs
.output_streams
[i
];
4464 int length
= util_last_bit(output_usage_mask
);
4466 if (!(ctx
->output_mask
& (1ull << i
)) ||
4467 output_stream
!= stream
)
4470 for (unsigned j
= 0; j
< length
; j
++) {
4471 LLVMValueRef value
, soffset
;
4473 if (!(output_usage_mask
& (1 << j
)))
4476 soffset
= LLVMConstInt(ctx
->ac
.i32
,
4478 ctx
->shader
->info
.gs
.vertices_out
* 16 * 4, false);
4482 value
= ac_build_buffer_load(&ctx
->ac
,
4485 vtx_offset
, soffset
,
4486 0, ac_glc
| ac_slc
, true, false);
4488 LLVMTypeRef type
= LLVMGetAllocatedType(ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
4489 if (ac_get_type_size(type
) == 2) {
4490 value
= LLVMBuildBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
4491 value
= LLVMBuildTrunc(ctx
->ac
.builder
, value
, ctx
->ac
.i16
, "");
4494 LLVMBuildStore(ctx
->ac
.builder
,
4495 ac_to_float(&ctx
->ac
, value
), ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
4499 if (!ctx
->args
->options
->use_ngg_streamout
&&
4500 ctx
->args
->shader_info
->so
.num_outputs
)
4501 radv_emit_streamout(ctx
, stream
);
4504 handle_vs_outputs_post(ctx
, false, true,
4505 &ctx
->args
->shader_info
->vs
.outinfo
);
4508 LLVMBuildBr(ctx
->ac
.builder
, end_bb
);
4511 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, end_bb
);
4515 radv_compile_gs_copy_shader(struct ac_llvm_compiler
*ac_llvm
,
4516 struct nir_shader
*geom_shader
,
4517 struct radv_shader_binary
**rbinary
,
4518 const struct radv_shader_args
*args
)
4520 struct radv_shader_context ctx
= {0};
4523 assert(args
->is_gs_copy_shader
);
4525 ac_llvm_context_init(&ctx
.ac
, ac_llvm
, args
->options
->chip_class
,
4526 args
->options
->family
, AC_FLOAT_MODE_DEFAULT
, 64, 64);
4527 ctx
.context
= ctx
.ac
.context
;
4529 ctx
.stage
= MESA_SHADER_VERTEX
;
4530 ctx
.shader
= geom_shader
;
4532 create_function(&ctx
, MESA_SHADER_VERTEX
, false);
4534 ac_setup_rings(&ctx
);
4536 nir_foreach_variable(variable
, &geom_shader
->outputs
) {
4537 scan_shader_output_decl(&ctx
, variable
, geom_shader
, MESA_SHADER_VERTEX
);
4538 ac_handle_shader_output_decl(&ctx
.ac
, &ctx
.abi
, geom_shader
,
4539 variable
, MESA_SHADER_VERTEX
);
4542 ac_gs_copy_shader_emit(&ctx
);
4544 LLVMBuildRetVoid(ctx
.ac
.builder
);
4546 ac_llvm_finalize_module(&ctx
, ac_llvm
->passmgr
, args
->options
);
4548 ac_compile_llvm_module(ac_llvm
, ctx
.ac
.module
, rbinary
,
4549 MESA_SHADER_VERTEX
, "GS Copy Shader", args
->options
);
4550 (*rbinary
)->is_gs_copy_shader
= true;