2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "radv_shader_helper.h"
33 #include <llvm-c/Core.h>
34 #include <llvm-c/TargetMachine.h>
35 #include <llvm-c/Transforms/Scalar.h>
36 #include <llvm-c/Transforms/Utils.h>
39 #include "ac_binary.h"
40 #include "ac_llvm_util.h"
41 #include "ac_llvm_build.h"
42 #include "ac_shader_abi.h"
43 #include "ac_shader_util.h"
44 #include "ac_exp_param.h"
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
48 struct radv_shader_context
{
49 struct ac_llvm_context ac
;
50 const struct radv_nir_compiler_options
*options
;
51 struct radv_shader_info
*shader_info
;
52 const struct nir_shader
*shader
;
53 struct ac_shader_abi abi
;
55 unsigned max_workgroup_size
;
56 LLVMContextRef context
;
57 LLVMValueRef main_function
;
59 LLVMValueRef descriptor_sets
[MAX_SETS
];
60 LLVMValueRef ring_offsets
;
62 LLVMValueRef vertex_buffers
;
63 LLVMValueRef rel_auto_id
;
64 LLVMValueRef vs_prim_id
;
65 LLVMValueRef es2gs_offset
;
68 LLVMValueRef merged_wave_info
;
69 LLVMValueRef tess_factor_offset
;
70 LLVMValueRef tes_rel_patch_id
;
76 * - bits 0..10: ordered_wave_id
77 * - bits 12..20: number of vertices in group
78 * - bits 22..30: number of primitives in group
80 LLVMValueRef gs_tg_info
;
81 LLVMValueRef gs2vs_offset
;
82 LLVMValueRef gs_wave_id
;
83 LLVMValueRef gs_vtx_offset
[6];
85 LLVMValueRef esgs_ring
;
86 LLVMValueRef gsvs_ring
[4];
87 LLVMValueRef hs_ring_tess_offchip
;
88 LLVMValueRef hs_ring_tess_factor
;
91 LLVMValueRef streamout_buffers
;
92 LLVMValueRef streamout_write_idx
;
93 LLVMValueRef streamout_config
;
94 LLVMValueRef streamout_offset
[4];
96 gl_shader_stage stage
;
98 LLVMValueRef inputs
[RADEON_LLVM_MAX_INPUTS
* 4];
100 uint64_t output_mask
;
102 bool is_gs_copy_shader
;
103 LLVMValueRef gs_next_vertex
[4];
104 LLVMValueRef gs_curprim_verts
[4];
105 LLVMValueRef gs_generated_prims
[4];
106 LLVMValueRef gs_ngg_emit
;
107 LLVMValueRef gs_ngg_scratch
;
109 uint32_t tcs_num_inputs
;
110 uint32_t tcs_num_patches
;
112 LLVMValueRef vertexptr
; /* GFX10 only */
115 struct radv_shader_output_values
{
116 LLVMValueRef values
[4];
122 enum radeon_llvm_calling_convention
{
123 RADEON_LLVM_AMDGPU_VS
= 87,
124 RADEON_LLVM_AMDGPU_GS
= 88,
125 RADEON_LLVM_AMDGPU_PS
= 89,
126 RADEON_LLVM_AMDGPU_CS
= 90,
127 RADEON_LLVM_AMDGPU_HS
= 93,
130 static inline struct radv_shader_context
*
131 radv_shader_context_from_abi(struct ac_shader_abi
*abi
)
133 struct radv_shader_context
*ctx
= NULL
;
134 return container_of(abi
, ctx
, abi
);
137 static LLVMValueRef
get_rel_patch_id(struct radv_shader_context
*ctx
)
139 switch (ctx
->stage
) {
140 case MESA_SHADER_TESS_CTRL
:
141 return ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
142 case MESA_SHADER_TESS_EVAL
:
143 return ctx
->tes_rel_patch_id
;
146 unreachable("Illegal stage");
151 get_tcs_num_patches(struct radv_shader_context
*ctx
)
153 unsigned num_tcs_input_cp
= ctx
->options
->key
.tcs
.input_vertices
;
154 unsigned num_tcs_output_cp
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
155 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
156 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
157 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->tcs
.outputs_written
);
158 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->tcs
.patch_outputs_written
);
159 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
160 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
161 uint32_t output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
162 unsigned num_patches
;
163 unsigned hardware_lds_size
;
165 /* Ensure that we only need one wave per SIMD so we don't need to check
166 * resource usage. Also ensures that the number of tcs in and out
167 * vertices per threadgroup are at most 256.
169 num_patches
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
) * 4;
170 /* Make sure that the data fits in LDS. This assumes the shaders only
171 * use LDS for the inputs and outputs.
173 hardware_lds_size
= 32768;
175 /* Looks like STONEY hangs if we use more than 32 KiB LDS in a single
176 * threadgroup, even though there is more than 32 KiB LDS.
178 * Test: dEQP-VK.tessellation.shader_input_output.barrier
180 if (ctx
->options
->chip_class
>= GFX7
&& ctx
->options
->family
!= CHIP_STONEY
)
181 hardware_lds_size
= 65536;
183 num_patches
= MIN2(num_patches
, hardware_lds_size
/ (input_patch_size
+ output_patch_size
));
184 /* Make sure the output data fits in the offchip buffer */
185 num_patches
= MIN2(num_patches
, (ctx
->options
->tess_offchip_block_dw_size
* 4) / output_patch_size
);
186 /* Not necessary for correctness, but improves performance. The
187 * specific value is taken from the proprietary driver.
189 num_patches
= MIN2(num_patches
, 40);
191 /* GFX6 bug workaround - limit LS-HS threadgroups to only one wave. */
192 if (ctx
->options
->chip_class
== GFX6
) {
193 unsigned one_wave
= 64 / MAX2(num_tcs_input_cp
, num_tcs_output_cp
);
194 num_patches
= MIN2(num_patches
, one_wave
);
200 calculate_tess_lds_size(struct radv_shader_context
*ctx
)
202 unsigned num_tcs_input_cp
= ctx
->options
->key
.tcs
.input_vertices
;
203 unsigned num_tcs_output_cp
;
204 unsigned num_tcs_outputs
, num_tcs_patch_outputs
;
205 unsigned input_vertex_size
, output_vertex_size
;
206 unsigned input_patch_size
, output_patch_size
;
207 unsigned pervertex_output_patch_size
;
208 unsigned output_patch0_offset
;
209 unsigned num_patches
;
212 num_tcs_output_cp
= ctx
->shader
->info
.tess
.tcs_vertices_out
;
213 num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->tcs
.outputs_written
);
214 num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->tcs
.patch_outputs_written
);
216 input_vertex_size
= ctx
->tcs_num_inputs
* 16;
217 output_vertex_size
= num_tcs_outputs
* 16;
219 input_patch_size
= num_tcs_input_cp
* input_vertex_size
;
221 pervertex_output_patch_size
= num_tcs_output_cp
* output_vertex_size
;
222 output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
224 num_patches
= ctx
->tcs_num_patches
;
225 output_patch0_offset
= input_patch_size
* num_patches
;
227 lds_size
= output_patch0_offset
+ output_patch_size
* num_patches
;
231 /* Tessellation shaders pass outputs to the next shader using LDS.
233 * LS outputs = TCS inputs
234 * TCS outputs = TES inputs
237 * - TCS inputs for patch 0
238 * - TCS inputs for patch 1
239 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
241 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
242 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
243 * - TCS outputs for patch 1
244 * - Per-patch TCS outputs for patch 1
245 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
246 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
249 * All three shaders VS(LS), TCS, TES share the same LDS space.
252 get_tcs_in_patch_stride(struct radv_shader_context
*ctx
)
254 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
255 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
256 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
258 input_patch_size
/= 4;
259 return LLVMConstInt(ctx
->ac
.i32
, input_patch_size
, false);
263 get_tcs_out_patch_stride(struct radv_shader_context
*ctx
)
265 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->tcs
.outputs_written
);
266 uint32_t num_tcs_patch_outputs
= util_last_bit64(ctx
->shader_info
->tcs
.patch_outputs_written
);
267 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
268 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
269 uint32_t output_patch_size
= pervertex_output_patch_size
+ num_tcs_patch_outputs
* 16;
270 output_patch_size
/= 4;
271 return LLVMConstInt(ctx
->ac
.i32
, output_patch_size
, false);
275 get_tcs_out_vertex_stride(struct radv_shader_context
*ctx
)
277 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->tcs
.outputs_written
);
278 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
279 output_vertex_size
/= 4;
280 return LLVMConstInt(ctx
->ac
.i32
, output_vertex_size
, false);
284 get_tcs_out_patch0_offset(struct radv_shader_context
*ctx
)
286 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
287 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
288 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
289 uint32_t output_patch0_offset
= input_patch_size
;
290 unsigned num_patches
= ctx
->tcs_num_patches
;
292 output_patch0_offset
*= num_patches
;
293 output_patch0_offset
/= 4;
294 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
298 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context
*ctx
)
300 assert (ctx
->stage
== MESA_SHADER_TESS_CTRL
);
301 uint32_t input_vertex_size
= ctx
->tcs_num_inputs
* 16;
302 uint32_t input_patch_size
= ctx
->options
->key
.tcs
.input_vertices
* input_vertex_size
;
303 uint32_t output_patch0_offset
= input_patch_size
;
305 uint32_t num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->tcs
.outputs_written
);
306 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
307 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
308 unsigned num_patches
= ctx
->tcs_num_patches
;
310 output_patch0_offset
*= num_patches
;
311 output_patch0_offset
+= pervertex_output_patch_size
;
312 output_patch0_offset
/= 4;
313 return LLVMConstInt(ctx
->ac
.i32
, output_patch0_offset
, false);
317 get_tcs_in_current_patch_offset(struct radv_shader_context
*ctx
)
319 LLVMValueRef patch_stride
= get_tcs_in_patch_stride(ctx
);
320 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
322 return LLVMBuildMul(ctx
->ac
.builder
, patch_stride
, rel_patch_id
, "");
326 get_tcs_out_current_patch_offset(struct radv_shader_context
*ctx
)
328 LLVMValueRef patch0_offset
= get_tcs_out_patch0_offset(ctx
);
329 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
330 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
332 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
,
337 get_tcs_out_current_patch_data_offset(struct radv_shader_context
*ctx
)
339 LLVMValueRef patch0_patch_data_offset
=
340 get_tcs_out_patch0_patch_data_offset(ctx
);
341 LLVMValueRef patch_stride
= get_tcs_out_patch_stride(ctx
);
342 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
344 return ac_build_imad(&ctx
->ac
, patch_stride
, rel_patch_id
,
345 patch0_patch_data_offset
);
350 LLVMTypeRef types
[MAX_ARGS
];
351 LLVMValueRef
*assign
[MAX_ARGS
];
354 uint8_t num_sgprs_used
;
355 uint8_t num_vgprs_used
;
358 enum ac_arg_regfile
{
364 add_arg(struct arg_info
*info
, enum ac_arg_regfile regfile
, LLVMTypeRef type
,
365 LLVMValueRef
*param_ptr
)
367 assert(info
->count
< MAX_ARGS
);
369 info
->assign
[info
->count
] = param_ptr
;
370 info
->types
[info
->count
] = type
;
373 if (regfile
== ARG_SGPR
) {
374 info
->num_sgprs_used
+= ac_get_type_size(type
) / 4;
377 assert(regfile
== ARG_VGPR
);
378 info
->num_vgprs_used
+= ac_get_type_size(type
) / 4;
382 static void assign_arguments(LLVMValueRef main_function
,
383 struct arg_info
*info
)
386 for (i
= 0; i
< info
->count
; i
++) {
388 *info
->assign
[i
] = LLVMGetParam(main_function
, i
);
393 create_llvm_function(LLVMContextRef ctx
, LLVMModuleRef module
,
394 LLVMBuilderRef builder
, LLVMTypeRef
*return_types
,
395 unsigned num_return_elems
,
396 struct arg_info
*args
,
397 unsigned max_workgroup_size
,
398 const struct radv_nir_compiler_options
*options
)
400 LLVMTypeRef main_function_type
, ret_type
;
401 LLVMBasicBlockRef main_function_body
;
403 if (num_return_elems
)
404 ret_type
= LLVMStructTypeInContext(ctx
, return_types
,
405 num_return_elems
, true);
407 ret_type
= LLVMVoidTypeInContext(ctx
);
409 /* Setup the function */
411 LLVMFunctionType(ret_type
, args
->types
, args
->count
, 0);
412 LLVMValueRef main_function
=
413 LLVMAddFunction(module
, "main", main_function_type
);
415 LLVMAppendBasicBlockInContext(ctx
, main_function
, "main_body");
416 LLVMPositionBuilderAtEnd(builder
, main_function_body
);
418 LLVMSetFunctionCallConv(main_function
, RADEON_LLVM_AMDGPU_CS
);
419 for (unsigned i
= 0; i
< args
->sgpr_count
; ++i
) {
420 LLVMValueRef P
= LLVMGetParam(main_function
, i
);
422 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_INREG
);
424 if (LLVMGetTypeKind(LLVMTypeOf(P
)) == LLVMPointerTypeKind
) {
425 ac_add_function_attr(ctx
, main_function
, i
+ 1, AC_FUNC_ATTR_NOALIAS
);
426 ac_add_attr_dereferenceable(P
, UINT64_MAX
);
430 if (options
->address32_hi
) {
431 ac_llvm_add_target_dep_function_attr(main_function
,
432 "amdgpu-32bit-address-high-bits",
433 options
->address32_hi
);
436 ac_llvm_set_workgroup_size(main_function
, max_workgroup_size
);
438 if (options
->unsafe_math
) {
439 /* These were copied from some LLVM test. */
440 LLVMAddTargetDependentFunctionAttr(main_function
,
441 "less-precise-fpmad",
443 LLVMAddTargetDependentFunctionAttr(main_function
,
446 LLVMAddTargetDependentFunctionAttr(main_function
,
449 LLVMAddTargetDependentFunctionAttr(main_function
,
452 LLVMAddTargetDependentFunctionAttr(main_function
,
453 "no-signed-zeros-fp-math",
456 return main_function
;
461 set_loc(struct radv_userdata_info
*ud_info
, uint8_t *sgpr_idx
,
464 ud_info
->sgpr_idx
= *sgpr_idx
;
465 ud_info
->num_sgprs
= num_sgprs
;
466 *sgpr_idx
+= num_sgprs
;
470 set_loc_shader(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
,
473 struct radv_userdata_info
*ud_info
=
474 &ctx
->shader_info
->user_sgprs_locs
.shader_data
[idx
];
477 set_loc(ud_info
, sgpr_idx
, num_sgprs
);
481 set_loc_shader_ptr(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
)
483 bool use_32bit_pointers
= idx
!= AC_UD_SCRATCH_RING_OFFSETS
;
485 set_loc_shader(ctx
, idx
, sgpr_idx
, use_32bit_pointers
? 1 : 2);
489 set_loc_desc(struct radv_shader_context
*ctx
, int idx
, uint8_t *sgpr_idx
)
491 struct radv_userdata_locations
*locs
=
492 &ctx
->shader_info
->user_sgprs_locs
;
493 struct radv_userdata_info
*ud_info
= &locs
->descriptor_sets
[idx
];
496 set_loc(ud_info
, sgpr_idx
, 1);
498 locs
->descriptor_sets_enabled
|= 1 << idx
;
501 struct user_sgpr_info
{
502 bool need_ring_offsets
;
503 bool indirect_all_descriptor_sets
;
504 uint8_t remaining_sgprs
;
507 static bool needs_view_index_sgpr(struct radv_shader_context
*ctx
,
508 gl_shader_stage stage
)
511 case MESA_SHADER_VERTEX
:
512 if (ctx
->shader_info
->needs_multiview_view_index
||
513 (!ctx
->options
->key
.vs_common_out
.as_es
&& !ctx
->options
->key
.vs_common_out
.as_ls
&& ctx
->options
->key
.has_multiview_view_index
))
516 case MESA_SHADER_TESS_EVAL
:
517 if (ctx
->shader_info
->needs_multiview_view_index
|| (!ctx
->options
->key
.vs_common_out
.as_es
&& ctx
->options
->key
.has_multiview_view_index
))
520 case MESA_SHADER_GEOMETRY
:
521 case MESA_SHADER_TESS_CTRL
:
522 if (ctx
->shader_info
->needs_multiview_view_index
)
532 count_vs_user_sgprs(struct radv_shader_context
*ctx
)
536 if (ctx
->shader_info
->vs
.has_vertex_buffers
)
538 count
+= ctx
->shader_info
->vs
.needs_draw_id
? 3 : 2;
543 static void allocate_inline_push_consts(struct radv_shader_context
*ctx
,
544 struct user_sgpr_info
*user_sgpr_info
)
546 uint8_t remaining_sgprs
= user_sgpr_info
->remaining_sgprs
;
548 /* Only supported if shaders use push constants. */
549 if (ctx
->shader_info
->min_push_constant_used
== UINT8_MAX
)
552 /* Only supported if shaders don't have indirect push constants. */
553 if (ctx
->shader_info
->has_indirect_push_constants
)
556 /* Only supported for 32-bit push constants. */
557 if (!ctx
->shader_info
->has_only_32bit_push_constants
)
560 uint8_t num_push_consts
=
561 (ctx
->shader_info
->max_push_constant_used
-
562 ctx
->shader_info
->min_push_constant_used
) / 4;
564 /* Check if the number of user SGPRs is large enough. */
565 if (num_push_consts
< remaining_sgprs
) {
566 ctx
->shader_info
->num_inline_push_consts
= num_push_consts
;
568 ctx
->shader_info
->num_inline_push_consts
= remaining_sgprs
;
571 /* Clamp to the maximum number of allowed inlined push constants. */
572 if (ctx
->shader_info
->num_inline_push_consts
> AC_MAX_INLINE_PUSH_CONSTS
)
573 ctx
->shader_info
->num_inline_push_consts
= AC_MAX_INLINE_PUSH_CONSTS
;
575 if (ctx
->shader_info
->num_inline_push_consts
== num_push_consts
&&
576 !ctx
->shader_info
->loads_dynamic_offsets
) {
577 /* Disable the default push constants path if all constants are
578 * inlined and if shaders don't use dynamic descriptors.
580 ctx
->shader_info
->loads_push_constants
= false;
583 ctx
->shader_info
->base_inline_push_consts
=
584 ctx
->shader_info
->min_push_constant_used
/ 4;
587 static void allocate_user_sgprs(struct radv_shader_context
*ctx
,
588 gl_shader_stage stage
,
589 bool has_previous_stage
,
590 gl_shader_stage previous_stage
,
591 bool needs_view_index
,
592 struct user_sgpr_info
*user_sgpr_info
)
594 uint8_t user_sgpr_count
= 0;
596 memset(user_sgpr_info
, 0, sizeof(struct user_sgpr_info
));
598 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
599 if (stage
== MESA_SHADER_GEOMETRY
||
600 stage
== MESA_SHADER_VERTEX
||
601 stage
== MESA_SHADER_TESS_CTRL
||
602 stage
== MESA_SHADER_TESS_EVAL
||
603 ctx
->is_gs_copy_shader
)
604 user_sgpr_info
->need_ring_offsets
= true;
606 if (stage
== MESA_SHADER_FRAGMENT
&&
607 ctx
->shader_info
->ps
.needs_sample_positions
)
608 user_sgpr_info
->need_ring_offsets
= true;
610 /* 2 user sgprs will nearly always be allocated for scratch/rings */
611 if (ctx
->options
->supports_spill
|| user_sgpr_info
->need_ring_offsets
) {
612 user_sgpr_count
+= 2;
616 case MESA_SHADER_COMPUTE
:
617 if (ctx
->shader_info
->cs
.uses_grid_size
)
618 user_sgpr_count
+= 3;
620 case MESA_SHADER_FRAGMENT
:
621 user_sgpr_count
+= ctx
->shader_info
->ps
.needs_sample_positions
;
623 case MESA_SHADER_VERTEX
:
624 if (!ctx
->is_gs_copy_shader
)
625 user_sgpr_count
+= count_vs_user_sgprs(ctx
);
627 case MESA_SHADER_TESS_CTRL
:
628 if (has_previous_stage
) {
629 if (previous_stage
== MESA_SHADER_VERTEX
)
630 user_sgpr_count
+= count_vs_user_sgprs(ctx
);
633 case MESA_SHADER_TESS_EVAL
:
635 case MESA_SHADER_GEOMETRY
:
636 if (has_previous_stage
) {
637 if (previous_stage
== MESA_SHADER_VERTEX
) {
638 user_sgpr_count
+= count_vs_user_sgprs(ctx
);
646 if (needs_view_index
)
649 if (ctx
->shader_info
->loads_push_constants
)
652 if (ctx
->shader_info
->so
.num_outputs
)
655 uint32_t available_sgprs
= ctx
->options
->chip_class
>= GFX9
&& stage
!= MESA_SHADER_COMPUTE
? 32 : 16;
656 uint32_t remaining_sgprs
= available_sgprs
- user_sgpr_count
;
657 uint32_t num_desc_set
=
658 util_bitcount(ctx
->shader_info
->desc_set_used_mask
);
660 if (remaining_sgprs
< num_desc_set
) {
661 user_sgpr_info
->indirect_all_descriptor_sets
= true;
662 user_sgpr_info
->remaining_sgprs
= remaining_sgprs
- 1;
664 user_sgpr_info
->remaining_sgprs
= remaining_sgprs
- num_desc_set
;
667 allocate_inline_push_consts(ctx
, user_sgpr_info
);
671 declare_global_input_sgprs(struct radv_shader_context
*ctx
,
672 const struct user_sgpr_info
*user_sgpr_info
,
673 struct arg_info
*args
,
674 LLVMValueRef
*desc_sets
)
676 LLVMTypeRef type
= ac_array_in_const32_addr_space(ctx
->ac
.i8
);
678 /* 1 for each descriptor set */
679 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
680 uint32_t mask
= ctx
->shader_info
->desc_set_used_mask
;
683 int i
= u_bit_scan(&mask
);
685 add_arg(args
, ARG_SGPR
, type
, &ctx
->descriptor_sets
[i
]);
688 add_arg(args
, ARG_SGPR
, ac_array_in_const32_addr_space(type
),
692 if (ctx
->shader_info
->loads_push_constants
) {
693 /* 1 for push constants and dynamic descriptors */
694 add_arg(args
, ARG_SGPR
, type
, &ctx
->abi
.push_constants
);
697 for (unsigned i
= 0; i
< ctx
->shader_info
->num_inline_push_consts
; i
++) {
698 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
,
699 &ctx
->abi
.inline_push_consts
[i
]);
701 ctx
->abi
.num_inline_push_consts
= ctx
->shader_info
->num_inline_push_consts
;
702 ctx
->abi
.base_inline_push_consts
= ctx
->shader_info
->base_inline_push_consts
;
704 if (ctx
->shader_info
->so
.num_outputs
) {
705 add_arg(args
, ARG_SGPR
,
706 ac_array_in_const32_addr_space(ctx
->ac
.v4i32
),
707 &ctx
->streamout_buffers
);
712 declare_vs_specific_input_sgprs(struct radv_shader_context
*ctx
,
713 gl_shader_stage stage
,
714 bool has_previous_stage
,
715 gl_shader_stage previous_stage
,
716 struct arg_info
*args
)
718 if (!ctx
->is_gs_copy_shader
&&
719 (stage
== MESA_SHADER_VERTEX
||
720 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
721 if (ctx
->shader_info
->vs
.has_vertex_buffers
) {
722 add_arg(args
, ARG_SGPR
,
723 ac_array_in_const32_addr_space(ctx
->ac
.v4i32
),
724 &ctx
->vertex_buffers
);
726 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.base_vertex
);
727 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.start_instance
);
728 if (ctx
->shader_info
->vs
.needs_draw_id
) {
729 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.draw_id
);
735 declare_vs_input_vgprs(struct radv_shader_context
*ctx
, struct arg_info
*args
)
737 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.vertex_id
);
738 if (!ctx
->is_gs_copy_shader
) {
739 if (ctx
->options
->key
.vs_common_out
.as_ls
) {
740 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->rel_auto_id
);
741 if (ctx
->ac
.chip_class
>= GFX10
) {
742 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* user vgpr */
743 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
745 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
746 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* unused */
749 if (ctx
->ac
.chip_class
>= GFX10
) {
750 if (ctx
->options
->key
.vs_common_out
.as_ngg
) {
751 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* user vgpr */
752 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* user vgpr */
753 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
755 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* unused */
756 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->vs_prim_id
);
757 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
760 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.instance_id
);
761 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->vs_prim_id
);
762 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* unused */
769 declare_streamout_sgprs(struct radv_shader_context
*ctx
, gl_shader_stage stage
,
770 struct arg_info
*args
)
774 if (ctx
->options
->use_ngg_streamout
)
777 /* Streamout SGPRs. */
778 if (ctx
->shader_info
->so
.num_outputs
) {
779 assert(stage
== MESA_SHADER_VERTEX
||
780 stage
== MESA_SHADER_TESS_EVAL
);
782 if (stage
!= MESA_SHADER_TESS_EVAL
) {
783 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->streamout_config
);
785 args
->assign
[args
->count
- 1] = &ctx
->streamout_config
;
786 args
->types
[args
->count
- 1] = ctx
->ac
.i32
;
789 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->streamout_write_idx
);
792 /* A streamout buffer offset is loaded if the stride is non-zero. */
793 for (i
= 0; i
< 4; i
++) {
794 if (!ctx
->shader_info
->so
.strides
[i
])
797 add_arg(args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->streamout_offset
[i
]);
802 declare_tes_input_vgprs(struct radv_shader_context
*ctx
, struct arg_info
*args
)
804 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_u
);
805 add_arg(args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->tes_v
);
806 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->tes_rel_patch_id
);
807 add_arg(args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.tes_patch_id
);
811 set_global_input_locs(struct radv_shader_context
*ctx
,
812 const struct user_sgpr_info
*user_sgpr_info
,
813 LLVMValueRef desc_sets
, uint8_t *user_sgpr_idx
)
815 uint32_t mask
= ctx
->shader_info
->desc_set_used_mask
;
817 if (!user_sgpr_info
->indirect_all_descriptor_sets
) {
819 int i
= u_bit_scan(&mask
);
821 set_loc_desc(ctx
, i
, user_sgpr_idx
);
824 set_loc_shader_ptr(ctx
, AC_UD_INDIRECT_DESCRIPTOR_SETS
,
828 int i
= u_bit_scan(&mask
);
830 ctx
->descriptor_sets
[i
] =
831 ac_build_load_to_sgpr(&ctx
->ac
, desc_sets
,
832 LLVMConstInt(ctx
->ac
.i32
, i
, false));
836 ctx
->shader_info
->need_indirect_descriptor_sets
= true;
839 if (ctx
->shader_info
->loads_push_constants
) {
840 set_loc_shader_ptr(ctx
, AC_UD_PUSH_CONSTANTS
, user_sgpr_idx
);
843 if (ctx
->shader_info
->num_inline_push_consts
) {
844 set_loc_shader(ctx
, AC_UD_INLINE_PUSH_CONSTANTS
, user_sgpr_idx
,
845 ctx
->shader_info
->num_inline_push_consts
);
848 if (ctx
->streamout_buffers
) {
849 set_loc_shader_ptr(ctx
, AC_UD_STREAMOUT_BUFFERS
,
855 set_vs_specific_input_locs(struct radv_shader_context
*ctx
,
856 gl_shader_stage stage
, bool has_previous_stage
,
857 gl_shader_stage previous_stage
,
858 uint8_t *user_sgpr_idx
)
860 if (!ctx
->is_gs_copy_shader
&&
861 (stage
== MESA_SHADER_VERTEX
||
862 (has_previous_stage
&& previous_stage
== MESA_SHADER_VERTEX
))) {
863 if (ctx
->shader_info
->vs
.has_vertex_buffers
) {
864 set_loc_shader_ptr(ctx
, AC_UD_VS_VERTEX_BUFFERS
,
869 if (ctx
->shader_info
->vs
.needs_draw_id
)
872 set_loc_shader(ctx
, AC_UD_VS_BASE_VERTEX_START_INSTANCE
,
873 user_sgpr_idx
, vs_num
);
877 static void set_llvm_calling_convention(LLVMValueRef func
,
878 gl_shader_stage stage
)
880 enum radeon_llvm_calling_convention calling_conv
;
883 case MESA_SHADER_VERTEX
:
884 case MESA_SHADER_TESS_EVAL
:
885 calling_conv
= RADEON_LLVM_AMDGPU_VS
;
887 case MESA_SHADER_GEOMETRY
:
888 calling_conv
= RADEON_LLVM_AMDGPU_GS
;
890 case MESA_SHADER_TESS_CTRL
:
891 calling_conv
= RADEON_LLVM_AMDGPU_HS
;
893 case MESA_SHADER_FRAGMENT
:
894 calling_conv
= RADEON_LLVM_AMDGPU_PS
;
896 case MESA_SHADER_COMPUTE
:
897 calling_conv
= RADEON_LLVM_AMDGPU_CS
;
900 unreachable("Unhandle shader type");
903 LLVMSetFunctionCallConv(func
, calling_conv
);
906 /* Returns whether the stage is a stage that can be directly before the GS */
907 static bool is_pre_gs_stage(gl_shader_stage stage
)
909 return stage
== MESA_SHADER_VERTEX
|| stage
== MESA_SHADER_TESS_EVAL
;
912 static void create_function(struct radv_shader_context
*ctx
,
913 gl_shader_stage stage
,
914 bool has_previous_stage
,
915 gl_shader_stage previous_stage
)
917 uint8_t user_sgpr_idx
;
918 struct user_sgpr_info user_sgpr_info
;
919 struct arg_info args
= {};
920 LLVMValueRef desc_sets
;
921 bool needs_view_index
= needs_view_index_sgpr(ctx
, stage
);
923 if (ctx
->ac
.chip_class
>= GFX10
) {
924 if (is_pre_gs_stage(stage
) && ctx
->options
->key
.vs_common_out
.as_ngg
) {
925 /* On GFX10, VS is merged into GS for NGG. */
926 previous_stage
= stage
;
927 stage
= MESA_SHADER_GEOMETRY
;
928 has_previous_stage
= true;
932 allocate_user_sgprs(ctx
, stage
, has_previous_stage
,
933 previous_stage
, needs_view_index
, &user_sgpr_info
);
935 if (user_sgpr_info
.need_ring_offsets
&& !ctx
->options
->supports_spill
) {
936 add_arg(&args
, ARG_SGPR
, ac_array_in_const_addr_space(ctx
->ac
.v4i32
),
941 case MESA_SHADER_COMPUTE
:
942 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
945 if (ctx
->shader_info
->cs
.uses_grid_size
) {
946 add_arg(&args
, ARG_SGPR
, ctx
->ac
.v3i32
,
947 &ctx
->abi
.num_work_groups
);
950 for (int i
= 0; i
< 3; i
++) {
951 ctx
->abi
.workgroup_ids
[i
] = NULL
;
952 if (ctx
->shader_info
->cs
.uses_block_id
[i
]) {
953 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
954 &ctx
->abi
.workgroup_ids
[i
]);
958 if (ctx
->shader_info
->cs
.uses_local_invocation_idx
)
959 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.tg_size
);
960 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
,
961 &ctx
->abi
.local_invocation_ids
);
963 case MESA_SHADER_VERTEX
:
964 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
967 declare_vs_specific_input_sgprs(ctx
, stage
, has_previous_stage
,
968 previous_stage
, &args
);
970 if (needs_view_index
)
971 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
972 &ctx
->abi
.view_index
);
973 if (ctx
->options
->key
.vs_common_out
.as_es
) {
974 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
976 } else if (ctx
->options
->key
.vs_common_out
.as_ls
) {
977 /* no extra parameters */
979 declare_streamout_sgprs(ctx
, stage
, &args
);
982 declare_vs_input_vgprs(ctx
, &args
);
984 case MESA_SHADER_TESS_CTRL
:
985 if (has_previous_stage
) {
986 // First 6 system regs
987 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
988 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
989 &ctx
->merged_wave_info
);
990 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
991 &ctx
->tess_factor_offset
);
993 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
994 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
995 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
997 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1000 declare_vs_specific_input_sgprs(ctx
, stage
,
1002 previous_stage
, &args
);
1004 if (needs_view_index
)
1005 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1006 &ctx
->abi
.view_index
);
1008 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1009 &ctx
->abi
.tcs_patch_id
);
1010 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1011 &ctx
->abi
.tcs_rel_ids
);
1013 declare_vs_input_vgprs(ctx
, &args
);
1015 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1018 if (needs_view_index
)
1019 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1020 &ctx
->abi
.view_index
);
1022 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1023 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1024 &ctx
->tess_factor_offset
);
1025 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1026 &ctx
->abi
.tcs_patch_id
);
1027 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1028 &ctx
->abi
.tcs_rel_ids
);
1031 case MESA_SHADER_TESS_EVAL
:
1032 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1035 if (needs_view_index
)
1036 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1037 &ctx
->abi
.view_index
);
1039 if (ctx
->options
->key
.vs_common_out
.as_es
) {
1040 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1041 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
1042 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1043 &ctx
->es2gs_offset
);
1045 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
);
1046 declare_streamout_sgprs(ctx
, stage
, &args
);
1047 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1049 declare_tes_input_vgprs(ctx
, &args
);
1051 case MESA_SHADER_GEOMETRY
:
1052 if (has_previous_stage
) {
1053 // First 6 system regs
1054 if (ctx
->options
->key
.vs_common_out
.as_ngg
) {
1055 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1058 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1059 &ctx
->gs2vs_offset
);
1062 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1063 &ctx
->merged_wave_info
);
1064 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->oc_lds
);
1066 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // scratch offset
1067 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1068 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, NULL
); // unknown
1070 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1073 if (previous_stage
!= MESA_SHADER_TESS_EVAL
) {
1074 declare_vs_specific_input_sgprs(ctx
, stage
,
1080 if (needs_view_index
)
1081 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1082 &ctx
->abi
.view_index
);
1084 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1085 &ctx
->gs_vtx_offset
[0]);
1086 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1087 &ctx
->gs_vtx_offset
[2]);
1088 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1089 &ctx
->abi
.gs_prim_id
);
1090 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1091 &ctx
->abi
.gs_invocation_id
);
1092 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1093 &ctx
->gs_vtx_offset
[4]);
1095 if (previous_stage
== MESA_SHADER_VERTEX
) {
1096 declare_vs_input_vgprs(ctx
, &args
);
1098 declare_tes_input_vgprs(ctx
, &args
);
1101 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1104 if (needs_view_index
)
1105 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
,
1106 &ctx
->abi
.view_index
);
1108 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs2vs_offset
);
1109 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->gs_wave_id
);
1110 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1111 &ctx
->gs_vtx_offset
[0]);
1112 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1113 &ctx
->gs_vtx_offset
[1]);
1114 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1115 &ctx
->abi
.gs_prim_id
);
1116 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1117 &ctx
->gs_vtx_offset
[2]);
1118 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1119 &ctx
->gs_vtx_offset
[3]);
1120 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1121 &ctx
->gs_vtx_offset
[4]);
1122 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1123 &ctx
->gs_vtx_offset
[5]);
1124 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
,
1125 &ctx
->abi
.gs_invocation_id
);
1128 case MESA_SHADER_FRAGMENT
:
1129 declare_global_input_sgprs(ctx
, &user_sgpr_info
, &args
,
1132 add_arg(&args
, ARG_SGPR
, ctx
->ac
.i32
, &ctx
->abi
.prim_mask
);
1133 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->abi
.persp_sample
);
1134 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->abi
.persp_center
);
1135 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->abi
.persp_centroid
);
1136 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v3i32
, NULL
); /* persp pull model */
1137 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->abi
.linear_sample
);
1138 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->abi
.linear_center
);
1139 add_arg(&args
, ARG_VGPR
, ctx
->ac
.v2i32
, &ctx
->abi
.linear_centroid
);
1140 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, NULL
); /* line stipple tex */
1141 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[0]);
1142 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[1]);
1143 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[2]);
1144 add_arg(&args
, ARG_VGPR
, ctx
->ac
.f32
, &ctx
->abi
.frag_pos
[3]);
1145 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.front_face
);
1146 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.ancillary
);
1147 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, &ctx
->abi
.sample_coverage
);
1148 add_arg(&args
, ARG_VGPR
, ctx
->ac
.i32
, NULL
); /* fixed pt */
1151 unreachable("Shader stage not implemented");
1154 ctx
->main_function
= create_llvm_function(
1155 ctx
->context
, ctx
->ac
.module
, ctx
->ac
.builder
, NULL
, 0, &args
,
1156 ctx
->max_workgroup_size
, ctx
->options
);
1157 set_llvm_calling_convention(ctx
->main_function
, stage
);
1160 ctx
->shader_info
->num_input_vgprs
= 0;
1161 ctx
->shader_info
->num_input_sgprs
= ctx
->options
->supports_spill
? 2 : 0;
1163 ctx
->shader_info
->num_input_sgprs
+= args
.num_sgprs_used
;
1165 if (ctx
->stage
!= MESA_SHADER_FRAGMENT
)
1166 ctx
->shader_info
->num_input_vgprs
= args
.num_vgprs_used
;
1168 assign_arguments(ctx
->main_function
, &args
);
1172 if (ctx
->options
->supports_spill
|| user_sgpr_info
.need_ring_offsets
) {
1173 set_loc_shader_ptr(ctx
, AC_UD_SCRATCH_RING_OFFSETS
,
1175 if (ctx
->options
->supports_spill
) {
1176 ctx
->ring_offsets
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.implicit.buffer.ptr",
1177 LLVMPointerType(ctx
->ac
.i8
, AC_ADDR_SPACE_CONST
),
1178 NULL
, 0, AC_FUNC_ATTR_READNONE
);
1179 ctx
->ring_offsets
= LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->ring_offsets
,
1180 ac_array_in_const_addr_space(ctx
->ac
.v4i32
), "");
1184 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1185 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1186 if (has_previous_stage
)
1189 set_global_input_locs(ctx
, &user_sgpr_info
, desc_sets
, &user_sgpr_idx
);
1192 case MESA_SHADER_COMPUTE
:
1193 if (ctx
->shader_info
->cs
.uses_grid_size
) {
1194 set_loc_shader(ctx
, AC_UD_CS_GRID_SIZE
,
1198 case MESA_SHADER_VERTEX
:
1199 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1200 previous_stage
, &user_sgpr_idx
);
1201 if (ctx
->abi
.view_index
)
1202 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1204 case MESA_SHADER_TESS_CTRL
:
1205 set_vs_specific_input_locs(ctx
, stage
, has_previous_stage
,
1206 previous_stage
, &user_sgpr_idx
);
1207 if (ctx
->abi
.view_index
)
1208 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1210 case MESA_SHADER_TESS_EVAL
:
1211 if (ctx
->abi
.view_index
)
1212 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1214 case MESA_SHADER_GEOMETRY
:
1215 if (has_previous_stage
) {
1216 if (previous_stage
== MESA_SHADER_VERTEX
)
1217 set_vs_specific_input_locs(ctx
, stage
,
1222 if (ctx
->abi
.view_index
)
1223 set_loc_shader(ctx
, AC_UD_VIEW_INDEX
, &user_sgpr_idx
, 1);
1225 case MESA_SHADER_FRAGMENT
:
1228 unreachable("Shader stage not implemented");
1231 if (stage
== MESA_SHADER_TESS_CTRL
||
1232 (stage
== MESA_SHADER_VERTEX
&& ctx
->options
->key
.vs_common_out
.as_ls
) ||
1233 /* GFX9 has the ESGS ring buffer in LDS. */
1234 (stage
== MESA_SHADER_GEOMETRY
&& has_previous_stage
)) {
1235 ac_declare_lds_as_pointer(&ctx
->ac
);
1238 ctx
->shader_info
->num_user_sgprs
= user_sgpr_idx
;
1243 radv_load_resource(struct ac_shader_abi
*abi
, LLVMValueRef index
,
1244 unsigned desc_set
, unsigned binding
)
1246 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1247 LLVMValueRef desc_ptr
= ctx
->descriptor_sets
[desc_set
];
1248 struct radv_pipeline_layout
*pipeline_layout
= ctx
->options
->layout
;
1249 struct radv_descriptor_set_layout
*layout
= pipeline_layout
->set
[desc_set
].layout
;
1250 unsigned base_offset
= layout
->binding
[binding
].offset
;
1251 LLVMValueRef offset
, stride
;
1253 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC
||
1254 layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC
) {
1255 unsigned idx
= pipeline_layout
->set
[desc_set
].dynamic_offset_start
+
1256 layout
->binding
[binding
].dynamic_offset_offset
;
1257 desc_ptr
= ctx
->abi
.push_constants
;
1258 base_offset
= pipeline_layout
->push_constant_size
+ 16 * idx
;
1259 stride
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
1261 stride
= LLVMConstInt(ctx
->ac
.i32
, layout
->binding
[binding
].size
, false);
1263 offset
= LLVMConstInt(ctx
->ac
.i32
, base_offset
, false);
1265 if (layout
->binding
[binding
].type
!= VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
1266 offset
= ac_build_imad(&ctx
->ac
, index
, stride
, offset
);
1269 desc_ptr
= LLVMBuildGEP(ctx
->ac
.builder
, desc_ptr
, &offset
, 1, "");
1270 desc_ptr
= ac_cast_ptr(&ctx
->ac
, desc_ptr
, ctx
->ac
.v4i32
);
1271 LLVMSetMetadata(desc_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1273 if (layout
->binding
[binding
].type
== VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT
) {
1274 uint32_t desc_type
= S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X
) |
1275 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y
) |
1276 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z
) |
1277 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W
);
1279 if (ctx
->ac
.chip_class
>= GFX10
) {
1280 desc_type
|= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT
) |
1281 S_008F0C_OOB_SELECT(3) |
1282 S_008F0C_RESOURCE_LEVEL(1);
1284 desc_type
|= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT
) |
1285 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32
);
1288 LLVMValueRef desc_components
[4] = {
1289 LLVMBuildPtrToInt(ctx
->ac
.builder
, desc_ptr
, ctx
->ac
.intptr
, ""),
1290 LLVMConstInt(ctx
->ac
.i32
, S_008F04_BASE_ADDRESS_HI(ctx
->options
->address32_hi
), false),
1291 /* High limit to support variable sizes. */
1292 LLVMConstInt(ctx
->ac
.i32
, 0xffffffff, false),
1293 LLVMConstInt(ctx
->ac
.i32
, desc_type
, false),
1296 return ac_build_gather_values(&ctx
->ac
, desc_components
, 4);
1303 /* The offchip buffer layout for TCS->TES is
1305 * - attribute 0 of patch 0 vertex 0
1306 * - attribute 0 of patch 0 vertex 1
1307 * - attribute 0 of patch 0 vertex 2
1309 * - attribute 0 of patch 1 vertex 0
1310 * - attribute 0 of patch 1 vertex 1
1312 * - attribute 1 of patch 0 vertex 0
1313 * - attribute 1 of patch 0 vertex 1
1315 * - per patch attribute 0 of patch 0
1316 * - per patch attribute 0 of patch 1
1319 * Note that every attribute has 4 components.
1321 static LLVMValueRef
get_non_vertex_index_offset(struct radv_shader_context
*ctx
)
1323 uint32_t num_patches
= ctx
->tcs_num_patches
;
1324 uint32_t num_tcs_outputs
;
1325 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
)
1326 num_tcs_outputs
= util_last_bit64(ctx
->shader_info
->tcs
.outputs_written
);
1328 num_tcs_outputs
= ctx
->options
->key
.tes
.tcs_num_outputs
;
1330 uint32_t output_vertex_size
= num_tcs_outputs
* 16;
1331 uint32_t pervertex_output_patch_size
= ctx
->shader
->info
.tess
.tcs_vertices_out
* output_vertex_size
;
1333 return LLVMConstInt(ctx
->ac
.i32
, pervertex_output_patch_size
* num_patches
, false);
1336 static LLVMValueRef
calc_param_stride(struct radv_shader_context
*ctx
,
1337 LLVMValueRef vertex_index
)
1339 LLVMValueRef param_stride
;
1341 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.tess
.tcs_vertices_out
* ctx
->tcs_num_patches
, false);
1343 param_stride
= LLVMConstInt(ctx
->ac
.i32
, ctx
->tcs_num_patches
, false);
1344 return param_stride
;
1347 static LLVMValueRef
get_tcs_tes_buffer_address(struct radv_shader_context
*ctx
,
1348 LLVMValueRef vertex_index
,
1349 LLVMValueRef param_index
)
1351 LLVMValueRef base_addr
;
1352 LLVMValueRef param_stride
, constant16
;
1353 LLVMValueRef rel_patch_id
= get_rel_patch_id(ctx
);
1354 LLVMValueRef vertices_per_patch
= LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.tess
.tcs_vertices_out
, false);
1355 constant16
= LLVMConstInt(ctx
->ac
.i32
, 16, false);
1356 param_stride
= calc_param_stride(ctx
, vertex_index
);
1358 base_addr
= ac_build_imad(&ctx
->ac
, rel_patch_id
,
1359 vertices_per_patch
, vertex_index
);
1361 base_addr
= rel_patch_id
;
1364 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
1365 LLVMBuildMul(ctx
->ac
.builder
, param_index
,
1366 param_stride
, ""), "");
1368 base_addr
= LLVMBuildMul(ctx
->ac
.builder
, base_addr
, constant16
, "");
1370 if (!vertex_index
) {
1371 LLVMValueRef patch_data_offset
= get_non_vertex_index_offset(ctx
);
1373 base_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_addr
,
1374 patch_data_offset
, "");
1379 static LLVMValueRef
get_tcs_tes_buffer_address_params(struct radv_shader_context
*ctx
,
1381 unsigned const_index
,
1383 LLVMValueRef vertex_index
,
1384 LLVMValueRef indir_index
)
1386 LLVMValueRef param_index
;
1389 param_index
= LLVMBuildAdd(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, param
, false),
1392 if (const_index
&& !is_compact
)
1393 param
+= const_index
;
1394 param_index
= LLVMConstInt(ctx
->ac
.i32
, param
, false);
1396 return get_tcs_tes_buffer_address(ctx
, vertex_index
, param_index
);
1400 get_dw_address(struct radv_shader_context
*ctx
,
1401 LLVMValueRef dw_addr
,
1403 unsigned const_index
,
1404 bool compact_const_index
,
1405 LLVMValueRef vertex_index
,
1406 LLVMValueRef stride
,
1407 LLVMValueRef indir_index
)
1412 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1413 LLVMBuildMul(ctx
->ac
.builder
,
1419 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1420 LLVMBuildMul(ctx
->ac
.builder
, indir_index
,
1421 LLVMConstInt(ctx
->ac
.i32
, 4, false), ""), "");
1422 else if (const_index
&& !compact_const_index
)
1423 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1424 LLVMConstInt(ctx
->ac
.i32
, const_index
* 4, false), "");
1426 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1427 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false), "");
1429 if (const_index
&& compact_const_index
)
1430 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1431 LLVMConstInt(ctx
->ac
.i32
, const_index
, false), "");
1436 load_tcs_varyings(struct ac_shader_abi
*abi
,
1438 LLVMValueRef vertex_index
,
1439 LLVMValueRef indir_index
,
1440 unsigned const_index
,
1442 unsigned driver_location
,
1444 unsigned num_components
,
1449 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1450 LLVMValueRef dw_addr
, stride
;
1451 LLVMValueRef value
[4], result
;
1452 unsigned param
= shader_io_get_unique_index(location
);
1455 uint32_t input_vertex_size
= (ctx
->tcs_num_inputs
* 16) / 4;
1456 stride
= LLVMConstInt(ctx
->ac
.i32
, input_vertex_size
, false);
1457 dw_addr
= get_tcs_in_current_patch_offset(ctx
);
1460 stride
= get_tcs_out_vertex_stride(ctx
);
1461 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1463 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1468 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
1471 for (unsigned i
= 0; i
< num_components
+ component
; i
++) {
1472 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
1473 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1476 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1481 store_tcs_output(struct ac_shader_abi
*abi
,
1482 const nir_variable
*var
,
1483 LLVMValueRef vertex_index
,
1484 LLVMValueRef param_index
,
1485 unsigned const_index
,
1489 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1490 const unsigned location
= var
->data
.location
;
1491 unsigned component
= var
->data
.location_frac
;
1492 const bool is_patch
= var
->data
.patch
;
1493 const bool is_compact
= var
->data
.compact
;
1494 LLVMValueRef dw_addr
;
1495 LLVMValueRef stride
= NULL
;
1496 LLVMValueRef buf_addr
= NULL
;
1498 bool store_lds
= true;
1501 if (!(ctx
->shader
->info
.patch_outputs_read
& (1U << (location
- VARYING_SLOT_PATCH0
))))
1504 if (!(ctx
->shader
->info
.outputs_read
& (1ULL << location
)))
1508 param
= shader_io_get_unique_index(location
);
1509 if ((location
== VARYING_SLOT_CLIP_DIST0
|| location
== VARYING_SLOT_CLIP_DIST1
) && is_compact
) {
1510 const_index
+= component
;
1513 if (const_index
>= 4) {
1520 stride
= get_tcs_out_vertex_stride(ctx
);
1521 dw_addr
= get_tcs_out_current_patch_offset(ctx
);
1523 dw_addr
= get_tcs_out_current_patch_data_offset(ctx
);
1526 dw_addr
= get_dw_address(ctx
, dw_addr
, param
, const_index
, is_compact
, vertex_index
, stride
,
1528 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
, is_compact
,
1529 vertex_index
, param_index
);
1531 bool is_tess_factor
= false;
1532 if (location
== VARYING_SLOT_TESS_LEVEL_INNER
||
1533 location
== VARYING_SLOT_TESS_LEVEL_OUTER
)
1534 is_tess_factor
= true;
1536 unsigned base
= is_compact
? const_index
: 0;
1537 for (unsigned chan
= 0; chan
< 8; chan
++) {
1538 if (!(writemask
& (1 << chan
)))
1540 LLVMValueRef value
= ac_llvm_extract_elem(&ctx
->ac
, src
, chan
- component
);
1541 value
= ac_to_integer(&ctx
->ac
, value
);
1542 value
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
1544 if (store_lds
|| is_tess_factor
) {
1545 LLVMValueRef dw_addr_chan
=
1546 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1547 LLVMConstInt(ctx
->ac
.i32
, chan
, false), "");
1548 ac_lds_store(&ctx
->ac
, dw_addr_chan
, value
);
1551 if (!is_tess_factor
&& writemask
!= 0xF)
1552 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, value
, 1,
1553 buf_addr
, ctx
->oc_lds
,
1554 4 * (base
+ chan
), ac_glc
, false);
1557 if (writemask
== 0xF) {
1558 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, src
, 4,
1559 buf_addr
, ctx
->oc_lds
,
1560 (base
* 4), ac_glc
, false);
1565 load_tes_input(struct ac_shader_abi
*abi
,
1567 LLVMValueRef vertex_index
,
1568 LLVMValueRef param_index
,
1569 unsigned const_index
,
1571 unsigned driver_location
,
1573 unsigned num_components
,
1578 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1579 LLVMValueRef buf_addr
;
1580 LLVMValueRef result
;
1581 unsigned param
= shader_io_get_unique_index(location
);
1583 if ((location
== VARYING_SLOT_CLIP_DIST0
|| location
== VARYING_SLOT_CLIP_DIST1
) && is_compact
) {
1584 const_index
+= component
;
1586 if (const_index
>= 4) {
1592 buf_addr
= get_tcs_tes_buffer_address_params(ctx
, param
, const_index
,
1593 is_compact
, vertex_index
, param_index
);
1595 LLVMValueRef comp_offset
= LLVMConstInt(ctx
->ac
.i32
, component
* 4, false);
1596 buf_addr
= LLVMBuildAdd(ctx
->ac
.builder
, buf_addr
, comp_offset
, "");
1598 result
= ac_build_buffer_load(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, num_components
, NULL
,
1599 buf_addr
, ctx
->oc_lds
, is_compact
? (4 * const_index
) : 0, ac_glc
, true, false);
1600 result
= ac_trim_vector(&ctx
->ac
, result
, num_components
);
1605 radv_emit_fetch_64bit(struct radv_shader_context
*ctx
,
1606 LLVMTypeRef type
, LLVMValueRef a
, LLVMValueRef b
)
1608 LLVMValueRef values
[2] = {
1609 ac_to_integer(&ctx
->ac
, a
),
1610 ac_to_integer(&ctx
->ac
, b
),
1612 LLVMValueRef result
= ac_build_gather_values(&ctx
->ac
, values
, 2);
1613 return LLVMBuildBitCast(ctx
->ac
.builder
, result
, type
, "");
1617 load_gs_input(struct ac_shader_abi
*abi
,
1619 unsigned driver_location
,
1621 unsigned num_components
,
1622 unsigned vertex_index
,
1623 unsigned const_index
,
1626 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1627 LLVMValueRef vtx_offset
;
1628 unsigned param
, vtx_offset_param
;
1629 LLVMValueRef value
[4], result
;
1631 vtx_offset_param
= vertex_index
;
1632 assert(vtx_offset_param
< 6);
1633 vtx_offset
= LLVMBuildMul(ctx
->ac
.builder
, ctx
->gs_vtx_offset
[vtx_offset_param
],
1634 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
1636 param
= shader_io_get_unique_index(location
);
1638 for (unsigned i
= component
; i
< num_components
+ component
; i
++) {
1639 if (ctx
->ac
.chip_class
>= GFX9
) {
1640 LLVMValueRef dw_addr
= ctx
->gs_vtx_offset
[vtx_offset_param
];
1641 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1642 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
, 0), "");
1643 value
[i
] = ac_lds_load(&ctx
->ac
, dw_addr
);
1645 if (ac_get_type_size(type
) == 8) {
1646 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
1647 LLVMConstInt(ctx
->ac
.i32
, param
* 4 + i
+ const_index
+ 1, 0), "");
1648 LLVMValueRef tmp
= ac_lds_load(&ctx
->ac
, dw_addr
);
1650 value
[i
] = radv_emit_fetch_64bit(ctx
, type
, value
[i
], tmp
);
1653 LLVMValueRef soffset
=
1654 LLVMConstInt(ctx
->ac
.i32
,
1655 (param
* 4 + i
+ const_index
) * 256,
1658 value
[i
] = ac_build_buffer_load(&ctx
->ac
,
1661 vtx_offset
, soffset
,
1662 0, ac_glc
, true, false);
1664 if (ac_get_type_size(type
) == 8) {
1665 soffset
= LLVMConstInt(ctx
->ac
.i32
,
1666 (param
* 4 + i
+ const_index
+ 1) * 256,
1670 ac_build_buffer_load(&ctx
->ac
,
1673 vtx_offset
, soffset
,
1674 0, ac_glc
, true, false);
1676 value
[i
] = radv_emit_fetch_64bit(ctx
, type
, value
[i
], tmp
);
1680 if (ac_get_type_size(type
) == 2) {
1681 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
], ctx
->ac
.i32
, "");
1682 value
[i
] = LLVMBuildTrunc(ctx
->ac
.builder
, value
[i
], ctx
->ac
.i16
, "");
1684 value
[i
] = LLVMBuildBitCast(ctx
->ac
.builder
, value
[i
], type
, "");
1686 result
= ac_build_varying_gather_values(&ctx
->ac
, value
, num_components
, component
);
1687 result
= ac_to_integer(&ctx
->ac
, result
);
1692 static void radv_emit_kill(struct ac_shader_abi
*abi
, LLVMValueRef visible
)
1694 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1695 ac_build_kill_if_false(&ctx
->ac
, visible
);
1699 radv_get_sample_pos_offset(uint32_t num_samples
)
1701 uint32_t sample_pos_offset
= 0;
1703 switch (num_samples
) {
1705 sample_pos_offset
= 1;
1708 sample_pos_offset
= 3;
1711 sample_pos_offset
= 7;
1716 return sample_pos_offset
;
1719 static LLVMValueRef
load_sample_position(struct ac_shader_abi
*abi
,
1720 LLVMValueRef sample_id
)
1722 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1724 LLVMValueRef result
;
1725 LLVMValueRef index
= LLVMConstInt(ctx
->ac
.i32
, RING_PS_SAMPLE_POSITIONS
, false);
1726 LLVMValueRef ptr
= LLVMBuildGEP(ctx
->ac
.builder
, ctx
->ring_offsets
, &index
, 1, "");
1728 ptr
= LLVMBuildBitCast(ctx
->ac
.builder
, ptr
,
1729 ac_array_in_const_addr_space(ctx
->ac
.v2f32
), "");
1731 uint32_t sample_pos_offset
=
1732 radv_get_sample_pos_offset(ctx
->options
->key
.fs
.num_samples
);
1735 LLVMBuildAdd(ctx
->ac
.builder
, sample_id
,
1736 LLVMConstInt(ctx
->ac
.i32
, sample_pos_offset
, false), "");
1737 result
= ac_build_load_invariant(&ctx
->ac
, ptr
, sample_id
);
1743 static LLVMValueRef
load_sample_mask_in(struct ac_shader_abi
*abi
)
1745 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1746 uint8_t log2_ps_iter_samples
;
1748 if (ctx
->shader_info
->ps
.force_persample
) {
1749 log2_ps_iter_samples
=
1750 util_logbase2(ctx
->options
->key
.fs
.num_samples
);
1752 log2_ps_iter_samples
= ctx
->options
->key
.fs
.log2_ps_iter_samples
;
1755 /* The bit pattern matches that used by fixed function fragment
1757 static const uint16_t ps_iter_masks
[] = {
1758 0xffff, /* not used */
1764 assert(log2_ps_iter_samples
< ARRAY_SIZE(ps_iter_masks
));
1766 uint32_t ps_iter_mask
= ps_iter_masks
[log2_ps_iter_samples
];
1768 LLVMValueRef result
, sample_id
;
1769 sample_id
= ac_unpack_param(&ctx
->ac
, abi
->ancillary
, 8, 4);
1770 sample_id
= LLVMBuildShl(ctx
->ac
.builder
, LLVMConstInt(ctx
->ac
.i32
, ps_iter_mask
, false), sample_id
, "");
1771 result
= LLVMBuildAnd(ctx
->ac
.builder
, sample_id
, abi
->sample_coverage
, "");
1776 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context
*ctx
,
1778 LLVMValueRef
*addrs
);
1781 visit_emit_vertex(struct ac_shader_abi
*abi
, unsigned stream
, LLVMValueRef
*addrs
)
1783 LLVMValueRef gs_next_vertex
;
1784 LLVMValueRef can_emit
;
1785 unsigned offset
= 0;
1786 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1788 if (ctx
->options
->key
.vs_common_out
.as_ngg
) {
1789 gfx10_ngg_gs_emit_vertex(ctx
, stream
, addrs
);
1793 /* Write vertex attribute values to GSVS ring */
1794 gs_next_vertex
= LLVMBuildLoad(ctx
->ac
.builder
,
1795 ctx
->gs_next_vertex
[stream
],
1798 /* If this thread has already emitted the declared maximum number of
1799 * vertices, don't emit any more: excessive vertex emissions are not
1800 * supposed to have any effect.
1802 can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
, gs_next_vertex
,
1803 LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.gs
.vertices_out
, false), "");
1805 bool use_kill
= !ctx
->shader_info
->gs
.writes_memory
;
1807 ac_build_kill_if_false(&ctx
->ac
, can_emit
);
1809 ac_build_ifcc(&ctx
->ac
, can_emit
, 6505);
1811 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
1812 unsigned output_usage_mask
=
1813 ctx
->shader_info
->gs
.output_usage_mask
[i
];
1814 uint8_t output_stream
=
1815 ctx
->shader_info
->gs
.output_streams
[i
];
1816 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
1817 int length
= util_last_bit(output_usage_mask
);
1819 if (!(ctx
->output_mask
& (1ull << i
)) ||
1820 output_stream
!= stream
)
1823 for (unsigned j
= 0; j
< length
; j
++) {
1824 if (!(output_usage_mask
& (1 << j
)))
1827 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
,
1829 LLVMValueRef voffset
=
1830 LLVMConstInt(ctx
->ac
.i32
, offset
*
1831 ctx
->shader
->info
.gs
.vertices_out
, false);
1835 voffset
= LLVMBuildAdd(ctx
->ac
.builder
, voffset
, gs_next_vertex
, "");
1836 voffset
= LLVMBuildMul(ctx
->ac
.builder
, voffset
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
1838 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
1839 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
1841 ac_build_buffer_store_dword(&ctx
->ac
,
1842 ctx
->gsvs_ring
[stream
],
1844 voffset
, ctx
->gs2vs_offset
, 0,
1845 ac_glc
| ac_slc
, true);
1849 gs_next_vertex
= LLVMBuildAdd(ctx
->ac
.builder
, gs_next_vertex
,
1851 LLVMBuildStore(ctx
->ac
.builder
, gs_next_vertex
, ctx
->gs_next_vertex
[stream
]);
1853 ac_build_sendmsg(&ctx
->ac
,
1854 AC_SENDMSG_GS_OP_EMIT
| AC_SENDMSG_GS
| (stream
<< 8),
1858 ac_build_endif(&ctx
->ac
, 6505);
1862 visit_end_primitive(struct ac_shader_abi
*abi
, unsigned stream
)
1864 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1866 if (ctx
->options
->key
.vs_common_out
.as_ngg
) {
1867 LLVMBuildStore(ctx
->ac
.builder
, ctx
->ac
.i32_0
, ctx
->gs_curprim_verts
[stream
]);
1871 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_CUT
| AC_SENDMSG_GS
| (stream
<< 8), ctx
->gs_wave_id
);
1875 load_tess_coord(struct ac_shader_abi
*abi
)
1877 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1879 LLVMValueRef coord
[4] = {
1886 if (ctx
->shader
->info
.tess
.primitive_mode
== GL_TRIANGLES
)
1887 coord
[2] = LLVMBuildFSub(ctx
->ac
.builder
, ctx
->ac
.f32_1
,
1888 LLVMBuildFAdd(ctx
->ac
.builder
, coord
[0], coord
[1], ""), "");
1890 return ac_build_gather_values(&ctx
->ac
, coord
, 3);
1894 load_patch_vertices_in(struct ac_shader_abi
*abi
)
1896 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1897 return LLVMConstInt(ctx
->ac
.i32
, ctx
->options
->key
.tcs
.input_vertices
, false);
1901 static LLVMValueRef
radv_load_base_vertex(struct ac_shader_abi
*abi
)
1903 return abi
->base_vertex
;
1906 static LLVMValueRef
radv_load_ssbo(struct ac_shader_abi
*abi
,
1907 LLVMValueRef buffer_ptr
, bool write
)
1909 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1910 LLVMValueRef result
;
1912 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1914 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
1915 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
1920 static LLVMValueRef
radv_load_ubo(struct ac_shader_abi
*abi
, LLVMValueRef buffer_ptr
)
1922 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1923 LLVMValueRef result
;
1925 if (LLVMGetTypeKind(LLVMTypeOf(buffer_ptr
)) != LLVMPointerTypeKind
) {
1926 /* Do not load the descriptor for inlined uniform blocks. */
1930 LLVMSetMetadata(buffer_ptr
, ctx
->ac
.uniform_md_kind
, ctx
->ac
.empty_md
);
1932 result
= LLVMBuildLoad(ctx
->ac
.builder
, buffer_ptr
, "");
1933 LLVMSetMetadata(result
, ctx
->ac
.invariant_load_md_kind
, ctx
->ac
.empty_md
);
1938 static LLVMValueRef
radv_get_sampler_desc(struct ac_shader_abi
*abi
,
1939 unsigned descriptor_set
,
1940 unsigned base_index
,
1941 unsigned constant_index
,
1943 enum ac_descriptor_type desc_type
,
1944 bool image
, bool write
,
1947 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
1948 LLVMValueRef list
= ctx
->descriptor_sets
[descriptor_set
];
1949 struct radv_descriptor_set_layout
*layout
= ctx
->options
->layout
->set
[descriptor_set
].layout
;
1950 struct radv_descriptor_set_binding_layout
*binding
= layout
->binding
+ base_index
;
1951 unsigned offset
= binding
->offset
;
1952 unsigned stride
= binding
->size
;
1954 LLVMBuilderRef builder
= ctx
->ac
.builder
;
1957 assert(base_index
< layout
->binding_count
);
1959 switch (desc_type
) {
1961 type
= ctx
->ac
.v8i32
;
1965 type
= ctx
->ac
.v8i32
;
1969 case AC_DESC_SAMPLER
:
1970 type
= ctx
->ac
.v4i32
;
1971 if (binding
->type
== VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER
) {
1972 offset
+= radv_combined_image_descriptor_sampler_offset(binding
);
1977 case AC_DESC_BUFFER
:
1978 type
= ctx
->ac
.v4i32
;
1981 case AC_DESC_PLANE_0
:
1982 case AC_DESC_PLANE_1
:
1983 case AC_DESC_PLANE_2
:
1984 type
= ctx
->ac
.v8i32
;
1986 offset
+= 32 * (desc_type
- AC_DESC_PLANE_0
);
1989 unreachable("invalid desc_type\n");
1992 offset
+= constant_index
* stride
;
1994 if (desc_type
== AC_DESC_SAMPLER
&& binding
->immutable_samplers_offset
&&
1995 (!index
|| binding
->immutable_samplers_equal
)) {
1996 if (binding
->immutable_samplers_equal
)
1999 const uint32_t *samplers
= radv_immutable_samplers(layout
, binding
);
2001 LLVMValueRef constants
[] = {
2002 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 0], 0),
2003 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 1], 0),
2004 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 2], 0),
2005 LLVMConstInt(ctx
->ac
.i32
, samplers
[constant_index
* 4 + 3], 0),
2007 return ac_build_gather_values(&ctx
->ac
, constants
, 4);
2010 assert(stride
% type_size
== 0);
2012 LLVMValueRef adjusted_index
= index
;
2013 if (!adjusted_index
)
2014 adjusted_index
= ctx
->ac
.i32_0
;
2016 adjusted_index
= LLVMBuildMul(builder
, adjusted_index
, LLVMConstInt(ctx
->ac
.i32
, stride
/ type_size
, 0), "");
2018 LLVMValueRef val_offset
= LLVMConstInt(ctx
->ac
.i32
, offset
, 0);
2019 list
= LLVMBuildGEP(builder
, list
, &val_offset
, 1, "");
2020 list
= LLVMBuildPointerCast(builder
, list
,
2021 ac_array_in_const32_addr_space(type
), "");
2023 LLVMValueRef descriptor
= ac_build_load_to_sgpr(&ctx
->ac
, list
, adjusted_index
);
2025 /* 3 plane formats always have same size and format for plane 1 & 2, so
2026 * use the tail from plane 1 so that we can store only the first 16 bytes
2027 * of the last plane. */
2028 if (desc_type
== AC_DESC_PLANE_2
) {
2029 LLVMValueRef descriptor2
= radv_get_sampler_desc(abi
, descriptor_set
, base_index
, constant_index
, index
, AC_DESC_PLANE_1
,image
, write
, bindless
);
2031 LLVMValueRef components
[8];
2032 for (unsigned i
= 0; i
< 4; ++i
)
2033 components
[i
] = ac_llvm_extract_elem(&ctx
->ac
, descriptor
, i
);
2035 for (unsigned i
= 4; i
< 8; ++i
)
2036 components
[i
] = ac_llvm_extract_elem(&ctx
->ac
, descriptor2
, i
);
2037 descriptor
= ac_build_gather_values(&ctx
->ac
, components
, 8);
2043 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
2044 * so we may need to fix it up. */
2046 adjust_vertex_fetch_alpha(struct radv_shader_context
*ctx
,
2047 unsigned adjustment
,
2050 if (adjustment
== RADV_ALPHA_ADJUST_NONE
)
2053 LLVMValueRef c30
= LLVMConstInt(ctx
->ac
.i32
, 30, 0);
2055 alpha
= LLVMBuildBitCast(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
2057 if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
)
2058 alpha
= LLVMBuildFPToUI(ctx
->ac
.builder
, alpha
, ctx
->ac
.i32
, "");
2060 alpha
= ac_to_integer(&ctx
->ac
, alpha
);
2062 /* For the integer-like cases, do a natural sign extension.
2064 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
2065 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
2068 alpha
= LLVMBuildShl(ctx
->ac
.builder
, alpha
,
2069 adjustment
== RADV_ALPHA_ADJUST_SNORM
?
2070 LLVMConstInt(ctx
->ac
.i32
, 7, 0) : c30
, "");
2071 alpha
= LLVMBuildAShr(ctx
->ac
.builder
, alpha
, c30
, "");
2073 /* Convert back to the right type. */
2074 if (adjustment
== RADV_ALPHA_ADJUST_SNORM
) {
2076 LLVMValueRef neg_one
= LLVMConstReal(ctx
->ac
.f32
, -1.0);
2077 alpha
= LLVMBuildSIToFP(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
2078 clamp
= LLVMBuildFCmp(ctx
->ac
.builder
, LLVMRealULT
, alpha
, neg_one
, "");
2079 alpha
= LLVMBuildSelect(ctx
->ac
.builder
, clamp
, neg_one
, alpha
, "");
2080 } else if (adjustment
== RADV_ALPHA_ADJUST_SSCALED
) {
2081 alpha
= LLVMBuildSIToFP(ctx
->ac
.builder
, alpha
, ctx
->ac
.f32
, "");
2084 return LLVMBuildBitCast(ctx
->ac
.builder
, alpha
, ctx
->ac
.i32
, "");
2088 get_num_channels_from_data_format(unsigned data_format
)
2090 switch (data_format
) {
2091 case V_008F0C_BUF_DATA_FORMAT_8
:
2092 case V_008F0C_BUF_DATA_FORMAT_16
:
2093 case V_008F0C_BUF_DATA_FORMAT_32
:
2095 case V_008F0C_BUF_DATA_FORMAT_8_8
:
2096 case V_008F0C_BUF_DATA_FORMAT_16_16
:
2097 case V_008F0C_BUF_DATA_FORMAT_32_32
:
2099 case V_008F0C_BUF_DATA_FORMAT_10_11_11
:
2100 case V_008F0C_BUF_DATA_FORMAT_11_11_10
:
2101 case V_008F0C_BUF_DATA_FORMAT_32_32_32
:
2103 case V_008F0C_BUF_DATA_FORMAT_8_8_8_8
:
2104 case V_008F0C_BUF_DATA_FORMAT_10_10_10_2
:
2105 case V_008F0C_BUF_DATA_FORMAT_2_10_10_10
:
2106 case V_008F0C_BUF_DATA_FORMAT_16_16_16_16
:
2107 case V_008F0C_BUF_DATA_FORMAT_32_32_32_32
:
2117 radv_fixup_vertex_input_fetches(struct radv_shader_context
*ctx
,
2119 unsigned num_channels
,
2122 LLVMValueRef zero
= is_float
? ctx
->ac
.f32_0
: ctx
->ac
.i32_0
;
2123 LLVMValueRef one
= is_float
? ctx
->ac
.f32_1
: ctx
->ac
.i32_1
;
2124 LLVMValueRef chan
[4];
2126 if (LLVMGetTypeKind(LLVMTypeOf(value
)) == LLVMVectorTypeKind
) {
2127 unsigned vec_size
= LLVMGetVectorSize(LLVMTypeOf(value
));
2129 if (num_channels
== 4 && num_channels
== vec_size
)
2132 num_channels
= MIN2(num_channels
, vec_size
);
2134 for (unsigned i
= 0; i
< num_channels
; i
++)
2135 chan
[i
] = ac_llvm_extract_elem(&ctx
->ac
, value
, i
);
2138 assert(num_channels
== 1);
2143 for (unsigned i
= num_channels
; i
< 4; i
++) {
2144 chan
[i
] = i
== 3 ? one
: zero
;
2145 chan
[i
] = ac_to_integer(&ctx
->ac
, chan
[i
]);
2148 return ac_build_gather_values(&ctx
->ac
, chan
, 4);
2152 handle_vs_input_decl(struct radv_shader_context
*ctx
,
2153 struct nir_variable
*variable
)
2155 LLVMValueRef t_list_ptr
= ctx
->vertex_buffers
;
2156 LLVMValueRef t_offset
;
2157 LLVMValueRef t_list
;
2159 LLVMValueRef buffer_index
;
2160 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, true);
2161 uint8_t input_usage_mask
=
2162 ctx
->shader_info
->vs
.input_usage_mask
[variable
->data
.location
];
2163 unsigned num_input_channels
= util_last_bit(input_usage_mask
);
2165 variable
->data
.driver_location
= variable
->data
.location
* 4;
2167 enum glsl_base_type type
= glsl_get_base_type(variable
->type
);
2168 for (unsigned i
= 0; i
< attrib_count
; ++i
) {
2169 LLVMValueRef output
[4];
2170 unsigned attrib_index
= variable
->data
.location
+ i
- VERT_ATTRIB_GENERIC0
;
2171 unsigned attrib_format
= ctx
->options
->key
.vs
.vertex_attribute_formats
[attrib_index
];
2172 unsigned data_format
= attrib_format
& 0x0f;
2173 unsigned num_format
= (attrib_format
>> 4) & 0x07;
2174 bool is_float
= num_format
!= V_008F0C_BUF_NUM_FORMAT_UINT
&&
2175 num_format
!= V_008F0C_BUF_NUM_FORMAT_SINT
;
2177 if (ctx
->options
->key
.vs
.instance_rate_inputs
& (1u << attrib_index
)) {
2178 uint32_t divisor
= ctx
->options
->key
.vs
.instance_rate_divisors
[attrib_index
];
2181 buffer_index
= ctx
->abi
.instance_id
;
2184 buffer_index
= LLVMBuildUDiv(ctx
->ac
.builder
, buffer_index
,
2185 LLVMConstInt(ctx
->ac
.i32
, divisor
, 0), "");
2188 buffer_index
= ctx
->ac
.i32_0
;
2191 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
, ctx
->abi
.start_instance
, buffer_index
, "");
2193 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
, ctx
->abi
.vertex_id
,
2194 ctx
->abi
.base_vertex
, "");
2196 /* Adjust the number of channels to load based on the vertex
2199 unsigned num_format_channels
= get_num_channels_from_data_format(data_format
);
2200 unsigned num_channels
= MIN2(num_input_channels
, num_format_channels
);
2201 unsigned attrib_binding
= ctx
->options
->key
.vs
.vertex_attribute_bindings
[attrib_index
];
2202 unsigned attrib_offset
= ctx
->options
->key
.vs
.vertex_attribute_offsets
[attrib_index
];
2203 unsigned attrib_stride
= ctx
->options
->key
.vs
.vertex_attribute_strides
[attrib_index
];
2205 if (ctx
->options
->key
.vs
.post_shuffle
& (1 << attrib_index
)) {
2206 /* Always load, at least, 3 channels for formats that
2207 * need to be shuffled because X<->Z.
2209 num_channels
= MAX2(num_channels
, 3);
2212 if (attrib_stride
!= 0 && attrib_offset
> attrib_stride
) {
2213 LLVMValueRef buffer_offset
=
2214 LLVMConstInt(ctx
->ac
.i32
,
2215 attrib_offset
/ attrib_stride
, false);
2217 buffer_index
= LLVMBuildAdd(ctx
->ac
.builder
,
2221 attrib_offset
= attrib_offset
% attrib_stride
;
2224 t_offset
= LLVMConstInt(ctx
->ac
.i32
, attrib_binding
, false);
2225 t_list
= ac_build_load_to_sgpr(&ctx
->ac
, t_list_ptr
, t_offset
);
2227 input
= ac_build_struct_tbuffer_load(&ctx
->ac
, t_list
,
2229 LLVMConstInt(ctx
->ac
.i32
, attrib_offset
, false),
2230 ctx
->ac
.i32_0
, ctx
->ac
.i32_0
,
2232 data_format
, num_format
, 0, true);
2234 if (ctx
->options
->key
.vs
.post_shuffle
& (1 << attrib_index
)) {
2236 c
[0] = ac_llvm_extract_elem(&ctx
->ac
, input
, 2);
2237 c
[1] = ac_llvm_extract_elem(&ctx
->ac
, input
, 1);
2238 c
[2] = ac_llvm_extract_elem(&ctx
->ac
, input
, 0);
2239 c
[3] = ac_llvm_extract_elem(&ctx
->ac
, input
, 3);
2241 input
= ac_build_gather_values(&ctx
->ac
, c
, 4);
2244 input
= radv_fixup_vertex_input_fetches(ctx
, input
, num_channels
,
2247 for (unsigned chan
= 0; chan
< 4; chan
++) {
2248 LLVMValueRef llvm_chan
= LLVMConstInt(ctx
->ac
.i32
, chan
, false);
2249 output
[chan
] = LLVMBuildExtractElement(ctx
->ac
.builder
, input
, llvm_chan
, "");
2250 if (type
== GLSL_TYPE_FLOAT16
) {
2251 output
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.f32
, "");
2252 output
[chan
] = LLVMBuildFPTrunc(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.f16
, "");
2256 unsigned alpha_adjust
= (ctx
->options
->key
.vs
.alpha_adjust
>> (attrib_index
* 2)) & 3;
2257 output
[3] = adjust_vertex_fetch_alpha(ctx
, alpha_adjust
, output
[3]);
2259 for (unsigned chan
= 0; chan
< 4; chan
++) {
2260 output
[chan
] = ac_to_integer(&ctx
->ac
, output
[chan
]);
2261 if (type
== GLSL_TYPE_UINT16
|| type
== GLSL_TYPE_INT16
)
2262 output
[chan
] = LLVMBuildTrunc(ctx
->ac
.builder
, output
[chan
], ctx
->ac
.i16
, "");
2264 ctx
->inputs
[ac_llvm_reg_index_soa(variable
->data
.location
+ i
, chan
)] = output
[chan
];
2270 handle_vs_inputs(struct radv_shader_context
*ctx
,
2271 struct nir_shader
*nir
) {
2272 nir_foreach_variable(variable
, &nir
->inputs
)
2273 handle_vs_input_decl(ctx
, variable
);
2277 prepare_interp_optimize(struct radv_shader_context
*ctx
,
2278 struct nir_shader
*nir
)
2280 bool uses_center
= false;
2281 bool uses_centroid
= false;
2282 nir_foreach_variable(variable
, &nir
->inputs
) {
2283 if (glsl_get_base_type(glsl_without_array(variable
->type
)) != GLSL_TYPE_FLOAT
||
2284 variable
->data
.sample
)
2287 if (variable
->data
.centroid
)
2288 uses_centroid
= true;
2293 if (uses_center
&& uses_centroid
) {
2294 LLVMValueRef sel
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntSLT
, ctx
->abi
.prim_mask
, ctx
->ac
.i32_0
, "");
2295 ctx
->abi
.persp_centroid
= LLVMBuildSelect(ctx
->ac
.builder
, sel
, ctx
->abi
.persp_center
, ctx
->abi
.persp_centroid
, "");
2296 ctx
->abi
.linear_centroid
= LLVMBuildSelect(ctx
->ac
.builder
, sel
, ctx
->abi
.linear_center
, ctx
->abi
.linear_centroid
, "");
2301 scan_shader_output_decl(struct radv_shader_context
*ctx
,
2302 struct nir_variable
*variable
,
2303 struct nir_shader
*shader
,
2304 gl_shader_stage stage
)
2306 int idx
= variable
->data
.location
+ variable
->data
.index
;
2307 unsigned attrib_count
= glsl_count_attribute_slots(variable
->type
, false);
2308 uint64_t mask_attribs
;
2310 variable
->data
.driver_location
= idx
* 4;
2312 /* tess ctrl has it's own load/store paths for outputs */
2313 if (stage
== MESA_SHADER_TESS_CTRL
)
2316 if (variable
->data
.compact
) {
2317 unsigned component_count
= variable
->data
.location_frac
+
2318 glsl_get_length(variable
->type
);
2319 attrib_count
= (component_count
+ 3) / 4;
2322 mask_attribs
= ((1ull << attrib_count
) - 1) << idx
;
2324 ctx
->output_mask
|= mask_attribs
;
2328 /* Initialize arguments for the shader export intrinsic */
2330 si_llvm_init_export_args(struct radv_shader_context
*ctx
,
2331 LLVMValueRef
*values
,
2332 unsigned enabled_channels
,
2334 struct ac_export_args
*args
)
2336 /* Specify the channels that are enabled. */
2337 args
->enabled_channels
= enabled_channels
;
2339 /* Specify whether the EXEC mask represents the valid mask */
2340 args
->valid_mask
= 0;
2342 /* Specify whether this is the last export */
2345 /* Specify the target we are exporting */
2346 args
->target
= target
;
2348 args
->compr
= false;
2349 args
->out
[0] = LLVMGetUndef(ctx
->ac
.f32
);
2350 args
->out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
2351 args
->out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
2352 args
->out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
2357 bool is_16bit
= ac_get_type_size(LLVMTypeOf(values
[0])) == 2;
2358 if (ctx
->stage
== MESA_SHADER_FRAGMENT
) {
2359 unsigned index
= target
- V_008DFC_SQ_EXP_MRT
;
2360 unsigned col_format
= (ctx
->options
->key
.fs
.col_format
>> (4 * index
)) & 0xf;
2361 bool is_int8
= (ctx
->options
->key
.fs
.is_int8
>> index
) & 1;
2362 bool is_int10
= (ctx
->options
->key
.fs
.is_int10
>> index
) & 1;
2365 LLVMValueRef (*packf
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2]) = NULL
;
2366 LLVMValueRef (*packi
)(struct ac_llvm_context
*ctx
, LLVMValueRef args
[2],
2367 unsigned bits
, bool hi
) = NULL
;
2369 switch(col_format
) {
2370 case V_028714_SPI_SHADER_ZERO
:
2371 args
->enabled_channels
= 0; /* writemask */
2372 args
->target
= V_008DFC_SQ_EXP_NULL
;
2375 case V_028714_SPI_SHADER_32_R
:
2376 args
->enabled_channels
= 1;
2377 args
->out
[0] = values
[0];
2380 case V_028714_SPI_SHADER_32_GR
:
2381 args
->enabled_channels
= 0x3;
2382 args
->out
[0] = values
[0];
2383 args
->out
[1] = values
[1];
2386 case V_028714_SPI_SHADER_32_AR
:
2387 if (ctx
->ac
.chip_class
>= GFX10
) {
2388 args
->enabled_channels
= 0x3;
2389 args
->out
[0] = values
[0];
2390 args
->out
[1] = values
[3];
2392 args
->enabled_channels
= 0x9;
2393 args
->out
[0] = values
[0];
2394 args
->out
[3] = values
[3];
2398 case V_028714_SPI_SHADER_FP16_ABGR
:
2399 args
->enabled_channels
= 0x5;
2400 packf
= ac_build_cvt_pkrtz_f16
;
2402 for (unsigned chan
= 0; chan
< 4; chan
++)
2403 values
[chan
] = LLVMBuildFPExt(ctx
->ac
.builder
,
2409 case V_028714_SPI_SHADER_UNORM16_ABGR
:
2410 args
->enabled_channels
= 0x5;
2411 packf
= ac_build_cvt_pknorm_u16
;
2414 case V_028714_SPI_SHADER_SNORM16_ABGR
:
2415 args
->enabled_channels
= 0x5;
2416 packf
= ac_build_cvt_pknorm_i16
;
2419 case V_028714_SPI_SHADER_UINT16_ABGR
:
2420 args
->enabled_channels
= 0x5;
2421 packi
= ac_build_cvt_pk_u16
;
2423 for (unsigned chan
= 0; chan
< 4; chan
++)
2424 values
[chan
] = LLVMBuildZExt(ctx
->ac
.builder
,
2425 ac_to_integer(&ctx
->ac
, values
[chan
]),
2430 case V_028714_SPI_SHADER_SINT16_ABGR
:
2431 args
->enabled_channels
= 0x5;
2432 packi
= ac_build_cvt_pk_i16
;
2434 for (unsigned chan
= 0; chan
< 4; chan
++)
2435 values
[chan
] = LLVMBuildSExt(ctx
->ac
.builder
,
2436 ac_to_integer(&ctx
->ac
, values
[chan
]),
2442 case V_028714_SPI_SHADER_32_ABGR
:
2443 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
2447 /* Pack f16 or norm_i16/u16. */
2449 for (chan
= 0; chan
< 2; chan
++) {
2450 LLVMValueRef pack_args
[2] = {
2452 values
[2 * chan
+ 1]
2454 LLVMValueRef packed
;
2456 packed
= packf(&ctx
->ac
, pack_args
);
2457 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2459 args
->compr
= 1; /* COMPR flag */
2464 for (chan
= 0; chan
< 2; chan
++) {
2465 LLVMValueRef pack_args
[2] = {
2466 ac_to_integer(&ctx
->ac
, values
[2 * chan
]),
2467 ac_to_integer(&ctx
->ac
, values
[2 * chan
+ 1])
2469 LLVMValueRef packed
;
2471 packed
= packi(&ctx
->ac
, pack_args
,
2472 is_int8
? 8 : is_int10
? 10 : 16,
2474 args
->out
[chan
] = ac_to_float(&ctx
->ac
, packed
);
2476 args
->compr
= 1; /* COMPR flag */
2482 for (unsigned chan
= 0; chan
< 4; chan
++) {
2483 values
[chan
] = LLVMBuildBitCast(ctx
->ac
.builder
, values
[chan
], ctx
->ac
.i16
, "");
2484 args
->out
[chan
] = LLVMBuildZExt(ctx
->ac
.builder
, values
[chan
], ctx
->ac
.i32
, "");
2487 memcpy(&args
->out
[0], values
, sizeof(values
[0]) * 4);
2489 for (unsigned i
= 0; i
< 4; ++i
)
2490 args
->out
[i
] = ac_to_float(&ctx
->ac
, args
->out
[i
]);
2494 radv_export_param(struct radv_shader_context
*ctx
, unsigned index
,
2495 LLVMValueRef
*values
, unsigned enabled_channels
)
2497 struct ac_export_args args
;
2499 si_llvm_init_export_args(ctx
, values
, enabled_channels
,
2500 V_008DFC_SQ_EXP_PARAM
+ index
, &args
);
2501 ac_build_export(&ctx
->ac
, &args
);
2505 radv_load_output(struct radv_shader_context
*ctx
, unsigned index
, unsigned chan
)
2507 LLVMValueRef output
= ctx
->abi
.outputs
[ac_llvm_reg_index_soa(index
, chan
)];
2508 return LLVMBuildLoad(ctx
->ac
.builder
, output
, "");
2512 radv_emit_stream_output(struct radv_shader_context
*ctx
,
2513 LLVMValueRef
const *so_buffers
,
2514 LLVMValueRef
const *so_write_offsets
,
2515 const struct radv_stream_output
*output
,
2516 struct radv_shader_output_values
*shader_out
)
2518 unsigned num_comps
= util_bitcount(output
->component_mask
);
2519 unsigned buf
= output
->buffer
;
2520 unsigned offset
= output
->offset
;
2522 LLVMValueRef out
[4];
2524 assert(num_comps
&& num_comps
<= 4);
2525 if (!num_comps
|| num_comps
> 4)
2528 /* Get the first component. */
2529 start
= ffs(output
->component_mask
) - 1;
2531 /* Load the output as int. */
2532 for (int i
= 0; i
< num_comps
; i
++) {
2533 out
[i
] = ac_to_integer(&ctx
->ac
, shader_out
->values
[start
+ i
]);
2536 /* Pack the output. */
2537 LLVMValueRef vdata
= NULL
;
2539 switch (num_comps
) {
2540 case 1: /* as i32 */
2543 case 2: /* as v2i32 */
2544 case 3: /* as v4i32 (aligned to 4) */
2545 out
[3] = LLVMGetUndef(ctx
->ac
.i32
);
2547 case 4: /* as v4i32 */
2548 vdata
= ac_build_gather_values(&ctx
->ac
, out
,
2549 !ac_has_vec3_support(ctx
->ac
.chip_class
, false) ?
2550 util_next_power_of_two(num_comps
) :
2555 ac_build_buffer_store_dword(&ctx
->ac
, so_buffers
[buf
],
2556 vdata
, num_comps
, so_write_offsets
[buf
],
2557 ctx
->ac
.i32_0
, offset
,
2558 ac_glc
| ac_slc
, false);
2562 radv_emit_streamout(struct radv_shader_context
*ctx
, unsigned stream
)
2566 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2567 assert(ctx
->streamout_config
);
2568 LLVMValueRef so_vtx_count
=
2569 ac_build_bfe(&ctx
->ac
, ctx
->streamout_config
,
2570 LLVMConstInt(ctx
->ac
.i32
, 16, false),
2571 LLVMConstInt(ctx
->ac
.i32
, 7, false), false);
2573 LLVMValueRef tid
= ac_get_thread_id(&ctx
->ac
);
2575 /* can_emit = tid < so_vtx_count; */
2576 LLVMValueRef can_emit
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntULT
,
2577 tid
, so_vtx_count
, "");
2579 /* Emit the streamout code conditionally. This actually avoids
2580 * out-of-bounds buffer access. The hw tells us via the SGPR
2581 * (so_vtx_count) which threads are allowed to emit streamout data.
2583 ac_build_ifcc(&ctx
->ac
, can_emit
, 6501);
2585 /* The buffer offset is computed as follows:
2586 * ByteOffset = streamout_offset[buffer_id]*4 +
2587 * (streamout_write_index + thread_id)*stride[buffer_id] +
2590 LLVMValueRef so_write_index
= ctx
->streamout_write_idx
;
2592 /* Compute (streamout_write_index + thread_id). */
2594 LLVMBuildAdd(ctx
->ac
.builder
, so_write_index
, tid
, "");
2596 /* Load the descriptor and compute the write offset for each
2599 LLVMValueRef so_write_offset
[4] = {};
2600 LLVMValueRef so_buffers
[4] = {};
2601 LLVMValueRef buf_ptr
= ctx
->streamout_buffers
;
2603 for (i
= 0; i
< 4; i
++) {
2604 uint16_t stride
= ctx
->shader_info
->so
.strides
[i
];
2609 LLVMValueRef offset
=
2610 LLVMConstInt(ctx
->ac
.i32
, i
, false);
2612 so_buffers
[i
] = ac_build_load_to_sgpr(&ctx
->ac
,
2615 LLVMValueRef so_offset
= ctx
->streamout_offset
[i
];
2617 so_offset
= LLVMBuildMul(ctx
->ac
.builder
, so_offset
,
2618 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
2620 so_write_offset
[i
] =
2621 ac_build_imad(&ctx
->ac
, so_write_index
,
2622 LLVMConstInt(ctx
->ac
.i32
,
2627 /* Write streamout data. */
2628 for (i
= 0; i
< ctx
->shader_info
->so
.num_outputs
; i
++) {
2629 struct radv_shader_output_values shader_out
= {};
2630 struct radv_stream_output
*output
=
2631 &ctx
->shader_info
->so
.outputs
[i
];
2633 if (stream
!= output
->stream
)
2636 for (int j
= 0; j
< 4; j
++) {
2637 shader_out
.values
[j
] =
2638 radv_load_output(ctx
, output
->location
, j
);
2641 radv_emit_stream_output(ctx
, so_buffers
,so_write_offset
,
2642 output
, &shader_out
);
2645 ac_build_endif(&ctx
->ac
, 6501);
2649 radv_build_param_exports(struct radv_shader_context
*ctx
,
2650 struct radv_shader_output_values
*outputs
,
2652 struct radv_vs_output_info
*outinfo
,
2653 bool export_clip_dists
)
2655 unsigned param_count
= 0;
2657 for (unsigned i
= 0; i
< noutput
; i
++) {
2658 unsigned slot_name
= outputs
[i
].slot_name
;
2659 unsigned usage_mask
= outputs
[i
].usage_mask
;
2661 if (slot_name
!= VARYING_SLOT_LAYER
&&
2662 slot_name
!= VARYING_SLOT_PRIMITIVE_ID
&&
2663 slot_name
!= VARYING_SLOT_CLIP_DIST0
&&
2664 slot_name
!= VARYING_SLOT_CLIP_DIST1
&&
2665 slot_name
< VARYING_SLOT_VAR0
)
2668 if ((slot_name
== VARYING_SLOT_CLIP_DIST0
||
2669 slot_name
== VARYING_SLOT_CLIP_DIST1
) && !export_clip_dists
)
2672 radv_export_param(ctx
, param_count
, outputs
[i
].values
, usage_mask
);
2674 assert(i
< ARRAY_SIZE(outinfo
->vs_output_param_offset
));
2675 outinfo
->vs_output_param_offset
[slot_name
] = param_count
++;
2678 outinfo
->param_exports
= param_count
;
2681 /* Generate export instructions for hardware VS shader stage or NGG GS stage
2682 * (position and parameter data only).
2685 radv_llvm_export_vs(struct radv_shader_context
*ctx
,
2686 struct radv_shader_output_values
*outputs
,
2688 struct radv_vs_output_info
*outinfo
,
2689 bool export_clip_dists
)
2691 LLVMValueRef psize_value
= NULL
, layer_value
= NULL
, viewport_value
= NULL
;
2692 struct ac_export_args pos_args
[4] = {};
2693 unsigned pos_idx
, index
;
2696 /* Build position exports */
2697 for (i
= 0; i
< noutput
; i
++) {
2698 switch (outputs
[i
].slot_name
) {
2699 case VARYING_SLOT_POS
:
2700 si_llvm_init_export_args(ctx
, outputs
[i
].values
, 0xf,
2701 V_008DFC_SQ_EXP_POS
, &pos_args
[0]);
2703 case VARYING_SLOT_PSIZ
:
2704 psize_value
= outputs
[i
].values
[0];
2706 case VARYING_SLOT_LAYER
:
2707 layer_value
= outputs
[i
].values
[0];
2709 case VARYING_SLOT_VIEWPORT
:
2710 viewport_value
= outputs
[i
].values
[0];
2712 case VARYING_SLOT_CLIP_DIST0
:
2713 case VARYING_SLOT_CLIP_DIST1
:
2714 index
= 2 + outputs
[i
].slot_index
;
2715 si_llvm_init_export_args(ctx
, outputs
[i
].values
, 0xf,
2716 V_008DFC_SQ_EXP_POS
+ index
,
2724 /* We need to add the position output manually if it's missing. */
2725 if (!pos_args
[0].out
[0]) {
2726 pos_args
[0].enabled_channels
= 0xf; /* writemask */
2727 pos_args
[0].valid_mask
= 0; /* EXEC mask */
2728 pos_args
[0].done
= 0; /* last export? */
2729 pos_args
[0].target
= V_008DFC_SQ_EXP_POS
;
2730 pos_args
[0].compr
= 0; /* COMPR flag */
2731 pos_args
[0].out
[0] = ctx
->ac
.f32_0
; /* X */
2732 pos_args
[0].out
[1] = ctx
->ac
.f32_0
; /* Y */
2733 pos_args
[0].out
[2] = ctx
->ac
.f32_0
; /* Z */
2734 pos_args
[0].out
[3] = ctx
->ac
.f32_1
; /* W */
2737 if (outinfo
->writes_pointsize
||
2738 outinfo
->writes_layer
||
2739 outinfo
->writes_viewport_index
) {
2740 pos_args
[1].enabled_channels
= ((outinfo
->writes_pointsize
== true ? 1 : 0) |
2741 (outinfo
->writes_layer
== true ? 4 : 0));
2742 pos_args
[1].valid_mask
= 0;
2743 pos_args
[1].done
= 0;
2744 pos_args
[1].target
= V_008DFC_SQ_EXP_POS
+ 1;
2745 pos_args
[1].compr
= 0;
2746 pos_args
[1].out
[0] = ctx
->ac
.f32_0
; /* X */
2747 pos_args
[1].out
[1] = ctx
->ac
.f32_0
; /* Y */
2748 pos_args
[1].out
[2] = ctx
->ac
.f32_0
; /* Z */
2749 pos_args
[1].out
[3] = ctx
->ac
.f32_0
; /* W */
2751 if (outinfo
->writes_pointsize
== true)
2752 pos_args
[1].out
[0] = psize_value
;
2753 if (outinfo
->writes_layer
== true)
2754 pos_args
[1].out
[2] = layer_value
;
2755 if (outinfo
->writes_viewport_index
== true) {
2756 if (ctx
->options
->chip_class
>= GFX9
) {
2757 /* GFX9 has the layer in out.z[10:0] and the viewport
2758 * index in out.z[19:16].
2760 LLVMValueRef v
= viewport_value
;
2761 v
= ac_to_integer(&ctx
->ac
, v
);
2762 v
= LLVMBuildShl(ctx
->ac
.builder
, v
,
2763 LLVMConstInt(ctx
->ac
.i32
, 16, false),
2765 v
= LLVMBuildOr(ctx
->ac
.builder
, v
,
2766 ac_to_integer(&ctx
->ac
, pos_args
[1].out
[2]), "");
2768 pos_args
[1].out
[2] = ac_to_float(&ctx
->ac
, v
);
2769 pos_args
[1].enabled_channels
|= 1 << 2;
2771 pos_args
[1].out
[3] = viewport_value
;
2772 pos_args
[1].enabled_channels
|= 1 << 3;
2777 for (i
= 0; i
< 4; i
++) {
2778 if (pos_args
[i
].out
[0])
2779 outinfo
->pos_exports
++;
2782 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
2783 * Setting valid_mask=1 prevents it and has no other effect.
2785 if (ctx
->ac
.family
== CHIP_NAVI10
||
2786 ctx
->ac
.family
== CHIP_NAVI12
||
2787 ctx
->ac
.family
== CHIP_NAVI14
)
2788 pos_args
[0].valid_mask
= 1;
2791 for (i
= 0; i
< 4; i
++) {
2792 if (!pos_args
[i
].out
[0])
2795 /* Specify the target we are exporting */
2796 pos_args
[i
].target
= V_008DFC_SQ_EXP_POS
+ pos_idx
++;
2798 if (pos_idx
== outinfo
->pos_exports
)
2799 /* Specify that this is the last export */
2800 pos_args
[i
].done
= 1;
2802 ac_build_export(&ctx
->ac
, &pos_args
[i
]);
2805 /* Build parameter exports */
2806 radv_build_param_exports(ctx
, outputs
, noutput
, outinfo
, export_clip_dists
);
2810 handle_vs_outputs_post(struct radv_shader_context
*ctx
,
2811 bool export_prim_id
,
2812 bool export_clip_dists
,
2813 struct radv_vs_output_info
*outinfo
)
2815 struct radv_shader_output_values
*outputs
;
2816 unsigned noutput
= 0;
2818 if (ctx
->options
->key
.has_multiview_view_index
) {
2819 LLVMValueRef
* tmp_out
= &ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, 0)];
2821 for(unsigned i
= 0; i
< 4; ++i
)
2822 ctx
->abi
.outputs
[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER
, i
)] =
2823 ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.f32
, "");
2826 LLVMBuildStore(ctx
->ac
.builder
, ac_to_float(&ctx
->ac
, ctx
->abi
.view_index
), *tmp_out
);
2827 ctx
->output_mask
|= 1ull << VARYING_SLOT_LAYER
;
2830 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
2831 sizeof(outinfo
->vs_output_param_offset
));
2832 outinfo
->pos_exports
= 0;
2834 if (!ctx
->options
->use_ngg_streamout
&&
2835 ctx
->shader_info
->so
.num_outputs
&&
2836 !ctx
->is_gs_copy_shader
) {
2837 /* The GS copy shader emission already emits streamout. */
2838 radv_emit_streamout(ctx
, 0);
2841 /* Allocate a temporary array for the output values. */
2842 unsigned num_outputs
= util_bitcount64(ctx
->output_mask
) + export_prim_id
;
2843 outputs
= malloc(num_outputs
* sizeof(outputs
[0]));
2845 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2846 if (!(ctx
->output_mask
& (1ull << i
)))
2849 outputs
[noutput
].slot_name
= i
;
2850 outputs
[noutput
].slot_index
= i
== VARYING_SLOT_CLIP_DIST1
;
2852 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
2853 !ctx
->is_gs_copy_shader
) {
2854 outputs
[noutput
].usage_mask
=
2855 ctx
->shader_info
->vs
.output_usage_mask
[i
];
2856 } else if (ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
2857 outputs
[noutput
].usage_mask
=
2858 ctx
->shader_info
->tes
.output_usage_mask
[i
];
2860 assert(ctx
->is_gs_copy_shader
);
2861 outputs
[noutput
].usage_mask
=
2862 ctx
->shader_info
->gs
.output_usage_mask
[i
];
2865 for (unsigned j
= 0; j
< 4; j
++) {
2866 outputs
[noutput
].values
[j
] =
2867 ac_to_float(&ctx
->ac
, radv_load_output(ctx
, i
, j
));
2873 /* Export PrimitiveID. */
2874 if (export_prim_id
) {
2875 outputs
[noutput
].slot_name
= VARYING_SLOT_PRIMITIVE_ID
;
2876 outputs
[noutput
].slot_index
= 0;
2877 outputs
[noutput
].usage_mask
= 0x1;
2878 outputs
[noutput
].values
[0] = ctx
->vs_prim_id
;
2879 for (unsigned j
= 1; j
< 4; j
++)
2880 outputs
[noutput
].values
[j
] = ctx
->ac
.f32_0
;
2884 radv_llvm_export_vs(ctx
, outputs
, noutput
, outinfo
, export_clip_dists
);
2890 handle_es_outputs_post(struct radv_shader_context
*ctx
,
2891 struct radv_es_output_info
*outinfo
)
2894 LLVMValueRef lds_base
= NULL
;
2896 if (ctx
->ac
.chip_class
>= GFX9
) {
2897 unsigned itemsize_dw
= outinfo
->esgs_itemsize
/ 4;
2898 LLVMValueRef vertex_idx
= ac_get_thread_id(&ctx
->ac
);
2899 LLVMValueRef wave_idx
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 24, 4);
2900 vertex_idx
= LLVMBuildOr(ctx
->ac
.builder
, vertex_idx
,
2901 LLVMBuildMul(ctx
->ac
.builder
, wave_idx
,
2902 LLVMConstInt(ctx
->ac
.i32
,
2903 ctx
->ac
.wave_size
, false), ""), "");
2904 lds_base
= LLVMBuildMul(ctx
->ac
.builder
, vertex_idx
,
2905 LLVMConstInt(ctx
->ac
.i32
, itemsize_dw
, 0), "");
2908 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2909 LLVMValueRef dw_addr
= NULL
;
2910 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
2911 unsigned output_usage_mask
;
2914 if (!(ctx
->output_mask
& (1ull << i
)))
2917 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
2919 ctx
->shader_info
->vs
.output_usage_mask
[i
];
2921 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
2923 ctx
->shader_info
->tes
.output_usage_mask
[i
];
2926 param_index
= shader_io_get_unique_index(i
);
2929 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
2930 LLVMConstInt(ctx
->ac
.i32
, param_index
* 4, false),
2934 for (j
= 0; j
< 4; j
++) {
2935 if (!(output_usage_mask
& (1 << j
)))
2938 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
2939 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
2940 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
2942 if (ctx
->ac
.chip_class
>= GFX9
) {
2943 LLVMValueRef dw_addr_offset
=
2944 LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
,
2945 LLVMConstInt(ctx
->ac
.i32
,
2948 ac_lds_store(&ctx
->ac
, dw_addr_offset
, out_val
);
2950 ac_build_buffer_store_dword(&ctx
->ac
,
2953 NULL
, ctx
->es2gs_offset
,
2954 (4 * param_index
+ j
) * 4,
2955 ac_glc
| ac_slc
, true);
2962 handle_ls_outputs_post(struct radv_shader_context
*ctx
)
2964 LLVMValueRef vertex_id
= ctx
->rel_auto_id
;
2965 uint32_t num_tcs_inputs
= util_last_bit64(ctx
->shader_info
->vs
.ls_outputs_written
);
2966 LLVMValueRef vertex_dw_stride
= LLVMConstInt(ctx
->ac
.i32
, num_tcs_inputs
* 4, false);
2967 LLVMValueRef base_dw_addr
= LLVMBuildMul(ctx
->ac
.builder
, vertex_id
,
2968 vertex_dw_stride
, "");
2970 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
2971 LLVMValueRef
*out_ptr
= &ctx
->abi
.outputs
[i
* 4];
2973 if (!(ctx
->output_mask
& (1ull << i
)))
2976 int param
= shader_io_get_unique_index(i
);
2977 LLVMValueRef dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, base_dw_addr
,
2978 LLVMConstInt(ctx
->ac
.i32
, param
* 4, false),
2980 for (unsigned j
= 0; j
< 4; j
++) {
2981 LLVMValueRef value
= LLVMBuildLoad(ctx
->ac
.builder
, out_ptr
[j
], "");
2982 value
= ac_to_integer(&ctx
->ac
, value
);
2983 value
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
2984 ac_lds_store(&ctx
->ac
, dw_addr
, value
);
2985 dw_addr
= LLVMBuildAdd(ctx
->ac
.builder
, dw_addr
, ctx
->ac
.i32_1
, "");
2990 static LLVMValueRef
get_wave_id_in_tg(struct radv_shader_context
*ctx
)
2992 return ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 24, 4);
2995 static LLVMValueRef
get_tgsize(struct radv_shader_context
*ctx
)
2997 return ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 28, 4);
3000 static LLVMValueRef
get_thread_id_in_tg(struct radv_shader_context
*ctx
)
3002 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3004 tmp
= LLVMBuildMul(builder
, get_wave_id_in_tg(ctx
),
3005 LLVMConstInt(ctx
->ac
.i32
, ctx
->ac
.wave_size
, false), "");
3006 return LLVMBuildAdd(builder
, tmp
, ac_get_thread_id(&ctx
->ac
), "");
3009 static LLVMValueRef
ngg_get_vtx_cnt(struct radv_shader_context
*ctx
)
3011 return ac_build_bfe(&ctx
->ac
, ctx
->gs_tg_info
,
3012 LLVMConstInt(ctx
->ac
.i32
, 12, false),
3013 LLVMConstInt(ctx
->ac
.i32
, 9, false),
3017 static LLVMValueRef
ngg_get_prim_cnt(struct radv_shader_context
*ctx
)
3019 return ac_build_bfe(&ctx
->ac
, ctx
->gs_tg_info
,
3020 LLVMConstInt(ctx
->ac
.i32
, 22, false),
3021 LLVMConstInt(ctx
->ac
.i32
, 9, false),
3025 static LLVMValueRef
ngg_get_ordered_id(struct radv_shader_context
*ctx
)
3027 return ac_build_bfe(&ctx
->ac
, ctx
->gs_tg_info
,
3029 LLVMConstInt(ctx
->ac
.i32
, 11, false),
3034 ngg_gs_get_vertex_storage(struct radv_shader_context
*ctx
)
3036 unsigned num_outputs
= util_bitcount64(ctx
->output_mask
);
3038 if (ctx
->options
->key
.has_multiview_view_index
)
3041 LLVMTypeRef elements
[2] = {
3042 LLVMArrayType(ctx
->ac
.i32
, 4 * num_outputs
),
3043 LLVMArrayType(ctx
->ac
.i8
, 4),
3045 LLVMTypeRef type
= LLVMStructTypeInContext(ctx
->ac
.context
, elements
, 2, false);
3046 type
= LLVMPointerType(LLVMArrayType(type
, 0), AC_ADDR_SPACE_LDS
);
3047 return LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->gs_ngg_emit
, type
, "");
3051 * Return a pointer to the LDS storage reserved for the N'th vertex, where N
3052 * is in emit order; that is:
3053 * - during the epilogue, N is the threadidx (relative to the entire threadgroup)
3054 * - during vertex emit, i.e. while the API GS shader invocation is running,
3055 * N = threadidx * gs_max_out_vertices + emitidx
3057 * Goals of the LDS memory layout:
3058 * 1. Eliminate bank conflicts on write for geometry shaders that have all emits
3059 * in uniform control flow
3060 * 2. Eliminate bank conflicts on read for export if, additionally, there is no
3062 * 3. Agnostic to the number of waves (since we don't know it before compiling)
3063 * 4. Allow coalescing of LDS instructions (ds_write_b128 etc.)
3064 * 5. Avoid wasting memory.
3066 * We use an AoS layout due to point 4 (this also helps point 3). In an AoS
3067 * layout, elimination of bank conflicts requires that each vertex occupy an
3068 * odd number of dwords. We use the additional dword to store the output stream
3069 * index as well as a flag to indicate whether this vertex ends a primitive
3070 * for rasterization.
3072 * Swizzling is required to satisfy points 1 and 2 simultaneously.
3074 * Vertices are stored in export order (gsthread * gs_max_out_vertices + emitidx).
3075 * Indices are swizzled in groups of 32, which ensures point 1 without
3076 * disturbing point 2.
3078 * \return an LDS pointer to type {[N x i32], [4 x i8]}
3081 ngg_gs_vertex_ptr(struct radv_shader_context
*ctx
, LLVMValueRef vertexidx
)
3083 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3084 LLVMValueRef storage
= ngg_gs_get_vertex_storage(ctx
);
3086 /* gs_max_out_vertices = 2^(write_stride_2exp) * some odd number */
3087 unsigned write_stride_2exp
= ffs(ctx
->shader
->info
.gs
.vertices_out
) - 1;
3088 if (write_stride_2exp
) {
3090 LLVMBuildLShr(builder
, vertexidx
,
3091 LLVMConstInt(ctx
->ac
.i32
, 5, false), "");
3092 LLVMValueRef swizzle
=
3093 LLVMBuildAnd(builder
, row
,
3094 LLVMConstInt(ctx
->ac
.i32
, (1u << write_stride_2exp
) - 1,
3096 vertexidx
= LLVMBuildXor(builder
, vertexidx
, swizzle
, "");
3099 return ac_build_gep0(&ctx
->ac
, storage
, vertexidx
);
3103 ngg_gs_emit_vertex_ptr(struct radv_shader_context
*ctx
, LLVMValueRef gsthread
,
3104 LLVMValueRef emitidx
)
3106 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3109 tmp
= LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.gs
.vertices_out
, false);
3110 tmp
= LLVMBuildMul(builder
, tmp
, gsthread
, "");
3111 const LLVMValueRef vertexidx
= LLVMBuildAdd(builder
, tmp
, emitidx
, "");
3112 return ngg_gs_vertex_ptr(ctx
, vertexidx
);
3115 /* Send GS Alloc Req message from the first wave of the group to SPI.
3116 * Message payload is:
3117 * - bits 0..10: vertices in group
3118 * - bits 12..22: primitives in group
3120 static void build_sendmsg_gs_alloc_req(struct radv_shader_context
*ctx
,
3121 LLVMValueRef vtx_cnt
,
3122 LLVMValueRef prim_cnt
)
3124 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3127 tmp
= LLVMBuildICmp(builder
, LLVMIntEQ
, get_wave_id_in_tg(ctx
), ctx
->ac
.i32_0
, "");
3128 ac_build_ifcc(&ctx
->ac
, tmp
, 5020);
3130 tmp
= LLVMBuildShl(builder
, prim_cnt
, LLVMConstInt(ctx
->ac
.i32
, 12, false),"");
3131 tmp
= LLVMBuildOr(builder
, tmp
, vtx_cnt
, "");
3132 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_ALLOC_REQ
, tmp
);
3134 ac_build_endif(&ctx
->ac
, 5020);
3138 unsigned num_vertices
;
3139 LLVMValueRef isnull
;
3141 LLVMValueRef index
[3];
3142 LLVMValueRef edgeflag
[3];
3145 static void build_export_prim(struct radv_shader_context
*ctx
,
3146 const struct ngg_prim
*prim
)
3148 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3149 struct ac_export_args args
;
3150 LLVMValueRef vertices
[3];
3151 LLVMValueRef odd
, even
;
3154 tmp
= LLVMBuildZExt(builder
, prim
->isnull
, ctx
->ac
.i32
, "");
3155 args
.out
[0] = LLVMBuildShl(builder
, tmp
, LLVMConstInt(ctx
->ac
.i32
, 31, false), "");
3157 for (unsigned i
= 0; i
< prim
->num_vertices
; ++i
) {
3158 tmp
= LLVMBuildZExt(builder
, prim
->edgeflag
[i
], ctx
->ac
.i32
, "");
3159 tmp
= LLVMBuildShl(builder
, tmp
,
3160 LLVMConstInt(ctx
->ac
.i32
, 9, false), "");
3161 vertices
[i
] = LLVMBuildOr(builder
, prim
->index
[i
], tmp
, "");
3164 switch (prim
->num_vertices
) {
3166 args
.out
[0] = LLVMBuildOr(builder
, args
.out
[0], vertices
[0], "");
3169 tmp
= LLVMBuildShl(builder
, vertices
[1],
3170 LLVMConstInt(ctx
->ac
.i32
, 10, false), "");
3171 tmp
= LLVMBuildOr(builder
, args
.out
[0], tmp
, "");
3172 args
.out
[0] = LLVMBuildOr(builder
, tmp
, vertices
[0], "");
3175 /* Swap vertices if needed to follow drawing order. */
3176 tmp
= LLVMBuildShl(builder
, vertices
[2],
3177 LLVMConstInt(ctx
->ac
.i32
, 20, false), "");
3178 even
= LLVMBuildOr(builder
, args
.out
[0], tmp
, "");
3179 tmp
= LLVMBuildShl(builder
, vertices
[1],
3180 LLVMConstInt(ctx
->ac
.i32
, 10, false), "");
3181 even
= LLVMBuildOr(builder
, even
, tmp
, "");
3182 even
= LLVMBuildOr(builder
, even
, vertices
[0], "");
3184 tmp
= LLVMBuildShl(builder
, vertices
[1],
3185 LLVMConstInt(ctx
->ac
.i32
, 20, false), "");
3186 odd
= LLVMBuildOr(builder
, args
.out
[0], tmp
, "");
3187 tmp
= LLVMBuildShl(builder
, vertices
[2],
3188 LLVMConstInt(ctx
->ac
.i32
, 10, false), "");
3189 odd
= LLVMBuildOr(builder
, odd
, tmp
, "");
3190 odd
= LLVMBuildOr(builder
, odd
, vertices
[0], "");
3192 args
.out
[0] = LLVMBuildSelect(builder
, prim
->swap
, odd
, even
, "");
3195 unreachable("invalid number of vertices");
3198 args
.out
[0] = LLVMBuildBitCast(builder
, args
.out
[0], ctx
->ac
.f32
, "");
3199 args
.out
[1] = LLVMGetUndef(ctx
->ac
.f32
);
3200 args
.out
[2] = LLVMGetUndef(ctx
->ac
.f32
);
3201 args
.out
[3] = LLVMGetUndef(ctx
->ac
.f32
);
3203 args
.target
= V_008DFC_SQ_EXP_PRIM
;
3204 args
.enabled_channels
= 1;
3206 args
.valid_mask
= false;
3209 ac_build_export(&ctx
->ac
, &args
);
3212 static struct radv_stream_output
*
3213 radv_get_stream_output_by_loc(struct radv_streamout_info
*so
, unsigned location
)
3215 for (unsigned i
= 0; i
< so
->num_outputs
; ++i
) {
3216 if (so
->outputs
[i
].location
== location
)
3217 return &so
->outputs
[i
];
3223 static void build_streamout_vertex(struct radv_shader_context
*ctx
,
3224 LLVMValueRef
*so_buffer
, LLVMValueRef
*wg_offset_dw
,
3225 unsigned stream
, LLVMValueRef offset_vtx
,
3226 LLVMValueRef vertexptr
)
3228 struct radv_streamout_info
*so
= &ctx
->shader_info
->so
;
3229 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3230 LLVMValueRef offset
[4] = {};
3233 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
3234 if (!wg_offset_dw
[buffer
])
3237 tmp
= LLVMBuildMul(builder
, offset_vtx
,
3238 LLVMConstInt(ctx
->ac
.i32
, so
->strides
[buffer
], false), "");
3239 tmp
= LLVMBuildAdd(builder
, wg_offset_dw
[buffer
], tmp
, "");
3240 offset
[buffer
] = LLVMBuildShl(builder
, tmp
, LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
3243 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
3244 struct radv_shader_output_values outputs
[AC_LLVM_MAX_OUTPUTS
];
3245 unsigned noutput
= 0;
3246 unsigned out_idx
= 0;
3248 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
3249 unsigned output_usage_mask
=
3250 ctx
->shader_info
->gs
.output_usage_mask
[i
];
3251 uint8_t output_stream
=
3252 output_stream
= ctx
->shader_info
->gs
.output_streams
[i
];
3254 if (!(ctx
->output_mask
& (1ull << i
)) ||
3255 output_stream
!= stream
)
3258 outputs
[noutput
].slot_name
= i
;
3259 outputs
[noutput
].slot_index
= i
== VARYING_SLOT_CLIP_DIST1
;
3260 outputs
[noutput
].usage_mask
= output_usage_mask
;
3262 int length
= util_last_bit(output_usage_mask
);
3264 for (unsigned j
= 0; j
< length
; j
++, out_idx
++) {
3265 if (!(output_usage_mask
& (1 << j
)))
3268 tmp
= ac_build_gep0(&ctx
->ac
, vertexptr
,
3269 LLVMConstInt(ctx
->ac
.i32
, out_idx
, false));
3270 outputs
[noutput
].values
[j
] = LLVMBuildLoad(builder
, tmp
, "");
3273 for (unsigned j
= length
; j
< 4; j
++)
3274 outputs
[noutput
].values
[j
] = LLVMGetUndef(ctx
->ac
.f32
);
3279 for (unsigned i
= 0; i
< noutput
; i
++) {
3280 struct radv_stream_output
*output
=
3281 radv_get_stream_output_by_loc(so
, outputs
[i
].slot_name
);
3284 output
->stream
!= stream
)
3287 struct radv_shader_output_values out
= {};
3289 for (unsigned j
= 0; j
< 4; j
++) {
3290 out
.values
[j
] = outputs
[i
].values
[j
];
3293 radv_emit_stream_output(ctx
, so_buffer
, offset
, output
, &out
);
3296 for (unsigned i
= 0; i
< so
->num_outputs
; ++i
) {
3297 struct radv_stream_output
*output
=
3298 &ctx
->shader_info
->so
.outputs
[i
];
3300 if (stream
!= output
->stream
)
3303 struct radv_shader_output_values out
= {};
3305 for (unsigned comp
= 0; comp
< 4; comp
++) {
3306 if (!(output
->component_mask
& (1 << comp
)))
3309 tmp
= ac_build_gep0(&ctx
->ac
, vertexptr
,
3310 LLVMConstInt(ctx
->ac
.i32
, 4 * i
+ comp
, false));
3311 out
.values
[comp
] = LLVMBuildLoad(builder
, tmp
, "");
3314 radv_emit_stream_output(ctx
, so_buffer
, offset
, output
, &out
);
3319 struct ngg_streamout
{
3320 LLVMValueRef num_vertices
;
3322 /* per-thread data */
3323 LLVMValueRef prim_enable
[4]; /* i1 per stream */
3324 LLVMValueRef vertices
[3]; /* [N x i32] addrspace(LDS)* */
3327 LLVMValueRef emit
[4]; /* per-stream emitted primitives (only valid for used streams) */
3331 * Build streamout logic.
3333 * Implies a barrier.
3335 * Writes number of emitted primitives to gs_ngg_scratch[4:7].
3337 * Clobbers gs_ngg_scratch[8:].
3339 static void build_streamout(struct radv_shader_context
*ctx
,
3340 struct ngg_streamout
*nggso
)
3342 struct radv_streamout_info
*so
= &ctx
->shader_info
->so
;
3343 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3344 LLVMValueRef buf_ptr
= ctx
->streamout_buffers
;
3345 LLVMValueRef tid
= get_thread_id_in_tg(ctx
);
3346 LLVMValueRef cond
, tmp
, tmp2
;
3347 LLVMValueRef i32_2
= LLVMConstInt(ctx
->ac
.i32
, 2, false);
3348 LLVMValueRef i32_4
= LLVMConstInt(ctx
->ac
.i32
, 4, false);
3349 LLVMValueRef i32_8
= LLVMConstInt(ctx
->ac
.i32
, 8, false);
3350 LLVMValueRef so_buffer
[4] = {};
3351 unsigned max_num_vertices
= 1 + (nggso
->vertices
[1] ? 1 : 0) +
3352 (nggso
->vertices
[2] ? 1 : 0);
3353 LLVMValueRef prim_stride_dw
[4] = {};
3354 LLVMValueRef prim_stride_dw_vgpr
= LLVMGetUndef(ctx
->ac
.i32
);
3355 int stream_for_buffer
[4] = { -1, -1, -1, -1 };
3356 unsigned bufmask_for_stream
[4] = {};
3357 bool isgs
= ctx
->stage
== MESA_SHADER_GEOMETRY
;
3358 unsigned scratch_emit_base
= isgs
? 4 : 0;
3359 LLVMValueRef scratch_emit_basev
= isgs
? i32_4
: ctx
->ac
.i32_0
;
3360 unsigned scratch_offset_base
= isgs
? 8 : 4;
3361 LLVMValueRef scratch_offset_basev
= isgs
? i32_8
: i32_4
;
3363 ac_llvm_add_target_dep_function_attr(ctx
->main_function
,
3364 "amdgpu-gds-size", 256);
3366 /* Determine the mapping of streamout buffers to vertex streams. */
3367 for (unsigned i
= 0; i
< so
->num_outputs
; ++i
) {
3368 unsigned buf
= so
->outputs
[i
].buffer
;
3369 unsigned stream
= so
->outputs
[i
].stream
;
3370 assert(stream_for_buffer
[buf
] < 0 || stream_for_buffer
[buf
] == stream
);
3371 stream_for_buffer
[buf
] = stream
;
3372 bufmask_for_stream
[stream
] |= 1 << buf
;
3375 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
3376 if (stream_for_buffer
[buffer
] == -1)
3379 assert(so
->strides
[buffer
]);
3381 LLVMValueRef stride_for_buffer
=
3382 LLVMConstInt(ctx
->ac
.i32
, so
->strides
[buffer
], false);
3383 prim_stride_dw
[buffer
] =
3384 LLVMBuildMul(builder
, stride_for_buffer
,
3385 nggso
->num_vertices
, "");
3386 prim_stride_dw_vgpr
= ac_build_writelane(
3387 &ctx
->ac
, prim_stride_dw_vgpr
, prim_stride_dw
[buffer
],
3388 LLVMConstInt(ctx
->ac
.i32
, buffer
, false));
3390 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, buffer
, false);
3391 so_buffer
[buffer
] = ac_build_load_to_sgpr(&ctx
->ac
, buf_ptr
,
3395 cond
= LLVMBuildICmp(builder
, LLVMIntEQ
, get_wave_id_in_tg(ctx
), ctx
->ac
.i32_0
, "");
3396 ac_build_ifcc(&ctx
->ac
, cond
, 5200);
3398 LLVMTypeRef gdsptr
= LLVMPointerType(ctx
->ac
.i32
, AC_ADDR_SPACE_GDS
);
3399 LLVMValueRef gdsbase
= LLVMBuildIntToPtr(builder
, ctx
->ac
.i32_0
, gdsptr
, "");
3401 /* Advance the streamout offsets in GDS. */
3402 LLVMValueRef offsets_vgpr
= ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.i32
, "");
3403 LLVMValueRef generated_by_stream_vgpr
= ac_build_alloca_undef(&ctx
->ac
, ctx
->ac
.i32
, "");
3405 cond
= LLVMBuildICmp(builder
, LLVMIntULT
, ac_get_thread_id(&ctx
->ac
), i32_4
, "");
3406 ac_build_ifcc(&ctx
->ac
, cond
, 5210);
3408 /* Fetch the number of generated primitives and store
3409 * it in GDS for later use.
3412 tmp
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, tid
);
3413 tmp
= LLVMBuildLoad(builder
, tmp
, "");
3415 tmp
= ac_build_writelane(&ctx
->ac
, ctx
->ac
.i32_0
,
3416 ngg_get_prim_cnt(ctx
), ctx
->ac
.i32_0
);
3418 LLVMBuildStore(builder
, tmp
, generated_by_stream_vgpr
);
3420 unsigned swizzle
[4];
3421 int unused_stream
= -1;
3422 for (unsigned stream
= 0; stream
< 4; ++stream
) {
3423 if (!ctx
->shader_info
->gs
.num_stream_output_components
[stream
]) {
3424 unused_stream
= stream
;
3428 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
3429 if (stream_for_buffer
[buffer
] >= 0) {
3430 swizzle
[buffer
] = stream_for_buffer
[buffer
];
3432 assert(unused_stream
>= 0);
3433 swizzle
[buffer
] = unused_stream
;
3437 tmp
= ac_build_quad_swizzle(&ctx
->ac
, tmp
,
3438 swizzle
[0], swizzle
[1], swizzle
[2], swizzle
[3]);
3439 tmp
= LLVMBuildMul(builder
, tmp
, prim_stride_dw_vgpr
, "");
3441 LLVMValueRef args
[] = {
3442 LLVMBuildIntToPtr(builder
, ngg_get_ordered_id(ctx
), gdsptr
, ""),
3444 ctx
->ac
.i32_0
, // ordering
3445 ctx
->ac
.i32_0
, // scope
3446 ctx
->ac
.i1false
, // isVolatile
3447 LLVMConstInt(ctx
->ac
.i32
, 4 << 24, false), // OA index
3448 ctx
->ac
.i1true
, // wave release
3449 ctx
->ac
.i1true
, // wave done
3452 tmp
= ac_build_intrinsic(&ctx
->ac
, "llvm.amdgcn.ds.ordered.add",
3453 ctx
->ac
.i32
, args
, ARRAY_SIZE(args
), 0);
3455 /* Keep offsets in a VGPR for quick retrieval via readlane by
3456 * the first wave for bounds checking, and also store in LDS
3457 * for retrieval by all waves later. */
3458 LLVMBuildStore(builder
, tmp
, offsets_vgpr
);
3460 tmp2
= LLVMBuildAdd(builder
, ac_get_thread_id(&ctx
->ac
),
3461 scratch_offset_basev
, "");
3462 tmp2
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, tmp2
);
3463 LLVMBuildStore(builder
, tmp
, tmp2
);
3465 ac_build_endif(&ctx
->ac
, 5210);
3467 /* Determine the max emit per buffer. This is done via the SALU, in part
3468 * because LLVM can't generate divide-by-multiply if we try to do this
3469 * via VALU with one lane per buffer.
3471 LLVMValueRef max_emit
[4] = {};
3472 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
3473 if (stream_for_buffer
[buffer
] == -1)
3476 /* Compute the streamout buffer size in DWORD. */
3477 LLVMValueRef bufsize_dw
=
3478 LLVMBuildLShr(builder
,
3479 LLVMBuildExtractElement(builder
, so_buffer
[buffer
], i32_2
, ""),
3482 /* Load the streamout buffer offset from GDS. */
3483 tmp
= LLVMBuildLoad(builder
, offsets_vgpr
, "");
3484 LLVMValueRef offset_dw
=
3485 ac_build_readlane(&ctx
->ac
, tmp
,
3486 LLVMConstInt(ctx
->ac
.i32
, buffer
, false));
3488 /* Compute the remaining size to emit. */
3489 LLVMValueRef remaining_dw
=
3490 LLVMBuildSub(builder
, bufsize_dw
, offset_dw
, "");
3491 tmp
= LLVMBuildUDiv(builder
, remaining_dw
,
3492 prim_stride_dw
[buffer
], "");
3494 cond
= LLVMBuildICmp(builder
, LLVMIntULT
,
3495 bufsize_dw
, offset_dw
, "");
3496 max_emit
[buffer
] = LLVMBuildSelect(builder
, cond
,
3497 ctx
->ac
.i32_0
, tmp
, "");
3500 /* Determine the number of emitted primitives per stream and fixup the
3501 * GDS counter if necessary.
3503 * This is complicated by the fact that a single stream can emit to
3504 * multiple buffers (but luckily not vice versa).
3506 LLVMValueRef emit_vgpr
= ctx
->ac
.i32_0
;
3508 for (unsigned stream
= 0; stream
< 4; ++stream
) {
3509 if (!ctx
->shader_info
->gs
.num_stream_output_components
[stream
])
3512 /* Load the number of generated primitives from GDS and
3513 * determine that number for the given stream.
3515 tmp
= LLVMBuildLoad(builder
, generated_by_stream_vgpr
, "");
3516 LLVMValueRef generated
=
3517 ac_build_readlane(&ctx
->ac
, tmp
,
3518 LLVMConstInt(ctx
->ac
.i32
, stream
, false));
3521 /* Compute the number of emitted primitives. */
3522 LLVMValueRef emit
= generated
;
3523 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
3524 if (stream_for_buffer
[buffer
] == stream
)
3525 emit
= ac_build_umin(&ctx
->ac
, emit
, max_emit
[buffer
]);
3528 /* Store the number of emitted primitives for that
3531 emit_vgpr
= ac_build_writelane(&ctx
->ac
, emit_vgpr
, emit
,
3532 LLVMConstInt(ctx
->ac
.i32
, stream
, false));
3534 /* Fixup the offset using a plain GDS atomic if we overflowed. */
3535 cond
= LLVMBuildICmp(builder
, LLVMIntULT
, emit
, generated
, "");
3536 ac_build_ifcc(&ctx
->ac
, cond
, 5221); /* scalar branch */
3537 tmp
= LLVMBuildLShr(builder
,
3538 LLVMConstInt(ctx
->ac
.i32
, bufmask_for_stream
[stream
], false),
3539 ac_get_thread_id(&ctx
->ac
), "");
3540 tmp
= LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
3541 ac_build_ifcc(&ctx
->ac
, tmp
, 5222);
3543 tmp
= LLVMBuildSub(builder
, generated
, emit
, "");
3544 tmp
= LLVMBuildMul(builder
, tmp
, prim_stride_dw_vgpr
, "");
3545 tmp2
= LLVMBuildGEP(builder
, gdsbase
, &tid
, 1, "");
3546 LLVMBuildAtomicRMW(builder
, LLVMAtomicRMWBinOpSub
, tmp2
, tmp
,
3547 LLVMAtomicOrderingMonotonic
, false);
3549 ac_build_endif(&ctx
->ac
, 5222);
3550 ac_build_endif(&ctx
->ac
, 5221);
3553 /* Store the number of emitted primitives to LDS for later use. */
3554 cond
= LLVMBuildICmp(builder
, LLVMIntULT
, ac_get_thread_id(&ctx
->ac
), i32_4
, "");
3555 ac_build_ifcc(&ctx
->ac
, cond
, 5225);
3557 tmp
= LLVMBuildAdd(builder
, ac_get_thread_id(&ctx
->ac
),
3558 scratch_emit_basev
, "");
3559 tmp
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, tmp
);
3560 LLVMBuildStore(builder
, emit_vgpr
, tmp
);
3562 ac_build_endif(&ctx
->ac
, 5225);
3564 ac_build_endif(&ctx
->ac
, 5200);
3566 /* Determine the workgroup-relative per-thread / primitive offset into
3567 * the streamout buffers */
3568 struct ac_wg_scan primemit_scan
[4] = {};
3571 for (unsigned stream
= 0; stream
< 4; ++stream
) {
3572 if (!ctx
->shader_info
->gs
.num_stream_output_components
[stream
])
3575 primemit_scan
[stream
].enable_exclusive
= true;
3576 primemit_scan
[stream
].op
= nir_op_iadd
;
3577 primemit_scan
[stream
].src
= nggso
->prim_enable
[stream
];
3578 primemit_scan
[stream
].scratch
=
3579 ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
,
3580 LLVMConstInt(ctx
->ac
.i32
, 12 + 8 * stream
, false));
3581 primemit_scan
[stream
].waveidx
= get_wave_id_in_tg(ctx
);
3582 primemit_scan
[stream
].numwaves
= get_tgsize(ctx
);
3583 primemit_scan
[stream
].maxwaves
= 8;
3584 ac_build_wg_scan_top(&ctx
->ac
, &primemit_scan
[stream
]);
3588 ac_build_s_barrier(&ctx
->ac
);
3590 /* Fetch the per-buffer offsets and per-stream emit counts in all waves. */
3591 LLVMValueRef wgoffset_dw
[4] = {};
3594 LLVMValueRef scratch_vgpr
;
3596 tmp
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, ac_get_thread_id(&ctx
->ac
));
3597 scratch_vgpr
= LLVMBuildLoad(builder
, tmp
, "");
3599 for (unsigned buffer
= 0; buffer
< 4; ++buffer
) {
3600 if (stream_for_buffer
[buffer
] >= 0) {
3601 wgoffset_dw
[buffer
] = ac_build_readlane(
3602 &ctx
->ac
, scratch_vgpr
,
3603 LLVMConstInt(ctx
->ac
.i32
, scratch_offset_base
+ buffer
, false));
3607 for (unsigned stream
= 0; stream
< 4; ++stream
) {
3608 if (ctx
->shader_info
->gs
.num_stream_output_components
[stream
]) {
3609 nggso
->emit
[stream
] = ac_build_readlane(
3610 &ctx
->ac
, scratch_vgpr
,
3611 LLVMConstInt(ctx
->ac
.i32
, scratch_emit_base
+ stream
, false));
3616 /* Write out primitive data */
3617 for (unsigned stream
= 0; stream
< 4; ++stream
) {
3618 if (!ctx
->shader_info
->gs
.num_stream_output_components
[stream
])
3622 ac_build_wg_scan_bottom(&ctx
->ac
, &primemit_scan
[stream
]);
3624 primemit_scan
[stream
].result_exclusive
= tid
;
3627 cond
= LLVMBuildICmp(builder
, LLVMIntULT
,
3628 primemit_scan
[stream
].result_exclusive
,
3629 nggso
->emit
[stream
], "");
3630 cond
= LLVMBuildAnd(builder
, cond
, nggso
->prim_enable
[stream
], "");
3631 ac_build_ifcc(&ctx
->ac
, cond
, 5240);
3633 LLVMValueRef offset_vtx
=
3634 LLVMBuildMul(builder
, primemit_scan
[stream
].result_exclusive
,
3635 nggso
->num_vertices
, "");
3637 for (unsigned i
= 0; i
< max_num_vertices
; ++i
) {
3638 cond
= LLVMBuildICmp(builder
, LLVMIntULT
,
3639 LLVMConstInt(ctx
->ac
.i32
, i
, false),
3640 nggso
->num_vertices
, "");
3641 ac_build_ifcc(&ctx
->ac
, cond
, 5241);
3642 build_streamout_vertex(ctx
, so_buffer
, wgoffset_dw
,
3643 stream
, offset_vtx
, nggso
->vertices
[i
]);
3644 ac_build_endif(&ctx
->ac
, 5241);
3645 offset_vtx
= LLVMBuildAdd(builder
, offset_vtx
, ctx
->ac
.i32_1
, "");
3648 ac_build_endif(&ctx
->ac
, 5240);
3652 static unsigned ngg_nogs_vertex_size(struct radv_shader_context
*ctx
)
3654 unsigned lds_vertex_size
= 0;
3656 if (ctx
->shader_info
->so
.num_outputs
)
3657 lds_vertex_size
= 4 * ctx
->shader_info
->so
.num_outputs
+ 1;
3659 return lds_vertex_size
;
3663 * Returns an `[N x i32] addrspace(LDS)*` pointing at contiguous LDS storage
3664 * for the vertex outputs.
3666 static LLVMValueRef
ngg_nogs_vertex_ptr(struct radv_shader_context
*ctx
,
3669 /* The extra dword is used to avoid LDS bank conflicts. */
3670 unsigned vertex_size
= ngg_nogs_vertex_size(ctx
);
3671 LLVMTypeRef ai32
= LLVMArrayType(ctx
->ac
.i32
, vertex_size
);
3672 LLVMTypeRef pai32
= LLVMPointerType(ai32
, AC_ADDR_SPACE_LDS
);
3673 LLVMValueRef tmp
= LLVMBuildBitCast(ctx
->ac
.builder
, ctx
->esgs_ring
, pai32
, "");
3674 return LLVMBuildGEP(ctx
->ac
.builder
, tmp
, &vtxid
, 1, "");
3678 handle_ngg_outputs_post_1(struct radv_shader_context
*ctx
)
3680 struct radv_streamout_info
*so
= &ctx
->shader_info
->so
;
3681 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3682 LLVMValueRef vertex_ptr
= NULL
;
3683 LLVMValueRef tmp
, tmp2
;
3685 assert((ctx
->stage
== MESA_SHADER_VERTEX
||
3686 ctx
->stage
== MESA_SHADER_TESS_EVAL
) && !ctx
->is_gs_copy_shader
);
3688 if (!ctx
->shader_info
->so
.num_outputs
)
3691 vertex_ptr
= ngg_nogs_vertex_ptr(ctx
, get_thread_id_in_tg(ctx
));
3693 for (unsigned i
= 0; i
< so
->num_outputs
; ++i
) {
3694 struct radv_stream_output
*output
=
3695 &ctx
->shader_info
->so
.outputs
[i
];
3697 unsigned loc
= output
->location
;
3699 for (unsigned comp
= 0; comp
< 4; comp
++) {
3700 if (!(output
->component_mask
& (1 << comp
)))
3703 tmp
= ac_build_gep0(&ctx
->ac
, vertex_ptr
,
3704 LLVMConstInt(ctx
->ac
.i32
, 4 * i
+ comp
, false));
3705 tmp2
= LLVMBuildLoad(builder
,
3706 ctx
->abi
.outputs
[4 * loc
+ comp
], "");
3707 tmp2
= ac_to_integer(&ctx
->ac
, tmp2
);
3708 LLVMBuildStore(builder
, tmp2
, tmp
);
3714 handle_ngg_outputs_post_2(struct radv_shader_context
*ctx
)
3716 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3719 assert((ctx
->stage
== MESA_SHADER_VERTEX
||
3720 ctx
->stage
== MESA_SHADER_TESS_EVAL
) && !ctx
->is_gs_copy_shader
);
3722 LLVMValueRef prims_in_wave
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 8, 8);
3723 LLVMValueRef vtx_in_wave
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 0, 8);
3724 LLVMValueRef is_gs_thread
= LLVMBuildICmp(builder
, LLVMIntULT
,
3725 ac_get_thread_id(&ctx
->ac
), prims_in_wave
, "");
3726 LLVMValueRef is_es_thread
= LLVMBuildICmp(builder
, LLVMIntULT
,
3727 ac_get_thread_id(&ctx
->ac
), vtx_in_wave
, "");
3728 LLVMValueRef vtxindex
[] = {
3729 ac_unpack_param(&ctx
->ac
, ctx
->gs_vtx_offset
[0], 0, 16),
3730 ac_unpack_param(&ctx
->ac
, ctx
->gs_vtx_offset
[0], 16, 16),
3731 ac_unpack_param(&ctx
->ac
, ctx
->gs_vtx_offset
[2], 0, 16),
3734 /* Determine the number of vertices per primitive. */
3735 unsigned num_vertices
;
3736 LLVMValueRef num_vertices_val
;
3738 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
3739 LLVMValueRef outprim_val
=
3740 LLVMConstInt(ctx
->ac
.i32
,
3741 ctx
->options
->key
.vs
.outprim
, false);
3742 num_vertices_val
= LLVMBuildAdd(builder
, outprim_val
,
3744 num_vertices
= 3; /* TODO: optimize for points & lines */
3746 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
3748 if (ctx
->shader
->info
.tess
.point_mode
)
3750 else if (ctx
->shader
->info
.tess
.primitive_mode
== GL_ISOLINES
)
3755 num_vertices_val
= LLVMConstInt(ctx
->ac
.i32
, num_vertices
, false);
3759 if (ctx
->shader_info
->so
.num_outputs
) {
3760 struct ngg_streamout nggso
= {};
3762 nggso
.num_vertices
= num_vertices_val
;
3763 nggso
.prim_enable
[0] = is_gs_thread
;
3765 for (unsigned i
= 0; i
< num_vertices
; ++i
)
3766 nggso
.vertices
[i
] = ngg_nogs_vertex_ptr(ctx
, vtxindex
[i
]);
3768 build_streamout(ctx
, &nggso
);
3771 /* Copy Primitive IDs from GS threads to the LDS address corresponding
3772 * to the ES thread of the provoking vertex.
3774 if (ctx
->stage
== MESA_SHADER_VERTEX
&&
3775 ctx
->options
->key
.vs_common_out
.export_prim_id
) {
3776 if (ctx
->shader_info
->so
.num_outputs
)
3777 ac_build_s_barrier(&ctx
->ac
);
3779 ac_build_ifcc(&ctx
->ac
, is_gs_thread
, 5400);
3780 /* Extract the PROVOKING_VTX_INDEX field. */
3781 LLVMValueRef provoking_vtx_in_prim
=
3782 LLVMConstInt(ctx
->ac
.i32
, 0, false);
3784 /* provoking_vtx_index = vtxindex[provoking_vtx_in_prim]; */
3785 LLVMValueRef indices
= ac_build_gather_values(&ctx
->ac
, vtxindex
, 3);
3786 LLVMValueRef provoking_vtx_index
=
3787 LLVMBuildExtractElement(builder
, indices
, provoking_vtx_in_prim
, "");
3789 LLVMBuildStore(builder
, ctx
->abi
.gs_prim_id
,
3790 ac_build_gep0(&ctx
->ac
, ctx
->esgs_ring
, provoking_vtx_index
));
3791 ac_build_endif(&ctx
->ac
, 5400);
3794 /* TODO: primitive culling */
3796 build_sendmsg_gs_alloc_req(ctx
, ngg_get_vtx_cnt(ctx
), ngg_get_prim_cnt(ctx
));
3798 /* TODO: streamout queries */
3799 /* Export primitive data to the index buffer. Format is:
3800 * - bits 0..8: index 0
3801 * - bit 9: edge flag 0
3802 * - bits 10..18: index 1
3803 * - bit 19: edge flag 1
3804 * - bits 20..28: index 2
3805 * - bit 29: edge flag 2
3806 * - bit 31: null primitive (skip)
3808 * For the first version, we will always build up all three indices
3809 * independent of the primitive type. The additional garbage data
3812 * TODO: culling depends on the primitive type, so can have some
3815 ac_build_ifcc(&ctx
->ac
, is_gs_thread
, 6001);
3817 struct ngg_prim prim
= {};
3819 prim
.num_vertices
= num_vertices
;
3820 prim
.isnull
= ctx
->ac
.i1false
;
3821 prim
.swap
= ctx
->ac
.i1false
;
3822 memcpy(prim
.index
, vtxindex
, sizeof(vtxindex
[0]) * 3);
3824 for (unsigned i
= 0; i
< num_vertices
; ++i
) {
3825 tmp
= LLVMBuildLShr(builder
, ctx
->abi
.gs_invocation_id
,
3826 LLVMConstInt(ctx
->ac
.i32
, 8 + i
, false), "");
3827 prim
.edgeflag
[i
] = LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
3830 build_export_prim(ctx
, &prim
);
3832 ac_build_endif(&ctx
->ac
, 6001);
3834 /* Export per-vertex data (positions and parameters). */
3835 ac_build_ifcc(&ctx
->ac
, is_es_thread
, 6002);
3837 struct radv_vs_output_info
*outinfo
=
3838 ctx
->stage
== MESA_SHADER_TESS_EVAL
? &ctx
->shader_info
->tes
.outinfo
: &ctx
->shader_info
->vs
.outinfo
;
3840 /* Exporting the primitive ID is handled below. */
3841 /* TODO: use the new VS export path */
3842 handle_vs_outputs_post(ctx
, false,
3843 ctx
->options
->key
.vs_common_out
.export_clip_dists
,
3846 if (ctx
->options
->key
.vs_common_out
.export_prim_id
) {
3847 unsigned param_count
= outinfo
->param_exports
;
3848 LLVMValueRef values
[4];
3850 if (ctx
->stage
== MESA_SHADER_VERTEX
) {
3851 /* Wait for GS stores to finish. */
3852 ac_build_s_barrier(&ctx
->ac
);
3854 tmp
= ac_build_gep0(&ctx
->ac
, ctx
->esgs_ring
,
3855 get_thread_id_in_tg(ctx
));
3856 values
[0] = LLVMBuildLoad(builder
, tmp
, "");
3858 assert(ctx
->stage
== MESA_SHADER_TESS_EVAL
);
3859 values
[0] = ctx
->abi
.tes_patch_id
;
3862 values
[0] = ac_to_float(&ctx
->ac
, values
[0]);
3863 for (unsigned j
= 1; j
< 4; j
++)
3864 values
[j
] = ctx
->ac
.f32_0
;
3866 radv_export_param(ctx
, param_count
, values
, 0x1);
3868 outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
] = param_count
++;
3869 outinfo
->param_exports
= param_count
;
3872 ac_build_endif(&ctx
->ac
, 6002);
3875 static void gfx10_ngg_gs_emit_prologue(struct radv_shader_context
*ctx
)
3877 /* Zero out the part of LDS scratch that is used to accumulate the
3878 * per-stream generated primitive count.
3880 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3881 LLVMValueRef scratchptr
= ctx
->gs_ngg_scratch
;
3882 LLVMValueRef tid
= get_thread_id_in_tg(ctx
);
3883 LLVMBasicBlockRef merge_block
;
3886 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
->ac
.builder
));
3887 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
3888 merge_block
= LLVMAppendBasicBlockInContext(ctx
->ac
.context
, fn
, "");
3890 cond
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
3891 LLVMBuildCondBr(ctx
->ac
.builder
, cond
, then_block
, merge_block
);
3892 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, then_block
);
3894 LLVMValueRef ptr
= ac_build_gep0(&ctx
->ac
, scratchptr
, tid
);
3895 LLVMBuildStore(builder
, ctx
->ac
.i32_0
, ptr
);
3897 LLVMBuildBr(ctx
->ac
.builder
, merge_block
);
3898 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, merge_block
);
3900 ac_build_s_barrier(&ctx
->ac
);
3903 static void gfx10_ngg_gs_emit_epilogue_1(struct radv_shader_context
*ctx
)
3905 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3906 LLVMValueRef i8_0
= LLVMConstInt(ctx
->ac
.i8
, 0, false);
3909 /* Zero out remaining (non-emitted) primitive flags.
3911 * Note: Alternatively, we could pass the relevant gs_next_vertex to
3912 * the emit threads via LDS. This is likely worse in the expected
3913 * typical case where each GS thread emits the full set of
3916 for (unsigned stream
= 0; stream
< 4; ++stream
) {
3917 unsigned num_components
;
3920 ctx
->shader_info
->gs
.num_stream_output_components
[stream
];
3921 if (!num_components
)
3924 const LLVMValueRef gsthread
= get_thread_id_in_tg(ctx
);
3926 ac_build_bgnloop(&ctx
->ac
, 5100);
3928 const LLVMValueRef vertexidx
=
3929 LLVMBuildLoad(builder
, ctx
->gs_next_vertex
[stream
], "");
3930 tmp
= LLVMBuildICmp(builder
, LLVMIntUGE
, vertexidx
,
3931 LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.gs
.vertices_out
, false), "");
3932 ac_build_ifcc(&ctx
->ac
, tmp
, 5101);
3933 ac_build_break(&ctx
->ac
);
3934 ac_build_endif(&ctx
->ac
, 5101);
3936 tmp
= LLVMBuildAdd(builder
, vertexidx
, ctx
->ac
.i32_1
, "");
3937 LLVMBuildStore(builder
, tmp
, ctx
->gs_next_vertex
[stream
]);
3939 tmp
= ngg_gs_emit_vertex_ptr(ctx
, gsthread
, vertexidx
);
3940 LLVMValueRef gep_idx
[3] = {
3941 ctx
->ac
.i32_0
, /* implied C-style array */
3942 ctx
->ac
.i32_1
, /* second entry of struct */
3943 LLVMConstInt(ctx
->ac
.i32
, stream
, false),
3945 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
3946 LLVMBuildStore(builder
, i8_0
, tmp
);
3948 ac_build_endloop(&ctx
->ac
, 5100);
3951 /* Accumulate generated primitives counts across the entire threadgroup. */
3952 for (unsigned stream
= 0; stream
< 4; ++stream
) {
3953 unsigned num_components
;
3956 ctx
->shader_info
->gs
.num_stream_output_components
[stream
];
3957 if (!num_components
)
3960 LLVMValueRef numprims
=
3961 LLVMBuildLoad(builder
, ctx
->gs_generated_prims
[stream
], "");
3962 numprims
= ac_build_reduce(&ctx
->ac
, numprims
, nir_op_iadd
, ctx
->ac
.wave_size
);
3964 tmp
= LLVMBuildICmp(builder
, LLVMIntEQ
, ac_get_thread_id(&ctx
->ac
), ctx
->ac
.i32_0
, "");
3965 ac_build_ifcc(&ctx
->ac
, tmp
, 5105);
3967 LLVMBuildAtomicRMW(builder
, LLVMAtomicRMWBinOpAdd
,
3968 ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
,
3969 LLVMConstInt(ctx
->ac
.i32
, stream
, false)),
3970 numprims
, LLVMAtomicOrderingMonotonic
, false);
3972 ac_build_endif(&ctx
->ac
, 5105);
3976 static void gfx10_ngg_gs_emit_epilogue_2(struct radv_shader_context
*ctx
)
3978 const unsigned verts_per_prim
= si_conv_gl_prim_to_vertices(ctx
->shader
->info
.gs
.output_primitive
);
3979 LLVMBuilderRef builder
= ctx
->ac
.builder
;
3980 LLVMValueRef tmp
, tmp2
;
3982 ac_build_s_barrier(&ctx
->ac
);
3984 const LLVMValueRef tid
= get_thread_id_in_tg(ctx
);
3985 LLVMValueRef num_emit_threads
= ngg_get_prim_cnt(ctx
);
3988 if (ctx
->shader_info
->so
.num_outputs
) {
3989 struct ngg_streamout nggso
= {};
3991 nggso
.num_vertices
= LLVMConstInt(ctx
->ac
.i32
, verts_per_prim
, false);
3993 LLVMValueRef vertexptr
= ngg_gs_vertex_ptr(ctx
, tid
);
3994 for (unsigned stream
= 0; stream
< 4; ++stream
) {
3995 if (!ctx
->shader_info
->gs
.num_stream_output_components
[stream
])
3998 LLVMValueRef gep_idx
[3] = {
3999 ctx
->ac
.i32_0
, /* implicit C-style array */
4000 ctx
->ac
.i32_1
, /* second value of struct */
4001 LLVMConstInt(ctx
->ac
.i32
, stream
, false),
4003 tmp
= LLVMBuildGEP(builder
, vertexptr
, gep_idx
, 3, "");
4004 tmp
= LLVMBuildLoad(builder
, tmp
, "");
4005 tmp
= LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
4006 tmp2
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, num_emit_threads
, "");
4007 nggso
.prim_enable
[stream
] = LLVMBuildAnd(builder
, tmp
, tmp2
, "");
4010 for (unsigned i
= 0; i
< verts_per_prim
; ++i
) {
4011 tmp
= LLVMBuildSub(builder
, tid
,
4012 LLVMConstInt(ctx
->ac
.i32
, verts_per_prim
- i
- 1, false), "");
4013 tmp
= ngg_gs_vertex_ptr(ctx
, tmp
);
4014 nggso
.vertices
[i
] = ac_build_gep0(&ctx
->ac
, tmp
, ctx
->ac
.i32_0
);
4017 build_streamout(ctx
, &nggso
);
4022 /* Determine vertex liveness. */
4023 LLVMValueRef vertliveptr
= ac_build_alloca(&ctx
->ac
, ctx
->ac
.i1
, "vertexlive");
4025 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, num_emit_threads
, "");
4026 ac_build_ifcc(&ctx
->ac
, tmp
, 5120);
4028 for (unsigned i
= 0; i
< verts_per_prim
; ++i
) {
4029 const LLVMValueRef primidx
=
4030 LLVMBuildAdd(builder
, tid
,
4031 LLVMConstInt(ctx
->ac
.i32
, i
, false), "");
4034 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, primidx
, num_emit_threads
, "");
4035 ac_build_ifcc(&ctx
->ac
, tmp
, 5121 + i
);
4038 /* Load primitive liveness */
4039 tmp
= ngg_gs_vertex_ptr(ctx
, primidx
);
4040 LLVMValueRef gep_idx
[3] = {
4041 ctx
->ac
.i32_0
, /* implicit C-style array */
4042 ctx
->ac
.i32_1
, /* second value of struct */
4043 ctx
->ac
.i32_0
, /* stream 0 */
4045 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
4046 tmp
= LLVMBuildLoad(builder
, tmp
, "");
4047 const LLVMValueRef primlive
=
4048 LLVMBuildTrunc(builder
, tmp
, ctx
->ac
.i1
, "");
4050 tmp
= LLVMBuildLoad(builder
, vertliveptr
, "");
4051 tmp
= LLVMBuildOr(builder
, tmp
, primlive
, ""),
4052 LLVMBuildStore(builder
, tmp
, vertliveptr
);
4055 ac_build_endif(&ctx
->ac
, 5121 + i
);
4058 ac_build_endif(&ctx
->ac
, 5120);
4060 /* Inclusive scan addition across the current wave. */
4061 LLVMValueRef vertlive
= LLVMBuildLoad(builder
, vertliveptr
, "");
4062 struct ac_wg_scan vertlive_scan
= {};
4063 vertlive_scan
.op
= nir_op_iadd
;
4064 vertlive_scan
.enable_reduce
= true;
4065 vertlive_scan
.enable_exclusive
= true;
4066 vertlive_scan
.src
= vertlive
;
4067 vertlive_scan
.scratch
= ac_build_gep0(&ctx
->ac
, ctx
->gs_ngg_scratch
, ctx
->ac
.i32_0
);
4068 vertlive_scan
.waveidx
= get_wave_id_in_tg(ctx
);
4069 vertlive_scan
.numwaves
= get_tgsize(ctx
);
4070 vertlive_scan
.maxwaves
= 8;
4072 ac_build_wg_scan(&ctx
->ac
, &vertlive_scan
);
4074 /* Skip all exports (including index exports) when possible. At least on
4075 * early gfx10 revisions this is also to avoid hangs.
4077 LLVMValueRef have_exports
=
4078 LLVMBuildICmp(builder
, LLVMIntNE
, vertlive_scan
.result_reduce
, ctx
->ac
.i32_0
, "");
4080 LLVMBuildSelect(builder
, have_exports
, num_emit_threads
, ctx
->ac
.i32_0
, "");
4082 /* Allocate export space. Send this message as early as possible, to
4083 * hide the latency of the SQ <-> SPI roundtrip.
4085 * Note: We could consider compacting primitives for export as well.
4086 * PA processes 1 non-null prim / clock, but it fetches 4 DW of
4087 * prim data per clock and skips null primitives at no additional
4088 * cost. So compacting primitives can only be beneficial when
4089 * there are 4 or more contiguous null primitives in the export
4090 * (in the common case of single-dword prim exports).
4092 build_sendmsg_gs_alloc_req(ctx
, vertlive_scan
.result_reduce
, num_emit_threads
);
4094 /* Setup the reverse vertex compaction permutation. We re-use stream 1
4095 * of the primitive liveness flags, relying on the fact that each
4096 * threadgroup can have at most 256 threads. */
4097 ac_build_ifcc(&ctx
->ac
, vertlive
, 5130);
4099 tmp
= ngg_gs_vertex_ptr(ctx
, vertlive_scan
.result_exclusive
);
4100 LLVMValueRef gep_idx
[3] = {
4101 ctx
->ac
.i32_0
, /* implicit C-style array */
4102 ctx
->ac
.i32_1
, /* second value of struct */
4103 ctx
->ac
.i32_1
, /* stream 1 */
4105 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
4106 tmp2
= LLVMBuildTrunc(builder
, tid
, ctx
->ac
.i8
, "");
4107 LLVMBuildStore(builder
, tmp2
, tmp
);
4109 ac_build_endif(&ctx
->ac
, 5130);
4111 ac_build_s_barrier(&ctx
->ac
);
4113 /* Export primitive data */
4114 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, num_emit_threads
, "");
4115 ac_build_ifcc(&ctx
->ac
, tmp
, 5140);
4117 struct ngg_prim prim
= {};
4118 prim
.num_vertices
= verts_per_prim
;
4120 tmp
= ngg_gs_vertex_ptr(ctx
, tid
);
4121 LLVMValueRef gep_idx
[3] = {
4122 ctx
->ac
.i32_0
, /* implicit C-style array */
4123 ctx
->ac
.i32_1
, /* second value of struct */
4124 ctx
->ac
.i32_0
, /* primflag */
4126 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
4127 tmp
= LLVMBuildLoad(builder
, tmp
, "");
4128 prim
.isnull
= LLVMBuildICmp(builder
, LLVMIntEQ
, tmp
,
4129 LLVMConstInt(ctx
->ac
.i8
, 0, false), "");
4130 prim
.swap
= LLVMBuildICmp(builder
, LLVMIntEQ
,
4131 LLVMBuildAnd(builder
, tid
, LLVMConstInt(ctx
->ac
.i32
, 1, false), ""),
4132 LLVMConstInt(ctx
->ac
.i32
, 1, false), "");
4134 for (unsigned i
= 0; i
< verts_per_prim
; ++i
) {
4135 prim
.index
[i
] = LLVMBuildSub(builder
, vertlive_scan
.result_exclusive
,
4136 LLVMConstInt(ctx
->ac
.i32
, verts_per_prim
- i
- 1, false), "");
4137 prim
.edgeflag
[i
] = ctx
->ac
.i1false
;
4140 build_export_prim(ctx
, &prim
);
4142 ac_build_endif(&ctx
->ac
, 5140);
4144 /* Export position and parameter data */
4145 tmp
= LLVMBuildICmp(builder
, LLVMIntULT
, tid
, vertlive_scan
.result_reduce
, "");
4146 ac_build_ifcc(&ctx
->ac
, tmp
, 5145);
4148 struct radv_vs_output_info
*outinfo
= &ctx
->shader_info
->vs
.outinfo
;
4149 bool export_view_index
= ctx
->options
->key
.has_multiview_view_index
;
4150 struct radv_shader_output_values
*outputs
;
4151 unsigned noutput
= 0;
4153 /* Allocate a temporary array for the output values. */
4154 unsigned num_outputs
= util_bitcount64(ctx
->output_mask
) + export_view_index
;
4155 outputs
= calloc(num_outputs
, sizeof(outputs
[0]));
4157 memset(outinfo
->vs_output_param_offset
, AC_EXP_PARAM_UNDEFINED
,
4158 sizeof(outinfo
->vs_output_param_offset
));
4159 outinfo
->pos_exports
= 0;
4161 tmp
= ngg_gs_vertex_ptr(ctx
, tid
);
4162 LLVMValueRef gep_idx
[3] = {
4163 ctx
->ac
.i32_0
, /* implicit C-style array */
4164 ctx
->ac
.i32_1
, /* second value of struct */
4165 ctx
->ac
.i32_1
, /* stream 1: source data index */
4167 tmp
= LLVMBuildGEP(builder
, tmp
, gep_idx
, 3, "");
4168 tmp
= LLVMBuildLoad(builder
, tmp
, "");
4169 tmp
= LLVMBuildZExt(builder
, tmp
, ctx
->ac
.i32
, "");
4170 const LLVMValueRef vertexptr
= ngg_gs_vertex_ptr(ctx
, tmp
);
4172 unsigned out_idx
= 0;
4173 gep_idx
[1] = ctx
->ac
.i32_0
;
4174 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
4175 unsigned output_usage_mask
=
4176 ctx
->shader_info
->gs
.output_usage_mask
[i
];
4177 int length
= util_last_bit(output_usage_mask
);
4179 if (!(ctx
->output_mask
& (1ull << i
)))
4182 outputs
[noutput
].slot_name
= i
;
4183 outputs
[noutput
].slot_index
= i
== VARYING_SLOT_CLIP_DIST1
;
4184 outputs
[noutput
].usage_mask
= output_usage_mask
;
4186 for (unsigned j
= 0; j
< length
; j
++, out_idx
++) {
4187 if (!(output_usage_mask
& (1 << j
)))
4190 gep_idx
[2] = LLVMConstInt(ctx
->ac
.i32
, out_idx
, false);
4191 tmp
= LLVMBuildGEP(builder
, vertexptr
, gep_idx
, 3, "");
4192 tmp
= LLVMBuildLoad(builder
, tmp
, "");
4194 LLVMTypeRef type
= LLVMGetAllocatedType(ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
4195 if (ac_get_type_size(type
) == 2) {
4196 tmp
= ac_to_integer(&ctx
->ac
, tmp
);
4197 tmp
= LLVMBuildTrunc(ctx
->ac
.builder
, tmp
, ctx
->ac
.i16
, "");
4200 outputs
[noutput
].values
[j
] = ac_to_float(&ctx
->ac
, tmp
);
4203 for (unsigned j
= length
; j
< 4; j
++)
4204 outputs
[noutput
].values
[j
] = LLVMGetUndef(ctx
->ac
.f32
);
4209 /* Export ViewIndex. */
4210 if (export_view_index
) {
4211 outputs
[noutput
].slot_name
= VARYING_SLOT_LAYER
;
4212 outputs
[noutput
].slot_index
= 0;
4213 outputs
[noutput
].usage_mask
= 0x1;
4214 outputs
[noutput
].values
[0] = ac_to_float(&ctx
->ac
, ctx
->abi
.view_index
);
4215 for (unsigned j
= 1; j
< 4; j
++)
4216 outputs
[noutput
].values
[j
] = ctx
->ac
.f32_0
;
4220 radv_llvm_export_vs(ctx
, outputs
, noutput
, outinfo
,
4221 ctx
->options
->key
.vs_common_out
.export_clip_dists
);
4224 ac_build_endif(&ctx
->ac
, 5145);
4227 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context
*ctx
,
4229 LLVMValueRef
*addrs
)
4231 LLVMBuilderRef builder
= ctx
->ac
.builder
;
4233 const LLVMValueRef vertexidx
=
4234 LLVMBuildLoad(builder
, ctx
->gs_next_vertex
[stream
], "");
4236 /* If this thread has already emitted the declared maximum number of
4237 * vertices, skip the write: excessive vertex emissions are not
4238 * supposed to have any effect.
4240 const LLVMValueRef can_emit
=
4241 LLVMBuildICmp(builder
, LLVMIntULT
, vertexidx
,
4242 LLVMConstInt(ctx
->ac
.i32
, ctx
->shader
->info
.gs
.vertices_out
, false), "");
4243 ac_build_ifcc(&ctx
->ac
, can_emit
, 9001);
4245 tmp
= LLVMBuildAdd(builder
, vertexidx
, ctx
->ac
.i32_1
, "");
4246 tmp
= LLVMBuildSelect(builder
, can_emit
, tmp
, vertexidx
, "");
4247 LLVMBuildStore(builder
, tmp
, ctx
->gs_next_vertex
[stream
]);
4249 const LLVMValueRef vertexptr
=
4250 ngg_gs_emit_vertex_ptr(ctx
, get_thread_id_in_tg(ctx
), vertexidx
);
4251 unsigned out_idx
= 0;
4252 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
4253 unsigned output_usage_mask
=
4254 ctx
->shader_info
->gs
.output_usage_mask
[i
];
4255 uint8_t output_stream
=
4256 ctx
->shader_info
->gs
.output_streams
[i
];
4257 LLVMValueRef
*out_ptr
= &addrs
[i
* 4];
4258 int length
= util_last_bit(output_usage_mask
);
4260 if (!(ctx
->output_mask
& (1ull << i
)) ||
4261 output_stream
!= stream
)
4264 for (unsigned j
= 0; j
< length
; j
++, out_idx
++) {
4265 if (!(output_usage_mask
& (1 << j
)))
4268 LLVMValueRef out_val
= LLVMBuildLoad(ctx
->ac
.builder
,
4270 LLVMValueRef gep_idx
[3] = {
4271 ctx
->ac
.i32_0
, /* implied C-style array */
4272 ctx
->ac
.i32_0
, /* first entry of struct */
4273 LLVMConstInt(ctx
->ac
.i32
, out_idx
, false),
4275 LLVMValueRef ptr
= LLVMBuildGEP(builder
, vertexptr
, gep_idx
, 3, "");
4277 out_val
= ac_to_integer(&ctx
->ac
, out_val
);
4278 out_val
= LLVMBuildZExtOrBitCast(ctx
->ac
.builder
, out_val
, ctx
->ac
.i32
, "");
4280 LLVMBuildStore(builder
, out_val
, ptr
);
4283 assert(out_idx
* 4 <= ctx
->shader_info
->gs
.gsvs_vertex_size
);
4285 /* Determine and store whether this vertex completed a primitive. */
4286 const LLVMValueRef curverts
= LLVMBuildLoad(builder
, ctx
->gs_curprim_verts
[stream
], "");
4288 tmp
= LLVMConstInt(ctx
->ac
.i32
, si_conv_gl_prim_to_vertices(ctx
->shader
->info
.gs
.output_primitive
) - 1, false);
4289 const LLVMValueRef iscompleteprim
=
4290 LLVMBuildICmp(builder
, LLVMIntUGE
, curverts
, tmp
, "");
4292 tmp
= LLVMBuildAdd(builder
, curverts
, ctx
->ac
.i32_1
, "");
4293 LLVMBuildStore(builder
, tmp
, ctx
->gs_curprim_verts
[stream
]);
4295 LLVMValueRef gep_idx
[3] = {
4296 ctx
->ac
.i32_0
, /* implied C-style array */
4297 ctx
->ac
.i32_1
, /* second struct entry */
4298 LLVMConstInt(ctx
->ac
.i32
, stream
, false),
4300 const LLVMValueRef primflagptr
=
4301 LLVMBuildGEP(builder
, vertexptr
, gep_idx
, 3, "");
4303 tmp
= LLVMBuildZExt(builder
, iscompleteprim
, ctx
->ac
.i8
, "");
4304 LLVMBuildStore(builder
, tmp
, primflagptr
);
4306 tmp
= LLVMBuildLoad(builder
, ctx
->gs_generated_prims
[stream
], "");
4307 tmp
= LLVMBuildAdd(builder
, tmp
, LLVMBuildZExt(builder
, iscompleteprim
, ctx
->ac
.i32
, ""), "");
4308 LLVMBuildStore(builder
, tmp
, ctx
->gs_generated_prims
[stream
]);
4310 ac_build_endif(&ctx
->ac
, 9001);
4314 write_tess_factors(struct radv_shader_context
*ctx
)
4316 unsigned stride
, outer_comps
, inner_comps
;
4317 LLVMValueRef invocation_id
= ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 8, 5);
4318 LLVMValueRef rel_patch_id
= ac_unpack_param(&ctx
->ac
, ctx
->abi
.tcs_rel_ids
, 0, 8);
4319 unsigned tess_inner_index
= 0, tess_outer_index
;
4320 LLVMValueRef lds_base
, lds_inner
= NULL
, lds_outer
, byteoffset
, buffer
;
4321 LLVMValueRef out
[6], vec0
, vec1
, tf_base
, inner
[4], outer
[4];
4323 ac_emit_barrier(&ctx
->ac
, ctx
->stage
);
4325 switch (ctx
->options
->key
.tcs
.primitive_mode
) {
4345 ac_build_ifcc(&ctx
->ac
,
4346 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
4347 invocation_id
, ctx
->ac
.i32_0
, ""), 6503);
4349 lds_base
= get_tcs_out_current_patch_data_offset(ctx
);
4352 tess_inner_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
4353 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
4354 LLVMConstInt(ctx
->ac
.i32
, tess_inner_index
* 4, false), "");
4357 tess_outer_index
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
4358 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_base
,
4359 LLVMConstInt(ctx
->ac
.i32
, tess_outer_index
* 4, false), "");
4361 for (i
= 0; i
< 4; i
++) {
4362 inner
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
4363 outer
[i
] = LLVMGetUndef(ctx
->ac
.i32
);
4367 if (ctx
->options
->key
.tcs
.primitive_mode
== GL_ISOLINES
) {
4368 outer
[0] = out
[1] = ac_lds_load(&ctx
->ac
, lds_outer
);
4369 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
4371 outer
[1] = out
[0] = ac_lds_load(&ctx
->ac
, lds_outer
);
4373 for (i
= 0; i
< outer_comps
; i
++) {
4375 ac_lds_load(&ctx
->ac
, lds_outer
);
4376 lds_outer
= LLVMBuildAdd(ctx
->ac
.builder
, lds_outer
,
4379 for (i
= 0; i
< inner_comps
; i
++) {
4380 inner
[i
] = out
[outer_comps
+i
] =
4381 ac_lds_load(&ctx
->ac
, lds_inner
);
4382 lds_inner
= LLVMBuildAdd(ctx
->ac
.builder
, lds_inner
,
4387 /* Convert the outputs to vectors for stores. */
4388 vec0
= ac_build_gather_values(&ctx
->ac
, out
, MIN2(stride
, 4));
4392 vec1
= ac_build_gather_values(&ctx
->ac
, out
+ 4, stride
- 4);
4395 buffer
= ctx
->hs_ring_tess_factor
;
4396 tf_base
= ctx
->tess_factor_offset
;
4397 byteoffset
= LLVMBuildMul(ctx
->ac
.builder
, rel_patch_id
,
4398 LLVMConstInt(ctx
->ac
.i32
, 4 * stride
, false), "");
4399 unsigned tf_offset
= 0;
4401 if (ctx
->options
->chip_class
<= GFX8
) {
4402 ac_build_ifcc(&ctx
->ac
,
4403 LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
,
4404 rel_patch_id
, ctx
->ac
.i32_0
, ""), 6504);
4406 /* Store the dynamic HS control word. */
4407 ac_build_buffer_store_dword(&ctx
->ac
, buffer
,
4408 LLVMConstInt(ctx
->ac
.i32
, 0x80000000, false),
4409 1, ctx
->ac
.i32_0
, tf_base
,
4413 ac_build_endif(&ctx
->ac
, 6504);
4416 /* Store the tessellation factors. */
4417 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec0
,
4418 MIN2(stride
, 4), byteoffset
, tf_base
,
4419 tf_offset
, ac_glc
, false);
4421 ac_build_buffer_store_dword(&ctx
->ac
, buffer
, vec1
,
4422 stride
- 4, byteoffset
, tf_base
,
4423 16 + tf_offset
, ac_glc
, false);
4425 //store to offchip for TES to read - only if TES reads them
4426 if (ctx
->options
->key
.tcs
.tes_reads_tess_factors
) {
4427 LLVMValueRef inner_vec
, outer_vec
, tf_outer_offset
;
4428 LLVMValueRef tf_inner_offset
;
4429 unsigned param_outer
, param_inner
;
4431 param_outer
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER
);
4432 tf_outer_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
4433 LLVMConstInt(ctx
->ac
.i32
, param_outer
, 0));
4435 outer_vec
= ac_build_gather_values(&ctx
->ac
, outer
,
4436 util_next_power_of_two(outer_comps
));
4438 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, outer_vec
,
4439 outer_comps
, tf_outer_offset
,
4440 ctx
->oc_lds
, 0, ac_glc
, false);
4442 param_inner
= shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER
);
4443 tf_inner_offset
= get_tcs_tes_buffer_address(ctx
, NULL
,
4444 LLVMConstInt(ctx
->ac
.i32
, param_inner
, 0));
4446 inner_vec
= inner_comps
== 1 ? inner
[0] :
4447 ac_build_gather_values(&ctx
->ac
, inner
, inner_comps
);
4448 ac_build_buffer_store_dword(&ctx
->ac
, ctx
->hs_ring_tess_offchip
, inner_vec
,
4449 inner_comps
, tf_inner_offset
,
4450 ctx
->oc_lds
, 0, ac_glc
, false);
4454 ac_build_endif(&ctx
->ac
, 6503);
4458 handle_tcs_outputs_post(struct radv_shader_context
*ctx
)
4460 write_tess_factors(ctx
);
4464 si_export_mrt_color(struct radv_shader_context
*ctx
,
4465 LLVMValueRef
*color
, unsigned index
,
4466 struct ac_export_args
*args
)
4469 si_llvm_init_export_args(ctx
, color
, 0xf,
4470 V_008DFC_SQ_EXP_MRT
+ index
, args
);
4471 if (!args
->enabled_channels
)
4472 return false; /* unnecessary NULL export */
4478 radv_export_mrt_z(struct radv_shader_context
*ctx
,
4479 LLVMValueRef depth
, LLVMValueRef stencil
,
4480 LLVMValueRef samplemask
)
4482 struct ac_export_args args
;
4484 ac_export_mrt_z(&ctx
->ac
, depth
, stencil
, samplemask
, &args
);
4486 ac_build_export(&ctx
->ac
, &args
);
4490 handle_fs_outputs_post(struct radv_shader_context
*ctx
)
4493 LLVMValueRef depth
= NULL
, stencil
= NULL
, samplemask
= NULL
;
4494 struct ac_export_args color_args
[8];
4496 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
4497 LLVMValueRef values
[4];
4499 if (!(ctx
->output_mask
& (1ull << i
)))
4502 if (i
< FRAG_RESULT_DATA0
)
4505 for (unsigned j
= 0; j
< 4; j
++)
4506 values
[j
] = ac_to_float(&ctx
->ac
,
4507 radv_load_output(ctx
, i
, j
));
4509 bool ret
= si_export_mrt_color(ctx
, values
,
4510 i
- FRAG_RESULT_DATA0
,
4511 &color_args
[index
]);
4516 /* Process depth, stencil, samplemask. */
4517 if (ctx
->shader_info
->ps
.writes_z
) {
4518 depth
= ac_to_float(&ctx
->ac
,
4519 radv_load_output(ctx
, FRAG_RESULT_DEPTH
, 0));
4521 if (ctx
->shader_info
->ps
.writes_stencil
) {
4522 stencil
= ac_to_float(&ctx
->ac
,
4523 radv_load_output(ctx
, FRAG_RESULT_STENCIL
, 0));
4525 if (ctx
->shader_info
->ps
.writes_sample_mask
) {
4526 samplemask
= ac_to_float(&ctx
->ac
,
4527 radv_load_output(ctx
, FRAG_RESULT_SAMPLE_MASK
, 0));
4530 /* Set the DONE bit on last non-null color export only if Z isn't
4534 !ctx
->shader_info
->ps
.writes_z
&&
4535 !ctx
->shader_info
->ps
.writes_stencil
&&
4536 !ctx
->shader_info
->ps
.writes_sample_mask
) {
4537 unsigned last
= index
- 1;
4539 color_args
[last
].valid_mask
= 1; /* whether the EXEC mask is valid */
4540 color_args
[last
].done
= 1; /* DONE bit */
4543 /* Export PS outputs. */
4544 for (unsigned i
= 0; i
< index
; i
++)
4545 ac_build_export(&ctx
->ac
, &color_args
[i
]);
4547 if (depth
|| stencil
|| samplemask
)
4548 radv_export_mrt_z(ctx
, depth
, stencil
, samplemask
);
4550 ac_build_export_null(&ctx
->ac
);
4554 emit_gs_epilogue(struct radv_shader_context
*ctx
)
4556 if (ctx
->options
->key
.vs_common_out
.as_ngg
) {
4557 gfx10_ngg_gs_emit_epilogue_1(ctx
);
4561 if (ctx
->ac
.chip_class
>= GFX10
)
4562 LLVMBuildFence(ctx
->ac
.builder
, LLVMAtomicOrderingRelease
, false, "");
4564 ac_build_sendmsg(&ctx
->ac
, AC_SENDMSG_GS_OP_NOP
| AC_SENDMSG_GS_DONE
, ctx
->gs_wave_id
);
4568 handle_shader_outputs_post(struct ac_shader_abi
*abi
, unsigned max_outputs
,
4569 LLVMValueRef
*addrs
)
4571 struct radv_shader_context
*ctx
= radv_shader_context_from_abi(abi
);
4573 switch (ctx
->stage
) {
4574 case MESA_SHADER_VERTEX
:
4575 if (ctx
->options
->key
.vs_common_out
.as_ls
)
4576 handle_ls_outputs_post(ctx
);
4577 else if (ctx
->options
->key
.vs_common_out
.as_es
)
4578 handle_es_outputs_post(ctx
, &ctx
->shader_info
->vs
.es_info
);
4579 else if (ctx
->options
->key
.vs_common_out
.as_ngg
)
4580 handle_ngg_outputs_post_1(ctx
);
4582 handle_vs_outputs_post(ctx
, ctx
->options
->key
.vs_common_out
.export_prim_id
,
4583 ctx
->options
->key
.vs_common_out
.export_clip_dists
,
4584 &ctx
->shader_info
->vs
.outinfo
);
4586 case MESA_SHADER_FRAGMENT
:
4587 handle_fs_outputs_post(ctx
);
4589 case MESA_SHADER_GEOMETRY
:
4590 emit_gs_epilogue(ctx
);
4592 case MESA_SHADER_TESS_CTRL
:
4593 handle_tcs_outputs_post(ctx
);
4595 case MESA_SHADER_TESS_EVAL
:
4596 if (ctx
->options
->key
.vs_common_out
.as_es
)
4597 handle_es_outputs_post(ctx
, &ctx
->shader_info
->tes
.es_info
);
4598 else if (ctx
->options
->key
.vs_common_out
.as_ngg
)
4599 handle_ngg_outputs_post_1(ctx
);
4601 handle_vs_outputs_post(ctx
, ctx
->options
->key
.vs_common_out
.export_prim_id
,
4602 ctx
->options
->key
.vs_common_out
.export_clip_dists
,
4603 &ctx
->shader_info
->tes
.outinfo
);
4610 static void ac_llvm_finalize_module(struct radv_shader_context
*ctx
,
4611 LLVMPassManagerRef passmgr
,
4612 const struct radv_nir_compiler_options
*options
)
4614 LLVMRunPassManager(passmgr
, ctx
->ac
.module
);
4615 LLVMDisposeBuilder(ctx
->ac
.builder
);
4617 ac_llvm_context_dispose(&ctx
->ac
);
4621 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context
*ctx
)
4623 struct radv_vs_output_info
*outinfo
;
4625 switch (ctx
->stage
) {
4626 case MESA_SHADER_FRAGMENT
:
4627 case MESA_SHADER_COMPUTE
:
4628 case MESA_SHADER_TESS_CTRL
:
4629 case MESA_SHADER_GEOMETRY
:
4631 case MESA_SHADER_VERTEX
:
4632 if (ctx
->options
->key
.vs_common_out
.as_ls
||
4633 ctx
->options
->key
.vs_common_out
.as_es
)
4635 outinfo
= &ctx
->shader_info
->vs
.outinfo
;
4637 case MESA_SHADER_TESS_EVAL
:
4638 if (ctx
->options
->key
.vs_common_out
.as_es
)
4640 outinfo
= &ctx
->shader_info
->tes
.outinfo
;
4643 unreachable("Unhandled shader type");
4646 ac_optimize_vs_outputs(&ctx
->ac
,
4648 outinfo
->vs_output_param_offset
,
4650 &outinfo
->param_exports
);
4654 ac_setup_rings(struct radv_shader_context
*ctx
)
4656 if (ctx
->options
->chip_class
<= GFX8
&&
4657 (ctx
->stage
== MESA_SHADER_GEOMETRY
||
4658 ctx
->options
->key
.vs_common_out
.as_es
|| ctx
->options
->key
.vs_common_out
.as_es
)) {
4659 unsigned ring
= ctx
->stage
== MESA_SHADER_GEOMETRY
? RING_ESGS_GS
4661 LLVMValueRef offset
= LLVMConstInt(ctx
->ac
.i32
, ring
, false);
4663 ctx
->esgs_ring
= ac_build_load_to_sgpr(&ctx
->ac
,
4668 if (ctx
->is_gs_copy_shader
) {
4670 ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
,
4671 LLVMConstInt(ctx
->ac
.i32
,
4672 RING_GSVS_VS
, false));
4675 if (ctx
->stage
== MESA_SHADER_GEOMETRY
) {
4676 /* The conceptual layout of the GSVS ring is
4677 * v0c0 .. vLv0 v0c1 .. vLc1 ..
4678 * but the real memory layout is swizzled across
4680 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
4682 * Override the buffer descriptor accordingly.
4684 LLVMTypeRef v2i64
= LLVMVectorType(ctx
->ac
.i64
, 2);
4685 uint64_t stream_offset
= 0;
4686 unsigned num_records
= ctx
->ac
.wave_size
;
4687 LLVMValueRef base_ring
;
4690 ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
,
4691 LLVMConstInt(ctx
->ac
.i32
,
4692 RING_GSVS_GS
, false));
4694 for (unsigned stream
= 0; stream
< 4; stream
++) {
4695 unsigned num_components
, stride
;
4696 LLVMValueRef ring
, tmp
;
4699 ctx
->shader_info
->gs
.num_stream_output_components
[stream
];
4701 if (!num_components
)
4704 stride
= 4 * num_components
* ctx
->shader
->info
.gs
.vertices_out
;
4706 /* Limit on the stride field for <= GFX7. */
4707 assert(stride
< (1 << 14));
4709 ring
= LLVMBuildBitCast(ctx
->ac
.builder
,
4710 base_ring
, v2i64
, "");
4711 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
,
4712 ring
, ctx
->ac
.i32_0
, "");
4713 tmp
= LLVMBuildAdd(ctx
->ac
.builder
, tmp
,
4714 LLVMConstInt(ctx
->ac
.i64
,
4715 stream_offset
, 0), "");
4716 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
,
4717 ring
, tmp
, ctx
->ac
.i32_0
, "");
4719 stream_offset
+= stride
* ctx
->ac
.wave_size
;
4721 ring
= LLVMBuildBitCast(ctx
->ac
.builder
, ring
,
4724 tmp
= LLVMBuildExtractElement(ctx
->ac
.builder
, ring
,
4726 tmp
= LLVMBuildOr(ctx
->ac
.builder
, tmp
,
4727 LLVMConstInt(ctx
->ac
.i32
,
4728 S_008F04_STRIDE(stride
), false), "");
4729 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ring
, tmp
,
4732 ring
= LLVMBuildInsertElement(ctx
->ac
.builder
, ring
,
4733 LLVMConstInt(ctx
->ac
.i32
,
4734 num_records
, false),
4735 LLVMConstInt(ctx
->ac
.i32
, 2, false), "");
4737 ctx
->gsvs_ring
[stream
] = ring
;
4741 if (ctx
->stage
== MESA_SHADER_TESS_CTRL
||
4742 ctx
->stage
== MESA_SHADER_TESS_EVAL
) {
4743 ctx
->hs_ring_tess_offchip
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_OFFCHIP
, false));
4744 ctx
->hs_ring_tess_factor
= ac_build_load_to_sgpr(&ctx
->ac
, ctx
->ring_offsets
, LLVMConstInt(ctx
->ac
.i32
, RING_HS_TESS_FACTOR
, false));
4749 radv_nir_get_max_workgroup_size(enum chip_class chip_class
,
4750 gl_shader_stage stage
,
4751 const struct nir_shader
*nir
)
4753 const unsigned backup_sizes
[] = {chip_class
>= GFX9
? 128 : 64, 1, 1};
4755 for (unsigned i
= 0; i
< 3; i
++)
4756 sizes
[i
] = nir
? nir
->info
.cs
.local_size
[i
] : backup_sizes
[i
];
4757 return radv_get_max_workgroup_size(chip_class
, stage
, sizes
);
4760 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
4761 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context
*ctx
)
4763 LLVMValueRef count
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 8, 8);
4764 LLVMValueRef hs_empty
= LLVMBuildICmp(ctx
->ac
.builder
, LLVMIntEQ
, count
,
4766 ctx
->abi
.instance_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->rel_auto_id
, ctx
->abi
.instance_id
, "");
4767 ctx
->rel_auto_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_rel_ids
, ctx
->rel_auto_id
, "");
4768 ctx
->abi
.vertex_id
= LLVMBuildSelect(ctx
->ac
.builder
, hs_empty
, ctx
->abi
.tcs_patch_id
, ctx
->abi
.vertex_id
, "");
4771 static void prepare_gs_input_vgprs(struct radv_shader_context
*ctx
)
4773 for(int i
= 5; i
>= 0; --i
) {
4774 ctx
->gs_vtx_offset
[i
] = ac_unpack_param(&ctx
->ac
, ctx
->gs_vtx_offset
[i
& ~1],
4778 ctx
->gs_wave_id
= ac_unpack_param(&ctx
->ac
, ctx
->merged_wave_info
, 16, 8);
4781 /* Ensure that the esgs ring is declared.
4783 * We declare it with 64KB alignment as a hint that the
4784 * pointer value will always be 0.
4786 static void declare_esgs_ring(struct radv_shader_context
*ctx
)
4791 assert(!LLVMGetNamedGlobal(ctx
->ac
.module
, "esgs_ring"));
4793 ctx
->esgs_ring
= LLVMAddGlobalInAddressSpace(
4794 ctx
->ac
.module
, LLVMArrayType(ctx
->ac
.i32
, 0),
4797 LLVMSetLinkage(ctx
->esgs_ring
, LLVMExternalLinkage
);
4798 LLVMSetAlignment(ctx
->esgs_ring
, 64 * 1024);
4802 LLVMModuleRef
ac_translate_nir_to_llvm(struct ac_llvm_compiler
*ac_llvm
,
4803 struct nir_shader
*const *shaders
,
4805 struct radv_shader_info
*shader_info
,
4806 const struct radv_nir_compiler_options
*options
)
4808 struct radv_shader_context ctx
= {0};
4810 ctx
.options
= options
;
4811 ctx
.shader_info
= shader_info
;
4813 enum ac_float_mode float_mode
= AC_FLOAT_MODE_DEFAULT
;
4815 if (shader_info
->float_controls_mode
& FLOAT_CONTROLS_DENORM_FLUSH_TO_ZERO_FP32
) {
4816 float_mode
= AC_FLOAT_MODE_DENORM_FLUSH_TO_ZERO
;
4817 } else if (options
->unsafe_math
) {
4818 float_mode
= AC_FLOAT_MODE_UNSAFE_FP_MATH
;
4821 ac_llvm_context_init(&ctx
.ac
, ac_llvm
, options
->chip_class
,
4822 options
->family
, float_mode
, shader_info
->wave_size
, 64);
4823 ctx
.context
= ctx
.ac
.context
;
4825 for (i
= 0; i
< MAX_SETS
; i
++)
4826 shader_info
->user_sgprs_locs
.descriptor_sets
[i
].sgpr_idx
= -1;
4827 for (i
= 0; i
< AC_UD_MAX_UD
; i
++)
4828 shader_info
->user_sgprs_locs
.shader_data
[i
].sgpr_idx
= -1;
4830 ctx
.max_workgroup_size
= 0;
4831 for (int i
= 0; i
< shader_count
; ++i
) {
4832 ctx
.max_workgroup_size
= MAX2(ctx
.max_workgroup_size
,
4833 radv_nir_get_max_workgroup_size(ctx
.options
->chip_class
,
4834 shaders
[i
]->info
.stage
,
4838 if (ctx
.ac
.chip_class
>= GFX10
) {
4839 if (is_pre_gs_stage(shaders
[0]->info
.stage
) &&
4840 options
->key
.vs_common_out
.as_ngg
) {
4841 ctx
.max_workgroup_size
= 128;
4845 create_function(&ctx
, shaders
[shader_count
- 1]->info
.stage
, shader_count
>= 2,
4846 shader_count
>= 2 ? shaders
[shader_count
- 2]->info
.stage
: MESA_SHADER_VERTEX
);
4848 ctx
.abi
.inputs
= &ctx
.inputs
[0];
4849 ctx
.abi
.emit_outputs
= handle_shader_outputs_post
;
4850 ctx
.abi
.emit_vertex
= visit_emit_vertex
;
4851 ctx
.abi
.load_ubo
= radv_load_ubo
;
4852 ctx
.abi
.load_ssbo
= radv_load_ssbo
;
4853 ctx
.abi
.load_sampler_desc
= radv_get_sampler_desc
;
4854 ctx
.abi
.load_resource
= radv_load_resource
;
4855 ctx
.abi
.clamp_shadow_reference
= false;
4856 ctx
.abi
.robust_buffer_access
= options
->robust_buffer_access
;
4858 bool is_ngg
= is_pre_gs_stage(shaders
[0]->info
.stage
) && ctx
.options
->key
.vs_common_out
.as_ngg
;
4859 if (shader_count
>= 2 || is_ngg
)
4860 ac_init_exec_full_mask(&ctx
.ac
);
4862 if (options
->has_ls_vgpr_init_bug
&&
4863 shaders
[shader_count
- 1]->info
.stage
== MESA_SHADER_TESS_CTRL
)
4864 ac_nir_fixup_ls_hs_input_vgprs(&ctx
);
4867 /* Declare scratch space base for streamout and vertex
4868 * compaction. Whether space is actually allocated is
4869 * determined during linking / PM4 creation.
4871 * Add an extra dword per vertex to ensure an odd stride, which
4872 * avoids bank conflicts for SoA accesses.
4874 declare_esgs_ring(&ctx
);
4876 /* This is really only needed when streamout and / or vertex
4877 * compaction is enabled.
4879 LLVMTypeRef asi32
= LLVMArrayType(ctx
.ac
.i32
, 8);
4880 ctx
.gs_ngg_scratch
= LLVMAddGlobalInAddressSpace(ctx
.ac
.module
,
4881 asi32
, "ngg_scratch", AC_ADDR_SPACE_LDS
);
4882 LLVMSetInitializer(ctx
.gs_ngg_scratch
, LLVMGetUndef(asi32
));
4883 LLVMSetAlignment(ctx
.gs_ngg_scratch
, 4);
4886 for(int i
= 0; i
< shader_count
; ++i
) {
4887 ctx
.stage
= shaders
[i
]->info
.stage
;
4888 ctx
.shader
= shaders
[i
];
4889 ctx
.output_mask
= 0;
4891 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
) {
4892 for (int i
= 0; i
< 4; i
++) {
4893 ctx
.gs_next_vertex
[i
] =
4894 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
4896 if (ctx
.options
->key
.vs_common_out
.as_ngg
) {
4897 for (unsigned i
= 0; i
< 4; ++i
) {
4898 ctx
.gs_curprim_verts
[i
] =
4899 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
4900 ctx
.gs_generated_prims
[i
] =
4901 ac_build_alloca(&ctx
.ac
, ctx
.ac
.i32
, "");
4904 unsigned scratch_size
= 8;
4905 if (ctx
.shader_info
->so
.num_outputs
)
4908 LLVMTypeRef ai32
= LLVMArrayType(ctx
.ac
.i32
, scratch_size
);
4909 ctx
.gs_ngg_scratch
=
4910 LLVMAddGlobalInAddressSpace(ctx
.ac
.module
,
4911 ai32
, "ngg_scratch", AC_ADDR_SPACE_LDS
);
4912 LLVMSetInitializer(ctx
.gs_ngg_scratch
, LLVMGetUndef(ai32
));
4913 LLVMSetAlignment(ctx
.gs_ngg_scratch
, 4);
4915 ctx
.gs_ngg_emit
= LLVMAddGlobalInAddressSpace(ctx
.ac
.module
,
4916 LLVMArrayType(ctx
.ac
.i32
, 0), "ngg_emit", AC_ADDR_SPACE_LDS
);
4917 LLVMSetLinkage(ctx
.gs_ngg_emit
, LLVMExternalLinkage
);
4918 LLVMSetAlignment(ctx
.gs_ngg_emit
, 4);
4921 ctx
.abi
.load_inputs
= load_gs_input
;
4922 ctx
.abi
.emit_primitive
= visit_end_primitive
;
4923 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
4924 ctx
.abi
.load_tess_varyings
= load_tcs_varyings
;
4925 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
4926 ctx
.abi
.store_tcs_outputs
= store_tcs_output
;
4927 if (shader_count
== 1)
4928 ctx
.tcs_num_inputs
= ctx
.options
->key
.tcs
.num_inputs
;
4930 ctx
.tcs_num_inputs
= util_last_bit64(shader_info
->vs
.ls_outputs_written
);
4931 ctx
.tcs_num_patches
= get_tcs_num_patches(&ctx
);
4932 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_EVAL
) {
4933 ctx
.abi
.load_tess_varyings
= load_tes_input
;
4934 ctx
.abi
.load_tess_coord
= load_tess_coord
;
4935 ctx
.abi
.load_patch_vertices_in
= load_patch_vertices_in
;
4936 ctx
.tcs_num_patches
= ctx
.options
->key
.tes
.num_patches
;
4937 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
) {
4938 ctx
.abi
.load_base_vertex
= radv_load_base_vertex
;
4939 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
) {
4940 ctx
.abi
.load_sample_position
= load_sample_position
;
4941 ctx
.abi
.load_sample_mask_in
= load_sample_mask_in
;
4942 ctx
.abi
.emit_kill
= radv_emit_kill
;
4945 if (shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
&&
4946 ctx
.options
->key
.vs_common_out
.as_ngg
&&
4947 ctx
.options
->key
.vs_common_out
.export_prim_id
) {
4948 declare_esgs_ring(&ctx
);
4951 bool nested_barrier
= false;
4954 if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
&&
4955 ctx
.options
->key
.vs_common_out
.as_ngg
) {
4956 gfx10_ngg_gs_emit_prologue(&ctx
);
4957 nested_barrier
= false;
4959 nested_barrier
= true;
4963 if (nested_barrier
) {
4964 /* Execute a barrier before the second shader in
4967 * Execute the barrier inside the conditional block,
4968 * so that empty waves can jump directly to s_endpgm,
4969 * which will also signal the barrier.
4971 * This is possible in gfx9, because an empty wave
4972 * for the second shader does not participate in
4973 * the epilogue. With NGG, empty waves may still
4974 * be required to export data (e.g. GS output vertices),
4975 * so we cannot let them exit early.
4977 * If the shader is TCS and the TCS epilog is present
4978 * and contains a barrier, it will wait there and then
4981 ac_emit_barrier(&ctx
.ac
, ctx
.stage
);
4984 nir_foreach_variable(variable
, &shaders
[i
]->outputs
)
4985 scan_shader_output_decl(&ctx
, variable
, shaders
[i
], shaders
[i
]->info
.stage
);
4987 ac_setup_rings(&ctx
);
4989 LLVMBasicBlockRef merge_block
;
4990 if (shader_count
>= 2 || is_ngg
) {
4991 LLVMValueRef fn
= LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx
.ac
.builder
));
4992 LLVMBasicBlockRef then_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
4993 merge_block
= LLVMAppendBasicBlockInContext(ctx
.ac
.context
, fn
, "");
4995 LLVMValueRef count
= ac_unpack_param(&ctx
.ac
, ctx
.merged_wave_info
, 8 * i
, 8);
4996 LLVMValueRef thread_id
= ac_get_thread_id(&ctx
.ac
);
4997 LLVMValueRef cond
= LLVMBuildICmp(ctx
.ac
.builder
, LLVMIntULT
,
4998 thread_id
, count
, "");
4999 LLVMBuildCondBr(ctx
.ac
.builder
, cond
, then_block
, merge_block
);
5001 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, then_block
);
5004 if (shaders
[i
]->info
.stage
== MESA_SHADER_FRAGMENT
)
5005 prepare_interp_optimize(&ctx
, shaders
[i
]);
5006 else if(shaders
[i
]->info
.stage
== MESA_SHADER_VERTEX
)
5007 handle_vs_inputs(&ctx
, shaders
[i
]);
5008 else if(shader_count
>= 2 && shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
)
5009 prepare_gs_input_vgprs(&ctx
);
5011 ac_nir_translate(&ctx
.ac
, &ctx
.abi
, shaders
[i
]);
5013 if (shader_count
>= 2 || is_ngg
) {
5014 LLVMBuildBr(ctx
.ac
.builder
, merge_block
);
5015 LLVMPositionBuilderAtEnd(ctx
.ac
.builder
, merge_block
);
5018 /* This needs to be outside the if wrapping the shader body, as sometimes
5019 * the HW generates waves with 0 es/vs threads. */
5020 if (is_pre_gs_stage(shaders
[i
]->info
.stage
) &&
5021 ctx
.options
->key
.vs_common_out
.as_ngg
&&
5022 i
== shader_count
- 1) {
5023 handle_ngg_outputs_post_2(&ctx
);
5024 } else if (shaders
[i
]->info
.stage
== MESA_SHADER_GEOMETRY
&&
5025 ctx
.options
->key
.vs_common_out
.as_ngg
) {
5026 gfx10_ngg_gs_emit_epilogue_2(&ctx
);
5029 if (shaders
[i
]->info
.stage
== MESA_SHADER_TESS_CTRL
) {
5030 shader_info
->tcs
.num_patches
= ctx
.tcs_num_patches
;
5031 shader_info
->tcs
.lds_size
= calculate_tess_lds_size(&ctx
);
5035 LLVMBuildRetVoid(ctx
.ac
.builder
);
5037 if (options
->dump_preoptir
) {
5038 fprintf(stderr
, "%s LLVM IR:\n\n",
5039 radv_get_shader_name(shader_info
,
5040 shaders
[shader_count
- 1]->info
.stage
));
5041 ac_dump_module(ctx
.ac
.module
);
5042 fprintf(stderr
, "\n");
5045 ac_llvm_finalize_module(&ctx
, ac_llvm
->passmgr
, options
);
5047 if (shader_count
== 1)
5048 ac_nir_eliminate_const_vs_outputs(&ctx
);
5050 if (options
->dump_shader
) {
5051 ctx
.shader_info
->private_mem_vgprs
=
5052 ac_count_scratch_private_memory(ctx
.main_function
);
5055 return ctx
.ac
.module
;
5058 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di
, void *context
)
5060 unsigned *retval
= (unsigned *)context
;
5061 LLVMDiagnosticSeverity severity
= LLVMGetDiagInfoSeverity(di
);
5062 char *description
= LLVMGetDiagInfoDescription(di
);
5064 if (severity
== LLVMDSError
) {
5066 fprintf(stderr
, "LLVM triggered Diagnostic Handler: %s\n",
5070 LLVMDisposeMessage(description
);
5073 static unsigned radv_llvm_compile(LLVMModuleRef M
,
5074 char **pelf_buffer
, size_t *pelf_size
,
5075 struct ac_llvm_compiler
*ac_llvm
)
5077 unsigned retval
= 0;
5078 LLVMContextRef llvm_ctx
;
5080 /* Setup Diagnostic Handler*/
5081 llvm_ctx
= LLVMGetModuleContext(M
);
5083 LLVMContextSetDiagnosticHandler(llvm_ctx
, ac_diagnostic_handler
,
5087 if (!radv_compile_to_elf(ac_llvm
, M
, pelf_buffer
, pelf_size
))
5092 static void ac_compile_llvm_module(struct ac_llvm_compiler
*ac_llvm
,
5093 LLVMModuleRef llvm_module
,
5094 struct radv_shader_binary
**rbinary
,
5095 gl_shader_stage stage
,
5097 const struct radv_nir_compiler_options
*options
)
5099 char *elf_buffer
= NULL
;
5100 size_t elf_size
= 0;
5101 char *llvm_ir_string
= NULL
;
5103 if (options
->dump_shader
) {
5104 fprintf(stderr
, "%s LLVM IR:\n\n", name
);
5105 ac_dump_module(llvm_module
);
5106 fprintf(stderr
, "\n");
5109 if (options
->record_ir
) {
5110 char *llvm_ir
= LLVMPrintModuleToString(llvm_module
);
5111 llvm_ir_string
= strdup(llvm_ir
);
5112 LLVMDisposeMessage(llvm_ir
);
5115 int v
= radv_llvm_compile(llvm_module
, &elf_buffer
, &elf_size
, ac_llvm
);
5117 fprintf(stderr
, "compile failed\n");
5120 LLVMContextRef ctx
= LLVMGetModuleContext(llvm_module
);
5121 LLVMDisposeModule(llvm_module
);
5122 LLVMContextDispose(ctx
);
5124 size_t llvm_ir_size
= llvm_ir_string
? strlen(llvm_ir_string
) : 0;
5125 size_t alloc_size
= sizeof(struct radv_shader_binary_rtld
) + elf_size
+ llvm_ir_size
+ 1;
5126 struct radv_shader_binary_rtld
*rbin
= calloc(1, alloc_size
);
5127 memcpy(rbin
->data
, elf_buffer
, elf_size
);
5129 memcpy(rbin
->data
+ elf_size
, llvm_ir_string
, llvm_ir_size
+ 1);
5131 rbin
->base
.type
= RADV_BINARY_TYPE_RTLD
;
5132 rbin
->base
.stage
= stage
;
5133 rbin
->base
.total_size
= alloc_size
;
5134 rbin
->elf_size
= elf_size
;
5135 rbin
->llvm_ir_size
= llvm_ir_size
;
5136 *rbinary
= &rbin
->base
;
5138 free(llvm_ir_string
);
5143 radv_compile_nir_shader(struct ac_llvm_compiler
*ac_llvm
,
5144 struct radv_shader_binary
**rbinary
,
5145 struct radv_shader_info
*shader_info
,
5146 struct nir_shader
*const *nir
,
5148 const struct radv_nir_compiler_options
*options
)
5151 LLVMModuleRef llvm_module
;
5153 llvm_module
= ac_translate_nir_to_llvm(ac_llvm
, nir
, nir_count
, shader_info
,
5156 ac_compile_llvm_module(ac_llvm
, llvm_module
, rbinary
,
5157 nir
[nir_count
- 1]->info
.stage
,
5158 radv_get_shader_name(shader_info
,
5159 nir
[nir_count
- 1]->info
.stage
),
5162 /* Determine the ES type (VS or TES) for the GS on GFX9. */
5163 if (options
->chip_class
>= GFX9
) {
5164 if (nir_count
== 2 &&
5165 nir
[1]->info
.stage
== MESA_SHADER_GEOMETRY
) {
5166 shader_info
->gs
.es_type
= nir
[0]->info
.stage
;
5172 ac_gs_copy_shader_emit(struct radv_shader_context
*ctx
)
5174 LLVMValueRef vtx_offset
=
5175 LLVMBuildMul(ctx
->ac
.builder
, ctx
->abi
.vertex_id
,
5176 LLVMConstInt(ctx
->ac
.i32
, 4, false), "");
5177 LLVMValueRef stream_id
;
5179 /* Fetch the vertex stream ID. */
5180 if (!ctx
->options
->use_ngg_streamout
&&
5181 ctx
->shader_info
->so
.num_outputs
) {
5183 ac_unpack_param(&ctx
->ac
, ctx
->streamout_config
, 24, 2);
5185 stream_id
= ctx
->ac
.i32_0
;
5188 LLVMBasicBlockRef end_bb
;
5189 LLVMValueRef switch_inst
;
5191 end_bb
= LLVMAppendBasicBlockInContext(ctx
->ac
.context
,
5192 ctx
->main_function
, "end");
5193 switch_inst
= LLVMBuildSwitch(ctx
->ac
.builder
, stream_id
, end_bb
, 4);
5195 for (unsigned stream
= 0; stream
< 4; stream
++) {
5196 unsigned num_components
=
5197 ctx
->shader_info
->gs
.num_stream_output_components
[stream
];
5198 LLVMBasicBlockRef bb
;
5201 if (stream
> 0 && !num_components
)
5204 if (stream
> 0 && !ctx
->shader_info
->so
.num_outputs
)
5207 bb
= LLVMInsertBasicBlockInContext(ctx
->ac
.context
, end_bb
, "out");
5208 LLVMAddCase(switch_inst
, LLVMConstInt(ctx
->ac
.i32
, stream
, 0), bb
);
5209 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, bb
);
5212 for (unsigned i
= 0; i
< AC_LLVM_MAX_OUTPUTS
; ++i
) {
5213 unsigned output_usage_mask
=
5214 ctx
->shader_info
->gs
.output_usage_mask
[i
];
5215 unsigned output_stream
=
5216 ctx
->shader_info
->gs
.output_streams
[i
];
5217 int length
= util_last_bit(output_usage_mask
);
5219 if (!(ctx
->output_mask
& (1ull << i
)) ||
5220 output_stream
!= stream
)
5223 for (unsigned j
= 0; j
< length
; j
++) {
5224 LLVMValueRef value
, soffset
;
5226 if (!(output_usage_mask
& (1 << j
)))
5229 soffset
= LLVMConstInt(ctx
->ac
.i32
,
5231 ctx
->shader
->info
.gs
.vertices_out
* 16 * 4, false);
5235 value
= ac_build_buffer_load(&ctx
->ac
,
5238 vtx_offset
, soffset
,
5239 0, ac_glc
| ac_slc
, true, false);
5241 LLVMTypeRef type
= LLVMGetAllocatedType(ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
5242 if (ac_get_type_size(type
) == 2) {
5243 value
= LLVMBuildBitCast(ctx
->ac
.builder
, value
, ctx
->ac
.i32
, "");
5244 value
= LLVMBuildTrunc(ctx
->ac
.builder
, value
, ctx
->ac
.i16
, "");
5247 LLVMBuildStore(ctx
->ac
.builder
,
5248 ac_to_float(&ctx
->ac
, value
), ctx
->abi
.outputs
[ac_llvm_reg_index_soa(i
, j
)]);
5252 if (!ctx
->options
->use_ngg_streamout
&&
5253 ctx
->shader_info
->so
.num_outputs
)
5254 radv_emit_streamout(ctx
, stream
);
5257 handle_vs_outputs_post(ctx
, false, true,
5258 &ctx
->shader_info
->vs
.outinfo
);
5261 LLVMBuildBr(ctx
->ac
.builder
, end_bb
);
5264 LLVMPositionBuilderAtEnd(ctx
->ac
.builder
, end_bb
);
5268 radv_compile_gs_copy_shader(struct ac_llvm_compiler
*ac_llvm
,
5269 struct nir_shader
*geom_shader
,
5270 struct radv_shader_binary
**rbinary
,
5271 struct radv_shader_info
*shader_info
,
5272 const struct radv_nir_compiler_options
*options
)
5274 struct radv_shader_context ctx
= {0};
5275 ctx
.options
= options
;
5276 ctx
.shader_info
= shader_info
;
5278 enum ac_float_mode float_mode
=
5279 options
->unsafe_math
? AC_FLOAT_MODE_UNSAFE_FP_MATH
:
5280 AC_FLOAT_MODE_DEFAULT
;
5282 ac_llvm_context_init(&ctx
.ac
, ac_llvm
, options
->chip_class
,
5283 options
->family
, float_mode
, 64, 64);
5284 ctx
.context
= ctx
.ac
.context
;
5286 ctx
.is_gs_copy_shader
= true;
5287 ctx
.stage
= MESA_SHADER_VERTEX
;
5288 ctx
.shader
= geom_shader
;
5290 create_function(&ctx
, MESA_SHADER_VERTEX
, false, MESA_SHADER_VERTEX
);
5292 ac_setup_rings(&ctx
);
5294 nir_foreach_variable(variable
, &geom_shader
->outputs
) {
5295 scan_shader_output_decl(&ctx
, variable
, geom_shader
, MESA_SHADER_VERTEX
);
5296 ac_handle_shader_output_decl(&ctx
.ac
, &ctx
.abi
, geom_shader
,
5297 variable
, MESA_SHADER_VERTEX
);
5300 ac_gs_copy_shader_emit(&ctx
);
5302 LLVMBuildRetVoid(ctx
.ac
.builder
);
5304 ac_llvm_finalize_module(&ctx
, ac_llvm
->passmgr
, options
);
5306 ac_compile_llvm_module(ac_llvm
, ctx
.ac
.module
, rbinary
,
5307 MESA_SHADER_VERTEX
, "GS Copy Shader", options
);
5308 (*rbinary
)->is_gs_copy_shader
= true;