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radv: always emit a position export in gs copy shaders
[mesa.git] / src / amd / vulkan / radv_nir_to_llvm.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "radv_private.h"
29 #include "radv_shader.h"
30 #include "radv_shader_helper.h"
31 #include "nir/nir.h"
32
33 #include <llvm-c/Core.h>
34 #include <llvm-c/TargetMachine.h>
35 #include <llvm-c/Transforms/Scalar.h>
36 #include <llvm-c/Transforms/Utils.h>
37
38 #include "sid.h"
39 #include "ac_binary.h"
40 #include "ac_llvm_util.h"
41 #include "ac_llvm_build.h"
42 #include "ac_shader_abi.h"
43 #include "ac_shader_util.h"
44 #include "ac_exp_param.h"
45
46 #define RADEON_LLVM_MAX_INPUTS (VARYING_SLOT_VAR31 + 1)
47
48 struct radv_shader_context {
49 struct ac_llvm_context ac;
50 const struct radv_nir_compiler_options *options;
51 struct radv_shader_info *shader_info;
52 const struct nir_shader *shader;
53 struct ac_shader_abi abi;
54
55 unsigned max_workgroup_size;
56 LLVMContextRef context;
57 LLVMValueRef main_function;
58
59 LLVMValueRef descriptor_sets[MAX_SETS];
60 LLVMValueRef ring_offsets;
61
62 LLVMValueRef vertex_buffers;
63 LLVMValueRef rel_auto_id;
64 LLVMValueRef vs_prim_id;
65 LLVMValueRef es2gs_offset;
66
67 LLVMValueRef oc_lds;
68 LLVMValueRef merged_wave_info;
69 LLVMValueRef tess_factor_offset;
70 LLVMValueRef tes_rel_patch_id;
71 LLVMValueRef tes_u;
72 LLVMValueRef tes_v;
73
74 /* HW GS */
75 /* On gfx10:
76 * - bits 0..10: ordered_wave_id
77 * - bits 12..20: number of vertices in group
78 * - bits 22..30: number of primitives in group
79 */
80 LLVMValueRef gs_tg_info;
81 LLVMValueRef gs2vs_offset;
82 LLVMValueRef gs_wave_id;
83 LLVMValueRef gs_vtx_offset[6];
84
85 LLVMValueRef esgs_ring;
86 LLVMValueRef gsvs_ring[4];
87 LLVMValueRef hs_ring_tess_offchip;
88 LLVMValueRef hs_ring_tess_factor;
89
90 /* Streamout */
91 LLVMValueRef streamout_buffers;
92 LLVMValueRef streamout_write_idx;
93 LLVMValueRef streamout_config;
94 LLVMValueRef streamout_offset[4];
95
96 gl_shader_stage stage;
97
98 LLVMValueRef inputs[RADEON_LLVM_MAX_INPUTS * 4];
99
100 uint64_t output_mask;
101
102 bool is_gs_copy_shader;
103 LLVMValueRef gs_next_vertex[4];
104 LLVMValueRef gs_curprim_verts[4];
105 LLVMValueRef gs_generated_prims[4];
106 LLVMValueRef gs_ngg_emit;
107 LLVMValueRef gs_ngg_scratch;
108
109 uint32_t tcs_num_inputs;
110 uint32_t tcs_num_patches;
111
112 LLVMValueRef vertexptr; /* GFX10 only */
113 };
114
115 struct radv_shader_output_values {
116 LLVMValueRef values[4];
117 unsigned slot_name;
118 unsigned slot_index;
119 unsigned usage_mask;
120 };
121
122 enum radeon_llvm_calling_convention {
123 RADEON_LLVM_AMDGPU_VS = 87,
124 RADEON_LLVM_AMDGPU_GS = 88,
125 RADEON_LLVM_AMDGPU_PS = 89,
126 RADEON_LLVM_AMDGPU_CS = 90,
127 RADEON_LLVM_AMDGPU_HS = 93,
128 };
129
130 static inline struct radv_shader_context *
131 radv_shader_context_from_abi(struct ac_shader_abi *abi)
132 {
133 struct radv_shader_context *ctx = NULL;
134 return container_of(abi, ctx, abi);
135 }
136
137 static LLVMValueRef get_rel_patch_id(struct radv_shader_context *ctx)
138 {
139 switch (ctx->stage) {
140 case MESA_SHADER_TESS_CTRL:
141 return ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
142 case MESA_SHADER_TESS_EVAL:
143 return ctx->tes_rel_patch_id;
144 break;
145 default:
146 unreachable("Illegal stage");
147 }
148 }
149
150 static unsigned
151 get_tcs_num_patches(struct radv_shader_context *ctx)
152 {
153 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
154 unsigned num_tcs_output_cp = ctx->shader->info.tess.tcs_vertices_out;
155 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
156 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
157 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->tcs.outputs_written);
158 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->tcs.patch_outputs_written);
159 uint32_t output_vertex_size = num_tcs_outputs * 16;
160 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
161 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
162 unsigned num_patches;
163 unsigned hardware_lds_size;
164
165 /* Ensure that we only need one wave per SIMD so we don't need to check
166 * resource usage. Also ensures that the number of tcs in and out
167 * vertices per threadgroup are at most 256.
168 */
169 num_patches = 64 / MAX2(num_tcs_input_cp, num_tcs_output_cp) * 4;
170 /* Make sure that the data fits in LDS. This assumes the shaders only
171 * use LDS for the inputs and outputs.
172 */
173 hardware_lds_size = 32768;
174
175 /* Looks like STONEY hangs if we use more than 32 KiB LDS in a single
176 * threadgroup, even though there is more than 32 KiB LDS.
177 *
178 * Test: dEQP-VK.tessellation.shader_input_output.barrier
179 */
180 if (ctx->options->chip_class >= GFX7 && ctx->options->family != CHIP_STONEY)
181 hardware_lds_size = 65536;
182
183 num_patches = MIN2(num_patches, hardware_lds_size / (input_patch_size + output_patch_size));
184 /* Make sure the output data fits in the offchip buffer */
185 num_patches = MIN2(num_patches, (ctx->options->tess_offchip_block_dw_size * 4) / output_patch_size);
186 /* Not necessary for correctness, but improves performance. The
187 * specific value is taken from the proprietary driver.
188 */
189 num_patches = MIN2(num_patches, 40);
190
191 /* GFX6 bug workaround - limit LS-HS threadgroups to only one wave. */
192 if (ctx->options->chip_class == GFX6) {
193 unsigned one_wave = ctx->options->wave_size / MAX2(num_tcs_input_cp, num_tcs_output_cp);
194 num_patches = MIN2(num_patches, one_wave);
195 }
196 return num_patches;
197 }
198
199 static unsigned
200 calculate_tess_lds_size(struct radv_shader_context *ctx)
201 {
202 unsigned num_tcs_input_cp = ctx->options->key.tcs.input_vertices;
203 unsigned num_tcs_output_cp;
204 unsigned num_tcs_outputs, num_tcs_patch_outputs;
205 unsigned input_vertex_size, output_vertex_size;
206 unsigned input_patch_size, output_patch_size;
207 unsigned pervertex_output_patch_size;
208 unsigned output_patch0_offset;
209 unsigned num_patches;
210 unsigned lds_size;
211
212 num_tcs_output_cp = ctx->shader->info.tess.tcs_vertices_out;
213 num_tcs_outputs = util_last_bit64(ctx->shader_info->tcs.outputs_written);
214 num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->tcs.patch_outputs_written);
215
216 input_vertex_size = ctx->tcs_num_inputs * 16;
217 output_vertex_size = num_tcs_outputs * 16;
218
219 input_patch_size = num_tcs_input_cp * input_vertex_size;
220
221 pervertex_output_patch_size = num_tcs_output_cp * output_vertex_size;
222 output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
223
224 num_patches = ctx->tcs_num_patches;
225 output_patch0_offset = input_patch_size * num_patches;
226
227 lds_size = output_patch0_offset + output_patch_size * num_patches;
228 return lds_size;
229 }
230
231 /* Tessellation shaders pass outputs to the next shader using LDS.
232 *
233 * LS outputs = TCS inputs
234 * TCS outputs = TES inputs
235 *
236 * The LDS layout is:
237 * - TCS inputs for patch 0
238 * - TCS inputs for patch 1
239 * - TCS inputs for patch 2 = get_tcs_in_current_patch_offset (if RelPatchID==2)
240 * - ...
241 * - TCS outputs for patch 0 = get_tcs_out_patch0_offset
242 * - Per-patch TCS outputs for patch 0 = get_tcs_out_patch0_patch_data_offset
243 * - TCS outputs for patch 1
244 * - Per-patch TCS outputs for patch 1
245 * - TCS outputs for patch 2 = get_tcs_out_current_patch_offset (if RelPatchID==2)
246 * - Per-patch TCS outputs for patch 2 = get_tcs_out_current_patch_data_offset (if RelPatchID==2)
247 * - ...
248 *
249 * All three shaders VS(LS), TCS, TES share the same LDS space.
250 */
251 static LLVMValueRef
252 get_tcs_in_patch_stride(struct radv_shader_context *ctx)
253 {
254 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
255 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
256 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
257
258 input_patch_size /= 4;
259 return LLVMConstInt(ctx->ac.i32, input_patch_size, false);
260 }
261
262 static LLVMValueRef
263 get_tcs_out_patch_stride(struct radv_shader_context *ctx)
264 {
265 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->tcs.outputs_written);
266 uint32_t num_tcs_patch_outputs = util_last_bit64(ctx->shader_info->tcs.patch_outputs_written);
267 uint32_t output_vertex_size = num_tcs_outputs * 16;
268 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
269 uint32_t output_patch_size = pervertex_output_patch_size + num_tcs_patch_outputs * 16;
270 output_patch_size /= 4;
271 return LLVMConstInt(ctx->ac.i32, output_patch_size, false);
272 }
273
274 static LLVMValueRef
275 get_tcs_out_vertex_stride(struct radv_shader_context *ctx)
276 {
277 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->tcs.outputs_written);
278 uint32_t output_vertex_size = num_tcs_outputs * 16;
279 output_vertex_size /= 4;
280 return LLVMConstInt(ctx->ac.i32, output_vertex_size, false);
281 }
282
283 static LLVMValueRef
284 get_tcs_out_patch0_offset(struct radv_shader_context *ctx)
285 {
286 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
287 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
288 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
289 uint32_t output_patch0_offset = input_patch_size;
290 unsigned num_patches = ctx->tcs_num_patches;
291
292 output_patch0_offset *= num_patches;
293 output_patch0_offset /= 4;
294 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
295 }
296
297 static LLVMValueRef
298 get_tcs_out_patch0_patch_data_offset(struct radv_shader_context *ctx)
299 {
300 assert (ctx->stage == MESA_SHADER_TESS_CTRL);
301 uint32_t input_vertex_size = ctx->tcs_num_inputs * 16;
302 uint32_t input_patch_size = ctx->options->key.tcs.input_vertices * input_vertex_size;
303 uint32_t output_patch0_offset = input_patch_size;
304
305 uint32_t num_tcs_outputs = util_last_bit64(ctx->shader_info->tcs.outputs_written);
306 uint32_t output_vertex_size = num_tcs_outputs * 16;
307 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
308 unsigned num_patches = ctx->tcs_num_patches;
309
310 output_patch0_offset *= num_patches;
311 output_patch0_offset += pervertex_output_patch_size;
312 output_patch0_offset /= 4;
313 return LLVMConstInt(ctx->ac.i32, output_patch0_offset, false);
314 }
315
316 static LLVMValueRef
317 get_tcs_in_current_patch_offset(struct radv_shader_context *ctx)
318 {
319 LLVMValueRef patch_stride = get_tcs_in_patch_stride(ctx);
320 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
321
322 return LLVMBuildMul(ctx->ac.builder, patch_stride, rel_patch_id, "");
323 }
324
325 static LLVMValueRef
326 get_tcs_out_current_patch_offset(struct radv_shader_context *ctx)
327 {
328 LLVMValueRef patch0_offset = get_tcs_out_patch0_offset(ctx);
329 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
330 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
331
332 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
333 patch0_offset);
334 }
335
336 static LLVMValueRef
337 get_tcs_out_current_patch_data_offset(struct radv_shader_context *ctx)
338 {
339 LLVMValueRef patch0_patch_data_offset =
340 get_tcs_out_patch0_patch_data_offset(ctx);
341 LLVMValueRef patch_stride = get_tcs_out_patch_stride(ctx);
342 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
343
344 return ac_build_imad(&ctx->ac, patch_stride, rel_patch_id,
345 patch0_patch_data_offset);
346 }
347
348 #define MAX_ARGS 64
349 struct arg_info {
350 LLVMTypeRef types[MAX_ARGS];
351 LLVMValueRef *assign[MAX_ARGS];
352 uint8_t count;
353 uint8_t sgpr_count;
354 uint8_t num_sgprs_used;
355 uint8_t num_vgprs_used;
356 };
357
358 enum ac_arg_regfile {
359 ARG_SGPR,
360 ARG_VGPR,
361 };
362
363 static void
364 add_arg(struct arg_info *info, enum ac_arg_regfile regfile, LLVMTypeRef type,
365 LLVMValueRef *param_ptr)
366 {
367 assert(info->count < MAX_ARGS);
368
369 info->assign[info->count] = param_ptr;
370 info->types[info->count] = type;
371 info->count++;
372
373 if (regfile == ARG_SGPR) {
374 info->num_sgprs_used += ac_get_type_size(type) / 4;
375 info->sgpr_count++;
376 } else {
377 assert(regfile == ARG_VGPR);
378 info->num_vgprs_used += ac_get_type_size(type) / 4;
379 }
380 }
381
382 static void assign_arguments(LLVMValueRef main_function,
383 struct arg_info *info)
384 {
385 unsigned i;
386 for (i = 0; i < info->count; i++) {
387 if (info->assign[i])
388 *info->assign[i] = LLVMGetParam(main_function, i);
389 }
390 }
391
392 static LLVMValueRef
393 create_llvm_function(LLVMContextRef ctx, LLVMModuleRef module,
394 LLVMBuilderRef builder, LLVMTypeRef *return_types,
395 unsigned num_return_elems,
396 struct arg_info *args,
397 unsigned max_workgroup_size,
398 const struct radv_nir_compiler_options *options)
399 {
400 LLVMTypeRef main_function_type, ret_type;
401 LLVMBasicBlockRef main_function_body;
402
403 if (num_return_elems)
404 ret_type = LLVMStructTypeInContext(ctx, return_types,
405 num_return_elems, true);
406 else
407 ret_type = LLVMVoidTypeInContext(ctx);
408
409 /* Setup the function */
410 main_function_type =
411 LLVMFunctionType(ret_type, args->types, args->count, 0);
412 LLVMValueRef main_function =
413 LLVMAddFunction(module, "main", main_function_type);
414 main_function_body =
415 LLVMAppendBasicBlockInContext(ctx, main_function, "main_body");
416 LLVMPositionBuilderAtEnd(builder, main_function_body);
417
418 LLVMSetFunctionCallConv(main_function, RADEON_LLVM_AMDGPU_CS);
419 for (unsigned i = 0; i < args->sgpr_count; ++i) {
420 LLVMValueRef P = LLVMGetParam(main_function, i);
421
422 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_INREG);
423
424 if (LLVMGetTypeKind(LLVMTypeOf(P)) == LLVMPointerTypeKind) {
425 ac_add_function_attr(ctx, main_function, i + 1, AC_FUNC_ATTR_NOALIAS);
426 ac_add_attr_dereferenceable(P, UINT64_MAX);
427 }
428 }
429
430 if (options->address32_hi) {
431 ac_llvm_add_target_dep_function_attr(main_function,
432 "amdgpu-32bit-address-high-bits",
433 options->address32_hi);
434 }
435
436 ac_llvm_set_workgroup_size(main_function, max_workgroup_size);
437
438 if (options->unsafe_math) {
439 /* These were copied from some LLVM test. */
440 LLVMAddTargetDependentFunctionAttr(main_function,
441 "less-precise-fpmad",
442 "true");
443 LLVMAddTargetDependentFunctionAttr(main_function,
444 "no-infs-fp-math",
445 "true");
446 LLVMAddTargetDependentFunctionAttr(main_function,
447 "no-nans-fp-math",
448 "true");
449 LLVMAddTargetDependentFunctionAttr(main_function,
450 "unsafe-fp-math",
451 "true");
452 LLVMAddTargetDependentFunctionAttr(main_function,
453 "no-signed-zeros-fp-math",
454 "true");
455 }
456 return main_function;
457 }
458
459
460 static void
461 set_loc(struct radv_userdata_info *ud_info, uint8_t *sgpr_idx,
462 uint8_t num_sgprs)
463 {
464 ud_info->sgpr_idx = *sgpr_idx;
465 ud_info->num_sgprs = num_sgprs;
466 *sgpr_idx += num_sgprs;
467 }
468
469 static void
470 set_loc_shader(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx,
471 uint8_t num_sgprs)
472 {
473 struct radv_userdata_info *ud_info =
474 &ctx->shader_info->user_sgprs_locs.shader_data[idx];
475 assert(ud_info);
476
477 set_loc(ud_info, sgpr_idx, num_sgprs);
478 }
479
480 static void
481 set_loc_shader_ptr(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx)
482 {
483 bool use_32bit_pointers = idx != AC_UD_SCRATCH_RING_OFFSETS;
484
485 set_loc_shader(ctx, idx, sgpr_idx, use_32bit_pointers ? 1 : 2);
486 }
487
488 static void
489 set_loc_desc(struct radv_shader_context *ctx, int idx, uint8_t *sgpr_idx)
490 {
491 struct radv_userdata_locations *locs =
492 &ctx->shader_info->user_sgprs_locs;
493 struct radv_userdata_info *ud_info = &locs->descriptor_sets[idx];
494 assert(ud_info);
495
496 set_loc(ud_info, sgpr_idx, 1);
497
498 locs->descriptor_sets_enabled |= 1 << idx;
499 }
500
501 struct user_sgpr_info {
502 bool need_ring_offsets;
503 bool indirect_all_descriptor_sets;
504 uint8_t remaining_sgprs;
505 };
506
507 static bool needs_view_index_sgpr(struct radv_shader_context *ctx,
508 gl_shader_stage stage)
509 {
510 switch (stage) {
511 case MESA_SHADER_VERTEX:
512 if (ctx->shader_info->needs_multiview_view_index ||
513 (!ctx->options->key.vs_common_out.as_es && !ctx->options->key.vs_common_out.as_ls && ctx->options->key.has_multiview_view_index))
514 return true;
515 break;
516 case MESA_SHADER_TESS_EVAL:
517 if (ctx->shader_info->needs_multiview_view_index || (!ctx->options->key.vs_common_out.as_es && ctx->options->key.has_multiview_view_index))
518 return true;
519 break;
520 case MESA_SHADER_GEOMETRY:
521 case MESA_SHADER_TESS_CTRL:
522 if (ctx->shader_info->needs_multiview_view_index)
523 return true;
524 break;
525 default:
526 break;
527 }
528 return false;
529 }
530
531 static uint8_t
532 count_vs_user_sgprs(struct radv_shader_context *ctx)
533 {
534 uint8_t count = 0;
535
536 if (ctx->shader_info->vs.has_vertex_buffers)
537 count++;
538 count += ctx->shader_info->vs.needs_draw_id ? 3 : 2;
539
540 return count;
541 }
542
543 static void allocate_inline_push_consts(struct radv_shader_context *ctx,
544 struct user_sgpr_info *user_sgpr_info)
545 {
546 uint8_t remaining_sgprs = user_sgpr_info->remaining_sgprs;
547
548 /* Only supported if shaders use push constants. */
549 if (ctx->shader_info->min_push_constant_used == UINT8_MAX)
550 return;
551
552 /* Only supported if shaders don't have indirect push constants. */
553 if (ctx->shader_info->has_indirect_push_constants)
554 return;
555
556 /* Only supported for 32-bit push constants. */
557 if (!ctx->shader_info->has_only_32bit_push_constants)
558 return;
559
560 uint8_t num_push_consts =
561 (ctx->shader_info->max_push_constant_used -
562 ctx->shader_info->min_push_constant_used) / 4;
563
564 /* Check if the number of user SGPRs is large enough. */
565 if (num_push_consts < remaining_sgprs) {
566 ctx->shader_info->num_inline_push_consts = num_push_consts;
567 } else {
568 ctx->shader_info->num_inline_push_consts = remaining_sgprs;
569 }
570
571 /* Clamp to the maximum number of allowed inlined push constants. */
572 if (ctx->shader_info->num_inline_push_consts > AC_MAX_INLINE_PUSH_CONSTS)
573 ctx->shader_info->num_inline_push_consts = AC_MAX_INLINE_PUSH_CONSTS;
574
575 if (ctx->shader_info->num_inline_push_consts == num_push_consts &&
576 !ctx->shader_info->loads_dynamic_offsets) {
577 /* Disable the default push constants path if all constants are
578 * inlined and if shaders don't use dynamic descriptors.
579 */
580 ctx->shader_info->loads_push_constants = false;
581 }
582
583 ctx->shader_info->base_inline_push_consts =
584 ctx->shader_info->min_push_constant_used / 4;
585 }
586
587 static void allocate_user_sgprs(struct radv_shader_context *ctx,
588 gl_shader_stage stage,
589 bool has_previous_stage,
590 gl_shader_stage previous_stage,
591 bool needs_view_index,
592 struct user_sgpr_info *user_sgpr_info)
593 {
594 uint8_t user_sgpr_count = 0;
595
596 memset(user_sgpr_info, 0, sizeof(struct user_sgpr_info));
597
598 /* until we sort out scratch/global buffers always assign ring offsets for gs/vs/es */
599 if (stage == MESA_SHADER_GEOMETRY ||
600 stage == MESA_SHADER_VERTEX ||
601 stage == MESA_SHADER_TESS_CTRL ||
602 stage == MESA_SHADER_TESS_EVAL ||
603 ctx->is_gs_copy_shader)
604 user_sgpr_info->need_ring_offsets = true;
605
606 if (stage == MESA_SHADER_FRAGMENT &&
607 ctx->shader_info->ps.needs_sample_positions)
608 user_sgpr_info->need_ring_offsets = true;
609
610 /* 2 user sgprs will nearly always be allocated for scratch/rings */
611 if (ctx->options->supports_spill || user_sgpr_info->need_ring_offsets) {
612 user_sgpr_count += 2;
613 }
614
615 switch (stage) {
616 case MESA_SHADER_COMPUTE:
617 if (ctx->shader_info->cs.uses_grid_size)
618 user_sgpr_count += 3;
619 break;
620 case MESA_SHADER_FRAGMENT:
621 user_sgpr_count += ctx->shader_info->ps.needs_sample_positions;
622 break;
623 case MESA_SHADER_VERTEX:
624 if (!ctx->is_gs_copy_shader)
625 user_sgpr_count += count_vs_user_sgprs(ctx);
626 break;
627 case MESA_SHADER_TESS_CTRL:
628 if (has_previous_stage) {
629 if (previous_stage == MESA_SHADER_VERTEX)
630 user_sgpr_count += count_vs_user_sgprs(ctx);
631 }
632 break;
633 case MESA_SHADER_TESS_EVAL:
634 break;
635 case MESA_SHADER_GEOMETRY:
636 if (has_previous_stage) {
637 if (previous_stage == MESA_SHADER_VERTEX) {
638 user_sgpr_count += count_vs_user_sgprs(ctx);
639 }
640 }
641 break;
642 default:
643 break;
644 }
645
646 if (needs_view_index)
647 user_sgpr_count++;
648
649 if (ctx->shader_info->loads_push_constants)
650 user_sgpr_count++;
651
652 if (ctx->shader_info->so.num_outputs)
653 user_sgpr_count++;
654
655 uint32_t available_sgprs = ctx->options->chip_class >= GFX9 && stage != MESA_SHADER_COMPUTE ? 32 : 16;
656 uint32_t remaining_sgprs = available_sgprs - user_sgpr_count;
657 uint32_t num_desc_set =
658 util_bitcount(ctx->shader_info->desc_set_used_mask);
659
660 if (remaining_sgprs < num_desc_set) {
661 user_sgpr_info->indirect_all_descriptor_sets = true;
662 user_sgpr_info->remaining_sgprs = remaining_sgprs - 1;
663 } else {
664 user_sgpr_info->remaining_sgprs = remaining_sgprs - num_desc_set;
665 }
666
667 allocate_inline_push_consts(ctx, user_sgpr_info);
668 }
669
670 static void
671 declare_global_input_sgprs(struct radv_shader_context *ctx,
672 const struct user_sgpr_info *user_sgpr_info,
673 struct arg_info *args,
674 LLVMValueRef *desc_sets)
675 {
676 LLVMTypeRef type = ac_array_in_const32_addr_space(ctx->ac.i8);
677
678 /* 1 for each descriptor set */
679 if (!user_sgpr_info->indirect_all_descriptor_sets) {
680 uint32_t mask = ctx->shader_info->desc_set_used_mask;
681
682 while (mask) {
683 int i = u_bit_scan(&mask);
684
685 add_arg(args, ARG_SGPR, type, &ctx->descriptor_sets[i]);
686 }
687 } else {
688 add_arg(args, ARG_SGPR, ac_array_in_const32_addr_space(type),
689 desc_sets);
690 }
691
692 if (ctx->shader_info->loads_push_constants) {
693 /* 1 for push constants and dynamic descriptors */
694 add_arg(args, ARG_SGPR, type, &ctx->abi.push_constants);
695 }
696
697 for (unsigned i = 0; i < ctx->shader_info->num_inline_push_consts; i++) {
698 add_arg(args, ARG_SGPR, ctx->ac.i32,
699 &ctx->abi.inline_push_consts[i]);
700 }
701 ctx->abi.num_inline_push_consts = ctx->shader_info->num_inline_push_consts;
702 ctx->abi.base_inline_push_consts = ctx->shader_info->base_inline_push_consts;
703
704 if (ctx->shader_info->so.num_outputs) {
705 add_arg(args, ARG_SGPR,
706 ac_array_in_const32_addr_space(ctx->ac.v4i32),
707 &ctx->streamout_buffers);
708 }
709 }
710
711 static void
712 declare_vs_specific_input_sgprs(struct radv_shader_context *ctx,
713 gl_shader_stage stage,
714 bool has_previous_stage,
715 gl_shader_stage previous_stage,
716 struct arg_info *args)
717 {
718 if (!ctx->is_gs_copy_shader &&
719 (stage == MESA_SHADER_VERTEX ||
720 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
721 if (ctx->shader_info->vs.has_vertex_buffers) {
722 add_arg(args, ARG_SGPR,
723 ac_array_in_const32_addr_space(ctx->ac.v4i32),
724 &ctx->vertex_buffers);
725 }
726 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.base_vertex);
727 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.start_instance);
728 if (ctx->shader_info->vs.needs_draw_id) {
729 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->abi.draw_id);
730 }
731 }
732 }
733
734 static void
735 declare_vs_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
736 {
737 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.vertex_id);
738 if (!ctx->is_gs_copy_shader) {
739 if (ctx->options->key.vs_common_out.as_ls) {
740 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->rel_auto_id);
741 if (ctx->ac.chip_class >= GFX10) {
742 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* user vgpr */
743 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
744 } else {
745 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
746 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
747 }
748 } else {
749 if (ctx->ac.chip_class >= GFX10) {
750 if (ctx->options->key.vs_common_out.as_ngg) {
751 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* user vgpr */
752 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* user vgpr */
753 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
754 } else {
755 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
756 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
757 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
758 }
759 } else {
760 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.instance_id);
761 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->vs_prim_id);
762 add_arg(args, ARG_VGPR, ctx->ac.i32, NULL); /* unused */
763 }
764 }
765 }
766 }
767
768 static void
769 declare_streamout_sgprs(struct radv_shader_context *ctx, gl_shader_stage stage,
770 struct arg_info *args)
771 {
772 int i;
773
774 if (ctx->options->use_ngg_streamout)
775 return;
776
777 /* Streamout SGPRs. */
778 if (ctx->shader_info->so.num_outputs) {
779 assert(stage == MESA_SHADER_VERTEX ||
780 stage == MESA_SHADER_TESS_EVAL);
781
782 if (stage != MESA_SHADER_TESS_EVAL) {
783 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->streamout_config);
784 } else {
785 args->assign[args->count - 1] = &ctx->streamout_config;
786 args->types[args->count - 1] = ctx->ac.i32;
787 }
788
789 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->streamout_write_idx);
790 }
791
792 /* A streamout buffer offset is loaded if the stride is non-zero. */
793 for (i = 0; i < 4; i++) {
794 if (!ctx->shader_info->so.strides[i])
795 continue;
796
797 add_arg(args, ARG_SGPR, ctx->ac.i32, &ctx->streamout_offset[i]);
798 }
799 }
800
801 static void
802 declare_tes_input_vgprs(struct radv_shader_context *ctx, struct arg_info *args)
803 {
804 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_u);
805 add_arg(args, ARG_VGPR, ctx->ac.f32, &ctx->tes_v);
806 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->tes_rel_patch_id);
807 add_arg(args, ARG_VGPR, ctx->ac.i32, &ctx->abi.tes_patch_id);
808 }
809
810 static void
811 set_global_input_locs(struct radv_shader_context *ctx,
812 const struct user_sgpr_info *user_sgpr_info,
813 LLVMValueRef desc_sets, uint8_t *user_sgpr_idx)
814 {
815 uint32_t mask = ctx->shader_info->desc_set_used_mask;
816
817 if (!user_sgpr_info->indirect_all_descriptor_sets) {
818 while (mask) {
819 int i = u_bit_scan(&mask);
820
821 set_loc_desc(ctx, i, user_sgpr_idx);
822 }
823 } else {
824 set_loc_shader_ptr(ctx, AC_UD_INDIRECT_DESCRIPTOR_SETS,
825 user_sgpr_idx);
826
827 while (mask) {
828 int i = u_bit_scan(&mask);
829
830 ctx->descriptor_sets[i] =
831 ac_build_load_to_sgpr(&ctx->ac, desc_sets,
832 LLVMConstInt(ctx->ac.i32, i, false));
833
834 }
835
836 ctx->shader_info->need_indirect_descriptor_sets = true;
837 }
838
839 if (ctx->shader_info->loads_push_constants) {
840 set_loc_shader_ptr(ctx, AC_UD_PUSH_CONSTANTS, user_sgpr_idx);
841 }
842
843 if (ctx->shader_info->num_inline_push_consts) {
844 set_loc_shader(ctx, AC_UD_INLINE_PUSH_CONSTANTS, user_sgpr_idx,
845 ctx->shader_info->num_inline_push_consts);
846 }
847
848 if (ctx->streamout_buffers) {
849 set_loc_shader_ptr(ctx, AC_UD_STREAMOUT_BUFFERS,
850 user_sgpr_idx);
851 }
852 }
853
854 static void
855 set_vs_specific_input_locs(struct radv_shader_context *ctx,
856 gl_shader_stage stage, bool has_previous_stage,
857 gl_shader_stage previous_stage,
858 uint8_t *user_sgpr_idx)
859 {
860 if (!ctx->is_gs_copy_shader &&
861 (stage == MESA_SHADER_VERTEX ||
862 (has_previous_stage && previous_stage == MESA_SHADER_VERTEX))) {
863 if (ctx->shader_info->vs.has_vertex_buffers) {
864 set_loc_shader_ptr(ctx, AC_UD_VS_VERTEX_BUFFERS,
865 user_sgpr_idx);
866 }
867
868 unsigned vs_num = 2;
869 if (ctx->shader_info->vs.needs_draw_id)
870 vs_num++;
871
872 set_loc_shader(ctx, AC_UD_VS_BASE_VERTEX_START_INSTANCE,
873 user_sgpr_idx, vs_num);
874 }
875 }
876
877 static void set_llvm_calling_convention(LLVMValueRef func,
878 gl_shader_stage stage)
879 {
880 enum radeon_llvm_calling_convention calling_conv;
881
882 switch (stage) {
883 case MESA_SHADER_VERTEX:
884 case MESA_SHADER_TESS_EVAL:
885 calling_conv = RADEON_LLVM_AMDGPU_VS;
886 break;
887 case MESA_SHADER_GEOMETRY:
888 calling_conv = RADEON_LLVM_AMDGPU_GS;
889 break;
890 case MESA_SHADER_TESS_CTRL:
891 calling_conv = RADEON_LLVM_AMDGPU_HS;
892 break;
893 case MESA_SHADER_FRAGMENT:
894 calling_conv = RADEON_LLVM_AMDGPU_PS;
895 break;
896 case MESA_SHADER_COMPUTE:
897 calling_conv = RADEON_LLVM_AMDGPU_CS;
898 break;
899 default:
900 unreachable("Unhandle shader type");
901 }
902
903 LLVMSetFunctionCallConv(func, calling_conv);
904 }
905
906 /* Returns whether the stage is a stage that can be directly before the GS */
907 static bool is_pre_gs_stage(gl_shader_stage stage)
908 {
909 return stage == MESA_SHADER_VERTEX || stage == MESA_SHADER_TESS_EVAL;
910 }
911
912 static void create_function(struct radv_shader_context *ctx,
913 gl_shader_stage stage,
914 bool has_previous_stage,
915 gl_shader_stage previous_stage)
916 {
917 uint8_t user_sgpr_idx;
918 struct user_sgpr_info user_sgpr_info;
919 struct arg_info args = {};
920 LLVMValueRef desc_sets;
921 bool needs_view_index = needs_view_index_sgpr(ctx, stage);
922
923 if (ctx->ac.chip_class >= GFX10) {
924 if (is_pre_gs_stage(stage) && ctx->options->key.vs_common_out.as_ngg) {
925 /* On GFX10, VS is merged into GS for NGG. */
926 previous_stage = stage;
927 stage = MESA_SHADER_GEOMETRY;
928 has_previous_stage = true;
929 }
930 }
931
932 allocate_user_sgprs(ctx, stage, has_previous_stage,
933 previous_stage, needs_view_index, &user_sgpr_info);
934
935 if (user_sgpr_info.need_ring_offsets && !ctx->options->supports_spill) {
936 add_arg(&args, ARG_SGPR, ac_array_in_const_addr_space(ctx->ac.v4i32),
937 &ctx->ring_offsets);
938 }
939
940 switch (stage) {
941 case MESA_SHADER_COMPUTE:
942 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
943 &desc_sets);
944
945 if (ctx->shader_info->cs.uses_grid_size) {
946 add_arg(&args, ARG_SGPR, ctx->ac.v3i32,
947 &ctx->abi.num_work_groups);
948 }
949
950 for (int i = 0; i < 3; i++) {
951 ctx->abi.workgroup_ids[i] = NULL;
952 if (ctx->shader_info->cs.uses_block_id[i]) {
953 add_arg(&args, ARG_SGPR, ctx->ac.i32,
954 &ctx->abi.workgroup_ids[i]);
955 }
956 }
957
958 if (ctx->shader_info->cs.uses_local_invocation_idx)
959 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.tg_size);
960 add_arg(&args, ARG_VGPR, ctx->ac.v3i32,
961 &ctx->abi.local_invocation_ids);
962 break;
963 case MESA_SHADER_VERTEX:
964 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
965 &desc_sets);
966
967 declare_vs_specific_input_sgprs(ctx, stage, has_previous_stage,
968 previous_stage, &args);
969
970 if (needs_view_index)
971 add_arg(&args, ARG_SGPR, ctx->ac.i32,
972 &ctx->abi.view_index);
973 if (ctx->options->key.vs_common_out.as_es) {
974 add_arg(&args, ARG_SGPR, ctx->ac.i32,
975 &ctx->es2gs_offset);
976 } else if (ctx->options->key.vs_common_out.as_ls) {
977 /* no extra parameters */
978 } else {
979 declare_streamout_sgprs(ctx, stage, &args);
980 }
981
982 declare_vs_input_vgprs(ctx, &args);
983 break;
984 case MESA_SHADER_TESS_CTRL:
985 if (has_previous_stage) {
986 // First 6 system regs
987 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
988 add_arg(&args, ARG_SGPR, ctx->ac.i32,
989 &ctx->merged_wave_info);
990 add_arg(&args, ARG_SGPR, ctx->ac.i32,
991 &ctx->tess_factor_offset);
992
993 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
994 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
995 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
996
997 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
998 &desc_sets);
999
1000 declare_vs_specific_input_sgprs(ctx, stage,
1001 has_previous_stage,
1002 previous_stage, &args);
1003
1004 if (needs_view_index)
1005 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1006 &ctx->abi.view_index);
1007
1008 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1009 &ctx->abi.tcs_patch_id);
1010 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1011 &ctx->abi.tcs_rel_ids);
1012
1013 declare_vs_input_vgprs(ctx, &args);
1014 } else {
1015 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
1016 &desc_sets);
1017
1018 if (needs_view_index)
1019 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1020 &ctx->abi.view_index);
1021
1022 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1023 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1024 &ctx->tess_factor_offset);
1025 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1026 &ctx->abi.tcs_patch_id);
1027 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1028 &ctx->abi.tcs_rel_ids);
1029 }
1030 break;
1031 case MESA_SHADER_TESS_EVAL:
1032 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
1033 &desc_sets);
1034
1035 if (needs_view_index)
1036 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1037 &ctx->abi.view_index);
1038
1039 if (ctx->options->key.vs_common_out.as_es) {
1040 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1041 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
1042 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1043 &ctx->es2gs_offset);
1044 } else {
1045 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL);
1046 declare_streamout_sgprs(ctx, stage, &args);
1047 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1048 }
1049 declare_tes_input_vgprs(ctx, &args);
1050 break;
1051 case MESA_SHADER_GEOMETRY:
1052 if (has_previous_stage) {
1053 // First 6 system regs
1054 if (ctx->options->key.vs_common_out.as_ngg) {
1055 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1056 &ctx->gs_tg_info);
1057 } else {
1058 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1059 &ctx->gs2vs_offset);
1060 }
1061
1062 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1063 &ctx->merged_wave_info);
1064 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->oc_lds);
1065
1066 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // scratch offset
1067 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
1068 add_arg(&args, ARG_SGPR, ctx->ac.i32, NULL); // unknown
1069
1070 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
1071 &desc_sets);
1072
1073 if (previous_stage != MESA_SHADER_TESS_EVAL) {
1074 declare_vs_specific_input_sgprs(ctx, stage,
1075 has_previous_stage,
1076 previous_stage,
1077 &args);
1078 }
1079
1080 if (needs_view_index)
1081 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1082 &ctx->abi.view_index);
1083
1084 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1085 &ctx->gs_vtx_offset[0]);
1086 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1087 &ctx->gs_vtx_offset[2]);
1088 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1089 &ctx->abi.gs_prim_id);
1090 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1091 &ctx->abi.gs_invocation_id);
1092 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1093 &ctx->gs_vtx_offset[4]);
1094
1095 if (previous_stage == MESA_SHADER_VERTEX) {
1096 declare_vs_input_vgprs(ctx, &args);
1097 } else {
1098 declare_tes_input_vgprs(ctx, &args);
1099 }
1100 } else {
1101 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
1102 &desc_sets);
1103
1104 if (needs_view_index)
1105 add_arg(&args, ARG_SGPR, ctx->ac.i32,
1106 &ctx->abi.view_index);
1107
1108 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs2vs_offset);
1109 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->gs_wave_id);
1110 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1111 &ctx->gs_vtx_offset[0]);
1112 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1113 &ctx->gs_vtx_offset[1]);
1114 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1115 &ctx->abi.gs_prim_id);
1116 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1117 &ctx->gs_vtx_offset[2]);
1118 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1119 &ctx->gs_vtx_offset[3]);
1120 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1121 &ctx->gs_vtx_offset[4]);
1122 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1123 &ctx->gs_vtx_offset[5]);
1124 add_arg(&args, ARG_VGPR, ctx->ac.i32,
1125 &ctx->abi.gs_invocation_id);
1126 }
1127 break;
1128 case MESA_SHADER_FRAGMENT:
1129 declare_global_input_sgprs(ctx, &user_sgpr_info, &args,
1130 &desc_sets);
1131
1132 add_arg(&args, ARG_SGPR, ctx->ac.i32, &ctx->abi.prim_mask);
1133 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->abi.persp_sample);
1134 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->abi.persp_center);
1135 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->abi.persp_centroid);
1136 add_arg(&args, ARG_VGPR, ctx->ac.v3i32, NULL); /* persp pull model */
1137 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->abi.linear_sample);
1138 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->abi.linear_center);
1139 add_arg(&args, ARG_VGPR, ctx->ac.v2i32, &ctx->abi.linear_centroid);
1140 add_arg(&args, ARG_VGPR, ctx->ac.f32, NULL); /* line stipple tex */
1141 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[0]);
1142 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[1]);
1143 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[2]);
1144 add_arg(&args, ARG_VGPR, ctx->ac.f32, &ctx->abi.frag_pos[3]);
1145 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.front_face);
1146 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.ancillary);
1147 add_arg(&args, ARG_VGPR, ctx->ac.i32, &ctx->abi.sample_coverage);
1148 add_arg(&args, ARG_VGPR, ctx->ac.i32, NULL); /* fixed pt */
1149 break;
1150 default:
1151 unreachable("Shader stage not implemented");
1152 }
1153
1154 ctx->main_function = create_llvm_function(
1155 ctx->context, ctx->ac.module, ctx->ac.builder, NULL, 0, &args,
1156 ctx->max_workgroup_size, ctx->options);
1157 set_llvm_calling_convention(ctx->main_function, stage);
1158
1159
1160 ctx->shader_info->num_input_vgprs = 0;
1161 ctx->shader_info->num_input_sgprs = ctx->options->supports_spill ? 2 : 0;
1162
1163 ctx->shader_info->num_input_sgprs += args.num_sgprs_used;
1164
1165 if (ctx->stage != MESA_SHADER_FRAGMENT)
1166 ctx->shader_info->num_input_vgprs = args.num_vgprs_used;
1167
1168 assign_arguments(ctx->main_function, &args);
1169
1170 user_sgpr_idx = 0;
1171
1172 if (ctx->options->supports_spill || user_sgpr_info.need_ring_offsets) {
1173 set_loc_shader_ptr(ctx, AC_UD_SCRATCH_RING_OFFSETS,
1174 &user_sgpr_idx);
1175 if (ctx->options->supports_spill) {
1176 ctx->ring_offsets = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.implicit.buffer.ptr",
1177 LLVMPointerType(ctx->ac.i8, AC_ADDR_SPACE_CONST),
1178 NULL, 0, AC_FUNC_ATTR_READNONE);
1179 ctx->ring_offsets = LLVMBuildBitCast(ctx->ac.builder, ctx->ring_offsets,
1180 ac_array_in_const_addr_space(ctx->ac.v4i32), "");
1181 }
1182 }
1183
1184 /* For merged shaders the user SGPRs start at 8, with 8 system SGPRs in front (including
1185 * the rw_buffers at s0/s1. With user SGPR0 = s8, lets restart the count from 0 */
1186 if (has_previous_stage)
1187 user_sgpr_idx = 0;
1188
1189 set_global_input_locs(ctx, &user_sgpr_info, desc_sets, &user_sgpr_idx);
1190
1191 switch (stage) {
1192 case MESA_SHADER_COMPUTE:
1193 if (ctx->shader_info->cs.uses_grid_size) {
1194 set_loc_shader(ctx, AC_UD_CS_GRID_SIZE,
1195 &user_sgpr_idx, 3);
1196 }
1197 break;
1198 case MESA_SHADER_VERTEX:
1199 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1200 previous_stage, &user_sgpr_idx);
1201 if (ctx->abi.view_index)
1202 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1203 break;
1204 case MESA_SHADER_TESS_CTRL:
1205 set_vs_specific_input_locs(ctx, stage, has_previous_stage,
1206 previous_stage, &user_sgpr_idx);
1207 if (ctx->abi.view_index)
1208 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1209 break;
1210 case MESA_SHADER_TESS_EVAL:
1211 if (ctx->abi.view_index)
1212 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1213 break;
1214 case MESA_SHADER_GEOMETRY:
1215 if (has_previous_stage) {
1216 if (previous_stage == MESA_SHADER_VERTEX)
1217 set_vs_specific_input_locs(ctx, stage,
1218 has_previous_stage,
1219 previous_stage,
1220 &user_sgpr_idx);
1221 }
1222 if (ctx->abi.view_index)
1223 set_loc_shader(ctx, AC_UD_VIEW_INDEX, &user_sgpr_idx, 1);
1224 break;
1225 case MESA_SHADER_FRAGMENT:
1226 break;
1227 default:
1228 unreachable("Shader stage not implemented");
1229 }
1230
1231 if (stage == MESA_SHADER_TESS_CTRL ||
1232 (stage == MESA_SHADER_VERTEX && ctx->options->key.vs_common_out.as_ls) ||
1233 /* GFX9 has the ESGS ring buffer in LDS. */
1234 (stage == MESA_SHADER_GEOMETRY && has_previous_stage)) {
1235 ac_declare_lds_as_pointer(&ctx->ac);
1236 }
1237
1238 ctx->shader_info->num_user_sgprs = user_sgpr_idx;
1239 }
1240
1241
1242 static LLVMValueRef
1243 radv_load_resource(struct ac_shader_abi *abi, LLVMValueRef index,
1244 unsigned desc_set, unsigned binding)
1245 {
1246 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1247 LLVMValueRef desc_ptr = ctx->descriptor_sets[desc_set];
1248 struct radv_pipeline_layout *pipeline_layout = ctx->options->layout;
1249 struct radv_descriptor_set_layout *layout = pipeline_layout->set[desc_set].layout;
1250 unsigned base_offset = layout->binding[binding].offset;
1251 LLVMValueRef offset, stride;
1252
1253 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_UNIFORM_BUFFER_DYNAMIC ||
1254 layout->binding[binding].type == VK_DESCRIPTOR_TYPE_STORAGE_BUFFER_DYNAMIC) {
1255 unsigned idx = pipeline_layout->set[desc_set].dynamic_offset_start +
1256 layout->binding[binding].dynamic_offset_offset;
1257 desc_ptr = ctx->abi.push_constants;
1258 base_offset = pipeline_layout->push_constant_size + 16 * idx;
1259 stride = LLVMConstInt(ctx->ac.i32, 16, false);
1260 } else
1261 stride = LLVMConstInt(ctx->ac.i32, layout->binding[binding].size, false);
1262
1263 offset = LLVMConstInt(ctx->ac.i32, base_offset, false);
1264
1265 if (layout->binding[binding].type != VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
1266 offset = ac_build_imad(&ctx->ac, index, stride, offset);
1267 }
1268
1269 desc_ptr = LLVMBuildGEP(ctx->ac.builder, desc_ptr, &offset, 1, "");
1270 desc_ptr = ac_cast_ptr(&ctx->ac, desc_ptr, ctx->ac.v4i32);
1271 LLVMSetMetadata(desc_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1272
1273 if (layout->binding[binding].type == VK_DESCRIPTOR_TYPE_INLINE_UNIFORM_BLOCK_EXT) {
1274 uint32_t desc_type = S_008F0C_DST_SEL_X(V_008F0C_SQ_SEL_X) |
1275 S_008F0C_DST_SEL_Y(V_008F0C_SQ_SEL_Y) |
1276 S_008F0C_DST_SEL_Z(V_008F0C_SQ_SEL_Z) |
1277 S_008F0C_DST_SEL_W(V_008F0C_SQ_SEL_W);
1278
1279 if (ctx->ac.chip_class >= GFX10) {
1280 desc_type |= S_008F0C_FORMAT(V_008F0C_IMG_FORMAT_32_FLOAT) |
1281 S_008F0C_OOB_SELECT(3) |
1282 S_008F0C_RESOURCE_LEVEL(1);
1283 } else {
1284 desc_type |= S_008F0C_NUM_FORMAT(V_008F0C_BUF_NUM_FORMAT_FLOAT) |
1285 S_008F0C_DATA_FORMAT(V_008F0C_BUF_DATA_FORMAT_32);
1286 }
1287
1288 LLVMValueRef desc_components[4] = {
1289 LLVMBuildPtrToInt(ctx->ac.builder, desc_ptr, ctx->ac.intptr, ""),
1290 LLVMConstInt(ctx->ac.i32, S_008F04_BASE_ADDRESS_HI(ctx->options->address32_hi), false),
1291 /* High limit to support variable sizes. */
1292 LLVMConstInt(ctx->ac.i32, 0xffffffff, false),
1293 LLVMConstInt(ctx->ac.i32, desc_type, false),
1294 };
1295
1296 return ac_build_gather_values(&ctx->ac, desc_components, 4);
1297 }
1298
1299 return desc_ptr;
1300 }
1301
1302
1303 /* The offchip buffer layout for TCS->TES is
1304 *
1305 * - attribute 0 of patch 0 vertex 0
1306 * - attribute 0 of patch 0 vertex 1
1307 * - attribute 0 of patch 0 vertex 2
1308 * ...
1309 * - attribute 0 of patch 1 vertex 0
1310 * - attribute 0 of patch 1 vertex 1
1311 * ...
1312 * - attribute 1 of patch 0 vertex 0
1313 * - attribute 1 of patch 0 vertex 1
1314 * ...
1315 * - per patch attribute 0 of patch 0
1316 * - per patch attribute 0 of patch 1
1317 * ...
1318 *
1319 * Note that every attribute has 4 components.
1320 */
1321 static LLVMValueRef get_non_vertex_index_offset(struct radv_shader_context *ctx)
1322 {
1323 uint32_t num_patches = ctx->tcs_num_patches;
1324 uint32_t num_tcs_outputs;
1325 if (ctx->stage == MESA_SHADER_TESS_CTRL)
1326 num_tcs_outputs = util_last_bit64(ctx->shader_info->tcs.outputs_written);
1327 else
1328 num_tcs_outputs = ctx->options->key.tes.tcs_num_outputs;
1329
1330 uint32_t output_vertex_size = num_tcs_outputs * 16;
1331 uint32_t pervertex_output_patch_size = ctx->shader->info.tess.tcs_vertices_out * output_vertex_size;
1332
1333 return LLVMConstInt(ctx->ac.i32, pervertex_output_patch_size * num_patches, false);
1334 }
1335
1336 static LLVMValueRef calc_param_stride(struct radv_shader_context *ctx,
1337 LLVMValueRef vertex_index)
1338 {
1339 LLVMValueRef param_stride;
1340 if (vertex_index)
1341 param_stride = LLVMConstInt(ctx->ac.i32, ctx->shader->info.tess.tcs_vertices_out * ctx->tcs_num_patches, false);
1342 else
1343 param_stride = LLVMConstInt(ctx->ac.i32, ctx->tcs_num_patches, false);
1344 return param_stride;
1345 }
1346
1347 static LLVMValueRef get_tcs_tes_buffer_address(struct radv_shader_context *ctx,
1348 LLVMValueRef vertex_index,
1349 LLVMValueRef param_index)
1350 {
1351 LLVMValueRef base_addr;
1352 LLVMValueRef param_stride, constant16;
1353 LLVMValueRef rel_patch_id = get_rel_patch_id(ctx);
1354 LLVMValueRef vertices_per_patch = LLVMConstInt(ctx->ac.i32, ctx->shader->info.tess.tcs_vertices_out, false);
1355 constant16 = LLVMConstInt(ctx->ac.i32, 16, false);
1356 param_stride = calc_param_stride(ctx, vertex_index);
1357 if (vertex_index) {
1358 base_addr = ac_build_imad(&ctx->ac, rel_patch_id,
1359 vertices_per_patch, vertex_index);
1360 } else {
1361 base_addr = rel_patch_id;
1362 }
1363
1364 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1365 LLVMBuildMul(ctx->ac.builder, param_index,
1366 param_stride, ""), "");
1367
1368 base_addr = LLVMBuildMul(ctx->ac.builder, base_addr, constant16, "");
1369
1370 if (!vertex_index) {
1371 LLVMValueRef patch_data_offset = get_non_vertex_index_offset(ctx);
1372
1373 base_addr = LLVMBuildAdd(ctx->ac.builder, base_addr,
1374 patch_data_offset, "");
1375 }
1376 return base_addr;
1377 }
1378
1379 static LLVMValueRef get_tcs_tes_buffer_address_params(struct radv_shader_context *ctx,
1380 unsigned param,
1381 unsigned const_index,
1382 bool is_compact,
1383 LLVMValueRef vertex_index,
1384 LLVMValueRef indir_index)
1385 {
1386 LLVMValueRef param_index;
1387
1388 if (indir_index)
1389 param_index = LLVMBuildAdd(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, param, false),
1390 indir_index, "");
1391 else {
1392 if (const_index && !is_compact)
1393 param += const_index;
1394 param_index = LLVMConstInt(ctx->ac.i32, param, false);
1395 }
1396 return get_tcs_tes_buffer_address(ctx, vertex_index, param_index);
1397 }
1398
1399 static LLVMValueRef
1400 get_dw_address(struct radv_shader_context *ctx,
1401 LLVMValueRef dw_addr,
1402 unsigned param,
1403 unsigned const_index,
1404 bool compact_const_index,
1405 LLVMValueRef vertex_index,
1406 LLVMValueRef stride,
1407 LLVMValueRef indir_index)
1408
1409 {
1410
1411 if (vertex_index) {
1412 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1413 LLVMBuildMul(ctx->ac.builder,
1414 vertex_index,
1415 stride, ""), "");
1416 }
1417
1418 if (indir_index)
1419 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1420 LLVMBuildMul(ctx->ac.builder, indir_index,
1421 LLVMConstInt(ctx->ac.i32, 4, false), ""), "");
1422 else if (const_index && !compact_const_index)
1423 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1424 LLVMConstInt(ctx->ac.i32, const_index * 4, false), "");
1425
1426 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1427 LLVMConstInt(ctx->ac.i32, param * 4, false), "");
1428
1429 if (const_index && compact_const_index)
1430 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1431 LLVMConstInt(ctx->ac.i32, const_index, false), "");
1432 return dw_addr;
1433 }
1434
1435 static LLVMValueRef
1436 load_tcs_varyings(struct ac_shader_abi *abi,
1437 LLVMTypeRef type,
1438 LLVMValueRef vertex_index,
1439 LLVMValueRef indir_index,
1440 unsigned const_index,
1441 unsigned location,
1442 unsigned driver_location,
1443 unsigned component,
1444 unsigned num_components,
1445 bool is_patch,
1446 bool is_compact,
1447 bool load_input)
1448 {
1449 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1450 LLVMValueRef dw_addr, stride;
1451 LLVMValueRef value[4], result;
1452 unsigned param = shader_io_get_unique_index(location);
1453
1454 if (load_input) {
1455 uint32_t input_vertex_size = (ctx->tcs_num_inputs * 16) / 4;
1456 stride = LLVMConstInt(ctx->ac.i32, input_vertex_size, false);
1457 dw_addr = get_tcs_in_current_patch_offset(ctx);
1458 } else {
1459 if (!is_patch) {
1460 stride = get_tcs_out_vertex_stride(ctx);
1461 dw_addr = get_tcs_out_current_patch_offset(ctx);
1462 } else {
1463 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1464 stride = NULL;
1465 }
1466 }
1467
1468 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1469 indir_index);
1470
1471 for (unsigned i = 0; i < num_components + component; i++) {
1472 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1473 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1474 ctx->ac.i32_1, "");
1475 }
1476 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1477 return result;
1478 }
1479
1480 static void
1481 store_tcs_output(struct ac_shader_abi *abi,
1482 const nir_variable *var,
1483 LLVMValueRef vertex_index,
1484 LLVMValueRef param_index,
1485 unsigned const_index,
1486 LLVMValueRef src,
1487 unsigned writemask)
1488 {
1489 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1490 const unsigned location = var->data.location;
1491 unsigned component = var->data.location_frac;
1492 const bool is_patch = var->data.patch;
1493 const bool is_compact = var->data.compact;
1494 LLVMValueRef dw_addr;
1495 LLVMValueRef stride = NULL;
1496 LLVMValueRef buf_addr = NULL;
1497 unsigned param;
1498 bool store_lds = true;
1499
1500 if (is_patch) {
1501 if (!(ctx->shader->info.patch_outputs_read & (1U << (location - VARYING_SLOT_PATCH0))))
1502 store_lds = false;
1503 } else {
1504 if (!(ctx->shader->info.outputs_read & (1ULL << location)))
1505 store_lds = false;
1506 }
1507
1508 param = shader_io_get_unique_index(location);
1509 if ((location == VARYING_SLOT_CLIP_DIST0 || location == VARYING_SLOT_CLIP_DIST1) && is_compact) {
1510 const_index += component;
1511 component = 0;
1512
1513 if (const_index >= 4) {
1514 const_index -= 4;
1515 param++;
1516 }
1517 }
1518
1519 if (!is_patch) {
1520 stride = get_tcs_out_vertex_stride(ctx);
1521 dw_addr = get_tcs_out_current_patch_offset(ctx);
1522 } else {
1523 dw_addr = get_tcs_out_current_patch_data_offset(ctx);
1524 }
1525
1526 dw_addr = get_dw_address(ctx, dw_addr, param, const_index, is_compact, vertex_index, stride,
1527 param_index);
1528 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index, is_compact,
1529 vertex_index, param_index);
1530
1531 bool is_tess_factor = false;
1532 if (location == VARYING_SLOT_TESS_LEVEL_INNER ||
1533 location == VARYING_SLOT_TESS_LEVEL_OUTER)
1534 is_tess_factor = true;
1535
1536 unsigned base = is_compact ? const_index : 0;
1537 for (unsigned chan = 0; chan < 8; chan++) {
1538 if (!(writemask & (1 << chan)))
1539 continue;
1540 LLVMValueRef value = ac_llvm_extract_elem(&ctx->ac, src, chan - component);
1541 value = ac_to_integer(&ctx->ac, value);
1542 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
1543
1544 if (store_lds || is_tess_factor) {
1545 LLVMValueRef dw_addr_chan =
1546 LLVMBuildAdd(ctx->ac.builder, dw_addr,
1547 LLVMConstInt(ctx->ac.i32, chan, false), "");
1548 ac_lds_store(&ctx->ac, dw_addr_chan, value);
1549 }
1550
1551 if (!is_tess_factor && writemask != 0xF)
1552 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, value, 1,
1553 buf_addr, ctx->oc_lds,
1554 4 * (base + chan), ac_glc, false);
1555 }
1556
1557 if (writemask == 0xF) {
1558 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, src, 4,
1559 buf_addr, ctx->oc_lds,
1560 (base * 4), ac_glc, false);
1561 }
1562 }
1563
1564 static LLVMValueRef
1565 load_tes_input(struct ac_shader_abi *abi,
1566 LLVMTypeRef type,
1567 LLVMValueRef vertex_index,
1568 LLVMValueRef param_index,
1569 unsigned const_index,
1570 unsigned location,
1571 unsigned driver_location,
1572 unsigned component,
1573 unsigned num_components,
1574 bool is_patch,
1575 bool is_compact,
1576 bool load_input)
1577 {
1578 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1579 LLVMValueRef buf_addr;
1580 LLVMValueRef result;
1581 unsigned param = shader_io_get_unique_index(location);
1582
1583 if ((location == VARYING_SLOT_CLIP_DIST0 || location == VARYING_SLOT_CLIP_DIST1) && is_compact) {
1584 const_index += component;
1585 component = 0;
1586 if (const_index >= 4) {
1587 const_index -= 4;
1588 param++;
1589 }
1590 }
1591
1592 buf_addr = get_tcs_tes_buffer_address_params(ctx, param, const_index,
1593 is_compact, vertex_index, param_index);
1594
1595 LLVMValueRef comp_offset = LLVMConstInt(ctx->ac.i32, component * 4, false);
1596 buf_addr = LLVMBuildAdd(ctx->ac.builder, buf_addr, comp_offset, "");
1597
1598 result = ac_build_buffer_load(&ctx->ac, ctx->hs_ring_tess_offchip, num_components, NULL,
1599 buf_addr, ctx->oc_lds, is_compact ? (4 * const_index) : 0, ac_glc, true, false);
1600 result = ac_trim_vector(&ctx->ac, result, num_components);
1601 return result;
1602 }
1603
1604 static LLVMValueRef
1605 load_gs_input(struct ac_shader_abi *abi,
1606 unsigned location,
1607 unsigned driver_location,
1608 unsigned component,
1609 unsigned num_components,
1610 unsigned vertex_index,
1611 unsigned const_index,
1612 LLVMTypeRef type)
1613 {
1614 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1615 LLVMValueRef vtx_offset;
1616 unsigned param, vtx_offset_param;
1617 LLVMValueRef value[4], result;
1618
1619 vtx_offset_param = vertex_index;
1620 assert(vtx_offset_param < 6);
1621 vtx_offset = LLVMBuildMul(ctx->ac.builder, ctx->gs_vtx_offset[vtx_offset_param],
1622 LLVMConstInt(ctx->ac.i32, 4, false), "");
1623
1624 param = shader_io_get_unique_index(location);
1625
1626 for (unsigned i = component; i < num_components + component; i++) {
1627 if (ctx->ac.chip_class >= GFX9) {
1628 LLVMValueRef dw_addr = ctx->gs_vtx_offset[vtx_offset_param];
1629 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr,
1630 LLVMConstInt(ctx->ac.i32, param * 4 + i + const_index, 0), "");
1631 value[i] = ac_lds_load(&ctx->ac, dw_addr);
1632 } else {
1633 LLVMValueRef soffset =
1634 LLVMConstInt(ctx->ac.i32,
1635 (param * 4 + i + const_index) * 256,
1636 false);
1637
1638 value[i] = ac_build_buffer_load(&ctx->ac,
1639 ctx->esgs_ring, 1,
1640 ctx->ac.i32_0,
1641 vtx_offset, soffset,
1642 0, ac_glc, true, false);
1643 }
1644
1645 if (ac_get_type_size(type) == 2) {
1646 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], ctx->ac.i32, "");
1647 value[i] = LLVMBuildTrunc(ctx->ac.builder, value[i], ctx->ac.i16, "");
1648 }
1649 value[i] = LLVMBuildBitCast(ctx->ac.builder, value[i], type, "");
1650 }
1651 result = ac_build_varying_gather_values(&ctx->ac, value, num_components, component);
1652 result = ac_to_integer(&ctx->ac, result);
1653 return result;
1654 }
1655
1656
1657 static void radv_emit_kill(struct ac_shader_abi *abi, LLVMValueRef visible)
1658 {
1659 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1660 ac_build_kill_if_false(&ctx->ac, visible);
1661 }
1662
1663 static uint32_t
1664 radv_get_sample_pos_offset(uint32_t num_samples)
1665 {
1666 uint32_t sample_pos_offset = 0;
1667
1668 switch (num_samples) {
1669 case 2:
1670 sample_pos_offset = 1;
1671 break;
1672 case 4:
1673 sample_pos_offset = 3;
1674 break;
1675 case 8:
1676 sample_pos_offset = 7;
1677 break;
1678 default:
1679 break;
1680 }
1681 return sample_pos_offset;
1682 }
1683
1684 static LLVMValueRef load_sample_position(struct ac_shader_abi *abi,
1685 LLVMValueRef sample_id)
1686 {
1687 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1688
1689 LLVMValueRef result;
1690 LLVMValueRef index = LLVMConstInt(ctx->ac.i32, RING_PS_SAMPLE_POSITIONS, false);
1691 LLVMValueRef ptr = LLVMBuildGEP(ctx->ac.builder, ctx->ring_offsets, &index, 1, "");
1692
1693 ptr = LLVMBuildBitCast(ctx->ac.builder, ptr,
1694 ac_array_in_const_addr_space(ctx->ac.v2f32), "");
1695
1696 uint32_t sample_pos_offset =
1697 radv_get_sample_pos_offset(ctx->options->key.fs.num_samples);
1698
1699 sample_id =
1700 LLVMBuildAdd(ctx->ac.builder, sample_id,
1701 LLVMConstInt(ctx->ac.i32, sample_pos_offset, false), "");
1702 result = ac_build_load_invariant(&ctx->ac, ptr, sample_id);
1703
1704 return result;
1705 }
1706
1707
1708 static LLVMValueRef load_sample_mask_in(struct ac_shader_abi *abi)
1709 {
1710 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1711 uint8_t log2_ps_iter_samples;
1712
1713 if (ctx->shader_info->ps.force_persample) {
1714 log2_ps_iter_samples =
1715 util_logbase2(ctx->options->key.fs.num_samples);
1716 } else {
1717 log2_ps_iter_samples = ctx->options->key.fs.log2_ps_iter_samples;
1718 }
1719
1720 /* The bit pattern matches that used by fixed function fragment
1721 * processing. */
1722 static const uint16_t ps_iter_masks[] = {
1723 0xffff, /* not used */
1724 0x5555,
1725 0x1111,
1726 0x0101,
1727 0x0001,
1728 };
1729 assert(log2_ps_iter_samples < ARRAY_SIZE(ps_iter_masks));
1730
1731 uint32_t ps_iter_mask = ps_iter_masks[log2_ps_iter_samples];
1732
1733 LLVMValueRef result, sample_id;
1734 sample_id = ac_unpack_param(&ctx->ac, abi->ancillary, 8, 4);
1735 sample_id = LLVMBuildShl(ctx->ac.builder, LLVMConstInt(ctx->ac.i32, ps_iter_mask, false), sample_id, "");
1736 result = LLVMBuildAnd(ctx->ac.builder, sample_id, abi->sample_coverage, "");
1737 return result;
1738 }
1739
1740
1741 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context *ctx,
1742 unsigned stream,
1743 LLVMValueRef *addrs);
1744
1745 static void
1746 visit_emit_vertex(struct ac_shader_abi *abi, unsigned stream, LLVMValueRef *addrs)
1747 {
1748 LLVMValueRef gs_next_vertex;
1749 LLVMValueRef can_emit;
1750 unsigned offset = 0;
1751 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1752
1753 if (ctx->options->key.vs_common_out.as_ngg) {
1754 gfx10_ngg_gs_emit_vertex(ctx, stream, addrs);
1755 return;
1756 }
1757
1758 /* Write vertex attribute values to GSVS ring */
1759 gs_next_vertex = LLVMBuildLoad(ctx->ac.builder,
1760 ctx->gs_next_vertex[stream],
1761 "");
1762
1763 /* If this thread has already emitted the declared maximum number of
1764 * vertices, don't emit any more: excessive vertex emissions are not
1765 * supposed to have any effect.
1766 */
1767 can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT, gs_next_vertex,
1768 LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false), "");
1769
1770 bool use_kill = !ctx->shader_info->gs.writes_memory;
1771 if (use_kill)
1772 ac_build_kill_if_false(&ctx->ac, can_emit);
1773 else
1774 ac_build_ifcc(&ctx->ac, can_emit, 6505);
1775
1776 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
1777 unsigned output_usage_mask =
1778 ctx->shader_info->gs.output_usage_mask[i];
1779 uint8_t output_stream =
1780 ctx->shader_info->gs.output_streams[i];
1781 LLVMValueRef *out_ptr = &addrs[i * 4];
1782 int length = util_last_bit(output_usage_mask);
1783
1784 if (!(ctx->output_mask & (1ull << i)) ||
1785 output_stream != stream)
1786 continue;
1787
1788 for (unsigned j = 0; j < length; j++) {
1789 if (!(output_usage_mask & (1 << j)))
1790 continue;
1791
1792 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
1793 out_ptr[j], "");
1794 LLVMValueRef voffset =
1795 LLVMConstInt(ctx->ac.i32, offset *
1796 ctx->shader->info.gs.vertices_out, false);
1797
1798 offset++;
1799
1800 voffset = LLVMBuildAdd(ctx->ac.builder, voffset, gs_next_vertex, "");
1801 voffset = LLVMBuildMul(ctx->ac.builder, voffset, LLVMConstInt(ctx->ac.i32, 4, false), "");
1802
1803 out_val = ac_to_integer(&ctx->ac, out_val);
1804 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
1805
1806 ac_build_buffer_store_dword(&ctx->ac,
1807 ctx->gsvs_ring[stream],
1808 out_val, 1,
1809 voffset, ctx->gs2vs_offset, 0,
1810 ac_glc | ac_slc, true);
1811 }
1812 }
1813
1814 gs_next_vertex = LLVMBuildAdd(ctx->ac.builder, gs_next_vertex,
1815 ctx->ac.i32_1, "");
1816 LLVMBuildStore(ctx->ac.builder, gs_next_vertex, ctx->gs_next_vertex[stream]);
1817
1818 ac_build_sendmsg(&ctx->ac,
1819 AC_SENDMSG_GS_OP_EMIT | AC_SENDMSG_GS | (stream << 8),
1820 ctx->gs_wave_id);
1821
1822 if (!use_kill)
1823 ac_build_endif(&ctx->ac, 6505);
1824 }
1825
1826 static void
1827 visit_end_primitive(struct ac_shader_abi *abi, unsigned stream)
1828 {
1829 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1830
1831 if (ctx->options->key.vs_common_out.as_ngg) {
1832 LLVMBuildStore(ctx->ac.builder, ctx->ac.i32_0, ctx->gs_curprim_verts[stream]);
1833 return;
1834 }
1835
1836 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_CUT | AC_SENDMSG_GS | (stream << 8), ctx->gs_wave_id);
1837 }
1838
1839 static LLVMValueRef
1840 load_tess_coord(struct ac_shader_abi *abi)
1841 {
1842 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1843
1844 LLVMValueRef coord[4] = {
1845 ctx->tes_u,
1846 ctx->tes_v,
1847 ctx->ac.f32_0,
1848 ctx->ac.f32_0,
1849 };
1850
1851 if (ctx->shader->info.tess.primitive_mode == GL_TRIANGLES)
1852 coord[2] = LLVMBuildFSub(ctx->ac.builder, ctx->ac.f32_1,
1853 LLVMBuildFAdd(ctx->ac.builder, coord[0], coord[1], ""), "");
1854
1855 return ac_build_gather_values(&ctx->ac, coord, 3);
1856 }
1857
1858 static LLVMValueRef
1859 load_patch_vertices_in(struct ac_shader_abi *abi)
1860 {
1861 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1862 return LLVMConstInt(ctx->ac.i32, ctx->options->key.tcs.input_vertices, false);
1863 }
1864
1865
1866 static LLVMValueRef radv_load_base_vertex(struct ac_shader_abi *abi)
1867 {
1868 return abi->base_vertex;
1869 }
1870
1871 static LLVMValueRef radv_load_ssbo(struct ac_shader_abi *abi,
1872 LLVMValueRef buffer_ptr, bool write)
1873 {
1874 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1875 LLVMValueRef result;
1876
1877 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1878
1879 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1880 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1881
1882 return result;
1883 }
1884
1885 static LLVMValueRef radv_load_ubo(struct ac_shader_abi *abi, LLVMValueRef buffer_ptr)
1886 {
1887 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1888 LLVMValueRef result;
1889
1890 if (LLVMGetTypeKind(LLVMTypeOf(buffer_ptr)) != LLVMPointerTypeKind) {
1891 /* Do not load the descriptor for inlined uniform blocks. */
1892 return buffer_ptr;
1893 }
1894
1895 LLVMSetMetadata(buffer_ptr, ctx->ac.uniform_md_kind, ctx->ac.empty_md);
1896
1897 result = LLVMBuildLoad(ctx->ac.builder, buffer_ptr, "");
1898 LLVMSetMetadata(result, ctx->ac.invariant_load_md_kind, ctx->ac.empty_md);
1899
1900 return result;
1901 }
1902
1903 static LLVMValueRef radv_get_sampler_desc(struct ac_shader_abi *abi,
1904 unsigned descriptor_set,
1905 unsigned base_index,
1906 unsigned constant_index,
1907 LLVMValueRef index,
1908 enum ac_descriptor_type desc_type,
1909 bool image, bool write,
1910 bool bindless)
1911 {
1912 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
1913 LLVMValueRef list = ctx->descriptor_sets[descriptor_set];
1914 struct radv_descriptor_set_layout *layout = ctx->options->layout->set[descriptor_set].layout;
1915 struct radv_descriptor_set_binding_layout *binding = layout->binding + base_index;
1916 unsigned offset = binding->offset;
1917 unsigned stride = binding->size;
1918 unsigned type_size;
1919 LLVMBuilderRef builder = ctx->ac.builder;
1920 LLVMTypeRef type;
1921
1922 assert(base_index < layout->binding_count);
1923
1924 switch (desc_type) {
1925 case AC_DESC_IMAGE:
1926 type = ctx->ac.v8i32;
1927 type_size = 32;
1928 break;
1929 case AC_DESC_FMASK:
1930 type = ctx->ac.v8i32;
1931 offset += 32;
1932 type_size = 32;
1933 break;
1934 case AC_DESC_SAMPLER:
1935 type = ctx->ac.v4i32;
1936 if (binding->type == VK_DESCRIPTOR_TYPE_COMBINED_IMAGE_SAMPLER) {
1937 offset += radv_combined_image_descriptor_sampler_offset(binding);
1938 }
1939
1940 type_size = 16;
1941 break;
1942 case AC_DESC_BUFFER:
1943 type = ctx->ac.v4i32;
1944 type_size = 16;
1945 break;
1946 case AC_DESC_PLANE_0:
1947 case AC_DESC_PLANE_1:
1948 case AC_DESC_PLANE_2:
1949 type = ctx->ac.v8i32;
1950 type_size = 32;
1951 offset += 32 * (desc_type - AC_DESC_PLANE_0);
1952 break;
1953 default:
1954 unreachable("invalid desc_type\n");
1955 }
1956
1957 offset += constant_index * stride;
1958
1959 if (desc_type == AC_DESC_SAMPLER && binding->immutable_samplers_offset &&
1960 (!index || binding->immutable_samplers_equal)) {
1961 if (binding->immutable_samplers_equal)
1962 constant_index = 0;
1963
1964 const uint32_t *samplers = radv_immutable_samplers(layout, binding);
1965
1966 LLVMValueRef constants[] = {
1967 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 0], 0),
1968 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 1], 0),
1969 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 2], 0),
1970 LLVMConstInt(ctx->ac.i32, samplers[constant_index * 4 + 3], 0),
1971 };
1972 return ac_build_gather_values(&ctx->ac, constants, 4);
1973 }
1974
1975 assert(stride % type_size == 0);
1976
1977 LLVMValueRef adjusted_index = index;
1978 if (!adjusted_index)
1979 adjusted_index = ctx->ac.i32_0;
1980
1981 adjusted_index = LLVMBuildMul(builder, adjusted_index, LLVMConstInt(ctx->ac.i32, stride / type_size, 0), "");
1982
1983 LLVMValueRef val_offset = LLVMConstInt(ctx->ac.i32, offset, 0);
1984 list = LLVMBuildGEP(builder, list, &val_offset, 1, "");
1985 list = LLVMBuildPointerCast(builder, list,
1986 ac_array_in_const32_addr_space(type), "");
1987
1988 LLVMValueRef descriptor = ac_build_load_to_sgpr(&ctx->ac, list, adjusted_index);
1989
1990 /* 3 plane formats always have same size and format for plane 1 & 2, so
1991 * use the tail from plane 1 so that we can store only the first 16 bytes
1992 * of the last plane. */
1993 if (desc_type == AC_DESC_PLANE_2) {
1994 LLVMValueRef descriptor2 = radv_get_sampler_desc(abi, descriptor_set, base_index, constant_index, index, AC_DESC_PLANE_1,image, write, bindless);
1995
1996 LLVMValueRef components[8];
1997 for (unsigned i = 0; i < 4; ++i)
1998 components[i] = ac_llvm_extract_elem(&ctx->ac, descriptor, i);
1999
2000 for (unsigned i = 4; i < 8; ++i)
2001 components[i] = ac_llvm_extract_elem(&ctx->ac, descriptor2, i);
2002 descriptor = ac_build_gather_values(&ctx->ac, components, 8);
2003 }
2004
2005 return descriptor;
2006 }
2007
2008 /* For 2_10_10_10 formats the alpha is handled as unsigned by pre-vega HW.
2009 * so we may need to fix it up. */
2010 static LLVMValueRef
2011 adjust_vertex_fetch_alpha(struct radv_shader_context *ctx,
2012 unsigned adjustment,
2013 LLVMValueRef alpha)
2014 {
2015 if (adjustment == RADV_ALPHA_ADJUST_NONE)
2016 return alpha;
2017
2018 LLVMValueRef c30 = LLVMConstInt(ctx->ac.i32, 30, 0);
2019
2020 alpha = LLVMBuildBitCast(ctx->ac.builder, alpha, ctx->ac.f32, "");
2021
2022 if (adjustment == RADV_ALPHA_ADJUST_SSCALED)
2023 alpha = LLVMBuildFPToUI(ctx->ac.builder, alpha, ctx->ac.i32, "");
2024 else
2025 alpha = ac_to_integer(&ctx->ac, alpha);
2026
2027 /* For the integer-like cases, do a natural sign extension.
2028 *
2029 * For the SNORM case, the values are 0.0, 0.333, 0.666, 1.0
2030 * and happen to contain 0, 1, 2, 3 as the two LSBs of the
2031 * exponent.
2032 */
2033 alpha = LLVMBuildShl(ctx->ac.builder, alpha,
2034 adjustment == RADV_ALPHA_ADJUST_SNORM ?
2035 LLVMConstInt(ctx->ac.i32, 7, 0) : c30, "");
2036 alpha = LLVMBuildAShr(ctx->ac.builder, alpha, c30, "");
2037
2038 /* Convert back to the right type. */
2039 if (adjustment == RADV_ALPHA_ADJUST_SNORM) {
2040 LLVMValueRef clamp;
2041 LLVMValueRef neg_one = LLVMConstReal(ctx->ac.f32, -1.0);
2042 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
2043 clamp = LLVMBuildFCmp(ctx->ac.builder, LLVMRealULT, alpha, neg_one, "");
2044 alpha = LLVMBuildSelect(ctx->ac.builder, clamp, neg_one, alpha, "");
2045 } else if (adjustment == RADV_ALPHA_ADJUST_SSCALED) {
2046 alpha = LLVMBuildSIToFP(ctx->ac.builder, alpha, ctx->ac.f32, "");
2047 }
2048
2049 return LLVMBuildBitCast(ctx->ac.builder, alpha, ctx->ac.i32, "");
2050 }
2051
2052 static unsigned
2053 get_num_channels_from_data_format(unsigned data_format)
2054 {
2055 switch (data_format) {
2056 case V_008F0C_BUF_DATA_FORMAT_8:
2057 case V_008F0C_BUF_DATA_FORMAT_16:
2058 case V_008F0C_BUF_DATA_FORMAT_32:
2059 return 1;
2060 case V_008F0C_BUF_DATA_FORMAT_8_8:
2061 case V_008F0C_BUF_DATA_FORMAT_16_16:
2062 case V_008F0C_BUF_DATA_FORMAT_32_32:
2063 return 2;
2064 case V_008F0C_BUF_DATA_FORMAT_10_11_11:
2065 case V_008F0C_BUF_DATA_FORMAT_11_11_10:
2066 case V_008F0C_BUF_DATA_FORMAT_32_32_32:
2067 return 3;
2068 case V_008F0C_BUF_DATA_FORMAT_8_8_8_8:
2069 case V_008F0C_BUF_DATA_FORMAT_10_10_10_2:
2070 case V_008F0C_BUF_DATA_FORMAT_2_10_10_10:
2071 case V_008F0C_BUF_DATA_FORMAT_16_16_16_16:
2072 case V_008F0C_BUF_DATA_FORMAT_32_32_32_32:
2073 return 4;
2074 default:
2075 break;
2076 }
2077
2078 return 4;
2079 }
2080
2081 static LLVMValueRef
2082 radv_fixup_vertex_input_fetches(struct radv_shader_context *ctx,
2083 LLVMValueRef value,
2084 unsigned num_channels,
2085 bool is_float)
2086 {
2087 LLVMValueRef zero = is_float ? ctx->ac.f32_0 : ctx->ac.i32_0;
2088 LLVMValueRef one = is_float ? ctx->ac.f32_1 : ctx->ac.i32_1;
2089 LLVMValueRef chan[4];
2090
2091 if (LLVMGetTypeKind(LLVMTypeOf(value)) == LLVMVectorTypeKind) {
2092 unsigned vec_size = LLVMGetVectorSize(LLVMTypeOf(value));
2093
2094 if (num_channels == 4 && num_channels == vec_size)
2095 return value;
2096
2097 num_channels = MIN2(num_channels, vec_size);
2098
2099 for (unsigned i = 0; i < num_channels; i++)
2100 chan[i] = ac_llvm_extract_elem(&ctx->ac, value, i);
2101 } else {
2102 if (num_channels) {
2103 assert(num_channels == 1);
2104 chan[0] = value;
2105 }
2106 }
2107
2108 for (unsigned i = num_channels; i < 4; i++) {
2109 chan[i] = i == 3 ? one : zero;
2110 chan[i] = ac_to_integer(&ctx->ac, chan[i]);
2111 }
2112
2113 return ac_build_gather_values(&ctx->ac, chan, 4);
2114 }
2115
2116 static void
2117 handle_vs_input_decl(struct radv_shader_context *ctx,
2118 struct nir_variable *variable)
2119 {
2120 LLVMValueRef t_list_ptr = ctx->vertex_buffers;
2121 LLVMValueRef t_offset;
2122 LLVMValueRef t_list;
2123 LLVMValueRef input;
2124 LLVMValueRef buffer_index;
2125 unsigned attrib_count = glsl_count_attribute_slots(variable->type, true);
2126 uint8_t input_usage_mask =
2127 ctx->shader_info->vs.input_usage_mask[variable->data.location];
2128 unsigned num_input_channels = util_last_bit(input_usage_mask);
2129
2130 variable->data.driver_location = variable->data.location * 4;
2131
2132 enum glsl_base_type type = glsl_get_base_type(variable->type);
2133 for (unsigned i = 0; i < attrib_count; ++i) {
2134 LLVMValueRef output[4];
2135 unsigned attrib_index = variable->data.location + i - VERT_ATTRIB_GENERIC0;
2136 unsigned attrib_format = ctx->options->key.vs.vertex_attribute_formats[attrib_index];
2137 unsigned data_format = attrib_format & 0x0f;
2138 unsigned num_format = (attrib_format >> 4) & 0x07;
2139 bool is_float = num_format != V_008F0C_BUF_NUM_FORMAT_UINT &&
2140 num_format != V_008F0C_BUF_NUM_FORMAT_SINT;
2141
2142 if (ctx->options->key.vs.instance_rate_inputs & (1u << attrib_index)) {
2143 uint32_t divisor = ctx->options->key.vs.instance_rate_divisors[attrib_index];
2144
2145 if (divisor) {
2146 buffer_index = ctx->abi.instance_id;
2147
2148 if (divisor != 1) {
2149 buffer_index = LLVMBuildUDiv(ctx->ac.builder, buffer_index,
2150 LLVMConstInt(ctx->ac.i32, divisor, 0), "");
2151 }
2152 } else {
2153 buffer_index = ctx->ac.i32_0;
2154 }
2155
2156 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.start_instance, buffer_index, "");
2157 } else
2158 buffer_index = LLVMBuildAdd(ctx->ac.builder, ctx->abi.vertex_id,
2159 ctx->abi.base_vertex, "");
2160
2161 /* Adjust the number of channels to load based on the vertex
2162 * attribute format.
2163 */
2164 unsigned num_format_channels = get_num_channels_from_data_format(data_format);
2165 unsigned num_channels = MIN2(num_input_channels, num_format_channels);
2166 unsigned attrib_binding = ctx->options->key.vs.vertex_attribute_bindings[attrib_index];
2167 unsigned attrib_offset = ctx->options->key.vs.vertex_attribute_offsets[attrib_index];
2168 unsigned attrib_stride = ctx->options->key.vs.vertex_attribute_strides[attrib_index];
2169
2170 if (ctx->options->key.vs.post_shuffle & (1 << attrib_index)) {
2171 /* Always load, at least, 3 channels for formats that
2172 * need to be shuffled because X<->Z.
2173 */
2174 num_channels = MAX2(num_channels, 3);
2175 }
2176
2177 if (attrib_stride != 0 && attrib_offset > attrib_stride) {
2178 LLVMValueRef buffer_offset =
2179 LLVMConstInt(ctx->ac.i32,
2180 attrib_offset / attrib_stride, false);
2181
2182 buffer_index = LLVMBuildAdd(ctx->ac.builder,
2183 buffer_index,
2184 buffer_offset, "");
2185
2186 attrib_offset = attrib_offset % attrib_stride;
2187 }
2188
2189 t_offset = LLVMConstInt(ctx->ac.i32, attrib_binding, false);
2190 t_list = ac_build_load_to_sgpr(&ctx->ac, t_list_ptr, t_offset);
2191
2192 input = ac_build_struct_tbuffer_load(&ctx->ac, t_list,
2193 buffer_index,
2194 LLVMConstInt(ctx->ac.i32, attrib_offset, false),
2195 ctx->ac.i32_0, ctx->ac.i32_0,
2196 num_channels,
2197 data_format, num_format, 0, true);
2198
2199 if (ctx->options->key.vs.post_shuffle & (1 << attrib_index)) {
2200 LLVMValueRef c[4];
2201 c[0] = ac_llvm_extract_elem(&ctx->ac, input, 2);
2202 c[1] = ac_llvm_extract_elem(&ctx->ac, input, 1);
2203 c[2] = ac_llvm_extract_elem(&ctx->ac, input, 0);
2204 c[3] = ac_llvm_extract_elem(&ctx->ac, input, 3);
2205
2206 input = ac_build_gather_values(&ctx->ac, c, 4);
2207 }
2208
2209 input = radv_fixup_vertex_input_fetches(ctx, input, num_channels,
2210 is_float);
2211
2212 for (unsigned chan = 0; chan < 4; chan++) {
2213 LLVMValueRef llvm_chan = LLVMConstInt(ctx->ac.i32, chan, false);
2214 output[chan] = LLVMBuildExtractElement(ctx->ac.builder, input, llvm_chan, "");
2215 if (type == GLSL_TYPE_FLOAT16) {
2216 output[chan] = LLVMBuildBitCast(ctx->ac.builder, output[chan], ctx->ac.f32, "");
2217 output[chan] = LLVMBuildFPTrunc(ctx->ac.builder, output[chan], ctx->ac.f16, "");
2218 }
2219 }
2220
2221 unsigned alpha_adjust = (ctx->options->key.vs.alpha_adjust >> (attrib_index * 2)) & 3;
2222 output[3] = adjust_vertex_fetch_alpha(ctx, alpha_adjust, output[3]);
2223
2224 for (unsigned chan = 0; chan < 4; chan++) {
2225 output[chan] = ac_to_integer(&ctx->ac, output[chan]);
2226 if (type == GLSL_TYPE_UINT16 || type == GLSL_TYPE_INT16)
2227 output[chan] = LLVMBuildTrunc(ctx->ac.builder, output[chan], ctx->ac.i16, "");
2228
2229 ctx->inputs[ac_llvm_reg_index_soa(variable->data.location + i, chan)] = output[chan];
2230 }
2231 }
2232 }
2233
2234 static void
2235 handle_vs_inputs(struct radv_shader_context *ctx,
2236 struct nir_shader *nir) {
2237 nir_foreach_variable(variable, &nir->inputs)
2238 handle_vs_input_decl(ctx, variable);
2239 }
2240
2241 static void
2242 prepare_interp_optimize(struct radv_shader_context *ctx,
2243 struct nir_shader *nir)
2244 {
2245 bool uses_center = false;
2246 bool uses_centroid = false;
2247 nir_foreach_variable(variable, &nir->inputs) {
2248 if (glsl_get_base_type(glsl_without_array(variable->type)) != GLSL_TYPE_FLOAT ||
2249 variable->data.sample)
2250 continue;
2251
2252 if (variable->data.centroid)
2253 uses_centroid = true;
2254 else
2255 uses_center = true;
2256 }
2257
2258 if (uses_center && uses_centroid) {
2259 LLVMValueRef sel = LLVMBuildICmp(ctx->ac.builder, LLVMIntSLT, ctx->abi.prim_mask, ctx->ac.i32_0, "");
2260 ctx->abi.persp_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->abi.persp_center, ctx->abi.persp_centroid, "");
2261 ctx->abi.linear_centroid = LLVMBuildSelect(ctx->ac.builder, sel, ctx->abi.linear_center, ctx->abi.linear_centroid, "");
2262 }
2263 }
2264
2265 static void
2266 scan_shader_output_decl(struct radv_shader_context *ctx,
2267 struct nir_variable *variable,
2268 struct nir_shader *shader,
2269 gl_shader_stage stage)
2270 {
2271 int idx = variable->data.location + variable->data.index;
2272 unsigned attrib_count = glsl_count_attribute_slots(variable->type, false);
2273 uint64_t mask_attribs;
2274
2275 variable->data.driver_location = idx * 4;
2276
2277 /* tess ctrl has it's own load/store paths for outputs */
2278 if (stage == MESA_SHADER_TESS_CTRL)
2279 return;
2280
2281 if (variable->data.compact) {
2282 unsigned component_count = variable->data.location_frac +
2283 glsl_get_length(variable->type);
2284 attrib_count = (component_count + 3) / 4;
2285 }
2286
2287 mask_attribs = ((1ull << attrib_count) - 1) << idx;
2288
2289 ctx->output_mask |= mask_attribs;
2290 }
2291
2292
2293 /* Initialize arguments for the shader export intrinsic */
2294 static void
2295 si_llvm_init_export_args(struct radv_shader_context *ctx,
2296 LLVMValueRef *values,
2297 unsigned enabled_channels,
2298 unsigned target,
2299 struct ac_export_args *args)
2300 {
2301 /* Specify the channels that are enabled. */
2302 args->enabled_channels = enabled_channels;
2303
2304 /* Specify whether the EXEC mask represents the valid mask */
2305 args->valid_mask = 0;
2306
2307 /* Specify whether this is the last export */
2308 args->done = 0;
2309
2310 /* Specify the target we are exporting */
2311 args->target = target;
2312
2313 args->compr = false;
2314 args->out[0] = LLVMGetUndef(ctx->ac.f32);
2315 args->out[1] = LLVMGetUndef(ctx->ac.f32);
2316 args->out[2] = LLVMGetUndef(ctx->ac.f32);
2317 args->out[3] = LLVMGetUndef(ctx->ac.f32);
2318
2319 if (!values)
2320 return;
2321
2322 bool is_16bit = ac_get_type_size(LLVMTypeOf(values[0])) == 2;
2323 if (ctx->stage == MESA_SHADER_FRAGMENT) {
2324 unsigned index = target - V_008DFC_SQ_EXP_MRT;
2325 unsigned col_format = (ctx->options->key.fs.col_format >> (4 * index)) & 0xf;
2326 bool is_int8 = (ctx->options->key.fs.is_int8 >> index) & 1;
2327 bool is_int10 = (ctx->options->key.fs.is_int10 >> index) & 1;
2328 unsigned chan;
2329
2330 LLVMValueRef (*packf)(struct ac_llvm_context *ctx, LLVMValueRef args[2]) = NULL;
2331 LLVMValueRef (*packi)(struct ac_llvm_context *ctx, LLVMValueRef args[2],
2332 unsigned bits, bool hi) = NULL;
2333
2334 switch(col_format) {
2335 case V_028714_SPI_SHADER_ZERO:
2336 args->enabled_channels = 0; /* writemask */
2337 args->target = V_008DFC_SQ_EXP_NULL;
2338 break;
2339
2340 case V_028714_SPI_SHADER_32_R:
2341 args->enabled_channels = 1;
2342 args->out[0] = values[0];
2343 break;
2344
2345 case V_028714_SPI_SHADER_32_GR:
2346 args->enabled_channels = 0x3;
2347 args->out[0] = values[0];
2348 args->out[1] = values[1];
2349 break;
2350
2351 case V_028714_SPI_SHADER_32_AR:
2352 if (ctx->ac.chip_class >= GFX10) {
2353 args->enabled_channels = 0x3;
2354 args->out[0] = values[0];
2355 args->out[1] = values[3];
2356 } else {
2357 args->enabled_channels = 0x9;
2358 args->out[0] = values[0];
2359 args->out[3] = values[3];
2360 }
2361 break;
2362
2363 case V_028714_SPI_SHADER_FP16_ABGR:
2364 args->enabled_channels = 0x5;
2365 packf = ac_build_cvt_pkrtz_f16;
2366 if (is_16bit) {
2367 for (unsigned chan = 0; chan < 4; chan++)
2368 values[chan] = LLVMBuildFPExt(ctx->ac.builder,
2369 values[chan],
2370 ctx->ac.f32, "");
2371 }
2372 break;
2373
2374 case V_028714_SPI_SHADER_UNORM16_ABGR:
2375 args->enabled_channels = 0x5;
2376 packf = ac_build_cvt_pknorm_u16;
2377 break;
2378
2379 case V_028714_SPI_SHADER_SNORM16_ABGR:
2380 args->enabled_channels = 0x5;
2381 packf = ac_build_cvt_pknorm_i16;
2382 break;
2383
2384 case V_028714_SPI_SHADER_UINT16_ABGR:
2385 args->enabled_channels = 0x5;
2386 packi = ac_build_cvt_pk_u16;
2387 if (is_16bit) {
2388 for (unsigned chan = 0; chan < 4; chan++)
2389 values[chan] = LLVMBuildZExt(ctx->ac.builder,
2390 ac_to_integer(&ctx->ac, values[chan]),
2391 ctx->ac.i32, "");
2392 }
2393 break;
2394
2395 case V_028714_SPI_SHADER_SINT16_ABGR:
2396 args->enabled_channels = 0x5;
2397 packi = ac_build_cvt_pk_i16;
2398 if (is_16bit) {
2399 for (unsigned chan = 0; chan < 4; chan++)
2400 values[chan] = LLVMBuildSExt(ctx->ac.builder,
2401 ac_to_integer(&ctx->ac, values[chan]),
2402 ctx->ac.i32, "");
2403 }
2404 break;
2405
2406 default:
2407 case V_028714_SPI_SHADER_32_ABGR:
2408 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2409 break;
2410 }
2411
2412 /* Pack f16 or norm_i16/u16. */
2413 if (packf) {
2414 for (chan = 0; chan < 2; chan++) {
2415 LLVMValueRef pack_args[2] = {
2416 values[2 * chan],
2417 values[2 * chan + 1]
2418 };
2419 LLVMValueRef packed;
2420
2421 packed = packf(&ctx->ac, pack_args);
2422 args->out[chan] = ac_to_float(&ctx->ac, packed);
2423 }
2424 args->compr = 1; /* COMPR flag */
2425 }
2426
2427 /* Pack i16/u16. */
2428 if (packi) {
2429 for (chan = 0; chan < 2; chan++) {
2430 LLVMValueRef pack_args[2] = {
2431 ac_to_integer(&ctx->ac, values[2 * chan]),
2432 ac_to_integer(&ctx->ac, values[2 * chan + 1])
2433 };
2434 LLVMValueRef packed;
2435
2436 packed = packi(&ctx->ac, pack_args,
2437 is_int8 ? 8 : is_int10 ? 10 : 16,
2438 chan == 1);
2439 args->out[chan] = ac_to_float(&ctx->ac, packed);
2440 }
2441 args->compr = 1; /* COMPR flag */
2442 }
2443 return;
2444 }
2445
2446 if (is_16bit) {
2447 for (unsigned chan = 0; chan < 4; chan++) {
2448 values[chan] = LLVMBuildBitCast(ctx->ac.builder, values[chan], ctx->ac.i16, "");
2449 args->out[chan] = LLVMBuildZExt(ctx->ac.builder, values[chan], ctx->ac.i32, "");
2450 }
2451 } else
2452 memcpy(&args->out[0], values, sizeof(values[0]) * 4);
2453
2454 for (unsigned i = 0; i < 4; ++i)
2455 args->out[i] = ac_to_float(&ctx->ac, args->out[i]);
2456 }
2457
2458 static void
2459 radv_export_param(struct radv_shader_context *ctx, unsigned index,
2460 LLVMValueRef *values, unsigned enabled_channels)
2461 {
2462 struct ac_export_args args;
2463
2464 si_llvm_init_export_args(ctx, values, enabled_channels,
2465 V_008DFC_SQ_EXP_PARAM + index, &args);
2466 ac_build_export(&ctx->ac, &args);
2467 }
2468
2469 static LLVMValueRef
2470 radv_load_output(struct radv_shader_context *ctx, unsigned index, unsigned chan)
2471 {
2472 LLVMValueRef output = ctx->abi.outputs[ac_llvm_reg_index_soa(index, chan)];
2473 return LLVMBuildLoad(ctx->ac.builder, output, "");
2474 }
2475
2476 static void
2477 radv_emit_stream_output(struct radv_shader_context *ctx,
2478 LLVMValueRef const *so_buffers,
2479 LLVMValueRef const *so_write_offsets,
2480 const struct radv_stream_output *output,
2481 struct radv_shader_output_values *shader_out)
2482 {
2483 unsigned num_comps = util_bitcount(output->component_mask);
2484 unsigned buf = output->buffer;
2485 unsigned offset = output->offset;
2486 unsigned start;
2487 LLVMValueRef out[4];
2488
2489 assert(num_comps && num_comps <= 4);
2490 if (!num_comps || num_comps > 4)
2491 return;
2492
2493 /* Get the first component. */
2494 start = ffs(output->component_mask) - 1;
2495
2496 /* Load the output as int. */
2497 for (int i = 0; i < num_comps; i++) {
2498 out[i] = ac_to_integer(&ctx->ac, shader_out->values[start + i]);
2499 }
2500
2501 /* Pack the output. */
2502 LLVMValueRef vdata = NULL;
2503
2504 switch (num_comps) {
2505 case 1: /* as i32 */
2506 vdata = out[0];
2507 break;
2508 case 2: /* as v2i32 */
2509 case 3: /* as v4i32 (aligned to 4) */
2510 out[3] = LLVMGetUndef(ctx->ac.i32);
2511 /* fall through */
2512 case 4: /* as v4i32 */
2513 vdata = ac_build_gather_values(&ctx->ac, out,
2514 !ac_has_vec3_support(ctx->ac.chip_class, false) ?
2515 util_next_power_of_two(num_comps) :
2516 num_comps);
2517 break;
2518 }
2519
2520 ac_build_buffer_store_dword(&ctx->ac, so_buffers[buf],
2521 vdata, num_comps, so_write_offsets[buf],
2522 ctx->ac.i32_0, offset,
2523 ac_glc | ac_slc, false);
2524 }
2525
2526 static void
2527 radv_emit_streamout(struct radv_shader_context *ctx, unsigned stream)
2528 {
2529 int i;
2530
2531 /* Get bits [22:16], i.e. (so_param >> 16) & 127; */
2532 assert(ctx->streamout_config);
2533 LLVMValueRef so_vtx_count =
2534 ac_build_bfe(&ctx->ac, ctx->streamout_config,
2535 LLVMConstInt(ctx->ac.i32, 16, false),
2536 LLVMConstInt(ctx->ac.i32, 7, false), false);
2537
2538 LLVMValueRef tid = ac_get_thread_id(&ctx->ac);
2539
2540 /* can_emit = tid < so_vtx_count; */
2541 LLVMValueRef can_emit = LLVMBuildICmp(ctx->ac.builder, LLVMIntULT,
2542 tid, so_vtx_count, "");
2543
2544 /* Emit the streamout code conditionally. This actually avoids
2545 * out-of-bounds buffer access. The hw tells us via the SGPR
2546 * (so_vtx_count) which threads are allowed to emit streamout data.
2547 */
2548 ac_build_ifcc(&ctx->ac, can_emit, 6501);
2549 {
2550 /* The buffer offset is computed as follows:
2551 * ByteOffset = streamout_offset[buffer_id]*4 +
2552 * (streamout_write_index + thread_id)*stride[buffer_id] +
2553 * attrib_offset
2554 */
2555 LLVMValueRef so_write_index = ctx->streamout_write_idx;
2556
2557 /* Compute (streamout_write_index + thread_id). */
2558 so_write_index =
2559 LLVMBuildAdd(ctx->ac.builder, so_write_index, tid, "");
2560
2561 /* Load the descriptor and compute the write offset for each
2562 * enabled buffer.
2563 */
2564 LLVMValueRef so_write_offset[4] = {};
2565 LLVMValueRef so_buffers[4] = {};
2566 LLVMValueRef buf_ptr = ctx->streamout_buffers;
2567
2568 for (i = 0; i < 4; i++) {
2569 uint16_t stride = ctx->shader_info->so.strides[i];
2570
2571 if (!stride)
2572 continue;
2573
2574 LLVMValueRef offset =
2575 LLVMConstInt(ctx->ac.i32, i, false);
2576
2577 so_buffers[i] = ac_build_load_to_sgpr(&ctx->ac,
2578 buf_ptr, offset);
2579
2580 LLVMValueRef so_offset = ctx->streamout_offset[i];
2581
2582 so_offset = LLVMBuildMul(ctx->ac.builder, so_offset,
2583 LLVMConstInt(ctx->ac.i32, 4, false), "");
2584
2585 so_write_offset[i] =
2586 ac_build_imad(&ctx->ac, so_write_index,
2587 LLVMConstInt(ctx->ac.i32,
2588 stride * 4, false),
2589 so_offset);
2590 }
2591
2592 /* Write streamout data. */
2593 for (i = 0; i < ctx->shader_info->so.num_outputs; i++) {
2594 struct radv_shader_output_values shader_out = {};
2595 struct radv_stream_output *output =
2596 &ctx->shader_info->so.outputs[i];
2597
2598 if (stream != output->stream)
2599 continue;
2600
2601 for (int j = 0; j < 4; j++) {
2602 shader_out.values[j] =
2603 radv_load_output(ctx, output->location, j);
2604 }
2605
2606 radv_emit_stream_output(ctx, so_buffers,so_write_offset,
2607 output, &shader_out);
2608 }
2609 }
2610 ac_build_endif(&ctx->ac, 6501);
2611 }
2612
2613 static void
2614 radv_build_param_exports(struct radv_shader_context *ctx,
2615 struct radv_shader_output_values *outputs,
2616 unsigned noutput,
2617 struct radv_vs_output_info *outinfo,
2618 bool export_clip_dists)
2619 {
2620 unsigned param_count = 0;
2621
2622 for (unsigned i = 0; i < noutput; i++) {
2623 unsigned slot_name = outputs[i].slot_name;
2624 unsigned usage_mask = outputs[i].usage_mask;
2625
2626 if (slot_name != VARYING_SLOT_LAYER &&
2627 slot_name != VARYING_SLOT_PRIMITIVE_ID &&
2628 slot_name != VARYING_SLOT_CLIP_DIST0 &&
2629 slot_name != VARYING_SLOT_CLIP_DIST1 &&
2630 slot_name < VARYING_SLOT_VAR0)
2631 continue;
2632
2633 if ((slot_name == VARYING_SLOT_CLIP_DIST0 ||
2634 slot_name == VARYING_SLOT_CLIP_DIST1) && !export_clip_dists)
2635 continue;
2636
2637 radv_export_param(ctx, param_count, outputs[i].values, usage_mask);
2638
2639 assert(i < ARRAY_SIZE(outinfo->vs_output_param_offset));
2640 outinfo->vs_output_param_offset[slot_name] = param_count++;
2641 }
2642
2643 outinfo->param_exports = param_count;
2644 }
2645
2646 /* Generate export instructions for hardware VS shader stage or NGG GS stage
2647 * (position and parameter data only).
2648 */
2649 static void
2650 radv_llvm_export_vs(struct radv_shader_context *ctx,
2651 struct radv_shader_output_values *outputs,
2652 unsigned noutput,
2653 struct radv_vs_output_info *outinfo,
2654 bool export_clip_dists)
2655 {
2656 LLVMValueRef psize_value = NULL, layer_value = NULL, viewport_value = NULL;
2657 struct ac_export_args pos_args[4] = {};
2658 unsigned pos_idx, index;
2659 int i;
2660
2661 /* Build position exports */
2662 for (i = 0; i < noutput; i++) {
2663 switch (outputs[i].slot_name) {
2664 case VARYING_SLOT_POS:
2665 si_llvm_init_export_args(ctx, outputs[i].values, 0xf,
2666 V_008DFC_SQ_EXP_POS, &pos_args[0]);
2667 break;
2668 case VARYING_SLOT_PSIZ:
2669 psize_value = outputs[i].values[0];
2670 break;
2671 case VARYING_SLOT_LAYER:
2672 layer_value = outputs[i].values[0];
2673 break;
2674 case VARYING_SLOT_VIEWPORT:
2675 viewport_value = outputs[i].values[0];
2676 break;
2677 case VARYING_SLOT_CLIP_DIST0:
2678 case VARYING_SLOT_CLIP_DIST1:
2679 index = 2 + outputs[i].slot_index;
2680 si_llvm_init_export_args(ctx, outputs[i].values, 0xf,
2681 V_008DFC_SQ_EXP_POS + index,
2682 &pos_args[index]);
2683 break;
2684 default:
2685 break;
2686 }
2687 }
2688
2689 /* We need to add the position output manually if it's missing. */
2690 if (!pos_args[0].out[0]) {
2691 pos_args[0].enabled_channels = 0xf; /* writemask */
2692 pos_args[0].valid_mask = 0; /* EXEC mask */
2693 pos_args[0].done = 0; /* last export? */
2694 pos_args[0].target = V_008DFC_SQ_EXP_POS;
2695 pos_args[0].compr = 0; /* COMPR flag */
2696 pos_args[0].out[0] = ctx->ac.f32_0; /* X */
2697 pos_args[0].out[1] = ctx->ac.f32_0; /* Y */
2698 pos_args[0].out[2] = ctx->ac.f32_0; /* Z */
2699 pos_args[0].out[3] = ctx->ac.f32_1; /* W */
2700 }
2701
2702 if (outinfo->writes_pointsize ||
2703 outinfo->writes_layer ||
2704 outinfo->writes_viewport_index) {
2705 pos_args[1].enabled_channels = ((outinfo->writes_pointsize == true ? 1 : 0) |
2706 (outinfo->writes_layer == true ? 4 : 0));
2707 pos_args[1].valid_mask = 0;
2708 pos_args[1].done = 0;
2709 pos_args[1].target = V_008DFC_SQ_EXP_POS + 1;
2710 pos_args[1].compr = 0;
2711 pos_args[1].out[0] = ctx->ac.f32_0; /* X */
2712 pos_args[1].out[1] = ctx->ac.f32_0; /* Y */
2713 pos_args[1].out[2] = ctx->ac.f32_0; /* Z */
2714 pos_args[1].out[3] = ctx->ac.f32_0; /* W */
2715
2716 if (outinfo->writes_pointsize == true)
2717 pos_args[1].out[0] = psize_value;
2718 if (outinfo->writes_layer == true)
2719 pos_args[1].out[2] = layer_value;
2720 if (outinfo->writes_viewport_index == true) {
2721 if (ctx->options->chip_class >= GFX9) {
2722 /* GFX9 has the layer in out.z[10:0] and the viewport
2723 * index in out.z[19:16].
2724 */
2725 LLVMValueRef v = viewport_value;
2726 v = ac_to_integer(&ctx->ac, v);
2727 v = LLVMBuildShl(ctx->ac.builder, v,
2728 LLVMConstInt(ctx->ac.i32, 16, false),
2729 "");
2730 v = LLVMBuildOr(ctx->ac.builder, v,
2731 ac_to_integer(&ctx->ac, pos_args[1].out[2]), "");
2732
2733 pos_args[1].out[2] = ac_to_float(&ctx->ac, v);
2734 pos_args[1].enabled_channels |= 1 << 2;
2735 } else {
2736 pos_args[1].out[3] = viewport_value;
2737 pos_args[1].enabled_channels |= 1 << 3;
2738 }
2739 }
2740 }
2741
2742 for (i = 0; i < 4; i++) {
2743 if (pos_args[i].out[0])
2744 outinfo->pos_exports++;
2745 }
2746
2747 /* Navi10-14 skip POS0 exports if EXEC=0 and DONE=0, causing a hang.
2748 * Setting valid_mask=1 prevents it and has no other effect.
2749 */
2750 if (ctx->ac.family == CHIP_NAVI10 ||
2751 ctx->ac.family == CHIP_NAVI12 ||
2752 ctx->ac.family == CHIP_NAVI14)
2753 pos_args[0].valid_mask = 1;
2754
2755 pos_idx = 0;
2756 for (i = 0; i < 4; i++) {
2757 if (!pos_args[i].out[0])
2758 continue;
2759
2760 /* Specify the target we are exporting */
2761 pos_args[i].target = V_008DFC_SQ_EXP_POS + pos_idx++;
2762
2763 if (pos_idx == outinfo->pos_exports)
2764 /* Specify that this is the last export */
2765 pos_args[i].done = 1;
2766
2767 ac_build_export(&ctx->ac, &pos_args[i]);
2768 }
2769
2770 /* Build parameter exports */
2771 radv_build_param_exports(ctx, outputs, noutput, outinfo, export_clip_dists);
2772 }
2773
2774 static void
2775 handle_vs_outputs_post(struct radv_shader_context *ctx,
2776 bool export_prim_id,
2777 bool export_clip_dists,
2778 struct radv_vs_output_info *outinfo)
2779 {
2780 struct radv_shader_output_values *outputs;
2781 unsigned noutput = 0;
2782
2783 if (ctx->options->key.has_multiview_view_index) {
2784 LLVMValueRef* tmp_out = &ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, 0)];
2785 if(!*tmp_out) {
2786 for(unsigned i = 0; i < 4; ++i)
2787 ctx->abi.outputs[ac_llvm_reg_index_soa(VARYING_SLOT_LAYER, i)] =
2788 ac_build_alloca_undef(&ctx->ac, ctx->ac.f32, "");
2789 }
2790
2791 LLVMBuildStore(ctx->ac.builder, ac_to_float(&ctx->ac, ctx->abi.view_index), *tmp_out);
2792 ctx->output_mask |= 1ull << VARYING_SLOT_LAYER;
2793 }
2794
2795 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
2796 sizeof(outinfo->vs_output_param_offset));
2797 outinfo->pos_exports = 0;
2798
2799 if (!ctx->options->use_ngg_streamout &&
2800 ctx->shader_info->so.num_outputs &&
2801 !ctx->is_gs_copy_shader) {
2802 /* The GS copy shader emission already emits streamout. */
2803 radv_emit_streamout(ctx, 0);
2804 }
2805
2806 /* Allocate a temporary array for the output values. */
2807 unsigned num_outputs = util_bitcount64(ctx->output_mask) + export_prim_id;
2808 outputs = malloc(num_outputs * sizeof(outputs[0]));
2809
2810 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2811 if (!(ctx->output_mask & (1ull << i)))
2812 continue;
2813
2814 outputs[noutput].slot_name = i;
2815 outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
2816
2817 if (ctx->stage == MESA_SHADER_VERTEX &&
2818 !ctx->is_gs_copy_shader) {
2819 outputs[noutput].usage_mask =
2820 ctx->shader_info->vs.output_usage_mask[i];
2821 } else if (ctx->stage == MESA_SHADER_TESS_EVAL) {
2822 outputs[noutput].usage_mask =
2823 ctx->shader_info->tes.output_usage_mask[i];
2824 } else {
2825 assert(ctx->is_gs_copy_shader);
2826 outputs[noutput].usage_mask =
2827 ctx->shader_info->gs.output_usage_mask[i];
2828 }
2829
2830 for (unsigned j = 0; j < 4; j++) {
2831 outputs[noutput].values[j] =
2832 ac_to_float(&ctx->ac, radv_load_output(ctx, i, j));
2833 }
2834
2835 noutput++;
2836 }
2837
2838 /* Export PrimitiveID. */
2839 if (export_prim_id) {
2840 outputs[noutput].slot_name = VARYING_SLOT_PRIMITIVE_ID;
2841 outputs[noutput].slot_index = 0;
2842 outputs[noutput].usage_mask = 0x1;
2843 outputs[noutput].values[0] = ctx->vs_prim_id;
2844 for (unsigned j = 1; j < 4; j++)
2845 outputs[noutput].values[j] = ctx->ac.f32_0;
2846 noutput++;
2847 }
2848
2849 radv_llvm_export_vs(ctx, outputs, noutput, outinfo, export_clip_dists);
2850
2851 free(outputs);
2852 }
2853
2854 static void
2855 handle_es_outputs_post(struct radv_shader_context *ctx,
2856 struct radv_es_output_info *outinfo)
2857 {
2858 int j;
2859 LLVMValueRef lds_base = NULL;
2860
2861 if (ctx->ac.chip_class >= GFX9) {
2862 unsigned itemsize_dw = outinfo->esgs_itemsize / 4;
2863 LLVMValueRef vertex_idx = ac_get_thread_id(&ctx->ac);
2864 LLVMValueRef wave_idx = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 24, 4);
2865 vertex_idx = LLVMBuildOr(ctx->ac.builder, vertex_idx,
2866 LLVMBuildMul(ctx->ac.builder, wave_idx,
2867 LLVMConstInt(ctx->ac.i32,
2868 ctx->ac.wave_size, false), ""), "");
2869 lds_base = LLVMBuildMul(ctx->ac.builder, vertex_idx,
2870 LLVMConstInt(ctx->ac.i32, itemsize_dw, 0), "");
2871 }
2872
2873 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2874 LLVMValueRef dw_addr = NULL;
2875 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2876 unsigned output_usage_mask;
2877 int param_index;
2878
2879 if (!(ctx->output_mask & (1ull << i)))
2880 continue;
2881
2882 if (ctx->stage == MESA_SHADER_VERTEX) {
2883 output_usage_mask =
2884 ctx->shader_info->vs.output_usage_mask[i];
2885 } else {
2886 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
2887 output_usage_mask =
2888 ctx->shader_info->tes.output_usage_mask[i];
2889 }
2890
2891 param_index = shader_io_get_unique_index(i);
2892
2893 if (lds_base) {
2894 dw_addr = LLVMBuildAdd(ctx->ac.builder, lds_base,
2895 LLVMConstInt(ctx->ac.i32, param_index * 4, false),
2896 "");
2897 }
2898
2899 for (j = 0; j < 4; j++) {
2900 if (!(output_usage_mask & (1 << j)))
2901 continue;
2902
2903 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2904 out_val = ac_to_integer(&ctx->ac, out_val);
2905 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
2906
2907 if (ctx->ac.chip_class >= GFX9) {
2908 LLVMValueRef dw_addr_offset =
2909 LLVMBuildAdd(ctx->ac.builder, dw_addr,
2910 LLVMConstInt(ctx->ac.i32,
2911 j, false), "");
2912
2913 ac_lds_store(&ctx->ac, dw_addr_offset, out_val);
2914 } else {
2915 ac_build_buffer_store_dword(&ctx->ac,
2916 ctx->esgs_ring,
2917 out_val, 1,
2918 NULL, ctx->es2gs_offset,
2919 (4 * param_index + j) * 4,
2920 ac_glc | ac_slc, true);
2921 }
2922 }
2923 }
2924 }
2925
2926 static void
2927 handle_ls_outputs_post(struct radv_shader_context *ctx)
2928 {
2929 LLVMValueRef vertex_id = ctx->rel_auto_id;
2930 uint32_t num_tcs_inputs = util_last_bit64(ctx->shader_info->vs.ls_outputs_written);
2931 LLVMValueRef vertex_dw_stride = LLVMConstInt(ctx->ac.i32, num_tcs_inputs * 4, false);
2932 LLVMValueRef base_dw_addr = LLVMBuildMul(ctx->ac.builder, vertex_id,
2933 vertex_dw_stride, "");
2934
2935 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
2936 LLVMValueRef *out_ptr = &ctx->abi.outputs[i * 4];
2937
2938 if (!(ctx->output_mask & (1ull << i)))
2939 continue;
2940
2941 int param = shader_io_get_unique_index(i);
2942 LLVMValueRef dw_addr = LLVMBuildAdd(ctx->ac.builder, base_dw_addr,
2943 LLVMConstInt(ctx->ac.i32, param * 4, false),
2944 "");
2945 for (unsigned j = 0; j < 4; j++) {
2946 LLVMValueRef value = LLVMBuildLoad(ctx->ac.builder, out_ptr[j], "");
2947 value = ac_to_integer(&ctx->ac, value);
2948 value = LLVMBuildZExtOrBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
2949 ac_lds_store(&ctx->ac, dw_addr, value);
2950 dw_addr = LLVMBuildAdd(ctx->ac.builder, dw_addr, ctx->ac.i32_1, "");
2951 }
2952 }
2953 }
2954
2955 static LLVMValueRef get_wave_id_in_tg(struct radv_shader_context *ctx)
2956 {
2957 return ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 24, 4);
2958 }
2959
2960 static LLVMValueRef get_tgsize(struct radv_shader_context *ctx)
2961 {
2962 return ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 28, 4);
2963 }
2964
2965 static LLVMValueRef get_thread_id_in_tg(struct radv_shader_context *ctx)
2966 {
2967 LLVMBuilderRef builder = ctx->ac.builder;
2968 LLVMValueRef tmp;
2969 tmp = LLVMBuildMul(builder, get_wave_id_in_tg(ctx),
2970 LLVMConstInt(ctx->ac.i32, ctx->ac.wave_size, false), "");
2971 return LLVMBuildAdd(builder, tmp, ac_get_thread_id(&ctx->ac), "");
2972 }
2973
2974 static LLVMValueRef ngg_get_vtx_cnt(struct radv_shader_context *ctx)
2975 {
2976 return ac_build_bfe(&ctx->ac, ctx->gs_tg_info,
2977 LLVMConstInt(ctx->ac.i32, 12, false),
2978 LLVMConstInt(ctx->ac.i32, 9, false),
2979 false);
2980 }
2981
2982 static LLVMValueRef ngg_get_prim_cnt(struct radv_shader_context *ctx)
2983 {
2984 return ac_build_bfe(&ctx->ac, ctx->gs_tg_info,
2985 LLVMConstInt(ctx->ac.i32, 22, false),
2986 LLVMConstInt(ctx->ac.i32, 9, false),
2987 false);
2988 }
2989
2990 static LLVMValueRef ngg_get_ordered_id(struct radv_shader_context *ctx)
2991 {
2992 return ac_build_bfe(&ctx->ac, ctx->gs_tg_info,
2993 ctx->ac.i32_0,
2994 LLVMConstInt(ctx->ac.i32, 11, false),
2995 false);
2996 }
2997
2998 static LLVMValueRef
2999 ngg_gs_get_vertex_storage(struct radv_shader_context *ctx)
3000 {
3001 unsigned num_outputs = util_bitcount64(ctx->output_mask);
3002
3003 if (ctx->options->key.has_multiview_view_index)
3004 num_outputs++;
3005
3006 LLVMTypeRef elements[2] = {
3007 LLVMArrayType(ctx->ac.i32, 4 * num_outputs),
3008 LLVMArrayType(ctx->ac.i8, 4),
3009 };
3010 LLVMTypeRef type = LLVMStructTypeInContext(ctx->ac.context, elements, 2, false);
3011 type = LLVMPointerType(LLVMArrayType(type, 0), AC_ADDR_SPACE_LDS);
3012 return LLVMBuildBitCast(ctx->ac.builder, ctx->gs_ngg_emit, type, "");
3013 }
3014
3015 /**
3016 * Return a pointer to the LDS storage reserved for the N'th vertex, where N
3017 * is in emit order; that is:
3018 * - during the epilogue, N is the threadidx (relative to the entire threadgroup)
3019 * - during vertex emit, i.e. while the API GS shader invocation is running,
3020 * N = threadidx * gs_max_out_vertices + emitidx
3021 *
3022 * Goals of the LDS memory layout:
3023 * 1. Eliminate bank conflicts on write for geometry shaders that have all emits
3024 * in uniform control flow
3025 * 2. Eliminate bank conflicts on read for export if, additionally, there is no
3026 * culling
3027 * 3. Agnostic to the number of waves (since we don't know it before compiling)
3028 * 4. Allow coalescing of LDS instructions (ds_write_b128 etc.)
3029 * 5. Avoid wasting memory.
3030 *
3031 * We use an AoS layout due to point 4 (this also helps point 3). In an AoS
3032 * layout, elimination of bank conflicts requires that each vertex occupy an
3033 * odd number of dwords. We use the additional dword to store the output stream
3034 * index as well as a flag to indicate whether this vertex ends a primitive
3035 * for rasterization.
3036 *
3037 * Swizzling is required to satisfy points 1 and 2 simultaneously.
3038 *
3039 * Vertices are stored in export order (gsthread * gs_max_out_vertices + emitidx).
3040 * Indices are swizzled in groups of 32, which ensures point 1 without
3041 * disturbing point 2.
3042 *
3043 * \return an LDS pointer to type {[N x i32], [4 x i8]}
3044 */
3045 static LLVMValueRef
3046 ngg_gs_vertex_ptr(struct radv_shader_context *ctx, LLVMValueRef vertexidx)
3047 {
3048 LLVMBuilderRef builder = ctx->ac.builder;
3049 LLVMValueRef storage = ngg_gs_get_vertex_storage(ctx);
3050
3051 /* gs_max_out_vertices = 2^(write_stride_2exp) * some odd number */
3052 unsigned write_stride_2exp = ffs(ctx->shader->info.gs.vertices_out) - 1;
3053 if (write_stride_2exp) {
3054 LLVMValueRef row =
3055 LLVMBuildLShr(builder, vertexidx,
3056 LLVMConstInt(ctx->ac.i32, 5, false), "");
3057 LLVMValueRef swizzle =
3058 LLVMBuildAnd(builder, row,
3059 LLVMConstInt(ctx->ac.i32, (1u << write_stride_2exp) - 1,
3060 false), "");
3061 vertexidx = LLVMBuildXor(builder, vertexidx, swizzle, "");
3062 }
3063
3064 return ac_build_gep0(&ctx->ac, storage, vertexidx);
3065 }
3066
3067 static LLVMValueRef
3068 ngg_gs_emit_vertex_ptr(struct radv_shader_context *ctx, LLVMValueRef gsthread,
3069 LLVMValueRef emitidx)
3070 {
3071 LLVMBuilderRef builder = ctx->ac.builder;
3072 LLVMValueRef tmp;
3073
3074 tmp = LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false);
3075 tmp = LLVMBuildMul(builder, tmp, gsthread, "");
3076 const LLVMValueRef vertexidx = LLVMBuildAdd(builder, tmp, emitidx, "");
3077 return ngg_gs_vertex_ptr(ctx, vertexidx);
3078 }
3079
3080 /* Send GS Alloc Req message from the first wave of the group to SPI.
3081 * Message payload is:
3082 * - bits 0..10: vertices in group
3083 * - bits 12..22: primitives in group
3084 */
3085 static void build_sendmsg_gs_alloc_req(struct radv_shader_context *ctx,
3086 LLVMValueRef vtx_cnt,
3087 LLVMValueRef prim_cnt)
3088 {
3089 LLVMBuilderRef builder = ctx->ac.builder;
3090 LLVMValueRef tmp;
3091
3092 tmp = LLVMBuildICmp(builder, LLVMIntEQ, get_wave_id_in_tg(ctx), ctx->ac.i32_0, "");
3093 ac_build_ifcc(&ctx->ac, tmp, 5020);
3094
3095 tmp = LLVMBuildShl(builder, prim_cnt, LLVMConstInt(ctx->ac.i32, 12, false),"");
3096 tmp = LLVMBuildOr(builder, tmp, vtx_cnt, "");
3097 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_ALLOC_REQ, tmp);
3098
3099 ac_build_endif(&ctx->ac, 5020);
3100 }
3101
3102 struct ngg_prim {
3103 unsigned num_vertices;
3104 LLVMValueRef isnull;
3105 LLVMValueRef index[3];
3106 LLVMValueRef edgeflag[3];
3107 };
3108
3109 static void build_export_prim(struct radv_shader_context *ctx,
3110 const struct ngg_prim *prim)
3111 {
3112 LLVMBuilderRef builder = ctx->ac.builder;
3113 struct ac_export_args args;
3114 LLVMValueRef tmp;
3115
3116 tmp = LLVMBuildZExt(builder, prim->isnull, ctx->ac.i32, "");
3117 args.out[0] = LLVMBuildShl(builder, tmp, LLVMConstInt(ctx->ac.i32, 31, false), "");
3118
3119 for (unsigned i = 0; i < prim->num_vertices; ++i) {
3120 tmp = LLVMBuildShl(builder, prim->index[i],
3121 LLVMConstInt(ctx->ac.i32, 10 * i, false), "");
3122 args.out[0] = LLVMBuildOr(builder, args.out[0], tmp, "");
3123 tmp = LLVMBuildZExt(builder, prim->edgeflag[i], ctx->ac.i32, "");
3124 tmp = LLVMBuildShl(builder, tmp,
3125 LLVMConstInt(ctx->ac.i32, 10 * i + 9, false), "");
3126 args.out[0] = LLVMBuildOr(builder, args.out[0], tmp, "");
3127 }
3128
3129 args.out[0] = LLVMBuildBitCast(builder, args.out[0], ctx->ac.f32, "");
3130 args.out[1] = LLVMGetUndef(ctx->ac.f32);
3131 args.out[2] = LLVMGetUndef(ctx->ac.f32);
3132 args.out[3] = LLVMGetUndef(ctx->ac.f32);
3133
3134 args.target = V_008DFC_SQ_EXP_PRIM;
3135 args.enabled_channels = 1;
3136 args.done = true;
3137 args.valid_mask = false;
3138 args.compr = false;
3139
3140 ac_build_export(&ctx->ac, &args);
3141 }
3142
3143 static void build_streamout_vertex(struct radv_shader_context *ctx,
3144 LLVMValueRef *so_buffer, LLVMValueRef *wg_offset_dw,
3145 unsigned stream, LLVMValueRef offset_vtx,
3146 LLVMValueRef vertexptr)
3147 {
3148 struct radv_streamout_info *so = &ctx->shader_info->so;
3149 LLVMBuilderRef builder = ctx->ac.builder;
3150 LLVMValueRef offset[4] = {};
3151 LLVMValueRef tmp;
3152
3153 for (unsigned buffer = 0; buffer < 4; ++buffer) {
3154 if (!wg_offset_dw[buffer])
3155 continue;
3156
3157 tmp = LLVMBuildMul(builder, offset_vtx,
3158 LLVMConstInt(ctx->ac.i32, so->strides[buffer], false), "");
3159 tmp = LLVMBuildAdd(builder, wg_offset_dw[buffer], tmp, "");
3160 offset[buffer] = LLVMBuildShl(builder, tmp, LLVMConstInt(ctx->ac.i32, 2, false), "");
3161 }
3162
3163 for (unsigned i = 0; i < so->num_outputs; ++i) {
3164 struct radv_stream_output *output =
3165 &ctx->shader_info->so.outputs[i];
3166
3167 if (stream != output->stream)
3168 continue;
3169
3170 unsigned loc = output->location;
3171 struct radv_shader_output_values out = {};
3172
3173 for (unsigned comp = 0; comp < 4; comp++) {
3174 tmp = ac_build_gep0(&ctx->ac, vertexptr,
3175 LLVMConstInt(ctx->ac.i32, 4 * loc + comp, false));
3176 out.values[comp] = LLVMBuildLoad(builder, tmp, "");
3177 }
3178
3179 radv_emit_stream_output(ctx, so_buffer, offset, output, &out);
3180 }
3181 }
3182
3183 struct ngg_streamout {
3184 LLVMValueRef num_vertices;
3185
3186 /* per-thread data */
3187 LLVMValueRef prim_enable[4]; /* i1 per stream */
3188 LLVMValueRef vertices[3]; /* [N x i32] addrspace(LDS)* */
3189
3190 /* Output */
3191 LLVMValueRef emit[4]; /* per-stream emitted primitives (only valid for used streams) */
3192 };
3193
3194 /**
3195 * Build streamout logic.
3196 *
3197 * Implies a barrier.
3198 *
3199 * Writes number of emitted primitives to gs_ngg_scratch[4:7].
3200 *
3201 * Clobbers gs_ngg_scratch[8:].
3202 */
3203 static void build_streamout(struct radv_shader_context *ctx,
3204 struct ngg_streamout *nggso)
3205 {
3206 struct radv_streamout_info *so = &ctx->shader_info->so;
3207 LLVMBuilderRef builder = ctx->ac.builder;
3208 LLVMValueRef buf_ptr = ctx->streamout_buffers;
3209 LLVMValueRef tid = get_thread_id_in_tg(ctx);
3210 LLVMValueRef cond, tmp, tmp2;
3211 LLVMValueRef i32_2 = LLVMConstInt(ctx->ac.i32, 2, false);
3212 LLVMValueRef i32_4 = LLVMConstInt(ctx->ac.i32, 4, false);
3213 LLVMValueRef i32_8 = LLVMConstInt(ctx->ac.i32, 8, false);
3214 LLVMValueRef so_buffer[4] = {};
3215 unsigned max_num_vertices = 1 + (nggso->vertices[1] ? 1 : 0) +
3216 (nggso->vertices[2] ? 1 : 0);
3217 LLVMValueRef prim_stride_dw[4] = {};
3218 LLVMValueRef prim_stride_dw_vgpr = LLVMGetUndef(ctx->ac.i32);
3219 int stream_for_buffer[4] = { -1, -1, -1, -1 };
3220 unsigned bufmask_for_stream[4] = {};
3221 bool isgs = ctx->stage == MESA_SHADER_GEOMETRY;
3222 unsigned scratch_emit_base = isgs ? 4 : 0;
3223 LLVMValueRef scratch_emit_basev = isgs ? i32_4 : ctx->ac.i32_0;
3224 unsigned scratch_offset_base = isgs ? 8 : 4;
3225 LLVMValueRef scratch_offset_basev = isgs ? i32_8 : i32_4;
3226
3227 ac_llvm_add_target_dep_function_attr(ctx->main_function,
3228 "amdgpu-gds-size", 256);
3229
3230 /* Determine the mapping of streamout buffers to vertex streams. */
3231 for (unsigned i = 0; i < so->num_outputs; ++i) {
3232 unsigned buf = so->outputs[i].buffer;
3233 unsigned stream = so->outputs[i].stream;
3234 assert(stream_for_buffer[buf] < 0 || stream_for_buffer[buf] == stream);
3235 stream_for_buffer[buf] = stream;
3236 bufmask_for_stream[stream] |= 1 << buf;
3237 }
3238
3239 for (unsigned buffer = 0; buffer < 4; ++buffer) {
3240 if (stream_for_buffer[buffer] == -1)
3241 continue;
3242
3243 assert(so->strides[buffer]);
3244
3245 LLVMValueRef stride_for_buffer =
3246 LLVMConstInt(ctx->ac.i32, so->strides[buffer], false);
3247 prim_stride_dw[buffer] =
3248 LLVMBuildMul(builder, stride_for_buffer,
3249 nggso->num_vertices, "");
3250 prim_stride_dw_vgpr = ac_build_writelane(
3251 &ctx->ac, prim_stride_dw_vgpr, prim_stride_dw[buffer],
3252 LLVMConstInt(ctx->ac.i32, buffer, false));
3253
3254 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, buffer, false);
3255 so_buffer[buffer] = ac_build_load_to_sgpr(&ctx->ac, buf_ptr,
3256 offset);
3257 }
3258
3259 cond = LLVMBuildICmp(builder, LLVMIntEQ, get_wave_id_in_tg(ctx), ctx->ac.i32_0, "");
3260 ac_build_ifcc(&ctx->ac, cond, 5200);
3261 {
3262 LLVMTypeRef gdsptr = LLVMPointerType(ctx->ac.i32, AC_ADDR_SPACE_GDS);
3263 LLVMValueRef gdsbase = LLVMBuildIntToPtr(builder, ctx->ac.i32_0, gdsptr, "");
3264
3265 /* Advance the streamout offsets in GDS. */
3266 LLVMValueRef offsets_vgpr = ac_build_alloca_undef(&ctx->ac, ctx->ac.i32, "");
3267 LLVMValueRef generated_by_stream_vgpr = ac_build_alloca_undef(&ctx->ac, ctx->ac.i32, "");
3268
3269 cond = LLVMBuildICmp(builder, LLVMIntULT, ac_get_thread_id(&ctx->ac), i32_4, "");
3270 ac_build_ifcc(&ctx->ac, cond, 5210);
3271 {
3272 /* Fetch the number of generated primitives and store
3273 * it in GDS for later use.
3274 */
3275 if (isgs) {
3276 tmp = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tid);
3277 tmp = LLVMBuildLoad(builder, tmp, "");
3278 } else {
3279 tmp = ac_build_writelane(&ctx->ac, ctx->ac.i32_0,
3280 ngg_get_prim_cnt(ctx), ctx->ac.i32_0);
3281 }
3282 LLVMBuildStore(builder, tmp, generated_by_stream_vgpr);
3283
3284 unsigned swizzle[4];
3285 int unused_stream = -1;
3286 for (unsigned stream = 0; stream < 4; ++stream) {
3287 if (!ctx->shader_info->gs.num_stream_output_components[stream]) {
3288 unused_stream = stream;
3289 break;
3290 }
3291 }
3292 for (unsigned buffer = 0; buffer < 4; ++buffer) {
3293 if (stream_for_buffer[buffer] >= 0) {
3294 swizzle[buffer] = stream_for_buffer[buffer];
3295 } else {
3296 assert(unused_stream >= 0);
3297 swizzle[buffer] = unused_stream;
3298 }
3299 }
3300
3301 tmp = ac_build_quad_swizzle(&ctx->ac, tmp,
3302 swizzle[0], swizzle[1], swizzle[2], swizzle[3]);
3303 tmp = LLVMBuildMul(builder, tmp, prim_stride_dw_vgpr, "");
3304
3305 LLVMValueRef args[] = {
3306 LLVMBuildIntToPtr(builder, ngg_get_ordered_id(ctx), gdsptr, ""),
3307 tmp,
3308 ctx->ac.i32_0, // ordering
3309 ctx->ac.i32_0, // scope
3310 ctx->ac.i1false, // isVolatile
3311 LLVMConstInt(ctx->ac.i32, 4 << 24, false), // OA index
3312 ctx->ac.i1true, // wave release
3313 ctx->ac.i1true, // wave done
3314 };
3315
3316 tmp = ac_build_intrinsic(&ctx->ac, "llvm.amdgcn.ds.ordered.add",
3317 ctx->ac.i32, args, ARRAY_SIZE(args), 0);
3318
3319 /* Keep offsets in a VGPR for quick retrieval via readlane by
3320 * the first wave for bounds checking, and also store in LDS
3321 * for retrieval by all waves later. */
3322 LLVMBuildStore(builder, tmp, offsets_vgpr);
3323
3324 tmp2 = LLVMBuildAdd(builder, ac_get_thread_id(&ctx->ac),
3325 scratch_offset_basev, "");
3326 tmp2 = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tmp2);
3327 LLVMBuildStore(builder, tmp, tmp2);
3328 }
3329 ac_build_endif(&ctx->ac, 5210);
3330
3331 /* Determine the max emit per buffer. This is done via the SALU, in part
3332 * because LLVM can't generate divide-by-multiply if we try to do this
3333 * via VALU with one lane per buffer.
3334 */
3335 LLVMValueRef max_emit[4] = {};
3336 for (unsigned buffer = 0; buffer < 4; ++buffer) {
3337 if (stream_for_buffer[buffer] == -1)
3338 continue;
3339
3340 /* Compute the streamout buffer size in DWORD. */
3341 LLVMValueRef bufsize_dw =
3342 LLVMBuildLShr(builder,
3343 LLVMBuildExtractElement(builder, so_buffer[buffer], i32_2, ""),
3344 i32_2, "");
3345
3346 /* Load the streamout buffer offset from GDS. */
3347 tmp = LLVMBuildLoad(builder, offsets_vgpr, "");
3348 LLVMValueRef offset_dw =
3349 ac_build_readlane(&ctx->ac, tmp,
3350 LLVMConstInt(ctx->ac.i32, buffer, false));
3351
3352 /* Compute the remaining size to emit. */
3353 LLVMValueRef remaining_dw =
3354 LLVMBuildSub(builder, bufsize_dw, offset_dw, "");
3355 tmp = LLVMBuildUDiv(builder, remaining_dw,
3356 prim_stride_dw[buffer], "");
3357
3358 cond = LLVMBuildICmp(builder, LLVMIntULT,
3359 bufsize_dw, offset_dw, "");
3360 max_emit[buffer] = LLVMBuildSelect(builder, cond,
3361 ctx->ac.i32_0, tmp, "");
3362 }
3363
3364 /* Determine the number of emitted primitives per stream and fixup the
3365 * GDS counter if necessary.
3366 *
3367 * This is complicated by the fact that a single stream can emit to
3368 * multiple buffers (but luckily not vice versa).
3369 */
3370 LLVMValueRef emit_vgpr = ctx->ac.i32_0;
3371
3372 for (unsigned stream = 0; stream < 4; ++stream) {
3373 if (!ctx->shader_info->gs.num_stream_output_components[stream])
3374 continue;
3375
3376 /* Load the number of generated primitives from GDS and
3377 * determine that number for the given stream.
3378 */
3379 tmp = LLVMBuildLoad(builder, generated_by_stream_vgpr, "");
3380 LLVMValueRef generated =
3381 ac_build_readlane(&ctx->ac, tmp,
3382 LLVMConstInt(ctx->ac.i32, stream, false));
3383
3384
3385 /* Compute the number of emitted primitives. */
3386 LLVMValueRef emit = generated;
3387 for (unsigned buffer = 0; buffer < 4; ++buffer) {
3388 if (stream_for_buffer[buffer] == stream)
3389 emit = ac_build_umin(&ctx->ac, emit, max_emit[buffer]);
3390 }
3391
3392 /* Store the number of emitted primitives for that
3393 * stream.
3394 */
3395 emit_vgpr = ac_build_writelane(&ctx->ac, emit_vgpr, emit,
3396 LLVMConstInt(ctx->ac.i32, stream, false));
3397
3398 /* Fixup the offset using a plain GDS atomic if we overflowed. */
3399 cond = LLVMBuildICmp(builder, LLVMIntULT, emit, generated, "");
3400 ac_build_ifcc(&ctx->ac, cond, 5221); /* scalar branch */
3401 tmp = LLVMBuildLShr(builder,
3402 LLVMConstInt(ctx->ac.i32, bufmask_for_stream[stream], false),
3403 ac_get_thread_id(&ctx->ac), "");
3404 tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3405 ac_build_ifcc(&ctx->ac, tmp, 5222);
3406 {
3407 tmp = LLVMBuildSub(builder, generated, emit, "");
3408 tmp = LLVMBuildMul(builder, tmp, prim_stride_dw_vgpr, "");
3409 tmp2 = LLVMBuildGEP(builder, gdsbase, &tid, 1, "");
3410 LLVMBuildAtomicRMW(builder, LLVMAtomicRMWBinOpSub, tmp2, tmp,
3411 LLVMAtomicOrderingMonotonic, false);
3412 }
3413 ac_build_endif(&ctx->ac, 5222);
3414 ac_build_endif(&ctx->ac, 5221);
3415 }
3416
3417 /* Store the number of emitted primitives to LDS for later use. */
3418 cond = LLVMBuildICmp(builder, LLVMIntULT, ac_get_thread_id(&ctx->ac), i32_4, "");
3419 ac_build_ifcc(&ctx->ac, cond, 5225);
3420 {
3421 tmp = LLVMBuildAdd(builder, ac_get_thread_id(&ctx->ac),
3422 scratch_emit_basev, "");
3423 tmp = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, tmp);
3424 LLVMBuildStore(builder, emit_vgpr, tmp);
3425 }
3426 ac_build_endif(&ctx->ac, 5225);
3427 }
3428 ac_build_endif(&ctx->ac, 5200);
3429
3430 /* Determine the workgroup-relative per-thread / primitive offset into
3431 * the streamout buffers */
3432 struct ac_wg_scan primemit_scan[4] = {};
3433
3434 if (isgs) {
3435 for (unsigned stream = 0; stream < 4; ++stream) {
3436 if (!ctx->shader_info->gs.num_stream_output_components[stream])
3437 continue;
3438
3439 primemit_scan[stream].enable_exclusive = true;
3440 primemit_scan[stream].op = nir_op_iadd;
3441 primemit_scan[stream].src = nggso->prim_enable[stream];
3442 primemit_scan[stream].scratch =
3443 ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch,
3444 LLVMConstInt(ctx->ac.i32, 12 + 8 * stream, false));
3445 primemit_scan[stream].waveidx = get_wave_id_in_tg(ctx);
3446 primemit_scan[stream].numwaves = get_tgsize(ctx);
3447 primemit_scan[stream].maxwaves = 8;
3448 ac_build_wg_scan_top(&ctx->ac, &primemit_scan[stream]);
3449 }
3450 }
3451
3452 ac_build_s_barrier(&ctx->ac);
3453
3454 /* Fetch the per-buffer offsets and per-stream emit counts in all waves. */
3455 LLVMValueRef wgoffset_dw[4] = {};
3456
3457 {
3458 LLVMValueRef scratch_vgpr;
3459
3460 tmp = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, ac_get_thread_id(&ctx->ac));
3461 scratch_vgpr = LLVMBuildLoad(builder, tmp, "");
3462
3463 for (unsigned buffer = 0; buffer < 4; ++buffer) {
3464 if (stream_for_buffer[buffer] >= 0) {
3465 wgoffset_dw[buffer] = ac_build_readlane(
3466 &ctx->ac, scratch_vgpr,
3467 LLVMConstInt(ctx->ac.i32, scratch_offset_base + buffer, false));
3468 }
3469 }
3470
3471 for (unsigned stream = 0; stream < 4; ++stream) {
3472 if (ctx->shader_info->gs.num_stream_output_components[stream]) {
3473 nggso->emit[stream] = ac_build_readlane(
3474 &ctx->ac, scratch_vgpr,
3475 LLVMConstInt(ctx->ac.i32, scratch_emit_base + stream, false));
3476 }
3477 }
3478 }
3479
3480 /* Write out primitive data */
3481 for (unsigned stream = 0; stream < 4; ++stream) {
3482 if (!ctx->shader_info->gs.num_stream_output_components[stream])
3483 continue;
3484
3485 if (isgs) {
3486 ac_build_wg_scan_bottom(&ctx->ac, &primemit_scan[stream]);
3487 } else {
3488 primemit_scan[stream].result_exclusive = tid;
3489 }
3490
3491 cond = LLVMBuildICmp(builder, LLVMIntULT,
3492 primemit_scan[stream].result_exclusive,
3493 nggso->emit[stream], "");
3494 cond = LLVMBuildAnd(builder, cond, nggso->prim_enable[stream], "");
3495 ac_build_ifcc(&ctx->ac, cond, 5240);
3496 {
3497 LLVMValueRef offset_vtx =
3498 LLVMBuildMul(builder, primemit_scan[stream].result_exclusive,
3499 nggso->num_vertices, "");
3500
3501 for (unsigned i = 0; i < max_num_vertices; ++i) {
3502 cond = LLVMBuildICmp(builder, LLVMIntULT,
3503 LLVMConstInt(ctx->ac.i32, i, false),
3504 nggso->num_vertices, "");
3505 ac_build_ifcc(&ctx->ac, cond, 5241);
3506 build_streamout_vertex(ctx, so_buffer, wgoffset_dw,
3507 stream, offset_vtx, nggso->vertices[i]);
3508 ac_build_endif(&ctx->ac, 5241);
3509 offset_vtx = LLVMBuildAdd(builder, offset_vtx, ctx->ac.i32_1, "");
3510 }
3511 }
3512 ac_build_endif(&ctx->ac, 5240);
3513 }
3514 }
3515
3516 static unsigned ngg_nogs_vertex_size(struct radv_shader_context *ctx)
3517 {
3518 unsigned lds_vertex_size = 0;
3519
3520 if (ctx->shader_info->so.num_outputs)
3521 lds_vertex_size = 4 * ctx->shader_info->so.num_outputs + 1;
3522
3523 return lds_vertex_size;
3524 }
3525
3526 /**
3527 * Returns an `[N x i32] addrspace(LDS)*` pointing at contiguous LDS storage
3528 * for the vertex outputs.
3529 */
3530 static LLVMValueRef ngg_nogs_vertex_ptr(struct radv_shader_context *ctx,
3531 LLVMValueRef vtxid)
3532 {
3533 /* The extra dword is used to avoid LDS bank conflicts. */
3534 unsigned vertex_size = ngg_nogs_vertex_size(ctx);
3535 LLVMTypeRef ai32 = LLVMArrayType(ctx->ac.i32, vertex_size);
3536 LLVMTypeRef pai32 = LLVMPointerType(ai32, AC_ADDR_SPACE_LDS);
3537 LLVMValueRef tmp = LLVMBuildBitCast(ctx->ac.builder, ctx->esgs_ring, pai32, "");
3538 return LLVMBuildGEP(ctx->ac.builder, tmp, &vtxid, 1, "");
3539 }
3540
3541 static void
3542 handle_ngg_outputs_post_1(struct radv_shader_context *ctx)
3543 {
3544 LLVMBuilderRef builder = ctx->ac.builder;
3545 LLVMValueRef vertex_ptr = NULL;
3546 LLVMValueRef tmp, tmp2;
3547
3548 assert((ctx->stage == MESA_SHADER_VERTEX ||
3549 ctx->stage == MESA_SHADER_TESS_EVAL) && !ctx->is_gs_copy_shader);
3550
3551 if (!ctx->shader_info->so.num_outputs)
3552 return;
3553
3554 vertex_ptr = ngg_nogs_vertex_ptr(ctx, get_thread_id_in_tg(ctx));
3555
3556 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
3557 if (!(ctx->output_mask & (1ull << i)))
3558 continue;
3559
3560 for (unsigned j = 0; j < 4; j++) {
3561 tmp = ac_build_gep0(&ctx->ac, vertex_ptr,
3562 LLVMConstInt(ctx->ac.i32, 4 * i + j, false));
3563 tmp2 = LLVMBuildLoad(builder,
3564 ctx->abi.outputs[4 * i + j], "");
3565 tmp2 = ac_to_integer(&ctx->ac, tmp2);
3566 LLVMBuildStore(builder, tmp2, tmp);
3567 }
3568 }
3569 }
3570
3571 static void
3572 handle_ngg_outputs_post_2(struct radv_shader_context *ctx)
3573 {
3574 LLVMBuilderRef builder = ctx->ac.builder;
3575 LLVMValueRef tmp;
3576
3577 assert((ctx->stage == MESA_SHADER_VERTEX ||
3578 ctx->stage == MESA_SHADER_TESS_EVAL) && !ctx->is_gs_copy_shader);
3579
3580 LLVMValueRef prims_in_wave = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 8, 8);
3581 LLVMValueRef vtx_in_wave = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 0, 8);
3582 LLVMValueRef is_gs_thread = LLVMBuildICmp(builder, LLVMIntULT,
3583 ac_get_thread_id(&ctx->ac), prims_in_wave, "");
3584 LLVMValueRef is_es_thread = LLVMBuildICmp(builder, LLVMIntULT,
3585 ac_get_thread_id(&ctx->ac), vtx_in_wave, "");
3586 LLVMValueRef vtxindex[] = {
3587 ac_unpack_param(&ctx->ac, ctx->gs_vtx_offset[0], 0, 16),
3588 ac_unpack_param(&ctx->ac, ctx->gs_vtx_offset[0], 16, 16),
3589 ac_unpack_param(&ctx->ac, ctx->gs_vtx_offset[2], 0, 16),
3590 };
3591
3592 /* Determine the number of vertices per primitive. */
3593 unsigned num_vertices;
3594 LLVMValueRef num_vertices_val;
3595
3596 if (ctx->stage == MESA_SHADER_VERTEX) {
3597 num_vertices_val = LLVMConstInt(ctx->ac.i32, 1, false);
3598 num_vertices = 3; /* TODO: optimize for points & lines */
3599 } else {
3600 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
3601
3602 if (ctx->shader->info.tess.point_mode)
3603 num_vertices = 1;
3604 else if (ctx->shader->info.tess.primitive_mode == GL_ISOLINES)
3605 num_vertices = 2;
3606 else
3607 num_vertices = 3;
3608
3609 num_vertices_val = LLVMConstInt(ctx->ac.i32, num_vertices, false);
3610 }
3611
3612 /* Streamout */
3613 if (ctx->shader_info->so.num_outputs) {
3614 struct ngg_streamout nggso = {};
3615
3616 nggso.num_vertices = num_vertices_val;
3617 nggso.prim_enable[0] = is_gs_thread;
3618
3619 for (unsigned i = 0; i < num_vertices; ++i)
3620 nggso.vertices[i] = ngg_nogs_vertex_ptr(ctx, vtxindex[i]);
3621
3622 build_streamout(ctx, &nggso);
3623 }
3624
3625 /* Copy Primitive IDs from GS threads to the LDS address corresponding
3626 * to the ES thread of the provoking vertex.
3627 */
3628 if (ctx->stage == MESA_SHADER_VERTEX &&
3629 ctx->options->key.vs_common_out.export_prim_id) {
3630 if (ctx->shader_info->so.num_outputs)
3631 ac_build_s_barrier(&ctx->ac);
3632
3633 ac_build_ifcc(&ctx->ac, is_gs_thread, 5400);
3634 /* Extract the PROVOKING_VTX_INDEX field. */
3635 LLVMValueRef provoking_vtx_in_prim =
3636 LLVMConstInt(ctx->ac.i32, 0, false);
3637
3638 /* provoking_vtx_index = vtxindex[provoking_vtx_in_prim]; */
3639 LLVMValueRef indices = ac_build_gather_values(&ctx->ac, vtxindex, 3);
3640 LLVMValueRef provoking_vtx_index =
3641 LLVMBuildExtractElement(builder, indices, provoking_vtx_in_prim, "");
3642
3643 LLVMBuildStore(builder, ctx->abi.gs_prim_id,
3644 ac_build_gep0(&ctx->ac, ctx->esgs_ring, provoking_vtx_index));
3645 ac_build_endif(&ctx->ac, 5400);
3646 }
3647
3648 /* TODO: primitive culling */
3649
3650 build_sendmsg_gs_alloc_req(ctx, ngg_get_vtx_cnt(ctx), ngg_get_prim_cnt(ctx));
3651
3652 /* TODO: streamout queries */
3653 /* Export primitive data to the index buffer. Format is:
3654 * - bits 0..8: index 0
3655 * - bit 9: edge flag 0
3656 * - bits 10..18: index 1
3657 * - bit 19: edge flag 1
3658 * - bits 20..28: index 2
3659 * - bit 29: edge flag 2
3660 * - bit 31: null primitive (skip)
3661 *
3662 * For the first version, we will always build up all three indices
3663 * independent of the primitive type. The additional garbage data
3664 * shouldn't hurt.
3665 *
3666 * TODO: culling depends on the primitive type, so can have some
3667 * interaction here.
3668 */
3669 ac_build_ifcc(&ctx->ac, is_gs_thread, 6001);
3670 {
3671 struct ngg_prim prim = {};
3672
3673 prim.num_vertices = num_vertices;
3674 prim.isnull = ctx->ac.i1false;
3675 memcpy(prim.index, vtxindex, sizeof(vtxindex[0]) * 3);
3676
3677 for (unsigned i = 0; i < num_vertices; ++i) {
3678 tmp = LLVMBuildLShr(builder, ctx->abi.gs_invocation_id,
3679 LLVMConstInt(ctx->ac.i32, 8 + i, false), "");
3680 prim.edgeflag[i] = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3681 }
3682
3683 build_export_prim(ctx, &prim);
3684 }
3685 ac_build_endif(&ctx->ac, 6001);
3686
3687 /* Export per-vertex data (positions and parameters). */
3688 ac_build_ifcc(&ctx->ac, is_es_thread, 6002);
3689 {
3690 struct radv_vs_output_info *outinfo =
3691 ctx->stage == MESA_SHADER_TESS_EVAL ? &ctx->shader_info->tes.outinfo : &ctx->shader_info->vs.outinfo;
3692
3693 /* Exporting the primitive ID is handled below. */
3694 /* TODO: use the new VS export path */
3695 handle_vs_outputs_post(ctx, false,
3696 ctx->options->key.vs_common_out.export_clip_dists,
3697 outinfo);
3698
3699 if (ctx->options->key.vs_common_out.export_prim_id) {
3700 unsigned param_count = outinfo->param_exports;
3701 LLVMValueRef values[4];
3702
3703 if (ctx->stage == MESA_SHADER_VERTEX) {
3704 /* Wait for GS stores to finish. */
3705 ac_build_s_barrier(&ctx->ac);
3706
3707 tmp = ac_build_gep0(&ctx->ac, ctx->esgs_ring,
3708 get_thread_id_in_tg(ctx));
3709 values[0] = LLVMBuildLoad(builder, tmp, "");
3710 } else {
3711 assert(ctx->stage == MESA_SHADER_TESS_EVAL);
3712 values[0] = ctx->abi.tes_patch_id;
3713 }
3714
3715 values[0] = ac_to_float(&ctx->ac, values[0]);
3716 for (unsigned j = 1; j < 4; j++)
3717 values[j] = ctx->ac.f32_0;
3718
3719 radv_export_param(ctx, param_count, values, 0x1);
3720
3721 outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID] = param_count++;
3722 outinfo->param_exports = param_count;
3723 }
3724 }
3725 ac_build_endif(&ctx->ac, 6002);
3726 }
3727
3728 static void gfx10_ngg_gs_emit_prologue(struct radv_shader_context *ctx)
3729 {
3730 /* Zero out the part of LDS scratch that is used to accumulate the
3731 * per-stream generated primitive count.
3732 */
3733 LLVMBuilderRef builder = ctx->ac.builder;
3734 LLVMValueRef scratchptr = ctx->gs_ngg_scratch;
3735 LLVMValueRef tid = get_thread_id_in_tg(ctx);
3736 LLVMBasicBlockRef merge_block;
3737 LLVMValueRef cond;
3738
3739 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx->ac.builder));
3740 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
3741 merge_block = LLVMAppendBasicBlockInContext(ctx->ac.context, fn, "");
3742
3743 cond = LLVMBuildICmp(builder, LLVMIntULT, tid, LLVMConstInt(ctx->ac.i32, 4, false), "");
3744 LLVMBuildCondBr(ctx->ac.builder, cond, then_block, merge_block);
3745 LLVMPositionBuilderAtEnd(ctx->ac.builder, then_block);
3746
3747 LLVMValueRef ptr = ac_build_gep0(&ctx->ac, scratchptr, tid);
3748 LLVMBuildStore(builder, ctx->ac.i32_0, ptr);
3749
3750 LLVMBuildBr(ctx->ac.builder, merge_block);
3751 LLVMPositionBuilderAtEnd(ctx->ac.builder, merge_block);
3752
3753 ac_build_s_barrier(&ctx->ac);
3754 }
3755
3756 static void gfx10_ngg_gs_emit_epilogue_1(struct radv_shader_context *ctx)
3757 {
3758 LLVMBuilderRef builder = ctx->ac.builder;
3759 LLVMValueRef i8_0 = LLVMConstInt(ctx->ac.i8, 0, false);
3760 LLVMValueRef tmp;
3761
3762 /* Zero out remaining (non-emitted) primitive flags.
3763 *
3764 * Note: Alternatively, we could pass the relevant gs_next_vertex to
3765 * the emit threads via LDS. This is likely worse in the expected
3766 * typical case where each GS thread emits the full set of
3767 * vertices.
3768 */
3769 for (unsigned stream = 0; stream < 4; ++stream) {
3770 unsigned num_components;
3771
3772 num_components =
3773 ctx->shader_info->gs.num_stream_output_components[stream];
3774 if (!num_components)
3775 continue;
3776
3777 const LLVMValueRef gsthread = get_thread_id_in_tg(ctx);
3778
3779 ac_build_bgnloop(&ctx->ac, 5100);
3780
3781 const LLVMValueRef vertexidx =
3782 LLVMBuildLoad(builder, ctx->gs_next_vertex[stream], "");
3783 tmp = LLVMBuildICmp(builder, LLVMIntUGE, vertexidx,
3784 LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false), "");
3785 ac_build_ifcc(&ctx->ac, tmp, 5101);
3786 ac_build_break(&ctx->ac);
3787 ac_build_endif(&ctx->ac, 5101);
3788
3789 tmp = LLVMBuildAdd(builder, vertexidx, ctx->ac.i32_1, "");
3790 LLVMBuildStore(builder, tmp, ctx->gs_next_vertex[stream]);
3791
3792 tmp = ngg_gs_emit_vertex_ptr(ctx, gsthread, vertexidx);
3793 LLVMValueRef gep_idx[3] = {
3794 ctx->ac.i32_0, /* implied C-style array */
3795 ctx->ac.i32_1, /* second entry of struct */
3796 LLVMConstInt(ctx->ac.i32, stream, false),
3797 };
3798 tmp = LLVMBuildGEP(builder, tmp, gep_idx, 3, "");
3799 LLVMBuildStore(builder, i8_0, tmp);
3800
3801 ac_build_endloop(&ctx->ac, 5100);
3802 }
3803
3804 /* Accumulate generated primitives counts across the entire threadgroup. */
3805 for (unsigned stream = 0; stream < 4; ++stream) {
3806 unsigned num_components;
3807
3808 num_components =
3809 ctx->shader_info->gs.num_stream_output_components[stream];
3810 if (!num_components)
3811 continue;
3812
3813 LLVMValueRef numprims =
3814 LLVMBuildLoad(builder, ctx->gs_generated_prims[stream], "");
3815 numprims = ac_build_reduce(&ctx->ac, numprims, nir_op_iadd, ctx->ac.wave_size);
3816
3817 tmp = LLVMBuildICmp(builder, LLVMIntEQ, ac_get_thread_id(&ctx->ac), ctx->ac.i32_0, "");
3818 ac_build_ifcc(&ctx->ac, tmp, 5105);
3819 {
3820 LLVMBuildAtomicRMW(builder, LLVMAtomicRMWBinOpAdd,
3821 ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch,
3822 LLVMConstInt(ctx->ac.i32, stream, false)),
3823 numprims, LLVMAtomicOrderingMonotonic, false);
3824 }
3825 ac_build_endif(&ctx->ac, 5105);
3826 }
3827 }
3828
3829 static void gfx10_ngg_gs_emit_epilogue_2(struct radv_shader_context *ctx)
3830 {
3831 const unsigned verts_per_prim = si_conv_gl_prim_to_vertices(ctx->shader->info.gs.output_primitive);
3832 LLVMBuilderRef builder = ctx->ac.builder;
3833 LLVMValueRef tmp, tmp2;
3834
3835 ac_build_s_barrier(&ctx->ac);
3836
3837 const LLVMValueRef tid = get_thread_id_in_tg(ctx);
3838 LLVMValueRef num_emit_threads = ngg_get_prim_cnt(ctx);
3839
3840 /* Streamout */
3841 if (ctx->shader_info->so.num_outputs) {
3842 struct ngg_streamout nggso = {};
3843
3844 nggso.num_vertices = LLVMConstInt(ctx->ac.i32, verts_per_prim, false);
3845
3846 LLVMValueRef vertexptr = ngg_gs_vertex_ptr(ctx, tid);
3847 for (unsigned stream = 0; stream < 4; ++stream) {
3848 if (!ctx->shader_info->gs.num_stream_output_components[stream])
3849 continue;
3850
3851 LLVMValueRef gep_idx[3] = {
3852 ctx->ac.i32_0, /* implicit C-style array */
3853 ctx->ac.i32_1, /* second value of struct */
3854 LLVMConstInt(ctx->ac.i32, stream, false),
3855 };
3856 tmp = LLVMBuildGEP(builder, vertexptr, gep_idx, 3, "");
3857 tmp = LLVMBuildLoad(builder, tmp, "");
3858 tmp = LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3859 tmp2 = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
3860 nggso.prim_enable[stream] = LLVMBuildAnd(builder, tmp, tmp2, "");
3861 }
3862
3863 for (unsigned i = 0; i < verts_per_prim; ++i) {
3864 tmp = LLVMBuildSub(builder, tid,
3865 LLVMConstInt(ctx->ac.i32, verts_per_prim - i - 1, false), "");
3866 tmp = ngg_gs_vertex_ptr(ctx, tmp);
3867 nggso.vertices[i] = ac_build_gep0(&ctx->ac, tmp, ctx->ac.i32_0);
3868 }
3869
3870 build_streamout(ctx, &nggso);
3871 }
3872
3873 /* TODO: culling */
3874
3875 /* Determine vertex liveness. */
3876 LLVMValueRef vertliveptr = ac_build_alloca(&ctx->ac, ctx->ac.i1, "vertexlive");
3877
3878 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
3879 ac_build_ifcc(&ctx->ac, tmp, 5120);
3880 {
3881 for (unsigned i = 0; i < verts_per_prim; ++i) {
3882 const LLVMValueRef primidx =
3883 LLVMBuildAdd(builder, tid,
3884 LLVMConstInt(ctx->ac.i32, i, false), "");
3885
3886 if (i > 0) {
3887 tmp = LLVMBuildICmp(builder, LLVMIntULT, primidx, num_emit_threads, "");
3888 ac_build_ifcc(&ctx->ac, tmp, 5121 + i);
3889 }
3890
3891 /* Load primitive liveness */
3892 tmp = ngg_gs_vertex_ptr(ctx, primidx);
3893 LLVMValueRef gep_idx[3] = {
3894 ctx->ac.i32_0, /* implicit C-style array */
3895 ctx->ac.i32_1, /* second value of struct */
3896 ctx->ac.i32_0, /* stream 0 */
3897 };
3898 tmp = LLVMBuildGEP(builder, tmp, gep_idx, 3, "");
3899 tmp = LLVMBuildLoad(builder, tmp, "");
3900 const LLVMValueRef primlive =
3901 LLVMBuildTrunc(builder, tmp, ctx->ac.i1, "");
3902
3903 tmp = LLVMBuildLoad(builder, vertliveptr, "");
3904 tmp = LLVMBuildOr(builder, tmp, primlive, ""),
3905 LLVMBuildStore(builder, tmp, vertliveptr);
3906
3907 if (i > 0)
3908 ac_build_endif(&ctx->ac, 5121 + i);
3909 }
3910 }
3911 ac_build_endif(&ctx->ac, 5120);
3912
3913 /* Inclusive scan addition across the current wave. */
3914 LLVMValueRef vertlive = LLVMBuildLoad(builder, vertliveptr, "");
3915 struct ac_wg_scan vertlive_scan = {};
3916 vertlive_scan.op = nir_op_iadd;
3917 vertlive_scan.enable_reduce = true;
3918 vertlive_scan.enable_exclusive = true;
3919 vertlive_scan.src = vertlive;
3920 vertlive_scan.scratch = ac_build_gep0(&ctx->ac, ctx->gs_ngg_scratch, ctx->ac.i32_0);
3921 vertlive_scan.waveidx = get_wave_id_in_tg(ctx);
3922 vertlive_scan.numwaves = get_tgsize(ctx);
3923 vertlive_scan.maxwaves = 8;
3924
3925 ac_build_wg_scan(&ctx->ac, &vertlive_scan);
3926
3927 /* Skip all exports (including index exports) when possible. At least on
3928 * early gfx10 revisions this is also to avoid hangs.
3929 */
3930 LLVMValueRef have_exports =
3931 LLVMBuildICmp(builder, LLVMIntNE, vertlive_scan.result_reduce, ctx->ac.i32_0, "");
3932 num_emit_threads =
3933 LLVMBuildSelect(builder, have_exports, num_emit_threads, ctx->ac.i32_0, "");
3934
3935 /* Allocate export space. Send this message as early as possible, to
3936 * hide the latency of the SQ <-> SPI roundtrip.
3937 *
3938 * Note: We could consider compacting primitives for export as well.
3939 * PA processes 1 non-null prim / clock, but it fetches 4 DW of
3940 * prim data per clock and skips null primitives at no additional
3941 * cost. So compacting primitives can only be beneficial when
3942 * there are 4 or more contiguous null primitives in the export
3943 * (in the common case of single-dword prim exports).
3944 */
3945 build_sendmsg_gs_alloc_req(ctx, vertlive_scan.result_reduce, num_emit_threads);
3946
3947 /* Setup the reverse vertex compaction permutation. We re-use stream 1
3948 * of the primitive liveness flags, relying on the fact that each
3949 * threadgroup can have at most 256 threads. */
3950 ac_build_ifcc(&ctx->ac, vertlive, 5130);
3951 {
3952 tmp = ngg_gs_vertex_ptr(ctx, vertlive_scan.result_exclusive);
3953 LLVMValueRef gep_idx[3] = {
3954 ctx->ac.i32_0, /* implicit C-style array */
3955 ctx->ac.i32_1, /* second value of struct */
3956 ctx->ac.i32_1, /* stream 1 */
3957 };
3958 tmp = LLVMBuildGEP(builder, tmp, gep_idx, 3, "");
3959 tmp2 = LLVMBuildTrunc(builder, tid, ctx->ac.i8, "");
3960 LLVMBuildStore(builder, tmp2, tmp);
3961 }
3962 ac_build_endif(&ctx->ac, 5130);
3963
3964 ac_build_s_barrier(&ctx->ac);
3965
3966 /* Export primitive data */
3967 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, num_emit_threads, "");
3968 ac_build_ifcc(&ctx->ac, tmp, 5140);
3969 {
3970 struct ngg_prim prim = {};
3971 prim.num_vertices = verts_per_prim;
3972
3973 tmp = ngg_gs_vertex_ptr(ctx, tid);
3974 LLVMValueRef gep_idx[3] = {
3975 ctx->ac.i32_0, /* implicit C-style array */
3976 ctx->ac.i32_1, /* second value of struct */
3977 ctx->ac.i32_0, /* primflag */
3978 };
3979 tmp = LLVMBuildGEP(builder, tmp, gep_idx, 3, "");
3980 tmp = LLVMBuildLoad(builder, tmp, "");
3981 prim.isnull = LLVMBuildICmp(builder, LLVMIntEQ, tmp,
3982 LLVMConstInt(ctx->ac.i8, 0, false), "");
3983
3984 for (unsigned i = 0; i < verts_per_prim; ++i) {
3985 prim.index[i] = LLVMBuildSub(builder, vertlive_scan.result_exclusive,
3986 LLVMConstInt(ctx->ac.i32, verts_per_prim - i - 1, false), "");
3987 prim.edgeflag[i] = ctx->ac.i1false;
3988 }
3989
3990 build_export_prim(ctx, &prim);
3991 }
3992 ac_build_endif(&ctx->ac, 5140);
3993
3994 /* Export position and parameter data */
3995 tmp = LLVMBuildICmp(builder, LLVMIntULT, tid, vertlive_scan.result_reduce, "");
3996 ac_build_ifcc(&ctx->ac, tmp, 5145);
3997 {
3998 struct radv_vs_output_info *outinfo = &ctx->shader_info->vs.outinfo;
3999 bool export_view_index = ctx->options->key.has_multiview_view_index;
4000 struct radv_shader_output_values *outputs;
4001 unsigned noutput = 0;
4002
4003 /* Allocate a temporary array for the output values. */
4004 unsigned num_outputs = util_bitcount64(ctx->output_mask) + export_view_index;
4005 outputs = calloc(num_outputs, sizeof(outputs[0]));
4006
4007 memset(outinfo->vs_output_param_offset, AC_EXP_PARAM_UNDEFINED,
4008 sizeof(outinfo->vs_output_param_offset));
4009 outinfo->pos_exports = 0;
4010
4011 tmp = ngg_gs_vertex_ptr(ctx, tid);
4012 LLVMValueRef gep_idx[3] = {
4013 ctx->ac.i32_0, /* implicit C-style array */
4014 ctx->ac.i32_1, /* second value of struct */
4015 ctx->ac.i32_1, /* stream 1: source data index */
4016 };
4017 tmp = LLVMBuildGEP(builder, tmp, gep_idx, 3, "");
4018 tmp = LLVMBuildLoad(builder, tmp, "");
4019 tmp = LLVMBuildZExt(builder, tmp, ctx->ac.i32, "");
4020 const LLVMValueRef vertexptr = ngg_gs_vertex_ptr(ctx, tmp);
4021
4022 unsigned out_idx = 0;
4023 gep_idx[1] = ctx->ac.i32_0;
4024 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
4025 unsigned output_usage_mask =
4026 ctx->shader_info->gs.output_usage_mask[i];
4027 int length = util_last_bit(output_usage_mask);
4028
4029 if (!(ctx->output_mask & (1ull << i)))
4030 continue;
4031
4032 outputs[noutput].slot_name = i;
4033 outputs[noutput].slot_index = i == VARYING_SLOT_CLIP_DIST1;
4034 outputs[noutput].usage_mask = output_usage_mask;
4035
4036 for (unsigned j = 0; j < length; j++, out_idx++) {
4037 if (!(output_usage_mask & (1 << j)))
4038 continue;
4039
4040 gep_idx[2] = LLVMConstInt(ctx->ac.i32, out_idx, false);
4041 tmp = LLVMBuildGEP(builder, vertexptr, gep_idx, 3, "");
4042 tmp = LLVMBuildLoad(builder, tmp, "");
4043
4044 LLVMTypeRef type = LLVMGetAllocatedType(ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
4045 if (ac_get_type_size(type) == 2) {
4046 tmp = ac_to_integer(&ctx->ac, tmp);
4047 tmp = LLVMBuildTrunc(ctx->ac.builder, tmp, ctx->ac.i16, "");
4048 }
4049
4050 outputs[noutput].values[j] = ac_to_float(&ctx->ac, tmp);
4051 }
4052
4053 for (unsigned j = length; j < 4; j++)
4054 outputs[noutput].values[j] = LLVMGetUndef(ctx->ac.f32);
4055
4056 noutput++;
4057 }
4058
4059 /* Export ViewIndex. */
4060 if (export_view_index) {
4061 outputs[noutput].slot_name = VARYING_SLOT_LAYER;
4062 outputs[noutput].slot_index = 0;
4063 outputs[noutput].usage_mask = 0x1;
4064 outputs[noutput].values[0] = ac_to_float(&ctx->ac, ctx->abi.view_index);
4065 for (unsigned j = 1; j < 4; j++)
4066 outputs[noutput].values[j] = ctx->ac.f32_0;
4067 noutput++;
4068 }
4069
4070 radv_llvm_export_vs(ctx, outputs, noutput, outinfo,
4071 ctx->options->key.vs_common_out.export_clip_dists);
4072 FREE(outputs);
4073 }
4074 ac_build_endif(&ctx->ac, 5145);
4075 }
4076
4077 static void gfx10_ngg_gs_emit_vertex(struct radv_shader_context *ctx,
4078 unsigned stream,
4079 LLVMValueRef *addrs)
4080 {
4081 LLVMBuilderRef builder = ctx->ac.builder;
4082 LLVMValueRef tmp;
4083 const LLVMValueRef vertexidx =
4084 LLVMBuildLoad(builder, ctx->gs_next_vertex[stream], "");
4085
4086 /* If this thread has already emitted the declared maximum number of
4087 * vertices, skip the write: excessive vertex emissions are not
4088 * supposed to have any effect.
4089 */
4090 const LLVMValueRef can_emit =
4091 LLVMBuildICmp(builder, LLVMIntULT, vertexidx,
4092 LLVMConstInt(ctx->ac.i32, ctx->shader->info.gs.vertices_out, false), "");
4093 ac_build_kill_if_false(&ctx->ac, can_emit);
4094
4095 tmp = LLVMBuildAdd(builder, vertexidx, ctx->ac.i32_1, "");
4096 tmp = LLVMBuildSelect(builder, can_emit, tmp, vertexidx, "");
4097 LLVMBuildStore(builder, tmp, ctx->gs_next_vertex[stream]);
4098
4099 const LLVMValueRef vertexptr =
4100 ngg_gs_emit_vertex_ptr(ctx, get_thread_id_in_tg(ctx), vertexidx);
4101 unsigned out_idx = 0;
4102 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
4103 unsigned output_usage_mask =
4104 ctx->shader_info->gs.output_usage_mask[i];
4105 uint8_t output_stream =
4106 ctx->shader_info->gs.output_streams[i];
4107 LLVMValueRef *out_ptr = &addrs[i * 4];
4108 int length = util_last_bit(output_usage_mask);
4109
4110 if (!(ctx->output_mask & (1ull << i)) ||
4111 output_stream != stream)
4112 continue;
4113
4114 for (unsigned j = 0; j < length; j++, out_idx++) {
4115 if (!(output_usage_mask & (1 << j)))
4116 continue;
4117
4118 LLVMValueRef out_val = LLVMBuildLoad(ctx->ac.builder,
4119 out_ptr[j], "");
4120 LLVMValueRef gep_idx[3] = {
4121 ctx->ac.i32_0, /* implied C-style array */
4122 ctx->ac.i32_0, /* first entry of struct */
4123 LLVMConstInt(ctx->ac.i32, out_idx, false),
4124 };
4125 LLVMValueRef ptr = LLVMBuildGEP(builder, vertexptr, gep_idx, 3, "");
4126
4127 out_val = ac_to_integer(&ctx->ac, out_val);
4128 out_val = LLVMBuildZExtOrBitCast(ctx->ac.builder, out_val, ctx->ac.i32, "");
4129
4130 LLVMBuildStore(builder, out_val, ptr);
4131 }
4132 }
4133 assert(out_idx * 4 <= ctx->shader_info->gs.gsvs_vertex_size);
4134
4135 /* Determine and store whether this vertex completed a primitive. */
4136 const LLVMValueRef curverts = LLVMBuildLoad(builder, ctx->gs_curprim_verts[stream], "");
4137
4138 tmp = LLVMConstInt(ctx->ac.i32, si_conv_gl_prim_to_vertices(ctx->shader->info.gs.output_primitive) - 1, false);
4139 const LLVMValueRef iscompleteprim =
4140 LLVMBuildICmp(builder, LLVMIntUGE, curverts, tmp, "");
4141
4142 tmp = LLVMBuildAdd(builder, curverts, ctx->ac.i32_1, "");
4143 LLVMBuildStore(builder, tmp, ctx->gs_curprim_verts[stream]);
4144
4145 LLVMValueRef gep_idx[3] = {
4146 ctx->ac.i32_0, /* implied C-style array */
4147 ctx->ac.i32_1, /* second struct entry */
4148 LLVMConstInt(ctx->ac.i32, stream, false),
4149 };
4150 const LLVMValueRef primflagptr =
4151 LLVMBuildGEP(builder, vertexptr, gep_idx, 3, "");
4152
4153 tmp = LLVMBuildZExt(builder, iscompleteprim, ctx->ac.i8, "");
4154 LLVMBuildStore(builder, tmp, primflagptr);
4155
4156 tmp = LLVMBuildLoad(builder, ctx->gs_generated_prims[stream], "");
4157 tmp = LLVMBuildAdd(builder, tmp, LLVMBuildZExt(builder, iscompleteprim, ctx->ac.i32, ""), "");
4158 LLVMBuildStore(builder, tmp, ctx->gs_generated_prims[stream]);
4159 }
4160
4161 static void
4162 write_tess_factors(struct radv_shader_context *ctx)
4163 {
4164 unsigned stride, outer_comps, inner_comps;
4165 LLVMValueRef invocation_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 8, 5);
4166 LLVMValueRef rel_patch_id = ac_unpack_param(&ctx->ac, ctx->abi.tcs_rel_ids, 0, 8);
4167 unsigned tess_inner_index = 0, tess_outer_index;
4168 LLVMValueRef lds_base, lds_inner = NULL, lds_outer, byteoffset, buffer;
4169 LLVMValueRef out[6], vec0, vec1, tf_base, inner[4], outer[4];
4170 int i;
4171 ac_emit_barrier(&ctx->ac, ctx->stage);
4172
4173 switch (ctx->options->key.tcs.primitive_mode) {
4174 case GL_ISOLINES:
4175 stride = 2;
4176 outer_comps = 2;
4177 inner_comps = 0;
4178 break;
4179 case GL_TRIANGLES:
4180 stride = 4;
4181 outer_comps = 3;
4182 inner_comps = 1;
4183 break;
4184 case GL_QUADS:
4185 stride = 6;
4186 outer_comps = 4;
4187 inner_comps = 2;
4188 break;
4189 default:
4190 return;
4191 }
4192
4193 ac_build_ifcc(&ctx->ac,
4194 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
4195 invocation_id, ctx->ac.i32_0, ""), 6503);
4196
4197 lds_base = get_tcs_out_current_patch_data_offset(ctx);
4198
4199 if (inner_comps) {
4200 tess_inner_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
4201 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_base,
4202 LLVMConstInt(ctx->ac.i32, tess_inner_index * 4, false), "");
4203 }
4204
4205 tess_outer_index = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
4206 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_base,
4207 LLVMConstInt(ctx->ac.i32, tess_outer_index * 4, false), "");
4208
4209 for (i = 0; i < 4; i++) {
4210 inner[i] = LLVMGetUndef(ctx->ac.i32);
4211 outer[i] = LLVMGetUndef(ctx->ac.i32);
4212 }
4213
4214 // LINES reversal
4215 if (ctx->options->key.tcs.primitive_mode == GL_ISOLINES) {
4216 outer[0] = out[1] = ac_lds_load(&ctx->ac, lds_outer);
4217 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
4218 ctx->ac.i32_1, "");
4219 outer[1] = out[0] = ac_lds_load(&ctx->ac, lds_outer);
4220 } else {
4221 for (i = 0; i < outer_comps; i++) {
4222 outer[i] = out[i] =
4223 ac_lds_load(&ctx->ac, lds_outer);
4224 lds_outer = LLVMBuildAdd(ctx->ac.builder, lds_outer,
4225 ctx->ac.i32_1, "");
4226 }
4227 for (i = 0; i < inner_comps; i++) {
4228 inner[i] = out[outer_comps+i] =
4229 ac_lds_load(&ctx->ac, lds_inner);
4230 lds_inner = LLVMBuildAdd(ctx->ac.builder, lds_inner,
4231 ctx->ac.i32_1, "");
4232 }
4233 }
4234
4235 /* Convert the outputs to vectors for stores. */
4236 vec0 = ac_build_gather_values(&ctx->ac, out, MIN2(stride, 4));
4237 vec1 = NULL;
4238
4239 if (stride > 4)
4240 vec1 = ac_build_gather_values(&ctx->ac, out + 4, stride - 4);
4241
4242
4243 buffer = ctx->hs_ring_tess_factor;
4244 tf_base = ctx->tess_factor_offset;
4245 byteoffset = LLVMBuildMul(ctx->ac.builder, rel_patch_id,
4246 LLVMConstInt(ctx->ac.i32, 4 * stride, false), "");
4247 unsigned tf_offset = 0;
4248
4249 if (ctx->options->chip_class <= GFX8) {
4250 ac_build_ifcc(&ctx->ac,
4251 LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ,
4252 rel_patch_id, ctx->ac.i32_0, ""), 6504);
4253
4254 /* Store the dynamic HS control word. */
4255 ac_build_buffer_store_dword(&ctx->ac, buffer,
4256 LLVMConstInt(ctx->ac.i32, 0x80000000, false),
4257 1, ctx->ac.i32_0, tf_base,
4258 0, ac_glc, false);
4259 tf_offset += 4;
4260
4261 ac_build_endif(&ctx->ac, 6504);
4262 }
4263
4264 /* Store the tessellation factors. */
4265 ac_build_buffer_store_dword(&ctx->ac, buffer, vec0,
4266 MIN2(stride, 4), byteoffset, tf_base,
4267 tf_offset, ac_glc, false);
4268 if (vec1)
4269 ac_build_buffer_store_dword(&ctx->ac, buffer, vec1,
4270 stride - 4, byteoffset, tf_base,
4271 16 + tf_offset, ac_glc, false);
4272
4273 //store to offchip for TES to read - only if TES reads them
4274 if (ctx->options->key.tcs.tes_reads_tess_factors) {
4275 LLVMValueRef inner_vec, outer_vec, tf_outer_offset;
4276 LLVMValueRef tf_inner_offset;
4277 unsigned param_outer, param_inner;
4278
4279 param_outer = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_OUTER);
4280 tf_outer_offset = get_tcs_tes_buffer_address(ctx, NULL,
4281 LLVMConstInt(ctx->ac.i32, param_outer, 0));
4282
4283 outer_vec = ac_build_gather_values(&ctx->ac, outer,
4284 util_next_power_of_two(outer_comps));
4285
4286 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, outer_vec,
4287 outer_comps, tf_outer_offset,
4288 ctx->oc_lds, 0, ac_glc, false);
4289 if (inner_comps) {
4290 param_inner = shader_io_get_unique_index(VARYING_SLOT_TESS_LEVEL_INNER);
4291 tf_inner_offset = get_tcs_tes_buffer_address(ctx, NULL,
4292 LLVMConstInt(ctx->ac.i32, param_inner, 0));
4293
4294 inner_vec = inner_comps == 1 ? inner[0] :
4295 ac_build_gather_values(&ctx->ac, inner, inner_comps);
4296 ac_build_buffer_store_dword(&ctx->ac, ctx->hs_ring_tess_offchip, inner_vec,
4297 inner_comps, tf_inner_offset,
4298 ctx->oc_lds, 0, ac_glc, false);
4299 }
4300 }
4301
4302 ac_build_endif(&ctx->ac, 6503);
4303 }
4304
4305 static void
4306 handle_tcs_outputs_post(struct radv_shader_context *ctx)
4307 {
4308 write_tess_factors(ctx);
4309 }
4310
4311 static bool
4312 si_export_mrt_color(struct radv_shader_context *ctx,
4313 LLVMValueRef *color, unsigned index,
4314 struct ac_export_args *args)
4315 {
4316 /* Export */
4317 si_llvm_init_export_args(ctx, color, 0xf,
4318 V_008DFC_SQ_EXP_MRT + index, args);
4319 if (!args->enabled_channels)
4320 return false; /* unnecessary NULL export */
4321
4322 return true;
4323 }
4324
4325 static void
4326 radv_export_mrt_z(struct radv_shader_context *ctx,
4327 LLVMValueRef depth, LLVMValueRef stencil,
4328 LLVMValueRef samplemask)
4329 {
4330 struct ac_export_args args;
4331
4332 ac_export_mrt_z(&ctx->ac, depth, stencil, samplemask, &args);
4333
4334 ac_build_export(&ctx->ac, &args);
4335 }
4336
4337 static void
4338 handle_fs_outputs_post(struct radv_shader_context *ctx)
4339 {
4340 unsigned index = 0;
4341 LLVMValueRef depth = NULL, stencil = NULL, samplemask = NULL;
4342 struct ac_export_args color_args[8];
4343
4344 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
4345 LLVMValueRef values[4];
4346
4347 if (!(ctx->output_mask & (1ull << i)))
4348 continue;
4349
4350 if (i < FRAG_RESULT_DATA0)
4351 continue;
4352
4353 for (unsigned j = 0; j < 4; j++)
4354 values[j] = ac_to_float(&ctx->ac,
4355 radv_load_output(ctx, i, j));
4356
4357 bool ret = si_export_mrt_color(ctx, values,
4358 i - FRAG_RESULT_DATA0,
4359 &color_args[index]);
4360 if (ret)
4361 index++;
4362 }
4363
4364 /* Process depth, stencil, samplemask. */
4365 if (ctx->shader_info->ps.writes_z) {
4366 depth = ac_to_float(&ctx->ac,
4367 radv_load_output(ctx, FRAG_RESULT_DEPTH, 0));
4368 }
4369 if (ctx->shader_info->ps.writes_stencil) {
4370 stencil = ac_to_float(&ctx->ac,
4371 radv_load_output(ctx, FRAG_RESULT_STENCIL, 0));
4372 }
4373 if (ctx->shader_info->ps.writes_sample_mask) {
4374 samplemask = ac_to_float(&ctx->ac,
4375 radv_load_output(ctx, FRAG_RESULT_SAMPLE_MASK, 0));
4376 }
4377
4378 /* Set the DONE bit on last non-null color export only if Z isn't
4379 * exported.
4380 */
4381 if (index > 0 &&
4382 !ctx->shader_info->ps.writes_z &&
4383 !ctx->shader_info->ps.writes_stencil &&
4384 !ctx->shader_info->ps.writes_sample_mask) {
4385 unsigned last = index - 1;
4386
4387 color_args[last].valid_mask = 1; /* whether the EXEC mask is valid */
4388 color_args[last].done = 1; /* DONE bit */
4389 }
4390
4391 /* Export PS outputs. */
4392 for (unsigned i = 0; i < index; i++)
4393 ac_build_export(&ctx->ac, &color_args[i]);
4394
4395 if (depth || stencil || samplemask)
4396 radv_export_mrt_z(ctx, depth, stencil, samplemask);
4397 else if (!index)
4398 ac_build_export_null(&ctx->ac);
4399 }
4400
4401 static void
4402 emit_gs_epilogue(struct radv_shader_context *ctx)
4403 {
4404 if (ctx->options->key.vs_common_out.as_ngg) {
4405 gfx10_ngg_gs_emit_epilogue_1(ctx);
4406 return;
4407 }
4408
4409 if (ctx->ac.chip_class >= GFX10)
4410 LLVMBuildFence(ctx->ac.builder, LLVMAtomicOrderingRelease, false, "");
4411
4412 ac_build_sendmsg(&ctx->ac, AC_SENDMSG_GS_OP_NOP | AC_SENDMSG_GS_DONE, ctx->gs_wave_id);
4413 }
4414
4415 static void
4416 handle_shader_outputs_post(struct ac_shader_abi *abi, unsigned max_outputs,
4417 LLVMValueRef *addrs)
4418 {
4419 struct radv_shader_context *ctx = radv_shader_context_from_abi(abi);
4420
4421 switch (ctx->stage) {
4422 case MESA_SHADER_VERTEX:
4423 if (ctx->options->key.vs_common_out.as_ls)
4424 handle_ls_outputs_post(ctx);
4425 else if (ctx->options->key.vs_common_out.as_es)
4426 handle_es_outputs_post(ctx, &ctx->shader_info->vs.es_info);
4427 else if (ctx->options->key.vs_common_out.as_ngg)
4428 handle_ngg_outputs_post_1(ctx);
4429 else
4430 handle_vs_outputs_post(ctx, ctx->options->key.vs_common_out.export_prim_id,
4431 ctx->options->key.vs_common_out.export_clip_dists,
4432 &ctx->shader_info->vs.outinfo);
4433 break;
4434 case MESA_SHADER_FRAGMENT:
4435 handle_fs_outputs_post(ctx);
4436 break;
4437 case MESA_SHADER_GEOMETRY:
4438 emit_gs_epilogue(ctx);
4439 break;
4440 case MESA_SHADER_TESS_CTRL:
4441 handle_tcs_outputs_post(ctx);
4442 break;
4443 case MESA_SHADER_TESS_EVAL:
4444 if (ctx->options->key.vs_common_out.as_es)
4445 handle_es_outputs_post(ctx, &ctx->shader_info->tes.es_info);
4446 else if (ctx->options->key.vs_common_out.as_ngg)
4447 handle_ngg_outputs_post_1(ctx);
4448 else
4449 handle_vs_outputs_post(ctx, ctx->options->key.vs_common_out.export_prim_id,
4450 ctx->options->key.vs_common_out.export_clip_dists,
4451 &ctx->shader_info->tes.outinfo);
4452 break;
4453 default:
4454 break;
4455 }
4456 }
4457
4458 static void ac_llvm_finalize_module(struct radv_shader_context *ctx,
4459 LLVMPassManagerRef passmgr,
4460 const struct radv_nir_compiler_options *options)
4461 {
4462 LLVMRunPassManager(passmgr, ctx->ac.module);
4463 LLVMDisposeBuilder(ctx->ac.builder);
4464
4465 ac_llvm_context_dispose(&ctx->ac);
4466 }
4467
4468 static void
4469 ac_nir_eliminate_const_vs_outputs(struct radv_shader_context *ctx)
4470 {
4471 struct radv_vs_output_info *outinfo;
4472
4473 switch (ctx->stage) {
4474 case MESA_SHADER_FRAGMENT:
4475 case MESA_SHADER_COMPUTE:
4476 case MESA_SHADER_TESS_CTRL:
4477 case MESA_SHADER_GEOMETRY:
4478 return;
4479 case MESA_SHADER_VERTEX:
4480 if (ctx->options->key.vs_common_out.as_ls ||
4481 ctx->options->key.vs_common_out.as_es)
4482 return;
4483 outinfo = &ctx->shader_info->vs.outinfo;
4484 break;
4485 case MESA_SHADER_TESS_EVAL:
4486 if (ctx->options->key.vs_common_out.as_es)
4487 return;
4488 outinfo = &ctx->shader_info->tes.outinfo;
4489 break;
4490 default:
4491 unreachable("Unhandled shader type");
4492 }
4493
4494 ac_optimize_vs_outputs(&ctx->ac,
4495 ctx->main_function,
4496 outinfo->vs_output_param_offset,
4497 VARYING_SLOT_MAX,
4498 &outinfo->param_exports);
4499 }
4500
4501 static void
4502 ac_setup_rings(struct radv_shader_context *ctx)
4503 {
4504 if (ctx->options->chip_class <= GFX8 &&
4505 (ctx->stage == MESA_SHADER_GEOMETRY ||
4506 ctx->options->key.vs_common_out.as_es || ctx->options->key.vs_common_out.as_es)) {
4507 unsigned ring = ctx->stage == MESA_SHADER_GEOMETRY ? RING_ESGS_GS
4508 : RING_ESGS_VS;
4509 LLVMValueRef offset = LLVMConstInt(ctx->ac.i32, ring, false);
4510
4511 ctx->esgs_ring = ac_build_load_to_sgpr(&ctx->ac,
4512 ctx->ring_offsets,
4513 offset);
4514 }
4515
4516 if (ctx->is_gs_copy_shader) {
4517 ctx->gsvs_ring[0] =
4518 ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets,
4519 LLVMConstInt(ctx->ac.i32,
4520 RING_GSVS_VS, false));
4521 }
4522
4523 if (ctx->stage == MESA_SHADER_GEOMETRY) {
4524 /* The conceptual layout of the GSVS ring is
4525 * v0c0 .. vLv0 v0c1 .. vLc1 ..
4526 * but the real memory layout is swizzled across
4527 * threads:
4528 * t0v0c0 .. t15v0c0 t0v1c0 .. t15v1c0 ... t15vLcL
4529 * t16v0c0 ..
4530 * Override the buffer descriptor accordingly.
4531 */
4532 LLVMTypeRef v2i64 = LLVMVectorType(ctx->ac.i64, 2);
4533 uint64_t stream_offset = 0;
4534 unsigned num_records = ctx->ac.wave_size;
4535 LLVMValueRef base_ring;
4536
4537 base_ring =
4538 ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets,
4539 LLVMConstInt(ctx->ac.i32,
4540 RING_GSVS_GS, false));
4541
4542 for (unsigned stream = 0; stream < 4; stream++) {
4543 unsigned num_components, stride;
4544 LLVMValueRef ring, tmp;
4545
4546 num_components =
4547 ctx->shader_info->gs.num_stream_output_components[stream];
4548
4549 if (!num_components)
4550 continue;
4551
4552 stride = 4 * num_components * ctx->shader->info.gs.vertices_out;
4553
4554 /* Limit on the stride field for <= GFX7. */
4555 assert(stride < (1 << 14));
4556
4557 ring = LLVMBuildBitCast(ctx->ac.builder,
4558 base_ring, v2i64, "");
4559 tmp = LLVMBuildExtractElement(ctx->ac.builder,
4560 ring, ctx->ac.i32_0, "");
4561 tmp = LLVMBuildAdd(ctx->ac.builder, tmp,
4562 LLVMConstInt(ctx->ac.i64,
4563 stream_offset, 0), "");
4564 ring = LLVMBuildInsertElement(ctx->ac.builder,
4565 ring, tmp, ctx->ac.i32_0, "");
4566
4567 stream_offset += stride * ctx->ac.wave_size;
4568
4569 ring = LLVMBuildBitCast(ctx->ac.builder, ring,
4570 ctx->ac.v4i32, "");
4571
4572 tmp = LLVMBuildExtractElement(ctx->ac.builder, ring,
4573 ctx->ac.i32_1, "");
4574 tmp = LLVMBuildOr(ctx->ac.builder, tmp,
4575 LLVMConstInt(ctx->ac.i32,
4576 S_008F04_STRIDE(stride), false), "");
4577 ring = LLVMBuildInsertElement(ctx->ac.builder, ring, tmp,
4578 ctx->ac.i32_1, "");
4579
4580 ring = LLVMBuildInsertElement(ctx->ac.builder, ring,
4581 LLVMConstInt(ctx->ac.i32,
4582 num_records, false),
4583 LLVMConstInt(ctx->ac.i32, 2, false), "");
4584
4585 ctx->gsvs_ring[stream] = ring;
4586 }
4587 }
4588
4589 if (ctx->stage == MESA_SHADER_TESS_CTRL ||
4590 ctx->stage == MESA_SHADER_TESS_EVAL) {
4591 ctx->hs_ring_tess_offchip = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_OFFCHIP, false));
4592 ctx->hs_ring_tess_factor = ac_build_load_to_sgpr(&ctx->ac, ctx->ring_offsets, LLVMConstInt(ctx->ac.i32, RING_HS_TESS_FACTOR, false));
4593 }
4594 }
4595
4596 unsigned
4597 radv_nir_get_max_workgroup_size(enum chip_class chip_class,
4598 gl_shader_stage stage,
4599 const struct nir_shader *nir)
4600 {
4601 const unsigned backup_sizes[] = {chip_class >= GFX9 ? 128 : 64, 1, 1};
4602 return radv_get_max_workgroup_size(chip_class, stage, nir ? nir->info.cs.local_size : backup_sizes);
4603 }
4604
4605 /* Fixup the HW not emitting the TCS regs if there are no HS threads. */
4606 static void ac_nir_fixup_ls_hs_input_vgprs(struct radv_shader_context *ctx)
4607 {
4608 LLVMValueRef count = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 8, 8);
4609 LLVMValueRef hs_empty = LLVMBuildICmp(ctx->ac.builder, LLVMIntEQ, count,
4610 ctx->ac.i32_0, "");
4611 ctx->abi.instance_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->rel_auto_id, ctx->abi.instance_id, "");
4612 ctx->rel_auto_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_rel_ids, ctx->rel_auto_id, "");
4613 ctx->abi.vertex_id = LLVMBuildSelect(ctx->ac.builder, hs_empty, ctx->abi.tcs_patch_id, ctx->abi.vertex_id, "");
4614 }
4615
4616 static void prepare_gs_input_vgprs(struct radv_shader_context *ctx)
4617 {
4618 for(int i = 5; i >= 0; --i) {
4619 ctx->gs_vtx_offset[i] = ac_unpack_param(&ctx->ac, ctx->gs_vtx_offset[i & ~1],
4620 (i & 1) * 16, 16);
4621 }
4622
4623 ctx->gs_wave_id = ac_unpack_param(&ctx->ac, ctx->merged_wave_info, 16, 8);
4624 }
4625
4626 /* Ensure that the esgs ring is declared.
4627 *
4628 * We declare it with 64KB alignment as a hint that the
4629 * pointer value will always be 0.
4630 */
4631 static void declare_esgs_ring(struct radv_shader_context *ctx)
4632 {
4633 if (ctx->esgs_ring)
4634 return;
4635
4636 assert(!LLVMGetNamedGlobal(ctx->ac.module, "esgs_ring"));
4637
4638 ctx->esgs_ring = LLVMAddGlobalInAddressSpace(
4639 ctx->ac.module, LLVMArrayType(ctx->ac.i32, 0),
4640 "esgs_ring",
4641 AC_ADDR_SPACE_LDS);
4642 LLVMSetLinkage(ctx->esgs_ring, LLVMExternalLinkage);
4643 LLVMSetAlignment(ctx->esgs_ring, 64 * 1024);
4644 }
4645
4646 static
4647 LLVMModuleRef ac_translate_nir_to_llvm(struct ac_llvm_compiler *ac_llvm,
4648 struct nir_shader *const *shaders,
4649 int shader_count,
4650 struct radv_shader_info *shader_info,
4651 const struct radv_nir_compiler_options *options)
4652 {
4653 struct radv_shader_context ctx = {0};
4654 unsigned i;
4655 ctx.options = options;
4656 ctx.shader_info = shader_info;
4657
4658 enum ac_float_mode float_mode =
4659 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
4660 AC_FLOAT_MODE_DEFAULT;
4661
4662 ac_llvm_context_init(&ctx.ac, ac_llvm, options->chip_class,
4663 options->family, float_mode, options->wave_size, 64);
4664 ctx.context = ctx.ac.context;
4665
4666 for (i = 0; i < MAX_SETS; i++)
4667 shader_info->user_sgprs_locs.descriptor_sets[i].sgpr_idx = -1;
4668 for (i = 0; i < AC_UD_MAX_UD; i++)
4669 shader_info->user_sgprs_locs.shader_data[i].sgpr_idx = -1;
4670
4671 ctx.max_workgroup_size = 0;
4672 for (int i = 0; i < shader_count; ++i) {
4673 ctx.max_workgroup_size = MAX2(ctx.max_workgroup_size,
4674 radv_nir_get_max_workgroup_size(ctx.options->chip_class,
4675 shaders[i]->info.stage,
4676 shaders[i]));
4677 }
4678
4679 if (ctx.ac.chip_class >= GFX10) {
4680 if (is_pre_gs_stage(shaders[0]->info.stage) &&
4681 options->key.vs_common_out.as_ngg) {
4682 ctx.max_workgroup_size = 128;
4683 }
4684 }
4685
4686 create_function(&ctx, shaders[shader_count - 1]->info.stage, shader_count >= 2,
4687 shader_count >= 2 ? shaders[shader_count - 2]->info.stage : MESA_SHADER_VERTEX);
4688
4689 ctx.abi.inputs = &ctx.inputs[0];
4690 ctx.abi.emit_outputs = handle_shader_outputs_post;
4691 ctx.abi.emit_vertex = visit_emit_vertex;
4692 ctx.abi.load_ubo = radv_load_ubo;
4693 ctx.abi.load_ssbo = radv_load_ssbo;
4694 ctx.abi.load_sampler_desc = radv_get_sampler_desc;
4695 ctx.abi.load_resource = radv_load_resource;
4696 ctx.abi.clamp_shadow_reference = false;
4697 ctx.abi.robust_buffer_access = options->robust_buffer_access;
4698
4699 bool is_ngg = is_pre_gs_stage(shaders[0]->info.stage) && ctx.options->key.vs_common_out.as_ngg;
4700 if (shader_count >= 2 || is_ngg)
4701 ac_init_exec_full_mask(&ctx.ac);
4702
4703 if (options->has_ls_vgpr_init_bug &&
4704 shaders[shader_count - 1]->info.stage == MESA_SHADER_TESS_CTRL)
4705 ac_nir_fixup_ls_hs_input_vgprs(&ctx);
4706
4707 if (shaders[shader_count - 1]->info.stage != MESA_SHADER_GEOMETRY &&
4708 (ctx.options->key.vs_common_out.as_ngg &&
4709 !ctx.options->key.vs_common_out.as_es)) {
4710 /* Unconditionally declare scratch space base for streamout and
4711 * vertex compaction. Whether space is actually allocated is
4712 * determined during linking / PM4 creation.
4713 *
4714 * Add an extra dword per vertex to ensure an odd stride, which
4715 * avoids bank conflicts for SoA accesses.
4716 */
4717 declare_esgs_ring(&ctx);
4718
4719 /* This is really only needed when streamout and / or vertex
4720 * compaction is enabled.
4721 */
4722 LLVMTypeRef asi32 = LLVMArrayType(ctx.ac.i32, 8);
4723 ctx.gs_ngg_scratch = LLVMAddGlobalInAddressSpace(ctx.ac.module,
4724 asi32, "ngg_scratch", AC_ADDR_SPACE_LDS);
4725 LLVMSetInitializer(ctx.gs_ngg_scratch, LLVMGetUndef(asi32));
4726 LLVMSetAlignment(ctx.gs_ngg_scratch, 4);
4727 }
4728
4729 for(int i = 0; i < shader_count; ++i) {
4730 ctx.stage = shaders[i]->info.stage;
4731 ctx.shader = shaders[i];
4732 ctx.output_mask = 0;
4733
4734 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY) {
4735 for (int i = 0; i < 4; i++) {
4736 ctx.gs_next_vertex[i] =
4737 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
4738 }
4739 if (ctx.options->key.vs_common_out.as_ngg) {
4740 for (unsigned i = 0; i < 4; ++i) {
4741 ctx.gs_curprim_verts[i] =
4742 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
4743 ctx.gs_generated_prims[i] =
4744 ac_build_alloca(&ctx.ac, ctx.ac.i32, "");
4745 }
4746
4747 unsigned scratch_size = 8;
4748 if (ctx.shader_info->so.num_outputs)
4749 scratch_size = 44;
4750
4751 LLVMTypeRef ai32 = LLVMArrayType(ctx.ac.i32, scratch_size);
4752 ctx.gs_ngg_scratch =
4753 LLVMAddGlobalInAddressSpace(ctx.ac.module,
4754 ai32, "ngg_scratch", AC_ADDR_SPACE_LDS);
4755 LLVMSetInitializer(ctx.gs_ngg_scratch, LLVMGetUndef(ai32));
4756 LLVMSetAlignment(ctx.gs_ngg_scratch, 4);
4757
4758 ctx.gs_ngg_emit = LLVMAddGlobalInAddressSpace(ctx.ac.module,
4759 LLVMArrayType(ctx.ac.i32, 0), "ngg_emit", AC_ADDR_SPACE_LDS);
4760 LLVMSetLinkage(ctx.gs_ngg_emit, LLVMExternalLinkage);
4761 LLVMSetAlignment(ctx.gs_ngg_emit, 4);
4762 }
4763
4764 ctx.abi.load_inputs = load_gs_input;
4765 ctx.abi.emit_primitive = visit_end_primitive;
4766 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
4767 ctx.abi.load_tess_varyings = load_tcs_varyings;
4768 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
4769 ctx.abi.store_tcs_outputs = store_tcs_output;
4770 if (shader_count == 1)
4771 ctx.tcs_num_inputs = ctx.options->key.tcs.num_inputs;
4772 else
4773 ctx.tcs_num_inputs = util_last_bit64(shader_info->vs.ls_outputs_written);
4774 ctx.tcs_num_patches = get_tcs_num_patches(&ctx);
4775 } else if (shaders[i]->info.stage == MESA_SHADER_TESS_EVAL) {
4776 ctx.abi.load_tess_varyings = load_tes_input;
4777 ctx.abi.load_tess_coord = load_tess_coord;
4778 ctx.abi.load_patch_vertices_in = load_patch_vertices_in;
4779 ctx.tcs_num_patches = ctx.options->key.tes.num_patches;
4780 } else if (shaders[i]->info.stage == MESA_SHADER_VERTEX) {
4781 ctx.abi.load_base_vertex = radv_load_base_vertex;
4782 } else if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT) {
4783 ctx.abi.load_sample_position = load_sample_position;
4784 ctx.abi.load_sample_mask_in = load_sample_mask_in;
4785 ctx.abi.emit_kill = radv_emit_kill;
4786 }
4787
4788 if (shaders[i]->info.stage == MESA_SHADER_VERTEX &&
4789 ctx.options->key.vs_common_out.as_ngg &&
4790 ctx.options->key.vs_common_out.export_prim_id) {
4791 declare_esgs_ring(&ctx);
4792 }
4793
4794 bool nested_barrier = false;
4795
4796 if (i) {
4797 if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
4798 ctx.options->key.vs_common_out.as_ngg) {
4799 gfx10_ngg_gs_emit_prologue(&ctx);
4800 nested_barrier = false;
4801 } else {
4802 nested_barrier = true;
4803 }
4804 }
4805
4806 if (nested_barrier) {
4807 /* Execute a barrier before the second shader in
4808 * a merged shader.
4809 *
4810 * Execute the barrier inside the conditional block,
4811 * so that empty waves can jump directly to s_endpgm,
4812 * which will also signal the barrier.
4813 *
4814 * This is possible in gfx9, because an empty wave
4815 * for the second shader does not participate in
4816 * the epilogue. With NGG, empty waves may still
4817 * be required to export data (e.g. GS output vertices),
4818 * so we cannot let them exit early.
4819 *
4820 * If the shader is TCS and the TCS epilog is present
4821 * and contains a barrier, it will wait there and then
4822 * reach s_endpgm.
4823 */
4824 ac_emit_barrier(&ctx.ac, ctx.stage);
4825 }
4826
4827 nir_foreach_variable(variable, &shaders[i]->outputs)
4828 scan_shader_output_decl(&ctx, variable, shaders[i], shaders[i]->info.stage);
4829
4830 ac_setup_rings(&ctx);
4831
4832 LLVMBasicBlockRef merge_block;
4833 if (shader_count >= 2 || is_ngg) {
4834 LLVMValueRef fn = LLVMGetBasicBlockParent(LLVMGetInsertBlock(ctx.ac.builder));
4835 LLVMBasicBlockRef then_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
4836 merge_block = LLVMAppendBasicBlockInContext(ctx.ac.context, fn, "");
4837
4838 LLVMValueRef count = ac_unpack_param(&ctx.ac, ctx.merged_wave_info, 8 * i, 8);
4839 LLVMValueRef thread_id = ac_get_thread_id(&ctx.ac);
4840 LLVMValueRef cond = LLVMBuildICmp(ctx.ac.builder, LLVMIntULT,
4841 thread_id, count, "");
4842 LLVMBuildCondBr(ctx.ac.builder, cond, then_block, merge_block);
4843
4844 LLVMPositionBuilderAtEnd(ctx.ac.builder, then_block);
4845 }
4846
4847 if (shaders[i]->info.stage == MESA_SHADER_FRAGMENT)
4848 prepare_interp_optimize(&ctx, shaders[i]);
4849 else if(shaders[i]->info.stage == MESA_SHADER_VERTEX)
4850 handle_vs_inputs(&ctx, shaders[i]);
4851 else if(shader_count >= 2 && shaders[i]->info.stage == MESA_SHADER_GEOMETRY)
4852 prepare_gs_input_vgprs(&ctx);
4853
4854 ac_nir_translate(&ctx.ac, &ctx.abi, shaders[i]);
4855
4856 if (shader_count >= 2 || is_ngg) {
4857 LLVMBuildBr(ctx.ac.builder, merge_block);
4858 LLVMPositionBuilderAtEnd(ctx.ac.builder, merge_block);
4859 }
4860
4861 /* This needs to be outside the if wrapping the shader body, as sometimes
4862 * the HW generates waves with 0 es/vs threads. */
4863 if (is_pre_gs_stage(shaders[i]->info.stage) &&
4864 ctx.options->key.vs_common_out.as_ngg &&
4865 i == shader_count - 1) {
4866 handle_ngg_outputs_post_2(&ctx);
4867 } else if (shaders[i]->info.stage == MESA_SHADER_GEOMETRY &&
4868 ctx.options->key.vs_common_out.as_ngg) {
4869 gfx10_ngg_gs_emit_epilogue_2(&ctx);
4870 }
4871
4872 if (shaders[i]->info.stage == MESA_SHADER_TESS_CTRL) {
4873 shader_info->tcs.num_patches = ctx.tcs_num_patches;
4874 shader_info->tcs.lds_size = calculate_tess_lds_size(&ctx);
4875 }
4876 }
4877
4878 LLVMBuildRetVoid(ctx.ac.builder);
4879
4880 if (options->dump_preoptir) {
4881 fprintf(stderr, "%s LLVM IR:\n\n",
4882 radv_get_shader_name(shader_info,
4883 shaders[shader_count - 1]->info.stage));
4884 ac_dump_module(ctx.ac.module);
4885 fprintf(stderr, "\n");
4886 }
4887
4888 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, options);
4889
4890 if (shader_count == 1)
4891 ac_nir_eliminate_const_vs_outputs(&ctx);
4892
4893 if (options->dump_shader) {
4894 ctx.shader_info->private_mem_vgprs =
4895 ac_count_scratch_private_memory(ctx.main_function);
4896 }
4897
4898 return ctx.ac.module;
4899 }
4900
4901 static void ac_diagnostic_handler(LLVMDiagnosticInfoRef di, void *context)
4902 {
4903 unsigned *retval = (unsigned *)context;
4904 LLVMDiagnosticSeverity severity = LLVMGetDiagInfoSeverity(di);
4905 char *description = LLVMGetDiagInfoDescription(di);
4906
4907 if (severity == LLVMDSError) {
4908 *retval = 1;
4909 fprintf(stderr, "LLVM triggered Diagnostic Handler: %s\n",
4910 description);
4911 }
4912
4913 LLVMDisposeMessage(description);
4914 }
4915
4916 static unsigned radv_llvm_compile(LLVMModuleRef M,
4917 char **pelf_buffer, size_t *pelf_size,
4918 struct ac_llvm_compiler *ac_llvm)
4919 {
4920 unsigned retval = 0;
4921 LLVMContextRef llvm_ctx;
4922
4923 /* Setup Diagnostic Handler*/
4924 llvm_ctx = LLVMGetModuleContext(M);
4925
4926 LLVMContextSetDiagnosticHandler(llvm_ctx, ac_diagnostic_handler,
4927 &retval);
4928
4929 /* Compile IR*/
4930 if (!radv_compile_to_elf(ac_llvm, M, pelf_buffer, pelf_size))
4931 retval = 1;
4932 return retval;
4933 }
4934
4935 static void ac_compile_llvm_module(struct ac_llvm_compiler *ac_llvm,
4936 LLVMModuleRef llvm_module,
4937 struct radv_shader_binary **rbinary,
4938 gl_shader_stage stage,
4939 const char *name,
4940 const struct radv_nir_compiler_options *options)
4941 {
4942 char *elf_buffer = NULL;
4943 size_t elf_size = 0;
4944 char *llvm_ir_string = NULL;
4945
4946 if (options->dump_shader) {
4947 fprintf(stderr, "%s LLVM IR:\n\n", name);
4948 ac_dump_module(llvm_module);
4949 fprintf(stderr, "\n");
4950 }
4951
4952 if (options->record_llvm_ir) {
4953 char *llvm_ir = LLVMPrintModuleToString(llvm_module);
4954 llvm_ir_string = strdup(llvm_ir);
4955 LLVMDisposeMessage(llvm_ir);
4956 }
4957
4958 int v = radv_llvm_compile(llvm_module, &elf_buffer, &elf_size, ac_llvm);
4959 if (v) {
4960 fprintf(stderr, "compile failed\n");
4961 }
4962
4963 LLVMContextRef ctx = LLVMGetModuleContext(llvm_module);
4964 LLVMDisposeModule(llvm_module);
4965 LLVMContextDispose(ctx);
4966
4967 size_t llvm_ir_size = llvm_ir_string ? strlen(llvm_ir_string) : 0;
4968 size_t alloc_size = sizeof(struct radv_shader_binary_rtld) + elf_size + llvm_ir_size + 1;
4969 struct radv_shader_binary_rtld *rbin = calloc(1, alloc_size);
4970 memcpy(rbin->data, elf_buffer, elf_size);
4971 if (llvm_ir_string)
4972 memcpy(rbin->data + elf_size, llvm_ir_string, llvm_ir_size + 1);
4973
4974 rbin->base.type = RADV_BINARY_TYPE_RTLD;
4975 rbin->base.stage = stage;
4976 rbin->base.total_size = alloc_size;
4977 rbin->elf_size = elf_size;
4978 rbin->llvm_ir_size = llvm_ir_size;
4979 *rbinary = &rbin->base;
4980
4981 free(llvm_ir_string);
4982 free(elf_buffer);
4983 }
4984
4985 void
4986 radv_compile_nir_shader(struct ac_llvm_compiler *ac_llvm,
4987 struct radv_shader_binary **rbinary,
4988 struct radv_shader_info *shader_info,
4989 struct nir_shader *const *nir,
4990 int nir_count,
4991 const struct radv_nir_compiler_options *options)
4992 {
4993
4994 LLVMModuleRef llvm_module;
4995
4996 llvm_module = ac_translate_nir_to_llvm(ac_llvm, nir, nir_count, shader_info,
4997 options);
4998
4999 ac_compile_llvm_module(ac_llvm, llvm_module, rbinary,
5000 nir[nir_count - 1]->info.stage,
5001 radv_get_shader_name(shader_info,
5002 nir[nir_count - 1]->info.stage),
5003 options);
5004
5005 /* Determine the ES type (VS or TES) for the GS on GFX9. */
5006 if (options->chip_class >= GFX9) {
5007 if (nir_count == 2 &&
5008 nir[1]->info.stage == MESA_SHADER_GEOMETRY) {
5009 shader_info->gs.es_type = nir[0]->info.stage;
5010 }
5011 }
5012 shader_info->wave_size = options->wave_size;
5013 }
5014
5015 static void
5016 ac_gs_copy_shader_emit(struct radv_shader_context *ctx)
5017 {
5018 LLVMValueRef vtx_offset =
5019 LLVMBuildMul(ctx->ac.builder, ctx->abi.vertex_id,
5020 LLVMConstInt(ctx->ac.i32, 4, false), "");
5021 LLVMValueRef stream_id;
5022
5023 /* Fetch the vertex stream ID. */
5024 if (!ctx->options->use_ngg_streamout &&
5025 ctx->shader_info->so.num_outputs) {
5026 stream_id =
5027 ac_unpack_param(&ctx->ac, ctx->streamout_config, 24, 2);
5028 } else {
5029 stream_id = ctx->ac.i32_0;
5030 }
5031
5032 LLVMBasicBlockRef end_bb;
5033 LLVMValueRef switch_inst;
5034
5035 end_bb = LLVMAppendBasicBlockInContext(ctx->ac.context,
5036 ctx->main_function, "end");
5037 switch_inst = LLVMBuildSwitch(ctx->ac.builder, stream_id, end_bb, 4);
5038
5039 for (unsigned stream = 0; stream < 4; stream++) {
5040 unsigned num_components =
5041 ctx->shader_info->gs.num_stream_output_components[stream];
5042 LLVMBasicBlockRef bb;
5043 unsigned offset;
5044
5045 if (stream > 0 && !num_components)
5046 continue;
5047
5048 if (stream > 0 && !ctx->shader_info->so.num_outputs)
5049 continue;
5050
5051 bb = LLVMInsertBasicBlockInContext(ctx->ac.context, end_bb, "out");
5052 LLVMAddCase(switch_inst, LLVMConstInt(ctx->ac.i32, stream, 0), bb);
5053 LLVMPositionBuilderAtEnd(ctx->ac.builder, bb);
5054
5055 offset = 0;
5056 for (unsigned i = 0; i < AC_LLVM_MAX_OUTPUTS; ++i) {
5057 unsigned output_usage_mask =
5058 ctx->shader_info->gs.output_usage_mask[i];
5059 unsigned output_stream =
5060 ctx->shader_info->gs.output_streams[i];
5061 int length = util_last_bit(output_usage_mask);
5062
5063 if (!(ctx->output_mask & (1ull << i)) ||
5064 output_stream != stream)
5065 continue;
5066
5067 for (unsigned j = 0; j < length; j++) {
5068 LLVMValueRef value, soffset;
5069
5070 if (!(output_usage_mask & (1 << j)))
5071 continue;
5072
5073 soffset = LLVMConstInt(ctx->ac.i32,
5074 offset *
5075 ctx->shader->info.gs.vertices_out * 16 * 4, false);
5076
5077 offset++;
5078
5079 value = ac_build_buffer_load(&ctx->ac,
5080 ctx->gsvs_ring[0],
5081 1, ctx->ac.i32_0,
5082 vtx_offset, soffset,
5083 0, ac_glc | ac_slc, true, false);
5084
5085 LLVMTypeRef type = LLVMGetAllocatedType(ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
5086 if (ac_get_type_size(type) == 2) {
5087 value = LLVMBuildBitCast(ctx->ac.builder, value, ctx->ac.i32, "");
5088 value = LLVMBuildTrunc(ctx->ac.builder, value, ctx->ac.i16, "");
5089 }
5090
5091 LLVMBuildStore(ctx->ac.builder,
5092 ac_to_float(&ctx->ac, value), ctx->abi.outputs[ac_llvm_reg_index_soa(i, j)]);
5093 }
5094 }
5095
5096 if (!ctx->options->use_ngg_streamout &&
5097 ctx->shader_info->so.num_outputs)
5098 radv_emit_streamout(ctx, stream);
5099
5100 if (stream == 0) {
5101 handle_vs_outputs_post(ctx, false, true,
5102 &ctx->shader_info->vs.outinfo);
5103 }
5104
5105 LLVMBuildBr(ctx->ac.builder, end_bb);
5106 }
5107
5108 LLVMPositionBuilderAtEnd(ctx->ac.builder, end_bb);
5109 }
5110
5111 void
5112 radv_compile_gs_copy_shader(struct ac_llvm_compiler *ac_llvm,
5113 struct nir_shader *geom_shader,
5114 struct radv_shader_binary **rbinary,
5115 struct radv_shader_info *shader_info,
5116 const struct radv_nir_compiler_options *options)
5117 {
5118 struct radv_shader_context ctx = {0};
5119 ctx.options = options;
5120 ctx.shader_info = shader_info;
5121
5122 enum ac_float_mode float_mode =
5123 options->unsafe_math ? AC_FLOAT_MODE_UNSAFE_FP_MATH :
5124 AC_FLOAT_MODE_DEFAULT;
5125
5126 ac_llvm_context_init(&ctx.ac, ac_llvm, options->chip_class,
5127 options->family, float_mode, 64, 64);
5128 ctx.context = ctx.ac.context;
5129
5130 ctx.is_gs_copy_shader = true;
5131 ctx.stage = MESA_SHADER_VERTEX;
5132 ctx.shader = geom_shader;
5133
5134 create_function(&ctx, MESA_SHADER_VERTEX, false, MESA_SHADER_VERTEX);
5135
5136 ac_setup_rings(&ctx);
5137
5138 nir_foreach_variable(variable, &geom_shader->outputs) {
5139 scan_shader_output_decl(&ctx, variable, geom_shader, MESA_SHADER_VERTEX);
5140 ac_handle_shader_output_decl(&ctx.ac, &ctx.abi, geom_shader,
5141 variable, MESA_SHADER_VERTEX);
5142 }
5143
5144 ac_gs_copy_shader_emit(&ctx);
5145
5146 LLVMBuildRetVoid(ctx.ac.builder);
5147
5148 ac_llvm_finalize_module(&ctx, ac_llvm->passmgr, options);
5149
5150 ac_compile_llvm_module(ac_llvm, ctx.ac.module, rbinary,
5151 MESA_SHADER_VERTEX, "GS Copy Shader", options);
5152 (*rbinary)->is_gs_copy_shader = true;
5153
5154 }