Revert "radv: add support for MRTs compaction to avoid holes"
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
33 #include "radv_cs.h"
34 #include "radv_shader.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
39 #include "vk_util.h"
40
41 #include "sid.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
48 #include "ac_shader_util.h"
49
50 struct radv_blend_state {
51 uint32_t blend_enable_4bit;
52 uint32_t need_src_alpha;
53
54 uint32_t cb_color_control;
55 uint32_t cb_target_mask;
56 uint32_t cb_target_enabled_4bit;
57 uint32_t sx_mrt_blend_opt[8];
58 uint32_t cb_blend_control[8];
59
60 uint32_t spi_shader_col_format;
61 uint32_t col_format_is_int8;
62 uint32_t col_format_is_int10;
63 uint32_t cb_shader_mask;
64 uint32_t db_alpha_to_mask;
65
66 uint32_t commutative_4bit;
67
68 bool single_cb_enable;
69 bool mrt0_is_dual_src;
70 };
71
72 struct radv_dsa_order_invariance {
73 /* Whether the final result in Z/S buffers is guaranteed to be
74 * invariant under changes to the order in which fragments arrive.
75 */
76 bool zs;
77
78 /* Whether the set of fragments that pass the combined Z/S test is
79 * guaranteed to be invariant under changes to the order in which
80 * fragments arrive.
81 */
82 bool pass_set;
83 };
84
85 struct radv_tessellation_state {
86 uint32_t ls_hs_config;
87 unsigned num_patches;
88 unsigned lds_size;
89 uint32_t tf_param;
90 };
91
92 static const VkPipelineMultisampleStateCreateInfo *
93 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
94 {
95 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
96 return pCreateInfo->pMultisampleState;
97 return NULL;
98 }
99
100 static const VkPipelineTessellationStateCreateInfo *
101 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
102 {
103 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
104 if (pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT ||
105 pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) {
106 return pCreateInfo->pTessellationState;
107 }
108 }
109 return NULL;
110 }
111
112 static const VkPipelineDepthStencilStateCreateInfo *
113 radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
114 {
115 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
116 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
117
118 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
119 subpass->depth_stencil_attachment)
120 return pCreateInfo->pDepthStencilState;
121 return NULL;
122 }
123
124 static const VkPipelineColorBlendStateCreateInfo *
125 radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
126 {
127 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
128 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
129
130 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
131 subpass->has_color_att)
132 return pCreateInfo->pColorBlendState;
133 return NULL;
134 }
135
136 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline)
137 {
138 struct radv_shader_variant *variant = NULL;
139 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
140 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
141 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
142 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
143 else if (pipeline->shaders[MESA_SHADER_VERTEX])
144 variant = pipeline->shaders[MESA_SHADER_VERTEX];
145 else
146 return false;
147 return variant->info.is_ngg;
148 }
149
150 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline *pipeline)
151 {
152 assert(radv_pipeline_has_ngg(pipeline));
153
154 struct radv_shader_variant *variant = NULL;
155 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
156 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
157 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
158 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
159 else if (pipeline->shaders[MESA_SHADER_VERTEX])
160 variant = pipeline->shaders[MESA_SHADER_VERTEX];
161 else
162 return false;
163 return variant->info.is_ngg_passthrough;
164 }
165
166 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline)
167 {
168 if (!radv_pipeline_has_gs(pipeline))
169 return false;
170
171 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
172 * On GFX10, it might be required in rare cases if it's not possible to
173 * enable NGG.
174 */
175 if (radv_pipeline_has_ngg(pipeline))
176 return false;
177
178 assert(pipeline->gs_copy_shader);
179 return true;
180 }
181
182 static void
183 radv_pipeline_destroy(struct radv_device *device,
184 struct radv_pipeline *pipeline,
185 const VkAllocationCallbacks* allocator)
186 {
187 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
188 if (pipeline->shaders[i])
189 radv_shader_variant_destroy(device, pipeline->shaders[i]);
190
191 if (pipeline->gs_copy_shader)
192 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
193
194 if(pipeline->cs.buf)
195 free(pipeline->cs.buf);
196
197 vk_object_base_finish(&pipeline->base);
198 vk_free2(&device->vk.alloc, allocator, pipeline);
199 }
200
201 void radv_DestroyPipeline(
202 VkDevice _device,
203 VkPipeline _pipeline,
204 const VkAllocationCallbacks* pAllocator)
205 {
206 RADV_FROM_HANDLE(radv_device, device, _device);
207 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
208
209 if (!_pipeline)
210 return;
211
212 radv_pipeline_destroy(device, pipeline, pAllocator);
213 }
214
215 static uint32_t get_hash_flags(struct radv_device *device)
216 {
217 uint32_t hash_flags = 0;
218
219 if (device->instance->debug_flags & RADV_DEBUG_NO_NGG)
220 hash_flags |= RADV_HASH_SHADER_NO_NGG;
221 if (device->physical_device->cs_wave_size == 32)
222 hash_flags |= RADV_HASH_SHADER_CS_WAVE32;
223 if (device->physical_device->ps_wave_size == 32)
224 hash_flags |= RADV_HASH_SHADER_PS_WAVE32;
225 if (device->physical_device->ge_wave_size == 32)
226 hash_flags |= RADV_HASH_SHADER_GE_WAVE32;
227 if (device->physical_device->use_llvm)
228 hash_flags |= RADV_HASH_SHADER_LLVM;
229 return hash_flags;
230 }
231
232 static VkResult
233 radv_pipeline_scratch_init(struct radv_device *device,
234 struct radv_pipeline *pipeline)
235 {
236 unsigned scratch_bytes_per_wave = 0;
237 unsigned max_waves = 0;
238 unsigned min_waves = 1;
239
240 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
241 if (pipeline->shaders[i] &&
242 pipeline->shaders[i]->config.scratch_bytes_per_wave) {
243 unsigned max_stage_waves = device->scratch_waves;
244
245 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
246 pipeline->shaders[i]->config.scratch_bytes_per_wave);
247
248 max_stage_waves = MIN2(max_stage_waves,
249 4 * device->physical_device->rad_info.num_good_compute_units *
250 (256 / pipeline->shaders[i]->config.num_vgprs));
251 max_waves = MAX2(max_waves, max_stage_waves);
252 }
253 }
254
255 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
256 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
257 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
258 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
259 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
260 }
261
262 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
263 pipeline->max_waves = max_waves;
264 return VK_SUCCESS;
265 }
266
267 static uint32_t si_translate_blend_logic_op(VkLogicOp op)
268 {
269 switch (op) {
270 case VK_LOGIC_OP_CLEAR:
271 return V_028808_ROP3_CLEAR;
272 case VK_LOGIC_OP_AND:
273 return V_028808_ROP3_AND;
274 case VK_LOGIC_OP_AND_REVERSE:
275 return V_028808_ROP3_AND_REVERSE;
276 case VK_LOGIC_OP_COPY:
277 return V_028808_ROP3_COPY;
278 case VK_LOGIC_OP_AND_INVERTED:
279 return V_028808_ROP3_AND_INVERTED;
280 case VK_LOGIC_OP_NO_OP:
281 return V_028808_ROP3_NO_OP;
282 case VK_LOGIC_OP_XOR:
283 return V_028808_ROP3_XOR;
284 case VK_LOGIC_OP_OR:
285 return V_028808_ROP3_OR;
286 case VK_LOGIC_OP_NOR:
287 return V_028808_ROP3_NOR;
288 case VK_LOGIC_OP_EQUIVALENT:
289 return V_028808_ROP3_EQUIVALENT;
290 case VK_LOGIC_OP_INVERT:
291 return V_028808_ROP3_INVERT;
292 case VK_LOGIC_OP_OR_REVERSE:
293 return V_028808_ROP3_OR_REVERSE;
294 case VK_LOGIC_OP_COPY_INVERTED:
295 return V_028808_ROP3_COPY_INVERTED;
296 case VK_LOGIC_OP_OR_INVERTED:
297 return V_028808_ROP3_OR_INVERTED;
298 case VK_LOGIC_OP_NAND:
299 return V_028808_ROP3_NAND;
300 case VK_LOGIC_OP_SET:
301 return V_028808_ROP3_SET;
302 default:
303 unreachable("Unhandled logic op");
304 }
305 }
306
307
308 static uint32_t si_translate_blend_function(VkBlendOp op)
309 {
310 switch (op) {
311 case VK_BLEND_OP_ADD:
312 return V_028780_COMB_DST_PLUS_SRC;
313 case VK_BLEND_OP_SUBTRACT:
314 return V_028780_COMB_SRC_MINUS_DST;
315 case VK_BLEND_OP_REVERSE_SUBTRACT:
316 return V_028780_COMB_DST_MINUS_SRC;
317 case VK_BLEND_OP_MIN:
318 return V_028780_COMB_MIN_DST_SRC;
319 case VK_BLEND_OP_MAX:
320 return V_028780_COMB_MAX_DST_SRC;
321 default:
322 return 0;
323 }
324 }
325
326 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
327 {
328 switch (factor) {
329 case VK_BLEND_FACTOR_ZERO:
330 return V_028780_BLEND_ZERO;
331 case VK_BLEND_FACTOR_ONE:
332 return V_028780_BLEND_ONE;
333 case VK_BLEND_FACTOR_SRC_COLOR:
334 return V_028780_BLEND_SRC_COLOR;
335 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
336 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
337 case VK_BLEND_FACTOR_DST_COLOR:
338 return V_028780_BLEND_DST_COLOR;
339 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
340 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
341 case VK_BLEND_FACTOR_SRC_ALPHA:
342 return V_028780_BLEND_SRC_ALPHA;
343 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
344 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
345 case VK_BLEND_FACTOR_DST_ALPHA:
346 return V_028780_BLEND_DST_ALPHA;
347 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
348 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
349 case VK_BLEND_FACTOR_CONSTANT_COLOR:
350 return V_028780_BLEND_CONSTANT_COLOR;
351 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
352 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
353 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
354 return V_028780_BLEND_CONSTANT_ALPHA;
355 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
356 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
357 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
358 return V_028780_BLEND_SRC_ALPHA_SATURATE;
359 case VK_BLEND_FACTOR_SRC1_COLOR:
360 return V_028780_BLEND_SRC1_COLOR;
361 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
362 return V_028780_BLEND_INV_SRC1_COLOR;
363 case VK_BLEND_FACTOR_SRC1_ALPHA:
364 return V_028780_BLEND_SRC1_ALPHA;
365 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
366 return V_028780_BLEND_INV_SRC1_ALPHA;
367 default:
368 return 0;
369 }
370 }
371
372 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
373 {
374 switch (op) {
375 case VK_BLEND_OP_ADD:
376 return V_028760_OPT_COMB_ADD;
377 case VK_BLEND_OP_SUBTRACT:
378 return V_028760_OPT_COMB_SUBTRACT;
379 case VK_BLEND_OP_REVERSE_SUBTRACT:
380 return V_028760_OPT_COMB_REVSUBTRACT;
381 case VK_BLEND_OP_MIN:
382 return V_028760_OPT_COMB_MIN;
383 case VK_BLEND_OP_MAX:
384 return V_028760_OPT_COMB_MAX;
385 default:
386 return V_028760_OPT_COMB_BLEND_DISABLED;
387 }
388 }
389
390 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
391 {
392 switch (factor) {
393 case VK_BLEND_FACTOR_ZERO:
394 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
395 case VK_BLEND_FACTOR_ONE:
396 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
397 case VK_BLEND_FACTOR_SRC_COLOR:
398 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
399 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
400 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
401 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
402 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
403 case VK_BLEND_FACTOR_SRC_ALPHA:
404 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
405 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
406 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
407 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
408 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
409 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
410 default:
411 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
412 }
413 }
414
415 /**
416 * Get rid of DST in the blend factors by commuting the operands:
417 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
418 */
419 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
420 unsigned *dst_factor, unsigned expected_dst,
421 unsigned replacement_src)
422 {
423 if (*src_factor == expected_dst &&
424 *dst_factor == VK_BLEND_FACTOR_ZERO) {
425 *src_factor = VK_BLEND_FACTOR_ZERO;
426 *dst_factor = replacement_src;
427
428 /* Commuting the operands requires reversing subtractions. */
429 if (*func == VK_BLEND_OP_SUBTRACT)
430 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
431 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
432 *func = VK_BLEND_OP_SUBTRACT;
433 }
434 }
435
436 static bool si_blend_factor_uses_dst(unsigned factor)
437 {
438 return factor == VK_BLEND_FACTOR_DST_COLOR ||
439 factor == VK_BLEND_FACTOR_DST_ALPHA ||
440 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
441 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
442 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
443 }
444
445 static bool is_dual_src(VkBlendFactor factor)
446 {
447 switch (factor) {
448 case VK_BLEND_FACTOR_SRC1_COLOR:
449 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
450 case VK_BLEND_FACTOR_SRC1_ALPHA:
451 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
452 return true;
453 default:
454 return false;
455 }
456 }
457
458 static unsigned radv_choose_spi_color_format(VkFormat vk_format,
459 bool blend_enable,
460 bool blend_need_alpha)
461 {
462 const struct vk_format_description *desc = vk_format_description(vk_format);
463 struct ac_spi_color_formats formats = {};
464 unsigned format, ntype, swap;
465
466 format = radv_translate_colorformat(vk_format);
467 ntype = radv_translate_color_numformat(vk_format, desc,
468 vk_format_get_first_non_void_channel(vk_format));
469 swap = radv_translate_colorswap(vk_format, false);
470
471 ac_choose_spi_color_formats(format, swap, ntype, false, &formats);
472
473 if (blend_enable && blend_need_alpha)
474 return formats.blend_alpha;
475 else if(blend_need_alpha)
476 return formats.alpha;
477 else if(blend_enable)
478 return formats.blend;
479 else
480 return formats.normal;
481 }
482
483 static bool
484 format_is_int8(VkFormat format)
485 {
486 const struct vk_format_description *desc = vk_format_description(format);
487 int channel = vk_format_get_first_non_void_channel(format);
488
489 return channel >= 0 && desc->channel[channel].pure_integer &&
490 desc->channel[channel].size == 8;
491 }
492
493 static bool
494 format_is_int10(VkFormat format)
495 {
496 const struct vk_format_description *desc = vk_format_description(format);
497
498 if (desc->nr_channels != 4)
499 return false;
500 for (unsigned i = 0; i < 4; i++) {
501 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
502 return true;
503 }
504 return false;
505 }
506
507 static void
508 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
509 const VkGraphicsPipelineCreateInfo *pCreateInfo,
510 struct radv_blend_state *blend)
511 {
512 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
513 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
514 unsigned col_format = 0, is_int8 = 0, is_int10 = 0;
515 unsigned num_targets;
516
517 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
518 unsigned cf;
519
520 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED ||
521 !(blend->cb_target_mask & (0xfu << (i * 4)))) {
522 cf = V_028714_SPI_SHADER_ZERO;
523 } else {
524 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
525 bool blend_enable =
526 blend->blend_enable_4bit & (0xfu << (i * 4));
527
528 cf = radv_choose_spi_color_format(attachment->format,
529 blend_enable,
530 blend->need_src_alpha & (1 << i));
531
532 if (format_is_int8(attachment->format))
533 is_int8 |= 1 << i;
534 if (format_is_int10(attachment->format))
535 is_int10 |= 1 << i;
536 }
537
538 col_format |= cf << (4 * i);
539 }
540
541 if (!(col_format & 0xf) && blend->need_src_alpha & (1 << 0)) {
542 /* When a subpass doesn't have any color attachments, write the
543 * alpha channel of MRT0 when alpha coverage is enabled because
544 * the depth attachment needs it.
545 */
546 col_format |= V_028714_SPI_SHADER_32_AR;
547 }
548
549 /* If the i-th target format is set, all previous target formats must
550 * be non-zero to avoid hangs.
551 */
552 num_targets = (util_last_bit(col_format) + 3) / 4;
553 for (unsigned i = 0; i < num_targets; i++) {
554 if (!(col_format & (0xf << (i * 4)))) {
555 col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
556 }
557 }
558
559 /* The output for dual source blending should have the same format as
560 * the first output.
561 */
562 if (blend->mrt0_is_dual_src)
563 col_format |= (col_format & 0xf) << 4;
564
565 blend->spi_shader_col_format = col_format;
566 blend->col_format_is_int8 = is_int8;
567 blend->col_format_is_int10 = is_int10;
568 }
569
570 /*
571 * Ordered so that for each i,
572 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
573 */
574 const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = {
575 VK_FORMAT_R32_SFLOAT,
576 VK_FORMAT_R32G32_SFLOAT,
577 VK_FORMAT_R8G8B8A8_UNORM,
578 VK_FORMAT_R16G16B16A16_UNORM,
579 VK_FORMAT_R16G16B16A16_SNORM,
580 VK_FORMAT_R16G16B16A16_UINT,
581 VK_FORMAT_R16G16B16A16_SINT,
582 VK_FORMAT_R32G32B32A32_SFLOAT,
583 VK_FORMAT_R8G8B8A8_UINT,
584 VK_FORMAT_R8G8B8A8_SINT,
585 VK_FORMAT_A2R10G10B10_UINT_PACK32,
586 VK_FORMAT_A2R10G10B10_SINT_PACK32,
587 };
588
589 unsigned radv_format_meta_fs_key(VkFormat format)
590 {
591 unsigned col_format = radv_choose_spi_color_format(format, false, false);
592
593 assert(col_format != V_028714_SPI_SHADER_32_AR);
594 if (col_format >= V_028714_SPI_SHADER_32_AR)
595 --col_format; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
596
597 --col_format; /* Skip V_028714_SPI_SHADER_ZERO */
598 bool is_int8 = format_is_int8(format);
599 bool is_int10 = format_is_int10(format);
600
601 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
602 }
603
604 static void
605 radv_blend_check_commutativity(struct radv_blend_state *blend,
606 VkBlendOp op, VkBlendFactor src,
607 VkBlendFactor dst, unsigned chanmask)
608 {
609 /* Src factor is allowed when it does not depend on Dst. */
610 static const uint32_t src_allowed =
611 (1u << VK_BLEND_FACTOR_ONE) |
612 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
613 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
614 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
615 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
616 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
617 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
618 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
619 (1u << VK_BLEND_FACTOR_ZERO) |
620 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
621 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
622 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
623 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
624 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
625 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
626
627 if (dst == VK_BLEND_FACTOR_ONE &&
628 (src_allowed & (1u << src))) {
629 /* Addition is commutative, but floating point addition isn't
630 * associative: subtle changes can be introduced via different
631 * rounding. Be conservative, only enable for min and max.
632 */
633 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
634 blend->commutative_4bit |= chanmask;
635 }
636 }
637
638 static struct radv_blend_state
639 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
640 const VkGraphicsPipelineCreateInfo *pCreateInfo,
641 const struct radv_graphics_pipeline_create_info *extra)
642 {
643 const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
644 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
645 struct radv_blend_state blend = {0};
646 unsigned mode = V_028808_CB_NORMAL;
647 int i;
648
649 if (extra && extra->custom_blend_mode) {
650 blend.single_cb_enable = true;
651 mode = extra->custom_blend_mode;
652 }
653
654 blend.cb_color_control = 0;
655 if (vkblend) {
656 if (vkblend->logicOpEnable)
657 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
658 else
659 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
660 }
661
662 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
663 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
664 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
665 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
666 S_028B70_OFFSET_ROUND(1);
667
668 if (vkms && vkms->alphaToCoverageEnable) {
669 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
670 blend.need_src_alpha |= 0x1;
671 }
672
673 blend.cb_target_mask = 0;
674 if (vkblend) {
675 for (i = 0; i < vkblend->attachmentCount; i++) {
676 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
677 unsigned blend_cntl = 0;
678 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
679 VkBlendOp eqRGB = att->colorBlendOp;
680 VkBlendFactor srcRGB = att->srcColorBlendFactor;
681 VkBlendFactor dstRGB = att->dstColorBlendFactor;
682 VkBlendOp eqA = att->alphaBlendOp;
683 VkBlendFactor srcA = att->srcAlphaBlendFactor;
684 VkBlendFactor dstA = att->dstAlphaBlendFactor;
685
686 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
687
688 if (!att->colorWriteMask)
689 continue;
690
691 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
692 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
693 if (!att->blendEnable) {
694 blend.cb_blend_control[i] = blend_cntl;
695 continue;
696 }
697
698 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
699 if (i == 0)
700 blend.mrt0_is_dual_src = true;
701
702 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
703 srcRGB = VK_BLEND_FACTOR_ONE;
704 dstRGB = VK_BLEND_FACTOR_ONE;
705 }
706 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
707 srcA = VK_BLEND_FACTOR_ONE;
708 dstA = VK_BLEND_FACTOR_ONE;
709 }
710
711 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
712 0x7 << (4 * i));
713 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
714 0x8 << (4 * i));
715
716 /* Blending optimizations for RB+.
717 * These transformations don't change the behavior.
718 *
719 * First, get rid of DST in the blend factors:
720 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
721 */
722 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
723 VK_BLEND_FACTOR_DST_COLOR,
724 VK_BLEND_FACTOR_SRC_COLOR);
725
726 si_blend_remove_dst(&eqA, &srcA, &dstA,
727 VK_BLEND_FACTOR_DST_COLOR,
728 VK_BLEND_FACTOR_SRC_COLOR);
729
730 si_blend_remove_dst(&eqA, &srcA, &dstA,
731 VK_BLEND_FACTOR_DST_ALPHA,
732 VK_BLEND_FACTOR_SRC_ALPHA);
733
734 /* Look up the ideal settings from tables. */
735 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
736 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
737 srcA_opt = si_translate_blend_opt_factor(srcA, true);
738 dstA_opt = si_translate_blend_opt_factor(dstA, true);
739
740 /* Handle interdependencies. */
741 if (si_blend_factor_uses_dst(srcRGB))
742 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
743 if (si_blend_factor_uses_dst(srcA))
744 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
745
746 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
747 (dstRGB == VK_BLEND_FACTOR_ZERO ||
748 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
749 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
750 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
751
752 /* Set the final value. */
753 blend.sx_mrt_blend_opt[i] =
754 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
755 S_028760_COLOR_DST_OPT(dstRGB_opt) |
756 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
757 S_028760_ALPHA_SRC_OPT(srcA_opt) |
758 S_028760_ALPHA_DST_OPT(dstA_opt) |
759 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
760 blend_cntl |= S_028780_ENABLE(1);
761
762 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
763 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
764 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
765 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
766 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
767 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
768 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
769 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
770 }
771 blend.cb_blend_control[i] = blend_cntl;
772
773 blend.blend_enable_4bit |= 0xfu << (i * 4);
774
775 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
776 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
777 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
778 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
779 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
780 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
781 blend.need_src_alpha |= 1 << i;
782 }
783 for (i = vkblend->attachmentCount; i < 8; i++) {
784 blend.cb_blend_control[i] = 0;
785 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
786 }
787 }
788
789 if (pipeline->device->physical_device->rad_info.has_rbplus) {
790 /* Disable RB+ blend optimizations for dual source blending. */
791 if (blend.mrt0_is_dual_src) {
792 for (i = 0; i < 8; i++) {
793 blend.sx_mrt_blend_opt[i] =
794 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
795 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
796 }
797 }
798
799 /* RB+ doesn't work with dual source blending, logic op and
800 * RESOLVE.
801 */
802 if (blend.mrt0_is_dual_src ||
803 (vkblend && vkblend->logicOpEnable) ||
804 mode == V_028808_CB_RESOLVE)
805 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
806 }
807
808 if (blend.cb_target_mask)
809 blend.cb_color_control |= S_028808_MODE(mode);
810 else
811 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
812
813 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
814 return blend;
815 }
816
817 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
818 {
819 switch (op) {
820 case VK_STENCIL_OP_KEEP:
821 return V_02842C_STENCIL_KEEP;
822 case VK_STENCIL_OP_ZERO:
823 return V_02842C_STENCIL_ZERO;
824 case VK_STENCIL_OP_REPLACE:
825 return V_02842C_STENCIL_REPLACE_TEST;
826 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
827 return V_02842C_STENCIL_ADD_CLAMP;
828 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
829 return V_02842C_STENCIL_SUB_CLAMP;
830 case VK_STENCIL_OP_INVERT:
831 return V_02842C_STENCIL_INVERT;
832 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
833 return V_02842C_STENCIL_ADD_WRAP;
834 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
835 return V_02842C_STENCIL_SUB_WRAP;
836 default:
837 return 0;
838 }
839 }
840
841 static uint32_t si_translate_fill(VkPolygonMode func)
842 {
843 switch(func) {
844 case VK_POLYGON_MODE_FILL:
845 return V_028814_X_DRAW_TRIANGLES;
846 case VK_POLYGON_MODE_LINE:
847 return V_028814_X_DRAW_LINES;
848 case VK_POLYGON_MODE_POINT:
849 return V_028814_X_DRAW_POINTS;
850 default:
851 assert(0);
852 return V_028814_X_DRAW_POINTS;
853 }
854 }
855
856 static uint8_t radv_pipeline_get_ps_iter_samples(const VkGraphicsPipelineCreateInfo *pCreateInfo)
857 {
858 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
859 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
860 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
861 uint32_t ps_iter_samples = 1;
862 uint32_t num_samples;
863
864 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
865 *
866 * "If the VK_AMD_mixed_attachment_samples extension is enabled and the
867 * subpass uses color attachments, totalSamples is the number of
868 * samples of the color attachments. Otherwise, totalSamples is the
869 * value of VkPipelineMultisampleStateCreateInfo::rasterizationSamples
870 * specified at pipeline creation time."
871 */
872 if (subpass->has_color_att) {
873 num_samples = subpass->color_sample_count;
874 } else {
875 num_samples = vkms->rasterizationSamples;
876 }
877
878 if (vkms->sampleShadingEnable) {
879 ps_iter_samples = ceilf(vkms->minSampleShading * num_samples);
880 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
881 }
882 return ps_iter_samples;
883 }
884
885 static bool
886 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
887 {
888 return pCreateInfo->depthTestEnable &&
889 pCreateInfo->depthWriteEnable &&
890 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
891 }
892
893 static bool
894 radv_writes_stencil(const VkStencilOpState *state)
895 {
896 return state->writeMask &&
897 (state->failOp != VK_STENCIL_OP_KEEP ||
898 state->passOp != VK_STENCIL_OP_KEEP ||
899 state->depthFailOp != VK_STENCIL_OP_KEEP);
900 }
901
902 static bool
903 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
904 {
905 return pCreateInfo->stencilTestEnable &&
906 (radv_writes_stencil(&pCreateInfo->front) ||
907 radv_writes_stencil(&pCreateInfo->back));
908 }
909
910 static bool
911 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
912 {
913 return radv_is_depth_write_enabled(pCreateInfo) ||
914 radv_is_stencil_write_enabled(pCreateInfo);
915 }
916
917 static bool
918 radv_order_invariant_stencil_op(VkStencilOp op)
919 {
920 /* REPLACE is normally order invariant, except when the stencil
921 * reference value is written by the fragment shader. Tracking this
922 * interaction does not seem worth the effort, so be conservative.
923 */
924 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
925 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
926 op != VK_STENCIL_OP_REPLACE;
927 }
928
929 static bool
930 radv_order_invariant_stencil_state(const VkStencilOpState *state)
931 {
932 /* Compute whether, assuming Z writes are disabled, this stencil state
933 * is order invariant in the sense that the set of passing fragments as
934 * well as the final stencil buffer result does not depend on the order
935 * of fragments.
936 */
937 return !state->writeMask ||
938 /* The following assumes that Z writes are disabled. */
939 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
940 radv_order_invariant_stencil_op(state->passOp) &&
941 radv_order_invariant_stencil_op(state->depthFailOp)) ||
942 (state->compareOp == VK_COMPARE_OP_NEVER &&
943 radv_order_invariant_stencil_op(state->failOp));
944 }
945
946 static bool
947 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
948 struct radv_blend_state *blend,
949 const VkGraphicsPipelineCreateInfo *pCreateInfo)
950 {
951 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
952 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
953 const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
954 const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
955 unsigned colormask = blend->cb_target_enabled_4bit;
956
957 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
958 return false;
959
960 /* Be conservative if a logic operation is enabled with color buffers. */
961 if (colormask && vkblend && vkblend->logicOpEnable)
962 return false;
963
964 /* Default depth/stencil invariance when no attachment is bound. */
965 struct radv_dsa_order_invariance dsa_order_invariant = {
966 .zs = true, .pass_set = true
967 };
968
969 if (vkds) {
970 struct radv_render_pass_attachment *attachment =
971 pass->attachments + subpass->depth_stencil_attachment->attachment;
972 bool has_stencil = vk_format_is_stencil(attachment->format);
973 struct radv_dsa_order_invariance order_invariance[2];
974 struct radv_shader_variant *ps =
975 pipeline->shaders[MESA_SHADER_FRAGMENT];
976
977 /* Compute depth/stencil order invariance in order to know if
978 * it's safe to enable out-of-order.
979 */
980 bool zfunc_is_ordered =
981 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
982 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
983 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
984 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
985 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
986
987 bool nozwrite_and_order_invariant_stencil =
988 !radv_is_ds_write_enabled(vkds) ||
989 (!radv_is_depth_write_enabled(vkds) &&
990 radv_order_invariant_stencil_state(&vkds->front) &&
991 radv_order_invariant_stencil_state(&vkds->back));
992
993 order_invariance[1].zs =
994 nozwrite_and_order_invariant_stencil ||
995 (!radv_is_stencil_write_enabled(vkds) &&
996 zfunc_is_ordered);
997 order_invariance[0].zs =
998 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
999
1000 order_invariance[1].pass_set =
1001 nozwrite_and_order_invariant_stencil ||
1002 (!radv_is_stencil_write_enabled(vkds) &&
1003 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1004 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
1005 order_invariance[0].pass_set =
1006 !radv_is_depth_write_enabled(vkds) ||
1007 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1008 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
1009
1010 dsa_order_invariant = order_invariance[has_stencil];
1011 if (!dsa_order_invariant.zs)
1012 return false;
1013
1014 /* The set of PS invocations is always order invariant,
1015 * except when early Z/S tests are requested.
1016 */
1017 if (ps &&
1018 ps->info.ps.writes_memory &&
1019 ps->info.ps.early_fragment_test &&
1020 !dsa_order_invariant.pass_set)
1021 return false;
1022
1023 /* Determine if out-of-order rasterization should be disabled
1024 * when occlusion queries are used.
1025 */
1026 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
1027 !dsa_order_invariant.pass_set;
1028 }
1029
1030 /* No color buffers are enabled for writing. */
1031 if (!colormask)
1032 return true;
1033
1034 unsigned blendmask = colormask & blend->blend_enable_4bit;
1035
1036 if (blendmask) {
1037 /* Only commutative blending. */
1038 if (blendmask & ~blend->commutative_4bit)
1039 return false;
1040
1041 if (!dsa_order_invariant.pass_set)
1042 return false;
1043 }
1044
1045 if (colormask & ~blendmask)
1046 return false;
1047
1048 return true;
1049 }
1050
1051 static void
1052 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1053 struct radv_blend_state *blend,
1054 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1055 {
1056 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
1057 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1058 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1059 bool out_of_order_rast = false;
1060 int ps_iter_samples = 1;
1061 uint32_t mask = 0xffff;
1062
1063 if (vkms) {
1064 ms->num_samples = vkms->rasterizationSamples;
1065
1066 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1067 *
1068 * "Sample shading is enabled for a graphics pipeline:
1069 *
1070 * - If the interface of the fragment shader entry point of the
1071 * graphics pipeline includes an input variable decorated
1072 * with SampleId or SamplePosition. In this case
1073 * minSampleShadingFactor takes the value 1.0.
1074 * - Else if the sampleShadingEnable member of the
1075 * VkPipelineMultisampleStateCreateInfo structure specified
1076 * when creating the graphics pipeline is set to VK_TRUE. In
1077 * this case minSampleShadingFactor takes the value of
1078 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1079 *
1080 * Otherwise, sample shading is considered disabled."
1081 */
1082 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.force_persample) {
1083 ps_iter_samples = ms->num_samples;
1084 } else {
1085 ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
1086 }
1087 } else {
1088 ms->num_samples = 1;
1089 }
1090
1091 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1092 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1093 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1094 /* Out-of-order rasterization is explicitly enabled by the
1095 * application.
1096 */
1097 out_of_order_rast = true;
1098 } else {
1099 /* Determine if the driver can enable out-of-order
1100 * rasterization internally.
1101 */
1102 out_of_order_rast =
1103 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1104 }
1105
1106 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1107 ms->pa_sc_aa_config = 0;
1108 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1109 S_028804_INCOHERENT_EQAA_READS(1) |
1110 S_028804_INTERPOLATE_COMP_Z(1) |
1111 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1112 ms->pa_sc_mode_cntl_1 =
1113 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1114 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1115 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
1116 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1117 /* always 1: */
1118 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1119 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1120 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1121 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1122 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1123 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1124 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1125 S_028A48_VPORT_SCISSOR_ENABLE(1);
1126
1127 const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line =
1128 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1129 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
1130 if (rast_line) {
1131 ms->pa_sc_mode_cntl_0 |= S_028A48_LINE_STIPPLE_ENABLE(rast_line->stippledLineEnable);
1132 if (rast_line->lineRasterizationMode == VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT) {
1133 /* From the Vulkan spec 1.1.129:
1134 *
1135 * "When VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT lines
1136 * are being rasterized, sample locations may all be
1137 * treated as being at the pixel center (this may
1138 * affect attribute and depth interpolation)."
1139 */
1140 ms->num_samples = 1;
1141 }
1142 }
1143
1144 if (ms->num_samples > 1) {
1145 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1146 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1147 uint32_t z_samples = subpass->depth_stencil_attachment ? subpass->depth_sample_count : ms->num_samples;
1148 unsigned log_samples = util_logbase2(ms->num_samples);
1149 unsigned log_z_samples = util_logbase2(z_samples);
1150 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1151 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1152 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
1153 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1154 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1155 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1156 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1157 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) |
1158 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples) | /* CM_R_028BE0_PA_SC_AA_CONFIG */
1159 S_028BE0_COVERED_CENTROID_IS_CENTER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3);
1160 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1161 if (ps_iter_samples > 1)
1162 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1163 }
1164
1165 if (vkms && vkms->pSampleMask) {
1166 mask = vkms->pSampleMask[0] & 0xffff;
1167 }
1168
1169 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1170 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1171 }
1172
1173 static bool
1174 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1175 {
1176 switch (topology) {
1177 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1178 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1179 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1180 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1181 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1182 return false;
1183 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1184 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1185 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1186 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1187 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1188 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1189 return true;
1190 default:
1191 unreachable("unhandled primitive type");
1192 }
1193 }
1194
1195 static uint32_t
1196 si_translate_prim(enum VkPrimitiveTopology topology)
1197 {
1198 switch (topology) {
1199 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1200 return V_008958_DI_PT_POINTLIST;
1201 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1202 return V_008958_DI_PT_LINELIST;
1203 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1204 return V_008958_DI_PT_LINESTRIP;
1205 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1206 return V_008958_DI_PT_TRILIST;
1207 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1208 return V_008958_DI_PT_TRISTRIP;
1209 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1210 return V_008958_DI_PT_TRIFAN;
1211 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1212 return V_008958_DI_PT_LINELIST_ADJ;
1213 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1214 return V_008958_DI_PT_LINESTRIP_ADJ;
1215 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1216 return V_008958_DI_PT_TRILIST_ADJ;
1217 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1218 return V_008958_DI_PT_TRISTRIP_ADJ;
1219 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1220 return V_008958_DI_PT_PATCH;
1221 default:
1222 assert(0);
1223 return 0;
1224 }
1225 }
1226
1227 static uint32_t
1228 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1229 {
1230 switch (gl_prim) {
1231 case 0: /* GL_POINTS */
1232 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1233 case 1: /* GL_LINES */
1234 case 3: /* GL_LINE_STRIP */
1235 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1236 case 0x8E7A: /* GL_ISOLINES */
1237 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1238
1239 case 4: /* GL_TRIANGLES */
1240 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1241 case 5: /* GL_TRIANGLE_STRIP */
1242 case 7: /* GL_QUADS */
1243 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1244 default:
1245 assert(0);
1246 return 0;
1247 }
1248 }
1249
1250 static uint32_t
1251 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1252 {
1253 switch (topology) {
1254 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1255 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1256 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1257 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1258 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1259 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1260 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1261 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1262 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1263 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1264 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1265 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1266 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1267 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1268 default:
1269 assert(0);
1270 return 0;
1271 }
1272 }
1273
1274 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1275 {
1276 switch(state) {
1277 case VK_DYNAMIC_STATE_VIEWPORT:
1278 return RADV_DYNAMIC_VIEWPORT;
1279 case VK_DYNAMIC_STATE_SCISSOR:
1280 return RADV_DYNAMIC_SCISSOR;
1281 case VK_DYNAMIC_STATE_LINE_WIDTH:
1282 return RADV_DYNAMIC_LINE_WIDTH;
1283 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1284 return RADV_DYNAMIC_DEPTH_BIAS;
1285 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1286 return RADV_DYNAMIC_BLEND_CONSTANTS;
1287 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1288 return RADV_DYNAMIC_DEPTH_BOUNDS;
1289 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1290 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1291 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1292 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1293 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1294 return RADV_DYNAMIC_STENCIL_REFERENCE;
1295 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1296 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1297 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
1298 return RADV_DYNAMIC_SAMPLE_LOCATIONS;
1299 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT:
1300 return RADV_DYNAMIC_LINE_STIPPLE;
1301 default:
1302 unreachable("Unhandled dynamic state");
1303 }
1304 }
1305
1306 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1307 {
1308 uint32_t states = RADV_DYNAMIC_ALL;
1309
1310 /* If rasterization is disabled we do not care about any of the dynamic states,
1311 * since they are all rasterization related only. */
1312 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1313 return 0;
1314
1315 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1316 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1317
1318 if (!pCreateInfo->pDepthStencilState ||
1319 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1320 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1321
1322 if (!pCreateInfo->pDepthStencilState ||
1323 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1324 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1325 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1326 RADV_DYNAMIC_STENCIL_REFERENCE);
1327
1328 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1329 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1330
1331 if (!pCreateInfo->pMultisampleState ||
1332 !vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1333 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT))
1334 states &= ~RADV_DYNAMIC_SAMPLE_LOCATIONS;
1335
1336 if (!pCreateInfo->pRasterizationState ||
1337 !vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1338 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT))
1339 states &= ~RADV_DYNAMIC_LINE_STIPPLE;
1340
1341 /* TODO: blend constants & line width. */
1342
1343 return states;
1344 }
1345
1346
1347 static void
1348 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1349 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1350 {
1351 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1352 uint32_t states = needed_states;
1353 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1354 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1355
1356 pipeline->dynamic_state = default_dynamic_state;
1357 pipeline->graphics.needed_dynamic_state = needed_states;
1358
1359 if (pCreateInfo->pDynamicState) {
1360 /* Remove all of the states that are marked as dynamic */
1361 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1362 for (uint32_t s = 0; s < count; s++)
1363 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1364 }
1365
1366 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1367
1368 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1369 assert(pCreateInfo->pViewportState);
1370
1371 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1372 if (states & RADV_DYNAMIC_VIEWPORT) {
1373 typed_memcpy(dynamic->viewport.viewports,
1374 pCreateInfo->pViewportState->pViewports,
1375 pCreateInfo->pViewportState->viewportCount);
1376 }
1377 }
1378
1379 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1380 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1381 if (states & RADV_DYNAMIC_SCISSOR) {
1382 typed_memcpy(dynamic->scissor.scissors,
1383 pCreateInfo->pViewportState->pScissors,
1384 pCreateInfo->pViewportState->scissorCount);
1385 }
1386 }
1387
1388 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1389 assert(pCreateInfo->pRasterizationState);
1390 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1391 }
1392
1393 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1394 assert(pCreateInfo->pRasterizationState);
1395 dynamic->depth_bias.bias =
1396 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1397 dynamic->depth_bias.clamp =
1398 pCreateInfo->pRasterizationState->depthBiasClamp;
1399 dynamic->depth_bias.slope =
1400 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1401 }
1402
1403 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1404 *
1405 * pColorBlendState is [...] NULL if the pipeline has rasterization
1406 * disabled or if the subpass of the render pass the pipeline is
1407 * created against does not use any color attachments.
1408 */
1409 if (subpass->has_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1410 assert(pCreateInfo->pColorBlendState);
1411 typed_memcpy(dynamic->blend_constants,
1412 pCreateInfo->pColorBlendState->blendConstants, 4);
1413 }
1414
1415 /* If there is no depthstencil attachment, then don't read
1416 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1417 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1418 * no need to override the depthstencil defaults in
1419 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1420 *
1421 * Section 9.2 of the Vulkan 1.0.15 spec says:
1422 *
1423 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1424 * disabled or if the subpass of the render pass the pipeline is created
1425 * against does not use a depth/stencil attachment.
1426 */
1427 if (needed_states && subpass->depth_stencil_attachment) {
1428 assert(pCreateInfo->pDepthStencilState);
1429
1430 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1431 dynamic->depth_bounds.min =
1432 pCreateInfo->pDepthStencilState->minDepthBounds;
1433 dynamic->depth_bounds.max =
1434 pCreateInfo->pDepthStencilState->maxDepthBounds;
1435 }
1436
1437 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1438 dynamic->stencil_compare_mask.front =
1439 pCreateInfo->pDepthStencilState->front.compareMask;
1440 dynamic->stencil_compare_mask.back =
1441 pCreateInfo->pDepthStencilState->back.compareMask;
1442 }
1443
1444 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1445 dynamic->stencil_write_mask.front =
1446 pCreateInfo->pDepthStencilState->front.writeMask;
1447 dynamic->stencil_write_mask.back =
1448 pCreateInfo->pDepthStencilState->back.writeMask;
1449 }
1450
1451 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1452 dynamic->stencil_reference.front =
1453 pCreateInfo->pDepthStencilState->front.reference;
1454 dynamic->stencil_reference.back =
1455 pCreateInfo->pDepthStencilState->back.reference;
1456 }
1457 }
1458
1459 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1460 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1461 if (needed_states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1462 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1463 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1464 typed_memcpy(dynamic->discard_rectangle.rectangles,
1465 discard_rectangle_info->pDiscardRectangles,
1466 discard_rectangle_info->discardRectangleCount);
1467 }
1468 }
1469
1470 if (needed_states & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
1471 const VkPipelineSampleLocationsStateCreateInfoEXT *sample_location_info =
1472 vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1473 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1474 /* If sampleLocationsEnable is VK_FALSE, the default sample
1475 * locations are used and the values specified in
1476 * sampleLocationsInfo are ignored.
1477 */
1478 if (sample_location_info->sampleLocationsEnable) {
1479 const VkSampleLocationsInfoEXT *pSampleLocationsInfo =
1480 &sample_location_info->sampleLocationsInfo;
1481
1482 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
1483
1484 dynamic->sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
1485 dynamic->sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
1486 dynamic->sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
1487 typed_memcpy(&dynamic->sample_location.locations[0],
1488 pSampleLocationsInfo->pSampleLocations,
1489 pSampleLocationsInfo->sampleLocationsCount);
1490 }
1491 }
1492
1493 const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line_info =
1494 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1495 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
1496 if (needed_states & RADV_DYNAMIC_LINE_STIPPLE) {
1497 dynamic->line_stipple.factor = rast_line_info->lineStippleFactor;
1498 dynamic->line_stipple.pattern = rast_line_info->lineStipplePattern;
1499 }
1500
1501 pipeline->dynamic_state.mask = states;
1502 }
1503
1504 static void
1505 gfx9_get_gs_info(const struct radv_pipeline_key *key,
1506 const struct radv_pipeline *pipeline,
1507 nir_shader **nir,
1508 struct radv_shader_info *infos,
1509 struct gfx9_gs_info *out)
1510 {
1511 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1512 struct radv_es_output_info *es_info;
1513 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1514 es_info = nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1515 else
1516 es_info = nir[MESA_SHADER_TESS_CTRL] ?
1517 &infos[MESA_SHADER_TESS_EVAL].tes.es_info :
1518 &infos[MESA_SHADER_VERTEX].vs.es_info;
1519
1520 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1521 bool uses_adjacency;
1522 switch(key->topology) {
1523 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1524 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1525 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1526 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1527 uses_adjacency = true;
1528 break;
1529 default:
1530 uses_adjacency = false;
1531 break;
1532 }
1533
1534 /* All these are in dwords: */
1535 /* We can't allow using the whole LDS, because GS waves compete with
1536 * other shader stages for LDS space. */
1537 const unsigned max_lds_size = 8 * 1024;
1538 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1539 unsigned esgs_lds_size;
1540
1541 /* All these are per subgroup: */
1542 const unsigned max_out_prims = 32 * 1024;
1543 const unsigned max_es_verts = 255;
1544 const unsigned ideal_gs_prims = 64;
1545 unsigned max_gs_prims, gs_prims;
1546 unsigned min_es_verts, es_verts, worst_case_es_verts;
1547
1548 if (uses_adjacency || gs_num_invocations > 1)
1549 max_gs_prims = 127 / gs_num_invocations;
1550 else
1551 max_gs_prims = 255;
1552
1553 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1554 * Make sure we don't go over the maximum value.
1555 */
1556 if (gs_info->gs.vertices_out > 0) {
1557 max_gs_prims = MIN2(max_gs_prims,
1558 max_out_prims /
1559 (gs_info->gs.vertices_out * gs_num_invocations));
1560 }
1561 assert(max_gs_prims > 0);
1562
1563 /* If the primitive has adjacency, halve the number of vertices
1564 * that will be reused in multiple primitives.
1565 */
1566 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1567
1568 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1569 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1570
1571 /* Compute ESGS LDS size based on the worst case number of ES vertices
1572 * needed to create the target number of GS prims per subgroup.
1573 */
1574 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1575
1576 /* If total LDS usage is too big, refactor partitions based on ratio
1577 * of ESGS item sizes.
1578 */
1579 if (esgs_lds_size > max_lds_size) {
1580 /* Our target GS Prims Per Subgroup was too large. Calculate
1581 * the maximum number of GS Prims Per Subgroup that will fit
1582 * into LDS, capped by the maximum that the hardware can support.
1583 */
1584 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1585 max_gs_prims);
1586 assert(gs_prims > 0);
1587 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1588 max_es_verts);
1589
1590 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1591 assert(esgs_lds_size <= max_lds_size);
1592 }
1593
1594 /* Now calculate remaining ESGS information. */
1595 if (esgs_lds_size)
1596 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1597 else
1598 es_verts = max_es_verts;
1599
1600 /* Vertices for adjacency primitives are not always reused, so restore
1601 * it for ES_VERTS_PER_SUBGRP.
1602 */
1603 min_es_verts = gs_info->gs.vertices_in;
1604
1605 /* For normal primitives, the VGT only checks if they are past the ES
1606 * verts per subgroup after allocating a full GS primitive and if they
1607 * are, kick off a new subgroup. But if those additional ES verts are
1608 * unique (e.g. not reused) we need to make sure there is enough LDS
1609 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1610 */
1611 es_verts -= min_es_verts - 1;
1612
1613 uint32_t es_verts_per_subgroup = es_verts;
1614 uint32_t gs_prims_per_subgroup = gs_prims;
1615 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1616 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1617 out->lds_size = align(esgs_lds_size, 128) / 128;
1618 out->vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1619 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1620 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1621 out->vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1622 out->vgt_esgs_ring_itemsize = esgs_itemsize;
1623 assert(max_prims_per_subgroup <= max_out_prims);
1624 }
1625
1626 static void clamp_gsprims_to_esverts(unsigned *max_gsprims, unsigned max_esverts,
1627 unsigned min_verts_per_prim, bool use_adjacency)
1628 {
1629 unsigned max_reuse = max_esverts - min_verts_per_prim;
1630 if (use_adjacency)
1631 max_reuse /= 2;
1632 *max_gsprims = MIN2(*max_gsprims, 1 + max_reuse);
1633 }
1634
1635 static unsigned
1636 radv_get_num_input_vertices(nir_shader **nir)
1637 {
1638 if (nir[MESA_SHADER_GEOMETRY]) {
1639 nir_shader *gs = nir[MESA_SHADER_GEOMETRY];
1640
1641 return gs->info.gs.vertices_in;
1642 }
1643
1644 if (nir[MESA_SHADER_TESS_CTRL]) {
1645 nir_shader *tes = nir[MESA_SHADER_TESS_EVAL];
1646
1647 if (tes->info.tess.point_mode)
1648 return 1;
1649 if (tes->info.tess.primitive_mode == GL_ISOLINES)
1650 return 2;
1651 return 3;
1652 }
1653
1654 return 3;
1655 }
1656
1657 static void
1658 gfx10_get_ngg_info(const struct radv_pipeline_key *key,
1659 struct radv_pipeline *pipeline,
1660 nir_shader **nir,
1661 struct radv_shader_info *infos,
1662 struct gfx10_ngg_info *ngg)
1663 {
1664 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1665 struct radv_es_output_info *es_info =
1666 nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1667 unsigned gs_type = nir[MESA_SHADER_GEOMETRY] ? MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX;
1668 unsigned max_verts_per_prim = radv_get_num_input_vertices(nir);
1669 unsigned min_verts_per_prim =
1670 gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1;
1671 unsigned gs_num_invocations = nir[MESA_SHADER_GEOMETRY] ? MAX2(gs_info->gs.invocations, 1) : 1;
1672 bool uses_adjacency;
1673 switch(key->topology) {
1674 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1675 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1676 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1677 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1678 uses_adjacency = true;
1679 break;
1680 default:
1681 uses_adjacency = false;
1682 break;
1683 }
1684
1685 /* All these are in dwords: */
1686 /* We can't allow using the whole LDS, because GS waves compete with
1687 * other shader stages for LDS space.
1688 *
1689 * TODO: We should really take the shader's internal LDS use into
1690 * account. The linker will fail if the size is greater than
1691 * 8K dwords.
1692 */
1693 const unsigned max_lds_size = 8 * 1024 - 768;
1694 const unsigned target_lds_size = max_lds_size;
1695 unsigned esvert_lds_size = 0;
1696 unsigned gsprim_lds_size = 0;
1697
1698 /* All these are per subgroup: */
1699 bool max_vert_out_per_gs_instance = false;
1700 unsigned max_esverts_base = 256;
1701 unsigned max_gsprims_base = 128; /* default prim group size clamp */
1702
1703 /* Hardware has the following non-natural restrictions on the value
1704 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1705 * the draw:
1706 * - at most 252 for any line input primitive type
1707 * - at most 251 for any quad input primitive type
1708 * - at most 251 for triangle strips with adjacency (this happens to
1709 * be the natural limit for triangle *lists* with adjacency)
1710 */
1711 max_esverts_base = MIN2(max_esverts_base, 251 + max_verts_per_prim - 1);
1712
1713 if (gs_type == MESA_SHADER_GEOMETRY) {
1714 unsigned max_out_verts_per_gsprim =
1715 gs_info->gs.vertices_out * gs_num_invocations;
1716
1717 if (max_out_verts_per_gsprim <= 256) {
1718 if (max_out_verts_per_gsprim) {
1719 max_gsprims_base = MIN2(max_gsprims_base,
1720 256 / max_out_verts_per_gsprim);
1721 }
1722 } else {
1723 /* Use special multi-cycling mode in which each GS
1724 * instance gets its own subgroup. Does not work with
1725 * tessellation. */
1726 max_vert_out_per_gs_instance = true;
1727 max_gsprims_base = 1;
1728 max_out_verts_per_gsprim = gs_info->gs.vertices_out;
1729 }
1730
1731 esvert_lds_size = es_info->esgs_itemsize / 4;
1732 gsprim_lds_size = (gs_info->gs.gsvs_vertex_size / 4 + 1) * max_out_verts_per_gsprim;
1733 } else {
1734 /* VS and TES. */
1735 /* LDS size for passing data from GS to ES. */
1736 struct radv_streamout_info *so_info = nir[MESA_SHADER_TESS_CTRL]
1737 ? &infos[MESA_SHADER_TESS_EVAL].so
1738 : &infos[MESA_SHADER_VERTEX].so;
1739
1740 if (so_info->num_outputs)
1741 esvert_lds_size = 4 * so_info->num_outputs + 1;
1742
1743 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1744 * corresponding to the ES thread of the provoking vertex. All
1745 * ES threads load and export PrimitiveID for their thread.
1746 */
1747 if (!nir[MESA_SHADER_TESS_CTRL] &&
1748 infos[MESA_SHADER_VERTEX].vs.outinfo.export_prim_id)
1749 esvert_lds_size = MAX2(esvert_lds_size, 1);
1750 }
1751
1752 unsigned max_gsprims = max_gsprims_base;
1753 unsigned max_esverts = max_esverts_base;
1754
1755 if (esvert_lds_size)
1756 max_esverts = MIN2(max_esverts, target_lds_size / esvert_lds_size);
1757 if (gsprim_lds_size)
1758 max_gsprims = MIN2(max_gsprims, target_lds_size / gsprim_lds_size);
1759
1760 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1761 clamp_gsprims_to_esverts(&max_gsprims, max_esverts, min_verts_per_prim, uses_adjacency);
1762 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1763
1764 if (esvert_lds_size || gsprim_lds_size) {
1765 /* Now that we have a rough proportionality between esverts
1766 * and gsprims based on the primitive type, scale both of them
1767 * down simultaneously based on required LDS space.
1768 *
1769 * We could be smarter about this if we knew how much vertex
1770 * reuse to expect.
1771 */
1772 unsigned lds_total = max_esverts * esvert_lds_size +
1773 max_gsprims * gsprim_lds_size;
1774 if (lds_total > target_lds_size) {
1775 max_esverts = max_esverts * target_lds_size / lds_total;
1776 max_gsprims = max_gsprims * target_lds_size / lds_total;
1777
1778 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1779 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1780 min_verts_per_prim, uses_adjacency);
1781 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1782 }
1783 }
1784
1785 /* Round up towards full wave sizes for better ALU utilization. */
1786 if (!max_vert_out_per_gs_instance) {
1787 unsigned orig_max_esverts;
1788 unsigned orig_max_gsprims;
1789 unsigned wavesize;
1790
1791 if (gs_type == MESA_SHADER_GEOMETRY) {
1792 wavesize = gs_info->wave_size;
1793 } else {
1794 wavesize = nir[MESA_SHADER_TESS_CTRL]
1795 ? infos[MESA_SHADER_TESS_EVAL].wave_size
1796 : infos[MESA_SHADER_VERTEX].wave_size;
1797 }
1798
1799 do {
1800 orig_max_esverts = max_esverts;
1801 orig_max_gsprims = max_gsprims;
1802
1803 max_esverts = align(max_esverts, wavesize);
1804 max_esverts = MIN2(max_esverts, max_esverts_base);
1805 if (esvert_lds_size)
1806 max_esverts = MIN2(max_esverts,
1807 (max_lds_size - max_gsprims * gsprim_lds_size) /
1808 esvert_lds_size);
1809 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1810
1811 max_gsprims = align(max_gsprims, wavesize);
1812 max_gsprims = MIN2(max_gsprims, max_gsprims_base);
1813 if (gsprim_lds_size)
1814 max_gsprims = MIN2(max_gsprims,
1815 (max_lds_size - max_esverts * esvert_lds_size) /
1816 gsprim_lds_size);
1817 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1818 min_verts_per_prim, uses_adjacency);
1819 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1820 } while (orig_max_esverts != max_esverts || orig_max_gsprims != max_gsprims);
1821 }
1822
1823 /* Hardware restriction: minimum value of max_esverts */
1824 max_esverts = MAX2(max_esverts, 23 + max_verts_per_prim);
1825
1826 unsigned max_out_vertices =
1827 max_vert_out_per_gs_instance ? gs_info->gs.vertices_out :
1828 gs_type == MESA_SHADER_GEOMETRY ?
1829 max_gsprims * gs_num_invocations * gs_info->gs.vertices_out :
1830 max_esverts;
1831 assert(max_out_vertices <= 256);
1832
1833 unsigned prim_amp_factor = 1;
1834 if (gs_type == MESA_SHADER_GEOMETRY) {
1835 /* Number of output primitives per GS input primitive after
1836 * GS instancing. */
1837 prim_amp_factor = gs_info->gs.vertices_out;
1838 }
1839
1840 /* The GE only checks against the maximum number of ES verts after
1841 * allocating a full GS primitive. So we need to ensure that whenever
1842 * this check passes, there is enough space for a full primitive without
1843 * vertex reuse.
1844 */
1845 ngg->hw_max_esverts = max_esverts - max_verts_per_prim + 1;
1846 ngg->max_gsprims = max_gsprims;
1847 ngg->max_out_verts = max_out_vertices;
1848 ngg->prim_amp_factor = prim_amp_factor;
1849 ngg->max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
1850 ngg->ngg_emit_size = max_gsprims * gsprim_lds_size;
1851 ngg->esgs_ring_size = 4 * max_esverts * esvert_lds_size;
1852
1853 if (gs_type == MESA_SHADER_GEOMETRY) {
1854 ngg->vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
1855 } else {
1856 ngg->vgt_esgs_ring_itemsize = 1;
1857 }
1858
1859 pipeline->graphics.esgs_ring_size = ngg->esgs_ring_size;
1860
1861 assert(ngg->hw_max_esverts >= 24); /* HW limitation */
1862 }
1863
1864 static void
1865 calculate_gs_ring_sizes(struct radv_pipeline *pipeline,
1866 const struct gfx9_gs_info *gs)
1867 {
1868 struct radv_device *device = pipeline->device;
1869 unsigned num_se = device->physical_device->rad_info.max_se;
1870 unsigned wave_size = 64;
1871 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1872 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1873 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1874 */
1875 unsigned gs_vertex_reuse =
1876 (device->physical_device->rad_info.chip_class >= GFX8 ? 32 : 16) * num_se;
1877 unsigned alignment = 256 * num_se;
1878 /* The maximum size is 63.999 MB per SE. */
1879 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1880 struct radv_shader_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1881
1882 /* Calculate the minimum size. */
1883 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1884 wave_size, alignment);
1885 /* These are recommended sizes, not minimum sizes. */
1886 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1887 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1888 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1889 gs_info->gs.max_gsvs_emit_size;
1890
1891 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1892 esgs_ring_size = align(esgs_ring_size, alignment);
1893 gsvs_ring_size = align(gsvs_ring_size, alignment);
1894
1895 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
1896 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1897
1898 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1899 }
1900
1901 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1902 unsigned *lds_size)
1903 {
1904 /* If tessellation is all offchip and on-chip GS isn't used, this
1905 * workaround is not needed.
1906 */
1907 return;
1908
1909 /* SPI barrier management bug:
1910 * Make sure we have at least 4k of LDS in use to avoid the bug.
1911 * It applies to workgroup sizes of more than one wavefront.
1912 */
1913 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1914 device->physical_device->rad_info.family == CHIP_KABINI)
1915 *lds_size = MAX2(*lds_size, 8);
1916 }
1917
1918 struct radv_shader_variant *
1919 radv_get_shader(struct radv_pipeline *pipeline,
1920 gl_shader_stage stage)
1921 {
1922 if (stage == MESA_SHADER_VERTEX) {
1923 if (pipeline->shaders[MESA_SHADER_VERTEX])
1924 return pipeline->shaders[MESA_SHADER_VERTEX];
1925 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1926 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1927 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1928 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1929 } else if (stage == MESA_SHADER_TESS_EVAL) {
1930 if (!radv_pipeline_has_tess(pipeline))
1931 return NULL;
1932 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1933 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1934 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1935 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1936 }
1937 return pipeline->shaders[stage];
1938 }
1939
1940 static struct radv_tessellation_state
1941 calculate_tess_state(struct radv_pipeline *pipeline,
1942 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1943 {
1944 unsigned num_tcs_input_cp;
1945 unsigned num_tcs_output_cp;
1946 unsigned lds_size;
1947 unsigned num_patches;
1948 struct radv_tessellation_state tess = {0};
1949
1950 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1951 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1952 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1953
1954 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
1955
1956 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
1957 assert(lds_size <= 65536);
1958 lds_size = align(lds_size, 512) / 512;
1959 } else {
1960 assert(lds_size <= 32768);
1961 lds_size = align(lds_size, 256) / 256;
1962 }
1963 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1964
1965 tess.lds_size = lds_size;
1966
1967 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1968 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1969 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1970 tess.num_patches = num_patches;
1971
1972 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
1973 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1974
1975 switch (tes->info.tes.primitive_mode) {
1976 case GL_TRIANGLES:
1977 type = V_028B6C_TESS_TRIANGLE;
1978 break;
1979 case GL_QUADS:
1980 type = V_028B6C_TESS_QUAD;
1981 break;
1982 case GL_ISOLINES:
1983 type = V_028B6C_TESS_ISOLINE;
1984 break;
1985 }
1986
1987 switch (tes->info.tes.spacing) {
1988 case TESS_SPACING_EQUAL:
1989 partitioning = V_028B6C_PART_INTEGER;
1990 break;
1991 case TESS_SPACING_FRACTIONAL_ODD:
1992 partitioning = V_028B6C_PART_FRAC_ODD;
1993 break;
1994 case TESS_SPACING_FRACTIONAL_EVEN:
1995 partitioning = V_028B6C_PART_FRAC_EVEN;
1996 break;
1997 default:
1998 break;
1999 }
2000
2001 bool ccw = tes->info.tes.ccw;
2002 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_origin_state =
2003 vk_find_struct_const(pCreateInfo->pTessellationState,
2004 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
2005
2006 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT)
2007 ccw = !ccw;
2008
2009 if (tes->info.tes.point_mode)
2010 topology = V_028B6C_OUTPUT_POINT;
2011 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
2012 topology = V_028B6C_OUTPUT_LINE;
2013 else if (ccw)
2014 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2015 else
2016 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2017
2018 if (pipeline->device->physical_device->rad_info.has_distributed_tess) {
2019 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
2020 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
2021 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
2022 else
2023 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
2024 } else
2025 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
2026
2027 tess.tf_param = S_028B6C_TYPE(type) |
2028 S_028B6C_PARTITIONING(partitioning) |
2029 S_028B6C_TOPOLOGY(topology) |
2030 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
2031
2032 return tess;
2033 }
2034
2035 static const struct radv_prim_vertex_count prim_size_table[] = {
2036 [V_008958_DI_PT_NONE] = {0, 0},
2037 [V_008958_DI_PT_POINTLIST] = {1, 1},
2038 [V_008958_DI_PT_LINELIST] = {2, 2},
2039 [V_008958_DI_PT_LINESTRIP] = {2, 1},
2040 [V_008958_DI_PT_TRILIST] = {3, 3},
2041 [V_008958_DI_PT_TRIFAN] = {3, 1},
2042 [V_008958_DI_PT_TRISTRIP] = {3, 1},
2043 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
2044 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
2045 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
2046 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
2047 [V_008958_DI_PT_RECTLIST] = {3, 3},
2048 [V_008958_DI_PT_LINELOOP] = {2, 1},
2049 [V_008958_DI_PT_POLYGON] = {3, 1},
2050 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
2051 };
2052
2053 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
2054 {
2055 if (radv_pipeline_has_gs(pipeline))
2056 if (radv_pipeline_has_ngg(pipeline))
2057 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
2058 else
2059 return &pipeline->gs_copy_shader->info.vs.outinfo;
2060 else if (radv_pipeline_has_tess(pipeline))
2061 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
2062 else
2063 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
2064 }
2065
2066 static void
2067 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
2068 {
2069 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
2070 int shader_count = 0;
2071
2072 if(shaders[MESA_SHADER_FRAGMENT]) {
2073 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
2074 }
2075 if(shaders[MESA_SHADER_GEOMETRY]) {
2076 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
2077 }
2078 if(shaders[MESA_SHADER_TESS_EVAL]) {
2079 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
2080 }
2081 if(shaders[MESA_SHADER_TESS_CTRL]) {
2082 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
2083 }
2084 if(shaders[MESA_SHADER_VERTEX]) {
2085 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
2086 }
2087
2088 if (shader_count > 1) {
2089 unsigned first = ordered_shaders[shader_count - 1]->info.stage;
2090 unsigned last = ordered_shaders[0]->info.stage;
2091
2092 if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
2093 ordered_shaders[1]->info.has_transform_feedback_varyings)
2094 nir_link_xfb_varyings(ordered_shaders[1], ordered_shaders[0]);
2095
2096 for (int i = 0; i < shader_count; ++i) {
2097 nir_variable_mode mask = 0;
2098
2099 if (ordered_shaders[i]->info.stage != first)
2100 mask = mask | nir_var_shader_in;
2101
2102 if (ordered_shaders[i]->info.stage != last)
2103 mask = mask | nir_var_shader_out;
2104
2105 nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
2106 radv_optimize_nir(ordered_shaders[i], false, false);
2107 }
2108 }
2109
2110 for (int i = 1; i < shader_count; ++i) {
2111 nir_lower_io_arrays_to_elements(ordered_shaders[i],
2112 ordered_shaders[i - 1]);
2113
2114 if (nir_link_opt_varyings(ordered_shaders[i],
2115 ordered_shaders[i - 1]))
2116 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2117
2118 nir_remove_dead_variables(ordered_shaders[i],
2119 nir_var_shader_out, NULL);
2120 nir_remove_dead_variables(ordered_shaders[i - 1],
2121 nir_var_shader_in, NULL);
2122
2123 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
2124 ordered_shaders[i - 1]);
2125
2126 nir_compact_varyings(ordered_shaders[i],
2127 ordered_shaders[i - 1], true);
2128
2129 if (progress) {
2130 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
2131 ac_lower_indirect_derefs(ordered_shaders[i],
2132 pipeline->device->physical_device->rad_info.chip_class);
2133 }
2134 radv_optimize_nir(ordered_shaders[i], false, false);
2135
2136 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
2137 ac_lower_indirect_derefs(ordered_shaders[i - 1],
2138 pipeline->device->physical_device->rad_info.chip_class);
2139 }
2140 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2141 }
2142 }
2143 }
2144
2145 static void
2146 radv_set_linked_driver_locations(struct radv_pipeline *pipeline, nir_shader **shaders,
2147 struct radv_shader_info infos[MESA_SHADER_STAGES])
2148 {
2149 bool has_tess = shaders[MESA_SHADER_TESS_CTRL];
2150 bool has_gs = shaders[MESA_SHADER_GEOMETRY];
2151
2152 if (!has_tess && !has_gs)
2153 return;
2154
2155 unsigned vs_info_idx = MESA_SHADER_VERTEX;
2156 unsigned tes_info_idx = MESA_SHADER_TESS_EVAL;
2157
2158 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2159 /* These are merged into the next stage */
2160 vs_info_idx = has_tess ? MESA_SHADER_TESS_CTRL : MESA_SHADER_GEOMETRY;
2161 tes_info_idx = has_gs ? MESA_SHADER_GEOMETRY : MESA_SHADER_TESS_EVAL;
2162 }
2163
2164 if (has_tess) {
2165 nir_linked_io_var_info vs2tcs =
2166 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_VERTEX], shaders[MESA_SHADER_TESS_CTRL]);
2167 nir_linked_io_var_info tcs2tes =
2168 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_TESS_CTRL], shaders[MESA_SHADER_TESS_EVAL]);
2169
2170 infos[vs_info_idx].vs.num_linked_outputs = vs2tcs.num_linked_io_vars;
2171 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_inputs = vs2tcs.num_linked_io_vars;
2172 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_outputs = tcs2tes.num_linked_io_vars;
2173 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_patch_outputs = tcs2tes.num_linked_patch_io_vars;
2174 infos[tes_info_idx].tes.num_linked_inputs = tcs2tes.num_linked_io_vars;
2175 infos[tes_info_idx].tes.num_linked_patch_inputs = tcs2tes.num_linked_patch_io_vars;
2176
2177 if (has_gs) {
2178 nir_linked_io_var_info tes2gs =
2179 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_TESS_EVAL], shaders[MESA_SHADER_GEOMETRY]);
2180
2181 infos[tes_info_idx].tes.num_linked_outputs = tes2gs.num_linked_io_vars;
2182 infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = tes2gs.num_linked_io_vars;
2183 }
2184 } else if (has_gs) {
2185 nir_linked_io_var_info vs2gs =
2186 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_VERTEX], shaders[MESA_SHADER_GEOMETRY]);
2187
2188 infos[vs_info_idx].vs.num_linked_outputs = vs2gs.num_linked_io_vars;
2189 infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = vs2gs.num_linked_io_vars;
2190 }
2191 }
2192
2193 static uint32_t
2194 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo *input_state,
2195 uint32_t attrib_binding)
2196 {
2197 for (uint32_t i = 0; i < input_state->vertexBindingDescriptionCount; i++) {
2198 const VkVertexInputBindingDescription *input_binding =
2199 &input_state->pVertexBindingDescriptions[i];
2200
2201 if (input_binding->binding == attrib_binding)
2202 return input_binding->stride;
2203 }
2204
2205 return 0;
2206 }
2207
2208 static struct radv_pipeline_key
2209 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
2210 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2211 const struct radv_blend_state *blend,
2212 bool has_view_index)
2213 {
2214 const VkPipelineVertexInputStateCreateInfo *input_state =
2215 pCreateInfo->pVertexInputState;
2216 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
2217 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
2218
2219 struct radv_pipeline_key key;
2220 memset(&key, 0, sizeof(key));
2221
2222 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
2223 key.optimisations_disabled = 1;
2224
2225 key.has_multiview_view_index = has_view_index;
2226
2227 uint32_t binding_input_rate = 0;
2228 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
2229 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
2230 if (input_state->pVertexBindingDescriptions[i].inputRate) {
2231 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
2232 binding_input_rate |= 1u << binding;
2233 instance_rate_divisors[binding] = 1;
2234 }
2235 }
2236 if (divisor_state) {
2237 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
2238 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
2239 divisor_state->pVertexBindingDivisors[i].divisor;
2240 }
2241 }
2242
2243 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
2244 const VkVertexInputAttributeDescription *desc =
2245 &input_state->pVertexAttributeDescriptions[i];
2246 const struct vk_format_description *format_desc;
2247 unsigned location = desc->location;
2248 unsigned binding = desc->binding;
2249 unsigned num_format, data_format;
2250 int first_non_void;
2251
2252 if (binding_input_rate & (1u << binding)) {
2253 key.instance_rate_inputs |= 1u << location;
2254 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
2255 }
2256
2257 format_desc = vk_format_description(desc->format);
2258 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2259
2260 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2261 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2262
2263 key.vertex_attribute_formats[location] = data_format | (num_format << 4);
2264 key.vertex_attribute_bindings[location] = desc->binding;
2265 key.vertex_attribute_offsets[location] = desc->offset;
2266 key.vertex_attribute_strides[location] = radv_get_attrib_stride(input_state, desc->binding);
2267
2268 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8 &&
2269 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
2270 VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
2271 uint64_t adjust;
2272 switch(format) {
2273 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2274 case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
2275 adjust = RADV_ALPHA_ADJUST_SNORM;
2276 break;
2277 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2278 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
2279 adjust = RADV_ALPHA_ADJUST_SSCALED;
2280 break;
2281 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2282 case VK_FORMAT_A2B10G10R10_SINT_PACK32:
2283 adjust = RADV_ALPHA_ADJUST_SINT;
2284 break;
2285 default:
2286 adjust = 0;
2287 break;
2288 }
2289 key.vertex_alpha_adjust |= adjust << (2 * location);
2290 }
2291
2292 switch (desc->format) {
2293 case VK_FORMAT_B8G8R8A8_UNORM:
2294 case VK_FORMAT_B8G8R8A8_SNORM:
2295 case VK_FORMAT_B8G8R8A8_USCALED:
2296 case VK_FORMAT_B8G8R8A8_SSCALED:
2297 case VK_FORMAT_B8G8R8A8_UINT:
2298 case VK_FORMAT_B8G8R8A8_SINT:
2299 case VK_FORMAT_B8G8R8A8_SRGB:
2300 case VK_FORMAT_A2R10G10B10_UNORM_PACK32:
2301 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2302 case VK_FORMAT_A2R10G10B10_USCALED_PACK32:
2303 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2304 case VK_FORMAT_A2R10G10B10_UINT_PACK32:
2305 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2306 key.vertex_post_shuffle |= 1 << location;
2307 break;
2308 default:
2309 break;
2310 }
2311 }
2312
2313 const VkPipelineTessellationStateCreateInfo *tess =
2314 radv_pipeline_get_tessellation_state(pCreateInfo);
2315 if (tess)
2316 key.tess_input_vertices = tess->patchControlPoints;
2317
2318 const VkPipelineMultisampleStateCreateInfo *vkms =
2319 radv_pipeline_get_multisample_state(pCreateInfo);
2320 if (vkms && vkms->rasterizationSamples > 1) {
2321 uint32_t num_samples = vkms->rasterizationSamples;
2322 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
2323 key.num_samples = num_samples;
2324 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
2325 }
2326
2327 key.col_format = blend->spi_shader_col_format;
2328 key.is_dual_src = blend->mrt0_is_dual_src;
2329 if (pipeline->device->physical_device->rad_info.chip_class < GFX8) {
2330 key.is_int8 = blend->col_format_is_int8;
2331 key.is_int10 = blend->col_format_is_int10;
2332 }
2333
2334 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10)
2335 key.topology = pCreateInfo->pInputAssemblyState->topology;
2336
2337 return key;
2338 }
2339
2340 static bool
2341 radv_nir_stage_uses_xfb(const nir_shader *nir)
2342 {
2343 nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
2344 bool uses_xfb = !!xfb;
2345
2346 ralloc_free(xfb);
2347 return uses_xfb;
2348 }
2349
2350 static void
2351 radv_fill_shader_keys(struct radv_device *device,
2352 struct radv_shader_variant_key *keys,
2353 const struct radv_pipeline_key *key,
2354 nir_shader **nir)
2355 {
2356 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
2357 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
2358 keys[MESA_SHADER_VERTEX].vs.post_shuffle = key->vertex_post_shuffle;
2359 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) {
2360 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
2361 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_formats[i] = key->vertex_attribute_formats[i];
2362 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_bindings[i] = key->vertex_attribute_bindings[i];
2363 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i];
2364 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i];
2365 }
2366 keys[MESA_SHADER_VERTEX].vs.outprim = si_conv_prim_to_gs_out(key->topology);
2367
2368 if (nir[MESA_SHADER_TESS_CTRL]) {
2369 keys[MESA_SHADER_VERTEX].vs_common_out.as_ls = true;
2370 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
2371 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
2372 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
2373
2374 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
2375 }
2376
2377 if (nir[MESA_SHADER_GEOMETRY]) {
2378 if (nir[MESA_SHADER_TESS_CTRL])
2379 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_es = true;
2380 else
2381 keys[MESA_SHADER_VERTEX].vs_common_out.as_es = true;
2382 }
2383
2384 if (device->physical_device->use_ngg) {
2385 if (nir[MESA_SHADER_TESS_CTRL]) {
2386 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = true;
2387 } else {
2388 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = true;
2389 }
2390
2391 if (nir[MESA_SHADER_TESS_CTRL] &&
2392 nir[MESA_SHADER_GEOMETRY] &&
2393 nir[MESA_SHADER_GEOMETRY]->info.gs.invocations *
2394 nir[MESA_SHADER_GEOMETRY]->info.gs.vertices_out > 256) {
2395 /* Fallback to the legacy path if tessellation is
2396 * enabled with extreme geometry because
2397 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2398 * might hang.
2399 */
2400 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2401 }
2402
2403 if (!device->physical_device->use_ngg_gs) {
2404 if (nir[MESA_SHADER_GEOMETRY]) {
2405 if (nir[MESA_SHADER_TESS_CTRL])
2406 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2407 else
2408 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2409 }
2410 }
2411
2412 gl_shader_stage last_xfb_stage = MESA_SHADER_VERTEX;
2413
2414 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
2415 if (nir[i])
2416 last_xfb_stage = i;
2417 }
2418
2419 bool uses_xfb = nir[last_xfb_stage] &&
2420 radv_nir_stage_uses_xfb(nir[last_xfb_stage]);
2421
2422 if (!device->physical_device->use_ngg_streamout && uses_xfb) {
2423 if (nir[MESA_SHADER_TESS_CTRL])
2424 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2425 else
2426 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2427 }
2428
2429 /* Determine if the pipeline is eligible for the NGG passthrough
2430 * mode. It can't be enabled for geometry shaders, for NGG
2431 * streamout or for vertex shaders that export the primitive ID
2432 * (this is checked later because we don't have the info here.)
2433 */
2434 if (!nir[MESA_SHADER_GEOMETRY] && !uses_xfb) {
2435 if (nir[MESA_SHADER_TESS_CTRL] &&
2436 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg) {
2437 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg_passthrough = true;
2438 } else if (nir[MESA_SHADER_VERTEX] &&
2439 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) {
2440 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = true;
2441 }
2442 }
2443 }
2444
2445 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
2446 keys[i].has_multiview_view_index = key->has_multiview_view_index;
2447
2448 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
2449 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
2450 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
2451 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
2452 keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples;
2453 keys[MESA_SHADER_FRAGMENT].fs.is_dual_src = key->is_dual_src;
2454
2455 if (nir[MESA_SHADER_COMPUTE]) {
2456 keys[MESA_SHADER_COMPUTE].cs.subgroup_size = key->compute_subgroup_size;
2457 }
2458 }
2459
2460 static uint8_t
2461 radv_get_wave_size(struct radv_device *device,
2462 const VkPipelineShaderStageCreateInfo *pStage,
2463 gl_shader_stage stage,
2464 const struct radv_shader_variant_key *key)
2465 {
2466 if (stage == MESA_SHADER_GEOMETRY && !key->vs_common_out.as_ngg)
2467 return 64;
2468 else if (stage == MESA_SHADER_COMPUTE) {
2469 if (key->cs.subgroup_size) {
2470 /* Return the required subgroup size if specified. */
2471 return key->cs.subgroup_size;
2472 }
2473 return device->physical_device->cs_wave_size;
2474 }
2475 else if (stage == MESA_SHADER_FRAGMENT)
2476 return device->physical_device->ps_wave_size;
2477 else
2478 return device->physical_device->ge_wave_size;
2479 }
2480
2481 static uint8_t
2482 radv_get_ballot_bit_size(struct radv_device *device,
2483 const VkPipelineShaderStageCreateInfo *pStage,
2484 gl_shader_stage stage,
2485 const struct radv_shader_variant_key *key)
2486 {
2487 if (stage == MESA_SHADER_COMPUTE && key->cs.subgroup_size)
2488 return key->cs.subgroup_size;
2489 return 64;
2490 }
2491
2492 static void
2493 radv_fill_shader_info(struct radv_pipeline *pipeline,
2494 const VkPipelineShaderStageCreateInfo **pStages,
2495 struct radv_shader_variant_key *keys,
2496 struct radv_shader_info *infos,
2497 nir_shader **nir)
2498 {
2499 unsigned active_stages = 0;
2500 unsigned filled_stages = 0;
2501
2502 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2503 if (nir[i])
2504 active_stages |= (1 << i);
2505 }
2506
2507 if (nir[MESA_SHADER_FRAGMENT]) {
2508 radv_nir_shader_info_init(&infos[MESA_SHADER_FRAGMENT]);
2509 radv_nir_shader_info_pass(nir[MESA_SHADER_FRAGMENT],
2510 pipeline->layout,
2511 &keys[MESA_SHADER_FRAGMENT],
2512 &infos[MESA_SHADER_FRAGMENT],
2513 pipeline->device->physical_device->use_llvm);
2514
2515 /* TODO: These are no longer used as keys we should refactor this */
2516 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2517 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2518 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2519 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2520 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2521 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2522 keys[MESA_SHADER_VERTEX].vs_common_out.export_viewport_index =
2523 infos[MESA_SHADER_FRAGMENT].ps.viewport_index_input;
2524 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2525 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2526 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2527 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2528 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2529 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2530 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_viewport_index =
2531 infos[MESA_SHADER_FRAGMENT].ps.viewport_index_input;
2532
2533 /* NGG passthrough mode can't be enabled for vertex shaders
2534 * that export the primitive ID.
2535 *
2536 * TODO: I should really refactor the keys logic.
2537 */
2538 if (nir[MESA_SHADER_VERTEX] &&
2539 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id) {
2540 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = false;
2541 }
2542
2543 filled_stages |= (1 << MESA_SHADER_FRAGMENT);
2544 }
2545
2546 if (nir[MESA_SHADER_TESS_CTRL]) {
2547 infos[MESA_SHADER_TESS_CTRL].tcs.tes_inputs_read =
2548 nir[MESA_SHADER_TESS_EVAL]->info.inputs_read;
2549 infos[MESA_SHADER_TESS_CTRL].tcs.tes_patch_inputs_read =
2550 nir[MESA_SHADER_TESS_EVAL]->info.patch_inputs_read;
2551 }
2552
2553 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2554 nir[MESA_SHADER_TESS_CTRL]) {
2555 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2556 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2557 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2558
2559 radv_nir_shader_info_init(&infos[MESA_SHADER_TESS_CTRL]);
2560
2561 for (int i = 0; i < 2; i++) {
2562 radv_nir_shader_info_pass(combined_nir[i],
2563 pipeline->layout, &key,
2564 &infos[MESA_SHADER_TESS_CTRL],
2565 pipeline->device->physical_device->use_llvm);
2566 }
2567
2568 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2569 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2570 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2571 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2572
2573 filled_stages |= (1 << MESA_SHADER_VERTEX);
2574 filled_stages |= (1 << MESA_SHADER_TESS_CTRL);
2575 }
2576
2577 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2578 nir[MESA_SHADER_GEOMETRY]) {
2579 gl_shader_stage pre_stage = nir[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2580 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2581
2582 radv_nir_shader_info_init(&infos[MESA_SHADER_GEOMETRY]);
2583
2584 for (int i = 0; i < 2; i++) {
2585 radv_nir_shader_info_pass(combined_nir[i],
2586 pipeline->layout,
2587 &keys[pre_stage],
2588 &infos[MESA_SHADER_GEOMETRY],
2589 pipeline->device->physical_device->use_llvm);
2590 }
2591
2592 filled_stages |= (1 << pre_stage);
2593 filled_stages |= (1 << MESA_SHADER_GEOMETRY);
2594 }
2595
2596 active_stages ^= filled_stages;
2597 while (active_stages) {
2598 int i = u_bit_scan(&active_stages);
2599
2600 if (i == MESA_SHADER_TESS_CTRL) {
2601 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs =
2602 util_last_bit64(infos[MESA_SHADER_VERTEX].vs.ls_outputs_written);
2603 }
2604
2605 if (i == MESA_SHADER_TESS_EVAL) {
2606 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2607 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2608 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2609 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2610 }
2611
2612 radv_nir_shader_info_init(&infos[i]);
2613 radv_nir_shader_info_pass(nir[i], pipeline->layout,
2614 &keys[i], &infos[i], pipeline->device->physical_device->use_llvm);
2615 }
2616
2617 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2618 if (nir[i]) {
2619 infos[i].wave_size =
2620 radv_get_wave_size(pipeline->device, pStages[i],
2621 i, &keys[i]);
2622 infos[i].ballot_bit_size =
2623 radv_get_ballot_bit_size(pipeline->device,
2624 pStages[i], i,
2625 &keys[i]);
2626 }
2627 }
2628 }
2629
2630 static void
2631 merge_tess_info(struct shader_info *tes_info,
2632 const struct shader_info *tcs_info)
2633 {
2634 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2635 *
2636 * "PointMode. Controls generation of points rather than triangles
2637 * or lines. This functionality defaults to disabled, and is
2638 * enabled if either shader stage includes the execution mode.
2639 *
2640 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2641 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2642 * and OutputVertices, it says:
2643 *
2644 * "One mode must be set in at least one of the tessellation
2645 * shader stages."
2646 *
2647 * So, the fields can be set in either the TCS or TES, but they must
2648 * agree if set in both. Our backend looks at TES, so bitwise-or in
2649 * the values from the TCS.
2650 */
2651 assert(tcs_info->tess.tcs_vertices_out == 0 ||
2652 tes_info->tess.tcs_vertices_out == 0 ||
2653 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
2654 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
2655
2656 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2657 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2658 tcs_info->tess.spacing == tes_info->tess.spacing);
2659 tes_info->tess.spacing |= tcs_info->tess.spacing;
2660
2661 assert(tcs_info->tess.primitive_mode == 0 ||
2662 tes_info->tess.primitive_mode == 0 ||
2663 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
2664 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
2665 tes_info->tess.ccw |= tcs_info->tess.ccw;
2666 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
2667 }
2668
2669 static
2670 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT *ext)
2671 {
2672 if (!ext)
2673 return;
2674
2675 if (ext->pPipelineCreationFeedback) {
2676 ext->pPipelineCreationFeedback->flags = 0;
2677 ext->pPipelineCreationFeedback->duration = 0;
2678 }
2679
2680 for (unsigned i = 0; i < ext->pipelineStageCreationFeedbackCount; ++i) {
2681 ext->pPipelineStageCreationFeedbacks[i].flags = 0;
2682 ext->pPipelineStageCreationFeedbacks[i].duration = 0;
2683 }
2684 }
2685
2686 static
2687 void radv_start_feedback(VkPipelineCreationFeedbackEXT *feedback)
2688 {
2689 if (!feedback)
2690 return;
2691
2692 feedback->duration -= radv_get_current_time();
2693 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT;
2694 }
2695
2696 static
2697 void radv_stop_feedback(VkPipelineCreationFeedbackEXT *feedback, bool cache_hit)
2698 {
2699 if (!feedback)
2700 return;
2701
2702 feedback->duration += radv_get_current_time();
2703 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT |
2704 (cache_hit ? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT : 0);
2705 }
2706
2707 VkResult radv_create_shaders(struct radv_pipeline *pipeline,
2708 struct radv_device *device,
2709 struct radv_pipeline_cache *cache,
2710 const struct radv_pipeline_key *key,
2711 const VkPipelineShaderStageCreateInfo **pStages,
2712 const VkPipelineCreateFlags flags,
2713 VkPipelineCreationFeedbackEXT *pipeline_feedback,
2714 VkPipelineCreationFeedbackEXT **stage_feedbacks)
2715 {
2716 struct radv_shader_module fs_m = {0};
2717 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2718 nir_shader *nir[MESA_SHADER_STAGES] = {0};
2719 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2720 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{{0}}}}};
2721 struct radv_shader_info infos[MESA_SHADER_STAGES] = {0};
2722 unsigned char hash[20], gs_copy_hash[20];
2723 bool keep_executable_info = (flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR) || device->keep_shader_info;
2724 bool keep_statistic_info = (flags & VK_PIPELINE_CREATE_CAPTURE_STATISTICS_BIT_KHR) ||
2725 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) ||
2726 device->keep_shader_info;
2727
2728 radv_start_feedback(pipeline_feedback);
2729
2730 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2731 if (pStages[i]) {
2732 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
2733 if (modules[i]->nir)
2734 _mesa_sha1_compute(modules[i]->nir->info.name,
2735 strlen(modules[i]->nir->info.name),
2736 modules[i]->sha1);
2737
2738 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
2739 }
2740 }
2741
2742 radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device));
2743 memcpy(gs_copy_hash, hash, 20);
2744 gs_copy_hash[0] ^= 1;
2745
2746 bool found_in_application_cache = true;
2747 if (modules[MESA_SHADER_GEOMETRY] && !keep_executable_info && !keep_statistic_info) {
2748 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2749 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants,
2750 &found_in_application_cache);
2751 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
2752 }
2753
2754 if (!keep_executable_info && !keep_statistic_info &&
2755 radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders,
2756 &found_in_application_cache) &&
2757 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
2758 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2759 return VK_SUCCESS;
2760 }
2761
2762 if (flags & VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_EXT) {
2763 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2764 return VK_PIPELINE_COMPILE_REQUIRED_EXT;
2765 }
2766
2767 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
2768 nir_builder fs_b;
2769 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2770 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2771 fs_m.nir = fs_b.shader;
2772 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2773 }
2774
2775 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2776 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
2777 unsigned subgroup_size = 64, ballot_bit_size = 64;
2778
2779 if (!modules[i])
2780 continue;
2781
2782 radv_start_feedback(stage_feedbacks[i]);
2783
2784 if (key->compute_subgroup_size) {
2785 /* Only compute shaders currently support requiring a
2786 * specific subgroup size.
2787 */
2788 assert(i == MESA_SHADER_COMPUTE);
2789 subgroup_size = key->compute_subgroup_size;
2790 ballot_bit_size = key->compute_subgroup_size;
2791 }
2792
2793 nir[i] = radv_shader_compile_to_nir(device, modules[i],
2794 stage ? stage->pName : "main", i,
2795 stage ? stage->pSpecializationInfo : NULL,
2796 flags, pipeline->layout,
2797 subgroup_size, ballot_bit_size);
2798
2799 /* We don't want to alter meta shaders IR directly so clone it
2800 * first.
2801 */
2802 if (nir[i]->info.name) {
2803 nir[i] = nir_shader_clone(NULL, nir[i]);
2804 }
2805
2806 radv_stop_feedback(stage_feedbacks[i], false);
2807 }
2808
2809 if (nir[MESA_SHADER_TESS_CTRL]) {
2810 nir_lower_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
2811 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
2812 }
2813
2814 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
2815 radv_link_shaders(pipeline, nir);
2816
2817 radv_set_linked_driver_locations(pipeline, nir, infos);
2818
2819 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2820 if (nir[i]) {
2821 /* do this again since information such as outputs_read can be out-of-date */
2822 nir_shader_gather_info(nir[i], nir_shader_get_entrypoint(nir[i]));
2823
2824 if (device->physical_device->use_llvm) {
2825 NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
2826 } else {
2827 NIR_PASS_V(nir[i], nir_lower_non_uniform_access,
2828 nir_lower_non_uniform_ubo_access |
2829 nir_lower_non_uniform_ssbo_access |
2830 nir_lower_non_uniform_texture_access |
2831 nir_lower_non_uniform_image_access);
2832 }
2833 }
2834 }
2835
2836 if (nir[MESA_SHADER_FRAGMENT])
2837 radv_lower_fs_io(nir[MESA_SHADER_FRAGMENT]);
2838
2839 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2840 if (radv_can_dump_shader(device, modules[i], false))
2841 nir_print_shader(nir[i], stderr);
2842 }
2843
2844 radv_fill_shader_keys(device, keys, key, nir);
2845
2846 radv_fill_shader_info(pipeline, pStages, keys, infos, nir);
2847
2848 if ((nir[MESA_SHADER_VERTEX] &&
2849 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) ||
2850 (nir[MESA_SHADER_TESS_EVAL] &&
2851 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg)) {
2852 struct gfx10_ngg_info *ngg_info;
2853
2854 if (nir[MESA_SHADER_GEOMETRY])
2855 ngg_info = &infos[MESA_SHADER_GEOMETRY].ngg_info;
2856 else if (nir[MESA_SHADER_TESS_CTRL])
2857 ngg_info = &infos[MESA_SHADER_TESS_EVAL].ngg_info;
2858 else
2859 ngg_info = &infos[MESA_SHADER_VERTEX].ngg_info;
2860
2861 gfx10_get_ngg_info(key, pipeline, nir, infos, ngg_info);
2862 } else if (nir[MESA_SHADER_GEOMETRY]) {
2863 struct gfx9_gs_info *gs_info =
2864 &infos[MESA_SHADER_GEOMETRY].gs_ring_info;
2865
2866 gfx9_get_gs_info(key, pipeline, nir, infos, gs_info);
2867 }
2868
2869 if(modules[MESA_SHADER_GEOMETRY]) {
2870 struct radv_shader_binary *gs_copy_binary = NULL;
2871 if (!pipeline->gs_copy_shader &&
2872 !radv_pipeline_has_ngg(pipeline)) {
2873 struct radv_shader_info info = {};
2874 struct radv_shader_variant_key key = {};
2875
2876 key.has_multiview_view_index =
2877 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index;
2878
2879 radv_nir_shader_info_pass(nir[MESA_SHADER_GEOMETRY],
2880 pipeline->layout, &key,
2881 &info, pipeline->device->physical_device->use_llvm);
2882 info.wave_size = 64; /* Wave32 not supported. */
2883 info.ballot_bit_size = 64;
2884
2885 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2886 device, nir[MESA_SHADER_GEOMETRY], &info,
2887 &gs_copy_binary, keep_executable_info, keep_statistic_info,
2888 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2889 }
2890
2891 if (!keep_executable_info && !keep_statistic_info && pipeline->gs_copy_shader) {
2892 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2893 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2894
2895 binaries[MESA_SHADER_GEOMETRY] = gs_copy_binary;
2896 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2897
2898 radv_pipeline_cache_insert_shaders(device, cache,
2899 gs_copy_hash,
2900 variants,
2901 binaries);
2902 }
2903 free(gs_copy_binary);
2904 }
2905
2906 if (nir[MESA_SHADER_FRAGMENT]) {
2907 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
2908 radv_start_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT]);
2909
2910 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2911 radv_shader_variant_compile(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
2912 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
2913 infos + MESA_SHADER_FRAGMENT,
2914 keep_executable_info, keep_statistic_info,
2915 &binaries[MESA_SHADER_FRAGMENT]);
2916
2917 radv_stop_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT], false);
2918 }
2919 }
2920
2921 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
2922 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
2923 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2924 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2925 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2926
2927 radv_start_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL]);
2928
2929 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
2930 pipeline->layout,
2931 &key, &infos[MESA_SHADER_TESS_CTRL], keep_executable_info,
2932 keep_statistic_info, &binaries[MESA_SHADER_TESS_CTRL]);
2933
2934 radv_stop_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL], false);
2935 }
2936 modules[MESA_SHADER_VERTEX] = NULL;
2937 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2938 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2939 }
2940
2941 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
2942 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2943 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
2944 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2945
2946 radv_start_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY]);
2947
2948 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2949 pipeline->layout,
2950 &keys[pre_stage], &infos[MESA_SHADER_GEOMETRY], keep_executable_info,
2951 keep_statistic_info, &binaries[MESA_SHADER_GEOMETRY]);
2952
2953 radv_stop_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY], false);
2954 }
2955 modules[pre_stage] = NULL;
2956 }
2957
2958 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2959 if(modules[i] && !pipeline->shaders[i]) {
2960 if (i == MESA_SHADER_TESS_CTRL) {
2961 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.ls_outputs_written);
2962 }
2963 if (i == MESA_SHADER_TESS_EVAL) {
2964 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2965 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2966 }
2967
2968 radv_start_feedback(stage_feedbacks[i]);
2969
2970 pipeline->shaders[i] = radv_shader_variant_compile(device, modules[i], &nir[i], 1,
2971 pipeline->layout,
2972 keys + i, infos + i, keep_executable_info,
2973 keep_statistic_info, &binaries[i]);
2974
2975 radv_stop_feedback(stage_feedbacks[i], false);
2976 }
2977 }
2978
2979 if (!keep_executable_info && !keep_statistic_info) {
2980 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
2981 binaries);
2982 }
2983
2984 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2985 free(binaries[i]);
2986 if (nir[i]) {
2987 ralloc_free(nir[i]);
2988
2989 if (radv_can_dump_shader_stats(device, modules[i]))
2990 radv_shader_dump_stats(device,
2991 pipeline->shaders[i],
2992 i, stderr);
2993 }
2994 }
2995
2996 if (fs_m.nir)
2997 ralloc_free(fs_m.nir);
2998
2999 radv_stop_feedback(pipeline_feedback, false);
3000 return VK_SUCCESS;
3001 }
3002
3003 static uint32_t
3004 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
3005 gl_shader_stage stage, enum chip_class chip_class)
3006 {
3007 bool has_gs = radv_pipeline_has_gs(pipeline);
3008 bool has_tess = radv_pipeline_has_tess(pipeline);
3009 bool has_ngg = radv_pipeline_has_ngg(pipeline);
3010
3011 switch (stage) {
3012 case MESA_SHADER_FRAGMENT:
3013 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
3014 case MESA_SHADER_VERTEX:
3015 if (has_tess) {
3016 if (chip_class >= GFX10) {
3017 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
3018 } else if (chip_class == GFX9) {
3019 return R_00B430_SPI_SHADER_USER_DATA_LS_0;
3020 } else {
3021 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
3022 }
3023
3024 }
3025
3026 if (has_gs) {
3027 if (chip_class >= GFX10) {
3028 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3029 } else {
3030 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
3031 }
3032 }
3033
3034 if (has_ngg)
3035 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3036
3037 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
3038 case MESA_SHADER_GEOMETRY:
3039 return chip_class == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
3040 R_00B230_SPI_SHADER_USER_DATA_GS_0;
3041 case MESA_SHADER_COMPUTE:
3042 return R_00B900_COMPUTE_USER_DATA_0;
3043 case MESA_SHADER_TESS_CTRL:
3044 return chip_class == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
3045 R_00B430_SPI_SHADER_USER_DATA_HS_0;
3046 case MESA_SHADER_TESS_EVAL:
3047 if (has_gs) {
3048 return chip_class >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0 :
3049 R_00B330_SPI_SHADER_USER_DATA_ES_0;
3050 } else if (has_ngg) {
3051 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3052 } else {
3053 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
3054 }
3055 default:
3056 unreachable("unknown shader");
3057 }
3058 }
3059
3060 struct radv_bin_size_entry {
3061 unsigned bpp;
3062 VkExtent2D extent;
3063 };
3064
3065 static VkExtent2D
3066 radv_gfx9_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3067 {
3068 static const struct radv_bin_size_entry color_size_table[][3][9] = {
3069 {
3070 /* One RB / SE */
3071 {
3072 /* One shader engine */
3073 { 0, {128, 128}},
3074 { 1, { 64, 128}},
3075 { 2, { 32, 128}},
3076 { 3, { 16, 128}},
3077 { 17, { 0, 0}},