projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
Revert "radv: add support for MRTs compaction to avoid holes"
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
33 #include "radv_cs.h"
34 #include "radv_shader.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
39 #include "vk_util.h"
40
41 #include "sid.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
48 #include "ac_shader_util.h"
49
50 struct radv_blend_state {
51 uint32_t blend_enable_4bit;
52 uint32_t need_src_alpha;
53
54 uint32_t cb_color_control;
55 uint32_t cb_target_mask;
56 uint32_t cb_target_enabled_4bit;
57 uint32_t sx_mrt_blend_opt[8];
58 uint32_t cb_blend_control[8];
59
60 uint32_t spi_shader_col_format;
61 uint32_t col_format_is_int8;
62 uint32_t col_format_is_int10;
63 uint32_t cb_shader_mask;
64 uint32_t db_alpha_to_mask;
65
66 uint32_t commutative_4bit;
67
68 bool single_cb_enable;
69 bool mrt0_is_dual_src;
70 };
71
72 struct radv_dsa_order_invariance {
73 /* Whether the final result in Z/S buffers is guaranteed to be
74 * invariant under changes to the order in which fragments arrive.
75 */
76 bool zs;
77
78 /* Whether the set of fragments that pass the combined Z/S test is
79 * guaranteed to be invariant under changes to the order in which
80 * fragments arrive.
81 */
82 bool pass_set;
83 };
84
85 struct radv_tessellation_state {
86 uint32_t ls_hs_config;
87 unsigned num_patches;
88 unsigned lds_size;
89 uint32_t tf_param;
90 };
91
92 static const VkPipelineMultisampleStateCreateInfo *
93 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
94 {
95 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
96 return pCreateInfo->pMultisampleState;
97 return NULL;
98 }
99
100 static const VkPipelineTessellationStateCreateInfo *
101 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
102 {
103 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
104 if (pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT ||
105 pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) {
106 return pCreateInfo->pTessellationState;
107 }
108 }
109 return NULL;
110 }
111
112 static const VkPipelineDepthStencilStateCreateInfo *
113 radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
114 {
115 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
116 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
117
118 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
119 subpass->depth_stencil_attachment)
120 return pCreateInfo->pDepthStencilState;
121 return NULL;
122 }
123
124 static const VkPipelineColorBlendStateCreateInfo *
125 radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
126 {
127 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
128 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
129
130 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
131 subpass->has_color_att)
132 return pCreateInfo->pColorBlendState;
133 return NULL;
134 }
135
136 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline)
137 {
138 struct radv_shader_variant *variant = NULL;
139 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
140 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
141 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
142 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
143 else if (pipeline->shaders[MESA_SHADER_VERTEX])
144 variant = pipeline->shaders[MESA_SHADER_VERTEX];
145 else
146 return false;
147 return variant->info.is_ngg;
148 }
149
150 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline *pipeline)
151 {
152 assert(radv_pipeline_has_ngg(pipeline));
153
154 struct radv_shader_variant *variant = NULL;
155 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
156 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
157 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
158 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
159 else if (pipeline->shaders[MESA_SHADER_VERTEX])
160 variant = pipeline->shaders[MESA_SHADER_VERTEX];
161 else
162 return false;
163 return variant->info.is_ngg_passthrough;
164 }
165
166 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline)
167 {
168 if (!radv_pipeline_has_gs(pipeline))
169 return false;
170
171 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
172 * On GFX10, it might be required in rare cases if it's not possible to
173 * enable NGG.
174 */
175 if (radv_pipeline_has_ngg(pipeline))
176 return false;
177
178 assert(pipeline->gs_copy_shader);
179 return true;
180 }
181
182 static void
183 radv_pipeline_destroy(struct radv_device *device,
184 struct radv_pipeline *pipeline,
185 const VkAllocationCallbacks* allocator)
186 {
187 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
188 if (pipeline->shaders[i])
189 radv_shader_variant_destroy(device, pipeline->shaders[i]);
190
191 if (pipeline->gs_copy_shader)
192 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
193
194 if(pipeline->cs.buf)
195 free(pipeline->cs.buf);
196
197 vk_object_base_finish(&pipeline->base);
198 vk_free2(&device->vk.alloc, allocator, pipeline);
199 }
200
201 void radv_DestroyPipeline(
202 VkDevice _device,
203 VkPipeline _pipeline,
204 const VkAllocationCallbacks* pAllocator)
205 {
206 RADV_FROM_HANDLE(radv_device, device, _device);
207 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
208
209 if (!_pipeline)
210 return;
211
212 radv_pipeline_destroy(device, pipeline, pAllocator);
213 }
214
215 static uint32_t get_hash_flags(struct radv_device *device)
216 {
217 uint32_t hash_flags = 0;
218
219 if (device->instance->debug_flags & RADV_DEBUG_NO_NGG)
220 hash_flags |= RADV_HASH_SHADER_NO_NGG;
221 if (device->physical_device->cs_wave_size == 32)
222 hash_flags |= RADV_HASH_SHADER_CS_WAVE32;
223 if (device->physical_device->ps_wave_size == 32)
224 hash_flags |= RADV_HASH_SHADER_PS_WAVE32;
225 if (device->physical_device->ge_wave_size == 32)
226 hash_flags |= RADV_HASH_SHADER_GE_WAVE32;
227 if (device->physical_device->use_llvm)
228 hash_flags |= RADV_HASH_SHADER_LLVM;
229 return hash_flags;
230 }
231
232 static VkResult
233 radv_pipeline_scratch_init(struct radv_device *device,
234 struct radv_pipeline *pipeline)
235 {
236 unsigned scratch_bytes_per_wave = 0;
237 unsigned max_waves = 0;
238 unsigned min_waves = 1;
239
240 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
241 if (pipeline->shaders[i] &&
242 pipeline->shaders[i]->config.scratch_bytes_per_wave) {
243 unsigned max_stage_waves = device->scratch_waves;
244
245 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
246 pipeline->shaders[i]->config.scratch_bytes_per_wave);
247
248 max_stage_waves = MIN2(max_stage_waves,
249 4 * device->physical_device->rad_info.num_good_compute_units *
250 (256 / pipeline->shaders[i]->config.num_vgprs));
251 max_waves = MAX2(max_waves, max_stage_waves);
252 }
253 }
254
255 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
256 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
257 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
258 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
259 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
260 }
261
262 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
263 pipeline->max_waves = max_waves;
264 return VK_SUCCESS;
265 }
266
267 static uint32_t si_translate_blend_logic_op(VkLogicOp op)
268 {
269 switch (op) {
270 case VK_LOGIC_OP_CLEAR:
271 return V_028808_ROP3_CLEAR;
272 case VK_LOGIC_OP_AND:
273 return V_028808_ROP3_AND;
274 case VK_LOGIC_OP_AND_REVERSE:
275 return V_028808_ROP3_AND_REVERSE;
276 case VK_LOGIC_OP_COPY:
277 return V_028808_ROP3_COPY;
278 case VK_LOGIC_OP_AND_INVERTED:
279 return V_028808_ROP3_AND_INVERTED;
280 case VK_LOGIC_OP_NO_OP:
281 return V_028808_ROP3_NO_OP;
282 case VK_LOGIC_OP_XOR:
283 return V_028808_ROP3_XOR;
284 case VK_LOGIC_OP_OR:
285 return V_028808_ROP3_OR;
286 case VK_LOGIC_OP_NOR:
287 return V_028808_ROP3_NOR;
288 case VK_LOGIC_OP_EQUIVALENT:
289 return V_028808_ROP3_EQUIVALENT;
290 case VK_LOGIC_OP_INVERT:
291 return V_028808_ROP3_INVERT;
292 case VK_LOGIC_OP_OR_REVERSE:
293 return V_028808_ROP3_OR_REVERSE;
294 case VK_LOGIC_OP_COPY_INVERTED:
295 return V_028808_ROP3_COPY_INVERTED;
296 case VK_LOGIC_OP_OR_INVERTED:
297 return V_028808_ROP3_OR_INVERTED;
298 case VK_LOGIC_OP_NAND:
299 return V_028808_ROP3_NAND;
300 case VK_LOGIC_OP_SET:
301 return V_028808_ROP3_SET;
302 default:
303 unreachable("Unhandled logic op");
304 }
305 }
306
307
308 static uint32_t si_translate_blend_function(VkBlendOp op)
309 {
310 switch (op) {
311 case VK_BLEND_OP_ADD:
312 return V_028780_COMB_DST_PLUS_SRC;
313 case VK_BLEND_OP_SUBTRACT:
314 return V_028780_COMB_SRC_MINUS_DST;
315 case VK_BLEND_OP_REVERSE_SUBTRACT:
316 return V_028780_COMB_DST_MINUS_SRC;
317 case VK_BLEND_OP_MIN:
318 return V_028780_COMB_MIN_DST_SRC;
319 case VK_BLEND_OP_MAX:
320 return V_028780_COMB_MAX_DST_SRC;
321 default:
322 return 0;
323 }
324 }
325
326 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
327 {
328 switch (factor) {
329 case VK_BLEND_FACTOR_ZERO:
330 return V_028780_BLEND_ZERO;
331 case VK_BLEND_FACTOR_ONE:
332 return V_028780_BLEND_ONE;
333 case VK_BLEND_FACTOR_SRC_COLOR:
334 return V_028780_BLEND_SRC_COLOR;
335 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
336 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
337 case VK_BLEND_FACTOR_DST_COLOR:
338 return V_028780_BLEND_DST_COLOR;
339 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
340 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
341 case VK_BLEND_FACTOR_SRC_ALPHA:
342 return V_028780_BLEND_SRC_ALPHA;
343 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
344 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
345 case VK_BLEND_FACTOR_DST_ALPHA:
346 return V_028780_BLEND_DST_ALPHA;
347 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
348 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
349 case VK_BLEND_FACTOR_CONSTANT_COLOR:
350 return V_028780_BLEND_CONSTANT_COLOR;
351 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
352 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
353 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
354 return V_028780_BLEND_CONSTANT_ALPHA;
355 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
356 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
357 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
358 return V_028780_BLEND_SRC_ALPHA_SATURATE;
359 case VK_BLEND_FACTOR_SRC1_COLOR:
360 return V_028780_BLEND_SRC1_COLOR;
361 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
362 return V_028780_BLEND_INV_SRC1_COLOR;
363 case VK_BLEND_FACTOR_SRC1_ALPHA:
364 return V_028780_BLEND_SRC1_ALPHA;
365 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
366 return V_028780_BLEND_INV_SRC1_ALPHA;
367 default:
368 return 0;
369 }
370 }
371
372 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
373 {
374 switch (op) {
375 case VK_BLEND_OP_ADD:
376 return V_028760_OPT_COMB_ADD;
377 case VK_BLEND_OP_SUBTRACT:
378 return V_028760_OPT_COMB_SUBTRACT;
379 case VK_BLEND_OP_REVERSE_SUBTRACT:
380 return V_028760_OPT_COMB_REVSUBTRACT;
381 case VK_BLEND_OP_MIN:
382 return V_028760_OPT_COMB_MIN;
383 case VK_BLEND_OP_MAX:
384 return V_028760_OPT_COMB_MAX;
385 default:
386 return V_028760_OPT_COMB_BLEND_DISABLED;
387 }
388 }
389
390 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
391 {
392 switch (factor) {
393 case VK_BLEND_FACTOR_ZERO:
394 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
395 case VK_BLEND_FACTOR_ONE:
396 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
397 case VK_BLEND_FACTOR_SRC_COLOR:
398 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
399 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
400 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
401 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
402 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
403 case VK_BLEND_FACTOR_SRC_ALPHA:
404 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
405 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
406 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
407 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
408 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
409 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
410 default:
411 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
412 }
413 }
414
415 /**
416 * Get rid of DST in the blend factors by commuting the operands:
417 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
418 */
419 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
420 unsigned *dst_factor, unsigned expected_dst,
421 unsigned replacement_src)
422 {
423 if (*src_factor == expected_dst &&
424 *dst_factor == VK_BLEND_FACTOR_ZERO) {
425 *src_factor = VK_BLEND_FACTOR_ZERO;
426 *dst_factor = replacement_src;
427
428 /* Commuting the operands requires reversing subtractions. */
429 if (*func == VK_BLEND_OP_SUBTRACT)
430 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
431 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
432 *func = VK_BLEND_OP_SUBTRACT;
433 }
434 }
435
436 static bool si_blend_factor_uses_dst(unsigned factor)
437 {
438 return factor == VK_BLEND_FACTOR_DST_COLOR ||
439 factor == VK_BLEND_FACTOR_DST_ALPHA ||
440 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
441 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
442 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
443 }
444
445 static bool is_dual_src(VkBlendFactor factor)
446 {
447 switch (factor) {
448 case VK_BLEND_FACTOR_SRC1_COLOR:
449 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
450 case VK_BLEND_FACTOR_SRC1_ALPHA:
451 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
452 return true;
453 default:
454 return false;
455 }
456 }
457
458 static unsigned radv_choose_spi_color_format(VkFormat vk_format,
459 bool blend_enable,
460 bool blend_need_alpha)
461 {
462 const struct vk_format_description *desc = vk_format_description(vk_format);
463 struct ac_spi_color_formats formats = {};
464 unsigned format, ntype, swap;
465
466 format = radv_translate_colorformat(vk_format);
467 ntype = radv_translate_color_numformat(vk_format, desc,
468 vk_format_get_first_non_void_channel(vk_format));
469 swap = radv_translate_colorswap(vk_format, false);
470
471 ac_choose_spi_color_formats(format, swap, ntype, false, &formats);
472
473 if (blend_enable && blend_need_alpha)
474 return formats.blend_alpha;
475 else if(blend_need_alpha)
476 return formats.alpha;
477 else if(blend_enable)
478 return formats.blend;
479 else
480 return formats.normal;
481 }
482
483 static bool
484 format_is_int8(VkFormat format)
485 {
486 const struct vk_format_description *desc = vk_format_description(format);
487 int channel = vk_format_get_first_non_void_channel(format);
488
489 return channel >= 0 && desc->channel[channel].pure_integer &&
490 desc->channel[channel].size == 8;
491 }
492
493 static bool
494 format_is_int10(VkFormat format)
495 {
496 const struct vk_format_description *desc = vk_format_description(format);
497
498 if (desc->nr_channels != 4)
499 return false;
500 for (unsigned i = 0; i < 4; i++) {
501 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
502 return true;
503 }
504 return false;
505 }
506
507 static void
508 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
509 const VkGraphicsPipelineCreateInfo *pCreateInfo,
510 struct radv_blend_state *blend)
511 {
512 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
513 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
514 unsigned col_format = 0, is_int8 = 0, is_int10 = 0;
515 unsigned num_targets;
516
517 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
518 unsigned cf;
519
520 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED ||
521 !(blend->cb_target_mask & (0xfu << (i * 4)))) {
522 cf = V_028714_SPI_SHADER_ZERO;
523 } else {
524 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
525 bool blend_enable =
526 blend->blend_enable_4bit & (0xfu << (i * 4));
527
528 cf = radv_choose_spi_color_format(attachment->format,
529 blend_enable,
530 blend->need_src_alpha & (1 << i));
531
532 if (format_is_int8(attachment->format))
533 is_int8 |= 1 << i;
534 if (format_is_int10(attachment->format))
535 is_int10 |= 1 << i;
536 }
537
538 col_format |= cf << (4 * i);
539 }
540
541 if (!(col_format & 0xf) && blend->need_src_alpha & (1 << 0)) {
542 /* When a subpass doesn't have any color attachments, write the
543 * alpha channel of MRT0 when alpha coverage is enabled because
544 * the depth attachment needs it.
545 */
546 col_format |= V_028714_SPI_SHADER_32_AR;
547 }
548
549 /* If the i-th target format is set, all previous target formats must
550 * be non-zero to avoid hangs.
551 */
552 num_targets = (util_last_bit(col_format) + 3) / 4;
553 for (unsigned i = 0; i < num_targets; i++) {
554 if (!(col_format & (0xf << (i * 4)))) {
555 col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
556 }
557 }
558
559 /* The output for dual source blending should have the same format as
560 * the first output.
561 */
562 if (blend->mrt0_is_dual_src)
563 col_format |= (col_format & 0xf) << 4;
564
565 blend->spi_shader_col_format = col_format;
566 blend->col_format_is_int8 = is_int8;
567 blend->col_format_is_int10 = is_int10;
568 }
569
570 /*
571 * Ordered so that for each i,
572 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
573 */
574 const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = {
575 VK_FORMAT_R32_SFLOAT,
576 VK_FORMAT_R32G32_SFLOAT,
577 VK_FORMAT_R8G8B8A8_UNORM,
578 VK_FORMAT_R16G16B16A16_UNORM,
579 VK_FORMAT_R16G16B16A16_SNORM,
580 VK_FORMAT_R16G16B16A16_UINT,
581 VK_FORMAT_R16G16B16A16_SINT,
582 VK_FORMAT_R32G32B32A32_SFLOAT,
583 VK_FORMAT_R8G8B8A8_UINT,
584 VK_FORMAT_R8G8B8A8_SINT,
585 VK_FORMAT_A2R10G10B10_UINT_PACK32,
586 VK_FORMAT_A2R10G10B10_SINT_PACK32,
587 };
588
589 unsigned radv_format_meta_fs_key(VkFormat format)
590 {
591 unsigned col_format = radv_choose_spi_color_format(format, false, false);
592
593 assert(col_format != V_028714_SPI_SHADER_32_AR);
594 if (col_format >= V_028714_SPI_SHADER_32_AR)
595 --col_format; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
596
597 --col_format; /* Skip V_028714_SPI_SHADER_ZERO */
598 bool is_int8 = format_is_int8(format);
599 bool is_int10 = format_is_int10(format);
600
601 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
602 }
603
604 static void
605 radv_blend_check_commutativity(struct radv_blend_state *blend,
606 VkBlendOp op, VkBlendFactor src,
607 VkBlendFactor dst, unsigned chanmask)
608 {
609 /* Src factor is allowed when it does not depend on Dst. */
610 static const uint32_t src_allowed =
611 (1u << VK_BLEND_FACTOR_ONE) |
612 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
613 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
614 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
615 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
616 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
617 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
618 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
619 (1u << VK_BLEND_FACTOR_ZERO) |
620 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
621 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
622 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
623 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
624 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
625 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
626
627 if (dst == VK_BLEND_FACTOR_ONE &&
628 (src_allowed & (1u << src))) {
629 /* Addition is commutative, but floating point addition isn't
630 * associative: subtle changes can be introduced via different
631 * rounding. Be conservative, only enable for min and max.
632 */
633 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
634 blend->commutative_4bit |= chanmask;
635 }
636 }
637
638 static struct radv_blend_state
639 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
640 const VkGraphicsPipelineCreateInfo *pCreateInfo,
641 const struct radv_graphics_pipeline_create_info *extra)
642 {
643 const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
644 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
645 struct radv_blend_state blend = {0};
646 unsigned mode = V_028808_CB_NORMAL;
647 int i;
648
649 if (extra && extra->custom_blend_mode) {
650 blend.single_cb_enable = true;
651 mode = extra->custom_blend_mode;
652 }
653
654 blend.cb_color_control = 0;
655 if (vkblend) {
656 if (vkblend->logicOpEnable)
657 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
658 else
659 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
660 }
661
662 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
663 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
664 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
665 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
666 S_028B70_OFFSET_ROUND(1);
667
668 if (vkms && vkms->alphaToCoverageEnable) {
669 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
670 blend.need_src_alpha |= 0x1;
671 }
672
673 blend.cb_target_mask = 0;
674 if (vkblend) {
675 for (i = 0; i < vkblend->attachmentCount; i++) {
676 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
677 unsigned blend_cntl = 0;
678 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
679 VkBlendOp eqRGB = att->colorBlendOp;
680 VkBlendFactor srcRGB = att->srcColorBlendFactor;
681 VkBlendFactor dstRGB = att->dstColorBlendFactor;
682 VkBlendOp eqA = att->alphaBlendOp;
683 VkBlendFactor srcA = att->srcAlphaBlendFactor;
684 VkBlendFactor dstA = att->dstAlphaBlendFactor;
685
686 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
687
688 if (!att->colorWriteMask)
689 continue;
690
691 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
692 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
693 if (!att->blendEnable) {
694 blend.cb_blend_control[i] = blend_cntl;
695 continue;
696 }
697
698 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
699 if (i == 0)
700 blend.mrt0_is_dual_src = true;
701
702 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
703 srcRGB = VK_BLEND_FACTOR_ONE;
704 dstRGB = VK_BLEND_FACTOR_ONE;
705 }
706 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
707 srcA = VK_BLEND_FACTOR_ONE;
708 dstA = VK_BLEND_FACTOR_ONE;
709 }
710
711 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
712 0x7 << (4 * i));
713 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
714 0x8 << (4 * i));
715
716 /* Blending optimizations for RB+.
717 * These transformations don't change the behavior.
718 *
719 * First, get rid of DST in the blend factors:
720 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
721 */
722 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
723 VK_BLEND_FACTOR_DST_COLOR,
724 VK_BLEND_FACTOR_SRC_COLOR);
725
726 si_blend_remove_dst(&eqA, &srcA, &dstA,
727 VK_BLEND_FACTOR_DST_COLOR,
728 VK_BLEND_FACTOR_SRC_COLOR);
729
730 si_blend_remove_dst(&eqA, &srcA, &dstA,
731 VK_BLEND_FACTOR_DST_ALPHA,
732 VK_BLEND_FACTOR_SRC_ALPHA);
733
734 /* Look up the ideal settings from tables. */
735 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
736 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
737 srcA_opt = si_translate_blend_opt_factor(srcA, true);
738 dstA_opt = si_translate_blend_opt_factor(dstA, true);
739
740 /* Handle interdependencies. */
741 if (si_blend_factor_uses_dst(srcRGB))
742 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
743 if (si_blend_factor_uses_dst(srcA))
744 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
745
746 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
747 (dstRGB == VK_BLEND_FACTOR_ZERO ||
748 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
749 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
750 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
751
752 /* Set the final value. */
753 blend.sx_mrt_blend_opt[i] =
754 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
755 S_028760_COLOR_DST_OPT(dstRGB_opt) |
756 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
757 S_028760_ALPHA_SRC_OPT(srcA_opt) |
758 S_028760_ALPHA_DST_OPT(dstA_opt) |
759 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
760 blend_cntl |= S_028780_ENABLE(1);
761
762 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
763 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
764 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
765 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
766 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
767 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
768 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
769 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
770 }
771 blend.cb_blend_control[i] = blend_cntl;
772
773 blend.blend_enable_4bit |= 0xfu << (i * 4);
774
775 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
776 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
777 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
778 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
779 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
780 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
781 blend.need_src_alpha |= 1 << i;
782 }
783 for (i = vkblend->attachmentCount; i < 8; i++) {
784 blend.cb_blend_control[i] = 0;
785 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
786 }
787 }
788
789 if (pipeline->device->physical_device->rad_info.has_rbplus) {
790 /* Disable RB+ blend optimizations for dual source blending. */
791 if (blend.mrt0_is_dual_src) {
792 for (i = 0; i < 8; i++) {
793 blend.sx_mrt_blend_opt[i] =
794 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
795 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
796 }
797 }
798
799 /* RB+ doesn't work with dual source blending, logic op and
800 * RESOLVE.
801 */
802 if (blend.mrt0_is_dual_src ||
803 (vkblend && vkblend->logicOpEnable) ||
804 mode == V_028808_CB_RESOLVE)
805 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
806 }
807
808 if (blend.cb_target_mask)
809 blend.cb_color_control |= S_028808_MODE(mode);
810 else
811 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
812
813 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
814 return blend;
815 }
816
817 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
818 {
819 switch (op) {
820 case VK_STENCIL_OP_KEEP:
821 return V_02842C_STENCIL_KEEP;
822 case VK_STENCIL_OP_ZERO:
823 return V_02842C_STENCIL_ZERO;
824 case VK_STENCIL_OP_REPLACE:
825 return V_02842C_STENCIL_REPLACE_TEST;
826 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
827 return V_02842C_STENCIL_ADD_CLAMP;
828 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
829 return V_02842C_STENCIL_SUB_CLAMP;
830 case VK_STENCIL_OP_INVERT:
831 return V_02842C_STENCIL_INVERT;
832 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
833 return V_02842C_STENCIL_ADD_WRAP;
834 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
835 return V_02842C_STENCIL_SUB_WRAP;
836 default:
837 return 0;
838 }
839 }
840
841 static uint32_t si_translate_fill(VkPolygonMode func)
842 {
843 switch(func) {
844 case VK_POLYGON_MODE_FILL:
845 return V_028814_X_DRAW_TRIANGLES;
846 case VK_POLYGON_MODE_LINE:
847 return V_028814_X_DRAW_LINES;
848 case VK_POLYGON_MODE_POINT:
849 return V_028814_X_DRAW_POINTS;
850 default:
851 assert(0);
852 return V_028814_X_DRAW_POINTS;
853 }
854 }
855
856 static uint8_t radv_pipeline_get_ps_iter_samples(const VkGraphicsPipelineCreateInfo *pCreateInfo)
857 {
858 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
859 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
860 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
861 uint32_t ps_iter_samples = 1;
862 uint32_t num_samples;
863
864 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
865 *
866 * "If the VK_AMD_mixed_attachment_samples extension is enabled and the
867 * subpass uses color attachments, totalSamples is the number of
868 * samples of the color attachments. Otherwise, totalSamples is the
869 * value of VkPipelineMultisampleStateCreateInfo::rasterizationSamples
870 * specified at pipeline creation time."
871 */
872 if (subpass->has_color_att) {
873 num_samples = subpass->color_sample_count;
874 } else {
875 num_samples = vkms->rasterizationSamples;
876 }
877
878 if (vkms->sampleShadingEnable) {
879 ps_iter_samples = ceilf(vkms->minSampleShading * num_samples);
880 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
881 }
882 return ps_iter_samples;
883 }
884
885 static bool
886 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
887 {
888 return pCreateInfo->depthTestEnable &&
889 pCreateInfo->depthWriteEnable &&
890 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
891 }
892
893 static bool
894 radv_writes_stencil(const VkStencilOpState *state)
895 {
896 return state->writeMask &&
897 (state->failOp != VK_STENCIL_OP_KEEP ||
898 state->passOp != VK_STENCIL_OP_KEEP ||
899 state->depthFailOp != VK_STENCIL_OP_KEEP);
900 }
901
902 static bool
903 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
904 {
905 return pCreateInfo->stencilTestEnable &&
906 (radv_writes_stencil(&pCreateInfo->front) ||
907 radv_writes_stencil(&pCreateInfo->back));
908 }
909
910 static bool
911 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
912 {
913 return radv_is_depth_write_enabled(pCreateInfo) ||
914 radv_is_stencil_write_enabled(pCreateInfo);
915 }
916
917 static bool
918 radv_order_invariant_stencil_op(VkStencilOp op)
919 {
920 /* REPLACE is normally order invariant, except when the stencil
921 * reference value is written by the fragment shader. Tracking this
922 * interaction does not seem worth the effort, so be conservative.
923 */
924 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
925 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
926 op != VK_STENCIL_OP_REPLACE;
927 }
928
929 static bool
930 radv_order_invariant_stencil_state(const VkStencilOpState *state)
931 {
932 /* Compute whether, assuming Z writes are disabled, this stencil state
933 * is order invariant in the sense that the set of passing fragments as
934 * well as the final stencil buffer result does not depend on the order
935 * of fragments.
936 */
937 return !state->writeMask ||
938 /* The following assumes that Z writes are disabled. */
939 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
940 radv_order_invariant_stencil_op(state->passOp) &&
941 radv_order_invariant_stencil_op(state->depthFailOp)) ||
942 (state->compareOp == VK_COMPARE_OP_NEVER &&
943 radv_order_invariant_stencil_op(state->failOp));
944 }
945
946 static bool
947 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
948 struct radv_blend_state *blend,
949 const VkGraphicsPipelineCreateInfo *pCreateInfo)
950 {
951 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
952 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
953 const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
954 const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
955 unsigned colormask = blend->cb_target_enabled_4bit;
956
957 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
958 return false;
959
960 /* Be conservative if a logic operation is enabled with color buffers. */
961 if (colormask && vkblend && vkblend->logicOpEnable)
962 return false;
963
964 /* Default depth/stencil invariance when no attachment is bound. */
965 struct radv_dsa_order_invariance dsa_order_invariant = {
966 .zs = true, .pass_set = true
967 };
968
969 if (vkds) {
970 struct radv_render_pass_attachment *attachment =
971 pass->attachments + subpass->depth_stencil_attachment->attachment;
972 bool has_stencil = vk_format_is_stencil(attachment->format);
973 struct radv_dsa_order_invariance order_invariance[2];
974 struct radv_shader_variant *ps =
975 pipeline->shaders[MESA_SHADER_FRAGMENT];
976
977 /* Compute depth/stencil order invariance in order to know if
978 * it's safe to enable out-of-order.
979 */
980 bool zfunc_is_ordered =
981 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
982 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
983 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
984 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
985 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
986
987 bool nozwrite_and_order_invariant_stencil =
988 !radv_is_ds_write_enabled(vkds) ||
989 (!radv_is_depth_write_enabled(vkds) &&
990 radv_order_invariant_stencil_state(&vkds->front) &&
991 radv_order_invariant_stencil_state(&vkds->back));
992
993 order_invariance[1].zs =
994 nozwrite_and_order_invariant_stencil ||
995 (!radv_is_stencil_write_enabled(vkds) &&
996 zfunc_is_ordered);
997 order_invariance[0].zs =
998 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
999
1000 order_invariance[1].pass_set =
1001 nozwrite_and_order_invariant_stencil ||
1002 (!radv_is_stencil_write_enabled(vkds) &&
1003 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1004 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
1005 order_invariance[0].pass_set =
1006 !radv_is_depth_write_enabled(vkds) ||
1007 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1008 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
1009
1010 dsa_order_invariant = order_invariance[has_stencil];
1011 if (!dsa_order_invariant.zs)
1012 return false;
1013
1014 /* The set of PS invocations is always order invariant,
1015 * except when early Z/S tests are requested.
1016 */
1017 if (ps &&
1018 ps->info.ps.writes_memory &&
1019 ps->info.ps.early_fragment_test &&
1020 !dsa_order_invariant.pass_set)
1021 return false;
1022
1023 /* Determine if out-of-order rasterization should be disabled
1024 * when occlusion queries are used.
1025 */
1026 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
1027 !dsa_order_invariant.pass_set;
1028 }
1029
1030 /* No color buffers are enabled for writing. */
1031 if (!colormask)
1032 return true;
1033
1034 unsigned blendmask = colormask & blend->blend_enable_4bit;
1035
1036 if (blendmask) {
1037 /* Only commutative blending. */
1038 if (blendmask & ~blend->commutative_4bit)
1039 return false;
1040
1041 if (!dsa_order_invariant.pass_set)
1042 return false;
1043 }
1044
1045 if (colormask & ~blendmask)
1046 return false;
1047
1048 return true;
1049 }
1050
1051 static void
1052 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1053 struct radv_blend_state *blend,
1054 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1055 {
1056 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
1057 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1058 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1059 bool out_of_order_rast = false;
1060 int ps_iter_samples = 1;
1061 uint32_t mask = 0xffff;
1062
1063 if (vkms) {
1064 ms->num_samples = vkms->rasterizationSamples;
1065
1066 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1067 *
1068 * "Sample shading is enabled for a graphics pipeline:
1069 *
1070 * - If the interface of the fragment shader entry point of the
1071 * graphics pipeline includes an input variable decorated
1072 * with SampleId or SamplePosition. In this case
1073 * minSampleShadingFactor takes the value 1.0.
1074 * - Else if the sampleShadingEnable member of the
1075 * VkPipelineMultisampleStateCreateInfo structure specified
1076 * when creating the graphics pipeline is set to VK_TRUE. In
1077 * this case minSampleShadingFactor takes the value of
1078 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1079 *
1080 * Otherwise, sample shading is considered disabled."
1081 */
1082 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.force_persample) {
1083 ps_iter_samples = ms->num_samples;
1084 } else {
1085 ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
1086 }
1087 } else {
1088 ms->num_samples = 1;
1089 }
1090
1091 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1092 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1093 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1094 /* Out-of-order rasterization is explicitly enabled by the
1095 * application.
1096 */
1097 out_of_order_rast = true;
1098 } else {
1099 /* Determine if the driver can enable out-of-order
1100 * rasterization internally.
1101 */
1102 out_of_order_rast =
1103 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1104 }
1105
1106 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1107 ms->pa_sc_aa_config = 0;
1108 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1109 S_028804_INCOHERENT_EQAA_READS(1) |
1110 S_028804_INTERPOLATE_COMP_Z(1) |
1111 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1112 ms->pa_sc_mode_cntl_1 =
1113 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1114 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1115 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
1116 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1117 /* always 1: */
1118 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1119 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1120 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1121 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1122 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1123 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1124 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1125 S_028A48_VPORT_SCISSOR_ENABLE(1);
1126
1127 const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line =
1128 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1129 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
1130 if (rast_line) {
1131 ms->pa_sc_mode_cntl_0 |= S_028A48_LINE_STIPPLE_ENABLE(rast_line->stippledLineEnable);
1132 if (rast_line->lineRasterizationMode == VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT) {
1133 /* From the Vulkan spec 1.1.129:
1134 *
1135 * "When VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT lines
1136 * are being rasterized, sample locations may all be
1137 * treated as being at the pixel center (this may
1138 * affect attribute and depth interpolation)."
1139 */
1140 ms->num_samples = 1;
1141 }
1142 }
1143
1144 if (ms->num_samples > 1) {
1145 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1146 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1147 uint32_t z_samples = subpass->depth_stencil_attachment ? subpass->depth_sample_count : ms->num_samples;
1148 unsigned log_samples = util_logbase2(ms->num_samples);
1149 unsigned log_z_samples = util_logbase2(z_samples);
1150 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1151 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1152 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
1153 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1154 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1155 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1156 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1157 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) |
1158 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples) | /* CM_R_028BE0_PA_SC_AA_CONFIG */
1159 S_028BE0_COVERED_CENTROID_IS_CENTER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3);
1160 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1161 if (ps_iter_samples > 1)
1162 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1163 }
1164
1165 if (vkms && vkms->pSampleMask) {
1166 mask = vkms->pSampleMask[0] & 0xffff;
1167 }
1168
1169 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1170 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1171 }
1172
1173 static bool
1174 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1175 {
1176 switch (topology) {
1177 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1178 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1179 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1180 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1181 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1182 return false;
1183 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1184 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1185 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1186 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1187 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1188 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1189 return true;
1190 default:
1191 unreachable("unhandled primitive type");
1192 }
1193 }
1194
1195 static uint32_t
1196 si_translate_prim(enum VkPrimitiveTopology topology)
1197 {
1198 switch (topology) {
1199 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1200 return V_008958_DI_PT_POINTLIST;
1201 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1202 return V_008958_DI_PT_LINELIST;
1203 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1204 return V_008958_DI_PT_LINESTRIP;
1205 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1206 return V_008958_DI_PT_TRILIST;
1207 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1208 return V_008958_DI_PT_TRISTRIP;
1209 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1210 return V_008958_DI_PT_TRIFAN;
1211 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1212 return V_008958_DI_PT_LINELIST_ADJ;
1213 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1214 return V_008958_DI_PT_LINESTRIP_ADJ;
1215 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1216 return V_008958_DI_PT_TRILIST_ADJ;
1217 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1218 return V_008958_DI_PT_TRISTRIP_ADJ;
1219 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1220 return V_008958_DI_PT_PATCH;
1221 default:
1222 assert(0);
1223 return 0;
1224 }
1225 }
1226
1227 static uint32_t
1228 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1229 {
1230 switch (gl_prim) {
1231 case 0: /* GL_POINTS */
1232 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1233 case 1: /* GL_LINES */
1234 case 3: /* GL_LINE_STRIP */
1235 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1236 case 0x8E7A: /* GL_ISOLINES */
1237 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1238
1239 case 4: /* GL_TRIANGLES */
1240 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1241 case 5: /* GL_TRIANGLE_STRIP */
1242 case 7: /* GL_QUADS */
1243 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1244 default:
1245 assert(0);
1246 return 0;
1247 }
1248 }
1249
1250 static uint32_t
1251 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1252 {
1253 switch (topology) {
1254 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1255 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1256 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1257 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1258 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1259 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1260 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1261 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1262 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1263 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1264 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1265 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1266 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1267 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1268 default:
1269 assert(0);
1270 return 0;
1271 }
1272 }
1273
1274 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1275 {
1276 switch(state) {
1277 case VK_DYNAMIC_STATE_VIEWPORT:
1278 return RADV_DYNAMIC_VIEWPORT;
1279 case VK_DYNAMIC_STATE_SCISSOR:
1280 return RADV_DYNAMIC_SCISSOR;
1281 case VK_DYNAMIC_STATE_LINE_WIDTH:
1282 return RADV_DYNAMIC_LINE_WIDTH;
1283 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1284 return RADV_DYNAMIC_DEPTH_BIAS;
1285 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1286 return RADV_DYNAMIC_BLEND_CONSTANTS;
1287 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1288 return RADV_DYNAMIC_DEPTH_BOUNDS;
1289 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1290 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1291 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1292 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1293 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1294 return RADV_DYNAMIC_STENCIL_REFERENCE;
1295 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1296 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1297 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
1298 return RADV_DYNAMIC_SAMPLE_LOCATIONS;
1299 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT:
1300 return RADV_DYNAMIC_LINE_STIPPLE;
1301 default:
1302 unreachable("Unhandled dynamic state");
1303 }
1304 }
1305
1306 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1307 {
1308 uint32_t states = RADV_DYNAMIC_ALL;
1309
1310 /* If rasterization is disabled we do not care about any of the dynamic states,
1311 * since they are all rasterization related only. */
1312 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1313 return 0;
1314
1315 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1316 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1317
1318 if (!pCreateInfo->pDepthStencilState ||
1319 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1320 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1321
1322 if (!pCreateInfo->pDepthStencilState ||
1323 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1324 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1325 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1326 RADV_DYNAMIC_STENCIL_REFERENCE);
1327
1328 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1329 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1330
1331 if (!pCreateInfo->pMultisampleState ||
1332 !vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1333 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT))
1334 states &= ~RADV_DYNAMIC_SAMPLE_LOCATIONS;
1335
1336 if (!pCreateInfo->pRasterizationState ||
1337 !vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1338 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT))
1339 states &= ~RADV_DYNAMIC_LINE_STIPPLE;
1340
1341 /* TODO: blend constants & line width. */
1342
1343 return states;
1344 }
1345
1346
1347 static void
1348 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1349 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1350 {
1351 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1352 uint32_t states = needed_states;
1353 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1354 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1355
1356 pipeline->dynamic_state = default_dynamic_state;
1357 pipeline->graphics.needed_dynamic_state = needed_states;
1358
1359 if (pCreateInfo->pDynamicState) {
1360 /* Remove all of the states that are marked as dynamic */
1361 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1362 for (uint32_t s = 0; s < count; s++)
1363 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1364 }
1365
1366 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1367
1368 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1369 assert(pCreateInfo->pViewportState);
1370
1371 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1372 if (states & RADV_DYNAMIC_VIEWPORT) {
1373 typed_memcpy(dynamic->viewport.viewports,
1374 pCreateInfo->pViewportState->pViewports,
1375 pCreateInfo->pViewportState->viewportCount);
1376 }
1377 }
1378
1379 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1380 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1381 if (states & RADV_DYNAMIC_SCISSOR) {
1382 typed_memcpy(dynamic->scissor.scissors,
1383 pCreateInfo->pViewportState->pScissors,
1384 pCreateInfo->pViewportState->scissorCount);
1385 }
1386 }
1387
1388 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1389 assert(pCreateInfo->pRasterizationState);
1390 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1391 }
1392
1393 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1394 assert(pCreateInfo->pRasterizationState);
1395 dynamic->depth_bias.bias =
1396 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1397 dynamic->depth_bias.clamp =
1398 pCreateInfo->pRasterizationState->depthBiasClamp;
1399 dynamic->depth_bias.slope =
1400 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1401 }
1402
1403 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1404 *
1405 * pColorBlendState is [...] NULL if the pipeline has rasterization
1406 * disabled or if the subpass of the render pass the pipeline is
1407 * created against does not use any color attachments.
1408 */
1409 if (subpass->has_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1410 assert(pCreateInfo->pColorBlendState);
1411 typed_memcpy(dynamic->blend_constants,
1412 pCreateInfo->pColorBlendState->blendConstants, 4);
1413 }
1414
1415 /* If there is no depthstencil attachment, then don't read
1416 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1417 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1418 * no need to override the depthstencil defaults in
1419 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1420 *
1421 * Section 9.2 of the Vulkan 1.0.15 spec says:
1422 *
1423 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1424 * disabled or if the subpass of the render pass the pipeline is created
1425 * against does not use a depth/stencil attachment.
1426 */
1427 if (needed_states && subpass->depth_stencil_attachment) {
1428 assert(pCreateInfo->pDepthStencilState);
1429
1430 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1431 dynamic->depth_bounds.min =
1432 pCreateInfo->pDepthStencilState->minDepthBounds;
1433 dynamic->depth_bounds.max =
1434 pCreateInfo->pDepthStencilState->maxDepthBounds;
1435 }
1436
1437 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1438 dynamic->stencil_compare_mask.front =
1439 pCreateInfo->pDepthStencilState->front.compareMask;
1440 dynamic->stencil_compare_mask.back =
1441 pCreateInfo->pDepthStencilState->back.compareMask;
1442 }
1443
1444 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1445 dynamic->stencil_write_mask.front =
1446 pCreateInfo->pDepthStencilState->front.writeMask;
1447 dynamic->stencil_write_mask.back =
1448 pCreateInfo->pDepthStencilState->back.writeMask;
1449 }
1450
1451 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1452 dynamic->stencil_reference.front =
1453 pCreateInfo->pDepthStencilState->front.reference;
1454 dynamic->stencil_reference.back =
1455 pCreateInfo->pDepthStencilState->back.reference;
1456 }
1457 }
1458
1459 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1460 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1461 if (needed_states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1462 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1463 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1464 typed_memcpy(dynamic->discard_rectangle.rectangles,
1465 discard_rectangle_info->pDiscardRectangles,
1466 discard_rectangle_info->discardRectangleCount);
1467 }
1468 }
1469
1470 if (needed_states & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
1471 const VkPipelineSampleLocationsStateCreateInfoEXT *sample_location_info =
1472 vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1473 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1474 /* If sampleLocationsEnable is VK_FALSE, the default sample
1475 * locations are used and the values specified in
1476 * sampleLocationsInfo are ignored.
1477 */
1478 if (sample_location_info->sampleLocationsEnable) {
1479 const VkSampleLocationsInfoEXT *pSampleLocationsInfo =
1480 &sample_location_info->sampleLocationsInfo;
1481
1482 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
1483
1484 dynamic->sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
1485 dynamic->sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
1486 dynamic->sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
1487 typed_memcpy(&dynamic->sample_location.locations[0],
1488 pSampleLocationsInfo->pSampleLocations,
1489 pSampleLocationsInfo->sampleLocationsCount);
1490 }
1491 }
1492
1493 const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line_info =
1494 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1495 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
1496 if (needed_states & RADV_DYNAMIC_LINE_STIPPLE) {
1497 dynamic->line_stipple.factor = rast_line_info->lineStippleFactor;
1498 dynamic->line_stipple.pattern = rast_line_info->lineStipplePattern;
1499 }
1500
1501 pipeline->dynamic_state.mask = states;
1502 }
1503
1504 static void
1505 gfx9_get_gs_info(const struct radv_pipeline_key *key,
1506 const struct radv_pipeline *pipeline,
1507 nir_shader **nir,
1508 struct radv_shader_info *infos,
1509 struct gfx9_gs_info *out)
1510 {
1511 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1512 struct radv_es_output_info *es_info;
1513 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1514 es_info = nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1515 else
1516 es_info = nir[MESA_SHADER_TESS_CTRL] ?
1517 &infos[MESA_SHADER_TESS_EVAL].tes.es_info :
1518 &infos[MESA_SHADER_VERTEX].vs.es_info;
1519
1520 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1521 bool uses_adjacency;
1522 switch(key->topology) {
1523 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1524 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1525 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1526 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1527 uses_adjacency = true;
1528 break;
1529 default:
1530 uses_adjacency = false;
1531 break;
1532 }
1533
1534 /* All these are in dwords: */
1535 /* We can't allow using the whole LDS, because GS waves compete with
1536 * other shader stages for LDS space. */
1537 const unsigned max_lds_size = 8 * 1024;
1538 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1539 unsigned esgs_lds_size;
1540
1541 /* All these are per subgroup: */
1542 const unsigned max_out_prims = 32 * 1024;
1543 const unsigned max_es_verts = 255;
1544 const unsigned ideal_gs_prims = 64;
1545 unsigned max_gs_prims, gs_prims;
1546 unsigned min_es_verts, es_verts, worst_case_es_verts;
1547
1548 if (uses_adjacency || gs_num_invocations > 1)
1549 max_gs_prims = 127 / gs_num_invocations;
1550 else
1551 max_gs_prims = 255;
1552
1553 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1554 * Make sure we don't go over the maximum value.
1555 */
1556 if (gs_info->gs.vertices_out > 0) {
1557 max_gs_prims = MIN2(max_gs_prims,
1558 max_out_prims /
1559 (gs_info->gs.vertices_out * gs_num_invocations));
1560 }
1561 assert(max_gs_prims > 0);
1562
1563 /* If the primitive has adjacency, halve the number of vertices
1564 * that will be reused in multiple primitives.
1565 */
1566 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1567
1568 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1569 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1570
1571 /* Compute ESGS LDS size based on the worst case number of ES vertices
1572 * needed to create the target number of GS prims per subgroup.
1573 */
1574 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1575
1576 /* If total LDS usage is too big, refactor partitions based on ratio
1577 * of ESGS item sizes.
1578 */
1579 if (esgs_lds_size > max_lds_size) {
1580 /* Our target GS Prims Per Subgroup was too large. Calculate
1581 * the maximum number of GS Prims Per Subgroup that will fit
1582 * into LDS, capped by the maximum that the hardware can support.
1583 */
1584 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1585 max_gs_prims);
1586 assert(gs_prims > 0);
1587 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1588 max_es_verts);
1589
1590 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1591 assert(esgs_lds_size <= max_lds_size);
1592 }
1593
1594 /* Now calculate remaining ESGS information. */
1595 if (esgs_lds_size)
1596 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1597 else
1598 es_verts = max_es_verts;
1599
1600 /* Vertices for adjacency primitives are not always reused, so restore
1601 * it for ES_VERTS_PER_SUBGRP.
1602 */
1603 min_es_verts = gs_info->gs.vertices_in;
1604
1605 /* For normal primitives, the VGT only checks if they are past the ES
1606 * verts per subgroup after allocating a full GS primitive and if they
1607 * are, kick off a new subgroup. But if those additional ES verts are
1608 * unique (e.g. not reused) we need to make sure there is enough LDS
1609 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1610 */
1611 es_verts -= min_es_verts - 1;
1612
1613 uint32_t es_verts_per_subgroup = es_verts;
1614 uint32_t gs_prims_per_subgroup = gs_prims;
1615 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1616 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1617 out->lds_size = align(esgs_lds_size, 128) / 128;
1618 out->vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1619 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1620 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1621 out->vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1622 out->vgt_esgs_ring_itemsize = esgs_itemsize;
1623 assert(max_prims_per_subgroup <= max_out_prims);
1624 }
1625
1626 static void clamp_gsprims_to_esverts(unsigned *max_gsprims, unsigned max_esverts,
1627 unsigned min_verts_per_prim, bool use_adjacency)
1628 {
1629 unsigned max_reuse = max_esverts - min_verts_per_prim;
1630 if (use_adjacency)
1631 max_reuse /= 2;
1632 *max_gsprims = MIN2(*max_gsprims, 1 + max_reuse);
1633 }
1634
1635 static unsigned
1636 radv_get_num_input_vertices(nir_shader **nir)
1637 {
1638 if (nir[MESA_SHADER_GEOMETRY]) {
1639 nir_shader *gs = nir[MESA_SHADER_GEOMETRY];
1640
1641 return gs->info.gs.vertices_in;
1642 }
1643
1644 if (nir[MESA_SHADER_TESS_CTRL]) {
1645 nir_shader *tes = nir[MESA_SHADER_TESS_EVAL];
1646
1647 if (tes->info.tess.point_mode)
1648 return 1;
1649 if (tes->info.tess.primitive_mode == GL_ISOLINES)
1650 return 2;
1651 return 3;
1652 }
1653
1654 return 3;
1655 }
1656
1657 static void
1658 gfx10_get_ngg_info(const struct radv_pipeline_key *key,
1659 struct radv_pipeline *pipeline,
1660 nir_shader **nir,
1661 struct radv_shader_info *infos,
1662 struct gfx10_ngg_info *ngg)
1663 {
1664 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1665 struct radv_es_output_info *es_info =
1666 nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1667 unsigned gs_type = nir[MESA_SHADER_GEOMETRY] ? MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX;
1668 unsigned max_verts_per_prim = radv_get_num_input_vertices(nir);
1669 unsigned min_verts_per_prim =
1670 gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1;
1671 unsigned gs_num_invocations = nir[MESA_SHADER_GEOMETRY] ? MAX2(gs_info->gs.invocations, 1) : 1;
1672 bool uses_adjacency;
1673 switch(key->topology) {
1674 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1675 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1676 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1677 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1678 uses_adjacency = true;
1679 break;
1680 default:
1681 uses_adjacency = false;
1682 break;
1683 }
1684
1685 /* All these are in dwords: */
1686 /* We can't allow using the whole LDS, because GS waves compete with
1687 * other shader stages for LDS space.
1688 *
1689 * TODO: We should really take the shader's internal LDS use into
1690 * account. The linker will fail if the size is greater than
1691 * 8K dwords.
1692 */
1693 const unsigned max_lds_size = 8 * 1024 - 768;
1694 const unsigned target_lds_size = max_lds_size;
1695 unsigned esvert_lds_size = 0;
1696 unsigned gsprim_lds_size = 0;
1697
1698 /* All these are per subgroup: */
1699 bool max_vert_out_per_gs_instance = false;
1700 unsigned max_esverts_base = 256;
1701 unsigned max_gsprims_base = 128; /* default prim group size clamp */
1702
1703 /* Hardware has the following non-natural restrictions on the value
1704 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1705 * the draw:
1706 * - at most 252 for any line input primitive type
1707 * - at most 251 for any quad input primitive type
1708 * - at most 251 for triangle strips with adjacency (this happens to
1709 * be the natural limit for triangle *lists* with adjacency)
1710 */
1711 max_esverts_base = MIN2(max_esverts_base, 251 + max_verts_per_prim - 1);
1712
1713 if (gs_type == MESA_SHADER_GEOMETRY) {
1714 unsigned max_out_verts_per_gsprim =
1715 gs_info->gs.vertices_out * gs_num_invocations;
1716
1717 if (max_out_verts_per_gsprim <= 256) {
1718 if (max_out_verts_per_gsprim) {
1719 max_gsprims_base = MIN2(max_gsprims_base,
1720 256 / max_out_verts_per_gsprim);
1721 }
1722 } else {
1723 /* Use special multi-cycling mode in which each GS
1724 * instance gets its own subgroup. Does not work with
1725 * tessellation. */
1726 max_vert_out_per_gs_instance = true;
1727 max_gsprims_base = 1;
1728 max_out_verts_per_gsprim = gs_info->gs.vertices_out;
1729 }
1730
1731 esvert_lds_size = es_info->esgs_itemsize / 4;
1732 gsprim_lds_size = (gs_info->gs.gsvs_vertex_size / 4 + 1) * max_out_verts_per_gsprim;
1733 } else {
1734 /* VS and TES. */
1735 /* LDS size for passing data from GS to ES. */
1736 struct radv_streamout_info *so_info = nir[MESA_SHADER_TESS_CTRL]
1737 ? &infos[MESA_SHADER_TESS_EVAL].so
1738 : &infos[MESA_SHADER_VERTEX].so;
1739
1740 if (so_info->num_outputs)
1741 esvert_lds_size = 4 * so_info->num_outputs + 1;
1742
1743 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1744 * corresponding to the ES thread of the provoking vertex. All
1745 * ES threads load and export PrimitiveID for their thread.
1746 */
1747 if (!nir[MESA_SHADER_TESS_CTRL] &&
1748 infos[MESA_SHADER_VERTEX].vs.outinfo.export_prim_id)
1749 esvert_lds_size = MAX2(esvert_lds_size, 1);
1750 }
1751
1752 unsigned max_gsprims = max_gsprims_base;
1753 unsigned max_esverts = max_esverts_base;
1754
1755 if (esvert_lds_size)
1756 max_esverts = MIN2(max_esverts, target_lds_size / esvert_lds_size);
1757 if (gsprim_lds_size)
1758 max_gsprims = MIN2(max_gsprims, target_lds_size / gsprim_lds_size);
1759
1760 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1761 clamp_gsprims_to_esverts(&max_gsprims, max_esverts, min_verts_per_prim, uses_adjacency);
1762 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1763
1764 if (esvert_lds_size || gsprim_lds_size) {
1765 /* Now that we have a rough proportionality between esverts
1766 * and gsprims based on the primitive type, scale both of them
1767 * down simultaneously based on required LDS space.
1768 *
1769 * We could be smarter about this if we knew how much vertex
1770 * reuse to expect.
1771 */
1772 unsigned lds_total = max_esverts * esvert_lds_size +
1773 max_gsprims * gsprim_lds_size;
1774 if (lds_total > target_lds_size) {
1775 max_esverts = max_esverts * target_lds_size / lds_total;
1776 max_gsprims = max_gsprims * target_lds_size / lds_total;
1777
1778 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1779 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1780 min_verts_per_prim, uses_adjacency);
1781 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1782 }
1783 }
1784
1785 /* Round up towards full wave sizes for better ALU utilization. */
1786 if (!max_vert_out_per_gs_instance) {
1787 unsigned orig_max_esverts;
1788 unsigned orig_max_gsprims;
1789 unsigned wavesize;
1790
1791 if (gs_type == MESA_SHADER_GEOMETRY) {
1792 wavesize = gs_info->wave_size;
1793 } else {
1794 wavesize = nir[MESA_SHADER_TESS_CTRL]
1795 ? infos[MESA_SHADER_TESS_EVAL].wave_size
1796 : infos[MESA_SHADER_VERTEX].wave_size;
1797 }
1798
1799 do {
1800 orig_max_esverts = max_esverts;
1801 orig_max_gsprims = max_gsprims;
1802
1803 max_esverts = align(max_esverts, wavesize);
1804 max_esverts = MIN2(max_esverts, max_esverts_base);
1805 if (esvert_lds_size)
1806 max_esverts = MIN2(max_esverts,
1807 (max_lds_size - max_gsprims * gsprim_lds_size) /
1808 esvert_lds_size);
1809 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1810
1811 max_gsprims = align(max_gsprims, wavesize);
1812 max_gsprims = MIN2(max_gsprims, max_gsprims_base);
1813 if (gsprim_lds_size)
1814 max_gsprims = MIN2(max_gsprims,
1815 (max_lds_size - max_esverts * esvert_lds_size) /
1816 gsprim_lds_size);
1817 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1818 min_verts_per_prim, uses_adjacency);
1819 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1820 } while (orig_max_esverts != max_esverts || orig_max_gsprims != max_gsprims);
1821 }
1822
1823 /* Hardware restriction: minimum value of max_esverts */
1824 max_esverts = MAX2(max_esverts, 23 + max_verts_per_prim);
1825
1826 unsigned max_out_vertices =
1827 max_vert_out_per_gs_instance ? gs_info->gs.vertices_out :
1828 gs_type == MESA_SHADER_GEOMETRY ?
1829 max_gsprims * gs_num_invocations * gs_info->gs.vertices_out :
1830 max_esverts;
1831 assert(max_out_vertices <= 256);
1832
1833 unsigned prim_amp_factor = 1;
1834 if (gs_type == MESA_SHADER_GEOMETRY) {
1835 /* Number of output primitives per GS input primitive after
1836 * GS instancing. */
1837 prim_amp_factor = gs_info->gs.vertices_out;
1838 }
1839
1840 /* The GE only checks against the maximum number of ES verts after
1841 * allocating a full GS primitive. So we need to ensure that whenever
1842 * this check passes, there is enough space for a full primitive without
1843 * vertex reuse.
1844 */
1845 ngg->hw_max_esverts = max_esverts - max_verts_per_prim + 1;
1846 ngg->max_gsprims = max_gsprims;
1847 ngg->max_out_verts = max_out_vertices;
1848 ngg->prim_amp_factor = prim_amp_factor;
1849 ngg->max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
1850 ngg->ngg_emit_size = max_gsprims * gsprim_lds_size;
1851 ngg->esgs_ring_size = 4 * max_esverts * esvert_lds_size;
1852
1853 if (gs_type == MESA_SHADER_GEOMETRY) {
1854 ngg->vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
1855 } else {
1856 ngg->vgt_esgs_ring_itemsize = 1;
1857 }
1858
1859 pipeline->graphics.esgs_ring_size = ngg->esgs_ring_size;
1860
1861 assert(ngg->hw_max_esverts >= 24); /* HW limitation */
1862 }
1863
1864 static void
1865 calculate_gs_ring_sizes(struct radv_pipeline *pipeline,
1866 const struct gfx9_gs_info *gs)
1867 {
1868 struct radv_device *device = pipeline->device;
1869 unsigned num_se = device->physical_device->rad_info.max_se;
1870 unsigned wave_size = 64;
1871 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1872 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1873 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1874 */
1875 unsigned gs_vertex_reuse =
1876 (device->physical_device->rad_info.chip_class >= GFX8 ? 32 : 16) * num_se;
1877 unsigned alignment = 256 * num_se;
1878 /* The maximum size is 63.999 MB per SE. */
1879 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1880 struct radv_shader_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1881
1882 /* Calculate the minimum size. */
1883 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1884 wave_size, alignment);
1885 /* These are recommended sizes, not minimum sizes. */
1886 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1887 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1888 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1889 gs_info->gs.max_gsvs_emit_size;
1890
1891 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1892 esgs_ring_size = align(esgs_ring_size, alignment);
1893 gsvs_ring_size = align(gsvs_ring_size, alignment);
1894
1895 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
1896 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1897
1898 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1899 }
1900
1901 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1902 unsigned *lds_size)
1903 {
1904 /* If tessellation is all offchip and on-chip GS isn't used, this
1905 * workaround is not needed.
1906 */
1907 return;
1908
1909 /* SPI barrier management bug:
1910 * Make sure we have at least 4k of LDS in use to avoid the bug.
1911 * It applies to workgroup sizes of more than one wavefront.
1912 */
1913 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1914 device->physical_device->rad_info.family == CHIP_KABINI)
1915 *lds_size = MAX2(*lds_size, 8);
1916 }
1917
1918 struct radv_shader_variant *
1919 radv_get_shader(struct radv_pipeline *pipeline,
1920 gl_shader_stage stage)
1921 {
1922 if (stage == MESA_SHADER_VERTEX) {
1923 if (pipeline->shaders[MESA_SHADER_VERTEX])
1924 return pipeline->shaders[MESA_SHADER_VERTEX];
1925 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1926 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1927 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1928 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1929 } else if (stage == MESA_SHADER_TESS_EVAL) {
1930 if (!radv_pipeline_has_tess(pipeline))
1931 return NULL;
1932 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1933 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1934 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1935 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1936 }
1937 return pipeline->shaders[stage];
1938 }
1939
1940 static struct radv_tessellation_state
1941 calculate_tess_state(struct radv_pipeline *pipeline,
1942 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1943 {
1944 unsigned num_tcs_input_cp;
1945 unsigned num_tcs_output_cp;
1946 unsigned lds_size;
1947 unsigned num_patches;
1948 struct radv_tessellation_state tess = {0};
1949
1950 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1951 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1952 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1953
1954 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
1955
1956 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
1957 assert(lds_size <= 65536);
1958 lds_size = align(lds_size, 512) / 512;
1959 } else {
1960 assert(lds_size <= 32768);
1961 lds_size = align(lds_size, 256) / 256;
1962 }
1963 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1964
1965 tess.lds_size = lds_size;
1966
1967 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1968 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1969 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1970 tess.num_patches = num_patches;
1971
1972 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
1973 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1974
1975 switch (tes->info.tes.primitive_mode) {
1976 case GL_TRIANGLES:
1977 type = V_028B6C_TESS_TRIANGLE;
1978 break;
1979 case GL_QUADS:
1980 type = V_028B6C_TESS_QUAD;
1981 break;
1982 case GL_ISOLINES:
1983 type = V_028B6C_TESS_ISOLINE;
1984 break;
1985 }
1986
1987 switch (tes->info.tes.spacing) {
1988 case TESS_SPACING_EQUAL:
1989 partitioning = V_028B6C_PART_INTEGER;
1990 break;
1991 case TESS_SPACING_FRACTIONAL_ODD:
1992 partitioning = V_028B6C_PART_FRAC_ODD;
1993 break;
1994 case TESS_SPACING_FRACTIONAL_EVEN:
1995 partitioning = V_028B6C_PART_FRAC_EVEN;
1996 break;
1997 default:
1998 break;
1999 }
2000
2001 bool ccw = tes->info.tes.ccw;
2002 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_origin_state =
2003 vk_find_struct_const(pCreateInfo->pTessellationState,
2004 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
2005
2006 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT)
2007 ccw = !ccw;
2008
2009 if (tes->info.tes.point_mode)
2010 topology = V_028B6C_OUTPUT_POINT;
2011 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
2012 topology = V_028B6C_OUTPUT_LINE;
2013 else if (ccw)
2014 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2015 else
2016 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2017
2018 if (pipeline->device->physical_device->rad_info.has_distributed_tess) {
2019 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
2020 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
2021 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
2022 else
2023 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
2024 } else
2025 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
2026
2027 tess.tf_param = S_028B6C_TYPE(type) |
2028 S_028B6C_PARTITIONING(partitioning) |
2029 S_028B6C_TOPOLOGY(topology) |
2030 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
2031
2032 return tess;
2033 }
2034
2035 static const struct radv_prim_vertex_count prim_size_table[] = {
2036 [V_008958_DI_PT_NONE] = {0, 0},
2037 [V_008958_DI_PT_POINTLIST] = {1, 1},
2038 [V_008958_DI_PT_LINELIST] = {2, 2},
2039 [V_008958_DI_PT_LINESTRIP] = {2, 1},
2040 [V_008958_DI_PT_TRILIST] = {3, 3},
2041 [V_008958_DI_PT_TRIFAN] = {3, 1},
2042 [V_008958_DI_PT_TRISTRIP] = {3, 1},
2043 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
2044 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
2045 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
2046 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
2047 [V_008958_DI_PT_RECTLIST] = {3, 3},
2048 [V_008958_DI_PT_LINELOOP] = {2, 1},
2049 [V_008958_DI_PT_POLYGON] = {3, 1},
2050 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
2051 };
2052
2053 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
2054 {
2055 if (radv_pipeline_has_gs(pipeline))
2056 if (radv_pipeline_has_ngg(pipeline))
2057 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
2058 else
2059 return &pipeline->gs_copy_shader->info.vs.outinfo;
2060 else if (radv_pipeline_has_tess(pipeline))
2061 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
2062 else
2063 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
2064 }
2065
2066 static void
2067 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
2068 {
2069 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
2070 int shader_count = 0;
2071
2072 if(shaders[MESA_SHADER_FRAGMENT]) {
2073 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
2074 }
2075 if(shaders[MESA_SHADER_GEOMETRY]) {
2076 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
2077 }
2078 if(shaders[MESA_SHADER_TESS_EVAL]) {
2079 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
2080 }
2081 if(shaders[MESA_SHADER_TESS_CTRL]) {
2082 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
2083 }
2084 if(shaders[MESA_SHADER_VERTEX]) {
2085 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
2086 }
2087
2088 if (shader_count > 1) {
2089 unsigned first = ordered_shaders[shader_count - 1]->info.stage;
2090 unsigned last = ordered_shaders[0]->info.stage;
2091
2092 if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
2093 ordered_shaders[1]->info.has_transform_feedback_varyings)
2094 nir_link_xfb_varyings(ordered_shaders[1], ordered_shaders[0]);
2095
2096 for (int i = 0; i < shader_count; ++i) {
2097 nir_variable_mode mask = 0;
2098
2099 if (ordered_shaders[i]->info.stage != first)
2100 mask = mask | nir_var_shader_in;
2101
2102 if (ordered_shaders[i]->info.stage != last)
2103 mask = mask | nir_var_shader_out;
2104
2105 nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
2106 radv_optimize_nir(ordered_shaders[i], false, false);
2107 }
2108 }
2109
2110 for (int i = 1; i < shader_count; ++i) {
2111 nir_lower_io_arrays_to_elements(ordered_shaders[i],
2112 ordered_shaders[i - 1]);
2113
2114 if (nir_link_opt_varyings(ordered_shaders[i],
2115 ordered_shaders[i - 1]))
2116 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2117
2118 nir_remove_dead_variables(ordered_shaders[i],
2119 nir_var_shader_out, NULL);
2120 nir_remove_dead_variables(ordered_shaders[i - 1],
2121 nir_var_shader_in, NULL);
2122
2123 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
2124 ordered_shaders[i - 1]);
2125
2126 nir_compact_varyings(ordered_shaders[i],
2127 ordered_shaders[i - 1], true);
2128
2129 if (progress) {
2130 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
2131 ac_lower_indirect_derefs(ordered_shaders[i],
2132 pipeline->device->physical_device->rad_info.chip_class);
2133 }
2134 radv_optimize_nir(ordered_shaders[i], false, false);
2135
2136 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
2137 ac_lower_indirect_derefs(ordered_shaders[i - 1],
2138 pipeline->device->physical_device->rad_info.chip_class);
2139 }
2140 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2141 }
2142 }
2143 }
2144
2145 static void
2146 radv_set_linked_driver_locations(struct radv_pipeline *pipeline, nir_shader **shaders,
2147 struct radv_shader_info infos[MESA_SHADER_STAGES])
2148 {
2149 bool has_tess = shaders[MESA_SHADER_TESS_CTRL];
2150 bool has_gs = shaders[MESA_SHADER_GEOMETRY];
2151
2152 if (!has_tess && !has_gs)
2153 return;
2154
2155 unsigned vs_info_idx = MESA_SHADER_VERTEX;
2156 unsigned tes_info_idx = MESA_SHADER_TESS_EVAL;
2157
2158 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2159 /* These are merged into the next stage */
2160 vs_info_idx = has_tess ? MESA_SHADER_TESS_CTRL : MESA_SHADER_GEOMETRY;
2161 tes_info_idx = has_gs ? MESA_SHADER_GEOMETRY : MESA_SHADER_TESS_EVAL;
2162 }
2163
2164 if (has_tess) {
2165 nir_linked_io_var_info vs2tcs =
2166 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_VERTEX], shaders[MESA_SHADER_TESS_CTRL]);
2167 nir_linked_io_var_info tcs2tes =
2168 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_TESS_CTRL], shaders[MESA_SHADER_TESS_EVAL]);
2169
2170 infos[vs_info_idx].vs.num_linked_outputs = vs2tcs.num_linked_io_vars;
2171 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_inputs = vs2tcs.num_linked_io_vars;
2172 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_outputs = tcs2tes.num_linked_io_vars;
2173 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_patch_outputs = tcs2tes.num_linked_patch_io_vars;
2174 infos[tes_info_idx].tes.num_linked_inputs = tcs2tes.num_linked_io_vars;
2175 infos[tes_info_idx].tes.num_linked_patch_inputs = tcs2tes.num_linked_patch_io_vars;
2176
2177 if (has_gs) {
2178 nir_linked_io_var_info tes2gs =
2179 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_TESS_EVAL], shaders[MESA_SHADER_GEOMETRY]);
2180
2181 infos[tes_info_idx].tes.num_linked_outputs = tes2gs.num_linked_io_vars;
2182 infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = tes2gs.num_linked_io_vars;
2183 }
2184 } else if (has_gs) {
2185 nir_linked_io_var_info vs2gs =
2186 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_VERTEX], shaders[MESA_SHADER_GEOMETRY]);
2187
2188 infos[vs_info_idx].vs.num_linked_outputs = vs2gs.num_linked_io_vars;
2189 infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = vs2gs.num_linked_io_vars;
2190 }
2191 }
2192
2193 static uint32_t
2194 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo *input_state,
2195 uint32_t attrib_binding)
2196 {
2197 for (uint32_t i = 0; i < input_state->vertexBindingDescriptionCount; i++) {
2198 const VkVertexInputBindingDescription *input_binding =
2199 &input_state->pVertexBindingDescriptions[i];
2200
2201 if (input_binding->binding == attrib_binding)
2202 return input_binding->stride;
2203 }
2204
2205 return 0;
2206 }
2207
2208 static struct radv_pipeline_key
2209 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
2210 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2211 const struct radv_blend_state *blend,
2212 bool has_view_index)
2213 {
2214 const VkPipelineVertexInputStateCreateInfo *input_state =
2215 pCreateInfo->pVertexInputState;
2216 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
2217 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
2218
2219 struct radv_pipeline_key key;
2220 memset(&key, 0, sizeof(key));
2221
2222 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
2223 key.optimisations_disabled = 1;
2224
2225 key.has_multiview_view_index = has_view_index;
2226
2227 uint32_t binding_input_rate = 0;
2228 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
2229 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
2230 if (input_state->pVertexBindingDescriptions[i].inputRate) {
2231 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
2232 binding_input_rate |= 1u << binding;
2233 instance_rate_divisors[binding] = 1;
2234 }
2235 }
2236 if (divisor_state) {
2237 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
2238 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
2239 divisor_state->pVertexBindingDivisors[i].divisor;
2240 }
2241 }
2242
2243 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
2244 const VkVertexInputAttributeDescription *desc =
2245 &input_state->pVertexAttributeDescriptions[i];
2246 const struct vk_format_description *format_desc;
2247 unsigned location = desc->location;
2248 unsigned binding = desc->binding;
2249 unsigned num_format, data_format;
2250 int first_non_void;
2251
2252 if (binding_input_rate & (1u << binding)) {
2253 key.instance_rate_inputs |= 1u << location;
2254 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
2255 }
2256
2257 format_desc = vk_format_description(desc->format);
2258 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2259
2260 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2261 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2262
2263 key.vertex_attribute_formats[location] = data_format | (num_format << 4);
2264 key.vertex_attribute_bindings[location] = desc->binding;
2265 key.vertex_attribute_offsets[location] = desc->offset;
2266 key.vertex_attribute_strides[location] = radv_get_attrib_stride(input_state, desc->binding);
2267
2268 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8 &&
2269 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
2270 VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
2271 uint64_t adjust;
2272 switch(format) {
2273 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2274 case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
2275 adjust = RADV_ALPHA_ADJUST_SNORM;
2276 break;
2277 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2278 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
2279 adjust = RADV_ALPHA_ADJUST_SSCALED;
2280 break;
2281 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2282 case VK_FORMAT_A2B10G10R10_SINT_PACK32:
2283 adjust = RADV_ALPHA_ADJUST_SINT;
2284 break;
2285 default:
2286 adjust = 0;
2287 break;
2288 }
2289 key.vertex_alpha_adjust |= adjust << (2 * location);
2290 }
2291
2292 switch (desc->format) {
2293 case VK_FORMAT_B8G8R8A8_UNORM:
2294 case VK_FORMAT_B8G8R8A8_SNORM:
2295 case VK_FORMAT_B8G8R8A8_USCALED:
2296 case VK_FORMAT_B8G8R8A8_SSCALED:
2297 case VK_FORMAT_B8G8R8A8_UINT:
2298 case VK_FORMAT_B8G8R8A8_SINT:
2299 case VK_FORMAT_B8G8R8A8_SRGB:
2300 case VK_FORMAT_A2R10G10B10_UNORM_PACK32:
2301 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2302 case VK_FORMAT_A2R10G10B10_USCALED_PACK32:
2303 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2304 case VK_FORMAT_A2R10G10B10_UINT_PACK32:
2305 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2306 key.vertex_post_shuffle |= 1 << location;
2307 break;
2308 default:
2309 break;
2310 }
2311 }
2312
2313 const VkPipelineTessellationStateCreateInfo *tess =
2314 radv_pipeline_get_tessellation_state(pCreateInfo);
2315 if (tess)
2316 key.tess_input_vertices = tess->patchControlPoints;
2317
2318 const VkPipelineMultisampleStateCreateInfo *vkms =
2319 radv_pipeline_get_multisample_state(pCreateInfo);
2320 if (vkms && vkms->rasterizationSamples > 1) {
2321 uint32_t num_samples = vkms->rasterizationSamples;
2322 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
2323 key.num_samples = num_samples;
2324 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
2325 }
2326
2327 key.col_format = blend->spi_shader_col_format;
2328 key.is_dual_src = blend->mrt0_is_dual_src;
2329 if (pipeline->device->physical_device->rad_info.chip_class < GFX8) {
2330 key.is_int8 = blend->col_format_is_int8;
2331 key.is_int10 = blend->col_format_is_int10;
2332 }
2333
2334 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10)
2335 key.topology = pCreateInfo->pInputAssemblyState->topology;
2336
2337 return key;
2338 }
2339
2340 static bool
2341 radv_nir_stage_uses_xfb(const nir_shader *nir)
2342 {
2343 nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
2344 bool uses_xfb = !!xfb;
2345
2346 ralloc_free(xfb);
2347 return uses_xfb;
2348 }
2349
2350 static void
2351 radv_fill_shader_keys(struct radv_device *device,
2352 struct radv_shader_variant_key *keys,
2353 const struct radv_pipeline_key *key,
2354 nir_shader **nir)
2355 {
2356 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
2357 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
2358 keys[MESA_SHADER_VERTEX].vs.post_shuffle = key->vertex_post_shuffle;
2359 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) {
2360 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
2361 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_formats[i] = key->vertex_attribute_formats[i];
2362 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_bindings[i] = key->vertex_attribute_bindings[i];
2363 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i];
2364 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i];
2365 }
2366 keys[MESA_SHADER_VERTEX].vs.outprim = si_conv_prim_to_gs_out(key->topology);
2367
2368 if (nir[MESA_SHADER_TESS_CTRL]) {
2369 keys[MESA_SHADER_VERTEX].vs_common_out.as_ls = true;
2370 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
2371 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
2372 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
2373
2374 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
2375 }
2376
2377 if (nir[MESA_SHADER_GEOMETRY]) {
2378 if (nir[MESA_SHADER_TESS_CTRL])
2379 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_es = true;
2380 else
2381 keys[MESA_SHADER_VERTEX].vs_common_out.as_es = true;
2382 }
2383
2384 if (device->physical_device->use_ngg) {
2385 if (nir[MESA_SHADER_TESS_CTRL]) {
2386 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = true;
2387 } else {
2388 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = true;
2389 }
2390
2391 if (nir[MESA_SHADER_TESS_CTRL] &&
2392 nir[MESA_SHADER_GEOMETRY] &&
2393 nir[MESA_SHADER_GEOMETRY]->info.gs.invocations *
2394 nir[MESA_SHADER_GEOMETRY]->info.gs.vertices_out > 256) {
2395 /* Fallback to the legacy path if tessellation is
2396 * enabled with extreme geometry because
2397 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2398 * might hang.
2399 */
2400 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2401 }
2402
2403 if (!device->physical_device->use_ngg_gs) {
2404 if (nir[MESA_SHADER_GEOMETRY]) {
2405 if (nir[MESA_SHADER_TESS_CTRL])
2406 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2407 else
2408 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2409 }
2410 }
2411
2412 gl_shader_stage last_xfb_stage = MESA_SHADER_VERTEX;
2413
2414 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
2415 if (nir[i])
2416 last_xfb_stage = i;
2417 }
2418
2419 bool uses_xfb = nir[last_xfb_stage] &&
2420 radv_nir_stage_uses_xfb(nir[last_xfb_stage]);
2421
2422 if (!device->physical_device->use_ngg_streamout && uses_xfb) {
2423 if (nir[MESA_SHADER_TESS_CTRL])
2424 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2425 else
2426 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2427 }
2428
2429 /* Determine if the pipeline is eligible for the NGG passthrough
2430 * mode. It can't be enabled for geometry shaders, for NGG
2431 * streamout or for vertex shaders that export the primitive ID
2432 * (this is checked later because we don't have the info here.)
2433 */
2434 if (!nir[MESA_SHADER_GEOMETRY] && !uses_xfb) {
2435 if (nir[MESA_SHADER_TESS_CTRL] &&
2436 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg) {
2437 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg_passthrough = true;
2438 } else if (nir[MESA_SHADER_VERTEX] &&
2439 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) {
2440 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = true;
2441 }
2442 }
2443 }
2444
2445 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
2446 keys[i].has_multiview_view_index = key->has_multiview_view_index;
2447
2448 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
2449 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
2450 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
2451 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
2452 keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples;
2453 keys[MESA_SHADER_FRAGMENT].fs.is_dual_src = key->is_dual_src;
2454
2455 if (nir[MESA_SHADER_COMPUTE]) {
2456 keys[MESA_SHADER_COMPUTE].cs.subgroup_size = key->compute_subgroup_size;
2457 }
2458 }
2459
2460 static uint8_t
2461 radv_get_wave_size(struct radv_device *device,
2462 const VkPipelineShaderStageCreateInfo *pStage,
2463 gl_shader_stage stage,
2464 const struct radv_shader_variant_key *key)
2465 {
2466 if (stage == MESA_SHADER_GEOMETRY && !key->vs_common_out.as_ngg)
2467 return 64;
2468 else if (stage == MESA_SHADER_COMPUTE) {
2469 if (key->cs.subgroup_size) {
2470 /* Return the required subgroup size if specified. */
2471 return key->cs.subgroup_size;
2472 }
2473 return device->physical_device->cs_wave_size;
2474 }
2475 else if (stage == MESA_SHADER_FRAGMENT)
2476 return device->physical_device->ps_wave_size;
2477 else
2478 return device->physical_device->ge_wave_size;
2479 }
2480
2481 static uint8_t
2482 radv_get_ballot_bit_size(struct radv_device *device,
2483 const VkPipelineShaderStageCreateInfo *pStage,
2484 gl_shader_stage stage,
2485 const struct radv_shader_variant_key *key)
2486 {
2487 if (stage == MESA_SHADER_COMPUTE && key->cs.subgroup_size)
2488 return key->cs.subgroup_size;
2489 return 64;
2490 }
2491
2492 static void
2493 radv_fill_shader_info(struct radv_pipeline *pipeline,
2494 const VkPipelineShaderStageCreateInfo **pStages,
2495 struct radv_shader_variant_key *keys,
2496 struct radv_shader_info *infos,
2497 nir_shader **nir)
2498 {
2499 unsigned active_stages = 0;
2500 unsigned filled_stages = 0;
2501
2502 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2503 if (nir[i])
2504 active_stages |= (1 << i);
2505 }
2506
2507 if (nir[MESA_SHADER_FRAGMENT]) {
2508 radv_nir_shader_info_init(&infos[MESA_SHADER_FRAGMENT]);
2509 radv_nir_shader_info_pass(nir[MESA_SHADER_FRAGMENT],
2510 pipeline->layout,
2511 &keys[MESA_SHADER_FRAGMENT],
2512 &infos[MESA_SHADER_FRAGMENT],
2513 pipeline->device->physical_device->use_llvm);
2514
2515 /* TODO: These are no longer used as keys we should refactor this */
2516 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2517 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2518 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2519 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2520 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2521 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2522 keys[MESA_SHADER_VERTEX].vs_common_out.export_viewport_index =
2523 infos[MESA_SHADER_FRAGMENT].ps.viewport_index_input;
2524 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2525 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2526 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2527 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2528 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2529 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2530 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_viewport_index =
2531 infos[MESA_SHADER_FRAGMENT].ps.viewport_index_input;
2532
2533 /* NGG passthrough mode can't be enabled for vertex shaders
2534 * that export the primitive ID.
2535 *
2536 * TODO: I should really refactor the keys logic.
2537 */
2538 if (nir[MESA_SHADER_VERTEX] &&
2539 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id) {
2540 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = false;
2541 }
2542
2543 filled_stages |= (1 << MESA_SHADER_FRAGMENT);
2544 }
2545
2546 if (nir[MESA_SHADER_TESS_CTRL]) {
2547 infos[MESA_SHADER_TESS_CTRL].tcs.tes_inputs_read =
2548 nir[MESA_SHADER_TESS_EVAL]->info.inputs_read;
2549 infos[MESA_SHADER_TESS_CTRL].tcs.tes_patch_inputs_read =
2550 nir[MESA_SHADER_TESS_EVAL]->info.patch_inputs_read;
2551 }
2552
2553 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2554 nir[MESA_SHADER_TESS_CTRL]) {
2555 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2556 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2557 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2558
2559 radv_nir_shader_info_init(&infos[MESA_SHADER_TESS_CTRL]);
2560
2561 for (int i = 0; i < 2; i++) {
2562 radv_nir_shader_info_pass(combined_nir[i],
2563 pipeline->layout, &key,
2564 &infos[MESA_SHADER_TESS_CTRL],
2565 pipeline->device->physical_device->use_llvm);
2566 }
2567
2568 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2569 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2570 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2571 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2572
2573 filled_stages |= (1 << MESA_SHADER_VERTEX);
2574 filled_stages |= (1 << MESA_SHADER_TESS_CTRL);
2575 }
2576
2577 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2578 nir[MESA_SHADER_GEOMETRY]) {
2579 gl_shader_stage pre_stage = nir[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2580 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2581
2582 radv_nir_shader_info_init(&infos[MESA_SHADER_GEOMETRY]);
2583
2584 for (int i = 0; i < 2; i++) {
2585 radv_nir_shader_info_pass(combined_nir[i],
2586 pipeline->layout,
2587 &keys[pre_stage],
2588 &infos[MESA_SHADER_GEOMETRY],
2589 pipeline->device->physical_device->use_llvm);
2590 }
2591
2592 filled_stages |= (1 << pre_stage);
2593 filled_stages |= (1 << MESA_SHADER_GEOMETRY);
2594 }
2595
2596 active_stages ^= filled_stages;
2597 while (active_stages) {
2598 int i = u_bit_scan(&active_stages);
2599
2600 if (i == MESA_SHADER_TESS_CTRL) {
2601 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs =
2602 util_last_bit64(infos[MESA_SHADER_VERTEX].vs.ls_outputs_written);
2603 }
2604
2605 if (i == MESA_SHADER_TESS_EVAL) {
2606 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2607 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2608 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2609 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2610 }
2611
2612 radv_nir_shader_info_init(&infos[i]);
2613 radv_nir_shader_info_pass(nir[i], pipeline->layout,
2614 &keys[i], &infos[i], pipeline->device->physical_device->use_llvm);
2615 }
2616
2617 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2618 if (nir[i]) {
2619 infos[i].wave_size =
2620 radv_get_wave_size(pipeline->device, pStages[i],
2621 i, &keys[i]);
2622 infos[i].ballot_bit_size =
2623 radv_get_ballot_bit_size(pipeline->device,
2624 pStages[i], i,
2625 &keys[i]);
2626 }
2627 }
2628 }
2629
2630 static void
2631 merge_tess_info(struct shader_info *tes_info,
2632 const struct shader_info *tcs_info)
2633 {
2634 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2635 *
2636 * "PointMode. Controls generation of points rather than triangles
2637 * or lines. This functionality defaults to disabled, and is
2638 * enabled if either shader stage includes the execution mode.
2639 *
2640 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2641 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2642 * and OutputVertices, it says:
2643 *
2644 * "One mode must be set in at least one of the tessellation
2645 * shader stages."
2646 *
2647 * So, the fields can be set in either the TCS or TES, but they must
2648 * agree if set in both. Our backend looks at TES, so bitwise-or in
2649 * the values from the TCS.
2650 */
2651 assert(tcs_info->tess.tcs_vertices_out == 0 ||
2652 tes_info->tess.tcs_vertices_out == 0 ||
2653 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
2654 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
2655
2656 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2657 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2658 tcs_info->tess.spacing == tes_info->tess.spacing);
2659 tes_info->tess.spacing |= tcs_info->tess.spacing;
2660
2661 assert(tcs_info->tess.primitive_mode == 0 ||
2662 tes_info->tess.primitive_mode == 0 ||
2663 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
2664 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
2665 tes_info->tess.ccw |= tcs_info->tess.ccw;
2666 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
2667 }
2668
2669 static
2670 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT *ext)
2671 {
2672 if (!ext)
2673 return;
2674
2675 if (ext->pPipelineCreationFeedback) {
2676 ext->pPipelineCreationFeedback->flags = 0;
2677 ext->pPipelineCreationFeedback->duration = 0;
2678 }
2679
2680 for (unsigned i = 0; i < ext->pipelineStageCreationFeedbackCount; ++i) {
2681 ext->pPipelineStageCreationFeedbacks[i].flags = 0;
2682 ext->pPipelineStageCreationFeedbacks[i].duration = 0;
2683 }
2684 }
2685
2686 static
2687 void radv_start_feedback(VkPipelineCreationFeedbackEXT *feedback)
2688 {
2689 if (!feedback)
2690 return;
2691
2692 feedback->duration -= radv_get_current_time();
2693 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT;
2694 }
2695
2696 static
2697 void radv_stop_feedback(VkPipelineCreationFeedbackEXT *feedback, bool cache_hit)
2698 {
2699 if (!feedback)
2700 return;
2701
2702 feedback->duration += radv_get_current_time();
2703 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT |
2704 (cache_hit ? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT : 0);
2705 }
2706
2707 VkResult radv_create_shaders(struct radv_pipeline *pipeline,
2708 struct radv_device *device,
2709 struct radv_pipeline_cache *cache,
2710 const struct radv_pipeline_key *key,
2711 const VkPipelineShaderStageCreateInfo **pStages,
2712 const VkPipelineCreateFlags flags,
2713 VkPipelineCreationFeedbackEXT *pipeline_feedback,
2714 VkPipelineCreationFeedbackEXT **stage_feedbacks)
2715 {
2716 struct radv_shader_module fs_m = {0};
2717 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2718 nir_shader *nir[MESA_SHADER_STAGES] = {0};
2719 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2720 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{{0}}}}};
2721 struct radv_shader_info infos[MESA_SHADER_STAGES] = {0};
2722 unsigned char hash[20], gs_copy_hash[20];
2723 bool keep_executable_info = (flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR) || device->keep_shader_info;
2724 bool keep_statistic_info = (flags & VK_PIPELINE_CREATE_CAPTURE_STATISTICS_BIT_KHR) ||
2725 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) ||
2726 device->keep_shader_info;
2727
2728 radv_start_feedback(pipeline_feedback);
2729
2730 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2731 if (pStages[i]) {
2732 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
2733 if (modules[i]->nir)
2734 _mesa_sha1_compute(modules[i]->nir->info.name,
2735 strlen(modules[i]->nir->info.name),
2736 modules[i]->sha1);
2737
2738 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
2739 }
2740 }
2741
2742 radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device));
2743 memcpy(gs_copy_hash, hash, 20);
2744 gs_copy_hash[0] ^= 1;
2745
2746 bool found_in_application_cache = true;
2747 if (modules[MESA_SHADER_GEOMETRY] && !keep_executable_info && !keep_statistic_info) {
2748 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2749 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants,
2750 &found_in_application_cache);
2751 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
2752 }
2753
2754 if (!keep_executable_info && !keep_statistic_info &&
2755 radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders,
2756 &found_in_application_cache) &&
2757 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
2758 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2759 return VK_SUCCESS;
2760 }
2761
2762 if (flags & VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_EXT) {
2763 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2764 return VK_PIPELINE_COMPILE_REQUIRED_EXT;
2765 }
2766
2767 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
2768 nir_builder fs_b;
2769 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2770 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2771 fs_m.nir = fs_b.shader;
2772 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2773 }
2774
2775 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2776 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
2777 unsigned subgroup_size = 64, ballot_bit_size = 64;
2778
2779 if (!modules[i])
2780 continue;
2781
2782 radv_start_feedback(stage_feedbacks[i]);
2783
2784 if (key->compute_subgroup_size) {
2785 /* Only compute shaders currently support requiring a
2786 * specific subgroup size.
2787 */
2788 assert(i == MESA_SHADER_COMPUTE);
2789 subgroup_size = key->compute_subgroup_size;
2790 ballot_bit_size = key->compute_subgroup_size;
2791 }
2792
2793 nir[i] = radv_shader_compile_to_nir(device, modules[i],
2794 stage ? stage->pName : "main", i,
2795 stage ? stage->pSpecializationInfo : NULL,
2796 flags, pipeline->layout,
2797 subgroup_size, ballot_bit_size);
2798
2799 /* We don't want to alter meta shaders IR directly so clone it
2800 * first.
2801 */
2802 if (nir[i]->info.name) {
2803 nir[i] = nir_shader_clone(NULL, nir[i]);
2804 }
2805
2806 radv_stop_feedback(stage_feedbacks[i], false);
2807 }
2808
2809 if (nir[MESA_SHADER_TESS_CTRL]) {
2810 nir_lower_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
2811 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
2812 }
2813
2814 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
2815 radv_link_shaders(pipeline, nir);
2816
2817 radv_set_linked_driver_locations(pipeline, nir, infos);
2818
2819 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2820 if (nir[i]) {
2821 /* do this again since information such as outputs_read can be out-of-date */
2822 nir_shader_gather_info(nir[i], nir_shader_get_entrypoint(nir[i]));
2823
2824 if (device->physical_device->use_llvm) {
2825 NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
2826 } else {
2827 NIR_PASS_V(nir[i], nir_lower_non_uniform_access,
2828 nir_lower_non_uniform_ubo_access |
2829 nir_lower_non_uniform_ssbo_access |
2830 nir_lower_non_uniform_texture_access |
2831 nir_lower_non_uniform_image_access);
2832 }
2833 }
2834 }
2835
2836 if (nir[MESA_SHADER_FRAGMENT])
2837 radv_lower_fs_io(nir[MESA_SHADER_FRAGMENT]);
2838
2839 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2840 if (radv_can_dump_shader(device, modules[i], false))
2841 nir_print_shader(nir[i], stderr);
2842 }
2843
2844 radv_fill_shader_keys(device, keys, key, nir);
2845
2846 radv_fill_shader_info(pipeline, pStages, keys, infos, nir);
2847
2848 if ((nir[MESA_SHADER_VERTEX] &&
2849 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) ||
2850 (nir[MESA_SHADER_TESS_EVAL] &&
2851 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg)) {
2852 struct gfx10_ngg_info *ngg_info;
2853
2854 if (nir[MESA_SHADER_GEOMETRY])
2855 ngg_info = &infos[MESA_SHADER_GEOMETRY].ngg_info;
2856 else if (nir[MESA_SHADER_TESS_CTRL])
2857 ngg_info = &infos[MESA_SHADER_TESS_EVAL].ngg_info;
2858 else
2859 ngg_info = &infos[MESA_SHADER_VERTEX].ngg_info;
2860
2861 gfx10_get_ngg_info(key, pipeline, nir, infos, ngg_info);
2862 } else if (nir[MESA_SHADER_GEOMETRY]) {
2863 struct gfx9_gs_info *gs_info =
2864 &infos[MESA_SHADER_GEOMETRY].gs_ring_info;
2865
2866 gfx9_get_gs_info(key, pipeline, nir, infos, gs_info);
2867 }
2868
2869 if(modules[MESA_SHADER_GEOMETRY]) {
2870 struct radv_shader_binary *gs_copy_binary = NULL;
2871 if (!pipeline->gs_copy_shader &&
2872 !radv_pipeline_has_ngg(pipeline)) {
2873 struct radv_shader_info info = {};
2874 struct radv_shader_variant_key key = {};
2875
2876 key.has_multiview_view_index =
2877 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index;
2878
2879 radv_nir_shader_info_pass(nir[MESA_SHADER_GEOMETRY],
2880 pipeline->layout, &key,
2881 &info, pipeline->device->physical_device->use_llvm);
2882 info.wave_size = 64; /* Wave32 not supported. */
2883 info.ballot_bit_size = 64;
2884
2885 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2886 device, nir[MESA_SHADER_GEOMETRY], &info,
2887 &gs_copy_binary, keep_executable_info, keep_statistic_info,
2888 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2889 }
2890
2891 if (!keep_executable_info && !keep_statistic_info && pipeline->gs_copy_shader) {
2892 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2893 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2894
2895 binaries[MESA_SHADER_GEOMETRY] = gs_copy_binary;
2896 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2897
2898 radv_pipeline_cache_insert_shaders(device, cache,
2899 gs_copy_hash,
2900 variants,
2901 binaries);
2902 }
2903 free(gs_copy_binary);
2904 }
2905
2906 if (nir[MESA_SHADER_FRAGMENT]) {
2907 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
2908 radv_start_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT]);
2909
2910 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2911 radv_shader_variant_compile(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
2912 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
2913 infos + MESA_SHADER_FRAGMENT,
2914 keep_executable_info, keep_statistic_info,
2915 &binaries[MESA_SHADER_FRAGMENT]);
2916
2917 radv_stop_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT], false);
2918 }
2919 }
2920
2921 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
2922 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
2923 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2924 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2925 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2926
2927 radv_start_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL]);
2928
2929 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
2930 pipeline->layout,
2931 &key, &infos[MESA_SHADER_TESS_CTRL], keep_executable_info,
2932 keep_statistic_info, &binaries[MESA_SHADER_TESS_CTRL]);
2933
2934 radv_stop_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL], false);
2935 }
2936 modules[MESA_SHADER_VERTEX] = NULL;
2937 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2938 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2939 }
2940
2941 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
2942 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2943 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
2944 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2945
2946 radv_start_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY]);
2947
2948 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2949 pipeline->layout,
2950 &keys[pre_stage], &infos[MESA_SHADER_GEOMETRY], keep_executable_info,
2951 keep_statistic_info, &binaries[MESA_SHADER_GEOMETRY]);
2952
2953 radv_stop_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY], false);
2954 }
2955 modules[pre_stage] = NULL;
2956 }
2957
2958 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2959 if(modules[i] && !pipeline->shaders[i]) {
2960 if (i == MESA_SHADER_TESS_CTRL) {
2961 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.ls_outputs_written);
2962 }
2963 if (i == MESA_SHADER_TESS_EVAL) {
2964 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2965 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2966 }
2967
2968 radv_start_feedback(stage_feedbacks[i]);
2969
2970 pipeline->shaders[i] = radv_shader_variant_compile(device, modules[i], &nir[i], 1,
2971 pipeline->layout,
2972 keys + i, infos + i, keep_executable_info,
2973 keep_statistic_info, &binaries[i]);
2974
2975 radv_stop_feedback(stage_feedbacks[i], false);
2976 }
2977 }
2978
2979 if (!keep_executable_info && !keep_statistic_info) {
2980 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
2981 binaries);
2982 }
2983
2984 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2985 free(binaries[i]);
2986 if (nir[i]) {
2987 ralloc_free(nir[i]);
2988
2989 if (radv_can_dump_shader_stats(device, modules[i]))
2990 radv_shader_dump_stats(device,
2991 pipeline->shaders[i],
2992 i, stderr);
2993 }
2994 }
2995
2996 if (fs_m.nir)
2997 ralloc_free(fs_m.nir);
2998
2999 radv_stop_feedback(pipeline_feedback, false);
3000 return VK_SUCCESS;
3001 }
3002
3003 static uint32_t
3004 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
3005 gl_shader_stage stage, enum chip_class chip_class)
3006 {
3007 bool has_gs = radv_pipeline_has_gs(pipeline);
3008 bool has_tess = radv_pipeline_has_tess(pipeline);
3009 bool has_ngg = radv_pipeline_has_ngg(pipeline);
3010
3011 switch (stage) {
3012 case MESA_SHADER_FRAGMENT:
3013 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
3014 case MESA_SHADER_VERTEX:
3015 if (has_tess) {
3016 if (chip_class >= GFX10) {
3017 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
3018 } else if (chip_class == GFX9) {
3019 return R_00B430_SPI_SHADER_USER_DATA_LS_0;
3020 } else {
3021 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
3022 }
3023
3024 }
3025
3026 if (has_gs) {
3027 if (chip_class >= GFX10) {
3028 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3029 } else {
3030 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
3031 }
3032 }
3033
3034 if (has_ngg)
3035 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3036
3037 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
3038 case MESA_SHADER_GEOMETRY:
3039 return chip_class == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
3040 R_00B230_SPI_SHADER_USER_DATA_GS_0;
3041 case MESA_SHADER_COMPUTE:
3042 return R_00B900_COMPUTE_USER_DATA_0;
3043 case MESA_SHADER_TESS_CTRL:
3044 return chip_class == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
3045 R_00B430_SPI_SHADER_USER_DATA_HS_0;
3046 case MESA_SHADER_TESS_EVAL:
3047 if (has_gs) {
3048 return chip_class >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0 :
3049 R_00B330_SPI_SHADER_USER_DATA_ES_0;
3050 } else if (has_ngg) {
3051 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3052 } else {
3053 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
3054 }
3055 default:
3056 unreachable("unknown shader");
3057 }
3058 }
3059
3060 struct radv_bin_size_entry {
3061 unsigned bpp;
3062 VkExtent2D extent;
3063 };
3064
3065 static VkExtent2D
3066 radv_gfx9_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3067 {
3068 static const struct radv_bin_size_entry color_size_table[][3][9] = {
3069 {
3070 /* One RB / SE */
3071 {
3072 /* One shader engine */
3073 { 0, {128, 128}},
3074 { 1, { 64, 128}},
3075 { 2, { 32, 128}},
3076 { 3, { 16, 128}},
3077 { 17, { 0, 0}},
3078 { UINT_MAX, { 0, 0}},
3079 },
3080 {
3081 /* Two shader engines */
3082 { 0, {128, 128}},
3083 { 2, { 64, 128}},
3084 { 3, { 32, 128}},
3085 { 5, { 16, 128}},
3086 { 17, { 0, 0}},
3087 { UINT_MAX, { 0, 0}},
3088 },
3089 {
3090 /* Four shader engines */
3091 { 0, {128, 128}},
3092 { 3, { 64, 128}},
3093 { 5, { 16, 128}},
3094 { 17, { 0, 0}},
3095 { UINT_MAX, { 0, 0}},
3096 },
3097 },
3098 {
3099 /* Two RB / SE */
3100 {
3101 /* One shader engine */
3102 { 0, {128, 128}},
3103 { 2, { 64, 128}},
3104 { 3, { 32, 128}},
3105 { 5, { 16, 128}},
3106 { 33, { 0, 0}},
3107 { UINT_MAX, { 0, 0}},
3108 },
3109 {
3110 /* Two shader engines */
3111 { 0, {128, 128}},
3112 { 3, { 64, 128}},
3113 { 5, { 32, 128}},
3114 { 9, { 16, 128}},
3115 { 33, { 0, 0}},
3116 { UINT_MAX, { 0, 0}},
3117 },
3118 {
3119 /* Four shader engines */
3120 { 0, {256, 256}},
3121 { 2, {128, 256}},
3122 { 3, {128, 128}},
3123 { 5, { 64, 128}},
3124 { 9, { 16, 128}},
3125 { 33, { 0, 0}},
3126 { UINT_MAX, { 0, 0}},
3127 },
3128 },
3129 {
3130 /* Four RB / SE */
3131 {
3132 /* One shader engine */
3133 { 0, {128, 256}},
3134 { 2, {128, 128}},
3135 { 3, { 64, 128}},
3136 { 5, { 32, 128}},
3137 { 9, { 16, 128}},
3138 { 33, { 0, 0}},
3139 { UINT_MAX, { 0, 0}},
3140 },
3141 {
3142 /* Two shader engines */
3143 { 0, {256, 256}},
3144 { 2, {128, 256}},
3145 { 3, {128, 128}},
3146 { 5, { 64, 128}},
3147 { 9, { 32, 128}},
3148 { 17, { 16, 128}},
3149 { 33, { 0, 0}},
3150 { UINT_MAX, { 0, 0}},
3151 },
3152 {
3153 /* Four shader engines */
3154 { 0, {256, 512}},
3155 { 2, {256, 256}},
3156 { 3, {128, 256}},
3157 { 5, {128, 128}},
3158 { 9, { 64, 128}},
3159 { 17, { 16, 128}},
3160 { 33, { 0, 0}},
3161 { UINT_MAX, { 0, 0}},
3162 },
3163 },
3164 };
3165 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
3166 {
3167 // One RB / SE
3168 {
3169 // One shader engine
3170 { 0, {128, 256}},
3171 { 2, {128, 128}},
3172 { 4, { 64, 128}},
3173 { 7, { 32, 128}},
3174 { 13, { 16, 128}},
3175 { 49, { 0, 0}},
3176 { UINT_MAX, { 0, 0}},
3177 },
3178 {
3179 // Two shader engines
3180 { 0, {256, 256}},
3181 { 2, {128, 256}},
3182 { 4, {128, 128}},
3183 { 7, { 64, 128}},
3184 { 13, { 32, 128}},
3185 { 25, { 16, 128}},
3186 { 49, { 0, 0}},
3187 { UINT_MAX, { 0, 0}},
3188 },
3189 {
3190 // Four shader engines
3191 { 0, {256, 512}},
3192 { 2, {256, 256}},
3193 { 4, {128, 256}},
3194 { 7, {128, 128}},
3195 { 13, { 64, 128}},
3196 { 25, { 16, 128}},
3197 { 49, { 0, 0}},
3198 { UINT_MAX, { 0, 0}},
3199 },
3200 },
3201 {
3202 // Two RB / SE
3203 {
3204 // One shader engine
3205 { 0, {256, 256}},
3206 { 2, {128, 256}},
3207 { 4, {128, 128}},
3208 { 7, { 64, 128}},
3209 { 13, { 32, 128}},
3210 { 25, { 16, 128}},
3211 { 97, { 0, 0}},
3212 { UINT_MAX, { 0, 0}},
3213 },
3214 {
3215 // Two shader engines
3216 { 0, {256, 512}},
3217 { 2, {256, 256}},
3218 { 4, {128, 256}},
3219 { 7, {128, 128}},
3220 { 13, { 64, 128}},
3221 { 25, { 32, 128}},
3222 { 49, { 16, 128}},
3223 { 97, { 0, 0}},
3224 { UINT_MAX, { 0, 0}},
3225 },
3226 {
3227 // Four shader engines
3228 { 0, {512, 512}},
3229 { 2, {256, 512}},
3230 { 4, {256, 256}},
3231 { 7, {128, 256}},
3232 { 13, {128, 128}},
3233 { 25, { 64, 128}},
3234 { 49, { 16, 128}},
3235 { 97, { 0, 0}},
3236 { UINT_MAX, { 0, 0}},
3237 },
3238 },
3239 {
3240 // Four RB / SE
3241 {
3242 // One shader engine
3243 { 0, {256, 512}},
3244 { 2, {256, 256}},
3245 { 4, {128, 256}},
3246 { 7, {128, 128}},
3247 { 13, { 64, 128}},
3248 { 25, { 32, 128}},
3249 { 49, { 16, 128}},
3250 { UINT_MAX, { 0, 0}},
3251 },
3252 {
3253 // Two shader engines
3254 { 0, {512, 512}},
3255 { 2, {256, 512}},
3256 { 4, {256, 256}},
3257 { 7, {128, 256}},
3258 { 13, {128, 128}},
3259 { 25, { 64, 128}},
3260 { 49, { 32, 128}},
3261 { 97, { 16, 128}},
3262 { UINT_MAX, { 0, 0}},
3263 },
3264 {
3265 // Four shader engines
3266 { 0, {512, 512}},
3267 { 4, {256, 512}},
3268 { 7, {256, 256}},
3269 { 13, {128, 256}},
3270 { 25, {128, 128}},
3271 { 49, { 64, 128}},
3272 { 97, { 16, 128}},
3273 { UINT_MAX, { 0, 0}},
3274 },
3275 },
3276 };
3277
3278 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3279 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3280 VkExtent2D extent = {512, 512};
3281
3282 unsigned log_num_rb_per_se =
3283 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
3284 pipeline->device->physical_device->rad_info.max_se);
3285 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
3286
3287 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3288 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
3289 unsigned effective_samples = total_samples;
3290 unsigned color_bytes_per_pixel = 0;
3291
3292 const VkPipelineColorBlendStateCreateInfo *vkblend =
3293 radv_pipeline_get_color_blend_state(pCreateInfo);
3294 if (vkblend) {
3295 for (unsigned i = 0; i < subpass->color_count; i++) {
3296 if (!vkblend->pAttachments[i].colorWriteMask)
3297 continue;
3298
3299 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3300 continue;
3301
3302 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3303 color_bytes_per_pixel += vk_format_get_blocksize(format);
3304 }
3305
3306 /* MSAA images typically don't use all samples all the time. */
3307 if (effective_samples >= 2 && ps_iter_samples <= 1)
3308 effective_samples = 2;
3309 color_bytes_per_pixel *= effective_samples;
3310 }
3311
3312 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
3313 while(color_entry[1].bpp <= color_bytes_per_pixel)
3314 ++color_entry;
3315
3316 extent = color_entry->extent;
3317
3318 if (subpass->depth_stencil_attachment) {
3319 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3320
3321 /* Coefficients taken from AMDVLK */
3322 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3323 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3324 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
3325
3326 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
3327 while(ds_entry[1].bpp <= ds_bytes_per_pixel)
3328 ++ds_entry;
3329
3330 if (ds_entry->extent.width * ds_entry->extent.height < extent.width * extent.height)
3331 extent = ds_entry->extent;
3332 }
3333
3334 return extent;
3335 }
3336
3337 static VkExtent2D
3338 radv_gfx10_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3339 {
3340 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3341 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3342 VkExtent2D extent = {512, 512};
3343
3344 const unsigned db_tag_size = 64;
3345 const unsigned db_tag_count = 312;
3346 const unsigned color_tag_size = 1024;
3347 const unsigned color_tag_count = 31;
3348 const unsigned fmask_tag_size = 256;
3349 const unsigned fmask_tag_count = 44;
3350
3351 const unsigned rb_count = pipeline->device->physical_device->rad_info.num_render_backends;
3352 const unsigned pipe_count = MAX2(rb_count, pipeline->device->physical_device->rad_info.num_sdp_interfaces);
3353
3354 const unsigned db_tag_part = (db_tag_count * rb_count / pipe_count) * db_tag_size * pipe_count;
3355 const unsigned color_tag_part = (color_tag_count * rb_count / pipe_count) * color_tag_size * pipe_count;
3356 const unsigned fmask_tag_part = (fmask_tag_count * rb_count / pipe_count) * fmask_tag_size * pipe_count;
3357
3358 const unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3359 const unsigned samples_log = util_logbase2_ceil(total_samples);
3360
3361 unsigned color_bytes_per_pixel = 0;
3362 unsigned fmask_bytes_per_pixel = 0;
3363
3364 const VkPipelineColorBlendStateCreateInfo *vkblend =
3365 radv_pipeline_get_color_blend_state(pCreateInfo);
3366 if (vkblend) {
3367 for (unsigned i = 0; i < subpass->color_count; i++) {
3368 if (!vkblend->pAttachments[i].colorWriteMask)
3369 continue;
3370
3371 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3372 continue;
3373
3374 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3375 color_bytes_per_pixel += vk_format_get_blocksize(format);
3376
3377 if (total_samples > 1) {
3378 assert(samples_log <= 3);
3379 const unsigned fmask_array[] = {0, 1, 1, 4};
3380 fmask_bytes_per_pixel += fmask_array[samples_log];
3381 }
3382 }
3383
3384 color_bytes_per_pixel *= total_samples;
3385 }
3386 color_bytes_per_pixel = MAX2(color_bytes_per_pixel, 1);
3387
3388 const unsigned color_pixel_count_log = util_logbase2(color_tag_part / color_bytes_per_pixel);
3389 extent.width = 1ull << ((color_pixel_count_log + 1) / 2);
3390 extent.height = 1ull << (color_pixel_count_log / 2);
3391
3392 if (fmask_bytes_per_pixel) {
3393 const unsigned fmask_pixel_count_log = util_logbase2(fmask_tag_part / fmask_bytes_per_pixel);
3394
3395 const VkExtent2D fmask_extent = (VkExtent2D){
3396 .width = 1ull << ((fmask_pixel_count_log + 1) / 2),
3397 .height = 1ull << (color_pixel_count_log / 2)
3398 };
3399
3400 if (fmask_extent.width * fmask_extent.height < extent.width * extent.height)
3401 extent = fmask_extent;
3402 }
3403
3404 if (subpass->depth_stencil_attachment) {
3405 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3406
3407 /* Coefficients taken from AMDVLK */
3408 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3409 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3410 unsigned db_bytes_per_pixel = (depth_coeff + stencil_coeff) * total_samples;
3411
3412 const unsigned db_pixel_count_log = util_logbase2(db_tag_part / db_bytes_per_pixel);
3413
3414 const VkExtent2D db_extent = (VkExtent2D){
3415 .width = 1ull << ((db_pixel_count_log + 1) / 2),
3416 .height = 1ull << (color_pixel_count_log / 2)
3417 };
3418
3419 if (db_extent.width * db_extent.height < extent.width * extent.height)
3420 extent = db_extent;
3421 }
3422
3423 extent.width = MAX2(extent.width, 128);
3424 extent.height = MAX2(extent.width, 64);
3425
3426 return extent;
3427 }
3428
3429 static void
3430 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf *ctx_cs,
3431 struct radv_pipeline *pipeline,
3432 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3433 {
3434 uint32_t pa_sc_binner_cntl_0 =
3435 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
3436 S_028C44_DISABLE_START_OF_PRIM(1);
3437 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3438
3439 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3440 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3441 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3442 const VkPipelineColorBlendStateCreateInfo *vkblend =
3443 radv_pipeline_get_color_blend_state(pCreateInfo);
3444 unsigned min_bytes_per_pixel = 0;
3445
3446 if (vkblend) {
3447 for (unsigned i = 0; i < subpass->color_count; i++) {
3448 if (!vkblend->pAttachments[i].colorWriteMask)
3449 continue;
3450
3451 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3452 continue;
3453
3454 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3455 unsigned bytes = vk_format_get_blocksize(format);
3456 if (!min_bytes_per_pixel || bytes < min_bytes_per_pixel)
3457 min_bytes_per_pixel = bytes;
3458 }
3459 }
3460
3461 pa_sc_binner_cntl_0 =
3462 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) |
3463 S_028C44_BIN_SIZE_X(0) |
3464 S_028C44_BIN_SIZE_Y(0) |
3465 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3466 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel <= 4 ? 2 : 1) | /* 128 or 64 */
3467 S_028C44_DISABLE_START_OF_PRIM(1);
3468 }
3469
3470 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3471 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3472 }
3473
3474 struct radv_binning_settings
3475 radv_get_binning_settings(const struct radv_physical_device *pdev)
3476 {
3477 struct radv_binning_settings settings;
3478 if (pdev->rad_info.has_dedicated_vram) {
3479 if (pdev->rad_info.num_render_backends > 4) {
3480 settings.context_states_per_bin = 1;
3481 settings.persistent_states_per_bin = 1;
3482 } else {
3483 settings.context_states_per_bin = 3;
3484 settings.persistent_states_per_bin = 8;
3485 }
3486 settings.fpovs_per_batch = 63;
3487 } else {
3488 /* The context states are affected by the scissor bug. */
3489 settings.context_states_per_bin = 6;
3490 /* 32 causes hangs for RAVEN. */
3491 settings.persistent_states_per_bin = 16;
3492 settings.fpovs_per_batch = 63;
3493 }
3494
3495 if (pdev->rad_info.has_gfx9_scissor_bug)
3496 settings.context_states_per_bin = 1;
3497
3498 return settings;
3499 }
3500
3501 static void
3502 radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs,
3503 struct radv_pipeline *pipeline,
3504 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3505 const struct radv_blend_state *blend)
3506 {
3507 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
3508 return;
3509
3510 VkExtent2D bin_size;
3511 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3512 bin_size = radv_gfx10_compute_bin_size(pipeline, pCreateInfo);
3513 } else if (pipeline->device->physical_device->rad_info.chip_class == GFX9) {
3514 bin_size = radv_gfx9_compute_bin_size(pipeline, pCreateInfo);
3515 } else
3516 unreachable("Unhandled generation for binning bin size calculation");
3517
3518 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
3519 struct radv_binning_settings settings =
3520 radv_get_binning_settings(pipeline->device->physical_device);
3521
3522 bool disable_start_of_prim = true;
3523 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3524
3525 const struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3526
3527 if (pipeline->device->dfsm_allowed && ps &&
3528 !ps->info.ps.can_discard &&
3529 !ps->info.ps.writes_memory &&
3530 blend->cb_target_enabled_4bit) {
3531 db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_AUTO);
3532 disable_start_of_prim = (blend->blend_enable_4bit & blend->cb_target_enabled_4bit) != 0;
3533 }
3534
3535 const uint32_t pa_sc_binner_cntl_0 =
3536 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
3537 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
3538 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
3539 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
3540 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
3541 S_028C44_CONTEXT_STATES_PER_BIN(settings.context_states_per_bin - 1) |
3542 S_028C44_PERSISTENT_STATES_PER_BIN(settings.persistent_states_per_bin - 1) |
3543 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim) |
3544 S_028C44_FPOVS_PER_BATCH(settings.fpovs_per_batch) |
3545 S_028C44_OPTIMAL_BIN_SELECTION(1);
3546
3547 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3548 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3549 } else
3550 radv_pipeline_generate_disabled_binning_state(ctx_cs, pipeline, pCreateInfo);
3551 }
3552
3553
3554 static void
3555 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs,
3556 struct radv_pipeline *pipeline,
3557 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3558 const struct radv_graphics_pipeline_create_info *extra)
3559 {
3560 const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
3561 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3562 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3563 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3564 struct radv_render_pass_attachment *attachment = NULL;
3565 uint32_t db_depth_control = 0, db_stencil_control = 0;
3566 uint32_t db_render_control = 0, db_render_override2 = 0;
3567 uint32_t db_render_override = 0;
3568
3569 if (subpass->depth_stencil_attachment)
3570 attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3571
3572 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
3573 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
3574
3575 if (vkds && has_depth_attachment) {
3576 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
3577 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
3578 S_028800_ZFUNC(vkds->depthCompareOp) |
3579 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
3580
3581 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3582 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
3583
3584 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10_3)
3585 db_render_override2 |= S_028010_CENTROID_COMPUTATION_MODE_GFX103(2);
3586 }
3587
3588 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
3589 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3590 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
3591 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
3592 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
3593 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
3594
3595 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
3596 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
3597 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
3598 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
3599 }
3600
3601 if (attachment && extra) {
3602 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
3603 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
3604
3605 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->resummarize_enable);
3606 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->depth_compress_disable);
3607 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->stencil_compress_disable);
3608 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
3609 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
3610 }
3611
3612 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3613 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
3614
3615 if (!pCreateInfo->pRasterizationState->depthClampEnable &&
3616 ps->info.ps.writes_z) {
3617 /* From VK_EXT_depth_range_unrestricted spec:
3618 *
3619 * "The behavior described in Primitive Clipping still applies.
3620 * If depth clamping is disabled the depth values are still
3621 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3622 * depth clamping is enabled the above equation is ignored and
3623 * the depth values are instead clamped to the VkViewport
3624 * minDepth and maxDepth values, which in the case of this
3625 * extension can be outside of the 0.0 to 1.0 range."
3626 */
3627 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3628 }
3629
3630 radeon_set_context_reg(ctx_cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
3631 radeon_set_context_reg(ctx_cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
3632
3633 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control);
3634 radeon_set_context_reg(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
3635 radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
3636 }
3637
3638 static void
3639 radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
3640 struct radv_pipeline *pipeline,
3641 const struct radv_blend_state *blend)
3642 {
3643 radeon_set_context_reg_seq(ctx_cs, R_028780_CB_BLEND0_CONTROL, 8);
3644 radeon_emit_array(ctx_cs, blend->cb_blend_control,
3645 8);
3646 radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
3647 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
3648
3649 if (pipeline->device->physical_device->rad_info.has_rbplus) {
3650
3651 radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
3652 radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
3653 }
3654
3655 radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
3656
3657 radeon_set_context_reg(ctx_cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
3658 radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
3659
3660 pipeline->graphics.col_format = blend->spi_shader_col_format;
3661 pipeline->graphics.cb_target_mask = blend->cb_target_mask;
3662 }
3663
3664 static const VkConservativeRasterizationModeEXT
3665 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo)
3666 {
3667 const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster =
3668 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT);
3669
3670 if (!conservative_raster)
3671 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT;
3672 return conservative_raster->conservativeRasterizationMode;
3673 }
3674
3675 static void
3676 radv_pipeline_generate_raster_state(struct radeon_cmdbuf *ctx_cs,
3677 struct radv_pipeline *pipeline,
3678 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3679 {
3680 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
3681 const VkConservativeRasterizationModeEXT mode =
3682 radv_get_conservative_raster_mode(vkraster);
3683 uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3684 bool depth_clip_disable = vkraster->depthClampEnable;
3685
3686 const VkPipelineRasterizationDepthClipStateCreateInfoEXT *depth_clip_state =
3687 vk_find_struct_const(vkraster->pNext, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT);
3688 if (depth_clip_state) {
3689 depth_clip_disable = !depth_clip_state->depthClipEnable;
3690 }
3691
3692 radeon_set_context_reg(ctx_cs, R_028810_PA_CL_CLIP_CNTL,
3693 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3694 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable ? 1 : 0) |
3695 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable ? 1 : 0) |
3696 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
3697 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3698
3699 radeon_set_context_reg(ctx_cs, R_0286D4_SPI_INTERP_CONTROL_0,
3700 S_0286D4_FLAT_SHADE_ENA(1) |
3701 S_0286D4_PNT_SPRITE_ENA(1) |
3702 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
3703 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
3704 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
3705 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
3706 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3707
3708 radeon_set_context_reg(ctx_cs, R_028BE4_PA_SU_VTX_CNTL,
3709 S_028BE4_PIX_CENTER(1) | // TODO verify
3710 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
3711 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
3712
3713 radeon_set_context_reg(ctx_cs, R_028814_PA_SU_SC_MODE_CNTL,
3714 S_028814_FACE(vkraster->frontFace) |
3715 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
3716 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
3717 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
3718 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3719 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3720 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3721 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3722 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
3723
3724 /* Conservative rasterization. */
3725 if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
3726 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3727
3728 ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3729 ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3730 S_028804_OVERRASTERIZATION_AMOUNT(4);
3731
3732 pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3733 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3734 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3735
3736 if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) {
3737 pa_sc_conservative_rast |=
3738 S_028C4C_OVER_RAST_ENABLE(1) |
3739 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3740 S_028C4C_UNDER_RAST_ENABLE(0) |
3741 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3742 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3743 } else {
3744 assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT);
3745 pa_sc_conservative_rast |=
3746 S_028C4C_OVER_RAST_ENABLE(0) |
3747 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3748 S_028C4C_UNDER_RAST_ENABLE(1) |
3749 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3750 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3751 }
3752 }
3753
3754 radeon_set_context_reg(ctx_cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
3755 pa_sc_conservative_rast);
3756 }
3757
3758
3759 static void
3760 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
3761 struct radv_pipeline *pipeline)
3762 {
3763 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3764
3765 radeon_set_context_reg_seq(ctx_cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3766 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[0]);
3767 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]);
3768
3769 radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa);
3770 radeon_set_context_reg(ctx_cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
3771 radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
3772 radeon_set_context_reg(ctx_cs, R_028BDC_PA_SC_LINE_CNTL, ms->pa_sc_line_cntl);
3773 radeon_set_context_reg(ctx_cs, R_028BE0_PA_SC_AA_CONFIG, ms->pa_sc_aa_config);
3774
3775 /* The exclusion bits can be set to improve rasterization efficiency
3776 * if no sample lies on the pixel boundary (-8 sample offset). It's
3777 * currently always TRUE because the driver doesn't support 16 samples.
3778 */
3779 bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= GFX7;
3780 radeon_set_context_reg(ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3781 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3782 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3783
3784 /* GFX9: Flush DFSM when the AA mode changes. */
3785 if (pipeline->device->dfsm_allowed) {
3786 radeon_emit(ctx_cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3787 radeon_emit(ctx_cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3788 }
3789 }
3790
3791 static void
3792 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
3793 struct radv_pipeline *pipeline)
3794 {
3795 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3796 const struct radv_shader_variant *vs =
3797 pipeline->shaders[MESA_SHADER_TESS_EVAL] ?
3798 pipeline->shaders[MESA_SHADER_TESS_EVAL] :
3799 pipeline->shaders[MESA_SHADER_VERTEX];
3800 unsigned vgt_primitiveid_en = 0;
3801 uint32_t vgt_gs_mode = 0;
3802
3803 if (radv_pipeline_has_ngg(pipeline))
3804 return;
3805
3806 if (radv_pipeline_has_gs(pipeline)) {
3807 const struct radv_shader_variant *gs =
3808 pipeline->shaders[MESA_SHADER_GEOMETRY];
3809
3810 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
3811 pipeline->device->physical_device->rad_info.chip_class);
3812 } else if (outinfo->export_prim_id || vs->info.uses_prim_id) {
3813 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
3814 vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(1);
3815 }
3816
3817 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
3818 radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
3819 }
3820
3821 static void
3822 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
3823 struct radeon_cmdbuf *cs,
3824 struct radv_pipeline *pipeline,
3825 struct radv_shader_variant *shader)
3826 {
3827 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3828
3829 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
3830 radeon_emit(cs, va >> 8);
3831 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
3832 radeon_emit(cs, shader->config.rsrc1);
3833 radeon_emit(cs, shader->config.rsrc2);
3834
3835 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3836 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3837 clip_dist_mask = outinfo->clip_dist_mask;
3838 cull_dist_mask = outinfo->cull_dist_mask;
3839 total_mask = clip_dist_mask | cull_dist_mask;
3840 bool misc_vec_ena = outinfo->writes_pointsize ||
3841 outinfo->writes_layer ||
3842 outinfo->writes_viewport_index;
3843 unsigned spi_vs_out_config, nparams;
3844
3845 /* VS is required to export at least one param. */
3846 nparams = MAX2(outinfo->param_exports, 1);
3847 spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
3848
3849 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3850 spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0);
3851 }
3852
3853 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, spi_vs_out_config);
3854
3855 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3856 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3857 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3858 V_02870C_SPI_SHADER_4COMP :
3859 V_02870C_SPI_SHADER_NONE) |
3860 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3861 V_02870C_SPI_SHADER_4COMP :
3862 V_02870C_SPI_SHADER_NONE) |
3863 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3864 V_02870C_SPI_SHADER_4COMP :
3865 V_02870C_SPI_SHADER_NONE));
3866
3867 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3868 S_028818_VTX_W0_FMT(1) |
3869 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3870 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3871 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3872
3873 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3874 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3875 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3876 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3877 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3878 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3879 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3880 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3881 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) |
3882 cull_dist_mask << 8 |
3883 clip_dist_mask);
3884
3885 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
3886 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
3887 outinfo->writes_viewport_index);
3888 }
3889
3890 static void
3891 radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs,
3892 struct radv_pipeline *pipeline,
3893 struct radv_shader_variant *shader)
3894 {
3895 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3896
3897 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
3898 radeon_emit(cs, va >> 8);
3899 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3900 radeon_emit(cs, shader->config.rsrc1);
3901 radeon_emit(cs, shader->config.rsrc2);
3902 }
3903
3904 static void
3905 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs,
3906 struct radv_pipeline *pipeline,
3907 struct radv_shader_variant *shader,
3908 const struct radv_tessellation_state *tess)
3909 {
3910 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3911 uint32_t rsrc2 = shader->config.rsrc2;
3912
3913 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3914 radeon_emit(cs, va >> 8);
3915 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3916
3917 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
3918 if (pipeline->device->physical_device->rad_info.chip_class == GFX7 &&
3919 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
3920 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
3921
3922 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
3923 radeon_emit(cs, shader->config.rsrc1);
3924 radeon_emit(cs, rsrc2);
3925 }
3926
3927 static void
3928 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
3929 struct radeon_cmdbuf *cs,
3930 struct radv_pipeline *pipeline,
3931 struct radv_shader_variant *shader)
3932 {
3933 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3934 gl_shader_stage es_type =
3935 radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
3936 struct radv_shader_variant *es =
3937 es_type == MESA_SHADER_TESS_EVAL ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX];
3938 const struct gfx10_ngg_info *ngg_state = &shader->info.ngg_info;
3939
3940 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
3941 radeon_emit(cs, va >> 8);
3942 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3943 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
3944 radeon_emit(cs, shader->config.rsrc1);
3945 radeon_emit(cs, shader->config.rsrc2);
3946
3947 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3948 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3949 clip_dist_mask = outinfo->clip_dist_mask;
3950 cull_dist_mask = outinfo->cull_dist_mask;
3951 total_mask = clip_dist_mask | cull_dist_mask;
3952 bool misc_vec_ena = outinfo->writes_pointsize ||
3953 outinfo->writes_layer ||
3954 outinfo->writes_viewport_index;
3955 bool es_enable_prim_id = outinfo->export_prim_id ||
3956 (es && es->info.uses_prim_id);
3957 bool break_wave_at_eoi = false;
3958 unsigned ge_cntl;
3959 unsigned nparams;
3960
3961 if (es_type == MESA_SHADER_TESS_EVAL) {
3962 struct radv_shader_variant *gs =
3963 pipeline->shaders[MESA_SHADER_GEOMETRY];
3964
3965 if (es_enable_prim_id || (gs && gs->info.uses_prim_id))
3966 break_wave_at_eoi = true;
3967 }
3968
3969 nparams = MAX2(outinfo->param_exports, 1);
3970 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG,
3971 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
3972 S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0));
3973
3974 radeon_set_context_reg(ctx_cs, R_028708_SPI_SHADER_IDX_FORMAT,
3975 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP));
3976 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3977 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3978 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3979 V_02870C_SPI_SHADER_4COMP :
3980 V_02870C_SPI_SHADER_NONE) |
3981 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3982 V_02870C_SPI_SHADER_4COMP :
3983 V_02870C_SPI_SHADER_NONE) |
3984 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3985 V_02870C_SPI_SHADER_4COMP :
3986 V_02870C_SPI_SHADER_NONE));
3987
3988 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3989 S_028818_VTX_W0_FMT(1) |
3990 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3991 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3992 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3993 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3994 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3995 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3996 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3997 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3998 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3999 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
4000 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
4001 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) |
4002 cull_dist_mask << 8 |
4003 clip_dist_mask);
4004
4005 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN,
4006 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
4007 S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo->export_prim_id));
4008
4009 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
4010 ngg_state->vgt_esgs_ring_itemsize);
4011
4012 /* NGG specific registers. */
4013 struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
4014 uint32_t gs_num_invocations = gs ? gs->info.gs.invocations : 1;
4015
4016 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
4017 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state->hw_max_esverts) |
4018 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state->max_gsprims) |
4019 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state->max_gsprims * gs_num_invocations));
4020 radeon_set_context_reg(ctx_cs, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
4021 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state->max_out_verts));
4022 radeon_set_context_reg(ctx_cs, R_028B4C_GE_NGG_SUBGRP_CNTL,
4023 S_028B4C_PRIM_AMP_FACTOR(ngg_state->prim_amp_factor) |
4024 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
4025 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
4026 S_028B90_CNT(gs_num_invocations) |
4027 S_028B90_ENABLE(gs_num_invocations > 1) |
4028 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state->max_vert_out_per_gs_instance));
4029
4030 /* User edge flags are set by the pos exports. If user edge flags are
4031 * not used, we must use hw-generated edge flags and pass them via
4032 * the prim export to prevent drawing lines on internal edges of
4033 * decomposed primitives (such as quads) with polygon mode = lines.
4034 *
4035 * TODO: We should combine hw-generated edge flags with user edge
4036 * flags in the shader.
4037 */
4038 radeon_set_context_reg(ctx_cs, R_028838_PA_CL_NGG_CNTL,
4039 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) &&
4040 !radv_pipeline_has_gs(pipeline)) |
4041 /* Reuse for NGG. */
4042 S_028838_VERTEX_REUSE_DEPTH_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3 ? 30 : 0));
4043
4044 ge_cntl = S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) |
4045 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
4046 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
4047
4048 /* Bug workaround for a possible hang with non-tessellation cases.
4049 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
4050 *
4051 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
4052 */
4053 if (pipeline->device->physical_device->rad_info.chip_class == GFX10 &&
4054 !radv_pipeline_has_tess(pipeline) &&
4055 ngg_state->hw_max_esverts != 256) {
4056 ge_cntl &= C_03096C_VERT_GRP_SIZE;
4057
4058 if (ngg_state->hw_max_esverts > 5) {
4059 ge_cntl |= S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts - 5);
4060 }
4061 }
4062
4063 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, ge_cntl);
4064 }
4065
4066 static void
4067 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
4068 struct radv_pipeline *pipeline,
4069 struct radv_shader_variant *shader,
4070 const struct radv_tessellation_state *tess)
4071 {
4072 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
4073
4074 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4075 unsigned hs_rsrc2 = shader->config.rsrc2;
4076
4077 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4078 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(tess->lds_size);
4079 } else {
4080 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(tess->lds_size);
4081 }
4082
4083 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4084 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
4085 radeon_emit(cs, va >> 8);
4086 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
4087 } else {
4088 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
4089 radeon_emit(cs, va >> 8);
4090 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
4091 }
4092
4093 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
4094 radeon_emit(cs, shader->config.rsrc1);
4095 radeon_emit(cs, hs_rsrc2);
4096 } else {
4097 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
4098 radeon_emit(cs, va >> 8);
4099 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
4100 radeon_emit(cs, shader->config.rsrc1);
4101 radeon_emit(cs, shader->config.rsrc2);
4102 }
4103 }
4104
4105 static void
4106 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *ctx_cs,
4107 struct radeon_cmdbuf *cs,
4108 struct radv_pipeline *pipeline,
4109 const struct radv_tessellation_state *tess)
4110 {
4111 struct radv_shader_variant *vs;
4112
4113 /* Skip shaders merged into HS/GS */
4114 vs = pipeline->shaders[MESA_SHADER_VERTEX];
4115 if (!vs)
4116 return;
4117
4118 if (vs->info.vs.as_ls)
4119 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
4120 else if (vs->info.vs.as_es)
4121 radv_pipeline_generate_hw_es(cs, pipeline, vs);
4122 else if (vs->info.is_ngg)
4123 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, vs);
4124 else
4125 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, vs);
4126 }
4127
4128 static void
4129 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs,
4130 struct radeon_cmdbuf *cs,
4131 struct radv_pipeline *pipeline,
4132 const struct radv_tessellation_state *tess)
4133 {
4134 if (!radv_pipeline_has_tess(pipeline))
4135 return;
4136
4137 struct radv_shader_variant *tes, *tcs;
4138
4139 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
4140 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
4141
4142 if (tes) {
4143 if (tes->info.is_ngg) {
4144 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, tes);
4145 } else if (tes->info.tes.as_es)
4146 radv_pipeline_generate_hw_es(cs, pipeline, tes);
4147 else
4148 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes);
4149 }
4150
4151 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
4152
4153 radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM,
4154 tess->tf_param);
4155
4156 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7)
4157 radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, 2,
4158 tess->ls_hs_config);
4159 else
4160 radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG,
4161 tess->ls_hs_config);
4162
4163 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 &&
4164 !radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
4165 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
4166 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4167 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4168 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4169 }
4170 }
4171
4172 static void
4173 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs,
4174 struct radeon_cmdbuf *cs,
4175 struct radv_pipeline *pipeline,
4176 struct radv_shader_variant *gs)
4177 {
4178 const struct gfx9_gs_info *gs_state = &gs->info.gs_ring_info;
4179 unsigned gs_max_out_vertices;
4180 uint8_t *num_components;
4181 uint8_t max_stream;
4182 unsigned offset;
4183 uint64_t va;
4184
4185 gs_max_out_vertices = gs->info.gs.vertices_out;
4186 max_stream = gs->info.gs.max_stream;
4187 num_components = gs->info.gs.num_stream_output_components;
4188
4189 offset = num_components[0] * gs_max_out_vertices;
4190
4191 radeon_set_context_reg_seq(ctx_cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
4192 radeon_emit(ctx_cs, offset);
4193 if (max_stream >= 1)
4194 offset += num_components[1] * gs_max_out_vertices;
4195 radeon_emit(ctx_cs, offset);
4196 if (max_stream >= 2)
4197 offset += num_components[2] * gs_max_out_vertices;
4198 radeon_emit(ctx_cs, offset);
4199 if (max_stream >= 3)
4200 offset += num_components[3] * gs_max_out_vertices;
4201 radeon_set_context_reg(ctx_cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
4202
4203 radeon_set_context_reg_seq(ctx_cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
4204 radeon_emit(ctx_cs, num_components[0]);
4205 radeon_emit(ctx_cs, (max_stream >= 1) ? num_components[1] : 0);
4206 radeon_emit(ctx_cs, (max_stream >= 2) ? num_components[2] : 0);
4207 radeon_emit(ctx_cs, (max_stream >= 3) ? num_components[3] : 0);
4208
4209 uint32_t gs_num_invocations = gs->info.gs.invocations;
4210 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
4211 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
4212 S_028B90_ENABLE(gs_num_invocations > 0));
4213
4214 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
4215 gs_state->vgt_esgs_ring_itemsize);
4216
4217 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
4218
4219 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4220 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4221 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
4222 radeon_emit(cs, va >> 8);
4223 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
4224 } else {
4225 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
4226 radeon_emit(cs, va >> 8);
4227 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
4228 }
4229
4230 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
4231 radeon_emit(cs, gs->config.rsrc1);
4232 radeon_emit(cs, gs->config.rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
4233
4234 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
4235 radeon_set_context_reg(ctx_cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
4236 } else {
4237 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
4238 radeon_emit(cs, va >> 8);
4239 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
4240 radeon_emit(cs, gs->config.rsrc1);
4241 radeon_emit(cs, gs->config.rsrc2);
4242 }
4243
4244 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, pipeline->gs_copy_shader);
4245 }
4246
4247 static void
4248 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
4249 struct radeon_cmdbuf *cs,
4250 struct radv_pipeline *pipeline)
4251 {
4252 struct radv_shader_variant *gs;
4253
4254 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
4255 if (!gs)
4256 return;
4257
4258 if (gs->info.is_ngg)
4259 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, gs);
4260 else
4261 radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs);
4262
4263 radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT,
4264 gs->info.gs.vertices_out);
4265 }
4266
4267 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade,
4268 bool explicit, bool float16)
4269 {
4270 uint32_t ps_input_cntl;
4271 if (offset <= AC_EXP_PARAM_OFFSET_31) {
4272 ps_input_cntl = S_028644_OFFSET(offset);
4273 if (flat_shade || explicit)
4274 ps_input_cntl |= S_028644_FLAT_SHADE(1);
4275 if (explicit) {
4276 /* Force parameter cache to be read in passthrough
4277 * mode.
4278 */
4279 ps_input_cntl |= S_028644_OFFSET(1 << 5);
4280 }
4281 if (float16) {
4282 ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) |
4283 S_028644_ATTR0_VALID(1);
4284 }
4285 } else {
4286 /* The input is a DEFAULT_VAL constant. */
4287 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
4288 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
4289 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
4290 ps_input_cntl = S_028644_OFFSET(0x20) |
4291 S_028644_DEFAULT_VAL(offset);
4292 }
4293 return ps_input_cntl;
4294 }
4295
4296 static void
4297 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
4298 struct radv_pipeline *pipeline)
4299 {
4300 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4301 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
4302 uint32_t ps_input_cntl[32];
4303
4304 unsigned ps_offset = 0;
4305
4306 if (ps->info.ps.prim_id_input) {
4307 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
4308 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4309 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4310 ++ps_offset;
4311 }
4312 }
4313
4314 if (ps->info.ps.layer_input ||
4315 ps->info.needs_multiview_view_index) {
4316 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
4317 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4318 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4319 else
4320 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false, false);
4321 ++ps_offset;
4322 }
4323
4324 if (ps->info.ps.viewport_index_input) {
4325 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VIEWPORT];
4326 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4327 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4328 else
4329 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false, false);
4330 ++ps_offset;
4331 }
4332
4333 if (ps->info.ps.has_pcoord) {
4334 unsigned val;
4335 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4336 ps_input_cntl[ps_offset] = val;
4337 ps_offset++;
4338 }
4339
4340 if (ps->info.ps.num_input_clips_culls) {
4341 unsigned vs_offset;
4342
4343 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
4344 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4345 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false, false);
4346 ++ps_offset;
4347 }
4348
4349 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
4350 if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
4351 ps->info.ps.num_input_clips_culls > 4) {
4352 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false, false);
4353 ++ps_offset;
4354 }
4355 }
4356
4357 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.ps.input_mask; ++i) {
4358 unsigned vs_offset;
4359 bool flat_shade;
4360 bool explicit;
4361 bool float16;
4362 if (!(ps->info.ps.input_mask & (1u << i)))
4363 continue;
4364
4365 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
4366 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
4367 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
4368 ++ps_offset;
4369 continue;
4370 }
4371
4372 flat_shade = !!(ps->info.ps.flat_shaded_mask & (1u << ps_offset));
4373 explicit = !!(ps->info.ps.explicit_shaded_mask & (1u << ps_offset));
4374 float16 = !!(ps->info.ps.float16_shaded_mask & (1u << ps_offset));
4375
4376 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade, explicit, float16);
4377 ++ps_offset;
4378 }
4379
4380 if (ps_offset) {
4381 radeon_set_context_reg_seq(ctx_cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
4382 for (unsigned i = 0; i < ps_offset; i++) {
4383 radeon_emit(ctx_cs, ps_input_cntl[i]);
4384 }
4385 }
4386 }
4387
4388 static uint32_t
4389 radv_compute_db_shader_control(const struct radv_device *device,
4390 const struct radv_pipeline *pipeline,
4391 const struct radv_shader_variant *ps)
4392 {
4393 unsigned conservative_z_export = V_02880C_EXPORT_ANY_Z;
4394 unsigned z_order;
4395 if (ps->info.ps.early_fragment_test || !ps->info.ps.writes_memory)
4396 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
4397 else
4398 z_order = V_02880C_LATE_Z;
4399
4400 if (ps->info.ps.depth_layout == FRAG_DEPTH_LAYOUT_GREATER)
4401 conservative_z_export = V_02880C_EXPORT_GREATER_THAN_Z;
4402 else if (ps->info.ps.depth_layout == FRAG_DEPTH_LAYOUT_LESS)
4403 conservative_z_export = V_02880C_EXPORT_LESS_THAN_Z;
4404
4405 bool disable_rbplus = device->physical_device->rad_info.has_rbplus &&
4406 !device->physical_device->rad_info.rbplus_allowed;
4407
4408 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4409 * but this appears to break Project Cars (DXVK). See
4410 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4411 */
4412 bool mask_export_enable = ps->info.ps.writes_sample_mask;
4413
4414 return S_02880C_Z_EXPORT_ENABLE(ps->info.ps.writes_z) |
4415 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.ps.writes_stencil) |
4416 S_02880C_KILL_ENABLE(!!ps->info.ps.can_discard) |
4417 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
4418 S_02880C_CONSERVATIVE_Z_EXPORT(conservative_z_export) |
4419 S_02880C_Z_ORDER(z_order) |
4420 S_02880C_DEPTH_BEFORE_SHADER(ps->info.ps.early_fragment_test) |
4421 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps->info.ps.post_depth_coverage) |
4422 S_02880C_EXEC_ON_HIER_FAIL(ps->info.ps.writes_memory) |
4423 S_02880C_EXEC_ON_NOOP(ps->info.ps.writes_memory) |
4424 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
4425 }
4426
4427 static void
4428 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs,
4429 struct radeon_cmdbuf *cs,
4430 struct radv_pipeline *pipeline)
4431 {
4432 struct radv_shader_variant *ps;
4433 uint64_t va;
4434 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
4435
4436 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4437 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
4438
4439 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
4440 radeon_emit(cs, va >> 8);
4441 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
4442 radeon_emit(cs, ps->config.rsrc1);
4443 radeon_emit(cs, ps->config.rsrc2);
4444
4445 radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL,
4446 radv_compute_db_shader_control(pipeline->device,
4447 pipeline, ps));
4448
4449 radeon_set_context_reg(ctx_cs, R_0286CC_SPI_PS_INPUT_ENA,
4450 ps->config.spi_ps_input_ena);
4451
4452 radeon_set_context_reg(ctx_cs, R_0286D0_SPI_PS_INPUT_ADDR,
4453 ps->config.spi_ps_input_addr);
4454
4455 radeon_set_context_reg(ctx_cs, R_0286D8_SPI_PS_IN_CONTROL,
4456 S_0286D8_NUM_INTERP(ps->info.ps.num_interp) |
4457 S_0286D8_PS_W32_EN(ps->info.wave_size == 32));
4458
4459 radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
4460
4461 radeon_set_context_reg(ctx_cs, R_028710_SPI_SHADER_Z_FORMAT,
4462 ac_get_spi_shader_z_format(ps->info.ps.writes_z,
4463 ps->info.ps.writes_stencil,
4464 ps->info.ps.writes_sample_mask));
4465
4466 if (pipeline->device->dfsm_allowed) {
4467 /* optimise this? */
4468 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4469 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
4470 }
4471 }
4472
4473 static void
4474 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs,
4475 struct radv_pipeline *pipeline)
4476 {
4477 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4478 pipeline->device->physical_device->rad_info.chip_class >= GFX10)
4479 return;
4480
4481 unsigned vtx_reuse_depth = 30;
4482 if (radv_pipeline_has_tess(pipeline) &&
4483 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
4484 vtx_reuse_depth = 14;
4485 }
4486 radeon_set_context_reg(ctx_cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
4487 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
4488 }
4489
4490 static uint32_t
4491 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
4492 {
4493 uint32_t stages = 0;
4494 if (radv_pipeline_has_tess(pipeline)) {
4495 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
4496 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4497
4498 if (radv_pipeline_has_gs(pipeline))
4499 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
4500 S_028B54_GS_EN(1);
4501 else if (radv_pipeline_has_ngg(pipeline))
4502 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
4503 else
4504 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
4505 } else if (radv_pipeline_has_gs(pipeline)) {
4506 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
4507 S_028B54_GS_EN(1);
4508 } else if (radv_pipeline_has_ngg(pipeline)) {
4509 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
4510 }
4511
4512 if (radv_pipeline_has_ngg(pipeline)) {
4513 stages |= S_028B54_PRIMGEN_EN(1);
4514 if (pipeline->streamout_shader)
4515 stages |= S_028B54_NGG_WAVE_ID_EN(1);
4516 if (radv_pipeline_has_ngg_passthrough(pipeline))
4517 stages |= S_028B54_PRIMGEN_PASSTHRU_EN(1);
4518 } else if (radv_pipeline_has_gs(pipeline)) {
4519 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
4520 }
4521
4522 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
4523 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4524
4525 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4526 uint8_t hs_size = 64, gs_size = 64, vs_size = 64;
4527
4528 if (radv_pipeline_has_tess(pipeline))
4529 hs_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.wave_size;
4530
4531 if (pipeline->shaders[MESA_SHADER_GEOMETRY]) {
4532 vs_size = gs_size = pipeline->shaders[MESA_SHADER_GEOMETRY]->info.wave_size;
4533 if (pipeline->gs_copy_shader)
4534 vs_size = pipeline->gs_copy_shader->info.wave_size;
4535 } else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
4536 vs_size = pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.wave_size;
4537 else if (pipeline->shaders[MESA_SHADER_VERTEX])
4538 vs_size = pipeline->shaders[MESA_SHADER_VERTEX]->info.wave_size;
4539
4540 if (radv_pipeline_has_ngg(pipeline))
4541 gs_size = vs_size;
4542
4543 /* legacy GS only supports Wave64 */
4544 stages |= S_028B54_HS_W32_EN(hs_size == 32 ? 1 : 0) |
4545 S_028B54_GS_W32_EN(gs_size == 32 ? 1 : 0) |
4546 S_028B54_VS_W32_EN(vs_size == 32 ? 1 : 0);
4547 }
4548
4549 return stages;
4550 }
4551
4552 static uint32_t
4553 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
4554 {
4555 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
4556 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
4557
4558 if (!discard_rectangle_info)
4559 return 0xffff;
4560
4561 unsigned mask = 0;
4562
4563 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
4564 /* Interpret i as a bitmask, and then set the bit in the mask if
4565 * that combination of rectangles in which the pixel is contained
4566 * should pass the cliprect test. */
4567 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
4568
4569 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
4570 !relevant_subset)
4571 continue;
4572
4573 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
4574 relevant_subset)
4575 continue;
4576
4577 mask |= 1u << i;
4578 }
4579
4580 return mask;
4581 }
4582
4583 static void
4584 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf *ctx_cs,
4585 struct radv_pipeline *pipeline,
4586 const struct radv_tessellation_state *tess)
4587 {
4588 bool break_wave_at_eoi = false;
4589 unsigned primgroup_size;
4590 unsigned vertgroup_size = 256; /* 256 = disable vertex grouping */
4591
4592 if (radv_pipeline_has_tess(pipeline)) {
4593 primgroup_size = tess->num_patches; /* must be a multiple of NUM_PATCHES */
4594 } else if (radv_pipeline_has_gs(pipeline)) {
4595 const struct gfx9_gs_info *gs_state =
4596 &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs_ring_info;
4597 unsigned vgt_gs_onchip_cntl = gs_state->vgt_gs_onchip_cntl;
4598 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
4599 } else {
4600 primgroup_size = 128; /* recommended without a GS and tess */
4601 }
4602
4603 if (radv_pipeline_has_tess(pipeline)) {
4604 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4605 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4606 break_wave_at_eoi = true;
4607 }
4608
4609 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL,
4610 S_03096C_PRIM_GRP_SIZE(primgroup_size) |
4611 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
4612 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4613 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi));
4614 }
4615
4616 static void
4617 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
4618 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4619 const struct radv_graphics_pipeline_create_info *extra,
4620 const struct radv_blend_state *blend,
4621 const struct radv_tessellation_state *tess,
4622 unsigned prim, unsigned gs_out)
4623 {
4624 struct radeon_cmdbuf *ctx_cs = &pipeline->ctx_cs;
4625 struct radeon_cmdbuf *cs = &pipeline->cs;
4626
4627 cs->max_dw = 64;
4628 ctx_cs->max_dw = 256;
4629 cs->buf = malloc(4 * (cs->max_dw + ctx_cs->max_dw));
4630 ctx_cs->buf = cs->buf + cs->max_dw;
4631
4632 radv_pipeline_generate_depth_stencil_state(ctx_cs, pipeline, pCreateInfo, extra);
4633 radv_pipeline_generate_blend_state(ctx_cs, pipeline, blend);
4634 radv_pipeline_generate_raster_state(ctx_cs, pipeline, pCreateInfo);
4635 radv_pipeline_generate_multisample_state(ctx_cs, pipeline);
4636 radv_pipeline_generate_vgt_gs_mode(ctx_cs, pipeline);
4637 radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline, tess);
4638 radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline, tess);
4639 radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline);
4640 radv_pipeline_generate_fragment_shader(ctx_cs, cs, pipeline);
4641 radv_pipeline_generate_ps_inputs(ctx_cs, pipeline);
4642 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline);
4643 radv_pipeline_generate_binning_state(ctx_cs, pipeline, pCreateInfo, blend);
4644
4645 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && !radv_pipeline_has_ngg(pipeline))
4646 gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline, tess);
4647
4648 radeon_set_context_reg(ctx_cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
4649
4650 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
4651 radeon_set_uconfig_reg_idx(pipeline->device->physical_device,
4652 cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
4653 } else {
4654 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
4655 }
4656 radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
4657
4658 radeon_set_context_reg(ctx_cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
4659
4660 pipeline->ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4);
4661
4662 assert(ctx_cs->cdw <= ctx_cs->max_dw);
4663 assert(cs->cdw <= cs->max_dw);
4664 }
4665
4666 static struct radv_ia_multi_vgt_param_helpers
4667 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
4668 const struct radv_tessellation_state *tess,
4669 uint32_t prim)
4670 {
4671 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
4672 const struct radv_device *device = pipeline->device;
4673
4674 if (radv_pipeline_has_tess(pipeline))
4675 ia_multi_vgt_param.primgroup_size = tess->num_patches;
4676 else if (radv_pipeline_has_gs(pipeline))
4677 ia_multi_vgt_param.primgroup_size = 64;
4678 else
4679 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
4680
4681 /* GS requirement. */
4682 ia_multi_vgt_param.partial_es_wave = false;
4683 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= GFX8)
4684 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
4685 ia_multi_vgt_param.partial_es_wave = true;
4686
4687 ia_multi_vgt_param.wd_switch_on_eop = false;
4688 if (device->physical_device->rad_info.chip_class >= GFX7) {
4689 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
4690 * 4 shader engines. Set 1 to pass the assertion below.
4691 * The other cases are hardware requirements. */
4692 if (device->physical_device->rad_info.max_se < 4 ||
4693 prim == V_008958_DI_PT_POLYGON ||
4694 prim == V_008958_DI_PT_LINELOOP ||
4695 prim == V_008958_DI_PT_TRIFAN ||
4696 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
4697 (pipeline->graphics.prim_restart_enable &&
4698 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4699 (prim != V_008958_DI_PT_POINTLIST &&
4700 prim != V_008958_DI_PT_LINESTRIP))))
4701 ia_multi_vgt_param.wd_switch_on_eop = true;
4702 }
4703
4704 ia_multi_vgt_param.ia_switch_on_eoi = false;
4705 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input)
4706 ia_multi_vgt_param.ia_switch_on_eoi = true;
4707 if (radv_pipeline_has_gs(pipeline) &&
4708 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.uses_prim_id)
4709 ia_multi_vgt_param.ia_switch_on_eoi = true;
4710 if (radv_pipeline_has_tess(pipeline)) {
4711 /* SWITCH_ON_EOI must be set if PrimID is used. */
4712 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4713 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4714 ia_multi_vgt_param.ia_switch_on_eoi = true;
4715 }
4716
4717 ia_multi_vgt_param.partial_vs_wave = false;
4718 if (radv_pipeline_has_tess(pipeline)) {
4719 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4720 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
4721 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
4722 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
4723 radv_pipeline_has_gs(pipeline))
4724 ia_multi_vgt_param.partial_vs_wave = true;
4725 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4726 if (device->physical_device->rad_info.has_distributed_tess) {
4727 if (radv_pipeline_has_gs(pipeline)) {
4728 if (device->physical_device->rad_info.chip_class <= GFX8)
4729 ia_multi_vgt_param.partial_es_wave = true;
4730 } else {
4731 ia_multi_vgt_param.partial_vs_wave = true;
4732 }
4733 }
4734 }
4735
4736 /* Workaround for a VGT hang when strip primitive types are used with
4737 * primitive restart.
4738 */
4739 if (pipeline->graphics.prim_restart_enable &&
4740 (prim == V_008958_DI_PT_LINESTRIP ||
4741 prim == V_008958_DI_PT_TRISTRIP ||
4742 prim == V_008958_DI_PT_LINESTRIP_ADJ ||
4743 prim == V_008958_DI_PT_TRISTRIP_ADJ)) {
4744 ia_multi_vgt_param.partial_vs_wave = true;
4745 }
4746
4747 if (radv_pipeline_has_gs(pipeline)) {
4748 /* On these chips there is the possibility of a hang if the
4749 * pipeline uses a GS and partial_vs_wave is not set.
4750 *
4751 * This mostly does not hit 4-SE chips, as those typically set
4752 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4753 * with GS due to another workaround.
4754 *
4755 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4756 */
4757 if (device->physical_device->rad_info.family == CHIP_TONGA ||
4758 device->physical_device->rad_info.family == CHIP_FIJI ||
4759 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
4760 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
4761 device->physical_device->rad_info.family == CHIP_POLARIS12 ||
4762 device->physical_device->rad_info.family == CHIP_VEGAM) {
4763 ia_multi_vgt_param.partial_vs_wave = true;
4764 }
4765 }
4766
4767 ia_multi_vgt_param.base =
4768 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
4769 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4770 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == GFX8 ? 2 : 0) |
4771 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
4772 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
4773
4774 return ia_multi_vgt_param;
4775 }
4776
4777
4778 static void
4779 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
4780 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4781 {
4782 const VkPipelineVertexInputStateCreateInfo *vi_info =
4783 pCreateInfo->pVertexInputState;
4784 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
4785
4786 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
4787 const VkVertexInputAttributeDescription *desc =
4788 &vi_info->pVertexAttributeDescriptions[i];
4789 unsigned loc = desc->location;
4790 const struct vk_format_description *format_desc;
4791
4792 format_desc = vk_format_description(desc->format);
4793
4794 velems->format_size[loc] = format_desc->block.bits / 8;
4795 }
4796
4797 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
4798 const VkVertexInputBindingDescription *desc =
4799 &vi_info->pVertexBindingDescriptions[i];
4800
4801 pipeline->binding_stride[desc->binding] = desc->stride;
4802 pipeline->num_vertex_bindings =
4803 MAX2(pipeline->num_vertex_bindings, desc->binding + 1);
4804 }
4805 }
4806
4807 static struct radv_shader_variant *
4808 radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline)
4809 {
4810 int i;
4811
4812 for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) {
4813 struct radv_shader_variant *shader =
4814 radv_get_shader(pipeline, i);
4815
4816 if (shader && shader->info.so.num_outputs > 0)
4817 return shader;
4818 }
4819
4820 return NULL;
4821 }
4822
4823 static VkResult
4824 radv_secure_compile(struct radv_pipeline *pipeline,
4825 struct radv_device *device,
4826 const struct radv_pipeline_key *key,
4827 const VkPipelineShaderStageCreateInfo **pStages,
4828 const VkPipelineCreateFlags flags,
4829 unsigned num_stages)
4830 {
4831 uint8_t allowed_pipeline_hashes[2][20];
4832 radv_hash_shaders(allowed_pipeline_hashes[0], pStages,
4833 pipeline->layout, key, get_hash_flags(device));
4834
4835 /* Generate the GC copy hash */
4836 memcpy(allowed_pipeline_hashes[1], allowed_pipeline_hashes[0], 20);
4837 allowed_pipeline_hashes[1][0] ^= 1;
4838
4839 uint8_t allowed_hashes[2][20];
4840 for (unsigned i = 0; i < 2; ++i) {
4841 disk_cache_compute_key(device->physical_device->disk_cache,
4842 allowed_pipeline_hashes[i], 20,
4843 allowed_hashes[i]);
4844 }
4845
4846 /* Do an early exit if all cache entries are already there. */
4847 bool may_need_copy_shader = pStages[MESA_SHADER_GEOMETRY];
4848 void *main_entry = disk_cache_get(device->physical_device->disk_cache, allowed_hashes[0], NULL);
4849 void *copy_entry = NULL;
4850 if (may_need_copy_shader)
4851 copy_entry = disk_cache_get(device->physical_device->disk_cache, allowed_hashes[1], NULL);
4852
4853 bool has_all_cache_entries = main_entry && (!may_need_copy_shader || copy_entry);
4854 free(main_entry);
4855 free(copy_entry);
4856
4857 if(has_all_cache_entries)
4858 return VK_SUCCESS;
4859
4860 unsigned process = 0;
4861 uint8_t sc_threads = device->instance->num_sc_threads;
4862 while (true) {
4863 mtx_lock(&device->sc_state->secure_compile_mutex);
4864 if (device->sc_state->secure_compile_thread_counter < sc_threads) {
4865 device->sc_state->secure_compile_thread_counter++;
4866 for (unsigned i = 0; i < sc_threads; i++) {
4867 if (!device->sc_state->secure_compile_processes[i].in_use) {
4868 device->sc_state->secure_compile_processes[i].in_use = true;
4869 process = i;
4870 break;
4871 }
4872 }
4873 mtx_unlock(&device->sc_state->secure_compile_mutex);
4874 break;
4875 }
4876 mtx_unlock(&device->sc_state->secure_compile_mutex);
4877 }
4878
4879 int fd_secure_input = device->sc_state->secure_compile_processes[process].fd_secure_input;
4880 int fd_secure_output = device->sc_state->secure_compile_processes[process].fd_secure_output;
4881
4882 /* Fork a copy of the slim untainted secure compile process */
4883 enum radv_secure_compile_type sc_type = RADV_SC_TYPE_FORK_DEVICE;
4884 write(fd_secure_input, &sc_type, sizeof(sc_type));
4885
4886 if (!radv_sc_read(fd_secure_output, &sc_type, sizeof(sc_type), true) ||
4887 sc_type != RADV_SC_TYPE_INIT_SUCCESS)
4888 return VK_ERROR_DEVICE_LOST;
4889
4890 fd_secure_input = device->sc_state->secure_compile_processes[process].fd_server;
4891 fd_secure_output = device->sc_state->secure_compile_processes[process].fd_client;
4892
4893 /* Write pipeline / shader module out to secure process via pipe */
4894 sc_type = RADV_SC_TYPE_COMPILE_PIPELINE;
4895 write(fd_secure_input, &sc_type, sizeof(sc_type));
4896
4897 /* Write pipeline layout out to secure process */
4898 struct radv_pipeline_layout *layout = pipeline->layout;
4899 write(fd_secure_input, layout, sizeof(struct radv_pipeline_layout));
4900 write(fd_secure_input, &layout->num_sets, sizeof(uint32_t));
4901 for (uint32_t set = 0; set < layout->num_sets; set++) {
4902 write(fd_secure_input, &layout->set[set].layout->layout_size, sizeof(uint32_t));
4903 write(fd_secure_input, layout->set[set].layout, layout->set[set].layout->layout_size);
4904 }
4905
4906 /* Write pipeline key out to secure process */
4907 write(fd_secure_input, key, sizeof(struct radv_pipeline_key));
4908
4909 /* Write pipeline create flags out to secure process */
4910 write(fd_secure_input, &flags, sizeof(VkPipelineCreateFlags));
4911
4912 /* Write stage and shader information out to secure process */
4913 write(fd_secure_input, &num_stages, sizeof(uint32_t));
4914 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
4915 if (!pStages[i])
4916 continue;
4917
4918 /* Write stage out to secure process */
4919 gl_shader_stage stage = ffs(pStages[i]->stage) - 1;
4920 write(fd_secure_input, &stage, sizeof(gl_shader_stage));
4921
4922 /* Write entry point name out to secure process */
4923 size_t name_size = strlen(pStages[i]->pName) + 1;
4924 write(fd_secure_input, &name_size, sizeof(size_t));
4925 write(fd_secure_input, pStages[i]->pName, name_size);
4926
4927 /* Write shader module out to secure process */
4928 struct radv_shader_module *module = radv_shader_module_from_handle(pStages[i]->module);
4929 assert(!module->nir);
4930 size_t module_size = sizeof(struct radv_shader_module) + module->size;
4931 write(fd_secure_input, &module_size, sizeof(size_t));
4932 write(fd_secure_input, module, module_size);
4933
4934 /* Write specialization info out to secure process */
4935 const VkSpecializationInfo *specInfo = pStages[i]->pSpecializationInfo;
4936 bool has_spec_info = specInfo ? true : false;
4937 write(fd_secure_input, &has_spec_info, sizeof(bool));
4938 if (specInfo) {
4939 write(fd_secure_input, &specInfo->dataSize, sizeof(size_t));
4940 write(fd_secure_input, specInfo->pData, specInfo->dataSize);
4941
4942 write(fd_secure_input, &specInfo->mapEntryCount, sizeof(uint32_t));
4943 for (uint32_t j = 0; j < specInfo->mapEntryCount; j++)
4944 write(fd_secure_input, &specInfo->pMapEntries[j], sizeof(VkSpecializationMapEntry));
4945 }
4946 }
4947
4948 /* Read the data returned from the secure process */
4949 while (sc_type != RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED) {
4950 if (!radv_sc_read(fd_secure_output, &sc_type, sizeof(sc_type), true))
4951 return VK_ERROR_DEVICE_LOST;
4952
4953 if (sc_type == RADV_SC_TYPE_WRITE_DISK_CACHE) {
4954 assert(device->physical_device->disk_cache);
4955
4956 uint8_t disk_sha1[20];
4957 if (!radv_sc_read(fd_secure_output, disk_sha1, sizeof(uint8_t) * 20, true))
4958 return VK_ERROR_DEVICE_LOST;
4959
4960 if (memcmp(disk_sha1, allowed_hashes[0], 20) &&
4961 memcmp(disk_sha1, allowed_hashes[1], 20))
4962 return VK_ERROR_DEVICE_LOST;
4963
4964 uint32_t entry_size;
4965 if (!radv_sc_read(fd_secure_output, &entry_size, sizeof(uint32_t), true))
4966 return VK_ERROR_DEVICE_LOST;
4967
4968 struct cache_entry *entry = malloc(entry_size);
4969 if (!radv_sc_read(fd_secure_output, entry, entry_size, true))
4970 return VK_ERROR_DEVICE_LOST;
4971
4972 disk_cache_put(device->physical_device->disk_cache,
4973 disk_sha1, entry, entry_size,
4974 NULL);
4975
4976 free(entry);
4977 } else if (sc_type == RADV_SC_TYPE_READ_DISK_CACHE) {
4978 uint8_t disk_sha1[20];
4979 if (!radv_sc_read(fd_secure_output, disk_sha1, sizeof(uint8_t) * 20, true))
4980 return VK_ERROR_DEVICE_LOST;
4981
4982 if (memcmp(disk_sha1, allowed_hashes[0], 20) &&
4983 memcmp(disk_sha1, allowed_hashes[1], 20))
4984 return VK_ERROR_DEVICE_LOST;
4985
4986 size_t size;
4987 struct cache_entry *entry = (struct cache_entry *)
4988 disk_cache_get(device->physical_device->disk_cache,
4989 disk_sha1, &size);
4990
4991 uint8_t found = entry ? 1 : 0;
4992 write(fd_secure_input, &found, sizeof(uint8_t));
4993
4994 if (found) {
4995 write(fd_secure_input, &size, sizeof(size_t));
4996 write(fd_secure_input, entry, size);
4997 }
4998
4999 free(entry);
5000 }
5001 }
5002
5003 sc_type = RADV_SC_TYPE_DESTROY_DEVICE;
5004 write(fd_secure_input, &sc_type, sizeof(sc_type));
5005
5006 mtx_lock(&device->sc_state->secure_compile_mutex);
5007 device->sc_state->secure_compile_thread_counter--;
5008 device->sc_state->secure_compile_processes[process].in_use = false;
5009 mtx_unlock(&device->sc_state->secure_compile_mutex);
5010
5011 return VK_SUCCESS;
5012 }
5013
5014 static VkResult
5015 radv_pipeline_init(struct radv_pipeline *pipeline,
5016 struct radv_device *device,
5017 struct radv_pipeline_cache *cache,
5018 const VkGraphicsPipelineCreateInfo *pCreateInfo,
5019 const struct radv_graphics_pipeline_create_info *extra)
5020 {
5021 VkResult result;
5022 bool has_view_index = false;
5023
5024 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
5025 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
5026 if (subpass->view_mask)
5027 has_view_index = true;
5028
5029 pipeline->device = device;
5030 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
5031 assert(pipeline->layout);
5032
5033 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
5034
5035 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
5036 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
5037 radv_init_feedback(creation_feedback);
5038
5039 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
5040
5041 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
5042 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
5043 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
5044 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
5045 pStages[stage] = &pCreateInfo->pStages[i];
5046 if(creation_feedback)
5047 stage_feedbacks[stage] = &creation_feedback->pPipelineStageCreationFeedbacks[i];
5048 }
5049
5050 struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index);
5051 if (radv_device_use_secure_compile(device->instance)) {
5052 return radv_secure_compile(pipeline, device, &key, pStages, pCreateInfo->flags, pCreateInfo->stageCount);
5053 } else {
5054 result = radv_create_shaders(pipeline, device, cache, &key, pStages,
5055 pCreateInfo->flags, pipeline_feedback,
5056 stage_feedbacks);
5057 if (result != VK_SUCCESS)
5058 return result;
5059 }
5060
5061 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
5062 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
5063 uint32_t gs_out;
5064 uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
5065
5066 pipeline->graphics.topology = pCreateInfo->pInputAssemblyState->topology;
5067 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
5068
5069 if (radv_pipeline_has_gs(pipeline)) {
5070 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
5071 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
5072 } else if (radv_pipeline_has_tess(pipeline)) {
5073 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode)
5074 gs_out = V_028A6C_OUTPRIM_TYPE_POINTLIST;
5075 else
5076 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.primitive_mode);
5077 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
5078 } else {
5079 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
5080 }
5081 if (extra && extra->use_rectlist) {
5082 prim = V_008958_DI_PT_RECTLIST;
5083 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
5084 pipeline->graphics.can_use_guardband = true;
5085 if (radv_pipeline_has_ngg(pipeline))
5086 gs_out = V_028A6C_VGT_OUT_RECT_V0;
5087 }
5088 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
5089 /* prim vertex count will need TESS changes */
5090 pipeline->graphics.prim_vertex_count = prim_size_table[prim];
5091
5092 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
5093
5094 /* Ensure that some export memory is always allocated, for two reasons:
5095 *
5096 * 1) Correctness: The hardware ignores the EXEC mask if no export
5097 * memory is allocated, so KILL and alpha test do not work correctly
5098 * without this.
5099 * 2) Performance: Every shader needs at least a NULL export, even when
5100 * it writes no color/depth output. The NULL export instruction
5101 * stalls without this setting.
5102 *
5103 * Don't add this to CB_SHADER_MASK.
5104 *
5105 * GFX10 supports pixel shaders without exports by setting both the
5106 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
5107 * instructions if any are present.
5108 */
5109 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
5110 if ((pipeline->device->physical_device->rad_info.chip_class <= GFX9 ||
5111 ps->info.ps.can_discard) &&
5112 !blend.spi_shader_col_format) {
5113 if (!ps->info.ps.writes_z &&
5114 !ps->info.ps.writes_stencil &&
5115 !ps->info.ps.writes_sample_mask)
5116 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
5117 }
5118
5119 blend.cb_shader_mask = ps->info.ps.cb_shader_mask;
5120
5121 if (extra &&
5122 (extra->custom_blend_mode == V_028808_CB_ELIMINATE_FAST_CLEAR ||
5123 extra->custom_blend_mode == V_028808_CB_FMASK_DECOMPRESS ||
5124 extra->custom_blend_mode == V_028808_CB_DCC_DECOMPRESS ||
5125 extra->custom_blend_mode == V_028808_CB_RESOLVE)) {
5126 /* According to the CB spec states, CB_SHADER_MASK should be
5127 * set to enable writes to all four channels of MRT0.
5128 */
5129 blend.cb_shader_mask = 0xf;
5130 }
5131
5132 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
5133 if (pipeline->shaders[i]) {
5134 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
5135 }
5136 }
5137
5138 if (radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
5139 struct radv_shader_variant *gs =
5140 pipeline->shaders[MESA_SHADER_GEOMETRY];
5141
5142 calculate_gs_ring_sizes(pipeline, &gs->info.gs_ring_info);
5143 }
5144
5145 struct radv_tessellation_state tess = {0};
5146 if (radv_pipeline_has_tess(pipeline)) {
5147 if (prim == V_008958_DI_PT_PATCH) {
5148 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
5149 pipeline->graphics.prim_vertex_count.incr = 1;
5150 }
5151 tess = calculate_tess_state(pipeline, pCreateInfo);
5152 }
5153
5154 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim);
5155
5156 radv_compute_vertex_input_state(pipeline, pCreateInfo);
5157
5158 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
5159 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
5160
5161 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
5162 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
5163 if (loc->sgpr_idx != -1) {
5164 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
5165 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
5166 if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id)
5167 pipeline->graphics.vtx_emit_num = 3;
5168 else
5169 pipeline->graphics.vtx_emit_num = 2;
5170 }
5171
5172 /* Find the last vertex shader stage that eventually uses streamout. */
5173 pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline);
5174
5175 result = radv_pipeline_scratch_init(device, pipeline);
5176 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, prim, gs_out);
5177
5178 return result;
5179 }
5180
5181 VkResult
5182 radv_graphics_pipeline_create(
5183 VkDevice _device,
5184 VkPipelineCache _cache,
5185 const VkGraphicsPipelineCreateInfo *pCreateInfo,
5186 const struct radv_graphics_pipeline_create_info *extra,
5187 const VkAllocationCallbacks *pAllocator,
5188 VkPipeline *pPipeline)
5189 {
5190 RADV_FROM_HANDLE(radv_device, device, _device);
5191 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
5192 struct radv_pipeline *pipeline;
5193 VkResult result;
5194
5195 pipeline = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8,
5196 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5197 if (pipeline == NULL)
5198 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5199
5200 vk_object_base_init(&device->vk, &pipeline->base,
5201 VK_OBJECT_TYPE_PIPELINE);
5202
5203 result = radv_pipeline_init(pipeline, device, cache,
5204 pCreateInfo, extra);
5205 if (result != VK_SUCCESS) {
5206 radv_pipeline_destroy(device, pipeline, pAllocator);
5207 return result;
5208 }
5209
5210 *pPipeline = radv_pipeline_to_handle(pipeline);
5211
5212 return VK_SUCCESS;
5213 }
5214
5215 VkResult radv_CreateGraphicsPipelines(
5216 VkDevice _device,
5217 VkPipelineCache pipelineCache,
5218 uint32_t count,
5219 const VkGraphicsPipelineCreateInfo* pCreateInfos,
5220 const VkAllocationCallbacks* pAllocator,
5221 VkPipeline* pPipelines)
5222 {
5223 VkResult result = VK_SUCCESS;
5224 unsigned i = 0;
5225
5226 for (; i < count; i++) {
5227 VkResult r;
5228 r = radv_graphics_pipeline_create(_device,
5229 pipelineCache,
5230 &pCreateInfos[i],
5231 NULL, pAllocator, &pPipelines[i]);
5232 if (r != VK_SUCCESS) {
5233 result = r;
5234 pPipelines[i] = VK_NULL_HANDLE;
5235
5236 if (pCreateInfos[i].flags & VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT)
5237 break;
5238 }
5239 }
5240
5241 for (; i < count; ++i)
5242 pPipelines[i] = VK_NULL_HANDLE;
5243
5244 return result;
5245 }
5246
5247
5248 static void
5249 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
5250 {
5251 struct radv_shader_variant *compute_shader;
5252 struct radv_device *device = pipeline->device;
5253 unsigned threads_per_threadgroup;
5254 unsigned threadgroups_per_cu = 1;
5255 unsigned waves_per_threadgroup;
5256 unsigned max_waves_per_sh = 0;
5257 uint64_t va;
5258
5259 pipeline->cs.max_dw = device->physical_device->rad_info.chip_class >= GFX10 ? 22 : 20;
5260 pipeline->cs.buf = malloc(pipeline->cs.max_dw * 4);
5261
5262 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5263 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
5264
5265 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
5266 radeon_emit(&pipeline->cs, va >> 8);
5267 radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40));
5268
5269 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
5270 radeon_emit(&pipeline->cs, compute_shader->config.rsrc1);
5271 radeon_emit(&pipeline->cs, compute_shader->config.rsrc2);
5272 if (device->physical_device->rad_info.chip_class >= GFX10) {
5273 radeon_set_sh_reg(&pipeline->cs, R_00B8A0_COMPUTE_PGM_RSRC3, compute_shader->config.rsrc3);
5274 }
5275
5276 /* Calculate best compute resource limits. */
5277 threads_per_threadgroup = compute_shader->info.cs.block_size[0] *
5278 compute_shader->info.cs.block_size[1] *
5279 compute_shader->info.cs.block_size[2];
5280 waves_per_threadgroup = DIV_ROUND_UP(threads_per_threadgroup,
5281 compute_shader->info.wave_size);
5282
5283 if (device->physical_device->rad_info.chip_class >= GFX10 &&
5284 waves_per_threadgroup == 1)
5285 threadgroups_per_cu = 2;
5286
5287 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
5288 ac_get_compute_resource_limits(&device->physical_device->rad_info,
5289 waves_per_threadgroup,
5290 max_waves_per_sh,
5291 threadgroups_per_cu));
5292
5293 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5294 radeon_emit(&pipeline->cs,
5295 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
5296 radeon_emit(&pipeline->cs,
5297 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
5298 radeon_emit(&pipeline->cs,
5299 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
5300
5301 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
5302 }
5303
5304 static struct radv_pipeline_key
5305 radv_generate_compute_pipeline_key(struct radv_pipeline *pipeline,
5306 const VkComputePipelineCreateInfo *pCreateInfo)
5307 {
5308 const VkPipelineShaderStageCreateInfo *stage = &pCreateInfo->stage;
5309 struct radv_pipeline_key key;
5310 memset(&key, 0, sizeof(key));
5311
5312 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
5313 key.optimisations_disabled = 1;
5314
5315 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT *subgroup_size =
5316 vk_find_struct_const(stage->pNext,
5317 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT);
5318
5319 if (subgroup_size) {
5320 assert(subgroup_size->requiredSubgroupSize == 32 ||
5321 subgroup_size->requiredSubgroupSize == 64);
5322 key.compute_subgroup_size = subgroup_size->requiredSubgroupSize;
5323 }
5324
5325 return key;
5326 }
5327
5328 static VkResult radv_compute_pipeline_create(
5329 VkDevice _device,
5330 VkPipelineCache _cache,
5331 const VkComputePipelineCreateInfo* pCreateInfo,
5332 const VkAllocationCallbacks* pAllocator,
5333 VkPipeline* pPipeline)
5334 {
5335 RADV_FROM_HANDLE(radv_device, device, _device);
5336 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
5337 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
5338 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
5339 struct radv_pipeline *pipeline;
5340 VkResult result;
5341
5342 pipeline = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8,
5343 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5344 if (pipeline == NULL)
5345 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5346
5347 vk_object_base_init(&device->vk, &pipeline->base,
5348 VK_OBJECT_TYPE_PIPELINE);
5349
5350 pipeline->device = device;
5351 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
5352 assert(pipeline->layout);
5353
5354 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
5355 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
5356 radv_init_feedback(creation_feedback);
5357
5358 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
5359 if (creation_feedback)
5360 stage_feedbacks[MESA_SHADER_COMPUTE] = &creation_feedback->pPipelineStageCreationFeedbacks[0];
5361
5362 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
5363
5364 struct radv_pipeline_key key =
5365 radv_generate_compute_pipeline_key(pipeline, pCreateInfo);
5366
5367 if (radv_device_use_secure_compile(device->instance)) {
5368 result = radv_secure_compile(pipeline, device, &key, pStages, pCreateInfo->flags, 1);
5369 *pPipeline = radv_pipeline_to_handle(pipeline);
5370
5371 return result;
5372 } else {
5373 result = radv_create_shaders(pipeline, device, cache, &key, pStages,
5374 pCreateInfo->flags, pipeline_feedback,
5375 stage_feedbacks);
5376 if (result != VK_SUCCESS) {
5377 radv_pipeline_destroy(device, pipeline, pAllocator);
5378 return result;
5379 }
5380 }
5381
5382 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
5383 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
5384 result = radv_pipeline_scratch_init(device, pipeline);
5385 if (result != VK_SUCCESS) {
5386 radv_pipeline_destroy(device, pipeline, pAllocator);
5387 return result;
5388 }
5389
5390 radv_compute_generate_pm4(pipeline);
5391
5392 *pPipeline = radv_pipeline_to_handle(pipeline);
5393
5394 return VK_SUCCESS;
5395 }
5396
5397 VkResult radv_CreateComputePipelines(
5398 VkDevice _device,
5399 VkPipelineCache pipelineCache,
5400 uint32_t count,
5401 const VkComputePipelineCreateInfo* pCreateInfos,
5402 const VkAllocationCallbacks* pAllocator,
5403 VkPipeline* pPipelines)
5404 {
5405 VkResult result = VK_SUCCESS;
5406
5407 unsigned i = 0;
5408 for (; i < count; i++) {
5409 VkResult r;
5410 r = radv_compute_pipeline_create(_device, pipelineCache,
5411 &pCreateInfos[i],
5412 pAllocator, &pPipelines[i]);
5413 if (r != VK_SUCCESS) {
5414 result = r;
5415 pPipelines[i] = VK_NULL_HANDLE;
5416
5417 if (pCreateInfos[i].flags & VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT)
5418 break;
5419 }
5420 }
5421
5422 for (; i < count; ++i)
5423 pPipelines[i] = VK_NULL_HANDLE;
5424
5425 return result;
5426 }
5427
5428
5429 static uint32_t radv_get_executable_count(const struct radv_pipeline *pipeline)
5430 {
5431 uint32_t ret = 0;
5432 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5433 if (!pipeline->shaders[i])
5434 continue;
5435
5436 if (i == MESA_SHADER_GEOMETRY &&
5437 !radv_pipeline_has_ngg(pipeline)) {
5438 ret += 2u;
5439 } else {
5440 ret += 1u;
5441 }
5442
5443 }
5444 return ret;
5445 }
5446
5447 static struct radv_shader_variant *
5448 radv_get_shader_from_executable_index(const struct radv_pipeline *pipeline, int index, gl_shader_stage *stage)
5449 {
5450 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5451 if (!pipeline->shaders[i])
5452 continue;
5453 if (!index) {
5454 *stage = i;
5455 return pipeline->shaders[i];
5456 }
5457
5458 --index;
5459
5460 if (i == MESA_SHADER_GEOMETRY &&
5461 !radv_pipeline_has_ngg(pipeline)) {
5462 if (!index) {
5463 *stage = i;
5464 return pipeline->gs_copy_shader;
5465 }
5466 --index;
5467 }
5468 }
5469
5470 *stage = -1;
5471 return NULL;
5472 }
5473
5474 /* Basically strlcpy (which does not exist on linux) specialized for
5475 * descriptions. */
5476 static void desc_copy(char *desc, const char *src) {
5477 int len = strlen(src);
5478 assert(len < VK_MAX_DESCRIPTION_SIZE);
5479 memcpy(desc, src, len);
5480 memset(desc + len, 0, VK_MAX_DESCRIPTION_SIZE - len);
5481 }
5482
5483 VkResult radv_GetPipelineExecutablePropertiesKHR(
5484 VkDevice _device,
5485 const VkPipelineInfoKHR* pPipelineInfo,
5486 uint32_t* pExecutableCount,
5487 VkPipelineExecutablePropertiesKHR* pProperties)
5488 {
5489 RADV_FROM_HANDLE(radv_pipeline, pipeline, pPipelineInfo->pipeline);
5490 const uint32_t total_count = radv_get_executable_count(pipeline);
5491
5492 if (!pProperties) {
5493 *pExecutableCount = total_count;
5494 return VK_SUCCESS;
5495 }
5496
5497 const uint32_t count = MIN2(total_count, *pExecutableCount);
5498 for (unsigned i = 0, executable_idx = 0;
5499 i < MESA_SHADER_STAGES && executable_idx < count; ++i) {
5500 if (!pipeline->shaders[i])
5501 continue;
5502 pProperties[executable_idx].stages = mesa_to_vk_shader_stage(i);
5503 const char *name = NULL;
5504 const char *description = NULL;
5505 switch(i) {
5506 case MESA_SHADER_VERTEX:
5507 name = "Vertex Shader";
5508 description = "Vulkan Vertex Shader";
5509 break;
5510 case MESA_SHADER_TESS_CTRL:
5511 if (!pipeline->shaders[MESA_SHADER_VERTEX]) {
5512 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5513 name = "Vertex + Tessellation Control Shaders";
5514 description = "Combined Vulkan Vertex and Tessellation Control Shaders";
5515 } else {
5516 name = "Tessellation Control Shader";
5517 description = "Vulkan Tessellation Control Shader";
5518 }
5519 break;
5520 case MESA_SHADER_TESS_EVAL:
5521 name = "Tessellation Evaluation Shader";
5522 description = "Vulkan Tessellation Evaluation Shader";
5523 break;
5524 case MESA_SHADER_GEOMETRY:
5525 if (radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
5526 pProperties[executable_idx].stages |= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT;
5527 name = "Tessellation Evaluation + Geometry Shaders";
5528 description = "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5529 } else if (!radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_VERTEX]) {
5530 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5531 name = "Vertex + Geometry Shader";
5532 description = "Combined Vulkan Vertex and Geometry Shaders";
5533 } else {
5534 name = "Geometry Shader";
5535 description = "Vulkan Geometry Shader";
5536 }
5537 break;
5538 case MESA_SHADER_FRAGMENT:
5539 name = "Fragment Shader";
5540 description = "Vulkan Fragment Shader";
5541 break;
5542 case MESA_SHADER_COMPUTE:
5543 name = "Compute Shader";
5544 description = "Vulkan Compute Shader";
5545 break;
5546 }
5547
5548 pProperties[executable_idx].subgroupSize = pipeline->shaders[i]->info.wave_size;
5549 desc_copy(pProperties[executable_idx].name, name);
5550 desc_copy(pProperties[executable_idx].description, description);
5551
5552 ++executable_idx;
5553 if (i == MESA_SHADER_GEOMETRY &&
5554 !radv_pipeline_has_ngg(pipeline)) {
5555 assert(pipeline->gs_copy_shader);
5556 if (executable_idx >= count)
5557 break;
5558
5559 pProperties[executable_idx].stages = VK_SHADER_STAGE_GEOMETRY_BIT;
5560 pProperties[executable_idx].subgroupSize = 64;
5561 desc_copy(pProperties[executable_idx].name, "GS Copy Shader");
5562 desc_copy(pProperties[executable_idx].description,
5563 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5564
5565 ++executable_idx;
5566 }
5567 }
5568
5569 VkResult result = *pExecutableCount < total_count ? VK_INCOMPLETE : VK_SUCCESS;
5570 *pExecutableCount = count;
5571 return result;
5572 }
5573
5574 VkResult radv_GetPipelineExecutableStatisticsKHR(
5575 VkDevice _device,
5576 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5577 uint32_t* pStatisticCount,
5578 VkPipelineExecutableStatisticKHR* pStatistics)
5579 {
5580 RADV_FROM_HANDLE(radv_device, device, _device);
5581 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5582 gl_shader_stage stage;
5583 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5584
5585 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
5586 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
5587 unsigned max_waves = radv_get_max_waves(device, shader, stage);
5588
5589 VkPipelineExecutableStatisticKHR *s = pStatistics;
5590 VkPipelineExecutableStatisticKHR *end = s + (pStatistics ? *pStatisticCount : 0);
5591 VkResult result = VK_SUCCESS;
5592
5593 if (s < end) {
5594 desc_copy(s->name, "SGPRs");
5595 desc_copy(s->description, "Number of SGPR registers allocated per subgroup");
5596 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5597 s->value.u64 = shader->config.num_sgprs;
5598 }
5599 ++s;
5600
5601 if (s < end) {
5602 desc_copy(s->name, "VGPRs");
5603 desc_copy(s->description, "Number of VGPR registers allocated per subgroup");
5604 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5605 s->value.u64 = shader->config.num_vgprs;
5606 }
5607 ++s;
5608
5609 if (s < end) {
5610 desc_copy(s->name, "Spilled SGPRs");
5611 desc_copy(s->description, "Number of SGPR registers spilled per subgroup");
5612 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5613 s->value.u64 = shader->config.spilled_sgprs;
5614 }
5615 ++s;
5616
5617 if (s < end) {
5618 desc_copy(s->name, "Spilled VGPRs");
5619 desc_copy(s->description, "Number of VGPR registers spilled per subgroup");
5620 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5621 s->value.u64 = shader->config.spilled_vgprs;
5622 }
5623 ++s;
5624
5625 if (s < end) {
5626 desc_copy(s->name, "PrivMem VGPRs");
5627 desc_copy(s->description, "Number of VGPRs stored in private memory per subgroup");
5628 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5629 s->value.u64 = shader->info.private_mem_vgprs;
5630 }
5631 ++s;
5632
5633 if (s < end) {
5634 desc_copy(s->name, "Code size");
5635 desc_copy(s->description, "Code size in bytes");
5636 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5637 s->value.u64 = shader->exec_size;
5638 }
5639 ++s;
5640
5641 if (s < end) {
5642 desc_copy(s->name, "LDS size");
5643 desc_copy(s->description, "LDS size in bytes per workgroup");
5644 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5645 s->value.u64 = shader->config.lds_size * lds_increment;
5646 }
5647 ++s;
5648
5649 if (s < end) {
5650 desc_copy(s->name, "Scratch size");
5651 desc_copy(s->description, "Private memory in bytes per subgroup");
5652 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5653 s->value.u64 = shader->config.scratch_bytes_per_wave;
5654 }
5655 ++s;
5656
5657 if (s < end) {
5658 desc_copy(s->name, "Subgroups per SIMD");
5659 desc_copy(s->description, "The maximum number of subgroups in flight on a SIMD unit");
5660 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5661 s->value.u64 = max_waves;
5662 }
5663 ++s;
5664
5665 if (shader->statistics) {
5666 for (unsigned i = 0; i < shader->statistics->count; i++) {
5667 struct radv_compiler_statistic_info *info = &shader->statistics->infos[i];
5668 uint32_t value = shader->statistics->values[i];
5669 if (s < end) {
5670 desc_copy(s->name, info->name);
5671 desc_copy(s->description, info->desc);
5672 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5673 s->value.u64 = value;
5674 }
5675 ++s;
5676 }
5677 }
5678
5679 if (!pStatistics)
5680 *pStatisticCount = s - pStatistics;
5681 else if (s > end) {
5682 *pStatisticCount = end - pStatistics;
5683 result = VK_INCOMPLETE;
5684 } else {
5685 *pStatisticCount = s - pStatistics;
5686 }
5687
5688 return result;
5689 }
5690
5691 static VkResult radv_copy_representation(void *data, size_t *data_size, const char *src)
5692 {
5693 size_t total_size = strlen(src) + 1;
5694
5695 if (!data) {
5696 *data_size = total_size;
5697 return VK_SUCCESS;
5698 }
5699
5700 size_t size = MIN2(total_size, *data_size);
5701
5702 memcpy(data, src, size);
5703 if (size)
5704 *((char*)data + size - 1) = 0;
5705 return size < total_size ? VK_INCOMPLETE : VK_SUCCESS;
5706 }
5707
5708 VkResult radv_GetPipelineExecutableInternalRepresentationsKHR(
5709 VkDevice device,
5710 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5711 uint32_t* pInternalRepresentationCount,
5712 VkPipelineExecutableInternalRepresentationKHR* pInternalRepresentations)
5713 {
5714 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5715 gl_shader_stage stage;
5716 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5717
5718 VkPipelineExecutableInternalRepresentationKHR *p = pInternalRepresentations;
5719 VkPipelineExecutableInternalRepresentationKHR *end = p + (pInternalRepresentations ? *pInternalRepresentationCount : 0);
5720 VkResult result = VK_SUCCESS;
5721 /* optimized NIR */
5722 if (p < end) {
5723 p->isText = true;
5724 desc_copy(p->name, "NIR Shader(s)");
5725 desc_copy(p->description, "The optimized NIR shader(s)");
5726 if (radv_copy_representation(p->pData, &p->dataSize, shader->nir_string) != VK_SUCCESS)
5727 result = VK_INCOMPLETE;
5728 }
5729 ++p;
5730
5731 /* backend IR */
5732 if (p < end) {
5733 p->isText = true;
5734 if (pipeline->device->physical_device->use_llvm) {
5735 desc_copy(p->name, "LLVM IR");
5736 desc_copy(p->description, "The LLVM IR after some optimizations");
5737 } else {
5738 desc_copy(p->name, "ACO IR");
5739 desc_copy(p->description, "The ACO IR after some optimizations");
5740 }
5741 if (radv_copy_representation(p->pData, &p->dataSize, shader->ir_string) != VK_SUCCESS)
5742 result = VK_INCOMPLETE;
5743 }
5744 ++p;
5745
5746 /* Disassembler */
5747 if (p < end) {
5748 p->isText = true;
5749 desc_copy(p->name, "Assembly");
5750 desc_copy(p->description, "Final Assembly");
5751 if (radv_copy_representation(p->pData, &p->dataSize, shader->disasm_string) != VK_SUCCESS)
5752 result = VK_INCOMPLETE;
5753 }
5754 ++p;
5755
5756 if (!pInternalRepresentations)
5757 *pInternalRepresentationCount = p - pInternalRepresentations;
5758 else if(p > end) {
5759 result = VK_INCOMPLETE;
5760 *pInternalRepresentationCount = end - pInternalRepresentations;
5761 } else {
5762 *pInternalRepresentationCount = p - pInternalRepresentations;
5763 }
5764
5765 return result;
5766 }