radv: clean up tessellation state emission
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
33 #include "radv_cs.h"
34 #include "radv_shader.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
39 #include "vk_util.h"
40
41 #include "sid.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
48 #include "ac_shader_util.h"
49
50 struct radv_blend_state {
51 uint32_t blend_enable_4bit;
52 uint32_t need_src_alpha;
53
54 uint32_t cb_color_control;
55 uint32_t cb_target_mask;
56 uint32_t cb_target_enabled_4bit;
57 uint32_t sx_mrt_blend_opt[8];
58 uint32_t cb_blend_control[8];
59
60 uint32_t spi_shader_col_format;
61 uint32_t col_format_is_int8;
62 uint32_t col_format_is_int10;
63 uint32_t cb_shader_mask;
64 uint32_t db_alpha_to_mask;
65
66 uint32_t commutative_4bit;
67
68 bool single_cb_enable;
69 bool mrt0_is_dual_src;
70 };
71
72 struct radv_dsa_order_invariance {
73 /* Whether the final result in Z/S buffers is guaranteed to be
74 * invariant under changes to the order in which fragments arrive.
75 */
76 bool zs;
77
78 /* Whether the set of fragments that pass the combined Z/S test is
79 * guaranteed to be invariant under changes to the order in which
80 * fragments arrive.
81 */
82 bool pass_set;
83 };
84
85 static const VkPipelineMultisampleStateCreateInfo *
86 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
87 {
88 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
89 return pCreateInfo->pMultisampleState;
90 return NULL;
91 }
92
93 static const VkPipelineTessellationStateCreateInfo *
94 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
95 {
96 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
97 if (pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT ||
98 pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) {
99 return pCreateInfo->pTessellationState;
100 }
101 }
102 return NULL;
103 }
104
105 static const VkPipelineDepthStencilStateCreateInfo *
106 radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
107 {
108 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
109 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
110
111 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
112 subpass->depth_stencil_attachment)
113 return pCreateInfo->pDepthStencilState;
114 return NULL;
115 }
116
117 static const VkPipelineColorBlendStateCreateInfo *
118 radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
119 {
120 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
121 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
122
123 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
124 subpass->has_color_att)
125 return pCreateInfo->pColorBlendState;
126 return NULL;
127 }
128
129 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline)
130 {
131 struct radv_shader_variant *variant = NULL;
132 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
133 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
134 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
135 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
136 else if (pipeline->shaders[MESA_SHADER_VERTEX])
137 variant = pipeline->shaders[MESA_SHADER_VERTEX];
138 else
139 return false;
140 return variant->info.is_ngg;
141 }
142
143 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline *pipeline)
144 {
145 assert(radv_pipeline_has_ngg(pipeline));
146
147 struct radv_shader_variant *variant = NULL;
148 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
149 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
150 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
151 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
152 else if (pipeline->shaders[MESA_SHADER_VERTEX])
153 variant = pipeline->shaders[MESA_SHADER_VERTEX];
154 else
155 return false;
156 return variant->info.is_ngg_passthrough;
157 }
158
159 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline)
160 {
161 if (!radv_pipeline_has_gs(pipeline))
162 return false;
163
164 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
165 * On GFX10, it might be required in rare cases if it's not possible to
166 * enable NGG.
167 */
168 if (radv_pipeline_has_ngg(pipeline))
169 return false;
170
171 assert(pipeline->gs_copy_shader);
172 return true;
173 }
174
175 static void
176 radv_pipeline_destroy(struct radv_device *device,
177 struct radv_pipeline *pipeline,
178 const VkAllocationCallbacks* allocator)
179 {
180 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
181 if (pipeline->shaders[i])
182 radv_shader_variant_destroy(device, pipeline->shaders[i]);
183
184 if (pipeline->gs_copy_shader)
185 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
186
187 if(pipeline->cs.buf)
188 free(pipeline->cs.buf);
189
190 vk_object_base_finish(&pipeline->base);
191 vk_free2(&device->vk.alloc, allocator, pipeline);
192 }
193
194 void radv_DestroyPipeline(
195 VkDevice _device,
196 VkPipeline _pipeline,
197 const VkAllocationCallbacks* pAllocator)
198 {
199 RADV_FROM_HANDLE(radv_device, device, _device);
200 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
201
202 if (!_pipeline)
203 return;
204
205 radv_pipeline_destroy(device, pipeline, pAllocator);
206 }
207
208 static uint32_t get_hash_flags(struct radv_device *device)
209 {
210 uint32_t hash_flags = 0;
211
212 if (device->instance->debug_flags & RADV_DEBUG_NO_NGG)
213 hash_flags |= RADV_HASH_SHADER_NO_NGG;
214 if (device->physical_device->cs_wave_size == 32)
215 hash_flags |= RADV_HASH_SHADER_CS_WAVE32;
216 if (device->physical_device->ps_wave_size == 32)
217 hash_flags |= RADV_HASH_SHADER_PS_WAVE32;
218 if (device->physical_device->ge_wave_size == 32)
219 hash_flags |= RADV_HASH_SHADER_GE_WAVE32;
220 if (device->physical_device->use_llvm)
221 hash_flags |= RADV_HASH_SHADER_LLVM;
222 return hash_flags;
223 }
224
225 static VkResult
226 radv_pipeline_scratch_init(struct radv_device *device,
227 struct radv_pipeline *pipeline)
228 {
229 unsigned scratch_bytes_per_wave = 0;
230 unsigned max_waves = 0;
231 unsigned min_waves = 1;
232
233 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
234 if (pipeline->shaders[i] &&
235 pipeline->shaders[i]->config.scratch_bytes_per_wave) {
236 unsigned max_stage_waves = device->scratch_waves;
237
238 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
239 pipeline->shaders[i]->config.scratch_bytes_per_wave);
240
241 max_stage_waves = MIN2(max_stage_waves,
242 4 * device->physical_device->rad_info.num_good_compute_units *
243 (256 / pipeline->shaders[i]->config.num_vgprs));
244 max_waves = MAX2(max_waves, max_stage_waves);
245 }
246 }
247
248 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
249 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
250 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
251 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
252 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
253 }
254
255 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
256 pipeline->max_waves = max_waves;
257 return VK_SUCCESS;
258 }
259
260 static uint32_t si_translate_blend_logic_op(VkLogicOp op)
261 {
262 switch (op) {
263 case VK_LOGIC_OP_CLEAR:
264 return V_028808_ROP3_CLEAR;
265 case VK_LOGIC_OP_AND:
266 return V_028808_ROP3_AND;
267 case VK_LOGIC_OP_AND_REVERSE:
268 return V_028808_ROP3_AND_REVERSE;
269 case VK_LOGIC_OP_COPY:
270 return V_028808_ROP3_COPY;
271 case VK_LOGIC_OP_AND_INVERTED:
272 return V_028808_ROP3_AND_INVERTED;
273 case VK_LOGIC_OP_NO_OP:
274 return V_028808_ROP3_NO_OP;
275 case VK_LOGIC_OP_XOR:
276 return V_028808_ROP3_XOR;
277 case VK_LOGIC_OP_OR:
278 return V_028808_ROP3_OR;
279 case VK_LOGIC_OP_NOR:
280 return V_028808_ROP3_NOR;
281 case VK_LOGIC_OP_EQUIVALENT:
282 return V_028808_ROP3_EQUIVALENT;
283 case VK_LOGIC_OP_INVERT:
284 return V_028808_ROP3_INVERT;
285 case VK_LOGIC_OP_OR_REVERSE:
286 return V_028808_ROP3_OR_REVERSE;
287 case VK_LOGIC_OP_COPY_INVERTED:
288 return V_028808_ROP3_COPY_INVERTED;
289 case VK_LOGIC_OP_OR_INVERTED:
290 return V_028808_ROP3_OR_INVERTED;
291 case VK_LOGIC_OP_NAND:
292 return V_028808_ROP3_NAND;
293 case VK_LOGIC_OP_SET:
294 return V_028808_ROP3_SET;
295 default:
296 unreachable("Unhandled logic op");
297 }
298 }
299
300
301 static uint32_t si_translate_blend_function(VkBlendOp op)
302 {
303 switch (op) {
304 case VK_BLEND_OP_ADD:
305 return V_028780_COMB_DST_PLUS_SRC;
306 case VK_BLEND_OP_SUBTRACT:
307 return V_028780_COMB_SRC_MINUS_DST;
308 case VK_BLEND_OP_REVERSE_SUBTRACT:
309 return V_028780_COMB_DST_MINUS_SRC;
310 case VK_BLEND_OP_MIN:
311 return V_028780_COMB_MIN_DST_SRC;
312 case VK_BLEND_OP_MAX:
313 return V_028780_COMB_MAX_DST_SRC;
314 default:
315 return 0;
316 }
317 }
318
319 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
320 {
321 switch (factor) {
322 case VK_BLEND_FACTOR_ZERO:
323 return V_028780_BLEND_ZERO;
324 case VK_BLEND_FACTOR_ONE:
325 return V_028780_BLEND_ONE;
326 case VK_BLEND_FACTOR_SRC_COLOR:
327 return V_028780_BLEND_SRC_COLOR;
328 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
329 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
330 case VK_BLEND_FACTOR_DST_COLOR:
331 return V_028780_BLEND_DST_COLOR;
332 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
333 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
334 case VK_BLEND_FACTOR_SRC_ALPHA:
335 return V_028780_BLEND_SRC_ALPHA;
336 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
337 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
338 case VK_BLEND_FACTOR_DST_ALPHA:
339 return V_028780_BLEND_DST_ALPHA;
340 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
341 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
342 case VK_BLEND_FACTOR_CONSTANT_COLOR:
343 return V_028780_BLEND_CONSTANT_COLOR;
344 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
345 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
346 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
347 return V_028780_BLEND_CONSTANT_ALPHA;
348 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
349 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
350 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
351 return V_028780_BLEND_SRC_ALPHA_SATURATE;
352 case VK_BLEND_FACTOR_SRC1_COLOR:
353 return V_028780_BLEND_SRC1_COLOR;
354 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
355 return V_028780_BLEND_INV_SRC1_COLOR;
356 case VK_BLEND_FACTOR_SRC1_ALPHA:
357 return V_028780_BLEND_SRC1_ALPHA;
358 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
359 return V_028780_BLEND_INV_SRC1_ALPHA;
360 default:
361 return 0;
362 }
363 }
364
365 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
366 {
367 switch (op) {
368 case VK_BLEND_OP_ADD:
369 return V_028760_OPT_COMB_ADD;
370 case VK_BLEND_OP_SUBTRACT:
371 return V_028760_OPT_COMB_SUBTRACT;
372 case VK_BLEND_OP_REVERSE_SUBTRACT:
373 return V_028760_OPT_COMB_REVSUBTRACT;
374 case VK_BLEND_OP_MIN:
375 return V_028760_OPT_COMB_MIN;
376 case VK_BLEND_OP_MAX:
377 return V_028760_OPT_COMB_MAX;
378 default:
379 return V_028760_OPT_COMB_BLEND_DISABLED;
380 }
381 }
382
383 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
384 {
385 switch (factor) {
386 case VK_BLEND_FACTOR_ZERO:
387 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
388 case VK_BLEND_FACTOR_ONE:
389 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
390 case VK_BLEND_FACTOR_SRC_COLOR:
391 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
392 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
393 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
394 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
395 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
396 case VK_BLEND_FACTOR_SRC_ALPHA:
397 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
398 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
399 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
400 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
401 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
402 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
403 default:
404 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
405 }
406 }
407
408 /**
409 * Get rid of DST in the blend factors by commuting the operands:
410 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
411 */
412 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
413 unsigned *dst_factor, unsigned expected_dst,
414 unsigned replacement_src)
415 {
416 if (*src_factor == expected_dst &&
417 *dst_factor == VK_BLEND_FACTOR_ZERO) {
418 *src_factor = VK_BLEND_FACTOR_ZERO;
419 *dst_factor = replacement_src;
420
421 /* Commuting the operands requires reversing subtractions. */
422 if (*func == VK_BLEND_OP_SUBTRACT)
423 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
424 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
425 *func = VK_BLEND_OP_SUBTRACT;
426 }
427 }
428
429 static bool si_blend_factor_uses_dst(unsigned factor)
430 {
431 return factor == VK_BLEND_FACTOR_DST_COLOR ||
432 factor == VK_BLEND_FACTOR_DST_ALPHA ||
433 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
434 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
435 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
436 }
437
438 static bool is_dual_src(VkBlendFactor factor)
439 {
440 switch (factor) {
441 case VK_BLEND_FACTOR_SRC1_COLOR:
442 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
443 case VK_BLEND_FACTOR_SRC1_ALPHA:
444 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
445 return true;
446 default:
447 return false;
448 }
449 }
450
451 static unsigned radv_choose_spi_color_format(VkFormat vk_format,
452 bool blend_enable,
453 bool blend_need_alpha)
454 {
455 const struct vk_format_description *desc = vk_format_description(vk_format);
456 struct ac_spi_color_formats formats = {};
457 unsigned format, ntype, swap;
458
459 format = radv_translate_colorformat(vk_format);
460 ntype = radv_translate_color_numformat(vk_format, desc,
461 vk_format_get_first_non_void_channel(vk_format));
462 swap = radv_translate_colorswap(vk_format, false);
463
464 ac_choose_spi_color_formats(format, swap, ntype, false, &formats);
465
466 if (blend_enable && blend_need_alpha)
467 return formats.blend_alpha;
468 else if(blend_need_alpha)
469 return formats.alpha;
470 else if(blend_enable)
471 return formats.blend;
472 else
473 return formats.normal;
474 }
475
476 static bool
477 format_is_int8(VkFormat format)
478 {
479 const struct vk_format_description *desc = vk_format_description(format);
480 int channel = vk_format_get_first_non_void_channel(format);
481
482 return channel >= 0 && desc->channel[channel].pure_integer &&
483 desc->channel[channel].size == 8;
484 }
485
486 static bool
487 format_is_int10(VkFormat format)
488 {
489 const struct vk_format_description *desc = vk_format_description(format);
490
491 if (desc->nr_channels != 4)
492 return false;
493 for (unsigned i = 0; i < 4; i++) {
494 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
495 return true;
496 }
497 return false;
498 }
499
500 static void
501 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
502 const VkGraphicsPipelineCreateInfo *pCreateInfo,
503 struct radv_blend_state *blend)
504 {
505 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
506 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
507 unsigned col_format = 0, is_int8 = 0, is_int10 = 0;
508 unsigned num_targets;
509
510 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
511 unsigned cf;
512
513 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED ||
514 !(blend->cb_target_mask & (0xfu << (i * 4)))) {
515 cf = V_028714_SPI_SHADER_ZERO;
516 } else {
517 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
518 bool blend_enable =
519 blend->blend_enable_4bit & (0xfu << (i * 4));
520
521 cf = radv_choose_spi_color_format(attachment->format,
522 blend_enable,
523 blend->need_src_alpha & (1 << i));
524
525 if (format_is_int8(attachment->format))
526 is_int8 |= 1 << i;
527 if (format_is_int10(attachment->format))
528 is_int10 |= 1 << i;
529 }
530
531 col_format |= cf << (4 * i);
532 }
533
534 if (!(col_format & 0xf) && blend->need_src_alpha & (1 << 0)) {
535 /* When a subpass doesn't have any color attachments, write the
536 * alpha channel of MRT0 when alpha coverage is enabled because
537 * the depth attachment needs it.
538 */
539 col_format |= V_028714_SPI_SHADER_32_AR;
540 }
541
542 /* If the i-th target format is set, all previous target formats must
543 * be non-zero to avoid hangs.
544 */
545 num_targets = (util_last_bit(col_format) + 3) / 4;
546 for (unsigned i = 0; i < num_targets; i++) {
547 if (!(col_format & (0xf << (i * 4)))) {
548 col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
549 }
550 }
551
552 /* The output for dual source blending should have the same format as
553 * the first output.
554 */
555 if (blend->mrt0_is_dual_src)
556 col_format |= (col_format & 0xf) << 4;
557
558 blend->spi_shader_col_format = col_format;
559 blend->col_format_is_int8 = is_int8;
560 blend->col_format_is_int10 = is_int10;
561 }
562
563 /*
564 * Ordered so that for each i,
565 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
566 */
567 const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = {
568 VK_FORMAT_R32_SFLOAT,
569 VK_FORMAT_R32G32_SFLOAT,
570 VK_FORMAT_R8G8B8A8_UNORM,
571 VK_FORMAT_R16G16B16A16_UNORM,
572 VK_FORMAT_R16G16B16A16_SNORM,
573 VK_FORMAT_R16G16B16A16_UINT,
574 VK_FORMAT_R16G16B16A16_SINT,
575 VK_FORMAT_R32G32B32A32_SFLOAT,
576 VK_FORMAT_R8G8B8A8_UINT,
577 VK_FORMAT_R8G8B8A8_SINT,
578 VK_FORMAT_A2R10G10B10_UINT_PACK32,
579 VK_FORMAT_A2R10G10B10_SINT_PACK32,
580 };
581
582 unsigned radv_format_meta_fs_key(VkFormat format)
583 {
584 unsigned col_format = radv_choose_spi_color_format(format, false, false);
585
586 assert(col_format != V_028714_SPI_SHADER_32_AR);
587 if (col_format >= V_028714_SPI_SHADER_32_AR)
588 --col_format; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
589
590 --col_format; /* Skip V_028714_SPI_SHADER_ZERO */
591 bool is_int8 = format_is_int8(format);
592 bool is_int10 = format_is_int10(format);
593
594 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
595 }
596
597 static void
598 radv_blend_check_commutativity(struct radv_blend_state *blend,
599 VkBlendOp op, VkBlendFactor src,
600 VkBlendFactor dst, unsigned chanmask)
601 {
602 /* Src factor is allowed when it does not depend on Dst. */
603 static const uint32_t src_allowed =
604 (1u << VK_BLEND_FACTOR_ONE) |
605 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
606 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
607 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
608 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
609 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
610 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
611 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
612 (1u << VK_BLEND_FACTOR_ZERO) |
613 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
614 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
615 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
616 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
617 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
618 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
619
620 if (dst == VK_BLEND_FACTOR_ONE &&
621 (src_allowed & (1u << src))) {
622 /* Addition is commutative, but floating point addition isn't
623 * associative: subtle changes can be introduced via different
624 * rounding. Be conservative, only enable for min and max.
625 */
626 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
627 blend->commutative_4bit |= chanmask;
628 }
629 }
630
631 static struct radv_blend_state
632 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
633 const VkGraphicsPipelineCreateInfo *pCreateInfo,
634 const struct radv_graphics_pipeline_create_info *extra)
635 {
636 const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
637 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
638 struct radv_blend_state blend = {0};
639 unsigned mode = V_028808_CB_NORMAL;
640 int i;
641
642 if (extra && extra->custom_blend_mode) {
643 blend.single_cb_enable = true;
644 mode = extra->custom_blend_mode;
645 }
646
647 blend.cb_color_control = 0;
648 if (vkblend) {
649 if (vkblend->logicOpEnable)
650 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
651 else
652 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
653 }
654
655 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
656 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
657 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
658 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
659 S_028B70_OFFSET_ROUND(1);
660
661 if (vkms && vkms->alphaToCoverageEnable) {
662 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
663 blend.need_src_alpha |= 0x1;
664 }
665
666 blend.cb_target_mask = 0;
667 if (vkblend) {
668 for (i = 0; i < vkblend->attachmentCount; i++) {
669 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
670 unsigned blend_cntl = 0;
671 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
672 VkBlendOp eqRGB = att->colorBlendOp;
673 VkBlendFactor srcRGB = att->srcColorBlendFactor;
674 VkBlendFactor dstRGB = att->dstColorBlendFactor;
675 VkBlendOp eqA = att->alphaBlendOp;
676 VkBlendFactor srcA = att->srcAlphaBlendFactor;
677 VkBlendFactor dstA = att->dstAlphaBlendFactor;
678
679 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
680
681 if (!att->colorWriteMask)
682 continue;
683
684 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
685 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
686 if (!att->blendEnable) {
687 blend.cb_blend_control[i] = blend_cntl;
688 continue;
689 }
690
691 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
692 if (i == 0)
693 blend.mrt0_is_dual_src = true;
694
695 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
696 srcRGB = VK_BLEND_FACTOR_ONE;
697 dstRGB = VK_BLEND_FACTOR_ONE;
698 }
699 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
700 srcA = VK_BLEND_FACTOR_ONE;
701 dstA = VK_BLEND_FACTOR_ONE;
702 }
703
704 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
705 0x7 << (4 * i));
706 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
707 0x8 << (4 * i));
708
709 /* Blending optimizations for RB+.
710 * These transformations don't change the behavior.
711 *
712 * First, get rid of DST in the blend factors:
713 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
714 */
715 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
716 VK_BLEND_FACTOR_DST_COLOR,
717 VK_BLEND_FACTOR_SRC_COLOR);
718
719 si_blend_remove_dst(&eqA, &srcA, &dstA,
720 VK_BLEND_FACTOR_DST_COLOR,
721 VK_BLEND_FACTOR_SRC_COLOR);
722
723 si_blend_remove_dst(&eqA, &srcA, &dstA,
724 VK_BLEND_FACTOR_DST_ALPHA,
725 VK_BLEND_FACTOR_SRC_ALPHA);
726
727 /* Look up the ideal settings from tables. */
728 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
729 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
730 srcA_opt = si_translate_blend_opt_factor(srcA, true);
731 dstA_opt = si_translate_blend_opt_factor(dstA, true);
732
733 /* Handle interdependencies. */
734 if (si_blend_factor_uses_dst(srcRGB))
735 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
736 if (si_blend_factor_uses_dst(srcA))
737 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
738
739 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
740 (dstRGB == VK_BLEND_FACTOR_ZERO ||
741 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
742 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
743 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
744
745 /* Set the final value. */
746 blend.sx_mrt_blend_opt[i] =
747 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
748 S_028760_COLOR_DST_OPT(dstRGB_opt) |
749 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
750 S_028760_ALPHA_SRC_OPT(srcA_opt) |
751 S_028760_ALPHA_DST_OPT(dstA_opt) |
752 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
753 blend_cntl |= S_028780_ENABLE(1);
754
755 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
756 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
757 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
758 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
759 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
760 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
761 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
762 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
763 }
764 blend.cb_blend_control[i] = blend_cntl;
765
766 blend.blend_enable_4bit |= 0xfu << (i * 4);
767
768 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
769 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
770 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
771 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
772 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
773 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
774 blend.need_src_alpha |= 1 << i;
775 }
776 for (i = vkblend->attachmentCount; i < 8; i++) {
777 blend.cb_blend_control[i] = 0;
778 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
779 }
780 }
781
782 if (pipeline->device->physical_device->rad_info.has_rbplus) {
783 /* Disable RB+ blend optimizations for dual source blending. */
784 if (blend.mrt0_is_dual_src) {
785 for (i = 0; i < 8; i++) {
786 blend.sx_mrt_blend_opt[i] =
787 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
788 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
789 }
790 }
791
792 /* RB+ doesn't work with dual source blending, logic op and
793 * RESOLVE.
794 */
795 if (blend.mrt0_is_dual_src ||
796 (vkblend && vkblend->logicOpEnable) ||
797 mode == V_028808_CB_RESOLVE)
798 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
799 }
800
801 if (blend.cb_target_mask)
802 blend.cb_color_control |= S_028808_MODE(mode);
803 else
804 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
805
806 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
807 return blend;
808 }
809
810 static uint32_t si_translate_fill(VkPolygonMode func)
811 {
812 switch(func) {
813 case VK_POLYGON_MODE_FILL:
814 return V_028814_X_DRAW_TRIANGLES;
815 case VK_POLYGON_MODE_LINE:
816 return V_028814_X_DRAW_LINES;
817 case VK_POLYGON_MODE_POINT:
818 return V_028814_X_DRAW_POINTS;
819 default:
820 assert(0);
821 return V_028814_X_DRAW_POINTS;
822 }
823 }
824
825 static uint8_t radv_pipeline_get_ps_iter_samples(const VkGraphicsPipelineCreateInfo *pCreateInfo)
826 {
827 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
828 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
829 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
830 uint32_t ps_iter_samples = 1;
831 uint32_t num_samples;
832
833 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
834 *
835 * "If the VK_AMD_mixed_attachment_samples extension is enabled and the
836 * subpass uses color attachments, totalSamples is the number of
837 * samples of the color attachments. Otherwise, totalSamples is the
838 * value of VkPipelineMultisampleStateCreateInfo::rasterizationSamples
839 * specified at pipeline creation time."
840 */
841 if (subpass->has_color_att) {
842 num_samples = subpass->color_sample_count;
843 } else {
844 num_samples = vkms->rasterizationSamples;
845 }
846
847 if (vkms->sampleShadingEnable) {
848 ps_iter_samples = ceilf(vkms->minSampleShading * num_samples);
849 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
850 }
851 return ps_iter_samples;
852 }
853
854 static bool
855 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
856 {
857 return pCreateInfo->depthTestEnable &&
858 pCreateInfo->depthWriteEnable &&
859 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
860 }
861
862 static bool
863 radv_writes_stencil(const VkStencilOpState *state)
864 {
865 return state->writeMask &&
866 (state->failOp != VK_STENCIL_OP_KEEP ||
867 state->passOp != VK_STENCIL_OP_KEEP ||
868 state->depthFailOp != VK_STENCIL_OP_KEEP);
869 }
870
871 static bool
872 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
873 {
874 return pCreateInfo->stencilTestEnable &&
875 (radv_writes_stencil(&pCreateInfo->front) ||
876 radv_writes_stencil(&pCreateInfo->back));
877 }
878
879 static bool
880 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
881 {
882 return radv_is_depth_write_enabled(pCreateInfo) ||
883 radv_is_stencil_write_enabled(pCreateInfo);
884 }
885
886 static bool
887 radv_order_invariant_stencil_op(VkStencilOp op)
888 {
889 /* REPLACE is normally order invariant, except when the stencil
890 * reference value is written by the fragment shader. Tracking this
891 * interaction does not seem worth the effort, so be conservative.
892 */
893 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
894 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
895 op != VK_STENCIL_OP_REPLACE;
896 }
897
898 static bool
899 radv_order_invariant_stencil_state(const VkStencilOpState *state)
900 {
901 /* Compute whether, assuming Z writes are disabled, this stencil state
902 * is order invariant in the sense that the set of passing fragments as
903 * well as the final stencil buffer result does not depend on the order
904 * of fragments.
905 */
906 return !state->writeMask ||
907 /* The following assumes that Z writes are disabled. */
908 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
909 radv_order_invariant_stencil_op(state->passOp) &&
910 radv_order_invariant_stencil_op(state->depthFailOp)) ||
911 (state->compareOp == VK_COMPARE_OP_NEVER &&
912 radv_order_invariant_stencil_op(state->failOp));
913 }
914
915 static bool
916 radv_pipeline_has_dynamic_ds_states(const VkGraphicsPipelineCreateInfo *pCreateInfo)
917 {
918 VkDynamicState ds_states[] = {
919 VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT,
920 VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT,
921 VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT,
922 VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT,
923 VK_DYNAMIC_STATE_STENCIL_OP_EXT,
924 };
925
926 if (pCreateInfo->pDynamicState) {
927 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
928 for (uint32_t i = 0; i < count; i++) {
929 for (uint32_t j = 0; j < ARRAY_SIZE(ds_states); j++) {
930 if (pCreateInfo->pDynamicState->pDynamicStates[i] == ds_states[j])
931 return true;
932 }
933 }
934 }
935
936 return false;
937 }
938
939 static bool
940 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
941 struct radv_blend_state *blend,
942 const VkGraphicsPipelineCreateInfo *pCreateInfo)
943 {
944 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
945 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
946 const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
947 const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
948 unsigned colormask = blend->cb_target_enabled_4bit;
949
950 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
951 return false;
952
953 /* Be conservative if a logic operation is enabled with color buffers. */
954 if (colormask && vkblend && vkblend->logicOpEnable)
955 return false;
956
957 /* Be conservative if an extended dynamic depth/stencil state is
958 * enabled because the driver can't update out-of-order rasterization
959 * dynamically.
960 */
961 if (radv_pipeline_has_dynamic_ds_states(pCreateInfo))
962 return false;
963
964 /* Default depth/stencil invariance when no attachment is bound. */
965 struct radv_dsa_order_invariance dsa_order_invariant = {
966 .zs = true, .pass_set = true
967 };
968
969 if (vkds) {
970 struct radv_render_pass_attachment *attachment =
971 pass->attachments + subpass->depth_stencil_attachment->attachment;
972 bool has_stencil = vk_format_is_stencil(attachment->format);
973 struct radv_dsa_order_invariance order_invariance[2];
974 struct radv_shader_variant *ps =
975 pipeline->shaders[MESA_SHADER_FRAGMENT];
976
977 /* Compute depth/stencil order invariance in order to know if
978 * it's safe to enable out-of-order.
979 */
980 bool zfunc_is_ordered =
981 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
982 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
983 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
984 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
985 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
986
987 bool nozwrite_and_order_invariant_stencil =
988 !radv_is_ds_write_enabled(vkds) ||
989 (!radv_is_depth_write_enabled(vkds) &&
990 radv_order_invariant_stencil_state(&vkds->front) &&
991 radv_order_invariant_stencil_state(&vkds->back));
992
993 order_invariance[1].zs =
994 nozwrite_and_order_invariant_stencil ||
995 (!radv_is_stencil_write_enabled(vkds) &&
996 zfunc_is_ordered);
997 order_invariance[0].zs =
998 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
999
1000 order_invariance[1].pass_set =
1001 nozwrite_and_order_invariant_stencil ||
1002 (!radv_is_stencil_write_enabled(vkds) &&
1003 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1004 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
1005 order_invariance[0].pass_set =
1006 !radv_is_depth_write_enabled(vkds) ||
1007 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1008 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
1009
1010 dsa_order_invariant = order_invariance[has_stencil];
1011 if (!dsa_order_invariant.zs)
1012 return false;
1013
1014 /* The set of PS invocations is always order invariant,
1015 * except when early Z/S tests are requested.
1016 */
1017 if (ps &&
1018 ps->info.ps.writes_memory &&
1019 ps->info.ps.early_fragment_test &&
1020 !dsa_order_invariant.pass_set)
1021 return false;
1022
1023 /* Determine if out-of-order rasterization should be disabled
1024 * when occlusion queries are used.
1025 */
1026 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
1027 !dsa_order_invariant.pass_set;
1028 }
1029
1030 /* No color buffers are enabled for writing. */
1031 if (!colormask)
1032 return true;
1033
1034 unsigned blendmask = colormask & blend->blend_enable_4bit;
1035
1036 if (blendmask) {
1037 /* Only commutative blending. */
1038 if (blendmask & ~blend->commutative_4bit)
1039 return false;
1040
1041 if (!dsa_order_invariant.pass_set)
1042 return false;
1043 }
1044
1045 if (colormask & ~blendmask)
1046 return false;
1047
1048 return true;
1049 }
1050
1051 static void
1052 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1053 struct radv_blend_state *blend,
1054 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1055 {
1056 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
1057 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1058 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1059 bool out_of_order_rast = false;
1060 int ps_iter_samples = 1;
1061 uint32_t mask = 0xffff;
1062
1063 if (vkms) {
1064 ms->num_samples = vkms->rasterizationSamples;
1065
1066 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1067 *
1068 * "Sample shading is enabled for a graphics pipeline:
1069 *
1070 * - If the interface of the fragment shader entry point of the
1071 * graphics pipeline includes an input variable decorated
1072 * with SampleId or SamplePosition. In this case
1073 * minSampleShadingFactor takes the value 1.0.
1074 * - Else if the sampleShadingEnable member of the
1075 * VkPipelineMultisampleStateCreateInfo structure specified
1076 * when creating the graphics pipeline is set to VK_TRUE. In
1077 * this case minSampleShadingFactor takes the value of
1078 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1079 *
1080 * Otherwise, sample shading is considered disabled."
1081 */
1082 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.force_persample) {
1083 ps_iter_samples = ms->num_samples;
1084 } else {
1085 ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
1086 }
1087 } else {
1088 ms->num_samples = 1;
1089 }
1090
1091 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1092 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1093 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1094 /* Out-of-order rasterization is explicitly enabled by the
1095 * application.
1096 */
1097 out_of_order_rast = true;
1098 } else {
1099 /* Determine if the driver can enable out-of-order
1100 * rasterization internally.
1101 */
1102 out_of_order_rast =
1103 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1104 }
1105
1106 ms->pa_sc_aa_config = 0;
1107 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1108 S_028804_INCOHERENT_EQAA_READS(1) |
1109 S_028804_INTERPOLATE_COMP_Z(1) |
1110 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1111 ms->pa_sc_mode_cntl_1 =
1112 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1113 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1114 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
1115 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1116 /* always 1: */
1117 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1118 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1119 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1120 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1121 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1122 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1123 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1124 S_028A48_VPORT_SCISSOR_ENABLE(1);
1125
1126 const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line =
1127 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1128 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
1129 if (rast_line) {
1130 ms->pa_sc_mode_cntl_0 |= S_028A48_LINE_STIPPLE_ENABLE(rast_line->stippledLineEnable);
1131 if (rast_line->lineRasterizationMode == VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT) {
1132 /* From the Vulkan spec 1.1.129:
1133 *
1134 * "When VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT lines
1135 * are being rasterized, sample locations may all be
1136 * treated as being at the pixel center (this may
1137 * affect attribute and depth interpolation)."
1138 */
1139 ms->num_samples = 1;
1140 }
1141 }
1142
1143 if (ms->num_samples > 1) {
1144 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1145 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1146 uint32_t z_samples = subpass->depth_stencil_attachment ? subpass->depth_sample_count : ms->num_samples;
1147 unsigned log_samples = util_logbase2(ms->num_samples);
1148 unsigned log_z_samples = util_logbase2(z_samples);
1149 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1150 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1151 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
1152 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1153 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1154 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1155 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1156 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) |
1157 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples) | /* CM_R_028BE0_PA_SC_AA_CONFIG */
1158 S_028BE0_COVERED_CENTROID_IS_CENTER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3);
1159 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1160 if (ps_iter_samples > 1)
1161 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1162 }
1163
1164 if (vkms && vkms->pSampleMask) {
1165 mask = vkms->pSampleMask[0] & 0xffff;
1166 }
1167
1168 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1169 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1170 }
1171
1172 static bool
1173 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1174 {
1175 switch (topology) {
1176 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1177 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1178 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1179 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1180 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1181 return false;
1182 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1183 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1184 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1185 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1186 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1187 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1188 return true;
1189 default:
1190 unreachable("unhandled primitive type");
1191 }
1192 }
1193
1194 static uint32_t
1195 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1196 {
1197 switch (gl_prim) {
1198 case 0: /* GL_POINTS */
1199 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1200 case 1: /* GL_LINES */
1201 case 3: /* GL_LINE_STRIP */
1202 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1203 case 0x8E7A: /* GL_ISOLINES */
1204 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1205
1206 case 4: /* GL_TRIANGLES */
1207 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1208 case 5: /* GL_TRIANGLE_STRIP */
1209 case 7: /* GL_QUADS */
1210 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1211 default:
1212 assert(0);
1213 return 0;
1214 }
1215 }
1216
1217 static uint32_t
1218 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1219 {
1220 switch (topology) {
1221 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1222 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1223 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1224 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1225 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1226 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1227 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1228 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1229 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1230 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1231 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1232 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1233 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1234 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1235 default:
1236 assert(0);
1237 return 0;
1238 }
1239 }
1240
1241 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1242 {
1243 switch(state) {
1244 case VK_DYNAMIC_STATE_VIEWPORT:
1245 case VK_DYNAMIC_STATE_VIEWPORT_WITH_COUNT_EXT:
1246 return RADV_DYNAMIC_VIEWPORT;
1247 case VK_DYNAMIC_STATE_SCISSOR:
1248 case VK_DYNAMIC_STATE_SCISSOR_WITH_COUNT_EXT:
1249 return RADV_DYNAMIC_SCISSOR;
1250 case VK_DYNAMIC_STATE_LINE_WIDTH:
1251 return RADV_DYNAMIC_LINE_WIDTH;
1252 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1253 return RADV_DYNAMIC_DEPTH_BIAS;
1254 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1255 return RADV_DYNAMIC_BLEND_CONSTANTS;
1256 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1257 return RADV_DYNAMIC_DEPTH_BOUNDS;
1258 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1259 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1260 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1261 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1262 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1263 return RADV_DYNAMIC_STENCIL_REFERENCE;
1264 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1265 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1266 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
1267 return RADV_DYNAMIC_SAMPLE_LOCATIONS;
1268 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT:
1269 return RADV_DYNAMIC_LINE_STIPPLE;
1270 case VK_DYNAMIC_STATE_CULL_MODE_EXT:
1271 return RADV_DYNAMIC_CULL_MODE;
1272 case VK_DYNAMIC_STATE_FRONT_FACE_EXT:
1273 return RADV_DYNAMIC_FRONT_FACE;
1274 case VK_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY_EXT:
1275 return RADV_DYNAMIC_PRIMITIVE_TOPOLOGY;
1276 case VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT:
1277 return RADV_DYNAMIC_DEPTH_TEST_ENABLE;
1278 case VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT:
1279 return RADV_DYNAMIC_DEPTH_WRITE_ENABLE;
1280 case VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT:
1281 return RADV_DYNAMIC_DEPTH_COMPARE_OP;
1282 case VK_DYNAMIC_STATE_DEPTH_BOUNDS_TEST_ENABLE_EXT:
1283 return RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE;
1284 case VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT:
1285 return RADV_DYNAMIC_STENCIL_TEST_ENABLE;
1286 case VK_DYNAMIC_STATE_STENCIL_OP_EXT:
1287 return RADV_DYNAMIC_STENCIL_OP;
1288 case VK_DYNAMIC_STATE_VERTEX_INPUT_BINDING_STRIDE_EXT:
1289 return RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE;
1290 default:
1291 unreachable("Unhandled dynamic state");
1292 }
1293 }
1294
1295 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1296 {
1297 uint32_t states = RADV_DYNAMIC_ALL;
1298
1299 /* If rasterization is disabled we do not care about any of the
1300 * dynamic states, since they are all rasterization related only,
1301 * except primitive topology and vertex binding stride.
1302 */
1303 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1304 return RADV_DYNAMIC_PRIMITIVE_TOPOLOGY |
1305 RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE;
1306
1307 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1308 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1309
1310 if (!pCreateInfo->pDepthStencilState ||
1311 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1312 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1313
1314 if (!pCreateInfo->pDepthStencilState ||
1315 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1316 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1317 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1318 RADV_DYNAMIC_STENCIL_REFERENCE);
1319
1320 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1321 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1322
1323 if (!pCreateInfo->pMultisampleState ||
1324 !vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1325 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT))
1326 states &= ~RADV_DYNAMIC_SAMPLE_LOCATIONS;
1327
1328 if (!pCreateInfo->pRasterizationState ||
1329 !vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1330 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT))
1331 states &= ~RADV_DYNAMIC_LINE_STIPPLE;
1332
1333 /* TODO: blend constants & line width. */
1334
1335 return states;
1336 }
1337
1338
1339 static void
1340 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1341 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1342 const struct radv_graphics_pipeline_create_info *extra)
1343 {
1344 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1345 uint32_t states = needed_states;
1346 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1347 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1348
1349 pipeline->dynamic_state = default_dynamic_state;
1350 pipeline->graphics.needed_dynamic_state = needed_states;
1351
1352 if (pCreateInfo->pDynamicState) {
1353 /* Remove all of the states that are marked as dynamic */
1354 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1355 for (uint32_t s = 0; s < count; s++)
1356 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1357 }
1358
1359 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1360
1361 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1362 assert(pCreateInfo->pViewportState);
1363
1364 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1365 if (states & RADV_DYNAMIC_VIEWPORT) {
1366 typed_memcpy(dynamic->viewport.viewports,
1367 pCreateInfo->pViewportState->pViewports,
1368 pCreateInfo->pViewportState->viewportCount);
1369 }
1370 }
1371
1372 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1373 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1374 if (states & RADV_DYNAMIC_SCISSOR) {
1375 typed_memcpy(dynamic->scissor.scissors,
1376 pCreateInfo->pViewportState->pScissors,
1377 pCreateInfo->pViewportState->scissorCount);
1378 }
1379 }
1380
1381 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1382 assert(pCreateInfo->pRasterizationState);
1383 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1384 }
1385
1386 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1387 assert(pCreateInfo->pRasterizationState);
1388 dynamic->depth_bias.bias =
1389 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1390 dynamic->depth_bias.clamp =
1391 pCreateInfo->pRasterizationState->depthBiasClamp;
1392 dynamic->depth_bias.slope =
1393 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1394 }
1395
1396 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1397 *
1398 * pColorBlendState is [...] NULL if the pipeline has rasterization
1399 * disabled or if the subpass of the render pass the pipeline is
1400 * created against does not use any color attachments.
1401 */
1402 if (subpass->has_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1403 assert(pCreateInfo->pColorBlendState);
1404 typed_memcpy(dynamic->blend_constants,
1405 pCreateInfo->pColorBlendState->blendConstants, 4);
1406 }
1407
1408 if (states & RADV_DYNAMIC_CULL_MODE) {
1409 dynamic->cull_mode =
1410 pCreateInfo->pRasterizationState->cullMode;
1411 }
1412
1413 if (states & RADV_DYNAMIC_FRONT_FACE) {
1414 dynamic->front_face =
1415 pCreateInfo->pRasterizationState->frontFace;
1416 }
1417
1418 if (states & RADV_DYNAMIC_PRIMITIVE_TOPOLOGY) {
1419 dynamic->primitive_topology =
1420 si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
1421 if (extra && extra->use_rectlist) {
1422 dynamic->primitive_topology = V_008958_DI_PT_RECTLIST;
1423 }
1424 }
1425
1426 /* If there is no depthstencil attachment, then don't read
1427 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1428 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1429 * no need to override the depthstencil defaults in
1430 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1431 *
1432 * Section 9.2 of the Vulkan 1.0.15 spec says:
1433 *
1434 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1435 * disabled or if the subpass of the render pass the pipeline is created
1436 * against does not use a depth/stencil attachment.
1437 */
1438 if (needed_states && subpass->depth_stencil_attachment) {
1439 assert(pCreateInfo->pDepthStencilState);
1440
1441 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1442 dynamic->depth_bounds.min =
1443 pCreateInfo->pDepthStencilState->minDepthBounds;
1444 dynamic->depth_bounds.max =
1445 pCreateInfo->pDepthStencilState->maxDepthBounds;
1446 }
1447
1448 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1449 dynamic->stencil_compare_mask.front =
1450 pCreateInfo->pDepthStencilState->front.compareMask;
1451 dynamic->stencil_compare_mask.back =
1452 pCreateInfo->pDepthStencilState->back.compareMask;
1453 }
1454
1455 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1456 dynamic->stencil_write_mask.front =
1457 pCreateInfo->pDepthStencilState->front.writeMask;
1458 dynamic->stencil_write_mask.back =
1459 pCreateInfo->pDepthStencilState->back.writeMask;
1460 }
1461
1462 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1463 dynamic->stencil_reference.front =
1464 pCreateInfo->pDepthStencilState->front.reference;
1465 dynamic->stencil_reference.back =
1466 pCreateInfo->pDepthStencilState->back.reference;
1467 }
1468
1469 if (states & RADV_DYNAMIC_DEPTH_TEST_ENABLE) {
1470 dynamic->depth_test_enable =
1471 pCreateInfo->pDepthStencilState->depthTestEnable;
1472 }
1473
1474 if (states & RADV_DYNAMIC_DEPTH_WRITE_ENABLE) {
1475 dynamic->depth_write_enable =
1476 pCreateInfo->pDepthStencilState->depthWriteEnable;
1477 }
1478
1479 if (states & RADV_DYNAMIC_DEPTH_COMPARE_OP) {
1480 dynamic->depth_compare_op =
1481 pCreateInfo->pDepthStencilState->depthCompareOp;
1482 }
1483
1484 if (states & RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE) {
1485 dynamic->depth_bounds_test_enable =
1486 pCreateInfo->pDepthStencilState->depthBoundsTestEnable;
1487 }
1488
1489 if (states & RADV_DYNAMIC_STENCIL_TEST_ENABLE) {
1490 dynamic->stencil_test_enable =
1491 pCreateInfo->pDepthStencilState->stencilTestEnable;
1492 }
1493
1494 if (states & RADV_DYNAMIC_STENCIL_OP) {
1495 dynamic->stencil_op.front.compare_op =
1496 pCreateInfo->pDepthStencilState->front.compareOp;
1497 dynamic->stencil_op.front.fail_op =
1498 pCreateInfo->pDepthStencilState->front.failOp;
1499 dynamic->stencil_op.front.pass_op =
1500 pCreateInfo->pDepthStencilState->front.passOp;
1501 dynamic->stencil_op.front.depth_fail_op =
1502 pCreateInfo->pDepthStencilState->front.depthFailOp;
1503
1504 dynamic->stencil_op.back.compare_op =
1505 pCreateInfo->pDepthStencilState->back.compareOp;
1506 dynamic->stencil_op.back.fail_op =
1507 pCreateInfo->pDepthStencilState->back.failOp;
1508 dynamic->stencil_op.back.pass_op =
1509 pCreateInfo->pDepthStencilState->back.passOp;
1510 dynamic->stencil_op.back.depth_fail_op =
1511 pCreateInfo->pDepthStencilState->back.depthFailOp;
1512 }
1513 }
1514
1515 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1516 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1517 if (needed_states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1518 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1519 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1520 typed_memcpy(dynamic->discard_rectangle.rectangles,
1521 discard_rectangle_info->pDiscardRectangles,
1522 discard_rectangle_info->discardRectangleCount);
1523 }
1524 }
1525
1526 if (needed_states & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
1527 const VkPipelineSampleLocationsStateCreateInfoEXT *sample_location_info =
1528 vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1529 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1530 /* If sampleLocationsEnable is VK_FALSE, the default sample
1531 * locations are used and the values specified in
1532 * sampleLocationsInfo are ignored.
1533 */
1534 if (sample_location_info->sampleLocationsEnable) {
1535 const VkSampleLocationsInfoEXT *pSampleLocationsInfo =
1536 &sample_location_info->sampleLocationsInfo;
1537
1538 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
1539
1540 dynamic->sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
1541 dynamic->sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
1542 dynamic->sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
1543 typed_memcpy(&dynamic->sample_location.locations[0],
1544 pSampleLocationsInfo->pSampleLocations,
1545 pSampleLocationsInfo->sampleLocationsCount);
1546 }
1547 }
1548
1549 const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line_info =
1550 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1551 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
1552 if (needed_states & RADV_DYNAMIC_LINE_STIPPLE) {
1553 dynamic->line_stipple.factor = rast_line_info->lineStippleFactor;
1554 dynamic->line_stipple.pattern = rast_line_info->lineStipplePattern;
1555 }
1556
1557 if (!(states & RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE))
1558 pipeline->graphics.uses_dynamic_stride = true;
1559
1560 pipeline->dynamic_state.mask = states;
1561 }
1562
1563 static void
1564 gfx9_get_gs_info(const struct radv_pipeline_key *key,
1565 const struct radv_pipeline *pipeline,
1566 nir_shader **nir,
1567 struct radv_shader_info *infos,
1568 struct gfx9_gs_info *out)
1569 {
1570 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1571 struct radv_es_output_info *es_info;
1572 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1573 es_info = nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1574 else
1575 es_info = nir[MESA_SHADER_TESS_CTRL] ?
1576 &infos[MESA_SHADER_TESS_EVAL].tes.es_info :
1577 &infos[MESA_SHADER_VERTEX].vs.es_info;
1578
1579 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1580 bool uses_adjacency;
1581 switch(key->topology) {
1582 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1583 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1584 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1585 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1586 uses_adjacency = true;
1587 break;
1588 default:
1589 uses_adjacency = false;
1590 break;
1591 }
1592
1593 /* All these are in dwords: */
1594 /* We can't allow using the whole LDS, because GS waves compete with
1595 * other shader stages for LDS space. */
1596 const unsigned max_lds_size = 8 * 1024;
1597 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1598 unsigned esgs_lds_size;
1599
1600 /* All these are per subgroup: */
1601 const unsigned max_out_prims = 32 * 1024;
1602 const unsigned max_es_verts = 255;
1603 const unsigned ideal_gs_prims = 64;
1604 unsigned max_gs_prims, gs_prims;
1605 unsigned min_es_verts, es_verts, worst_case_es_verts;
1606
1607 if (uses_adjacency || gs_num_invocations > 1)
1608 max_gs_prims = 127 / gs_num_invocations;
1609 else
1610 max_gs_prims = 255;
1611
1612 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1613 * Make sure we don't go over the maximum value.
1614 */
1615 if (gs_info->gs.vertices_out > 0) {
1616 max_gs_prims = MIN2(max_gs_prims,
1617 max_out_prims /
1618 (gs_info->gs.vertices_out * gs_num_invocations));
1619 }
1620 assert(max_gs_prims > 0);
1621
1622 /* If the primitive has adjacency, halve the number of vertices
1623 * that will be reused in multiple primitives.
1624 */
1625 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1626
1627 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1628 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1629
1630 /* Compute ESGS LDS size based on the worst case number of ES vertices
1631 * needed to create the target number of GS prims per subgroup.
1632 */
1633 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1634
1635 /* If total LDS usage is too big, refactor partitions based on ratio
1636 * of ESGS item sizes.
1637 */
1638 if (esgs_lds_size > max_lds_size) {
1639 /* Our target GS Prims Per Subgroup was too large. Calculate
1640 * the maximum number of GS Prims Per Subgroup that will fit
1641 * into LDS, capped by the maximum that the hardware can support.
1642 */
1643 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1644 max_gs_prims);
1645 assert(gs_prims > 0);
1646 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1647 max_es_verts);
1648
1649 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1650 assert(esgs_lds_size <= max_lds_size);
1651 }
1652
1653 /* Now calculate remaining ESGS information. */
1654 if (esgs_lds_size)
1655 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1656 else
1657 es_verts = max_es_verts;
1658
1659 /* Vertices for adjacency primitives are not always reused, so restore
1660 * it for ES_VERTS_PER_SUBGRP.
1661 */
1662 min_es_verts = gs_info->gs.vertices_in;
1663
1664 /* For normal primitives, the VGT only checks if they are past the ES
1665 * verts per subgroup after allocating a full GS primitive and if they
1666 * are, kick off a new subgroup. But if those additional ES verts are
1667 * unique (e.g. not reused) we need to make sure there is enough LDS
1668 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1669 */
1670 es_verts -= min_es_verts - 1;
1671
1672 uint32_t es_verts_per_subgroup = es_verts;
1673 uint32_t gs_prims_per_subgroup = gs_prims;
1674 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1675 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1676 out->lds_size = align(esgs_lds_size, 128) / 128;
1677 out->vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1678 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1679 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1680 out->vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1681 out->vgt_esgs_ring_itemsize = esgs_itemsize;
1682 assert(max_prims_per_subgroup <= max_out_prims);
1683 }
1684
1685 static void clamp_gsprims_to_esverts(unsigned *max_gsprims, unsigned max_esverts,
1686 unsigned min_verts_per_prim, bool use_adjacency)
1687 {
1688 unsigned max_reuse = max_esverts - min_verts_per_prim;
1689 if (use_adjacency)
1690 max_reuse /= 2;
1691 *max_gsprims = MIN2(*max_gsprims, 1 + max_reuse);
1692 }
1693
1694 static unsigned
1695 radv_get_num_input_vertices(nir_shader **nir)
1696 {
1697 if (nir[MESA_SHADER_GEOMETRY]) {
1698 nir_shader *gs = nir[MESA_SHADER_GEOMETRY];
1699
1700 return gs->info.gs.vertices_in;
1701 }
1702
1703 if (nir[MESA_SHADER_TESS_CTRL]) {
1704 nir_shader *tes = nir[MESA_SHADER_TESS_EVAL];
1705
1706 if (tes->info.tess.point_mode)
1707 return 1;
1708 if (tes->info.tess.primitive_mode == GL_ISOLINES)
1709 return 2;
1710 return 3;
1711 }
1712
1713 return 3;
1714 }
1715
1716 static void
1717 gfx10_get_ngg_info(const struct radv_pipeline_key *key,
1718 struct radv_pipeline *pipeline,
1719 nir_shader **nir,
1720 struct radv_shader_info *infos,
1721 struct gfx10_ngg_info *ngg)
1722 {
1723 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1724 struct radv_es_output_info *es_info =
1725 nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1726 unsigned gs_type = nir[MESA_SHADER_GEOMETRY] ? MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX;
1727 unsigned max_verts_per_prim = radv_get_num_input_vertices(nir);
1728 unsigned min_verts_per_prim =
1729 gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1;
1730 unsigned gs_num_invocations = nir[MESA_SHADER_GEOMETRY] ? MAX2(gs_info->gs.invocations, 1) : 1;
1731 bool uses_adjacency;
1732 switch(key->topology) {
1733 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1734 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1735 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1736 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1737 uses_adjacency = true;
1738 break;
1739 default:
1740 uses_adjacency = false;
1741 break;
1742 }
1743
1744 /* All these are in dwords: */
1745 /* We can't allow using the whole LDS, because GS waves compete with
1746 * other shader stages for LDS space.
1747 *
1748 * TODO: We should really take the shader's internal LDS use into
1749 * account. The linker will fail if the size is greater than
1750 * 8K dwords.
1751 */
1752 const unsigned max_lds_size = 8 * 1024 - 768;
1753 const unsigned target_lds_size = max_lds_size;
1754 unsigned esvert_lds_size = 0;
1755 unsigned gsprim_lds_size = 0;
1756
1757 /* All these are per subgroup: */
1758 bool max_vert_out_per_gs_instance = false;
1759 unsigned max_esverts_base = 256;
1760 unsigned max_gsprims_base = 128; /* default prim group size clamp */
1761
1762 /* Hardware has the following non-natural restrictions on the value
1763 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1764 * the draw:
1765 * - at most 252 for any line input primitive type
1766 * - at most 251 for any quad input primitive type
1767 * - at most 251 for triangle strips with adjacency (this happens to
1768 * be the natural limit for triangle *lists* with adjacency)
1769 */
1770 max_esverts_base = MIN2(max_esverts_base, 251 + max_verts_per_prim - 1);
1771
1772 if (gs_type == MESA_SHADER_GEOMETRY) {
1773 unsigned max_out_verts_per_gsprim =
1774 gs_info->gs.vertices_out * gs_num_invocations;
1775
1776 if (max_out_verts_per_gsprim <= 256) {
1777 if (max_out_verts_per_gsprim) {
1778 max_gsprims_base = MIN2(max_gsprims_base,
1779 256 / max_out_verts_per_gsprim);
1780 }
1781 } else {
1782 /* Use special multi-cycling mode in which each GS
1783 * instance gets its own subgroup. Does not work with
1784 * tessellation. */
1785 max_vert_out_per_gs_instance = true;
1786 max_gsprims_base = 1;
1787 max_out_verts_per_gsprim = gs_info->gs.vertices_out;
1788 }
1789
1790 esvert_lds_size = es_info->esgs_itemsize / 4;
1791 gsprim_lds_size = (gs_info->gs.gsvs_vertex_size / 4 + 1) * max_out_verts_per_gsprim;
1792 } else {
1793 /* VS and TES. */
1794 /* LDS size for passing data from GS to ES. */
1795 struct radv_streamout_info *so_info = nir[MESA_SHADER_TESS_CTRL]
1796 ? &infos[MESA_SHADER_TESS_EVAL].so
1797 : &infos[MESA_SHADER_VERTEX].so;
1798
1799 if (so_info->num_outputs)
1800 esvert_lds_size = 4 * so_info->num_outputs + 1;
1801
1802 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1803 * corresponding to the ES thread of the provoking vertex. All
1804 * ES threads load and export PrimitiveID for their thread.
1805 */
1806 if (!nir[MESA_SHADER_TESS_CTRL] &&
1807 infos[MESA_SHADER_VERTEX].vs.outinfo.export_prim_id)
1808 esvert_lds_size = MAX2(esvert_lds_size, 1);
1809 }
1810
1811 unsigned max_gsprims = max_gsprims_base;
1812 unsigned max_esverts = max_esverts_base;
1813
1814 if (esvert_lds_size)
1815 max_esverts = MIN2(max_esverts, target_lds_size / esvert_lds_size);
1816 if (gsprim_lds_size)
1817 max_gsprims = MIN2(max_gsprims, target_lds_size / gsprim_lds_size);
1818
1819 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1820 clamp_gsprims_to_esverts(&max_gsprims, max_esverts, min_verts_per_prim, uses_adjacency);
1821 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1822
1823 if (esvert_lds_size || gsprim_lds_size) {
1824 /* Now that we have a rough proportionality between esverts
1825 * and gsprims based on the primitive type, scale both of them
1826 * down simultaneously based on required LDS space.
1827 *
1828 * We could be smarter about this if we knew how much vertex
1829 * reuse to expect.
1830 */
1831 unsigned lds_total = max_esverts * esvert_lds_size +
1832 max_gsprims * gsprim_lds_size;
1833 if (lds_total > target_lds_size) {
1834 max_esverts = max_esverts * target_lds_size / lds_total;
1835 max_gsprims = max_gsprims * target_lds_size / lds_total;
1836
1837 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1838 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1839 min_verts_per_prim, uses_adjacency);
1840 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1841 }
1842 }
1843
1844 /* Round up towards full wave sizes for better ALU utilization. */
1845 if (!max_vert_out_per_gs_instance) {
1846 unsigned orig_max_esverts;
1847 unsigned orig_max_gsprims;
1848 unsigned wavesize;
1849
1850 if (gs_type == MESA_SHADER_GEOMETRY) {
1851 wavesize = gs_info->wave_size;
1852 } else {
1853 wavesize = nir[MESA_SHADER_TESS_CTRL]
1854 ? infos[MESA_SHADER_TESS_EVAL].wave_size
1855 : infos[MESA_SHADER_VERTEX].wave_size;
1856 }
1857
1858 do {
1859 orig_max_esverts = max_esverts;
1860 orig_max_gsprims = max_gsprims;
1861
1862 max_esverts = align(max_esverts, wavesize);
1863 max_esverts = MIN2(max_esverts, max_esverts_base);
1864 if (esvert_lds_size)
1865 max_esverts = MIN2(max_esverts,
1866 (max_lds_size - max_gsprims * gsprim_lds_size) /
1867 esvert_lds_size);
1868 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1869
1870 max_gsprims = align(max_gsprims, wavesize);
1871 max_gsprims = MIN2(max_gsprims, max_gsprims_base);
1872 if (gsprim_lds_size)
1873 max_gsprims = MIN2(max_gsprims,
1874 (max_lds_size - max_esverts * esvert_lds_size) /
1875 gsprim_lds_size);
1876 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1877 min_verts_per_prim, uses_adjacency);
1878 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1879 } while (orig_max_esverts != max_esverts || orig_max_gsprims != max_gsprims);
1880 }
1881
1882 /* Hardware restriction: minimum value of max_esverts */
1883 max_esverts = MAX2(max_esverts, 23 + max_verts_per_prim);
1884
1885 unsigned max_out_vertices =
1886 max_vert_out_per_gs_instance ? gs_info->gs.vertices_out :
1887 gs_type == MESA_SHADER_GEOMETRY ?
1888 max_gsprims * gs_num_invocations * gs_info->gs.vertices_out :
1889 max_esverts;
1890 assert(max_out_vertices <= 256);
1891
1892 unsigned prim_amp_factor = 1;
1893 if (gs_type == MESA_SHADER_GEOMETRY) {
1894 /* Number of output primitives per GS input primitive after
1895 * GS instancing. */
1896 prim_amp_factor = gs_info->gs.vertices_out;
1897 }
1898
1899 /* The GE only checks against the maximum number of ES verts after
1900 * allocating a full GS primitive. So we need to ensure that whenever
1901 * this check passes, there is enough space for a full primitive without
1902 * vertex reuse.
1903 */
1904 ngg->hw_max_esverts = max_esverts - max_verts_per_prim + 1;
1905 ngg->max_gsprims = max_gsprims;
1906 ngg->max_out_verts = max_out_vertices;
1907 ngg->prim_amp_factor = prim_amp_factor;
1908 ngg->max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
1909 ngg->ngg_emit_size = max_gsprims * gsprim_lds_size;
1910 ngg->esgs_ring_size = 4 * max_esverts * esvert_lds_size;
1911
1912 if (gs_type == MESA_SHADER_GEOMETRY) {
1913 ngg->vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
1914 } else {
1915 ngg->vgt_esgs_ring_itemsize = 1;
1916 }
1917
1918 pipeline->graphics.esgs_ring_size = ngg->esgs_ring_size;
1919
1920 assert(ngg->hw_max_esverts >= 24); /* HW limitation */
1921 }
1922
1923 static void
1924 calculate_gs_ring_sizes(struct radv_pipeline *pipeline,
1925 const struct gfx9_gs_info *gs)
1926 {
1927 struct radv_device *device = pipeline->device;
1928 unsigned num_se = device->physical_device->rad_info.max_se;
1929 unsigned wave_size = 64;
1930 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1931 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1932 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1933 */
1934 unsigned gs_vertex_reuse =
1935 (device->physical_device->rad_info.chip_class >= GFX8 ? 32 : 16) * num_se;
1936 unsigned alignment = 256 * num_se;
1937 /* The maximum size is 63.999 MB per SE. */
1938 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1939 struct radv_shader_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1940
1941 /* Calculate the minimum size. */
1942 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1943 wave_size, alignment);
1944 /* These are recommended sizes, not minimum sizes. */
1945 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1946 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1947 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1948 gs_info->gs.max_gsvs_emit_size;
1949
1950 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1951 esgs_ring_size = align(esgs_ring_size, alignment);
1952 gsvs_ring_size = align(gsvs_ring_size, alignment);
1953
1954 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
1955 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1956
1957 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1958 }
1959
1960 struct radv_shader_variant *
1961 radv_get_shader(struct radv_pipeline *pipeline,
1962 gl_shader_stage stage)
1963 {
1964 if (stage == MESA_SHADER_VERTEX) {
1965 if (pipeline->shaders[MESA_SHADER_VERTEX])
1966 return pipeline->shaders[MESA_SHADER_VERTEX];
1967 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1968 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1969 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1970 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1971 } else if (stage == MESA_SHADER_TESS_EVAL) {
1972 if (!radv_pipeline_has_tess(pipeline))
1973 return NULL;
1974 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1975 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1976 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1977 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1978 }
1979 return pipeline->shaders[stage];
1980 }
1981
1982 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
1983 {
1984 if (radv_pipeline_has_gs(pipeline))
1985 if (radv_pipeline_has_ngg(pipeline))
1986 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
1987 else
1988 return &pipeline->gs_copy_shader->info.vs.outinfo;
1989 else if (radv_pipeline_has_tess(pipeline))
1990 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
1991 else
1992 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
1993 }
1994
1995 static void
1996 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
1997 {
1998 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
1999 int shader_count = 0;
2000
2001 if(shaders[MESA_SHADER_FRAGMENT]) {
2002 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
2003 }
2004 if(shaders[MESA_SHADER_GEOMETRY]) {
2005 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
2006 }
2007 if(shaders[MESA_SHADER_TESS_EVAL]) {
2008 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
2009 }
2010 if(shaders[MESA_SHADER_TESS_CTRL]) {
2011 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
2012 }
2013 if(shaders[MESA_SHADER_VERTEX]) {
2014 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
2015 }
2016
2017 if (shader_count > 1) {
2018 unsigned first = ordered_shaders[shader_count - 1]->info.stage;
2019 unsigned last = ordered_shaders[0]->info.stage;
2020
2021 if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
2022 ordered_shaders[1]->info.has_transform_feedback_varyings)
2023 nir_link_xfb_varyings(ordered_shaders[1], ordered_shaders[0]);
2024
2025 for (int i = 0; i < shader_count; ++i) {
2026 nir_variable_mode mask = 0;
2027
2028 if (ordered_shaders[i]->info.stage != first)
2029 mask = mask | nir_var_shader_in;
2030
2031 if (ordered_shaders[i]->info.stage != last)
2032 mask = mask | nir_var_shader_out;
2033
2034 nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
2035 radv_optimize_nir(ordered_shaders[i], false, false);
2036 }
2037 }
2038
2039 for (int i = 1; i < shader_count; ++i) {
2040 nir_lower_io_arrays_to_elements(ordered_shaders[i],
2041 ordered_shaders[i - 1]);
2042
2043 if (nir_link_opt_varyings(ordered_shaders[i],
2044 ordered_shaders[i - 1]))
2045 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2046
2047 nir_remove_dead_variables(ordered_shaders[i],
2048 nir_var_shader_out, NULL);
2049 nir_remove_dead_variables(ordered_shaders[i - 1],
2050 nir_var_shader_in, NULL);
2051
2052 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
2053 ordered_shaders[i - 1]);
2054
2055 nir_compact_varyings(ordered_shaders[i],
2056 ordered_shaders[i - 1], true);
2057
2058 if (progress) {
2059 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
2060 ac_lower_indirect_derefs(ordered_shaders[i],
2061 pipeline->device->physical_device->rad_info.chip_class);
2062 }
2063 radv_optimize_nir(ordered_shaders[i], false, false);
2064
2065 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
2066 ac_lower_indirect_derefs(ordered_shaders[i - 1],
2067 pipeline->device->physical_device->rad_info.chip_class);
2068 }
2069 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2070 }
2071 }
2072 }
2073
2074 static void
2075 radv_set_linked_driver_locations(struct radv_pipeline *pipeline, nir_shader **shaders,
2076 struct radv_shader_info infos[MESA_SHADER_STAGES])
2077 {
2078 bool has_tess = shaders[MESA_SHADER_TESS_CTRL];
2079 bool has_gs = shaders[MESA_SHADER_GEOMETRY];
2080
2081 if (!has_tess && !has_gs)
2082 return;
2083
2084 unsigned vs_info_idx = MESA_SHADER_VERTEX;
2085 unsigned tes_info_idx = MESA_SHADER_TESS_EVAL;
2086
2087 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2088 /* These are merged into the next stage */
2089 vs_info_idx = has_tess ? MESA_SHADER_TESS_CTRL : MESA_SHADER_GEOMETRY;
2090 tes_info_idx = has_gs ? MESA_SHADER_GEOMETRY : MESA_SHADER_TESS_EVAL;
2091 }
2092
2093 if (has_tess) {
2094 nir_linked_io_var_info vs2tcs =
2095 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_VERTEX], shaders[MESA_SHADER_TESS_CTRL]);
2096 nir_linked_io_var_info tcs2tes =
2097 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_TESS_CTRL], shaders[MESA_SHADER_TESS_EVAL]);
2098
2099 infos[vs_info_idx].vs.num_linked_outputs = vs2tcs.num_linked_io_vars;
2100 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_inputs = vs2tcs.num_linked_io_vars;
2101 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_outputs = tcs2tes.num_linked_io_vars;
2102 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_patch_outputs = tcs2tes.num_linked_patch_io_vars;
2103 infos[tes_info_idx].tes.num_linked_inputs = tcs2tes.num_linked_io_vars;
2104 infos[tes_info_idx].tes.num_linked_patch_inputs = tcs2tes.num_linked_patch_io_vars;
2105
2106 if (has_gs) {
2107 nir_linked_io_var_info tes2gs =
2108 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_TESS_EVAL], shaders[MESA_SHADER_GEOMETRY]);
2109
2110 infos[tes_info_idx].tes.num_linked_outputs = tes2gs.num_linked_io_vars;
2111 infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = tes2gs.num_linked_io_vars;
2112 }
2113 } else if (has_gs) {
2114 nir_linked_io_var_info vs2gs =
2115 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_VERTEX], shaders[MESA_SHADER_GEOMETRY]);
2116
2117 infos[vs_info_idx].vs.num_linked_outputs = vs2gs.num_linked_io_vars;
2118 infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = vs2gs.num_linked_io_vars;
2119 }
2120 }
2121
2122 static uint32_t
2123 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo *input_state,
2124 uint32_t attrib_binding)
2125 {
2126 for (uint32_t i = 0; i < input_state->vertexBindingDescriptionCount; i++) {
2127 const VkVertexInputBindingDescription *input_binding =
2128 &input_state->pVertexBindingDescriptions[i];
2129
2130 if (input_binding->binding == attrib_binding)
2131 return input_binding->stride;
2132 }
2133
2134 return 0;
2135 }
2136
2137 static struct radv_pipeline_key
2138 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
2139 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2140 const struct radv_blend_state *blend)
2141 {
2142 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2143 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2144 const VkPipelineVertexInputStateCreateInfo *input_state =
2145 pCreateInfo->pVertexInputState;
2146 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
2147 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
2148
2149 struct radv_pipeline_key key;
2150 memset(&key, 0, sizeof(key));
2151
2152 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
2153 key.optimisations_disabled = 1;
2154
2155 key.has_multiview_view_index = !!subpass->view_mask;
2156
2157 uint32_t binding_input_rate = 0;
2158 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
2159 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
2160 if (input_state->pVertexBindingDescriptions[i].inputRate) {
2161 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
2162 binding_input_rate |= 1u << binding;
2163 instance_rate_divisors[binding] = 1;
2164 }
2165 }
2166 if (divisor_state) {
2167 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
2168 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
2169 divisor_state->pVertexBindingDivisors[i].divisor;
2170 }
2171 }
2172
2173 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
2174 const VkVertexInputAttributeDescription *desc =
2175 &input_state->pVertexAttributeDescriptions[i];
2176 const struct vk_format_description *format_desc;
2177 unsigned location = desc->location;
2178 unsigned binding = desc->binding;
2179 unsigned num_format, data_format;
2180 int first_non_void;
2181
2182 if (binding_input_rate & (1u << binding)) {
2183 key.instance_rate_inputs |= 1u << location;
2184 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
2185 }
2186
2187 format_desc = vk_format_description(desc->format);
2188 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2189
2190 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2191 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2192
2193 key.vertex_attribute_formats[location] = data_format | (num_format << 4);
2194 key.vertex_attribute_bindings[location] = desc->binding;
2195 key.vertex_attribute_offsets[location] = desc->offset;
2196 key.vertex_attribute_strides[location] = radv_get_attrib_stride(input_state, desc->binding);
2197
2198 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8 &&
2199 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
2200 VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
2201 uint64_t adjust;
2202 switch(format) {
2203 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2204 case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
2205 adjust = RADV_ALPHA_ADJUST_SNORM;
2206 break;
2207 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2208 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
2209 adjust = RADV_ALPHA_ADJUST_SSCALED;
2210 break;
2211 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2212 case VK_FORMAT_A2B10G10R10_SINT_PACK32:
2213 adjust = RADV_ALPHA_ADJUST_SINT;
2214 break;
2215 default:
2216 adjust = 0;
2217 break;
2218 }
2219 key.vertex_alpha_adjust |= adjust << (2 * location);
2220 }
2221
2222 switch (desc->format) {
2223 case VK_FORMAT_B8G8R8A8_UNORM:
2224 case VK_FORMAT_B8G8R8A8_SNORM:
2225 case VK_FORMAT_B8G8R8A8_USCALED:
2226 case VK_FORMAT_B8G8R8A8_SSCALED:
2227 case VK_FORMAT_B8G8R8A8_UINT:
2228 case VK_FORMAT_B8G8R8A8_SINT:
2229 case VK_FORMAT_B8G8R8A8_SRGB:
2230 case VK_FORMAT_A2R10G10B10_UNORM_PACK32:
2231 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2232 case VK_FORMAT_A2R10G10B10_USCALED_PACK32:
2233 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2234 case VK_FORMAT_A2R10G10B10_UINT_PACK32:
2235 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2236 key.vertex_post_shuffle |= 1 << location;
2237 break;
2238 default:
2239 break;
2240 }
2241 }
2242
2243 const VkPipelineTessellationStateCreateInfo *tess =
2244 radv_pipeline_get_tessellation_state(pCreateInfo);
2245 if (tess)
2246 key.tess_input_vertices = tess->patchControlPoints;
2247
2248 const VkPipelineMultisampleStateCreateInfo *vkms =
2249 radv_pipeline_get_multisample_state(pCreateInfo);
2250 if (vkms && vkms->rasterizationSamples > 1) {
2251 uint32_t num_samples = vkms->rasterizationSamples;
2252 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
2253 key.num_samples = num_samples;
2254 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
2255 }
2256
2257 key.col_format = blend->spi_shader_col_format;
2258 key.is_dual_src = blend->mrt0_is_dual_src;
2259 if (pipeline->device->physical_device->rad_info.chip_class < GFX8) {
2260 key.is_int8 = blend->col_format_is_int8;
2261 key.is_int10 = blend->col_format_is_int10;
2262 }
2263
2264 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10)
2265 key.topology = pCreateInfo->pInputAssemblyState->topology;
2266
2267 return key;
2268 }
2269
2270 static bool
2271 radv_nir_stage_uses_xfb(const nir_shader *nir)
2272 {
2273 nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
2274 bool uses_xfb = !!xfb;
2275
2276 ralloc_free(xfb);
2277 return uses_xfb;
2278 }
2279
2280 static void
2281 radv_fill_shader_keys(struct radv_device *device,
2282 struct radv_shader_variant_key *keys,
2283 const struct radv_pipeline_key *key,
2284 nir_shader **nir)
2285 {
2286 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
2287 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
2288 keys[MESA_SHADER_VERTEX].vs.post_shuffle = key->vertex_post_shuffle;
2289 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) {
2290 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
2291 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_formats[i] = key->vertex_attribute_formats[i];
2292 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_bindings[i] = key->vertex_attribute_bindings[i];
2293 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i];
2294 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i];
2295 }
2296 keys[MESA_SHADER_VERTEX].vs.outprim = si_conv_prim_to_gs_out(key->topology);
2297
2298 if (nir[MESA_SHADER_TESS_CTRL]) {
2299 keys[MESA_SHADER_VERTEX].vs_common_out.as_ls = true;
2300 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
2301 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
2302 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
2303
2304 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
2305 }
2306
2307 if (nir[MESA_SHADER_GEOMETRY]) {
2308 if (nir[MESA_SHADER_TESS_CTRL])
2309 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_es = true;
2310 else
2311 keys[MESA_SHADER_VERTEX].vs_common_out.as_es = true;
2312 }
2313
2314 if (device->physical_device->use_ngg) {
2315 if (nir[MESA_SHADER_TESS_CTRL]) {
2316 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = true;
2317 } else {
2318 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = true;
2319 }
2320
2321 if (nir[MESA_SHADER_TESS_CTRL] &&
2322 nir[MESA_SHADER_GEOMETRY] &&
2323 nir[MESA_SHADER_GEOMETRY]->info.gs.invocations *
2324 nir[MESA_SHADER_GEOMETRY]->info.gs.vertices_out > 256) {
2325 /* Fallback to the legacy path if tessellation is
2326 * enabled with extreme geometry because
2327 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2328 * might hang.
2329 */
2330 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2331 }
2332
2333 if (!device->physical_device->use_ngg_gs) {
2334 if (nir[MESA_SHADER_GEOMETRY]) {
2335 if (nir[MESA_SHADER_TESS_CTRL])
2336 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2337 else
2338 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2339 }
2340 }
2341
2342 gl_shader_stage last_xfb_stage = MESA_SHADER_VERTEX;
2343
2344 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
2345 if (nir[i])
2346 last_xfb_stage = i;
2347 }
2348
2349 bool uses_xfb = nir[last_xfb_stage] &&
2350 radv_nir_stage_uses_xfb(nir[last_xfb_stage]);
2351
2352 if (!device->physical_device->use_ngg_streamout && uses_xfb) {
2353 if (nir[MESA_SHADER_TESS_CTRL])
2354 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2355 else
2356 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2357 }
2358
2359 /* Determine if the pipeline is eligible for the NGG passthrough
2360 * mode. It can't be enabled for geometry shaders, for NGG
2361 * streamout or for vertex shaders that export the primitive ID
2362 * (this is checked later because we don't have the info here.)
2363 */
2364 if (!nir[MESA_SHADER_GEOMETRY] && !uses_xfb) {
2365 if (nir[MESA_SHADER_TESS_CTRL] &&
2366 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg) {
2367 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg_passthrough = true;
2368 } else if (nir[MESA_SHADER_VERTEX] &&
2369 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) {
2370 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = true;
2371 }
2372 }
2373 }
2374
2375 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
2376 keys[i].has_multiview_view_index = key->has_multiview_view_index;
2377
2378 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
2379 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
2380 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
2381 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
2382 keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples;
2383 keys[MESA_SHADER_FRAGMENT].fs.is_dual_src = key->is_dual_src;
2384
2385 if (nir[MESA_SHADER_COMPUTE]) {
2386 keys[MESA_SHADER_COMPUTE].cs.subgroup_size = key->compute_subgroup_size;
2387 }
2388 }
2389
2390 static uint8_t
2391 radv_get_wave_size(struct radv_device *device,
2392 const VkPipelineShaderStageCreateInfo *pStage,
2393 gl_shader_stage stage,
2394 const struct radv_shader_variant_key *key)
2395 {
2396 if (stage == MESA_SHADER_GEOMETRY && !key->vs_common_out.as_ngg)
2397 return 64;
2398 else if (stage == MESA_SHADER_COMPUTE) {
2399 if (key->cs.subgroup_size) {
2400 /* Return the required subgroup size if specified. */
2401 return key->cs.subgroup_size;
2402 }
2403 return device->physical_device->cs_wave_size;
2404 }
2405 else if (stage == MESA_SHADER_FRAGMENT)
2406 return device->physical_device->ps_wave_size;
2407 else
2408 return device->physical_device->ge_wave_size;
2409 }
2410
2411 static uint8_t
2412 radv_get_ballot_bit_size(struct radv_device *device,
2413 const VkPipelineShaderStageCreateInfo *pStage,
2414 gl_shader_stage stage,
2415 const struct radv_shader_variant_key *key)
2416 {
2417 if (stage == MESA_SHADER_COMPUTE && key->cs.subgroup_size)
2418 return key->cs.subgroup_size;
2419 return 64;
2420 }
2421
2422 static void
2423 radv_fill_shader_info(struct radv_pipeline *pipeline,
2424 const VkPipelineShaderStageCreateInfo **pStages,
2425 struct radv_shader_variant_key *keys,
2426 struct radv_shader_info *infos,
2427 nir_shader **nir)
2428 {
2429 unsigned active_stages = 0;
2430 unsigned filled_stages = 0;
2431
2432 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2433 if (nir[i])
2434 active_stages |= (1 << i);
2435 }
2436
2437 if (nir[MESA_SHADER_FRAGMENT]) {
2438 radv_nir_shader_info_init(&infos[MESA_SHADER_FRAGMENT]);
2439 radv_nir_shader_info_pass(nir[MESA_SHADER_FRAGMENT],
2440 pipeline->layout,
2441 &keys[MESA_SHADER_FRAGMENT],
2442 &infos[MESA_SHADER_FRAGMENT],
2443 pipeline->device->physical_device->use_llvm);
2444
2445 /* TODO: These are no longer used as keys we should refactor this */
2446 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2447 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2448 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2449 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2450 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2451 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2452 keys[MESA_SHADER_VERTEX].vs_common_out.export_viewport_index =
2453 infos[MESA_SHADER_FRAGMENT].ps.viewport_index_input;
2454 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2455 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2456 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2457 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2458 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2459 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2460 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_viewport_index =
2461 infos[MESA_SHADER_FRAGMENT].ps.viewport_index_input;
2462
2463 /* NGG passthrough mode can't be enabled for vertex shaders
2464 * that export the primitive ID.
2465 *
2466 * TODO: I should really refactor the keys logic.
2467 */
2468 if (nir[MESA_SHADER_VERTEX] &&
2469 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id) {
2470 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = false;
2471 }
2472
2473 filled_stages |= (1 << MESA_SHADER_FRAGMENT);
2474 }
2475
2476 if (nir[MESA_SHADER_TESS_CTRL]) {
2477 infos[MESA_SHADER_TESS_CTRL].tcs.tes_inputs_read =
2478 nir[MESA_SHADER_TESS_EVAL]->info.inputs_read;
2479 infos[MESA_SHADER_TESS_CTRL].tcs.tes_patch_inputs_read =
2480 nir[MESA_SHADER_TESS_EVAL]->info.patch_inputs_read;
2481 }
2482
2483 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2484 nir[MESA_SHADER_TESS_CTRL]) {
2485 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2486 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2487 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2488
2489 radv_nir_shader_info_init(&infos[MESA_SHADER_TESS_CTRL]);
2490
2491 for (int i = 0; i < 2; i++) {
2492 radv_nir_shader_info_pass(combined_nir[i],
2493 pipeline->layout, &key,
2494 &infos[MESA_SHADER_TESS_CTRL],
2495 pipeline->device->physical_device->use_llvm);
2496 }
2497
2498 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2499 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2500 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2501 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2502
2503 filled_stages |= (1 << MESA_SHADER_VERTEX);
2504 filled_stages |= (1 << MESA_SHADER_TESS_CTRL);
2505 }
2506
2507 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2508 nir[MESA_SHADER_GEOMETRY]) {
2509 gl_shader_stage pre_stage = nir[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2510 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2511
2512 radv_nir_shader_info_init(&infos[MESA_SHADER_GEOMETRY]);
2513
2514 for (int i = 0; i < 2; i++) {
2515 radv_nir_shader_info_pass(combined_nir[i],
2516 pipeline->layout,
2517 &keys[pre_stage],
2518 &infos[MESA_SHADER_GEOMETRY],
2519 pipeline->device->physical_device->use_llvm);
2520 }
2521
2522 filled_stages |= (1 << pre_stage);
2523 filled_stages |= (1 << MESA_SHADER_GEOMETRY);
2524 }
2525
2526 active_stages ^= filled_stages;
2527 while (active_stages) {
2528 int i = u_bit_scan(&active_stages);
2529
2530 if (i == MESA_SHADER_TESS_CTRL) {
2531 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs =
2532 util_last_bit64(infos[MESA_SHADER_VERTEX].vs.ls_outputs_written);
2533 }
2534
2535 if (i == MESA_SHADER_TESS_EVAL) {
2536 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2537 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2538 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2539 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2540 }
2541
2542 radv_nir_shader_info_init(&infos[i]);
2543 radv_nir_shader_info_pass(nir[i], pipeline->layout,
2544 &keys[i], &infos[i], pipeline->device->physical_device->use_llvm);
2545 }
2546
2547 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2548 if (nir[i]) {
2549 infos[i].wave_size =
2550 radv_get_wave_size(pipeline->device, pStages[i],
2551 i, &keys[i]);
2552 infos[i].ballot_bit_size =
2553 radv_get_ballot_bit_size(pipeline->device,
2554 pStages[i], i,
2555 &keys[i]);
2556 }
2557 }
2558 }
2559
2560 static void
2561 merge_tess_info(struct shader_info *tes_info,
2562 const struct shader_info *tcs_info)
2563 {
2564 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2565 *
2566 * "PointMode. Controls generation of points rather than triangles
2567 * or lines. This functionality defaults to disabled, and is
2568 * enabled if either shader stage includes the execution mode.
2569 *
2570 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2571 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2572 * and OutputVertices, it says:
2573 *
2574 * "One mode must be set in at least one of the tessellation
2575 * shader stages."
2576 *
2577 * So, the fields can be set in either the TCS or TES, but they must
2578 * agree if set in both. Our backend looks at TES, so bitwise-or in
2579 * the values from the TCS.
2580 */
2581 assert(tcs_info->tess.tcs_vertices_out == 0 ||
2582 tes_info->tess.tcs_vertices_out == 0 ||
2583 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
2584 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
2585
2586 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2587 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2588 tcs_info->tess.spacing == tes_info->tess.spacing);
2589 tes_info->tess.spacing |= tcs_info->tess.spacing;
2590
2591 assert(tcs_info->tess.primitive_mode == 0 ||
2592 tes_info->tess.primitive_mode == 0 ||
2593 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
2594 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
2595 tes_info->tess.ccw |= tcs_info->tess.ccw;
2596 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
2597 }
2598
2599 static
2600 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT *ext)
2601 {
2602 if (!ext)
2603 return;
2604
2605 if (ext->pPipelineCreationFeedback) {
2606 ext->pPipelineCreationFeedback->flags = 0;
2607 ext->pPipelineCreationFeedback->duration = 0;
2608 }
2609
2610 for (unsigned i = 0; i < ext->pipelineStageCreationFeedbackCount; ++i) {
2611 ext->pPipelineStageCreationFeedbacks[i].flags = 0;
2612 ext->pPipelineStageCreationFeedbacks[i].duration = 0;
2613 }
2614 }
2615
2616 static
2617 void radv_start_feedback(VkPipelineCreationFeedbackEXT *feedback)
2618 {
2619 if (!feedback)
2620 return;
2621
2622 feedback->duration -= radv_get_current_time();
2623 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT;
2624 }
2625
2626 static
2627 void radv_stop_feedback(VkPipelineCreationFeedbackEXT *feedback, bool cache_hit)
2628 {
2629 if (!feedback)
2630 return;
2631
2632 feedback->duration += radv_get_current_time();
2633 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT |
2634 (cache_hit ? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT : 0);
2635 }
2636
2637 VkResult radv_create_shaders(struct radv_pipeline *pipeline,
2638 struct radv_device *device,
2639 struct radv_pipeline_cache *cache,
2640 const struct radv_pipeline_key *key,
2641 const VkPipelineShaderStageCreateInfo **pStages,
2642 const VkPipelineCreateFlags flags,
2643 VkPipelineCreationFeedbackEXT *pipeline_feedback,
2644 VkPipelineCreationFeedbackEXT **stage_feedbacks)
2645 {
2646 struct radv_shader_module fs_m = {0};
2647 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2648 nir_shader *nir[MESA_SHADER_STAGES] = {0};
2649 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2650 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{{0}}}}};
2651 struct radv_shader_info infos[MESA_SHADER_STAGES] = {0};
2652 unsigned char hash[20], gs_copy_hash[20];
2653 bool keep_executable_info = (flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR) || device->keep_shader_info;
2654 bool keep_statistic_info = (flags & VK_PIPELINE_CREATE_CAPTURE_STATISTICS_BIT_KHR) ||
2655 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) ||
2656 device->keep_shader_info;
2657
2658 radv_start_feedback(pipeline_feedback);
2659
2660 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2661 if (pStages[i]) {
2662 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
2663 if (modules[i]->nir)
2664 _mesa_sha1_compute(modules[i]->nir->info.name,
2665 strlen(modules[i]->nir->info.name),
2666 modules[i]->sha1);
2667
2668 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
2669 }
2670 }
2671
2672 radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device));
2673 memcpy(gs_copy_hash, hash, 20);
2674 gs_copy_hash[0] ^= 1;
2675
2676 bool found_in_application_cache = true;
2677 if (modules[MESA_SHADER_GEOMETRY] && !keep_executable_info && !keep_statistic_info) {
2678 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2679 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants,
2680 &found_in_application_cache);
2681 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
2682 }
2683
2684 if (!keep_executable_info && !keep_statistic_info &&
2685 radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders,
2686 &found_in_application_cache) &&
2687 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
2688 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2689 return VK_SUCCESS;
2690 }
2691
2692 if (flags & VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_EXT) {
2693 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2694 return VK_PIPELINE_COMPILE_REQUIRED_EXT;
2695 }
2696
2697 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
2698 nir_builder fs_b;
2699 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2700 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2701 fs_m.nir = fs_b.shader;
2702 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2703 }
2704
2705 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2706 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
2707 unsigned subgroup_size = 64, ballot_bit_size = 64;
2708
2709 if (!modules[i])
2710 continue;
2711
2712 radv_start_feedback(stage_feedbacks[i]);
2713
2714 if (key->compute_subgroup_size) {
2715 /* Only compute shaders currently support requiring a
2716 * specific subgroup size.
2717 */
2718 assert(i == MESA_SHADER_COMPUTE);
2719 subgroup_size = key->compute_subgroup_size;
2720 ballot_bit_size = key->compute_subgroup_size;
2721 }
2722
2723 nir[i] = radv_shader_compile_to_nir(device, modules[i],
2724 stage ? stage->pName : "main", i,
2725 stage ? stage->pSpecializationInfo : NULL,
2726 flags, pipeline->layout,
2727 subgroup_size, ballot_bit_size);
2728
2729 /* We don't want to alter meta shaders IR directly so clone it
2730 * first.
2731 */
2732 if (nir[i]->info.name) {
2733 nir[i] = nir_shader_clone(NULL, nir[i]);
2734 }
2735
2736 radv_stop_feedback(stage_feedbacks[i], false);
2737 }
2738
2739 if (nir[MESA_SHADER_TESS_CTRL]) {
2740 nir_lower_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
2741 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
2742 }
2743
2744 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
2745 radv_link_shaders(pipeline, nir);
2746
2747 radv_set_linked_driver_locations(pipeline, nir, infos);
2748
2749 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2750 if (nir[i]) {
2751 /* do this again since information such as outputs_read can be out-of-date */
2752 nir_shader_gather_info(nir[i], nir_shader_get_entrypoint(nir[i]));
2753
2754 if (device->physical_device->use_llvm) {
2755 NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
2756 } else {
2757 NIR_PASS_V(nir[i], nir_lower_non_uniform_access,
2758 nir_lower_non_uniform_ubo_access |
2759 nir_lower_non_uniform_ssbo_access |
2760 nir_lower_non_uniform_texture_access |
2761 nir_lower_non_uniform_image_access);
2762 }
2763 }
2764 }
2765
2766 if (nir[MESA_SHADER_FRAGMENT])
2767 radv_lower_fs_io(nir[MESA_SHADER_FRAGMENT]);
2768
2769 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2770 if (radv_can_dump_shader(device, modules[i], false))
2771 nir_print_shader(nir[i], stderr);
2772 }
2773
2774 radv_fill_shader_keys(device, keys, key, nir);
2775
2776 radv_fill_shader_info(pipeline, pStages, keys, infos, nir);
2777
2778 if ((nir[MESA_SHADER_VERTEX] &&
2779 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) ||
2780 (nir[MESA_SHADER_TESS_EVAL] &&
2781 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg)) {
2782 struct gfx10_ngg_info *ngg_info;
2783
2784 if (nir[MESA_SHADER_GEOMETRY])
2785 ngg_info = &infos[MESA_SHADER_GEOMETRY].ngg_info;
2786 else if (nir[MESA_SHADER_TESS_CTRL])
2787 ngg_info = &infos[MESA_SHADER_TESS_EVAL].ngg_info;
2788 else
2789 ngg_info = &infos[MESA_SHADER_VERTEX].ngg_info;
2790
2791 gfx10_get_ngg_info(key, pipeline, nir, infos, ngg_info);
2792 } else if (nir[MESA_SHADER_GEOMETRY]) {
2793 struct gfx9_gs_info *gs_info =
2794 &infos[MESA_SHADER_GEOMETRY].gs_ring_info;
2795
2796 gfx9_get_gs_info(key, pipeline, nir, infos, gs_info);
2797 }
2798
2799 if(modules[MESA_SHADER_GEOMETRY]) {
2800 struct radv_shader_binary *gs_copy_binary = NULL;
2801 if (!pipeline->gs_copy_shader &&
2802 !radv_pipeline_has_ngg(pipeline)) {
2803 struct radv_shader_info info = {};
2804 struct radv_shader_variant_key key = {};
2805
2806 key.has_multiview_view_index =
2807 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index;
2808
2809 radv_nir_shader_info_pass(nir[MESA_SHADER_GEOMETRY],
2810 pipeline->layout, &key,
2811 &info, pipeline->device->physical_device->use_llvm);
2812 info.wave_size = 64; /* Wave32 not supported. */
2813 info.ballot_bit_size = 64;
2814
2815 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2816 device, nir[MESA_SHADER_GEOMETRY], &info,
2817 &gs_copy_binary, keep_executable_info, keep_statistic_info,
2818 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2819 }
2820
2821 if (!keep_executable_info && !keep_statistic_info && pipeline->gs_copy_shader) {
2822 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2823 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2824
2825 binaries[MESA_SHADER_GEOMETRY] = gs_copy_binary;
2826 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2827
2828 radv_pipeline_cache_insert_shaders(device, cache,
2829 gs_copy_hash,
2830 variants,
2831 binaries);
2832 }
2833 free(gs_copy_binary);
2834 }
2835
2836 if (nir[MESA_SHADER_FRAGMENT]) {
2837 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
2838 radv_start_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT]);
2839
2840 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2841 radv_shader_variant_compile(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
2842 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
2843 infos + MESA_SHADER_FRAGMENT,
2844 keep_executable_info, keep_statistic_info,
2845 &binaries[MESA_SHADER_FRAGMENT]);
2846
2847 radv_stop_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT], false);
2848 }
2849 }
2850
2851 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
2852 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
2853 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2854 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2855 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2856
2857 radv_start_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL]);
2858
2859 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
2860 pipeline->layout,
2861 &key, &infos[MESA_SHADER_TESS_CTRL], keep_executable_info,
2862 keep_statistic_info, &binaries[MESA_SHADER_TESS_CTRL]);
2863
2864 radv_stop_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL], false);
2865 }
2866 modules[MESA_SHADER_VERTEX] = NULL;
2867 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2868 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2869 }
2870
2871 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
2872 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2873 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
2874 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2875
2876 radv_start_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY]);
2877
2878 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2879 pipeline->layout,
2880 &keys[pre_stage], &infos[MESA_SHADER_GEOMETRY], keep_executable_info,
2881 keep_statistic_info, &binaries[MESA_SHADER_GEOMETRY]);
2882
2883 radv_stop_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY], false);
2884 }
2885 modules[pre_stage] = NULL;
2886 }
2887
2888 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2889 if(modules[i] && !pipeline->shaders[i]) {
2890 if (i == MESA_SHADER_TESS_CTRL) {
2891 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.ls_outputs_written);
2892 }
2893 if (i == MESA_SHADER_TESS_EVAL) {
2894 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2895 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2896 }
2897
2898 radv_start_feedback(stage_feedbacks[i]);
2899
2900 pipeline->shaders[i] = radv_shader_variant_compile(device, modules[i], &nir[i], 1,
2901 pipeline->layout,
2902 keys + i, infos + i, keep_executable_info,
2903 keep_statistic_info, &binaries[i]);
2904
2905 radv_stop_feedback(stage_feedbacks[i], false);
2906 }
2907 }
2908
2909 if (!keep_executable_info && !keep_statistic_info) {
2910 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
2911 binaries);
2912 }
2913
2914 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2915 free(binaries[i]);
2916 if (nir[i]) {
2917 ralloc_free(nir[i]);
2918
2919 if (radv_can_dump_shader_stats(device, modules[i]))
2920 radv_shader_dump_stats(device,
2921 pipeline->shaders[i],
2922 i, stderr);
2923 }
2924 }
2925
2926 if (fs_m.nir)
2927 ralloc_free(fs_m.nir);
2928
2929 radv_stop_feedback(pipeline_feedback, false);
2930 return VK_SUCCESS;
2931 }
2932
2933 static uint32_t
2934 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
2935 gl_shader_stage stage, enum chip_class chip_class)
2936 {
2937 bool has_gs = radv_pipeline_has_gs(pipeline);
2938 bool has_tess = radv_pipeline_has_tess(pipeline);
2939 bool has_ngg = radv_pipeline_has_ngg(pipeline);
2940
2941 switch (stage) {
2942 case MESA_SHADER_FRAGMENT:
2943 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
2944 case MESA_SHADER_VERTEX:
2945 if (has_tess) {
2946 if (chip_class >= GFX10) {
2947 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
2948 } else if (chip_class == GFX9) {
2949 return R_00B430_SPI_SHADER_USER_DATA_LS_0;
2950 } else {
2951 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
2952 }
2953
2954 }
2955
2956 if (has_gs) {
2957 if (chip_class >= GFX10) {
2958 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2959 } else {
2960 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
2961 }
2962 }
2963
2964 if (has_ngg)
2965 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2966
2967 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2968 case MESA_SHADER_GEOMETRY:
2969 return chip_class == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2970 R_00B230_SPI_SHADER_USER_DATA_GS_0;
2971 case MESA_SHADER_COMPUTE:
2972 return R_00B900_COMPUTE_USER_DATA_0;
2973 case MESA_SHADER_TESS_CTRL:
2974 return chip_class == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2975 R_00B430_SPI_SHADER_USER_DATA_HS_0;
2976 case MESA_SHADER_TESS_EVAL:
2977 if (has_gs) {
2978 return chip_class >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0 :
2979 R_00B330_SPI_SHADER_USER_DATA_ES_0;
2980 } else if (has_ngg) {
2981 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2982 } else {
2983 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2984 }
2985 default:
2986 unreachable("unknown shader");
2987 }
2988 }
2989
2990 struct radv_bin_size_entry {
2991 unsigned bpp;
2992 VkExtent2D extent;
2993 };
2994
2995 static VkExtent2D
2996 radv_gfx9_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
2997 {
2998 static const struct radv_bin_size_entry color_size_table[][3][9] = {
2999 {
3000 /* One RB / SE */
3001 {
3002 /* One shader engine */
3003 { 0, {128, 128}},
3004 { 1, { 64, 128}},
3005 { 2, { 32, 128}},
3006 { 3, { 16, 128}},
3007 { 17, { 0, 0}},
3008 { UINT_MAX, { 0, 0}},
3009 },
3010 {
3011 /* Two shader engines */
3012 { 0, {128, 128}},
3013 { 2, { 64, 128}},
3014 { 3, { 32, 128}},
3015 { 5, { 16, 128}},
3016 { 17, { 0, 0}},
3017 { UINT_MAX, { 0, 0}},
3018 },
3019 {
3020 /* Four shader engines */
3021 { 0, {128, 128}},
3022 { 3, { 64, 128}},
3023 { 5, { 16, 128}},
3024 { 17, { 0, 0}},
3025 { UINT_MAX, { 0, 0}},
3026 },
3027 },
3028 {
3029 /* Two RB / SE */
3030 {
3031 /* One shader engine */
3032 { 0, {128, 128}},
3033 { 2, { 64, 128}},
3034 { 3, { 32, 128}},
3035 { 5, { 16, 128}},
3036 { 33, { 0, 0}},
3037 { UINT_MAX, { 0, 0}},
3038 },
3039 {
3040 /* Two shader engines */
3041 { 0, {128, 128}},
3042 { 3, { 64, 128}},
3043 { 5, { 32, 128}},
3044 { 9, { 16, 128}},
3045 { 33, { 0, 0}},
3046 { UINT_MAX, { 0, 0}},
3047 },
3048 {
3049 /* Four shader engines */
3050 { 0, {256, 256}},
3051 { 2, {128, 256}},
3052 { 3, {128, 128}},
3053 { 5, { 64, 128}},
3054 { 9, { 16, 128}},
3055 { 33, { 0, 0}},
3056 { UINT_MAX, { 0, 0}},
3057 },
3058 },
3059 {
3060 /* Four RB / SE */
3061 {
3062 /* One shader engine */
3063 { 0, {128, 256}},
3064 { 2, {128, 128}},
3065 { 3, { 64, 128}},
3066 { 5, { 32, 128}},
3067 { 9, { 16, 128}},