projects / mesa.git / blob
? search:


6d4df832fe5a43ede2b3efe631c8f18f0f25bac4
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
33 #include "radv_cs.h"
34 #include "radv_shader.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
39 #include "vk_util.h"
40
41 #include "sid.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
48 #include "ac_shader_util.h"
49
50 struct radv_blend_state {
51 uint32_t blend_enable_4bit;
52 uint32_t need_src_alpha;
53
54 uint32_t cb_color_control;
55 uint32_t cb_target_mask;
56 uint32_t cb_target_enabled_4bit;
57 uint32_t sx_mrt_blend_opt[8];
58 uint32_t cb_blend_control[8];
59
60 uint32_t spi_shader_col_format;
61 uint32_t col_format_is_int8;
62 uint32_t col_format_is_int10;
63 uint32_t cb_shader_mask;
64 uint32_t db_alpha_to_mask;
65
66 uint32_t commutative_4bit;
67
68 bool single_cb_enable;
69 bool mrt0_is_dual_src;
70 };
71
72 struct radv_dsa_order_invariance {
73 /* Whether the final result in Z/S buffers is guaranteed to be
74 * invariant under changes to the order in which fragments arrive.
75 */
76 bool zs;
77
78 /* Whether the set of fragments that pass the combined Z/S test is
79 * guaranteed to be invariant under changes to the order in which
80 * fragments arrive.
81 */
82 bool pass_set;
83 };
84
85 static const VkPipelineMultisampleStateCreateInfo *
86 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
87 {
88 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
89 return pCreateInfo->pMultisampleState;
90 return NULL;
91 }
92
93 static const VkPipelineTessellationStateCreateInfo *
94 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
95 {
96 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
97 if (pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT ||
98 pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) {
99 return pCreateInfo->pTessellationState;
100 }
101 }
102 return NULL;
103 }
104
105 static const VkPipelineDepthStencilStateCreateInfo *
106 radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
107 {
108 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
109 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
110
111 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
112 subpass->depth_stencil_attachment)
113 return pCreateInfo->pDepthStencilState;
114 return NULL;
115 }
116
117 static const VkPipelineColorBlendStateCreateInfo *
118 radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
119 {
120 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
121 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
122
123 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
124 subpass->has_color_att)
125 return pCreateInfo->pColorBlendState;
126 return NULL;
127 }
128
129 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline)
130 {
131 struct radv_shader_variant *variant = NULL;
132 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
133 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
134 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
135 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
136 else if (pipeline->shaders[MESA_SHADER_VERTEX])
137 variant = pipeline->shaders[MESA_SHADER_VERTEX];
138 else
139 return false;
140 return variant->info.is_ngg;
141 }
142
143 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline *pipeline)
144 {
145 assert(radv_pipeline_has_ngg(pipeline));
146
147 struct radv_shader_variant *variant = NULL;
148 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
149 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
150 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
151 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
152 else if (pipeline->shaders[MESA_SHADER_VERTEX])
153 variant = pipeline->shaders[MESA_SHADER_VERTEX];
154 else
155 return false;
156 return variant->info.is_ngg_passthrough;
157 }
158
159 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline)
160 {
161 if (!radv_pipeline_has_gs(pipeline))
162 return false;
163
164 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
165 * On GFX10, it might be required in rare cases if it's not possible to
166 * enable NGG.
167 */
168 if (radv_pipeline_has_ngg(pipeline))
169 return false;
170
171 assert(pipeline->gs_copy_shader);
172 return true;
173 }
174
175 static void
176 radv_pipeline_destroy(struct radv_device *device,
177 struct radv_pipeline *pipeline,
178 const VkAllocationCallbacks* allocator)
179 {
180 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
181 if (pipeline->shaders[i])
182 radv_shader_variant_destroy(device, pipeline->shaders[i]);
183
184 if (pipeline->gs_copy_shader)
185 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
186
187 if(pipeline->cs.buf)
188 free(pipeline->cs.buf);
189
190 vk_object_base_finish(&pipeline->base);
191 vk_free2(&device->vk.alloc, allocator, pipeline);
192 }
193
194 void radv_DestroyPipeline(
195 VkDevice _device,
196 VkPipeline _pipeline,
197 const VkAllocationCallbacks* pAllocator)
198 {
199 RADV_FROM_HANDLE(radv_device, device, _device);
200 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
201
202 if (!_pipeline)
203 return;
204
205 radv_pipeline_destroy(device, pipeline, pAllocator);
206 }
207
208 static uint32_t get_hash_flags(struct radv_device *device)
209 {
210 uint32_t hash_flags = 0;
211
212 if (device->instance->debug_flags & RADV_DEBUG_NO_NGG)
213 hash_flags |= RADV_HASH_SHADER_NO_NGG;
214 if (device->physical_device->cs_wave_size == 32)
215 hash_flags |= RADV_HASH_SHADER_CS_WAVE32;
216 if (device->physical_device->ps_wave_size == 32)
217 hash_flags |= RADV_HASH_SHADER_PS_WAVE32;
218 if (device->physical_device->ge_wave_size == 32)
219 hash_flags |= RADV_HASH_SHADER_GE_WAVE32;
220 if (device->physical_device->use_llvm)
221 hash_flags |= RADV_HASH_SHADER_LLVM;
222 return hash_flags;
223 }
224
225 static void
226 radv_pipeline_init_scratch(struct radv_device *device,
227 struct radv_pipeline *pipeline)
228 {
229 unsigned scratch_bytes_per_wave = 0;
230 unsigned max_waves = 0;
231 unsigned min_waves = 1;
232
233 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
234 if (pipeline->shaders[i] &&
235 pipeline->shaders[i]->config.scratch_bytes_per_wave) {
236 unsigned max_stage_waves = device->scratch_waves;
237
238 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
239 pipeline->shaders[i]->config.scratch_bytes_per_wave);
240
241 max_stage_waves = MIN2(max_stage_waves,
242 4 * device->physical_device->rad_info.num_good_compute_units *
243 (256 / pipeline->shaders[i]->config.num_vgprs));
244 max_waves = MAX2(max_waves, max_stage_waves);
245 }
246 }
247
248 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
249 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
250 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
251 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
252 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
253 }
254
255 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
256 pipeline->max_waves = max_waves;
257 }
258
259 static uint32_t si_translate_blend_logic_op(VkLogicOp op)
260 {
261 switch (op) {
262 case VK_LOGIC_OP_CLEAR:
263 return V_028808_ROP3_CLEAR;
264 case VK_LOGIC_OP_AND:
265 return V_028808_ROP3_AND;
266 case VK_LOGIC_OP_AND_REVERSE:
267 return V_028808_ROP3_AND_REVERSE;
268 case VK_LOGIC_OP_COPY:
269 return V_028808_ROP3_COPY;
270 case VK_LOGIC_OP_AND_INVERTED:
271 return V_028808_ROP3_AND_INVERTED;
272 case VK_LOGIC_OP_NO_OP:
273 return V_028808_ROP3_NO_OP;
274 case VK_LOGIC_OP_XOR:
275 return V_028808_ROP3_XOR;
276 case VK_LOGIC_OP_OR:
277 return V_028808_ROP3_OR;
278 case VK_LOGIC_OP_NOR:
279 return V_028808_ROP3_NOR;
280 case VK_LOGIC_OP_EQUIVALENT:
281 return V_028808_ROP3_EQUIVALENT;
282 case VK_LOGIC_OP_INVERT:
283 return V_028808_ROP3_INVERT;
284 case VK_LOGIC_OP_OR_REVERSE:
285 return V_028808_ROP3_OR_REVERSE;
286 case VK_LOGIC_OP_COPY_INVERTED:
287 return V_028808_ROP3_COPY_INVERTED;
288 case VK_LOGIC_OP_OR_INVERTED:
289 return V_028808_ROP3_OR_INVERTED;
290 case VK_LOGIC_OP_NAND:
291 return V_028808_ROP3_NAND;
292 case VK_LOGIC_OP_SET:
293 return V_028808_ROP3_SET;
294 default:
295 unreachable("Unhandled logic op");
296 }
297 }
298
299
300 static uint32_t si_translate_blend_function(VkBlendOp op)
301 {
302 switch (op) {
303 case VK_BLEND_OP_ADD:
304 return V_028780_COMB_DST_PLUS_SRC;
305 case VK_BLEND_OP_SUBTRACT:
306 return V_028780_COMB_SRC_MINUS_DST;
307 case VK_BLEND_OP_REVERSE_SUBTRACT:
308 return V_028780_COMB_DST_MINUS_SRC;
309 case VK_BLEND_OP_MIN:
310 return V_028780_COMB_MIN_DST_SRC;
311 case VK_BLEND_OP_MAX:
312 return V_028780_COMB_MAX_DST_SRC;
313 default:
314 return 0;
315 }
316 }
317
318 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
319 {
320 switch (factor) {
321 case VK_BLEND_FACTOR_ZERO:
322 return V_028780_BLEND_ZERO;
323 case VK_BLEND_FACTOR_ONE:
324 return V_028780_BLEND_ONE;
325 case VK_BLEND_FACTOR_SRC_COLOR:
326 return V_028780_BLEND_SRC_COLOR;
327 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
328 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
329 case VK_BLEND_FACTOR_DST_COLOR:
330 return V_028780_BLEND_DST_COLOR;
331 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
332 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
333 case VK_BLEND_FACTOR_SRC_ALPHA:
334 return V_028780_BLEND_SRC_ALPHA;
335 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
336 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
337 case VK_BLEND_FACTOR_DST_ALPHA:
338 return V_028780_BLEND_DST_ALPHA;
339 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
340 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
341 case VK_BLEND_FACTOR_CONSTANT_COLOR:
342 return V_028780_BLEND_CONSTANT_COLOR;
343 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
344 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
345 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
346 return V_028780_BLEND_CONSTANT_ALPHA;
347 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
348 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
349 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
350 return V_028780_BLEND_SRC_ALPHA_SATURATE;
351 case VK_BLEND_FACTOR_SRC1_COLOR:
352 return V_028780_BLEND_SRC1_COLOR;
353 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
354 return V_028780_BLEND_INV_SRC1_COLOR;
355 case VK_BLEND_FACTOR_SRC1_ALPHA:
356 return V_028780_BLEND_SRC1_ALPHA;
357 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
358 return V_028780_BLEND_INV_SRC1_ALPHA;
359 default:
360 return 0;
361 }
362 }
363
364 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
365 {
366 switch (op) {
367 case VK_BLEND_OP_ADD:
368 return V_028760_OPT_COMB_ADD;
369 case VK_BLEND_OP_SUBTRACT:
370 return V_028760_OPT_COMB_SUBTRACT;
371 case VK_BLEND_OP_REVERSE_SUBTRACT:
372 return V_028760_OPT_COMB_REVSUBTRACT;
373 case VK_BLEND_OP_MIN:
374 return V_028760_OPT_COMB_MIN;
375 case VK_BLEND_OP_MAX:
376 return V_028760_OPT_COMB_MAX;
377 default:
378 return V_028760_OPT_COMB_BLEND_DISABLED;
379 }
380 }
381
382 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
383 {
384 switch (factor) {
385 case VK_BLEND_FACTOR_ZERO:
386 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
387 case VK_BLEND_FACTOR_ONE:
388 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
389 case VK_BLEND_FACTOR_SRC_COLOR:
390 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
391 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
392 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
393 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
394 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
395 case VK_BLEND_FACTOR_SRC_ALPHA:
396 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
397 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
398 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
399 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
400 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
401 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
402 default:
403 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
404 }
405 }
406
407 /**
408 * Get rid of DST in the blend factors by commuting the operands:
409 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
410 */
411 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
412 unsigned *dst_factor, unsigned expected_dst,
413 unsigned replacement_src)
414 {
415 if (*src_factor == expected_dst &&
416 *dst_factor == VK_BLEND_FACTOR_ZERO) {
417 *src_factor = VK_BLEND_FACTOR_ZERO;
418 *dst_factor = replacement_src;
419
420 /* Commuting the operands requires reversing subtractions. */
421 if (*func == VK_BLEND_OP_SUBTRACT)
422 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
423 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
424 *func = VK_BLEND_OP_SUBTRACT;
425 }
426 }
427
428 static bool si_blend_factor_uses_dst(unsigned factor)
429 {
430 return factor == VK_BLEND_FACTOR_DST_COLOR ||
431 factor == VK_BLEND_FACTOR_DST_ALPHA ||
432 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
433 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
434 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
435 }
436
437 static bool is_dual_src(VkBlendFactor factor)
438 {
439 switch (factor) {
440 case VK_BLEND_FACTOR_SRC1_COLOR:
441 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
442 case VK_BLEND_FACTOR_SRC1_ALPHA:
443 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
444 return true;
445 default:
446 return false;
447 }
448 }
449
450 static unsigned radv_choose_spi_color_format(VkFormat vk_format,
451 bool blend_enable,
452 bool blend_need_alpha)
453 {
454 const struct vk_format_description *desc = vk_format_description(vk_format);
455 struct ac_spi_color_formats formats = {};
456 unsigned format, ntype, swap;
457
458 format = radv_translate_colorformat(vk_format);
459 ntype = radv_translate_color_numformat(vk_format, desc,
460 vk_format_get_first_non_void_channel(vk_format));
461 swap = radv_translate_colorswap(vk_format, false);
462
463 ac_choose_spi_color_formats(format, swap, ntype, false, &formats);
464
465 if (blend_enable && blend_need_alpha)
466 return formats.blend_alpha;
467 else if(blend_need_alpha)
468 return formats.alpha;
469 else if(blend_enable)
470 return formats.blend;
471 else
472 return formats.normal;
473 }
474
475 static bool
476 format_is_int8(VkFormat format)
477 {
478 const struct vk_format_description *desc = vk_format_description(format);
479 int channel = vk_format_get_first_non_void_channel(format);
480
481 return channel >= 0 && desc->channel[channel].pure_integer &&
482 desc->channel[channel].size == 8;
483 }
484
485 static bool
486 format_is_int10(VkFormat format)
487 {
488 const struct vk_format_description *desc = vk_format_description(format);
489
490 if (desc->nr_channels != 4)
491 return false;
492 for (unsigned i = 0; i < 4; i++) {
493 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
494 return true;
495 }
496 return false;
497 }
498
499 static void
500 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
501 const VkGraphicsPipelineCreateInfo *pCreateInfo,
502 struct radv_blend_state *blend)
503 {
504 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
505 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
506 unsigned col_format = 0, is_int8 = 0, is_int10 = 0;
507 unsigned num_targets;
508
509 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
510 unsigned cf;
511
512 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED ||
513 !(blend->cb_target_mask & (0xfu << (i * 4)))) {
514 cf = V_028714_SPI_SHADER_ZERO;
515 } else {
516 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
517 bool blend_enable =
518 blend->blend_enable_4bit & (0xfu << (i * 4));
519
520 cf = radv_choose_spi_color_format(attachment->format,
521 blend_enable,
522 blend->need_src_alpha & (1 << i));
523
524 if (format_is_int8(attachment->format))
525 is_int8 |= 1 << i;
526 if (format_is_int10(attachment->format))
527 is_int10 |= 1 << i;
528 }
529
530 col_format |= cf << (4 * i);
531 }
532
533 if (!(col_format & 0xf) && blend->need_src_alpha & (1 << 0)) {
534 /* When a subpass doesn't have any color attachments, write the
535 * alpha channel of MRT0 when alpha coverage is enabled because
536 * the depth attachment needs it.
537 */
538 col_format |= V_028714_SPI_SHADER_32_AR;
539 }
540
541 /* If the i-th target format is set, all previous target formats must
542 * be non-zero to avoid hangs.
543 */
544 num_targets = (util_last_bit(col_format) + 3) / 4;
545 for (unsigned i = 0; i < num_targets; i++) {
546 if (!(col_format & (0xf << (i * 4)))) {
547 col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
548 }
549 }
550
551 /* The output for dual source blending should have the same format as
552 * the first output.
553 */
554 if (blend->mrt0_is_dual_src)
555 col_format |= (col_format & 0xf) << 4;
556
557 blend->spi_shader_col_format = col_format;
558 blend->col_format_is_int8 = is_int8;
559 blend->col_format_is_int10 = is_int10;
560 }
561
562 /*
563 * Ordered so that for each i,
564 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
565 */
566 const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = {
567 VK_FORMAT_R32_SFLOAT,
568 VK_FORMAT_R32G32_SFLOAT,
569 VK_FORMAT_R8G8B8A8_UNORM,
570 VK_FORMAT_R16G16B16A16_UNORM,
571 VK_FORMAT_R16G16B16A16_SNORM,
572 VK_FORMAT_R16G16B16A16_UINT,
573 VK_FORMAT_R16G16B16A16_SINT,
574 VK_FORMAT_R32G32B32A32_SFLOAT,
575 VK_FORMAT_R8G8B8A8_UINT,
576 VK_FORMAT_R8G8B8A8_SINT,
577 VK_FORMAT_A2R10G10B10_UINT_PACK32,
578 VK_FORMAT_A2R10G10B10_SINT_PACK32,
579 };
580
581 unsigned radv_format_meta_fs_key(VkFormat format)
582 {
583 unsigned col_format = radv_choose_spi_color_format(format, false, false);
584
585 assert(col_format != V_028714_SPI_SHADER_32_AR);
586 if (col_format >= V_028714_SPI_SHADER_32_AR)
587 --col_format; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
588
589 --col_format; /* Skip V_028714_SPI_SHADER_ZERO */
590 bool is_int8 = format_is_int8(format);
591 bool is_int10 = format_is_int10(format);
592
593 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
594 }
595
596 static void
597 radv_blend_check_commutativity(struct radv_blend_state *blend,
598 VkBlendOp op, VkBlendFactor src,
599 VkBlendFactor dst, unsigned chanmask)
600 {
601 /* Src factor is allowed when it does not depend on Dst. */
602 static const uint32_t src_allowed =
603 (1u << VK_BLEND_FACTOR_ONE) |
604 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
605 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
606 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
607 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
608 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
609 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
610 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
611 (1u << VK_BLEND_FACTOR_ZERO) |
612 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
613 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
614 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
615 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
616 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
617 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
618
619 if (dst == VK_BLEND_FACTOR_ONE &&
620 (src_allowed & (1u << src))) {
621 /* Addition is commutative, but floating point addition isn't
622 * associative: subtle changes can be introduced via different
623 * rounding. Be conservative, only enable for min and max.
624 */
625 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
626 blend->commutative_4bit |= chanmask;
627 }
628 }
629
630 static struct radv_blend_state
631 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
632 const VkGraphicsPipelineCreateInfo *pCreateInfo,
633 const struct radv_graphics_pipeline_create_info *extra)
634 {
635 const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
636 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
637 struct radv_blend_state blend = {0};
638 unsigned mode = V_028808_CB_NORMAL;
639 int i;
640
641 if (extra && extra->custom_blend_mode) {
642 blend.single_cb_enable = true;
643 mode = extra->custom_blend_mode;
644 }
645
646 blend.cb_color_control = 0;
647 if (vkblend) {
648 if (vkblend->logicOpEnable)
649 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
650 else
651 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
652 }
653
654 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
655 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
656 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
657 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
658 S_028B70_OFFSET_ROUND(1);
659
660 if (vkms && vkms->alphaToCoverageEnable) {
661 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
662 blend.need_src_alpha |= 0x1;
663 }
664
665 blend.cb_target_mask = 0;
666 if (vkblend) {
667 for (i = 0; i < vkblend->attachmentCount; i++) {
668 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
669 unsigned blend_cntl = 0;
670 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
671 VkBlendOp eqRGB = att->colorBlendOp;
672 VkBlendFactor srcRGB = att->srcColorBlendFactor;
673 VkBlendFactor dstRGB = att->dstColorBlendFactor;
674 VkBlendOp eqA = att->alphaBlendOp;
675 VkBlendFactor srcA = att->srcAlphaBlendFactor;
676 VkBlendFactor dstA = att->dstAlphaBlendFactor;
677
678 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
679
680 if (!att->colorWriteMask)
681 continue;
682
683 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
684 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
685 if (!att->blendEnable) {
686 blend.cb_blend_control[i] = blend_cntl;
687 continue;
688 }
689
690 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
691 if (i == 0)
692 blend.mrt0_is_dual_src = true;
693
694 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
695 srcRGB = VK_BLEND_FACTOR_ONE;
696 dstRGB = VK_BLEND_FACTOR_ONE;
697 }
698 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
699 srcA = VK_BLEND_FACTOR_ONE;
700 dstA = VK_BLEND_FACTOR_ONE;
701 }
702
703 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
704 0x7 << (4 * i));
705 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
706 0x8 << (4 * i));
707
708 /* Blending optimizations for RB+.
709 * These transformations don't change the behavior.
710 *
711 * First, get rid of DST in the blend factors:
712 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
713 */
714 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
715 VK_BLEND_FACTOR_DST_COLOR,
716 VK_BLEND_FACTOR_SRC_COLOR);
717
718 si_blend_remove_dst(&eqA, &srcA, &dstA,
719 VK_BLEND_FACTOR_DST_COLOR,
720 VK_BLEND_FACTOR_SRC_COLOR);
721
722 si_blend_remove_dst(&eqA, &srcA, &dstA,
723 VK_BLEND_FACTOR_DST_ALPHA,
724 VK_BLEND_FACTOR_SRC_ALPHA);
725
726 /* Look up the ideal settings from tables. */
727 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
728 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
729 srcA_opt = si_translate_blend_opt_factor(srcA, true);
730 dstA_opt = si_translate_blend_opt_factor(dstA, true);
731
732 /* Handle interdependencies. */
733 if (si_blend_factor_uses_dst(srcRGB))
734 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
735 if (si_blend_factor_uses_dst(srcA))
736 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
737
738 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
739 (dstRGB == VK_BLEND_FACTOR_ZERO ||
740 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
741 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
742 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
743
744 /* Set the final value. */
745 blend.sx_mrt_blend_opt[i] =
746 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
747 S_028760_COLOR_DST_OPT(dstRGB_opt) |
748 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
749 S_028760_ALPHA_SRC_OPT(srcA_opt) |
750 S_028760_ALPHA_DST_OPT(dstA_opt) |
751 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
752 blend_cntl |= S_028780_ENABLE(1);
753
754 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
755 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
756 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
757 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
758 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
759 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
760 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
761 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
762 }
763 blend.cb_blend_control[i] = blend_cntl;
764
765 blend.blend_enable_4bit |= 0xfu << (i * 4);
766
767 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
768 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
769 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
770 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
771 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
772 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
773 blend.need_src_alpha |= 1 << i;
774 }
775 for (i = vkblend->attachmentCount; i < 8; i++) {
776 blend.cb_blend_control[i] = 0;
777 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
778 }
779 }
780
781 if (pipeline->device->physical_device->rad_info.has_rbplus) {
782 /* Disable RB+ blend optimizations for dual source blending. */
783 if (blend.mrt0_is_dual_src) {
784 for (i = 0; i < 8; i++) {
785 blend.sx_mrt_blend_opt[i] =
786 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
787 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
788 }
789 }
790
791 /* RB+ doesn't work with dual source blending, logic op and
792 * RESOLVE.
793 */
794 if (blend.mrt0_is_dual_src ||
795 (vkblend && vkblend->logicOpEnable) ||
796 mode == V_028808_CB_RESOLVE)
797 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
798 }
799
800 if (blend.cb_target_mask)
801 blend.cb_color_control |= S_028808_MODE(mode);
802 else
803 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
804
805 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
806 return blend;
807 }
808
809 static uint32_t si_translate_fill(VkPolygonMode func)
810 {
811 switch(func) {
812 case VK_POLYGON_MODE_FILL:
813 return V_028814_X_DRAW_TRIANGLES;
814 case VK_POLYGON_MODE_LINE:
815 return V_028814_X_DRAW_LINES;
816 case VK_POLYGON_MODE_POINT:
817 return V_028814_X_DRAW_POINTS;
818 default:
819 assert(0);
820 return V_028814_X_DRAW_POINTS;
821 }
822 }
823
824 static uint8_t radv_pipeline_get_ps_iter_samples(const VkGraphicsPipelineCreateInfo *pCreateInfo)
825 {
826 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
827 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
828 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
829 uint32_t ps_iter_samples = 1;
830 uint32_t num_samples;
831
832 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
833 *
834 * "If the VK_AMD_mixed_attachment_samples extension is enabled and the
835 * subpass uses color attachments, totalSamples is the number of
836 * samples of the color attachments. Otherwise, totalSamples is the
837 * value of VkPipelineMultisampleStateCreateInfo::rasterizationSamples
838 * specified at pipeline creation time."
839 */
840 if (subpass->has_color_att) {
841 num_samples = subpass->color_sample_count;
842 } else {
843 num_samples = vkms->rasterizationSamples;
844 }
845
846 if (vkms->sampleShadingEnable) {
847 ps_iter_samples = ceilf(vkms->minSampleShading * num_samples);
848 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
849 }
850 return ps_iter_samples;
851 }
852
853 static bool
854 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
855 {
856 return pCreateInfo->depthTestEnable &&
857 pCreateInfo->depthWriteEnable &&
858 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
859 }
860
861 static bool
862 radv_writes_stencil(const VkStencilOpState *state)
863 {
864 return state->writeMask &&
865 (state->failOp != VK_STENCIL_OP_KEEP ||
866 state->passOp != VK_STENCIL_OP_KEEP ||
867 state->depthFailOp != VK_STENCIL_OP_KEEP);
868 }
869
870 static bool
871 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
872 {
873 return pCreateInfo->stencilTestEnable &&
874 (radv_writes_stencil(&pCreateInfo->front) ||
875 radv_writes_stencil(&pCreateInfo->back));
876 }
877
878 static bool
879 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
880 {
881 return radv_is_depth_write_enabled(pCreateInfo) ||
882 radv_is_stencil_write_enabled(pCreateInfo);
883 }
884
885 static bool
886 radv_order_invariant_stencil_op(VkStencilOp op)
887 {
888 /* REPLACE is normally order invariant, except when the stencil
889 * reference value is written by the fragment shader. Tracking this
890 * interaction does not seem worth the effort, so be conservative.
891 */
892 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
893 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
894 op != VK_STENCIL_OP_REPLACE;
895 }
896
897 static bool
898 radv_order_invariant_stencil_state(const VkStencilOpState *state)
899 {
900 /* Compute whether, assuming Z writes are disabled, this stencil state
901 * is order invariant in the sense that the set of passing fragments as
902 * well as the final stencil buffer result does not depend on the order
903 * of fragments.
904 */
905 return !state->writeMask ||
906 /* The following assumes that Z writes are disabled. */
907 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
908 radv_order_invariant_stencil_op(state->passOp) &&
909 radv_order_invariant_stencil_op(state->depthFailOp)) ||
910 (state->compareOp == VK_COMPARE_OP_NEVER &&
911 radv_order_invariant_stencil_op(state->failOp));
912 }
913
914 static bool
915 radv_pipeline_has_dynamic_ds_states(const VkGraphicsPipelineCreateInfo *pCreateInfo)
916 {
917 VkDynamicState ds_states[] = {
918 VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT,
919 VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT,
920 VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT,
921 VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT,
922 VK_DYNAMIC_STATE_STENCIL_OP_EXT,
923 };
924
925 if (pCreateInfo->pDynamicState) {
926 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
927 for (uint32_t i = 0; i < count; i++) {
928 for (uint32_t j = 0; j < ARRAY_SIZE(ds_states); j++) {
929 if (pCreateInfo->pDynamicState->pDynamicStates[i] == ds_states[j])
930 return true;
931 }
932 }
933 }
934
935 return false;
936 }
937
938 static bool
939 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
940 struct radv_blend_state *blend,
941 const VkGraphicsPipelineCreateInfo *pCreateInfo)
942 {
943 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
944 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
945 const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
946 const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
947 unsigned colormask = blend->cb_target_enabled_4bit;
948
949 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
950 return false;
951
952 /* Be conservative if a logic operation is enabled with color buffers. */
953 if (colormask && vkblend && vkblend->logicOpEnable)
954 return false;
955
956 /* Be conservative if an extended dynamic depth/stencil state is
957 * enabled because the driver can't update out-of-order rasterization
958 * dynamically.
959 */
960 if (radv_pipeline_has_dynamic_ds_states(pCreateInfo))
961 return false;
962
963 /* Default depth/stencil invariance when no attachment is bound. */
964 struct radv_dsa_order_invariance dsa_order_invariant = {
965 .zs = true, .pass_set = true
966 };
967
968 if (vkds) {
969 struct radv_render_pass_attachment *attachment =
970 pass->attachments + subpass->depth_stencil_attachment->attachment;
971 bool has_stencil = vk_format_is_stencil(attachment->format);
972 struct radv_dsa_order_invariance order_invariance[2];
973 struct radv_shader_variant *ps =
974 pipeline->shaders[MESA_SHADER_FRAGMENT];
975
976 /* Compute depth/stencil order invariance in order to know if
977 * it's safe to enable out-of-order.
978 */
979 bool zfunc_is_ordered =
980 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
981 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
982 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
983 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
984 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
985
986 bool nozwrite_and_order_invariant_stencil =
987 !radv_is_ds_write_enabled(vkds) ||
988 (!radv_is_depth_write_enabled(vkds) &&
989 radv_order_invariant_stencil_state(&vkds->front) &&
990 radv_order_invariant_stencil_state(&vkds->back));
991
992 order_invariance[1].zs =
993 nozwrite_and_order_invariant_stencil ||
994 (!radv_is_stencil_write_enabled(vkds) &&
995 zfunc_is_ordered);
996 order_invariance[0].zs =
997 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
998
999 order_invariance[1].pass_set =
1000 nozwrite_and_order_invariant_stencil ||
1001 (!radv_is_stencil_write_enabled(vkds) &&
1002 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1003 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
1004 order_invariance[0].pass_set =
1005 !radv_is_depth_write_enabled(vkds) ||
1006 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1007 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
1008
1009 dsa_order_invariant = order_invariance[has_stencil];
1010 if (!dsa_order_invariant.zs)
1011 return false;
1012
1013 /* The set of PS invocations is always order invariant,
1014 * except when early Z/S tests are requested.
1015 */
1016 if (ps &&
1017 ps->info.ps.writes_memory &&
1018 ps->info.ps.early_fragment_test &&
1019 !dsa_order_invariant.pass_set)
1020 return false;
1021
1022 /* Determine if out-of-order rasterization should be disabled
1023 * when occlusion queries are used.
1024 */
1025 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
1026 !dsa_order_invariant.pass_set;
1027 }
1028
1029 /* No color buffers are enabled for writing. */
1030 if (!colormask)
1031 return true;
1032
1033 unsigned blendmask = colormask & blend->blend_enable_4bit;
1034
1035 if (blendmask) {
1036 /* Only commutative blending. */
1037 if (blendmask & ~blend->commutative_4bit)
1038 return false;
1039
1040 if (!dsa_order_invariant.pass_set)
1041 return false;
1042 }
1043
1044 if (colormask & ~blendmask)
1045 return false;
1046
1047 return true;
1048 }
1049
1050 static const VkConservativeRasterizationModeEXT
1051 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo)
1052 {
1053 const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster =
1054 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT);
1055
1056 if (!conservative_raster)
1057 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT;
1058 return conservative_raster->conservativeRasterizationMode;
1059 }
1060
1061 static void
1062 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1063 struct radv_blend_state *blend,
1064 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1065 {
1066 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
1067 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1068 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1069 const VkConservativeRasterizationModeEXT mode =
1070 radv_get_conservative_raster_mode(pCreateInfo->pRasterizationState);
1071 bool out_of_order_rast = false;
1072 int ps_iter_samples = 1;
1073 uint32_t mask = 0xffff;
1074
1075 if (vkms) {
1076 ms->num_samples = vkms->rasterizationSamples;
1077
1078 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1079 *
1080 * "Sample shading is enabled for a graphics pipeline:
1081 *
1082 * - If the interface of the fragment shader entry point of the
1083 * graphics pipeline includes an input variable decorated
1084 * with SampleId or SamplePosition. In this case
1085 * minSampleShadingFactor takes the value 1.0.
1086 * - Else if the sampleShadingEnable member of the
1087 * VkPipelineMultisampleStateCreateInfo structure specified
1088 * when creating the graphics pipeline is set to VK_TRUE. In
1089 * this case minSampleShadingFactor takes the value of
1090 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1091 *
1092 * Otherwise, sample shading is considered disabled."
1093 */
1094 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.force_persample) {
1095 ps_iter_samples = ms->num_samples;
1096 } else {
1097 ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
1098 }
1099 } else {
1100 ms->num_samples = 1;
1101 }
1102
1103 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1104 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1105 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1106 /* Out-of-order rasterization is explicitly enabled by the
1107 * application.
1108 */
1109 out_of_order_rast = true;
1110 } else {
1111 /* Determine if the driver can enable out-of-order
1112 * rasterization internally.
1113 */
1114 out_of_order_rast =
1115 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1116 }
1117
1118 ms->pa_sc_aa_config = 0;
1119 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1120 S_028804_INCOHERENT_EQAA_READS(1) |
1121 S_028804_INTERPOLATE_COMP_Z(1) |
1122 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1123
1124 /* Adjust MSAA state if conservative rasterization is enabled. */
1125 if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
1126 ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1);
1127
1128 ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
1129 S_028804_OVERRASTERIZATION_AMOUNT(4);
1130 }
1131
1132 ms->pa_sc_mode_cntl_1 =
1133 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1134 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1135 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
1136 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1137 /* always 1: */
1138 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1139 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1140 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1141 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1142 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1143 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1144 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1145 S_028A48_VPORT_SCISSOR_ENABLE(1);
1146
1147 const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line =
1148 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1149 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
1150 if (rast_line) {
1151 ms->pa_sc_mode_cntl_0 |= S_028A48_LINE_STIPPLE_ENABLE(rast_line->stippledLineEnable);
1152 if (rast_line->lineRasterizationMode == VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT) {
1153 /* From the Vulkan spec 1.1.129:
1154 *
1155 * "When VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT lines
1156 * are being rasterized, sample locations may all be
1157 * treated as being at the pixel center (this may
1158 * affect attribute and depth interpolation)."
1159 */
1160 ms->num_samples = 1;
1161 }
1162 }
1163
1164 if (ms->num_samples > 1) {
1165 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1166 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1167 uint32_t z_samples = subpass->depth_stencil_attachment ? subpass->depth_sample_count : ms->num_samples;
1168 unsigned log_samples = util_logbase2(ms->num_samples);
1169 unsigned log_z_samples = util_logbase2(z_samples);
1170 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1171 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1172 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
1173 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1174 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1175 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1176 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1177 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) |
1178 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples) | /* CM_R_028BE0_PA_SC_AA_CONFIG */
1179 S_028BE0_COVERED_CENTROID_IS_CENTER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3);
1180 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1181 if (ps_iter_samples > 1)
1182 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1183 }
1184
1185 if (vkms && vkms->pSampleMask) {
1186 mask = vkms->pSampleMask[0] & 0xffff;
1187 }
1188
1189 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1190 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1191 }
1192
1193 static bool
1194 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1195 {
1196 switch (topology) {
1197 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1198 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1199 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1200 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1201 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1202 return false;
1203 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1204 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1205 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1206 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1207 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1208 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1209 return true;
1210 default:
1211 unreachable("unhandled primitive type");
1212 }
1213 }
1214
1215 static uint32_t
1216 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1217 {
1218 switch (gl_prim) {
1219 case 0: /* GL_POINTS */
1220 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1221 case 1: /* GL_LINES */
1222 case 3: /* GL_LINE_STRIP */
1223 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1224 case 0x8E7A: /* GL_ISOLINES */
1225 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1226
1227 case 4: /* GL_TRIANGLES */
1228 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1229 case 5: /* GL_TRIANGLE_STRIP */
1230 case 7: /* GL_QUADS */
1231 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1232 default:
1233 assert(0);
1234 return 0;
1235 }
1236 }
1237
1238 static uint32_t
1239 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1240 {
1241 switch (topology) {
1242 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1243 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1244 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1245 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1246 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1247 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1248 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1249 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1250 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1251 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1252 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1253 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1254 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1255 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1256 default:
1257 assert(0);
1258 return 0;
1259 }
1260 }
1261
1262 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1263 {
1264 switch(state) {
1265 case VK_DYNAMIC_STATE_VIEWPORT:
1266 case VK_DYNAMIC_STATE_VIEWPORT_WITH_COUNT_EXT:
1267 return RADV_DYNAMIC_VIEWPORT;
1268 case VK_DYNAMIC_STATE_SCISSOR:
1269 case VK_DYNAMIC_STATE_SCISSOR_WITH_COUNT_EXT:
1270 return RADV_DYNAMIC_SCISSOR;
1271 case VK_DYNAMIC_STATE_LINE_WIDTH:
1272 return RADV_DYNAMIC_LINE_WIDTH;
1273 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1274 return RADV_DYNAMIC_DEPTH_BIAS;
1275 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1276 return RADV_DYNAMIC_BLEND_CONSTANTS;
1277 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1278 return RADV_DYNAMIC_DEPTH_BOUNDS;
1279 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1280 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1281 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1282 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1283 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1284 return RADV_DYNAMIC_STENCIL_REFERENCE;
1285 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1286 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1287 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
1288 return RADV_DYNAMIC_SAMPLE_LOCATIONS;
1289 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT:
1290 return RADV_DYNAMIC_LINE_STIPPLE;
1291 case VK_DYNAMIC_STATE_CULL_MODE_EXT:
1292 return RADV_DYNAMIC_CULL_MODE;
1293 case VK_DYNAMIC_STATE_FRONT_FACE_EXT:
1294 return RADV_DYNAMIC_FRONT_FACE;
1295 case VK_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY_EXT:
1296 return RADV_DYNAMIC_PRIMITIVE_TOPOLOGY;
1297 case VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT:
1298 return RADV_DYNAMIC_DEPTH_TEST_ENABLE;
1299 case VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT:
1300 return RADV_DYNAMIC_DEPTH_WRITE_ENABLE;
1301 case VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT:
1302 return RADV_DYNAMIC_DEPTH_COMPARE_OP;
1303 case VK_DYNAMIC_STATE_DEPTH_BOUNDS_TEST_ENABLE_EXT:
1304 return RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE;
1305 case VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT:
1306 return RADV_DYNAMIC_STENCIL_TEST_ENABLE;
1307 case VK_DYNAMIC_STATE_STENCIL_OP_EXT:
1308 return RADV_DYNAMIC_STENCIL_OP;
1309 case VK_DYNAMIC_STATE_VERTEX_INPUT_BINDING_STRIDE_EXT:
1310 return RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE;
1311 default:
1312 unreachable("Unhandled dynamic state");
1313 }
1314 }
1315
1316 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1317 {
1318 uint32_t states = RADV_DYNAMIC_ALL;
1319
1320 /* If rasterization is disabled we do not care about any of the
1321 * dynamic states, since they are all rasterization related only,
1322 * except primitive topology and vertex binding stride.
1323 */
1324 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1325 return RADV_DYNAMIC_PRIMITIVE_TOPOLOGY |
1326 RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE;
1327
1328 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1329 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1330
1331 if (!pCreateInfo->pDepthStencilState ||
1332 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1333 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1334
1335 if (!pCreateInfo->pDepthStencilState ||
1336 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1337 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1338 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1339 RADV_DYNAMIC_STENCIL_REFERENCE);
1340
1341 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1342 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1343
1344 if (!pCreateInfo->pMultisampleState ||
1345 !vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1346 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT))
1347 states &= ~RADV_DYNAMIC_SAMPLE_LOCATIONS;
1348
1349 if (!pCreateInfo->pRasterizationState ||
1350 !vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1351 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT))
1352 states &= ~RADV_DYNAMIC_LINE_STIPPLE;
1353
1354 /* TODO: blend constants & line width. */
1355
1356 return states;
1357 }
1358
1359 static struct radv_ia_multi_vgt_param_helpers
1360 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline)
1361 {
1362 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
1363 const struct radv_device *device = pipeline->device;
1364
1365 if (radv_pipeline_has_tess(pipeline))
1366 ia_multi_vgt_param.primgroup_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1367 else if (radv_pipeline_has_gs(pipeline))
1368 ia_multi_vgt_param.primgroup_size = 64;
1369 else
1370 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
1371
1372 /* GS requirement. */
1373 ia_multi_vgt_param.partial_es_wave = false;
1374 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= GFX8)
1375 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
1376 ia_multi_vgt_param.partial_es_wave = true;
1377
1378 ia_multi_vgt_param.ia_switch_on_eoi = false;
1379 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input)
1380 ia_multi_vgt_param.ia_switch_on_eoi = true;
1381 if (radv_pipeline_has_gs(pipeline) &&
1382 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.uses_prim_id)
1383 ia_multi_vgt_param.ia_switch_on_eoi = true;
1384 if (radv_pipeline_has_tess(pipeline)) {
1385 /* SWITCH_ON_EOI must be set if PrimID is used. */
1386 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
1387 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
1388 ia_multi_vgt_param.ia_switch_on_eoi = true;
1389 }
1390
1391 ia_multi_vgt_param.partial_vs_wave = false;
1392 if (radv_pipeline_has_tess(pipeline)) {
1393 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
1394 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
1395 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
1396 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
1397 radv_pipeline_has_gs(pipeline))
1398 ia_multi_vgt_param.partial_vs_wave = true;
1399 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
1400 if (device->physical_device->rad_info.has_distributed_tess) {
1401 if (radv_pipeline_has_gs(pipeline)) {
1402 if (device->physical_device->rad_info.chip_class <= GFX8)
1403 ia_multi_vgt_param.partial_es_wave = true;
1404 } else {
1405 ia_multi_vgt_param.partial_vs_wave = true;
1406 }
1407 }
1408 }
1409
1410 if (radv_pipeline_has_gs(pipeline)) {
1411 /* On these chips there is the possibility of a hang if the
1412 * pipeline uses a GS and partial_vs_wave is not set.
1413 *
1414 * This mostly does not hit 4-SE chips, as those typically set
1415 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
1416 * with GS due to another workaround.
1417 *
1418 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
1419 */
1420 if (device->physical_device->rad_info.family == CHIP_TONGA ||
1421 device->physical_device->rad_info.family == CHIP_FIJI ||
1422 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
1423 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
1424 device->physical_device->rad_info.family == CHIP_POLARIS12 ||
1425 device->physical_device->rad_info.family == CHIP_VEGAM) {
1426 ia_multi_vgt_param.partial_vs_wave = true;
1427 }
1428 }
1429
1430 ia_multi_vgt_param.base =
1431 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
1432 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
1433 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == GFX8 ? 2 : 0) |
1434 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
1435 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
1436
1437 return ia_multi_vgt_param;
1438 }
1439
1440 static void
1441 radv_pipeline_init_input_assembly_state(struct radv_pipeline *pipeline,
1442 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1443 const struct radv_graphics_pipeline_create_info *extra)
1444 {
1445 const VkPipelineInputAssemblyStateCreateInfo *ia_state = pCreateInfo->pInputAssemblyState;
1446 struct radv_shader_variant *tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
1447 struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
1448
1449 pipeline->graphics.prim_restart_enable = !!ia_state->primitiveRestartEnable;
1450 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(ia_state->topology);
1451
1452 if (radv_pipeline_has_gs(pipeline)) {
1453 if (si_conv_gl_prim_to_gs_out(gs->info.gs.output_prim) == V_028A6C_OUTPRIM_TYPE_TRISTRIP)
1454 pipeline->graphics.can_use_guardband = true;
1455 } else if (radv_pipeline_has_tess(pipeline)) {
1456 if (!tes->info.tes.point_mode &&
1457 si_conv_gl_prim_to_gs_out(tes->info.tes.primitive_mode) == V_028A6C_OUTPRIM_TYPE_TRISTRIP)
1458 pipeline->graphics.can_use_guardband = true;
1459 }
1460
1461 if (extra && extra->use_rectlist) {
1462 pipeline->graphics.can_use_guardband = true;
1463 }
1464
1465 pipeline->graphics.ia_multi_vgt_param =
1466 radv_compute_ia_multi_vgt_param_helpers(pipeline);
1467 }
1468
1469 static void
1470 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1471 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1472 const struct radv_graphics_pipeline_create_info *extra)
1473 {
1474 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1475 uint32_t states = needed_states;
1476 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1477 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1478
1479 pipeline->dynamic_state = default_dynamic_state;
1480 pipeline->graphics.needed_dynamic_state = needed_states;
1481
1482 if (pCreateInfo->pDynamicState) {
1483 /* Remove all of the states that are marked as dynamic */
1484 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1485 for (uint32_t s = 0; s < count; s++)
1486 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1487 }
1488
1489 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1490
1491 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1492 assert(pCreateInfo->pViewportState);
1493
1494 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1495 if (states & RADV_DYNAMIC_VIEWPORT) {
1496 typed_memcpy(dynamic->viewport.viewports,
1497 pCreateInfo->pViewportState->pViewports,
1498 pCreateInfo->pViewportState->viewportCount);
1499 }
1500 }
1501
1502 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1503 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1504 if (states & RADV_DYNAMIC_SCISSOR) {
1505 typed_memcpy(dynamic->scissor.scissors,
1506 pCreateInfo->pViewportState->pScissors,
1507 pCreateInfo->pViewportState->scissorCount);
1508 }
1509 }
1510
1511 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1512 assert(pCreateInfo->pRasterizationState);
1513 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1514 }
1515
1516 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1517 assert(pCreateInfo->pRasterizationState);
1518 dynamic->depth_bias.bias =
1519 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1520 dynamic->depth_bias.clamp =
1521 pCreateInfo->pRasterizationState->depthBiasClamp;
1522 dynamic->depth_bias.slope =
1523 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1524 }
1525
1526 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1527 *
1528 * pColorBlendState is [...] NULL if the pipeline has rasterization
1529 * disabled or if the subpass of the render pass the pipeline is
1530 * created against does not use any color attachments.
1531 */
1532 if (subpass->has_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1533 assert(pCreateInfo->pColorBlendState);
1534 typed_memcpy(dynamic->blend_constants,
1535 pCreateInfo->pColorBlendState->blendConstants, 4);
1536 }
1537
1538 if (states & RADV_DYNAMIC_CULL_MODE) {
1539 dynamic->cull_mode =
1540 pCreateInfo->pRasterizationState->cullMode;
1541 }
1542
1543 if (states & RADV_DYNAMIC_FRONT_FACE) {
1544 dynamic->front_face =
1545 pCreateInfo->pRasterizationState->frontFace;
1546 }
1547
1548 if (states & RADV_DYNAMIC_PRIMITIVE_TOPOLOGY) {
1549 dynamic->primitive_topology =
1550 si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
1551 if (extra && extra->use_rectlist) {
1552 dynamic->primitive_topology = V_008958_DI_PT_RECTLIST;
1553 }
1554 }
1555
1556 /* If there is no depthstencil attachment, then don't read
1557 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1558 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1559 * no need to override the depthstencil defaults in
1560 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1561 *
1562 * Section 9.2 of the Vulkan 1.0.15 spec says:
1563 *
1564 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1565 * disabled or if the subpass of the render pass the pipeline is created
1566 * against does not use a depth/stencil attachment.
1567 */
1568 if (needed_states && subpass->depth_stencil_attachment) {
1569 assert(pCreateInfo->pDepthStencilState);
1570
1571 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1572 dynamic->depth_bounds.min =
1573 pCreateInfo->pDepthStencilState->minDepthBounds;
1574 dynamic->depth_bounds.max =
1575 pCreateInfo->pDepthStencilState->maxDepthBounds;
1576 }
1577
1578 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1579 dynamic->stencil_compare_mask.front =
1580 pCreateInfo->pDepthStencilState->front.compareMask;
1581 dynamic->stencil_compare_mask.back =
1582 pCreateInfo->pDepthStencilState->back.compareMask;
1583 }
1584
1585 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1586 dynamic->stencil_write_mask.front =
1587 pCreateInfo->pDepthStencilState->front.writeMask;
1588 dynamic->stencil_write_mask.back =
1589 pCreateInfo->pDepthStencilState->back.writeMask;
1590 }
1591
1592 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1593 dynamic->stencil_reference.front =
1594 pCreateInfo->pDepthStencilState->front.reference;
1595 dynamic->stencil_reference.back =
1596 pCreateInfo->pDepthStencilState->back.reference;
1597 }
1598
1599 if (states & RADV_DYNAMIC_DEPTH_TEST_ENABLE) {
1600 dynamic->depth_test_enable =
1601 pCreateInfo->pDepthStencilState->depthTestEnable;
1602 }
1603
1604 if (states & RADV_DYNAMIC_DEPTH_WRITE_ENABLE) {
1605 dynamic->depth_write_enable =
1606 pCreateInfo->pDepthStencilState->depthWriteEnable;
1607 }
1608
1609 if (states & RADV_DYNAMIC_DEPTH_COMPARE_OP) {
1610 dynamic->depth_compare_op =
1611 pCreateInfo->pDepthStencilState->depthCompareOp;
1612 }
1613
1614 if (states & RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE) {
1615 dynamic->depth_bounds_test_enable =
1616 pCreateInfo->pDepthStencilState->depthBoundsTestEnable;
1617 }
1618
1619 if (states & RADV_DYNAMIC_STENCIL_TEST_ENABLE) {
1620 dynamic->stencil_test_enable =
1621 pCreateInfo->pDepthStencilState->stencilTestEnable;
1622 }
1623
1624 if (states & RADV_DYNAMIC_STENCIL_OP) {
1625 dynamic->stencil_op.front.compare_op =
1626 pCreateInfo->pDepthStencilState->front.compareOp;
1627 dynamic->stencil_op.front.fail_op =
1628 pCreateInfo->pDepthStencilState->front.failOp;
1629 dynamic->stencil_op.front.pass_op =
1630 pCreateInfo->pDepthStencilState->front.passOp;
1631 dynamic->stencil_op.front.depth_fail_op =
1632 pCreateInfo->pDepthStencilState->front.depthFailOp;
1633
1634 dynamic->stencil_op.back.compare_op =
1635 pCreateInfo->pDepthStencilState->back.compareOp;
1636 dynamic->stencil_op.back.fail_op =
1637 pCreateInfo->pDepthStencilState->back.failOp;
1638 dynamic->stencil_op.back.pass_op =
1639 pCreateInfo->pDepthStencilState->back.passOp;
1640 dynamic->stencil_op.back.depth_fail_op =
1641 pCreateInfo->pDepthStencilState->back.depthFailOp;
1642 }
1643 }
1644
1645 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1646 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1647 if (needed_states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1648 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1649 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1650 typed_memcpy(dynamic->discard_rectangle.rectangles,
1651 discard_rectangle_info->pDiscardRectangles,
1652 discard_rectangle_info->discardRectangleCount);
1653 }
1654 }
1655
1656 if (needed_states & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
1657 const VkPipelineSampleLocationsStateCreateInfoEXT *sample_location_info =
1658 vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1659 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1660 /* If sampleLocationsEnable is VK_FALSE, the default sample
1661 * locations are used and the values specified in
1662 * sampleLocationsInfo are ignored.
1663 */
1664 if (sample_location_info->sampleLocationsEnable) {
1665 const VkSampleLocationsInfoEXT *pSampleLocationsInfo =
1666 &sample_location_info->sampleLocationsInfo;
1667
1668 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
1669
1670 dynamic->sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
1671 dynamic->sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
1672 dynamic->sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
1673 typed_memcpy(&dynamic->sample_location.locations[0],
1674 pSampleLocationsInfo->pSampleLocations,
1675 pSampleLocationsInfo->sampleLocationsCount);
1676 }
1677 }
1678
1679 const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line_info =
1680 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1681 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
1682 if (needed_states & RADV_DYNAMIC_LINE_STIPPLE) {
1683 dynamic->line_stipple.factor = rast_line_info->lineStippleFactor;
1684 dynamic->line_stipple.pattern = rast_line_info->lineStipplePattern;
1685 }
1686
1687 if (!(states & RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE))
1688 pipeline->graphics.uses_dynamic_stride = true;
1689
1690 pipeline->dynamic_state.mask = states;
1691 }
1692
1693 static void
1694 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
1695 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1696 {
1697 const VkPipelineRasterizationStateCreateInfo *raster_info =
1698 pCreateInfo->pRasterizationState;
1699
1700 pipeline->graphics.pa_su_sc_mode_cntl =
1701 S_028814_FACE(raster_info->frontFace) |
1702 S_028814_CULL_FRONT(!!(raster_info->cullMode & VK_CULL_MODE_FRONT_BIT)) |
1703 S_028814_CULL_BACK(!!(raster_info->cullMode & VK_CULL_MODE_BACK_BIT)) |
1704 S_028814_POLY_MODE(raster_info->polygonMode != VK_POLYGON_MODE_FILL) |
1705 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(raster_info->polygonMode)) |
1706 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(raster_info->polygonMode)) |
1707 S_028814_POLY_OFFSET_FRONT_ENABLE(raster_info->depthBiasEnable ? 1 : 0) |
1708 S_028814_POLY_OFFSET_BACK_ENABLE(raster_info->depthBiasEnable ? 1 : 0) |
1709 S_028814_POLY_OFFSET_PARA_ENABLE(raster_info->depthBiasEnable ? 1 : 0);
1710 }
1711
1712 static void
1713 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
1714 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1715 {
1716 const VkPipelineDepthStencilStateCreateInfo *ds_info
1717 = radv_pipeline_get_depth_stencil_state(pCreateInfo);
1718 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1719 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1720 struct radv_render_pass_attachment *attachment = NULL;
1721 uint32_t db_depth_control = 0;
1722
1723 if (subpass->depth_stencil_attachment)
1724 attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
1725
1726 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
1727 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
1728
1729 if (ds_info) {
1730 if (has_depth_attachment) {
1731 db_depth_control = S_028800_Z_ENABLE(ds_info->depthTestEnable ? 1 : 0) |
1732 S_028800_Z_WRITE_ENABLE(ds_info->depthWriteEnable ? 1 : 0) |
1733 S_028800_ZFUNC(ds_info->depthCompareOp) |
1734 S_028800_DEPTH_BOUNDS_ENABLE(ds_info->depthBoundsTestEnable ? 1 : 0);
1735 }
1736
1737 if (has_stencil_attachment && ds_info->stencilTestEnable) {
1738 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
1739 db_depth_control |= S_028800_STENCILFUNC(ds_info->front.compareOp);
1740 db_depth_control |= S_028800_STENCILFUNC_BF(ds_info->back.compareOp);
1741 }
1742 }
1743
1744 pipeline->graphics.db_depth_control = db_depth_control;
1745 }
1746
1747 static void
1748 gfx9_get_gs_info(const struct radv_pipeline_key *key,
1749 const struct radv_pipeline *pipeline,
1750 nir_shader **nir,
1751 struct radv_shader_info *infos,
1752 struct gfx9_gs_info *out)
1753 {
1754 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1755 struct radv_es_output_info *es_info;
1756 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1757 es_info = nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1758 else
1759 es_info = nir[MESA_SHADER_TESS_CTRL] ?
1760 &infos[MESA_SHADER_TESS_EVAL].tes.es_info :
1761 &infos[MESA_SHADER_VERTEX].vs.es_info;
1762
1763 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1764 bool uses_adjacency;
1765 switch(key->topology) {
1766 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1767 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1768 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1769 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1770 uses_adjacency = true;
1771 break;
1772 default:
1773 uses_adjacency = false;
1774 break;
1775 }
1776
1777 /* All these are in dwords: */
1778 /* We can't allow using the whole LDS, because GS waves compete with
1779 * other shader stages for LDS space. */
1780 const unsigned max_lds_size = 8 * 1024;
1781 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1782 unsigned esgs_lds_size;
1783
1784 /* All these are per subgroup: */
1785 const unsigned max_out_prims = 32 * 1024;
1786 const unsigned max_es_verts = 255;
1787 const unsigned ideal_gs_prims = 64;
1788 unsigned max_gs_prims, gs_prims;
1789 unsigned min_es_verts, es_verts, worst_case_es_verts;
1790
1791 if (uses_adjacency || gs_num_invocations > 1)
1792 max_gs_prims = 127 / gs_num_invocations;
1793 else
1794 max_gs_prims = 255;
1795
1796 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1797 * Make sure we don't go over the maximum value.
1798 */
1799 if (gs_info->gs.vertices_out > 0) {
1800 max_gs_prims = MIN2(max_gs_prims,
1801 max_out_prims /
1802 (gs_info->gs.vertices_out * gs_num_invocations));
1803 }
1804 assert(max_gs_prims > 0);
1805
1806 /* If the primitive has adjacency, halve the number of vertices
1807 * that will be reused in multiple primitives.
1808 */
1809 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1810
1811 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1812 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1813
1814 /* Compute ESGS LDS size based on the worst case number of ES vertices
1815 * needed to create the target number of GS prims per subgroup.
1816 */
1817 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1818
1819 /* If total LDS usage is too big, refactor partitions based on ratio
1820 * of ESGS item sizes.
1821 */
1822 if (esgs_lds_size > max_lds_size) {
1823 /* Our target GS Prims Per Subgroup was too large. Calculate
1824 * the maximum number of GS Prims Per Subgroup that will fit
1825 * into LDS, capped by the maximum that the hardware can support.
1826 */
1827 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1828 max_gs_prims);
1829 assert(gs_prims > 0);
1830 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1831 max_es_verts);
1832
1833 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1834 assert(esgs_lds_size <= max_lds_size);
1835 }
1836
1837 /* Now calculate remaining ESGS information. */
1838 if (esgs_lds_size)
1839 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1840 else
1841 es_verts = max_es_verts;
1842
1843 /* Vertices for adjacency primitives are not always reused, so restore
1844 * it for ES_VERTS_PER_SUBGRP.
1845 */
1846 min_es_verts = gs_info->gs.vertices_in;
1847
1848 /* For normal primitives, the VGT only checks if they are past the ES
1849 * verts per subgroup after allocating a full GS primitive and if they
1850 * are, kick off a new subgroup. But if those additional ES verts are
1851 * unique (e.g. not reused) we need to make sure there is enough LDS
1852 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1853 */
1854 es_verts -= min_es_verts - 1;
1855
1856 uint32_t es_verts_per_subgroup = es_verts;
1857 uint32_t gs_prims_per_subgroup = gs_prims;
1858 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1859 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1860 out->lds_size = align(esgs_lds_size, 128) / 128;
1861 out->vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1862 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1863 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1864 out->vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1865 out->vgt_esgs_ring_itemsize = esgs_itemsize;
1866 assert(max_prims_per_subgroup <= max_out_prims);
1867 }
1868
1869 static void clamp_gsprims_to_esverts(unsigned *max_gsprims, unsigned max_esverts,
1870 unsigned min_verts_per_prim, bool use_adjacency)
1871 {
1872 unsigned max_reuse = max_esverts - min_verts_per_prim;
1873 if (use_adjacency)
1874 max_reuse /= 2;
1875 *max_gsprims = MIN2(*max_gsprims, 1 + max_reuse);
1876 }
1877
1878 static unsigned
1879 radv_get_num_input_vertices(nir_shader **nir)
1880 {
1881 if (nir[MESA_SHADER_GEOMETRY]) {
1882 nir_shader *gs = nir[MESA_SHADER_GEOMETRY];
1883
1884 return gs->info.gs.vertices_in;
1885 }
1886
1887 if (nir[MESA_SHADER_TESS_CTRL]) {
1888 nir_shader *tes = nir[MESA_SHADER_TESS_EVAL];
1889
1890 if (tes->info.tess.point_mode)
1891 return 1;
1892 if (tes->info.tess.primitive_mode == GL_ISOLINES)
1893 return 2;
1894 return 3;
1895 }
1896
1897 return 3;
1898 }
1899
1900 static void
1901 gfx10_get_ngg_info(const struct radv_pipeline_key *key,
1902 struct radv_pipeline *pipeline,
1903 nir_shader **nir,
1904 struct radv_shader_info *infos,
1905 struct gfx10_ngg_info *ngg)
1906 {
1907 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1908 struct radv_es_output_info *es_info =
1909 nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1910 unsigned gs_type = nir[MESA_SHADER_GEOMETRY] ? MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX;
1911 unsigned max_verts_per_prim = radv_get_num_input_vertices(nir);
1912 unsigned min_verts_per_prim =
1913 gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1;
1914 unsigned gs_num_invocations = nir[MESA_SHADER_GEOMETRY] ? MAX2(gs_info->gs.invocations, 1) : 1;
1915 bool uses_adjacency;
1916 switch(key->topology) {
1917 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1918 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1919 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1920 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1921 uses_adjacency = true;
1922 break;
1923 default:
1924 uses_adjacency = false;
1925 break;
1926 }
1927
1928 /* All these are in dwords: */
1929 /* We can't allow using the whole LDS, because GS waves compete with
1930 * other shader stages for LDS space.
1931 *
1932 * TODO: We should really take the shader's internal LDS use into
1933 * account. The linker will fail if the size is greater than
1934 * 8K dwords.
1935 */
1936 const unsigned max_lds_size = 8 * 1024 - 768;
1937 const unsigned target_lds_size = max_lds_size;
1938 unsigned esvert_lds_size = 0;
1939 unsigned gsprim_lds_size = 0;
1940
1941 /* All these are per subgroup: */
1942 bool max_vert_out_per_gs_instance = false;
1943 unsigned max_esverts_base = 256;
1944 unsigned max_gsprims_base = 128; /* default prim group size clamp */
1945
1946 /* Hardware has the following non-natural restrictions on the value
1947 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1948 * the draw:
1949 * - at most 252 for any line input primitive type
1950 * - at most 251 for any quad input primitive type
1951 * - at most 251 for triangle strips with adjacency (this happens to
1952 * be the natural limit for triangle *lists* with adjacency)
1953 */
1954 max_esverts_base = MIN2(max_esverts_base, 251 + max_verts_per_prim - 1);
1955
1956 if (gs_type == MESA_SHADER_GEOMETRY) {
1957 unsigned max_out_verts_per_gsprim =
1958 gs_info->gs.vertices_out * gs_num_invocations;
1959
1960 if (max_out_verts_per_gsprim <= 256) {
1961 if (max_out_verts_per_gsprim) {
1962 max_gsprims_base = MIN2(max_gsprims_base,
1963 256 / max_out_verts_per_gsprim);
1964 }
1965 } else {
1966 /* Use special multi-cycling mode in which each GS
1967 * instance gets its own subgroup. Does not work with
1968 * tessellation. */
1969 max_vert_out_per_gs_instance = true;
1970 max_gsprims_base = 1;
1971 max_out_verts_per_gsprim = gs_info->gs.vertices_out;
1972 }
1973
1974 esvert_lds_size = es_info->esgs_itemsize / 4;
1975 gsprim_lds_size = (gs_info->gs.gsvs_vertex_size / 4 + 1) * max_out_verts_per_gsprim;
1976 } else {
1977 /* VS and TES. */
1978 /* LDS size for passing data from GS to ES. */
1979 struct radv_streamout_info *so_info = nir[MESA_SHADER_TESS_CTRL]
1980 ? &infos[MESA_SHADER_TESS_EVAL].so
1981 : &infos[MESA_SHADER_VERTEX].so;
1982
1983 if (so_info->num_outputs)
1984 esvert_lds_size = 4 * so_info->num_outputs + 1;
1985
1986 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1987 * corresponding to the ES thread of the provoking vertex. All
1988 * ES threads load and export PrimitiveID for their thread.
1989 */
1990 if (!nir[MESA_SHADER_TESS_CTRL] &&
1991 infos[MESA_SHADER_VERTEX].vs.outinfo.export_prim_id)
1992 esvert_lds_size = MAX2(esvert_lds_size, 1);
1993 }
1994
1995 unsigned max_gsprims = max_gsprims_base;
1996 unsigned max_esverts = max_esverts_base;
1997
1998 if (esvert_lds_size)
1999 max_esverts = MIN2(max_esverts, target_lds_size / esvert_lds_size);
2000 if (gsprim_lds_size)
2001 max_gsprims = MIN2(max_gsprims, target_lds_size / gsprim_lds_size);
2002
2003 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
2004 clamp_gsprims_to_esverts(&max_gsprims, max_esverts, min_verts_per_prim, uses_adjacency);
2005 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
2006
2007 if (esvert_lds_size || gsprim_lds_size) {
2008 /* Now that we have a rough proportionality between esverts
2009 * and gsprims based on the primitive type, scale both of them
2010 * down simultaneously based on required LDS space.
2011 *
2012 * We could be smarter about this if we knew how much vertex
2013 * reuse to expect.
2014 */
2015 unsigned lds_total = max_esverts * esvert_lds_size +
2016 max_gsprims * gsprim_lds_size;
2017 if (lds_total > target_lds_size) {
2018 max_esverts = max_esverts * target_lds_size / lds_total;
2019 max_gsprims = max_gsprims * target_lds_size / lds_total;
2020
2021 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
2022 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
2023 min_verts_per_prim, uses_adjacency);
2024 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
2025 }
2026 }
2027
2028 /* Round up towards full wave sizes for better ALU utilization. */
2029 if (!max_vert_out_per_gs_instance) {
2030 unsigned orig_max_esverts;
2031 unsigned orig_max_gsprims;
2032 unsigned wavesize;
2033
2034 if (gs_type == MESA_SHADER_GEOMETRY) {
2035 wavesize = gs_info->wave_size;
2036 } else {
2037 wavesize = nir[MESA_SHADER_TESS_CTRL]
2038 ? infos[MESA_SHADER_TESS_EVAL].wave_size
2039 : infos[MESA_SHADER_VERTEX].wave_size;
2040 }
2041
2042 do {
2043 orig_max_esverts = max_esverts;
2044 orig_max_gsprims = max_gsprims;
2045
2046 max_esverts = align(max_esverts, wavesize);
2047 max_esverts = MIN2(max_esverts, max_esverts_base);
2048 if (esvert_lds_size)
2049 max_esverts = MIN2(max_esverts,
2050 (max_lds_size - max_gsprims * gsprim_lds_size) /
2051 esvert_lds_size);
2052 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
2053
2054 max_gsprims = align(max_gsprims, wavesize);
2055 max_gsprims = MIN2(max_gsprims, max_gsprims_base);
2056 if (gsprim_lds_size)
2057 max_gsprims = MIN2(max_gsprims,
2058 (max_lds_size - max_esverts * esvert_lds_size) /
2059 gsprim_lds_size);
2060 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
2061 min_verts_per_prim, uses_adjacency);
2062 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
2063 } while (orig_max_esverts != max_esverts || orig_max_gsprims != max_gsprims);
2064 }
2065
2066 /* Hardware restriction: minimum value of max_esverts */
2067 max_esverts = MAX2(max_esverts, 23 + max_verts_per_prim);
2068
2069 unsigned max_out_vertices =
2070 max_vert_out_per_gs_instance ? gs_info->gs.vertices_out :
2071 gs_type == MESA_SHADER_GEOMETRY ?
2072 max_gsprims * gs_num_invocations * gs_info->gs.vertices_out :
2073 max_esverts;
2074 assert(max_out_vertices <= 256);
2075
2076 unsigned prim_amp_factor = 1;
2077 if (gs_type == MESA_SHADER_GEOMETRY) {
2078 /* Number of output primitives per GS input primitive after
2079 * GS instancing. */
2080 prim_amp_factor = gs_info->gs.vertices_out;
2081 }
2082
2083 /* The GE only checks against the maximum number of ES verts after
2084 * allocating a full GS primitive. So we need to ensure that whenever
2085 * this check passes, there is enough space for a full primitive without
2086 * vertex reuse.
2087 */
2088 ngg->hw_max_esverts = max_esverts - max_verts_per_prim + 1;
2089 ngg->max_gsprims = max_gsprims;
2090 ngg->max_out_verts = max_out_vertices;
2091 ngg->prim_amp_factor = prim_amp_factor;
2092 ngg->max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
2093 ngg->ngg_emit_size = max_gsprims * gsprim_lds_size;
2094 ngg->esgs_ring_size = 4 * max_esverts * esvert_lds_size;
2095
2096 if (gs_type == MESA_SHADER_GEOMETRY) {
2097 ngg->vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
2098 } else {
2099 ngg->vgt_esgs_ring_itemsize = 1;
2100 }
2101
2102 pipeline->graphics.esgs_ring_size = ngg->esgs_ring_size;
2103
2104 assert(ngg->hw_max_esverts >= 24); /* HW limitation */
2105 }
2106
2107 static void
2108 radv_pipeline_init_gs_ring_state(struct radv_pipeline *pipeline,
2109 const struct gfx9_gs_info *gs)
2110 {
2111 struct radv_device *device = pipeline->device;
2112 unsigned num_se = device->physical_device->rad_info.max_se;
2113 unsigned wave_size = 64;
2114 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
2115 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
2116 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2117 */
2118 unsigned gs_vertex_reuse =
2119 (device->physical_device->rad_info.chip_class >= GFX8 ? 32 : 16) * num_se;
2120 unsigned alignment = 256 * num_se;
2121 /* The maximum size is 63.999 MB per SE. */
2122 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
2123 struct radv_shader_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
2124
2125 /* Calculate the minimum size. */
2126 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
2127 wave_size, alignment);
2128 /* These are recommended sizes, not minimum sizes. */
2129 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
2130 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
2131 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
2132 gs_info->gs.max_gsvs_emit_size;
2133
2134 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
2135 esgs_ring_size = align(esgs_ring_size, alignment);
2136 gsvs_ring_size = align(gsvs_ring_size, alignment);
2137
2138 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
2139 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
2140
2141 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
2142 }
2143
2144 struct radv_shader_variant *
2145 radv_get_shader(const struct radv_pipeline *pipeline,
2146 gl_shader_stage stage)
2147 {
2148 if (stage == MESA_SHADER_VERTEX) {
2149 if (pipeline->shaders[MESA_SHADER_VERTEX])
2150 return pipeline->shaders[MESA_SHADER_VERTEX];
2151 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
2152 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
2153 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
2154 return pipeline->shaders[MESA_SHADER_GEOMETRY];
2155 } else if (stage == MESA_SHADER_TESS_EVAL) {
2156 if (!radv_pipeline_has_tess(pipeline))
2157 return NULL;
2158 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
2159 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
2160 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
2161 return pipeline->shaders[MESA_SHADER_GEOMETRY];
2162 }
2163 return pipeline->shaders[stage];
2164 }
2165
2166 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
2167 {
2168 if (radv_pipeline_has_gs(pipeline))
2169 if (radv_pipeline_has_ngg(pipeline))
2170 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
2171 else
2172 return &pipeline->gs_copy_shader->info.vs.outinfo;
2173 else if (radv_pipeline_has_tess(pipeline))
2174 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
2175 else
2176 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
2177 }
2178
2179 static void
2180 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
2181 {
2182 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
2183 int shader_count = 0;
2184
2185 if(shaders[MESA_SHADER_FRAGMENT]) {
2186 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
2187 }
2188 if(shaders[MESA_SHADER_GEOMETRY]) {
2189 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
2190 }
2191 if(shaders[MESA_SHADER_TESS_EVAL]) {
2192 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
2193 }
2194 if(shaders[MESA_SHADER_TESS_CTRL]) {
2195 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
2196 }
2197 if(shaders[MESA_SHADER_VERTEX]) {
2198 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
2199 }
2200
2201 if (shader_count > 1) {
2202 unsigned first = ordered_shaders[shader_count - 1]->info.stage;
2203 unsigned last = ordered_shaders[0]->info.stage;
2204
2205 if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
2206 ordered_shaders[1]->info.has_transform_feedback_varyings)
2207 nir_link_xfb_varyings(ordered_shaders[1], ordered_shaders[0]);
2208
2209 for (int i = 0; i < shader_count; ++i) {
2210 nir_variable_mode mask = 0;
2211
2212 if (ordered_shaders[i]->info.stage != first)
2213 mask = mask | nir_var_shader_in;
2214
2215 if (ordered_shaders[i]->info.stage != last)
2216 mask = mask | nir_var_shader_out;
2217
2218 nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
2219 radv_optimize_nir(ordered_shaders[i], false, false);
2220 }
2221 }
2222
2223 for (int i = 1; i < shader_count; ++i) {
2224 nir_lower_io_arrays_to_elements(ordered_shaders[i],
2225 ordered_shaders[i - 1]);
2226
2227 if (nir_link_opt_varyings(ordered_shaders[i],
2228 ordered_shaders[i - 1]))
2229 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2230
2231 nir_remove_dead_variables(ordered_shaders[i],
2232 nir_var_shader_out, NULL);
2233 nir_remove_dead_variables(ordered_shaders[i - 1],
2234 nir_var_shader_in, NULL);
2235
2236 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
2237 ordered_shaders[i - 1]);
2238
2239 nir_compact_varyings(ordered_shaders[i],
2240 ordered_shaders[i - 1], true);
2241
2242 if (progress) {
2243 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
2244 ac_lower_indirect_derefs(ordered_shaders[i],
2245 pipeline->device->physical_device->rad_info.chip_class);
2246 }
2247 radv_optimize_nir(ordered_shaders[i], false, false);
2248
2249 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
2250 ac_lower_indirect_derefs(ordered_shaders[i - 1],
2251 pipeline->device->physical_device->rad_info.chip_class);
2252 }
2253 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2254 }
2255 }
2256 }
2257
2258 static void
2259 radv_set_linked_driver_locations(struct radv_pipeline *pipeline, nir_shader **shaders,
2260 struct radv_shader_info infos[MESA_SHADER_STAGES])
2261 {
2262 bool has_tess = shaders[MESA_SHADER_TESS_CTRL];
2263 bool has_gs = shaders[MESA_SHADER_GEOMETRY];
2264
2265 if (!has_tess && !has_gs)
2266 return;
2267
2268 unsigned vs_info_idx = MESA_SHADER_VERTEX;
2269 unsigned tes_info_idx = MESA_SHADER_TESS_EVAL;
2270
2271 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2272 /* These are merged into the next stage */
2273 vs_info_idx = has_tess ? MESA_SHADER_TESS_CTRL : MESA_SHADER_GEOMETRY;
2274 tes_info_idx = has_gs ? MESA_SHADER_GEOMETRY : MESA_SHADER_TESS_EVAL;
2275 }
2276
2277 if (has_tess) {
2278 nir_linked_io_var_info vs2tcs =
2279 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_VERTEX], shaders[MESA_SHADER_TESS_CTRL]);
2280 nir_linked_io_var_info tcs2tes =
2281 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_TESS_CTRL], shaders[MESA_SHADER_TESS_EVAL]);
2282
2283 infos[vs_info_idx].vs.num_linked_outputs = vs2tcs.num_linked_io_vars;
2284 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_inputs = vs2tcs.num_linked_io_vars;
2285 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_outputs = tcs2tes.num_linked_io_vars;
2286 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_patch_outputs = tcs2tes.num_linked_patch_io_vars;
2287 infos[tes_info_idx].tes.num_linked_inputs = tcs2tes.num_linked_io_vars;
2288 infos[tes_info_idx].tes.num_linked_patch_inputs = tcs2tes.num_linked_patch_io_vars;
2289
2290 if (has_gs) {
2291 nir_linked_io_var_info tes2gs =
2292 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_TESS_EVAL], shaders[MESA_SHADER_GEOMETRY]);
2293
2294 infos[tes_info_idx].tes.num_linked_outputs = tes2gs.num_linked_io_vars;
2295 infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = tes2gs.num_linked_io_vars;
2296 }
2297 } else if (has_gs) {
2298 nir_linked_io_var_info vs2gs =
2299 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_VERTEX], shaders[MESA_SHADER_GEOMETRY]);
2300
2301 infos[vs_info_idx].vs.num_linked_outputs = vs2gs.num_linked_io_vars;
2302 infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = vs2gs.num_linked_io_vars;
2303 }
2304 }
2305
2306 static uint32_t
2307 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo *input_state,
2308 uint32_t attrib_binding)
2309 {
2310 for (uint32_t i = 0; i < input_state->vertexBindingDescriptionCount; i++) {
2311 const VkVertexInputBindingDescription *input_binding =
2312 &input_state->pVertexBindingDescriptions[i];
2313
2314 if (input_binding->binding == attrib_binding)
2315 return input_binding->stride;
2316 }
2317
2318 return 0;
2319 }
2320
2321 static struct radv_pipeline_key
2322 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
2323 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2324 const struct radv_blend_state *blend)
2325 {
2326 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2327 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2328 const VkPipelineVertexInputStateCreateInfo *input_state =
2329 pCreateInfo->pVertexInputState;
2330 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
2331 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
2332
2333 struct radv_pipeline_key key;
2334 memset(&key, 0, sizeof(key));
2335
2336 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
2337 key.optimisations_disabled = 1;
2338
2339 key.has_multiview_view_index = !!subpass->view_mask;
2340
2341 uint32_t binding_input_rate = 0;
2342 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
2343 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
2344 if (input_state->pVertexBindingDescriptions[i].inputRate) {
2345 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
2346 binding_input_rate |= 1u << binding;
2347 instance_rate_divisors[binding] = 1;
2348 }
2349 }
2350 if (divisor_state) {
2351 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
2352 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
2353 divisor_state->pVertexBindingDivisors[i].divisor;
2354 }
2355 }
2356
2357 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
2358 const VkVertexInputAttributeDescription *desc =
2359 &input_state->pVertexAttributeDescriptions[i];
2360 const struct vk_format_description *format_desc;
2361 unsigned location = desc->location;
2362 unsigned binding = desc->binding;
2363 unsigned num_format, data_format;
2364 int first_non_void;
2365
2366 if (binding_input_rate & (1u << binding)) {
2367 key.instance_rate_inputs |= 1u << location;
2368 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
2369 }
2370
2371 format_desc = vk_format_description(desc->format);
2372 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2373
2374 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2375 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2376
2377 key.vertex_attribute_formats[location] = data_format | (num_format << 4);
2378 key.vertex_attribute_bindings[location] = desc->binding;
2379 key.vertex_attribute_offsets[location] = desc->offset;
2380 key.vertex_attribute_strides[location] = radv_get_attrib_stride(input_state, desc->binding);
2381
2382 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8 &&
2383 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
2384 VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
2385 uint64_t adjust;
2386 switch(format) {
2387 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2388 case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
2389 adjust = RADV_ALPHA_ADJUST_SNORM;
2390 break;
2391 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2392 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
2393 adjust = RADV_ALPHA_ADJUST_SSCALED;
2394 break;
2395 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2396 case VK_FORMAT_A2B10G10R10_SINT_PACK32:
2397 adjust = RADV_ALPHA_ADJUST_SINT;
2398 break;
2399 default:
2400 adjust = 0;
2401 break;
2402 }
2403 key.vertex_alpha_adjust |= adjust << (2 * location);
2404 }
2405
2406 switch (desc->format) {
2407 case VK_FORMAT_B8G8R8A8_UNORM:
2408 case VK_FORMAT_B8G8R8A8_SNORM:
2409 case VK_FORMAT_B8G8R8A8_USCALED:
2410 case VK_FORMAT_B8G8R8A8_SSCALED:
2411 case VK_FORMAT_B8G8R8A8_UINT:
2412 case VK_FORMAT_B8G8R8A8_SINT:
2413 case VK_FORMAT_B8G8R8A8_SRGB:
2414 case VK_FORMAT_A2R10G10B10_UNORM_PACK32:
2415 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2416 case VK_FORMAT_A2R10G10B10_USCALED_PACK32:
2417 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2418 case VK_FORMAT_A2R10G10B10_UINT_PACK32:
2419 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2420 key.vertex_post_shuffle |= 1 << location;
2421 break;
2422 default:
2423 break;
2424 }
2425 }
2426
2427 const VkPipelineTessellationStateCreateInfo *tess =
2428 radv_pipeline_get_tessellation_state(pCreateInfo);
2429 if (tess)
2430 key.tess_input_vertices = tess->patchControlPoints;
2431
2432 const VkPipelineMultisampleStateCreateInfo *vkms =
2433 radv_pipeline_get_multisample_state(pCreateInfo);
2434 if (vkms && vkms->rasterizationSamples > 1) {
2435 uint32_t num_samples = vkms->rasterizationSamples;
2436 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
2437 key.num_samples = num_samples;
2438 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
2439 }
2440
2441 key.col_format = blend->spi_shader_col_format;
2442 key.is_dual_src = blend->mrt0_is_dual_src;
2443 if (pipeline->device->physical_device->rad_info.chip_class < GFX8) {
2444 key.is_int8 = blend->col_format_is_int8;
2445 key.is_int10 = blend->col_format_is_int10;
2446 }
2447
2448 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10)
2449 key.topology = pCreateInfo->pInputAssemblyState->topology;
2450
2451 return key;
2452 }
2453
2454 static bool
2455 radv_nir_stage_uses_xfb(const nir_shader *nir)
2456 {
2457 nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
2458 bool uses_xfb = !!xfb;
2459
2460 ralloc_free(xfb);
2461 return uses_xfb;
2462 }
2463
2464 static void
2465 radv_fill_shader_keys(struct radv_device *device,
2466 struct radv_shader_variant_key *keys,
2467 const struct radv_pipeline_key *key,
2468 nir_shader **nir)
2469 {
2470 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
2471 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
2472 keys[MESA_SHADER_VERTEX].vs.post_shuffle = key->vertex_post_shuffle;
2473 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) {
2474 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
2475 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_formats[i] = key->vertex_attribute_formats[i];
2476 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_bindings[i] = key->vertex_attribute_bindings[i];
2477 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i];
2478 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i];
2479 }
2480 keys[MESA_SHADER_VERTEX].vs.outprim = si_conv_prim_to_gs_out(key->topology);
2481
2482 if (nir[MESA_SHADER_TESS_CTRL]) {
2483 keys[MESA_SHADER_VERTEX].vs_common_out.as_ls = true;
2484 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
2485 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
2486 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
2487
2488 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
2489 }
2490
2491 if (nir[MESA_SHADER_GEOMETRY]) {
2492 if (nir[MESA_SHADER_TESS_CTRL])
2493 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_es = true;
2494 else
2495 keys[MESA_SHADER_VERTEX].vs_common_out.as_es = true;
2496 }
2497
2498 if (device->physical_device->use_ngg) {
2499 if (nir[MESA_SHADER_TESS_CTRL]) {
2500 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = true;
2501 } else {
2502 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = true;
2503 }
2504
2505 if (nir[MESA_SHADER_TESS_CTRL] &&
2506 nir[MESA_SHADER_GEOMETRY] &&
2507 nir[MESA_SHADER_GEOMETRY]->info.gs.invocations *
2508 nir[MESA_SHADER_GEOMETRY]->info.gs.vertices_out > 256) {
2509 /* Fallback to the legacy path if tessellation is
2510 * enabled with extreme geometry because
2511 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2512 * might hang.
2513 */
2514 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2515 }
2516
2517 if (!device->physical_device->use_ngg_gs) {
2518 if (nir[MESA_SHADER_GEOMETRY]) {
2519 if (nir[MESA_SHADER_TESS_CTRL])
2520 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2521 else
2522 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2523 }
2524 }
2525
2526 gl_shader_stage last_xfb_stage = MESA_SHADER_VERTEX;
2527
2528 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
2529 if (nir[i])
2530 last_xfb_stage = i;
2531 }
2532
2533 bool uses_xfb = nir[last_xfb_stage] &&
2534 radv_nir_stage_uses_xfb(nir[last_xfb_stage]);
2535
2536 if (!device->physical_device->use_ngg_streamout && uses_xfb) {
2537 if (nir[MESA_SHADER_TESS_CTRL])
2538 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2539 else
2540 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2541 }
2542
2543 /* Determine if the pipeline is eligible for the NGG passthrough
2544 * mode. It can't be enabled for geometry shaders, for NGG
2545 * streamout or for vertex shaders that export the primitive ID
2546 * (this is checked later because we don't have the info here.)
2547 */
2548 if (!nir[MESA_SHADER_GEOMETRY] && !uses_xfb) {
2549 if (nir[MESA_SHADER_TESS_CTRL] &&
2550 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg) {
2551 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg_passthrough = true;
2552 } else if (nir[MESA_SHADER_VERTEX] &&
2553 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) {
2554 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = true;
2555 }
2556 }
2557 }
2558
2559 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
2560 keys[i].has_multiview_view_index = key->has_multiview_view_index;
2561
2562 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
2563 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
2564 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
2565 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
2566 keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples;
2567 keys[MESA_SHADER_FRAGMENT].fs.is_dual_src = key->is_dual_src;
2568
2569 if (nir[MESA_SHADER_COMPUTE]) {
2570 keys[MESA_SHADER_COMPUTE].cs.subgroup_size = key->compute_subgroup_size;
2571 }
2572 }
2573
2574 static uint8_t
2575 radv_get_wave_size(struct radv_device *device,
2576 const VkPipelineShaderStageCreateInfo *pStage,
2577 gl_shader_stage stage,
2578 const struct radv_shader_variant_key *key)
2579 {
2580 if (stage == MESA_SHADER_GEOMETRY && !key->vs_common_out.as_ngg)
2581 return 64;
2582 else if (stage == MESA_SHADER_COMPUTE) {
2583 if (key->cs.subgroup_size) {
2584 /* Return the required subgroup size if specified. */
2585 return key->cs.subgroup_size;
2586 }
2587 return device->physical_device->cs_wave_size;
2588 }
2589 else if (stage == MESA_SHADER_FRAGMENT)
2590 return device->physical_device->ps_wave_size;
2591 else
2592 return device->physical_device->ge_wave_size;
2593 }
2594
2595 static uint8_t
2596 radv_get_ballot_bit_size(struct radv_device *device,
2597 const VkPipelineShaderStageCreateInfo *pStage,
2598 gl_shader_stage stage,
2599 const struct radv_shader_variant_key *key)
2600 {
2601 if (stage == MESA_SHADER_COMPUTE && key->cs.subgroup_size)
2602 return key->cs.subgroup_size;
2603 return 64;
2604 }
2605
2606 static void
2607 radv_fill_shader_info(struct radv_pipeline *pipeline,
2608 const VkPipelineShaderStageCreateInfo **pStages,
2609 struct radv_shader_variant_key *keys,
2610 struct radv_shader_info *infos,
2611 nir_shader **nir)
2612 {
2613 unsigned active_stages = 0;
2614 unsigned filled_stages = 0;
2615
2616 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2617 if (nir[i])
2618 active_stages |= (1 << i);
2619 }
2620
2621 if (nir[MESA_SHADER_FRAGMENT]) {
2622 radv_nir_shader_info_init(&infos[MESA_SHADER_FRAGMENT]);
2623 radv_nir_shader_info_pass(nir[MESA_SHADER_FRAGMENT],
2624 pipeline->layout,
2625 &keys[MESA_SHADER_FRAGMENT],
2626 &infos[MESA_SHADER_FRAGMENT],
2627 pipeline->device->physical_device->use_llvm);
2628
2629 /* TODO: These are no longer used as keys we should refactor this */
2630 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2631 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2632 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2633 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2634 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2635 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2636 keys[MESA_SHADER_VERTEX].vs_common_out.export_viewport_index =
2637 infos[MESA_SHADER_FRAGMENT].ps.viewport_index_input;
2638 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2639 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2640 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2641 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2642 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2643 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2644 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_viewport_index =
2645 infos[MESA_SHADER_FRAGMENT].ps.viewport_index_input;
2646
2647 /* NGG passthrough mode can't be enabled for vertex shaders
2648 * that export the primitive ID.
2649 *
2650 * TODO: I should really refactor the keys logic.
2651 */
2652 if (nir[MESA_SHADER_VERTEX] &&
2653 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id) {
2654 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = false;
2655 }
2656
2657 filled_stages |= (1 << MESA_SHADER_FRAGMENT);
2658 }
2659
2660 if (nir[MESA_SHADER_TESS_CTRL]) {
2661 infos[MESA_SHADER_TESS_CTRL].tcs.tes_inputs_read =
2662 nir[MESA_SHADER_TESS_EVAL]->info.inputs_read;
2663 infos[MESA_SHADER_TESS_CTRL].tcs.tes_patch_inputs_read =
2664 nir[MESA_SHADER_TESS_EVAL]->info.patch_inputs_read;
2665 }
2666
2667 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2668 nir[MESA_SHADER_TESS_CTRL]) {
2669 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2670 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2671 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2672
2673 radv_nir_shader_info_init(&infos[MESA_SHADER_TESS_CTRL]);
2674
2675 for (int i = 0; i < 2; i++) {
2676 radv_nir_shader_info_pass(combined_nir[i],
2677 pipeline->layout, &key,
2678 &infos[MESA_SHADER_TESS_CTRL],
2679 pipeline->device->physical_device->use_llvm);
2680 }
2681
2682 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2683 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2684 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2685 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2686
2687 filled_stages |= (1 << MESA_SHADER_VERTEX);
2688 filled_stages |= (1 << MESA_SHADER_TESS_CTRL);
2689 }
2690
2691 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2692 nir[MESA_SHADER_GEOMETRY]) {
2693 gl_shader_stage pre_stage = nir[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2694 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2695
2696 radv_nir_shader_info_init(&infos[MESA_SHADER_GEOMETRY]);
2697
2698 for (int i = 0; i < 2; i++) {
2699 radv_nir_shader_info_pass(combined_nir[i],
2700 pipeline->layout,
2701 &keys[pre_stage],
2702 &infos[MESA_SHADER_GEOMETRY],
2703 pipeline->device->physical_device->use_llvm);
2704 }
2705
2706 filled_stages |= (1 << pre_stage);
2707 filled_stages |= (1 << MESA_SHADER_GEOMETRY);
2708 }
2709
2710 active_stages ^= filled_stages;
2711 while (active_stages) {
2712 int i = u_bit_scan(&active_stages);
2713
2714 if (i == MESA_SHADER_TESS_CTRL) {
2715 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs =
2716 util_last_bit64(infos[MESA_SHADER_VERTEX].vs.ls_outputs_written);
2717 }
2718
2719 if (i == MESA_SHADER_TESS_EVAL) {
2720 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2721 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2722 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2723 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2724 }
2725
2726 radv_nir_shader_info_init(&infos[i]);
2727 radv_nir_shader_info_pass(nir[i], pipeline->layout,
2728 &keys[i], &infos[i], pipeline->device->physical_device->use_llvm);
2729 }
2730
2731 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2732 if (nir[i]) {
2733 infos[i].wave_size =
2734 radv_get_wave_size(pipeline->device, pStages[i],
2735 i, &keys[i]);
2736 infos[i].ballot_bit_size =
2737 radv_get_ballot_bit_size(pipeline->device,
2738 pStages[i], i,
2739 &keys[i]);
2740 }
2741 }
2742 }
2743
2744 static void
2745 merge_tess_info(struct shader_info *tes_info,
2746 const struct shader_info *tcs_info)
2747 {
2748 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2749 *
2750 * "PointMode. Controls generation of points rather than triangles
2751 * or lines. This functionality defaults to disabled, and is
2752 * enabled if either shader stage includes the execution mode.
2753 *
2754 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2755 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2756 * and OutputVertices, it says:
2757 *
2758 * "One mode must be set in at least one of the tessellation
2759 * shader stages."
2760 *
2761 * So, the fields can be set in either the TCS or TES, but they must
2762 * agree if set in both. Our backend looks at TES, so bitwise-or in
2763 * the values from the TCS.
2764 */
2765 assert(tcs_info->tess.tcs_vertices_out == 0 ||
2766 tes_info->tess.tcs_vertices_out == 0 ||
2767 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
2768 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
2769
2770 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2771 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2772 tcs_info->tess.spacing == tes_info->tess.spacing);
2773 tes_info->tess.spacing |= tcs_info->tess.spacing;
2774
2775 assert(tcs_info->tess.primitive_mode == 0 ||
2776 tes_info->tess.primitive_mode == 0 ||
2777 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
2778 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
2779 tes_info->tess.ccw |= tcs_info->tess.ccw;
2780 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
2781 }
2782
2783 static
2784 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT *ext)
2785 {
2786 if (!ext)
2787 return;
2788
2789 if (ext->pPipelineCreationFeedback) {
2790 ext->pPipelineCreationFeedback->flags = 0;
2791 ext->pPipelineCreationFeedback->duration = 0;
2792 }
2793
2794 for (unsigned i = 0; i < ext->pipelineStageCreationFeedbackCount; ++i) {
2795 ext->pPipelineStageCreationFeedbacks[i].flags = 0;
2796 ext->pPipelineStageCreationFeedbacks[i].duration = 0;
2797 }
2798 }
2799
2800 static
2801 void radv_start_feedback(VkPipelineCreationFeedbackEXT *feedback)
2802 {
2803 if (!feedback)
2804 return;
2805
2806 feedback->duration -= radv_get_current_time();
2807 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT;
2808 }
2809
2810 static
2811 void radv_stop_feedback(VkPipelineCreationFeedbackEXT *feedback, bool cache_hit)
2812 {
2813 if (!feedback)
2814 return;
2815
2816 feedback->duration += radv_get_current_time();
2817 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT |
2818 (cache_hit ? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT : 0);
2819 }
2820
2821 VkResult radv_create_shaders(struct radv_pipeline *pipeline,
2822 struct radv_device *device,
2823 struct radv_pipeline_cache *cache,
2824 const struct radv_pipeline_key *key,
2825 const VkPipelineShaderStageCreateInfo **pStages,
2826 const VkPipelineCreateFlags flags,
2827 VkPipelineCreationFeedbackEXT *pipeline_feedback,
2828 VkPipelineCreationFeedbackEXT **stage_feedbacks)
2829 {
2830 struct radv_shader_module fs_m = {0};
2831 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2832 nir_shader *nir[MESA_SHADER_STAGES] = {0};
2833 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2834 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{{0}}}}};
2835 struct radv_shader_info infos[MESA_SHADER_STAGES] = {0};
2836 unsigned char hash[20], gs_copy_hash[20];
2837 bool keep_executable_info = (flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR) || device->keep_shader_info;
2838 bool keep_statistic_info = (flags & VK_PIPELINE_CREATE_CAPTURE_STATISTICS_BIT_KHR) ||
2839 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) ||
2840 device->keep_shader_info;
2841
2842 radv_start_feedback(pipeline_feedback);
2843
2844 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2845 if (pStages[i]) {
2846 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
2847 if (modules[i]->nir)
2848 _mesa_sha1_compute(modules[i]->nir->info.name,
2849 strlen(modules[i]->nir->info.name),
2850 modules[i]->sha1);
2851
2852 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
2853 }
2854 }
2855
2856 radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device));
2857 memcpy(gs_copy_hash, hash, 20);
2858 gs_copy_hash[0] ^= 1;
2859
2860 bool found_in_application_cache = true;
2861 if (modules[MESA_SHADER_GEOMETRY] && !keep_executable_info && !keep_statistic_info) {
2862 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2863 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants,
2864 &found_in_application_cache);
2865 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
2866 }
2867
2868 if (!keep_executable_info && !keep_statistic_info &&
2869 radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders,
2870 &found_in_application_cache) &&
2871 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
2872 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2873 return VK_SUCCESS;
2874 }
2875
2876 if (flags & VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_EXT) {
2877 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2878 return VK_PIPELINE_COMPILE_REQUIRED_EXT;
2879 }
2880
2881 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
2882 nir_builder fs_b;
2883 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2884 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2885 fs_m.nir = fs_b.shader;
2886 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2887 }
2888
2889 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2890 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
2891 unsigned subgroup_size = 64, ballot_bit_size = 64;
2892
2893 if (!modules[i])
2894 continue;
2895
2896 radv_start_feedback(stage_feedbacks[i]);
2897
2898 if (key->compute_subgroup_size) {
2899 /* Only compute shaders currently support requiring a
2900 * specific subgroup size.
2901 */
2902 assert(i == MESA_SHADER_COMPUTE);
2903 subgroup_size = key->compute_subgroup_size;
2904 ballot_bit_size = key->compute_subgroup_size;
2905 }
2906
2907 nir[i] = radv_shader_compile_to_nir(device, modules[i],
2908 stage ? stage->pName : "main", i,
2909 stage ? stage->pSpecializationInfo : NULL,
2910 flags, pipeline->layout,
2911 subgroup_size, ballot_bit_size);
2912
2913 /* We don't want to alter meta shaders IR directly so clone it
2914 * first.
2915 */
2916 if (nir[i]->info.name) {
2917 nir[i] = nir_shader_clone(NULL, nir[i]);
2918 }
2919
2920 radv_stop_feedback(stage_feedbacks[i], false);
2921 }
2922
2923 if (nir[MESA_SHADER_TESS_CTRL]) {
2924 nir_lower_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
2925 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
2926 }
2927
2928 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
2929 radv_link_shaders(pipeline, nir);
2930
2931 radv_set_linked_driver_locations(pipeline, nir, infos);
2932
2933 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2934 if (nir[i]) {
2935 /* do this again since information such as outputs_read can be out-of-date */
2936 nir_shader_gather_info(nir[i], nir_shader_get_entrypoint(nir[i]));
2937
2938 if (device->physical_device->use_llvm) {
2939 NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
2940 } else {
2941 NIR_PASS_V(nir[i], nir_lower_non_uniform_access,
2942 nir_lower_non_uniform_ubo_access |
2943 nir_lower_non_uniform_ssbo_access |
2944 nir_lower_non_uniform_texture_access |
2945 nir_lower_non_uniform_image_access);
2946 }
2947 NIR_PASS_V(nir[i], nir_lower_memory_model);
2948 }
2949 }
2950
2951 if (nir[MESA_SHADER_FRAGMENT])
2952 radv_lower_fs_io(nir[MESA_SHADER_FRAGMENT]);
2953
2954 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2955 if (radv_can_dump_shader(device, modules[i], false))
2956 nir_print_shader(nir[i], stderr);
2957 }
2958
2959 radv_fill_shader_keys(device, keys, key, nir);
2960
2961 radv_fill_shader_info(pipeline, pStages, keys, infos, nir);
2962
2963 if ((nir[MESA_SHADER_VERTEX] &&
2964 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) ||
2965 (nir[MESA_SHADER_TESS_EVAL] &&
2966 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg)) {
2967 struct gfx10_ngg_info *ngg_info;
2968
2969 if (nir[MESA_SHADER_GEOMETRY])
2970 ngg_info = &infos[MESA_SHADER_GEOMETRY].ngg_info;
2971 else if (nir[MESA_SHADER_TESS_CTRL])
2972 ngg_info = &infos[MESA_SHADER_TESS_EVAL].ngg_info;
2973 else
2974 ngg_info = &infos[MESA_SHADER_VERTEX].ngg_info;
2975
2976 gfx10_get_ngg_info(key, pipeline, nir, infos, ngg_info);
2977 } else if (nir[MESA_SHADER_GEOMETRY]) {
2978 struct gfx9_gs_info *gs_info =
2979 &infos[MESA_SHADER_GEOMETRY].gs_ring_info;
2980
2981 gfx9_get_gs_info(key, pipeline, nir, infos, gs_info);
2982 }
2983
2984 if(modules[MESA_SHADER_GEOMETRY]) {
2985 struct radv_shader_binary *gs_copy_binary = NULL;
2986 if (!pipeline->gs_copy_shader &&
2987 !radv_pipeline_has_ngg(pipeline)) {
2988 struct radv_shader_info info = {};
2989 struct radv_shader_variant_key key = {};
2990
2991 key.has_multiview_view_index =
2992 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index;
2993
2994 radv_nir_shader_info_pass(nir[MESA_SHADER_GEOMETRY],
2995 pipeline->layout, &key,
2996 &info, pipeline->device->physical_device->use_llvm);
2997 info.wave_size = 64; /* Wave32 not supported. */
2998 info.ballot_bit_size = 64;
2999
3000 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
3001 device, nir[MESA_SHADER_GEOMETRY], &info,
3002 &gs_copy_binary, keep_executable_info, keep_statistic_info,
3003 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
3004 }
3005
3006 if (!keep_executable_info && !keep_statistic_info && pipeline->gs_copy_shader) {
3007 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
3008 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
3009
3010 binaries[MESA_SHADER_GEOMETRY] = gs_copy_binary;
3011 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
3012
3013 radv_pipeline_cache_insert_shaders(device, cache,
3014 gs_copy_hash,
3015 variants,
3016 binaries);
3017 }
3018 free(gs_copy_binary);
3019 }
3020
3021 if (nir[MESA_SHADER_FRAGMENT]) {
3022 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
3023 radv_start_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT]);
3024
3025 pipeline->shaders[MESA_SHADER_FRAGMENT] =
3026 radv_shader_variant_compile(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
3027 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
3028 infos + MESA_SHADER_FRAGMENT,
3029 keep_executable_info, keep_statistic_info,
3030 &binaries[MESA_SHADER_FRAGMENT]);
3031
3032 radv_stop_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT], false);
3033 }
3034 }
3035
3036 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
3037 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
3038 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
3039 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
3040 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
3041
3042 radv_start_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL]);
3043
3044 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
3045 pipeline->layout,
3046 &key, &infos[MESA_SHADER_TESS_CTRL], keep_executable_info,
3047 keep_statistic_info, &binaries[MESA_SHADER_TESS_CTRL]);
3048
3049 radv_stop_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL], false);
3050 }
3051 modules[MESA_SHADER_VERTEX] = NULL;
3052 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
3053 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
3054 }
3055
3056 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
3057 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
3058 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
3059 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
3060
3061 radv_start_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY]);
3062
3063 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
3064 pipeline->layout,
3065 &keys[pre_stage], &infos[MESA_SHADER_GEOMETRY], keep_executable_info,
3066 keep_statistic_info, &binaries[MESA_SHADER_GEOMETRY]);
3067
3068 radv_stop_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY], false);
3069 }
3070 modules[pre_stage] = NULL;
3071 }
3072
3073 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
3074 if(modules[i] && !pipeline->shaders[i]) {
3075 if (i == MESA_SHADER_TESS_CTRL) {
3076 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.ls_outputs_written);
3077 }
3078 if (i == MESA_SHADER_TESS_EVAL) {
3079 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
3080 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
3081 }
3082
3083 radv_start_feedback(stage_feedbacks[i]);
3084
3085 pipeline->shaders[i] = radv_shader_variant_compile(device, modules[i], &nir[i], 1,
3086 pipeline->layout,
3087 keys + i, infos + i, keep_executable_info,
3088 keep_statistic_info, &binaries[i]);
3089
3090 radv_stop_feedback(stage_feedbacks[i], false);
3091 }
3092 }
3093
3094 if (!keep_executable_info && !keep_statistic_info) {
3095 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
3096 binaries);
3097 }
3098
3099 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
3100 free(binaries[i]);
3101 if (nir[i]) {
3102 ralloc_free(nir[i]);
3103
3104 if (radv_can_dump_shader_stats(device, modules[i]))
3105 radv_shader_dump_stats(device,
3106 pipeline->shaders[i],
3107 i, stderr);
3108 }
3109 }
3110
3111 if (fs_m.nir)
3112 ralloc_free(fs_m.nir);
3113
3114 radv_stop_feedback(pipeline_feedback, false);
3115 return VK_SUCCESS;
3116 }
3117
3118 static uint32_t
3119 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
3120 gl_shader_stage stage, enum chip_class chip_class)
3121 {
3122 bool has_gs = radv_pipeline_has_gs(pipeline);
3123 bool has_tess = radv_pipeline_has_tess(pipeline);
3124 bool has_ngg = radv_pipeline_has_ngg(pipeline);
3125
3126 switch (stage) {
3127 case MESA_SHADER_FRAGMENT:
3128 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
3129 case MESA_SHADER_VERTEX:
3130 if (has_tess) {
3131 if (chip_class >= GFX10) {
3132 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
3133 } else if (chip_class == GFX9) {
3134 return R_00B430_SPI_SHADER_USER_DATA_LS_0;
3135 } else {
3136 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
3137 }
3138
3139 }
3140
3141 if (has_gs) {
3142 if (chip_class >= GFX10) {
3143 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3144 } else {
3145 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
3146 }
3147 }
3148
3149 if (has_ngg)
3150 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3151
3152 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
3153 case MESA_SHADER_GEOMETRY:
3154 return chip_class == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
3155 R_00B230_SPI_SHADER_USER_DATA_GS_0;
3156 case MESA_SHADER_COMPUTE:
3157 return R_00B900_COMPUTE_USER_DATA_0;
3158 case MESA_SHADER_TESS_CTRL:
3159 return chip_class == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
3160 R_00B430_SPI_SHADER_USER_DATA_HS_0;
3161 case MESA_SHADER_TESS_EVAL:
3162 if (has_gs) {
3163 return chip_class >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0 :
3164 R_00B330_SPI_SHADER_USER_DATA_ES_0;
3165 } else if (has_ngg) {
3166 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3167 } else {
3168 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
3169 }
3170 default:
3171 unreachable("unknown shader");
3172 }
3173 }
3174
3175 struct radv_bin_size_entry {
3176 unsigned bpp;
3177 VkExtent2D extent;
3178 };
3179
3180 static VkExtent2D
3181 radv_gfx9_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3182 {
3183 static const struct radv_bin_size_entry color_size_table[][3][9] = {
3184 {
3185 /* One RB / SE */
3186 {
3187 /* One shader engine */
3188 { 0, {128, 128}},
3189 { 1, { 64, 128}},
3190 { 2, { 32, 128}},
3191 { 3, { 16, 128}},
3192 { 17, { 0, 0}},
3193 { UINT_MAX, { 0, 0}},
3194 },
3195 {
3196 /* Two shader engines */
3197 { 0, {128, 128}},
3198 { 2, { 64, 128}},
3199 { 3, { 32, 128}},
3200 { 5, { 16, 128}},
3201 { 17, { 0, 0}},
3202 { UINT_MAX, { 0, 0}},
3203 },
3204 {
3205 /* Four shader engines */
3206 { 0, {128, 128}},
3207 { 3, { 64, 128}},
3208 { 5, { 16, 128}},
3209 { 17, { 0, 0}},
3210 { UINT_MAX, { 0, 0}},
3211 },
3212 },
3213 {
3214 /* Two RB / SE */
3215 {
3216 /* One shader engine */
3217 { 0, {128, 128}},
3218 { 2, { 64, 128}},
3219 { 3, { 32, 128}},
3220 { 5, { 16, 128}},
3221 { 33, { 0, 0}},
3222 { UINT_MAX, { 0, 0}},
3223 },
3224 {
3225 /* Two shader engines */
3226 { 0, {128, 128}},
3227 { 3, { 64, 128}},
3228 { 5, { 32, 128}},
3229 { 9, { 16, 128}},
3230 { 33, { 0, 0}},
3231 { UINT_MAX, { 0, 0}},
3232 },
3233 {
3234 /* Four shader engines */
3235 { 0, {256, 256}},
3236 { 2, {128, 256}},
3237 { 3, {128, 128}},
3238 { 5, { 64, 128}},
3239 { 9, { 16, 128}},
3240 { 33, { 0, 0}},
3241 { UINT_MAX, { 0, 0}},
3242 },
3243 },
3244 {
3245 /* Four RB / SE */
3246 {
3247 /* One shader engine */
3248 { 0, {128, 256}},
3249 { 2, {128, 128}},
3250 { 3, { 64, 128}},
3251 { 5, { 32, 128}},
3252 { 9, { 16, 128}},
3253 { 33, { 0, 0}},
3254 { UINT_MAX, { 0, 0}},
3255 },
3256 {
3257 /* Two shader engines */
3258 { 0, {256, 256}},
3259 { 2, {128, 256}},
3260 { 3, {128, 128}},
3261 { 5, { 64, 128}},
3262 { 9, { 32, 128}},
3263 { 17, { 16, 128}},
3264 { 33, { 0, 0}},
3265 { UINT_MAX, { 0, 0}},
3266 },
3267 {
3268 /* Four shader engines */
3269 { 0, {256, 512}},
3270 { 2, {256, 256}},
3271 { 3, {128, 256}},
3272 { 5, {128, 128}},
3273 { 9, { 64, 128}},
3274 { 17, { 16, 128}},
3275 { 33, { 0, 0}},
3276 { UINT_MAX, { 0, 0}},
3277 },
3278 },
3279 };
3280 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
3281 {
3282 // One RB / SE
3283 {
3284 // One shader engine
3285 { 0, {128, 256}},
3286 { 2, {128, 128}},
3287 { 4, { 64, 128}},
3288 { 7, { 32, 128}},
3289 { 13, { 16, 128}},
3290 { 49, { 0, 0}},
3291 { UINT_MAX, { 0, 0}},
3292 },
3293 {
3294 // Two shader engines
3295 { 0, {256, 256}},
3296 { 2, {128, 256}},
3297 { 4, {128, 128}},
3298 { 7, { 64, 128}},
3299 { 13, { 32, 128}},
3300 { 25, { 16, 128}},
3301 { 49, { 0, 0}},
3302 { UINT_MAX, { 0, 0}},
3303 },
3304 {
3305 // Four shader engines
3306 { 0, {256, 512}},
3307 { 2, {256, 256}},
3308 { 4, {128, 256}},
3309 { 7, {128, 128}},
3310 { 13, { 64, 128}},
3311 { 25, { 16, 128}},
3312 { 49, { 0, 0}},
3313 { UINT_MAX, { 0, 0}},
3314 },
3315 },
3316 {
3317 // Two RB / SE
3318 {
3319 // One shader engine
3320 { 0, {256, 256}},
3321 { 2, {128, 256}},
3322 { 4, {128, 128}},
3323 { 7, { 64, 128}},
3324 { 13, { 32, 128}},
3325 { 25, { 16, 128}},
3326 { 97, { 0, 0}},
3327 { UINT_MAX, { 0, 0}},
3328 },
3329 {
3330 // Two shader engines
3331 { 0, {256, 512}},
3332 { 2, {256, 256}},
3333 { 4, {128, 256}},
3334 { 7, {128, 128}},
3335 { 13, { 64, 128}},
3336 { 25, { 32, 128}},
3337 { 49, { 16, 128}},
3338 { 97, { 0, 0}},
3339 { UINT_MAX, { 0, 0}},
3340 },
3341 {
3342 // Four shader engines
3343 { 0, {512, 512}},
3344 { 2, {256, 512}},
3345 { 4, {256, 256}},
3346 { 7, {128, 256}},
3347 { 13, {128, 128}},
3348 { 25, { 64, 128}},
3349 { 49, { 16, 128}},
3350 { 97, { 0, 0}},
3351 { UINT_MAX, { 0, 0}},
3352 },
3353 },
3354 {
3355 // Four RB / SE
3356 {
3357 // One shader engine
3358 { 0, {256, 512}},
3359 { 2, {256, 256}},
3360 { 4, {128, 256}},
3361 { 7, {128, 128}},
3362 { 13, { 64, 128}},
3363 { 25, { 32, 128}},
3364 { 49, { 16, 128}},
3365 { UINT_MAX, { 0, 0}},
3366 },
3367 {
3368 // Two shader engines
3369 { 0, {512, 512}},
3370 { 2, {256, 512}},
3371 { 4, {256, 256}},
3372 { 7, {128, 256}},
3373 { 13, {128, 128}},
3374 { 25, { 64, 128}},
3375 { 49, { 32, 128}},
3376 { 97, { 16, 128}},
3377 { UINT_MAX, { 0, 0}},
3378 },
3379 {
3380 // Four shader engines
3381 { 0, {512, 512}},
3382 { 4, {256, 512}},
3383 { 7, {256, 256}},
3384 { 13, {128, 256}},
3385 { 25, {128, 128}},
3386 { 49, { 64, 128}},
3387 { 97, { 16, 128}},
3388 { UINT_MAX, { 0, 0}},
3389 },
3390 },
3391 };
3392
3393 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3394 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3395 VkExtent2D extent = {512, 512};
3396
3397 unsigned log_num_rb_per_se =
3398 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
3399 pipeline->device->physical_device->rad_info.max_se);
3400 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
3401
3402 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3403 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
3404 unsigned effective_samples = total_samples;
3405 unsigned color_bytes_per_pixel = 0;
3406
3407 const VkPipelineColorBlendStateCreateInfo *vkblend =
3408 radv_pipeline_get_color_blend_state(pCreateInfo);
3409 if (vkblend) {
3410 for (unsigned i = 0; i < subpass->color_count; i++) {
3411 if (!vkblend->pAttachments[i].colorWriteMask)
3412 continue;
3413
3414 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3415 continue;
3416
3417 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3418 color_bytes_per_pixel += vk_format_get_blocksize(format);
3419 }
3420
3421 /* MSAA images typically don't use all samples all the time. */
3422 if (effective_samples >= 2 && ps_iter_samples <= 1)
3423 effective_samples = 2;
3424 color_bytes_per_pixel *= effective_samples;
3425 }
3426
3427 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
3428 while(color_entry[1].bpp <= color_bytes_per_pixel)
3429 ++color_entry;
3430
3431 extent = color_entry->extent;
3432
3433 if (subpass->depth_stencil_attachment) {
3434 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3435
3436 /* Coefficients taken from AMDVLK */
3437 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3438 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3439 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
3440
3441 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
3442 while(ds_entry[1].bpp <= ds_bytes_per_pixel)
3443 ++ds_entry;
3444
3445 if (ds_entry->extent.width * ds_entry->extent.height < extent.width * extent.height)
3446 extent = ds_entry->extent;
3447 }
3448
3449 return extent;
3450 }
3451
3452 static VkExtent2D
3453 radv_gfx10_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3454 {
3455 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3456 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3457 VkExtent2D extent = {512, 512};
3458
3459 const unsigned db_tag_size = 64;
3460 const unsigned db_tag_count = 312;
3461 const unsigned color_tag_size = 1024;
3462 const unsigned color_tag_count = 31;
3463 const unsigned fmask_tag_size = 256;
3464 const unsigned fmask_tag_count = 44;
3465
3466 const unsigned rb_count = pipeline->device->physical_device->rad_info.num_render_backends;
3467 const unsigned pipe_count = MAX2(rb_count, pipeline->device->physical_device->rad_info.num_sdp_interfaces);
3468
3469 const unsigned db_tag_part = (db_tag_count * rb_count / pipe_count) * db_tag_size * pipe_count;
3470 const unsigned color_tag_part = (color_tag_count * rb_count / pipe_count) * color_tag_size * pipe_count;
3471 const unsigned fmask_tag_part = (fmask_tag_count * rb_count / pipe_count) * fmask_tag_size * pipe_count;
3472
3473 const unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3474 const unsigned samples_log = util_logbase2_ceil(total_samples);
3475
3476 unsigned color_bytes_per_pixel = 0;
3477 unsigned fmask_bytes_per_pixel = 0;
3478
3479 const VkPipelineColorBlendStateCreateInfo *vkblend =
3480 radv_pipeline_get_color_blend_state(pCreateInfo);
3481 if (vkblend) {
3482 for (unsigned i = 0; i < subpass->color_count; i++) {
3483 if (!vkblend->pAttachments[i].colorWriteMask)
3484 continue;
3485
3486 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3487 continue;
3488
3489 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3490 color_bytes_per_pixel += vk_format_get_blocksize(format);
3491
3492 if (total_samples > 1) {
3493 assert(samples_log <= 3);
3494 const unsigned fmask_array[] = {0, 1, 1, 4};
3495 fmask_bytes_per_pixel += fmask_array[samples_log];
3496 }
3497 }
3498
3499 color_bytes_per_pixel *= total_samples;
3500 }
3501 color_bytes_per_pixel = MAX2(color_bytes_per_pixel, 1);
3502
3503 const unsigned color_pixel_count_log = util_logbase2(color_tag_part / color_bytes_per_pixel);
3504 extent.width = 1ull << ((color_pixel_count_log + 1) / 2);
3505 extent.height = 1ull << (color_pixel_count_log / 2);
3506
3507 if (fmask_bytes_per_pixel) {
3508 const unsigned fmask_pixel_count_log = util_logbase2(fmask_tag_part / fmask_bytes_per_pixel);
3509
3510 const VkExtent2D fmask_extent = (VkExtent2D){
3511 .width = 1ull << ((fmask_pixel_count_log + 1) / 2),
3512 .height = 1ull << (color_pixel_count_log / 2)
3513 };
3514
3515 if (fmask_extent.width * fmask_extent.height < extent.width * extent.height)
3516 extent = fmask_extent;
3517 }
3518
3519 if (subpass->depth_stencil_attachment) {
3520 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3521
3522 /* Coefficients taken from AMDVLK */
3523 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3524 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3525 unsigned db_bytes_per_pixel = (depth_coeff + stencil_coeff) * total_samples;
3526
3527 const unsigned db_pixel_count_log = util_logbase2(db_tag_part / db_bytes_per_pixel);
3528
3529 const VkExtent2D db_extent = (VkExtent2D){
3530 .width = 1ull << ((db_pixel_count_log + 1) / 2),
3531 .height = 1ull << (color_pixel_count_log / 2)
3532 };
3533
3534 if (db_extent.width * db_extent.height < extent.width * extent.height)
3535 extent = db_extent;
3536 }
3537
3538 extent.width = MAX2(extent.width, 128);
3539 extent.height = MAX2(extent.width, 64);
3540
3541 return extent;
3542 }
3543
3544 static void
3545 radv_pipeline_init_disabled_binning_state(struct radv_pipeline *pipeline,
3546 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3547 {
3548 uint32_t pa_sc_binner_cntl_0 =
3549 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
3550 S_028C44_DISABLE_START_OF_PRIM(1);
3551 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3552
3553 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3554 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3555 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3556 const VkPipelineColorBlendStateCreateInfo *vkblend =
3557 radv_pipeline_get_color_blend_state(pCreateInfo);
3558 unsigned min_bytes_per_pixel = 0;
3559
3560 if (vkblend) {
3561 for (unsigned i = 0; i < subpass->color_count; i++) {
3562 if (!vkblend->pAttachments[i].colorWriteMask)
3563 continue;
3564
3565 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3566 continue;
3567
3568 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3569 unsigned bytes = vk_format_get_blocksize(format);
3570 if (!min_bytes_per_pixel || bytes < min_bytes_per_pixel)
3571 min_bytes_per_pixel = bytes;
3572 }
3573 }
3574
3575 pa_sc_binner_cntl_0 =
3576 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) |
3577 S_028C44_BIN_SIZE_X(0) |
3578 S_028C44_BIN_SIZE_Y(0) |
3579 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3580 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel <= 4 ? 2 : 1) | /* 128 or 64 */
3581 S_028C44_DISABLE_START_OF_PRIM(1);
3582 }
3583
3584 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3585 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3586 }
3587
3588 struct radv_binning_settings
3589 radv_get_binning_settings(const struct radv_physical_device *pdev)
3590 {
3591 struct radv_binning_settings settings;
3592 if (pdev->rad_info.has_dedicated_vram) {
3593 if (pdev->rad_info.num_render_backends > 4) {
3594 settings.context_states_per_bin = 1;
3595 settings.persistent_states_per_bin = 1;
3596 } else {
3597 settings.context_states_per_bin = 3;
3598 settings.persistent_states_per_bin = 8;
3599 }
3600 settings.fpovs_per_batch = 63;
3601 } else {
3602 /* The context states are affected by the scissor bug. */
3603 settings.context_states_per_bin = 6;
3604 /* 32 causes hangs for RAVEN. */
3605 settings.persistent_states_per_bin = 16;
3606 settings.fpovs_per_batch = 63;
3607 }
3608
3609 if (pdev->rad_info.has_gfx9_scissor_bug)
3610 settings.context_states_per_bin = 1;
3611
3612 return settings;
3613 }
3614
3615 static void
3616 radv_pipeline_init_binning_state(struct radv_pipeline *pipeline,
3617 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3618 const struct radv_blend_state *blend)
3619 {
3620 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
3621 return;
3622
3623 VkExtent2D bin_size;
3624 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3625 bin_size = radv_gfx10_compute_bin_size(pipeline, pCreateInfo);
3626 } else if (pipeline->device->physical_device->rad_info.chip_class == GFX9) {
3627 bin_size = radv_gfx9_compute_bin_size(pipeline, pCreateInfo);
3628 } else
3629 unreachable("Unhandled generation for binning bin size calculation");
3630
3631 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
3632 struct radv_binning_settings settings =
3633 radv_get_binning_settings(pipeline->device->physical_device);
3634
3635 bool disable_start_of_prim = true;
3636 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3637
3638 const struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3639
3640 if (pipeline->device->dfsm_allowed && ps &&
3641 !ps->info.ps.can_discard &&
3642 !ps->info.ps.writes_memory &&
3643 blend->cb_target_enabled_4bit) {
3644 db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_AUTO);
3645 disable_start_of_prim = (blend->blend_enable_4bit & blend->cb_target_enabled_4bit) != 0;
3646 }
3647
3648 const uint32_t pa_sc_binner_cntl_0 =
3649 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
3650 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
3651 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
3652 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
3653 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
3654 S_028C44_CONTEXT_STATES_PER_BIN(settings.context_states_per_bin - 1) |
3655 S_028C44_PERSISTENT_STATES_PER_BIN(settings.persistent_states_per_bin - 1) |
3656 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim) |
3657 S_028C44_FPOVS_PER_BATCH(settings.fpovs_per_batch) |
3658 S_028C44_OPTIMAL_BIN_SELECTION(1);
3659
3660 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3661 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3662 } else
3663 radv_pipeline_init_disabled_binning_state(pipeline, pCreateInfo);
3664 }
3665
3666
3667 static void
3668 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs,
3669 const struct radv_pipeline *pipeline,
3670 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3671 const struct radv_graphics_pipeline_create_info *extra)
3672 {
3673 const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
3674 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3675 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3676 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3677 struct radv_render_pass_attachment *attachment = NULL;
3678 uint32_t db_render_control = 0, db_render_override2 = 0;
3679 uint32_t db_render_override = 0;
3680
3681 if (subpass->depth_stencil_attachment)
3682 attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3683
3684 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
3685
3686 if (vkds && has_depth_attachment) {
3687 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3688 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
3689
3690 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10_3)
3691 db_render_override2 |= S_028010_CENTROID_COMPUTATION_MODE_GFX103(2);
3692 }
3693
3694 if (attachment && extra) {
3695 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
3696 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
3697
3698 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->resummarize_enable);
3699 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->depth_compress_disable);
3700 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->stencil_compress_disable);
3701 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
3702 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
3703 }
3704
3705 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3706 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
3707
3708 if (!pCreateInfo->pRasterizationState->depthClampEnable &&
3709 ps->info.ps.writes_z) {
3710 /* From VK_EXT_depth_range_unrestricted spec:
3711 *
3712 * "The behavior described in Primitive Clipping still applies.
3713 * If depth clamping is disabled the depth values are still
3714 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3715 * depth clamping is enabled the above equation is ignored and
3716 * the depth values are instead clamped to the VkViewport
3717 * minDepth and maxDepth values, which in the case of this
3718 * extension can be outside of the 0.0 to 1.0 range."
3719 */
3720 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3721 }
3722
3723 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control);
3724 radeon_set_context_reg(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
3725 radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
3726 }
3727
3728 static void
3729 radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
3730 const struct radv_pipeline *pipeline,
3731 const struct radv_blend_state *blend)
3732 {
3733 radeon_set_context_reg_seq(ctx_cs, R_028780_CB_BLEND0_CONTROL, 8);
3734 radeon_emit_array(ctx_cs, blend->cb_blend_control,
3735 8);
3736 radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
3737 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
3738
3739 if (pipeline->device->physical_device->rad_info.has_rbplus) {
3740
3741 radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
3742 radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
3743 }
3744
3745 radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
3746
3747 radeon_set_context_reg(ctx_cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
3748 radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
3749 }
3750
3751 static void
3752 radv_pipeline_generate_raster_state(struct radeon_cmdbuf *ctx_cs,
3753 const struct radv_pipeline *pipeline,
3754 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3755 {
3756 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
3757 const VkConservativeRasterizationModeEXT mode =
3758 radv_get_conservative_raster_mode(vkraster);
3759 uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3760 bool depth_clip_disable = vkraster->depthClampEnable;
3761
3762 const VkPipelineRasterizationDepthClipStateCreateInfoEXT *depth_clip_state =
3763 vk_find_struct_const(vkraster->pNext, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT);
3764 if (depth_clip_state) {
3765 depth_clip_disable = !depth_clip_state->depthClipEnable;
3766 }
3767
3768 radeon_set_context_reg(ctx_cs, R_028810_PA_CL_CLIP_CNTL,
3769 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3770 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable ? 1 : 0) |
3771 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable ? 1 : 0) |
3772 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
3773 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3774
3775 radeon_set_context_reg(ctx_cs, R_028BDC_PA_SC_LINE_CNTL,
3776 S_028BDC_DX10_DIAMOND_TEST_ENA(1));
3777
3778 /* Conservative rasterization. */
3779 if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
3780 pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3781 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3782 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3783
3784 if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) {
3785 pa_sc_conservative_rast |=
3786 S_028C4C_OVER_RAST_ENABLE(1) |
3787 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3788 S_028C4C_UNDER_RAST_ENABLE(0) |
3789 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3790 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3791 } else {
3792 assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT);
3793 pa_sc_conservative_rast |=
3794 S_028C4C_OVER_RAST_ENABLE(0) |
3795 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3796 S_028C4C_UNDER_RAST_ENABLE(1) |
3797 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3798 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3799 }
3800 }
3801
3802 radeon_set_context_reg(ctx_cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
3803 pa_sc_conservative_rast);
3804 }
3805
3806
3807 static void
3808 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
3809 const struct radv_pipeline *pipeline)
3810 {
3811 const struct radv_multisample_state *ms = &pipeline->graphics.ms;
3812
3813 radeon_set_context_reg_seq(ctx_cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3814 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[0]);
3815 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]);
3816
3817 radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa);
3818 radeon_set_context_reg(ctx_cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
3819 radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
3820 radeon_set_context_reg(ctx_cs, R_028BE0_PA_SC_AA_CONFIG, ms->pa_sc_aa_config);
3821
3822 /* The exclusion bits can be set to improve rasterization efficiency
3823 * if no sample lies on the pixel boundary (-8 sample offset). It's
3824 * currently always TRUE because the driver doesn't support 16 samples.
3825 */
3826 bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= GFX7;
3827 radeon_set_context_reg(ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3828 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3829 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3830
3831 /* GFX9: Flush DFSM when the AA mode changes. */
3832 if (pipeline->device->dfsm_allowed) {
3833 radeon_emit(ctx_cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3834 radeon_emit(ctx_cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3835 }
3836 }
3837
3838 static void
3839 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
3840 const struct radv_pipeline *pipeline)
3841 {
3842 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3843 const struct radv_shader_variant *vs =
3844 pipeline->shaders[MESA_SHADER_TESS_EVAL] ?
3845 pipeline->shaders[MESA_SHADER_TESS_EVAL] :
3846 pipeline->shaders[MESA_SHADER_VERTEX];
3847 unsigned vgt_primitiveid_en = 0;
3848 uint32_t vgt_gs_mode = 0;
3849
3850 if (radv_pipeline_has_ngg(pipeline))
3851 return;
3852
3853 if (radv_pipeline_has_gs(pipeline)) {
3854 const struct radv_shader_variant *gs =
3855 pipeline->shaders[MESA_SHADER_GEOMETRY];
3856
3857 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
3858 pipeline->device->physical_device->rad_info.chip_class);
3859 } else if (outinfo->export_prim_id || vs->info.uses_prim_id) {
3860 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
3861 vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(1);
3862 }
3863
3864 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
3865 radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
3866 }
3867
3868 static void
3869 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
3870 struct radeon_cmdbuf *cs,
3871 const struct radv_pipeline *pipeline,
3872 const struct radv_shader_variant *shader)
3873 {
3874 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3875
3876 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
3877 radeon_emit(cs, va >> 8);
3878 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
3879 radeon_emit(cs, shader->config.rsrc1);
3880 radeon_emit(cs, shader->config.rsrc2);
3881
3882 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3883 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3884 clip_dist_mask = outinfo->clip_dist_mask;
3885 cull_dist_mask = outinfo->cull_dist_mask;
3886 total_mask = clip_dist_mask | cull_dist_mask;
3887 bool misc_vec_ena = outinfo->writes_pointsize ||
3888 outinfo->writes_layer ||
3889 outinfo->writes_viewport_index;
3890 unsigned spi_vs_out_config, nparams;
3891
3892 /* VS is required to export at least one param. */
3893 nparams = MAX2(outinfo->param_exports, 1);
3894 spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
3895
3896 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3897 spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0);
3898 }
3899
3900 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, spi_vs_out_config);
3901
3902 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3903 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3904 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3905 V_02870C_SPI_SHADER_4COMP :
3906 V_02870C_SPI_SHADER_NONE) |
3907 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3908 V_02870C_SPI_SHADER_4COMP :
3909 V_02870C_SPI_SHADER_NONE) |
3910 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3911 V_02870C_SPI_SHADER_4COMP :
3912 V_02870C_SPI_SHADER_NONE));
3913
3914 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3915 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3916 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3917 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3918 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3919 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3920 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3921 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3922 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) |
3923 cull_dist_mask << 8 |
3924 clip_dist_mask);
3925
3926 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
3927 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
3928 outinfo->writes_viewport_index);
3929 }
3930
3931 static void
3932 radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs,
3933 const struct radv_pipeline *pipeline,
3934 const struct radv_shader_variant *shader)
3935 {
3936 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3937
3938 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
3939 radeon_emit(cs, va >> 8);
3940 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3941 radeon_emit(cs, shader->config.rsrc1);
3942 radeon_emit(cs, shader->config.rsrc2);
3943 }
3944
3945 static void
3946 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs,
3947 const struct radv_pipeline *pipeline,
3948 const struct radv_shader_variant *shader)
3949 {
3950 unsigned num_lds_blocks = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_lds_blocks;
3951 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3952 uint32_t rsrc2 = shader->config.rsrc2;
3953
3954 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3955 radeon_emit(cs, va >> 8);
3956 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3957
3958 rsrc2 |= S_00B52C_LDS_SIZE(num_lds_blocks);
3959 if (pipeline->device->physical_device->rad_info.chip_class == GFX7 &&
3960 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
3961 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
3962
3963 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
3964 radeon_emit(cs, shader->config.rsrc1);
3965 radeon_emit(cs, rsrc2);
3966 }
3967
3968 static void
3969 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
3970 struct radeon_cmdbuf *cs,
3971 const struct radv_pipeline *pipeline,
3972 const struct radv_shader_variant *shader)
3973 {
3974 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3975 gl_shader_stage es_type =
3976 radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
3977 struct radv_shader_variant *es =
3978 es_type == MESA_SHADER_TESS_EVAL ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX];
3979 const struct gfx10_ngg_info *ngg_state = &shader->info.ngg_info;
3980
3981 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
3982 radeon_emit(cs, va >> 8);
3983 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3984 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
3985 radeon_emit(cs, shader->config.rsrc1);
3986 radeon_emit(cs, shader->config.rsrc2);
3987
3988 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3989 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3990 clip_dist_mask = outinfo->clip_dist_mask;
3991 cull_dist_mask = outinfo->cull_dist_mask;
3992 total_mask = clip_dist_mask | cull_dist_mask;
3993 bool misc_vec_ena = outinfo->writes_pointsize ||
3994 outinfo->writes_layer ||
3995 outinfo->writes_viewport_index;
3996 bool es_enable_prim_id = outinfo->export_prim_id ||
3997 (es && es->info.uses_prim_id);
3998 bool break_wave_at_eoi = false;
3999 unsigned ge_cntl;
4000 unsigned nparams;
4001
4002 if (es_type == MESA_SHADER_TESS_EVAL) {
4003 struct radv_shader_variant *gs =
4004 pipeline->shaders[MESA_SHADER_GEOMETRY];
4005
4006 if (es_enable_prim_id || (gs && gs->info.uses_prim_id))
4007 break_wave_at_eoi = true;
4008 }
4009
4010 nparams = MAX2(outinfo->param_exports, 1);
4011 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG,
4012 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
4013 S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0));
4014
4015 radeon_set_context_reg(ctx_cs, R_028708_SPI_SHADER_IDX_FORMAT,
4016 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP));
4017 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
4018 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
4019 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
4020 V_02870C_SPI_SHADER_4COMP :
4021 V_02870C_SPI_SHADER_NONE) |
4022 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
4023 V_02870C_SPI_SHADER_4COMP :
4024 V_02870C_SPI_SHADER_NONE) |
4025 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
4026 V_02870C_SPI_SHADER_4COMP :
4027 V_02870C_SPI_SHADER_NONE));
4028
4029 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
4030 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
4031 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
4032 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
4033 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
4034 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
4035 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
4036 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
4037 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) |
4038 cull_dist_mask << 8 |
4039 clip_dist_mask);
4040
4041 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN,
4042 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
4043 S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo->export_prim_id));
4044
4045 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
4046 ngg_state->vgt_esgs_ring_itemsize);
4047
4048 /* NGG specific registers. */
4049 struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
4050 uint32_t gs_num_invocations = gs ? gs->info.gs.invocations : 1;
4051
4052 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
4053 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state->hw_max_esverts) |
4054 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state->max_gsprims) |
4055 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state->max_gsprims * gs_num_invocations));
4056 radeon_set_context_reg(ctx_cs, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
4057 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state->max_out_verts));
4058 radeon_set_context_reg(ctx_cs, R_028B4C_GE_NGG_SUBGRP_CNTL,
4059 S_028B4C_PRIM_AMP_FACTOR(ngg_state->prim_amp_factor) |
4060 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
4061 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
4062 S_028B90_CNT(gs_num_invocations) |
4063 S_028B90_ENABLE(gs_num_invocations > 1) |
4064 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state->max_vert_out_per_gs_instance));
4065
4066 /* User edge flags are set by the pos exports. If user edge flags are
4067 * not used, we must use hw-generated edge flags and pass them via
4068 * the prim export to prevent drawing lines on internal edges of
4069 * decomposed primitives (such as quads) with polygon mode = lines.
4070 *
4071 * TODO: We should combine hw-generated edge flags with user edge
4072 * flags in the shader.
4073 */
4074 radeon_set_context_reg(ctx_cs, R_028838_PA_CL_NGG_CNTL,
4075 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) &&
4076 !radv_pipeline_has_gs(pipeline)) |
4077 /* Reuse for NGG. */
4078 S_028838_VERTEX_REUSE_DEPTH_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3 ? 30 : 0));
4079
4080 ge_cntl = S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) |
4081 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
4082 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
4083
4084 /* Bug workaround for a possible hang with non-tessellation cases.
4085 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
4086 *
4087 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
4088 */
4089 if (pipeline->device->physical_device->rad_info.chip_class == GFX10 &&
4090 !radv_pipeline_has_tess(pipeline) &&
4091 ngg_state->hw_max_esverts != 256) {
4092 ge_cntl &= C_03096C_VERT_GRP_SIZE;
4093
4094 if (ngg_state->hw_max_esverts > 5) {
4095 ge_cntl |= S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts - 5);
4096 }
4097 }
4098
4099 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, ge_cntl);
4100 }
4101
4102 static void
4103 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
4104 const struct radv_pipeline *pipeline,
4105 const struct radv_shader_variant *shader)
4106 {
4107 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
4108
4109 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4110 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4111 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
4112 radeon_emit(cs, va >> 8);
4113 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
4114 } else {
4115 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
4116 radeon_emit(cs, va >> 8);
4117 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
4118 }
4119
4120 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
4121 radeon_emit(cs, shader->config.rsrc1);
4122 radeon_emit(cs, shader->config.rsrc2);
4123 } else {
4124 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
4125 radeon_emit(cs, va >> 8);
4126 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
4127 radeon_emit(cs, shader->config.rsrc1);
4128 radeon_emit(cs, shader->config.rsrc2);
4129 }
4130 }
4131
4132 static void
4133 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *ctx_cs,
4134 struct radeon_cmdbuf *cs,
4135 const struct radv_pipeline *pipeline)
4136 {
4137 struct radv_shader_variant *vs;
4138
4139 /* Skip shaders merged into HS/GS */
4140 vs = pipeline->shaders[MESA_SHADER_VERTEX];
4141 if (!vs)
4142 return;
4143
4144 if (vs->info.vs.as_ls)
4145 radv_pipeline_generate_hw_ls(cs, pipeline, vs);
4146 else if (vs->info.vs.as_es)
4147 radv_pipeline_generate_hw_es(cs, pipeline, vs);
4148 else if (vs->info.is_ngg)
4149 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, vs);
4150 else
4151 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, vs);
4152 }
4153
4154 static void
4155 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs,
4156 struct radeon_cmdbuf *cs,
4157 const struct radv_pipeline *pipeline)
4158 {
4159 struct radv_shader_variant *tes, *tcs;
4160
4161 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
4162 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
4163
4164 if (tes) {
4165 if (tes->info.is_ngg) {
4166 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, tes);
4167 } else if (tes->info.tes.as_es)
4168 radv_pipeline_generate_hw_es(cs, pipeline, tes);
4169 else
4170 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes);
4171 }
4172
4173 radv_pipeline_generate_hw_hs(cs, pipeline, tcs);
4174
4175 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 &&
4176 !radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
4177 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
4178 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4179 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4180 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4181 }
4182 }
4183
4184 static void
4185 radv_pipeline_generate_tess_state(struct radeon_cmdbuf *ctx_cs,
4186 const struct radv_pipeline *pipeline,
4187 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4188 {
4189 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
4190 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
4191 unsigned num_tcs_input_cp, num_tcs_output_cp, num_patches;
4192 unsigned ls_hs_config;
4193
4194 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
4195 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
4196 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
4197
4198 ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
4199 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
4200 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
4201
4202 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
4203 radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG,
4204 2, ls_hs_config);
4205 } else {
4206 radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG,
4207 ls_hs_config);
4208 }
4209
4210 switch (tes->info.tes.primitive_mode) {
4211 case GL_TRIANGLES:
4212 type = V_028B6C_TESS_TRIANGLE;
4213 break;
4214 case GL_QUADS:
4215 type = V_028B6C_TESS_QUAD;
4216 break;
4217 case GL_ISOLINES:
4218 type = V_028B6C_TESS_ISOLINE;
4219 break;
4220 }
4221
4222 switch (tes->info.tes.spacing) {
4223 case TESS_SPACING_EQUAL:
4224 partitioning = V_028B6C_PART_INTEGER;
4225 break;
4226 case TESS_SPACING_FRACTIONAL_ODD:
4227 partitioning = V_028B6C_PART_FRAC_ODD;
4228 break;
4229 case TESS_SPACING_FRACTIONAL_EVEN:
4230 partitioning = V_028B6C_PART_FRAC_EVEN;
4231 break;
4232 default:
4233 break;
4234 }
4235
4236 bool ccw = tes->info.tes.ccw;
4237 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_origin_state =
4238 vk_find_struct_const(pCreateInfo->pTessellationState,
4239 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
4240
4241 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT)
4242 ccw = !ccw;
4243
4244 if (tes->info.tes.point_mode)
4245 topology = V_028B6C_OUTPUT_POINT;
4246 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
4247 topology = V_028B6C_OUTPUT_LINE;
4248 else if (ccw)
4249 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
4250 else
4251 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
4252
4253 if (pipeline->device->physical_device->rad_info.has_distributed_tess) {
4254 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
4255 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
4256 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
4257 else
4258 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
4259 } else
4260 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
4261
4262 radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM,
4263 S_028B6C_TYPE(type) |
4264 S_028B6C_PARTITIONING(partitioning) |
4265 S_028B6C_TOPOLOGY(topology) |
4266 S_028B6C_DISTRIBUTION_MODE(distribution_mode));
4267 }
4268
4269 static void
4270 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs,
4271 struct radeon_cmdbuf *cs,
4272 const struct radv_pipeline *pipeline,
4273 const struct radv_shader_variant *gs)
4274 {
4275 const struct gfx9_gs_info *gs_state = &gs->info.gs_ring_info;
4276 unsigned gs_max_out_vertices;
4277 const uint8_t *num_components;
4278 uint8_t max_stream;
4279 unsigned offset;
4280 uint64_t va;
4281
4282 gs_max_out_vertices = gs->info.gs.vertices_out;
4283 max_stream = gs->info.gs.max_stream;
4284 num_components = gs->info.gs.num_stream_output_components;
4285
4286 offset = num_components[0] * gs_max_out_vertices;
4287
4288 radeon_set_context_reg_seq(ctx_cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
4289 radeon_emit(ctx_cs, offset);
4290 if (max_stream >= 1)
4291 offset += num_components[1] * gs_max_out_vertices;
4292 radeon_emit(ctx_cs, offset);
4293 if (max_stream >= 2)
4294 offset += num_components[2] * gs_max_out_vertices;
4295 radeon_emit(ctx_cs, offset);
4296 if (max_stream >= 3)
4297 offset += num_components[3] * gs_max_out_vertices;
4298 radeon_set_context_reg(ctx_cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
4299
4300 radeon_set_context_reg_seq(ctx_cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
4301 radeon_emit(ctx_cs, num_components[0]);
4302 radeon_emit(ctx_cs, (max_stream >= 1) ? num_components[1] : 0);
4303 radeon_emit(ctx_cs, (max_stream >= 2) ? num_components[2] : 0);
4304 radeon_emit(ctx_cs, (max_stream >= 3) ? num_components[3] : 0);
4305
4306 uint32_t gs_num_invocations = gs->info.gs.invocations;
4307 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
4308 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
4309 S_028B90_ENABLE(gs_num_invocations > 0));
4310
4311 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
4312 gs_state->vgt_esgs_ring_itemsize);
4313
4314 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
4315
4316 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4317 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4318 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
4319 radeon_emit(cs, va >> 8);
4320 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
4321 } else {
4322 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
4323 radeon_emit(cs, va >> 8);
4324 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
4325 }
4326
4327 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
4328 radeon_emit(cs, gs->config.rsrc1);
4329 radeon_emit(cs, gs->config.rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
4330
4331 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
4332 radeon_set_context_reg(ctx_cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
4333 } else {
4334 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
4335 radeon_emit(cs, va >> 8);
4336 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
4337 radeon_emit(cs, gs->config.rsrc1);
4338 radeon_emit(cs, gs->config.rsrc2);
4339 }
4340
4341 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, pipeline->gs_copy_shader);
4342 }
4343
4344 static void
4345 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
4346 struct radeon_cmdbuf *cs,
4347 const struct radv_pipeline *pipeline)
4348 {
4349 struct radv_shader_variant *gs;
4350
4351 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
4352 if (!gs)
4353 return;
4354
4355 if (gs->info.is_ngg)
4356 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, gs);
4357 else
4358 radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs);
4359
4360 radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT,
4361 gs->info.gs.vertices_out);
4362 }
4363
4364 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade,
4365 bool explicit, bool float16)
4366 {
4367 uint32_t ps_input_cntl;
4368 if (offset <= AC_EXP_PARAM_OFFSET_31) {
4369 ps_input_cntl = S_028644_OFFSET(offset);
4370 if (flat_shade || explicit)
4371 ps_input_cntl |= S_028644_FLAT_SHADE(1);
4372 if (explicit) {
4373 /* Force parameter cache to be read in passthrough
4374 * mode.
4375 */
4376 ps_input_cntl |= S_028644_OFFSET(1 << 5);
4377 }
4378 if (float16) {
4379 ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) |
4380 S_028644_ATTR0_VALID(1);
4381 }
4382 } else {
4383 /* The input is a DEFAULT_VAL constant. */
4384 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
4385 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
4386 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
4387 ps_input_cntl = S_028644_OFFSET(0x20) |
4388 S_028644_DEFAULT_VAL(offset);
4389 }
4390 return ps_input_cntl;
4391 }
4392
4393 static void
4394 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
4395 const struct radv_pipeline *pipeline)
4396 {
4397 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4398 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
4399 uint32_t ps_input_cntl[32];
4400
4401 unsigned ps_offset = 0;
4402
4403 if (ps->info.ps.prim_id_input) {
4404 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
4405 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4406 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4407 ++ps_offset;
4408 }
4409 }
4410
4411 if (ps->info.ps.layer_input ||
4412 ps->info.needs_multiview_view_index) {
4413 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
4414 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4415 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4416 else
4417 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false, false);
4418 ++ps_offset;
4419 }
4420
4421 if (ps->info.ps.viewport_index_input) {
4422 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VIEWPORT];
4423 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4424 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4425 else
4426 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false, false);
4427 ++ps_offset;
4428 }
4429
4430 if (ps->info.ps.has_pcoord) {
4431 unsigned val;
4432 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4433 ps_input_cntl[ps_offset] = val;
4434 ps_offset++;
4435 }
4436
4437 if (ps->info.ps.num_input_clips_culls) {
4438 unsigned vs_offset;
4439
4440 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
4441 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4442 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false, false);
4443 ++ps_offset;
4444 }
4445
4446 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
4447 if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
4448 ps->info.ps.num_input_clips_culls > 4) {
4449 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false, false);
4450 ++ps_offset;
4451 }
4452 }
4453
4454 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.ps.input_mask; ++i) {
4455 unsigned vs_offset;
4456 bool flat_shade;
4457 bool explicit;
4458 bool float16;
4459 if (!(ps->info.ps.input_mask & (1u << i)))
4460 continue;
4461
4462 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
4463 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
4464 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
4465 ++ps_offset;
4466 continue;
4467 }
4468
4469 flat_shade = !!(ps->info.ps.flat_shaded_mask & (1u << ps_offset));
4470 explicit = !!(ps->info.ps.explicit_shaded_mask & (1u << ps_offset));
4471 float16 = !!(ps->info.ps.float16_shaded_mask & (1u << ps_offset));
4472
4473 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade, explicit, float16);
4474 ++ps_offset;
4475 }
4476
4477 if (ps_offset) {
4478 radeon_set_context_reg_seq(ctx_cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
4479 for (unsigned i = 0; i < ps_offset; i++) {
4480 radeon_emit(ctx_cs, ps_input_cntl[i]);
4481 }
4482 }
4483 }
4484
4485 static uint32_t
4486 radv_compute_db_shader_control(const struct radv_device *device,
4487 const struct radv_pipeline *pipeline,
4488 const struct radv_shader_variant *ps)
4489 {
4490 unsigned conservative_z_export = V_02880C_EXPORT_ANY_Z;
4491 unsigned z_order;
4492 if (ps->info.ps.early_fragment_test || !ps->info.ps.writes_memory)
4493 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
4494 else
4495 z_order = V_02880C_LATE_Z;
4496
4497 if (ps->info.ps.depth_layout == FRAG_DEPTH_LAYOUT_GREATER)
4498 conservative_z_export = V_02880C_EXPORT_GREATER_THAN_Z;
4499 else if (ps->info.ps.depth_layout == FRAG_DEPTH_LAYOUT_LESS)
4500 conservative_z_export = V_02880C_EXPORT_LESS_THAN_Z;
4501
4502 bool disable_rbplus = device->physical_device->rad_info.has_rbplus &&
4503 !device->physical_device->rad_info.rbplus_allowed;
4504
4505 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4506 * but this appears to break Project Cars (DXVK). See
4507 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4508 */
4509 bool mask_export_enable = ps->info.ps.writes_sample_mask;
4510
4511 return S_02880C_Z_EXPORT_ENABLE(ps->info.ps.writes_z) |
4512 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.ps.writes_stencil) |
4513 S_02880C_KILL_ENABLE(!!ps->info.ps.can_discard) |
4514 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
4515 S_02880C_CONSERVATIVE_Z_EXPORT(conservative_z_export) |
4516 S_02880C_Z_ORDER(z_order) |
4517 S_02880C_DEPTH_BEFORE_SHADER(ps->info.ps.early_fragment_test) |
4518 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps->info.ps.post_depth_coverage) |
4519 S_02880C_EXEC_ON_HIER_FAIL(ps->info.ps.writes_memory) |
4520 S_02880C_EXEC_ON_NOOP(ps->info.ps.writes_memory) |
4521 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
4522 }
4523
4524 static void
4525 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs,
4526 struct radeon_cmdbuf *cs,
4527 struct radv_pipeline *pipeline)
4528 {
4529 struct radv_shader_variant *ps;
4530 uint64_t va;
4531 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
4532
4533 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4534 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
4535
4536 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
4537 radeon_emit(cs, va >> 8);
4538 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
4539 radeon_emit(cs, ps->config.rsrc1);
4540 radeon_emit(cs, ps->config.rsrc2);
4541
4542 radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL,
4543 radv_compute_db_shader_control(pipeline->device,
4544 pipeline, ps));
4545
4546 radeon_set_context_reg(ctx_cs, R_0286CC_SPI_PS_INPUT_ENA,
4547 ps->config.spi_ps_input_ena);
4548
4549 radeon_set_context_reg(ctx_cs, R_0286D0_SPI_PS_INPUT_ADDR,
4550 ps->config.spi_ps_input_addr);
4551
4552 radeon_set_context_reg(ctx_cs, R_0286D8_SPI_PS_IN_CONTROL,
4553 S_0286D8_NUM_INTERP(ps->info.ps.num_interp) |
4554 S_0286D8_PS_W32_EN(ps->info.wave_size == 32));
4555
4556 radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
4557
4558 radeon_set_context_reg(ctx_cs, R_028710_SPI_SHADER_Z_FORMAT,
4559 ac_get_spi_shader_z_format(ps->info.ps.writes_z,
4560 ps->info.ps.writes_stencil,
4561 ps->info.ps.writes_sample_mask));
4562
4563 if (pipeline->device->dfsm_allowed) {
4564 /* optimise this? */
4565 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4566 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
4567 }
4568 }
4569
4570 static void
4571 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs,
4572 const struct radv_pipeline *pipeline)
4573 {
4574 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4575 pipeline->device->physical_device->rad_info.chip_class >= GFX10)
4576 return;
4577
4578 unsigned vtx_reuse_depth = 30;
4579 if (radv_pipeline_has_tess(pipeline) &&
4580 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
4581 vtx_reuse_depth = 14;
4582 }
4583 radeon_set_context_reg(ctx_cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
4584 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
4585 }
4586
4587 static void
4588 radv_pipeline_generate_vgt_shader_config(struct radeon_cmdbuf *ctx_cs,
4589 const struct radv_pipeline *pipeline)
4590 {
4591 uint32_t stages = 0;
4592 if (radv_pipeline_has_tess(pipeline)) {
4593 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
4594 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4595
4596 if (radv_pipeline_has_gs(pipeline))
4597 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
4598 S_028B54_GS_EN(1);
4599 else if (radv_pipeline_has_ngg(pipeline))
4600 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
4601 else
4602 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
4603 } else if (radv_pipeline_has_gs(pipeline)) {
4604 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
4605 S_028B54_GS_EN(1);
4606 } else if (radv_pipeline_has_ngg(pipeline)) {
4607 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
4608 }
4609
4610 if (radv_pipeline_has_ngg(pipeline)) {
4611 stages |= S_028B54_PRIMGEN_EN(1);
4612 if (pipeline->streamout_shader)
4613 stages |= S_028B54_NGG_WAVE_ID_EN(1);
4614 if (radv_pipeline_has_ngg_passthrough(pipeline))
4615 stages |= S_028B54_PRIMGEN_PASSTHRU_EN(1);
4616 } else if (radv_pipeline_has_gs(pipeline)) {
4617 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
4618 }
4619
4620 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
4621 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4622
4623 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4624 uint8_t hs_size = 64, gs_size = 64, vs_size = 64;
4625
4626 if (radv_pipeline_has_tess(pipeline))
4627 hs_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.wave_size;
4628
4629 if (pipeline->shaders[MESA_SHADER_GEOMETRY]) {
4630 vs_size = gs_size = pipeline->shaders[MESA_SHADER_GEOMETRY]->info.wave_size;
4631 if (pipeline->gs_copy_shader)
4632 vs_size = pipeline->gs_copy_shader->info.wave_size;
4633 } else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
4634 vs_size = pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.wave_size;
4635 else if (pipeline->shaders[MESA_SHADER_VERTEX])
4636 vs_size = pipeline->shaders[MESA_SHADER_VERTEX]->info.wave_size;
4637
4638 if (radv_pipeline_has_ngg(pipeline))
4639 gs_size = vs_size;
4640
4641 /* legacy GS only supports Wave64 */
4642 stages |= S_028B54_HS_W32_EN(hs_size == 32 ? 1 : 0) |
4643 S_028B54_GS_W32_EN(gs_size == 32 ? 1 : 0) |
4644 S_028B54_VS_W32_EN(vs_size == 32 ? 1 : 0);
4645 }
4646
4647 radeon_set_context_reg(ctx_cs, R_028B54_VGT_SHADER_STAGES_EN, stages);
4648 }
4649
4650 static void
4651 radv_pipeline_generate_cliprect_rule(struct radeon_cmdbuf *ctx_cs,
4652 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4653 {
4654 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
4655 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
4656 uint32_t cliprect_rule = 0;
4657
4658 if (!discard_rectangle_info) {
4659 cliprect_rule = 0xffff;
4660 } else {
4661 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
4662 /* Interpret i as a bitmask, and then set the bit in
4663 * the mask if that combination of rectangles in which
4664 * the pixel is contained should pass the cliprect
4665 * test.
4666 */
4667 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
4668
4669 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
4670 !relevant_subset)
4671 continue;
4672
4673 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
4674 relevant_subset)
4675 continue;
4676
4677 cliprect_rule |= 1u << i;
4678 }
4679 }
4680
4681 radeon_set_context_reg(ctx_cs, R_02820C_PA_SC_CLIPRECT_RULE, cliprect_rule);
4682 }
4683
4684 static void
4685 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf *ctx_cs,
4686 struct radv_pipeline *pipeline)
4687 {
4688 bool break_wave_at_eoi = false;
4689 unsigned primgroup_size;
4690 unsigned vertgroup_size = 256; /* 256 = disable vertex grouping */
4691
4692 if (radv_pipeline_has_tess(pipeline)) {
4693 primgroup_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
4694 } else if (radv_pipeline_has_gs(pipeline)) {
4695 const struct gfx9_gs_info *gs_state =
4696 &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs_ring_info;
4697 unsigned vgt_gs_onchip_cntl = gs_state->vgt_gs_onchip_cntl;
4698 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
4699 } else {
4700 primgroup_size = 128; /* recommended without a GS and tess */
4701 }
4702
4703 if (radv_pipeline_has_tess(pipeline)) {
4704 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4705 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4706 break_wave_at_eoi = true;
4707 }
4708
4709 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL,
4710 S_03096C_PRIM_GRP_SIZE(primgroup_size) |
4711 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
4712 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4713 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi));
4714 }
4715
4716 static void
4717 radv_pipeline_generate_vgt_gs_out(struct radeon_cmdbuf *ctx_cs,
4718 const struct radv_pipeline *pipeline,
4719 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4720 const struct radv_graphics_pipeline_create_info *extra)
4721 {
4722 uint32_t gs_out;
4723
4724 if (radv_pipeline_has_gs(pipeline)) {
4725 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
4726 } else if (radv_pipeline_has_tess(pipeline)) {
4727 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode) {
4728 gs_out = V_028A6C_OUTPRIM_TYPE_POINTLIST;
4729 } else {
4730 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.primitive_mode);
4731 }
4732 } else {
4733 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
4734 }
4735
4736 if (extra && extra->use_rectlist) {
4737 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4738 if (radv_pipeline_has_ngg(pipeline))
4739 gs_out = V_028A6C_VGT_OUT_RECT_V0;
4740 }
4741
4742 radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
4743 }
4744
4745 static void
4746 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
4747 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4748 const struct radv_graphics_pipeline_create_info *extra,
4749 const struct radv_blend_state *blend)
4750 {
4751 struct radeon_cmdbuf *ctx_cs = &pipeline->ctx_cs;
4752 struct radeon_cmdbuf *cs = &pipeline->cs;
4753
4754 cs->max_dw = 64;
4755 ctx_cs->max_dw = 256;
4756 cs->buf = malloc(4 * (cs->max_dw + ctx_cs->max_dw));
4757 ctx_cs->buf = cs->buf + cs->max_dw;
4758
4759 radv_pipeline_generate_depth_stencil_state(ctx_cs, pipeline, pCreateInfo, extra);
4760 radv_pipeline_generate_blend_state(ctx_cs, pipeline, blend);
4761 radv_pipeline_generate_raster_state(ctx_cs, pipeline, pCreateInfo);
4762 radv_pipeline_generate_multisample_state(ctx_cs, pipeline);
4763 radv_pipeline_generate_vgt_gs_mode(ctx_cs, pipeline);
4764 radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline);
4765
4766 if (radv_pipeline_has_tess(pipeline)) {
4767 radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline);
4768 radv_pipeline_generate_tess_state(ctx_cs, pipeline, pCreateInfo);
4769 }
4770
4771 radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline);
4772 radv_pipeline_generate_fragment_shader(ctx_cs, cs, pipeline);
4773 radv_pipeline_generate_ps_inputs(ctx_cs, pipeline);
4774 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline);
4775 radv_pipeline_generate_vgt_shader_config(ctx_cs, pipeline);
4776 radv_pipeline_generate_cliprect_rule(ctx_cs, pCreateInfo);
4777 radv_pipeline_generate_vgt_gs_out(ctx_cs, pipeline, pCreateInfo, extra);
4778
4779 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && !radv_pipeline_has_ngg(pipeline))
4780 gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline);
4781
4782 pipeline->ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4);
4783
4784 assert(ctx_cs->cdw <= ctx_cs->max_dw);
4785 assert(cs->cdw <= cs->max_dw);
4786 }
4787
4788 static void
4789 radv_pipeline_init_vertex_input_state(struct radv_pipeline *pipeline,
4790 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4791 {
4792 const VkPipelineVertexInputStateCreateInfo *vi_info =
4793 pCreateInfo->pVertexInputState;
4794
4795 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
4796 const VkVertexInputBindingDescription *desc =
4797 &vi_info->pVertexBindingDescriptions[i];
4798
4799 pipeline->binding_stride[desc->binding] = desc->stride;
4800 pipeline->num_vertex_bindings =
4801 MAX2(pipeline->num_vertex_bindings, desc->binding + 1);
4802 }
4803 }
4804
4805 static struct radv_shader_variant *
4806 radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline)
4807 {
4808 int i;
4809
4810 for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) {
4811 struct radv_shader_variant *shader =
4812 radv_get_shader(pipeline, i);
4813
4814 if (shader && shader->info.so.num_outputs > 0)
4815 return shader;
4816 }
4817
4818 return NULL;
4819 }
4820
4821 static void
4822 radv_pipeline_init_shader_stages_state(struct radv_pipeline *pipeline)
4823 {
4824 struct radv_device *device = pipeline->device;
4825
4826 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
4827 pipeline->user_data_0[i] =
4828 radv_pipeline_stage_to_user_data_0(pipeline, i,
4829 device->physical_device->rad_info.chip_class);
4830
4831 if (pipeline->shaders[i]) {
4832 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
4833 }
4834 }
4835
4836 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
4837 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
4838 if (loc->sgpr_idx != -1) {
4839 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
4840 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
4841 if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id)
4842 pipeline->graphics.vtx_emit_num = 3;
4843 else
4844 pipeline->graphics.vtx_emit_num = 2;
4845 }
4846 }
4847
4848 static VkResult
4849 radv_pipeline_init(struct radv_pipeline *pipeline,
4850 struct radv_device *device,
4851 struct radv_pipeline_cache *cache,
4852 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4853 const struct radv_graphics_pipeline_create_info *extra)
4854 {
4855 VkResult result;
4856
4857 pipeline->device = device;
4858 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
4859 assert(pipeline->layout);
4860
4861 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
4862
4863 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
4864 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
4865 radv_init_feedback(creation_feedback);
4866
4867 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
4868
4869 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
4870 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
4871 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
4872 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
4873 pStages[stage] = &pCreateInfo->pStages[i];
4874 if(creation_feedback)
4875 stage_feedbacks[stage] = &creation_feedback->pPipelineStageCreationFeedbacks[i];
4876 }
4877
4878 struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend);
4879
4880 result = radv_create_shaders(pipeline, device, cache, &key, pStages,
4881 pCreateInfo->flags, pipeline_feedback,
4882 stage_feedbacks);
4883 if (result != VK_SUCCESS)
4884 return result;
4885
4886 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
4887 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
4888 radv_pipeline_init_input_assembly_state(pipeline, pCreateInfo, extra);
4889 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo, extra);
4890 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
4891 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo);
4892
4893 /* Ensure that some export memory is always allocated, for two reasons:
4894 *
4895 * 1) Correctness: The hardware ignores the EXEC mask if no export
4896 * memory is allocated, so KILL and alpha test do not work correctly
4897 * without this.
4898 * 2) Performance: Every shader needs at least a NULL export, even when
4899 * it writes no color/depth output. The NULL export instruction
4900 * stalls without this setting.
4901 *
4902 * Don't add this to CB_SHADER_MASK.
4903 *
4904 * GFX10 supports pixel shaders without exports by setting both the
4905 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
4906 * instructions if any are present.
4907 */
4908 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4909 if ((pipeline->device->physical_device->rad_info.chip_class <= GFX9 ||
4910 ps->info.ps.can_discard) &&
4911 !blend.spi_shader_col_format) {
4912 if (!ps->info.ps.writes_z &&
4913 !ps->info.ps.writes_stencil &&
4914 !ps->info.ps.writes_sample_mask)
4915 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
4916 }
4917
4918 blend.cb_shader_mask = ps->info.ps.cb_shader_mask;
4919
4920 if (extra &&
4921 (extra->custom_blend_mode == V_028808_CB_ELIMINATE_FAST_CLEAR ||
4922 extra->custom_blend_mode == V_028808_CB_FMASK_DECOMPRESS ||
4923 extra->custom_blend_mode == V_028808_CB_DCC_DECOMPRESS ||
4924 extra->custom_blend_mode == V_028808_CB_RESOLVE)) {
4925 /* According to the CB spec states, CB_SHADER_MASK should be
4926 * set to enable writes to all four channels of MRT0.
4927 */
4928 blend.cb_shader_mask = 0xf;
4929 }
4930
4931 pipeline->graphics.col_format = blend.spi_shader_col_format;
4932 pipeline->graphics.cb_target_mask = blend.cb_target_mask;
4933
4934 if (radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
4935 struct radv_shader_variant *gs =
4936 pipeline->shaders[MESA_SHADER_GEOMETRY];
4937
4938 radv_pipeline_init_gs_ring_state(pipeline, &gs->info.gs_ring_info);
4939 }
4940
4941 if (radv_pipeline_has_tess(pipeline)) {
4942 pipeline->graphics.tess_patch_control_points =
4943 pCreateInfo->pTessellationState->patchControlPoints;
4944 }
4945
4946 radv_pipeline_init_vertex_input_state(pipeline, pCreateInfo);
4947 radv_pipeline_init_binning_state(pipeline, pCreateInfo, &blend);
4948 radv_pipeline_init_shader_stages_state(pipeline);
4949 radv_pipeline_init_scratch(device, pipeline);
4950
4951 /* Find the last vertex shader stage that eventually uses streamout. */
4952 pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline);
4953
4954 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend);
4955
4956 return result;
4957 }
4958
4959 VkResult
4960 radv_graphics_pipeline_create(
4961 VkDevice _device,
4962 VkPipelineCache _cache,
4963 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4964 const struct radv_graphics_pipeline_create_info *extra,
4965 const VkAllocationCallbacks *pAllocator,
4966 VkPipeline *pPipeline)
4967 {
4968 RADV_FROM_HANDLE(radv_device, device, _device);
4969 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
4970 struct radv_pipeline *pipeline;
4971 VkResult result;
4972
4973 pipeline = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8,
4974 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4975 if (pipeline == NULL)
4976 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4977
4978 vk_object_base_init(&device->vk, &pipeline->base,
4979 VK_OBJECT_TYPE_PIPELINE);
4980
4981 result = radv_pipeline_init(pipeline, device, cache,
4982 pCreateInfo, extra);
4983 if (result != VK_SUCCESS) {
4984 radv_pipeline_destroy(device, pipeline, pAllocator);
4985 return result;
4986 }
4987
4988 *pPipeline = radv_pipeline_to_handle(pipeline);
4989
4990 return VK_SUCCESS;
4991 }
4992
4993 VkResult radv_CreateGraphicsPipelines(
4994 VkDevice _device,
4995 VkPipelineCache pipelineCache,
4996 uint32_t count,
4997 const VkGraphicsPipelineCreateInfo* pCreateInfos,
4998 const VkAllocationCallbacks* pAllocator,
4999 VkPipeline* pPipelines)
5000 {
5001 VkResult result = VK_SUCCESS;
5002 unsigned i = 0;
5003
5004 for (; i < count; i++) {
5005 VkResult r;
5006 r = radv_graphics_pipeline_create(_device,
5007 pipelineCache,
5008 &pCreateInfos[i],
5009 NULL, pAllocator, &pPipelines[i]);
5010 if (r != VK_SUCCESS) {
5011 result = r;
5012 pPipelines[i] = VK_NULL_HANDLE;
5013
5014 if (pCreateInfos[i].flags & VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT)
5015 break;
5016 }
5017 }
5018
5019 for (; i < count; ++i)
5020 pPipelines[i] = VK_NULL_HANDLE;
5021
5022 return result;
5023 }
5024
5025 static void
5026 radv_pipeline_generate_hw_cs(struct radeon_cmdbuf *cs,
5027 const struct radv_pipeline *pipeline)
5028 {
5029 struct radv_shader_variant *shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5030 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
5031 struct radv_device *device = pipeline->device;
5032
5033 radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
5034 radeon_emit(cs, va >> 8);
5035 radeon_emit(cs, S_00B834_DATA(va >> 40));
5036
5037 radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
5038 radeon_emit(cs, shader->config.rsrc1);
5039 radeon_emit(cs, shader->config.rsrc2);
5040 if (device->physical_device->rad_info.chip_class >= GFX10) {
5041 radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, shader->config.rsrc3);
5042 }
5043 }
5044
5045 static void
5046 radv_pipeline_generate_compute_state(struct radeon_cmdbuf *cs,
5047 const struct radv_pipeline *pipeline)
5048 {
5049 struct radv_shader_variant *shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5050 struct radv_device *device = pipeline->device;
5051 unsigned threads_per_threadgroup;
5052 unsigned threadgroups_per_cu = 1;
5053 unsigned waves_per_threadgroup;
5054 unsigned max_waves_per_sh = 0;
5055
5056 /* Calculate best compute resource limits. */
5057 threads_per_threadgroup = shader->info.cs.block_size[0] *
5058 shader->info.cs.block_size[1] *
5059 shader->info.cs.block_size[2];
5060 waves_per_threadgroup = DIV_ROUND_UP(threads_per_threadgroup,
5061 shader->info.wave_size);
5062
5063 if (device->physical_device->rad_info.chip_class >= GFX10 &&
5064 waves_per_threadgroup == 1)
5065 threadgroups_per_cu = 2;
5066
5067 radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
5068 ac_get_compute_resource_limits(&device->physical_device->rad_info,
5069 waves_per_threadgroup,
5070 max_waves_per_sh,
5071 threadgroups_per_cu));
5072
5073 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5074 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(shader->info.cs.block_size[0]));
5075 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(shader->info.cs.block_size[1]));
5076 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(shader->info.cs.block_size[2]));
5077 }
5078
5079 static void
5080 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
5081 {
5082 struct radv_device *device = pipeline->device;
5083 struct radeon_cmdbuf *cs = &pipeline->cs;
5084
5085 cs->max_dw = device->physical_device->rad_info.chip_class >= GFX10 ? 19 : 16;
5086 cs->buf = malloc(cs->max_dw * 4);
5087
5088 radv_pipeline_generate_hw_cs(cs, pipeline);
5089 radv_pipeline_generate_compute_state(cs, pipeline);
5090
5091 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
5092 }
5093
5094 static struct radv_pipeline_key
5095 radv_generate_compute_pipeline_key(struct radv_pipeline *pipeline,
5096 const VkComputePipelineCreateInfo *pCreateInfo)
5097 {
5098 const VkPipelineShaderStageCreateInfo *stage = &pCreateInfo->stage;
5099 struct radv_pipeline_key key;
5100 memset(&key, 0, sizeof(key));
5101
5102 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
5103 key.optimisations_disabled = 1;
5104
5105 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT *subgroup_size =
5106 vk_find_struct_const(stage->pNext,
5107 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT);
5108
5109 if (subgroup_size) {
5110 assert(subgroup_size->requiredSubgroupSize == 32 ||
5111 subgroup_size->requiredSubgroupSize == 64);
5112 key.compute_subgroup_size = subgroup_size->requiredSubgroupSize;
5113 }
5114
5115 return key;
5116 }
5117
5118 static VkResult radv_compute_pipeline_create(
5119 VkDevice _device,
5120 VkPipelineCache _cache,
5121 const VkComputePipelineCreateInfo* pCreateInfo,
5122 const VkAllocationCallbacks* pAllocator,
5123 VkPipeline* pPipeline)
5124 {
5125 RADV_FROM_HANDLE(radv_device, device, _device);
5126 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
5127 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
5128 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
5129 struct radv_pipeline *pipeline;
5130 VkResult result;
5131
5132 pipeline = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8,
5133 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5134 if (pipeline == NULL)
5135 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5136
5137 vk_object_base_init(&device->vk, &pipeline->base,
5138 VK_OBJECT_TYPE_PIPELINE);
5139
5140 pipeline->device = device;
5141 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
5142 assert(pipeline->layout);
5143
5144 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
5145 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
5146 radv_init_feedback(creation_feedback);
5147
5148 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
5149 if (creation_feedback)
5150 stage_feedbacks[MESA_SHADER_COMPUTE] = &creation_feedback->pPipelineStageCreationFeedbacks[0];
5151
5152 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
5153
5154 struct radv_pipeline_key key =
5155 radv_generate_compute_pipeline_key(pipeline, pCreateInfo);
5156
5157 result = radv_create_shaders(pipeline, device, cache, &key, pStages,
5158 pCreateInfo->flags, pipeline_feedback,
5159 stage_feedbacks);
5160 if (result != VK_SUCCESS) {
5161 radv_pipeline_destroy(device, pipeline, pAllocator);
5162 return result;
5163 }
5164
5165 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
5166 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
5167 radv_pipeline_init_scratch(device, pipeline);
5168
5169 radv_compute_generate_pm4(pipeline);
5170
5171 *pPipeline = radv_pipeline_to_handle(pipeline);
5172
5173 return VK_SUCCESS;
5174 }
5175
5176 VkResult radv_CreateComputePipelines(
5177 VkDevice _device,
5178 VkPipelineCache pipelineCache,
5179 uint32_t count,
5180 const VkComputePipelineCreateInfo* pCreateInfos,
5181 const VkAllocationCallbacks* pAllocator,
5182 VkPipeline* pPipelines)
5183 {
5184 VkResult result = VK_SUCCESS;
5185
5186 unsigned i = 0;
5187 for (; i < count; i++) {
5188 VkResult r;
5189 r = radv_compute_pipeline_create(_device, pipelineCache,
5190 &pCreateInfos[i],
5191 pAllocator, &pPipelines[i]);
5192 if (r != VK_SUCCESS) {
5193 result = r;
5194 pPipelines[i] = VK_NULL_HANDLE;
5195
5196 if (pCreateInfos[i].flags & VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT)
5197 break;
5198 }
5199 }
5200
5201 for (; i < count; ++i)
5202 pPipelines[i] = VK_NULL_HANDLE;
5203
5204 return result;
5205 }
5206
5207
5208 static uint32_t radv_get_executable_count(const struct radv_pipeline *pipeline)
5209 {
5210 uint32_t ret = 0;
5211 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5212 if (!pipeline->shaders[i])
5213 continue;
5214
5215 if (i == MESA_SHADER_GEOMETRY &&
5216 !radv_pipeline_has_ngg(pipeline)) {
5217 ret += 2u;
5218 } else {
5219 ret += 1u;
5220 }
5221
5222 }
5223 return ret;
5224 }
5225
5226 static struct radv_shader_variant *
5227 radv_get_shader_from_executable_index(const struct radv_pipeline *pipeline, int index, gl_shader_stage *stage)
5228 {
5229 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5230 if (!pipeline->shaders[i])
5231 continue;
5232 if (!index) {
5233 *stage = i;
5234 return pipeline->shaders[i];
5235 }
5236
5237 --index;
5238
5239 if (i == MESA_SHADER_GEOMETRY &&
5240 !radv_pipeline_has_ngg(pipeline)) {
5241 if (!index) {
5242 *stage = i;
5243 return pipeline->gs_copy_shader;
5244 }
5245 --index;
5246 }
5247 }
5248
5249 *stage = -1;
5250 return NULL;
5251 }
5252
5253 /* Basically strlcpy (which does not exist on linux) specialized for
5254 * descriptions. */
5255 static void desc_copy(char *desc, const char *src) {
5256 int len = strlen(src);
5257 assert(len < VK_MAX_DESCRIPTION_SIZE);
5258 memcpy(desc, src, len);
5259 memset(desc + len, 0, VK_MAX_DESCRIPTION_SIZE - len);
5260 }
5261
5262 VkResult radv_GetPipelineExecutablePropertiesKHR(
5263 VkDevice _device,
5264 const VkPipelineInfoKHR* pPipelineInfo,
5265 uint32_t* pExecutableCount,
5266 VkPipelineExecutablePropertiesKHR* pProperties)
5267 {
5268 RADV_FROM_HANDLE(radv_pipeline, pipeline, pPipelineInfo->pipeline);
5269 const uint32_t total_count = radv_get_executable_count(pipeline);
5270
5271 if (!pProperties) {
5272 *pExecutableCount = total_count;
5273 return VK_SUCCESS;
5274 }
5275
5276 const uint32_t count = MIN2(total_count, *pExecutableCount);
5277 for (unsigned i = 0, executable_idx = 0;
5278 i < MESA_SHADER_STAGES && executable_idx < count; ++i) {
5279 if (!pipeline->shaders[i])
5280 continue;
5281 pProperties[executable_idx].stages = mesa_to_vk_shader_stage(i);
5282 const char *name = NULL;
5283 const char *description = NULL;
5284 switch(i) {
5285 case MESA_SHADER_VERTEX:
5286 name = "Vertex Shader";
5287 description = "Vulkan Vertex Shader";
5288 break;
5289 case MESA_SHADER_TESS_CTRL:
5290 if (!pipeline->shaders[MESA_SHADER_VERTEX]) {
5291 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5292 name = "Vertex + Tessellation Control Shaders";
5293 description = "Combined Vulkan Vertex and Tessellation Control Shaders";
5294 } else {
5295 name = "Tessellation Control Shader";
5296 description = "Vulkan Tessellation Control Shader";
5297 }
5298 break;
5299 case MESA_SHADER_TESS_EVAL:
5300 name = "Tessellation Evaluation Shader";
5301 description = "Vulkan Tessellation Evaluation Shader";
5302 break;
5303 case MESA_SHADER_GEOMETRY:
5304 if (radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
5305 pProperties[executable_idx].stages |= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT;
5306 name = "Tessellation Evaluation + Geometry Shaders";
5307 description = "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5308 } else if (!radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_VERTEX]) {
5309 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5310 name = "Vertex + Geometry Shader";
5311 description = "Combined Vulkan Vertex and Geometry Shaders";
5312 } else {
5313 name = "Geometry Shader";
5314 description = "Vulkan Geometry Shader";
5315 }
5316 break;
5317 case MESA_SHADER_FRAGMENT:
5318 name = "Fragment Shader";
5319 description = "Vulkan Fragment Shader";
5320 break;
5321 case MESA_SHADER_COMPUTE:
5322 name = "Compute Shader";
5323 description = "Vulkan Compute Shader";
5324 break;
5325 }
5326
5327 pProperties[executable_idx].subgroupSize = pipeline->shaders[i]->info.wave_size;
5328 desc_copy(pProperties[executable_idx].name, name);
5329 desc_copy(pProperties[executable_idx].description, description);
5330
5331 ++executable_idx;
5332 if (i == MESA_SHADER_GEOMETRY &&
5333 !radv_pipeline_has_ngg(pipeline)) {
5334 assert(pipeline->gs_copy_shader);
5335 if (executable_idx >= count)
5336 break;
5337
5338 pProperties[executable_idx].stages = VK_SHADER_STAGE_GEOMETRY_BIT;
5339 pProperties[executable_idx].subgroupSize = 64;
5340 desc_copy(pProperties[executable_idx].name, "GS Copy Shader");
5341 desc_copy(pProperties[executable_idx].description,
5342 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5343
5344 ++executable_idx;
5345 }
5346 }
5347
5348 VkResult result = *pExecutableCount < total_count ? VK_INCOMPLETE : VK_SUCCESS;
5349 *pExecutableCount = count;
5350 return result;
5351 }
5352
5353 VkResult radv_GetPipelineExecutableStatisticsKHR(
5354 VkDevice _device,
5355 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5356 uint32_t* pStatisticCount,
5357 VkPipelineExecutableStatisticKHR* pStatistics)
5358 {
5359 RADV_FROM_HANDLE(radv_device, device, _device);
5360 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5361 gl_shader_stage stage;
5362 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5363
5364 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
5365 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
5366 unsigned max_waves = radv_get_max_waves(device, shader, stage);
5367
5368 VkPipelineExecutableStatisticKHR *s = pStatistics;
5369 VkPipelineExecutableStatisticKHR *end = s + (pStatistics ? *pStatisticCount : 0);
5370 VkResult result = VK_SUCCESS;
5371
5372 if (s < end) {
5373 desc_copy(s->name, "SGPRs");
5374 desc_copy(s->description, "Number of SGPR registers allocated per subgroup");
5375 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5376 s->value.u64 = shader->config.num_sgprs;
5377 }
5378 ++s;
5379
5380 if (s < end) {
5381 desc_copy(s->name, "VGPRs");
5382 desc_copy(s->description, "Number of VGPR registers allocated per subgroup");
5383 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5384 s->value.u64 = shader->config.num_vgprs;
5385 }
5386 ++s;
5387
5388 if (s < end) {
5389 desc_copy(s->name, "Spilled SGPRs");
5390 desc_copy(s->description, "Number of SGPR registers spilled per subgroup");
5391 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5392 s->value.u64 = shader->config.spilled_sgprs;
5393 }
5394 ++s;
5395
5396 if (s < end) {
5397 desc_copy(s->name, "Spilled VGPRs");
5398 desc_copy(s->description, "Number of VGPR registers spilled per subgroup");
5399 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5400 s->value.u64 = shader->config.spilled_vgprs;
5401 }
5402 ++s;
5403
5404 if (s < end) {
5405 desc_copy(s->name, "PrivMem VGPRs");
5406 desc_copy(s->description, "Number of VGPRs stored in private memory per subgroup");
5407 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5408 s->value.u64 = shader->info.private_mem_vgprs;
5409 }
5410 ++s;
5411
5412 if (s < end) {
5413 desc_copy(s->name, "Code size");
5414 desc_copy(s->description, "Code size in bytes");
5415 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5416 s->value.u64 = shader->exec_size;
5417 }
5418 ++s;
5419
5420 if (s < end) {
5421 desc_copy(s->name, "LDS size");
5422 desc_copy(s->description, "LDS size in bytes per workgroup");
5423 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5424 s->value.u64 = shader->config.lds_size * lds_increment;
5425 }
5426 ++s;
5427
5428 if (s < end) {
5429 desc_copy(s->name, "Scratch size");
5430 desc_copy(s->description, "Private memory in bytes per subgroup");
5431 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5432 s->value.u64 = shader->config.scratch_bytes_per_wave;
5433 }
5434 ++s;
5435
5436 if (s < end) {
5437 desc_copy(s->name, "Subgroups per SIMD");
5438 desc_copy(s->description, "The maximum number of subgroups in flight on a SIMD unit");
5439 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5440 s->value.u64 = max_waves;
5441 }
5442 ++s;
5443
5444 if (shader->statistics) {
5445 for (unsigned i = 0; i < shader->statistics->count; i++) {
5446 struct radv_compiler_statistic_info *info = &shader->statistics->infos[i];
5447 uint32_t value = shader->statistics->values[i];
5448 if (s < end) {
5449 desc_copy(s->name, info->name);
5450 desc_copy(s->description, info->desc);
5451 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5452 s->value.u64 = value;
5453 }
5454 ++s;
5455 }
5456 }
5457
5458 if (!pStatistics)
5459 *pStatisticCount = s - pStatistics;
5460 else if (s > end) {
5461 *pStatisticCount = end - pStatistics;
5462 result = VK_INCOMPLETE;
5463 } else {
5464 *pStatisticCount = s - pStatistics;
5465 }
5466
5467 return result;
5468 }
5469
5470 static VkResult radv_copy_representation(void *data, size_t *data_size, const char *src)
5471 {
5472 size_t total_size = strlen(src) + 1;
5473
5474 if (!data) {
5475 *data_size = total_size;
5476 return VK_SUCCESS;
5477 }
5478
5479 size_t size = MIN2(total_size, *data_size);
5480
5481 memcpy(data, src, size);
5482 if (size)
5483 *((char*)data + size - 1) = 0;
5484 return size < total_size ? VK_INCOMPLETE : VK_SUCCESS;
5485 }
5486
5487 VkResult radv_GetPipelineExecutableInternalRepresentationsKHR(
5488 VkDevice device,
5489 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5490 uint32_t* pInternalRepresentationCount,
5491 VkPipelineExecutableInternalRepresentationKHR* pInternalRepresentations)
5492 {
5493 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5494 gl_shader_stage stage;
5495 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5496
5497 VkPipelineExecutableInternalRepresentationKHR *p = pInternalRepresentations;
5498 VkPipelineExecutableInternalRepresentationKHR *end = p + (pInternalRepresentations ? *pInternalRepresentationCount : 0);
5499 VkResult result = VK_SUCCESS;
5500 /* optimized NIR */
5501 if (p < end) {
5502 p->isText = true;
5503 desc_copy(p->name, "NIR Shader(s)");
5504 desc_copy(p->description, "The optimized NIR shader(s)");
5505 if (radv_copy_representation(p->pData, &p->dataSize, shader->nir_string) != VK_SUCCESS)
5506 result = VK_INCOMPLETE;
5507 }
5508 ++p;
5509
5510 /* backend IR */
5511 if (p < end) {
5512 p->isText = true;
5513 if (pipeline->device->physical_device->use_llvm) {
5514 desc_copy(p->name, "LLVM IR");
5515 desc_copy(p->description, "The LLVM IR after some optimizations");
5516 } else {
5517 desc_copy(p->name, "ACO IR");
5518 desc_copy(p->description, "The ACO IR after some optimizations");
5519 }
5520 if (radv_copy_representation(p->pData, &p->dataSize, shader->ir_string) != VK_SUCCESS)
5521 result = VK_INCOMPLETE;
5522 }
5523 ++p;
5524
5525 /* Disassembler */
5526 if (p < end) {
5527 p->isText = true;
5528 desc_copy(p->name, "Assembly");
5529 desc_copy(p->description, "Final Assembly");
5530 if (radv_copy_representation(p->pData, &p->dataSize, shader->disasm_string) != VK_SUCCESS)
5531 result = VK_INCOMPLETE;
5532 }
5533 ++p;
5534
5535 if (!pInternalRepresentations)
5536 *pInternalRepresentationCount = p - pInternalRepresentations;
5537 else if(p > end) {
5538 result = VK_INCOMPLETE;
5539 *pInternalRepresentationCount = end - pInternalRepresentations;
5540 } else {
5541 *pInternalRepresentationCount = p - pInternalRepresentations;
5542 }
5543
5544 return result;
5545 }