projects / mesa.git / blob
? search:
summary | shortlog | log | commit | commitdiff | tree
history | raw | HEAD
radv: emit PA_SC_LINE_CNTL as part of the rasterization state
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
33 #include "radv_cs.h"
34 #include "radv_shader.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
39 #include "vk_util.h"
40
41 #include "sid.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
48 #include "ac_shader_util.h"
49
50 struct radv_blend_state {
51 uint32_t blend_enable_4bit;
52 uint32_t need_src_alpha;
53
54 uint32_t cb_color_control;
55 uint32_t cb_target_mask;
56 uint32_t cb_target_enabled_4bit;
57 uint32_t sx_mrt_blend_opt[8];
58 uint32_t cb_blend_control[8];
59
60 uint32_t spi_shader_col_format;
61 uint32_t col_format_is_int8;
62 uint32_t col_format_is_int10;
63 uint32_t cb_shader_mask;
64 uint32_t db_alpha_to_mask;
65
66 uint32_t commutative_4bit;
67
68 bool single_cb_enable;
69 bool mrt0_is_dual_src;
70 };
71
72 struct radv_dsa_order_invariance {
73 /* Whether the final result in Z/S buffers is guaranteed to be
74 * invariant under changes to the order in which fragments arrive.
75 */
76 bool zs;
77
78 /* Whether the set of fragments that pass the combined Z/S test is
79 * guaranteed to be invariant under changes to the order in which
80 * fragments arrive.
81 */
82 bool pass_set;
83 };
84
85 struct radv_tessellation_state {
86 uint32_t ls_hs_config;
87 unsigned num_patches;
88 unsigned lds_size;
89 uint32_t tf_param;
90 };
91
92 static const VkPipelineMultisampleStateCreateInfo *
93 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
94 {
95 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
96 return pCreateInfo->pMultisampleState;
97 return NULL;
98 }
99
100 static const VkPipelineTessellationStateCreateInfo *
101 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
102 {
103 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
104 if (pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT ||
105 pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) {
106 return pCreateInfo->pTessellationState;
107 }
108 }
109 return NULL;
110 }
111
112 static const VkPipelineDepthStencilStateCreateInfo *
113 radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
114 {
115 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
116 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
117
118 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
119 subpass->depth_stencil_attachment)
120 return pCreateInfo->pDepthStencilState;
121 return NULL;
122 }
123
124 static const VkPipelineColorBlendStateCreateInfo *
125 radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
126 {
127 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
128 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
129
130 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
131 subpass->has_color_att)
132 return pCreateInfo->pColorBlendState;
133 return NULL;
134 }
135
136 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline)
137 {
138 struct radv_shader_variant *variant = NULL;
139 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
140 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
141 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
142 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
143 else if (pipeline->shaders[MESA_SHADER_VERTEX])
144 variant = pipeline->shaders[MESA_SHADER_VERTEX];
145 else
146 return false;
147 return variant->info.is_ngg;
148 }
149
150 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline *pipeline)
151 {
152 assert(radv_pipeline_has_ngg(pipeline));
153
154 struct radv_shader_variant *variant = NULL;
155 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
156 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
157 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
158 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
159 else if (pipeline->shaders[MESA_SHADER_VERTEX])
160 variant = pipeline->shaders[MESA_SHADER_VERTEX];
161 else
162 return false;
163 return variant->info.is_ngg_passthrough;
164 }
165
166 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline)
167 {
168 if (!radv_pipeline_has_gs(pipeline))
169 return false;
170
171 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
172 * On GFX10, it might be required in rare cases if it's not possible to
173 * enable NGG.
174 */
175 if (radv_pipeline_has_ngg(pipeline))
176 return false;
177
178 assert(pipeline->gs_copy_shader);
179 return true;
180 }
181
182 static void
183 radv_pipeline_destroy(struct radv_device *device,
184 struct radv_pipeline *pipeline,
185 const VkAllocationCallbacks* allocator)
186 {
187 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
188 if (pipeline->shaders[i])
189 radv_shader_variant_destroy(device, pipeline->shaders[i]);
190
191 if (pipeline->gs_copy_shader)
192 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
193
194 if(pipeline->cs.buf)
195 free(pipeline->cs.buf);
196
197 vk_object_base_finish(&pipeline->base);
198 vk_free2(&device->vk.alloc, allocator, pipeline);
199 }
200
201 void radv_DestroyPipeline(
202 VkDevice _device,
203 VkPipeline _pipeline,
204 const VkAllocationCallbacks* pAllocator)
205 {
206 RADV_FROM_HANDLE(radv_device, device, _device);
207 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
208
209 if (!_pipeline)
210 return;
211
212 radv_pipeline_destroy(device, pipeline, pAllocator);
213 }
214
215 static uint32_t get_hash_flags(struct radv_device *device)
216 {
217 uint32_t hash_flags = 0;
218
219 if (device->instance->debug_flags & RADV_DEBUG_NO_NGG)
220 hash_flags |= RADV_HASH_SHADER_NO_NGG;
221 if (device->physical_device->cs_wave_size == 32)
222 hash_flags |= RADV_HASH_SHADER_CS_WAVE32;
223 if (device->physical_device->ps_wave_size == 32)
224 hash_flags |= RADV_HASH_SHADER_PS_WAVE32;
225 if (device->physical_device->ge_wave_size == 32)
226 hash_flags |= RADV_HASH_SHADER_GE_WAVE32;
227 if (device->physical_device->use_llvm)
228 hash_flags |= RADV_HASH_SHADER_LLVM;
229 return hash_flags;
230 }
231
232 static VkResult
233 radv_pipeline_scratch_init(struct radv_device *device,
234 struct radv_pipeline *pipeline)
235 {
236 unsigned scratch_bytes_per_wave = 0;
237 unsigned max_waves = 0;
238 unsigned min_waves = 1;
239
240 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
241 if (pipeline->shaders[i] &&
242 pipeline->shaders[i]->config.scratch_bytes_per_wave) {
243 unsigned max_stage_waves = device->scratch_waves;
244
245 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
246 pipeline->shaders[i]->config.scratch_bytes_per_wave);
247
248 max_stage_waves = MIN2(max_stage_waves,
249 4 * device->physical_device->rad_info.num_good_compute_units *
250 (256 / pipeline->shaders[i]->config.num_vgprs));
251 max_waves = MAX2(max_waves, max_stage_waves);
252 }
253 }
254
255 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
256 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
257 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
258 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
259 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
260 }
261
262 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
263 pipeline->max_waves = max_waves;
264 return VK_SUCCESS;
265 }
266
267 static uint32_t si_translate_blend_logic_op(VkLogicOp op)
268 {
269 switch (op) {
270 case VK_LOGIC_OP_CLEAR:
271 return V_028808_ROP3_CLEAR;
272 case VK_LOGIC_OP_AND:
273 return V_028808_ROP3_AND;
274 case VK_LOGIC_OP_AND_REVERSE:
275 return V_028808_ROP3_AND_REVERSE;
276 case VK_LOGIC_OP_COPY:
277 return V_028808_ROP3_COPY;
278 case VK_LOGIC_OP_AND_INVERTED:
279 return V_028808_ROP3_AND_INVERTED;
280 case VK_LOGIC_OP_NO_OP:
281 return V_028808_ROP3_NO_OP;
282 case VK_LOGIC_OP_XOR:
283 return V_028808_ROP3_XOR;
284 case VK_LOGIC_OP_OR:
285 return V_028808_ROP3_OR;
286 case VK_LOGIC_OP_NOR:
287 return V_028808_ROP3_NOR;
288 case VK_LOGIC_OP_EQUIVALENT:
289 return V_028808_ROP3_EQUIVALENT;
290 case VK_LOGIC_OP_INVERT:
291 return V_028808_ROP3_INVERT;
292 case VK_LOGIC_OP_OR_REVERSE:
293 return V_028808_ROP3_OR_REVERSE;
294 case VK_LOGIC_OP_COPY_INVERTED:
295 return V_028808_ROP3_COPY_INVERTED;
296 case VK_LOGIC_OP_OR_INVERTED:
297 return V_028808_ROP3_OR_INVERTED;
298 case VK_LOGIC_OP_NAND:
299 return V_028808_ROP3_NAND;
300 case VK_LOGIC_OP_SET:
301 return V_028808_ROP3_SET;
302 default:
303 unreachable("Unhandled logic op");
304 }
305 }
306
307
308 static uint32_t si_translate_blend_function(VkBlendOp op)
309 {
310 switch (op) {
311 case VK_BLEND_OP_ADD:
312 return V_028780_COMB_DST_PLUS_SRC;
313 case VK_BLEND_OP_SUBTRACT:
314 return V_028780_COMB_SRC_MINUS_DST;
315 case VK_BLEND_OP_REVERSE_SUBTRACT:
316 return V_028780_COMB_DST_MINUS_SRC;
317 case VK_BLEND_OP_MIN:
318 return V_028780_COMB_MIN_DST_SRC;
319 case VK_BLEND_OP_MAX:
320 return V_028780_COMB_MAX_DST_SRC;
321 default:
322 return 0;
323 }
324 }
325
326 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
327 {
328 switch (factor) {
329 case VK_BLEND_FACTOR_ZERO:
330 return V_028780_BLEND_ZERO;
331 case VK_BLEND_FACTOR_ONE:
332 return V_028780_BLEND_ONE;
333 case VK_BLEND_FACTOR_SRC_COLOR:
334 return V_028780_BLEND_SRC_COLOR;
335 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
336 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
337 case VK_BLEND_FACTOR_DST_COLOR:
338 return V_028780_BLEND_DST_COLOR;
339 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
340 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
341 case VK_BLEND_FACTOR_SRC_ALPHA:
342 return V_028780_BLEND_SRC_ALPHA;
343 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
344 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
345 case VK_BLEND_FACTOR_DST_ALPHA:
346 return V_028780_BLEND_DST_ALPHA;
347 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
348 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
349 case VK_BLEND_FACTOR_CONSTANT_COLOR:
350 return V_028780_BLEND_CONSTANT_COLOR;
351 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
352 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
353 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
354 return V_028780_BLEND_CONSTANT_ALPHA;
355 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
356 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
357 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
358 return V_028780_BLEND_SRC_ALPHA_SATURATE;
359 case VK_BLEND_FACTOR_SRC1_COLOR:
360 return V_028780_BLEND_SRC1_COLOR;
361 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
362 return V_028780_BLEND_INV_SRC1_COLOR;
363 case VK_BLEND_FACTOR_SRC1_ALPHA:
364 return V_028780_BLEND_SRC1_ALPHA;
365 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
366 return V_028780_BLEND_INV_SRC1_ALPHA;
367 default:
368 return 0;
369 }
370 }
371
372 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
373 {
374 switch (op) {
375 case VK_BLEND_OP_ADD:
376 return V_028760_OPT_COMB_ADD;
377 case VK_BLEND_OP_SUBTRACT:
378 return V_028760_OPT_COMB_SUBTRACT;
379 case VK_BLEND_OP_REVERSE_SUBTRACT:
380 return V_028760_OPT_COMB_REVSUBTRACT;
381 case VK_BLEND_OP_MIN:
382 return V_028760_OPT_COMB_MIN;
383 case VK_BLEND_OP_MAX:
384 return V_028760_OPT_COMB_MAX;
385 default:
386 return V_028760_OPT_COMB_BLEND_DISABLED;
387 }
388 }
389
390 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
391 {
392 switch (factor) {
393 case VK_BLEND_FACTOR_ZERO:
394 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
395 case VK_BLEND_FACTOR_ONE:
396 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
397 case VK_BLEND_FACTOR_SRC_COLOR:
398 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
399 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
400 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
401 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
402 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
403 case VK_BLEND_FACTOR_SRC_ALPHA:
404 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
405 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
406 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
407 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
408 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
409 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
410 default:
411 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
412 }
413 }
414
415 /**
416 * Get rid of DST in the blend factors by commuting the operands:
417 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
418 */
419 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
420 unsigned *dst_factor, unsigned expected_dst,
421 unsigned replacement_src)
422 {
423 if (*src_factor == expected_dst &&
424 *dst_factor == VK_BLEND_FACTOR_ZERO) {
425 *src_factor = VK_BLEND_FACTOR_ZERO;
426 *dst_factor = replacement_src;
427
428 /* Commuting the operands requires reversing subtractions. */
429 if (*func == VK_BLEND_OP_SUBTRACT)
430 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
431 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
432 *func = VK_BLEND_OP_SUBTRACT;
433 }
434 }
435
436 static bool si_blend_factor_uses_dst(unsigned factor)
437 {
438 return factor == VK_BLEND_FACTOR_DST_COLOR ||
439 factor == VK_BLEND_FACTOR_DST_ALPHA ||
440 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
441 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
442 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
443 }
444
445 static bool is_dual_src(VkBlendFactor factor)
446 {
447 switch (factor) {
448 case VK_BLEND_FACTOR_SRC1_COLOR:
449 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
450 case VK_BLEND_FACTOR_SRC1_ALPHA:
451 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
452 return true;
453 default:
454 return false;
455 }
456 }
457
458 static unsigned radv_choose_spi_color_format(VkFormat vk_format,
459 bool blend_enable,
460 bool blend_need_alpha)
461 {
462 const struct vk_format_description *desc = vk_format_description(vk_format);
463 struct ac_spi_color_formats formats = {};
464 unsigned format, ntype, swap;
465
466 format = radv_translate_colorformat(vk_format);
467 ntype = radv_translate_color_numformat(vk_format, desc,
468 vk_format_get_first_non_void_channel(vk_format));
469 swap = radv_translate_colorswap(vk_format, false);
470
471 ac_choose_spi_color_formats(format, swap, ntype, false, &formats);
472
473 if (blend_enable && blend_need_alpha)
474 return formats.blend_alpha;
475 else if(blend_need_alpha)
476 return formats.alpha;
477 else if(blend_enable)
478 return formats.blend;
479 else
480 return formats.normal;
481 }
482
483 static bool
484 format_is_int8(VkFormat format)
485 {
486 const struct vk_format_description *desc = vk_format_description(format);
487 int channel = vk_format_get_first_non_void_channel(format);
488
489 return channel >= 0 && desc->channel[channel].pure_integer &&
490 desc->channel[channel].size == 8;
491 }
492
493 static bool
494 format_is_int10(VkFormat format)
495 {
496 const struct vk_format_description *desc = vk_format_description(format);
497
498 if (desc->nr_channels != 4)
499 return false;
500 for (unsigned i = 0; i < 4; i++) {
501 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
502 return true;
503 }
504 return false;
505 }
506
507 static void
508 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
509 const VkGraphicsPipelineCreateInfo *pCreateInfo,
510 struct radv_blend_state *blend)
511 {
512 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
513 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
514 unsigned col_format = 0, is_int8 = 0, is_int10 = 0;
515 unsigned num_targets;
516
517 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
518 unsigned cf;
519
520 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED ||
521 !(blend->cb_target_mask & (0xfu << (i * 4)))) {
522 cf = V_028714_SPI_SHADER_ZERO;
523 } else {
524 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
525 bool blend_enable =
526 blend->blend_enable_4bit & (0xfu << (i * 4));
527
528 cf = radv_choose_spi_color_format(attachment->format,
529 blend_enable,
530 blend->need_src_alpha & (1 << i));
531
532 if (format_is_int8(attachment->format))
533 is_int8 |= 1 << i;
534 if (format_is_int10(attachment->format))
535 is_int10 |= 1 << i;
536 }
537
538 col_format |= cf << (4 * i);
539 }
540
541 if (!(col_format & 0xf) && blend->need_src_alpha & (1 << 0)) {
542 /* When a subpass doesn't have any color attachments, write the
543 * alpha channel of MRT0 when alpha coverage is enabled because
544 * the depth attachment needs it.
545 */
546 col_format |= V_028714_SPI_SHADER_32_AR;
547 }
548
549 /* If the i-th target format is set, all previous target formats must
550 * be non-zero to avoid hangs.
551 */
552 num_targets = (util_last_bit(col_format) + 3) / 4;
553 for (unsigned i = 0; i < num_targets; i++) {
554 if (!(col_format & (0xf << (i * 4)))) {
555 col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
556 }
557 }
558
559 /* The output for dual source blending should have the same format as
560 * the first output.
561 */
562 if (blend->mrt0_is_dual_src)
563 col_format |= (col_format & 0xf) << 4;
564
565 blend->spi_shader_col_format = col_format;
566 blend->col_format_is_int8 = is_int8;
567 blend->col_format_is_int10 = is_int10;
568 }
569
570 /*
571 * Ordered so that for each i,
572 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
573 */
574 const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = {
575 VK_FORMAT_R32_SFLOAT,
576 VK_FORMAT_R32G32_SFLOAT,
577 VK_FORMAT_R8G8B8A8_UNORM,
578 VK_FORMAT_R16G16B16A16_UNORM,
579 VK_FORMAT_R16G16B16A16_SNORM,
580 VK_FORMAT_R16G16B16A16_UINT,
581 VK_FORMAT_R16G16B16A16_SINT,
582 VK_FORMAT_R32G32B32A32_SFLOAT,
583 VK_FORMAT_R8G8B8A8_UINT,
584 VK_FORMAT_R8G8B8A8_SINT,
585 VK_FORMAT_A2R10G10B10_UINT_PACK32,
586 VK_FORMAT_A2R10G10B10_SINT_PACK32,
587 };
588
589 unsigned radv_format_meta_fs_key(VkFormat format)
590 {
591 unsigned col_format = radv_choose_spi_color_format(format, false, false);
592
593 assert(col_format != V_028714_SPI_SHADER_32_AR);
594 if (col_format >= V_028714_SPI_SHADER_32_AR)
595 --col_format; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
596
597 --col_format; /* Skip V_028714_SPI_SHADER_ZERO */
598 bool is_int8 = format_is_int8(format);
599 bool is_int10 = format_is_int10(format);
600
601 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
602 }
603
604 static void
605 radv_blend_check_commutativity(struct radv_blend_state *blend,
606 VkBlendOp op, VkBlendFactor src,
607 VkBlendFactor dst, unsigned chanmask)
608 {
609 /* Src factor is allowed when it does not depend on Dst. */
610 static const uint32_t src_allowed =
611 (1u << VK_BLEND_FACTOR_ONE) |
612 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
613 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
614 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
615 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
616 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
617 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
618 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
619 (1u << VK_BLEND_FACTOR_ZERO) |
620 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
621 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
622 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
623 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
624 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
625 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
626
627 if (dst == VK_BLEND_FACTOR_ONE &&
628 (src_allowed & (1u << src))) {
629 /* Addition is commutative, but floating point addition isn't
630 * associative: subtle changes can be introduced via different
631 * rounding. Be conservative, only enable for min and max.
632 */
633 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
634 blend->commutative_4bit |= chanmask;
635 }
636 }
637
638 static struct radv_blend_state
639 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
640 const VkGraphicsPipelineCreateInfo *pCreateInfo,
641 const struct radv_graphics_pipeline_create_info *extra)
642 {
643 const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
644 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
645 struct radv_blend_state blend = {0};
646 unsigned mode = V_028808_CB_NORMAL;
647 int i;
648
649 if (extra && extra->custom_blend_mode) {
650 blend.single_cb_enable = true;
651 mode = extra->custom_blend_mode;
652 }
653
654 blend.cb_color_control = 0;
655 if (vkblend) {
656 if (vkblend->logicOpEnable)
657 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
658 else
659 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
660 }
661
662 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
663 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
664 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
665 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
666 S_028B70_OFFSET_ROUND(1);
667
668 if (vkms && vkms->alphaToCoverageEnable) {
669 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
670 blend.need_src_alpha |= 0x1;
671 }
672
673 blend.cb_target_mask = 0;
674 if (vkblend) {
675 for (i = 0; i < vkblend->attachmentCount; i++) {
676 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
677 unsigned blend_cntl = 0;
678 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
679 VkBlendOp eqRGB = att->colorBlendOp;
680 VkBlendFactor srcRGB = att->srcColorBlendFactor;
681 VkBlendFactor dstRGB = att->dstColorBlendFactor;
682 VkBlendOp eqA = att->alphaBlendOp;
683 VkBlendFactor srcA = att->srcAlphaBlendFactor;
684 VkBlendFactor dstA = att->dstAlphaBlendFactor;
685
686 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
687
688 if (!att->colorWriteMask)
689 continue;
690
691 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
692 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
693 if (!att->blendEnable) {
694 blend.cb_blend_control[i] = blend_cntl;
695 continue;
696 }
697
698 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
699 if (i == 0)
700 blend.mrt0_is_dual_src = true;
701
702 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
703 srcRGB = VK_BLEND_FACTOR_ONE;
704 dstRGB = VK_BLEND_FACTOR_ONE;
705 }
706 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
707 srcA = VK_BLEND_FACTOR_ONE;
708 dstA = VK_BLEND_FACTOR_ONE;
709 }
710
711 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
712 0x7 << (4 * i));
713 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
714 0x8 << (4 * i));
715
716 /* Blending optimizations for RB+.
717 * These transformations don't change the behavior.
718 *
719 * First, get rid of DST in the blend factors:
720 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
721 */
722 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
723 VK_BLEND_FACTOR_DST_COLOR,
724 VK_BLEND_FACTOR_SRC_COLOR);
725
726 si_blend_remove_dst(&eqA, &srcA, &dstA,
727 VK_BLEND_FACTOR_DST_COLOR,
728 VK_BLEND_FACTOR_SRC_COLOR);
729
730 si_blend_remove_dst(&eqA, &srcA, &dstA,
731 VK_BLEND_FACTOR_DST_ALPHA,
732 VK_BLEND_FACTOR_SRC_ALPHA);
733
734 /* Look up the ideal settings from tables. */
735 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
736 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
737 srcA_opt = si_translate_blend_opt_factor(srcA, true);
738 dstA_opt = si_translate_blend_opt_factor(dstA, true);
739
740 /* Handle interdependencies. */
741 if (si_blend_factor_uses_dst(srcRGB))
742 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
743 if (si_blend_factor_uses_dst(srcA))
744 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
745
746 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
747 (dstRGB == VK_BLEND_FACTOR_ZERO ||
748 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
749 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
750 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
751
752 /* Set the final value. */
753 blend.sx_mrt_blend_opt[i] =
754 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
755 S_028760_COLOR_DST_OPT(dstRGB_opt) |
756 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
757 S_028760_ALPHA_SRC_OPT(srcA_opt) |
758 S_028760_ALPHA_DST_OPT(dstA_opt) |
759 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
760 blend_cntl |= S_028780_ENABLE(1);
761
762 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
763 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
764 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
765 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
766 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
767 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
768 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
769 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
770 }
771 blend.cb_blend_control[i] = blend_cntl;
772
773 blend.blend_enable_4bit |= 0xfu << (i * 4);
774
775 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
776 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
777 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
778 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
779 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
780 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
781 blend.need_src_alpha |= 1 << i;
782 }
783 for (i = vkblend->attachmentCount; i < 8; i++) {
784 blend.cb_blend_control[i] = 0;
785 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
786 }
787 }
788
789 if (pipeline->device->physical_device->rad_info.has_rbplus) {
790 /* Disable RB+ blend optimizations for dual source blending. */
791 if (blend.mrt0_is_dual_src) {
792 for (i = 0; i < 8; i++) {
793 blend.sx_mrt_blend_opt[i] =
794 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
795 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
796 }
797 }
798
799 /* RB+ doesn't work with dual source blending, logic op and
800 * RESOLVE.
801 */
802 if (blend.mrt0_is_dual_src ||
803 (vkblend && vkblend->logicOpEnable) ||
804 mode == V_028808_CB_RESOLVE)
805 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
806 }
807
808 if (blend.cb_target_mask)
809 blend.cb_color_control |= S_028808_MODE(mode);
810 else
811 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
812
813 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
814 return blend;
815 }
816
817 static uint32_t si_translate_fill(VkPolygonMode func)
818 {
819 switch(func) {
820 case VK_POLYGON_MODE_FILL:
821 return V_028814_X_DRAW_TRIANGLES;
822 case VK_POLYGON_MODE_LINE:
823 return V_028814_X_DRAW_LINES;
824 case VK_POLYGON_MODE_POINT:
825 return V_028814_X_DRAW_POINTS;
826 default:
827 assert(0);
828 return V_028814_X_DRAW_POINTS;
829 }
830 }
831
832 static uint8_t radv_pipeline_get_ps_iter_samples(const VkGraphicsPipelineCreateInfo *pCreateInfo)
833 {
834 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
835 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
836 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
837 uint32_t ps_iter_samples = 1;
838 uint32_t num_samples;
839
840 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
841 *
842 * "If the VK_AMD_mixed_attachment_samples extension is enabled and the
843 * subpass uses color attachments, totalSamples is the number of
844 * samples of the color attachments. Otherwise, totalSamples is the
845 * value of VkPipelineMultisampleStateCreateInfo::rasterizationSamples
846 * specified at pipeline creation time."
847 */
848 if (subpass->has_color_att) {
849 num_samples = subpass->color_sample_count;
850 } else {
851 num_samples = vkms->rasterizationSamples;
852 }
853
854 if (vkms->sampleShadingEnable) {
855 ps_iter_samples = ceilf(vkms->minSampleShading * num_samples);
856 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
857 }
858 return ps_iter_samples;
859 }
860
861 static bool
862 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
863 {
864 return pCreateInfo->depthTestEnable &&
865 pCreateInfo->depthWriteEnable &&
866 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
867 }
868
869 static bool
870 radv_writes_stencil(const VkStencilOpState *state)
871 {
872 return state->writeMask &&
873 (state->failOp != VK_STENCIL_OP_KEEP ||
874 state->passOp != VK_STENCIL_OP_KEEP ||
875 state->depthFailOp != VK_STENCIL_OP_KEEP);
876 }
877
878 static bool
879 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
880 {
881 return pCreateInfo->stencilTestEnable &&
882 (radv_writes_stencil(&pCreateInfo->front) ||
883 radv_writes_stencil(&pCreateInfo->back));
884 }
885
886 static bool
887 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
888 {
889 return radv_is_depth_write_enabled(pCreateInfo) ||
890 radv_is_stencil_write_enabled(pCreateInfo);
891 }
892
893 static bool
894 radv_order_invariant_stencil_op(VkStencilOp op)
895 {
896 /* REPLACE is normally order invariant, except when the stencil
897 * reference value is written by the fragment shader. Tracking this
898 * interaction does not seem worth the effort, so be conservative.
899 */
900 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
901 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
902 op != VK_STENCIL_OP_REPLACE;
903 }
904
905 static bool
906 radv_order_invariant_stencil_state(const VkStencilOpState *state)
907 {
908 /* Compute whether, assuming Z writes are disabled, this stencil state
909 * is order invariant in the sense that the set of passing fragments as
910 * well as the final stencil buffer result does not depend on the order
911 * of fragments.
912 */
913 return !state->writeMask ||
914 /* The following assumes that Z writes are disabled. */
915 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
916 radv_order_invariant_stencil_op(state->passOp) &&
917 radv_order_invariant_stencil_op(state->depthFailOp)) ||
918 (state->compareOp == VK_COMPARE_OP_NEVER &&
919 radv_order_invariant_stencil_op(state->failOp));
920 }
921
922 static bool
923 radv_pipeline_has_dynamic_ds_states(const VkGraphicsPipelineCreateInfo *pCreateInfo)
924 {
925 VkDynamicState ds_states[] = {
926 VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT,
927 VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT,
928 VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT,
929 VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT,
930 VK_DYNAMIC_STATE_STENCIL_OP_EXT,
931 };
932
933 if (pCreateInfo->pDynamicState) {
934 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
935 for (uint32_t i = 0; i < count; i++) {
936 for (uint32_t j = 0; j < ARRAY_SIZE(ds_states); j++) {
937 if (pCreateInfo->pDynamicState->pDynamicStates[i] == ds_states[j])
938 return true;
939 }
940 }
941 }
942
943 return false;
944 }
945
946 static bool
947 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
948 struct radv_blend_state *blend,
949 const VkGraphicsPipelineCreateInfo *pCreateInfo)
950 {
951 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
952 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
953 const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
954 const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
955 unsigned colormask = blend->cb_target_enabled_4bit;
956
957 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
958 return false;
959
960 /* Be conservative if a logic operation is enabled with color buffers. */
961 if (colormask && vkblend && vkblend->logicOpEnable)
962 return false;
963
964 /* Be conservative if an extended dynamic depth/stencil state is
965 * enabled because the driver can't update out-of-order rasterization
966 * dynamically.
967 */
968 if (radv_pipeline_has_dynamic_ds_states(pCreateInfo))
969 return false;
970
971 /* Default depth/stencil invariance when no attachment is bound. */
972 struct radv_dsa_order_invariance dsa_order_invariant = {
973 .zs = true, .pass_set = true
974 };
975
976 if (vkds) {
977 struct radv_render_pass_attachment *attachment =
978 pass->attachments + subpass->depth_stencil_attachment->attachment;
979 bool has_stencil = vk_format_is_stencil(attachment->format);
980 struct radv_dsa_order_invariance order_invariance[2];
981 struct radv_shader_variant *ps =
982 pipeline->shaders[MESA_SHADER_FRAGMENT];
983
984 /* Compute depth/stencil order invariance in order to know if
985 * it's safe to enable out-of-order.
986 */
987 bool zfunc_is_ordered =
988 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
989 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
990 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
991 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
992 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
993
994 bool nozwrite_and_order_invariant_stencil =
995 !radv_is_ds_write_enabled(vkds) ||
996 (!radv_is_depth_write_enabled(vkds) &&
997 radv_order_invariant_stencil_state(&vkds->front) &&
998 radv_order_invariant_stencil_state(&vkds->back));
999
1000 order_invariance[1].zs =
1001 nozwrite_and_order_invariant_stencil ||
1002 (!radv_is_stencil_write_enabled(vkds) &&
1003 zfunc_is_ordered);
1004 order_invariance[0].zs =
1005 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
1006
1007 order_invariance[1].pass_set =
1008 nozwrite_and_order_invariant_stencil ||
1009 (!radv_is_stencil_write_enabled(vkds) &&
1010 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1011 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
1012 order_invariance[0].pass_set =
1013 !radv_is_depth_write_enabled(vkds) ||
1014 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1015 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
1016
1017 dsa_order_invariant = order_invariance[has_stencil];
1018 if (!dsa_order_invariant.zs)
1019 return false;
1020
1021 /* The set of PS invocations is always order invariant,
1022 * except when early Z/S tests are requested.
1023 */
1024 if (ps &&
1025 ps->info.ps.writes_memory &&
1026 ps->info.ps.early_fragment_test &&
1027 !dsa_order_invariant.pass_set)
1028 return false;
1029
1030 /* Determine if out-of-order rasterization should be disabled
1031 * when occlusion queries are used.
1032 */
1033 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
1034 !dsa_order_invariant.pass_set;
1035 }
1036
1037 /* No color buffers are enabled for writing. */
1038 if (!colormask)
1039 return true;
1040
1041 unsigned blendmask = colormask & blend->blend_enable_4bit;
1042
1043 if (blendmask) {
1044 /* Only commutative blending. */
1045 if (blendmask & ~blend->commutative_4bit)
1046 return false;
1047
1048 if (!dsa_order_invariant.pass_set)
1049 return false;
1050 }
1051
1052 if (colormask & ~blendmask)
1053 return false;
1054
1055 return true;
1056 }
1057
1058 static void
1059 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1060 struct radv_blend_state *blend,
1061 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1062 {
1063 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
1064 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1065 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1066 bool out_of_order_rast = false;
1067 int ps_iter_samples = 1;
1068 uint32_t mask = 0xffff;
1069
1070 if (vkms) {
1071 ms->num_samples = vkms->rasterizationSamples;
1072
1073 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1074 *
1075 * "Sample shading is enabled for a graphics pipeline:
1076 *
1077 * - If the interface of the fragment shader entry point of the
1078 * graphics pipeline includes an input variable decorated
1079 * with SampleId or SamplePosition. In this case
1080 * minSampleShadingFactor takes the value 1.0.
1081 * - Else if the sampleShadingEnable member of the
1082 * VkPipelineMultisampleStateCreateInfo structure specified
1083 * when creating the graphics pipeline is set to VK_TRUE. In
1084 * this case minSampleShadingFactor takes the value of
1085 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1086 *
1087 * Otherwise, sample shading is considered disabled."
1088 */
1089 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.force_persample) {
1090 ps_iter_samples = ms->num_samples;
1091 } else {
1092 ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
1093 }
1094 } else {
1095 ms->num_samples = 1;
1096 }
1097
1098 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1099 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1100 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1101 /* Out-of-order rasterization is explicitly enabled by the
1102 * application.
1103 */
1104 out_of_order_rast = true;
1105 } else {
1106 /* Determine if the driver can enable out-of-order
1107 * rasterization internally.
1108 */
1109 out_of_order_rast =
1110 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1111 }
1112
1113 ms->pa_sc_aa_config = 0;
1114 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1115 S_028804_INCOHERENT_EQAA_READS(1) |
1116 S_028804_INTERPOLATE_COMP_Z(1) |
1117 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1118 ms->pa_sc_mode_cntl_1 =
1119 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1120 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1121 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
1122 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1123 /* always 1: */
1124 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1125 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1126 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1127 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1128 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1129 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1130 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1131 S_028A48_VPORT_SCISSOR_ENABLE(1);
1132
1133 const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line =
1134 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1135 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
1136 if (rast_line) {
1137 ms->pa_sc_mode_cntl_0 |= S_028A48_LINE_STIPPLE_ENABLE(rast_line->stippledLineEnable);
1138 if (rast_line->lineRasterizationMode == VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT) {
1139 /* From the Vulkan spec 1.1.129:
1140 *
1141 * "When VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT lines
1142 * are being rasterized, sample locations may all be
1143 * treated as being at the pixel center (this may
1144 * affect attribute and depth interpolation)."
1145 */
1146 ms->num_samples = 1;
1147 }
1148 }
1149
1150 if (ms->num_samples > 1) {
1151 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1152 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1153 uint32_t z_samples = subpass->depth_stencil_attachment ? subpass->depth_sample_count : ms->num_samples;
1154 unsigned log_samples = util_logbase2(ms->num_samples);
1155 unsigned log_z_samples = util_logbase2(z_samples);
1156 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1157 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1158 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
1159 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1160 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1161 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1162 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1163 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) |
1164 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples) | /* CM_R_028BE0_PA_SC_AA_CONFIG */
1165 S_028BE0_COVERED_CENTROID_IS_CENTER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3);
1166 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1167 if (ps_iter_samples > 1)
1168 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1169 }
1170
1171 if (vkms && vkms->pSampleMask) {
1172 mask = vkms->pSampleMask[0] & 0xffff;
1173 }
1174
1175 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1176 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1177 }
1178
1179 static bool
1180 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1181 {
1182 switch (topology) {
1183 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1184 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1185 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1186 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1187 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1188 return false;
1189 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1190 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1191 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1192 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1193 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1194 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1195 return true;
1196 default:
1197 unreachable("unhandled primitive type");
1198 }
1199 }
1200
1201 static uint32_t
1202 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1203 {
1204 switch (gl_prim) {
1205 case 0: /* GL_POINTS */
1206 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1207 case 1: /* GL_LINES */
1208 case 3: /* GL_LINE_STRIP */
1209 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1210 case 0x8E7A: /* GL_ISOLINES */
1211 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1212
1213 case 4: /* GL_TRIANGLES */
1214 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1215 case 5: /* GL_TRIANGLE_STRIP */
1216 case 7: /* GL_QUADS */
1217 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1218 default:
1219 assert(0);
1220 return 0;
1221 }
1222 }
1223
1224 static uint32_t
1225 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1226 {
1227 switch (topology) {
1228 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1229 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1230 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1231 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1232 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1233 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1234 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1235 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1236 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1237 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1238 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1239 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1240 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1241 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1242 default:
1243 assert(0);
1244 return 0;
1245 }
1246 }
1247
1248 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1249 {
1250 switch(state) {
1251 case VK_DYNAMIC_STATE_VIEWPORT:
1252 case VK_DYNAMIC_STATE_VIEWPORT_WITH_COUNT_EXT:
1253 return RADV_DYNAMIC_VIEWPORT;
1254 case VK_DYNAMIC_STATE_SCISSOR:
1255 case VK_DYNAMIC_STATE_SCISSOR_WITH_COUNT_EXT:
1256 return RADV_DYNAMIC_SCISSOR;
1257 case VK_DYNAMIC_STATE_LINE_WIDTH:
1258 return RADV_DYNAMIC_LINE_WIDTH;
1259 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1260 return RADV_DYNAMIC_DEPTH_BIAS;
1261 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1262 return RADV_DYNAMIC_BLEND_CONSTANTS;
1263 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1264 return RADV_DYNAMIC_DEPTH_BOUNDS;
1265 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1266 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1267 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1268 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1269 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1270 return RADV_DYNAMIC_STENCIL_REFERENCE;
1271 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1272 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1273 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
1274 return RADV_DYNAMIC_SAMPLE_LOCATIONS;
1275 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT:
1276 return RADV_DYNAMIC_LINE_STIPPLE;
1277 case VK_DYNAMIC_STATE_CULL_MODE_EXT:
1278 return RADV_DYNAMIC_CULL_MODE;
1279 case VK_DYNAMIC_STATE_FRONT_FACE_EXT:
1280 return RADV_DYNAMIC_FRONT_FACE;
1281 case VK_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY_EXT:
1282 return RADV_DYNAMIC_PRIMITIVE_TOPOLOGY;
1283 case VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT:
1284 return RADV_DYNAMIC_DEPTH_TEST_ENABLE;
1285 case VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT:
1286 return RADV_DYNAMIC_DEPTH_WRITE_ENABLE;
1287 case VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT:
1288 return RADV_DYNAMIC_DEPTH_COMPARE_OP;
1289 case VK_DYNAMIC_STATE_DEPTH_BOUNDS_TEST_ENABLE_EXT:
1290 return RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE;
1291 case VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT:
1292 return RADV_DYNAMIC_STENCIL_TEST_ENABLE;
1293 case VK_DYNAMIC_STATE_STENCIL_OP_EXT:
1294 return RADV_DYNAMIC_STENCIL_OP;
1295 case VK_DYNAMIC_STATE_VERTEX_INPUT_BINDING_STRIDE_EXT:
1296 return RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE;
1297 default:
1298 unreachable("Unhandled dynamic state");
1299 }
1300 }
1301
1302 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1303 {
1304 uint32_t states = RADV_DYNAMIC_ALL;
1305
1306 /* If rasterization is disabled we do not care about any of the
1307 * dynamic states, since they are all rasterization related only,
1308 * except primitive topology and vertex binding stride.
1309 */
1310 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1311 return RADV_DYNAMIC_PRIMITIVE_TOPOLOGY |
1312 RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE;
1313
1314 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1315 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1316
1317 if (!pCreateInfo->pDepthStencilState ||
1318 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1319 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1320
1321 if (!pCreateInfo->pDepthStencilState ||
1322 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1323 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1324 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1325 RADV_DYNAMIC_STENCIL_REFERENCE);
1326
1327 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1328 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1329
1330 if (!pCreateInfo->pMultisampleState ||
1331 !vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1332 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT))
1333 states &= ~RADV_DYNAMIC_SAMPLE_LOCATIONS;
1334
1335 if (!pCreateInfo->pRasterizationState ||
1336 !vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1337 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT))
1338 states &= ~RADV_DYNAMIC_LINE_STIPPLE;
1339
1340 /* TODO: blend constants & line width. */
1341
1342 return states;
1343 }
1344
1345
1346 static void
1347 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1348 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1349 const struct radv_graphics_pipeline_create_info *extra)
1350 {
1351 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1352 uint32_t states = needed_states;
1353 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1354 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1355
1356 pipeline->dynamic_state = default_dynamic_state;
1357 pipeline->graphics.needed_dynamic_state = needed_states;
1358
1359 if (pCreateInfo->pDynamicState) {
1360 /* Remove all of the states that are marked as dynamic */
1361 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1362 for (uint32_t s = 0; s < count; s++)
1363 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1364 }
1365
1366 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1367
1368 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1369 assert(pCreateInfo->pViewportState);
1370
1371 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1372 if (states & RADV_DYNAMIC_VIEWPORT) {
1373 typed_memcpy(dynamic->viewport.viewports,
1374 pCreateInfo->pViewportState->pViewports,
1375 pCreateInfo->pViewportState->viewportCount);
1376 }
1377 }
1378
1379 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1380 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1381 if (states & RADV_DYNAMIC_SCISSOR) {
1382 typed_memcpy(dynamic->scissor.scissors,
1383 pCreateInfo->pViewportState->pScissors,
1384 pCreateInfo->pViewportState->scissorCount);
1385 }
1386 }
1387
1388 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1389 assert(pCreateInfo->pRasterizationState);
1390 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1391 }
1392
1393 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1394 assert(pCreateInfo->pRasterizationState);
1395 dynamic->depth_bias.bias =
1396 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1397 dynamic->depth_bias.clamp =
1398 pCreateInfo->pRasterizationState->depthBiasClamp;
1399 dynamic->depth_bias.slope =
1400 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1401 }
1402
1403 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1404 *
1405 * pColorBlendState is [...] NULL if the pipeline has rasterization
1406 * disabled or if the subpass of the render pass the pipeline is
1407 * created against does not use any color attachments.
1408 */
1409 if (subpass->has_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1410 assert(pCreateInfo->pColorBlendState);
1411 typed_memcpy(dynamic->blend_constants,
1412 pCreateInfo->pColorBlendState->blendConstants, 4);
1413 }
1414
1415 if (states & RADV_DYNAMIC_CULL_MODE) {
1416 dynamic->cull_mode =
1417 pCreateInfo->pRasterizationState->cullMode;
1418 }
1419
1420 if (states & RADV_DYNAMIC_FRONT_FACE) {
1421 dynamic->front_face =
1422 pCreateInfo->pRasterizationState->frontFace;
1423 }
1424
1425 if (states & RADV_DYNAMIC_PRIMITIVE_TOPOLOGY) {
1426 dynamic->primitive_topology =
1427 si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
1428 if (extra && extra->use_rectlist) {
1429 dynamic->primitive_topology = V_008958_DI_PT_RECTLIST;
1430 }
1431 }
1432
1433 /* If there is no depthstencil attachment, then don't read
1434 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1435 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1436 * no need to override the depthstencil defaults in
1437 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1438 *
1439 * Section 9.2 of the Vulkan 1.0.15 spec says:
1440 *
1441 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1442 * disabled or if the subpass of the render pass the pipeline is created
1443 * against does not use a depth/stencil attachment.
1444 */
1445 if (needed_states && subpass->depth_stencil_attachment) {
1446 assert(pCreateInfo->pDepthStencilState);
1447
1448 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1449 dynamic->depth_bounds.min =
1450 pCreateInfo->pDepthStencilState->minDepthBounds;
1451 dynamic->depth_bounds.max =
1452 pCreateInfo->pDepthStencilState->maxDepthBounds;
1453 }
1454
1455 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1456 dynamic->stencil_compare_mask.front =
1457 pCreateInfo->pDepthStencilState->front.compareMask;
1458 dynamic->stencil_compare_mask.back =
1459 pCreateInfo->pDepthStencilState->back.compareMask;
1460 }
1461
1462 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1463 dynamic->stencil_write_mask.front =
1464 pCreateInfo->pDepthStencilState->front.writeMask;
1465 dynamic->stencil_write_mask.back =
1466 pCreateInfo->pDepthStencilState->back.writeMask;
1467 }
1468
1469 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1470 dynamic->stencil_reference.front =
1471 pCreateInfo->pDepthStencilState->front.reference;
1472 dynamic->stencil_reference.back =
1473 pCreateInfo->pDepthStencilState->back.reference;
1474 }
1475
1476 if (states & RADV_DYNAMIC_DEPTH_TEST_ENABLE) {
1477 dynamic->depth_test_enable =
1478 pCreateInfo->pDepthStencilState->depthTestEnable;
1479 }
1480
1481 if (states & RADV_DYNAMIC_DEPTH_WRITE_ENABLE) {
1482 dynamic->depth_write_enable =
1483 pCreateInfo->pDepthStencilState->depthWriteEnable;
1484 }
1485
1486 if (states & RADV_DYNAMIC_DEPTH_COMPARE_OP) {
1487 dynamic->depth_compare_op =
1488 pCreateInfo->pDepthStencilState->depthCompareOp;
1489 }
1490
1491 if (states & RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE) {
1492 dynamic->depth_bounds_test_enable =
1493 pCreateInfo->pDepthStencilState->depthBoundsTestEnable;
1494 }
1495
1496 if (states & RADV_DYNAMIC_STENCIL_TEST_ENABLE) {
1497 dynamic->stencil_test_enable =
1498 pCreateInfo->pDepthStencilState->stencilTestEnable;
1499 }
1500
1501 if (states & RADV_DYNAMIC_STENCIL_OP) {
1502 dynamic->stencil_op.front.compare_op =
1503 pCreateInfo->pDepthStencilState->front.compareOp;
1504 dynamic->stencil_op.front.fail_op =
1505 pCreateInfo->pDepthStencilState->front.failOp;
1506 dynamic->stencil_op.front.pass_op =
1507 pCreateInfo->pDepthStencilState->front.passOp;
1508 dynamic->stencil_op.front.depth_fail_op =
1509 pCreateInfo->pDepthStencilState->front.depthFailOp;
1510
1511 dynamic->stencil_op.back.compare_op =
1512 pCreateInfo->pDepthStencilState->back.compareOp;
1513 dynamic->stencil_op.back.fail_op =
1514 pCreateInfo->pDepthStencilState->back.failOp;
1515 dynamic->stencil_op.back.pass_op =
1516 pCreateInfo->pDepthStencilState->back.passOp;
1517 dynamic->stencil_op.back.depth_fail_op =
1518 pCreateInfo->pDepthStencilState->back.depthFailOp;
1519 }
1520 }
1521
1522 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1523 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1524 if (needed_states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1525 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1526 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1527 typed_memcpy(dynamic->discard_rectangle.rectangles,
1528 discard_rectangle_info->pDiscardRectangles,
1529 discard_rectangle_info->discardRectangleCount);
1530 }
1531 }
1532
1533 if (needed_states & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
1534 const VkPipelineSampleLocationsStateCreateInfoEXT *sample_location_info =
1535 vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1536 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1537 /* If sampleLocationsEnable is VK_FALSE, the default sample
1538 * locations are used and the values specified in
1539 * sampleLocationsInfo are ignored.
1540 */
1541 if (sample_location_info->sampleLocationsEnable) {
1542 const VkSampleLocationsInfoEXT *pSampleLocationsInfo =
1543 &sample_location_info->sampleLocationsInfo;
1544
1545 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
1546
1547 dynamic->sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
1548 dynamic->sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
1549 dynamic->sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
1550 typed_memcpy(&dynamic->sample_location.locations[0],
1551 pSampleLocationsInfo->pSampleLocations,
1552 pSampleLocationsInfo->sampleLocationsCount);
1553 }
1554 }
1555
1556 const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line_info =
1557 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1558 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
1559 if (needed_states & RADV_DYNAMIC_LINE_STIPPLE) {
1560 dynamic->line_stipple.factor = rast_line_info->lineStippleFactor;
1561 dynamic->line_stipple.pattern = rast_line_info->lineStipplePattern;
1562 }
1563
1564 if (!(states & RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE))
1565 pipeline->graphics.uses_dynamic_stride = true;
1566
1567 pipeline->dynamic_state.mask = states;
1568 }
1569
1570 static void
1571 gfx9_get_gs_info(const struct radv_pipeline_key *key,
1572 const struct radv_pipeline *pipeline,
1573 nir_shader **nir,
1574 struct radv_shader_info *infos,
1575 struct gfx9_gs_info *out)
1576 {
1577 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1578 struct radv_es_output_info *es_info;
1579 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1580 es_info = nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1581 else
1582 es_info = nir[MESA_SHADER_TESS_CTRL] ?
1583 &infos[MESA_SHADER_TESS_EVAL].tes.es_info :
1584 &infos[MESA_SHADER_VERTEX].vs.es_info;
1585
1586 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1587 bool uses_adjacency;
1588 switch(key->topology) {
1589 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1590 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1591 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1592 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1593 uses_adjacency = true;
1594 break;
1595 default:
1596 uses_adjacency = false;
1597 break;
1598 }
1599
1600 /* All these are in dwords: */
1601 /* We can't allow using the whole LDS, because GS waves compete with
1602 * other shader stages for LDS space. */
1603 const unsigned max_lds_size = 8 * 1024;
1604 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1605 unsigned esgs_lds_size;
1606
1607 /* All these are per subgroup: */
1608 const unsigned max_out_prims = 32 * 1024;
1609 const unsigned max_es_verts = 255;
1610 const unsigned ideal_gs_prims = 64;
1611 unsigned max_gs_prims, gs_prims;
1612 unsigned min_es_verts, es_verts, worst_case_es_verts;
1613
1614 if (uses_adjacency || gs_num_invocations > 1)
1615 max_gs_prims = 127 / gs_num_invocations;
1616 else
1617 max_gs_prims = 255;
1618
1619 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1620 * Make sure we don't go over the maximum value.
1621 */
1622 if (gs_info->gs.vertices_out > 0) {
1623 max_gs_prims = MIN2(max_gs_prims,
1624 max_out_prims /
1625 (gs_info->gs.vertices_out * gs_num_invocations));
1626 }
1627 assert(max_gs_prims > 0);
1628
1629 /* If the primitive has adjacency, halve the number of vertices
1630 * that will be reused in multiple primitives.
1631 */
1632 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1633
1634 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1635 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1636
1637 /* Compute ESGS LDS size based on the worst case number of ES vertices
1638 * needed to create the target number of GS prims per subgroup.
1639 */
1640 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1641
1642 /* If total LDS usage is too big, refactor partitions based on ratio
1643 * of ESGS item sizes.
1644 */
1645 if (esgs_lds_size > max_lds_size) {
1646 /* Our target GS Prims Per Subgroup was too large. Calculate
1647 * the maximum number of GS Prims Per Subgroup that will fit
1648 * into LDS, capped by the maximum that the hardware can support.
1649 */
1650 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1651 max_gs_prims);
1652 assert(gs_prims > 0);
1653 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1654 max_es_verts);
1655
1656 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1657 assert(esgs_lds_size <= max_lds_size);
1658 }
1659
1660 /* Now calculate remaining ESGS information. */
1661 if (esgs_lds_size)
1662 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1663 else
1664 es_verts = max_es_verts;
1665
1666 /* Vertices for adjacency primitives are not always reused, so restore
1667 * it for ES_VERTS_PER_SUBGRP.
1668 */
1669 min_es_verts = gs_info->gs.vertices_in;
1670
1671 /* For normal primitives, the VGT only checks if they are past the ES
1672 * verts per subgroup after allocating a full GS primitive and if they
1673 * are, kick off a new subgroup. But if those additional ES verts are
1674 * unique (e.g. not reused) we need to make sure there is enough LDS
1675 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1676 */
1677 es_verts -= min_es_verts - 1;
1678
1679 uint32_t es_verts_per_subgroup = es_verts;
1680 uint32_t gs_prims_per_subgroup = gs_prims;
1681 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1682 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1683 out->lds_size = align(esgs_lds_size, 128) / 128;
1684 out->vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1685 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1686 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1687 out->vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1688 out->vgt_esgs_ring_itemsize = esgs_itemsize;
1689 assert(max_prims_per_subgroup <= max_out_prims);
1690 }
1691
1692 static void clamp_gsprims_to_esverts(unsigned *max_gsprims, unsigned max_esverts,
1693 unsigned min_verts_per_prim, bool use_adjacency)
1694 {
1695 unsigned max_reuse = max_esverts - min_verts_per_prim;
1696 if (use_adjacency)
1697 max_reuse /= 2;
1698 *max_gsprims = MIN2(*max_gsprims, 1 + max_reuse);
1699 }
1700
1701 static unsigned
1702 radv_get_num_input_vertices(nir_shader **nir)
1703 {
1704 if (nir[MESA_SHADER_GEOMETRY]) {
1705 nir_shader *gs = nir[MESA_SHADER_GEOMETRY];
1706
1707 return gs->info.gs.vertices_in;
1708 }
1709
1710 if (nir[MESA_SHADER_TESS_CTRL]) {
1711 nir_shader *tes = nir[MESA_SHADER_TESS_EVAL];
1712
1713 if (tes->info.tess.point_mode)
1714 return 1;
1715 if (tes->info.tess.primitive_mode == GL_ISOLINES)
1716 return 2;
1717 return 3;
1718 }
1719
1720 return 3;
1721 }
1722
1723 static void
1724 gfx10_get_ngg_info(const struct radv_pipeline_key *key,
1725 struct radv_pipeline *pipeline,
1726 nir_shader **nir,
1727 struct radv_shader_info *infos,
1728 struct gfx10_ngg_info *ngg)
1729 {
1730 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1731 struct radv_es_output_info *es_info =
1732 nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1733 unsigned gs_type = nir[MESA_SHADER_GEOMETRY] ? MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX;
1734 unsigned max_verts_per_prim = radv_get_num_input_vertices(nir);
1735 unsigned min_verts_per_prim =
1736 gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1;
1737 unsigned gs_num_invocations = nir[MESA_SHADER_GEOMETRY] ? MAX2(gs_info->gs.invocations, 1) : 1;
1738 bool uses_adjacency;
1739 switch(key->topology) {
1740 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1741 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1742 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1743 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1744 uses_adjacency = true;
1745 break;
1746 default:
1747 uses_adjacency = false;
1748 break;
1749 }
1750
1751 /* All these are in dwords: */
1752 /* We can't allow using the whole LDS, because GS waves compete with
1753 * other shader stages for LDS space.
1754 *
1755 * TODO: We should really take the shader's internal LDS use into
1756 * account. The linker will fail if the size is greater than
1757 * 8K dwords.
1758 */
1759 const unsigned max_lds_size = 8 * 1024 - 768;
1760 const unsigned target_lds_size = max_lds_size;
1761 unsigned esvert_lds_size = 0;
1762 unsigned gsprim_lds_size = 0;
1763
1764 /* All these are per subgroup: */
1765 bool max_vert_out_per_gs_instance = false;
1766 unsigned max_esverts_base = 256;
1767 unsigned max_gsprims_base = 128; /* default prim group size clamp */
1768
1769 /* Hardware has the following non-natural restrictions on the value
1770 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1771 * the draw:
1772 * - at most 252 for any line input primitive type
1773 * - at most 251 for any quad input primitive type
1774 * - at most 251 for triangle strips with adjacency (this happens to
1775 * be the natural limit for triangle *lists* with adjacency)
1776 */
1777 max_esverts_base = MIN2(max_esverts_base, 251 + max_verts_per_prim - 1);
1778
1779 if (gs_type == MESA_SHADER_GEOMETRY) {
1780 unsigned max_out_verts_per_gsprim =
1781 gs_info->gs.vertices_out * gs_num_invocations;
1782
1783 if (max_out_verts_per_gsprim <= 256) {
1784 if (max_out_verts_per_gsprim) {
1785 max_gsprims_base = MIN2(max_gsprims_base,
1786 256 / max_out_verts_per_gsprim);
1787 }
1788 } else {
1789 /* Use special multi-cycling mode in which each GS
1790 * instance gets its own subgroup. Does not work with
1791 * tessellation. */
1792 max_vert_out_per_gs_instance = true;
1793 max_gsprims_base = 1;
1794 max_out_verts_per_gsprim = gs_info->gs.vertices_out;
1795 }
1796
1797 esvert_lds_size = es_info->esgs_itemsize / 4;
1798 gsprim_lds_size = (gs_info->gs.gsvs_vertex_size / 4 + 1) * max_out_verts_per_gsprim;
1799 } else {
1800 /* VS and TES. */
1801 /* LDS size for passing data from GS to ES. */
1802 struct radv_streamout_info *so_info = nir[MESA_SHADER_TESS_CTRL]
1803 ? &infos[MESA_SHADER_TESS_EVAL].so
1804 : &infos[MESA_SHADER_VERTEX].so;
1805
1806 if (so_info->num_outputs)
1807 esvert_lds_size = 4 * so_info->num_outputs + 1;
1808
1809 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1810 * corresponding to the ES thread of the provoking vertex. All
1811 * ES threads load and export PrimitiveID for their thread.
1812 */
1813 if (!nir[MESA_SHADER_TESS_CTRL] &&
1814 infos[MESA_SHADER_VERTEX].vs.outinfo.export_prim_id)
1815 esvert_lds_size = MAX2(esvert_lds_size, 1);
1816 }
1817
1818 unsigned max_gsprims = max_gsprims_base;
1819 unsigned max_esverts = max_esverts_base;
1820
1821 if (esvert_lds_size)
1822 max_esverts = MIN2(max_esverts, target_lds_size / esvert_lds_size);
1823 if (gsprim_lds_size)
1824 max_gsprims = MIN2(max_gsprims, target_lds_size / gsprim_lds_size);
1825
1826 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1827 clamp_gsprims_to_esverts(&max_gsprims, max_esverts, min_verts_per_prim, uses_adjacency);
1828 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1829
1830 if (esvert_lds_size || gsprim_lds_size) {
1831 /* Now that we have a rough proportionality between esverts
1832 * and gsprims based on the primitive type, scale both of them
1833 * down simultaneously based on required LDS space.
1834 *
1835 * We could be smarter about this if we knew how much vertex
1836 * reuse to expect.
1837 */
1838 unsigned lds_total = max_esverts * esvert_lds_size +
1839 max_gsprims * gsprim_lds_size;
1840 if (lds_total > target_lds_size) {
1841 max_esverts = max_esverts * target_lds_size / lds_total;
1842 max_gsprims = max_gsprims * target_lds_size / lds_total;
1843
1844 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1845 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1846 min_verts_per_prim, uses_adjacency);
1847 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1848 }
1849 }
1850
1851 /* Round up towards full wave sizes for better ALU utilization. */
1852 if (!max_vert_out_per_gs_instance) {
1853 unsigned orig_max_esverts;
1854 unsigned orig_max_gsprims;
1855 unsigned wavesize;
1856
1857 if (gs_type == MESA_SHADER_GEOMETRY) {
1858 wavesize = gs_info->wave_size;
1859 } else {
1860 wavesize = nir[MESA_SHADER_TESS_CTRL]
1861 ? infos[MESA_SHADER_TESS_EVAL].wave_size
1862 : infos[MESA_SHADER_VERTEX].wave_size;
1863 }
1864
1865 do {
1866 orig_max_esverts = max_esverts;
1867 orig_max_gsprims = max_gsprims;
1868
1869 max_esverts = align(max_esverts, wavesize);
1870 max_esverts = MIN2(max_esverts, max_esverts_base);
1871 if (esvert_lds_size)
1872 max_esverts = MIN2(max_esverts,
1873 (max_lds_size - max_gsprims * gsprim_lds_size) /
1874 esvert_lds_size);
1875 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1876
1877 max_gsprims = align(max_gsprims, wavesize);
1878 max_gsprims = MIN2(max_gsprims, max_gsprims_base);
1879 if (gsprim_lds_size)
1880 max_gsprims = MIN2(max_gsprims,
1881 (max_lds_size - max_esverts * esvert_lds_size) /
1882 gsprim_lds_size);
1883 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1884 min_verts_per_prim, uses_adjacency);
1885 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1886 } while (orig_max_esverts != max_esverts || orig_max_gsprims != max_gsprims);
1887 }
1888
1889 /* Hardware restriction: minimum value of max_esverts */
1890 max_esverts = MAX2(max_esverts, 23 + max_verts_per_prim);
1891
1892 unsigned max_out_vertices =
1893 max_vert_out_per_gs_instance ? gs_info->gs.vertices_out :
1894 gs_type == MESA_SHADER_GEOMETRY ?
1895 max_gsprims * gs_num_invocations * gs_info->gs.vertices_out :
1896 max_esverts;
1897 assert(max_out_vertices <= 256);
1898
1899 unsigned prim_amp_factor = 1;
1900 if (gs_type == MESA_SHADER_GEOMETRY) {
1901 /* Number of output primitives per GS input primitive after
1902 * GS instancing. */
1903 prim_amp_factor = gs_info->gs.vertices_out;
1904 }
1905
1906 /* The GE only checks against the maximum number of ES verts after
1907 * allocating a full GS primitive. So we need to ensure that whenever
1908 * this check passes, there is enough space for a full primitive without
1909 * vertex reuse.
1910 */
1911 ngg->hw_max_esverts = max_esverts - max_verts_per_prim + 1;
1912 ngg->max_gsprims = max_gsprims;
1913 ngg->max_out_verts = max_out_vertices;
1914 ngg->prim_amp_factor = prim_amp_factor;
1915 ngg->max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
1916 ngg->ngg_emit_size = max_gsprims * gsprim_lds_size;
1917 ngg->esgs_ring_size = 4 * max_esverts * esvert_lds_size;
1918
1919 if (gs_type == MESA_SHADER_GEOMETRY) {
1920 ngg->vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
1921 } else {
1922 ngg->vgt_esgs_ring_itemsize = 1;
1923 }
1924
1925 pipeline->graphics.esgs_ring_size = ngg->esgs_ring_size;
1926
1927 assert(ngg->hw_max_esverts >= 24); /* HW limitation */
1928 }
1929
1930 static void
1931 calculate_gs_ring_sizes(struct radv_pipeline *pipeline,
1932 const struct gfx9_gs_info *gs)
1933 {
1934 struct radv_device *device = pipeline->device;
1935 unsigned num_se = device->physical_device->rad_info.max_se;
1936 unsigned wave_size = 64;
1937 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1938 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1939 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1940 */
1941 unsigned gs_vertex_reuse =
1942 (device->physical_device->rad_info.chip_class >= GFX8 ? 32 : 16) * num_se;
1943 unsigned alignment = 256 * num_se;
1944 /* The maximum size is 63.999 MB per SE. */
1945 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1946 struct radv_shader_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1947
1948 /* Calculate the minimum size. */
1949 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1950 wave_size, alignment);
1951 /* These are recommended sizes, not minimum sizes. */
1952 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1953 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1954 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1955 gs_info->gs.max_gsvs_emit_size;
1956
1957 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1958 esgs_ring_size = align(esgs_ring_size, alignment);
1959 gsvs_ring_size = align(gsvs_ring_size, alignment);
1960
1961 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
1962 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1963
1964 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1965 }
1966
1967 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1968 unsigned *lds_size)
1969 {
1970 /* If tessellation is all offchip and on-chip GS isn't used, this
1971 * workaround is not needed.
1972 */
1973 return;
1974
1975 /* SPI barrier management bug:
1976 * Make sure we have at least 4k of LDS in use to avoid the bug.
1977 * It applies to workgroup sizes of more than one wavefront.
1978 */
1979 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1980 device->physical_device->rad_info.family == CHIP_KABINI)
1981 *lds_size = MAX2(*lds_size, 8);
1982 }
1983
1984 struct radv_shader_variant *
1985 radv_get_shader(struct radv_pipeline *pipeline,
1986 gl_shader_stage stage)
1987 {
1988 if (stage == MESA_SHADER_VERTEX) {
1989 if (pipeline->shaders[MESA_SHADER_VERTEX])
1990 return pipeline->shaders[MESA_SHADER_VERTEX];
1991 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1992 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1993 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1994 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1995 } else if (stage == MESA_SHADER_TESS_EVAL) {
1996 if (!radv_pipeline_has_tess(pipeline))
1997 return NULL;
1998 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1999 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
2000 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
2001 return pipeline->shaders[MESA_SHADER_GEOMETRY];
2002 }
2003 return pipeline->shaders[stage];
2004 }
2005
2006 static struct radv_tessellation_state
2007 calculate_tess_state(struct radv_pipeline *pipeline,
2008 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2009 {
2010 unsigned num_tcs_input_cp;
2011 unsigned num_tcs_output_cp;
2012 unsigned lds_size;
2013 unsigned num_patches;
2014 struct radv_tessellation_state tess = {0};
2015
2016 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
2017 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
2018 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2019
2020 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
2021
2022 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
2023 assert(lds_size <= 65536);
2024 lds_size = align(lds_size, 512) / 512;
2025 } else {
2026 assert(lds_size <= 32768);
2027 lds_size = align(lds_size, 256) / 256;
2028 }
2029 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
2030
2031 tess.lds_size = lds_size;
2032
2033 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
2034 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
2035 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
2036 tess.num_patches = num_patches;
2037
2038 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
2039 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
2040
2041 switch (tes->info.tes.primitive_mode) {
2042 case GL_TRIANGLES:
2043 type = V_028B6C_TESS_TRIANGLE;
2044 break;
2045 case GL_QUADS:
2046 type = V_028B6C_TESS_QUAD;
2047 break;
2048 case GL_ISOLINES:
2049 type = V_028B6C_TESS_ISOLINE;
2050 break;
2051 }
2052
2053 switch (tes->info.tes.spacing) {
2054 case TESS_SPACING_EQUAL:
2055 partitioning = V_028B6C_PART_INTEGER;
2056 break;
2057 case TESS_SPACING_FRACTIONAL_ODD:
2058 partitioning = V_028B6C_PART_FRAC_ODD;
2059 break;
2060 case TESS_SPACING_FRACTIONAL_EVEN:
2061 partitioning = V_028B6C_PART_FRAC_EVEN;
2062 break;
2063 default:
2064 break;
2065 }
2066
2067 bool ccw = tes->info.tes.ccw;
2068 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_origin_state =
2069 vk_find_struct_const(pCreateInfo->pTessellationState,
2070 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
2071
2072 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT)
2073 ccw = !ccw;
2074
2075 if (tes->info.tes.point_mode)
2076 topology = V_028B6C_OUTPUT_POINT;
2077 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
2078 topology = V_028B6C_OUTPUT_LINE;
2079 else if (ccw)
2080 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2081 else
2082 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2083
2084 if (pipeline->device->physical_device->rad_info.has_distributed_tess) {
2085 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
2086 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
2087 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
2088 else
2089 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
2090 } else
2091 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
2092
2093 tess.tf_param = S_028B6C_TYPE(type) |
2094 S_028B6C_PARTITIONING(partitioning) |
2095 S_028B6C_TOPOLOGY(topology) |
2096 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
2097
2098 return tess;
2099 }
2100
2101 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
2102 {
2103 if (radv_pipeline_has_gs(pipeline))
2104 if (radv_pipeline_has_ngg(pipeline))
2105 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
2106 else
2107 return &pipeline->gs_copy_shader->info.vs.outinfo;
2108 else if (radv_pipeline_has_tess(pipeline))
2109 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
2110 else
2111 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
2112 }
2113
2114 static void
2115 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
2116 {
2117 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
2118 int shader_count = 0;
2119
2120 if(shaders[MESA_SHADER_FRAGMENT]) {
2121 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
2122 }
2123 if(shaders[MESA_SHADER_GEOMETRY]) {
2124 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
2125 }
2126 if(shaders[MESA_SHADER_TESS_EVAL]) {
2127 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
2128 }
2129 if(shaders[MESA_SHADER_TESS_CTRL]) {
2130 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
2131 }
2132 if(shaders[MESA_SHADER_VERTEX]) {
2133 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
2134 }
2135
2136 if (shader_count > 1) {
2137 unsigned first = ordered_shaders[shader_count - 1]->info.stage;
2138 unsigned last = ordered_shaders[0]->info.stage;
2139
2140 if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
2141 ordered_shaders[1]->info.has_transform_feedback_varyings)
2142 nir_link_xfb_varyings(ordered_shaders[1], ordered_shaders[0]);
2143
2144 for (int i = 0; i < shader_count; ++i) {
2145 nir_variable_mode mask = 0;
2146
2147 if (ordered_shaders[i]->info.stage != first)
2148 mask = mask | nir_var_shader_in;
2149
2150 if (ordered_shaders[i]->info.stage != last)
2151 mask = mask | nir_var_shader_out;
2152
2153 nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
2154 radv_optimize_nir(ordered_shaders[i], false, false);
2155 }
2156 }
2157
2158 for (int i = 1; i < shader_count; ++i) {
2159 nir_lower_io_arrays_to_elements(ordered_shaders[i],
2160 ordered_shaders[i - 1]);
2161
2162 if (nir_link_opt_varyings(ordered_shaders[i],
2163 ordered_shaders[i - 1]))
2164 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2165
2166 nir_remove_dead_variables(ordered_shaders[i],
2167 nir_var_shader_out, NULL);
2168 nir_remove_dead_variables(ordered_shaders[i - 1],
2169 nir_var_shader_in, NULL);
2170
2171 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
2172 ordered_shaders[i - 1]);
2173
2174 nir_compact_varyings(ordered_shaders[i],
2175 ordered_shaders[i - 1], true);
2176
2177 if (progress) {
2178 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
2179 ac_lower_indirect_derefs(ordered_shaders[i],
2180 pipeline->device->physical_device->rad_info.chip_class);
2181 }
2182 radv_optimize_nir(ordered_shaders[i], false, false);
2183
2184 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
2185 ac_lower_indirect_derefs(ordered_shaders[i - 1],
2186 pipeline->device->physical_device->rad_info.chip_class);
2187 }
2188 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2189 }
2190 }
2191 }
2192
2193 static void
2194 radv_set_linked_driver_locations(struct radv_pipeline *pipeline, nir_shader **shaders,
2195 struct radv_shader_info infos[MESA_SHADER_STAGES])
2196 {
2197 bool has_tess = shaders[MESA_SHADER_TESS_CTRL];
2198 bool has_gs = shaders[MESA_SHADER_GEOMETRY];
2199
2200 if (!has_tess && !has_gs)
2201 return;
2202
2203 unsigned vs_info_idx = MESA_SHADER_VERTEX;
2204 unsigned tes_info_idx = MESA_SHADER_TESS_EVAL;
2205
2206 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2207 /* These are merged into the next stage */
2208 vs_info_idx = has_tess ? MESA_SHADER_TESS_CTRL : MESA_SHADER_GEOMETRY;
2209 tes_info_idx = has_gs ? MESA_SHADER_GEOMETRY : MESA_SHADER_TESS_EVAL;
2210 }
2211
2212 if (has_tess) {
2213 nir_linked_io_var_info vs2tcs =
2214 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_VERTEX], shaders[MESA_SHADER_TESS_CTRL]);
2215 nir_linked_io_var_info tcs2tes =
2216 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_TESS_CTRL], shaders[MESA_SHADER_TESS_EVAL]);
2217
2218 infos[vs_info_idx].vs.num_linked_outputs = vs2tcs.num_linked_io_vars;
2219 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_inputs = vs2tcs.num_linked_io_vars;
2220 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_outputs = tcs2tes.num_linked_io_vars;
2221 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_patch_outputs = tcs2tes.num_linked_patch_io_vars;
2222 infos[tes_info_idx].tes.num_linked_inputs = tcs2tes.num_linked_io_vars;
2223 infos[tes_info_idx].tes.num_linked_patch_inputs = tcs2tes.num_linked_patch_io_vars;
2224
2225 if (has_gs) {
2226 nir_linked_io_var_info tes2gs =
2227 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_TESS_EVAL], shaders[MESA_SHADER_GEOMETRY]);
2228
2229 infos[tes_info_idx].tes.num_linked_outputs = tes2gs.num_linked_io_vars;
2230 infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = tes2gs.num_linked_io_vars;
2231 }
2232 } else if (has_gs) {
2233 nir_linked_io_var_info vs2gs =
2234 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_VERTEX], shaders[MESA_SHADER_GEOMETRY]);
2235
2236 infos[vs_info_idx].vs.num_linked_outputs = vs2gs.num_linked_io_vars;
2237 infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = vs2gs.num_linked_io_vars;
2238 }
2239 }
2240
2241 static uint32_t
2242 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo *input_state,
2243 uint32_t attrib_binding)
2244 {
2245 for (uint32_t i = 0; i < input_state->vertexBindingDescriptionCount; i++) {
2246 const VkVertexInputBindingDescription *input_binding =
2247 &input_state->pVertexBindingDescriptions[i];
2248
2249 if (input_binding->binding == attrib_binding)
2250 return input_binding->stride;
2251 }
2252
2253 return 0;
2254 }
2255
2256 static struct radv_pipeline_key
2257 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
2258 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2259 const struct radv_blend_state *blend,
2260 bool has_view_index)
2261 {
2262 const VkPipelineVertexInputStateCreateInfo *input_state =
2263 pCreateInfo->pVertexInputState;
2264 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
2265 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
2266
2267 struct radv_pipeline_key key;
2268 memset(&key, 0, sizeof(key));
2269
2270 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
2271 key.optimisations_disabled = 1;
2272
2273 key.has_multiview_view_index = has_view_index;
2274
2275 uint32_t binding_input_rate = 0;
2276 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
2277 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
2278 if (input_state->pVertexBindingDescriptions[i].inputRate) {
2279 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
2280 binding_input_rate |= 1u << binding;
2281 instance_rate_divisors[binding] = 1;
2282 }
2283 }
2284 if (divisor_state) {
2285 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
2286 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
2287 divisor_state->pVertexBindingDivisors[i].divisor;
2288 }
2289 }
2290
2291 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
2292 const VkVertexInputAttributeDescription *desc =
2293 &input_state->pVertexAttributeDescriptions[i];
2294 const struct vk_format_description *format_desc;
2295 unsigned location = desc->location;
2296 unsigned binding = desc->binding;
2297 unsigned num_format, data_format;
2298 int first_non_void;
2299
2300 if (binding_input_rate & (1u << binding)) {
2301 key.instance_rate_inputs |= 1u << location;
2302 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
2303 }
2304
2305 format_desc = vk_format_description(desc->format);
2306 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2307
2308 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2309 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2310
2311 key.vertex_attribute_formats[location] = data_format | (num_format << 4);
2312 key.vertex_attribute_bindings[location] = desc->binding;
2313 key.vertex_attribute_offsets[location] = desc->offset;
2314 key.vertex_attribute_strides[location] = radv_get_attrib_stride(input_state, desc->binding);
2315
2316 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8 &&
2317 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
2318 VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
2319 uint64_t adjust;
2320 switch(format) {
2321 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2322 case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
2323 adjust = RADV_ALPHA_ADJUST_SNORM;
2324 break;
2325 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2326 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
2327 adjust = RADV_ALPHA_ADJUST_SSCALED;
2328 break;
2329 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2330 case VK_FORMAT_A2B10G10R10_SINT_PACK32:
2331 adjust = RADV_ALPHA_ADJUST_SINT;
2332 break;
2333 default:
2334 adjust = 0;
2335 break;
2336 }
2337 key.vertex_alpha_adjust |= adjust << (2 * location);
2338 }
2339
2340 switch (desc->format) {
2341 case VK_FORMAT_B8G8R8A8_UNORM:
2342 case VK_FORMAT_B8G8R8A8_SNORM:
2343 case VK_FORMAT_B8G8R8A8_USCALED:
2344 case VK_FORMAT_B8G8R8A8_SSCALED:
2345 case VK_FORMAT_B8G8R8A8_UINT:
2346 case VK_FORMAT_B8G8R8A8_SINT:
2347 case VK_FORMAT_B8G8R8A8_SRGB:
2348 case VK_FORMAT_A2R10G10B10_UNORM_PACK32:
2349 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2350 case VK_FORMAT_A2R10G10B10_USCALED_PACK32:
2351 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2352 case VK_FORMAT_A2R10G10B10_UINT_PACK32:
2353 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2354 key.vertex_post_shuffle |= 1 << location;
2355 break;
2356 default:
2357 break;
2358 }
2359 }
2360
2361 const VkPipelineTessellationStateCreateInfo *tess =
2362 radv_pipeline_get_tessellation_state(pCreateInfo);
2363 if (tess)
2364 key.tess_input_vertices = tess->patchControlPoints;
2365
2366 const VkPipelineMultisampleStateCreateInfo *vkms =
2367 radv_pipeline_get_multisample_state(pCreateInfo);
2368 if (vkms && vkms->rasterizationSamples > 1) {
2369 uint32_t num_samples = vkms->rasterizationSamples;
2370 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
2371 key.num_samples = num_samples;
2372 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
2373 }
2374
2375 key.col_format = blend->spi_shader_col_format;
2376 key.is_dual_src = blend->mrt0_is_dual_src;
2377 if (pipeline->device->physical_device->rad_info.chip_class < GFX8) {
2378 key.is_int8 = blend->col_format_is_int8;
2379 key.is_int10 = blend->col_format_is_int10;
2380 }
2381
2382 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10)
2383 key.topology = pCreateInfo->pInputAssemblyState->topology;
2384
2385 return key;
2386 }
2387
2388 static bool
2389 radv_nir_stage_uses_xfb(const nir_shader *nir)
2390 {
2391 nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
2392 bool uses_xfb = !!xfb;
2393
2394 ralloc_free(xfb);
2395 return uses_xfb;
2396 }
2397
2398 static void
2399 radv_fill_shader_keys(struct radv_device *device,
2400 struct radv_shader_variant_key *keys,
2401 const struct radv_pipeline_key *key,
2402 nir_shader **nir)
2403 {
2404 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
2405 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
2406 keys[MESA_SHADER_VERTEX].vs.post_shuffle = key->vertex_post_shuffle;
2407 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) {
2408 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
2409 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_formats[i] = key->vertex_attribute_formats[i];
2410 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_bindings[i] = key->vertex_attribute_bindings[i];
2411 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i];
2412 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i];
2413 }
2414 keys[MESA_SHADER_VERTEX].vs.outprim = si_conv_prim_to_gs_out(key->topology);
2415
2416 if (nir[MESA_SHADER_TESS_CTRL]) {
2417 keys[MESA_SHADER_VERTEX].vs_common_out.as_ls = true;
2418 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
2419 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
2420 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
2421
2422 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
2423 }
2424
2425 if (nir[MESA_SHADER_GEOMETRY]) {
2426 if (nir[MESA_SHADER_TESS_CTRL])
2427 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_es = true;
2428 else
2429 keys[MESA_SHADER_VERTEX].vs_common_out.as_es = true;
2430 }
2431
2432 if (device->physical_device->use_ngg) {
2433 if (nir[MESA_SHADER_TESS_CTRL]) {
2434 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = true;
2435 } else {
2436 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = true;
2437 }
2438
2439 if (nir[MESA_SHADER_TESS_CTRL] &&
2440 nir[MESA_SHADER_GEOMETRY] &&
2441 nir[MESA_SHADER_GEOMETRY]->info.gs.invocations *
2442 nir[MESA_SHADER_GEOMETRY]->info.gs.vertices_out > 256) {
2443 /* Fallback to the legacy path if tessellation is
2444 * enabled with extreme geometry because
2445 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2446 * might hang.
2447 */
2448 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2449 }
2450
2451 if (!device->physical_device->use_ngg_gs) {
2452 if (nir[MESA_SHADER_GEOMETRY]) {
2453 if (nir[MESA_SHADER_TESS_CTRL])
2454 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2455 else
2456 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2457 }
2458 }
2459
2460 gl_shader_stage last_xfb_stage = MESA_SHADER_VERTEX;
2461
2462 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
2463 if (nir[i])
2464 last_xfb_stage = i;
2465 }
2466
2467 bool uses_xfb = nir[last_xfb_stage] &&
2468 radv_nir_stage_uses_xfb(nir[last_xfb_stage]);
2469
2470 if (!device->physical_device->use_ngg_streamout && uses_xfb) {
2471 if (nir[MESA_SHADER_TESS_CTRL])
2472 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2473 else
2474 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2475 }
2476
2477 /* Determine if the pipeline is eligible for the NGG passthrough
2478 * mode. It can't be enabled for geometry shaders, for NGG
2479 * streamout or for vertex shaders that export the primitive ID
2480 * (this is checked later because we don't have the info here.)
2481 */
2482 if (!nir[MESA_SHADER_GEOMETRY] && !uses_xfb) {
2483 if (nir[MESA_SHADER_TESS_CTRL] &&
2484 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg) {
2485 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg_passthrough = true;
2486 } else if (nir[MESA_SHADER_VERTEX] &&
2487 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) {
2488 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = true;
2489 }
2490 }
2491 }
2492
2493 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
2494 keys[i].has_multiview_view_index = key->has_multiview_view_index;
2495
2496 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
2497 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
2498 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
2499 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
2500 keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples;
2501 keys[MESA_SHADER_FRAGMENT].fs.is_dual_src = key->is_dual_src;
2502
2503 if (nir[MESA_SHADER_COMPUTE]) {
2504 keys[MESA_SHADER_COMPUTE].cs.subgroup_size = key->compute_subgroup_size;
2505 }
2506 }
2507
2508 static uint8_t
2509 radv_get_wave_size(struct radv_device *device,
2510 const VkPipelineShaderStageCreateInfo *pStage,
2511 gl_shader_stage stage,
2512 const struct radv_shader_variant_key *key)
2513 {
2514 if (stage == MESA_SHADER_GEOMETRY && !key->vs_common_out.as_ngg)
2515 return 64;
2516 else if (stage == MESA_SHADER_COMPUTE) {
2517 if (key->cs.subgroup_size) {
2518 /* Return the required subgroup size if specified. */
2519 return key->cs.subgroup_size;
2520 }
2521 return device->physical_device->cs_wave_size;
2522 }
2523 else if (stage == MESA_SHADER_FRAGMENT)
2524 return device->physical_device->ps_wave_size;
2525 else
2526 return device->physical_device->ge_wave_size;
2527 }
2528
2529 static uint8_t
2530 radv_get_ballot_bit_size(struct radv_device *device,
2531 const VkPipelineShaderStageCreateInfo *pStage,
2532 gl_shader_stage stage,
2533 const struct radv_shader_variant_key *key)
2534 {
2535 if (stage == MESA_SHADER_COMPUTE && key->cs.subgroup_size)
2536 return key->cs.subgroup_size;
2537 return 64;
2538 }
2539
2540 static void
2541 radv_fill_shader_info(struct radv_pipeline *pipeline,
2542 const VkPipelineShaderStageCreateInfo **pStages,
2543 struct radv_shader_variant_key *keys,
2544 struct radv_shader_info *infos,
2545 nir_shader **nir)
2546 {
2547 unsigned active_stages = 0;
2548 unsigned filled_stages = 0;
2549
2550 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2551 if (nir[i])
2552 active_stages |= (1 << i);
2553 }
2554
2555 if (nir[MESA_SHADER_FRAGMENT]) {
2556 radv_nir_shader_info_init(&infos[MESA_SHADER_FRAGMENT]);
2557 radv_nir_shader_info_pass(nir[MESA_SHADER_FRAGMENT],
2558 pipeline->layout,
2559 &keys[MESA_SHADER_FRAGMENT],
2560 &infos[MESA_SHADER_FRAGMENT],
2561 pipeline->device->physical_device->use_llvm);
2562
2563 /* TODO: These are no longer used as keys we should refactor this */
2564 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2565 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2566 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2567 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2568 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2569 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2570 keys[MESA_SHADER_VERTEX].vs_common_out.export_viewport_index =
2571 infos[MESA_SHADER_FRAGMENT].ps.viewport_index_input;
2572 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2573 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2574 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2575 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2576 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2577 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2578 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_viewport_index =
2579 infos[MESA_SHADER_FRAGMENT].ps.viewport_index_input;
2580
2581 /* NGG passthrough mode can't be enabled for vertex shaders
2582 * that export the primitive ID.
2583 *
2584 * TODO: I should really refactor the keys logic.
2585 */
2586 if (nir[MESA_SHADER_VERTEX] &&
2587 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id) {
2588 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = false;
2589 }
2590
2591 filled_stages |= (1 << MESA_SHADER_FRAGMENT);
2592 }
2593
2594 if (nir[MESA_SHADER_TESS_CTRL]) {
2595 infos[MESA_SHADER_TESS_CTRL].tcs.tes_inputs_read =
2596 nir[MESA_SHADER_TESS_EVAL]->info.inputs_read;
2597 infos[MESA_SHADER_TESS_CTRL].tcs.tes_patch_inputs_read =
2598 nir[MESA_SHADER_TESS_EVAL]->info.patch_inputs_read;
2599 }
2600
2601 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2602 nir[MESA_SHADER_TESS_CTRL]) {
2603 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2604 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2605 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2606
2607 radv_nir_shader_info_init(&infos[MESA_SHADER_TESS_CTRL]);
2608
2609 for (int i = 0; i < 2; i++) {
2610 radv_nir_shader_info_pass(combined_nir[i],
2611 pipeline->layout, &key,
2612 &infos[MESA_SHADER_TESS_CTRL],
2613 pipeline->device->physical_device->use_llvm);
2614 }
2615
2616 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2617 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2618 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2619 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2620
2621 filled_stages |= (1 << MESA_SHADER_VERTEX);
2622 filled_stages |= (1 << MESA_SHADER_TESS_CTRL);
2623 }
2624
2625 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2626 nir[MESA_SHADER_GEOMETRY]) {
2627 gl_shader_stage pre_stage = nir[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2628 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2629
2630 radv_nir_shader_info_init(&infos[MESA_SHADER_GEOMETRY]);
2631
2632 for (int i = 0; i < 2; i++) {
2633 radv_nir_shader_info_pass(combined_nir[i],
2634 pipeline->layout,
2635 &keys[pre_stage],
2636 &infos[MESA_SHADER_GEOMETRY],
2637 pipeline->device->physical_device->use_llvm);
2638 }
2639
2640 filled_stages |= (1 << pre_stage);
2641 filled_stages |= (1 << MESA_SHADER_GEOMETRY);
2642 }
2643
2644 active_stages ^= filled_stages;
2645 while (active_stages) {
2646 int i = u_bit_scan(&active_stages);
2647
2648 if (i == MESA_SHADER_TESS_CTRL) {
2649 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs =
2650 util_last_bit64(infos[MESA_SHADER_VERTEX].vs.ls_outputs_written);
2651 }
2652
2653 if (i == MESA_SHADER_TESS_EVAL) {
2654 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2655 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2656 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2657 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2658 }
2659
2660 radv_nir_shader_info_init(&infos[i]);
2661 radv_nir_shader_info_pass(nir[i], pipeline->layout,
2662 &keys[i], &infos[i], pipeline->device->physical_device->use_llvm);
2663 }
2664
2665 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2666 if (nir[i]) {
2667 infos[i].wave_size =
2668 radv_get_wave_size(pipeline->device, pStages[i],
2669 i, &keys[i]);
2670 infos[i].ballot_bit_size =
2671 radv_get_ballot_bit_size(pipeline->device,
2672 pStages[i], i,
2673 &keys[i]);
2674 }
2675 }
2676 }
2677
2678 static void
2679 merge_tess_info(struct shader_info *tes_info,
2680 const struct shader_info *tcs_info)
2681 {
2682 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2683 *
2684 * "PointMode. Controls generation of points rather than triangles
2685 * or lines. This functionality defaults to disabled, and is
2686 * enabled if either shader stage includes the execution mode.
2687 *
2688 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2689 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2690 * and OutputVertices, it says:
2691 *
2692 * "One mode must be set in at least one of the tessellation
2693 * shader stages."
2694 *
2695 * So, the fields can be set in either the TCS or TES, but they must
2696 * agree if set in both. Our backend looks at TES, so bitwise-or in
2697 * the values from the TCS.
2698 */
2699 assert(tcs_info->tess.tcs_vertices_out == 0 ||
2700 tes_info->tess.tcs_vertices_out == 0 ||
2701 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
2702 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
2703
2704 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2705 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2706 tcs_info->tess.spacing == tes_info->tess.spacing);
2707 tes_info->tess.spacing |= tcs_info->tess.spacing;
2708
2709 assert(tcs_info->tess.primitive_mode == 0 ||
2710 tes_info->tess.primitive_mode == 0 ||
2711 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
2712 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
2713 tes_info->tess.ccw |= tcs_info->tess.ccw;
2714 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
2715 }
2716
2717 static
2718 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT *ext)
2719 {
2720 if (!ext)
2721 return;
2722
2723 if (ext->pPipelineCreationFeedback) {
2724 ext->pPipelineCreationFeedback->flags = 0;
2725 ext->pPipelineCreationFeedback->duration = 0;
2726 }
2727
2728 for (unsigned i = 0; i < ext->pipelineStageCreationFeedbackCount; ++i) {
2729 ext->pPipelineStageCreationFeedbacks[i].flags = 0;
2730 ext->pPipelineStageCreationFeedbacks[i].duration = 0;
2731 }
2732 }
2733
2734 static
2735 void radv_start_feedback(VkPipelineCreationFeedbackEXT *feedback)
2736 {
2737 if (!feedback)
2738 return;
2739
2740 feedback->duration -= radv_get_current_time();
2741 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT;
2742 }
2743
2744 static
2745 void radv_stop_feedback(VkPipelineCreationFeedbackEXT *feedback, bool cache_hit)
2746 {
2747 if (!feedback)
2748 return;
2749
2750 feedback->duration += radv_get_current_time();
2751 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT |
2752 (cache_hit ? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT : 0);
2753 }
2754
2755 VkResult radv_create_shaders(struct radv_pipeline *pipeline,
2756 struct radv_device *device,
2757 struct radv_pipeline_cache *cache,
2758 const struct radv_pipeline_key *key,
2759 const VkPipelineShaderStageCreateInfo **pStages,
2760 const VkPipelineCreateFlags flags,
2761 VkPipelineCreationFeedbackEXT *pipeline_feedback,
2762 VkPipelineCreationFeedbackEXT **stage_feedbacks)
2763 {
2764 struct radv_shader_module fs_m = {0};
2765 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2766 nir_shader *nir[MESA_SHADER_STAGES] = {0};
2767 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2768 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{{0}}}}};
2769 struct radv_shader_info infos[MESA_SHADER_STAGES] = {0};
2770 unsigned char hash[20], gs_copy_hash[20];
2771 bool keep_executable_info = (flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR) || device->keep_shader_info;
2772 bool keep_statistic_info = (flags & VK_PIPELINE_CREATE_CAPTURE_STATISTICS_BIT_KHR) ||
2773 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) ||
2774 device->keep_shader_info;
2775
2776 radv_start_feedback(pipeline_feedback);
2777
2778 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2779 if (pStages[i]) {
2780 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
2781 if (modules[i]->nir)
2782 _mesa_sha1_compute(modules[i]->nir->info.name,
2783 strlen(modules[i]->nir->info.name),
2784 modules[i]->sha1);
2785
2786 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
2787 }
2788 }
2789
2790 radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device));
2791 memcpy(gs_copy_hash, hash, 20);
2792 gs_copy_hash[0] ^= 1;
2793
2794 bool found_in_application_cache = true;
2795 if (modules[MESA_SHADER_GEOMETRY] && !keep_executable_info && !keep_statistic_info) {
2796 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2797 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants,
2798 &found_in_application_cache);
2799 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
2800 }
2801
2802 if (!keep_executable_info && !keep_statistic_info &&
2803 radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders,
2804 &found_in_application_cache) &&
2805 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
2806 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2807 return VK_SUCCESS;
2808 }
2809
2810 if (flags & VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_EXT) {
2811 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2812 return VK_PIPELINE_COMPILE_REQUIRED_EXT;
2813 }
2814
2815 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
2816 nir_builder fs_b;
2817 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2818 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2819 fs_m.nir = fs_b.shader;
2820 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2821 }
2822
2823 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2824 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
2825 unsigned subgroup_size = 64, ballot_bit_size = 64;
2826
2827 if (!modules[i])
2828 continue;
2829
2830 radv_start_feedback(stage_feedbacks[i]);
2831
2832 if (key->compute_subgroup_size) {
2833 /* Only compute shaders currently support requiring a
2834 * specific subgroup size.
2835 */
2836 assert(i == MESA_SHADER_COMPUTE);
2837 subgroup_size = key->compute_subgroup_size;
2838 ballot_bit_size = key->compute_subgroup_size;
2839 }
2840
2841 nir[i] = radv_shader_compile_to_nir(device, modules[i],
2842 stage ? stage->pName : "main", i,
2843 stage ? stage->pSpecializationInfo : NULL,
2844 flags, pipeline->layout,
2845 subgroup_size, ballot_bit_size);
2846
2847 /* We don't want to alter meta shaders IR directly so clone it
2848 * first.
2849 */
2850 if (nir[i]->info.name) {
2851 nir[i] = nir_shader_clone(NULL, nir[i]);
2852 }
2853
2854 radv_stop_feedback(stage_feedbacks[i], false);
2855 }
2856
2857 if (nir[MESA_SHADER_TESS_CTRL]) {
2858 nir_lower_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
2859 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
2860 }
2861
2862 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
2863 radv_link_shaders(pipeline, nir);
2864
2865 radv_set_linked_driver_locations(pipeline, nir, infos);
2866
2867 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2868 if (nir[i]) {
2869 /* do this again since information such as outputs_read can be out-of-date */
2870 nir_shader_gather_info(nir[i], nir_shader_get_entrypoint(nir[i]));
2871
2872 if (device->physical_device->use_llvm) {
2873 NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
2874 } else {
2875 NIR_PASS_V(nir[i], nir_lower_non_uniform_access,
2876 nir_lower_non_uniform_ubo_access |
2877 nir_lower_non_uniform_ssbo_access |
2878 nir_lower_non_uniform_texture_access |
2879 nir_lower_non_uniform_image_access);
2880 }
2881 }
2882 }
2883
2884 if (nir[MESA_SHADER_FRAGMENT])
2885 radv_lower_fs_io(nir[MESA_SHADER_FRAGMENT]);
2886
2887 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2888 if (radv_can_dump_shader(device, modules[i], false))
2889 nir_print_shader(nir[i], stderr);
2890 }
2891
2892 radv_fill_shader_keys(device, keys, key, nir);
2893
2894 radv_fill_shader_info(pipeline, pStages, keys, infos, nir);
2895
2896 if ((nir[MESA_SHADER_VERTEX] &&
2897 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) ||
2898 (nir[MESA_SHADER_TESS_EVAL] &&
2899 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg)) {
2900 struct gfx10_ngg_info *ngg_info;
2901
2902 if (nir[MESA_SHADER_GEOMETRY])
2903 ngg_info = &infos[MESA_SHADER_GEOMETRY].ngg_info;
2904 else if (nir[MESA_SHADER_TESS_CTRL])
2905 ngg_info = &infos[MESA_SHADER_TESS_EVAL].ngg_info;
2906 else
2907 ngg_info = &infos[MESA_SHADER_VERTEX].ngg_info;
2908
2909 gfx10_get_ngg_info(key, pipeline, nir, infos, ngg_info);
2910 } else if (nir[MESA_SHADER_GEOMETRY]) {
2911 struct gfx9_gs_info *gs_info =
2912 &infos[MESA_SHADER_GEOMETRY].gs_ring_info;
2913
2914 gfx9_get_gs_info(key, pipeline, nir, infos, gs_info);
2915 }
2916
2917 if(modules[MESA_SHADER_GEOMETRY]) {
2918 struct radv_shader_binary *gs_copy_binary = NULL;
2919 if (!pipeline->gs_copy_shader &&
2920 !radv_pipeline_has_ngg(pipeline)) {
2921 struct radv_shader_info info = {};
2922 struct radv_shader_variant_key key = {};
2923
2924 key.has_multiview_view_index =
2925 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index;
2926
2927 radv_nir_shader_info_pass(nir[MESA_SHADER_GEOMETRY],
2928 pipeline->layout, &key,
2929 &info, pipeline->device->physical_device->use_llvm);
2930 info.wave_size = 64; /* Wave32 not supported. */
2931 info.ballot_bit_size = 64;
2932
2933 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2934 device, nir[MESA_SHADER_GEOMETRY], &info,
2935 &gs_copy_binary, keep_executable_info, keep_statistic_info,
2936 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2937 }
2938
2939 if (!keep_executable_info && !keep_statistic_info && pipeline->gs_copy_shader) {
2940 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2941 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2942
2943 binaries[MESA_SHADER_GEOMETRY] = gs_copy_binary;
2944 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2945
2946 radv_pipeline_cache_insert_shaders(device, cache,
2947 gs_copy_hash,
2948 variants,
2949 binaries);
2950 }
2951 free(gs_copy_binary);
2952 }
2953
2954 if (nir[MESA_SHADER_FRAGMENT]) {
2955 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
2956 radv_start_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT]);
2957
2958 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2959 radv_shader_variant_compile(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
2960 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
2961 infos + MESA_SHADER_FRAGMENT,
2962 keep_executable_info, keep_statistic_info,
2963 &binaries[MESA_SHADER_FRAGMENT]);
2964
2965 radv_stop_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT], false);
2966 }
2967 }
2968
2969 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
2970 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
2971 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2972 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2973 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2974
2975 radv_start_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL]);
2976
2977 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
2978 pipeline->layout,
2979 &key, &infos[MESA_SHADER_TESS_CTRL], keep_executable_info,
2980 keep_statistic_info, &binaries[MESA_SHADER_TESS_CTRL]);
2981
2982 radv_stop_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL], false);
2983 }
2984 modules[MESA_SHADER_VERTEX] = NULL;
2985 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2986 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2987 }
2988
2989 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
2990 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2991 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
2992 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2993
2994 radv_start_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY]);
2995
2996 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2997 pipeline->layout,
2998 &keys[pre_stage], &infos[MESA_SHADER_GEOMETRY], keep_executable_info,
2999 keep_statistic_info, &binaries[MESA_SHADER_GEOMETRY]);
3000
3001 radv_stop_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY], false);
3002 }
3003 modules[pre_stage] = NULL;
3004 }
3005
3006 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
3007 if(modules[i] && !pipeline->shaders[i]) {
3008 if (i == MESA_SHADER_TESS_CTRL) {
3009 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.ls_outputs_written);
3010 }
3011 if (i == MESA_SHADER_TESS_EVAL) {
3012 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
3013 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
3014 }
3015
3016 radv_start_feedback(stage_feedbacks[i]);
3017
3018 pipeline->shaders[i] = radv_shader_variant_compile(device, modules[i], &nir[i], 1,
3019 pipeline->layout,
3020 keys + i, infos + i, keep_executable_info,
3021 keep_statistic_info, &binaries[i]);
3022
3023 radv_stop_feedback(stage_feedbacks[i], false);
3024 }
3025 }
3026
3027 if (!keep_executable_info && !keep_statistic_info) {
3028 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
3029 binaries);
3030 }
3031
3032 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
3033 free(binaries[i]);
3034 if (nir[i]) {
3035 ralloc_free(nir[i]);
3036
3037 if (radv_can_dump_shader_stats(device, modules[i]))
3038 radv_shader_dump_stats(device,
3039 pipeline->shaders[i],
3040 i, stderr);
3041 }
3042 }
3043
3044 if (fs_m.nir)
3045 ralloc_free(fs_m.nir);
3046
3047 radv_stop_feedback(pipeline_feedback, false);
3048 return VK_SUCCESS;
3049 }
3050
3051 static uint32_t
3052 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
3053 gl_shader_stage stage, enum chip_class chip_class)
3054 {
3055 bool has_gs = radv_pipeline_has_gs(pipeline);
3056 bool has_tess = radv_pipeline_has_tess(pipeline);
3057 bool has_ngg = radv_pipeline_has_ngg(pipeline);
3058
3059 switch (stage) {
3060 case MESA_SHADER_FRAGMENT:
3061 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
3062 case MESA_SHADER_VERTEX:
3063 if (has_tess) {
3064 if (chip_class >= GFX10) {
3065 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
3066 } else if (chip_class == GFX9) {
3067 return R_00B430_SPI_SHADER_USER_DATA_LS_0;
3068 } else {
3069 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
3070 }
3071
3072 }
3073
3074 if (has_gs) {
3075 if (chip_class >= GFX10) {
3076 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3077 } else {
3078 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
3079 }
3080 }
3081
3082 if (has_ngg)
3083 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3084
3085 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
3086 case MESA_SHADER_GEOMETRY:
3087 return chip_class == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
3088 R_00B230_SPI_SHADER_USER_DATA_GS_0;
3089 case MESA_SHADER_COMPUTE:
3090 return R_00B900_COMPUTE_USER_DATA_0;
3091 case MESA_SHADER_TESS_CTRL:
3092 return chip_class == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
3093 R_00B430_SPI_SHADER_USER_DATA_HS_0;
3094 case MESA_SHADER_TESS_EVAL:
3095 if (has_gs) {
3096 return chip_class >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0 :
3097 R_00B330_SPI_SHADER_USER_DATA_ES_0;
3098 } else if (has_ngg) {
3099 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3100 } else {
3101 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
3102 }
3103 default:
3104 unreachable("unknown shader");
3105 }
3106 }
3107
3108 struct radv_bin_size_entry {
3109 unsigned bpp;
3110 VkExtent2D extent;
3111 };
3112
3113 static VkExtent2D
3114 radv_gfx9_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3115 {
3116 static const struct radv_bin_size_entry color_size_table[][3][9] = {
3117 {
3118 /* One RB / SE */
3119 {
3120 /* One shader engine */
3121 { 0, {128, 128}},
3122 { 1, { 64, 128}},
3123 { 2, { 32, 128}},
3124 { 3, { 16, 128}},
3125 { 17, { 0, 0}},
3126 { UINT_MAX, { 0, 0}},
3127 },
3128 {
3129 /* Two shader engines */
3130 { 0, {128, 128}},
3131 { 2, { 64, 128}},
3132 { 3, { 32, 128}},
3133 { 5, { 16, 128}},
3134 { 17, { 0, 0}},
3135 { UINT_MAX, { 0, 0}},
3136 },
3137 {
3138 /* Four shader engines */
3139 { 0, {128, 128}},
3140 { 3, { 64, 128}},
3141 { 5, { 16, 128}},
3142 { 17, { 0, 0}},
3143 { UINT_MAX, { 0, 0}},
3144 },
3145 },
3146 {
3147 /* Two RB / SE */
3148 {
3149 /* One shader engine */
3150 { 0, {128, 128}},
3151 { 2, { 64, 128}},
3152 { 3, { 32, 128}},
3153 { 5, { 16, 128}},
3154 { 33, { 0, 0}},
3155 { UINT_MAX, { 0, 0}},
3156 },
3157 {
3158 /* Two shader engines */
3159 { 0, {128, 128}},
3160 { 3, { 64, 128}},
3161 { 5, { 32, 128}},
3162 { 9, { 16, 128}},
3163 { 33, { 0, 0}},
3164 { UINT_MAX, { 0, 0}},
3165 },
3166 {
3167 /* Four shader engines */
3168 { 0, {256, 256}},
3169 { 2, {128, 256}},
3170 { 3, {128, 128}},
3171 { 5, { 64, 128}},
3172 { 9, { 16, 128}},
3173 { 33, { 0, 0}},
3174 { UINT_MAX, { 0, 0}},
3175 },
3176 },
3177 {
3178 /* Four RB / SE */
3179 {
3180 /* One shader engine */
3181 { 0, {128, 256}},
3182 { 2, {128, 128}},
3183 { 3, { 64, 128}},
3184 { 5, { 32, 128}},
3185 { 9, { 16, 128}},
3186 { 33, { 0, 0}},
3187 { UINT_MAX, { 0, 0}},
3188 },
3189 {
3190 /* Two shader engines */
3191 { 0, {256, 256}},
3192 { 2, {128, 256}},
3193 { 3, {128, 128}},
3194 { 5, { 64, 128}},
3195 { 9, { 32, 128}},
3196 { 17, { 16, 128}},
3197 { 33, { 0, 0}},
3198 { UINT_MAX, { 0, 0}},
3199 },
3200 {
3201 /* Four shader engines */
3202 { 0, {256, 512}},
3203 { 2, {256, 256}},
3204 { 3, {128, 256}},
3205 { 5, {128, 128}},
3206 { 9, { 64, 128}},
3207 { 17, { 16, 128}},
3208 { 33, { 0, 0}},
3209 { UINT_MAX, { 0, 0}},
3210 },
3211 },
3212 };
3213 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
3214 {
3215 // One RB / SE
3216 {
3217 // One shader engine
3218 { 0, {128, 256}},
3219 { 2, {128, 128}},
3220 { 4, { 64, 128}},
3221 { 7, { 32, 128}},
3222 { 13, { 16, 128}},
3223 { 49, { 0, 0}},
3224 { UINT_MAX, { 0, 0}},
3225 },
3226 {
3227 // Two shader engines
3228 { 0, {256, 256}},
3229 { 2, {128, 256}},
3230 { 4, {128, 128}},
3231 { 7, { 64, 128}},
3232 { 13, { 32, 128}},
3233 { 25, { 16, 128}},
3234 { 49, { 0, 0}},
3235 { UINT_MAX, { 0, 0}},
3236 },
3237 {
3238 // Four shader engines
3239 { 0, {256, 512}},
3240 { 2, {256, 256}},
3241 { 4, {128, 256}},
3242 { 7, {128, 128}},
3243 { 13, { 64, 128}},
3244 { 25, { 16, 128}},
3245 { 49, { 0, 0}},
3246 { UINT_MAX, { 0, 0}},
3247 },
3248 },
3249 {
3250 // Two RB / SE
3251 {
3252 // One shader engine
3253 { 0, {256, 256}},
3254 { 2, {128, 256}},
3255 { 4, {128, 128}},
3256 { 7, { 64, 128}},
3257 { 13, { 32, 128}},
3258 { 25, { 16, 128}},
3259 { 97, { 0, 0}},
3260 { UINT_MAX, { 0, 0}},
3261 },
3262 {
3263 // Two shader engines
3264 { 0, {256, 512}},
3265 { 2, {256, 256}},
3266 { 4, {128, 256}},
3267 { 7, {128, 128}},
3268 { 13, { 64, 128}},
3269 { 25, { 32, 128}},
3270 { 49, { 16, 128}},
3271 { 97, { 0, 0}},
3272 { UINT_MAX, { 0, 0}},
3273 },
3274 {
3275 // Four shader engines
3276 { 0, {512, 512}},
3277 { 2, {256, 512}},
3278 { 4, {256, 256}},
3279 { 7, {128, 256}},
3280 { 13, {128, 128}},
3281 { 25, { 64, 128}},
3282 { 49, { 16, 128}},
3283 { 97, { 0, 0}},
3284 { UINT_MAX, { 0, 0}},
3285 },
3286 },
3287 {
3288 // Four RB / SE
3289 {
3290 // One shader engine
3291 { 0, {256, 512}},
3292 { 2, {256, 256}},
3293 { 4, {128, 256}},
3294 { 7, {128, 128}},
3295 { 13, { 64, 128}},
3296 { 25, { 32, 128}},
3297 { 49, { 16, 128}},
3298 { UINT_MAX, { 0, 0}},
3299 },
3300 {
3301 // Two shader engines
3302 { 0, {512, 512}},
3303 { 2, {256, 512}},
3304 { 4, {256, 256}},
3305 { 7, {128, 256}},
3306 { 13, {128, 128}},
3307 { 25, { 64, 128}},
3308 { 49, { 32, 128}},
3309 { 97, { 16, 128}},
3310 { UINT_MAX, { 0, 0}},
3311 },
3312 {
3313 // Four shader engines
3314 { 0, {512, 512}},
3315 { 4, {256, 512}},
3316 { 7, {256, 256}},
3317 { 13, {128, 256}},
3318 { 25, {128, 128}},
3319 { 49, { 64, 128}},
3320 { 97, { 16, 128}},
3321 { UINT_MAX, { 0, 0}},
3322 },
3323 },
3324 };
3325
3326 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3327 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3328 VkExtent2D extent = {512, 512};
3329
3330 unsigned log_num_rb_per_se =
3331 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
3332 pipeline->device->physical_device->rad_info.max_se);
3333 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
3334
3335 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3336 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
3337 unsigned effective_samples = total_samples;
3338 unsigned color_bytes_per_pixel = 0;
3339
3340 const VkPipelineColorBlendStateCreateInfo *vkblend =
3341 radv_pipeline_get_color_blend_state(pCreateInfo);
3342 if (vkblend) {
3343 for (unsigned i = 0; i < subpass->color_count; i++) {
3344 if (!vkblend->pAttachments[i].colorWriteMask)
3345 continue;
3346
3347 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3348 continue;
3349
3350 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3351 color_bytes_per_pixel += vk_format_get_blocksize(format);
3352 }
3353
3354 /* MSAA images typically don't use all samples all the time. */
3355 if (effective_samples >= 2 && ps_iter_samples <= 1)
3356 effective_samples = 2;
3357 color_bytes_per_pixel *= effective_samples;
3358 }
3359
3360 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
3361 while(color_entry[1].bpp <= color_bytes_per_pixel)
3362 ++color_entry;
3363
3364 extent = color_entry->extent;
3365
3366 if (subpass->depth_stencil_attachment) {
3367 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3368
3369 /* Coefficients taken from AMDVLK */
3370 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3371 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3372 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
3373
3374 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
3375 while(ds_entry[1].bpp <= ds_bytes_per_pixel)
3376 ++ds_entry;
3377
3378 if (ds_entry->extent.width * ds_entry->extent.height < extent.width * extent.height)
3379 extent = ds_entry->extent;
3380 }
3381
3382 return extent;
3383 }
3384
3385 static VkExtent2D
3386 radv_gfx10_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3387 {
3388 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3389 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3390 VkExtent2D extent = {512, 512};
3391
3392 const unsigned db_tag_size = 64;
3393 const unsigned db_tag_count = 312;
3394 const unsigned color_tag_size = 1024;
3395 const unsigned color_tag_count = 31;
3396 const unsigned fmask_tag_size = 256;
3397 const unsigned fmask_tag_count = 44;
3398
3399 const unsigned rb_count = pipeline->device->physical_device->rad_info.num_render_backends;
3400 const unsigned pipe_count = MAX2(rb_count, pipeline->device->physical_device->rad_info.num_sdp_interfaces);
3401
3402 const unsigned db_tag_part = (db_tag_count * rb_count / pipe_count) * db_tag_size * pipe_count;
3403 const unsigned color_tag_part = (color_tag_count * rb_count / pipe_count) * color_tag_size * pipe_count;
3404 const unsigned fmask_tag_part = (fmask_tag_count * rb_count / pipe_count) * fmask_tag_size * pipe_count;
3405
3406 const unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3407 const unsigned samples_log = util_logbase2_ceil(total_samples);
3408
3409 unsigned color_bytes_per_pixel = 0;
3410 unsigned fmask_bytes_per_pixel = 0;
3411
3412 const VkPipelineColorBlendStateCreateInfo *vkblend =
3413 radv_pipeline_get_color_blend_state(pCreateInfo);
3414 if (vkblend) {
3415 for (unsigned i = 0; i < subpass->color_count; i++) {
3416 if (!vkblend->pAttachments[i].colorWriteMask)
3417 continue;
3418
3419 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3420 continue;
3421
3422 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3423 color_bytes_per_pixel += vk_format_get_blocksize(format);
3424
3425 if (total_samples > 1) {
3426 assert(samples_log <= 3);
3427 const unsigned fmask_array[] = {0, 1, 1, 4};
3428 fmask_bytes_per_pixel += fmask_array[samples_log];
3429 }
3430 }
3431
3432 color_bytes_per_pixel *= total_samples;
3433 }
3434 color_bytes_per_pixel = MAX2(color_bytes_per_pixel, 1);
3435
3436 const unsigned color_pixel_count_log = util_logbase2(color_tag_part / color_bytes_per_pixel);
3437 extent.width = 1ull << ((color_pixel_count_log + 1) / 2);
3438 extent.height = 1ull << (color_pixel_count_log / 2);
3439
3440 if (fmask_bytes_per_pixel) {
3441 const unsigned fmask_pixel_count_log = util_logbase2(fmask_tag_part / fmask_bytes_per_pixel);
3442
3443 const VkExtent2D fmask_extent = (VkExtent2D){
3444 .width = 1ull << ((fmask_pixel_count_log + 1) / 2),
3445 .height = 1ull << (color_pixel_count_log / 2)
3446 };
3447
3448 if (fmask_extent.width * fmask_extent.height < extent.width * extent.height)
3449 extent = fmask_extent;
3450 }
3451
3452 if (subpass->depth_stencil_attachment) {
3453 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3454
3455 /* Coefficients taken from AMDVLK */
3456 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3457 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3458 unsigned db_bytes_per_pixel = (depth_coeff + stencil_coeff) * total_samples;
3459
3460 const unsigned db_pixel_count_log = util_logbase2(db_tag_part / db_bytes_per_pixel);
3461
3462 const VkExtent2D db_extent = (VkExtent2D){
3463 .width = 1ull << ((db_pixel_count_log + 1) / 2),
3464 .height = 1ull << (color_pixel_count_log / 2)
3465 };
3466
3467 if (db_extent.width * db_extent.height < extent.width * extent.height)
3468 extent = db_extent;
3469 }
3470
3471 extent.width = MAX2(extent.width, 128);
3472 extent.height = MAX2(extent.width, 64);
3473
3474 return extent;
3475 }
3476
3477 static void
3478 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf *ctx_cs,
3479 struct radv_pipeline *pipeline,
3480 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3481 {
3482 uint32_t pa_sc_binner_cntl_0 =
3483 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
3484 S_028C44_DISABLE_START_OF_PRIM(1);
3485 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3486
3487 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3488 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3489 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3490 const VkPipelineColorBlendStateCreateInfo *vkblend =
3491 radv_pipeline_get_color_blend_state(pCreateInfo);
3492 unsigned min_bytes_per_pixel = 0;
3493
3494 if (vkblend) {
3495 for (unsigned i = 0; i < subpass->color_count; i++) {
3496 if (!vkblend->pAttachments[i].colorWriteMask)
3497 continue;
3498
3499 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3500 continue;
3501
3502 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3503 unsigned bytes = vk_format_get_blocksize(format);
3504 if (!min_bytes_per_pixel || bytes < min_bytes_per_pixel)
3505 min_bytes_per_pixel = bytes;
3506 }
3507 }
3508
3509 pa_sc_binner_cntl_0 =
3510 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) |
3511 S_028C44_BIN_SIZE_X(0) |
3512 S_028C44_BIN_SIZE_Y(0) |
3513 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3514 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel <= 4 ? 2 : 1) | /* 128 or 64 */
3515 S_028C44_DISABLE_START_OF_PRIM(1);
3516 }
3517
3518 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3519 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3520 }
3521
3522 struct radv_binning_settings
3523 radv_get_binning_settings(const struct radv_physical_device *pdev)
3524 {
3525 struct radv_binning_settings settings;
3526 if (pdev->rad_info.has_dedicated_vram) {
3527 if (pdev->rad_info.num_render_backends > 4) {
3528 settings.context_states_per_bin = 1;
3529 settings.persistent_states_per_bin = 1;
3530 } else {
3531 settings.context_states_per_bin = 3;
3532 settings.persistent_states_per_bin = 8;
3533 }
3534 settings.fpovs_per_batch = 63;
3535 } else {
3536 /* The context states are affected by the scissor bug. */
3537 settings.context_states_per_bin = 6;
3538 /* 32 causes hangs for RAVEN. */
3539 settings.persistent_states_per_bin = 16;
3540 settings.fpovs_per_batch = 63;
3541 }
3542
3543 if (pdev->rad_info.has_gfx9_scissor_bug)
3544 settings.context_states_per_bin = 1;
3545
3546 return settings;
3547 }
3548
3549 static void
3550 radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs,
3551 struct radv_pipeline *pipeline,
3552 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3553 const struct radv_blend_state *blend)
3554 {
3555 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
3556 return;
3557
3558 VkExtent2D bin_size;
3559 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3560 bin_size = radv_gfx10_compute_bin_size(pipeline, pCreateInfo);
3561 } else if (pipeline->device->physical_device->rad_info.chip_class == GFX9) {
3562 bin_size = radv_gfx9_compute_bin_size(pipeline, pCreateInfo);
3563 } else
3564 unreachable("Unhandled generation for binning bin size calculation");
3565
3566 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
3567 struct radv_binning_settings settings =
3568 radv_get_binning_settings(pipeline->device->physical_device);
3569
3570 bool disable_start_of_prim = true;
3571 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3572
3573 const struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3574
3575 if (pipeline->device->dfsm_allowed && ps &&
3576 !ps->info.ps.can_discard &&
3577 !ps->info.ps.writes_memory &&
3578 blend->cb_target_enabled_4bit) {
3579 db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_AUTO);
3580 disable_start_of_prim = (blend->blend_enable_4bit & blend->cb_target_enabled_4bit) != 0;
3581 }
3582
3583 const uint32_t pa_sc_binner_cntl_0 =
3584 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
3585 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
3586 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
3587 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
3588 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
3589 S_028C44_CONTEXT_STATES_PER_BIN(settings.context_states_per_bin - 1) |
3590 S_028C44_PERSISTENT_STATES_PER_BIN(settings.persistent_states_per_bin - 1) |
3591 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim) |
3592 S_028C44_FPOVS_PER_BATCH(settings.fpovs_per_batch) |
3593 S_028C44_OPTIMAL_BIN_SELECTION(1);
3594
3595 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3596 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3597 } else
3598 radv_pipeline_generate_disabled_binning_state(ctx_cs, pipeline, pCreateInfo);
3599 }
3600
3601
3602 static void
3603 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs,
3604 struct radv_pipeline *pipeline,
3605 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3606 const struct radv_graphics_pipeline_create_info *extra)
3607 {
3608 const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
3609 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3610 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3611 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3612 struct radv_render_pass_attachment *attachment = NULL;
3613 uint32_t db_depth_control = 0;
3614 uint32_t db_render_control = 0, db_render_override2 = 0;
3615 uint32_t db_render_override = 0;
3616
3617 if (subpass->depth_stencil_attachment)
3618 attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3619
3620 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
3621 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
3622
3623 if (vkds && has_depth_attachment) {
3624 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
3625 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
3626 S_028800_ZFUNC(vkds->depthCompareOp) |
3627 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
3628
3629 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3630 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
3631
3632 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10_3)
3633 db_render_override2 |= S_028010_CENTROID_COMPUTATION_MODE_GFX103(2);
3634 }
3635
3636 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
3637 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3638 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
3639
3640 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
3641 }
3642
3643 if (attachment && extra) {
3644 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
3645 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
3646
3647 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->resummarize_enable);
3648 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->depth_compress_disable);
3649 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->stencil_compress_disable);
3650 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
3651 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
3652 }
3653
3654 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3655 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
3656
3657 if (!pCreateInfo->pRasterizationState->depthClampEnable &&
3658 ps->info.ps.writes_z) {
3659 /* From VK_EXT_depth_range_unrestricted spec:
3660 *
3661 * "The behavior described in Primitive Clipping still applies.
3662 * If depth clamping is disabled the depth values are still
3663 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3664 * depth clamping is enabled the above equation is ignored and
3665 * the depth values are instead clamped to the VkViewport
3666 * minDepth and maxDepth values, which in the case of this
3667 * extension can be outside of the 0.0 to 1.0 range."
3668 */
3669 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3670 }
3671
3672 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control);
3673 radeon_set_context_reg(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
3674 radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
3675
3676 pipeline->graphics.db_depth_control = db_depth_control;
3677 }
3678
3679 static void
3680 radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
3681 struct radv_pipeline *pipeline,
3682 const struct radv_blend_state *blend)
3683 {
3684 radeon_set_context_reg_seq(ctx_cs, R_028780_CB_BLEND0_CONTROL, 8);
3685 radeon_emit_array(ctx_cs, blend->cb_blend_control,
3686 8);
3687 radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
3688 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
3689
3690 if (pipeline->device->physical_device->rad_info.has_rbplus) {
3691
3692 radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
3693 radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
3694 }
3695
3696 radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
3697
3698 radeon_set_context_reg(ctx_cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
3699 radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
3700
3701 pipeline->graphics.col_format = blend->spi_shader_col_format;
3702 pipeline->graphics.cb_target_mask = blend->cb_target_mask;
3703 }
3704
3705 static const VkConservativeRasterizationModeEXT
3706 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo)
3707 {
3708 const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster =
3709 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT);
3710
3711 if (!conservative_raster)
3712 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT;
3713 return conservative_raster->conservativeRasterizationMode;
3714 }
3715
3716 static void
3717 radv_pipeline_generate_raster_state(struct radeon_cmdbuf *ctx_cs,
3718 struct radv_pipeline *pipeline,
3719 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3720 {
3721 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
3722 const VkConservativeRasterizationModeEXT mode =
3723 radv_get_conservative_raster_mode(vkraster);
3724 uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3725 bool depth_clip_disable = vkraster->depthClampEnable;
3726
3727 const VkPipelineRasterizationDepthClipStateCreateInfoEXT *depth_clip_state =
3728 vk_find_struct_const(vkraster->pNext, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT);
3729 if (depth_clip_state) {
3730 depth_clip_disable = !depth_clip_state->depthClipEnable;
3731 }
3732
3733 radeon_set_context_reg(ctx_cs, R_028810_PA_CL_CLIP_CNTL,
3734 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3735 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable ? 1 : 0) |
3736 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable ? 1 : 0) |
3737 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
3738 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3739
3740 pipeline->graphics.pa_su_sc_mode_cntl =
3741 S_028814_FACE(vkraster->frontFace) |
3742 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
3743 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
3744 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
3745 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3746 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3747 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3748 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3749 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
3750
3751 radeon_set_context_reg(ctx_cs, R_028BDC_PA_SC_LINE_CNTL,
3752 S_028BDC_DX10_DIAMOND_TEST_ENA(1));
3753
3754 /* Conservative rasterization. */
3755 if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
3756 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3757
3758 ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3759 ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3760 S_028804_OVERRASTERIZATION_AMOUNT(4);
3761
3762 pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3763 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3764 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3765
3766 if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) {
3767 pa_sc_conservative_rast |=
3768 S_028C4C_OVER_RAST_ENABLE(1) |
3769 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3770 S_028C4C_UNDER_RAST_ENABLE(0) |
3771 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3772 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3773 } else {
3774 assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT);
3775 pa_sc_conservative_rast |=
3776 S_028C4C_OVER_RAST_ENABLE(0) |
3777 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3778 S_028C4C_UNDER_RAST_ENABLE(1) |
3779 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3780 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3781 }
3782 }
3783
3784 radeon_set_context_reg(ctx_cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
3785 pa_sc_conservative_rast);
3786 }
3787
3788
3789 static void
3790 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
3791 struct radv_pipeline *pipeline)
3792 {
3793 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3794
3795 radeon_set_context_reg_seq(ctx_cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3796 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[0]);
3797 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]);
3798
3799 radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa);
3800 radeon_set_context_reg(ctx_cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
3801 radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
3802 radeon_set_context_reg(ctx_cs, R_028BE0_PA_SC_AA_CONFIG, ms->pa_sc_aa_config);
3803
3804 /* The exclusion bits can be set to improve rasterization efficiency
3805 * if no sample lies on the pixel boundary (-8 sample offset). It's
3806 * currently always TRUE because the driver doesn't support 16 samples.
3807 */
3808 bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= GFX7;
3809 radeon_set_context_reg(ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3810 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3811 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3812
3813 /* GFX9: Flush DFSM when the AA mode changes. */
3814 if (pipeline->device->dfsm_allowed) {
3815 radeon_emit(ctx_cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3816 radeon_emit(ctx_cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3817 }
3818 }
3819
3820 static void
3821 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
3822 struct radv_pipeline *pipeline)
3823 {
3824 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3825 const struct radv_shader_variant *vs =
3826 pipeline->shaders[MESA_SHADER_TESS_EVAL] ?
3827 pipeline->shaders[MESA_SHADER_TESS_EVAL] :
3828 pipeline->shaders[MESA_SHADER_VERTEX];
3829 unsigned vgt_primitiveid_en = 0;
3830 uint32_t vgt_gs_mode = 0;
3831
3832 if (radv_pipeline_has_ngg(pipeline))
3833 return;
3834
3835 if (radv_pipeline_has_gs(pipeline)) {
3836 const struct radv_shader_variant *gs =
3837 pipeline->shaders[MESA_SHADER_GEOMETRY];
3838
3839 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
3840 pipeline->device->physical_device->rad_info.chip_class);
3841 } else if (outinfo->export_prim_id || vs->info.uses_prim_id) {
3842 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
3843 vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(1);
3844 }
3845
3846 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
3847 radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
3848 }
3849
3850 static void
3851 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
3852 struct radeon_cmdbuf *cs,
3853 struct radv_pipeline *pipeline,
3854 struct radv_shader_variant *shader)
3855 {
3856 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3857
3858 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
3859 radeon_emit(cs, va >> 8);
3860 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
3861 radeon_emit(cs, shader->config.rsrc1);
3862 radeon_emit(cs, shader->config.rsrc2);
3863
3864 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3865 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3866 clip_dist_mask = outinfo->clip_dist_mask;
3867 cull_dist_mask = outinfo->cull_dist_mask;
3868 total_mask = clip_dist_mask | cull_dist_mask;
3869 bool misc_vec_ena = outinfo->writes_pointsize ||
3870 outinfo->writes_layer ||
3871 outinfo->writes_viewport_index;
3872 unsigned spi_vs_out_config, nparams;
3873
3874 /* VS is required to export at least one param. */
3875 nparams = MAX2(outinfo->param_exports, 1);
3876 spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
3877
3878 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3879 spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0);
3880 }
3881
3882 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, spi_vs_out_config);
3883
3884 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3885 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3886 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3887 V_02870C_SPI_SHADER_4COMP :
3888 V_02870C_SPI_SHADER_NONE) |
3889 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3890 V_02870C_SPI_SHADER_4COMP :
3891 V_02870C_SPI_SHADER_NONE) |
3892 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3893 V_02870C_SPI_SHADER_4COMP :
3894 V_02870C_SPI_SHADER_NONE));
3895
3896 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3897 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3898 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3899 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3900 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3901 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3902 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3903 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3904 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) |
3905 cull_dist_mask << 8 |
3906 clip_dist_mask);
3907
3908 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
3909 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
3910 outinfo->writes_viewport_index);
3911 }
3912
3913 static void
3914 radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs,
3915 struct radv_pipeline *pipeline,
3916 struct radv_shader_variant *shader)
3917 {
3918 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3919
3920 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
3921 radeon_emit(cs, va >> 8);
3922 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3923 radeon_emit(cs, shader->config.rsrc1);
3924 radeon_emit(cs, shader->config.rsrc2);
3925 }
3926
3927 static void
3928 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs,
3929 struct radv_pipeline *pipeline,
3930 struct radv_shader_variant *shader,
3931 const struct radv_tessellation_state *tess)
3932 {
3933 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3934 uint32_t rsrc2 = shader->config.rsrc2;
3935
3936 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3937 radeon_emit(cs, va >> 8);
3938 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3939
3940 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
3941 if (pipeline->device->physical_device->rad_info.chip_class == GFX7 &&
3942 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
3943 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
3944
3945 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
3946 radeon_emit(cs, shader->config.rsrc1);
3947 radeon_emit(cs, rsrc2);
3948 }
3949
3950 static void
3951 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
3952 struct radeon_cmdbuf *cs,
3953 struct radv_pipeline *pipeline,
3954 struct radv_shader_variant *shader)
3955 {
3956 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3957 gl_shader_stage es_type =
3958 radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
3959 struct radv_shader_variant *es =
3960 es_type == MESA_SHADER_TESS_EVAL ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX];
3961 const struct gfx10_ngg_info *ngg_state = &shader->info.ngg_info;
3962
3963 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
3964 radeon_emit(cs, va >> 8);
3965 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3966 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
3967 radeon_emit(cs, shader->config.rsrc1);
3968 radeon_emit(cs, shader->config.rsrc2);
3969
3970 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3971 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3972 clip_dist_mask = outinfo->clip_dist_mask;
3973 cull_dist_mask = outinfo->cull_dist_mask;
3974 total_mask = clip_dist_mask | cull_dist_mask;
3975 bool misc_vec_ena = outinfo->writes_pointsize ||
3976 outinfo->writes_layer ||
3977 outinfo->writes_viewport_index;
3978 bool es_enable_prim_id = outinfo->export_prim_id ||
3979 (es && es->info.uses_prim_id);
3980 bool break_wave_at_eoi = false;
3981 unsigned ge_cntl;
3982 unsigned nparams;
3983
3984 if (es_type == MESA_SHADER_TESS_EVAL) {
3985 struct radv_shader_variant *gs =
3986 pipeline->shaders[MESA_SHADER_GEOMETRY];
3987
3988 if (es_enable_prim_id || (gs && gs->info.uses_prim_id))
3989 break_wave_at_eoi = true;
3990 }
3991
3992 nparams = MAX2(outinfo->param_exports, 1);
3993 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG,
3994 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
3995 S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0));
3996
3997 radeon_set_context_reg(ctx_cs, R_028708_SPI_SHADER_IDX_FORMAT,
3998 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP));
3999 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
4000 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
4001 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
4002 V_02870C_SPI_SHADER_4COMP :
4003 V_02870C_SPI_SHADER_NONE) |
4004 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
4005 V_02870C_SPI_SHADER_4COMP :
4006 V_02870C_SPI_SHADER_NONE) |
4007 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
4008 V_02870C_SPI_SHADER_4COMP :
4009 V_02870C_SPI_SHADER_NONE));
4010
4011 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
4012 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
4013 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
4014 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
4015 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
4016 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
4017 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
4018 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
4019 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) |
4020 cull_dist_mask << 8 |
4021 clip_dist_mask);
4022
4023 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN,
4024 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
4025 S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo->export_prim_id));
4026
4027 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
4028 ngg_state->vgt_esgs_ring_itemsize);
4029
4030 /* NGG specific registers. */
4031 struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
4032 uint32_t gs_num_invocations = gs ? gs->info.gs.invocations : 1;
4033
4034 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
4035 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state->hw_max_esverts) |
4036 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state->max_gsprims) |
4037 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state->max_gsprims * gs_num_invocations));
4038 radeon_set_context_reg(ctx_cs, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
4039 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state->max_out_verts));
4040 radeon_set_context_reg(ctx_cs, R_028B4C_GE_NGG_SUBGRP_CNTL,
4041 S_028B4C_PRIM_AMP_FACTOR(ngg_state->prim_amp_factor) |
4042 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
4043 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
4044 S_028B90_CNT(gs_num_invocations) |
4045 S_028B90_ENABLE(gs_num_invocations > 1) |
4046 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state->max_vert_out_per_gs_instance));
4047
4048 /* User edge flags are set by the pos exports. If user edge flags are
4049 * not used, we must use hw-generated edge flags and pass them via
4050 * the prim export to prevent drawing lines on internal edges of
4051 * decomposed primitives (such as quads) with polygon mode = lines.
4052 *
4053 * TODO: We should combine hw-generated edge flags with user edge
4054 * flags in the shader.
4055 */
4056 radeon_set_context_reg(ctx_cs, R_028838_PA_CL_NGG_CNTL,
4057 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) &&
4058 !radv_pipeline_has_gs(pipeline)) |
4059 /* Reuse for NGG. */
4060 S_028838_VERTEX_REUSE_DEPTH_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3 ? 30 : 0));
4061
4062 ge_cntl = S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) |
4063 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
4064 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
4065
4066 /* Bug workaround for a possible hang with non-tessellation cases.
4067 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
4068 *
4069 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
4070 */
4071 if (pipeline->device->physical_device->rad_info.chip_class == GFX10 &&
4072 !radv_pipeline_has_tess(pipeline) &&
4073 ngg_state->hw_max_esverts != 256) {
4074 ge_cntl &= C_03096C_VERT_GRP_SIZE;
4075
4076 if (ngg_state->hw_max_esverts > 5) {
4077 ge_cntl |= S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts - 5);
4078 }
4079 }
4080
4081 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, ge_cntl);
4082 }
4083
4084 static void
4085 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
4086 struct radv_pipeline *pipeline,
4087 struct radv_shader_variant *shader,
4088 const struct radv_tessellation_state *tess)
4089 {
4090 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
4091
4092 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4093 unsigned hs_rsrc2 = shader->config.rsrc2;
4094
4095 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4096 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(tess->lds_size);
4097 } else {
4098 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(tess->lds_size);
4099 }
4100
4101 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4102 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
4103 radeon_emit(cs, va >> 8);
4104 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
4105 } else {
4106 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
4107 radeon_emit(cs, va >> 8);
4108 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
4109 }
4110
4111 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
4112 radeon_emit(cs, shader->config.rsrc1);
4113 radeon_emit(cs, hs_rsrc2);
4114 } else {
4115 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
4116 radeon_emit(cs, va >> 8);
4117 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
4118 radeon_emit(cs, shader->config.rsrc1);
4119 radeon_emit(cs, shader->config.rsrc2);
4120 }
4121 }
4122
4123 static void
4124 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *ctx_cs,
4125 struct radeon_cmdbuf *cs,
4126 struct radv_pipeline *pipeline,
4127 const struct radv_tessellation_state *tess)
4128 {
4129 struct radv_shader_variant *vs;
4130
4131 /* Skip shaders merged into HS/GS */
4132 vs = pipeline->shaders[MESA_SHADER_VERTEX];
4133 if (!vs)
4134 return;
4135
4136 if (vs->info.vs.as_ls)
4137 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
4138 else if (vs->info.vs.as_es)
4139 radv_pipeline_generate_hw_es(cs, pipeline, vs);
4140 else if (vs->info.is_ngg)
4141 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, vs);
4142 else
4143 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, vs);
4144 }
4145
4146 static void
4147 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs,
4148 struct radeon_cmdbuf *cs,
4149 struct radv_pipeline *pipeline,
4150 const struct radv_tessellation_state *tess)
4151 {
4152 if (!radv_pipeline_has_tess(pipeline))
4153 return;
4154
4155 struct radv_shader_variant *tes, *tcs;
4156
4157 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
4158 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
4159
4160 if (tes) {
4161 if (tes->info.is_ngg) {
4162 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, tes);
4163 } else if (tes->info.tes.as_es)
4164 radv_pipeline_generate_hw_es(cs, pipeline, tes);
4165 else
4166 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes);
4167 }
4168
4169 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
4170
4171 radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM,
4172 tess->tf_param);
4173
4174 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7)
4175 radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, 2,
4176 tess->ls_hs_config);
4177 else
4178 radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG,
4179 tess->ls_hs_config);
4180
4181 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 &&
4182 !radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
4183 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
4184 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4185 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4186 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4187 }
4188 }
4189
4190 static void
4191 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs,
4192 struct radeon_cmdbuf *cs,
4193 struct radv_pipeline *pipeline,
4194 struct radv_shader_variant *gs)
4195 {
4196 const struct gfx9_gs_info *gs_state = &gs->info.gs_ring_info;
4197 unsigned gs_max_out_vertices;
4198 uint8_t *num_components;
4199 uint8_t max_stream;
4200 unsigned offset;
4201 uint64_t va;
4202
4203 gs_max_out_vertices = gs->info.gs.vertices_out;
4204 max_stream = gs->info.gs.max_stream;
4205 num_components = gs->info.gs.num_stream_output_components;
4206
4207 offset = num_components[0] * gs_max_out_vertices;
4208
4209 radeon_set_context_reg_seq(ctx_cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
4210 radeon_emit(ctx_cs, offset);
4211 if (max_stream >= 1)
4212 offset += num_components[1] * gs_max_out_vertices;
4213 radeon_emit(ctx_cs, offset);
4214 if (max_stream >= 2)
4215 offset += num_components[2] * gs_max_out_vertices;
4216 radeon_emit(ctx_cs, offset);
4217 if (max_stream >= 3)
4218 offset += num_components[3] * gs_max_out_vertices;
4219 radeon_set_context_reg(ctx_cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
4220
4221 radeon_set_context_reg_seq(ctx_cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
4222 radeon_emit(ctx_cs, num_components[0]);
4223 radeon_emit(ctx_cs, (max_stream >= 1) ? num_components[1] : 0);
4224 radeon_emit(ctx_cs, (max_stream >= 2) ? num_components[2] : 0);
4225 radeon_emit(ctx_cs, (max_stream >= 3) ? num_components[3] : 0);
4226
4227 uint32_t gs_num_invocations = gs->info.gs.invocations;
4228 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
4229 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
4230 S_028B90_ENABLE(gs_num_invocations > 0));
4231
4232 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
4233 gs_state->vgt_esgs_ring_itemsize);
4234
4235 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
4236
4237 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4238 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4239 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
4240 radeon_emit(cs, va >> 8);
4241 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
4242 } else {
4243 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
4244 radeon_emit(cs, va >> 8);
4245 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
4246 }
4247
4248 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
4249 radeon_emit(cs, gs->config.rsrc1);
4250 radeon_emit(cs, gs->config.rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
4251
4252 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
4253 radeon_set_context_reg(ctx_cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
4254 } else {
4255 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
4256 radeon_emit(cs, va >> 8);
4257 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
4258 radeon_emit(cs, gs->config.rsrc1);
4259 radeon_emit(cs, gs->config.rsrc2);
4260 }
4261
4262 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, pipeline->gs_copy_shader);
4263 }
4264
4265 static void
4266 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
4267 struct radeon_cmdbuf *cs,
4268 struct radv_pipeline *pipeline)
4269 {
4270 struct radv_shader_variant *gs;
4271
4272 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
4273 if (!gs)
4274 return;
4275
4276 if (gs->info.is_ngg)
4277 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, gs);
4278 else
4279 radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs);
4280
4281 radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT,
4282 gs->info.gs.vertices_out);
4283 }
4284
4285 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade,
4286 bool explicit, bool float16)
4287 {
4288 uint32_t ps_input_cntl;
4289 if (offset <= AC_EXP_PARAM_OFFSET_31) {
4290 ps_input_cntl = S_028644_OFFSET(offset);
4291 if (flat_shade || explicit)
4292 ps_input_cntl |= S_028644_FLAT_SHADE(1);
4293 if (explicit) {
4294 /* Force parameter cache to be read in passthrough
4295 * mode.
4296 */
4297 ps_input_cntl |= S_028644_OFFSET(1 << 5);
4298 }
4299 if (float16) {
4300 ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) |
4301 S_028644_ATTR0_VALID(1);
4302 }
4303 } else {
4304 /* The input is a DEFAULT_VAL constant. */
4305 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
4306 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
4307 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
4308 ps_input_cntl = S_028644_OFFSET(0x20) |
4309 S_028644_DEFAULT_VAL(offset);
4310 }
4311 return ps_input_cntl;
4312 }
4313
4314 static void
4315 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
4316 struct radv_pipeline *pipeline)
4317 {
4318 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4319 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
4320 uint32_t ps_input_cntl[32];
4321
4322 unsigned ps_offset = 0;
4323
4324 if (ps->info.ps.prim_id_input) {
4325 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
4326 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4327 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4328 ++ps_offset;
4329 }
4330 }
4331
4332 if (ps->info.ps.layer_input ||
4333 ps->info.needs_multiview_view_index) {
4334 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
4335 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4336 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4337 else
4338 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false, false);
4339 ++ps_offset;
4340 }
4341
4342 if (ps->info.ps.viewport_index_input) {
4343 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VIEWPORT];
4344 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4345 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4346 else
4347 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false, false);
4348 ++ps_offset;
4349 }
4350
4351 if (ps->info.ps.has_pcoord) {
4352 unsigned val;
4353 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4354 ps_input_cntl[ps_offset] = val;
4355 ps_offset++;
4356 }
4357
4358 if (ps->info.ps.num_input_clips_culls) {
4359 unsigned vs_offset;
4360
4361 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
4362 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4363 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false, false);
4364 ++ps_offset;
4365 }
4366
4367 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
4368 if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
4369 ps->info.ps.num_input_clips_culls > 4) {
4370 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false, false);
4371 ++ps_offset;
4372 }
4373 }
4374
4375 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.ps.input_mask; ++i) {
4376 unsigned vs_offset;
4377 bool flat_shade;
4378 bool explicit;
4379 bool float16;
4380 if (!(ps->info.ps.input_mask & (1u << i)))
4381 continue;
4382
4383 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
4384 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
4385 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
4386 ++ps_offset;
4387 continue;
4388 }
4389
4390 flat_shade = !!(ps->info.ps.flat_shaded_mask & (1u << ps_offset));
4391 explicit = !!(ps->info.ps.explicit_shaded_mask & (1u << ps_offset));
4392 float16 = !!(ps->info.ps.float16_shaded_mask & (1u << ps_offset));
4393
4394 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade, explicit, float16);
4395 ++ps_offset;
4396 }
4397
4398 if (ps_offset) {
4399 radeon_set_context_reg_seq(ctx_cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
4400 for (unsigned i = 0; i < ps_offset; i++) {
4401 radeon_emit(ctx_cs, ps_input_cntl[i]);
4402 }
4403 }
4404 }
4405
4406 static uint32_t
4407 radv_compute_db_shader_control(const struct radv_device *device,
4408 const struct radv_pipeline *pipeline,
4409 const struct radv_shader_variant *ps)
4410 {
4411 unsigned conservative_z_export = V_02880C_EXPORT_ANY_Z;
4412 unsigned z_order;
4413 if (ps->info.ps.early_fragment_test || !ps->info.ps.writes_memory)
4414 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
4415 else
4416 z_order = V_02880C_LATE_Z;
4417
4418 if (ps->info.ps.depth_layout == FRAG_DEPTH_LAYOUT_GREATER)
4419 conservative_z_export = V_02880C_EXPORT_GREATER_THAN_Z;
4420 else if (ps->info.ps.depth_layout == FRAG_DEPTH_LAYOUT_LESS)
4421 conservative_z_export = V_02880C_EXPORT_LESS_THAN_Z;
4422
4423 bool disable_rbplus = device->physical_device->rad_info.has_rbplus &&
4424 !device->physical_device->rad_info.rbplus_allowed;
4425
4426 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4427 * but this appears to break Project Cars (DXVK). See
4428 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4429 */
4430 bool mask_export_enable = ps->info.ps.writes_sample_mask;
4431
4432 return S_02880C_Z_EXPORT_ENABLE(ps->info.ps.writes_z) |
4433 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.ps.writes_stencil) |
4434 S_02880C_KILL_ENABLE(!!ps->info.ps.can_discard) |
4435 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
4436 S_02880C_CONSERVATIVE_Z_EXPORT(conservative_z_export) |
4437 S_02880C_Z_ORDER(z_order) |
4438 S_02880C_DEPTH_BEFORE_SHADER(ps->info.ps.early_fragment_test) |
4439 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps->info.ps.post_depth_coverage) |
4440 S_02880C_EXEC_ON_HIER_FAIL(ps->info.ps.writes_memory) |
4441 S_02880C_EXEC_ON_NOOP(ps->info.ps.writes_memory) |
4442 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
4443 }
4444
4445 static void
4446 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs,
4447 struct radeon_cmdbuf *cs,
4448 struct radv_pipeline *pipeline)
4449 {
4450 struct radv_shader_variant *ps;
4451 uint64_t va;
4452 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
4453
4454 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4455 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
4456
4457 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
4458 radeon_emit(cs, va >> 8);
4459 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
4460 radeon_emit(cs, ps->config.rsrc1);
4461 radeon_emit(cs, ps->config.rsrc2);
4462
4463 radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL,
4464 radv_compute_db_shader_control(pipeline->device,
4465 pipeline, ps));
4466
4467 radeon_set_context_reg(ctx_cs, R_0286CC_SPI_PS_INPUT_ENA,
4468 ps->config.spi_ps_input_ena);
4469
4470 radeon_set_context_reg(ctx_cs, R_0286D0_SPI_PS_INPUT_ADDR,
4471 ps->config.spi_ps_input_addr);
4472
4473 radeon_set_context_reg(ctx_cs, R_0286D8_SPI_PS_IN_CONTROL,
4474 S_0286D8_NUM_INTERP(ps->info.ps.num_interp) |
4475 S_0286D8_PS_W32_EN(ps->info.wave_size == 32));
4476
4477 radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
4478
4479 radeon_set_context_reg(ctx_cs, R_028710_SPI_SHADER_Z_FORMAT,
4480 ac_get_spi_shader_z_format(ps->info.ps.writes_z,
4481 ps->info.ps.writes_stencil,
4482 ps->info.ps.writes_sample_mask));
4483
4484 if (pipeline->device->dfsm_allowed) {
4485 /* optimise this? */
4486 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4487 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
4488 }
4489 }
4490
4491 static void
4492 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs,
4493 struct radv_pipeline *pipeline)
4494 {
4495 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4496 pipeline->device->physical_device->rad_info.chip_class >= GFX10)
4497 return;
4498
4499 unsigned vtx_reuse_depth = 30;
4500 if (radv_pipeline_has_tess(pipeline) &&
4501 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
4502 vtx_reuse_depth = 14;
4503 }
4504 radeon_set_context_reg(ctx_cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
4505 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
4506 }
4507
4508 static uint32_t
4509 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
4510 {
4511 uint32_t stages = 0;
4512 if (radv_pipeline_has_tess(pipeline)) {
4513 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
4514 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4515
4516 if (radv_pipeline_has_gs(pipeline))
4517 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
4518 S_028B54_GS_EN(1);
4519 else if (radv_pipeline_has_ngg(pipeline))
4520 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
4521 else
4522 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
4523 } else if (radv_pipeline_has_gs(pipeline)) {
4524 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
4525 S_028B54_GS_EN(1);
4526 } else if (radv_pipeline_has_ngg(pipeline)) {
4527 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
4528 }
4529
4530 if (radv_pipeline_has_ngg(pipeline)) {
4531 stages |= S_028B54_PRIMGEN_EN(1);
4532 if (pipeline->streamout_shader)
4533 stages |= S_028B54_NGG_WAVE_ID_EN(1);
4534 if (radv_pipeline_has_ngg_passthrough(pipeline))
4535 stages |= S_028B54_PRIMGEN_PASSTHRU_EN(1);
4536 } else if (radv_pipeline_has_gs(pipeline)) {
4537 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
4538 }
4539
4540 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
4541 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4542
4543 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4544 uint8_t hs_size = 64, gs_size = 64, vs_size = 64;
4545
4546 if (radv_pipeline_has_tess(pipeline))
4547 hs_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.wave_size;
4548
4549 if (pipeline->shaders[MESA_SHADER_GEOMETRY]) {
4550 vs_size = gs_size = pipeline->shaders[MESA_SHADER_GEOMETRY]->info.wave_size;
4551 if (pipeline->gs_copy_shader)
4552 vs_size = pipeline->gs_copy_shader->info.wave_size;
4553 } else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
4554 vs_size = pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.wave_size;
4555 else if (pipeline->shaders[MESA_SHADER_VERTEX])
4556 vs_size = pipeline->shaders[MESA_SHADER_VERTEX]->info.wave_size;
4557
4558 if (radv_pipeline_has_ngg(pipeline))
4559 gs_size = vs_size;
4560
4561 /* legacy GS only supports Wave64 */
4562 stages |= S_028B54_HS_W32_EN(hs_size == 32 ? 1 : 0) |
4563 S_028B54_GS_W32_EN(gs_size == 32 ? 1 : 0) |
4564 S_028B54_VS_W32_EN(vs_size == 32 ? 1 : 0);
4565 }
4566
4567 return stages;
4568 }
4569
4570 static uint32_t
4571 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
4572 {
4573 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
4574 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
4575
4576 if (!discard_rectangle_info)
4577 return 0xffff;
4578
4579 unsigned mask = 0;
4580
4581 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
4582 /* Interpret i as a bitmask, and then set the bit in the mask if
4583 * that combination of rectangles in which the pixel is contained
4584 * should pass the cliprect test. */
4585 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
4586
4587 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
4588 !relevant_subset)
4589 continue;
4590
4591 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
4592 relevant_subset)
4593 continue;
4594
4595 mask |= 1u << i;
4596 }
4597
4598 return mask;
4599 }
4600
4601 static void
4602 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf *ctx_cs,
4603 struct radv_pipeline *pipeline,
4604 const struct radv_tessellation_state *tess)
4605 {
4606 bool break_wave_at_eoi = false;
4607 unsigned primgroup_size;
4608 unsigned vertgroup_size = 256; /* 256 = disable vertex grouping */
4609
4610 if (radv_pipeline_has_tess(pipeline)) {
4611 primgroup_size = tess->num_patches; /* must be a multiple of NUM_PATCHES */
4612 } else if (radv_pipeline_has_gs(pipeline)) {
4613 const struct gfx9_gs_info *gs_state =
4614 &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs_ring_info;
4615 unsigned vgt_gs_onchip_cntl = gs_state->vgt_gs_onchip_cntl;
4616 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
4617 } else {
4618 primgroup_size = 128; /* recommended without a GS and tess */
4619 }
4620
4621 if (radv_pipeline_has_tess(pipeline)) {
4622 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4623 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4624 break_wave_at_eoi = true;
4625 }
4626
4627 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL,
4628 S_03096C_PRIM_GRP_SIZE(primgroup_size) |
4629 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
4630 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4631 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi));
4632 }
4633
4634 static void
4635 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
4636 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4637 const struct radv_graphics_pipeline_create_info *extra,
4638 const struct radv_blend_state *blend,
4639 const struct radv_tessellation_state *tess,
4640 unsigned gs_out)
4641 {
4642 struct radeon_cmdbuf *ctx_cs = &pipeline->ctx_cs;
4643 struct radeon_cmdbuf *cs = &pipeline->cs;
4644
4645 cs->max_dw = 64;
4646 ctx_cs->max_dw = 256;
4647 cs->buf = malloc(4 * (cs->max_dw + ctx_cs->max_dw));
4648 ctx_cs->buf = cs->buf + cs->max_dw;
4649
4650 radv_pipeline_generate_depth_stencil_state(ctx_cs, pipeline, pCreateInfo, extra);
4651 radv_pipeline_generate_blend_state(ctx_cs, pipeline, blend);
4652 radv_pipeline_generate_raster_state(ctx_cs, pipeline, pCreateInfo);
4653 radv_pipeline_generate_multisample_state(ctx_cs, pipeline);
4654 radv_pipeline_generate_vgt_gs_mode(ctx_cs, pipeline);
4655 radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline, tess);
4656 radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline, tess);
4657 radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline);
4658 radv_pipeline_generate_fragment_shader(ctx_cs, cs, pipeline);
4659 radv_pipeline_generate_ps_inputs(ctx_cs, pipeline);
4660 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline);
4661 radv_pipeline_generate_binning_state(ctx_cs, pipeline, pCreateInfo, blend);
4662
4663 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && !radv_pipeline_has_ngg(pipeline))
4664 gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline, tess);
4665
4666 radeon_set_context_reg(ctx_cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
4667 radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
4668
4669 radeon_set_context_reg(ctx_cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
4670
4671 pipeline->ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4);
4672
4673 assert(ctx_cs->cdw <= ctx_cs->max_dw);
4674 assert(cs->cdw <= cs->max_dw);
4675 }
4676
4677 static struct radv_ia_multi_vgt_param_helpers
4678 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
4679 const struct radv_tessellation_state *tess)
4680 {
4681 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
4682 const struct radv_device *device = pipeline->device;
4683
4684 if (radv_pipeline_has_tess(pipeline))
4685 ia_multi_vgt_param.primgroup_size = tess->num_patches;
4686 else if (radv_pipeline_has_gs(pipeline))
4687 ia_multi_vgt_param.primgroup_size = 64;
4688 else
4689 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
4690
4691 /* GS requirement. */
4692 ia_multi_vgt_param.partial_es_wave = false;
4693 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= GFX8)
4694 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
4695 ia_multi_vgt_param.partial_es_wave = true;
4696
4697 ia_multi_vgt_param.ia_switch_on_eoi = false;
4698 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input)
4699 ia_multi_vgt_param.ia_switch_on_eoi = true;
4700 if (radv_pipeline_has_gs(pipeline) &&
4701 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.uses_prim_id)
4702 ia_multi_vgt_param.ia_switch_on_eoi = true;
4703 if (radv_pipeline_has_tess(pipeline)) {
4704 /* SWITCH_ON_EOI must be set if PrimID is used. */
4705 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4706 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4707 ia_multi_vgt_param.ia_switch_on_eoi = true;
4708 }
4709
4710 ia_multi_vgt_param.partial_vs_wave = false;
4711 if (radv_pipeline_has_tess(pipeline)) {
4712 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4713 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
4714 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
4715 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
4716 radv_pipeline_has_gs(pipeline))
4717 ia_multi_vgt_param.partial_vs_wave = true;
4718 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4719 if (device->physical_device->rad_info.has_distributed_tess) {
4720 if (radv_pipeline_has_gs(pipeline)) {
4721 if (device->physical_device->rad_info.chip_class <= GFX8)
4722 ia_multi_vgt_param.partial_es_wave = true;
4723 } else {
4724 ia_multi_vgt_param.partial_vs_wave = true;
4725 }
4726 }
4727 }
4728
4729 if (radv_pipeline_has_gs(pipeline)) {
4730 /* On these chips there is the possibility of a hang if the
4731 * pipeline uses a GS and partial_vs_wave is not set.
4732 *
4733 * This mostly does not hit 4-SE chips, as those typically set
4734 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4735 * with GS due to another workaround.
4736 *
4737 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4738 */
4739 if (device->physical_device->rad_info.family == CHIP_TONGA ||
4740 device->physical_device->rad_info.family == CHIP_FIJI ||
4741 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
4742 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
4743 device->physical_device->rad_info.family == CHIP_POLARIS12 ||
4744 device->physical_device->rad_info.family == CHIP_VEGAM) {
4745 ia_multi_vgt_param.partial_vs_wave = true;
4746 }
4747 }
4748
4749 ia_multi_vgt_param.base =
4750 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
4751 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4752 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == GFX8 ? 2 : 0) |
4753 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
4754 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
4755
4756 return ia_multi_vgt_param;
4757 }
4758
4759
4760 static void
4761 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
4762 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4763 {
4764 const VkPipelineVertexInputStateCreateInfo *vi_info =
4765 pCreateInfo->pVertexInputState;
4766
4767 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
4768 const VkVertexInputBindingDescription *desc =
4769 &vi_info->pVertexBindingDescriptions[i];
4770
4771 pipeline->binding_stride[desc->binding] = desc->stride;
4772 pipeline->num_vertex_bindings =
4773 MAX2(pipeline->num_vertex_bindings, desc->binding + 1);
4774 }
4775 }
4776
4777 static struct radv_shader_variant *
4778 radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline)
4779 {
4780 int i;
4781
4782 for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) {
4783 struct radv_shader_variant *shader =
4784 radv_get_shader(pipeline, i);
4785
4786 if (shader && shader->info.so.num_outputs > 0)
4787 return shader;
4788 }
4789
4790 return NULL;
4791 }
4792
4793 static VkResult
4794 radv_pipeline_init(struct radv_pipeline *pipeline,
4795 struct radv_device *device,
4796 struct radv_pipeline_cache *cache,
4797 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4798 const struct radv_graphics_pipeline_create_info *extra)
4799 {
4800 VkResult result;
4801 bool has_view_index = false;
4802
4803 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
4804 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
4805 if (subpass->view_mask)
4806 has_view_index = true;
4807
4808 pipeline->device = device;
4809 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
4810 assert(pipeline->layout);
4811
4812 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
4813
4814 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
4815 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
4816 radv_init_feedback(creation_feedback);
4817
4818 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
4819
4820 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
4821 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
4822 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
4823 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
4824 pStages[stage] = &pCreateInfo->pStages[i];
4825 if(creation_feedback)
4826 stage_feedbacks[stage] = &creation_feedback->pPipelineStageCreationFeedbacks[i];
4827 }
4828
4829 struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index);
4830
4831 result = radv_create_shaders(pipeline, device, cache, &key, pStages,
4832 pCreateInfo->flags, pipeline_feedback,
4833 stage_feedbacks);
4834 if (result != VK_SUCCESS)
4835 return result;
4836
4837 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
4838 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
4839 uint32_t gs_out;
4840
4841 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
4842
4843 if (radv_pipeline_has_gs(pipeline)) {
4844 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
4845 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4846 } else if (radv_pipeline_has_tess(pipeline)) {
4847 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode)
4848 gs_out = V_028A6C_OUTPRIM_TYPE_POINTLIST;
4849 else
4850 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.primitive_mode);
4851 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4852 } else {
4853 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
4854 }
4855 if (extra && extra->use_rectlist) {
4856 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4857 pipeline->graphics.can_use_guardband = true;
4858 if (radv_pipeline_has_ngg(pipeline))
4859 gs_out = V_028A6C_VGT_OUT_RECT_V0;
4860 }
4861 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
4862
4863 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo, extra);
4864
4865 /* Ensure that some export memory is always allocated, for two reasons:
4866 *
4867 * 1) Correctness: The hardware ignores the EXEC mask if no export
4868 * memory is allocated, so KILL and alpha test do not work correctly
4869 * without this.
4870 * 2) Performance: Every shader needs at least a NULL export, even when
4871 * it writes no color/depth output. The NULL export instruction
4872 * stalls without this setting.
4873 *
4874 * Don't add this to CB_SHADER_MASK.
4875 *
4876 * GFX10 supports pixel shaders without exports by setting both the
4877 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
4878 * instructions if any are present.
4879 */
4880 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4881 if ((pipeline->device->physical_device->rad_info.chip_class <= GFX9 ||
4882 ps->info.ps.can_discard) &&
4883 !blend.spi_shader_col_format) {
4884 if (!ps->info.ps.writes_z &&
4885 !ps->info.ps.writes_stencil &&
4886 !ps->info.ps.writes_sample_mask)
4887 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
4888 }
4889
4890 blend.cb_shader_mask = ps->info.ps.cb_shader_mask;
4891
4892 if (extra &&
4893 (extra->custom_blend_mode == V_028808_CB_ELIMINATE_FAST_CLEAR ||
4894 extra->custom_blend_mode == V_028808_CB_FMASK_DECOMPRESS ||
4895 extra->custom_blend_mode == V_028808_CB_DCC_DECOMPRESS ||
4896 extra->custom_blend_mode == V_028808_CB_RESOLVE)) {
4897 /* According to the CB spec states, CB_SHADER_MASK should be
4898 * set to enable writes to all four channels of MRT0.
4899 */
4900 blend.cb_shader_mask = 0xf;
4901 }
4902
4903 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
4904 if (pipeline->shaders[i]) {
4905 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
4906 }
4907 }
4908
4909 if (radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
4910 struct radv_shader_variant *gs =
4911 pipeline->shaders[MESA_SHADER_GEOMETRY];
4912
4913 calculate_gs_ring_sizes(pipeline, &gs->info.gs_ring_info);
4914 }
4915
4916 struct radv_tessellation_state tess = {0};
4917 if (radv_pipeline_has_tess(pipeline)) {
4918 pipeline->graphics.tess_patch_control_points =
4919 pCreateInfo->pTessellationState->patchControlPoints;
4920 tess = calculate_tess_state(pipeline, pCreateInfo);
4921 }
4922
4923 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess);
4924
4925 radv_compute_vertex_input_state(pipeline, pCreateInfo);
4926
4927 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
4928 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
4929
4930 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
4931 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
4932 if (loc->sgpr_idx != -1) {
4933 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
4934 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
4935 if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id)
4936 pipeline->graphics.vtx_emit_num = 3;
4937 else
4938 pipeline->graphics.vtx_emit_num = 2;
4939 }
4940
4941 /* Find the last vertex shader stage that eventually uses streamout. */
4942 pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline);
4943
4944 result = radv_pipeline_scratch_init(device, pipeline);
4945 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, gs_out);
4946
4947 return result;
4948 }
4949
4950 VkResult
4951 radv_graphics_pipeline_create(
4952 VkDevice _device,
4953 VkPipelineCache _cache,
4954 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4955 const struct radv_graphics_pipeline_create_info *extra,
4956 const VkAllocationCallbacks *pAllocator,
4957 VkPipeline *pPipeline)
4958 {
4959 RADV_FROM_HANDLE(radv_device, device, _device);
4960 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
4961 struct radv_pipeline *pipeline;
4962 VkResult result;
4963
4964 pipeline = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8,
4965 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4966 if (pipeline == NULL)
4967 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4968
4969 vk_object_base_init(&device->vk, &pipeline->base,
4970 VK_OBJECT_TYPE_PIPELINE);
4971
4972 result = radv_pipeline_init(pipeline, device, cache,
4973 pCreateInfo, extra);
4974 if (result != VK_SUCCESS) {
4975 radv_pipeline_destroy(device, pipeline, pAllocator);
4976 return result;
4977 }
4978
4979 *pPipeline = radv_pipeline_to_handle(pipeline);
4980
4981 return VK_SUCCESS;
4982 }
4983
4984 VkResult radv_CreateGraphicsPipelines(
4985 VkDevice _device,
4986 VkPipelineCache pipelineCache,
4987 uint32_t count,
4988 const VkGraphicsPipelineCreateInfo* pCreateInfos,
4989 const VkAllocationCallbacks* pAllocator,
4990 VkPipeline* pPipelines)
4991 {
4992 VkResult result = VK_SUCCESS;
4993 unsigned i = 0;
4994
4995 for (; i < count; i++) {
4996 VkResult r;
4997 r = radv_graphics_pipeline_create(_device,
4998 pipelineCache,
4999 &pCreateInfos[i],
5000 NULL, pAllocator, &pPipelines[i]);
5001 if (r != VK_SUCCESS) {
5002 result = r;
5003 pPipelines[i] = VK_NULL_HANDLE;
5004
5005 if (pCreateInfos[i].flags & VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT)
5006 break;
5007 }
5008 }
5009
5010 for (; i < count; ++i)
5011 pPipelines[i] = VK_NULL_HANDLE;
5012
5013 return result;
5014 }
5015
5016
5017 static void
5018 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
5019 {
5020 struct radv_shader_variant *compute_shader;
5021 struct radv_device *device = pipeline->device;
5022 unsigned threads_per_threadgroup;
5023 unsigned threadgroups_per_cu = 1;
5024 unsigned waves_per_threadgroup;
5025 unsigned max_waves_per_sh = 0;
5026 uint64_t va;
5027
5028 pipeline->cs.max_dw = device->physical_device->rad_info.chip_class >= GFX10 ? 22 : 20;
5029 pipeline->cs.buf = malloc(pipeline->cs.max_dw * 4);
5030
5031 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5032 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
5033
5034 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
5035 radeon_emit(&pipeline->cs, va >> 8);
5036 radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40));
5037
5038 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
5039 radeon_emit(&pipeline->cs, compute_shader->config.rsrc1);
5040 radeon_emit(&pipeline->cs, compute_shader->config.rsrc2);
5041 if (device->physical_device->rad_info.chip_class >= GFX10) {
5042 radeon_set_sh_reg(&pipeline->cs, R_00B8A0_COMPUTE_PGM_RSRC3, compute_shader->config.rsrc3);
5043 }
5044
5045 /* Calculate best compute resource limits. */
5046 threads_per_threadgroup = compute_shader->info.cs.block_size[0] *
5047 compute_shader->info.cs.block_size[1] *
5048 compute_shader->info.cs.block_size[2];
5049 waves_per_threadgroup = DIV_ROUND_UP(threads_per_threadgroup,
5050 compute_shader->info.wave_size);
5051
5052 if (device->physical_device->rad_info.chip_class >= GFX10 &&
5053 waves_per_threadgroup == 1)
5054 threadgroups_per_cu = 2;
5055
5056 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
5057 ac_get_compute_resource_limits(&device->physical_device->rad_info,
5058 waves_per_threadgroup,
5059 max_waves_per_sh,
5060 threadgroups_per_cu));
5061
5062 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5063 radeon_emit(&pipeline->cs,
5064 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
5065 radeon_emit(&pipeline->cs,
5066 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
5067 radeon_emit(&pipeline->cs,
5068 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
5069
5070 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
5071 }
5072
5073 static struct radv_pipeline_key
5074 radv_generate_compute_pipeline_key(struct radv_pipeline *pipeline,
5075 const VkComputePipelineCreateInfo *pCreateInfo)
5076 {
5077 const VkPipelineShaderStageCreateInfo *stage = &pCreateInfo->stage;
5078 struct radv_pipeline_key key;
5079 memset(&key, 0, sizeof(key));
5080
5081 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
5082 key.optimisations_disabled = 1;
5083
5084 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT *subgroup_size =
5085 vk_find_struct_const(stage->pNext,
5086 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT);
5087
5088 if (subgroup_size) {
5089 assert(subgroup_size->requiredSubgroupSize == 32 ||
5090 subgroup_size->requiredSubgroupSize == 64);
5091 key.compute_subgroup_size = subgroup_size->requiredSubgroupSize;
5092 }
5093
5094 return key;
5095 }
5096
5097 static VkResult radv_compute_pipeline_create(
5098 VkDevice _device,
5099 VkPipelineCache _cache,
5100 const VkComputePipelineCreateInfo* pCreateInfo,
5101 const VkAllocationCallbacks* pAllocator,
5102 VkPipeline* pPipeline)
5103 {
5104 RADV_FROM_HANDLE(radv_device, device, _device);
5105 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
5106 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
5107 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
5108 struct radv_pipeline *pipeline;
5109 VkResult result;
5110
5111 pipeline = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8,
5112 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5113 if (pipeline == NULL)
5114 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5115
5116 vk_object_base_init(&device->vk, &pipeline->base,
5117 VK_OBJECT_TYPE_PIPELINE);
5118
5119 pipeline->device = device;
5120 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
5121 assert(pipeline->layout);
5122
5123 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
5124 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
5125 radv_init_feedback(creation_feedback);
5126
5127 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
5128 if (creation_feedback)
5129 stage_feedbacks[MESA_SHADER_COMPUTE] = &creation_feedback->pPipelineStageCreationFeedbacks[0];
5130
5131 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
5132
5133 struct radv_pipeline_key key =
5134 radv_generate_compute_pipeline_key(pipeline, pCreateInfo);
5135
5136 result = radv_create_shaders(pipeline, device, cache, &key, pStages,
5137 pCreateInfo->flags, pipeline_feedback,
5138 stage_feedbacks);
5139 if (result != VK_SUCCESS) {
5140 radv_pipeline_destroy(device, pipeline, pAllocator);
5141 return result;
5142 }
5143
5144 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
5145 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
5146 result = radv_pipeline_scratch_init(device, pipeline);
5147 if (result != VK_SUCCESS) {
5148 radv_pipeline_destroy(device, pipeline, pAllocator);
5149 return result;
5150 }
5151
5152 radv_compute_generate_pm4(pipeline);
5153
5154 *pPipeline = radv_pipeline_to_handle(pipeline);
5155
5156 return VK_SUCCESS;
5157 }
5158
5159 VkResult radv_CreateComputePipelines(
5160 VkDevice _device,
5161 VkPipelineCache pipelineCache,
5162 uint32_t count,
5163 const VkComputePipelineCreateInfo* pCreateInfos,
5164 const VkAllocationCallbacks* pAllocator,
5165 VkPipeline* pPipelines)
5166 {
5167 VkResult result = VK_SUCCESS;
5168
5169 unsigned i = 0;
5170 for (; i < count; i++) {
5171 VkResult r;
5172 r = radv_compute_pipeline_create(_device, pipelineCache,
5173 &pCreateInfos[i],
5174 pAllocator, &pPipelines[i]);
5175 if (r != VK_SUCCESS) {
5176 result = r;
5177 pPipelines[i] = VK_NULL_HANDLE;
5178
5179 if (pCreateInfos[i].flags & VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT)
5180 break;
5181 }
5182 }
5183
5184 for (; i < count; ++i)
5185 pPipelines[i] = VK_NULL_HANDLE;
5186
5187 return result;
5188 }
5189
5190
5191 static uint32_t radv_get_executable_count(const struct radv_pipeline *pipeline)
5192 {
5193 uint32_t ret = 0;
5194 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5195 if (!pipeline->shaders[i])
5196 continue;
5197
5198 if (i == MESA_SHADER_GEOMETRY &&
5199 !radv_pipeline_has_ngg(pipeline)) {
5200 ret += 2u;
5201 } else {
5202 ret += 1u;
5203 }
5204
5205 }
5206 return ret;
5207 }
5208
5209 static struct radv_shader_variant *
5210 radv_get_shader_from_executable_index(const struct radv_pipeline *pipeline, int index, gl_shader_stage *stage)
5211 {
5212 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5213 if (!pipeline->shaders[i])
5214 continue;
5215 if (!index) {
5216 *stage = i;
5217 return pipeline->shaders[i];
5218 }
5219
5220 --index;
5221
5222 if (i == MESA_SHADER_GEOMETRY &&
5223 !radv_pipeline_has_ngg(pipeline)) {
5224 if (!index) {
5225 *stage = i;
5226 return pipeline->gs_copy_shader;
5227 }
5228 --index;
5229 }
5230 }
5231
5232 *stage = -1;
5233 return NULL;
5234 }
5235
5236 /* Basically strlcpy (which does not exist on linux) specialized for
5237 * descriptions. */
5238 static void desc_copy(char *desc, const char *src) {
5239 int len = strlen(src);
5240 assert(len < VK_MAX_DESCRIPTION_SIZE);
5241 memcpy(desc, src, len);
5242 memset(desc + len, 0, VK_MAX_DESCRIPTION_SIZE - len);
5243 }
5244
5245 VkResult radv_GetPipelineExecutablePropertiesKHR(
5246 VkDevice _device,
5247 const VkPipelineInfoKHR* pPipelineInfo,
5248 uint32_t* pExecutableCount,
5249 VkPipelineExecutablePropertiesKHR* pProperties)
5250 {
5251 RADV_FROM_HANDLE(radv_pipeline, pipeline, pPipelineInfo->pipeline);
5252 const uint32_t total_count = radv_get_executable_count(pipeline);
5253
5254 if (!pProperties) {
5255 *pExecutableCount = total_count;
5256 return VK_SUCCESS;
5257 }
5258
5259 const uint32_t count = MIN2(total_count, *pExecutableCount);
5260 for (unsigned i = 0, executable_idx = 0;
5261 i < MESA_SHADER_STAGES && executable_idx < count; ++i) {
5262 if (!pipeline->shaders[i])
5263 continue;
5264 pProperties[executable_idx].stages = mesa_to_vk_shader_stage(i);
5265 const char *name = NULL;
5266 const char *description = NULL;
5267 switch(i) {
5268 case MESA_SHADER_VERTEX:
5269 name = "Vertex Shader";
5270 description = "Vulkan Vertex Shader";
5271 break;
5272 case MESA_SHADER_TESS_CTRL:
5273 if (!pipeline->shaders[MESA_SHADER_VERTEX]) {
5274 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5275 name = "Vertex + Tessellation Control Shaders";
5276 description = "Combined Vulkan Vertex and Tessellation Control Shaders";
5277 } else {
5278 name = "Tessellation Control Shader";
5279 description = "Vulkan Tessellation Control Shader";
5280 }
5281 break;
5282 case MESA_SHADER_TESS_EVAL:
5283 name = "Tessellation Evaluation Shader";
5284 description = "Vulkan Tessellation Evaluation Shader";
5285 break;
5286 case MESA_SHADER_GEOMETRY:
5287 if (radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
5288 pProperties[executable_idx].stages |= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT;
5289 name = "Tessellation Evaluation + Geometry Shaders";
5290 description = "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5291 } else if (!radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_VERTEX]) {
5292 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5293 name = "Vertex + Geometry Shader";
5294 description = "Combined Vulkan Vertex and Geometry Shaders";
5295 } else {
5296 name = "Geometry Shader";
5297 description = "Vulkan Geometry Shader";
5298 }
5299 break;
5300 case MESA_SHADER_FRAGMENT:
5301 name = "Fragment Shader";
5302 description = "Vulkan Fragment Shader";
5303 break;
5304 case MESA_SHADER_COMPUTE:
5305 name = "Compute Shader";
5306 description = "Vulkan Compute Shader";
5307 break;
5308 }
5309
5310 pProperties[executable_idx].subgroupSize = pipeline->shaders[i]->info.wave_size;
5311 desc_copy(pProperties[executable_idx].name, name);
5312 desc_copy(pProperties[executable_idx].description, description);
5313
5314 ++executable_idx;
5315 if (i == MESA_SHADER_GEOMETRY &&
5316 !radv_pipeline_has_ngg(pipeline)) {
5317 assert(pipeline->gs_copy_shader);
5318 if (executable_idx >= count)
5319 break;
5320
5321 pProperties[executable_idx].stages = VK_SHADER_STAGE_GEOMETRY_BIT;
5322 pProperties[executable_idx].subgroupSize = 64;
5323 desc_copy(pProperties[executable_idx].name, "GS Copy Shader");
5324 desc_copy(pProperties[executable_idx].description,
5325 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5326
5327 ++executable_idx;
5328 }
5329 }
5330
5331 VkResult result = *pExecutableCount < total_count ? VK_INCOMPLETE : VK_SUCCESS;
5332 *pExecutableCount = count;
5333 return result;
5334 }
5335
5336 VkResult radv_GetPipelineExecutableStatisticsKHR(
5337 VkDevice _device,
5338 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5339 uint32_t* pStatisticCount,
5340 VkPipelineExecutableStatisticKHR* pStatistics)
5341 {
5342 RADV_FROM_HANDLE(radv_device, device, _device);
5343 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5344 gl_shader_stage stage;
5345 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5346
5347 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
5348 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
5349 unsigned max_waves = radv_get_max_waves(device, shader, stage);
5350
5351 VkPipelineExecutableStatisticKHR *s = pStatistics;
5352 VkPipelineExecutableStatisticKHR *end = s + (pStatistics ? *pStatisticCount : 0);
5353 VkResult result = VK_SUCCESS;
5354
5355 if (s < end) {
5356 desc_copy(s->name, "SGPRs");
5357 desc_copy(s->description, "Number of SGPR registers allocated per subgroup");
5358 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5359 s->value.u64 = shader->config.num_sgprs;
5360 }
5361 ++s;
5362
5363 if (s < end) {
5364 desc_copy(s->name, "VGPRs");
5365 desc_copy(s->description, "Number of VGPR registers allocated per subgroup");
5366 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5367 s->value.u64 = shader->config.num_vgprs;
5368 }
5369 ++s;
5370
5371 if (s < end) {
5372 desc_copy(s->name, "Spilled SGPRs");
5373 desc_copy(s->description, "Number of SGPR registers spilled per subgroup");
5374 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5375 s->value.u64 = shader->config.spilled_sgprs;
5376 }
5377 ++s;
5378
5379 if (s < end) {
5380 desc_copy(s->name, "Spilled VGPRs");
5381 desc_copy(s->description, "Number of VGPR registers spilled per subgroup");
5382 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5383 s->value.u64 = shader->config.spilled_vgprs;
5384 }
5385 ++s;
5386
5387 if (s < end) {
5388 desc_copy(s->name, "PrivMem VGPRs");
5389 desc_copy(s->description, "Number of VGPRs stored in private memory per subgroup");
5390 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5391 s->value.u64 = shader->info.private_mem_vgprs;
5392 }
5393 ++s;
5394
5395 if (s < end) {
5396 desc_copy(s->name, "Code size");
5397 desc_copy(s->description, "Code size in bytes");
5398 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5399 s->value.u64 = shader->exec_size;
5400 }
5401 ++s;
5402
5403 if (s < end) {
5404 desc_copy(s->name, "LDS size");
5405 desc_copy(s->description, "LDS size in bytes per workgroup");
5406 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5407 s->value.u64 = shader->config.lds_size * lds_increment;
5408 }
5409 ++s;
5410
5411 if (s < end) {
5412 desc_copy(s->name, "Scratch size");
5413 desc_copy(s->description, "Private memory in bytes per subgroup");
5414 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5415 s->value.u64 = shader->config.scratch_bytes_per_wave;
5416 }
5417 ++s;
5418
5419 if (s < end) {
5420 desc_copy(s->name, "Subgroups per SIMD");
5421 desc_copy(s->description, "The maximum number of subgroups in flight on a SIMD unit");
5422 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5423 s->value.u64 = max_waves;
5424 }
5425 ++s;
5426
5427 if (shader->statistics) {
5428 for (unsigned i = 0; i < shader->statistics->count; i++) {
5429 struct radv_compiler_statistic_info *info = &shader->statistics->infos[i];
5430 uint32_t value = shader->statistics->values[i];
5431 if (s < end) {
5432 desc_copy(s->name, info->name);
5433 desc_copy(s->description, info->desc);
5434 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5435 s->value.u64 = value;
5436 }
5437 ++s;
5438 }
5439 }
5440
5441 if (!pStatistics)
5442 *pStatisticCount = s - pStatistics;
5443 else if (s > end) {
5444 *pStatisticCount = end - pStatistics;
5445 result = VK_INCOMPLETE;
5446 } else {
5447 *pStatisticCount = s - pStatistics;
5448 }
5449
5450 return result;
5451 }
5452
5453 static VkResult radv_copy_representation(void *data, size_t *data_size, const char *src)
5454 {
5455 size_t total_size = strlen(src) + 1;
5456
5457 if (!data) {
5458 *data_size = total_size;
5459 return VK_SUCCESS;
5460 }
5461
5462 size_t size = MIN2(total_size, *data_size);
5463
5464 memcpy(data, src, size);
5465 if (size)
5466 *((char*)data + size - 1) = 0;
5467 return size < total_size ? VK_INCOMPLETE : VK_SUCCESS;
5468 }
5469
5470 VkResult radv_GetPipelineExecutableInternalRepresentationsKHR(
5471 VkDevice device,
5472 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5473 uint32_t* pInternalRepresentationCount,
5474 VkPipelineExecutableInternalRepresentationKHR* pInternalRepresentations)
5475 {
5476 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5477 gl_shader_stage stage;
5478 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5479
5480 VkPipelineExecutableInternalRepresentationKHR *p = pInternalRepresentations;
5481 VkPipelineExecutableInternalRepresentationKHR *end = p + (pInternalRepresentations ? *pInternalRepresentationCount : 0);
5482 VkResult result = VK_SUCCESS;
5483 /* optimized NIR */
5484 if (p < end) {
5485 p->isText = true;
5486 desc_copy(p->name, "NIR Shader(s)");
5487 desc_copy(p->description, "The optimized NIR shader(s)");
5488 if (radv_copy_representation(p->pData, &p->dataSize, shader->nir_string) != VK_SUCCESS)
5489 result = VK_INCOMPLETE;
5490 }
5491 ++p;
5492
5493 /* backend IR */
5494 if (p < end) {
5495 p->isText = true;
5496 if (pipeline->device->physical_device->use_llvm) {
5497 desc_copy(p->name, "LLVM IR");
5498 desc_copy(p->description, "The LLVM IR after some optimizations");
5499 } else {
5500 desc_copy(p->name, "ACO IR");
5501 desc_copy(p->description, "The ACO IR after some optimizations");
5502 }
5503 if (radv_copy_representation(p->pData, &p->dataSize, shader->ir_string) != VK_SUCCESS)
5504 result = VK_INCOMPLETE;
5505 }
5506 ++p;
5507
5508 /* Disassembler */
5509 if (p < end) {
5510 p->isText = true;
5511 desc_copy(p->name, "Assembly");
5512 desc_copy(p->description, "Final Assembly");
5513 if (radv_copy_representation(p->pData, &p->dataSize, shader->disasm_string) != VK_SUCCESS)
5514 result = VK_INCOMPLETE;
5515 }
5516 ++p;
5517
5518 if (!pInternalRepresentations)
5519 *pInternalRepresentationCount = p - pInternalRepresentations;
5520 else if(p > end) {
5521 result = VK_INCOMPLETE;
5522 *pInternalRepresentationCount = end - pInternalRepresentations;
5523 } else {
5524 *pInternalRepresentationCount = p - pInternalRepresentations;
5525 }
5526
5527 return result;
5528 }