2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
34 #include "radv_shader.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
48 #include "ac_shader_util.h"
50 struct radv_blend_state
{
51 uint32_t blend_enable_4bit
;
52 uint32_t need_src_alpha
;
54 uint32_t cb_color_control
;
55 uint32_t cb_target_mask
;
56 uint32_t cb_target_enabled_4bit
;
57 uint32_t sx_mrt_blend_opt
[8];
58 uint32_t cb_blend_control
[8];
60 uint32_t spi_shader_col_format
;
61 uint32_t cb_shader_mask
;
62 uint32_t db_alpha_to_mask
;
64 uint32_t commutative_4bit
;
66 bool single_cb_enable
;
67 bool mrt0_is_dual_src
;
70 struct radv_dsa_order_invariance
{
71 /* Whether the final result in Z/S buffers is guaranteed to be
72 * invariant under changes to the order in which fragments arrive.
76 /* Whether the set of fragments that pass the combined Z/S test is
77 * guaranteed to be invariant under changes to the order in which
83 struct radv_tessellation_state
{
84 uint32_t ls_hs_config
;
90 static const VkPipelineMultisampleStateCreateInfo
*
91 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
93 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
94 return pCreateInfo
->pMultisampleState
;
98 static const VkPipelineTessellationStateCreateInfo
*
99 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
101 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
102 if (pCreateInfo
->pStages
[i
].stage
== VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
||
103 pCreateInfo
->pStages
[i
].stage
== VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
) {
104 return pCreateInfo
->pTessellationState
;
110 static const VkPipelineDepthStencilStateCreateInfo
*
111 radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
113 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
114 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
116 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
117 subpass
->depth_stencil_attachment
)
118 return pCreateInfo
->pDepthStencilState
;
122 static const VkPipelineColorBlendStateCreateInfo
*
123 radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
125 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
126 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
128 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
129 subpass
->has_color_att
)
130 return pCreateInfo
->pColorBlendState
;
134 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
)
136 struct radv_shader_variant
*variant
= NULL
;
137 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
138 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
139 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
140 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
141 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
142 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
145 return variant
->info
.is_ngg
;
148 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline
*pipeline
)
150 assert(radv_pipeline_has_ngg(pipeline
));
152 struct radv_shader_variant
*variant
= NULL
;
153 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
154 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
155 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
156 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
157 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
158 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
161 return variant
->info
.is_ngg_passthrough
;
164 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
)
166 if (!radv_pipeline_has_gs(pipeline
))
169 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
170 * On GFX10, it might be required in rare cases if it's not possible to
173 if (radv_pipeline_has_ngg(pipeline
))
176 assert(pipeline
->gs_copy_shader
);
181 radv_pipeline_destroy(struct radv_device
*device
,
182 struct radv_pipeline
*pipeline
,
183 const VkAllocationCallbacks
* allocator
)
185 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
186 if (pipeline
->shaders
[i
])
187 radv_shader_variant_destroy(device
, pipeline
->shaders
[i
]);
189 if (pipeline
->gs_copy_shader
)
190 radv_shader_variant_destroy(device
, pipeline
->gs_copy_shader
);
193 free(pipeline
->cs
.buf
);
195 vk_object_base_finish(&pipeline
->base
);
196 vk_free2(&device
->vk
.alloc
, allocator
, pipeline
);
199 void radv_DestroyPipeline(
201 VkPipeline _pipeline
,
202 const VkAllocationCallbacks
* pAllocator
)
204 RADV_FROM_HANDLE(radv_device
, device
, _device
);
205 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
210 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
213 static uint32_t get_hash_flags(struct radv_device
*device
)
215 uint32_t hash_flags
= 0;
217 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_NGG
)
218 hash_flags
|= RADV_HASH_SHADER_NO_NGG
;
219 if (device
->physical_device
->cs_wave_size
== 32)
220 hash_flags
|= RADV_HASH_SHADER_CS_WAVE32
;
221 if (device
->physical_device
->ps_wave_size
== 32)
222 hash_flags
|= RADV_HASH_SHADER_PS_WAVE32
;
223 if (device
->physical_device
->ge_wave_size
== 32)
224 hash_flags
|= RADV_HASH_SHADER_GE_WAVE32
;
225 if (device
->physical_device
->use_aco
)
226 hash_flags
|= RADV_HASH_SHADER_ACO
;
231 radv_pipeline_scratch_init(struct radv_device
*device
,
232 struct radv_pipeline
*pipeline
)
234 unsigned scratch_bytes_per_wave
= 0;
235 unsigned max_waves
= 0;
236 unsigned min_waves
= 1;
238 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
239 if (pipeline
->shaders
[i
] &&
240 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
) {
241 unsigned max_stage_waves
= device
->scratch_waves
;
243 scratch_bytes_per_wave
= MAX2(scratch_bytes_per_wave
,
244 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
);
246 max_stage_waves
= MIN2(max_stage_waves
,
247 4 * device
->physical_device
->rad_info
.num_good_compute_units
*
248 (256 / pipeline
->shaders
[i
]->config
.num_vgprs
));
249 max_waves
= MAX2(max_waves
, max_stage_waves
);
253 if (pipeline
->shaders
[MESA_SHADER_COMPUTE
]) {
254 unsigned group_size
= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[0] *
255 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[1] *
256 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[2];
257 min_waves
= MAX2(min_waves
, round_up_u32(group_size
, 64));
260 pipeline
->scratch_bytes_per_wave
= scratch_bytes_per_wave
;
261 pipeline
->max_waves
= max_waves
;
265 static uint32_t si_translate_blend_logic_op(VkLogicOp op
)
268 case VK_LOGIC_OP_CLEAR
:
269 return V_028808_ROP3_CLEAR
;
270 case VK_LOGIC_OP_AND
:
271 return V_028808_ROP3_AND
;
272 case VK_LOGIC_OP_AND_REVERSE
:
273 return V_028808_ROP3_AND_REVERSE
;
274 case VK_LOGIC_OP_COPY
:
275 return V_028808_ROP3_COPY
;
276 case VK_LOGIC_OP_AND_INVERTED
:
277 return V_028808_ROP3_AND_INVERTED
;
278 case VK_LOGIC_OP_NO_OP
:
279 return V_028808_ROP3_NO_OP
;
280 case VK_LOGIC_OP_XOR
:
281 return V_028808_ROP3_XOR
;
283 return V_028808_ROP3_OR
;
284 case VK_LOGIC_OP_NOR
:
285 return V_028808_ROP3_NOR
;
286 case VK_LOGIC_OP_EQUIVALENT
:
287 return V_028808_ROP3_EQUIVALENT
;
288 case VK_LOGIC_OP_INVERT
:
289 return V_028808_ROP3_INVERT
;
290 case VK_LOGIC_OP_OR_REVERSE
:
291 return V_028808_ROP3_OR_REVERSE
;
292 case VK_LOGIC_OP_COPY_INVERTED
:
293 return V_028808_ROP3_COPY_INVERTED
;
294 case VK_LOGIC_OP_OR_INVERTED
:
295 return V_028808_ROP3_OR_INVERTED
;
296 case VK_LOGIC_OP_NAND
:
297 return V_028808_ROP3_NAND
;
298 case VK_LOGIC_OP_SET
:
299 return V_028808_ROP3_SET
;
301 unreachable("Unhandled logic op");
306 static uint32_t si_translate_blend_function(VkBlendOp op
)
309 case VK_BLEND_OP_ADD
:
310 return V_028780_COMB_DST_PLUS_SRC
;
311 case VK_BLEND_OP_SUBTRACT
:
312 return V_028780_COMB_SRC_MINUS_DST
;
313 case VK_BLEND_OP_REVERSE_SUBTRACT
:
314 return V_028780_COMB_DST_MINUS_SRC
;
315 case VK_BLEND_OP_MIN
:
316 return V_028780_COMB_MIN_DST_SRC
;
317 case VK_BLEND_OP_MAX
:
318 return V_028780_COMB_MAX_DST_SRC
;
324 static uint32_t si_translate_blend_factor(VkBlendFactor factor
)
327 case VK_BLEND_FACTOR_ZERO
:
328 return V_028780_BLEND_ZERO
;
329 case VK_BLEND_FACTOR_ONE
:
330 return V_028780_BLEND_ONE
;
331 case VK_BLEND_FACTOR_SRC_COLOR
:
332 return V_028780_BLEND_SRC_COLOR
;
333 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
334 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
335 case VK_BLEND_FACTOR_DST_COLOR
:
336 return V_028780_BLEND_DST_COLOR
;
337 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
338 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
339 case VK_BLEND_FACTOR_SRC_ALPHA
:
340 return V_028780_BLEND_SRC_ALPHA
;
341 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
342 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
343 case VK_BLEND_FACTOR_DST_ALPHA
:
344 return V_028780_BLEND_DST_ALPHA
;
345 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
346 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
347 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
348 return V_028780_BLEND_CONSTANT_COLOR
;
349 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
350 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
351 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
352 return V_028780_BLEND_CONSTANT_ALPHA
;
353 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
354 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
355 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
356 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
357 case VK_BLEND_FACTOR_SRC1_COLOR
:
358 return V_028780_BLEND_SRC1_COLOR
;
359 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
360 return V_028780_BLEND_INV_SRC1_COLOR
;
361 case VK_BLEND_FACTOR_SRC1_ALPHA
:
362 return V_028780_BLEND_SRC1_ALPHA
;
363 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
364 return V_028780_BLEND_INV_SRC1_ALPHA
;
370 static uint32_t si_translate_blend_opt_function(VkBlendOp op
)
373 case VK_BLEND_OP_ADD
:
374 return V_028760_OPT_COMB_ADD
;
375 case VK_BLEND_OP_SUBTRACT
:
376 return V_028760_OPT_COMB_SUBTRACT
;
377 case VK_BLEND_OP_REVERSE_SUBTRACT
:
378 return V_028760_OPT_COMB_REVSUBTRACT
;
379 case VK_BLEND_OP_MIN
:
380 return V_028760_OPT_COMB_MIN
;
381 case VK_BLEND_OP_MAX
:
382 return V_028760_OPT_COMB_MAX
;
384 return V_028760_OPT_COMB_BLEND_DISABLED
;
388 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor
, bool is_alpha
)
391 case VK_BLEND_FACTOR_ZERO
:
392 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
393 case VK_BLEND_FACTOR_ONE
:
394 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
395 case VK_BLEND_FACTOR_SRC_COLOR
:
396 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
397 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
398 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
399 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
400 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
401 case VK_BLEND_FACTOR_SRC_ALPHA
:
402 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
403 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
404 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
405 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
406 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
407 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
409 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
414 * Get rid of DST in the blend factors by commuting the operands:
415 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
417 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
418 unsigned *dst_factor
, unsigned expected_dst
,
419 unsigned replacement_src
)
421 if (*src_factor
== expected_dst
&&
422 *dst_factor
== VK_BLEND_FACTOR_ZERO
) {
423 *src_factor
= VK_BLEND_FACTOR_ZERO
;
424 *dst_factor
= replacement_src
;
426 /* Commuting the operands requires reversing subtractions. */
427 if (*func
== VK_BLEND_OP_SUBTRACT
)
428 *func
= VK_BLEND_OP_REVERSE_SUBTRACT
;
429 else if (*func
== VK_BLEND_OP_REVERSE_SUBTRACT
)
430 *func
= VK_BLEND_OP_SUBTRACT
;
434 static bool si_blend_factor_uses_dst(unsigned factor
)
436 return factor
== VK_BLEND_FACTOR_DST_COLOR
||
437 factor
== VK_BLEND_FACTOR_DST_ALPHA
||
438 factor
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
439 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
||
440 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
;
443 static bool is_dual_src(VkBlendFactor factor
)
446 case VK_BLEND_FACTOR_SRC1_COLOR
:
447 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
448 case VK_BLEND_FACTOR_SRC1_ALPHA
:
449 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
456 static unsigned si_choose_spi_color_format(VkFormat vk_format
,
458 bool blend_need_alpha
)
460 const struct vk_format_description
*desc
= vk_format_description(vk_format
);
461 unsigned format
, ntype
, swap
;
463 /* Alpha is needed for alpha-to-coverage.
464 * Blending may be with or without alpha.
466 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
467 unsigned alpha
= 0; /* exports alpha, but may not support blending */
468 unsigned blend
= 0; /* supports blending, but may not export alpha */
469 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
471 format
= radv_translate_colorformat(vk_format
);
472 ntype
= radv_translate_color_numformat(vk_format
, desc
,
473 vk_format_get_first_non_void_channel(vk_format
));
474 swap
= radv_translate_colorswap(vk_format
, false);
476 /* Choose the SPI color formats. These are required values for Stoney/RB+.
477 * Other chips have multiple choices, though they are not necessarily better.
480 case V_028C70_COLOR_5_6_5
:
481 case V_028C70_COLOR_1_5_5_5
:
482 case V_028C70_COLOR_5_5_5_1
:
483 case V_028C70_COLOR_4_4_4_4
:
484 case V_028C70_COLOR_10_11_11
:
485 case V_028C70_COLOR_11_11_10
:
486 case V_028C70_COLOR_8
:
487 case V_028C70_COLOR_8_8
:
488 case V_028C70_COLOR_8_8_8_8
:
489 case V_028C70_COLOR_10_10_10_2
:
490 case V_028C70_COLOR_2_10_10_10
:
491 if (ntype
== V_028C70_NUMBER_UINT
)
492 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
493 else if (ntype
== V_028C70_NUMBER_SINT
)
494 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
496 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
499 case V_028C70_COLOR_16
:
500 case V_028C70_COLOR_16_16
:
501 case V_028C70_COLOR_16_16_16_16
:
502 if (ntype
== V_028C70_NUMBER_UNORM
||
503 ntype
== V_028C70_NUMBER_SNORM
) {
504 /* UNORM16 and SNORM16 don't support blending */
505 if (ntype
== V_028C70_NUMBER_UNORM
)
506 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
508 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
510 /* Use 32 bits per channel for blending. */
511 if (format
== V_028C70_COLOR_16
) {
512 if (swap
== V_028C70_SWAP_STD
) { /* R */
513 blend
= V_028714_SPI_SHADER_32_R
;
514 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
515 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
516 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
519 } else if (format
== V_028C70_COLOR_16_16
) {
520 if (swap
== V_028C70_SWAP_STD
) { /* RG */
521 blend
= V_028714_SPI_SHADER_32_GR
;
522 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
523 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
524 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
527 } else /* 16_16_16_16 */
528 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
529 } else if (ntype
== V_028C70_NUMBER_UINT
)
530 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
531 else if (ntype
== V_028C70_NUMBER_SINT
)
532 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
533 else if (ntype
== V_028C70_NUMBER_FLOAT
)
534 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
539 case V_028C70_COLOR_32
:
540 if (swap
== V_028C70_SWAP_STD
) { /* R */
541 blend
= normal
= V_028714_SPI_SHADER_32_R
;
542 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
543 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
544 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
549 case V_028C70_COLOR_32_32
:
550 if (swap
== V_028C70_SWAP_STD
) { /* RG */
551 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
552 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
553 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
554 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
559 case V_028C70_COLOR_32_32_32_32
:
560 case V_028C70_COLOR_8_24
:
561 case V_028C70_COLOR_24_8
:
562 case V_028C70_COLOR_X24_8_32_FLOAT
:
563 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
567 unreachable("unhandled blend format");
570 if (blend_enable
&& blend_need_alpha
)
572 else if(blend_need_alpha
)
574 else if(blend_enable
)
581 radv_pipeline_compute_spi_color_formats(struct radv_pipeline
*pipeline
,
582 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
583 struct radv_blend_state
*blend
)
585 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
586 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
587 unsigned col_format
= 0;
588 unsigned num_targets
;
590 for (unsigned i
= 0; i
< (blend
->single_cb_enable
? 1 : subpass
->color_count
); ++i
) {
593 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
594 cf
= V_028714_SPI_SHADER_ZERO
;
596 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
598 blend
->blend_enable_4bit
& (0xfu
<< (i
* 4));
600 cf
= si_choose_spi_color_format(attachment
->format
,
602 blend
->need_src_alpha
& (1 << i
));
605 col_format
|= cf
<< (4 * i
);
608 if (!(col_format
& 0xf) && blend
->need_src_alpha
& (1 << 0)) {
609 /* When a subpass doesn't have any color attachments, write the
610 * alpha channel of MRT0 when alpha coverage is enabled because
611 * the depth attachment needs it.
613 col_format
|= V_028714_SPI_SHADER_32_AR
;
616 /* If the i-th target format is set, all previous target formats must
617 * be non-zero to avoid hangs.
619 num_targets
= (util_last_bit(col_format
) + 3) / 4;
620 for (unsigned i
= 0; i
< num_targets
; i
++) {
621 if (!(col_format
& (0xf << (i
* 4)))) {
622 col_format
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
626 /* The output for dual source blending should have the same format as
629 if (blend
->mrt0_is_dual_src
)
630 col_format
|= (col_format
& 0xf) << 4;
632 blend
->cb_shader_mask
= ac_get_cb_shader_mask(col_format
);
633 blend
->spi_shader_col_format
= col_format
;
637 format_is_int8(VkFormat format
)
639 const struct vk_format_description
*desc
= vk_format_description(format
);
640 int channel
= vk_format_get_first_non_void_channel(format
);
642 return channel
>= 0 && desc
->channel
[channel
].pure_integer
&&
643 desc
->channel
[channel
].size
== 8;
647 format_is_int10(VkFormat format
)
649 const struct vk_format_description
*desc
= vk_format_description(format
);
651 if (desc
->nr_channels
!= 4)
653 for (unsigned i
= 0; i
< 4; i
++) {
654 if (desc
->channel
[i
].pure_integer
&& desc
->channel
[i
].size
== 10)
661 * Ordered so that for each i,
662 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
664 const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
] = {
665 VK_FORMAT_R32_SFLOAT
,
666 VK_FORMAT_R32G32_SFLOAT
,
667 VK_FORMAT_R8G8B8A8_UNORM
,
668 VK_FORMAT_R16G16B16A16_UNORM
,
669 VK_FORMAT_R16G16B16A16_SNORM
,
670 VK_FORMAT_R16G16B16A16_UINT
,
671 VK_FORMAT_R16G16B16A16_SINT
,
672 VK_FORMAT_R32G32B32A32_SFLOAT
,
673 VK_FORMAT_R8G8B8A8_UINT
,
674 VK_FORMAT_R8G8B8A8_SINT
,
675 VK_FORMAT_A2R10G10B10_UINT_PACK32
,
676 VK_FORMAT_A2R10G10B10_SINT_PACK32
,
679 unsigned radv_format_meta_fs_key(VkFormat format
)
681 unsigned col_format
= si_choose_spi_color_format(format
, false, false);
683 assert(col_format
!= V_028714_SPI_SHADER_32_AR
);
684 if (col_format
>= V_028714_SPI_SHADER_32_AR
)
685 --col_format
; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
687 --col_format
; /* Skip V_028714_SPI_SHADER_ZERO */
688 bool is_int8
= format_is_int8(format
);
689 bool is_int10
= format_is_int10(format
);
691 return col_format
+ (is_int8
? 3 : is_int10
? 5 : 0);
695 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
696 unsigned *is_int8
, unsigned *is_int10
)
698 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
699 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
703 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
704 struct radv_render_pass_attachment
*attachment
;
706 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
709 attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
711 if (format_is_int8(attachment
->format
))
713 if (format_is_int10(attachment
->format
))
719 radv_blend_check_commutativity(struct radv_blend_state
*blend
,
720 VkBlendOp op
, VkBlendFactor src
,
721 VkBlendFactor dst
, unsigned chanmask
)
723 /* Src factor is allowed when it does not depend on Dst. */
724 static const uint32_t src_allowed
=
725 (1u << VK_BLEND_FACTOR_ONE
) |
726 (1u << VK_BLEND_FACTOR_SRC_COLOR
) |
727 (1u << VK_BLEND_FACTOR_SRC_ALPHA
) |
728 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
) |
729 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR
) |
730 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA
) |
731 (1u << VK_BLEND_FACTOR_SRC1_COLOR
) |
732 (1u << VK_BLEND_FACTOR_SRC1_ALPHA
) |
733 (1u << VK_BLEND_FACTOR_ZERO
) |
734 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
) |
735 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
) |
736 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
) |
737 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
) |
738 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
) |
739 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
);
741 if (dst
== VK_BLEND_FACTOR_ONE
&&
742 (src_allowed
& (1u << src
))) {
743 /* Addition is commutative, but floating point addition isn't
744 * associative: subtle changes can be introduced via different
745 * rounding. Be conservative, only enable for min and max.
747 if (op
== VK_BLEND_OP_MAX
|| op
== VK_BLEND_OP_MIN
)
748 blend
->commutative_4bit
|= chanmask
;
752 static struct radv_blend_state
753 radv_pipeline_init_blend_state(struct radv_pipeline
*pipeline
,
754 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
755 const struct radv_graphics_pipeline_create_info
*extra
)
757 const VkPipelineColorBlendStateCreateInfo
*vkblend
= radv_pipeline_get_color_blend_state(pCreateInfo
);
758 const VkPipelineMultisampleStateCreateInfo
*vkms
= radv_pipeline_get_multisample_state(pCreateInfo
);
759 struct radv_blend_state blend
= {0};
760 unsigned mode
= V_028808_CB_NORMAL
;
763 if (extra
&& extra
->custom_blend_mode
) {
764 blend
.single_cb_enable
= true;
765 mode
= extra
->custom_blend_mode
;
768 blend
.cb_color_control
= 0;
770 if (vkblend
->logicOpEnable
)
771 blend
.cb_color_control
|= S_028808_ROP3(si_translate_blend_logic_op(vkblend
->logicOp
));
773 blend
.cb_color_control
|= S_028808_ROP3(V_028808_ROP3_COPY
);
776 blend
.db_alpha_to_mask
= S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
777 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
778 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
779 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
780 S_028B70_OFFSET_ROUND(1);
782 if (vkms
&& vkms
->alphaToCoverageEnable
) {
783 blend
.db_alpha_to_mask
|= S_028B70_ALPHA_TO_MASK_ENABLE(1);
784 blend
.need_src_alpha
|= 0x1;
787 blend
.cb_target_mask
= 0;
789 for (i
= 0; i
< vkblend
->attachmentCount
; i
++) {
790 const VkPipelineColorBlendAttachmentState
*att
= &vkblend
->pAttachments
[i
];
791 unsigned blend_cntl
= 0;
792 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
793 VkBlendOp eqRGB
= att
->colorBlendOp
;
794 VkBlendFactor srcRGB
= att
->srcColorBlendFactor
;
795 VkBlendFactor dstRGB
= att
->dstColorBlendFactor
;
796 VkBlendOp eqA
= att
->alphaBlendOp
;
797 VkBlendFactor srcA
= att
->srcAlphaBlendFactor
;
798 VkBlendFactor dstA
= att
->dstAlphaBlendFactor
;
800 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
802 if (!att
->colorWriteMask
)
805 blend
.cb_target_mask
|= (unsigned)att
->colorWriteMask
<< (4 * i
);
806 blend
.cb_target_enabled_4bit
|= 0xf << (4 * i
);
807 if (!att
->blendEnable
) {
808 blend
.cb_blend_control
[i
] = blend_cntl
;
812 if (is_dual_src(srcRGB
) || is_dual_src(dstRGB
) || is_dual_src(srcA
) || is_dual_src(dstA
))
814 blend
.mrt0_is_dual_src
= true;
816 if (eqRGB
== VK_BLEND_OP_MIN
|| eqRGB
== VK_BLEND_OP_MAX
) {
817 srcRGB
= VK_BLEND_FACTOR_ONE
;
818 dstRGB
= VK_BLEND_FACTOR_ONE
;
820 if (eqA
== VK_BLEND_OP_MIN
|| eqA
== VK_BLEND_OP_MAX
) {
821 srcA
= VK_BLEND_FACTOR_ONE
;
822 dstA
= VK_BLEND_FACTOR_ONE
;
825 radv_blend_check_commutativity(&blend
, eqRGB
, srcRGB
, dstRGB
,
827 radv_blend_check_commutativity(&blend
, eqA
, srcA
, dstA
,
830 /* Blending optimizations for RB+.
831 * These transformations don't change the behavior.
833 * First, get rid of DST in the blend factors:
834 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
836 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
837 VK_BLEND_FACTOR_DST_COLOR
,
838 VK_BLEND_FACTOR_SRC_COLOR
);
840 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
841 VK_BLEND_FACTOR_DST_COLOR
,
842 VK_BLEND_FACTOR_SRC_COLOR
);
844 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
845 VK_BLEND_FACTOR_DST_ALPHA
,
846 VK_BLEND_FACTOR_SRC_ALPHA
);
848 /* Look up the ideal settings from tables. */
849 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
850 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
851 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
852 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
854 /* Handle interdependencies. */
855 if (si_blend_factor_uses_dst(srcRGB
))
856 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
857 if (si_blend_factor_uses_dst(srcA
))
858 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
860 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
&&
861 (dstRGB
== VK_BLEND_FACTOR_ZERO
||
862 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
863 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
))
864 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
866 /* Set the final value. */
867 blend
.sx_mrt_blend_opt
[i
] =
868 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
869 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
870 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
871 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
872 S_028760_ALPHA_DST_OPT(dstA_opt
) |
873 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
874 blend_cntl
|= S_028780_ENABLE(1);
876 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
877 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
878 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
879 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
880 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
881 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
882 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
883 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
885 blend
.cb_blend_control
[i
] = blend_cntl
;
887 blend
.blend_enable_4bit
|= 0xfu
<< (i
* 4);
889 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
890 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
891 srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
892 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
893 srcRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
||
894 dstRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
)
895 blend
.need_src_alpha
|= 1 << i
;
897 for (i
= vkblend
->attachmentCount
; i
< 8; i
++) {
898 blend
.cb_blend_control
[i
] = 0;
899 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
903 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
904 /* Disable RB+ blend optimizations for dual source blending. */
905 if (blend
.mrt0_is_dual_src
) {
906 for (i
= 0; i
< 8; i
++) {
907 blend
.sx_mrt_blend_opt
[i
] =
908 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
909 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
913 /* RB+ doesn't work with dual source blending, logic op and
916 if (blend
.mrt0_is_dual_src
||
917 (vkblend
&& vkblend
->logicOpEnable
) ||
918 mode
== V_028808_CB_RESOLVE
)
919 blend
.cb_color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
922 if (blend
.cb_target_mask
)
923 blend
.cb_color_control
|= S_028808_MODE(mode
);
925 blend
.cb_color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
927 radv_pipeline_compute_spi_color_formats(pipeline
, pCreateInfo
, &blend
);
931 static uint32_t si_translate_stencil_op(enum VkStencilOp op
)
934 case VK_STENCIL_OP_KEEP
:
935 return V_02842C_STENCIL_KEEP
;
936 case VK_STENCIL_OP_ZERO
:
937 return V_02842C_STENCIL_ZERO
;
938 case VK_STENCIL_OP_REPLACE
:
939 return V_02842C_STENCIL_REPLACE_TEST
;
940 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
941 return V_02842C_STENCIL_ADD_CLAMP
;
942 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
943 return V_02842C_STENCIL_SUB_CLAMP
;
944 case VK_STENCIL_OP_INVERT
:
945 return V_02842C_STENCIL_INVERT
;
946 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
947 return V_02842C_STENCIL_ADD_WRAP
;
948 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
949 return V_02842C_STENCIL_SUB_WRAP
;
955 static uint32_t si_translate_fill(VkPolygonMode func
)
958 case VK_POLYGON_MODE_FILL
:
959 return V_028814_X_DRAW_TRIANGLES
;
960 case VK_POLYGON_MODE_LINE
:
961 return V_028814_X_DRAW_LINES
;
962 case VK_POLYGON_MODE_POINT
:
963 return V_028814_X_DRAW_POINTS
;
966 return V_028814_X_DRAW_POINTS
;
970 static uint8_t radv_pipeline_get_ps_iter_samples(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
972 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
973 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
974 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
975 uint32_t ps_iter_samples
= 1;
976 uint32_t num_samples
;
978 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
980 * "If the VK_AMD_mixed_attachment_samples extension is enabled and the
981 * subpass uses color attachments, totalSamples is the number of
982 * samples of the color attachments. Otherwise, totalSamples is the
983 * value of VkPipelineMultisampleStateCreateInfo::rasterizationSamples
984 * specified at pipeline creation time."
986 if (subpass
->has_color_att
) {
987 num_samples
= subpass
->color_sample_count
;
989 num_samples
= vkms
->rasterizationSamples
;
992 if (vkms
->sampleShadingEnable
) {
993 ps_iter_samples
= ceilf(vkms
->minSampleShading
* num_samples
);
994 ps_iter_samples
= util_next_power_of_two(ps_iter_samples
);
996 return ps_iter_samples
;
1000 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
1002 return pCreateInfo
->depthTestEnable
&&
1003 pCreateInfo
->depthWriteEnable
&&
1004 pCreateInfo
->depthCompareOp
!= VK_COMPARE_OP_NEVER
;
1008 radv_writes_stencil(const VkStencilOpState
*state
)
1010 return state
->writeMask
&&
1011 (state
->failOp
!= VK_STENCIL_OP_KEEP
||
1012 state
->passOp
!= VK_STENCIL_OP_KEEP
||
1013 state
->depthFailOp
!= VK_STENCIL_OP_KEEP
);
1017 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
1019 return pCreateInfo
->stencilTestEnable
&&
1020 (radv_writes_stencil(&pCreateInfo
->front
) ||
1021 radv_writes_stencil(&pCreateInfo
->back
));
1025 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
1027 return radv_is_depth_write_enabled(pCreateInfo
) ||
1028 radv_is_stencil_write_enabled(pCreateInfo
);
1032 radv_order_invariant_stencil_op(VkStencilOp op
)
1034 /* REPLACE is normally order invariant, except when the stencil
1035 * reference value is written by the fragment shader. Tracking this
1036 * interaction does not seem worth the effort, so be conservative.
1038 return op
!= VK_STENCIL_OP_INCREMENT_AND_CLAMP
&&
1039 op
!= VK_STENCIL_OP_DECREMENT_AND_CLAMP
&&
1040 op
!= VK_STENCIL_OP_REPLACE
;
1044 radv_order_invariant_stencil_state(const VkStencilOpState
*state
)
1046 /* Compute whether, assuming Z writes are disabled, this stencil state
1047 * is order invariant in the sense that the set of passing fragments as
1048 * well as the final stencil buffer result does not depend on the order
1051 return !state
->writeMask
||
1052 /* The following assumes that Z writes are disabled. */
1053 (state
->compareOp
== VK_COMPARE_OP_ALWAYS
&&
1054 radv_order_invariant_stencil_op(state
->passOp
) &&
1055 radv_order_invariant_stencil_op(state
->depthFailOp
)) ||
1056 (state
->compareOp
== VK_COMPARE_OP_NEVER
&&
1057 radv_order_invariant_stencil_op(state
->failOp
));
1061 radv_pipeline_out_of_order_rast(struct radv_pipeline
*pipeline
,
1062 struct radv_blend_state
*blend
,
1063 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1065 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1066 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
1067 const VkPipelineDepthStencilStateCreateInfo
*vkds
= radv_pipeline_get_depth_stencil_state(pCreateInfo
);
1068 const VkPipelineColorBlendStateCreateInfo
*vkblend
= radv_pipeline_get_color_blend_state(pCreateInfo
);
1069 unsigned colormask
= blend
->cb_target_enabled_4bit
;
1071 if (!pipeline
->device
->physical_device
->out_of_order_rast_allowed
)
1074 /* Be conservative if a logic operation is enabled with color buffers. */
1075 if (colormask
&& vkblend
&& vkblend
->logicOpEnable
)
1078 /* Default depth/stencil invariance when no attachment is bound. */
1079 struct radv_dsa_order_invariance dsa_order_invariant
= {
1080 .zs
= true, .pass_set
= true
1084 struct radv_render_pass_attachment
*attachment
=
1085 pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
1086 bool has_stencil
= vk_format_is_stencil(attachment
->format
);
1087 struct radv_dsa_order_invariance order_invariance
[2];
1088 struct radv_shader_variant
*ps
=
1089 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
1091 /* Compute depth/stencil order invariance in order to know if
1092 * it's safe to enable out-of-order.
1094 bool zfunc_is_ordered
=
1095 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
||
1096 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS
||
1097 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS_OR_EQUAL
||
1098 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER
||
1099 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER_OR_EQUAL
;
1101 bool nozwrite_and_order_invariant_stencil
=
1102 !radv_is_ds_write_enabled(vkds
) ||
1103 (!radv_is_depth_write_enabled(vkds
) &&
1104 radv_order_invariant_stencil_state(&vkds
->front
) &&
1105 radv_order_invariant_stencil_state(&vkds
->back
));
1107 order_invariance
[1].zs
=
1108 nozwrite_and_order_invariant_stencil
||
1109 (!radv_is_stencil_write_enabled(vkds
) &&
1111 order_invariance
[0].zs
=
1112 !radv_is_depth_write_enabled(vkds
) || zfunc_is_ordered
;
1114 order_invariance
[1].pass_set
=
1115 nozwrite_and_order_invariant_stencil
||
1116 (!radv_is_stencil_write_enabled(vkds
) &&
1117 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1118 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
));
1119 order_invariance
[0].pass_set
=
1120 !radv_is_depth_write_enabled(vkds
) ||
1121 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1122 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
);
1124 dsa_order_invariant
= order_invariance
[has_stencil
];
1125 if (!dsa_order_invariant
.zs
)
1128 /* The set of PS invocations is always order invariant,
1129 * except when early Z/S tests are requested.
1132 ps
->info
.ps
.writes_memory
&&
1133 ps
->info
.ps
.early_fragment_test
&&
1134 !dsa_order_invariant
.pass_set
)
1137 /* Determine if out-of-order rasterization should be disabled
1138 * when occlusion queries are used.
1140 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
=
1141 !dsa_order_invariant
.pass_set
;
1144 /* No color buffers are enabled for writing. */
1148 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
1151 /* Only commutative blending. */
1152 if (blendmask
& ~blend
->commutative_4bit
)
1155 if (!dsa_order_invariant
.pass_set
)
1159 if (colormask
& ~blendmask
)
1166 radv_pipeline_init_multisample_state(struct radv_pipeline
*pipeline
,
1167 struct radv_blend_state
*blend
,
1168 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1170 const VkPipelineMultisampleStateCreateInfo
*vkms
= radv_pipeline_get_multisample_state(pCreateInfo
);
1171 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
1172 unsigned num_tile_pipes
= pipeline
->device
->physical_device
->rad_info
.num_tile_pipes
;
1173 bool out_of_order_rast
= false;
1174 int ps_iter_samples
= 1;
1175 uint32_t mask
= 0xffff;
1178 ms
->num_samples
= vkms
->rasterizationSamples
;
1180 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1182 * "Sample shading is enabled for a graphics pipeline:
1184 * - If the interface of the fragment shader entry point of the
1185 * graphics pipeline includes an input variable decorated
1186 * with SampleId or SamplePosition. In this case
1187 * minSampleShadingFactor takes the value 1.0.
1188 * - Else if the sampleShadingEnable member of the
1189 * VkPipelineMultisampleStateCreateInfo structure specified
1190 * when creating the graphics pipeline is set to VK_TRUE. In
1191 * this case minSampleShadingFactor takes the value of
1192 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1194 * Otherwise, sample shading is considered disabled."
1196 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.force_persample
) {
1197 ps_iter_samples
= ms
->num_samples
;
1199 ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
);
1202 ms
->num_samples
= 1;
1205 const struct VkPipelineRasterizationStateRasterizationOrderAMD
*raster_order
=
1206 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD
);
1207 if (raster_order
&& raster_order
->rasterizationOrder
== VK_RASTERIZATION_ORDER_RELAXED_AMD
) {
1208 /* Out-of-order rasterization is explicitly enabled by the
1211 out_of_order_rast
= true;
1213 /* Determine if the driver can enable out-of-order
1214 * rasterization internally.
1217 radv_pipeline_out_of_order_rast(pipeline
, blend
, pCreateInfo
);
1220 ms
->pa_sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1221 ms
->pa_sc_aa_config
= 0;
1222 ms
->db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1223 S_028804_INCOHERENT_EQAA_READS(1) |
1224 S_028804_INTERPOLATE_COMP_Z(1) |
1225 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1226 ms
->pa_sc_mode_cntl_1
=
1227 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1228 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
1229 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
1230 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1232 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1233 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1234 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1235 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1236 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1237 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1238 ms
->pa_sc_mode_cntl_0
= S_028A48_ALTERNATE_RBS_PER_TILE(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
1239 S_028A48_VPORT_SCISSOR_ENABLE(1);
1241 const VkPipelineRasterizationLineStateCreateInfoEXT
*rast_line
=
1242 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1243 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1245 ms
->pa_sc_mode_cntl_0
|= S_028A48_LINE_STIPPLE_ENABLE(rast_line
->stippledLineEnable
);
1246 if (rast_line
->lineRasterizationMode
== VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT
) {
1247 /* From the Vulkan spec 1.1.129:
1249 * "When VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT lines
1250 * are being rasterized, sample locations may all be
1251 * treated as being at the pixel center (this may
1252 * affect attribute and depth interpolation)."
1254 ms
->num_samples
= 1;
1258 if (ms
->num_samples
> 1) {
1259 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1260 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1261 uint32_t z_samples
= subpass
->depth_stencil_attachment
? subpass
->depth_sample_count
: ms
->num_samples
;
1262 unsigned log_samples
= util_logbase2(ms
->num_samples
);
1263 unsigned log_z_samples
= util_logbase2(z_samples
);
1264 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
1265 ms
->pa_sc_mode_cntl_0
|= S_028A48_MSAA_ENABLE(1);
1266 ms
->pa_sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1267 ms
->db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples
) |
1268 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
1269 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
1270 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
1271 ms
->pa_sc_aa_config
|= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
1272 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples
)) |
1273 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1274 ms
->pa_sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
1275 if (ps_iter_samples
> 1)
1276 pipeline
->graphics
.spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1279 if (vkms
&& vkms
->pSampleMask
) {
1280 mask
= vkms
->pSampleMask
[0] & 0xffff;
1283 ms
->pa_sc_aa_mask
[0] = mask
| (mask
<< 16);
1284 ms
->pa_sc_aa_mask
[1] = mask
| (mask
<< 16);
1288 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology
)
1291 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1292 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1293 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1294 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1295 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1297 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1298 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1299 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1300 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1301 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1302 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1305 unreachable("unhandled primitive type");
1310 si_translate_prim(enum VkPrimitiveTopology topology
)
1313 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1314 return V_008958_DI_PT_POINTLIST
;
1315 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1316 return V_008958_DI_PT_LINELIST
;
1317 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1318 return V_008958_DI_PT_LINESTRIP
;
1319 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1320 return V_008958_DI_PT_TRILIST
;
1321 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1322 return V_008958_DI_PT_TRISTRIP
;
1323 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1324 return V_008958_DI_PT_TRIFAN
;
1325 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1326 return V_008958_DI_PT_LINELIST_ADJ
;
1327 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1328 return V_008958_DI_PT_LINESTRIP_ADJ
;
1329 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1330 return V_008958_DI_PT_TRILIST_ADJ
;
1331 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1332 return V_008958_DI_PT_TRISTRIP_ADJ
;
1333 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1334 return V_008958_DI_PT_PATCH
;
1342 si_conv_gl_prim_to_gs_out(unsigned gl_prim
)
1345 case 0: /* GL_POINTS */
1346 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1347 case 1: /* GL_LINES */
1348 case 3: /* GL_LINE_STRIP */
1349 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1350 case 0x8E7A: /* GL_ISOLINES */
1351 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1353 case 4: /* GL_TRIANGLES */
1354 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1355 case 5: /* GL_TRIANGLE_STRIP */
1356 case 7: /* GL_QUADS */
1357 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1365 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology
)
1368 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1369 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1370 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1371 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1372 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1373 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1374 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1375 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1376 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1377 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1378 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1379 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1380 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1381 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1388 static unsigned radv_dynamic_state_mask(VkDynamicState state
)
1391 case VK_DYNAMIC_STATE_VIEWPORT
:
1392 return RADV_DYNAMIC_VIEWPORT
;
1393 case VK_DYNAMIC_STATE_SCISSOR
:
1394 return RADV_DYNAMIC_SCISSOR
;
1395 case VK_DYNAMIC_STATE_LINE_WIDTH
:
1396 return RADV_DYNAMIC_LINE_WIDTH
;
1397 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
1398 return RADV_DYNAMIC_DEPTH_BIAS
;
1399 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
1400 return RADV_DYNAMIC_BLEND_CONSTANTS
;
1401 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
1402 return RADV_DYNAMIC_DEPTH_BOUNDS
;
1403 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
1404 return RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
1405 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
1406 return RADV_DYNAMIC_STENCIL_WRITE_MASK
;
1407 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
1408 return RADV_DYNAMIC_STENCIL_REFERENCE
;
1409 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT
:
1410 return RADV_DYNAMIC_DISCARD_RECTANGLE
;
1411 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT
:
1412 return RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1413 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
1414 return RADV_DYNAMIC_LINE_STIPPLE
;
1416 unreachable("Unhandled dynamic state");
1420 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1422 uint32_t states
= RADV_DYNAMIC_ALL
;
1424 /* If rasterization is disabled we do not care about any of the dynamic states,
1425 * since they are all rasterization related only. */
1426 if (pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
1429 if (!pCreateInfo
->pRasterizationState
->depthBiasEnable
)
1430 states
&= ~RADV_DYNAMIC_DEPTH_BIAS
;
1432 if (!pCreateInfo
->pDepthStencilState
||
1433 !pCreateInfo
->pDepthStencilState
->depthBoundsTestEnable
)
1434 states
&= ~RADV_DYNAMIC_DEPTH_BOUNDS
;
1436 if (!pCreateInfo
->pDepthStencilState
||
1437 !pCreateInfo
->pDepthStencilState
->stencilTestEnable
)
1438 states
&= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK
|
1439 RADV_DYNAMIC_STENCIL_WRITE_MASK
|
1440 RADV_DYNAMIC_STENCIL_REFERENCE
);
1442 if (!vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
))
1443 states
&= ~RADV_DYNAMIC_DISCARD_RECTANGLE
;
1445 if (!pCreateInfo
->pMultisampleState
||
1446 !vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1447 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
))
1448 states
&= ~RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1450 if (!pCreateInfo
->pRasterizationState
||
1451 !vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1452 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
))
1453 states
&= ~RADV_DYNAMIC_LINE_STIPPLE
;
1455 /* TODO: blend constants & line width. */
1462 radv_pipeline_init_dynamic_state(struct radv_pipeline
*pipeline
,
1463 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1465 uint32_t needed_states
= radv_pipeline_needed_dynamic_state(pCreateInfo
);
1466 uint32_t states
= needed_states
;
1467 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1468 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1470 pipeline
->dynamic_state
= default_dynamic_state
;
1471 pipeline
->graphics
.needed_dynamic_state
= needed_states
;
1473 if (pCreateInfo
->pDynamicState
) {
1474 /* Remove all of the states that are marked as dynamic */
1475 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1476 for (uint32_t s
= 0; s
< count
; s
++)
1477 states
&= ~radv_dynamic_state_mask(pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1480 struct radv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1482 if (needed_states
& RADV_DYNAMIC_VIEWPORT
) {
1483 assert(pCreateInfo
->pViewportState
);
1485 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1486 if (states
& RADV_DYNAMIC_VIEWPORT
) {
1487 typed_memcpy(dynamic
->viewport
.viewports
,
1488 pCreateInfo
->pViewportState
->pViewports
,
1489 pCreateInfo
->pViewportState
->viewportCount
);
1493 if (needed_states
& RADV_DYNAMIC_SCISSOR
) {
1494 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1495 if (states
& RADV_DYNAMIC_SCISSOR
) {
1496 typed_memcpy(dynamic
->scissor
.scissors
,
1497 pCreateInfo
->pViewportState
->pScissors
,
1498 pCreateInfo
->pViewportState
->scissorCount
);
1502 if (states
& RADV_DYNAMIC_LINE_WIDTH
) {
1503 assert(pCreateInfo
->pRasterizationState
);
1504 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1507 if (states
& RADV_DYNAMIC_DEPTH_BIAS
) {
1508 assert(pCreateInfo
->pRasterizationState
);
1509 dynamic
->depth_bias
.bias
=
1510 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1511 dynamic
->depth_bias
.clamp
=
1512 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1513 dynamic
->depth_bias
.slope
=
1514 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1517 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1519 * pColorBlendState is [...] NULL if the pipeline has rasterization
1520 * disabled or if the subpass of the render pass the pipeline is
1521 * created against does not use any color attachments.
1523 if (subpass
->has_color_att
&& states
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
1524 assert(pCreateInfo
->pColorBlendState
);
1525 typed_memcpy(dynamic
->blend_constants
,
1526 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1529 /* If there is no depthstencil attachment, then don't read
1530 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1531 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1532 * no need to override the depthstencil defaults in
1533 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1535 * Section 9.2 of the Vulkan 1.0.15 spec says:
1537 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1538 * disabled or if the subpass of the render pass the pipeline is created
1539 * against does not use a depth/stencil attachment.
1541 if (needed_states
&& subpass
->depth_stencil_attachment
) {
1542 assert(pCreateInfo
->pDepthStencilState
);
1544 if (states
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
1545 dynamic
->depth_bounds
.min
=
1546 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1547 dynamic
->depth_bounds
.max
=
1548 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1551 if (states
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
1552 dynamic
->stencil_compare_mask
.front
=
1553 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1554 dynamic
->stencil_compare_mask
.back
=
1555 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1558 if (states
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
1559 dynamic
->stencil_write_mask
.front
=
1560 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1561 dynamic
->stencil_write_mask
.back
=
1562 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1565 if (states
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
1566 dynamic
->stencil_reference
.front
=
1567 pCreateInfo
->pDepthStencilState
->front
.reference
;
1568 dynamic
->stencil_reference
.back
=
1569 pCreateInfo
->pDepthStencilState
->back
.reference
;
1573 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
1574 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
1575 if (needed_states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1576 dynamic
->discard_rectangle
.count
= discard_rectangle_info
->discardRectangleCount
;
1577 if (states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1578 typed_memcpy(dynamic
->discard_rectangle
.rectangles
,
1579 discard_rectangle_info
->pDiscardRectangles
,
1580 discard_rectangle_info
->discardRectangleCount
);
1584 if (needed_states
& RADV_DYNAMIC_SAMPLE_LOCATIONS
) {
1585 const VkPipelineSampleLocationsStateCreateInfoEXT
*sample_location_info
=
1586 vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1587 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
);
1588 /* If sampleLocationsEnable is VK_FALSE, the default sample
1589 * locations are used and the values specified in
1590 * sampleLocationsInfo are ignored.
1592 if (sample_location_info
->sampleLocationsEnable
) {
1593 const VkSampleLocationsInfoEXT
*pSampleLocationsInfo
=
1594 &sample_location_info
->sampleLocationsInfo
;
1596 assert(pSampleLocationsInfo
->sampleLocationsCount
<= MAX_SAMPLE_LOCATIONS
);
1598 dynamic
->sample_location
.per_pixel
= pSampleLocationsInfo
->sampleLocationsPerPixel
;
1599 dynamic
->sample_location
.grid_size
= pSampleLocationsInfo
->sampleLocationGridSize
;
1600 dynamic
->sample_location
.count
= pSampleLocationsInfo
->sampleLocationsCount
;
1601 typed_memcpy(&dynamic
->sample_location
.locations
[0],
1602 pSampleLocationsInfo
->pSampleLocations
,
1603 pSampleLocationsInfo
->sampleLocationsCount
);
1607 const VkPipelineRasterizationLineStateCreateInfoEXT
*rast_line_info
=
1608 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1609 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1610 if (needed_states
& RADV_DYNAMIC_LINE_STIPPLE
) {
1611 dynamic
->line_stipple
.factor
= rast_line_info
->lineStippleFactor
;
1612 dynamic
->line_stipple
.pattern
= rast_line_info
->lineStipplePattern
;
1615 pipeline
->dynamic_state
.mask
= states
;
1619 gfx9_get_gs_info(const struct radv_pipeline_key
*key
,
1620 const struct radv_pipeline
*pipeline
,
1622 struct radv_shader_info
*infos
,
1623 struct gfx9_gs_info
*out
)
1625 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1626 struct radv_es_output_info
*es_info
;
1627 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1628 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1630 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ?
1631 &infos
[MESA_SHADER_TESS_EVAL
].tes
.es_info
:
1632 &infos
[MESA_SHADER_VERTEX
].vs
.es_info
;
1634 unsigned gs_num_invocations
= MAX2(gs_info
->gs
.invocations
, 1);
1635 bool uses_adjacency
;
1636 switch(key
->topology
) {
1637 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1638 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1639 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1640 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1641 uses_adjacency
= true;
1644 uses_adjacency
= false;
1648 /* All these are in dwords: */
1649 /* We can't allow using the whole LDS, because GS waves compete with
1650 * other shader stages for LDS space. */
1651 const unsigned max_lds_size
= 8 * 1024;
1652 const unsigned esgs_itemsize
= es_info
->esgs_itemsize
/ 4;
1653 unsigned esgs_lds_size
;
1655 /* All these are per subgroup: */
1656 const unsigned max_out_prims
= 32 * 1024;
1657 const unsigned max_es_verts
= 255;
1658 const unsigned ideal_gs_prims
= 64;
1659 unsigned max_gs_prims
, gs_prims
;
1660 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
1662 if (uses_adjacency
|| gs_num_invocations
> 1)
1663 max_gs_prims
= 127 / gs_num_invocations
;
1667 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1668 * Make sure we don't go over the maximum value.
1670 if (gs_info
->gs
.vertices_out
> 0) {
1671 max_gs_prims
= MIN2(max_gs_prims
,
1673 (gs_info
->gs
.vertices_out
* gs_num_invocations
));
1675 assert(max_gs_prims
> 0);
1677 /* If the primitive has adjacency, halve the number of vertices
1678 * that will be reused in multiple primitives.
1680 min_es_verts
= gs_info
->gs
.vertices_in
/ (uses_adjacency
? 2 : 1);
1682 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
1683 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
1685 /* Compute ESGS LDS size based on the worst case number of ES vertices
1686 * needed to create the target number of GS prims per subgroup.
1688 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1690 /* If total LDS usage is too big, refactor partitions based on ratio
1691 * of ESGS item sizes.
1693 if (esgs_lds_size
> max_lds_size
) {
1694 /* Our target GS Prims Per Subgroup was too large. Calculate
1695 * the maximum number of GS Prims Per Subgroup that will fit
1696 * into LDS, capped by the maximum that the hardware can support.
1698 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
1700 assert(gs_prims
> 0);
1701 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
1704 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1705 assert(esgs_lds_size
<= max_lds_size
);
1708 /* Now calculate remaining ESGS information. */
1710 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
1712 es_verts
= max_es_verts
;
1714 /* Vertices for adjacency primitives are not always reused, so restore
1715 * it for ES_VERTS_PER_SUBGRP.
1717 min_es_verts
= gs_info
->gs
.vertices_in
;
1719 /* For normal primitives, the VGT only checks if they are past the ES
1720 * verts per subgroup after allocating a full GS primitive and if they
1721 * are, kick off a new subgroup. But if those additional ES verts are
1722 * unique (e.g. not reused) we need to make sure there is enough LDS
1723 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1725 es_verts
-= min_es_verts
- 1;
1727 uint32_t es_verts_per_subgroup
= es_verts
;
1728 uint32_t gs_prims_per_subgroup
= gs_prims
;
1729 uint32_t gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
1730 uint32_t max_prims_per_subgroup
= gs_inst_prims_in_subgroup
* gs_info
->gs
.vertices_out
;
1731 out
->lds_size
= align(esgs_lds_size
, 128) / 128;
1732 out
->vgt_gs_onchip_cntl
= S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup
) |
1733 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup
) |
1734 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup
);
1735 out
->vgt_gs_max_prims_per_subgroup
= S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup
);
1736 out
->vgt_esgs_ring_itemsize
= esgs_itemsize
;
1737 assert(max_prims_per_subgroup
<= max_out_prims
);
1740 static void clamp_gsprims_to_esverts(unsigned *max_gsprims
, unsigned max_esverts
,
1741 unsigned min_verts_per_prim
, bool use_adjacency
)
1743 unsigned max_reuse
= max_esverts
- min_verts_per_prim
;
1746 *max_gsprims
= MIN2(*max_gsprims
, 1 + max_reuse
);
1750 radv_get_num_input_vertices(nir_shader
**nir
)
1752 if (nir
[MESA_SHADER_GEOMETRY
]) {
1753 nir_shader
*gs
= nir
[MESA_SHADER_GEOMETRY
];
1755 return gs
->info
.gs
.vertices_in
;
1758 if (nir
[MESA_SHADER_TESS_CTRL
]) {
1759 nir_shader
*tes
= nir
[MESA_SHADER_TESS_EVAL
];
1761 if (tes
->info
.tess
.point_mode
)
1763 if (tes
->info
.tess
.primitive_mode
== GL_ISOLINES
)
1772 gfx10_get_ngg_info(const struct radv_pipeline_key
*key
,
1773 struct radv_pipeline
*pipeline
,
1775 struct radv_shader_info
*infos
,
1776 struct gfx10_ngg_info
*ngg
)
1778 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1779 struct radv_es_output_info
*es_info
=
1780 nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1781 unsigned gs_type
= nir
[MESA_SHADER_GEOMETRY
] ? MESA_SHADER_GEOMETRY
: MESA_SHADER_VERTEX
;
1782 unsigned max_verts_per_prim
= radv_get_num_input_vertices(nir
);
1783 unsigned min_verts_per_prim
=
1784 gs_type
== MESA_SHADER_GEOMETRY
? max_verts_per_prim
: 1;
1785 unsigned gs_num_invocations
= nir
[MESA_SHADER_GEOMETRY
] ? MAX2(gs_info
->gs
.invocations
, 1) : 1;
1786 bool uses_adjacency
;
1787 switch(key
->topology
) {
1788 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1789 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1790 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1791 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1792 uses_adjacency
= true;
1795 uses_adjacency
= false;
1799 /* All these are in dwords: */
1800 /* We can't allow using the whole LDS, because GS waves compete with
1801 * other shader stages for LDS space.
1803 * TODO: We should really take the shader's internal LDS use into
1804 * account. The linker will fail if the size is greater than
1807 const unsigned max_lds_size
= 8 * 1024 - 768;
1808 const unsigned target_lds_size
= max_lds_size
;
1809 unsigned esvert_lds_size
= 0;
1810 unsigned gsprim_lds_size
= 0;
1812 /* All these are per subgroup: */
1813 bool max_vert_out_per_gs_instance
= false;
1814 unsigned max_esverts_base
= 256;
1815 unsigned max_gsprims_base
= 128; /* default prim group size clamp */
1817 /* Hardware has the following non-natural restrictions on the value
1818 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1820 * - at most 252 for any line input primitive type
1821 * - at most 251 for any quad input primitive type
1822 * - at most 251 for triangle strips with adjacency (this happens to
1823 * be the natural limit for triangle *lists* with adjacency)
1825 max_esverts_base
= MIN2(max_esverts_base
, 251 + max_verts_per_prim
- 1);
1827 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1828 unsigned max_out_verts_per_gsprim
=
1829 gs_info
->gs
.vertices_out
* gs_num_invocations
;
1831 if (max_out_verts_per_gsprim
<= 256) {
1832 if (max_out_verts_per_gsprim
) {
1833 max_gsprims_base
= MIN2(max_gsprims_base
,
1834 256 / max_out_verts_per_gsprim
);
1837 /* Use special multi-cycling mode in which each GS
1838 * instance gets its own subgroup. Does not work with
1840 max_vert_out_per_gs_instance
= true;
1841 max_gsprims_base
= 1;
1842 max_out_verts_per_gsprim
= gs_info
->gs
.vertices_out
;
1845 esvert_lds_size
= es_info
->esgs_itemsize
/ 4;
1846 gsprim_lds_size
= (gs_info
->gs
.gsvs_vertex_size
/ 4 + 1) * max_out_verts_per_gsprim
;
1849 /* LDS size for passing data from GS to ES. */
1850 struct radv_streamout_info
*so_info
= nir
[MESA_SHADER_TESS_CTRL
]
1851 ? &infos
[MESA_SHADER_TESS_EVAL
].so
1852 : &infos
[MESA_SHADER_VERTEX
].so
;
1854 if (so_info
->num_outputs
)
1855 esvert_lds_size
= 4 * so_info
->num_outputs
+ 1;
1857 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1858 * corresponding to the ES thread of the provoking vertex. All
1859 * ES threads load and export PrimitiveID for their thread.
1861 if (!nir
[MESA_SHADER_TESS_CTRL
] &&
1862 infos
[MESA_SHADER_VERTEX
].vs
.outinfo
.export_prim_id
)
1863 esvert_lds_size
= MAX2(esvert_lds_size
, 1);
1866 unsigned max_gsprims
= max_gsprims_base
;
1867 unsigned max_esverts
= max_esverts_base
;
1869 if (esvert_lds_size
)
1870 max_esverts
= MIN2(max_esverts
, target_lds_size
/ esvert_lds_size
);
1871 if (gsprim_lds_size
)
1872 max_gsprims
= MIN2(max_gsprims
, target_lds_size
/ gsprim_lds_size
);
1874 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1875 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
, min_verts_per_prim
, uses_adjacency
);
1876 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1878 if (esvert_lds_size
|| gsprim_lds_size
) {
1879 /* Now that we have a rough proportionality between esverts
1880 * and gsprims based on the primitive type, scale both of them
1881 * down simultaneously based on required LDS space.
1883 * We could be smarter about this if we knew how much vertex
1886 unsigned lds_total
= max_esverts
* esvert_lds_size
+
1887 max_gsprims
* gsprim_lds_size
;
1888 if (lds_total
> target_lds_size
) {
1889 max_esverts
= max_esverts
* target_lds_size
/ lds_total
;
1890 max_gsprims
= max_gsprims
* target_lds_size
/ lds_total
;
1892 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1893 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1894 min_verts_per_prim
, uses_adjacency
);
1895 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1899 /* Round up towards full wave sizes for better ALU utilization. */
1900 if (!max_vert_out_per_gs_instance
) {
1901 unsigned orig_max_esverts
;
1902 unsigned orig_max_gsprims
;
1905 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1906 wavesize
= gs_info
->wave_size
;
1908 wavesize
= nir
[MESA_SHADER_TESS_CTRL
]
1909 ? infos
[MESA_SHADER_TESS_EVAL
].wave_size
1910 : infos
[MESA_SHADER_VERTEX
].wave_size
;
1914 orig_max_esverts
= max_esverts
;
1915 orig_max_gsprims
= max_gsprims
;
1917 max_esverts
= align(max_esverts
, wavesize
);
1918 max_esverts
= MIN2(max_esverts
, max_esverts_base
);
1919 if (esvert_lds_size
)
1920 max_esverts
= MIN2(max_esverts
,
1921 (max_lds_size
- max_gsprims
* gsprim_lds_size
) /
1923 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1925 max_gsprims
= align(max_gsprims
, wavesize
);
1926 max_gsprims
= MIN2(max_gsprims
, max_gsprims_base
);
1927 if (gsprim_lds_size
)
1928 max_gsprims
= MIN2(max_gsprims
,
1929 (max_lds_size
- max_esverts
* esvert_lds_size
) /
1931 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1932 min_verts_per_prim
, uses_adjacency
);
1933 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1934 } while (orig_max_esverts
!= max_esverts
|| orig_max_gsprims
!= max_gsprims
);
1937 /* Hardware restriction: minimum value of max_esverts */
1938 max_esverts
= MAX2(max_esverts
, 23 + max_verts_per_prim
);
1940 unsigned max_out_vertices
=
1941 max_vert_out_per_gs_instance
? gs_info
->gs
.vertices_out
:
1942 gs_type
== MESA_SHADER_GEOMETRY
?
1943 max_gsprims
* gs_num_invocations
* gs_info
->gs
.vertices_out
:
1945 assert(max_out_vertices
<= 256);
1947 unsigned prim_amp_factor
= 1;
1948 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1949 /* Number of output primitives per GS input primitive after
1951 prim_amp_factor
= gs_info
->gs
.vertices_out
;
1954 /* The GE only checks against the maximum number of ES verts after
1955 * allocating a full GS primitive. So we need to ensure that whenever
1956 * this check passes, there is enough space for a full primitive without
1959 ngg
->hw_max_esverts
= max_esverts
- max_verts_per_prim
+ 1;
1960 ngg
->max_gsprims
= max_gsprims
;
1961 ngg
->max_out_verts
= max_out_vertices
;
1962 ngg
->prim_amp_factor
= prim_amp_factor
;
1963 ngg
->max_vert_out_per_gs_instance
= max_vert_out_per_gs_instance
;
1964 ngg
->ngg_emit_size
= max_gsprims
* gsprim_lds_size
;
1965 ngg
->esgs_ring_size
= 4 * max_esverts
* esvert_lds_size
;
1967 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1968 ngg
->vgt_esgs_ring_itemsize
= es_info
->esgs_itemsize
/ 4;
1970 ngg
->vgt_esgs_ring_itemsize
= 1;
1973 pipeline
->graphics
.esgs_ring_size
= ngg
->esgs_ring_size
;
1975 assert(ngg
->hw_max_esverts
>= 24); /* HW limitation */
1979 calculate_gs_ring_sizes(struct radv_pipeline
*pipeline
,
1980 const struct gfx9_gs_info
*gs
)
1982 struct radv_device
*device
= pipeline
->device
;
1983 unsigned num_se
= device
->physical_device
->rad_info
.max_se
;
1984 unsigned wave_size
= 64;
1985 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
1986 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1987 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1989 unsigned gs_vertex_reuse
=
1990 (device
->physical_device
->rad_info
.chip_class
>= GFX8
? 32 : 16) * num_se
;
1991 unsigned alignment
= 256 * num_se
;
1992 /* The maximum size is 63.999 MB per SE. */
1993 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
1994 struct radv_shader_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
1996 /* Calculate the minimum size. */
1997 unsigned min_esgs_ring_size
= align(gs
->vgt_esgs_ring_itemsize
* 4 * gs_vertex_reuse
*
1998 wave_size
, alignment
);
1999 /* These are recommended sizes, not minimum sizes. */
2000 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
2001 gs
->vgt_esgs_ring_itemsize
* 4 * gs_info
->gs
.vertices_in
;
2002 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
2003 gs_info
->gs
.max_gsvs_emit_size
;
2005 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
2006 esgs_ring_size
= align(esgs_ring_size
, alignment
);
2007 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
2009 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
2010 pipeline
->graphics
.esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
2012 pipeline
->graphics
.gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
2015 static void si_multiwave_lds_size_workaround(struct radv_device
*device
,
2018 /* If tessellation is all offchip and on-chip GS isn't used, this
2019 * workaround is not needed.
2023 /* SPI barrier management bug:
2024 * Make sure we have at least 4k of LDS in use to avoid the bug.
2025 * It applies to workgroup sizes of more than one wavefront.
2027 if (device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
||
2028 device
->physical_device
->rad_info
.family
== CHIP_KABINI
)
2029 *lds_size
= MAX2(*lds_size
, 8);
2032 struct radv_shader_variant
*
2033 radv_get_shader(struct radv_pipeline
*pipeline
,
2034 gl_shader_stage stage
)
2036 if (stage
== MESA_SHADER_VERTEX
) {
2037 if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
2038 return pipeline
->shaders
[MESA_SHADER_VERTEX
];
2039 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
])
2040 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
2041 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
2042 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
2043 } else if (stage
== MESA_SHADER_TESS_EVAL
) {
2044 if (!radv_pipeline_has_tess(pipeline
))
2046 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
2047 return pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
2048 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
2049 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
2051 return pipeline
->shaders
[stage
];
2054 static struct radv_tessellation_state
2055 calculate_tess_state(struct radv_pipeline
*pipeline
,
2056 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
2058 unsigned num_tcs_input_cp
;
2059 unsigned num_tcs_output_cp
;
2061 unsigned num_patches
;
2062 struct radv_tessellation_state tess
= {0};
2064 num_tcs_input_cp
= pCreateInfo
->pTessellationState
->patchControlPoints
;
2065 num_tcs_output_cp
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.tcs_vertices_out
; //TCS VERTICES OUT
2066 num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2068 lds_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.lds_size
;
2070 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2071 assert(lds_size
<= 65536);
2072 lds_size
= align(lds_size
, 512) / 512;
2074 assert(lds_size
<= 32768);
2075 lds_size
= align(lds_size
, 256) / 256;
2077 si_multiwave_lds_size_workaround(pipeline
->device
, &lds_size
);
2079 tess
.lds_size
= lds_size
;
2081 tess
.ls_hs_config
= S_028B58_NUM_PATCHES(num_patches
) |
2082 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
2083 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
2084 tess
.num_patches
= num_patches
;
2086 struct radv_shader_variant
*tes
= radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
);
2087 unsigned type
= 0, partitioning
= 0, topology
= 0, distribution_mode
= 0;
2089 switch (tes
->info
.tes
.primitive_mode
) {
2091 type
= V_028B6C_TESS_TRIANGLE
;
2094 type
= V_028B6C_TESS_QUAD
;
2097 type
= V_028B6C_TESS_ISOLINE
;
2101 switch (tes
->info
.tes
.spacing
) {
2102 case TESS_SPACING_EQUAL
:
2103 partitioning
= V_028B6C_PART_INTEGER
;
2105 case TESS_SPACING_FRACTIONAL_ODD
:
2106 partitioning
= V_028B6C_PART_FRAC_ODD
;
2108 case TESS_SPACING_FRACTIONAL_EVEN
:
2109 partitioning
= V_028B6C_PART_FRAC_EVEN
;
2115 bool ccw
= tes
->info
.tes
.ccw
;
2116 const VkPipelineTessellationDomainOriginStateCreateInfo
*domain_origin_state
=
2117 vk_find_struct_const(pCreateInfo
->pTessellationState
,
2118 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO
);
2120 if (domain_origin_state
&& domain_origin_state
->domainOrigin
!= VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT
)
2123 if (tes
->info
.tes
.point_mode
)
2124 topology
= V_028B6C_OUTPUT_POINT
;
2125 else if (tes
->info
.tes
.primitive_mode
== GL_ISOLINES
)
2126 topology
= V_028B6C_OUTPUT_LINE
;
2128 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
2130 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
2132 if (pipeline
->device
->physical_device
->rad_info
.has_distributed_tess
) {
2133 if (pipeline
->device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
2134 pipeline
->device
->physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
2135 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
2137 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
2139 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
2141 tess
.tf_param
= S_028B6C_TYPE(type
) |
2142 S_028B6C_PARTITIONING(partitioning
) |
2143 S_028B6C_TOPOLOGY(topology
) |
2144 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
2149 static const struct radv_prim_vertex_count prim_size_table
[] = {
2150 [V_008958_DI_PT_NONE
] = {0, 0},
2151 [V_008958_DI_PT_POINTLIST
] = {1, 1},
2152 [V_008958_DI_PT_LINELIST
] = {2, 2},
2153 [V_008958_DI_PT_LINESTRIP
] = {2, 1},
2154 [V_008958_DI_PT_TRILIST
] = {3, 3},
2155 [V_008958_DI_PT_TRIFAN
] = {3, 1},
2156 [V_008958_DI_PT_TRISTRIP
] = {3, 1},
2157 [V_008958_DI_PT_LINELIST_ADJ
] = {4, 4},
2158 [V_008958_DI_PT_LINESTRIP_ADJ
] = {4, 1},
2159 [V_008958_DI_PT_TRILIST_ADJ
] = {6, 6},
2160 [V_008958_DI_PT_TRISTRIP_ADJ
] = {6, 2},
2161 [V_008958_DI_PT_RECTLIST
] = {3, 3},
2162 [V_008958_DI_PT_LINELOOP
] = {2, 1},
2163 [V_008958_DI_PT_POLYGON
] = {3, 1},
2164 [V_008958_DI_PT_2D_TRI_STRIP
] = {0, 0},
2167 static const struct radv_vs_output_info
*get_vs_output_info(const struct radv_pipeline
*pipeline
)
2169 if (radv_pipeline_has_gs(pipeline
))
2170 if (radv_pipeline_has_ngg(pipeline
))
2171 return &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.vs
.outinfo
;
2173 return &pipeline
->gs_copy_shader
->info
.vs
.outinfo
;
2174 else if (radv_pipeline_has_tess(pipeline
))
2175 return &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.outinfo
;
2177 return &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.outinfo
;
2181 radv_link_shaders(struct radv_pipeline
*pipeline
, nir_shader
**shaders
)
2183 nir_shader
* ordered_shaders
[MESA_SHADER_STAGES
];
2184 int shader_count
= 0;
2186 if(shaders
[MESA_SHADER_FRAGMENT
]) {
2187 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_FRAGMENT
];
2189 if(shaders
[MESA_SHADER_GEOMETRY
]) {
2190 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_GEOMETRY
];
2192 if(shaders
[MESA_SHADER_TESS_EVAL
]) {
2193 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_EVAL
];
2195 if(shaders
[MESA_SHADER_TESS_CTRL
]) {
2196 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_CTRL
];
2198 if(shaders
[MESA_SHADER_VERTEX
]) {
2199 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_VERTEX
];
2202 if (shader_count
> 1) {
2203 unsigned first
= ordered_shaders
[shader_count
- 1]->info
.stage
;
2204 unsigned last
= ordered_shaders
[0]->info
.stage
;
2206 if (ordered_shaders
[0]->info
.stage
== MESA_SHADER_FRAGMENT
&&
2207 ordered_shaders
[1]->info
.has_transform_feedback_varyings
)
2208 nir_link_xfb_varyings(ordered_shaders
[1], ordered_shaders
[0]);
2210 for (int i
= 0; i
< shader_count
; ++i
) {
2211 nir_variable_mode mask
= 0;
2213 if (ordered_shaders
[i
]->info
.stage
!= first
)
2214 mask
= mask
| nir_var_shader_in
;
2216 if (ordered_shaders
[i
]->info
.stage
!= last
)
2217 mask
= mask
| nir_var_shader_out
;
2219 nir_lower_io_to_scalar_early(ordered_shaders
[i
], mask
);
2220 radv_optimize_nir(ordered_shaders
[i
], false, false);
2224 for (int i
= 1; i
< shader_count
; ++i
) {
2225 nir_lower_io_arrays_to_elements(ordered_shaders
[i
],
2226 ordered_shaders
[i
- 1]);
2228 if (nir_link_opt_varyings(ordered_shaders
[i
],
2229 ordered_shaders
[i
- 1]))
2230 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2232 nir_remove_dead_variables(ordered_shaders
[i
],
2233 nir_var_shader_out
);
2234 nir_remove_dead_variables(ordered_shaders
[i
- 1],
2237 bool progress
= nir_remove_unused_varyings(ordered_shaders
[i
],
2238 ordered_shaders
[i
- 1]);
2240 nir_compact_varyings(ordered_shaders
[i
],
2241 ordered_shaders
[i
- 1], true);
2244 if (nir_lower_global_vars_to_local(ordered_shaders
[i
])) {
2245 ac_lower_indirect_derefs(ordered_shaders
[i
],
2246 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2248 radv_optimize_nir(ordered_shaders
[i
], false, false);
2250 if (nir_lower_global_vars_to_local(ordered_shaders
[i
- 1])) {
2251 ac_lower_indirect_derefs(ordered_shaders
[i
- 1],
2252 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2254 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2260 radv_set_linked_driver_locations(struct radv_pipeline
*pipeline
, nir_shader
**shaders
,
2261 struct radv_shader_info infos
[MESA_SHADER_STAGES
])
2263 bool has_tess
= shaders
[MESA_SHADER_TESS_CTRL
];
2264 bool has_gs
= shaders
[MESA_SHADER_GEOMETRY
];
2266 if (!has_tess
&& !has_gs
)
2269 unsigned vs_info_idx
= MESA_SHADER_VERTEX
;
2270 unsigned tes_info_idx
= MESA_SHADER_TESS_EVAL
;
2272 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2273 /* These are merged into the next stage */
2274 vs_info_idx
= has_tess
? MESA_SHADER_TESS_CTRL
: MESA_SHADER_GEOMETRY
;
2275 tes_info_idx
= has_gs
? MESA_SHADER_GEOMETRY
: MESA_SHADER_TESS_EVAL
;
2279 nir_linked_io_var_info vs2tcs
=
2280 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_VERTEX
], shaders
[MESA_SHADER_TESS_CTRL
]);
2281 nir_linked_io_var_info tcs2tes
=
2282 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_TESS_CTRL
], shaders
[MESA_SHADER_TESS_EVAL
]);
2284 infos
[vs_info_idx
].vs
.num_linked_outputs
= vs2tcs
.num_linked_io_vars
;
2285 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_inputs
= vs2tcs
.num_linked_io_vars
;
2286 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_outputs
= tcs2tes
.num_linked_io_vars
;
2287 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_patch_outputs
= tcs2tes
.num_linked_patch_io_vars
;
2288 infos
[tes_info_idx
].tes
.num_linked_inputs
= tcs2tes
.num_linked_io_vars
;
2289 infos
[tes_info_idx
].tes
.num_linked_patch_inputs
= tcs2tes
.num_linked_patch_io_vars
;
2292 nir_linked_io_var_info tes2gs
=
2293 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_TESS_EVAL
], shaders
[MESA_SHADER_GEOMETRY
]);
2295 infos
[tes_info_idx
].tes
.num_linked_outputs
= tes2gs
.num_linked_io_vars
;
2296 infos
[MESA_SHADER_GEOMETRY
].gs
.num_linked_inputs
= tes2gs
.num_linked_io_vars
;
2298 } else if (has_gs
) {
2299 nir_linked_io_var_info vs2gs
=
2300 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_VERTEX
], shaders
[MESA_SHADER_GEOMETRY
]);
2302 infos
[vs_info_idx
].vs
.num_linked_outputs
= vs2gs
.num_linked_io_vars
;
2303 infos
[MESA_SHADER_GEOMETRY
].gs
.num_linked_inputs
= vs2gs
.num_linked_io_vars
;
2308 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo
*input_state
,
2309 uint32_t attrib_binding
)
2311 for (uint32_t i
= 0; i
< input_state
->vertexBindingDescriptionCount
; i
++) {
2312 const VkVertexInputBindingDescription
*input_binding
=
2313 &input_state
->pVertexBindingDescriptions
[i
];
2315 if (input_binding
->binding
== attrib_binding
)
2316 return input_binding
->stride
;
2322 static struct radv_pipeline_key
2323 radv_generate_graphics_pipeline_key(struct radv_pipeline
*pipeline
,
2324 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2325 const struct radv_blend_state
*blend
,
2326 bool has_view_index
)
2328 const VkPipelineVertexInputStateCreateInfo
*input_state
=
2329 pCreateInfo
->pVertexInputState
;
2330 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*divisor_state
=
2331 vk_find_struct_const(input_state
->pNext
, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
2333 struct radv_pipeline_key key
;
2334 memset(&key
, 0, sizeof(key
));
2336 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
2337 key
.optimisations_disabled
= 1;
2339 key
.has_multiview_view_index
= has_view_index
;
2341 uint32_t binding_input_rate
= 0;
2342 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
2343 for (unsigned i
= 0; i
< input_state
->vertexBindingDescriptionCount
; ++i
) {
2344 if (input_state
->pVertexBindingDescriptions
[i
].inputRate
) {
2345 unsigned binding
= input_state
->pVertexBindingDescriptions
[i
].binding
;
2346 binding_input_rate
|= 1u << binding
;
2347 instance_rate_divisors
[binding
] = 1;
2350 if (divisor_state
) {
2351 for (unsigned i
= 0; i
< divisor_state
->vertexBindingDivisorCount
; ++i
) {
2352 instance_rate_divisors
[divisor_state
->pVertexBindingDivisors
[i
].binding
] =
2353 divisor_state
->pVertexBindingDivisors
[i
].divisor
;
2357 for (unsigned i
= 0; i
< input_state
->vertexAttributeDescriptionCount
; ++i
) {
2358 const VkVertexInputAttributeDescription
*desc
=
2359 &input_state
->pVertexAttributeDescriptions
[i
];
2360 const struct vk_format_description
*format_desc
;
2361 unsigned location
= desc
->location
;
2362 unsigned binding
= desc
->binding
;
2363 unsigned num_format
, data_format
;
2366 if (binding_input_rate
& (1u << binding
)) {
2367 key
.instance_rate_inputs
|= 1u << location
;
2368 key
.instance_rate_divisors
[location
] = instance_rate_divisors
[binding
];
2371 format_desc
= vk_format_description(desc
->format
);
2372 first_non_void
= vk_format_get_first_non_void_channel(desc
->format
);
2374 num_format
= radv_translate_buffer_numformat(format_desc
, first_non_void
);
2375 data_format
= radv_translate_buffer_dataformat(format_desc
, first_non_void
);
2377 key
.vertex_attribute_formats
[location
] = data_format
| (num_format
<< 4);
2378 key
.vertex_attribute_bindings
[location
] = desc
->binding
;
2379 key
.vertex_attribute_offsets
[location
] = desc
->offset
;
2380 key
.vertex_attribute_strides
[location
] = radv_get_attrib_stride(input_state
, desc
->binding
);
2382 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
&&
2383 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_STONEY
) {
2384 VkFormat format
= input_state
->pVertexAttributeDescriptions
[i
].format
;
2387 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2388 case VK_FORMAT_A2B10G10R10_SNORM_PACK32
:
2389 adjust
= RADV_ALPHA_ADJUST_SNORM
;
2391 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2392 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32
:
2393 adjust
= RADV_ALPHA_ADJUST_SSCALED
;
2395 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2396 case VK_FORMAT_A2B10G10R10_SINT_PACK32
:
2397 adjust
= RADV_ALPHA_ADJUST_SINT
;
2403 key
.vertex_alpha_adjust
|= adjust
<< (2 * location
);
2406 switch (desc
->format
) {
2407 case VK_FORMAT_B8G8R8A8_UNORM
:
2408 case VK_FORMAT_B8G8R8A8_SNORM
:
2409 case VK_FORMAT_B8G8R8A8_USCALED
:
2410 case VK_FORMAT_B8G8R8A8_SSCALED
:
2411 case VK_FORMAT_B8G8R8A8_UINT
:
2412 case VK_FORMAT_B8G8R8A8_SINT
:
2413 case VK_FORMAT_B8G8R8A8_SRGB
:
2414 case VK_FORMAT_A2R10G10B10_UNORM_PACK32
:
2415 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2416 case VK_FORMAT_A2R10G10B10_USCALED_PACK32
:
2417 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2418 case VK_FORMAT_A2R10G10B10_UINT_PACK32
:
2419 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2420 key
.vertex_post_shuffle
|= 1 << location
;
2427 const VkPipelineTessellationStateCreateInfo
*tess
=
2428 radv_pipeline_get_tessellation_state(pCreateInfo
);
2430 key
.tess_input_vertices
= tess
->patchControlPoints
;
2432 const VkPipelineMultisampleStateCreateInfo
*vkms
=
2433 radv_pipeline_get_multisample_state(pCreateInfo
);
2434 if (vkms
&& vkms
->rasterizationSamples
> 1) {
2435 uint32_t num_samples
= vkms
->rasterizationSamples
;
2436 uint32_t ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
);
2437 key
.num_samples
= num_samples
;
2438 key
.log2_ps_iter_samples
= util_logbase2(ps_iter_samples
);
2441 key
.col_format
= blend
->spi_shader_col_format
;
2442 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX8
)
2443 radv_pipeline_compute_get_int_clamp(pCreateInfo
, &key
.is_int8
, &key
.is_int10
);
2445 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
2446 key
.topology
= pCreateInfo
->pInputAssemblyState
->topology
;
2452 radv_nir_stage_uses_xfb(const nir_shader
*nir
)
2454 nir_xfb_info
*xfb
= nir_gather_xfb_info(nir
, NULL
);
2455 bool uses_xfb
= !!xfb
;
2462 radv_fill_shader_keys(struct radv_device
*device
,
2463 struct radv_shader_variant_key
*keys
,
2464 const struct radv_pipeline_key
*key
,
2467 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_inputs
= key
->instance_rate_inputs
;
2468 keys
[MESA_SHADER_VERTEX
].vs
.alpha_adjust
= key
->vertex_alpha_adjust
;
2469 keys
[MESA_SHADER_VERTEX
].vs
.post_shuffle
= key
->vertex_post_shuffle
;
2470 for (unsigned i
= 0; i
< MAX_VERTEX_ATTRIBS
; ++i
) {
2471 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_divisors
[i
] = key
->instance_rate_divisors
[i
];
2472 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_formats
[i
] = key
->vertex_attribute_formats
[i
];
2473 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_bindings
[i
] = key
->vertex_attribute_bindings
[i
];
2474 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_offsets
[i
] = key
->vertex_attribute_offsets
[i
];
2475 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_strides
[i
] = key
->vertex_attribute_strides
[i
];
2477 keys
[MESA_SHADER_VERTEX
].vs
.outprim
= si_conv_prim_to_gs_out(key
->topology
);
2479 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2480 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ls
= true;
2481 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= 0;
2482 keys
[MESA_SHADER_TESS_CTRL
].tcs
.input_vertices
= key
->tess_input_vertices
;
2483 keys
[MESA_SHADER_TESS_CTRL
].tcs
.primitive_mode
= nir
[MESA_SHADER_TESS_EVAL
]->info
.tess
.primitive_mode
;
2485 keys
[MESA_SHADER_TESS_CTRL
].tcs
.tes_reads_tess_factors
= !!(nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
& (VARYING_BIT_TESS_LEVEL_INNER
| VARYING_BIT_TESS_LEVEL_OUTER
));
2488 if (nir
[MESA_SHADER_GEOMETRY
]) {
2489 if (nir
[MESA_SHADER_TESS_CTRL
])
2490 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_es
= true;
2492 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_es
= true;
2495 if (device
->physical_device
->use_ngg
) {
2496 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2497 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= true;
2499 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= true;
2502 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2503 nir
[MESA_SHADER_GEOMETRY
] &&
2504 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.invocations
*
2505 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.vertices_out
> 256) {
2506 /* Fallback to the legacy path if tessellation is
2507 * enabled with extreme geometry because
2508 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2511 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2514 if (!device
->physical_device
->use_ngg_gs
) {
2515 if (nir
[MESA_SHADER_GEOMETRY
]) {
2516 if (nir
[MESA_SHADER_TESS_CTRL
])
2517 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2519 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2523 gl_shader_stage last_xfb_stage
= MESA_SHADER_VERTEX
;
2525 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2530 bool uses_xfb
= nir
[last_xfb_stage
] &&
2531 radv_nir_stage_uses_xfb(nir
[last_xfb_stage
]);
2533 if (!device
->physical_device
->use_ngg_streamout
&& uses_xfb
) {
2534 if (nir
[MESA_SHADER_TESS_CTRL
])
2535 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2537 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2540 /* Determine if the pipeline is eligible for the NGG passthrough
2541 * mode. It can't be enabled for geometry shaders, for NGG
2542 * streamout or for vertex shaders that export the primitive ID
2543 * (this is checked later because we don't have the info here.)
2545 if (!nir
[MESA_SHADER_GEOMETRY
] && !uses_xfb
) {
2546 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2547 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
) {
2548 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg_passthrough
= true;
2549 } else if (nir
[MESA_SHADER_VERTEX
] &&
2550 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) {
2551 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg_passthrough
= true;
2556 for(int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
2557 keys
[i
].has_multiview_view_index
= key
->has_multiview_view_index
;
2559 keys
[MESA_SHADER_FRAGMENT
].fs
.col_format
= key
->col_format
;
2560 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int8
= key
->is_int8
;
2561 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int10
= key
->is_int10
;
2562 keys
[MESA_SHADER_FRAGMENT
].fs
.log2_ps_iter_samples
= key
->log2_ps_iter_samples
;
2563 keys
[MESA_SHADER_FRAGMENT
].fs
.num_samples
= key
->num_samples
;
2565 if (nir
[MESA_SHADER_COMPUTE
]) {
2566 keys
[MESA_SHADER_COMPUTE
].cs
.subgroup_size
= key
->compute_subgroup_size
;
2571 radv_get_wave_size(struct radv_device
*device
,
2572 const VkPipelineShaderStageCreateInfo
*pStage
,
2573 gl_shader_stage stage
,
2574 const struct radv_shader_variant_key
*key
)
2576 if (stage
== MESA_SHADER_GEOMETRY
&& !key
->vs_common_out
.as_ngg
)
2578 else if (stage
== MESA_SHADER_COMPUTE
) {
2579 if (key
->cs
.subgroup_size
) {
2580 /* Return the required subgroup size if specified. */
2581 return key
->cs
.subgroup_size
;
2583 return device
->physical_device
->cs_wave_size
;
2585 else if (stage
== MESA_SHADER_FRAGMENT
)
2586 return device
->physical_device
->ps_wave_size
;
2588 return device
->physical_device
->ge_wave_size
;
2592 radv_get_ballot_bit_size(struct radv_device
*device
,
2593 const VkPipelineShaderStageCreateInfo
*pStage
,
2594 gl_shader_stage stage
,
2595 const struct radv_shader_variant_key
*key
)
2597 if (stage
== MESA_SHADER_COMPUTE
&& key
->cs
.subgroup_size
)
2598 return key
->cs
.subgroup_size
;
2603 radv_fill_shader_info(struct radv_pipeline
*pipeline
,
2604 const VkPipelineShaderStageCreateInfo
**pStages
,
2605 struct radv_shader_variant_key
*keys
,
2606 struct radv_shader_info
*infos
,
2609 unsigned active_stages
= 0;
2610 unsigned filled_stages
= 0;
2612 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2614 active_stages
|= (1 << i
);
2617 if (nir
[MESA_SHADER_FRAGMENT
]) {
2618 radv_nir_shader_info_init(&infos
[MESA_SHADER_FRAGMENT
]);
2619 radv_nir_shader_info_pass(nir
[MESA_SHADER_FRAGMENT
],
2621 &keys
[MESA_SHADER_FRAGMENT
],
2622 &infos
[MESA_SHADER_FRAGMENT
],
2623 pipeline
->device
->physical_device
->use_aco
);
2625 /* TODO: These are no longer used as keys we should refactor this */
2626 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
=
2627 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2628 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_layer_id
=
2629 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2630 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_clip_dists
=
2631 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2632 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_viewport_index
=
2633 infos
[MESA_SHADER_FRAGMENT
].ps
.viewport_index_input
;
2634 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_prim_id
=
2635 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2636 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_layer_id
=
2637 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2638 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_clip_dists
=
2639 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2640 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_viewport_index
=
2641 infos
[MESA_SHADER_FRAGMENT
].ps
.viewport_index_input
;
2643 /* NGG passthrough mode can't be enabled for vertex shaders
2644 * that export the primitive ID.
2646 * TODO: I should really refactor the keys logic.
2648 if (nir
[MESA_SHADER_VERTEX
] &&
2649 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
) {
2650 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg_passthrough
= false;
2653 filled_stages
|= (1 << MESA_SHADER_FRAGMENT
);
2656 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2657 infos
[MESA_SHADER_TESS_CTRL
].tcs
.tes_inputs_read
=
2658 nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
;
2659 infos
[MESA_SHADER_TESS_CTRL
].tcs
.tes_patch_inputs_read
=
2660 nir
[MESA_SHADER_TESS_EVAL
]->info
.patch_inputs_read
;
2663 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2664 nir
[MESA_SHADER_TESS_CTRL
]) {
2665 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2666 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2667 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2669 radv_nir_shader_info_init(&infos
[MESA_SHADER_TESS_CTRL
]);
2671 for (int i
= 0; i
< 2; i
++) {
2672 radv_nir_shader_info_pass(combined_nir
[i
],
2673 pipeline
->layout
, &key
,
2674 &infos
[MESA_SHADER_TESS_CTRL
],
2675 pipeline
->device
->physical_device
->use_aco
);
2678 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2679 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2680 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2681 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2683 filled_stages
|= (1 << MESA_SHADER_VERTEX
);
2684 filled_stages
|= (1 << MESA_SHADER_TESS_CTRL
);
2687 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2688 nir
[MESA_SHADER_GEOMETRY
]) {
2689 gl_shader_stage pre_stage
= nir
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2690 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2692 radv_nir_shader_info_init(&infos
[MESA_SHADER_GEOMETRY
]);
2694 for (int i
= 0; i
< 2; i
++) {
2695 radv_nir_shader_info_pass(combined_nir
[i
],
2698 &infos
[MESA_SHADER_GEOMETRY
],
2699 pipeline
->device
->physical_device
->use_aco
);
2702 filled_stages
|= (1 << pre_stage
);
2703 filled_stages
|= (1 << MESA_SHADER_GEOMETRY
);
2706 active_stages
^= filled_stages
;
2707 while (active_stages
) {
2708 int i
= u_bit_scan(&active_stages
);
2710 if (i
== MESA_SHADER_TESS_CTRL
) {
2711 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
=
2712 util_last_bit64(infos
[MESA_SHADER_VERTEX
].vs
.ls_outputs_written
);
2715 if (i
== MESA_SHADER_TESS_EVAL
) {
2716 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2717 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2718 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2719 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2722 radv_nir_shader_info_init(&infos
[i
]);
2723 radv_nir_shader_info_pass(nir
[i
], pipeline
->layout
,
2724 &keys
[i
], &infos
[i
], pipeline
->device
->physical_device
->use_aco
);
2727 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2729 infos
[i
].wave_size
=
2730 radv_get_wave_size(pipeline
->device
, pStages
[i
],
2732 infos
[i
].ballot_bit_size
=
2733 radv_get_ballot_bit_size(pipeline
->device
,
2741 merge_tess_info(struct shader_info
*tes_info
,
2742 const struct shader_info
*tcs_info
)
2744 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2746 * "PointMode. Controls generation of points rather than triangles
2747 * or lines. This functionality defaults to disabled, and is
2748 * enabled if either shader stage includes the execution mode.
2750 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2751 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2752 * and OutputVertices, it says:
2754 * "One mode must be set in at least one of the tessellation
2757 * So, the fields can be set in either the TCS or TES, but they must
2758 * agree if set in both. Our backend looks at TES, so bitwise-or in
2759 * the values from the TCS.
2761 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
2762 tes_info
->tess
.tcs_vertices_out
== 0 ||
2763 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
2764 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
2766 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2767 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2768 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
2769 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
2771 assert(tcs_info
->tess
.primitive_mode
== 0 ||
2772 tes_info
->tess
.primitive_mode
== 0 ||
2773 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
2774 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
2775 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
2776 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
2780 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT
*ext
)
2785 if (ext
->pPipelineCreationFeedback
) {
2786 ext
->pPipelineCreationFeedback
->flags
= 0;
2787 ext
->pPipelineCreationFeedback
->duration
= 0;
2790 for (unsigned i
= 0; i
< ext
->pipelineStageCreationFeedbackCount
; ++i
) {
2791 ext
->pPipelineStageCreationFeedbacks
[i
].flags
= 0;
2792 ext
->pPipelineStageCreationFeedbacks
[i
].duration
= 0;
2797 void radv_start_feedback(VkPipelineCreationFeedbackEXT
*feedback
)
2802 feedback
->duration
-= radv_get_current_time();
2803 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
2807 void radv_stop_feedback(VkPipelineCreationFeedbackEXT
*feedback
, bool cache_hit
)
2812 feedback
->duration
+= radv_get_current_time();
2813 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
|
2814 (cache_hit
? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
: 0);
2817 void radv_create_shaders(struct radv_pipeline
*pipeline
,
2818 struct radv_device
*device
,
2819 struct radv_pipeline_cache
*cache
,
2820 const struct radv_pipeline_key
*key
,
2821 const VkPipelineShaderStageCreateInfo
**pStages
,
2822 const VkPipelineCreateFlags flags
,
2823 VkPipelineCreationFeedbackEXT
*pipeline_feedback
,
2824 VkPipelineCreationFeedbackEXT
**stage_feedbacks
)
2826 struct radv_shader_module fs_m
= {0};
2827 struct radv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
2828 nir_shader
*nir
[MESA_SHADER_STAGES
] = {0};
2829 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2830 struct radv_shader_variant_key keys
[MESA_SHADER_STAGES
] = {{{{{0}}}}};
2831 struct radv_shader_info infos
[MESA_SHADER_STAGES
] = {0};
2832 unsigned char hash
[20], gs_copy_hash
[20];
2833 bool keep_executable_info
= (flags
& VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
) || device
->keep_shader_info
;
2834 bool keep_statistic_info
= (flags
& VK_PIPELINE_CREATE_CAPTURE_STATISTICS_BIT_KHR
) || device
->keep_shader_info
;
2836 radv_start_feedback(pipeline_feedback
);
2838 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2840 modules
[i
] = radv_shader_module_from_handle(pStages
[i
]->module
);
2841 if (modules
[i
]->nir
)
2842 _mesa_sha1_compute(modules
[i
]->nir
->info
.name
,
2843 strlen(modules
[i
]->nir
->info
.name
),
2846 pipeline
->active_stages
|= mesa_to_vk_shader_stage(i
);
2850 radv_hash_shaders(hash
, pStages
, pipeline
->layout
, key
, get_hash_flags(device
));
2851 memcpy(gs_copy_hash
, hash
, 20);
2852 gs_copy_hash
[0] ^= 1;
2854 bool found_in_application_cache
= true;
2855 if (modules
[MESA_SHADER_GEOMETRY
] && !keep_executable_info
&& !keep_statistic_info
) {
2856 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2857 radv_create_shader_variants_from_pipeline_cache(device
, cache
, gs_copy_hash
, variants
,
2858 &found_in_application_cache
);
2859 pipeline
->gs_copy_shader
= variants
[MESA_SHADER_GEOMETRY
];
2862 if (!keep_executable_info
&& !keep_statistic_info
&&
2863 radv_create_shader_variants_from_pipeline_cache(device
, cache
, hash
, pipeline
->shaders
,
2864 &found_in_application_cache
) &&
2865 (!modules
[MESA_SHADER_GEOMETRY
] || pipeline
->gs_copy_shader
)) {
2866 radv_stop_feedback(pipeline_feedback
, found_in_application_cache
);
2870 if (!modules
[MESA_SHADER_FRAGMENT
] && !modules
[MESA_SHADER_COMPUTE
]) {
2872 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
2873 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "noop_fs");
2874 fs_m
.nir
= fs_b
.shader
;
2875 modules
[MESA_SHADER_FRAGMENT
] = &fs_m
;
2878 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2879 const VkPipelineShaderStageCreateInfo
*stage
= pStages
[i
];
2880 unsigned subgroup_size
= 64, ballot_bit_size
= 64;
2885 radv_start_feedback(stage_feedbacks
[i
]);
2887 if (key
->compute_subgroup_size
) {
2888 /* Only compute shaders currently support requiring a
2889 * specific subgroup size.
2891 assert(i
== MESA_SHADER_COMPUTE
);
2892 subgroup_size
= key
->compute_subgroup_size
;
2893 ballot_bit_size
= key
->compute_subgroup_size
;
2896 nir
[i
] = radv_shader_compile_to_nir(device
, modules
[i
],
2897 stage
? stage
->pName
: "main", i
,
2898 stage
? stage
->pSpecializationInfo
: NULL
,
2899 flags
, pipeline
->layout
,
2900 subgroup_size
, ballot_bit_size
);
2902 /* We don't want to alter meta shaders IR directly so clone it
2905 if (nir
[i
]->info
.name
) {
2906 nir
[i
] = nir_shader_clone(NULL
, nir
[i
]);
2909 radv_stop_feedback(stage_feedbacks
[i
], false);
2912 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2913 nir_lower_patch_vertices(nir
[MESA_SHADER_TESS_EVAL
], nir
[MESA_SHADER_TESS_CTRL
]->info
.tess
.tcs_vertices_out
, NULL
);
2914 merge_tess_info(&nir
[MESA_SHADER_TESS_EVAL
]->info
, &nir
[MESA_SHADER_TESS_CTRL
]->info
);
2917 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
2918 radv_link_shaders(pipeline
, nir
);
2920 radv_set_linked_driver_locations(pipeline
, nir
, infos
);
2922 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2924 /* do this again since information such as outputs_read can be out-of-date */
2925 nir_shader_gather_info(nir
[i
], nir_shader_get_entrypoint(nir
[i
]));
2927 if (device
->physical_device
->use_aco
) {
2928 NIR_PASS_V(nir
[i
], nir_lower_non_uniform_access
,
2929 nir_lower_non_uniform_ubo_access
|
2930 nir_lower_non_uniform_ssbo_access
|
2931 nir_lower_non_uniform_texture_access
|
2932 nir_lower_non_uniform_image_access
);
2934 NIR_PASS_V(nir
[i
], nir_lower_bool_to_int32
);
2938 if (nir
[MESA_SHADER_FRAGMENT
])
2939 radv_lower_fs_io(nir
[MESA_SHADER_FRAGMENT
]);
2941 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2942 if (radv_can_dump_shader(device
, modules
[i
], false))
2943 nir_print_shader(nir
[i
], stderr
);
2946 radv_fill_shader_keys(device
, keys
, key
, nir
);
2948 radv_fill_shader_info(pipeline
, pStages
, keys
, infos
, nir
);
2950 if ((nir
[MESA_SHADER_VERTEX
] &&
2951 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) ||
2952 (nir
[MESA_SHADER_TESS_EVAL
] &&
2953 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
)) {
2954 struct gfx10_ngg_info
*ngg_info
;
2956 if (nir
[MESA_SHADER_GEOMETRY
])
2957 ngg_info
= &infos
[MESA_SHADER_GEOMETRY
].ngg_info
;
2958 else if (nir
[MESA_SHADER_TESS_CTRL
])
2959 ngg_info
= &infos
[MESA_SHADER_TESS_EVAL
].ngg_info
;
2961 ngg_info
= &infos
[MESA_SHADER_VERTEX
].ngg_info
;
2963 gfx10_get_ngg_info(key
, pipeline
, nir
, infos
, ngg_info
);
2964 } else if (nir
[MESA_SHADER_GEOMETRY
]) {
2965 struct gfx9_gs_info
*gs_info
=
2966 &infos
[MESA_SHADER_GEOMETRY
].gs_ring_info
;
2968 gfx9_get_gs_info(key
, pipeline
, nir
, infos
, gs_info
);
2971 if(modules
[MESA_SHADER_GEOMETRY
]) {
2972 struct radv_shader_binary
*gs_copy_binary
= NULL
;
2973 if (!pipeline
->gs_copy_shader
&&
2974 !radv_pipeline_has_ngg(pipeline
)) {
2975 struct radv_shader_info info
= {};
2976 struct radv_shader_variant_key key
= {};
2978 key
.has_multiview_view_index
=
2979 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
;
2981 radv_nir_shader_info_pass(nir
[MESA_SHADER_GEOMETRY
],
2982 pipeline
->layout
, &key
,
2983 &info
, pipeline
->device
->physical_device
->use_aco
);
2984 info
.wave_size
= 64; /* Wave32 not supported. */
2985 info
.ballot_bit_size
= 64;
2987 pipeline
->gs_copy_shader
= radv_create_gs_copy_shader(
2988 device
, nir
[MESA_SHADER_GEOMETRY
], &info
,
2989 &gs_copy_binary
, keep_executable_info
, keep_statistic_info
,
2990 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
);
2993 if (!keep_executable_info
&& !keep_statistic_info
&& pipeline
->gs_copy_shader
) {
2994 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2995 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2997 binaries
[MESA_SHADER_GEOMETRY
] = gs_copy_binary
;
2998 variants
[MESA_SHADER_GEOMETRY
] = pipeline
->gs_copy_shader
;
3000 radv_pipeline_cache_insert_shaders(device
, cache
,
3005 free(gs_copy_binary
);
3008 if (nir
[MESA_SHADER_FRAGMENT
]) {
3009 if (!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]) {
3010 radv_start_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
]);
3012 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] =
3013 radv_shader_variant_compile(device
, modules
[MESA_SHADER_FRAGMENT
], &nir
[MESA_SHADER_FRAGMENT
], 1,
3014 pipeline
->layout
, keys
+ MESA_SHADER_FRAGMENT
,
3015 infos
+ MESA_SHADER_FRAGMENT
,
3016 keep_executable_info
, keep_statistic_info
,
3017 &binaries
[MESA_SHADER_FRAGMENT
]);
3019 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
], false);
3023 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_TESS_CTRL
]) {
3024 if (!pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]) {
3025 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
3026 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
3027 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
3029 radv_start_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
]);
3031 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_TESS_CTRL
], combined_nir
, 2,
3033 &key
, &infos
[MESA_SHADER_TESS_CTRL
], keep_executable_info
,
3034 keep_statistic_info
, &binaries
[MESA_SHADER_TESS_CTRL
]);
3036 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
], false);
3038 modules
[MESA_SHADER_VERTEX
] = NULL
;
3039 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
3040 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
3043 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_GEOMETRY
]) {
3044 gl_shader_stage pre_stage
= modules
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
3045 if (!pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
3046 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
3048 radv_start_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
]);
3050 pipeline
->shaders
[MESA_SHADER_GEOMETRY
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_GEOMETRY
], combined_nir
, 2,
3052 &keys
[pre_stage
], &infos
[MESA_SHADER_GEOMETRY
], keep_executable_info
,
3053 keep_statistic_info
, &binaries
[MESA_SHADER_GEOMETRY
]);
3055 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
], false);
3057 modules
[pre_stage
] = NULL
;
3060 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
3061 if(modules
[i
] && !pipeline
->shaders
[i
]) {
3062 if (i
== MESA_SHADER_TESS_CTRL
) {
3063 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.ls_outputs_written
);
3065 if (i
== MESA_SHADER_TESS_EVAL
) {
3066 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
3067 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
3070 radv_start_feedback(stage_feedbacks
[i
]);
3072 pipeline
->shaders
[i
] = radv_shader_variant_compile(device
, modules
[i
], &nir
[i
], 1,
3074 keys
+ i
, infos
+ i
, keep_executable_info
,
3075 keep_statistic_info
, &binaries
[i
]);
3077 radv_stop_feedback(stage_feedbacks
[i
], false);
3081 if (!keep_executable_info
&& !keep_statistic_info
) {
3082 radv_pipeline_cache_insert_shaders(device
, cache
, hash
, pipeline
->shaders
,
3086 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
3089 ralloc_free(nir
[i
]);
3091 if (radv_can_dump_shader_stats(device
, modules
[i
]))
3092 radv_shader_dump_stats(device
,
3093 pipeline
->shaders
[i
],
3099 ralloc_free(fs_m
.nir
);
3101 radv_stop_feedback(pipeline_feedback
, false);
3105 radv_pipeline_stage_to_user_data_0(struct radv_pipeline
*pipeline
,
3106 gl_shader_stage stage
, enum chip_class chip_class
)
3108 bool has_gs
= radv_pipeline_has_gs(pipeline
);
3109 bool has_tess
= radv_pipeline_has_tess(pipeline
);
3110 bool has_ngg
= radv_pipeline_has_ngg(pipeline
);
3113 case MESA_SHADER_FRAGMENT
:
3114 return R_00B030_SPI_SHADER_USER_DATA_PS_0
;
3115 case MESA_SHADER_VERTEX
:
3117 if (chip_class
>= GFX10
) {
3118 return R_00B430_SPI_SHADER_USER_DATA_HS_0
;
3119 } else if (chip_class
== GFX9
) {
3120 return R_00B430_SPI_SHADER_USER_DATA_LS_0
;
3122 return R_00B530_SPI_SHADER_USER_DATA_LS_0
;
3128 if (chip_class
>= GFX10
) {
3129 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3131 return R_00B330_SPI_SHADER_USER_DATA_ES_0
;
3136 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3138 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3139 case MESA_SHADER_GEOMETRY
:
3140 return chip_class
== GFX9
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
3141 R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3142 case MESA_SHADER_COMPUTE
:
3143 return R_00B900_COMPUTE_USER_DATA_0
;
3144 case MESA_SHADER_TESS_CTRL
:
3145 return chip_class
== GFX9
? R_00B430_SPI_SHADER_USER_DATA_LS_0
:
3146 R_00B430_SPI_SHADER_USER_DATA_HS_0
;
3147 case MESA_SHADER_TESS_EVAL
:
3149 return chip_class
>= GFX10
? R_00B230_SPI_SHADER_USER_DATA_GS_0
:
3150 R_00B330_SPI_SHADER_USER_DATA_ES_0
;
3151 } else if (has_ngg
) {
3152 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3154 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3157 unreachable("unknown shader");
3161 struct radv_bin_size_entry
{
3167 radv_gfx9_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3169 static const struct radv_bin_size_entry color_size_table
[][3][9] = {
3173 /* One shader engine */
3179 { UINT_MAX
, { 0, 0}},
3182 /* Two shader engines */
3188 { UINT_MAX
, { 0, 0}},
3191 /* Four shader engines */
3196 { UINT_MAX
, { 0, 0}},
3202 /* One shader engine */
3208 { UINT_MAX
, { 0, 0}},
3211 /* Two shader engines */
3217 { UINT_MAX
, { 0, 0}},
3220 /* Four shader engines */
3227 { UINT_MAX
, { 0, 0}},
3233 /* One shader engine */
3240 { UINT_MAX
, { 0, 0}},
3243 /* Two shader engines */
3251 { UINT_MAX
, { 0, 0}},
3254 /* Four shader engines */
3262 { UINT_MAX
, { 0, 0}},
3266 static const struct radv_bin_size_entry ds_size_table
[][3][9] = {
3270 // One shader engine
3277 { UINT_MAX
, { 0, 0}},
3280 // Two shader engines
3288 { UINT_MAX
, { 0, 0}},
3291 // Four shader engines
3299 { UINT_MAX
, { 0, 0}},
3305 // One shader engine
3313 { UINT_MAX
, { 0, 0}},
3316 // Two shader engines
3325 { UINT_MAX
, { 0, 0}},
3328 // Four shader engines
3337 { UINT_MAX
, { 0, 0}},
3343 // One shader engine
3351 { UINT_MAX
, { 0, 0}},
3354 // Two shader engines
3363 { UINT_MAX
, { 0, 0}},
3366 // Four shader engines
3374 { UINT_MAX
, { 0, 0}},
3379 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3380 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3381 VkExtent2D extent
= {512, 512};
3383 unsigned log_num_rb_per_se
=
3384 util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.num_render_backends
/
3385 pipeline
->device
->physical_device
->rad_info
.max_se
);
3386 unsigned log_num_se
= util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.max_se
);
3388 unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3389 unsigned ps_iter_samples
= 1u << G_028804_PS_ITER_SAMPLES(pipeline
->graphics
.ms
.db_eqaa
);
3390 unsigned effective_samples
= total_samples
;
3391 unsigned color_bytes_per_pixel
= 0;
3393 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3394 radv_pipeline_get_color_blend_state(pCreateInfo
);
3396 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3397 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3400 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3403 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3404 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3407 /* MSAA images typically don't use all samples all the time. */
3408 if (effective_samples
>= 2 && ps_iter_samples
<= 1)
3409 effective_samples
= 2;
3410 color_bytes_per_pixel
*= effective_samples
;
3413 const struct radv_bin_size_entry
*color_entry
= color_size_table
[log_num_rb_per_se
][log_num_se
];
3414 while(color_entry
[1].bpp
<= color_bytes_per_pixel
)
3417 extent
= color_entry
->extent
;
3419 if (subpass
->depth_stencil_attachment
) {
3420 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3422 /* Coefficients taken from AMDVLK */
3423 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3424 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3425 unsigned ds_bytes_per_pixel
= 4 * (depth_coeff
+ stencil_coeff
) * total_samples
;
3427 const struct radv_bin_size_entry
*ds_entry
= ds_size_table
[log_num_rb_per_se
][log_num_se
];
3428 while(ds_entry
[1].bpp
<= ds_bytes_per_pixel
)
3431 if (ds_entry
->extent
.width
* ds_entry
->extent
.height
< extent
.width
* extent
.height
)
3432 extent
= ds_entry
->extent
;
3439 radv_gfx10_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3441 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3442 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3443 VkExtent2D extent
= {512, 512};
3445 const unsigned db_tag_size
= 64;
3446 const unsigned db_tag_count
= 312;
3447 const unsigned color_tag_size
= 1024;
3448 const unsigned color_tag_count
= 31;
3449 const unsigned fmask_tag_size
= 256;
3450 const unsigned fmask_tag_count
= 44;
3452 const unsigned rb_count
= pipeline
->device
->physical_device
->rad_info
.num_render_backends
;
3453 const unsigned pipe_count
= MAX2(rb_count
, pipeline
->device
->physical_device
->rad_info
.num_sdp_interfaces
);
3455 const unsigned db_tag_part
= (db_tag_count
* rb_count
/ pipe_count
) * db_tag_size
* pipe_count
;
3456 const unsigned color_tag_part
= (color_tag_count
* rb_count
/ pipe_count
) * color_tag_size
* pipe_count
;
3457 const unsigned fmask_tag_part
= (fmask_tag_count
* rb_count
/ pipe_count
) * fmask_tag_size
* pipe_count
;
3459 const unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3460 const unsigned samples_log
= util_logbase2_ceil(total_samples
);
3462 unsigned color_bytes_per_pixel
= 0;
3463 unsigned fmask_bytes_per_pixel
= 0;
3465 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3466 radv_pipeline_get_color_blend_state(pCreateInfo
);
3468 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3469 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3472 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3475 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3476 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3478 if (total_samples
> 1) {
3479 assert(samples_log
<= 3);
3480 const unsigned fmask_array
[] = {0, 1, 1, 4};
3481 fmask_bytes_per_pixel
+= fmask_array
[samples_log
];
3485 color_bytes_per_pixel
*= total_samples
;
3487 color_bytes_per_pixel
= MAX2(color_bytes_per_pixel
, 1);
3489 const unsigned color_pixel_count_log
= util_logbase2(color_tag_part
/ color_bytes_per_pixel
);
3490 extent
.width
= 1ull << ((color_pixel_count_log
+ 1) / 2);
3491 extent
.height
= 1ull << (color_pixel_count_log
/ 2);
3493 if (fmask_bytes_per_pixel
) {
3494 const unsigned fmask_pixel_count_log
= util_logbase2(fmask_tag_part
/ fmask_bytes_per_pixel
);
3496 const VkExtent2D fmask_extent
= (VkExtent2D
){
3497 .width
= 1ull << ((fmask_pixel_count_log
+ 1) / 2),
3498 .height
= 1ull << (color_pixel_count_log
/ 2)
3501 if (fmask_extent
.width
* fmask_extent
.height
< extent
.width
* extent
.height
)
3502 extent
= fmask_extent
;
3505 if (subpass
->depth_stencil_attachment
) {
3506 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3508 /* Coefficients taken from AMDVLK */
3509 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3510 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3511 unsigned db_bytes_per_pixel
= (depth_coeff
+ stencil_coeff
) * total_samples
;
3513 const unsigned db_pixel_count_log
= util_logbase2(db_tag_part
/ db_bytes_per_pixel
);
3515 const VkExtent2D db_extent
= (VkExtent2D
){
3516 .width
= 1ull << ((db_pixel_count_log
+ 1) / 2),
3517 .height
= 1ull << (color_pixel_count_log
/ 2)
3520 if (db_extent
.width
* db_extent
.height
< extent
.width
* extent
.height
)
3524 extent
.width
= MAX2(extent
.width
, 128);
3525 extent
.height
= MAX2(extent
.width
, 64);
3531 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3532 struct radv_pipeline
*pipeline
,
3533 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3535 uint32_t pa_sc_binner_cntl_0
=
3536 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC
) |
3537 S_028C44_DISABLE_START_OF_PRIM(1);
3538 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3540 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3541 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3542 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3543 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3544 radv_pipeline_get_color_blend_state(pCreateInfo
);
3545 unsigned min_bytes_per_pixel
= 0;
3548 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3549 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3552 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3555 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3556 unsigned bytes
= vk_format_get_blocksize(format
);
3557 if (!min_bytes_per_pixel
|| bytes
< min_bytes_per_pixel
)
3558 min_bytes_per_pixel
= bytes
;
3562 pa_sc_binner_cntl_0
=
3563 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC
) |
3564 S_028C44_BIN_SIZE_X(0) |
3565 S_028C44_BIN_SIZE_Y(0) |
3566 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3567 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel
<= 4 ? 2 : 1) | /* 128 or 64 */
3568 S_028C44_DISABLE_START_OF_PRIM(1);
3571 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3572 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3575 struct radv_binning_settings
3576 radv_get_binning_settings(const struct radv_physical_device
*pdev
)
3578 struct radv_binning_settings settings
;
3579 if (pdev
->rad_info
.has_dedicated_vram
) {
3580 if (pdev
->rad_info
.num_render_backends
> 4) {
3581 settings
.context_states_per_bin
= 1;
3582 settings
.persistent_states_per_bin
= 1;
3584 settings
.context_states_per_bin
= 3;
3585 settings
.persistent_states_per_bin
= 8;
3587 settings
.fpovs_per_batch
= 63;
3589 /* The context states are affected by the scissor bug. */
3590 settings
.context_states_per_bin
= 6;
3591 /* 32 causes hangs for RAVEN. */
3592 settings
.persistent_states_per_bin
= 16;
3593 settings
.fpovs_per_batch
= 63;
3596 if (pdev
->rad_info
.has_gfx9_scissor_bug
)
3597 settings
.context_states_per_bin
= 1;
3603 radv_pipeline_generate_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3604 struct radv_pipeline
*pipeline
,
3605 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3606 const struct radv_blend_state
*blend
)
3608 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
3611 VkExtent2D bin_size
;
3612 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3613 bin_size
= radv_gfx10_compute_bin_size(pipeline
, pCreateInfo
);
3614 } else if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3615 bin_size
= radv_gfx9_compute_bin_size(pipeline
, pCreateInfo
);
3617 unreachable("Unhandled generation for binning bin size calculation");
3619 if (pipeline
->device
->pbb_allowed
&& bin_size
.width
&& bin_size
.height
) {
3620 struct radv_binning_settings settings
=
3621 radv_get_binning_settings(pipeline
->device
->physical_device
);
3623 bool disable_start_of_prim
= true;
3624 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3626 const struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3628 if (pipeline
->device
->dfsm_allowed
&& ps
&&
3629 !ps
->info
.ps
.can_discard
&&
3630 !ps
->info
.ps
.writes_memory
&&
3631 blend
->cb_target_enabled_4bit
) {
3632 db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_AUTO
);
3633 disable_start_of_prim
= (blend
->blend_enable_4bit
& blend
->cb_target_enabled_4bit
) != 0;
3636 const uint32_t pa_sc_binner_cntl_0
=
3637 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED
) |
3638 S_028C44_BIN_SIZE_X(bin_size
.width
== 16) |
3639 S_028C44_BIN_SIZE_Y(bin_size
.height
== 16) |
3640 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size
.width
, 32)) - 5) |
3641 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size
.height
, 32)) - 5) |
3642 S_028C44_CONTEXT_STATES_PER_BIN(settings
.context_states_per_bin
- 1) |
3643 S_028C44_PERSISTENT_STATES_PER_BIN(settings
.persistent_states_per_bin
- 1) |
3644 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim
) |
3645 S_028C44_FPOVS_PER_BATCH(settings
.fpovs_per_batch
) |
3646 S_028C44_OPTIMAL_BIN_SELECTION(1);
3648 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3649 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3651 radv_pipeline_generate_disabled_binning_state(ctx_cs
, pipeline
, pCreateInfo
);
3656 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf
*ctx_cs
,
3657 struct radv_pipeline
*pipeline
,
3658 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3659 const struct radv_graphics_pipeline_create_info
*extra
)
3661 const VkPipelineDepthStencilStateCreateInfo
*vkds
= radv_pipeline_get_depth_stencil_state(pCreateInfo
);
3662 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3663 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3664 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3665 struct radv_render_pass_attachment
*attachment
= NULL
;
3666 uint32_t db_depth_control
= 0, db_stencil_control
= 0;
3667 uint32_t db_render_control
= 0, db_render_override2
= 0;
3668 uint32_t db_render_override
= 0;
3670 if (subpass
->depth_stencil_attachment
)
3671 attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3673 bool has_depth_attachment
= attachment
&& vk_format_is_depth(attachment
->format
);
3674 bool has_stencil_attachment
= attachment
&& vk_format_is_stencil(attachment
->format
);
3676 if (vkds
&& has_depth_attachment
) {
3677 db_depth_control
= S_028800_Z_ENABLE(vkds
->depthTestEnable
? 1 : 0) |
3678 S_028800_Z_WRITE_ENABLE(vkds
->depthWriteEnable
? 1 : 0) |
3679 S_028800_ZFUNC(vkds
->depthCompareOp
) |
3680 S_028800_DEPTH_BOUNDS_ENABLE(vkds
->depthBoundsTestEnable
? 1 : 0);
3682 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3683 db_render_override2
|= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment
->samples
> 2);
3686 if (has_stencil_attachment
&& vkds
&& vkds
->stencilTestEnable
) {
3687 db_depth_control
|= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3688 db_depth_control
|= S_028800_STENCILFUNC(vkds
->front
.compareOp
);
3689 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds
->front
.failOp
));
3690 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds
->front
.passOp
));
3691 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds
->front
.depthFailOp
));
3693 db_depth_control
|= S_028800_STENCILFUNC_BF(vkds
->back
.compareOp
);
3694 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds
->back
.failOp
));
3695 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds
->back
.passOp
));
3696 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds
->back
.depthFailOp
));
3699 if (attachment
&& extra
) {
3700 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(extra
->db_depth_clear
);
3701 db_render_control
|= S_028000_STENCIL_CLEAR_ENABLE(extra
->db_stencil_clear
);
3703 db_render_control
|= S_028000_RESUMMARIZE_ENABLE(extra
->resummarize_enable
);
3704 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(extra
->depth_compress_disable
);
3705 db_render_control
|= S_028000_STENCIL_COMPRESS_DISABLE(extra
->stencil_compress_disable
);
3706 db_render_override2
|= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra
->db_depth_disable_expclear
);
3707 db_render_override2
|= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra
->db_stencil_disable_expclear
);
3710 db_render_override
|= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
3711 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
3713 if (!pCreateInfo
->pRasterizationState
->depthClampEnable
&&
3714 ps
->info
.ps
.writes_z
) {
3715 /* From VK_EXT_depth_range_unrestricted spec:
3717 * "The behavior described in Primitive Clipping still applies.
3718 * If depth clamping is disabled the depth values are still
3719 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3720 * depth clamping is enabled the above equation is ignored and
3721 * the depth values are instead clamped to the VkViewport
3722 * minDepth and maxDepth values, which in the case of this
3723 * extension can be outside of the 0.0 to 1.0 range."
3725 db_render_override
|= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3728 radeon_set_context_reg(ctx_cs
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
3729 radeon_set_context_reg(ctx_cs
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
3731 radeon_set_context_reg(ctx_cs
, R_028000_DB_RENDER_CONTROL
, db_render_control
);
3732 radeon_set_context_reg(ctx_cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
3733 radeon_set_context_reg(ctx_cs
, R_028010_DB_RENDER_OVERRIDE2
, db_render_override2
);
3737 radv_pipeline_generate_blend_state(struct radeon_cmdbuf
*ctx_cs
,
3738 struct radv_pipeline
*pipeline
,
3739 const struct radv_blend_state
*blend
)
3741 radeon_set_context_reg_seq(ctx_cs
, R_028780_CB_BLEND0_CONTROL
, 8);
3742 radeon_emit_array(ctx_cs
, blend
->cb_blend_control
,
3744 radeon_set_context_reg(ctx_cs
, R_028808_CB_COLOR_CONTROL
, blend
->cb_color_control
);
3745 radeon_set_context_reg(ctx_cs
, R_028B70_DB_ALPHA_TO_MASK
, blend
->db_alpha_to_mask
);
3747 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
3749 radeon_set_context_reg_seq(ctx_cs
, R_028760_SX_MRT0_BLEND_OPT
, 8);
3750 radeon_emit_array(ctx_cs
, blend
->sx_mrt_blend_opt
, 8);
3753 radeon_set_context_reg(ctx_cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
3755 radeon_set_context_reg(ctx_cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
3756 radeon_set_context_reg(ctx_cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
3758 pipeline
->graphics
.col_format
= blend
->spi_shader_col_format
;
3759 pipeline
->graphics
.cb_target_mask
= blend
->cb_target_mask
;
3762 static const VkConservativeRasterizationModeEXT
3763 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo
*pCreateInfo
)
3765 const VkPipelineRasterizationConservativeStateCreateInfoEXT
*conservative_raster
=
3766 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT
);
3768 if (!conservative_raster
)
3769 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
;
3770 return conservative_raster
->conservativeRasterizationMode
;
3774 radv_pipeline_generate_raster_state(struct radeon_cmdbuf
*ctx_cs
,
3775 struct radv_pipeline
*pipeline
,
3776 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3778 const VkPipelineRasterizationStateCreateInfo
*vkraster
= pCreateInfo
->pRasterizationState
;
3779 const VkConservativeRasterizationModeEXT mode
=
3780 radv_get_conservative_raster_mode(vkraster
);
3781 uint32_t pa_sc_conservative_rast
= S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3782 bool depth_clip_disable
= vkraster
->depthClampEnable
;
3784 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*depth_clip_state
=
3785 vk_find_struct_const(vkraster
->pNext
, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
3786 if (depth_clip_state
) {
3787 depth_clip_disable
= !depth_clip_state
->depthClipEnable
;
3790 radeon_set_context_reg(ctx_cs
, R_028810_PA_CL_CLIP_CNTL
,
3791 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3792 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable
? 1 : 0) |
3793 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable
? 1 : 0) |
3794 S_028810_DX_RASTERIZATION_KILL(vkraster
->rasterizerDiscardEnable
? 1 : 0) |
3795 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3797 radeon_set_context_reg(ctx_cs
, R_0286D4_SPI_INTERP_CONTROL_0
,
3798 S_0286D4_FLAT_SHADE_ENA(1) |
3799 S_0286D4_PNT_SPRITE_ENA(1) |
3800 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
3801 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
3802 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
3803 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
3804 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3806 radeon_set_context_reg(ctx_cs
, R_028BE4_PA_SU_VTX_CNTL
,
3807 S_028BE4_PIX_CENTER(1) | // TODO verify
3808 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN
) |
3809 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
3811 radeon_set_context_reg(ctx_cs
, R_028814_PA_SU_SC_MODE_CNTL
,
3812 S_028814_FACE(vkraster
->frontFace
) |
3813 S_028814_CULL_FRONT(!!(vkraster
->cullMode
& VK_CULL_MODE_FRONT_BIT
)) |
3814 S_028814_CULL_BACK(!!(vkraster
->cullMode
& VK_CULL_MODE_BACK_BIT
)) |
3815 S_028814_POLY_MODE(vkraster
->polygonMode
!= VK_POLYGON_MODE_FILL
) |
3816 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3817 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3818 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3819 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3820 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster
->depthBiasEnable
? 1 : 0));
3822 /* Conservative rasterization. */
3823 if (mode
!= VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
) {
3824 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3826 ms
->pa_sc_aa_config
|= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3827 ms
->db_eqaa
|= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3828 S_028804_OVERRASTERIZATION_AMOUNT(4);
3830 pa_sc_conservative_rast
= S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3831 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3832 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3834 if (mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT
) {
3835 pa_sc_conservative_rast
|=
3836 S_028C4C_OVER_RAST_ENABLE(1) |
3837 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3838 S_028C4C_UNDER_RAST_ENABLE(0) |
3839 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3840 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3842 assert(mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT
);
3843 pa_sc_conservative_rast
|=
3844 S_028C4C_OVER_RAST_ENABLE(0) |
3845 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3846 S_028C4C_UNDER_RAST_ENABLE(1) |
3847 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3848 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3852 radeon_set_context_reg(ctx_cs
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
3853 pa_sc_conservative_rast
);
3858 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf
*ctx_cs
,
3859 struct radv_pipeline
*pipeline
)
3861 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3863 radeon_set_context_reg_seq(ctx_cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
3864 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[0]);
3865 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[1]);
3867 radeon_set_context_reg(ctx_cs
, R_028804_DB_EQAA
, ms
->db_eqaa
);
3868 radeon_set_context_reg(ctx_cs
, R_028A48_PA_SC_MODE_CNTL_0
, ms
->pa_sc_mode_cntl_0
);
3869 radeon_set_context_reg(ctx_cs
, R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
3870 radeon_set_context_reg(ctx_cs
, R_028BDC_PA_SC_LINE_CNTL
, ms
->pa_sc_line_cntl
);
3871 radeon_set_context_reg(ctx_cs
, R_028BE0_PA_SC_AA_CONFIG
, ms
->pa_sc_aa_config
);
3873 /* The exclusion bits can be set to improve rasterization efficiency
3874 * if no sample lies on the pixel boundary (-8 sample offset). It's
3875 * currently always TRUE because the driver doesn't support 16 samples.
3877 bool exclusion
= pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
3878 radeon_set_context_reg(ctx_cs
, R_02882C_PA_SU_PRIM_FILTER_CNTL
,
3879 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) |
3880 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3882 /* GFX9: Flush DFSM when the AA mode changes. */
3883 if (pipeline
->device
->dfsm_allowed
) {
3884 radeon_emit(ctx_cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3885 radeon_emit(ctx_cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3890 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf
*ctx_cs
,
3891 struct radv_pipeline
*pipeline
)
3893 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3894 const struct radv_shader_variant
*vs
=
3895 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] ?
3896 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] :
3897 pipeline
->shaders
[MESA_SHADER_VERTEX
];
3898 unsigned vgt_primitiveid_en
= 0;
3899 uint32_t vgt_gs_mode
= 0;
3901 if (radv_pipeline_has_ngg(pipeline
))
3904 if (radv_pipeline_has_gs(pipeline
)) {
3905 const struct radv_shader_variant
*gs
=
3906 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3908 vgt_gs_mode
= ac_vgt_gs_mode(gs
->info
.gs
.vertices_out
,
3909 pipeline
->device
->physical_device
->rad_info
.chip_class
);
3910 } else if (outinfo
->export_prim_id
|| vs
->info
.uses_prim_id
) {
3911 vgt_gs_mode
= S_028A40_MODE(V_028A40_GS_SCENARIO_A
);
3912 vgt_primitiveid_en
|= S_028A84_PRIMITIVEID_EN(1);
3915 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
, vgt_primitiveid_en
);
3916 radeon_set_context_reg(ctx_cs
, R_028A40_VGT_GS_MODE
, vgt_gs_mode
);
3920 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf
*ctx_cs
,
3921 struct radeon_cmdbuf
*cs
,
3922 struct radv_pipeline
*pipeline
,
3923 struct radv_shader_variant
*shader
)
3925 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3927 radeon_set_sh_reg_seq(cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
3928 radeon_emit(cs
, va
>> 8);
3929 radeon_emit(cs
, S_00B124_MEM_BASE(va
>> 40));
3930 radeon_emit(cs
, shader
->config
.rsrc1
);
3931 radeon_emit(cs
, shader
->config
.rsrc2
);
3933 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3934 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3935 clip_dist_mask
= outinfo
->clip_dist_mask
;
3936 cull_dist_mask
= outinfo
->cull_dist_mask
;
3937 total_mask
= clip_dist_mask
| cull_dist_mask
;
3938 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3939 outinfo
->writes_layer
||
3940 outinfo
->writes_viewport_index
;
3941 unsigned spi_vs_out_config
, nparams
;
3943 /* VS is required to export at least one param. */
3944 nparams
= MAX2(outinfo
->param_exports
, 1);
3945 spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
3947 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3948 spi_vs_out_config
|= S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0);
3951 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
, spi_vs_out_config
);
3953 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3954 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3955 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3956 V_02870C_SPI_SHADER_4COMP
:
3957 V_02870C_SPI_SHADER_NONE
) |
3958 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3959 V_02870C_SPI_SHADER_4COMP
:
3960 V_02870C_SPI_SHADER_NONE
) |
3961 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3962 V_02870C_SPI_SHADER_4COMP
:
3963 V_02870C_SPI_SHADER_NONE
));
3965 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
3966 S_028818_VTX_W0_FMT(1) |
3967 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3968 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3969 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3971 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3972 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3973 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3974 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3975 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3976 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3977 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3978 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3979 cull_dist_mask
<< 8 |
3982 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
3983 radeon_set_context_reg(ctx_cs
, R_028AB4_VGT_REUSE_OFF
,
3984 outinfo
->writes_viewport_index
);
3988 radv_pipeline_generate_hw_es(struct radeon_cmdbuf
*cs
,
3989 struct radv_pipeline
*pipeline
,
3990 struct radv_shader_variant
*shader
)
3992 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3994 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
3995 radeon_emit(cs
, va
>> 8);
3996 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3997 radeon_emit(cs
, shader
->config
.rsrc1
);
3998 radeon_emit(cs
, shader
->config
.rsrc2
);
4002 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf
*cs
,
4003 struct radv_pipeline
*pipeline
,
4004 struct radv_shader_variant
*shader
,
4005 const struct radv_tessellation_state
*tess
)
4007 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
4008 uint32_t rsrc2
= shader
->config
.rsrc2
;
4010 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
4011 radeon_emit(cs
, va
>> 8);
4012 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
4014 rsrc2
|= S_00B52C_LDS_SIZE(tess
->lds_size
);
4015 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX7
&&
4016 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
4017 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
4019 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
4020 radeon_emit(cs
, shader
->config
.rsrc1
);
4021 radeon_emit(cs
, rsrc2
);
4025 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf
*ctx_cs
,
4026 struct radeon_cmdbuf
*cs
,
4027 struct radv_pipeline
*pipeline
,
4028 struct radv_shader_variant
*shader
)
4030 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
4031 gl_shader_stage es_type
=
4032 radv_pipeline_has_tess(pipeline
) ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
4033 struct radv_shader_variant
*es
=
4034 es_type
== MESA_SHADER_TESS_EVAL
? pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] : pipeline
->shaders
[MESA_SHADER_VERTEX
];
4035 const struct gfx10_ngg_info
*ngg_state
= &shader
->info
.ngg_info
;
4037 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
4038 radeon_emit(cs
, va
>> 8);
4039 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
4040 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
4041 radeon_emit(cs
, shader
->config
.rsrc1
);
4042 radeon_emit(cs
, shader
->config
.rsrc2
);
4044 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
4045 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
4046 clip_dist_mask
= outinfo
->clip_dist_mask
;
4047 cull_dist_mask
= outinfo
->cull_dist_mask
;
4048 total_mask
= clip_dist_mask
| cull_dist_mask
;
4049 bool misc_vec_ena
= outinfo
->writes_pointsize
||
4050 outinfo
->writes_layer
||
4051 outinfo
->writes_viewport_index
;
4052 bool es_enable_prim_id
= outinfo
->export_prim_id
||
4053 (es
&& es
->info
.uses_prim_id
);
4054 bool break_wave_at_eoi
= false;
4058 if (es_type
== MESA_SHADER_TESS_EVAL
) {
4059 struct radv_shader_variant
*gs
=
4060 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4062 if (es_enable_prim_id
|| (gs
&& gs
->info
.uses_prim_id
))
4063 break_wave_at_eoi
= true;
4066 nparams
= MAX2(outinfo
->param_exports
, 1);
4067 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
4068 S_0286C4_VS_EXPORT_COUNT(nparams
- 1) |
4069 S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0));
4071 radeon_set_context_reg(ctx_cs
, R_028708_SPI_SHADER_IDX_FORMAT
,
4072 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP
));
4073 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
4074 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
4075 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
4076 V_02870C_SPI_SHADER_4COMP
:
4077 V_02870C_SPI_SHADER_NONE
) |
4078 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
4079 V_02870C_SPI_SHADER_4COMP
:
4080 V_02870C_SPI_SHADER_NONE
) |
4081 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
4082 V_02870C_SPI_SHADER_4COMP
:
4083 V_02870C_SPI_SHADER_NONE
));
4085 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
4086 S_028818_VTX_W0_FMT(1) |
4087 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
4088 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
4089 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
4090 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
4091 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
4092 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
4093 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
4094 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
4095 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
4096 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
4097 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
4098 cull_dist_mask
<< 8 |
4101 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
,
4102 S_028A84_PRIMITIVEID_EN(es_enable_prim_id
) |
4103 S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo
->export_prim_id
));
4105 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
4106 ngg_state
->vgt_esgs_ring_itemsize
);
4108 /* NGG specific registers. */
4109 struct radv_shader_variant
*gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4110 uint32_t gs_num_invocations
= gs
? gs
->info
.gs
.invocations
: 1;
4112 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4113 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state
->hw_max_esverts
) |
4114 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state
->max_gsprims
) |
4115 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state
->max_gsprims
* gs_num_invocations
));
4116 radeon_set_context_reg(ctx_cs
, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP
,
4117 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state
->max_out_verts
));
4118 radeon_set_context_reg(ctx_cs
, R_028B4C_GE_NGG_SUBGRP_CNTL
,
4119 S_028B4C_PRIM_AMP_FACTOR(ngg_state
->prim_amp_factor
) |
4120 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
4121 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
4122 S_028B90_CNT(gs_num_invocations
) |
4123 S_028B90_ENABLE(gs_num_invocations
> 1) |
4124 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state
->max_vert_out_per_gs_instance
));
4126 /* User edge flags are set by the pos exports. If user edge flags are
4127 * not used, we must use hw-generated edge flags and pass them via
4128 * the prim export to prevent drawing lines on internal edges of
4129 * decomposed primitives (such as quads) with polygon mode = lines.
4131 * TODO: We should combine hw-generated edge flags with user edge
4132 * flags in the shader.
4134 radeon_set_context_reg(ctx_cs
, R_028838_PA_CL_NGG_CNTL
,
4135 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline
) &&
4136 !radv_pipeline_has_gs(pipeline
)));
4138 ge_cntl
= S_03096C_PRIM_GRP_SIZE(ngg_state
->max_gsprims
) |
4139 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
4140 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
);
4142 /* Bug workaround for a possible hang with non-tessellation cases.
4143 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
4145 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
4147 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX10
&&
4148 !radv_pipeline_has_tess(pipeline
) &&
4149 ngg_state
->hw_max_esverts
!= 256) {
4150 ge_cntl
&= C_03096C_VERT_GRP_SIZE
;
4152 if (ngg_state
->hw_max_esverts
> 5) {
4153 ge_cntl
|= S_03096C_VERT_GRP_SIZE(ngg_state
->hw_max_esverts
- 5);
4157 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
, ge_cntl
);
4161 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf
*cs
,
4162 struct radv_pipeline
*pipeline
,
4163 struct radv_shader_variant
*shader
,
4164 const struct radv_tessellation_state
*tess
)
4166 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
4168 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4169 unsigned hs_rsrc2
= shader
->config
.rsrc2
;
4171 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4172 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX10(tess
->lds_size
);
4174 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX9(tess
->lds_size
);
4177 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4178 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
4179 radeon_emit(cs
, va
>> 8);
4180 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
4182 radeon_set_sh_reg_seq(cs
, R_00B410_SPI_SHADER_PGM_LO_LS
, 2);
4183 radeon_emit(cs
, va
>> 8);
4184 radeon_emit(cs
, S_00B414_MEM_BASE(va
>> 40));
4187 radeon_set_sh_reg_seq(cs
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
, 2);
4188 radeon_emit(cs
, shader
->config
.rsrc1
);
4189 radeon_emit(cs
, hs_rsrc2
);
4191 radeon_set_sh_reg_seq(cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
4192 radeon_emit(cs
, va
>> 8);
4193 radeon_emit(cs
, S_00B424_MEM_BASE(va
>> 40));
4194 radeon_emit(cs
, shader
->config
.rsrc1
);
4195 radeon_emit(cs
, shader
->config
.rsrc2
);
4200 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf
*ctx_cs
,
4201 struct radeon_cmdbuf
*cs
,
4202 struct radv_pipeline
*pipeline
,
4203 const struct radv_tessellation_state
*tess
)
4205 struct radv_shader_variant
*vs
;
4207 /* Skip shaders merged into HS/GS */
4208 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
4212 if (vs
->info
.vs
.as_ls
)
4213 radv_pipeline_generate_hw_ls(cs
, pipeline
, vs
, tess
);
4214 else if (vs
->info
.vs
.as_es
)
4215 radv_pipeline_generate_hw_es(cs
, pipeline
, vs
);
4216 else if (vs
->info
.is_ngg
)
4217 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, vs
);
4219 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, vs
);
4223 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf
*ctx_cs
,
4224 struct radeon_cmdbuf
*cs
,
4225 struct radv_pipeline
*pipeline
,
4226 const struct radv_tessellation_state
*tess
)
4228 if (!radv_pipeline_has_tess(pipeline
))
4231 struct radv_shader_variant
*tes
, *tcs
;
4233 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
4234 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
4237 if (tes
->info
.is_ngg
) {
4238 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, tes
);
4239 } else if (tes
->info
.tes
.as_es
)
4240 radv_pipeline_generate_hw_es(cs
, pipeline
, tes
);
4242 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, tes
);
4245 radv_pipeline_generate_hw_hs(cs
, pipeline
, tcs
, tess
);
4247 radeon_set_context_reg(ctx_cs
, R_028B6C_VGT_TF_PARAM
,
4250 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
)
4251 radeon_set_context_reg_idx(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
4252 tess
->ls_hs_config
);
4254 radeon_set_context_reg(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
,
4255 tess
->ls_hs_config
);
4257 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
4258 !radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
4259 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4260 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4261 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4262 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4267 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf
*ctx_cs
,
4268 struct radeon_cmdbuf
*cs
,
4269 struct radv_pipeline
*pipeline
,
4270 struct radv_shader_variant
*gs
)
4272 const struct gfx9_gs_info
*gs_state
= &gs
->info
.gs_ring_info
;
4273 unsigned gs_max_out_vertices
;
4274 uint8_t *num_components
;
4279 gs_max_out_vertices
= gs
->info
.gs
.vertices_out
;
4280 max_stream
= gs
->info
.gs
.max_stream
;
4281 num_components
= gs
->info
.gs
.num_stream_output_components
;
4283 offset
= num_components
[0] * gs_max_out_vertices
;
4285 radeon_set_context_reg_seq(ctx_cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
4286 radeon_emit(ctx_cs
, offset
);
4287 if (max_stream
>= 1)
4288 offset
+= num_components
[1] * gs_max_out_vertices
;
4289 radeon_emit(ctx_cs
, offset
);
4290 if (max_stream
>= 2)
4291 offset
+= num_components
[2] * gs_max_out_vertices
;
4292 radeon_emit(ctx_cs
, offset
);
4293 if (max_stream
>= 3)
4294 offset
+= num_components
[3] * gs_max_out_vertices
;
4295 radeon_set_context_reg(ctx_cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
4297 radeon_set_context_reg_seq(ctx_cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
4298 radeon_emit(ctx_cs
, num_components
[0]);
4299 radeon_emit(ctx_cs
, (max_stream
>= 1) ? num_components
[1] : 0);
4300 radeon_emit(ctx_cs
, (max_stream
>= 2) ? num_components
[2] : 0);
4301 radeon_emit(ctx_cs
, (max_stream
>= 3) ? num_components
[3] : 0);
4303 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
4304 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
4305 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
4306 S_028B90_ENABLE(gs_num_invocations
> 0));
4308 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
4309 gs_state
->vgt_esgs_ring_itemsize
);
4311 va
= radv_buffer_get_va(gs
->bo
) + gs
->bo_offset
;
4313 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4314 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4315 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
4316 radeon_emit(cs
, va
>> 8);
4317 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
4319 radeon_set_sh_reg_seq(cs
, R_00B210_SPI_SHADER_PGM_LO_ES
, 2);
4320 radeon_emit(cs
, va
>> 8);
4321 radeon_emit(cs
, S_00B214_MEM_BASE(va
>> 40));
4324 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
4325 radeon_emit(cs
, gs
->config
.rsrc1
);
4326 radeon_emit(cs
, gs
->config
.rsrc2
| S_00B22C_LDS_SIZE(gs_state
->lds_size
));
4328 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
, gs_state
->vgt_gs_onchip_cntl
);
4329 radeon_set_context_reg(ctx_cs
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
, gs_state
->vgt_gs_max_prims_per_subgroup
);
4331 radeon_set_sh_reg_seq(cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
4332 radeon_emit(cs
, va
>> 8);
4333 radeon_emit(cs
, S_00B224_MEM_BASE(va
>> 40));
4334 radeon_emit(cs
, gs
->config
.rsrc1
);
4335 radeon_emit(cs
, gs
->config
.rsrc2
);
4338 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, pipeline
->gs_copy_shader
);
4342 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf
*ctx_cs
,
4343 struct radeon_cmdbuf
*cs
,
4344 struct radv_pipeline
*pipeline
)
4346 struct radv_shader_variant
*gs
;
4348 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4352 if (gs
->info
.is_ngg
)
4353 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, gs
);
4355 radv_pipeline_generate_hw_gs(ctx_cs
, cs
, pipeline
, gs
);
4357 radeon_set_context_reg(ctx_cs
, R_028B38_VGT_GS_MAX_VERT_OUT
,
4358 gs
->info
.gs
.vertices_out
);
4361 static uint32_t offset_to_ps_input(uint32_t offset
, bool flat_shade
,
4362 bool explicit, bool float16
)
4364 uint32_t ps_input_cntl
;
4365 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
4366 ps_input_cntl
= S_028644_OFFSET(offset
);
4367 if (flat_shade
|| explicit)
4368 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
4370 /* Force parameter cache to be read in passthrough
4373 ps_input_cntl
|= S_028644_OFFSET(1 << 5);
4376 ps_input_cntl
|= S_028644_FP16_INTERP_MODE(1) |
4377 S_028644_ATTR0_VALID(1);
4380 /* The input is a DEFAULT_VAL constant. */
4381 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
4382 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
4383 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
4384 ps_input_cntl
= S_028644_OFFSET(0x20) |
4385 S_028644_DEFAULT_VAL(offset
);
4387 return ps_input_cntl
;
4391 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf
*ctx_cs
,
4392 struct radv_pipeline
*pipeline
)
4394 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4395 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
4396 uint32_t ps_input_cntl
[32];
4398 unsigned ps_offset
= 0;
4400 if (ps
->info
.ps
.prim_id_input
) {
4401 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
];
4402 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4403 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4408 if (ps
->info
.ps
.layer_input
||
4409 ps
->info
.needs_multiview_view_index
) {
4410 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
];
4411 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
4412 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4414 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false, false);
4418 if (ps
->info
.ps
.viewport_index_input
) {
4419 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VIEWPORT
];
4420 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
4421 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4423 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false, false);
4427 if (ps
->info
.ps
.has_pcoord
) {
4429 val
= S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4430 ps_input_cntl
[ps_offset
] = val
;
4434 if (ps
->info
.ps
.num_input_clips_culls
) {
4437 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST0
];
4438 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4439 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false, false);
4443 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST1
];
4444 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
&&
4445 ps
->info
.ps
.num_input_clips_culls
> 4) {
4446 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false, false);
4451 for (unsigned i
= 0; i
< 32 && (1u << i
) <= ps
->info
.ps
.input_mask
; ++i
) {
4456 if (!(ps
->info
.ps
.input_mask
& (1u << i
)))
4459 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VAR0
+ i
];
4460 if (vs_offset
== AC_EXP_PARAM_UNDEFINED
) {
4461 ps_input_cntl
[ps_offset
] = S_028644_OFFSET(0x20);
4466 flat_shade
= !!(ps
->info
.ps
.flat_shaded_mask
& (1u << ps_offset
));
4467 explicit = !!(ps
->info
.ps
.explicit_shaded_mask
& (1u << ps_offset
));
4468 float16
= !!(ps
->info
.ps
.float16_shaded_mask
& (1u << ps_offset
));
4470 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, flat_shade
, explicit, float16
);
4475 radeon_set_context_reg_seq(ctx_cs
, R_028644_SPI_PS_INPUT_CNTL_0
, ps_offset
);
4476 for (unsigned i
= 0; i
< ps_offset
; i
++) {
4477 radeon_emit(ctx_cs
, ps_input_cntl
[i
]);
4483 radv_compute_db_shader_control(const struct radv_device
*device
,
4484 const struct radv_pipeline
*pipeline
,
4485 const struct radv_shader_variant
*ps
)
4488 if (ps
->info
.ps
.early_fragment_test
|| !ps
->info
.ps
.writes_memory
)
4489 z_order
= V_02880C_EARLY_Z_THEN_LATE_Z
;
4491 z_order
= V_02880C_LATE_Z
;
4493 bool disable_rbplus
= device
->physical_device
->rad_info
.has_rbplus
&&
4494 !device
->physical_device
->rad_info
.rbplus_allowed
;
4496 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4497 * but this appears to break Project Cars (DXVK). See
4498 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4500 bool mask_export_enable
= ps
->info
.ps
.writes_sample_mask
;
4502 return S_02880C_Z_EXPORT_ENABLE(ps
->info
.ps
.writes_z
) |
4503 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps
->info
.ps
.writes_stencil
) |
4504 S_02880C_KILL_ENABLE(!!ps
->info
.ps
.can_discard
) |
4505 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable
) |
4506 S_02880C_Z_ORDER(z_order
) |
4507 S_02880C_DEPTH_BEFORE_SHADER(ps
->info
.ps
.early_fragment_test
) |
4508 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps
->info
.ps
.post_depth_coverage
) |
4509 S_02880C_EXEC_ON_HIER_FAIL(ps
->info
.ps
.writes_memory
) |
4510 S_02880C_EXEC_ON_NOOP(ps
->info
.ps
.writes_memory
) |
4511 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus
);
4515 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf
*ctx_cs
,
4516 struct radeon_cmdbuf
*cs
,
4517 struct radv_pipeline
*pipeline
)
4519 struct radv_shader_variant
*ps
;
4521 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
4523 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4524 va
= radv_buffer_get_va(ps
->bo
) + ps
->bo_offset
;
4526 radeon_set_sh_reg_seq(cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
4527 radeon_emit(cs
, va
>> 8);
4528 radeon_emit(cs
, S_00B024_MEM_BASE(va
>> 40));
4529 radeon_emit(cs
, ps
->config
.rsrc1
);
4530 radeon_emit(cs
, ps
->config
.rsrc2
);
4532 radeon_set_context_reg(ctx_cs
, R_02880C_DB_SHADER_CONTROL
,
4533 radv_compute_db_shader_control(pipeline
->device
,
4536 radeon_set_context_reg(ctx_cs
, R_0286CC_SPI_PS_INPUT_ENA
,
4537 ps
->config
.spi_ps_input_ena
);
4539 radeon_set_context_reg(ctx_cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
4540 ps
->config
.spi_ps_input_addr
);
4542 radeon_set_context_reg(ctx_cs
, R_0286D8_SPI_PS_IN_CONTROL
,
4543 S_0286D8_NUM_INTERP(ps
->info
.ps
.num_interp
) |
4544 S_0286D8_PS_W32_EN(ps
->info
.wave_size
== 32));
4546 radeon_set_context_reg(ctx_cs
, R_0286E0_SPI_BARYC_CNTL
, pipeline
->graphics
.spi_baryc_cntl
);
4548 radeon_set_context_reg(ctx_cs
, R_028710_SPI_SHADER_Z_FORMAT
,
4549 ac_get_spi_shader_z_format(ps
->info
.ps
.writes_z
,
4550 ps
->info
.ps
.writes_stencil
,
4551 ps
->info
.ps
.writes_sample_mask
));
4553 if (pipeline
->device
->dfsm_allowed
) {
4554 /* optimise this? */
4555 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
4556 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
4561 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf
*ctx_cs
,
4562 struct radv_pipeline
*pipeline
)
4564 if (pipeline
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4565 pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
4568 unsigned vtx_reuse_depth
= 30;
4569 if (radv_pipeline_has_tess(pipeline
) &&
4570 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.tes
.spacing
== TESS_SPACING_FRACTIONAL_ODD
) {
4571 vtx_reuse_depth
= 14;
4573 radeon_set_context_reg(ctx_cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
4574 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth
));
4578 radv_compute_vgt_shader_stages_en(const struct radv_pipeline
*pipeline
)
4580 uint32_t stages
= 0;
4581 if (radv_pipeline_has_tess(pipeline
)) {
4582 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
4583 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4585 if (radv_pipeline_has_gs(pipeline
))
4586 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
4588 else if (radv_pipeline_has_ngg(pipeline
))
4589 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
4591 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
4592 } else if (radv_pipeline_has_gs(pipeline
)) {
4593 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
4595 } else if (radv_pipeline_has_ngg(pipeline
)) {
4596 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
4599 if (radv_pipeline_has_ngg(pipeline
)) {
4600 stages
|= S_028B54_PRIMGEN_EN(1);
4601 if (pipeline
->streamout_shader
)
4602 stages
|= S_028B54_NGG_WAVE_ID_EN(1);
4603 if (radv_pipeline_has_ngg_passthrough(pipeline
))
4604 stages
|= S_028B54_PRIMGEN_PASSTHRU_EN(1);
4605 } else if (radv_pipeline_has_gs(pipeline
)) {
4606 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
4609 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
4610 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4612 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4613 uint8_t hs_size
= 64, gs_size
= 64, vs_size
= 64;
4615 if (radv_pipeline_has_tess(pipeline
))
4616 hs_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.wave_size
;
4618 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
4619 vs_size
= gs_size
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.wave_size
;
4620 if (pipeline
->gs_copy_shader
)
4621 vs_size
= pipeline
->gs_copy_shader
->info
.wave_size
;
4622 } else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
4623 vs_size
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.wave_size
;
4624 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
4625 vs_size
= pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.wave_size
;
4627 if (radv_pipeline_has_ngg(pipeline
))
4630 /* legacy GS only supports Wave64 */
4631 stages
|= S_028B54_HS_W32_EN(hs_size
== 32 ? 1 : 0) |
4632 S_028B54_GS_W32_EN(gs_size
== 32 ? 1 : 0) |
4633 S_028B54_VS_W32_EN(vs_size
== 32 ? 1 : 0);
4640 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4642 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
4643 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
4645 if (!discard_rectangle_info
)
4650 for (unsigned i
= 0; i
< (1u << MAX_DISCARD_RECTANGLES
); ++i
) {
4651 /* Interpret i as a bitmask, and then set the bit in the mask if
4652 * that combination of rectangles in which the pixel is contained
4653 * should pass the cliprect test. */
4654 unsigned relevant_subset
= i
& ((1u << discard_rectangle_info
->discardRectangleCount
) - 1);
4656 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT
&&
4660 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT
&&
4671 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf
*ctx_cs
,
4672 struct radv_pipeline
*pipeline
,
4673 const struct radv_tessellation_state
*tess
)
4675 bool break_wave_at_eoi
= false;
4676 unsigned primgroup_size
;
4677 unsigned vertgroup_size
= 256; /* 256 = disable vertex grouping */
4679 if (radv_pipeline_has_tess(pipeline
)) {
4680 primgroup_size
= tess
->num_patches
; /* must be a multiple of NUM_PATCHES */
4681 } else if (radv_pipeline_has_gs(pipeline
)) {
4682 const struct gfx9_gs_info
*gs_state
=
4683 &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs_ring_info
;
4684 unsigned vgt_gs_onchip_cntl
= gs_state
->vgt_gs_onchip_cntl
;
4685 primgroup_size
= G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl
);
4687 primgroup_size
= 128; /* recommended without a GS and tess */
4690 if (radv_pipeline_has_tess(pipeline
)) {
4691 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4692 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4693 break_wave_at_eoi
= true;
4696 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
,
4697 S_03096C_PRIM_GRP_SIZE(primgroup_size
) |
4698 S_03096C_VERT_GRP_SIZE(vertgroup_size
) |
4699 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4700 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
));
4704 radv_pipeline_generate_pm4(struct radv_pipeline
*pipeline
,
4705 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4706 const struct radv_graphics_pipeline_create_info
*extra
,
4707 const struct radv_blend_state
*blend
,
4708 const struct radv_tessellation_state
*tess
,
4709 unsigned prim
, unsigned gs_out
)
4711 struct radeon_cmdbuf
*ctx_cs
= &pipeline
->ctx_cs
;
4712 struct radeon_cmdbuf
*cs
= &pipeline
->cs
;
4715 ctx_cs
->max_dw
= 256;
4716 cs
->buf
= malloc(4 * (cs
->max_dw
+ ctx_cs
->max_dw
));
4717 ctx_cs
->buf
= cs
->buf
+ cs
->max_dw
;
4719 radv_pipeline_generate_depth_stencil_state(ctx_cs
, pipeline
, pCreateInfo
, extra
);
4720 radv_pipeline_generate_blend_state(ctx_cs
, pipeline
, blend
);
4721 radv_pipeline_generate_raster_state(ctx_cs
, pipeline
, pCreateInfo
);
4722 radv_pipeline_generate_multisample_state(ctx_cs
, pipeline
);
4723 radv_pipeline_generate_vgt_gs_mode(ctx_cs
, pipeline
);
4724 radv_pipeline_generate_vertex_shader(ctx_cs
, cs
, pipeline
, tess
);
4725 radv_pipeline_generate_tess_shaders(ctx_cs
, cs
, pipeline
, tess
);
4726 radv_pipeline_generate_geometry_shader(ctx_cs
, cs
, pipeline
);
4727 radv_pipeline_generate_fragment_shader(ctx_cs
, cs
, pipeline
);
4728 radv_pipeline_generate_ps_inputs(ctx_cs
, pipeline
);
4729 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs
, pipeline
);
4730 radv_pipeline_generate_binning_state(ctx_cs
, pipeline
, pCreateInfo
, blend
);
4732 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&& !radv_pipeline_has_ngg(pipeline
))
4733 gfx10_pipeline_generate_ge_cntl(ctx_cs
, pipeline
, tess
);
4735 radeon_set_context_reg(ctx_cs
, R_028B54_VGT_SHADER_STAGES_EN
, radv_compute_vgt_shader_stages_en(pipeline
));
4737 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4738 radeon_set_uconfig_reg_idx(pipeline
->device
->physical_device
,
4739 cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, prim
);
4741 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
4743 radeon_set_context_reg(ctx_cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, gs_out
);
4745 radeon_set_context_reg(ctx_cs
, R_02820C_PA_SC_CLIPRECT_RULE
, radv_compute_cliprect_rule(pCreateInfo
));
4747 pipeline
->ctx_cs_hash
= _mesa_hash_data(ctx_cs
->buf
, ctx_cs
->cdw
* 4);
4749 assert(ctx_cs
->cdw
<= ctx_cs
->max_dw
);
4750 assert(cs
->cdw
<= cs
->max_dw
);
4753 static struct radv_ia_multi_vgt_param_helpers
4754 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline
*pipeline
,
4755 const struct radv_tessellation_state
*tess
,
4758 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
= {0};
4759 const struct radv_device
*device
= pipeline
->device
;
4761 if (radv_pipeline_has_tess(pipeline
))
4762 ia_multi_vgt_param
.primgroup_size
= tess
->num_patches
;
4763 else if (radv_pipeline_has_gs(pipeline
))
4764 ia_multi_vgt_param
.primgroup_size
= 64;
4766 ia_multi_vgt_param
.primgroup_size
= 128; /* recommended without a GS */
4768 /* GS requirement. */
4769 ia_multi_vgt_param
.partial_es_wave
= false;
4770 if (radv_pipeline_has_gs(pipeline
) && device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4771 if (SI_GS_PER_ES
/ ia_multi_vgt_param
.primgroup_size
>= pipeline
->device
->gs_table_depth
- 3)
4772 ia_multi_vgt_param
.partial_es_wave
= true;
4774 ia_multi_vgt_param
.wd_switch_on_eop
= false;
4775 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4776 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
4777 * 4 shader engines. Set 1 to pass the assertion below.
4778 * The other cases are hardware requirements. */
4779 if (device
->physical_device
->rad_info
.max_se
< 4 ||
4780 prim
== V_008958_DI_PT_POLYGON
||
4781 prim
== V_008958_DI_PT_LINELOOP
||
4782 prim
== V_008958_DI_PT_TRIFAN
||
4783 prim
== V_008958_DI_PT_TRISTRIP_ADJ
||
4784 (pipeline
->graphics
.prim_restart_enable
&&
4785 (device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4786 (prim
!= V_008958_DI_PT_POINTLIST
&&
4787 prim
!= V_008958_DI_PT_LINESTRIP
))))
4788 ia_multi_vgt_param
.wd_switch_on_eop
= true;
4791 ia_multi_vgt_param
.ia_switch_on_eoi
= false;
4792 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.prim_id_input
)
4793 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4794 if (radv_pipeline_has_gs(pipeline
) &&
4795 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.uses_prim_id
)
4796 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4797 if (radv_pipeline_has_tess(pipeline
)) {
4798 /* SWITCH_ON_EOI must be set if PrimID is used. */
4799 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4800 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4801 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4804 ia_multi_vgt_param
.partial_vs_wave
= false;
4805 if (radv_pipeline_has_tess(pipeline
)) {
4806 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4807 if ((device
->physical_device
->rad_info
.family
== CHIP_TAHITI
||
4808 device
->physical_device
->rad_info
.family
== CHIP_PITCAIRN
||
4809 device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
) &&
4810 radv_pipeline_has_gs(pipeline
))
4811 ia_multi_vgt_param
.partial_vs_wave
= true;
4812 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4813 if (device
->physical_device
->rad_info
.has_distributed_tess
) {
4814 if (radv_pipeline_has_gs(pipeline
)) {
4815 if (device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4816 ia_multi_vgt_param
.partial_es_wave
= true;
4818 ia_multi_vgt_param
.partial_vs_wave
= true;
4823 /* Workaround for a VGT hang when strip primitive types are used with
4824 * primitive restart.
4826 if (pipeline
->graphics
.prim_restart_enable
&&
4827 (prim
== V_008958_DI_PT_LINESTRIP
||
4828 prim
== V_008958_DI_PT_TRISTRIP
||
4829 prim
== V_008958_DI_PT_LINESTRIP_ADJ
||
4830 prim
== V_008958_DI_PT_TRISTRIP_ADJ
)) {
4831 ia_multi_vgt_param
.partial_vs_wave
= true;
4834 if (radv_pipeline_has_gs(pipeline
)) {
4835 /* On these chips there is the possibility of a hang if the
4836 * pipeline uses a GS and partial_vs_wave is not set.
4838 * This mostly does not hit 4-SE chips, as those typically set
4839 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4840 * with GS due to another workaround.
4842 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4844 if (device
->physical_device
->rad_info
.family
== CHIP_TONGA
||
4845 device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
4846 device
->physical_device
->rad_info
.family
== CHIP_POLARIS10
||
4847 device
->physical_device
->rad_info
.family
== CHIP_POLARIS11
||
4848 device
->physical_device
->rad_info
.family
== CHIP_POLARIS12
||
4849 device
->physical_device
->rad_info
.family
== CHIP_VEGAM
) {
4850 ia_multi_vgt_param
.partial_vs_wave
= true;
4854 ia_multi_vgt_param
.base
=
4855 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param
.primgroup_size
- 1) |
4856 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4857 S_028AA8_MAX_PRIMGRP_IN_WAVE(device
->physical_device
->rad_info
.chip_class
== GFX8
? 2 : 0) |
4858 S_030960_EN_INST_OPT_BASIC(device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
4859 S_030960_EN_INST_OPT_ADV(device
->physical_device
->rad_info
.chip_class
>= GFX9
);
4861 return ia_multi_vgt_param
;
4866 radv_compute_vertex_input_state(struct radv_pipeline
*pipeline
,
4867 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4869 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
4870 pCreateInfo
->pVertexInputState
;
4871 struct radv_vertex_elements_info
*velems
= &pipeline
->vertex_elements
;
4873 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
4874 const VkVertexInputAttributeDescription
*desc
=
4875 &vi_info
->pVertexAttributeDescriptions
[i
];
4876 unsigned loc
= desc
->location
;
4877 const struct vk_format_description
*format_desc
;
4879 format_desc
= vk_format_description(desc
->format
);
4881 velems
->format_size
[loc
] = format_desc
->block
.bits
/ 8;
4884 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
4885 const VkVertexInputBindingDescription
*desc
=
4886 &vi_info
->pVertexBindingDescriptions
[i
];
4888 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
4889 pipeline
->num_vertex_bindings
=
4890 MAX2(pipeline
->num_vertex_bindings
, desc
->binding
+ 1);
4894 static struct radv_shader_variant
*
4895 radv_pipeline_get_streamout_shader(struct radv_pipeline
*pipeline
)
4899 for (i
= MESA_SHADER_GEOMETRY
; i
>= MESA_SHADER_VERTEX
; i
--) {
4900 struct radv_shader_variant
*shader
=
4901 radv_get_shader(pipeline
, i
);
4903 if (shader
&& shader
->info
.so
.num_outputs
> 0)
4911 radv_secure_compile(struct radv_pipeline
*pipeline
,
4912 struct radv_device
*device
,
4913 const struct radv_pipeline_key
*key
,
4914 const VkPipelineShaderStageCreateInfo
**pStages
,
4915 const VkPipelineCreateFlags flags
,
4916 unsigned num_stages
)
4918 uint8_t allowed_pipeline_hashes
[2][20];
4919 radv_hash_shaders(allowed_pipeline_hashes
[0], pStages
,
4920 pipeline
->layout
, key
, get_hash_flags(device
));
4922 /* Generate the GC copy hash */
4923 memcpy(allowed_pipeline_hashes
[1], allowed_pipeline_hashes
[0], 20);
4924 allowed_pipeline_hashes
[1][0] ^= 1;
4926 uint8_t allowed_hashes
[2][20];
4927 for (unsigned i
= 0; i
< 2; ++i
) {
4928 disk_cache_compute_key(device
->physical_device
->disk_cache
,
4929 allowed_pipeline_hashes
[i
], 20,
4933 /* Do an early exit if all cache entries are already there. */
4934 bool may_need_copy_shader
= pStages
[MESA_SHADER_GEOMETRY
];
4935 void *main_entry
= disk_cache_get(device
->physical_device
->disk_cache
, allowed_hashes
[0], NULL
);
4936 void *copy_entry
= NULL
;
4937 if (may_need_copy_shader
)
4938 copy_entry
= disk_cache_get(device
->physical_device
->disk_cache
, allowed_hashes
[1], NULL
);
4940 bool has_all_cache_entries
= main_entry
&& (!may_need_copy_shader
|| copy_entry
);
4944 if(has_all_cache_entries
)
4947 unsigned process
= 0;
4948 uint8_t sc_threads
= device
->instance
->num_sc_threads
;
4950 mtx_lock(&device
->sc_state
->secure_compile_mutex
);
4951 if (device
->sc_state
->secure_compile_thread_counter
< sc_threads
) {
4952 device
->sc_state
->secure_compile_thread_counter
++;
4953 for (unsigned i
= 0; i
< sc_threads
; i
++) {
4954 if (!device
->sc_state
->secure_compile_processes
[i
].in_use
) {
4955 device
->sc_state
->secure_compile_processes
[i
].in_use
= true;
4960 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
4963 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
4966 int fd_secure_input
= device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
;
4967 int fd_secure_output
= device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
;
4969 /* Fork a copy of the slim untainted secure compile process */
4970 enum radv_secure_compile_type sc_type
= RADV_SC_TYPE_FORK_DEVICE
;
4971 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
4973 if (!radv_sc_read(fd_secure_output
, &sc_type
, sizeof(sc_type
), true) ||
4974 sc_type
!= RADV_SC_TYPE_INIT_SUCCESS
)
4975 return VK_ERROR_DEVICE_LOST
;
4977 fd_secure_input
= device
->sc_state
->secure_compile_processes
[process
].fd_server
;
4978 fd_secure_output
= device
->sc_state
->secure_compile_processes
[process
].fd_client
;
4980 /* Write pipeline / shader module out to secure process via pipe */
4981 sc_type
= RADV_SC_TYPE_COMPILE_PIPELINE
;
4982 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
4984 /* Write pipeline layout out to secure process */
4985 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
4986 write(fd_secure_input
, layout
, sizeof(struct radv_pipeline_layout
));
4987 write(fd_secure_input
, &layout
->num_sets
, sizeof(uint32_t));
4988 for (uint32_t set
= 0; set
< layout
->num_sets
; set
++) {
4989 write(fd_secure_input
, &layout
->set
[set
].layout
->layout_size
, sizeof(uint32_t));
4990 write(fd_secure_input
, layout
->set
[set
].layout
, layout
->set
[set
].layout
->layout_size
);
4993 /* Write pipeline key out to secure process */
4994 write(fd_secure_input
, key
, sizeof(struct radv_pipeline_key
));
4996 /* Write pipeline create flags out to secure process */
4997 write(fd_secure_input
, &flags
, sizeof(VkPipelineCreateFlags
));
4999 /* Write stage and shader information out to secure process */
5000 write(fd_secure_input
, &num_stages
, sizeof(uint32_t));
5001 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
5005 /* Write stage out to secure process */
5006 gl_shader_stage stage
= ffs(pStages
[i
]->stage
) - 1;
5007 write(fd_secure_input
, &stage
, sizeof(gl_shader_stage
));
5009 /* Write entry point name out to secure process */
5010 size_t name_size
= strlen(pStages
[i
]->pName
) + 1;
5011 write(fd_secure_input
, &name_size
, sizeof(size_t));
5012 write(fd_secure_input
, pStages
[i
]->pName
, name_size
);
5014 /* Write shader module out to secure process */
5015 struct radv_shader_module
*module
= radv_shader_module_from_handle(pStages
[i
]->module
);
5016 assert(!module
->nir
);
5017 size_t module_size
= sizeof(struct radv_shader_module
) + module
->size
;
5018 write(fd_secure_input
, &module_size
, sizeof(size_t));
5019 write(fd_secure_input
, module
, module_size
);
5021 /* Write specialization info out to secure process */
5022 const VkSpecializationInfo
*specInfo
= pStages
[i
]->pSpecializationInfo
;
5023 bool has_spec_info
= specInfo
? true : false;
5024 write(fd_secure_input
, &has_spec_info
, sizeof(bool));
5026 write(fd_secure_input
, &specInfo
->dataSize
, sizeof(size_t));
5027 write(fd_secure_input
, specInfo
->pData
, specInfo
->dataSize
);
5029 write(fd_secure_input
, &specInfo
->mapEntryCount
, sizeof(uint32_t));
5030 for (uint32_t j
= 0; j
< specInfo
->mapEntryCount
; j
++)
5031 write(fd_secure_input
, &specInfo
->pMapEntries
[j
], sizeof(VkSpecializationMapEntry
));
5035 /* Read the data returned from the secure process */
5036 while (sc_type
!= RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED
) {
5037 if (!radv_sc_read(fd_secure_output
, &sc_type
, sizeof(sc_type
), true))
5038 return VK_ERROR_DEVICE_LOST
;
5040 if (sc_type
== RADV_SC_TYPE_WRITE_DISK_CACHE
) {
5041 assert(device
->physical_device
->disk_cache
);
5043 uint8_t disk_sha1
[20];
5044 if (!radv_sc_read(fd_secure_output
, disk_sha1
, sizeof(uint8_t) * 20, true))
5045 return VK_ERROR_DEVICE_LOST
;
5047 if (memcmp(disk_sha1
, allowed_hashes
[0], 20) &&
5048 memcmp(disk_sha1
, allowed_hashes
[1], 20))
5049 return VK_ERROR_DEVICE_LOST
;
5051 uint32_t entry_size
;
5052 if (!radv_sc_read(fd_secure_output
, &entry_size
, sizeof(uint32_t), true))
5053 return VK_ERROR_DEVICE_LOST
;
5055 struct cache_entry
*entry
= malloc(entry_size
);
5056 if (!radv_sc_read(fd_secure_output
, entry
, entry_size
, true))
5057 return VK_ERROR_DEVICE_LOST
;
5059 disk_cache_put(device
->physical_device
->disk_cache
,
5060 disk_sha1
, entry
, entry_size
,
5064 } else if (sc_type
== RADV_SC_TYPE_READ_DISK_CACHE
) {
5065 uint8_t disk_sha1
[20];
5066 if (!radv_sc_read(fd_secure_output
, disk_sha1
, sizeof(uint8_t) * 20, true))
5067 return VK_ERROR_DEVICE_LOST
;
5069 if (memcmp(disk_sha1
, allowed_hashes
[0], 20) &&
5070 memcmp(disk_sha1
, allowed_hashes
[1], 20))
5071 return VK_ERROR_DEVICE_LOST
;
5074 struct cache_entry
*entry
= (struct cache_entry
*)
5075 disk_cache_get(device
->physical_device
->disk_cache
,
5078 uint8_t found
= entry
? 1 : 0;
5079 write(fd_secure_input
, &found
, sizeof(uint8_t));
5082 write(fd_secure_input
, &size
, sizeof(size_t));
5083 write(fd_secure_input
, entry
, size
);
5090 sc_type
= RADV_SC_TYPE_DESTROY_DEVICE
;
5091 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
5093 mtx_lock(&device
->sc_state
->secure_compile_mutex
);
5094 device
->sc_state
->secure_compile_thread_counter
--;
5095 device
->sc_state
->secure_compile_processes
[process
].in_use
= false;
5096 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
5102 radv_pipeline_init(struct radv_pipeline
*pipeline
,
5103 struct radv_device
*device
,
5104 struct radv_pipeline_cache
*cache
,
5105 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
5106 const struct radv_graphics_pipeline_create_info
*extra
)
5109 bool has_view_index
= false;
5111 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
5112 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
5113 if (subpass
->view_mask
)
5114 has_view_index
= true;
5116 pipeline
->device
= device
;
5117 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
5118 assert(pipeline
->layout
);
5120 struct radv_blend_state blend
= radv_pipeline_init_blend_state(pipeline
, pCreateInfo
, extra
);
5122 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
5123 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
5124 radv_init_feedback(creation_feedback
);
5126 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
5128 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
5129 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
5130 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
5131 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
5132 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
5133 if(creation_feedback
)
5134 stage_feedbacks
[stage
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[i
];
5137 struct radv_pipeline_key key
= radv_generate_graphics_pipeline_key(pipeline
, pCreateInfo
, &blend
, has_view_index
);
5138 if (radv_device_use_secure_compile(device
->instance
)) {
5139 return radv_secure_compile(pipeline
, device
, &key
, pStages
, pCreateInfo
->flags
, pCreateInfo
->stageCount
);
5141 radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
, pCreateInfo
->flags
, pipeline_feedback
, stage_feedbacks
);
5144 pipeline
->graphics
.spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
5145 radv_pipeline_init_multisample_state(pipeline
, &blend
, pCreateInfo
);
5147 uint32_t prim
= si_translate_prim(pCreateInfo
->pInputAssemblyState
->topology
);
5149 pipeline
->graphics
.topology
= pCreateInfo
->pInputAssemblyState
->topology
;
5150 pipeline
->graphics
.can_use_guardband
= radv_prim_can_use_guardband(pCreateInfo
->pInputAssemblyState
->topology
);
5152 if (radv_pipeline_has_gs(pipeline
)) {
5153 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs
.output_prim
);
5154 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
5155 } else if (radv_pipeline_has_tess(pipeline
)) {
5156 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.point_mode
)
5157 gs_out
= V_028A6C_OUTPRIM_TYPE_POINTLIST
;
5159 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.primitive_mode
);
5160 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
5162 gs_out
= si_conv_prim_to_gs_out(pCreateInfo
->pInputAssemblyState
->topology
);
5164 if (extra
&& extra
->use_rectlist
) {
5165 prim
= V_008958_DI_PT_RECTLIST
;
5166 gs_out
= V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
5167 pipeline
->graphics
.can_use_guardband
= true;
5168 if (radv_pipeline_has_ngg(pipeline
))
5169 gs_out
= V_028A6C_VGT_OUT_RECT_V0
;
5171 pipeline
->graphics
.prim_restart_enable
= !!pCreateInfo
->pInputAssemblyState
->primitiveRestartEnable
;
5172 /* prim vertex count will need TESS changes */
5173 pipeline
->graphics
.prim_vertex_count
= prim_size_table
[prim
];
5175 radv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
);
5177 /* Ensure that some export memory is always allocated, for two reasons:
5179 * 1) Correctness: The hardware ignores the EXEC mask if no export
5180 * memory is allocated, so KILL and alpha test do not work correctly
5182 * 2) Performance: Every shader needs at least a NULL export, even when
5183 * it writes no color/depth output. The NULL export instruction
5184 * stalls without this setting.
5186 * Don't add this to CB_SHADER_MASK.
5188 * GFX10 supports pixel shaders without exports by setting both the
5189 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
5190 * instructions if any are present.
5192 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
5193 if ((pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX9
||
5194 ps
->info
.ps
.can_discard
) &&
5195 !blend
.spi_shader_col_format
) {
5196 if (!ps
->info
.ps
.writes_z
&&
5197 !ps
->info
.ps
.writes_stencil
&&
5198 !ps
->info
.ps
.writes_sample_mask
)
5199 blend
.spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
5202 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
5203 if (pipeline
->shaders
[i
]) {
5204 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[i
]->info
.need_indirect_descriptor_sets
;
5208 if (radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
5209 struct radv_shader_variant
*gs
=
5210 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
5212 calculate_gs_ring_sizes(pipeline
, &gs
->info
.gs_ring_info
);
5215 struct radv_tessellation_state tess
= {0};
5216 if (radv_pipeline_has_tess(pipeline
)) {
5217 if (prim
== V_008958_DI_PT_PATCH
) {
5218 pipeline
->graphics
.prim_vertex_count
.min
= pCreateInfo
->pTessellationState
->patchControlPoints
;
5219 pipeline
->graphics
.prim_vertex_count
.incr
= 1;
5221 tess
= calculate_tess_state(pipeline
, pCreateInfo
);
5224 pipeline
->graphics
.ia_multi_vgt_param
= radv_compute_ia_multi_vgt_param_helpers(pipeline
, &tess
, prim
);
5226 radv_compute_vertex_input_state(pipeline
, pCreateInfo
);
5228 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++)
5229 pipeline
->user_data_0
[i
] = radv_pipeline_stage_to_user_data_0(pipeline
, i
, device
->physical_device
->rad_info
.chip_class
);
5231 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
,
5232 AC_UD_VS_BASE_VERTEX_START_INSTANCE
);
5233 if (loc
->sgpr_idx
!= -1) {
5234 pipeline
->graphics
.vtx_base_sgpr
= pipeline
->user_data_0
[MESA_SHADER_VERTEX
];
5235 pipeline
->graphics
.vtx_base_sgpr
+= loc
->sgpr_idx
* 4;
5236 if (radv_get_shader(pipeline
, MESA_SHADER_VERTEX
)->info
.vs
.needs_draw_id
)
5237 pipeline
->graphics
.vtx_emit_num
= 3;
5239 pipeline
->graphics
.vtx_emit_num
= 2;
5242 /* Find the last vertex shader stage that eventually uses streamout. */
5243 pipeline
->streamout_shader
= radv_pipeline_get_streamout_shader(pipeline
);
5245 result
= radv_pipeline_scratch_init(device
, pipeline
);
5246 radv_pipeline_generate_pm4(pipeline
, pCreateInfo
, extra
, &blend
, &tess
, prim
, gs_out
);
5252 radv_graphics_pipeline_create(
5254 VkPipelineCache _cache
,
5255 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
5256 const struct radv_graphics_pipeline_create_info
*extra
,
5257 const VkAllocationCallbacks
*pAllocator
,
5258 VkPipeline
*pPipeline
)
5260 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5261 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
5262 struct radv_pipeline
*pipeline
;
5265 pipeline
= vk_zalloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*pipeline
), 8,
5266 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5267 if (pipeline
== NULL
)
5268 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5270 vk_object_base_init(&device
->vk
, &pipeline
->base
,
5271 VK_OBJECT_TYPE_PIPELINE
);
5273 result
= radv_pipeline_init(pipeline
, device
, cache
,
5274 pCreateInfo
, extra
);
5275 if (result
!= VK_SUCCESS
) {
5276 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5280 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5285 VkResult
radv_CreateGraphicsPipelines(
5287 VkPipelineCache pipelineCache
,
5289 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
5290 const VkAllocationCallbacks
* pAllocator
,
5291 VkPipeline
* pPipelines
)
5293 VkResult result
= VK_SUCCESS
;
5296 for (; i
< count
; i
++) {
5298 r
= radv_graphics_pipeline_create(_device
,
5301 NULL
, pAllocator
, &pPipelines
[i
]);
5302 if (r
!= VK_SUCCESS
) {
5304 pPipelines
[i
] = VK_NULL_HANDLE
;
5313 radv_compute_generate_pm4(struct radv_pipeline
*pipeline
)
5315 struct radv_shader_variant
*compute_shader
;
5316 struct radv_device
*device
= pipeline
->device
;
5317 unsigned threads_per_threadgroup
;
5318 unsigned threadgroups_per_cu
= 1;
5319 unsigned waves_per_threadgroup
;
5320 unsigned max_waves_per_sh
= 0;
5323 pipeline
->cs
.max_dw
= device
->physical_device
->rad_info
.chip_class
>= GFX10
? 22 : 20;
5324 pipeline
->cs
.buf
= malloc(pipeline
->cs
.max_dw
* 4);
5326 compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
5327 va
= radv_buffer_get_va(compute_shader
->bo
) + compute_shader
->bo_offset
;
5329 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B830_COMPUTE_PGM_LO
, 2);
5330 radeon_emit(&pipeline
->cs
, va
>> 8);
5331 radeon_emit(&pipeline
->cs
, S_00B834_DATA(va
>> 40));
5333 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
5334 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc1
);
5335 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc2
);
5336 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
5337 radeon_set_sh_reg(&pipeline
->cs
, R_00B8A0_COMPUTE_PGM_RSRC3
, compute_shader
->config
.rsrc3
);
5340 /* Calculate best compute resource limits. */
5341 threads_per_threadgroup
= compute_shader
->info
.cs
.block_size
[0] *
5342 compute_shader
->info
.cs
.block_size
[1] *
5343 compute_shader
->info
.cs
.block_size
[2];
5344 waves_per_threadgroup
= DIV_ROUND_UP(threads_per_threadgroup
,
5345 compute_shader
->info
.wave_size
);
5347 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
5348 waves_per_threadgroup
== 1)
5349 threadgroups_per_cu
= 2;
5351 radeon_set_sh_reg(&pipeline
->cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
5352 ac_get_compute_resource_limits(&device
->physical_device
->rad_info
,
5353 waves_per_threadgroup
,
5355 threadgroups_per_cu
));
5357 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
5358 radeon_emit(&pipeline
->cs
,
5359 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]));
5360 radeon_emit(&pipeline
->cs
,
5361 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]));
5362 radeon_emit(&pipeline
->cs
,
5363 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]));
5365 assert(pipeline
->cs
.cdw
<= pipeline
->cs
.max_dw
);
5368 static struct radv_pipeline_key
5369 radv_generate_compute_pipeline_key(struct radv_pipeline
*pipeline
,
5370 const VkComputePipelineCreateInfo
*pCreateInfo
)
5372 const VkPipelineShaderStageCreateInfo
*stage
= &pCreateInfo
->stage
;
5373 struct radv_pipeline_key key
;
5374 memset(&key
, 0, sizeof(key
));
5376 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
5377 key
.optimisations_disabled
= 1;
5379 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*subgroup_size
=
5380 vk_find_struct_const(stage
->pNext
,
5381 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT
);
5383 if (subgroup_size
) {
5384 assert(subgroup_size
->requiredSubgroupSize
== 32 ||
5385 subgroup_size
->requiredSubgroupSize
== 64);
5386 key
.compute_subgroup_size
= subgroup_size
->requiredSubgroupSize
;
5392 static VkResult
radv_compute_pipeline_create(
5394 VkPipelineCache _cache
,
5395 const VkComputePipelineCreateInfo
* pCreateInfo
,
5396 const VkAllocationCallbacks
* pAllocator
,
5397 VkPipeline
* pPipeline
)
5399 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5400 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
5401 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
5402 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
5403 struct radv_pipeline
*pipeline
;
5406 pipeline
= vk_zalloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*pipeline
), 8,
5407 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5408 if (pipeline
== NULL
)
5409 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5411 vk_object_base_init(&device
->vk
, &pipeline
->base
,
5412 VK_OBJECT_TYPE_PIPELINE
);
5414 pipeline
->device
= device
;
5415 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
5416 assert(pipeline
->layout
);
5418 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
5419 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
5420 radv_init_feedback(creation_feedback
);
5422 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
5423 if (creation_feedback
)
5424 stage_feedbacks
[MESA_SHADER_COMPUTE
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[0];
5426 pStages
[MESA_SHADER_COMPUTE
] = &pCreateInfo
->stage
;
5428 struct radv_pipeline_key key
=
5429 radv_generate_compute_pipeline_key(pipeline
, pCreateInfo
);
5431 if (radv_device_use_secure_compile(device
->instance
)) {
5432 result
= radv_secure_compile(pipeline
, device
, &key
, pStages
, pCreateInfo
->flags
, 1);
5433 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5437 radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
, pCreateInfo
->flags
, pipeline_feedback
, stage_feedbacks
);
5440 pipeline
->user_data_0
[MESA_SHADER_COMPUTE
] = radv_pipeline_stage_to_user_data_0(pipeline
, MESA_SHADER_COMPUTE
, device
->physical_device
->rad_info
.chip_class
);
5441 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.need_indirect_descriptor_sets
;
5442 result
= radv_pipeline_scratch_init(device
, pipeline
);
5443 if (result
!= VK_SUCCESS
) {
5444 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5448 radv_compute_generate_pm4(pipeline
);
5450 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5455 VkResult
radv_CreateComputePipelines(
5457 VkPipelineCache pipelineCache
,
5459 const VkComputePipelineCreateInfo
* pCreateInfos
,
5460 const VkAllocationCallbacks
* pAllocator
,
5461 VkPipeline
* pPipelines
)
5463 VkResult result
= VK_SUCCESS
;
5466 for (; i
< count
; i
++) {
5468 r
= radv_compute_pipeline_create(_device
, pipelineCache
,
5470 pAllocator
, &pPipelines
[i
]);
5471 if (r
!= VK_SUCCESS
) {
5473 pPipelines
[i
] = VK_NULL_HANDLE
;
5481 static uint32_t radv_get_executable_count(const struct radv_pipeline
*pipeline
)
5484 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5485 if (!pipeline
->shaders
[i
])
5488 if (i
== MESA_SHADER_GEOMETRY
&&
5489 !radv_pipeline_has_ngg(pipeline
)) {
5499 static struct radv_shader_variant
*
5500 radv_get_shader_from_executable_index(const struct radv_pipeline
*pipeline
, int index
, gl_shader_stage
*stage
)
5502 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5503 if (!pipeline
->shaders
[i
])
5507 return pipeline
->shaders
[i
];
5512 if (i
== MESA_SHADER_GEOMETRY
&&
5513 !radv_pipeline_has_ngg(pipeline
)) {
5516 return pipeline
->gs_copy_shader
;
5526 /* Basically strlcpy (which does not exist on linux) specialized for
5528 static void desc_copy(char *desc
, const char *src
) {
5529 int len
= strlen(src
);
5530 assert(len
< VK_MAX_DESCRIPTION_SIZE
);
5531 memcpy(desc
, src
, len
);
5532 memset(desc
+ len
, 0, VK_MAX_DESCRIPTION_SIZE
- len
);
5535 VkResult
radv_GetPipelineExecutablePropertiesKHR(
5537 const VkPipelineInfoKHR
* pPipelineInfo
,
5538 uint32_t* pExecutableCount
,
5539 VkPipelineExecutablePropertiesKHR
* pProperties
)
5541 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pPipelineInfo
->pipeline
);
5542 const uint32_t total_count
= radv_get_executable_count(pipeline
);
5545 *pExecutableCount
= total_count
;
5549 const uint32_t count
= MIN2(total_count
, *pExecutableCount
);
5550 for (unsigned i
= 0, executable_idx
= 0;
5551 i
< MESA_SHADER_STAGES
&& executable_idx
< count
; ++i
) {
5552 if (!pipeline
->shaders
[i
])
5554 pProperties
[executable_idx
].stages
= mesa_to_vk_shader_stage(i
);
5555 const char *name
= NULL
;
5556 const char *description
= NULL
;
5558 case MESA_SHADER_VERTEX
:
5559 name
= "Vertex Shader";
5560 description
= "Vulkan Vertex Shader";
5562 case MESA_SHADER_TESS_CTRL
:
5563 if (!pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5564 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5565 name
= "Vertex + Tessellation Control Shaders";
5566 description
= "Combined Vulkan Vertex and Tessellation Control Shaders";
5568 name
= "Tessellation Control Shader";
5569 description
= "Vulkan Tessellation Control Shader";
5572 case MESA_SHADER_TESS_EVAL
:
5573 name
= "Tessellation Evaluation Shader";
5574 description
= "Vulkan Tessellation Evaluation Shader";
5576 case MESA_SHADER_GEOMETRY
:
5577 if (radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]) {
5578 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
;
5579 name
= "Tessellation Evaluation + Geometry Shaders";
5580 description
= "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5581 } else if (!radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5582 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5583 name
= "Vertex + Geometry Shader";
5584 description
= "Combined Vulkan Vertex and Geometry Shaders";
5586 name
= "Geometry Shader";
5587 description
= "Vulkan Geometry Shader";
5590 case MESA_SHADER_FRAGMENT
:
5591 name
= "Fragment Shader";
5592 description
= "Vulkan Fragment Shader";
5594 case MESA_SHADER_COMPUTE
:
5595 name
= "Compute Shader";
5596 description
= "Vulkan Compute Shader";
5600 pProperties
[executable_idx
].subgroupSize
= pipeline
->shaders
[i
]->info
.wave_size
;
5601 desc_copy(pProperties
[executable_idx
].name
, name
);
5602 desc_copy(pProperties
[executable_idx
].description
, description
);
5605 if (i
== MESA_SHADER_GEOMETRY
&&
5606 !radv_pipeline_has_ngg(pipeline
)) {
5607 assert(pipeline
->gs_copy_shader
);
5608 if (executable_idx
>= count
)
5611 pProperties
[executable_idx
].stages
= VK_SHADER_STAGE_GEOMETRY_BIT
;
5612 pProperties
[executable_idx
].subgroupSize
= 64;
5613 desc_copy(pProperties
[executable_idx
].name
, "GS Copy Shader");
5614 desc_copy(pProperties
[executable_idx
].description
,
5615 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5621 VkResult result
= *pExecutableCount
< total_count
? VK_INCOMPLETE
: VK_SUCCESS
;
5622 *pExecutableCount
= count
;
5626 VkResult
radv_GetPipelineExecutableStatisticsKHR(
5628 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5629 uint32_t* pStatisticCount
,
5630 VkPipelineExecutableStatisticKHR
* pStatistics
)
5632 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5633 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5634 gl_shader_stage stage
;
5635 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5637 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
5638 unsigned lds_increment
= chip_class
>= GFX7
? 512 : 256;
5639 unsigned max_waves
= radv_get_max_waves(device
, shader
, stage
);
5641 VkPipelineExecutableStatisticKHR
*s
= pStatistics
;
5642 VkPipelineExecutableStatisticKHR
*end
= s
+ (pStatistics
? *pStatisticCount
: 0);
5643 VkResult result
= VK_SUCCESS
;
5646 desc_copy(s
->name
, "SGPRs");
5647 desc_copy(s
->description
, "Number of SGPR registers allocated per subgroup");
5648 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5649 s
->value
.u64
= shader
->config
.num_sgprs
;
5654 desc_copy(s
->name
, "VGPRs");
5655 desc_copy(s
->description
, "Number of VGPR registers allocated per subgroup");
5656 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5657 s
->value
.u64
= shader
->config
.num_vgprs
;
5662 desc_copy(s
->name
, "Spilled SGPRs");
5663 desc_copy(s
->description
, "Number of SGPR registers spilled per subgroup");
5664 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5665 s
->value
.u64
= shader
->config
.spilled_sgprs
;
5670 desc_copy(s
->name
, "Spilled VGPRs");
5671 desc_copy(s
->description
, "Number of VGPR registers spilled per subgroup");
5672 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5673 s
->value
.u64
= shader
->config
.spilled_vgprs
;
5678 desc_copy(s
->name
, "PrivMem VGPRs");
5679 desc_copy(s
->description
, "Number of VGPRs stored in private memory per subgroup");
5680 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5681 s
->value
.u64
= shader
->info
.private_mem_vgprs
;
5686 desc_copy(s
->name
, "Code size");
5687 desc_copy(s
->description
, "Code size in bytes");
5688 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5689 s
->value
.u64
= shader
->exec_size
;
5694 desc_copy(s
->name
, "LDS size");
5695 desc_copy(s
->description
, "LDS size in bytes per workgroup");
5696 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5697 s
->value
.u64
= shader
->config
.lds_size
* lds_increment
;
5702 desc_copy(s
->name
, "Scratch size");
5703 desc_copy(s
->description
, "Private memory in bytes per subgroup");
5704 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5705 s
->value
.u64
= shader
->config
.scratch_bytes_per_wave
;
5710 desc_copy(s
->name
, "Subgroups per SIMD");
5711 desc_copy(s
->description
, "The maximum number of subgroups in flight on a SIMD unit");
5712 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5713 s
->value
.u64
= max_waves
;
5717 if (shader
->statistics
) {
5718 for (unsigned i
= 0; i
< shader
->statistics
->count
; i
++) {
5719 struct radv_compiler_statistic_info
*info
= &shader
->statistics
->infos
[i
];
5720 uint32_t value
= shader
->statistics
->values
[i
];
5722 desc_copy(s
->name
, info
->name
);
5723 desc_copy(s
->description
, info
->desc
);
5724 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5725 s
->value
.u64
= value
;
5732 *pStatisticCount
= s
- pStatistics
;
5734 *pStatisticCount
= end
- pStatistics
;
5735 result
= VK_INCOMPLETE
;
5737 *pStatisticCount
= s
- pStatistics
;
5743 static VkResult
radv_copy_representation(void *data
, size_t *data_size
, const char *src
)
5745 size_t total_size
= strlen(src
) + 1;
5748 *data_size
= total_size
;
5752 size_t size
= MIN2(total_size
, *data_size
);
5754 memcpy(data
, src
, size
);
5756 *((char*)data
+ size
- 1) = 0;
5757 return size
< total_size
? VK_INCOMPLETE
: VK_SUCCESS
;
5760 VkResult
radv_GetPipelineExecutableInternalRepresentationsKHR(
5762 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5763 uint32_t* pInternalRepresentationCount
,
5764 VkPipelineExecutableInternalRepresentationKHR
* pInternalRepresentations
)
5766 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5767 gl_shader_stage stage
;
5768 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5770 VkPipelineExecutableInternalRepresentationKHR
*p
= pInternalRepresentations
;
5771 VkPipelineExecutableInternalRepresentationKHR
*end
= p
+ (pInternalRepresentations
? *pInternalRepresentationCount
: 0);
5772 VkResult result
= VK_SUCCESS
;
5776 desc_copy(p
->name
, "NIR Shader(s)");
5777 desc_copy(p
->description
, "The optimized NIR shader(s)");
5778 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->nir_string
) != VK_SUCCESS
)
5779 result
= VK_INCOMPLETE
;
5786 if (pipeline
->device
->physical_device
->use_aco
) {
5787 desc_copy(p
->name
, "ACO IR");
5788 desc_copy(p
->description
, "The ACO IR after some optimizations");
5790 desc_copy(p
->name
, "LLVM IR");
5791 desc_copy(p
->description
, "The LLVM IR after some optimizations");
5793 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->ir_string
) != VK_SUCCESS
)
5794 result
= VK_INCOMPLETE
;
5801 desc_copy(p
->name
, "Assembly");
5802 desc_copy(p
->description
, "Final Assembly");
5803 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->disasm_string
) != VK_SUCCESS
)
5804 result
= VK_INCOMPLETE
;
5808 if (!pInternalRepresentations
)
5809 *pInternalRepresentationCount
= p
- pInternalRepresentations
;
5811 result
= VK_INCOMPLETE
;
5812 *pInternalRepresentationCount
= end
- pInternalRepresentations
;
5814 *pInternalRepresentationCount
= p
- pInternalRepresentations
;