2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
34 #include "radv_shader.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
48 #include "ac_shader_util.h"
50 struct radv_blend_state
{
51 uint32_t blend_enable_4bit
;
52 uint32_t need_src_alpha
;
54 uint32_t cb_color_control
;
55 uint32_t cb_target_mask
;
56 uint32_t cb_target_enabled_4bit
;
57 uint32_t sx_mrt_blend_opt
[8];
58 uint32_t cb_blend_control
[8];
60 uint32_t spi_shader_col_format
;
61 uint32_t col_format_is_int8
;
62 uint32_t col_format_is_int10
;
63 uint32_t cb_shader_mask
;
64 uint32_t db_alpha_to_mask
;
66 uint32_t commutative_4bit
;
68 bool single_cb_enable
;
69 bool mrt0_is_dual_src
;
72 struct radv_dsa_order_invariance
{
73 /* Whether the final result in Z/S buffers is guaranteed to be
74 * invariant under changes to the order in which fragments arrive.
78 /* Whether the set of fragments that pass the combined Z/S test is
79 * guaranteed to be invariant under changes to the order in which
85 struct radv_tessellation_state
{
86 uint32_t ls_hs_config
;
90 static const VkPipelineMultisampleStateCreateInfo
*
91 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
93 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
94 return pCreateInfo
->pMultisampleState
;
98 static const VkPipelineTessellationStateCreateInfo
*
99 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
101 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
102 if (pCreateInfo
->pStages
[i
].stage
== VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
||
103 pCreateInfo
->pStages
[i
].stage
== VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
) {
104 return pCreateInfo
->pTessellationState
;
110 static const VkPipelineDepthStencilStateCreateInfo
*
111 radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
113 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
114 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
116 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
117 subpass
->depth_stencil_attachment
)
118 return pCreateInfo
->pDepthStencilState
;
122 static const VkPipelineColorBlendStateCreateInfo
*
123 radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
125 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
126 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
128 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
129 subpass
->has_color_att
)
130 return pCreateInfo
->pColorBlendState
;
134 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
)
136 struct radv_shader_variant
*variant
= NULL
;
137 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
138 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
139 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
140 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
141 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
142 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
145 return variant
->info
.is_ngg
;
148 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline
*pipeline
)
150 assert(radv_pipeline_has_ngg(pipeline
));
152 struct radv_shader_variant
*variant
= NULL
;
153 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
154 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
155 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
156 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
157 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
158 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
161 return variant
->info
.is_ngg_passthrough
;
164 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
)
166 if (!radv_pipeline_has_gs(pipeline
))
169 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
170 * On GFX10, it might be required in rare cases if it's not possible to
173 if (radv_pipeline_has_ngg(pipeline
))
176 assert(pipeline
->gs_copy_shader
);
181 radv_pipeline_destroy(struct radv_device
*device
,
182 struct radv_pipeline
*pipeline
,
183 const VkAllocationCallbacks
* allocator
)
185 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
186 if (pipeline
->shaders
[i
])
187 radv_shader_variant_destroy(device
, pipeline
->shaders
[i
]);
189 if (pipeline
->gs_copy_shader
)
190 radv_shader_variant_destroy(device
, pipeline
->gs_copy_shader
);
193 free(pipeline
->cs
.buf
);
195 vk_object_base_finish(&pipeline
->base
);
196 vk_free2(&device
->vk
.alloc
, allocator
, pipeline
);
199 void radv_DestroyPipeline(
201 VkPipeline _pipeline
,
202 const VkAllocationCallbacks
* pAllocator
)
204 RADV_FROM_HANDLE(radv_device
, device
, _device
);
205 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
210 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
213 static uint32_t get_hash_flags(struct radv_device
*device
)
215 uint32_t hash_flags
= 0;
217 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_NGG
)
218 hash_flags
|= RADV_HASH_SHADER_NO_NGG
;
219 if (device
->physical_device
->cs_wave_size
== 32)
220 hash_flags
|= RADV_HASH_SHADER_CS_WAVE32
;
221 if (device
->physical_device
->ps_wave_size
== 32)
222 hash_flags
|= RADV_HASH_SHADER_PS_WAVE32
;
223 if (device
->physical_device
->ge_wave_size
== 32)
224 hash_flags
|= RADV_HASH_SHADER_GE_WAVE32
;
225 if (device
->physical_device
->use_llvm
)
226 hash_flags
|= RADV_HASH_SHADER_LLVM
;
231 radv_pipeline_scratch_init(struct radv_device
*device
,
232 struct radv_pipeline
*pipeline
)
234 unsigned scratch_bytes_per_wave
= 0;
235 unsigned max_waves
= 0;
236 unsigned min_waves
= 1;
238 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
239 if (pipeline
->shaders
[i
] &&
240 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
) {
241 unsigned max_stage_waves
= device
->scratch_waves
;
243 scratch_bytes_per_wave
= MAX2(scratch_bytes_per_wave
,
244 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
);
246 max_stage_waves
= MIN2(max_stage_waves
,
247 4 * device
->physical_device
->rad_info
.num_good_compute_units
*
248 (256 / pipeline
->shaders
[i
]->config
.num_vgprs
));
249 max_waves
= MAX2(max_waves
, max_stage_waves
);
253 if (pipeline
->shaders
[MESA_SHADER_COMPUTE
]) {
254 unsigned group_size
= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[0] *
255 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[1] *
256 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[2];
257 min_waves
= MAX2(min_waves
, round_up_u32(group_size
, 64));
260 pipeline
->scratch_bytes_per_wave
= scratch_bytes_per_wave
;
261 pipeline
->max_waves
= max_waves
;
265 static uint32_t si_translate_blend_logic_op(VkLogicOp op
)
268 case VK_LOGIC_OP_CLEAR
:
269 return V_028808_ROP3_CLEAR
;
270 case VK_LOGIC_OP_AND
:
271 return V_028808_ROP3_AND
;
272 case VK_LOGIC_OP_AND_REVERSE
:
273 return V_028808_ROP3_AND_REVERSE
;
274 case VK_LOGIC_OP_COPY
:
275 return V_028808_ROP3_COPY
;
276 case VK_LOGIC_OP_AND_INVERTED
:
277 return V_028808_ROP3_AND_INVERTED
;
278 case VK_LOGIC_OP_NO_OP
:
279 return V_028808_ROP3_NO_OP
;
280 case VK_LOGIC_OP_XOR
:
281 return V_028808_ROP3_XOR
;
283 return V_028808_ROP3_OR
;
284 case VK_LOGIC_OP_NOR
:
285 return V_028808_ROP3_NOR
;
286 case VK_LOGIC_OP_EQUIVALENT
:
287 return V_028808_ROP3_EQUIVALENT
;
288 case VK_LOGIC_OP_INVERT
:
289 return V_028808_ROP3_INVERT
;
290 case VK_LOGIC_OP_OR_REVERSE
:
291 return V_028808_ROP3_OR_REVERSE
;
292 case VK_LOGIC_OP_COPY_INVERTED
:
293 return V_028808_ROP3_COPY_INVERTED
;
294 case VK_LOGIC_OP_OR_INVERTED
:
295 return V_028808_ROP3_OR_INVERTED
;
296 case VK_LOGIC_OP_NAND
:
297 return V_028808_ROP3_NAND
;
298 case VK_LOGIC_OP_SET
:
299 return V_028808_ROP3_SET
;
301 unreachable("Unhandled logic op");
306 static uint32_t si_translate_blend_function(VkBlendOp op
)
309 case VK_BLEND_OP_ADD
:
310 return V_028780_COMB_DST_PLUS_SRC
;
311 case VK_BLEND_OP_SUBTRACT
:
312 return V_028780_COMB_SRC_MINUS_DST
;
313 case VK_BLEND_OP_REVERSE_SUBTRACT
:
314 return V_028780_COMB_DST_MINUS_SRC
;
315 case VK_BLEND_OP_MIN
:
316 return V_028780_COMB_MIN_DST_SRC
;
317 case VK_BLEND_OP_MAX
:
318 return V_028780_COMB_MAX_DST_SRC
;
324 static uint32_t si_translate_blend_factor(VkBlendFactor factor
)
327 case VK_BLEND_FACTOR_ZERO
:
328 return V_028780_BLEND_ZERO
;
329 case VK_BLEND_FACTOR_ONE
:
330 return V_028780_BLEND_ONE
;
331 case VK_BLEND_FACTOR_SRC_COLOR
:
332 return V_028780_BLEND_SRC_COLOR
;
333 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
334 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
335 case VK_BLEND_FACTOR_DST_COLOR
:
336 return V_028780_BLEND_DST_COLOR
;
337 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
338 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
339 case VK_BLEND_FACTOR_SRC_ALPHA
:
340 return V_028780_BLEND_SRC_ALPHA
;
341 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
342 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
343 case VK_BLEND_FACTOR_DST_ALPHA
:
344 return V_028780_BLEND_DST_ALPHA
;
345 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
346 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
347 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
348 return V_028780_BLEND_CONSTANT_COLOR
;
349 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
350 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
351 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
352 return V_028780_BLEND_CONSTANT_ALPHA
;
353 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
354 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
355 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
356 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
357 case VK_BLEND_FACTOR_SRC1_COLOR
:
358 return V_028780_BLEND_SRC1_COLOR
;
359 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
360 return V_028780_BLEND_INV_SRC1_COLOR
;
361 case VK_BLEND_FACTOR_SRC1_ALPHA
:
362 return V_028780_BLEND_SRC1_ALPHA
;
363 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
364 return V_028780_BLEND_INV_SRC1_ALPHA
;
370 static uint32_t si_translate_blend_opt_function(VkBlendOp op
)
373 case VK_BLEND_OP_ADD
:
374 return V_028760_OPT_COMB_ADD
;
375 case VK_BLEND_OP_SUBTRACT
:
376 return V_028760_OPT_COMB_SUBTRACT
;
377 case VK_BLEND_OP_REVERSE_SUBTRACT
:
378 return V_028760_OPT_COMB_REVSUBTRACT
;
379 case VK_BLEND_OP_MIN
:
380 return V_028760_OPT_COMB_MIN
;
381 case VK_BLEND_OP_MAX
:
382 return V_028760_OPT_COMB_MAX
;
384 return V_028760_OPT_COMB_BLEND_DISABLED
;
388 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor
, bool is_alpha
)
391 case VK_BLEND_FACTOR_ZERO
:
392 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
393 case VK_BLEND_FACTOR_ONE
:
394 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
395 case VK_BLEND_FACTOR_SRC_COLOR
:
396 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
397 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
398 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
399 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
400 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
401 case VK_BLEND_FACTOR_SRC_ALPHA
:
402 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
403 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
404 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
405 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
406 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
407 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
409 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
414 * Get rid of DST in the blend factors by commuting the operands:
415 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
417 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
418 unsigned *dst_factor
, unsigned expected_dst
,
419 unsigned replacement_src
)
421 if (*src_factor
== expected_dst
&&
422 *dst_factor
== VK_BLEND_FACTOR_ZERO
) {
423 *src_factor
= VK_BLEND_FACTOR_ZERO
;
424 *dst_factor
= replacement_src
;
426 /* Commuting the operands requires reversing subtractions. */
427 if (*func
== VK_BLEND_OP_SUBTRACT
)
428 *func
= VK_BLEND_OP_REVERSE_SUBTRACT
;
429 else if (*func
== VK_BLEND_OP_REVERSE_SUBTRACT
)
430 *func
= VK_BLEND_OP_SUBTRACT
;
434 static bool si_blend_factor_uses_dst(unsigned factor
)
436 return factor
== VK_BLEND_FACTOR_DST_COLOR
||
437 factor
== VK_BLEND_FACTOR_DST_ALPHA
||
438 factor
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
439 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
||
440 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
;
443 static bool is_dual_src(VkBlendFactor factor
)
446 case VK_BLEND_FACTOR_SRC1_COLOR
:
447 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
448 case VK_BLEND_FACTOR_SRC1_ALPHA
:
449 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
456 static unsigned radv_choose_spi_color_format(VkFormat vk_format
,
458 bool blend_need_alpha
)
460 const struct vk_format_description
*desc
= vk_format_description(vk_format
);
461 struct ac_spi_color_formats formats
= {};
462 unsigned format
, ntype
, swap
;
464 format
= radv_translate_colorformat(vk_format
);
465 ntype
= radv_translate_color_numformat(vk_format
, desc
,
466 vk_format_get_first_non_void_channel(vk_format
));
467 swap
= radv_translate_colorswap(vk_format
, false);
469 ac_choose_spi_color_formats(format
, swap
, ntype
, false, &formats
);
471 if (blend_enable
&& blend_need_alpha
)
472 return formats
.blend_alpha
;
473 else if(blend_need_alpha
)
474 return formats
.alpha
;
475 else if(blend_enable
)
476 return formats
.blend
;
478 return formats
.normal
;
482 format_is_int8(VkFormat format
)
484 const struct vk_format_description
*desc
= vk_format_description(format
);
485 int channel
= vk_format_get_first_non_void_channel(format
);
487 return channel
>= 0 && desc
->channel
[channel
].pure_integer
&&
488 desc
->channel
[channel
].size
== 8;
492 format_is_int10(VkFormat format
)
494 const struct vk_format_description
*desc
= vk_format_description(format
);
496 if (desc
->nr_channels
!= 4)
498 for (unsigned i
= 0; i
< 4; i
++) {
499 if (desc
->channel
[i
].pure_integer
&& desc
->channel
[i
].size
== 10)
506 radv_pipeline_compute_spi_color_formats(struct radv_pipeline
*pipeline
,
507 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
508 struct radv_blend_state
*blend
)
510 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
511 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
512 unsigned col_format
= 0, is_int8
= 0, is_int10
= 0;
513 unsigned num_targets
;
515 for (unsigned i
= 0; i
< (blend
->single_cb_enable
? 1 : subpass
->color_count
); ++i
) {
518 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
||
519 !(blend
->cb_target_mask
& (0xfu
<< (i
* 4)))) {
520 cf
= V_028714_SPI_SHADER_ZERO
;
522 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
524 blend
->blend_enable_4bit
& (0xfu
<< (i
* 4));
526 cf
= radv_choose_spi_color_format(attachment
->format
,
528 blend
->need_src_alpha
& (1 << i
));
530 if (format_is_int8(attachment
->format
))
532 if (format_is_int10(attachment
->format
))
536 col_format
|= cf
<< (4 * i
);
539 if (!(col_format
& 0xf) && blend
->need_src_alpha
& (1 << 0)) {
540 /* When a subpass doesn't have any color attachments, write the
541 * alpha channel of MRT0 when alpha coverage is enabled because
542 * the depth attachment needs it.
544 col_format
|= V_028714_SPI_SHADER_32_AR
;
547 /* If the i-th target format is set, all previous target formats must
548 * be non-zero to avoid hangs.
550 num_targets
= (util_last_bit(col_format
) + 3) / 4;
551 for (unsigned i
= 0; i
< num_targets
; i
++) {
552 if (!(col_format
& (0xf << (i
* 4)))) {
553 col_format
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
557 /* The output for dual source blending should have the same format as
560 if (blend
->mrt0_is_dual_src
)
561 col_format
|= (col_format
& 0xf) << 4;
563 blend
->spi_shader_col_format
= col_format
;
564 blend
->col_format_is_int8
= is_int8
;
565 blend
->col_format_is_int10
= is_int10
;
569 * Ordered so that for each i,
570 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
572 const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
] = {
573 VK_FORMAT_R32_SFLOAT
,
574 VK_FORMAT_R32G32_SFLOAT
,
575 VK_FORMAT_R8G8B8A8_UNORM
,
576 VK_FORMAT_R16G16B16A16_UNORM
,
577 VK_FORMAT_R16G16B16A16_SNORM
,
578 VK_FORMAT_R16G16B16A16_UINT
,
579 VK_FORMAT_R16G16B16A16_SINT
,
580 VK_FORMAT_R32G32B32A32_SFLOAT
,
581 VK_FORMAT_R8G8B8A8_UINT
,
582 VK_FORMAT_R8G8B8A8_SINT
,
583 VK_FORMAT_A2R10G10B10_UINT_PACK32
,
584 VK_FORMAT_A2R10G10B10_SINT_PACK32
,
587 unsigned radv_format_meta_fs_key(VkFormat format
)
589 unsigned col_format
= radv_choose_spi_color_format(format
, false, false);
591 assert(col_format
!= V_028714_SPI_SHADER_32_AR
);
592 if (col_format
>= V_028714_SPI_SHADER_32_AR
)
593 --col_format
; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
595 --col_format
; /* Skip V_028714_SPI_SHADER_ZERO */
596 bool is_int8
= format_is_int8(format
);
597 bool is_int10
= format_is_int10(format
);
599 return col_format
+ (is_int8
? 3 : is_int10
? 5 : 0);
603 radv_blend_check_commutativity(struct radv_blend_state
*blend
,
604 VkBlendOp op
, VkBlendFactor src
,
605 VkBlendFactor dst
, unsigned chanmask
)
607 /* Src factor is allowed when it does not depend on Dst. */
608 static const uint32_t src_allowed
=
609 (1u << VK_BLEND_FACTOR_ONE
) |
610 (1u << VK_BLEND_FACTOR_SRC_COLOR
) |
611 (1u << VK_BLEND_FACTOR_SRC_ALPHA
) |
612 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
) |
613 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR
) |
614 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA
) |
615 (1u << VK_BLEND_FACTOR_SRC1_COLOR
) |
616 (1u << VK_BLEND_FACTOR_SRC1_ALPHA
) |
617 (1u << VK_BLEND_FACTOR_ZERO
) |
618 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
) |
619 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
) |
620 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
) |
621 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
) |
622 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
) |
623 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
);
625 if (dst
== VK_BLEND_FACTOR_ONE
&&
626 (src_allowed
& (1u << src
))) {
627 /* Addition is commutative, but floating point addition isn't
628 * associative: subtle changes can be introduced via different
629 * rounding. Be conservative, only enable for min and max.
631 if (op
== VK_BLEND_OP_MAX
|| op
== VK_BLEND_OP_MIN
)
632 blend
->commutative_4bit
|= chanmask
;
636 static struct radv_blend_state
637 radv_pipeline_init_blend_state(struct radv_pipeline
*pipeline
,
638 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
639 const struct radv_graphics_pipeline_create_info
*extra
)
641 const VkPipelineColorBlendStateCreateInfo
*vkblend
= radv_pipeline_get_color_blend_state(pCreateInfo
);
642 const VkPipelineMultisampleStateCreateInfo
*vkms
= radv_pipeline_get_multisample_state(pCreateInfo
);
643 struct radv_blend_state blend
= {0};
644 unsigned mode
= V_028808_CB_NORMAL
;
647 if (extra
&& extra
->custom_blend_mode
) {
648 blend
.single_cb_enable
= true;
649 mode
= extra
->custom_blend_mode
;
652 blend
.cb_color_control
= 0;
654 if (vkblend
->logicOpEnable
)
655 blend
.cb_color_control
|= S_028808_ROP3(si_translate_blend_logic_op(vkblend
->logicOp
));
657 blend
.cb_color_control
|= S_028808_ROP3(V_028808_ROP3_COPY
);
660 blend
.db_alpha_to_mask
= S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
661 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
662 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
663 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
664 S_028B70_OFFSET_ROUND(1);
666 if (vkms
&& vkms
->alphaToCoverageEnable
) {
667 blend
.db_alpha_to_mask
|= S_028B70_ALPHA_TO_MASK_ENABLE(1);
668 blend
.need_src_alpha
|= 0x1;
671 blend
.cb_target_mask
= 0;
673 for (i
= 0; i
< vkblend
->attachmentCount
; i
++) {
674 const VkPipelineColorBlendAttachmentState
*att
= &vkblend
->pAttachments
[i
];
675 unsigned blend_cntl
= 0;
676 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
677 VkBlendOp eqRGB
= att
->colorBlendOp
;
678 VkBlendFactor srcRGB
= att
->srcColorBlendFactor
;
679 VkBlendFactor dstRGB
= att
->dstColorBlendFactor
;
680 VkBlendOp eqA
= att
->alphaBlendOp
;
681 VkBlendFactor srcA
= att
->srcAlphaBlendFactor
;
682 VkBlendFactor dstA
= att
->dstAlphaBlendFactor
;
684 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
686 if (!att
->colorWriteMask
)
689 blend
.cb_target_mask
|= (unsigned)att
->colorWriteMask
<< (4 * i
);
690 blend
.cb_target_enabled_4bit
|= 0xf << (4 * i
);
691 if (!att
->blendEnable
) {
692 blend
.cb_blend_control
[i
] = blend_cntl
;
696 if (is_dual_src(srcRGB
) || is_dual_src(dstRGB
) || is_dual_src(srcA
) || is_dual_src(dstA
))
698 blend
.mrt0_is_dual_src
= true;
700 if (eqRGB
== VK_BLEND_OP_MIN
|| eqRGB
== VK_BLEND_OP_MAX
) {
701 srcRGB
= VK_BLEND_FACTOR_ONE
;
702 dstRGB
= VK_BLEND_FACTOR_ONE
;
704 if (eqA
== VK_BLEND_OP_MIN
|| eqA
== VK_BLEND_OP_MAX
) {
705 srcA
= VK_BLEND_FACTOR_ONE
;
706 dstA
= VK_BLEND_FACTOR_ONE
;
709 radv_blend_check_commutativity(&blend
, eqRGB
, srcRGB
, dstRGB
,
711 radv_blend_check_commutativity(&blend
, eqA
, srcA
, dstA
,
714 /* Blending optimizations for RB+.
715 * These transformations don't change the behavior.
717 * First, get rid of DST in the blend factors:
718 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
720 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
721 VK_BLEND_FACTOR_DST_COLOR
,
722 VK_BLEND_FACTOR_SRC_COLOR
);
724 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
725 VK_BLEND_FACTOR_DST_COLOR
,
726 VK_BLEND_FACTOR_SRC_COLOR
);
728 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
729 VK_BLEND_FACTOR_DST_ALPHA
,
730 VK_BLEND_FACTOR_SRC_ALPHA
);
732 /* Look up the ideal settings from tables. */
733 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
734 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
735 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
736 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
738 /* Handle interdependencies. */
739 if (si_blend_factor_uses_dst(srcRGB
))
740 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
741 if (si_blend_factor_uses_dst(srcA
))
742 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
744 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
&&
745 (dstRGB
== VK_BLEND_FACTOR_ZERO
||
746 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
747 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
))
748 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
750 /* Set the final value. */
751 blend
.sx_mrt_blend_opt
[i
] =
752 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
753 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
754 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
755 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
756 S_028760_ALPHA_DST_OPT(dstA_opt
) |
757 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
758 blend_cntl
|= S_028780_ENABLE(1);
760 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
761 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
762 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
763 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
764 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
765 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
766 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
767 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
769 blend
.cb_blend_control
[i
] = blend_cntl
;
771 blend
.blend_enable_4bit
|= 0xfu
<< (i
* 4);
773 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
774 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
775 srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
776 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
777 srcRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
||
778 dstRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
)
779 blend
.need_src_alpha
|= 1 << i
;
781 for (i
= vkblend
->attachmentCount
; i
< 8; i
++) {
782 blend
.cb_blend_control
[i
] = 0;
783 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
787 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
788 /* Disable RB+ blend optimizations for dual source blending. */
789 if (blend
.mrt0_is_dual_src
) {
790 for (i
= 0; i
< 8; i
++) {
791 blend
.sx_mrt_blend_opt
[i
] =
792 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
793 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
797 /* RB+ doesn't work with dual source blending, logic op and
800 if (blend
.mrt0_is_dual_src
||
801 (vkblend
&& vkblend
->logicOpEnable
) ||
802 mode
== V_028808_CB_RESOLVE
)
803 blend
.cb_color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
806 if (blend
.cb_target_mask
)
807 blend
.cb_color_control
|= S_028808_MODE(mode
);
809 blend
.cb_color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
811 radv_pipeline_compute_spi_color_formats(pipeline
, pCreateInfo
, &blend
);
815 static uint32_t si_translate_fill(VkPolygonMode func
)
818 case VK_POLYGON_MODE_FILL
:
819 return V_028814_X_DRAW_TRIANGLES
;
820 case VK_POLYGON_MODE_LINE
:
821 return V_028814_X_DRAW_LINES
;
822 case VK_POLYGON_MODE_POINT
:
823 return V_028814_X_DRAW_POINTS
;
826 return V_028814_X_DRAW_POINTS
;
830 static uint8_t radv_pipeline_get_ps_iter_samples(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
832 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
833 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
834 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
835 uint32_t ps_iter_samples
= 1;
836 uint32_t num_samples
;
838 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
840 * "If the VK_AMD_mixed_attachment_samples extension is enabled and the
841 * subpass uses color attachments, totalSamples is the number of
842 * samples of the color attachments. Otherwise, totalSamples is the
843 * value of VkPipelineMultisampleStateCreateInfo::rasterizationSamples
844 * specified at pipeline creation time."
846 if (subpass
->has_color_att
) {
847 num_samples
= subpass
->color_sample_count
;
849 num_samples
= vkms
->rasterizationSamples
;
852 if (vkms
->sampleShadingEnable
) {
853 ps_iter_samples
= ceilf(vkms
->minSampleShading
* num_samples
);
854 ps_iter_samples
= util_next_power_of_two(ps_iter_samples
);
856 return ps_iter_samples
;
860 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
862 return pCreateInfo
->depthTestEnable
&&
863 pCreateInfo
->depthWriteEnable
&&
864 pCreateInfo
->depthCompareOp
!= VK_COMPARE_OP_NEVER
;
868 radv_writes_stencil(const VkStencilOpState
*state
)
870 return state
->writeMask
&&
871 (state
->failOp
!= VK_STENCIL_OP_KEEP
||
872 state
->passOp
!= VK_STENCIL_OP_KEEP
||
873 state
->depthFailOp
!= VK_STENCIL_OP_KEEP
);
877 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
879 return pCreateInfo
->stencilTestEnable
&&
880 (radv_writes_stencil(&pCreateInfo
->front
) ||
881 radv_writes_stencil(&pCreateInfo
->back
));
885 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
887 return radv_is_depth_write_enabled(pCreateInfo
) ||
888 radv_is_stencil_write_enabled(pCreateInfo
);
892 radv_order_invariant_stencil_op(VkStencilOp op
)
894 /* REPLACE is normally order invariant, except when the stencil
895 * reference value is written by the fragment shader. Tracking this
896 * interaction does not seem worth the effort, so be conservative.
898 return op
!= VK_STENCIL_OP_INCREMENT_AND_CLAMP
&&
899 op
!= VK_STENCIL_OP_DECREMENT_AND_CLAMP
&&
900 op
!= VK_STENCIL_OP_REPLACE
;
904 radv_order_invariant_stencil_state(const VkStencilOpState
*state
)
906 /* Compute whether, assuming Z writes are disabled, this stencil state
907 * is order invariant in the sense that the set of passing fragments as
908 * well as the final stencil buffer result does not depend on the order
911 return !state
->writeMask
||
912 /* The following assumes that Z writes are disabled. */
913 (state
->compareOp
== VK_COMPARE_OP_ALWAYS
&&
914 radv_order_invariant_stencil_op(state
->passOp
) &&
915 radv_order_invariant_stencil_op(state
->depthFailOp
)) ||
916 (state
->compareOp
== VK_COMPARE_OP_NEVER
&&
917 radv_order_invariant_stencil_op(state
->failOp
));
921 radv_pipeline_has_dynamic_ds_states(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
923 VkDynamicState ds_states
[] = {
924 VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT
,
925 VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT
,
926 VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT
,
927 VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT
,
928 VK_DYNAMIC_STATE_STENCIL_OP_EXT
,
931 if (pCreateInfo
->pDynamicState
) {
932 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
933 for (uint32_t i
= 0; i
< count
; i
++) {
934 for (uint32_t j
= 0; j
< ARRAY_SIZE(ds_states
); j
++) {
935 if (pCreateInfo
->pDynamicState
->pDynamicStates
[i
] == ds_states
[j
])
945 radv_pipeline_out_of_order_rast(struct radv_pipeline
*pipeline
,
946 struct radv_blend_state
*blend
,
947 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
949 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
950 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
951 const VkPipelineDepthStencilStateCreateInfo
*vkds
= radv_pipeline_get_depth_stencil_state(pCreateInfo
);
952 const VkPipelineColorBlendStateCreateInfo
*vkblend
= radv_pipeline_get_color_blend_state(pCreateInfo
);
953 unsigned colormask
= blend
->cb_target_enabled_4bit
;
955 if (!pipeline
->device
->physical_device
->out_of_order_rast_allowed
)
958 /* Be conservative if a logic operation is enabled with color buffers. */
959 if (colormask
&& vkblend
&& vkblend
->logicOpEnable
)
962 /* Be conservative if an extended dynamic depth/stencil state is
963 * enabled because the driver can't update out-of-order rasterization
966 if (radv_pipeline_has_dynamic_ds_states(pCreateInfo
))
969 /* Default depth/stencil invariance when no attachment is bound. */
970 struct radv_dsa_order_invariance dsa_order_invariant
= {
971 .zs
= true, .pass_set
= true
975 struct radv_render_pass_attachment
*attachment
=
976 pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
977 bool has_stencil
= vk_format_is_stencil(attachment
->format
);
978 struct radv_dsa_order_invariance order_invariance
[2];
979 struct radv_shader_variant
*ps
=
980 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
982 /* Compute depth/stencil order invariance in order to know if
983 * it's safe to enable out-of-order.
985 bool zfunc_is_ordered
=
986 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
||
987 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS
||
988 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS_OR_EQUAL
||
989 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER
||
990 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER_OR_EQUAL
;
992 bool nozwrite_and_order_invariant_stencil
=
993 !radv_is_ds_write_enabled(vkds
) ||
994 (!radv_is_depth_write_enabled(vkds
) &&
995 radv_order_invariant_stencil_state(&vkds
->front
) &&
996 radv_order_invariant_stencil_state(&vkds
->back
));
998 order_invariance
[1].zs
=
999 nozwrite_and_order_invariant_stencil
||
1000 (!radv_is_stencil_write_enabled(vkds
) &&
1002 order_invariance
[0].zs
=
1003 !radv_is_depth_write_enabled(vkds
) || zfunc_is_ordered
;
1005 order_invariance
[1].pass_set
=
1006 nozwrite_and_order_invariant_stencil
||
1007 (!radv_is_stencil_write_enabled(vkds
) &&
1008 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1009 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
));
1010 order_invariance
[0].pass_set
=
1011 !radv_is_depth_write_enabled(vkds
) ||
1012 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1013 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
);
1015 dsa_order_invariant
= order_invariance
[has_stencil
];
1016 if (!dsa_order_invariant
.zs
)
1019 /* The set of PS invocations is always order invariant,
1020 * except when early Z/S tests are requested.
1023 ps
->info
.ps
.writes_memory
&&
1024 ps
->info
.ps
.early_fragment_test
&&
1025 !dsa_order_invariant
.pass_set
)
1028 /* Determine if out-of-order rasterization should be disabled
1029 * when occlusion queries are used.
1031 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
=
1032 !dsa_order_invariant
.pass_set
;
1035 /* No color buffers are enabled for writing. */
1039 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
1042 /* Only commutative blending. */
1043 if (blendmask
& ~blend
->commutative_4bit
)
1046 if (!dsa_order_invariant
.pass_set
)
1050 if (colormask
& ~blendmask
)
1057 radv_pipeline_init_multisample_state(struct radv_pipeline
*pipeline
,
1058 struct radv_blend_state
*blend
,
1059 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1061 const VkPipelineMultisampleStateCreateInfo
*vkms
= radv_pipeline_get_multisample_state(pCreateInfo
);
1062 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
1063 unsigned num_tile_pipes
= pipeline
->device
->physical_device
->rad_info
.num_tile_pipes
;
1064 bool out_of_order_rast
= false;
1065 int ps_iter_samples
= 1;
1066 uint32_t mask
= 0xffff;
1069 ms
->num_samples
= vkms
->rasterizationSamples
;
1071 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1073 * "Sample shading is enabled for a graphics pipeline:
1075 * - If the interface of the fragment shader entry point of the
1076 * graphics pipeline includes an input variable decorated
1077 * with SampleId or SamplePosition. In this case
1078 * minSampleShadingFactor takes the value 1.0.
1079 * - Else if the sampleShadingEnable member of the
1080 * VkPipelineMultisampleStateCreateInfo structure specified
1081 * when creating the graphics pipeline is set to VK_TRUE. In
1082 * this case minSampleShadingFactor takes the value of
1083 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1085 * Otherwise, sample shading is considered disabled."
1087 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.force_persample
) {
1088 ps_iter_samples
= ms
->num_samples
;
1090 ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
);
1093 ms
->num_samples
= 1;
1096 const struct VkPipelineRasterizationStateRasterizationOrderAMD
*raster_order
=
1097 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD
);
1098 if (raster_order
&& raster_order
->rasterizationOrder
== VK_RASTERIZATION_ORDER_RELAXED_AMD
) {
1099 /* Out-of-order rasterization is explicitly enabled by the
1102 out_of_order_rast
= true;
1104 /* Determine if the driver can enable out-of-order
1105 * rasterization internally.
1108 radv_pipeline_out_of_order_rast(pipeline
, blend
, pCreateInfo
);
1111 ms
->pa_sc_aa_config
= 0;
1112 ms
->db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1113 S_028804_INCOHERENT_EQAA_READS(1) |
1114 S_028804_INTERPOLATE_COMP_Z(1) |
1115 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1116 ms
->pa_sc_mode_cntl_1
=
1117 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1118 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
1119 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
1120 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1122 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1123 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1124 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1125 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1126 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1127 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1128 ms
->pa_sc_mode_cntl_0
= S_028A48_ALTERNATE_RBS_PER_TILE(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
1129 S_028A48_VPORT_SCISSOR_ENABLE(1);
1131 const VkPipelineRasterizationLineStateCreateInfoEXT
*rast_line
=
1132 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1133 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1135 ms
->pa_sc_mode_cntl_0
|= S_028A48_LINE_STIPPLE_ENABLE(rast_line
->stippledLineEnable
);
1136 if (rast_line
->lineRasterizationMode
== VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT
) {
1137 /* From the Vulkan spec 1.1.129:
1139 * "When VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT lines
1140 * are being rasterized, sample locations may all be
1141 * treated as being at the pixel center (this may
1142 * affect attribute and depth interpolation)."
1144 ms
->num_samples
= 1;
1148 if (ms
->num_samples
> 1) {
1149 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1150 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1151 uint32_t z_samples
= subpass
->depth_stencil_attachment
? subpass
->depth_sample_count
: ms
->num_samples
;
1152 unsigned log_samples
= util_logbase2(ms
->num_samples
);
1153 unsigned log_z_samples
= util_logbase2(z_samples
);
1154 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
1155 ms
->pa_sc_mode_cntl_0
|= S_028A48_MSAA_ENABLE(1);
1156 ms
->db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples
) |
1157 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
1158 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
1159 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
1160 ms
->pa_sc_aa_config
|= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
1161 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples
)) |
1162 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
) | /* CM_R_028BE0_PA_SC_AA_CONFIG */
1163 S_028BE0_COVERED_CENTROID_IS_CENTER_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
);
1164 ms
->pa_sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
1165 if (ps_iter_samples
> 1)
1166 pipeline
->graphics
.spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1169 if (vkms
&& vkms
->pSampleMask
) {
1170 mask
= vkms
->pSampleMask
[0] & 0xffff;
1173 ms
->pa_sc_aa_mask
[0] = mask
| (mask
<< 16);
1174 ms
->pa_sc_aa_mask
[1] = mask
| (mask
<< 16);
1178 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology
)
1181 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1182 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1183 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1184 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1185 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1187 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1188 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1189 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1190 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1191 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1192 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1195 unreachable("unhandled primitive type");
1200 si_conv_gl_prim_to_gs_out(unsigned gl_prim
)
1203 case 0: /* GL_POINTS */
1204 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1205 case 1: /* GL_LINES */
1206 case 3: /* GL_LINE_STRIP */
1207 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1208 case 0x8E7A: /* GL_ISOLINES */
1209 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1211 case 4: /* GL_TRIANGLES */
1212 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1213 case 5: /* GL_TRIANGLE_STRIP */
1214 case 7: /* GL_QUADS */
1215 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1223 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology
)
1226 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1227 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1228 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1229 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1230 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1231 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1232 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1233 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1234 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1235 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1236 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1237 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1238 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1239 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1246 static unsigned radv_dynamic_state_mask(VkDynamicState state
)
1249 case VK_DYNAMIC_STATE_VIEWPORT
:
1250 case VK_DYNAMIC_STATE_VIEWPORT_WITH_COUNT_EXT
:
1251 return RADV_DYNAMIC_VIEWPORT
;
1252 case VK_DYNAMIC_STATE_SCISSOR
:
1253 case VK_DYNAMIC_STATE_SCISSOR_WITH_COUNT_EXT
:
1254 return RADV_DYNAMIC_SCISSOR
;
1255 case VK_DYNAMIC_STATE_LINE_WIDTH
:
1256 return RADV_DYNAMIC_LINE_WIDTH
;
1257 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
1258 return RADV_DYNAMIC_DEPTH_BIAS
;
1259 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
1260 return RADV_DYNAMIC_BLEND_CONSTANTS
;
1261 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
1262 return RADV_DYNAMIC_DEPTH_BOUNDS
;
1263 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
1264 return RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
1265 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
1266 return RADV_DYNAMIC_STENCIL_WRITE_MASK
;
1267 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
1268 return RADV_DYNAMIC_STENCIL_REFERENCE
;
1269 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT
:
1270 return RADV_DYNAMIC_DISCARD_RECTANGLE
;
1271 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT
:
1272 return RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1273 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
1274 return RADV_DYNAMIC_LINE_STIPPLE
;
1275 case VK_DYNAMIC_STATE_CULL_MODE_EXT
:
1276 return RADV_DYNAMIC_CULL_MODE
;
1277 case VK_DYNAMIC_STATE_FRONT_FACE_EXT
:
1278 return RADV_DYNAMIC_FRONT_FACE
;
1279 case VK_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY_EXT
:
1280 return RADV_DYNAMIC_PRIMITIVE_TOPOLOGY
;
1281 case VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT
:
1282 return RADV_DYNAMIC_DEPTH_TEST_ENABLE
;
1283 case VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT
:
1284 return RADV_DYNAMIC_DEPTH_WRITE_ENABLE
;
1285 case VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT
:
1286 return RADV_DYNAMIC_DEPTH_COMPARE_OP
;
1287 case VK_DYNAMIC_STATE_DEPTH_BOUNDS_TEST_ENABLE_EXT
:
1288 return RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE
;
1289 case VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT
:
1290 return RADV_DYNAMIC_STENCIL_TEST_ENABLE
;
1291 case VK_DYNAMIC_STATE_STENCIL_OP_EXT
:
1292 return RADV_DYNAMIC_STENCIL_OP
;
1293 case VK_DYNAMIC_STATE_VERTEX_INPUT_BINDING_STRIDE_EXT
:
1294 return RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE
;
1296 unreachable("Unhandled dynamic state");
1300 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1302 uint32_t states
= RADV_DYNAMIC_ALL
;
1304 /* If rasterization is disabled we do not care about any of the
1305 * dynamic states, since they are all rasterization related only,
1306 * except primitive topology and vertex binding stride.
1308 if (pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
1309 return RADV_DYNAMIC_PRIMITIVE_TOPOLOGY
|
1310 RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE
;
1312 if (!pCreateInfo
->pRasterizationState
->depthBiasEnable
)
1313 states
&= ~RADV_DYNAMIC_DEPTH_BIAS
;
1315 if (!pCreateInfo
->pDepthStencilState
||
1316 !pCreateInfo
->pDepthStencilState
->depthBoundsTestEnable
)
1317 states
&= ~RADV_DYNAMIC_DEPTH_BOUNDS
;
1319 if (!pCreateInfo
->pDepthStencilState
||
1320 !pCreateInfo
->pDepthStencilState
->stencilTestEnable
)
1321 states
&= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK
|
1322 RADV_DYNAMIC_STENCIL_WRITE_MASK
|
1323 RADV_DYNAMIC_STENCIL_REFERENCE
);
1325 if (!vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
))
1326 states
&= ~RADV_DYNAMIC_DISCARD_RECTANGLE
;
1328 if (!pCreateInfo
->pMultisampleState
||
1329 !vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1330 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
))
1331 states
&= ~RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1333 if (!pCreateInfo
->pRasterizationState
||
1334 !vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1335 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
))
1336 states
&= ~RADV_DYNAMIC_LINE_STIPPLE
;
1338 /* TODO: blend constants & line width. */
1345 radv_pipeline_init_dynamic_state(struct radv_pipeline
*pipeline
,
1346 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1347 const struct radv_graphics_pipeline_create_info
*extra
)
1349 uint32_t needed_states
= radv_pipeline_needed_dynamic_state(pCreateInfo
);
1350 uint32_t states
= needed_states
;
1351 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1352 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1354 pipeline
->dynamic_state
= default_dynamic_state
;
1355 pipeline
->graphics
.needed_dynamic_state
= needed_states
;
1357 if (pCreateInfo
->pDynamicState
) {
1358 /* Remove all of the states that are marked as dynamic */
1359 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1360 for (uint32_t s
= 0; s
< count
; s
++)
1361 states
&= ~radv_dynamic_state_mask(pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1364 struct radv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1366 if (needed_states
& RADV_DYNAMIC_VIEWPORT
) {
1367 assert(pCreateInfo
->pViewportState
);
1369 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1370 if (states
& RADV_DYNAMIC_VIEWPORT
) {
1371 typed_memcpy(dynamic
->viewport
.viewports
,
1372 pCreateInfo
->pViewportState
->pViewports
,
1373 pCreateInfo
->pViewportState
->viewportCount
);
1377 if (needed_states
& RADV_DYNAMIC_SCISSOR
) {
1378 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1379 if (states
& RADV_DYNAMIC_SCISSOR
) {
1380 typed_memcpy(dynamic
->scissor
.scissors
,
1381 pCreateInfo
->pViewportState
->pScissors
,
1382 pCreateInfo
->pViewportState
->scissorCount
);
1386 if (states
& RADV_DYNAMIC_LINE_WIDTH
) {
1387 assert(pCreateInfo
->pRasterizationState
);
1388 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1391 if (states
& RADV_DYNAMIC_DEPTH_BIAS
) {
1392 assert(pCreateInfo
->pRasterizationState
);
1393 dynamic
->depth_bias
.bias
=
1394 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1395 dynamic
->depth_bias
.clamp
=
1396 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1397 dynamic
->depth_bias
.slope
=
1398 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1401 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1403 * pColorBlendState is [...] NULL if the pipeline has rasterization
1404 * disabled or if the subpass of the render pass the pipeline is
1405 * created against does not use any color attachments.
1407 if (subpass
->has_color_att
&& states
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
1408 assert(pCreateInfo
->pColorBlendState
);
1409 typed_memcpy(dynamic
->blend_constants
,
1410 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1413 if (states
& RADV_DYNAMIC_CULL_MODE
) {
1414 dynamic
->cull_mode
=
1415 pCreateInfo
->pRasterizationState
->cullMode
;
1418 if (states
& RADV_DYNAMIC_FRONT_FACE
) {
1419 dynamic
->front_face
=
1420 pCreateInfo
->pRasterizationState
->frontFace
;
1423 if (states
& RADV_DYNAMIC_PRIMITIVE_TOPOLOGY
) {
1424 dynamic
->primitive_topology
=
1425 si_translate_prim(pCreateInfo
->pInputAssemblyState
->topology
);
1426 if (extra
&& extra
->use_rectlist
) {
1427 dynamic
->primitive_topology
= V_008958_DI_PT_RECTLIST
;
1431 /* If there is no depthstencil attachment, then don't read
1432 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1433 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1434 * no need to override the depthstencil defaults in
1435 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1437 * Section 9.2 of the Vulkan 1.0.15 spec says:
1439 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1440 * disabled or if the subpass of the render pass the pipeline is created
1441 * against does not use a depth/stencil attachment.
1443 if (needed_states
&& subpass
->depth_stencil_attachment
) {
1444 assert(pCreateInfo
->pDepthStencilState
);
1446 if (states
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
1447 dynamic
->depth_bounds
.min
=
1448 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1449 dynamic
->depth_bounds
.max
=
1450 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1453 if (states
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
1454 dynamic
->stencil_compare_mask
.front
=
1455 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1456 dynamic
->stencil_compare_mask
.back
=
1457 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1460 if (states
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
1461 dynamic
->stencil_write_mask
.front
=
1462 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1463 dynamic
->stencil_write_mask
.back
=
1464 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1467 if (states
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
1468 dynamic
->stencil_reference
.front
=
1469 pCreateInfo
->pDepthStencilState
->front
.reference
;
1470 dynamic
->stencil_reference
.back
=
1471 pCreateInfo
->pDepthStencilState
->back
.reference
;
1474 if (states
& RADV_DYNAMIC_DEPTH_TEST_ENABLE
) {
1475 dynamic
->depth_test_enable
=
1476 pCreateInfo
->pDepthStencilState
->depthTestEnable
;
1479 if (states
& RADV_DYNAMIC_DEPTH_WRITE_ENABLE
) {
1480 dynamic
->depth_write_enable
=
1481 pCreateInfo
->pDepthStencilState
->depthWriteEnable
;
1484 if (states
& RADV_DYNAMIC_DEPTH_COMPARE_OP
) {
1485 dynamic
->depth_compare_op
=
1486 pCreateInfo
->pDepthStencilState
->depthCompareOp
;
1489 if (states
& RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE
) {
1490 dynamic
->depth_bounds_test_enable
=
1491 pCreateInfo
->pDepthStencilState
->depthBoundsTestEnable
;
1494 if (states
& RADV_DYNAMIC_STENCIL_TEST_ENABLE
) {
1495 dynamic
->stencil_test_enable
=
1496 pCreateInfo
->pDepthStencilState
->stencilTestEnable
;
1499 if (states
& RADV_DYNAMIC_STENCIL_OP
) {
1500 dynamic
->stencil_op
.front
.compare_op
=
1501 pCreateInfo
->pDepthStencilState
->front
.compareOp
;
1502 dynamic
->stencil_op
.front
.fail_op
=
1503 pCreateInfo
->pDepthStencilState
->front
.failOp
;
1504 dynamic
->stencil_op
.front
.pass_op
=
1505 pCreateInfo
->pDepthStencilState
->front
.passOp
;
1506 dynamic
->stencil_op
.front
.depth_fail_op
=
1507 pCreateInfo
->pDepthStencilState
->front
.depthFailOp
;
1509 dynamic
->stencil_op
.back
.compare_op
=
1510 pCreateInfo
->pDepthStencilState
->back
.compareOp
;
1511 dynamic
->stencil_op
.back
.fail_op
=
1512 pCreateInfo
->pDepthStencilState
->back
.failOp
;
1513 dynamic
->stencil_op
.back
.pass_op
=
1514 pCreateInfo
->pDepthStencilState
->back
.passOp
;
1515 dynamic
->stencil_op
.back
.depth_fail_op
=
1516 pCreateInfo
->pDepthStencilState
->back
.depthFailOp
;
1520 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
1521 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
1522 if (needed_states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1523 dynamic
->discard_rectangle
.count
= discard_rectangle_info
->discardRectangleCount
;
1524 if (states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1525 typed_memcpy(dynamic
->discard_rectangle
.rectangles
,
1526 discard_rectangle_info
->pDiscardRectangles
,
1527 discard_rectangle_info
->discardRectangleCount
);
1531 if (needed_states
& RADV_DYNAMIC_SAMPLE_LOCATIONS
) {
1532 const VkPipelineSampleLocationsStateCreateInfoEXT
*sample_location_info
=
1533 vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1534 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
);
1535 /* If sampleLocationsEnable is VK_FALSE, the default sample
1536 * locations are used and the values specified in
1537 * sampleLocationsInfo are ignored.
1539 if (sample_location_info
->sampleLocationsEnable
) {
1540 const VkSampleLocationsInfoEXT
*pSampleLocationsInfo
=
1541 &sample_location_info
->sampleLocationsInfo
;
1543 assert(pSampleLocationsInfo
->sampleLocationsCount
<= MAX_SAMPLE_LOCATIONS
);
1545 dynamic
->sample_location
.per_pixel
= pSampleLocationsInfo
->sampleLocationsPerPixel
;
1546 dynamic
->sample_location
.grid_size
= pSampleLocationsInfo
->sampleLocationGridSize
;
1547 dynamic
->sample_location
.count
= pSampleLocationsInfo
->sampleLocationsCount
;
1548 typed_memcpy(&dynamic
->sample_location
.locations
[0],
1549 pSampleLocationsInfo
->pSampleLocations
,
1550 pSampleLocationsInfo
->sampleLocationsCount
);
1554 const VkPipelineRasterizationLineStateCreateInfoEXT
*rast_line_info
=
1555 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1556 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1557 if (needed_states
& RADV_DYNAMIC_LINE_STIPPLE
) {
1558 dynamic
->line_stipple
.factor
= rast_line_info
->lineStippleFactor
;
1559 dynamic
->line_stipple
.pattern
= rast_line_info
->lineStipplePattern
;
1562 if (!(states
& RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE
))
1563 pipeline
->graphics
.uses_dynamic_stride
= true;
1565 pipeline
->dynamic_state
.mask
= states
;
1569 gfx9_get_gs_info(const struct radv_pipeline_key
*key
,
1570 const struct radv_pipeline
*pipeline
,
1572 struct radv_shader_info
*infos
,
1573 struct gfx9_gs_info
*out
)
1575 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1576 struct radv_es_output_info
*es_info
;
1577 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1578 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1580 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ?
1581 &infos
[MESA_SHADER_TESS_EVAL
].tes
.es_info
:
1582 &infos
[MESA_SHADER_VERTEX
].vs
.es_info
;
1584 unsigned gs_num_invocations
= MAX2(gs_info
->gs
.invocations
, 1);
1585 bool uses_adjacency
;
1586 switch(key
->topology
) {
1587 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1588 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1589 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1590 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1591 uses_adjacency
= true;
1594 uses_adjacency
= false;
1598 /* All these are in dwords: */
1599 /* We can't allow using the whole LDS, because GS waves compete with
1600 * other shader stages for LDS space. */
1601 const unsigned max_lds_size
= 8 * 1024;
1602 const unsigned esgs_itemsize
= es_info
->esgs_itemsize
/ 4;
1603 unsigned esgs_lds_size
;
1605 /* All these are per subgroup: */
1606 const unsigned max_out_prims
= 32 * 1024;
1607 const unsigned max_es_verts
= 255;
1608 const unsigned ideal_gs_prims
= 64;
1609 unsigned max_gs_prims
, gs_prims
;
1610 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
1612 if (uses_adjacency
|| gs_num_invocations
> 1)
1613 max_gs_prims
= 127 / gs_num_invocations
;
1617 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1618 * Make sure we don't go over the maximum value.
1620 if (gs_info
->gs
.vertices_out
> 0) {
1621 max_gs_prims
= MIN2(max_gs_prims
,
1623 (gs_info
->gs
.vertices_out
* gs_num_invocations
));
1625 assert(max_gs_prims
> 0);
1627 /* If the primitive has adjacency, halve the number of vertices
1628 * that will be reused in multiple primitives.
1630 min_es_verts
= gs_info
->gs
.vertices_in
/ (uses_adjacency
? 2 : 1);
1632 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
1633 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
1635 /* Compute ESGS LDS size based on the worst case number of ES vertices
1636 * needed to create the target number of GS prims per subgroup.
1638 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1640 /* If total LDS usage is too big, refactor partitions based on ratio
1641 * of ESGS item sizes.
1643 if (esgs_lds_size
> max_lds_size
) {
1644 /* Our target GS Prims Per Subgroup was too large. Calculate
1645 * the maximum number of GS Prims Per Subgroup that will fit
1646 * into LDS, capped by the maximum that the hardware can support.
1648 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
1650 assert(gs_prims
> 0);
1651 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
1654 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1655 assert(esgs_lds_size
<= max_lds_size
);
1658 /* Now calculate remaining ESGS information. */
1660 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
1662 es_verts
= max_es_verts
;
1664 /* Vertices for adjacency primitives are not always reused, so restore
1665 * it for ES_VERTS_PER_SUBGRP.
1667 min_es_verts
= gs_info
->gs
.vertices_in
;
1669 /* For normal primitives, the VGT only checks if they are past the ES
1670 * verts per subgroup after allocating a full GS primitive and if they
1671 * are, kick off a new subgroup. But if those additional ES verts are
1672 * unique (e.g. not reused) we need to make sure there is enough LDS
1673 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1675 es_verts
-= min_es_verts
- 1;
1677 uint32_t es_verts_per_subgroup
= es_verts
;
1678 uint32_t gs_prims_per_subgroup
= gs_prims
;
1679 uint32_t gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
1680 uint32_t max_prims_per_subgroup
= gs_inst_prims_in_subgroup
* gs_info
->gs
.vertices_out
;
1681 out
->lds_size
= align(esgs_lds_size
, 128) / 128;
1682 out
->vgt_gs_onchip_cntl
= S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup
) |
1683 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup
) |
1684 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup
);
1685 out
->vgt_gs_max_prims_per_subgroup
= S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup
);
1686 out
->vgt_esgs_ring_itemsize
= esgs_itemsize
;
1687 assert(max_prims_per_subgroup
<= max_out_prims
);
1690 static void clamp_gsprims_to_esverts(unsigned *max_gsprims
, unsigned max_esverts
,
1691 unsigned min_verts_per_prim
, bool use_adjacency
)
1693 unsigned max_reuse
= max_esverts
- min_verts_per_prim
;
1696 *max_gsprims
= MIN2(*max_gsprims
, 1 + max_reuse
);
1700 radv_get_num_input_vertices(nir_shader
**nir
)
1702 if (nir
[MESA_SHADER_GEOMETRY
]) {
1703 nir_shader
*gs
= nir
[MESA_SHADER_GEOMETRY
];
1705 return gs
->info
.gs
.vertices_in
;
1708 if (nir
[MESA_SHADER_TESS_CTRL
]) {
1709 nir_shader
*tes
= nir
[MESA_SHADER_TESS_EVAL
];
1711 if (tes
->info
.tess
.point_mode
)
1713 if (tes
->info
.tess
.primitive_mode
== GL_ISOLINES
)
1722 gfx10_get_ngg_info(const struct radv_pipeline_key
*key
,
1723 struct radv_pipeline
*pipeline
,
1725 struct radv_shader_info
*infos
,
1726 struct gfx10_ngg_info
*ngg
)
1728 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1729 struct radv_es_output_info
*es_info
=
1730 nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1731 unsigned gs_type
= nir
[MESA_SHADER_GEOMETRY
] ? MESA_SHADER_GEOMETRY
: MESA_SHADER_VERTEX
;
1732 unsigned max_verts_per_prim
= radv_get_num_input_vertices(nir
);
1733 unsigned min_verts_per_prim
=
1734 gs_type
== MESA_SHADER_GEOMETRY
? max_verts_per_prim
: 1;
1735 unsigned gs_num_invocations
= nir
[MESA_SHADER_GEOMETRY
] ? MAX2(gs_info
->gs
.invocations
, 1) : 1;
1736 bool uses_adjacency
;
1737 switch(key
->topology
) {
1738 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1739 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1740 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1741 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1742 uses_adjacency
= true;
1745 uses_adjacency
= false;
1749 /* All these are in dwords: */
1750 /* We can't allow using the whole LDS, because GS waves compete with
1751 * other shader stages for LDS space.
1753 * TODO: We should really take the shader's internal LDS use into
1754 * account. The linker will fail if the size is greater than
1757 const unsigned max_lds_size
= 8 * 1024 - 768;
1758 const unsigned target_lds_size
= max_lds_size
;
1759 unsigned esvert_lds_size
= 0;
1760 unsigned gsprim_lds_size
= 0;
1762 /* All these are per subgroup: */
1763 bool max_vert_out_per_gs_instance
= false;
1764 unsigned max_esverts_base
= 256;
1765 unsigned max_gsprims_base
= 128; /* default prim group size clamp */
1767 /* Hardware has the following non-natural restrictions on the value
1768 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1770 * - at most 252 for any line input primitive type
1771 * - at most 251 for any quad input primitive type
1772 * - at most 251 for triangle strips with adjacency (this happens to
1773 * be the natural limit for triangle *lists* with adjacency)
1775 max_esverts_base
= MIN2(max_esverts_base
, 251 + max_verts_per_prim
- 1);
1777 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1778 unsigned max_out_verts_per_gsprim
=
1779 gs_info
->gs
.vertices_out
* gs_num_invocations
;
1781 if (max_out_verts_per_gsprim
<= 256) {
1782 if (max_out_verts_per_gsprim
) {
1783 max_gsprims_base
= MIN2(max_gsprims_base
,
1784 256 / max_out_verts_per_gsprim
);
1787 /* Use special multi-cycling mode in which each GS
1788 * instance gets its own subgroup. Does not work with
1790 max_vert_out_per_gs_instance
= true;
1791 max_gsprims_base
= 1;
1792 max_out_verts_per_gsprim
= gs_info
->gs
.vertices_out
;
1795 esvert_lds_size
= es_info
->esgs_itemsize
/ 4;
1796 gsprim_lds_size
= (gs_info
->gs
.gsvs_vertex_size
/ 4 + 1) * max_out_verts_per_gsprim
;
1799 /* LDS size for passing data from GS to ES. */
1800 struct radv_streamout_info
*so_info
= nir
[MESA_SHADER_TESS_CTRL
]
1801 ? &infos
[MESA_SHADER_TESS_EVAL
].so
1802 : &infos
[MESA_SHADER_VERTEX
].so
;
1804 if (so_info
->num_outputs
)
1805 esvert_lds_size
= 4 * so_info
->num_outputs
+ 1;
1807 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1808 * corresponding to the ES thread of the provoking vertex. All
1809 * ES threads load and export PrimitiveID for their thread.
1811 if (!nir
[MESA_SHADER_TESS_CTRL
] &&
1812 infos
[MESA_SHADER_VERTEX
].vs
.outinfo
.export_prim_id
)
1813 esvert_lds_size
= MAX2(esvert_lds_size
, 1);
1816 unsigned max_gsprims
= max_gsprims_base
;
1817 unsigned max_esverts
= max_esverts_base
;
1819 if (esvert_lds_size
)
1820 max_esverts
= MIN2(max_esverts
, target_lds_size
/ esvert_lds_size
);
1821 if (gsprim_lds_size
)
1822 max_gsprims
= MIN2(max_gsprims
, target_lds_size
/ gsprim_lds_size
);
1824 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1825 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
, min_verts_per_prim
, uses_adjacency
);
1826 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1828 if (esvert_lds_size
|| gsprim_lds_size
) {
1829 /* Now that we have a rough proportionality between esverts
1830 * and gsprims based on the primitive type, scale both of them
1831 * down simultaneously based on required LDS space.
1833 * We could be smarter about this if we knew how much vertex
1836 unsigned lds_total
= max_esverts
* esvert_lds_size
+
1837 max_gsprims
* gsprim_lds_size
;
1838 if (lds_total
> target_lds_size
) {
1839 max_esverts
= max_esverts
* target_lds_size
/ lds_total
;
1840 max_gsprims
= max_gsprims
* target_lds_size
/ lds_total
;
1842 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1843 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1844 min_verts_per_prim
, uses_adjacency
);
1845 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1849 /* Round up towards full wave sizes for better ALU utilization. */
1850 if (!max_vert_out_per_gs_instance
) {
1851 unsigned orig_max_esverts
;
1852 unsigned orig_max_gsprims
;
1855 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1856 wavesize
= gs_info
->wave_size
;
1858 wavesize
= nir
[MESA_SHADER_TESS_CTRL
]
1859 ? infos
[MESA_SHADER_TESS_EVAL
].wave_size
1860 : infos
[MESA_SHADER_VERTEX
].wave_size
;
1864 orig_max_esverts
= max_esverts
;
1865 orig_max_gsprims
= max_gsprims
;
1867 max_esverts
= align(max_esverts
, wavesize
);
1868 max_esverts
= MIN2(max_esverts
, max_esverts_base
);
1869 if (esvert_lds_size
)
1870 max_esverts
= MIN2(max_esverts
,
1871 (max_lds_size
- max_gsprims
* gsprim_lds_size
) /
1873 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1875 max_gsprims
= align(max_gsprims
, wavesize
);
1876 max_gsprims
= MIN2(max_gsprims
, max_gsprims_base
);
1877 if (gsprim_lds_size
)
1878 max_gsprims
= MIN2(max_gsprims
,
1879 (max_lds_size
- max_esverts
* esvert_lds_size
) /
1881 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1882 min_verts_per_prim
, uses_adjacency
);
1883 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1884 } while (orig_max_esverts
!= max_esverts
|| orig_max_gsprims
!= max_gsprims
);
1887 /* Hardware restriction: minimum value of max_esverts */
1888 max_esverts
= MAX2(max_esverts
, 23 + max_verts_per_prim
);
1890 unsigned max_out_vertices
=
1891 max_vert_out_per_gs_instance
? gs_info
->gs
.vertices_out
:
1892 gs_type
== MESA_SHADER_GEOMETRY
?
1893 max_gsprims
* gs_num_invocations
* gs_info
->gs
.vertices_out
:
1895 assert(max_out_vertices
<= 256);
1897 unsigned prim_amp_factor
= 1;
1898 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1899 /* Number of output primitives per GS input primitive after
1901 prim_amp_factor
= gs_info
->gs
.vertices_out
;
1904 /* The GE only checks against the maximum number of ES verts after
1905 * allocating a full GS primitive. So we need to ensure that whenever
1906 * this check passes, there is enough space for a full primitive without
1909 ngg
->hw_max_esverts
= max_esverts
- max_verts_per_prim
+ 1;
1910 ngg
->max_gsprims
= max_gsprims
;
1911 ngg
->max_out_verts
= max_out_vertices
;
1912 ngg
->prim_amp_factor
= prim_amp_factor
;
1913 ngg
->max_vert_out_per_gs_instance
= max_vert_out_per_gs_instance
;
1914 ngg
->ngg_emit_size
= max_gsprims
* gsprim_lds_size
;
1915 ngg
->esgs_ring_size
= 4 * max_esverts
* esvert_lds_size
;
1917 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1918 ngg
->vgt_esgs_ring_itemsize
= es_info
->esgs_itemsize
/ 4;
1920 ngg
->vgt_esgs_ring_itemsize
= 1;
1923 pipeline
->graphics
.esgs_ring_size
= ngg
->esgs_ring_size
;
1925 assert(ngg
->hw_max_esverts
>= 24); /* HW limitation */
1929 calculate_gs_ring_sizes(struct radv_pipeline
*pipeline
,
1930 const struct gfx9_gs_info
*gs
)
1932 struct radv_device
*device
= pipeline
->device
;
1933 unsigned num_se
= device
->physical_device
->rad_info
.max_se
;
1934 unsigned wave_size
= 64;
1935 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
1936 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1937 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1939 unsigned gs_vertex_reuse
=
1940 (device
->physical_device
->rad_info
.chip_class
>= GFX8
? 32 : 16) * num_se
;
1941 unsigned alignment
= 256 * num_se
;
1942 /* The maximum size is 63.999 MB per SE. */
1943 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
1944 struct radv_shader_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
1946 /* Calculate the minimum size. */
1947 unsigned min_esgs_ring_size
= align(gs
->vgt_esgs_ring_itemsize
* 4 * gs_vertex_reuse
*
1948 wave_size
, alignment
);
1949 /* These are recommended sizes, not minimum sizes. */
1950 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
1951 gs
->vgt_esgs_ring_itemsize
* 4 * gs_info
->gs
.vertices_in
;
1952 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
1953 gs_info
->gs
.max_gsvs_emit_size
;
1955 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
1956 esgs_ring_size
= align(esgs_ring_size
, alignment
);
1957 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
1959 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
1960 pipeline
->graphics
.esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
1962 pipeline
->graphics
.gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
1965 struct radv_shader_variant
*
1966 radv_get_shader(struct radv_pipeline
*pipeline
,
1967 gl_shader_stage stage
)
1969 if (stage
== MESA_SHADER_VERTEX
) {
1970 if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
1971 return pipeline
->shaders
[MESA_SHADER_VERTEX
];
1972 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
])
1973 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
1974 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1975 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1976 } else if (stage
== MESA_SHADER_TESS_EVAL
) {
1977 if (!radv_pipeline_has_tess(pipeline
))
1979 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
1980 return pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
1981 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1982 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1984 return pipeline
->shaders
[stage
];
1987 static struct radv_tessellation_state
1988 calculate_tess_state(struct radv_pipeline
*pipeline
,
1989 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1991 unsigned num_tcs_input_cp
;
1992 unsigned num_tcs_output_cp
;
1993 unsigned num_patches
;
1994 struct radv_tessellation_state tess
= {0};
1996 num_tcs_input_cp
= pCreateInfo
->pTessellationState
->patchControlPoints
;
1997 num_tcs_output_cp
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.tcs_vertices_out
; //TCS VERTICES OUT
1998 num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2000 tess
.ls_hs_config
= S_028B58_NUM_PATCHES(num_patches
) |
2001 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
2002 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
2004 struct radv_shader_variant
*tes
= radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
);
2005 unsigned type
= 0, partitioning
= 0, topology
= 0, distribution_mode
= 0;
2007 switch (tes
->info
.tes
.primitive_mode
) {
2009 type
= V_028B6C_TESS_TRIANGLE
;
2012 type
= V_028B6C_TESS_QUAD
;
2015 type
= V_028B6C_TESS_ISOLINE
;
2019 switch (tes
->info
.tes
.spacing
) {
2020 case TESS_SPACING_EQUAL
:
2021 partitioning
= V_028B6C_PART_INTEGER
;
2023 case TESS_SPACING_FRACTIONAL_ODD
:
2024 partitioning
= V_028B6C_PART_FRAC_ODD
;
2026 case TESS_SPACING_FRACTIONAL_EVEN
:
2027 partitioning
= V_028B6C_PART_FRAC_EVEN
;
2033 bool ccw
= tes
->info
.tes
.ccw
;
2034 const VkPipelineTessellationDomainOriginStateCreateInfo
*domain_origin_state
=
2035 vk_find_struct_const(pCreateInfo
->pTessellationState
,
2036 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO
);
2038 if (domain_origin_state
&& domain_origin_state
->domainOrigin
!= VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT
)
2041 if (tes
->info
.tes
.point_mode
)
2042 topology
= V_028B6C_OUTPUT_POINT
;
2043 else if (tes
->info
.tes
.primitive_mode
== GL_ISOLINES
)
2044 topology
= V_028B6C_OUTPUT_LINE
;
2046 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
2048 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
2050 if (pipeline
->device
->physical_device
->rad_info
.has_distributed_tess
) {
2051 if (pipeline
->device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
2052 pipeline
->device
->physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
2053 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
2055 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
2057 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
2059 tess
.tf_param
= S_028B6C_TYPE(type
) |
2060 S_028B6C_PARTITIONING(partitioning
) |
2061 S_028B6C_TOPOLOGY(topology
) |
2062 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
2067 static const struct radv_vs_output_info
*get_vs_output_info(const struct radv_pipeline
*pipeline
)
2069 if (radv_pipeline_has_gs(pipeline
))
2070 if (radv_pipeline_has_ngg(pipeline
))
2071 return &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.vs
.outinfo
;
2073 return &pipeline
->gs_copy_shader
->info
.vs
.outinfo
;
2074 else if (radv_pipeline_has_tess(pipeline
))
2075 return &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.outinfo
;
2077 return &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.outinfo
;
2081 radv_link_shaders(struct radv_pipeline
*pipeline
, nir_shader
**shaders
)
2083 nir_shader
* ordered_shaders
[MESA_SHADER_STAGES
];
2084 int shader_count
= 0;
2086 if(shaders
[MESA_SHADER_FRAGMENT
]) {
2087 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_FRAGMENT
];
2089 if(shaders
[MESA_SHADER_GEOMETRY
]) {
2090 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_GEOMETRY
];
2092 if(shaders
[MESA_SHADER_TESS_EVAL
]) {
2093 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_EVAL
];
2095 if(shaders
[MESA_SHADER_TESS_CTRL
]) {
2096 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_CTRL
];
2098 if(shaders
[MESA_SHADER_VERTEX
]) {
2099 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_VERTEX
];
2102 if (shader_count
> 1) {
2103 unsigned first
= ordered_shaders
[shader_count
- 1]->info
.stage
;
2104 unsigned last
= ordered_shaders
[0]->info
.stage
;
2106 if (ordered_shaders
[0]->info
.stage
== MESA_SHADER_FRAGMENT
&&
2107 ordered_shaders
[1]->info
.has_transform_feedback_varyings
)
2108 nir_link_xfb_varyings(ordered_shaders
[1], ordered_shaders
[0]);
2110 for (int i
= 0; i
< shader_count
; ++i
) {
2111 nir_variable_mode mask
= 0;
2113 if (ordered_shaders
[i
]->info
.stage
!= first
)
2114 mask
= mask
| nir_var_shader_in
;
2116 if (ordered_shaders
[i
]->info
.stage
!= last
)
2117 mask
= mask
| nir_var_shader_out
;
2119 nir_lower_io_to_scalar_early(ordered_shaders
[i
], mask
);
2120 radv_optimize_nir(ordered_shaders
[i
], false, false);
2124 for (int i
= 1; i
< shader_count
; ++i
) {
2125 nir_lower_io_arrays_to_elements(ordered_shaders
[i
],
2126 ordered_shaders
[i
- 1]);
2128 if (nir_link_opt_varyings(ordered_shaders
[i
],
2129 ordered_shaders
[i
- 1]))
2130 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2132 nir_remove_dead_variables(ordered_shaders
[i
],
2133 nir_var_shader_out
, NULL
);
2134 nir_remove_dead_variables(ordered_shaders
[i
- 1],
2135 nir_var_shader_in
, NULL
);
2137 bool progress
= nir_remove_unused_varyings(ordered_shaders
[i
],
2138 ordered_shaders
[i
- 1]);
2140 nir_compact_varyings(ordered_shaders
[i
],
2141 ordered_shaders
[i
- 1], true);
2144 if (nir_lower_global_vars_to_local(ordered_shaders
[i
])) {
2145 ac_lower_indirect_derefs(ordered_shaders
[i
],
2146 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2148 radv_optimize_nir(ordered_shaders
[i
], false, false);
2150 if (nir_lower_global_vars_to_local(ordered_shaders
[i
- 1])) {
2151 ac_lower_indirect_derefs(ordered_shaders
[i
- 1],
2152 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2154 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2160 radv_set_linked_driver_locations(struct radv_pipeline
*pipeline
, nir_shader
**shaders
,
2161 struct radv_shader_info infos
[MESA_SHADER_STAGES
])
2163 bool has_tess
= shaders
[MESA_SHADER_TESS_CTRL
];
2164 bool has_gs
= shaders
[MESA_SHADER_GEOMETRY
];
2166 if (!has_tess
&& !has_gs
)
2169 unsigned vs_info_idx
= MESA_SHADER_VERTEX
;
2170 unsigned tes_info_idx
= MESA_SHADER_TESS_EVAL
;
2172 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2173 /* These are merged into the next stage */
2174 vs_info_idx
= has_tess
? MESA_SHADER_TESS_CTRL
: MESA_SHADER_GEOMETRY
;
2175 tes_info_idx
= has_gs
? MESA_SHADER_GEOMETRY
: MESA_SHADER_TESS_EVAL
;
2179 nir_linked_io_var_info vs2tcs
=
2180 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_VERTEX
], shaders
[MESA_SHADER_TESS_CTRL
]);
2181 nir_linked_io_var_info tcs2tes
=
2182 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_TESS_CTRL
], shaders
[MESA_SHADER_TESS_EVAL
]);
2184 infos
[vs_info_idx
].vs
.num_linked_outputs
= vs2tcs
.num_linked_io_vars
;
2185 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_inputs
= vs2tcs
.num_linked_io_vars
;
2186 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_outputs
= tcs2tes
.num_linked_io_vars
;
2187 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_patch_outputs
= tcs2tes
.num_linked_patch_io_vars
;
2188 infos
[tes_info_idx
].tes
.num_linked_inputs
= tcs2tes
.num_linked_io_vars
;
2189 infos
[tes_info_idx
].tes
.num_linked_patch_inputs
= tcs2tes
.num_linked_patch_io_vars
;
2192 nir_linked_io_var_info tes2gs
=
2193 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_TESS_EVAL
], shaders
[MESA_SHADER_GEOMETRY
]);
2195 infos
[tes_info_idx
].tes
.num_linked_outputs
= tes2gs
.num_linked_io_vars
;
2196 infos
[MESA_SHADER_GEOMETRY
].gs
.num_linked_inputs
= tes2gs
.num_linked_io_vars
;
2198 } else if (has_gs
) {
2199 nir_linked_io_var_info vs2gs
=
2200 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_VERTEX
], shaders
[MESA_SHADER_GEOMETRY
]);
2202 infos
[vs_info_idx
].vs
.num_linked_outputs
= vs2gs
.num_linked_io_vars
;
2203 infos
[MESA_SHADER_GEOMETRY
].gs
.num_linked_inputs
= vs2gs
.num_linked_io_vars
;
2208 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo
*input_state
,
2209 uint32_t attrib_binding
)
2211 for (uint32_t i
= 0; i
< input_state
->vertexBindingDescriptionCount
; i
++) {
2212 const VkVertexInputBindingDescription
*input_binding
=
2213 &input_state
->pVertexBindingDescriptions
[i
];
2215 if (input_binding
->binding
== attrib_binding
)
2216 return input_binding
->stride
;
2222 static struct radv_pipeline_key
2223 radv_generate_graphics_pipeline_key(struct radv_pipeline
*pipeline
,
2224 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2225 const struct radv_blend_state
*blend
)
2227 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
2228 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
2229 const VkPipelineVertexInputStateCreateInfo
*input_state
=
2230 pCreateInfo
->pVertexInputState
;
2231 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*divisor_state
=
2232 vk_find_struct_const(input_state
->pNext
, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
2234 struct radv_pipeline_key key
;
2235 memset(&key
, 0, sizeof(key
));
2237 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
2238 key
.optimisations_disabled
= 1;
2240 key
.has_multiview_view_index
= !!subpass
->view_mask
;
2242 uint32_t binding_input_rate
= 0;
2243 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
2244 for (unsigned i
= 0; i
< input_state
->vertexBindingDescriptionCount
; ++i
) {
2245 if (input_state
->pVertexBindingDescriptions
[i
].inputRate
) {
2246 unsigned binding
= input_state
->pVertexBindingDescriptions
[i
].binding
;
2247 binding_input_rate
|= 1u << binding
;
2248 instance_rate_divisors
[binding
] = 1;
2251 if (divisor_state
) {
2252 for (unsigned i
= 0; i
< divisor_state
->vertexBindingDivisorCount
; ++i
) {
2253 instance_rate_divisors
[divisor_state
->pVertexBindingDivisors
[i
].binding
] =
2254 divisor_state
->pVertexBindingDivisors
[i
].divisor
;
2258 for (unsigned i
= 0; i
< input_state
->vertexAttributeDescriptionCount
; ++i
) {
2259 const VkVertexInputAttributeDescription
*desc
=
2260 &input_state
->pVertexAttributeDescriptions
[i
];
2261 const struct vk_format_description
*format_desc
;
2262 unsigned location
= desc
->location
;
2263 unsigned binding
= desc
->binding
;
2264 unsigned num_format
, data_format
;
2267 if (binding_input_rate
& (1u << binding
)) {
2268 key
.instance_rate_inputs
|= 1u << location
;
2269 key
.instance_rate_divisors
[location
] = instance_rate_divisors
[binding
];
2272 format_desc
= vk_format_description(desc
->format
);
2273 first_non_void
= vk_format_get_first_non_void_channel(desc
->format
);
2275 num_format
= radv_translate_buffer_numformat(format_desc
, first_non_void
);
2276 data_format
= radv_translate_buffer_dataformat(format_desc
, first_non_void
);
2278 key
.vertex_attribute_formats
[location
] = data_format
| (num_format
<< 4);
2279 key
.vertex_attribute_bindings
[location
] = desc
->binding
;
2280 key
.vertex_attribute_offsets
[location
] = desc
->offset
;
2281 key
.vertex_attribute_strides
[location
] = radv_get_attrib_stride(input_state
, desc
->binding
);
2283 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
&&
2284 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_STONEY
) {
2285 VkFormat format
= input_state
->pVertexAttributeDescriptions
[i
].format
;
2288 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2289 case VK_FORMAT_A2B10G10R10_SNORM_PACK32
:
2290 adjust
= RADV_ALPHA_ADJUST_SNORM
;
2292 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2293 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32
:
2294 adjust
= RADV_ALPHA_ADJUST_SSCALED
;
2296 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2297 case VK_FORMAT_A2B10G10R10_SINT_PACK32
:
2298 adjust
= RADV_ALPHA_ADJUST_SINT
;
2304 key
.vertex_alpha_adjust
|= adjust
<< (2 * location
);
2307 switch (desc
->format
) {
2308 case VK_FORMAT_B8G8R8A8_UNORM
:
2309 case VK_FORMAT_B8G8R8A8_SNORM
:
2310 case VK_FORMAT_B8G8R8A8_USCALED
:
2311 case VK_FORMAT_B8G8R8A8_SSCALED
:
2312 case VK_FORMAT_B8G8R8A8_UINT
:
2313 case VK_FORMAT_B8G8R8A8_SINT
:
2314 case VK_FORMAT_B8G8R8A8_SRGB
:
2315 case VK_FORMAT_A2R10G10B10_UNORM_PACK32
:
2316 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2317 case VK_FORMAT_A2R10G10B10_USCALED_PACK32
:
2318 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2319 case VK_FORMAT_A2R10G10B10_UINT_PACK32
:
2320 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2321 key
.vertex_post_shuffle
|= 1 << location
;
2328 const VkPipelineTessellationStateCreateInfo
*tess
=
2329 radv_pipeline_get_tessellation_state(pCreateInfo
);
2331 key
.tess_input_vertices
= tess
->patchControlPoints
;
2333 const VkPipelineMultisampleStateCreateInfo
*vkms
=
2334 radv_pipeline_get_multisample_state(pCreateInfo
);
2335 if (vkms
&& vkms
->rasterizationSamples
> 1) {
2336 uint32_t num_samples
= vkms
->rasterizationSamples
;
2337 uint32_t ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
);
2338 key
.num_samples
= num_samples
;
2339 key
.log2_ps_iter_samples
= util_logbase2(ps_iter_samples
);
2342 key
.col_format
= blend
->spi_shader_col_format
;
2343 key
.is_dual_src
= blend
->mrt0_is_dual_src
;
2344 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX8
) {
2345 key
.is_int8
= blend
->col_format_is_int8
;
2346 key
.is_int10
= blend
->col_format_is_int10
;
2349 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
2350 key
.topology
= pCreateInfo
->pInputAssemblyState
->topology
;
2356 radv_nir_stage_uses_xfb(const nir_shader
*nir
)
2358 nir_xfb_info
*xfb
= nir_gather_xfb_info(nir
, NULL
);
2359 bool uses_xfb
= !!xfb
;
2366 radv_fill_shader_keys(struct radv_device
*device
,
2367 struct radv_shader_variant_key
*keys
,
2368 const struct radv_pipeline_key
*key
,
2371 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_inputs
= key
->instance_rate_inputs
;
2372 keys
[MESA_SHADER_VERTEX
].vs
.alpha_adjust
= key
->vertex_alpha_adjust
;
2373 keys
[MESA_SHADER_VERTEX
].vs
.post_shuffle
= key
->vertex_post_shuffle
;
2374 for (unsigned i
= 0; i
< MAX_VERTEX_ATTRIBS
; ++i
) {
2375 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_divisors
[i
] = key
->instance_rate_divisors
[i
];
2376 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_formats
[i
] = key
->vertex_attribute_formats
[i
];
2377 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_bindings
[i
] = key
->vertex_attribute_bindings
[i
];
2378 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_offsets
[i
] = key
->vertex_attribute_offsets
[i
];
2379 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_strides
[i
] = key
->vertex_attribute_strides
[i
];
2381 keys
[MESA_SHADER_VERTEX
].vs
.outprim
= si_conv_prim_to_gs_out(key
->topology
);
2383 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2384 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ls
= true;
2385 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= 0;
2386 keys
[MESA_SHADER_TESS_CTRL
].tcs
.input_vertices
= key
->tess_input_vertices
;
2387 keys
[MESA_SHADER_TESS_CTRL
].tcs
.primitive_mode
= nir
[MESA_SHADER_TESS_EVAL
]->info
.tess
.primitive_mode
;
2389 keys
[MESA_SHADER_TESS_CTRL
].tcs
.tes_reads_tess_factors
= !!(nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
& (VARYING_BIT_TESS_LEVEL_INNER
| VARYING_BIT_TESS_LEVEL_OUTER
));
2392 if (nir
[MESA_SHADER_GEOMETRY
]) {
2393 if (nir
[MESA_SHADER_TESS_CTRL
])
2394 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_es
= true;
2396 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_es
= true;
2399 if (device
->physical_device
->use_ngg
) {
2400 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2401 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= true;
2403 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= true;
2406 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2407 nir
[MESA_SHADER_GEOMETRY
] &&
2408 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.invocations
*
2409 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.vertices_out
> 256) {
2410 /* Fallback to the legacy path if tessellation is
2411 * enabled with extreme geometry because
2412 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2415 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2418 if (!device
->physical_device
->use_ngg_gs
) {
2419 if (nir
[MESA_SHADER_GEOMETRY
]) {
2420 if (nir
[MESA_SHADER_TESS_CTRL
])
2421 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2423 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2427 gl_shader_stage last_xfb_stage
= MESA_SHADER_VERTEX
;
2429 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2434 bool uses_xfb
= nir
[last_xfb_stage
] &&
2435 radv_nir_stage_uses_xfb(nir
[last_xfb_stage
]);
2437 if (!device
->physical_device
->use_ngg_streamout
&& uses_xfb
) {
2438 if (nir
[MESA_SHADER_TESS_CTRL
])
2439 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2441 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2444 /* Determine if the pipeline is eligible for the NGG passthrough
2445 * mode. It can't be enabled for geometry shaders, for NGG
2446 * streamout or for vertex shaders that export the primitive ID
2447 * (this is checked later because we don't have the info here.)
2449 if (!nir
[MESA_SHADER_GEOMETRY
] && !uses_xfb
) {
2450 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2451 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
) {
2452 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg_passthrough
= true;
2453 } else if (nir
[MESA_SHADER_VERTEX
] &&
2454 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) {
2455 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg_passthrough
= true;
2460 for(int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
2461 keys
[i
].has_multiview_view_index
= key
->has_multiview_view_index
;
2463 keys
[MESA_SHADER_FRAGMENT
].fs
.col_format
= key
->col_format
;
2464 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int8
= key
->is_int8
;
2465 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int10
= key
->is_int10
;
2466 keys
[MESA_SHADER_FRAGMENT
].fs
.log2_ps_iter_samples
= key
->log2_ps_iter_samples
;
2467 keys
[MESA_SHADER_FRAGMENT
].fs
.num_samples
= key
->num_samples
;
2468 keys
[MESA_SHADER_FRAGMENT
].fs
.is_dual_src
= key
->is_dual_src
;
2470 if (nir
[MESA_SHADER_COMPUTE
]) {
2471 keys
[MESA_SHADER_COMPUTE
].cs
.subgroup_size
= key
->compute_subgroup_size
;
2476 radv_get_wave_size(struct radv_device
*device
,
2477 const VkPipelineShaderStageCreateInfo
*pStage
,
2478 gl_shader_stage stage
,
2479 const struct radv_shader_variant_key
*key
)
2481 if (stage
== MESA_SHADER_GEOMETRY
&& !key
->vs_common_out
.as_ngg
)
2483 else if (stage
== MESA_SHADER_COMPUTE
) {
2484 if (key
->cs
.subgroup_size
) {
2485 /* Return the required subgroup size if specified. */
2486 return key
->cs
.subgroup_size
;
2488 return device
->physical_device
->cs_wave_size
;
2490 else if (stage
== MESA_SHADER_FRAGMENT
)
2491 return device
->physical_device
->ps_wave_size
;
2493 return device
->physical_device
->ge_wave_size
;
2497 radv_get_ballot_bit_size(struct radv_device
*device
,
2498 const VkPipelineShaderStageCreateInfo
*pStage
,
2499 gl_shader_stage stage
,
2500 const struct radv_shader_variant_key
*key
)
2502 if (stage
== MESA_SHADER_COMPUTE
&& key
->cs
.subgroup_size
)
2503 return key
->cs
.subgroup_size
;
2508 radv_fill_shader_info(struct radv_pipeline
*pipeline
,
2509 const VkPipelineShaderStageCreateInfo
**pStages
,
2510 struct radv_shader_variant_key
*keys
,
2511 struct radv_shader_info
*infos
,
2514 unsigned active_stages
= 0;
2515 unsigned filled_stages
= 0;
2517 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2519 active_stages
|= (1 << i
);
2522 if (nir
[MESA_SHADER_FRAGMENT
]) {
2523 radv_nir_shader_info_init(&infos
[MESA_SHADER_FRAGMENT
]);
2524 radv_nir_shader_info_pass(nir
[MESA_SHADER_FRAGMENT
],
2526 &keys
[MESA_SHADER_FRAGMENT
],
2527 &infos
[MESA_SHADER_FRAGMENT
],
2528 pipeline
->device
->physical_device
->use_llvm
);
2530 /* TODO: These are no longer used as keys we should refactor this */
2531 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
=
2532 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2533 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_layer_id
=
2534 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2535 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_clip_dists
=
2536 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2537 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_viewport_index
=
2538 infos
[MESA_SHADER_FRAGMENT
].ps
.viewport_index_input
;
2539 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_prim_id
=
2540 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2541 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_layer_id
=
2542 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2543 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_clip_dists
=
2544 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2545 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_viewport_index
=
2546 infos
[MESA_SHADER_FRAGMENT
].ps
.viewport_index_input
;
2548 /* NGG passthrough mode can't be enabled for vertex shaders
2549 * that export the primitive ID.
2551 * TODO: I should really refactor the keys logic.
2553 if (nir
[MESA_SHADER_VERTEX
] &&
2554 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
) {
2555 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg_passthrough
= false;
2558 filled_stages
|= (1 << MESA_SHADER_FRAGMENT
);
2561 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2562 infos
[MESA_SHADER_TESS_CTRL
].tcs
.tes_inputs_read
=
2563 nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
;
2564 infos
[MESA_SHADER_TESS_CTRL
].tcs
.tes_patch_inputs_read
=
2565 nir
[MESA_SHADER_TESS_EVAL
]->info
.patch_inputs_read
;
2568 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2569 nir
[MESA_SHADER_TESS_CTRL
]) {
2570 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2571 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2572 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2574 radv_nir_shader_info_init(&infos
[MESA_SHADER_TESS_CTRL
]);
2576 for (int i
= 0; i
< 2; i
++) {
2577 radv_nir_shader_info_pass(combined_nir
[i
],
2578 pipeline
->layout
, &key
,
2579 &infos
[MESA_SHADER_TESS_CTRL
],
2580 pipeline
->device
->physical_device
->use_llvm
);
2583 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2584 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2585 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2586 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2588 filled_stages
|= (1 << MESA_SHADER_VERTEX
);
2589 filled_stages
|= (1 << MESA_SHADER_TESS_CTRL
);
2592 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2593 nir
[MESA_SHADER_GEOMETRY
]) {
2594 gl_shader_stage pre_stage
= nir
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2595 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2597 radv_nir_shader_info_init(&infos
[MESA_SHADER_GEOMETRY
]);
2599 for (int i
= 0; i
< 2; i
++) {
2600 radv_nir_shader_info_pass(combined_nir
[i
],
2603 &infos
[MESA_SHADER_GEOMETRY
],
2604 pipeline
->device
->physical_device
->use_llvm
);
2607 filled_stages
|= (1 << pre_stage
);
2608 filled_stages
|= (1 << MESA_SHADER_GEOMETRY
);
2611 active_stages
^= filled_stages
;
2612 while (active_stages
) {
2613 int i
= u_bit_scan(&active_stages
);
2615 if (i
== MESA_SHADER_TESS_CTRL
) {
2616 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
=
2617 util_last_bit64(infos
[MESA_SHADER_VERTEX
].vs
.ls_outputs_written
);
2620 if (i
== MESA_SHADER_TESS_EVAL
) {
2621 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2622 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2623 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2624 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2627 radv_nir_shader_info_init(&infos
[i
]);
2628 radv_nir_shader_info_pass(nir
[i
], pipeline
->layout
,
2629 &keys
[i
], &infos
[i
], pipeline
->device
->physical_device
->use_llvm
);
2632 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2634 infos
[i
].wave_size
=
2635 radv_get_wave_size(pipeline
->device
, pStages
[i
],
2637 infos
[i
].ballot_bit_size
=
2638 radv_get_ballot_bit_size(pipeline
->device
,
2646 merge_tess_info(struct shader_info
*tes_info
,
2647 const struct shader_info
*tcs_info
)
2649 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2651 * "PointMode. Controls generation of points rather than triangles
2652 * or lines. This functionality defaults to disabled, and is
2653 * enabled if either shader stage includes the execution mode.
2655 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2656 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2657 * and OutputVertices, it says:
2659 * "One mode must be set in at least one of the tessellation
2662 * So, the fields can be set in either the TCS or TES, but they must
2663 * agree if set in both. Our backend looks at TES, so bitwise-or in
2664 * the values from the TCS.
2666 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
2667 tes_info
->tess
.tcs_vertices_out
== 0 ||
2668 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
2669 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
2671 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2672 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2673 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
2674 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
2676 assert(tcs_info
->tess
.primitive_mode
== 0 ||
2677 tes_info
->tess
.primitive_mode
== 0 ||
2678 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
2679 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
2680 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
2681 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
2685 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT
*ext
)
2690 if (ext
->pPipelineCreationFeedback
) {
2691 ext
->pPipelineCreationFeedback
->flags
= 0;
2692 ext
->pPipelineCreationFeedback
->duration
= 0;
2695 for (unsigned i
= 0; i
< ext
->pipelineStageCreationFeedbackCount
; ++i
) {
2696 ext
->pPipelineStageCreationFeedbacks
[i
].flags
= 0;
2697 ext
->pPipelineStageCreationFeedbacks
[i
].duration
= 0;
2702 void radv_start_feedback(VkPipelineCreationFeedbackEXT
*feedback
)
2707 feedback
->duration
-= radv_get_current_time();
2708 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
2712 void radv_stop_feedback(VkPipelineCreationFeedbackEXT
*feedback
, bool cache_hit
)
2717 feedback
->duration
+= radv_get_current_time();
2718 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
|
2719 (cache_hit
? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
: 0);
2722 VkResult
radv_create_shaders(struct radv_pipeline
*pipeline
,
2723 struct radv_device
*device
,
2724 struct radv_pipeline_cache
*cache
,
2725 const struct radv_pipeline_key
*key
,
2726 const VkPipelineShaderStageCreateInfo
**pStages
,
2727 const VkPipelineCreateFlags flags
,
2728 VkPipelineCreationFeedbackEXT
*pipeline_feedback
,
2729 VkPipelineCreationFeedbackEXT
**stage_feedbacks
)
2731 struct radv_shader_module fs_m
= {0};
2732 struct radv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
2733 nir_shader
*nir
[MESA_SHADER_STAGES
] = {0};
2734 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2735 struct radv_shader_variant_key keys
[MESA_SHADER_STAGES
] = {{{{{0}}}}};
2736 struct radv_shader_info infos
[MESA_SHADER_STAGES
] = {0};
2737 unsigned char hash
[20], gs_copy_hash
[20];
2738 bool keep_executable_info
= (flags
& VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
) || device
->keep_shader_info
;
2739 bool keep_statistic_info
= (flags
& VK_PIPELINE_CREATE_CAPTURE_STATISTICS_BIT_KHR
) ||
2740 (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SHADER_STATS
) ||
2741 device
->keep_shader_info
;
2743 radv_start_feedback(pipeline_feedback
);
2745 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2747 modules
[i
] = radv_shader_module_from_handle(pStages
[i
]->module
);
2748 if (modules
[i
]->nir
)
2749 _mesa_sha1_compute(modules
[i
]->nir
->info
.name
,
2750 strlen(modules
[i
]->nir
->info
.name
),
2753 pipeline
->active_stages
|= mesa_to_vk_shader_stage(i
);
2757 radv_hash_shaders(hash
, pStages
, pipeline
->layout
, key
, get_hash_flags(device
));
2758 memcpy(gs_copy_hash
, hash
, 20);
2759 gs_copy_hash
[0] ^= 1;
2761 bool found_in_application_cache
= true;
2762 if (modules
[MESA_SHADER_GEOMETRY
] && !keep_executable_info
&& !keep_statistic_info
) {
2763 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2764 radv_create_shader_variants_from_pipeline_cache(device
, cache
, gs_copy_hash
, variants
,
2765 &found_in_application_cache
);
2766 pipeline
->gs_copy_shader
= variants
[MESA_SHADER_GEOMETRY
];
2769 if (!keep_executable_info
&& !keep_statistic_info
&&
2770 radv_create_shader_variants_from_pipeline_cache(device
, cache
, hash
, pipeline
->shaders
,
2771 &found_in_application_cache
) &&
2772 (!modules
[MESA_SHADER_GEOMETRY
] || pipeline
->gs_copy_shader
)) {
2773 radv_stop_feedback(pipeline_feedback
, found_in_application_cache
);
2777 if (flags
& VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_EXT
) {
2778 radv_stop_feedback(pipeline_feedback
, found_in_application_cache
);
2779 return VK_PIPELINE_COMPILE_REQUIRED_EXT
;
2782 if (!modules
[MESA_SHADER_FRAGMENT
] && !modules
[MESA_SHADER_COMPUTE
]) {
2784 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
2785 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "noop_fs");
2786 fs_m
.nir
= fs_b
.shader
;
2787 modules
[MESA_SHADER_FRAGMENT
] = &fs_m
;
2790 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2791 const VkPipelineShaderStageCreateInfo
*stage
= pStages
[i
];
2792 unsigned subgroup_size
= 64, ballot_bit_size
= 64;
2797 radv_start_feedback(stage_feedbacks
[i
]);
2799 if (key
->compute_subgroup_size
) {
2800 /* Only compute shaders currently support requiring a
2801 * specific subgroup size.
2803 assert(i
== MESA_SHADER_COMPUTE
);
2804 subgroup_size
= key
->compute_subgroup_size
;
2805 ballot_bit_size
= key
->compute_subgroup_size
;
2808 nir
[i
] = radv_shader_compile_to_nir(device
, modules
[i
],
2809 stage
? stage
->pName
: "main", i
,
2810 stage
? stage
->pSpecializationInfo
: NULL
,
2811 flags
, pipeline
->layout
,
2812 subgroup_size
, ballot_bit_size
);
2814 /* We don't want to alter meta shaders IR directly so clone it
2817 if (nir
[i
]->info
.name
) {
2818 nir
[i
] = nir_shader_clone(NULL
, nir
[i
]);
2821 radv_stop_feedback(stage_feedbacks
[i
], false);
2824 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2825 nir_lower_patch_vertices(nir
[MESA_SHADER_TESS_EVAL
], nir
[MESA_SHADER_TESS_CTRL
]->info
.tess
.tcs_vertices_out
, NULL
);
2826 merge_tess_info(&nir
[MESA_SHADER_TESS_EVAL
]->info
, &nir
[MESA_SHADER_TESS_CTRL
]->info
);
2829 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
2830 radv_link_shaders(pipeline
, nir
);
2832 radv_set_linked_driver_locations(pipeline
, nir
, infos
);
2834 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2836 /* do this again since information such as outputs_read can be out-of-date */
2837 nir_shader_gather_info(nir
[i
], nir_shader_get_entrypoint(nir
[i
]));
2839 if (device
->physical_device
->use_llvm
) {
2840 NIR_PASS_V(nir
[i
], nir_lower_bool_to_int32
);
2842 NIR_PASS_V(nir
[i
], nir_lower_non_uniform_access
,
2843 nir_lower_non_uniform_ubo_access
|
2844 nir_lower_non_uniform_ssbo_access
|
2845 nir_lower_non_uniform_texture_access
|
2846 nir_lower_non_uniform_image_access
);
2851 if (nir
[MESA_SHADER_FRAGMENT
])
2852 radv_lower_fs_io(nir
[MESA_SHADER_FRAGMENT
]);
2854 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2855 if (radv_can_dump_shader(device
, modules
[i
], false))
2856 nir_print_shader(nir
[i
], stderr
);
2859 radv_fill_shader_keys(device
, keys
, key
, nir
);
2861 radv_fill_shader_info(pipeline
, pStages
, keys
, infos
, nir
);
2863 if ((nir
[MESA_SHADER_VERTEX
] &&
2864 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) ||
2865 (nir
[MESA_SHADER_TESS_EVAL
] &&
2866 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
)) {
2867 struct gfx10_ngg_info
*ngg_info
;
2869 if (nir
[MESA_SHADER_GEOMETRY
])
2870 ngg_info
= &infos
[MESA_SHADER_GEOMETRY
].ngg_info
;
2871 else if (nir
[MESA_SHADER_TESS_CTRL
])
2872 ngg_info
= &infos
[MESA_SHADER_TESS_EVAL
].ngg_info
;
2874 ngg_info
= &infos
[MESA_SHADER_VERTEX
].ngg_info
;
2876 gfx10_get_ngg_info(key
, pipeline
, nir
, infos
, ngg_info
);
2877 } else if (nir
[MESA_SHADER_GEOMETRY
]) {
2878 struct gfx9_gs_info
*gs_info
=
2879 &infos
[MESA_SHADER_GEOMETRY
].gs_ring_info
;
2881 gfx9_get_gs_info(key
, pipeline
, nir
, infos
, gs_info
);
2884 if(modules
[MESA_SHADER_GEOMETRY
]) {
2885 struct radv_shader_binary
*gs_copy_binary
= NULL
;
2886 if (!pipeline
->gs_copy_shader
&&
2887 !radv_pipeline_has_ngg(pipeline
)) {
2888 struct radv_shader_info info
= {};
2889 struct radv_shader_variant_key key
= {};
2891 key
.has_multiview_view_index
=
2892 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
;
2894 radv_nir_shader_info_pass(nir
[MESA_SHADER_GEOMETRY
],
2895 pipeline
->layout
, &key
,
2896 &info
, pipeline
->device
->physical_device
->use_llvm
);
2897 info
.wave_size
= 64; /* Wave32 not supported. */
2898 info
.ballot_bit_size
= 64;
2900 pipeline
->gs_copy_shader
= radv_create_gs_copy_shader(
2901 device
, nir
[MESA_SHADER_GEOMETRY
], &info
,
2902 &gs_copy_binary
, keep_executable_info
, keep_statistic_info
,
2903 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
);
2906 if (!keep_executable_info
&& !keep_statistic_info
&& pipeline
->gs_copy_shader
) {
2907 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2908 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2910 binaries
[MESA_SHADER_GEOMETRY
] = gs_copy_binary
;
2911 variants
[MESA_SHADER_GEOMETRY
] = pipeline
->gs_copy_shader
;
2913 radv_pipeline_cache_insert_shaders(device
, cache
,
2918 free(gs_copy_binary
);
2921 if (nir
[MESA_SHADER_FRAGMENT
]) {
2922 if (!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]) {
2923 radv_start_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
]);
2925 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] =
2926 radv_shader_variant_compile(device
, modules
[MESA_SHADER_FRAGMENT
], &nir
[MESA_SHADER_FRAGMENT
], 1,
2927 pipeline
->layout
, keys
+ MESA_SHADER_FRAGMENT
,
2928 infos
+ MESA_SHADER_FRAGMENT
,
2929 keep_executable_info
, keep_statistic_info
,
2930 &binaries
[MESA_SHADER_FRAGMENT
]);
2932 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
], false);
2936 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_TESS_CTRL
]) {
2937 if (!pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]) {
2938 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2939 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2940 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2942 radv_start_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
]);
2944 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_TESS_CTRL
], combined_nir
, 2,
2946 &key
, &infos
[MESA_SHADER_TESS_CTRL
], keep_executable_info
,
2947 keep_statistic_info
, &binaries
[MESA_SHADER_TESS_CTRL
]);
2949 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
], false);
2951 modules
[MESA_SHADER_VERTEX
] = NULL
;
2952 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2953 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2956 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_GEOMETRY
]) {
2957 gl_shader_stage pre_stage
= modules
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2958 if (!pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
2959 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2961 radv_start_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
]);
2963 pipeline
->shaders
[MESA_SHADER_GEOMETRY
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_GEOMETRY
], combined_nir
, 2,
2965 &keys
[pre_stage
], &infos
[MESA_SHADER_GEOMETRY
], keep_executable_info
,
2966 keep_statistic_info
, &binaries
[MESA_SHADER_GEOMETRY
]);
2968 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
], false);
2970 modules
[pre_stage
] = NULL
;
2973 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2974 if(modules
[i
] && !pipeline
->shaders
[i
]) {
2975 if (i
== MESA_SHADER_TESS_CTRL
) {
2976 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.ls_outputs_written
);
2978 if (i
== MESA_SHADER_TESS_EVAL
) {
2979 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2980 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2983 radv_start_feedback(stage_feedbacks
[i
]);
2985 pipeline
->shaders
[i
] = radv_shader_variant_compile(device
, modules
[i
], &nir
[i
], 1,
2987 keys
+ i
, infos
+ i
, keep_executable_info
,
2988 keep_statistic_info
, &binaries
[i
]);
2990 radv_stop_feedback(stage_feedbacks
[i
], false);
2994 if (!keep_executable_info
&& !keep_statistic_info
) {
2995 radv_pipeline_cache_insert_shaders(device
, cache
, hash
, pipeline
->shaders
,
2999 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
3002 ralloc_free(nir
[i
]);
3004 if (radv_can_dump_shader_stats(device
, modules
[i
]))
3005 radv_shader_dump_stats(device
,
3006 pipeline
->shaders
[i
],
3012 ralloc_free(fs_m
.nir
);
3014 radv_stop_feedback(pipeline_feedback
, false);
3019 radv_pipeline_stage_to_user_data_0(struct radv_pipeline
*pipeline
,
3020 gl_shader_stage stage
, enum chip_class chip_class
)
3022 bool has_gs
= radv_pipeline_has_gs(pipeline
);
3023 bool has_tess
= radv_pipeline_has_tess(pipeline
);
3024 bool has_ngg
= radv_pipeline_has_ngg(pipeline
);
3027 case MESA_SHADER_FRAGMENT
:
3028 return R_00B030_SPI_SHADER_USER_DATA_PS_0
;
3029 case MESA_SHADER_VERTEX
:
3031 if (chip_class
>= GFX10
) {
3032 return R_00B430_SPI_SHADER_USER_DATA_HS_0
;
3033 } else if (chip_class
== GFX9
) {
3034 return R_00B430_SPI_SHADER_USER_DATA_LS_0
;
3036 return R_00B530_SPI_SHADER_USER_DATA_LS_0
;
3042 if (chip_class
>= GFX10
) {
3043 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3045 return R_00B330_SPI_SHADER_USER_DATA_ES_0
;
3050 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3052 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3053 case MESA_SHADER_GEOMETRY
:
3054 return chip_class
== GFX9
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
3055 R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3056 case MESA_SHADER_COMPUTE
:
3057 return R_00B900_COMPUTE_USER_DATA_0
;
3058 case MESA_SHADER_TESS_CTRL
:
3059 return chip_class
== GFX9
? R_00B430_SPI_SHADER_USER_DATA_LS_0
:
3060 R_00B430_SPI_SHADER_USER_DATA_HS_0
;
3061 case MESA_SHADER_TESS_EVAL
:
3063 return chip_class
>= GFX10
? R_00B230_SPI_SHADER_USER_DATA_GS_0
:
3064 R_00B330_SPI_SHADER_USER_DATA_ES_0
;
3065 } else if (has_ngg
) {
3066 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3068 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3071 unreachable("unknown shader");
3075 struct radv_bin_size_entry
{
3081 radv_gfx9_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3083 static const struct radv_bin_size_entry color_size_table
[][3][9] = {
3087 /* One shader engine */
3093 { UINT_MAX
, { 0, 0}},
3096 /* Two shader engines */
3102 { UINT_MAX
, { 0, 0}},
3105 /* Four shader engines */
3110 { UINT_MAX
, { 0, 0}},
3116 /* One shader engine */
3122 { UINT_MAX
, { 0, 0}},
3125 /* Two shader engines */
3131 { UINT_MAX
, { 0, 0}},
3134 /* Four shader engines */
3141 { UINT_MAX
, { 0, 0}},
3147 /* One shader engine */
3154 { UINT_MAX
, { 0, 0}},
3157 /* Two shader engines */
3165 { UINT_MAX
, { 0, 0}},
3168 /* Four shader engines */
3176 { UINT_MAX
, { 0, 0}},
3180 static const struct radv_bin_size_entry ds_size_table
[][3][9] = {
3184 // One shader engine
3191 { UINT_MAX
, { 0, 0}},
3194 // Two shader engines
3202 { UINT_MAX
, { 0, 0}},
3205 // Four shader engines
3213 { UINT_MAX
, { 0, 0}},
3219 // One shader engine
3227 { UINT_MAX
, { 0, 0}},
3230 // Two shader engines
3239 { UINT_MAX
, { 0, 0}},
3242 // Four shader engines
3251 { UINT_MAX
, { 0, 0}},
3257 // One shader engine
3265 { UINT_MAX
, { 0, 0}},
3268 // Two shader engines
3277 { UINT_MAX
, { 0, 0}},
3280 // Four shader engines
3288 { UINT_MAX
, { 0, 0}},
3293 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3294 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3295 VkExtent2D extent
= {512, 512};
3297 unsigned log_num_rb_per_se
=
3298 util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.num_render_backends
/
3299 pipeline
->device
->physical_device
->rad_info
.max_se
);
3300 unsigned log_num_se
= util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.max_se
);
3302 unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3303 unsigned ps_iter_samples
= 1u << G_028804_PS_ITER_SAMPLES(pipeline
->graphics
.ms
.db_eqaa
);
3304 unsigned effective_samples
= total_samples
;
3305 unsigned color_bytes_per_pixel
= 0;
3307 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3308 radv_pipeline_get_color_blend_state(pCreateInfo
);
3310 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3311 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3314 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3317 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3318 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3321 /* MSAA images typically don't use all samples all the time. */
3322 if (effective_samples
>= 2 && ps_iter_samples
<= 1)
3323 effective_samples
= 2;
3324 color_bytes_per_pixel
*= effective_samples
;
3327 const struct radv_bin_size_entry
*color_entry
= color_size_table
[log_num_rb_per_se
][log_num_se
];
3328 while(color_entry
[1].bpp
<= color_bytes_per_pixel
)
3331 extent
= color_entry
->extent
;
3333 if (subpass
->depth_stencil_attachment
) {
3334 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3336 /* Coefficients taken from AMDVLK */
3337 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3338 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3339 unsigned ds_bytes_per_pixel
= 4 * (depth_coeff
+ stencil_coeff
) * total_samples
;
3341 const struct radv_bin_size_entry
*ds_entry
= ds_size_table
[log_num_rb_per_se
][log_num_se
];
3342 while(ds_entry
[1].bpp
<= ds_bytes_per_pixel
)
3345 if (ds_entry
->extent
.width
* ds_entry
->extent
.height
< extent
.width
* extent
.height
)
3346 extent
= ds_entry
->extent
;
3353 radv_gfx10_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3355 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3356 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3357 VkExtent2D extent
= {512, 512};
3359 const unsigned db_tag_size
= 64;
3360 const unsigned db_tag_count
= 312;
3361 const unsigned color_tag_size
= 1024;
3362 const unsigned color_tag_count
= 31;
3363 const unsigned fmask_tag_size
= 256;
3364 const unsigned fmask_tag_count
= 44;
3366 const unsigned rb_count
= pipeline
->device
->physical_device
->rad_info
.num_render_backends
;
3367 const unsigned pipe_count
= MAX2(rb_count
, pipeline
->device
->physical_device
->rad_info
.num_sdp_interfaces
);
3369 const unsigned db_tag_part
= (db_tag_count
* rb_count
/ pipe_count
) * db_tag_size
* pipe_count
;
3370 const unsigned color_tag_part
= (color_tag_count
* rb_count
/ pipe_count
) * color_tag_size
* pipe_count
;
3371 const unsigned fmask_tag_part
= (fmask_tag_count
* rb_count
/ pipe_count
) * fmask_tag_size
* pipe_count
;
3373 const unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3374 const unsigned samples_log
= util_logbase2_ceil(total_samples
);
3376 unsigned color_bytes_per_pixel
= 0;
3377 unsigned fmask_bytes_per_pixel
= 0;
3379 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3380 radv_pipeline_get_color_blend_state(pCreateInfo
);
3382 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3383 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3386 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3389 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3390 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3392 if (total_samples
> 1) {
3393 assert(samples_log
<= 3);
3394 const unsigned fmask_array
[] = {0, 1, 1, 4};
3395 fmask_bytes_per_pixel
+= fmask_array
[samples_log
];
3399 color_bytes_per_pixel
*= total_samples
;
3401 color_bytes_per_pixel
= MAX2(color_bytes_per_pixel
, 1);
3403 const unsigned color_pixel_count_log
= util_logbase2(color_tag_part
/ color_bytes_per_pixel
);
3404 extent
.width
= 1ull << ((color_pixel_count_log
+ 1) / 2);
3405 extent
.height
= 1ull << (color_pixel_count_log
/ 2);
3407 if (fmask_bytes_per_pixel
) {
3408 const unsigned fmask_pixel_count_log
= util_logbase2(fmask_tag_part
/ fmask_bytes_per_pixel
);
3410 const VkExtent2D fmask_extent
= (VkExtent2D
){
3411 .width
= 1ull << ((fmask_pixel_count_log
+ 1) / 2),
3412 .height
= 1ull << (color_pixel_count_log
/ 2)
3415 if (fmask_extent
.width
* fmask_extent
.height
< extent
.width
* extent
.height
)
3416 extent
= fmask_extent
;
3419 if (subpass
->depth_stencil_attachment
) {
3420 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3422 /* Coefficients taken from AMDVLK */
3423 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3424 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3425 unsigned db_bytes_per_pixel
= (depth_coeff
+ stencil_coeff
) * total_samples
;
3427 const unsigned db_pixel_count_log
= util_logbase2(db_tag_part
/ db_bytes_per_pixel
);
3429 const VkExtent2D db_extent
= (VkExtent2D
){
3430 .width
= 1ull << ((db_pixel_count_log
+ 1) / 2),
3431 .height
= 1ull << (color_pixel_count_log
/ 2)
3434 if (db_extent
.width
* db_extent
.height
< extent
.width
* extent
.height
)
3438 extent
.width
= MAX2(extent
.width
, 128);
3439 extent
.height
= MAX2(extent
.width
, 64);
3445 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3446 struct radv_pipeline
*pipeline
,
3447 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3449 uint32_t pa_sc_binner_cntl_0
=
3450 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC
) |
3451 S_028C44_DISABLE_START_OF_PRIM(1);
3452 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3454 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3455 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3456 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3457 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3458 radv_pipeline_get_color_blend_state(pCreateInfo
);
3459 unsigned min_bytes_per_pixel
= 0;
3462 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3463 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3466 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3469 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3470 unsigned bytes
= vk_format_get_blocksize(format
);
3471 if (!min_bytes_per_pixel
|| bytes
< min_bytes_per_pixel
)
3472 min_bytes_per_pixel
= bytes
;
3476 pa_sc_binner_cntl_0
=
3477 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC
) |
3478 S_028C44_BIN_SIZE_X(0) |
3479 S_028C44_BIN_SIZE_Y(0) |
3480 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3481 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel
<= 4 ? 2 : 1) | /* 128 or 64 */
3482 S_028C44_DISABLE_START_OF_PRIM(1);
3485 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3486 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3489 struct radv_binning_settings
3490 radv_get_binning_settings(const struct radv_physical_device
*pdev
)
3492 struct radv_binning_settings settings
;
3493 if (pdev
->rad_info
.has_dedicated_vram
) {
3494 if (pdev
->rad_info
.num_render_backends
> 4) {
3495 settings
.context_states_per_bin
= 1;
3496 settings
.persistent_states_per_bin
= 1;
3498 settings
.context_states_per_bin
= 3;
3499 settings
.persistent_states_per_bin
= 8;
3501 settings
.fpovs_per_batch
= 63;
3503 /* The context states are affected by the scissor bug. */
3504 settings
.context_states_per_bin
= 6;
3505 /* 32 causes hangs for RAVEN. */
3506 settings
.persistent_states_per_bin
= 16;
3507 settings
.fpovs_per_batch
= 63;
3510 if (pdev
->rad_info
.has_gfx9_scissor_bug
)
3511 settings
.context_states_per_bin
= 1;
3517 radv_pipeline_generate_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3518 struct radv_pipeline
*pipeline
,
3519 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3520 const struct radv_blend_state
*blend
)
3522 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
3525 VkExtent2D bin_size
;
3526 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3527 bin_size
= radv_gfx10_compute_bin_size(pipeline
, pCreateInfo
);
3528 } else if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3529 bin_size
= radv_gfx9_compute_bin_size(pipeline
, pCreateInfo
);
3531 unreachable("Unhandled generation for binning bin size calculation");
3533 if (pipeline
->device
->pbb_allowed
&& bin_size
.width
&& bin_size
.height
) {
3534 struct radv_binning_settings settings
=
3535 radv_get_binning_settings(pipeline
->device
->physical_device
);
3537 bool disable_start_of_prim
= true;
3538 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3540 const struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3542 if (pipeline
->device
->dfsm_allowed
&& ps
&&
3543 !ps
->info
.ps
.can_discard
&&
3544 !ps
->info
.ps
.writes_memory
&&
3545 blend
->cb_target_enabled_4bit
) {
3546 db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_AUTO
);
3547 disable_start_of_prim
= (blend
->blend_enable_4bit
& blend
->cb_target_enabled_4bit
) != 0;
3550 const uint32_t pa_sc_binner_cntl_0
=
3551 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED
) |
3552 S_028C44_BIN_SIZE_X(bin_size
.width
== 16) |
3553 S_028C44_BIN_SIZE_Y(bin_size
.height
== 16) |
3554 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size
.width
, 32)) - 5) |
3555 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size
.height
, 32)) - 5) |
3556 S_028C44_CONTEXT_STATES_PER_BIN(settings
.context_states_per_bin
- 1) |
3557 S_028C44_PERSISTENT_STATES_PER_BIN(settings
.persistent_states_per_bin
- 1) |
3558 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim
) |
3559 S_028C44_FPOVS_PER_BATCH(settings
.fpovs_per_batch
) |
3560 S_028C44_OPTIMAL_BIN_SELECTION(1);
3562 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3563 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3565 radv_pipeline_generate_disabled_binning_state(ctx_cs
, pipeline
, pCreateInfo
);
3570 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf
*ctx_cs
,
3571 struct radv_pipeline
*pipeline
,
3572 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3573 const struct radv_graphics_pipeline_create_info
*extra
)
3575 const VkPipelineDepthStencilStateCreateInfo
*vkds
= radv_pipeline_get_depth_stencil_state(pCreateInfo
);
3576 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3577 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3578 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3579 struct radv_render_pass_attachment
*attachment
= NULL
;
3580 uint32_t db_depth_control
= 0;
3581 uint32_t db_render_control
= 0, db_render_override2
= 0;
3582 uint32_t db_render_override
= 0;
3584 if (subpass
->depth_stencil_attachment
)
3585 attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3587 bool has_depth_attachment
= attachment
&& vk_format_is_depth(attachment
->format
);
3588 bool has_stencil_attachment
= attachment
&& vk_format_is_stencil(attachment
->format
);
3590 if (vkds
&& has_depth_attachment
) {
3591 db_depth_control
= S_028800_Z_ENABLE(vkds
->depthTestEnable
? 1 : 0) |
3592 S_028800_Z_WRITE_ENABLE(vkds
->depthWriteEnable
? 1 : 0) |
3593 S_028800_ZFUNC(vkds
->depthCompareOp
) |
3594 S_028800_DEPTH_BOUNDS_ENABLE(vkds
->depthBoundsTestEnable
? 1 : 0);
3596 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3597 db_render_override2
|= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment
->samples
> 2);
3599 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
)
3600 db_render_override2
|= S_028010_CENTROID_COMPUTATION_MODE_GFX103(2);
3603 if (has_stencil_attachment
&& vkds
&& vkds
->stencilTestEnable
) {
3604 db_depth_control
|= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3605 db_depth_control
|= S_028800_STENCILFUNC(vkds
->front
.compareOp
);
3607 db_depth_control
|= S_028800_STENCILFUNC_BF(vkds
->back
.compareOp
);
3610 if (attachment
&& extra
) {
3611 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(extra
->db_depth_clear
);
3612 db_render_control
|= S_028000_STENCIL_CLEAR_ENABLE(extra
->db_stencil_clear
);
3614 db_render_control
|= S_028000_RESUMMARIZE_ENABLE(extra
->resummarize_enable
);
3615 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(extra
->depth_compress_disable
);
3616 db_render_control
|= S_028000_STENCIL_COMPRESS_DISABLE(extra
->stencil_compress_disable
);
3617 db_render_override2
|= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra
->db_depth_disable_expclear
);
3618 db_render_override2
|= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra
->db_stencil_disable_expclear
);
3621 db_render_override
|= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
3622 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
3624 if (!pCreateInfo
->pRasterizationState
->depthClampEnable
&&
3625 ps
->info
.ps
.writes_z
) {
3626 /* From VK_EXT_depth_range_unrestricted spec:
3628 * "The behavior described in Primitive Clipping still applies.
3629 * If depth clamping is disabled the depth values are still
3630 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3631 * depth clamping is enabled the above equation is ignored and
3632 * the depth values are instead clamped to the VkViewport
3633 * minDepth and maxDepth values, which in the case of this
3634 * extension can be outside of the 0.0 to 1.0 range."
3636 db_render_override
|= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3639 radeon_set_context_reg(ctx_cs
, R_028000_DB_RENDER_CONTROL
, db_render_control
);
3640 radeon_set_context_reg(ctx_cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
3641 radeon_set_context_reg(ctx_cs
, R_028010_DB_RENDER_OVERRIDE2
, db_render_override2
);
3643 pipeline
->graphics
.db_depth_control
= db_depth_control
;
3647 radv_pipeline_generate_blend_state(struct radeon_cmdbuf
*ctx_cs
,
3648 struct radv_pipeline
*pipeline
,
3649 const struct radv_blend_state
*blend
)
3651 radeon_set_context_reg_seq(ctx_cs
, R_028780_CB_BLEND0_CONTROL
, 8);
3652 radeon_emit_array(ctx_cs
, blend
->cb_blend_control
,
3654 radeon_set_context_reg(ctx_cs
, R_028808_CB_COLOR_CONTROL
, blend
->cb_color_control
);
3655 radeon_set_context_reg(ctx_cs
, R_028B70_DB_ALPHA_TO_MASK
, blend
->db_alpha_to_mask
);
3657 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
3659 radeon_set_context_reg_seq(ctx_cs
, R_028760_SX_MRT0_BLEND_OPT
, 8);
3660 radeon_emit_array(ctx_cs
, blend
->sx_mrt_blend_opt
, 8);
3663 radeon_set_context_reg(ctx_cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
3665 radeon_set_context_reg(ctx_cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
3666 radeon_set_context_reg(ctx_cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
3668 pipeline
->graphics
.col_format
= blend
->spi_shader_col_format
;
3669 pipeline
->graphics
.cb_target_mask
= blend
->cb_target_mask
;
3672 static const VkConservativeRasterizationModeEXT
3673 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo
*pCreateInfo
)
3675 const VkPipelineRasterizationConservativeStateCreateInfoEXT
*conservative_raster
=
3676 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT
);
3678 if (!conservative_raster
)
3679 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
;
3680 return conservative_raster
->conservativeRasterizationMode
;
3684 radv_pipeline_generate_raster_state(struct radeon_cmdbuf
*ctx_cs
,
3685 struct radv_pipeline
*pipeline
,
3686 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3688 const VkPipelineRasterizationStateCreateInfo
*vkraster
= pCreateInfo
->pRasterizationState
;
3689 const VkConservativeRasterizationModeEXT mode
=
3690 radv_get_conservative_raster_mode(vkraster
);
3691 uint32_t pa_sc_conservative_rast
= S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3692 bool depth_clip_disable
= vkraster
->depthClampEnable
;
3694 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*depth_clip_state
=
3695 vk_find_struct_const(vkraster
->pNext
, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
3696 if (depth_clip_state
) {
3697 depth_clip_disable
= !depth_clip_state
->depthClipEnable
;
3700 radeon_set_context_reg(ctx_cs
, R_028810_PA_CL_CLIP_CNTL
,
3701 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3702 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable
? 1 : 0) |
3703 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable
? 1 : 0) |
3704 S_028810_DX_RASTERIZATION_KILL(vkraster
->rasterizerDiscardEnable
? 1 : 0) |
3705 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3707 pipeline
->graphics
.pa_su_sc_mode_cntl
=
3708 S_028814_FACE(vkraster
->frontFace
) |
3709 S_028814_CULL_FRONT(!!(vkraster
->cullMode
& VK_CULL_MODE_FRONT_BIT
)) |
3710 S_028814_CULL_BACK(!!(vkraster
->cullMode
& VK_CULL_MODE_BACK_BIT
)) |
3711 S_028814_POLY_MODE(vkraster
->polygonMode
!= VK_POLYGON_MODE_FILL
) |
3712 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3713 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3714 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3715 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3716 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster
->depthBiasEnable
? 1 : 0);
3718 radeon_set_context_reg(ctx_cs
, R_028BDC_PA_SC_LINE_CNTL
,
3719 S_028BDC_DX10_DIAMOND_TEST_ENA(1));
3721 /* Conservative rasterization. */
3722 if (mode
!= VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
) {
3723 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3725 ms
->pa_sc_aa_config
|= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3726 ms
->db_eqaa
|= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3727 S_028804_OVERRASTERIZATION_AMOUNT(4);
3729 pa_sc_conservative_rast
= S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3730 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3731 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3733 if (mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT
) {
3734 pa_sc_conservative_rast
|=
3735 S_028C4C_OVER_RAST_ENABLE(1) |
3736 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3737 S_028C4C_UNDER_RAST_ENABLE(0) |
3738 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3739 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3741 assert(mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT
);
3742 pa_sc_conservative_rast
|=
3743 S_028C4C_OVER_RAST_ENABLE(0) |
3744 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3745 S_028C4C_UNDER_RAST_ENABLE(1) |
3746 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3747 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3751 radeon_set_context_reg(ctx_cs
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
3752 pa_sc_conservative_rast
);
3757 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf
*ctx_cs
,
3758 struct radv_pipeline
*pipeline
)
3760 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3762 radeon_set_context_reg_seq(ctx_cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
3763 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[0]);
3764 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[1]);
3766 radeon_set_context_reg(ctx_cs
, R_028804_DB_EQAA
, ms
->db_eqaa
);
3767 radeon_set_context_reg(ctx_cs
, R_028A48_PA_SC_MODE_CNTL_0
, ms
->pa_sc_mode_cntl_0
);
3768 radeon_set_context_reg(ctx_cs
, R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
3769 radeon_set_context_reg(ctx_cs
, R_028BE0_PA_SC_AA_CONFIG
, ms
->pa_sc_aa_config
);
3771 /* The exclusion bits can be set to improve rasterization efficiency
3772 * if no sample lies on the pixel boundary (-8 sample offset). It's
3773 * currently always TRUE because the driver doesn't support 16 samples.
3775 bool exclusion
= pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
3776 radeon_set_context_reg(ctx_cs
, R_02882C_PA_SU_PRIM_FILTER_CNTL
,
3777 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) |
3778 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3780 /* GFX9: Flush DFSM when the AA mode changes. */
3781 if (pipeline
->device
->dfsm_allowed
) {
3782 radeon_emit(ctx_cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3783 radeon_emit(ctx_cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3788 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf
*ctx_cs
,
3789 struct radv_pipeline
*pipeline
)
3791 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3792 const struct radv_shader_variant
*vs
=
3793 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] ?
3794 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] :
3795 pipeline
->shaders
[MESA_SHADER_VERTEX
];
3796 unsigned vgt_primitiveid_en
= 0;
3797 uint32_t vgt_gs_mode
= 0;
3799 if (radv_pipeline_has_ngg(pipeline
))
3802 if (radv_pipeline_has_gs(pipeline
)) {
3803 const struct radv_shader_variant
*gs
=
3804 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3806 vgt_gs_mode
= ac_vgt_gs_mode(gs
->info
.gs
.vertices_out
,
3807 pipeline
->device
->physical_device
->rad_info
.chip_class
);
3808 } else if (outinfo
->export_prim_id
|| vs
->info
.uses_prim_id
) {
3809 vgt_gs_mode
= S_028A40_MODE(V_028A40_GS_SCENARIO_A
);
3810 vgt_primitiveid_en
|= S_028A84_PRIMITIVEID_EN(1);
3813 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
, vgt_primitiveid_en
);
3814 radeon_set_context_reg(ctx_cs
, R_028A40_VGT_GS_MODE
, vgt_gs_mode
);
3818 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf
*ctx_cs
,
3819 struct radeon_cmdbuf
*cs
,
3820 struct radv_pipeline
*pipeline
,
3821 struct radv_shader_variant
*shader
)
3823 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3825 radeon_set_sh_reg_seq(cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
3826 radeon_emit(cs
, va
>> 8);
3827 radeon_emit(cs
, S_00B124_MEM_BASE(va
>> 40));
3828 radeon_emit(cs
, shader
->config
.rsrc1
);
3829 radeon_emit(cs
, shader
->config
.rsrc2
);
3831 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3832 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3833 clip_dist_mask
= outinfo
->clip_dist_mask
;
3834 cull_dist_mask
= outinfo
->cull_dist_mask
;
3835 total_mask
= clip_dist_mask
| cull_dist_mask
;
3836 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3837 outinfo
->writes_layer
||
3838 outinfo
->writes_viewport_index
;
3839 unsigned spi_vs_out_config
, nparams
;
3841 /* VS is required to export at least one param. */
3842 nparams
= MAX2(outinfo
->param_exports
, 1);
3843 spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
3845 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3846 spi_vs_out_config
|= S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0);
3849 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
, spi_vs_out_config
);
3851 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3852 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3853 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3854 V_02870C_SPI_SHADER_4COMP
:
3855 V_02870C_SPI_SHADER_NONE
) |
3856 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3857 V_02870C_SPI_SHADER_4COMP
:
3858 V_02870C_SPI_SHADER_NONE
) |
3859 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3860 V_02870C_SPI_SHADER_4COMP
:
3861 V_02870C_SPI_SHADER_NONE
));
3863 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3864 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3865 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3866 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3867 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3868 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3869 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3870 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3871 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
) |
3872 cull_dist_mask
<< 8 |
3875 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
3876 radeon_set_context_reg(ctx_cs
, R_028AB4_VGT_REUSE_OFF
,
3877 outinfo
->writes_viewport_index
);
3881 radv_pipeline_generate_hw_es(struct radeon_cmdbuf
*cs
,
3882 struct radv_pipeline
*pipeline
,
3883 struct radv_shader_variant
*shader
)
3885 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3887 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
3888 radeon_emit(cs
, va
>> 8);
3889 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3890 radeon_emit(cs
, shader
->config
.rsrc1
);
3891 radeon_emit(cs
, shader
->config
.rsrc2
);
3895 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf
*cs
,
3896 struct radv_pipeline
*pipeline
,
3897 struct radv_shader_variant
*shader
)
3899 unsigned num_lds_blocks
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_lds_blocks
;
3900 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3901 uint32_t rsrc2
= shader
->config
.rsrc2
;
3903 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
3904 radeon_emit(cs
, va
>> 8);
3905 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
3907 rsrc2
|= S_00B52C_LDS_SIZE(num_lds_blocks
);
3908 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX7
&&
3909 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
3910 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
3912 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
3913 radeon_emit(cs
, shader
->config
.rsrc1
);
3914 radeon_emit(cs
, rsrc2
);
3918 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf
*ctx_cs
,
3919 struct radeon_cmdbuf
*cs
,
3920 struct radv_pipeline
*pipeline
,
3921 struct radv_shader_variant
*shader
)
3923 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3924 gl_shader_stage es_type
=
3925 radv_pipeline_has_tess(pipeline
) ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
3926 struct radv_shader_variant
*es
=
3927 es_type
== MESA_SHADER_TESS_EVAL
? pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] : pipeline
->shaders
[MESA_SHADER_VERTEX
];
3928 const struct gfx10_ngg_info
*ngg_state
= &shader
->info
.ngg_info
;
3930 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
3931 radeon_emit(cs
, va
>> 8);
3932 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3933 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
3934 radeon_emit(cs
, shader
->config
.rsrc1
);
3935 radeon_emit(cs
, shader
->config
.rsrc2
);
3937 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3938 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3939 clip_dist_mask
= outinfo
->clip_dist_mask
;
3940 cull_dist_mask
= outinfo
->cull_dist_mask
;
3941 total_mask
= clip_dist_mask
| cull_dist_mask
;
3942 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3943 outinfo
->writes_layer
||
3944 outinfo
->writes_viewport_index
;
3945 bool es_enable_prim_id
= outinfo
->export_prim_id
||
3946 (es
&& es
->info
.uses_prim_id
);
3947 bool break_wave_at_eoi
= false;
3951 if (es_type
== MESA_SHADER_TESS_EVAL
) {
3952 struct radv_shader_variant
*gs
=
3953 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3955 if (es_enable_prim_id
|| (gs
&& gs
->info
.uses_prim_id
))
3956 break_wave_at_eoi
= true;
3959 nparams
= MAX2(outinfo
->param_exports
, 1);
3960 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
3961 S_0286C4_VS_EXPORT_COUNT(nparams
- 1) |
3962 S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0));
3964 radeon_set_context_reg(ctx_cs
, R_028708_SPI_SHADER_IDX_FORMAT
,
3965 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP
));
3966 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3967 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3968 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3969 V_02870C_SPI_SHADER_4COMP
:
3970 V_02870C_SPI_SHADER_NONE
) |
3971 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3972 V_02870C_SPI_SHADER_4COMP
:
3973 V_02870C_SPI_SHADER_NONE
) |
3974 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3975 V_02870C_SPI_SHADER_4COMP
:
3976 V_02870C_SPI_SHADER_NONE
));
3978 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3979 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3980 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3981 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3982 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3983 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3984 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3985 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3986 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
) |
3987 cull_dist_mask
<< 8 |
3990 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
,
3991 S_028A84_PRIMITIVEID_EN(es_enable_prim_id
) |
3992 S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo
->export_prim_id
));
3994 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
3995 ngg_state
->vgt_esgs_ring_itemsize
);
3997 /* NGG specific registers. */
3998 struct radv_shader_variant
*gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3999 uint32_t gs_num_invocations
= gs
? gs
->info
.gs
.invocations
: 1;
4001 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4002 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state
->hw_max_esverts
) |
4003 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state
->max_gsprims
) |
4004 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state
->max_gsprims
* gs_num_invocations
));
4005 radeon_set_context_reg(ctx_cs
, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP
,
4006 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state
->max_out_verts
));
4007 radeon_set_context_reg(ctx_cs
, R_028B4C_GE_NGG_SUBGRP_CNTL
,
4008 S_028B4C_PRIM_AMP_FACTOR(ngg_state
->prim_amp_factor
) |
4009 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
4010 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
4011 S_028B90_CNT(gs_num_invocations
) |
4012 S_028B90_ENABLE(gs_num_invocations
> 1) |
4013 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state
->max_vert_out_per_gs_instance
));
4015 /* User edge flags are set by the pos exports. If user edge flags are
4016 * not used, we must use hw-generated edge flags and pass them via
4017 * the prim export to prevent drawing lines on internal edges of
4018 * decomposed primitives (such as quads) with polygon mode = lines.
4020 * TODO: We should combine hw-generated edge flags with user edge
4021 * flags in the shader.
4023 radeon_set_context_reg(ctx_cs
, R_028838_PA_CL_NGG_CNTL
,
4024 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline
) &&
4025 !radv_pipeline_has_gs(pipeline
)) |
4026 /* Reuse for NGG. */
4027 S_028838_VERTEX_REUSE_DEPTH_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
? 30 : 0));
4029 ge_cntl
= S_03096C_PRIM_GRP_SIZE(ngg_state
->max_gsprims
) |
4030 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
4031 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
);
4033 /* Bug workaround for a possible hang with non-tessellation cases.
4034 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
4036 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
4038 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX10
&&
4039 !radv_pipeline_has_tess(pipeline
) &&
4040 ngg_state
->hw_max_esverts
!= 256) {
4041 ge_cntl
&= C_03096C_VERT_GRP_SIZE
;
4043 if (ngg_state
->hw_max_esverts
> 5) {
4044 ge_cntl
|= S_03096C_VERT_GRP_SIZE(ngg_state
->hw_max_esverts
- 5);
4048 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
, ge_cntl
);
4052 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf
*cs
,
4053 struct radv_pipeline
*pipeline
,
4054 struct radv_shader_variant
*shader
)
4056 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
4058 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4059 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4060 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
4061 radeon_emit(cs
, va
>> 8);
4062 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
4064 radeon_set_sh_reg_seq(cs
, R_00B410_SPI_SHADER_PGM_LO_LS
, 2);
4065 radeon_emit(cs
, va
>> 8);
4066 radeon_emit(cs
, S_00B414_MEM_BASE(va
>> 40));
4069 radeon_set_sh_reg_seq(cs
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
, 2);
4070 radeon_emit(cs
, shader
->config
.rsrc1
);
4071 radeon_emit(cs
, shader
->config
.rsrc2
);
4073 radeon_set_sh_reg_seq(cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
4074 radeon_emit(cs
, va
>> 8);
4075 radeon_emit(cs
, S_00B424_MEM_BASE(va
>> 40));
4076 radeon_emit(cs
, shader
->config
.rsrc1
);
4077 radeon_emit(cs
, shader
->config
.rsrc2
);
4082 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf
*ctx_cs
,
4083 struct radeon_cmdbuf
*cs
,
4084 struct radv_pipeline
*pipeline
)
4086 struct radv_shader_variant
*vs
;
4088 /* Skip shaders merged into HS/GS */
4089 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
4093 if (vs
->info
.vs
.as_ls
)
4094 radv_pipeline_generate_hw_ls(cs
, pipeline
, vs
);
4095 else if (vs
->info
.vs
.as_es
)
4096 radv_pipeline_generate_hw_es(cs
, pipeline
, vs
);
4097 else if (vs
->info
.is_ngg
)
4098 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, vs
);
4100 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, vs
);
4104 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf
*ctx_cs
,
4105 struct radeon_cmdbuf
*cs
,
4106 struct radv_pipeline
*pipeline
,
4107 const struct radv_tessellation_state
*tess
)
4109 if (!radv_pipeline_has_tess(pipeline
))
4112 struct radv_shader_variant
*tes
, *tcs
;
4114 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
4115 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
4118 if (tes
->info
.is_ngg
) {
4119 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, tes
);
4120 } else if (tes
->info
.tes
.as_es
)
4121 radv_pipeline_generate_hw_es(cs
, pipeline
, tes
);
4123 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, tes
);
4126 radv_pipeline_generate_hw_hs(cs
, pipeline
, tcs
);
4128 radeon_set_context_reg(ctx_cs
, R_028B6C_VGT_TF_PARAM
,
4131 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
)
4132 radeon_set_context_reg_idx(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
4133 tess
->ls_hs_config
);
4135 radeon_set_context_reg(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
,
4136 tess
->ls_hs_config
);
4138 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
4139 !radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
4140 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4141 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4142 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4143 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4148 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf
*ctx_cs
,
4149 struct radeon_cmdbuf
*cs
,
4150 struct radv_pipeline
*pipeline
,
4151 struct radv_shader_variant
*gs
)
4153 const struct gfx9_gs_info
*gs_state
= &gs
->info
.gs_ring_info
;
4154 unsigned gs_max_out_vertices
;
4155 uint8_t *num_components
;
4160 gs_max_out_vertices
= gs
->info
.gs
.vertices_out
;
4161 max_stream
= gs
->info
.gs
.max_stream
;
4162 num_components
= gs
->info
.gs
.num_stream_output_components
;
4164 offset
= num_components
[0] * gs_max_out_vertices
;
4166 radeon_set_context_reg_seq(ctx_cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
4167 radeon_emit(ctx_cs
, offset
);
4168 if (max_stream
>= 1)
4169 offset
+= num_components
[1] * gs_max_out_vertices
;
4170 radeon_emit(ctx_cs
, offset
);
4171 if (max_stream
>= 2)
4172 offset
+= num_components
[2] * gs_max_out_vertices
;
4173 radeon_emit(ctx_cs
, offset
);
4174 if (max_stream
>= 3)
4175 offset
+= num_components
[3] * gs_max_out_vertices
;
4176 radeon_set_context_reg(ctx_cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
4178 radeon_set_context_reg_seq(ctx_cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
4179 radeon_emit(ctx_cs
, num_components
[0]);
4180 radeon_emit(ctx_cs
, (max_stream
>= 1) ? num_components
[1] : 0);
4181 radeon_emit(ctx_cs
, (max_stream
>= 2) ? num_components
[2] : 0);
4182 radeon_emit(ctx_cs
, (max_stream
>= 3) ? num_components
[3] : 0);
4184 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
4185 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
4186 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
4187 S_028B90_ENABLE(gs_num_invocations
> 0));
4189 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
4190 gs_state
->vgt_esgs_ring_itemsize
);
4192 va
= radv_buffer_get_va(gs
->bo
) + gs
->bo_offset
;
4194 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4195 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4196 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
4197 radeon_emit(cs
, va
>> 8);
4198 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
4200 radeon_set_sh_reg_seq(cs
, R_00B210_SPI_SHADER_PGM_LO_ES
, 2);
4201 radeon_emit(cs
, va
>> 8);
4202 radeon_emit(cs
, S_00B214_MEM_BASE(va
>> 40));
4205 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
4206 radeon_emit(cs
, gs
->config
.rsrc1
);
4207 radeon_emit(cs
, gs
->config
.rsrc2
| S_00B22C_LDS_SIZE(gs_state
->lds_size
));
4209 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
, gs_state
->vgt_gs_onchip_cntl
);
4210 radeon_set_context_reg(ctx_cs
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
, gs_state
->vgt_gs_max_prims_per_subgroup
);
4212 radeon_set_sh_reg_seq(cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
4213 radeon_emit(cs
, va
>> 8);
4214 radeon_emit(cs
, S_00B224_MEM_BASE(va
>> 40));
4215 radeon_emit(cs
, gs
->config
.rsrc1
);
4216 radeon_emit(cs
, gs
->config
.rsrc2
);
4219 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, pipeline
->gs_copy_shader
);
4223 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf
*ctx_cs
,
4224 struct radeon_cmdbuf
*cs
,
4225 struct radv_pipeline
*pipeline
)
4227 struct radv_shader_variant
*gs
;
4229 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4233 if (gs
->info
.is_ngg
)
4234 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, gs
);
4236 radv_pipeline_generate_hw_gs(ctx_cs
, cs
, pipeline
, gs
);
4238 radeon_set_context_reg(ctx_cs
, R_028B38_VGT_GS_MAX_VERT_OUT
,
4239 gs
->info
.gs
.vertices_out
);
4242 static uint32_t offset_to_ps_input(uint32_t offset
, bool flat_shade
,
4243 bool explicit, bool float16
)
4245 uint32_t ps_input_cntl
;
4246 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
4247 ps_input_cntl
= S_028644_OFFSET(offset
);
4248 if (flat_shade
|| explicit)
4249 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
4251 /* Force parameter cache to be read in passthrough
4254 ps_input_cntl
|= S_028644_OFFSET(1 << 5);
4257 ps_input_cntl
|= S_028644_FP16_INTERP_MODE(1) |
4258 S_028644_ATTR0_VALID(1);
4261 /* The input is a DEFAULT_VAL constant. */
4262 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
4263 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
4264 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
4265 ps_input_cntl
= S_028644_OFFSET(0x20) |
4266 S_028644_DEFAULT_VAL(offset
);
4268 return ps_input_cntl
;
4272 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf
*ctx_cs
,
4273 struct radv_pipeline
*pipeline
)
4275 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4276 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
4277 uint32_t ps_input_cntl
[32];
4279 unsigned ps_offset
= 0;
4281 if (ps
->info
.ps
.prim_id_input
) {
4282 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
];
4283 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4284 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4289 if (ps
->info
.ps
.layer_input
||
4290 ps
->info
.needs_multiview_view_index
) {
4291 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
];
4292 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
4293 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4295 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false, false);
4299 if (ps
->info
.ps
.viewport_index_input
) {
4300 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VIEWPORT
];
4301 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
4302 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4304 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false, false);
4308 if (ps
->info
.ps
.has_pcoord
) {
4310 val
= S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4311 ps_input_cntl
[ps_offset
] = val
;
4315 if (ps
->info
.ps
.num_input_clips_culls
) {
4318 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST0
];
4319 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4320 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false, false);
4324 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST1
];
4325 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
&&
4326 ps
->info
.ps
.num_input_clips_culls
> 4) {
4327 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false, false);
4332 for (unsigned i
= 0; i
< 32 && (1u << i
) <= ps
->info
.ps
.input_mask
; ++i
) {
4337 if (!(ps
->info
.ps
.input_mask
& (1u << i
)))
4340 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VAR0
+ i
];
4341 if (vs_offset
== AC_EXP_PARAM_UNDEFINED
) {
4342 ps_input_cntl
[ps_offset
] = S_028644_OFFSET(0x20);
4347 flat_shade
= !!(ps
->info
.ps
.flat_shaded_mask
& (1u << ps_offset
));
4348 explicit = !!(ps
->info
.ps
.explicit_shaded_mask
& (1u << ps_offset
));
4349 float16
= !!(ps
->info
.ps
.float16_shaded_mask
& (1u << ps_offset
));
4351 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, flat_shade
, explicit, float16
);
4356 radeon_set_context_reg_seq(ctx_cs
, R_028644_SPI_PS_INPUT_CNTL_0
, ps_offset
);
4357 for (unsigned i
= 0; i
< ps_offset
; i
++) {
4358 radeon_emit(ctx_cs
, ps_input_cntl
[i
]);
4364 radv_compute_db_shader_control(const struct radv_device
*device
,
4365 const struct radv_pipeline
*pipeline
,
4366 const struct radv_shader_variant
*ps
)
4368 unsigned conservative_z_export
= V_02880C_EXPORT_ANY_Z
;
4370 if (ps
->info
.ps
.early_fragment_test
|| !ps
->info
.ps
.writes_memory
)
4371 z_order
= V_02880C_EARLY_Z_THEN_LATE_Z
;
4373 z_order
= V_02880C_LATE_Z
;
4375 if (ps
->info
.ps
.depth_layout
== FRAG_DEPTH_LAYOUT_GREATER
)
4376 conservative_z_export
= V_02880C_EXPORT_GREATER_THAN_Z
;
4377 else if (ps
->info
.ps
.depth_layout
== FRAG_DEPTH_LAYOUT_LESS
)
4378 conservative_z_export
= V_02880C_EXPORT_LESS_THAN_Z
;
4380 bool disable_rbplus
= device
->physical_device
->rad_info
.has_rbplus
&&
4381 !device
->physical_device
->rad_info
.rbplus_allowed
;
4383 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4384 * but this appears to break Project Cars (DXVK). See
4385 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4387 bool mask_export_enable
= ps
->info
.ps
.writes_sample_mask
;
4389 return S_02880C_Z_EXPORT_ENABLE(ps
->info
.ps
.writes_z
) |
4390 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps
->info
.ps
.writes_stencil
) |
4391 S_02880C_KILL_ENABLE(!!ps
->info
.ps
.can_discard
) |
4392 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable
) |
4393 S_02880C_CONSERVATIVE_Z_EXPORT(conservative_z_export
) |
4394 S_02880C_Z_ORDER(z_order
) |
4395 S_02880C_DEPTH_BEFORE_SHADER(ps
->info
.ps
.early_fragment_test
) |
4396 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps
->info
.ps
.post_depth_coverage
) |
4397 S_02880C_EXEC_ON_HIER_FAIL(ps
->info
.ps
.writes_memory
) |
4398 S_02880C_EXEC_ON_NOOP(ps
->info
.ps
.writes_memory
) |
4399 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus
);
4403 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf
*ctx_cs
,
4404 struct radeon_cmdbuf
*cs
,
4405 struct radv_pipeline
*pipeline
)
4407 struct radv_shader_variant
*ps
;
4409 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
4411 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4412 va
= radv_buffer_get_va(ps
->bo
) + ps
->bo_offset
;
4414 radeon_set_sh_reg_seq(cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
4415 radeon_emit(cs
, va
>> 8);
4416 radeon_emit(cs
, S_00B024_MEM_BASE(va
>> 40));
4417 radeon_emit(cs
, ps
->config
.rsrc1
);
4418 radeon_emit(cs
, ps
->config
.rsrc2
);
4420 radeon_set_context_reg(ctx_cs
, R_02880C_DB_SHADER_CONTROL
,
4421 radv_compute_db_shader_control(pipeline
->device
,
4424 radeon_set_context_reg(ctx_cs
, R_0286CC_SPI_PS_INPUT_ENA
,
4425 ps
->config
.spi_ps_input_ena
);
4427 radeon_set_context_reg(ctx_cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
4428 ps
->config
.spi_ps_input_addr
);
4430 radeon_set_context_reg(ctx_cs
, R_0286D8_SPI_PS_IN_CONTROL
,
4431 S_0286D8_NUM_INTERP(ps
->info
.ps
.num_interp
) |
4432 S_0286D8_PS_W32_EN(ps
->info
.wave_size
== 32));
4434 radeon_set_context_reg(ctx_cs
, R_0286E0_SPI_BARYC_CNTL
, pipeline
->graphics
.spi_baryc_cntl
);
4436 radeon_set_context_reg(ctx_cs
, R_028710_SPI_SHADER_Z_FORMAT
,
4437 ac_get_spi_shader_z_format(ps
->info
.ps
.writes_z
,
4438 ps
->info
.ps
.writes_stencil
,
4439 ps
->info
.ps
.writes_sample_mask
));
4441 if (pipeline
->device
->dfsm_allowed
) {
4442 /* optimise this? */
4443 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
4444 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
4449 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf
*ctx_cs
,
4450 struct radv_pipeline
*pipeline
)
4452 if (pipeline
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4453 pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
4456 unsigned vtx_reuse_depth
= 30;
4457 if (radv_pipeline_has_tess(pipeline
) &&
4458 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.tes
.spacing
== TESS_SPACING_FRACTIONAL_ODD
) {
4459 vtx_reuse_depth
= 14;
4461 radeon_set_context_reg(ctx_cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
4462 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth
));
4466 radv_pipeline_generate_vgt_shader_config(struct radeon_cmdbuf
*ctx_cs
,
4467 const struct radv_pipeline
*pipeline
)
4469 uint32_t stages
= 0;
4470 if (radv_pipeline_has_tess(pipeline
)) {
4471 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
4472 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4474 if (radv_pipeline_has_gs(pipeline
))
4475 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
4477 else if (radv_pipeline_has_ngg(pipeline
))
4478 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
4480 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
4481 } else if (radv_pipeline_has_gs(pipeline
)) {
4482 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
4484 } else if (radv_pipeline_has_ngg(pipeline
)) {
4485 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
4488 if (radv_pipeline_has_ngg(pipeline
)) {
4489 stages
|= S_028B54_PRIMGEN_EN(1);
4490 if (pipeline
->streamout_shader
)
4491 stages
|= S_028B54_NGG_WAVE_ID_EN(1);
4492 if (radv_pipeline_has_ngg_passthrough(pipeline
))
4493 stages
|= S_028B54_PRIMGEN_PASSTHRU_EN(1);
4494 } else if (radv_pipeline_has_gs(pipeline
)) {
4495 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
4498 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
4499 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4501 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4502 uint8_t hs_size
= 64, gs_size
= 64, vs_size
= 64;
4504 if (radv_pipeline_has_tess(pipeline
))
4505 hs_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.wave_size
;
4507 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
4508 vs_size
= gs_size
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.wave_size
;
4509 if (pipeline
->gs_copy_shader
)
4510 vs_size
= pipeline
->gs_copy_shader
->info
.wave_size
;
4511 } else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
4512 vs_size
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.wave_size
;
4513 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
4514 vs_size
= pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.wave_size
;
4516 if (radv_pipeline_has_ngg(pipeline
))
4519 /* legacy GS only supports Wave64 */
4520 stages
|= S_028B54_HS_W32_EN(hs_size
== 32 ? 1 : 0) |
4521 S_028B54_GS_W32_EN(gs_size
== 32 ? 1 : 0) |
4522 S_028B54_VS_W32_EN(vs_size
== 32 ? 1 : 0);
4525 radeon_set_context_reg(ctx_cs
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
4529 radv_pipeline_generate_cliprect_rule(struct radeon_cmdbuf
*ctx_cs
,
4530 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4532 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
4533 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
4534 uint32_t cliprect_rule
= 0;
4536 if (!discard_rectangle_info
) {
4537 cliprect_rule
= 0xffff;
4539 for (unsigned i
= 0; i
< (1u << MAX_DISCARD_RECTANGLES
); ++i
) {
4540 /* Interpret i as a bitmask, and then set the bit in
4541 * the mask if that combination of rectangles in which
4542 * the pixel is contained should pass the cliprect
4545 unsigned relevant_subset
= i
& ((1u << discard_rectangle_info
->discardRectangleCount
) - 1);
4547 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT
&&
4551 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT
&&
4555 cliprect_rule
|= 1u << i
;
4559 radeon_set_context_reg(ctx_cs
, R_02820C_PA_SC_CLIPRECT_RULE
, cliprect_rule
);
4563 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf
*ctx_cs
,
4564 struct radv_pipeline
*pipeline
)
4566 bool break_wave_at_eoi
= false;
4567 unsigned primgroup_size
;
4568 unsigned vertgroup_size
= 256; /* 256 = disable vertex grouping */
4570 if (radv_pipeline_has_tess(pipeline
)) {
4571 primgroup_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
4572 } else if (radv_pipeline_has_gs(pipeline
)) {
4573 const struct gfx9_gs_info
*gs_state
=
4574 &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs_ring_info
;
4575 unsigned vgt_gs_onchip_cntl
= gs_state
->vgt_gs_onchip_cntl
;
4576 primgroup_size
= G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl
);
4578 primgroup_size
= 128; /* recommended without a GS and tess */
4581 if (radv_pipeline_has_tess(pipeline
)) {
4582 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4583 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4584 break_wave_at_eoi
= true;
4587 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
,
4588 S_03096C_PRIM_GRP_SIZE(primgroup_size
) |
4589 S_03096C_VERT_GRP_SIZE(vertgroup_size
) |
4590 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4591 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
));
4595 radv_pipeline_generate_pm4(struct radv_pipeline
*pipeline
,
4596 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4597 const struct radv_graphics_pipeline_create_info
*extra
,
4598 const struct radv_blend_state
*blend
,
4599 const struct radv_tessellation_state
*tess
,
4602 struct radeon_cmdbuf
*ctx_cs
= &pipeline
->ctx_cs
;
4603 struct radeon_cmdbuf
*cs
= &pipeline
->cs
;
4606 ctx_cs
->max_dw
= 256;
4607 cs
->buf
= malloc(4 * (cs
->max_dw
+ ctx_cs
->max_dw
));
4608 ctx_cs
->buf
= cs
->buf
+ cs
->max_dw
;
4610 radv_pipeline_generate_depth_stencil_state(ctx_cs
, pipeline
, pCreateInfo
, extra
);
4611 radv_pipeline_generate_blend_state(ctx_cs
, pipeline
, blend
);
4612 radv_pipeline_generate_raster_state(ctx_cs
, pipeline
, pCreateInfo
);
4613 radv_pipeline_generate_multisample_state(ctx_cs
, pipeline
);
4614 radv_pipeline_generate_vgt_gs_mode(ctx_cs
, pipeline
);
4615 radv_pipeline_generate_vertex_shader(ctx_cs
, cs
, pipeline
);
4616 radv_pipeline_generate_tess_shaders(ctx_cs
, cs
, pipeline
, tess
);
4617 radv_pipeline_generate_geometry_shader(ctx_cs
, cs
, pipeline
);
4618 radv_pipeline_generate_fragment_shader(ctx_cs
, cs
, pipeline
);
4619 radv_pipeline_generate_ps_inputs(ctx_cs
, pipeline
);
4620 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs
, pipeline
);
4621 radv_pipeline_generate_binning_state(ctx_cs
, pipeline
, pCreateInfo
, blend
);
4622 radv_pipeline_generate_vgt_shader_config(ctx_cs
, pipeline
);
4623 radv_pipeline_generate_cliprect_rule(ctx_cs
, pCreateInfo
);
4625 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&& !radv_pipeline_has_ngg(pipeline
))
4626 gfx10_pipeline_generate_ge_cntl(ctx_cs
, pipeline
);
4628 radeon_set_context_reg(ctx_cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, gs_out
);
4630 pipeline
->ctx_cs_hash
= _mesa_hash_data(ctx_cs
->buf
, ctx_cs
->cdw
* 4);
4632 assert(ctx_cs
->cdw
<= ctx_cs
->max_dw
);
4633 assert(cs
->cdw
<= cs
->max_dw
);
4636 static struct radv_ia_multi_vgt_param_helpers
4637 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline
*pipeline
)
4639 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
= {0};
4640 const struct radv_device
*device
= pipeline
->device
;
4642 if (radv_pipeline_has_tess(pipeline
))
4643 ia_multi_vgt_param
.primgroup_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
4644 else if (radv_pipeline_has_gs(pipeline
))
4645 ia_multi_vgt_param
.primgroup_size
= 64;
4647 ia_multi_vgt_param
.primgroup_size
= 128; /* recommended without a GS */
4649 /* GS requirement. */
4650 ia_multi_vgt_param
.partial_es_wave
= false;
4651 if (radv_pipeline_has_gs(pipeline
) && device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4652 if (SI_GS_PER_ES
/ ia_multi_vgt_param
.primgroup_size
>= pipeline
->device
->gs_table_depth
- 3)
4653 ia_multi_vgt_param
.partial_es_wave
= true;
4655 ia_multi_vgt_param
.ia_switch_on_eoi
= false;
4656 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.prim_id_input
)
4657 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4658 if (radv_pipeline_has_gs(pipeline
) &&
4659 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.uses_prim_id
)
4660 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4661 if (radv_pipeline_has_tess(pipeline
)) {
4662 /* SWITCH_ON_EOI must be set if PrimID is used. */
4663 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4664 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4665 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4668 ia_multi_vgt_param
.partial_vs_wave
= false;
4669 if (radv_pipeline_has_tess(pipeline
)) {
4670 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4671 if ((device
->physical_device
->rad_info
.family
== CHIP_TAHITI
||
4672 device
->physical_device
->rad_info
.family
== CHIP_PITCAIRN
||
4673 device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
) &&
4674 radv_pipeline_has_gs(pipeline
))
4675 ia_multi_vgt_param
.partial_vs_wave
= true;
4676 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4677 if (device
->physical_device
->rad_info
.has_distributed_tess
) {
4678 if (radv_pipeline_has_gs(pipeline
)) {
4679 if (device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4680 ia_multi_vgt_param
.partial_es_wave
= true;
4682 ia_multi_vgt_param
.partial_vs_wave
= true;
4687 if (radv_pipeline_has_gs(pipeline
)) {
4688 /* On these chips there is the possibility of a hang if the
4689 * pipeline uses a GS and partial_vs_wave is not set.
4691 * This mostly does not hit 4-SE chips, as those typically set
4692 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4693 * with GS due to another workaround.
4695 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4697 if (device
->physical_device
->rad_info
.family
== CHIP_TONGA
||
4698 device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
4699 device
->physical_device
->rad_info
.family
== CHIP_POLARIS10
||
4700 device
->physical_device
->rad_info
.family
== CHIP_POLARIS11
||
4701 device
->physical_device
->rad_info
.family
== CHIP_POLARIS12
||
4702 device
->physical_device
->rad_info
.family
== CHIP_VEGAM
) {
4703 ia_multi_vgt_param
.partial_vs_wave
= true;
4707 ia_multi_vgt_param
.base
=
4708 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param
.primgroup_size
- 1) |
4709 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4710 S_028AA8_MAX_PRIMGRP_IN_WAVE(device
->physical_device
->rad_info
.chip_class
== GFX8
? 2 : 0) |
4711 S_030960_EN_INST_OPT_BASIC(device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
4712 S_030960_EN_INST_OPT_ADV(device
->physical_device
->rad_info
.chip_class
>= GFX9
);
4714 return ia_multi_vgt_param
;
4719 radv_compute_vertex_input_state(struct radv_pipeline
*pipeline
,
4720 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4722 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
4723 pCreateInfo
->pVertexInputState
;
4725 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
4726 const VkVertexInputBindingDescription
*desc
=
4727 &vi_info
->pVertexBindingDescriptions
[i
];
4729 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
4730 pipeline
->num_vertex_bindings
=
4731 MAX2(pipeline
->num_vertex_bindings
, desc
->binding
+ 1);
4735 static struct radv_shader_variant
*
4736 radv_pipeline_get_streamout_shader(struct radv_pipeline
*pipeline
)
4740 for (i
= MESA_SHADER_GEOMETRY
; i
>= MESA_SHADER_VERTEX
; i
--) {
4741 struct radv_shader_variant
*shader
=
4742 radv_get_shader(pipeline
, i
);
4744 if (shader
&& shader
->info
.so
.num_outputs
> 0)
4752 radv_pipeline_init(struct radv_pipeline
*pipeline
,
4753 struct radv_device
*device
,
4754 struct radv_pipeline_cache
*cache
,
4755 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4756 const struct radv_graphics_pipeline_create_info
*extra
)
4760 pipeline
->device
= device
;
4761 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
4762 assert(pipeline
->layout
);
4764 struct radv_blend_state blend
= radv_pipeline_init_blend_state(pipeline
, pCreateInfo
, extra
);
4766 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
4767 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
4768 radv_init_feedback(creation_feedback
);
4770 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
4772 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
4773 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
4774 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
4775 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
4776 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
4777 if(creation_feedback
)
4778 stage_feedbacks
[stage
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[i
];
4781 struct radv_pipeline_key key
= radv_generate_graphics_pipeline_key(pipeline
, pCreateInfo
, &blend
);
4783 result
= radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
,
4784 pCreateInfo
->flags
, pipeline_feedback
,
4786 if (result
!= VK_SUCCESS
)
4789 pipeline
->graphics
.spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
4790 radv_pipeline_init_multisample_state(pipeline
, &blend
, pCreateInfo
);
4793 pipeline
->graphics
.can_use_guardband
= radv_prim_can_use_guardband(pCreateInfo
->pInputAssemblyState
->topology
);
4795 if (radv_pipeline_has_gs(pipeline
)) {
4796 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs
.output_prim
);
4797 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4798 } else if (radv_pipeline_has_tess(pipeline
)) {
4799 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.point_mode
)
4800 gs_out
= V_028A6C_OUTPRIM_TYPE_POINTLIST
;
4802 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.primitive_mode
);
4803 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4805 gs_out
= si_conv_prim_to_gs_out(pCreateInfo
->pInputAssemblyState
->topology
);
4807 if (extra
&& extra
->use_rectlist
) {
4808 gs_out
= V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4809 pipeline
->graphics
.can_use_guardband
= true;
4810 if (radv_pipeline_has_ngg(pipeline
))
4811 gs_out
= V_028A6C_VGT_OUT_RECT_V0
;
4813 pipeline
->graphics
.prim_restart_enable
= !!pCreateInfo
->pInputAssemblyState
->primitiveRestartEnable
;
4815 radv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
, extra
);
4817 /* Ensure that some export memory is always allocated, for two reasons:
4819 * 1) Correctness: The hardware ignores the EXEC mask if no export
4820 * memory is allocated, so KILL and alpha test do not work correctly
4822 * 2) Performance: Every shader needs at least a NULL export, even when
4823 * it writes no color/depth output. The NULL export instruction
4824 * stalls without this setting.
4826 * Don't add this to CB_SHADER_MASK.
4828 * GFX10 supports pixel shaders without exports by setting both the
4829 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
4830 * instructions if any are present.
4832 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4833 if ((pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX9
||
4834 ps
->info
.ps
.can_discard
) &&
4835 !blend
.spi_shader_col_format
) {
4836 if (!ps
->info
.ps
.writes_z
&&
4837 !ps
->info
.ps
.writes_stencil
&&
4838 !ps
->info
.ps
.writes_sample_mask
)
4839 blend
.spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
4842 blend
.cb_shader_mask
= ps
->info
.ps
.cb_shader_mask
;
4845 (extra
->custom_blend_mode
== V_028808_CB_ELIMINATE_FAST_CLEAR
||
4846 extra
->custom_blend_mode
== V_028808_CB_FMASK_DECOMPRESS
||
4847 extra
->custom_blend_mode
== V_028808_CB_DCC_DECOMPRESS
||
4848 extra
->custom_blend_mode
== V_028808_CB_RESOLVE
)) {
4849 /* According to the CB spec states, CB_SHADER_MASK should be
4850 * set to enable writes to all four channels of MRT0.
4852 blend
.cb_shader_mask
= 0xf;
4855 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
4856 if (pipeline
->shaders
[i
]) {
4857 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[i
]->info
.need_indirect_descriptor_sets
;
4861 if (radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
4862 struct radv_shader_variant
*gs
=
4863 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4865 calculate_gs_ring_sizes(pipeline
, &gs
->info
.gs_ring_info
);
4868 struct radv_tessellation_state tess
= {0};
4869 if (radv_pipeline_has_tess(pipeline
)) {
4870 pipeline
->graphics
.tess_patch_control_points
=
4871 pCreateInfo
->pTessellationState
->patchControlPoints
;
4872 tess
= calculate_tess_state(pipeline
, pCreateInfo
);
4875 pipeline
->graphics
.ia_multi_vgt_param
= radv_compute_ia_multi_vgt_param_helpers(pipeline
);
4877 radv_compute_vertex_input_state(pipeline
, pCreateInfo
);
4879 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++)
4880 pipeline
->user_data_0
[i
] = radv_pipeline_stage_to_user_data_0(pipeline
, i
, device
->physical_device
->rad_info
.chip_class
);
4882 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
,
4883 AC_UD_VS_BASE_VERTEX_START_INSTANCE
);
4884 if (loc
->sgpr_idx
!= -1) {
4885 pipeline
->graphics
.vtx_base_sgpr
= pipeline
->user_data_0
[MESA_SHADER_VERTEX
];
4886 pipeline
->graphics
.vtx_base_sgpr
+= loc
->sgpr_idx
* 4;
4887 if (radv_get_shader(pipeline
, MESA_SHADER_VERTEX
)->info
.vs
.needs_draw_id
)
4888 pipeline
->graphics
.vtx_emit_num
= 3;
4890 pipeline
->graphics
.vtx_emit_num
= 2;
4893 /* Find the last vertex shader stage that eventually uses streamout. */
4894 pipeline
->streamout_shader
= radv_pipeline_get_streamout_shader(pipeline
);
4896 result
= radv_pipeline_scratch_init(device
, pipeline
);
4897 radv_pipeline_generate_pm4(pipeline
, pCreateInfo
, extra
, &blend
, &tess
, gs_out
);
4903 radv_graphics_pipeline_create(
4905 VkPipelineCache _cache
,
4906 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4907 const struct radv_graphics_pipeline_create_info
*extra
,
4908 const VkAllocationCallbacks
*pAllocator
,
4909 VkPipeline
*pPipeline
)
4911 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4912 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
4913 struct radv_pipeline
*pipeline
;
4916 pipeline
= vk_zalloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*pipeline
), 8,
4917 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4918 if (pipeline
== NULL
)
4919 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4921 vk_object_base_init(&device
->vk
, &pipeline
->base
,
4922 VK_OBJECT_TYPE_PIPELINE
);
4924 result
= radv_pipeline_init(pipeline
, device
, cache
,
4925 pCreateInfo
, extra
);
4926 if (result
!= VK_SUCCESS
) {
4927 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
4931 *pPipeline
= radv_pipeline_to_handle(pipeline
);
4936 VkResult
radv_CreateGraphicsPipelines(
4938 VkPipelineCache pipelineCache
,
4940 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
4941 const VkAllocationCallbacks
* pAllocator
,
4942 VkPipeline
* pPipelines
)
4944 VkResult result
= VK_SUCCESS
;
4947 for (; i
< count
; i
++) {
4949 r
= radv_graphics_pipeline_create(_device
,
4952 NULL
, pAllocator
, &pPipelines
[i
]);
4953 if (r
!= VK_SUCCESS
) {
4955 pPipelines
[i
] = VK_NULL_HANDLE
;
4957 if (pCreateInfos
[i
].flags
& VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT
)
4962 for (; i
< count
; ++i
)
4963 pPipelines
[i
] = VK_NULL_HANDLE
;
4969 radv_pipeline_generate_hw_cs(struct radeon_cmdbuf
*cs
,
4970 struct radv_pipeline
*pipeline
)
4972 struct radv_shader_variant
*shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
4973 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
4974 struct radv_device
*device
= pipeline
->device
;
4976 radeon_set_sh_reg_seq(cs
, R_00B830_COMPUTE_PGM_LO
, 2);
4977 radeon_emit(cs
, va
>> 8);
4978 radeon_emit(cs
, S_00B834_DATA(va
>> 40));
4980 radeon_set_sh_reg_seq(cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
4981 radeon_emit(cs
, shader
->config
.rsrc1
);
4982 radeon_emit(cs
, shader
->config
.rsrc2
);
4983 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4984 radeon_set_sh_reg(cs
, R_00B8A0_COMPUTE_PGM_RSRC3
, shader
->config
.rsrc3
);
4989 radv_pipeline_generate_compute_state(struct radeon_cmdbuf
*cs
,
4990 struct radv_pipeline
*pipeline
)
4992 struct radv_shader_variant
*shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
4993 struct radv_device
*device
= pipeline
->device
;
4994 unsigned threads_per_threadgroup
;
4995 unsigned threadgroups_per_cu
= 1;
4996 unsigned waves_per_threadgroup
;
4997 unsigned max_waves_per_sh
= 0;
4999 /* Calculate best compute resource limits. */
5000 threads_per_threadgroup
= shader
->info
.cs
.block_size
[0] *
5001 shader
->info
.cs
.block_size
[1] *
5002 shader
->info
.cs
.block_size
[2];
5003 waves_per_threadgroup
= DIV_ROUND_UP(threads_per_threadgroup
,
5004 shader
->info
.wave_size
);
5006 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
5007 waves_per_threadgroup
== 1)
5008 threadgroups_per_cu
= 2;
5010 radeon_set_sh_reg(cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
5011 ac_get_compute_resource_limits(&device
->physical_device
->rad_info
,
5012 waves_per_threadgroup
,
5014 threadgroups_per_cu
));
5016 radeon_set_sh_reg_seq(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
5017 radeon_emit(cs
, S_00B81C_NUM_THREAD_FULL(shader
->info
.cs
.block_size
[0]));
5018 radeon_emit(cs
, S_00B81C_NUM_THREAD_FULL(shader
->info
.cs
.block_size
[1]));
5019 radeon_emit(cs
, S_00B81C_NUM_THREAD_FULL(shader
->info
.cs
.block_size
[2]));
5023 radv_compute_generate_pm4(struct radv_pipeline
*pipeline
)
5025 struct radv_device
*device
= pipeline
->device
;
5026 struct radeon_cmdbuf
*cs
= &pipeline
->cs
;
5028 cs
->max_dw
= device
->physical_device
->rad_info
.chip_class
>= GFX10
? 19 : 16;
5029 cs
->buf
= malloc(cs
->max_dw
* 4);
5031 radv_pipeline_generate_hw_cs(cs
, pipeline
);
5032 radv_pipeline_generate_compute_state(cs
, pipeline
);
5034 assert(pipeline
->cs
.cdw
<= pipeline
->cs
.max_dw
);
5037 static struct radv_pipeline_key
5038 radv_generate_compute_pipeline_key(struct radv_pipeline
*pipeline
,
5039 const VkComputePipelineCreateInfo
*pCreateInfo
)
5041 const VkPipelineShaderStageCreateInfo
*stage
= &pCreateInfo
->stage
;
5042 struct radv_pipeline_key key
;
5043 memset(&key
, 0, sizeof(key
));
5045 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
5046 key
.optimisations_disabled
= 1;
5048 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*subgroup_size
=
5049 vk_find_struct_const(stage
->pNext
,
5050 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT
);
5052 if (subgroup_size
) {
5053 assert(subgroup_size
->requiredSubgroupSize
== 32 ||
5054 subgroup_size
->requiredSubgroupSize
== 64);
5055 key
.compute_subgroup_size
= subgroup_size
->requiredSubgroupSize
;
5061 static VkResult
radv_compute_pipeline_create(
5063 VkPipelineCache _cache
,
5064 const VkComputePipelineCreateInfo
* pCreateInfo
,
5065 const VkAllocationCallbacks
* pAllocator
,
5066 VkPipeline
* pPipeline
)
5068 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5069 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
5070 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
5071 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
5072 struct radv_pipeline
*pipeline
;
5075 pipeline
= vk_zalloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*pipeline
), 8,
5076 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5077 if (pipeline
== NULL
)
5078 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5080 vk_object_base_init(&device
->vk
, &pipeline
->base
,
5081 VK_OBJECT_TYPE_PIPELINE
);
5083 pipeline
->device
= device
;
5084 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
5085 assert(pipeline
->layout
);
5087 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
5088 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
5089 radv_init_feedback(creation_feedback
);
5091 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
5092 if (creation_feedback
)
5093 stage_feedbacks
[MESA_SHADER_COMPUTE
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[0];
5095 pStages
[MESA_SHADER_COMPUTE
] = &pCreateInfo
->stage
;
5097 struct radv_pipeline_key key
=
5098 radv_generate_compute_pipeline_key(pipeline
, pCreateInfo
);
5100 result
= radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
,
5101 pCreateInfo
->flags
, pipeline_feedback
,
5103 if (result
!= VK_SUCCESS
) {
5104 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5108 pipeline
->user_data_0
[MESA_SHADER_COMPUTE
] = radv_pipeline_stage_to_user_data_0(pipeline
, MESA_SHADER_COMPUTE
, device
->physical_device
->rad_info
.chip_class
);
5109 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.need_indirect_descriptor_sets
;
5110 result
= radv_pipeline_scratch_init(device
, pipeline
);
5111 if (result
!= VK_SUCCESS
) {
5112 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5116 radv_compute_generate_pm4(pipeline
);
5118 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5123 VkResult
radv_CreateComputePipelines(
5125 VkPipelineCache pipelineCache
,
5127 const VkComputePipelineCreateInfo
* pCreateInfos
,
5128 const VkAllocationCallbacks
* pAllocator
,
5129 VkPipeline
* pPipelines
)
5131 VkResult result
= VK_SUCCESS
;
5134 for (; i
< count
; i
++) {
5136 r
= radv_compute_pipeline_create(_device
, pipelineCache
,
5138 pAllocator
, &pPipelines
[i
]);
5139 if (r
!= VK_SUCCESS
) {
5141 pPipelines
[i
] = VK_NULL_HANDLE
;
5143 if (pCreateInfos
[i
].flags
& VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT
)
5148 for (; i
< count
; ++i
)
5149 pPipelines
[i
] = VK_NULL_HANDLE
;
5155 static uint32_t radv_get_executable_count(const struct radv_pipeline
*pipeline
)
5158 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5159 if (!pipeline
->shaders
[i
])
5162 if (i
== MESA_SHADER_GEOMETRY
&&
5163 !radv_pipeline_has_ngg(pipeline
)) {
5173 static struct radv_shader_variant
*
5174 radv_get_shader_from_executable_index(const struct radv_pipeline
*pipeline
, int index
, gl_shader_stage
*stage
)
5176 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5177 if (!pipeline
->shaders
[i
])
5181 return pipeline
->shaders
[i
];
5186 if (i
== MESA_SHADER_GEOMETRY
&&
5187 !radv_pipeline_has_ngg(pipeline
)) {
5190 return pipeline
->gs_copy_shader
;
5200 /* Basically strlcpy (which does not exist on linux) specialized for
5202 static void desc_copy(char *desc
, const char *src
) {
5203 int len
= strlen(src
);
5204 assert(len
< VK_MAX_DESCRIPTION_SIZE
);
5205 memcpy(desc
, src
, len
);
5206 memset(desc
+ len
, 0, VK_MAX_DESCRIPTION_SIZE
- len
);
5209 VkResult
radv_GetPipelineExecutablePropertiesKHR(
5211 const VkPipelineInfoKHR
* pPipelineInfo
,
5212 uint32_t* pExecutableCount
,
5213 VkPipelineExecutablePropertiesKHR
* pProperties
)
5215 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pPipelineInfo
->pipeline
);
5216 const uint32_t total_count
= radv_get_executable_count(pipeline
);
5219 *pExecutableCount
= total_count
;
5223 const uint32_t count
= MIN2(total_count
, *pExecutableCount
);
5224 for (unsigned i
= 0, executable_idx
= 0;
5225 i
< MESA_SHADER_STAGES
&& executable_idx
< count
; ++i
) {
5226 if (!pipeline
->shaders
[i
])
5228 pProperties
[executable_idx
].stages
= mesa_to_vk_shader_stage(i
);
5229 const char *name
= NULL
;
5230 const char *description
= NULL
;
5232 case MESA_SHADER_VERTEX
:
5233 name
= "Vertex Shader";
5234 description
= "Vulkan Vertex Shader";
5236 case MESA_SHADER_TESS_CTRL
:
5237 if (!pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5238 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5239 name
= "Vertex + Tessellation Control Shaders";
5240 description
= "Combined Vulkan Vertex and Tessellation Control Shaders";
5242 name
= "Tessellation Control Shader";
5243 description
= "Vulkan Tessellation Control Shader";
5246 case MESA_SHADER_TESS_EVAL
:
5247 name
= "Tessellation Evaluation Shader";
5248 description
= "Vulkan Tessellation Evaluation Shader";
5250 case MESA_SHADER_GEOMETRY
:
5251 if (radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]) {
5252 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
;
5253 name
= "Tessellation Evaluation + Geometry Shaders";
5254 description
= "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5255 } else if (!radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5256 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5257 name
= "Vertex + Geometry Shader";
5258 description
= "Combined Vulkan Vertex and Geometry Shaders";
5260 name
= "Geometry Shader";
5261 description
= "Vulkan Geometry Shader";
5264 case MESA_SHADER_FRAGMENT
:
5265 name
= "Fragment Shader";
5266 description
= "Vulkan Fragment Shader";
5268 case MESA_SHADER_COMPUTE
:
5269 name
= "Compute Shader";
5270 description
= "Vulkan Compute Shader";
5274 pProperties
[executable_idx
].subgroupSize
= pipeline
->shaders
[i
]->info
.wave_size
;
5275 desc_copy(pProperties
[executable_idx
].name
, name
);
5276 desc_copy(pProperties
[executable_idx
].description
, description
);
5279 if (i
== MESA_SHADER_GEOMETRY
&&
5280 !radv_pipeline_has_ngg(pipeline
)) {
5281 assert(pipeline
->gs_copy_shader
);
5282 if (executable_idx
>= count
)
5285 pProperties
[executable_idx
].stages
= VK_SHADER_STAGE_GEOMETRY_BIT
;
5286 pProperties
[executable_idx
].subgroupSize
= 64;
5287 desc_copy(pProperties
[executable_idx
].name
, "GS Copy Shader");
5288 desc_copy(pProperties
[executable_idx
].description
,
5289 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5295 VkResult result
= *pExecutableCount
< total_count
? VK_INCOMPLETE
: VK_SUCCESS
;
5296 *pExecutableCount
= count
;
5300 VkResult
radv_GetPipelineExecutableStatisticsKHR(
5302 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5303 uint32_t* pStatisticCount
,
5304 VkPipelineExecutableStatisticKHR
* pStatistics
)
5306 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5307 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5308 gl_shader_stage stage
;
5309 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5311 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
5312 unsigned lds_increment
= chip_class
>= GFX7
? 512 : 256;
5313 unsigned max_waves
= radv_get_max_waves(device
, shader
, stage
);
5315 VkPipelineExecutableStatisticKHR
*s
= pStatistics
;
5316 VkPipelineExecutableStatisticKHR
*end
= s
+ (pStatistics
? *pStatisticCount
: 0);
5317 VkResult result
= VK_SUCCESS
;
5320 desc_copy(s
->name
, "SGPRs");
5321 desc_copy(s
->description
, "Number of SGPR registers allocated per subgroup");
5322 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5323 s
->value
.u64
= shader
->config
.num_sgprs
;
5328 desc_copy(s
->name
, "VGPRs");
5329 desc_copy(s
->description
, "Number of VGPR registers allocated per subgroup");
5330 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5331 s
->value
.u64
= shader
->config
.num_vgprs
;
5336 desc_copy(s
->name
, "Spilled SGPRs");
5337 desc_copy(s
->description
, "Number of SGPR registers spilled per subgroup");
5338 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5339 s
->value
.u64
= shader
->config
.spilled_sgprs
;
5344 desc_copy(s
->name
, "Spilled VGPRs");
5345 desc_copy(s
->description
, "Number of VGPR registers spilled per subgroup");
5346 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5347 s
->value
.u64
= shader
->config
.spilled_vgprs
;
5352 desc_copy(s
->name
, "PrivMem VGPRs");
5353 desc_copy(s
->description
, "Number of VGPRs stored in private memory per subgroup");
5354 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5355 s
->value
.u64
= shader
->info
.private_mem_vgprs
;
5360 desc_copy(s
->name
, "Code size");
5361 desc_copy(s
->description
, "Code size in bytes");
5362 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5363 s
->value
.u64
= shader
->exec_size
;
5368 desc_copy(s
->name
, "LDS size");
5369 desc_copy(s
->description
, "LDS size in bytes per workgroup");
5370 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5371 s
->value
.u64
= shader
->config
.lds_size
* lds_increment
;
5376 desc_copy(s
->name
, "Scratch size");
5377 desc_copy(s
->description
, "Private memory in bytes per subgroup");
5378 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5379 s
->value
.u64
= shader
->config
.scratch_bytes_per_wave
;
5384 desc_copy(s
->name
, "Subgroups per SIMD");
5385 desc_copy(s
->description
, "The maximum number of subgroups in flight on a SIMD unit");
5386 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5387 s
->value
.u64
= max_waves
;
5391 if (shader
->statistics
) {
5392 for (unsigned i
= 0; i
< shader
->statistics
->count
; i
++) {
5393 struct radv_compiler_statistic_info
*info
= &shader
->statistics
->infos
[i
];
5394 uint32_t value
= shader
->statistics
->values
[i
];
5396 desc_copy(s
->name
, info
->name
);
5397 desc_copy(s
->description
, info
->desc
);
5398 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5399 s
->value
.u64
= value
;
5406 *pStatisticCount
= s
- pStatistics
;
5408 *pStatisticCount
= end
- pStatistics
;
5409 result
= VK_INCOMPLETE
;
5411 *pStatisticCount
= s
- pStatistics
;
5417 static VkResult
radv_copy_representation(void *data
, size_t *data_size
, const char *src
)
5419 size_t total_size
= strlen(src
) + 1;
5422 *data_size
= total_size
;
5426 size_t size
= MIN2(total_size
, *data_size
);
5428 memcpy(data
, src
, size
);
5430 *((char*)data
+ size
- 1) = 0;
5431 return size
< total_size
? VK_INCOMPLETE
: VK_SUCCESS
;
5434 VkResult
radv_GetPipelineExecutableInternalRepresentationsKHR(
5436 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5437 uint32_t* pInternalRepresentationCount
,
5438 VkPipelineExecutableInternalRepresentationKHR
* pInternalRepresentations
)
5440 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5441 gl_shader_stage stage
;
5442 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5444 VkPipelineExecutableInternalRepresentationKHR
*p
= pInternalRepresentations
;
5445 VkPipelineExecutableInternalRepresentationKHR
*end
= p
+ (pInternalRepresentations
? *pInternalRepresentationCount
: 0);
5446 VkResult result
= VK_SUCCESS
;
5450 desc_copy(p
->name
, "NIR Shader(s)");
5451 desc_copy(p
->description
, "The optimized NIR shader(s)");
5452 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->nir_string
) != VK_SUCCESS
)
5453 result
= VK_INCOMPLETE
;
5460 if (pipeline
->device
->physical_device
->use_llvm
) {
5461 desc_copy(p
->name
, "LLVM IR");
5462 desc_copy(p
->description
, "The LLVM IR after some optimizations");
5464 desc_copy(p
->name
, "ACO IR");
5465 desc_copy(p
->description
, "The ACO IR after some optimizations");
5467 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->ir_string
) != VK_SUCCESS
)
5468 result
= VK_INCOMPLETE
;
5475 desc_copy(p
->name
, "Assembly");
5476 desc_copy(p
->description
, "Final Assembly");
5477 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->disasm_string
) != VK_SUCCESS
)
5478 result
= VK_INCOMPLETE
;
5482 if (!pInternalRepresentations
)
5483 *pInternalRepresentationCount
= p
- pInternalRepresentations
;
5485 result
= VK_INCOMPLETE
;
5486 *pInternalRepresentationCount
= end
- pInternalRepresentations
;
5488 *pInternalRepresentationCount
= p
- pInternalRepresentations
;