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Added few more stubs so that control reaches to DestroyDevice().
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
33 #include "radv_cs.h"
34 #include "radv_shader.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
39 #include "vk_util.h"
40
41 #include "sid.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
48 #include "ac_shader_util.h"
49
50 struct radv_blend_state {
51 uint32_t blend_enable_4bit;
52 uint32_t need_src_alpha;
53
54 uint32_t cb_color_control;
55 uint32_t cb_target_mask;
56 uint32_t cb_target_enabled_4bit;
57 uint32_t sx_mrt_blend_opt[8];
58 uint32_t cb_blend_control[8];
59
60 uint32_t spi_shader_col_format;
61 uint32_t col_format_is_int8;
62 uint32_t col_format_is_int10;
63 uint32_t cb_shader_mask;
64 uint32_t db_alpha_to_mask;
65
66 uint32_t commutative_4bit;
67
68 bool single_cb_enable;
69 bool mrt0_is_dual_src;
70 };
71
72 struct radv_dsa_order_invariance {
73 /* Whether the final result in Z/S buffers is guaranteed to be
74 * invariant under changes to the order in which fragments arrive.
75 */
76 bool zs;
77
78 /* Whether the set of fragments that pass the combined Z/S test is
79 * guaranteed to be invariant under changes to the order in which
80 * fragments arrive.
81 */
82 bool pass_set;
83 };
84
85 static const VkPipelineMultisampleStateCreateInfo *
86 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
87 {
88 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
89 return pCreateInfo->pMultisampleState;
90 return NULL;
91 }
92
93 static const VkPipelineTessellationStateCreateInfo *
94 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
95 {
96 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
97 if (pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT ||
98 pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) {
99 return pCreateInfo->pTessellationState;
100 }
101 }
102 return NULL;
103 }
104
105 static const VkPipelineDepthStencilStateCreateInfo *
106 radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
107 {
108 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
109 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
110
111 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
112 subpass->depth_stencil_attachment)
113 return pCreateInfo->pDepthStencilState;
114 return NULL;
115 }
116
117 static const VkPipelineColorBlendStateCreateInfo *
118 radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
119 {
120 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
121 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
122
123 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
124 subpass->has_color_att)
125 return pCreateInfo->pColorBlendState;
126 return NULL;
127 }
128
129 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline)
130 {
131 struct radv_shader_variant *variant = NULL;
132 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
133 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
134 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
135 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
136 else if (pipeline->shaders[MESA_SHADER_VERTEX])
137 variant = pipeline->shaders[MESA_SHADER_VERTEX];
138 else
139 return false;
140 return variant->info.is_ngg;
141 }
142
143 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline *pipeline)
144 {
145 assert(radv_pipeline_has_ngg(pipeline));
146
147 struct radv_shader_variant *variant = NULL;
148 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
149 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
150 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
151 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
152 else if (pipeline->shaders[MESA_SHADER_VERTEX])
153 variant = pipeline->shaders[MESA_SHADER_VERTEX];
154 else
155 return false;
156 return variant->info.is_ngg_passthrough;
157 }
158
159 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline)
160 {
161 if (!radv_pipeline_has_gs(pipeline))
162 return false;
163
164 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
165 * On GFX10, it might be required in rare cases if it's not possible to
166 * enable NGG.
167 */
168 if (radv_pipeline_has_ngg(pipeline))
169 return false;
170
171 assert(pipeline->gs_copy_shader);
172 return true;
173 }
174
175 static void
176 radv_pipeline_destroy(struct radv_device *device,
177 struct radv_pipeline *pipeline,
178 const VkAllocationCallbacks* allocator)
179 {
180 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
181 if (pipeline->shaders[i])
182 radv_shader_variant_destroy(device, pipeline->shaders[i]);
183
184 if (pipeline->gs_copy_shader)
185 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
186
187 if(pipeline->cs.buf)
188 free(pipeline->cs.buf);
189
190 vk_object_base_finish(&pipeline->base);
191 vk_free2(&device->vk.alloc, allocator, pipeline);
192 }
193
194 void radv_DestroyPipeline(
195 VkDevice _device,
196 VkPipeline _pipeline,
197 const VkAllocationCallbacks* pAllocator)
198 {
199 RADV_FROM_HANDLE(radv_device, device, _device);
200 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
201
202 if (!_pipeline)
203 return;
204
205 radv_pipeline_destroy(device, pipeline, pAllocator);
206 }
207
208 static uint32_t get_hash_flags(struct radv_device *device)
209 {
210 uint32_t hash_flags = 0;
211
212 if (device->instance->debug_flags & RADV_DEBUG_NO_NGG)
213 hash_flags |= RADV_HASH_SHADER_NO_NGG;
214 if (device->physical_device->cs_wave_size == 32)
215 hash_flags |= RADV_HASH_SHADER_CS_WAVE32;
216 if (device->physical_device->ps_wave_size == 32)
217 hash_flags |= RADV_HASH_SHADER_PS_WAVE32;
218 if (device->physical_device->ge_wave_size == 32)
219 hash_flags |= RADV_HASH_SHADER_GE_WAVE32;
220 if (device->physical_device->use_llvm)
221 hash_flags |= RADV_HASH_SHADER_LLVM;
222 return hash_flags;
223 }
224
225 static void
226 radv_pipeline_init_scratch(struct radv_device *device,
227 struct radv_pipeline *pipeline)
228 {
229 unsigned scratch_bytes_per_wave = 0;
230 unsigned max_waves = 0;
231 unsigned min_waves = 1;
232
233 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
234 if (pipeline->shaders[i] &&
235 pipeline->shaders[i]->config.scratch_bytes_per_wave) {
236 unsigned max_stage_waves = device->scratch_waves;
237
238 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
239 pipeline->shaders[i]->config.scratch_bytes_per_wave);
240
241 max_stage_waves = MIN2(max_stage_waves,
242 4 * device->physical_device->rad_info.num_good_compute_units *
243 (256 / pipeline->shaders[i]->config.num_vgprs));
244 max_waves = MAX2(max_waves, max_stage_waves);
245 }
246 }
247
248 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
249 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
250 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
251 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
252 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
253 }
254
255 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
256 pipeline->max_waves = max_waves;
257 }
258
259 static uint32_t si_translate_blend_logic_op(VkLogicOp op)
260 {
261 switch (op) {
262 case VK_LOGIC_OP_CLEAR:
263 return V_028808_ROP3_CLEAR;
264 case VK_LOGIC_OP_AND:
265 return V_028808_ROP3_AND;
266 case VK_LOGIC_OP_AND_REVERSE:
267 return V_028808_ROP3_AND_REVERSE;
268 case VK_LOGIC_OP_COPY:
269 return V_028808_ROP3_COPY;
270 case VK_LOGIC_OP_AND_INVERTED:
271 return V_028808_ROP3_AND_INVERTED;
272 case VK_LOGIC_OP_NO_OP:
273 return V_028808_ROP3_NO_OP;
274 case VK_LOGIC_OP_XOR:
275 return V_028808_ROP3_XOR;
276 case VK_LOGIC_OP_OR:
277 return V_028808_ROP3_OR;
278 case VK_LOGIC_OP_NOR:
279 return V_028808_ROP3_NOR;
280 case VK_LOGIC_OP_EQUIVALENT:
281 return V_028808_ROP3_EQUIVALENT;
282 case VK_LOGIC_OP_INVERT:
283 return V_028808_ROP3_INVERT;
284 case VK_LOGIC_OP_OR_REVERSE:
285 return V_028808_ROP3_OR_REVERSE;
286 case VK_LOGIC_OP_COPY_INVERTED:
287 return V_028808_ROP3_COPY_INVERTED;
288 case VK_LOGIC_OP_OR_INVERTED:
289 return V_028808_ROP3_OR_INVERTED;
290 case VK_LOGIC_OP_NAND:
291 return V_028808_ROP3_NAND;
292 case VK_LOGIC_OP_SET:
293 return V_028808_ROP3_SET;
294 default:
295 unreachable("Unhandled logic op");
296 }
297 }
298
299
300 static uint32_t si_translate_blend_function(VkBlendOp op)
301 {
302 switch (op) {
303 case VK_BLEND_OP_ADD:
304 return V_028780_COMB_DST_PLUS_SRC;
305 case VK_BLEND_OP_SUBTRACT:
306 return V_028780_COMB_SRC_MINUS_DST;
307 case VK_BLEND_OP_REVERSE_SUBTRACT:
308 return V_028780_COMB_DST_MINUS_SRC;
309 case VK_BLEND_OP_MIN:
310 return V_028780_COMB_MIN_DST_SRC;
311 case VK_BLEND_OP_MAX:
312 return V_028780_COMB_MAX_DST_SRC;
313 default:
314 return 0;
315 }
316 }
317
318 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
319 {
320 switch (factor) {
321 case VK_BLEND_FACTOR_ZERO:
322 return V_028780_BLEND_ZERO;
323 case VK_BLEND_FACTOR_ONE:
324 return V_028780_BLEND_ONE;
325 case VK_BLEND_FACTOR_SRC_COLOR:
326 return V_028780_BLEND_SRC_COLOR;
327 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
328 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
329 case VK_BLEND_FACTOR_DST_COLOR:
330 return V_028780_BLEND_DST_COLOR;
331 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
332 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
333 case VK_BLEND_FACTOR_SRC_ALPHA:
334 return V_028780_BLEND_SRC_ALPHA;
335 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
336 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
337 case VK_BLEND_FACTOR_DST_ALPHA:
338 return V_028780_BLEND_DST_ALPHA;
339 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
340 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
341 case VK_BLEND_FACTOR_CONSTANT_COLOR:
342 return V_028780_BLEND_CONSTANT_COLOR;
343 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
344 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
345 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
346 return V_028780_BLEND_CONSTANT_ALPHA;
347 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
348 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
349 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
350 return V_028780_BLEND_SRC_ALPHA_SATURATE;
351 case VK_BLEND_FACTOR_SRC1_COLOR:
352 return V_028780_BLEND_SRC1_COLOR;
353 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
354 return V_028780_BLEND_INV_SRC1_COLOR;
355 case VK_BLEND_FACTOR_SRC1_ALPHA:
356 return V_028780_BLEND_SRC1_ALPHA;
357 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
358 return V_028780_BLEND_INV_SRC1_ALPHA;
359 default:
360 return 0;
361 }
362 }
363
364 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
365 {
366 switch (op) {
367 case VK_BLEND_OP_ADD:
368 return V_028760_OPT_COMB_ADD;
369 case VK_BLEND_OP_SUBTRACT:
370 return V_028760_OPT_COMB_SUBTRACT;
371 case VK_BLEND_OP_REVERSE_SUBTRACT:
372 return V_028760_OPT_COMB_REVSUBTRACT;
373 case VK_BLEND_OP_MIN:
374 return V_028760_OPT_COMB_MIN;
375 case VK_BLEND_OP_MAX:
376 return V_028760_OPT_COMB_MAX;
377 default:
378 return V_028760_OPT_COMB_BLEND_DISABLED;
379 }
380 }
381
382 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
383 {
384 switch (factor) {
385 case VK_BLEND_FACTOR_ZERO:
386 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
387 case VK_BLEND_FACTOR_ONE:
388 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
389 case VK_BLEND_FACTOR_SRC_COLOR:
390 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
391 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
392 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
393 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
394 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
395 case VK_BLEND_FACTOR_SRC_ALPHA:
396 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
397 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
398 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
399 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
400 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
401 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
402 default:
403 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
404 }
405 }
406
407 /**
408 * Get rid of DST in the blend factors by commuting the operands:
409 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
410 */
411 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
412 unsigned *dst_factor, unsigned expected_dst,
413 unsigned replacement_src)
414 {
415 if (*src_factor == expected_dst &&
416 *dst_factor == VK_BLEND_FACTOR_ZERO) {
417 *src_factor = VK_BLEND_FACTOR_ZERO;
418 *dst_factor = replacement_src;
419
420 /* Commuting the operands requires reversing subtractions. */
421 if (*func == VK_BLEND_OP_SUBTRACT)
422 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
423 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
424 *func = VK_BLEND_OP_SUBTRACT;
425 }
426 }
427
428 static bool si_blend_factor_uses_dst(unsigned factor)
429 {
430 return factor == VK_BLEND_FACTOR_DST_COLOR ||
431 factor == VK_BLEND_FACTOR_DST_ALPHA ||
432 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
433 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
434 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
435 }
436
437 static bool is_dual_src(VkBlendFactor factor)
438 {
439 switch (factor) {
440 case VK_BLEND_FACTOR_SRC1_COLOR:
441 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
442 case VK_BLEND_FACTOR_SRC1_ALPHA:
443 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
444 return true;
445 default:
446 return false;
447 }
448 }
449
450 static unsigned radv_choose_spi_color_format(VkFormat vk_format,
451 bool blend_enable,
452 bool blend_need_alpha)
453 {
454 const struct vk_format_description *desc = vk_format_description(vk_format);
455 struct ac_spi_color_formats formats = {};
456 unsigned format, ntype, swap;
457
458 format = radv_translate_colorformat(vk_format);
459 ntype = radv_translate_color_numformat(vk_format, desc,
460 vk_format_get_first_non_void_channel(vk_format));
461 swap = radv_translate_colorswap(vk_format, false);
462
463 ac_choose_spi_color_formats(format, swap, ntype, false, &formats);
464
465 if (blend_enable && blend_need_alpha)
466 return formats.blend_alpha;
467 else if(blend_need_alpha)
468 return formats.alpha;
469 else if(blend_enable)
470 return formats.blend;
471 else
472 return formats.normal;
473 }
474
475 static bool
476 format_is_int8(VkFormat format)
477 {
478 const struct vk_format_description *desc = vk_format_description(format);
479 int channel = vk_format_get_first_non_void_channel(format);
480
481 return channel >= 0 && desc->channel[channel].pure_integer &&
482 desc->channel[channel].size == 8;
483 }
484
485 static bool
486 format_is_int10(VkFormat format)
487 {
488 const struct vk_format_description *desc = vk_format_description(format);
489
490 if (desc->nr_channels != 4)
491 return false;
492 for (unsigned i = 0; i < 4; i++) {
493 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
494 return true;
495 }
496 return false;
497 }
498
499 static void
500 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
501 const VkGraphicsPipelineCreateInfo *pCreateInfo,
502 struct radv_blend_state *blend)
503 {
504 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
505 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
506 unsigned col_format = 0, is_int8 = 0, is_int10 = 0;
507 unsigned num_targets;
508
509 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
510 unsigned cf;
511
512 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED ||
513 !(blend->cb_target_mask & (0xfu << (i * 4)))) {
514 cf = V_028714_SPI_SHADER_ZERO;
515 } else {
516 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
517 bool blend_enable =
518 blend->blend_enable_4bit & (0xfu << (i * 4));
519
520 cf = radv_choose_spi_color_format(attachment->format,
521 blend_enable,
522 blend->need_src_alpha & (1 << i));
523
524 if (format_is_int8(attachment->format))
525 is_int8 |= 1 << i;
526 if (format_is_int10(attachment->format))
527 is_int10 |= 1 << i;
528 }
529
530 col_format |= cf << (4 * i);
531 }
532
533 if (!(col_format & 0xf) && blend->need_src_alpha & (1 << 0)) {
534 /* When a subpass doesn't have any color attachments, write the
535 * alpha channel of MRT0 when alpha coverage is enabled because
536 * the depth attachment needs it.
537 */
538 col_format |= V_028714_SPI_SHADER_32_AR;
539 }
540
541 /* If the i-th target format is set, all previous target formats must
542 * be non-zero to avoid hangs.
543 */
544 num_targets = (util_last_bit(col_format) + 3) / 4;
545 for (unsigned i = 0; i < num_targets; i++) {
546 if (!(col_format & (0xfu << (i * 4)))) {
547 col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
548 }
549 }
550
551 /* The output for dual source blending should have the same format as
552 * the first output.
553 */
554 if (blend->mrt0_is_dual_src)
555 col_format |= (col_format & 0xf) << 4;
556
557 blend->spi_shader_col_format = col_format;
558 blend->col_format_is_int8 = is_int8;
559 blend->col_format_is_int10 = is_int10;
560 }
561
562 /*
563 * Ordered so that for each i,
564 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
565 */
566 const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = {
567 VK_FORMAT_R32_SFLOAT,
568 VK_FORMAT_R32G32_SFLOAT,
569 VK_FORMAT_R8G8B8A8_UNORM,
570 VK_FORMAT_R16G16B16A16_UNORM,
571 VK_FORMAT_R16G16B16A16_SNORM,
572 VK_FORMAT_R16G16B16A16_UINT,
573 VK_FORMAT_R16G16B16A16_SINT,
574 VK_FORMAT_R32G32B32A32_SFLOAT,
575 VK_FORMAT_R8G8B8A8_UINT,
576 VK_FORMAT_R8G8B8A8_SINT,
577 VK_FORMAT_A2R10G10B10_UINT_PACK32,
578 VK_FORMAT_A2R10G10B10_SINT_PACK32,
579 };
580
581 unsigned radv_format_meta_fs_key(VkFormat format)
582 {
583 unsigned col_format = radv_choose_spi_color_format(format, false, false);
584
585 assert(col_format != V_028714_SPI_SHADER_32_AR);
586 if (col_format >= V_028714_SPI_SHADER_32_AR)
587 --col_format; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
588
589 --col_format; /* Skip V_028714_SPI_SHADER_ZERO */
590 bool is_int8 = format_is_int8(format);
591 bool is_int10 = format_is_int10(format);
592
593 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
594 }
595
596 static void
597 radv_blend_check_commutativity(struct radv_blend_state *blend,
598 VkBlendOp op, VkBlendFactor src,
599 VkBlendFactor dst, unsigned chanmask)
600 {
601 /* Src factor is allowed when it does not depend on Dst. */
602 static const uint32_t src_allowed =
603 (1u << VK_BLEND_FACTOR_ONE) |
604 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
605 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
606 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
607 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
608 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
609 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
610 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
611 (1u << VK_BLEND_FACTOR_ZERO) |
612 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
613 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
614 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
615 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
616 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
617 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
618
619 if (dst == VK_BLEND_FACTOR_ONE &&
620 (src_allowed & (1u << src))) {
621 /* Addition is commutative, but floating point addition isn't
622 * associative: subtle changes can be introduced via different
623 * rounding. Be conservative, only enable for min and max.
624 */
625 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
626 blend->commutative_4bit |= chanmask;
627 }
628 }
629
630 static struct radv_blend_state
631 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
632 const VkGraphicsPipelineCreateInfo *pCreateInfo,
633 const struct radv_graphics_pipeline_create_info *extra)
634 {
635 const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
636 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
637 struct radv_blend_state blend = {0};
638 unsigned mode = V_028808_CB_NORMAL;
639 int i;
640
641 if (extra && extra->custom_blend_mode) {
642 blend.single_cb_enable = true;
643 mode = extra->custom_blend_mode;
644 }
645
646 blend.cb_color_control = 0;
647 if (vkblend) {
648 if (vkblend->logicOpEnable)
649 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
650 else
651 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
652 }
653
654 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
655 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
656 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
657 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
658 S_028B70_OFFSET_ROUND(1);
659
660 if (vkms && vkms->alphaToCoverageEnable) {
661 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
662 blend.need_src_alpha |= 0x1;
663 }
664
665 blend.cb_target_mask = 0;
666 if (vkblend) {
667 for (i = 0; i < vkblend->attachmentCount; i++) {
668 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
669 unsigned blend_cntl = 0;
670 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
671 VkBlendOp eqRGB = att->colorBlendOp;
672 VkBlendFactor srcRGB = att->srcColorBlendFactor;
673 VkBlendFactor dstRGB = att->dstColorBlendFactor;
674 VkBlendOp eqA = att->alphaBlendOp;
675 VkBlendFactor srcA = att->srcAlphaBlendFactor;
676 VkBlendFactor dstA = att->dstAlphaBlendFactor;
677
678 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
679
680 if (!att->colorWriteMask)
681 continue;
682
683 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
684 blend.cb_target_enabled_4bit |= 0xfu << (4 * i);
685 if (!att->blendEnable) {
686 blend.cb_blend_control[i] = blend_cntl;
687 continue;
688 }
689
690 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
691 if (i == 0)
692 blend.mrt0_is_dual_src = true;
693
694 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
695 srcRGB = VK_BLEND_FACTOR_ONE;
696 dstRGB = VK_BLEND_FACTOR_ONE;
697 }
698 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
699 srcA = VK_BLEND_FACTOR_ONE;
700 dstA = VK_BLEND_FACTOR_ONE;
701 }
702
703 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
704 0x7u << (4 * i));
705 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
706 0x8u << (4 * i));
707
708 /* Blending optimizations for RB+.
709 * These transformations don't change the behavior.
710 *
711 * First, get rid of DST in the blend factors:
712 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
713 */
714 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
715 VK_BLEND_FACTOR_DST_COLOR,
716 VK_BLEND_FACTOR_SRC_COLOR);
717
718 si_blend_remove_dst(&eqA, &srcA, &dstA,
719 VK_BLEND_FACTOR_DST_COLOR,
720 VK_BLEND_FACTOR_SRC_COLOR);
721
722 si_blend_remove_dst(&eqA, &srcA, &dstA,
723 VK_BLEND_FACTOR_DST_ALPHA,
724 VK_BLEND_FACTOR_SRC_ALPHA);
725
726 /* Look up the ideal settings from tables. */
727 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
728 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
729 srcA_opt = si_translate_blend_opt_factor(srcA, true);
730 dstA_opt = si_translate_blend_opt_factor(dstA, true);
731
732 /* Handle interdependencies. */
733 if (si_blend_factor_uses_dst(srcRGB))
734 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
735 if (si_blend_factor_uses_dst(srcA))
736 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
737
738 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
739 (dstRGB == VK_BLEND_FACTOR_ZERO ||
740 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
741 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
742 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
743
744 /* Set the final value. */
745 blend.sx_mrt_blend_opt[i] =
746 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
747 S_028760_COLOR_DST_OPT(dstRGB_opt) |
748 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
749 S_028760_ALPHA_SRC_OPT(srcA_opt) |
750 S_028760_ALPHA_DST_OPT(dstA_opt) |
751 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
752 blend_cntl |= S_028780_ENABLE(1);
753
754 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
755 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
756 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
757 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
758 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
759 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
760 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
761 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
762 }
763 blend.cb_blend_control[i] = blend_cntl;
764
765 blend.blend_enable_4bit |= 0xfu << (i * 4);
766
767 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
768 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
769 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
770 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
771 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
772 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
773 blend.need_src_alpha |= 1 << i;
774 }
775 for (i = vkblend->attachmentCount; i < 8; i++) {
776 blend.cb_blend_control[i] = 0;
777 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
778 }
779 }
780
781 if (pipeline->device->physical_device->rad_info.has_rbplus) {
782 /* Disable RB+ blend optimizations for dual source blending. */
783 if (blend.mrt0_is_dual_src) {
784 for (i = 0; i < 8; i++) {
785 blend.sx_mrt_blend_opt[i] =
786 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
787 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
788 }
789 }
790
791 /* RB+ doesn't work with dual source blending, logic op and
792 * RESOLVE.
793 */
794 if (blend.mrt0_is_dual_src ||
795 (vkblend && vkblend->logicOpEnable) ||
796 mode == V_028808_CB_RESOLVE)
797 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
798 }
799
800 if (blend.cb_target_mask)
801 blend.cb_color_control |= S_028808_MODE(mode);
802 else
803 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
804
805 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
806 return blend;
807 }
808
809 static uint32_t si_translate_fill(VkPolygonMode func)
810 {
811 switch(func) {
812 case VK_POLYGON_MODE_FILL:
813 return V_028814_X_DRAW_TRIANGLES;
814 case VK_POLYGON_MODE_LINE:
815 return V_028814_X_DRAW_LINES;
816 case VK_POLYGON_MODE_POINT:
817 return V_028814_X_DRAW_POINTS;
818 default:
819 assert(0);
820 return V_028814_X_DRAW_POINTS;
821 }
822 }
823
824 static uint8_t radv_pipeline_get_ps_iter_samples(const VkGraphicsPipelineCreateInfo *pCreateInfo)
825 {
826 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
827 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
828 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
829 uint32_t ps_iter_samples = 1;
830 uint32_t num_samples;
831
832 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
833 *
834 * "If the VK_AMD_mixed_attachment_samples extension is enabled and the
835 * subpass uses color attachments, totalSamples is the number of
836 * samples of the color attachments. Otherwise, totalSamples is the
837 * value of VkPipelineMultisampleStateCreateInfo::rasterizationSamples
838 * specified at pipeline creation time."
839 */
840 if (subpass->has_color_att) {
841 num_samples = subpass->color_sample_count;
842 } else {
843 num_samples = vkms->rasterizationSamples;
844 }
845
846 if (vkms->sampleShadingEnable) {
847 ps_iter_samples = ceilf(vkms->minSampleShading * num_samples);
848 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
849 }
850 return ps_iter_samples;
851 }
852
853 static bool
854 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
855 {
856 return pCreateInfo->depthTestEnable &&
857 pCreateInfo->depthWriteEnable &&
858 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
859 }
860
861 static bool
862 radv_writes_stencil(const VkStencilOpState *state)
863 {
864 return state->writeMask &&
865 (state->failOp != VK_STENCIL_OP_KEEP ||
866 state->passOp != VK_STENCIL_OP_KEEP ||
867 state->depthFailOp != VK_STENCIL_OP_KEEP);
868 }
869
870 static bool
871 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
872 {
873 return pCreateInfo->stencilTestEnable &&
874 (radv_writes_stencil(&pCreateInfo->front) ||
875 radv_writes_stencil(&pCreateInfo->back));
876 }
877
878 static bool
879 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
880 {
881 return radv_is_depth_write_enabled(pCreateInfo) ||
882 radv_is_stencil_write_enabled(pCreateInfo);
883 }
884
885 static bool
886 radv_order_invariant_stencil_op(VkStencilOp op)
887 {
888 /* REPLACE is normally order invariant, except when the stencil
889 * reference value is written by the fragment shader. Tracking this
890 * interaction does not seem worth the effort, so be conservative.
891 */
892 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
893 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
894 op != VK_STENCIL_OP_REPLACE;
895 }
896
897 static bool
898 radv_order_invariant_stencil_state(const VkStencilOpState *state)
899 {
900 /* Compute whether, assuming Z writes are disabled, this stencil state
901 * is order invariant in the sense that the set of passing fragments as
902 * well as the final stencil buffer result does not depend on the order
903 * of fragments.
904 */
905 return !state->writeMask ||
906 /* The following assumes that Z writes are disabled. */
907 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
908 radv_order_invariant_stencil_op(state->passOp) &&
909 radv_order_invariant_stencil_op(state->depthFailOp)) ||
910 (state->compareOp == VK_COMPARE_OP_NEVER &&
911 radv_order_invariant_stencil_op(state->failOp));
912 }
913
914 static bool
915 radv_pipeline_has_dynamic_ds_states(const VkGraphicsPipelineCreateInfo *pCreateInfo)
916 {
917 VkDynamicState ds_states[] = {
918 VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT,
919 VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT,
920 VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT,
921 VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT,
922 VK_DYNAMIC_STATE_STENCIL_OP_EXT,
923 };
924
925 if (pCreateInfo->pDynamicState) {
926 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
927 for (uint32_t i = 0; i < count; i++) {
928 for (uint32_t j = 0; j < ARRAY_SIZE(ds_states); j++) {
929 if (pCreateInfo->pDynamicState->pDynamicStates[i] == ds_states[j])
930 return true;
931 }
932 }
933 }
934
935 return false;
936 }
937
938 static bool
939 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
940 struct radv_blend_state *blend,
941 const VkGraphicsPipelineCreateInfo *pCreateInfo)
942 {
943 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
944 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
945 const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
946 const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
947 unsigned colormask = blend->cb_target_enabled_4bit;
948
949 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
950 return false;
951
952 /* Be conservative if a logic operation is enabled with color buffers. */
953 if (colormask && vkblend && vkblend->logicOpEnable)
954 return false;
955
956 /* Be conservative if an extended dynamic depth/stencil state is
957 * enabled because the driver can't update out-of-order rasterization
958 * dynamically.
959 */
960 if (radv_pipeline_has_dynamic_ds_states(pCreateInfo))
961 return false;
962
963 /* Default depth/stencil invariance when no attachment is bound. */
964 struct radv_dsa_order_invariance dsa_order_invariant = {
965 .zs = true, .pass_set = true
966 };
967
968 if (vkds) {
969 struct radv_render_pass_attachment *attachment =
970 pass->attachments + subpass->depth_stencil_attachment->attachment;
971 bool has_stencil = vk_format_is_stencil(attachment->format);
972 struct radv_dsa_order_invariance order_invariance[2];
973 struct radv_shader_variant *ps =
974 pipeline->shaders[MESA_SHADER_FRAGMENT];
975
976 /* Compute depth/stencil order invariance in order to know if
977 * it's safe to enable out-of-order.
978 */
979 bool zfunc_is_ordered =
980 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
981 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
982 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
983 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
984 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
985
986 bool nozwrite_and_order_invariant_stencil =
987 !radv_is_ds_write_enabled(vkds) ||
988 (!radv_is_depth_write_enabled(vkds) &&
989 radv_order_invariant_stencil_state(&vkds->front) &&
990 radv_order_invariant_stencil_state(&vkds->back));
991
992 order_invariance[1].zs =
993 nozwrite_and_order_invariant_stencil ||
994 (!radv_is_stencil_write_enabled(vkds) &&
995 zfunc_is_ordered);
996 order_invariance[0].zs =
997 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
998
999 order_invariance[1].pass_set =
1000 nozwrite_and_order_invariant_stencil ||
1001 (!radv_is_stencil_write_enabled(vkds) &&
1002 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1003 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
1004 order_invariance[0].pass_set =
1005 !radv_is_depth_write_enabled(vkds) ||
1006 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1007 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
1008
1009 dsa_order_invariant = order_invariance[has_stencil];
1010 if (!dsa_order_invariant.zs)
1011 return false;
1012
1013 /* The set of PS invocations is always order invariant,
1014 * except when early Z/S tests are requested.
1015 */
1016 if (ps &&
1017 ps->info.ps.writes_memory &&
1018 ps->info.ps.early_fragment_test &&
1019 !dsa_order_invariant.pass_set)
1020 return false;
1021
1022 /* Determine if out-of-order rasterization should be disabled
1023 * when occlusion queries are used.
1024 */
1025 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
1026 !dsa_order_invariant.pass_set;
1027 }
1028
1029 /* No color buffers are enabled for writing. */
1030 if (!colormask)
1031 return true;
1032
1033 unsigned blendmask = colormask & blend->blend_enable_4bit;
1034
1035 if (blendmask) {
1036 /* Only commutative blending. */
1037 if (blendmask & ~blend->commutative_4bit)
1038 return false;
1039
1040 if (!dsa_order_invariant.pass_set)
1041 return false;
1042 }
1043
1044 if (colormask & ~blendmask)
1045 return false;
1046
1047 return true;
1048 }
1049
1050 static const VkConservativeRasterizationModeEXT
1051 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo)
1052 {
1053 const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster =
1054 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT);
1055
1056 if (!conservative_raster)
1057 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT;
1058 return conservative_raster->conservativeRasterizationMode;
1059 }
1060
1061 static void
1062 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1063 struct radv_blend_state *blend,
1064 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1065 {
1066 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
1067 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1068 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1069 const VkConservativeRasterizationModeEXT mode =
1070 radv_get_conservative_raster_mode(pCreateInfo->pRasterizationState);
1071 bool out_of_order_rast = false;
1072 int ps_iter_samples = 1;
1073 uint32_t mask = 0xffff;
1074
1075 if (vkms) {
1076 ms->num_samples = vkms->rasterizationSamples;
1077
1078 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1079 *
1080 * "Sample shading is enabled for a graphics pipeline:
1081 *
1082 * - If the interface of the fragment shader entry point of the
1083 * graphics pipeline includes an input variable decorated
1084 * with SampleId or SamplePosition. In this case
1085 * minSampleShadingFactor takes the value 1.0.
1086 * - Else if the sampleShadingEnable member of the
1087 * VkPipelineMultisampleStateCreateInfo structure specified
1088 * when creating the graphics pipeline is set to VK_TRUE. In
1089 * this case minSampleShadingFactor takes the value of
1090 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1091 *
1092 * Otherwise, sample shading is considered disabled."
1093 */
1094 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.force_persample) {
1095 ps_iter_samples = ms->num_samples;
1096 } else {
1097 ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
1098 }
1099 } else {
1100 ms->num_samples = 1;
1101 }
1102
1103 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1104 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1105 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1106 /* Out-of-order rasterization is explicitly enabled by the
1107 * application.
1108 */
1109 out_of_order_rast = true;
1110 } else {
1111 /* Determine if the driver can enable out-of-order
1112 * rasterization internally.
1113 */
1114 out_of_order_rast =
1115 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1116 }
1117
1118 ms->pa_sc_aa_config = 0;
1119 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1120 S_028804_INCOHERENT_EQAA_READS(1) |
1121 S_028804_INTERPOLATE_COMP_Z(1) |
1122 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1123
1124 /* Adjust MSAA state if conservative rasterization is enabled. */
1125 if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
1126 ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1);
1127
1128 ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
1129 S_028804_OVERRASTERIZATION_AMOUNT(4);
1130 }
1131
1132 ms->pa_sc_mode_cntl_1 =
1133 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1134 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1135 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
1136 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1137 /* always 1: */
1138 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1139 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1140 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1141 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1142 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1143 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1144 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1145 S_028A48_VPORT_SCISSOR_ENABLE(1);
1146
1147 const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line =
1148 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1149 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
1150 if (rast_line) {
1151 ms->pa_sc_mode_cntl_0 |= S_028A48_LINE_STIPPLE_ENABLE(rast_line->stippledLineEnable);
1152 if (rast_line->lineRasterizationMode == VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT) {
1153 /* From the Vulkan spec 1.1.129:
1154 *
1155 * "When VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT lines
1156 * are being rasterized, sample locations may all be
1157 * treated as being at the pixel center (this may
1158 * affect attribute and depth interpolation)."
1159 */
1160 ms->num_samples = 1;
1161 }
1162 }
1163
1164 if (ms->num_samples > 1) {
1165 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1166 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1167 uint32_t z_samples = subpass->depth_stencil_attachment ? subpass->depth_sample_count : ms->num_samples;
1168 unsigned log_samples = util_logbase2(ms->num_samples);
1169 unsigned log_z_samples = util_logbase2(z_samples);
1170 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1171 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1172 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
1173 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1174 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1175 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1176 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1177 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) |
1178 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples) | /* CM_R_028BE0_PA_SC_AA_CONFIG */
1179 S_028BE0_COVERED_CENTROID_IS_CENTER(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3);
1180 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1181 if (ps_iter_samples > 1)
1182 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1183 }
1184
1185 if (vkms && vkms->pSampleMask) {
1186 mask = vkms->pSampleMask[0] & 0xffff;
1187 }
1188
1189 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1190 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1191 }
1192
1193 static bool
1194 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1195 {
1196 switch (topology) {
1197 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1198 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1199 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1200 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1201 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1202 return false;
1203 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1204 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1205 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1206 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1207 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1208 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1209 return true;
1210 default:
1211 unreachable("unhandled primitive type");
1212 }
1213 }
1214
1215 static uint32_t
1216 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1217 {
1218 switch (gl_prim) {
1219 case 0: /* GL_POINTS */
1220 return V_028A6C_POINTLIST;
1221 case 1: /* GL_LINES */
1222 case 3: /* GL_LINE_STRIP */
1223 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1224 case 0x8E7A: /* GL_ISOLINES */
1225 return V_028A6C_LINESTRIP;
1226
1227 case 4: /* GL_TRIANGLES */
1228 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1229 case 5: /* GL_TRIANGLE_STRIP */
1230 case 7: /* GL_QUADS */
1231 return V_028A6C_TRISTRIP;
1232 default:
1233 assert(0);
1234 return 0;
1235 }
1236 }
1237
1238 static uint32_t
1239 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1240 {
1241 switch (topology) {
1242 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1243 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1244 return V_028A6C_POINTLIST;
1245 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1246 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1247 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1248 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1249 return V_028A6C_LINESTRIP;
1250 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1251 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1252 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1253 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1254 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1255 return V_028A6C_TRISTRIP;
1256 default:
1257 assert(0);
1258 return 0;
1259 }
1260 }
1261
1262 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1263 {
1264 switch(state) {
1265 case VK_DYNAMIC_STATE_VIEWPORT:
1266 case VK_DYNAMIC_STATE_VIEWPORT_WITH_COUNT_EXT:
1267 return RADV_DYNAMIC_VIEWPORT;
1268 case VK_DYNAMIC_STATE_SCISSOR:
1269 case VK_DYNAMIC_STATE_SCISSOR_WITH_COUNT_EXT:
1270 return RADV_DYNAMIC_SCISSOR;
1271 case VK_DYNAMIC_STATE_LINE_WIDTH:
1272 return RADV_DYNAMIC_LINE_WIDTH;
1273 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1274 return RADV_DYNAMIC_DEPTH_BIAS;
1275 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1276 return RADV_DYNAMIC_BLEND_CONSTANTS;
1277 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1278 return RADV_DYNAMIC_DEPTH_BOUNDS;
1279 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1280 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1281 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1282 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1283 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1284 return RADV_DYNAMIC_STENCIL_REFERENCE;
1285 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1286 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1287 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
1288 return RADV_DYNAMIC_SAMPLE_LOCATIONS;
1289 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT:
1290 return RADV_DYNAMIC_LINE_STIPPLE;
1291 case VK_DYNAMIC_STATE_CULL_MODE_EXT:
1292 return RADV_DYNAMIC_CULL_MODE;
1293 case VK_DYNAMIC_STATE_FRONT_FACE_EXT:
1294 return RADV_DYNAMIC_FRONT_FACE;
1295 case VK_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY_EXT:
1296 return RADV_DYNAMIC_PRIMITIVE_TOPOLOGY;
1297 case VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT:
1298 return RADV_DYNAMIC_DEPTH_TEST_ENABLE;
1299 case VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT:
1300 return RADV_DYNAMIC_DEPTH_WRITE_ENABLE;
1301 case VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT:
1302 return RADV_DYNAMIC_DEPTH_COMPARE_OP;
1303 case VK_DYNAMIC_STATE_DEPTH_BOUNDS_TEST_ENABLE_EXT:
1304 return RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE;
1305 case VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT:
1306 return RADV_DYNAMIC_STENCIL_TEST_ENABLE;
1307 case VK_DYNAMIC_STATE_STENCIL_OP_EXT:
1308 return RADV_DYNAMIC_STENCIL_OP;
1309 case VK_DYNAMIC_STATE_VERTEX_INPUT_BINDING_STRIDE_EXT:
1310 return RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE;
1311 default:
1312 unreachable("Unhandled dynamic state");
1313 }
1314 }
1315
1316 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1317 {
1318 uint32_t states = RADV_DYNAMIC_ALL;
1319
1320 /* If rasterization is disabled we do not care about any of the
1321 * dynamic states, since they are all rasterization related only,
1322 * except primitive topology and vertex binding stride.
1323 */
1324 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1325 return RADV_DYNAMIC_PRIMITIVE_TOPOLOGY |
1326 RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE;
1327
1328 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1329 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1330
1331 if (!pCreateInfo->pDepthStencilState ||
1332 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1333 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1334
1335 if (!pCreateInfo->pDepthStencilState ||
1336 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1337 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1338 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1339 RADV_DYNAMIC_STENCIL_REFERENCE);
1340
1341 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1342 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1343
1344 if (!pCreateInfo->pMultisampleState ||
1345 !vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1346 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT))
1347 states &= ~RADV_DYNAMIC_SAMPLE_LOCATIONS;
1348
1349 if (!pCreateInfo->pRasterizationState ||
1350 !vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1351 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT))
1352 states &= ~RADV_DYNAMIC_LINE_STIPPLE;
1353
1354 /* TODO: blend constants & line width. */
1355
1356 return states;
1357 }
1358
1359 static struct radv_ia_multi_vgt_param_helpers
1360 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline)
1361 {
1362 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
1363 const struct radv_device *device = pipeline->device;
1364
1365 if (radv_pipeline_has_tess(pipeline))
1366 ia_multi_vgt_param.primgroup_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1367 else if (radv_pipeline_has_gs(pipeline))
1368 ia_multi_vgt_param.primgroup_size = 64;
1369 else
1370 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
1371
1372 /* GS requirement. */
1373 ia_multi_vgt_param.partial_es_wave = false;
1374 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= GFX8)
1375 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
1376 ia_multi_vgt_param.partial_es_wave = true;
1377
1378 ia_multi_vgt_param.ia_switch_on_eoi = false;
1379 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input)
1380 ia_multi_vgt_param.ia_switch_on_eoi = true;
1381 if (radv_pipeline_has_gs(pipeline) &&
1382 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.uses_prim_id)
1383 ia_multi_vgt_param.ia_switch_on_eoi = true;
1384 if (radv_pipeline_has_tess(pipeline)) {
1385 /* SWITCH_ON_EOI must be set if PrimID is used. */
1386 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
1387 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
1388 ia_multi_vgt_param.ia_switch_on_eoi = true;
1389 }
1390
1391 ia_multi_vgt_param.partial_vs_wave = false;
1392 if (radv_pipeline_has_tess(pipeline)) {
1393 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
1394 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
1395 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
1396 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
1397 radv_pipeline_has_gs(pipeline))
1398 ia_multi_vgt_param.partial_vs_wave = true;
1399 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
1400 if (device->physical_device->rad_info.has_distributed_tess) {
1401 if (radv_pipeline_has_gs(pipeline)) {
1402 if (device->physical_device->rad_info.chip_class <= GFX8)
1403 ia_multi_vgt_param.partial_es_wave = true;
1404 } else {
1405 ia_multi_vgt_param.partial_vs_wave = true;
1406 }
1407 }
1408 }
1409
1410 if (radv_pipeline_has_gs(pipeline)) {
1411 /* On these chips there is the possibility of a hang if the
1412 * pipeline uses a GS and partial_vs_wave is not set.
1413 *
1414 * This mostly does not hit 4-SE chips, as those typically set
1415 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
1416 * with GS due to another workaround.
1417 *
1418 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
1419 */
1420 if (device->physical_device->rad_info.family == CHIP_TONGA ||
1421 device->physical_device->rad_info.family == CHIP_FIJI ||
1422 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
1423 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
1424 device->physical_device->rad_info.family == CHIP_POLARIS12 ||
1425 device->physical_device->rad_info.family == CHIP_VEGAM) {
1426 ia_multi_vgt_param.partial_vs_wave = true;
1427 }
1428 }
1429
1430 ia_multi_vgt_param.base =
1431 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
1432 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
1433 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == GFX8 ? 2 : 0) |
1434 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
1435 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
1436
1437 return ia_multi_vgt_param;
1438 }
1439
1440 static void
1441 radv_pipeline_init_input_assembly_state(struct radv_pipeline *pipeline,
1442 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1443 const struct radv_graphics_pipeline_create_info *extra)
1444 {
1445 const VkPipelineInputAssemblyStateCreateInfo *ia_state = pCreateInfo->pInputAssemblyState;
1446 struct radv_shader_variant *tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
1447 struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
1448
1449 pipeline->graphics.prim_restart_enable = !!ia_state->primitiveRestartEnable;
1450 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(ia_state->topology);
1451
1452 if (radv_pipeline_has_gs(pipeline)) {
1453 if (si_conv_gl_prim_to_gs_out(gs->info.gs.output_prim) == V_028A6C_TRISTRIP)
1454 pipeline->graphics.can_use_guardband = true;
1455 } else if (radv_pipeline_has_tess(pipeline)) {
1456 if (!tes->info.tes.point_mode &&
1457 si_conv_gl_prim_to_gs_out(tes->info.tes.primitive_mode) == V_028A6C_TRISTRIP)
1458 pipeline->graphics.can_use_guardband = true;
1459 }
1460
1461 if (extra && extra->use_rectlist) {
1462 pipeline->graphics.can_use_guardband = true;
1463 }
1464
1465 pipeline->graphics.ia_multi_vgt_param =
1466 radv_compute_ia_multi_vgt_param_helpers(pipeline);
1467 }
1468
1469 static void
1470 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1471 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1472 const struct radv_graphics_pipeline_create_info *extra)
1473 {
1474 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1475 uint32_t states = needed_states;
1476 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1477 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1478
1479 pipeline->dynamic_state = default_dynamic_state;
1480 pipeline->graphics.needed_dynamic_state = needed_states;
1481
1482 if (pCreateInfo->pDynamicState) {
1483 /* Remove all of the states that are marked as dynamic */
1484 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1485 for (uint32_t s = 0; s < count; s++)
1486 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1487 }
1488
1489 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1490
1491 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1492 assert(pCreateInfo->pViewportState);
1493
1494 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1495 if (states & RADV_DYNAMIC_VIEWPORT) {
1496 typed_memcpy(dynamic->viewport.viewports,
1497 pCreateInfo->pViewportState->pViewports,
1498 pCreateInfo->pViewportState->viewportCount);
1499 }
1500 }
1501
1502 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1503 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1504 if (states & RADV_DYNAMIC_SCISSOR) {
1505 typed_memcpy(dynamic->scissor.scissors,
1506 pCreateInfo->pViewportState->pScissors,
1507 pCreateInfo->pViewportState->scissorCount);
1508 }
1509 }
1510
1511 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1512 assert(pCreateInfo->pRasterizationState);
1513 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1514 }
1515
1516 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1517 assert(pCreateInfo->pRasterizationState);
1518 dynamic->depth_bias.bias =
1519 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1520 dynamic->depth_bias.clamp =
1521 pCreateInfo->pRasterizationState->depthBiasClamp;
1522 dynamic->depth_bias.slope =
1523 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1524 }
1525
1526 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1527 *
1528 * pColorBlendState is [...] NULL if the pipeline has rasterization
1529 * disabled or if the subpass of the render pass the pipeline is
1530 * created against does not use any color attachments.
1531 */
1532 if (subpass->has_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1533 assert(pCreateInfo->pColorBlendState);
1534 typed_memcpy(dynamic->blend_constants,
1535 pCreateInfo->pColorBlendState->blendConstants, 4);
1536 }
1537
1538 if (states & RADV_DYNAMIC_CULL_MODE) {
1539 dynamic->cull_mode =
1540 pCreateInfo->pRasterizationState->cullMode;
1541 }
1542
1543 if (states & RADV_DYNAMIC_FRONT_FACE) {
1544 dynamic->front_face =
1545 pCreateInfo->pRasterizationState->frontFace;
1546 }
1547
1548 if (states & RADV_DYNAMIC_PRIMITIVE_TOPOLOGY) {
1549 dynamic->primitive_topology =
1550 si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
1551 if (extra && extra->use_rectlist) {
1552 dynamic->primitive_topology = V_008958_DI_PT_RECTLIST;
1553 }
1554 }
1555
1556 /* If there is no depthstencil attachment, then don't read
1557 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1558 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1559 * no need to override the depthstencil defaults in
1560 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1561 *
1562 * Section 9.2 of the Vulkan 1.0.15 spec says:
1563 *
1564 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1565 * disabled or if the subpass of the render pass the pipeline is created
1566 * against does not use a depth/stencil attachment.
1567 */
1568 if (needed_states && subpass->depth_stencil_attachment) {
1569 assert(pCreateInfo->pDepthStencilState);
1570
1571 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1572 dynamic->depth_bounds.min =
1573 pCreateInfo->pDepthStencilState->minDepthBounds;
1574 dynamic->depth_bounds.max =
1575 pCreateInfo->pDepthStencilState->maxDepthBounds;
1576 }
1577
1578 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1579 dynamic->stencil_compare_mask.front =
1580 pCreateInfo->pDepthStencilState->front.compareMask;
1581 dynamic->stencil_compare_mask.back =
1582 pCreateInfo->pDepthStencilState->back.compareMask;
1583 }
1584
1585 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1586 dynamic->stencil_write_mask.front =
1587 pCreateInfo->pDepthStencilState->front.writeMask;
1588 dynamic->stencil_write_mask.back =
1589 pCreateInfo->pDepthStencilState->back.writeMask;
1590 }
1591
1592 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1593 dynamic->stencil_reference.front =
1594 pCreateInfo->pDepthStencilState->front.reference;
1595 dynamic->stencil_reference.back =
1596 pCreateInfo->pDepthStencilState->back.reference;
1597 }
1598
1599 if (states & RADV_DYNAMIC_DEPTH_TEST_ENABLE) {
1600 dynamic->depth_test_enable =
1601 pCreateInfo->pDepthStencilState->depthTestEnable;
1602 }
1603
1604 if (states & RADV_DYNAMIC_DEPTH_WRITE_ENABLE) {
1605 dynamic->depth_write_enable =
1606 pCreateInfo->pDepthStencilState->depthWriteEnable;
1607 }
1608
1609 if (states & RADV_DYNAMIC_DEPTH_COMPARE_OP) {
1610 dynamic->depth_compare_op =
1611 pCreateInfo->pDepthStencilState->depthCompareOp;
1612 }
1613
1614 if (states & RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE) {
1615 dynamic->depth_bounds_test_enable =
1616 pCreateInfo->pDepthStencilState->depthBoundsTestEnable;
1617 }
1618
1619 if (states & RADV_DYNAMIC_STENCIL_TEST_ENABLE) {
1620 dynamic->stencil_test_enable =
1621 pCreateInfo->pDepthStencilState->stencilTestEnable;
1622 }
1623
1624 if (states & RADV_DYNAMIC_STENCIL_OP) {
1625 dynamic->stencil_op.front.compare_op =
1626 pCreateInfo->pDepthStencilState->front.compareOp;
1627 dynamic->stencil_op.front.fail_op =
1628 pCreateInfo->pDepthStencilState->front.failOp;
1629 dynamic->stencil_op.front.pass_op =
1630 pCreateInfo->pDepthStencilState->front.passOp;
1631 dynamic->stencil_op.front.depth_fail_op =
1632 pCreateInfo->pDepthStencilState->front.depthFailOp;
1633
1634 dynamic->stencil_op.back.compare_op =
1635 pCreateInfo->pDepthStencilState->back.compareOp;
1636 dynamic->stencil_op.back.fail_op =
1637 pCreateInfo->pDepthStencilState->back.failOp;
1638 dynamic->stencil_op.back.pass_op =
1639 pCreateInfo->pDepthStencilState->back.passOp;
1640 dynamic->stencil_op.back.depth_fail_op =
1641 pCreateInfo->pDepthStencilState->back.depthFailOp;
1642 }
1643 }
1644
1645 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1646 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1647 if (needed_states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1648 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1649 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1650 typed_memcpy(dynamic->discard_rectangle.rectangles,
1651 discard_rectangle_info->pDiscardRectangles,
1652 discard_rectangle_info->discardRectangleCount);
1653 }
1654 }
1655
1656 if (needed_states & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
1657 const VkPipelineSampleLocationsStateCreateInfoEXT *sample_location_info =
1658 vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1659 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1660 /* If sampleLocationsEnable is VK_FALSE, the default sample
1661 * locations are used and the values specified in
1662 * sampleLocationsInfo are ignored.
1663 */
1664 if (sample_location_info->sampleLocationsEnable) {
1665 const VkSampleLocationsInfoEXT *pSampleLocationsInfo =
1666 &sample_location_info->sampleLocationsInfo;
1667
1668 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
1669
1670 dynamic->sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
1671 dynamic->sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
1672 dynamic->sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
1673 typed_memcpy(&dynamic->sample_location.locations[0],
1674 pSampleLocationsInfo->pSampleLocations,
1675 pSampleLocationsInfo->sampleLocationsCount);
1676 }
1677 }
1678
1679 const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line_info =
1680 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1681 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
1682 if (needed_states & RADV_DYNAMIC_LINE_STIPPLE) {
1683 dynamic->line_stipple.factor = rast_line_info->lineStippleFactor;
1684 dynamic->line_stipple.pattern = rast_line_info->lineStipplePattern;
1685 }
1686
1687 if (!(states & RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE))
1688 pipeline->graphics.uses_dynamic_stride = true;
1689
1690 pipeline->dynamic_state.mask = states;
1691 }
1692
1693 static void
1694 radv_pipeline_init_raster_state(struct radv_pipeline *pipeline,
1695 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1696 {
1697 const VkPipelineRasterizationStateCreateInfo *raster_info =
1698 pCreateInfo->pRasterizationState;
1699
1700 pipeline->graphics.pa_su_sc_mode_cntl =
1701 S_028814_FACE(raster_info->frontFace) |
1702 S_028814_CULL_FRONT(!!(raster_info->cullMode & VK_CULL_MODE_FRONT_BIT)) |
1703 S_028814_CULL_BACK(!!(raster_info->cullMode & VK_CULL_MODE_BACK_BIT)) |
1704 S_028814_POLY_MODE(raster_info->polygonMode != VK_POLYGON_MODE_FILL) |
1705 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(raster_info->polygonMode)) |
1706 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(raster_info->polygonMode)) |
1707 S_028814_POLY_OFFSET_FRONT_ENABLE(raster_info->depthBiasEnable ? 1 : 0) |
1708 S_028814_POLY_OFFSET_BACK_ENABLE(raster_info->depthBiasEnable ? 1 : 0) |
1709 S_028814_POLY_OFFSET_PARA_ENABLE(raster_info->depthBiasEnable ? 1 : 0);
1710 }
1711
1712 static void
1713 radv_pipeline_init_depth_stencil_state(struct radv_pipeline *pipeline,
1714 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1715 {
1716 const VkPipelineDepthStencilStateCreateInfo *ds_info
1717 = radv_pipeline_get_depth_stencil_state(pCreateInfo);
1718 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1719 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1720 struct radv_render_pass_attachment *attachment = NULL;
1721 uint32_t db_depth_control = 0;
1722
1723 if (subpass->depth_stencil_attachment)
1724 attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
1725
1726 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
1727 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
1728
1729 if (ds_info) {
1730 if (has_depth_attachment) {
1731 db_depth_control = S_028800_Z_ENABLE(ds_info->depthTestEnable ? 1 : 0) |
1732 S_028800_Z_WRITE_ENABLE(ds_info->depthWriteEnable ? 1 : 0) |
1733 S_028800_ZFUNC(ds_info->depthCompareOp) |
1734 S_028800_DEPTH_BOUNDS_ENABLE(ds_info->depthBoundsTestEnable ? 1 : 0);
1735 }
1736
1737 if (has_stencil_attachment && ds_info->stencilTestEnable) {
1738 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
1739 db_depth_control |= S_028800_STENCILFUNC(ds_info->front.compareOp);
1740 db_depth_control |= S_028800_STENCILFUNC_BF(ds_info->back.compareOp);
1741 }
1742 }
1743
1744 pipeline->graphics.db_depth_control = db_depth_control;
1745 }
1746
1747 static void
1748 gfx9_get_gs_info(const struct radv_pipeline_key *key,
1749 const struct radv_pipeline *pipeline,
1750 nir_shader **nir,
1751 struct radv_shader_info *infos,
1752 struct gfx9_gs_info *out)
1753 {
1754 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1755 struct radv_es_output_info *es_info;
1756 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1757 es_info = nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1758 else
1759 es_info = nir[MESA_SHADER_TESS_CTRL] ?
1760 &infos[MESA_SHADER_TESS_EVAL].tes.es_info :
1761 &infos[MESA_SHADER_VERTEX].vs.es_info;
1762
1763 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1764 bool uses_adjacency;
1765 switch(key->topology) {
1766 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1767 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1768 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1769 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1770 uses_adjacency = true;
1771 break;
1772 default:
1773 uses_adjacency = false;
1774 break;
1775 }
1776
1777 /* All these are in dwords: */
1778 /* We can't allow using the whole LDS, because GS waves compete with
1779 * other shader stages for LDS space. */
1780 const unsigned max_lds_size = 8 * 1024;
1781 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1782 unsigned esgs_lds_size;
1783
1784 /* All these are per subgroup: */
1785 const unsigned max_out_prims = 32 * 1024;
1786 const unsigned max_es_verts = 255;
1787 const unsigned ideal_gs_prims = 64;
1788 unsigned max_gs_prims, gs_prims;
1789 unsigned min_es_verts, es_verts, worst_case_es_verts;
1790
1791 if (uses_adjacency || gs_num_invocations > 1)
1792 max_gs_prims = 127 / gs_num_invocations;
1793 else
1794 max_gs_prims = 255;
1795
1796 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1797 * Make sure we don't go over the maximum value.
1798 */
1799 if (gs_info->gs.vertices_out > 0) {
1800 max_gs_prims = MIN2(max_gs_prims,
1801 max_out_prims /
1802 (gs_info->gs.vertices_out * gs_num_invocations));
1803 }
1804 assert(max_gs_prims > 0);
1805
1806 /* If the primitive has adjacency, halve the number of vertices
1807 * that will be reused in multiple primitives.
1808 */
1809 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1810
1811 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1812 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1813
1814 /* Compute ESGS LDS size based on the worst case number of ES vertices
1815 * needed to create the target number of GS prims per subgroup.
1816 */
1817 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1818
1819 /* If total LDS usage is too big, refactor partitions based on ratio
1820 * of ESGS item sizes.
1821 */
1822 if (esgs_lds_size > max_lds_size) {
1823 /* Our target GS Prims Per Subgroup was too large. Calculate
1824 * the maximum number of GS Prims Per Subgroup that will fit
1825 * into LDS, capped by the maximum that the hardware can support.
1826 */
1827 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1828 max_gs_prims);
1829 assert(gs_prims > 0);
1830 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1831 max_es_verts);
1832
1833 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1834 assert(esgs_lds_size <= max_lds_size);
1835 }
1836
1837 /* Now calculate remaining ESGS information. */
1838 if (esgs_lds_size)
1839 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1840 else
1841 es_verts = max_es_verts;
1842
1843 /* Vertices for adjacency primitives are not always reused, so restore
1844 * it for ES_VERTS_PER_SUBGRP.
1845 */
1846 min_es_verts = gs_info->gs.vertices_in;
1847
1848 /* For normal primitives, the VGT only checks if they are past the ES
1849 * verts per subgroup after allocating a full GS primitive and if they
1850 * are, kick off a new subgroup. But if those additional ES verts are
1851 * unique (e.g. not reused) we need to make sure there is enough LDS
1852 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1853 */
1854 es_verts -= min_es_verts - 1;
1855
1856 uint32_t es_verts_per_subgroup = es_verts;
1857 uint32_t gs_prims_per_subgroup = gs_prims;
1858 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1859 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1860 out->lds_size = align(esgs_lds_size, 128) / 128;
1861 out->vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1862 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1863 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1864 out->vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1865 out->vgt_esgs_ring_itemsize = esgs_itemsize;
1866 assert(max_prims_per_subgroup <= max_out_prims);
1867 }
1868
1869 static void clamp_gsprims_to_esverts(unsigned *max_gsprims, unsigned max_esverts,
1870 unsigned min_verts_per_prim, bool use_adjacency)
1871 {
1872 unsigned max_reuse = max_esverts - min_verts_per_prim;
1873 if (use_adjacency)
1874 max_reuse /= 2;
1875 *max_gsprims = MIN2(*max_gsprims, 1 + max_reuse);
1876 }
1877
1878 static unsigned
1879 radv_get_num_input_vertices(nir_shader **nir)
1880 {
1881 if (nir[MESA_SHADER_GEOMETRY]) {
1882 nir_shader *gs = nir[MESA_SHADER_GEOMETRY];
1883
1884 return gs->info.gs.vertices_in;
1885 }
1886
1887 if (nir[MESA_SHADER_TESS_CTRL]) {
1888 nir_shader *tes = nir[MESA_SHADER_TESS_EVAL];
1889
1890 if (tes->info.tess.point_mode)
1891 return 1;
1892 if (tes->info.tess.primitive_mode == GL_ISOLINES)
1893 return 2;
1894 return 3;
1895 }
1896
1897 return 3;
1898 }
1899
1900 static void
1901 gfx10_get_ngg_info(const struct radv_pipeline_key *key,
1902 struct radv_pipeline *pipeline,
1903 nir_shader **nir,
1904 struct radv_shader_info *infos,
1905 struct gfx10_ngg_info *ngg)
1906 {
1907 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1908 struct radv_es_output_info *es_info =
1909 nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1910 unsigned gs_type = nir[MESA_SHADER_GEOMETRY] ? MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX;
1911 unsigned max_verts_per_prim = radv_get_num_input_vertices(nir);
1912 unsigned min_verts_per_prim =
1913 gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1;
1914 unsigned gs_num_invocations = nir[MESA_SHADER_GEOMETRY] ? MAX2(gs_info->gs.invocations, 1) : 1;
1915 bool uses_adjacency;
1916 switch(key->topology) {
1917 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1918 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1919 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1920 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1921 uses_adjacency = true;
1922 break;
1923 default:
1924 uses_adjacency = false;
1925 break;
1926 }
1927
1928 /* All these are in dwords: */
1929 /* We can't allow using the whole LDS, because GS waves compete with
1930 * other shader stages for LDS space.
1931 *
1932 * TODO: We should really take the shader's internal LDS use into
1933 * account. The linker will fail if the size is greater than
1934 * 8K dwords.
1935 */
1936 const unsigned max_lds_size = 8 * 1024 - 768;
1937 const unsigned target_lds_size = max_lds_size;
1938 unsigned esvert_lds_size = 0;
1939 unsigned gsprim_lds_size = 0;
1940
1941 /* All these are per subgroup: */
1942 const unsigned min_esverts = pipeline->device->physical_device->rad_info.chip_class >= GFX10_3 ? 29 : 24;
1943 bool max_vert_out_per_gs_instance = false;
1944 unsigned max_esverts_base = 256;
1945 unsigned max_gsprims_base = 128; /* default prim group size clamp */
1946
1947 /* Hardware has the following non-natural restrictions on the value
1948 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1949 * the draw:
1950 * - at most 252 for any line input primitive type
1951 * - at most 251 for any quad input primitive type
1952 * - at most 251 for triangle strips with adjacency (this happens to
1953 * be the natural limit for triangle *lists* with adjacency)
1954 */
1955 max_esverts_base = MIN2(max_esverts_base, 251 + max_verts_per_prim - 1);
1956
1957 if (gs_type == MESA_SHADER_GEOMETRY) {
1958 unsigned max_out_verts_per_gsprim =
1959 gs_info->gs.vertices_out * gs_num_invocations;
1960
1961 if (max_out_verts_per_gsprim <= 256) {
1962 if (max_out_verts_per_gsprim) {
1963 max_gsprims_base = MIN2(max_gsprims_base,
1964 256 / max_out_verts_per_gsprim);
1965 }
1966 } else {
1967 /* Use special multi-cycling mode in which each GS
1968 * instance gets its own subgroup. Does not work with
1969 * tessellation. */
1970 max_vert_out_per_gs_instance = true;
1971 max_gsprims_base = 1;
1972 max_out_verts_per_gsprim = gs_info->gs.vertices_out;
1973 }
1974
1975 esvert_lds_size = es_info->esgs_itemsize / 4;
1976 gsprim_lds_size = (gs_info->gs.gsvs_vertex_size / 4 + 1) * max_out_verts_per_gsprim;
1977 } else {
1978 /* VS and TES. */
1979 /* LDS size for passing data from GS to ES. */
1980 struct radv_streamout_info *so_info = nir[MESA_SHADER_TESS_CTRL]
1981 ? &infos[MESA_SHADER_TESS_EVAL].so
1982 : &infos[MESA_SHADER_VERTEX].so;
1983
1984 if (so_info->num_outputs)
1985 esvert_lds_size = 4 * so_info->num_outputs + 1;
1986
1987 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1988 * corresponding to the ES thread of the provoking vertex. All
1989 * ES threads load and export PrimitiveID for their thread.
1990 */
1991 if (!nir[MESA_SHADER_TESS_CTRL] &&
1992 infos[MESA_SHADER_VERTEX].vs.outinfo.export_prim_id)
1993 esvert_lds_size = MAX2(esvert_lds_size, 1);
1994 }
1995
1996 unsigned max_gsprims = max_gsprims_base;
1997 unsigned max_esverts = max_esverts_base;
1998
1999 if (esvert_lds_size)
2000 max_esverts = MIN2(max_esverts, target_lds_size / esvert_lds_size);
2001 if (gsprim_lds_size)
2002 max_gsprims = MIN2(max_gsprims, target_lds_size / gsprim_lds_size);
2003
2004 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
2005 clamp_gsprims_to_esverts(&max_gsprims, max_esverts, min_verts_per_prim, uses_adjacency);
2006 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
2007
2008 if (esvert_lds_size || gsprim_lds_size) {
2009 /* Now that we have a rough proportionality between esverts
2010 * and gsprims based on the primitive type, scale both of them
2011 * down simultaneously based on required LDS space.
2012 *
2013 * We could be smarter about this if we knew how much vertex
2014 * reuse to expect.
2015 */
2016 unsigned lds_total = max_esverts * esvert_lds_size +
2017 max_gsprims * gsprim_lds_size;
2018 if (lds_total > target_lds_size) {
2019 max_esverts = max_esverts * target_lds_size / lds_total;
2020 max_gsprims = max_gsprims * target_lds_size / lds_total;
2021
2022 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
2023 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
2024 min_verts_per_prim, uses_adjacency);
2025 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
2026 }
2027 }
2028
2029 /* Round up towards full wave sizes for better ALU utilization. */
2030 if (!max_vert_out_per_gs_instance) {
2031 unsigned orig_max_esverts;
2032 unsigned orig_max_gsprims;
2033 unsigned wavesize;
2034
2035 if (gs_type == MESA_SHADER_GEOMETRY) {
2036 wavesize = gs_info->wave_size;
2037 } else {
2038 wavesize = nir[MESA_SHADER_TESS_CTRL]
2039 ? infos[MESA_SHADER_TESS_EVAL].wave_size
2040 : infos[MESA_SHADER_VERTEX].wave_size;
2041 }
2042
2043 do {
2044 orig_max_esverts = max_esverts;
2045 orig_max_gsprims = max_gsprims;
2046
2047 max_esverts = align(max_esverts, wavesize);
2048 max_esverts = MIN2(max_esverts, max_esverts_base);
2049 if (esvert_lds_size)
2050 max_esverts = MIN2(max_esverts,
2051 (max_lds_size - max_gsprims * gsprim_lds_size) /
2052 esvert_lds_size);
2053 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
2054
2055 max_gsprims = align(max_gsprims, wavesize);
2056 max_gsprims = MIN2(max_gsprims, max_gsprims_base);
2057 if (gsprim_lds_size)
2058 max_gsprims = MIN2(max_gsprims,
2059 (max_lds_size - max_esverts * esvert_lds_size) /
2060 gsprim_lds_size);
2061 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
2062 min_verts_per_prim, uses_adjacency);
2063 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
2064 } while (orig_max_esverts != max_esverts || orig_max_gsprims != max_gsprims);
2065 }
2066
2067 /* Hardware restriction: minimum value of max_esverts */
2068 max_esverts = MAX2(max_esverts, min_esverts - 1 + max_verts_per_prim);
2069
2070 unsigned max_out_vertices =
2071 max_vert_out_per_gs_instance ? gs_info->gs.vertices_out :
2072 gs_type == MESA_SHADER_GEOMETRY ?
2073 max_gsprims * gs_num_invocations * gs_info->gs.vertices_out :
2074 max_esverts;
2075 assert(max_out_vertices <= 256);
2076
2077 unsigned prim_amp_factor = 1;
2078 if (gs_type == MESA_SHADER_GEOMETRY) {
2079 /* Number of output primitives per GS input primitive after
2080 * GS instancing. */
2081 prim_amp_factor = gs_info->gs.vertices_out;
2082 }
2083
2084 /* The GE only checks against the maximum number of ES verts after
2085 * allocating a full GS primitive. So we need to ensure that whenever
2086 * this check passes, there is enough space for a full primitive without
2087 * vertex reuse.
2088 */
2089 ngg->hw_max_esverts = max_esverts - max_verts_per_prim + 1;
2090 ngg->max_gsprims = max_gsprims;
2091 ngg->max_out_verts = max_out_vertices;
2092 ngg->prim_amp_factor = prim_amp_factor;
2093 ngg->max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
2094 ngg->ngg_emit_size = max_gsprims * gsprim_lds_size;
2095 ngg->esgs_ring_size = 4 * max_esverts * esvert_lds_size;
2096
2097 if (gs_type == MESA_SHADER_GEOMETRY) {
2098 ngg->vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
2099 } else {
2100 ngg->vgt_esgs_ring_itemsize = 1;
2101 }
2102
2103 pipeline->graphics.esgs_ring_size = ngg->esgs_ring_size;
2104
2105 assert(ngg->hw_max_esverts >= min_esverts); /* HW limitation */
2106 }
2107
2108 static void
2109 radv_pipeline_init_gs_ring_state(struct radv_pipeline *pipeline,
2110 const struct gfx9_gs_info *gs)
2111 {
2112 struct radv_device *device = pipeline->device;
2113 unsigned num_se = device->physical_device->rad_info.max_se;
2114 unsigned wave_size = 64;
2115 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
2116 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
2117 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2118 */
2119 unsigned gs_vertex_reuse =
2120 (device->physical_device->rad_info.chip_class >= GFX8 ? 32 : 16) * num_se;
2121 unsigned alignment = 256 * num_se;
2122 /* The maximum size is 63.999 MB per SE. */
2123 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
2124 struct radv_shader_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
2125
2126 /* Calculate the minimum size. */
2127 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
2128 wave_size, alignment);
2129 /* These are recommended sizes, not minimum sizes. */
2130 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
2131 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
2132 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
2133 gs_info->gs.max_gsvs_emit_size;
2134
2135 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
2136 esgs_ring_size = align(esgs_ring_size, alignment);
2137 gsvs_ring_size = align(gsvs_ring_size, alignment);
2138
2139 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
2140 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
2141
2142 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
2143 }
2144
2145 struct radv_shader_variant *
2146 radv_get_shader(const struct radv_pipeline *pipeline,
2147 gl_shader_stage stage)
2148 {
2149 if (stage == MESA_SHADER_VERTEX) {
2150 if (pipeline->shaders[MESA_SHADER_VERTEX])
2151 return pipeline->shaders[MESA_SHADER_VERTEX];
2152 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
2153 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
2154 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
2155 return pipeline->shaders[MESA_SHADER_GEOMETRY];
2156 } else if (stage == MESA_SHADER_TESS_EVAL) {
2157 if (!radv_pipeline_has_tess(pipeline))
2158 return NULL;
2159 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
2160 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
2161 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
2162 return pipeline->shaders[MESA_SHADER_GEOMETRY];
2163 }
2164 return pipeline->shaders[stage];
2165 }
2166
2167 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
2168 {
2169 if (radv_pipeline_has_gs(pipeline))
2170 if (radv_pipeline_has_ngg(pipeline))
2171 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
2172 else
2173 return &pipeline->gs_copy_shader->info.vs.outinfo;
2174 else if (radv_pipeline_has_tess(pipeline))
2175 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
2176 else
2177 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
2178 }
2179
2180 static void
2181 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
2182 {
2183 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
2184 int shader_count = 0;
2185
2186 if(shaders[MESA_SHADER_FRAGMENT]) {
2187 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
2188 }
2189 if(shaders[MESA_SHADER_GEOMETRY]) {
2190 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
2191 }
2192 if(shaders[MESA_SHADER_TESS_EVAL]) {
2193 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
2194 }
2195 if(shaders[MESA_SHADER_TESS_CTRL]) {
2196 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
2197 }
2198 if(shaders[MESA_SHADER_VERTEX]) {
2199 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
2200 }
2201
2202 if (shader_count > 1) {
2203 unsigned first = ordered_shaders[shader_count - 1]->info.stage;
2204 unsigned last = ordered_shaders[0]->info.stage;
2205
2206 if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
2207 ordered_shaders[1]->info.has_transform_feedback_varyings)
2208 nir_link_xfb_varyings(ordered_shaders[1], ordered_shaders[0]);
2209
2210 for (int i = 0; i < shader_count; ++i) {
2211 nir_variable_mode mask = 0;
2212
2213 if (ordered_shaders[i]->info.stage != first)
2214 mask = mask | nir_var_shader_in;
2215
2216 if (ordered_shaders[i]->info.stage != last)
2217 mask = mask | nir_var_shader_out;
2218
2219 nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
2220 radv_optimize_nir(ordered_shaders[i], false, false);
2221 }
2222 }
2223
2224 for (int i = 1; i < shader_count; ++i) {
2225 nir_lower_io_arrays_to_elements(ordered_shaders[i],
2226 ordered_shaders[i - 1]);
2227
2228 if (nir_link_opt_varyings(ordered_shaders[i],
2229 ordered_shaders[i - 1]))
2230 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2231
2232 nir_remove_dead_variables(ordered_shaders[i],
2233 nir_var_shader_out, NULL);
2234 nir_remove_dead_variables(ordered_shaders[i - 1],
2235 nir_var_shader_in, NULL);
2236
2237 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
2238 ordered_shaders[i - 1]);
2239
2240 nir_compact_varyings(ordered_shaders[i],
2241 ordered_shaders[i - 1], true);
2242
2243 if (progress) {
2244 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
2245 ac_lower_indirect_derefs(ordered_shaders[i],
2246 pipeline->device->physical_device->rad_info.chip_class);
2247 }
2248 radv_optimize_nir(ordered_shaders[i], false, false);
2249
2250 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
2251 ac_lower_indirect_derefs(ordered_shaders[i - 1],
2252 pipeline->device->physical_device->rad_info.chip_class);
2253 }
2254 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2255 }
2256 }
2257 }
2258
2259 static void
2260 radv_set_linked_driver_locations(struct radv_pipeline *pipeline, nir_shader **shaders,
2261 struct radv_shader_info infos[MESA_SHADER_STAGES])
2262 {
2263 bool has_tess = shaders[MESA_SHADER_TESS_CTRL];
2264 bool has_gs = shaders[MESA_SHADER_GEOMETRY];
2265
2266 if (!has_tess && !has_gs)
2267 return;
2268
2269 unsigned vs_info_idx = MESA_SHADER_VERTEX;
2270 unsigned tes_info_idx = MESA_SHADER_TESS_EVAL;
2271
2272 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2273 /* These are merged into the next stage */
2274 vs_info_idx = has_tess ? MESA_SHADER_TESS_CTRL : MESA_SHADER_GEOMETRY;
2275 tes_info_idx = has_gs ? MESA_SHADER_GEOMETRY : MESA_SHADER_TESS_EVAL;
2276 }
2277
2278 if (has_tess) {
2279 nir_linked_io_var_info vs2tcs =
2280 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_VERTEX], shaders[MESA_SHADER_TESS_CTRL]);
2281 nir_linked_io_var_info tcs2tes =
2282 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_TESS_CTRL], shaders[MESA_SHADER_TESS_EVAL]);
2283
2284 infos[vs_info_idx].vs.num_linked_outputs = vs2tcs.num_linked_io_vars;
2285 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_inputs = vs2tcs.num_linked_io_vars;
2286 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_outputs = tcs2tes.num_linked_io_vars;
2287 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_patch_outputs = tcs2tes.num_linked_patch_io_vars;
2288 infos[tes_info_idx].tes.num_linked_inputs = tcs2tes.num_linked_io_vars;
2289 infos[tes_info_idx].tes.num_linked_patch_inputs = tcs2tes.num_linked_patch_io_vars;
2290
2291 if (has_gs) {
2292 nir_linked_io_var_info tes2gs =
2293 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_TESS_EVAL], shaders[MESA_SHADER_GEOMETRY]);
2294
2295 infos[tes_info_idx].tes.num_linked_outputs = tes2gs.num_linked_io_vars;
2296 infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = tes2gs.num_linked_io_vars;
2297 }
2298 } else if (has_gs) {
2299 nir_linked_io_var_info vs2gs =
2300 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_VERTEX], shaders[MESA_SHADER_GEOMETRY]);
2301
2302 infos[vs_info_idx].vs.num_linked_outputs = vs2gs.num_linked_io_vars;
2303 infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = vs2gs.num_linked_io_vars;
2304 }
2305 }
2306
2307 static uint32_t
2308 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo *input_state,
2309 uint32_t attrib_binding)
2310 {
2311 for (uint32_t i = 0; i < input_state->vertexBindingDescriptionCount; i++) {
2312 const VkVertexInputBindingDescription *input_binding =
2313 &input_state->pVertexBindingDescriptions[i];
2314
2315 if (input_binding->binding == attrib_binding)
2316 return input_binding->stride;
2317 }
2318
2319 return 0;
2320 }
2321
2322 static struct radv_pipeline_key
2323 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
2324 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2325 const struct radv_blend_state *blend)
2326 {
2327 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2328 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2329 const VkPipelineVertexInputStateCreateInfo *input_state =
2330 pCreateInfo->pVertexInputState;
2331 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
2332 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
2333
2334 struct radv_pipeline_key key;
2335 memset(&key, 0, sizeof(key));
2336
2337 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
2338 key.optimisations_disabled = 1;
2339
2340 key.has_multiview_view_index = !!subpass->view_mask;
2341
2342 uint32_t binding_input_rate = 0;
2343 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
2344 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
2345 if (input_state->pVertexBindingDescriptions[i].inputRate) {
2346 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
2347 binding_input_rate |= 1u << binding;
2348 instance_rate_divisors[binding] = 1;
2349 }
2350 }
2351 if (divisor_state) {
2352 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
2353 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
2354 divisor_state->pVertexBindingDivisors[i].divisor;
2355 }
2356 }
2357
2358 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
2359 const VkVertexInputAttributeDescription *desc =
2360 &input_state->pVertexAttributeDescriptions[i];
2361 const struct vk_format_description *format_desc;
2362 unsigned location = desc->location;
2363 unsigned binding = desc->binding;
2364 unsigned num_format, data_format;
2365 int first_non_void;
2366
2367 if (binding_input_rate & (1u << binding)) {
2368 key.instance_rate_inputs |= 1u << location;
2369 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
2370 }
2371
2372 format_desc = vk_format_description(desc->format);
2373 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2374
2375 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2376 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2377
2378 key.vertex_attribute_formats[location] = data_format | (num_format << 4);
2379 key.vertex_attribute_bindings[location] = desc->binding;
2380 key.vertex_attribute_offsets[location] = desc->offset;
2381 key.vertex_attribute_strides[location] = radv_get_attrib_stride(input_state, desc->binding);
2382
2383 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8 &&
2384 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
2385 VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
2386 uint64_t adjust;
2387 switch(format) {
2388 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2389 case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
2390 adjust = RADV_ALPHA_ADJUST_SNORM;
2391 break;
2392 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2393 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
2394 adjust = RADV_ALPHA_ADJUST_SSCALED;
2395 break;
2396 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2397 case VK_FORMAT_A2B10G10R10_SINT_PACK32:
2398 adjust = RADV_ALPHA_ADJUST_SINT;
2399 break;
2400 default:
2401 adjust = 0;
2402 break;
2403 }
2404 key.vertex_alpha_adjust |= adjust << (2 * location);
2405 }
2406
2407 switch (desc->format) {
2408 case VK_FORMAT_B8G8R8A8_UNORM:
2409 case VK_FORMAT_B8G8R8A8_SNORM:
2410 case VK_FORMAT_B8G8R8A8_USCALED:
2411 case VK_FORMAT_B8G8R8A8_SSCALED:
2412 case VK_FORMAT_B8G8R8A8_UINT:
2413 case VK_FORMAT_B8G8R8A8_SINT:
2414 case VK_FORMAT_B8G8R8A8_SRGB:
2415 case VK_FORMAT_A2R10G10B10_UNORM_PACK32:
2416 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2417 case VK_FORMAT_A2R10G10B10_USCALED_PACK32:
2418 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2419 case VK_FORMAT_A2R10G10B10_UINT_PACK32:
2420 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2421 key.vertex_post_shuffle |= 1 << location;
2422 break;
2423 default:
2424 break;
2425 }
2426 }
2427
2428 const VkPipelineTessellationStateCreateInfo *tess =
2429 radv_pipeline_get_tessellation_state(pCreateInfo);
2430 if (tess)
2431 key.tess_input_vertices = tess->patchControlPoints;
2432
2433 const VkPipelineMultisampleStateCreateInfo *vkms =
2434 radv_pipeline_get_multisample_state(pCreateInfo);
2435 if (vkms && vkms->rasterizationSamples > 1) {
2436 uint32_t num_samples = vkms->rasterizationSamples;
2437 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
2438 key.num_samples = num_samples;
2439 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
2440 }
2441
2442 key.col_format = blend->spi_shader_col_format;
2443 key.is_dual_src = blend->mrt0_is_dual_src;
2444 if (pipeline->device->physical_device->rad_info.chip_class < GFX8) {
2445 key.is_int8 = blend->col_format_is_int8;
2446 key.is_int10 = blend->col_format_is_int10;
2447 }
2448
2449 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10)
2450 key.topology = pCreateInfo->pInputAssemblyState->topology;
2451
2452 return key;
2453 }
2454
2455 static bool
2456 radv_nir_stage_uses_xfb(const nir_shader *nir)
2457 {
2458 nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
2459 bool uses_xfb = !!xfb;
2460
2461 ralloc_free(xfb);
2462 return uses_xfb;
2463 }
2464
2465 static void
2466 radv_fill_shader_keys(struct radv_device *device,
2467 struct radv_shader_variant_key *keys,
2468 const struct radv_pipeline_key *key,
2469 nir_shader **nir)
2470 {
2471 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
2472 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
2473 keys[MESA_SHADER_VERTEX].vs.post_shuffle = key->vertex_post_shuffle;
2474 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) {
2475 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
2476 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_formats[i] = key->vertex_attribute_formats[i];
2477 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_bindings[i] = key->vertex_attribute_bindings[i];
2478 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i];
2479 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i];
2480 }
2481 keys[MESA_SHADER_VERTEX].vs.outprim = si_conv_prim_to_gs_out(key->topology);
2482
2483 if (nir[MESA_SHADER_TESS_CTRL]) {
2484 keys[MESA_SHADER_VERTEX].vs_common_out.as_ls = true;
2485 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
2486 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
2487 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
2488
2489 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
2490 }
2491
2492 if (nir[MESA_SHADER_GEOMETRY]) {
2493 if (nir[MESA_SHADER_TESS_CTRL])
2494 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_es = true;
2495 else
2496 keys[MESA_SHADER_VERTEX].vs_common_out.as_es = true;
2497 }
2498
2499 if (device->physical_device->use_ngg) {
2500 if (nir[MESA_SHADER_TESS_CTRL]) {
2501 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = true;
2502 } else {
2503 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = true;
2504 }
2505
2506 if (nir[MESA_SHADER_TESS_CTRL] &&
2507 nir[MESA_SHADER_GEOMETRY] &&
2508 nir[MESA_SHADER_GEOMETRY]->info.gs.invocations *
2509 nir[MESA_SHADER_GEOMETRY]->info.gs.vertices_out > 256) {
2510 /* Fallback to the legacy path if tessellation is
2511 * enabled with extreme geometry because
2512 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2513 * might hang.
2514 */
2515 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2516 }
2517
2518 if (!device->physical_device->use_ngg_gs) {
2519 if (nir[MESA_SHADER_GEOMETRY]) {
2520 if (nir[MESA_SHADER_TESS_CTRL])
2521 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2522 else
2523 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2524 }
2525 }
2526
2527 gl_shader_stage last_xfb_stage = MESA_SHADER_VERTEX;
2528
2529 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
2530 if (nir[i])
2531 last_xfb_stage = i;
2532 }
2533
2534 bool uses_xfb = nir[last_xfb_stage] &&
2535 radv_nir_stage_uses_xfb(nir[last_xfb_stage]);
2536
2537 if (!device->physical_device->use_ngg_streamout && uses_xfb) {
2538 if (nir[MESA_SHADER_TESS_CTRL])
2539 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2540 else
2541 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2542 }
2543
2544 /* Determine if the pipeline is eligible for the NGG passthrough
2545 * mode. It can't be enabled for geometry shaders, for NGG
2546 * streamout or for vertex shaders that export the primitive ID
2547 * (this is checked later because we don't have the info here.)
2548 */
2549 if (!nir[MESA_SHADER_GEOMETRY] && !uses_xfb) {
2550 if (nir[MESA_SHADER_TESS_CTRL] &&
2551 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg) {
2552 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg_passthrough = true;
2553 } else if (nir[MESA_SHADER_VERTEX] &&
2554 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) {
2555 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = true;
2556 }
2557 }
2558 }
2559
2560 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
2561 keys[i].has_multiview_view_index = key->has_multiview_view_index;
2562
2563 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
2564 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
2565 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
2566 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
2567 keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples;
2568 keys[MESA_SHADER_FRAGMENT].fs.is_dual_src = key->is_dual_src;
2569
2570 if (nir[MESA_SHADER_COMPUTE]) {
2571 keys[MESA_SHADER_COMPUTE].cs.subgroup_size = key->compute_subgroup_size;
2572 }
2573 }
2574
2575 static uint8_t
2576 radv_get_wave_size(struct radv_device *device,
2577 const VkPipelineShaderStageCreateInfo *pStage,
2578 gl_shader_stage stage,
2579 const struct radv_shader_variant_key *key)
2580 {
2581 if (stage == MESA_SHADER_GEOMETRY && !key->vs_common_out.as_ngg)
2582 return 64;
2583 else if (stage == MESA_SHADER_COMPUTE) {
2584 if (key->cs.subgroup_size) {
2585 /* Return the required subgroup size if specified. */
2586 return key->cs.subgroup_size;
2587 }
2588 return device->physical_device->cs_wave_size;
2589 }
2590 else if (stage == MESA_SHADER_FRAGMENT)
2591 return device->physical_device->ps_wave_size;
2592 else
2593 return device->physical_device->ge_wave_size;
2594 }
2595
2596 static uint8_t
2597 radv_get_ballot_bit_size(struct radv_device *device,
2598 const VkPipelineShaderStageCreateInfo *pStage,
2599 gl_shader_stage stage,
2600 const struct radv_shader_variant_key *key)
2601 {
2602 if (stage == MESA_SHADER_COMPUTE && key->cs.subgroup_size)
2603 return key->cs.subgroup_size;
2604 return 64;
2605 }
2606
2607 static void
2608 radv_fill_shader_info(struct radv_pipeline *pipeline,
2609 const VkPipelineShaderStageCreateInfo **pStages,
2610 struct radv_shader_variant_key *keys,
2611 struct radv_shader_info *infos,
2612 nir_shader **nir)
2613 {
2614 unsigned active_stages = 0;
2615 unsigned filled_stages = 0;
2616
2617 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2618 if (nir[i])
2619 active_stages |= (1 << i);
2620 }
2621
2622 if (nir[MESA_SHADER_FRAGMENT]) {
2623 radv_nir_shader_info_init(&infos[MESA_SHADER_FRAGMENT]);
2624 radv_nir_shader_info_pass(nir[MESA_SHADER_FRAGMENT],
2625 pipeline->layout,
2626 &keys[MESA_SHADER_FRAGMENT],
2627 &infos[MESA_SHADER_FRAGMENT],
2628 radv_use_llvm_for_stage(pipeline->device, MESA_SHADER_FRAGMENT));
2629
2630 /* TODO: These are no longer used as keys we should refactor this */
2631 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2632 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2633 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2634 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2635 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2636 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2637 keys[MESA_SHADER_VERTEX].vs_common_out.export_viewport_index =
2638 infos[MESA_SHADER_FRAGMENT].ps.viewport_index_input;
2639 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2640 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2641 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2642 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2643 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2644 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2645 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_viewport_index =
2646 infos[MESA_SHADER_FRAGMENT].ps.viewport_index_input;
2647
2648 /* NGG passthrough mode can't be enabled for vertex shaders
2649 * that export the primitive ID.
2650 *
2651 * TODO: I should really refactor the keys logic.
2652 */
2653 if (nir[MESA_SHADER_VERTEX] &&
2654 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id) {
2655 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = false;
2656 }
2657
2658 filled_stages |= (1 << MESA_SHADER_FRAGMENT);
2659 }
2660
2661 if (nir[MESA_SHADER_TESS_CTRL]) {
2662 infos[MESA_SHADER_TESS_CTRL].tcs.tes_inputs_read =
2663 nir[MESA_SHADER_TESS_EVAL]->info.inputs_read;
2664 infos[MESA_SHADER_TESS_CTRL].tcs.tes_patch_inputs_read =
2665 nir[MESA_SHADER_TESS_EVAL]->info.patch_inputs_read;
2666 }
2667
2668 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2669 nir[MESA_SHADER_TESS_CTRL]) {
2670 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2671 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2672 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2673
2674 radv_nir_shader_info_init(&infos[MESA_SHADER_TESS_CTRL]);
2675
2676 for (int i = 0; i < 2; i++) {
2677 radv_nir_shader_info_pass(combined_nir[i],
2678 pipeline->layout, &key,
2679 &infos[MESA_SHADER_TESS_CTRL],
2680 radv_use_llvm_for_stage(pipeline->device, MESA_SHADER_TESS_CTRL));
2681 }
2682
2683 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2684 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2685 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2686 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2687
2688 filled_stages |= (1 << MESA_SHADER_VERTEX);
2689 filled_stages |= (1 << MESA_SHADER_TESS_CTRL);
2690 }
2691
2692 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2693 nir[MESA_SHADER_GEOMETRY]) {
2694 gl_shader_stage pre_stage = nir[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2695 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2696
2697 radv_nir_shader_info_init(&infos[MESA_SHADER_GEOMETRY]);
2698
2699 for (int i = 0; i < 2; i++) {
2700 radv_nir_shader_info_pass(combined_nir[i],
2701 pipeline->layout,
2702 &keys[pre_stage],
2703 &infos[MESA_SHADER_GEOMETRY],
2704 radv_use_llvm_for_stage(pipeline->device, MESA_SHADER_GEOMETRY));
2705 }
2706
2707 filled_stages |= (1 << pre_stage);
2708 filled_stages |= (1 << MESA_SHADER_GEOMETRY);
2709 }
2710
2711 active_stages ^= filled_stages;
2712 while (active_stages) {
2713 int i = u_bit_scan(&active_stages);
2714
2715 if (i == MESA_SHADER_TESS_CTRL) {
2716 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs =
2717 util_last_bit64(infos[MESA_SHADER_VERTEX].vs.ls_outputs_written);
2718 }
2719
2720 if (i == MESA_SHADER_TESS_EVAL) {
2721 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2722 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2723 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2724 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2725 }
2726
2727 radv_nir_shader_info_init(&infos[i]);
2728 radv_nir_shader_info_pass(nir[i], pipeline->layout,
2729 &keys[i], &infos[i],
2730 radv_use_llvm_for_stage(pipeline->device, i));
2731 }
2732
2733 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2734 if (nir[i]) {
2735 infos[i].wave_size =
2736 radv_get_wave_size(pipeline->device, pStages[i],
2737 i, &keys[i]);
2738 infos[i].ballot_bit_size =
2739 radv_get_ballot_bit_size(pipeline->device,
2740 pStages[i], i,
2741 &keys[i]);
2742 }
2743 }
2744 }
2745
2746 static void
2747 merge_tess_info(struct shader_info *tes_info,
2748 const struct shader_info *tcs_info)
2749 {
2750 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2751 *
2752 * "PointMode. Controls generation of points rather than triangles
2753 * or lines. This functionality defaults to disabled, and is
2754 * enabled if either shader stage includes the execution mode.
2755 *
2756 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2757 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2758 * and OutputVertices, it says:
2759 *
2760 * "One mode must be set in at least one of the tessellation
2761 * shader stages."
2762 *
2763 * So, the fields can be set in either the TCS or TES, but they must
2764 * agree if set in both. Our backend looks at TES, so bitwise-or in
2765 * the values from the TCS.
2766 */
2767 assert(tcs_info->tess.tcs_vertices_out == 0 ||
2768 tes_info->tess.tcs_vertices_out == 0 ||
2769 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
2770 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
2771
2772 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2773 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2774 tcs_info->tess.spacing == tes_info->tess.spacing);
2775 tes_info->tess.spacing |= tcs_info->tess.spacing;
2776
2777 assert(tcs_info->tess.primitive_mode == 0 ||
2778 tes_info->tess.primitive_mode == 0 ||
2779 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
2780 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
2781 tes_info->tess.ccw |= tcs_info->tess.ccw;
2782 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
2783 }
2784
2785 static
2786 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT *ext)
2787 {
2788 if (!ext)
2789 return;
2790
2791 if (ext->pPipelineCreationFeedback) {
2792 ext->pPipelineCreationFeedback->flags = 0;
2793 ext->pPipelineCreationFeedback->duration = 0;
2794 }
2795
2796 for (unsigned i = 0; i < ext->pipelineStageCreationFeedbackCount; ++i) {
2797 ext->pPipelineStageCreationFeedbacks[i].flags = 0;
2798 ext->pPipelineStageCreationFeedbacks[i].duration = 0;
2799 }
2800 }
2801
2802 static
2803 void radv_start_feedback(VkPipelineCreationFeedbackEXT *feedback)
2804 {
2805 if (!feedback)
2806 return;
2807
2808 feedback->duration -= radv_get_current_time();
2809 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT;
2810 }
2811
2812 static
2813 void radv_stop_feedback(VkPipelineCreationFeedbackEXT *feedback, bool cache_hit)
2814 {
2815 if (!feedback)
2816 return;
2817
2818 feedback->duration += radv_get_current_time();
2819 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT |
2820 (cache_hit ? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT : 0);
2821 }
2822
2823 VkResult radv_create_shaders(struct radv_pipeline *pipeline,
2824 struct radv_device *device,
2825 struct radv_pipeline_cache *cache,
2826 const struct radv_pipeline_key *key,
2827 const VkPipelineShaderStageCreateInfo **pStages,
2828 const VkPipelineCreateFlags flags,
2829 VkPipelineCreationFeedbackEXT *pipeline_feedback,
2830 VkPipelineCreationFeedbackEXT **stage_feedbacks)
2831 {
2832 struct radv_shader_module fs_m = {0};
2833 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2834 nir_shader *nir[MESA_SHADER_STAGES] = {0};
2835 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2836 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{{0}}}}};
2837 struct radv_shader_info infos[MESA_SHADER_STAGES] = {0};
2838 unsigned char hash[20], gs_copy_hash[20];
2839 bool keep_executable_info = (flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR) || device->keep_shader_info;
2840 bool keep_statistic_info = (flags & VK_PIPELINE_CREATE_CAPTURE_STATISTICS_BIT_KHR) ||
2841 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) ||
2842 device->keep_shader_info;
2843 bool disable_optimizations = flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT;
2844
2845 radv_start_feedback(pipeline_feedback);
2846
2847 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2848 if (pStages[i]) {
2849 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
2850 if (modules[i]->nir)
2851 _mesa_sha1_compute(modules[i]->nir->info.name,
2852 strlen(modules[i]->nir->info.name),
2853 modules[i]->sha1);
2854
2855 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
2856 }
2857 }
2858
2859 radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device));
2860 memcpy(gs_copy_hash, hash, 20);
2861 gs_copy_hash[0] ^= 1;
2862
2863 bool found_in_application_cache = true;
2864 if (modules[MESA_SHADER_GEOMETRY] && !keep_executable_info && !keep_statistic_info) {
2865 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2866 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants,
2867 &found_in_application_cache);
2868 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
2869 }
2870
2871 if (!keep_executable_info && !keep_statistic_info &&
2872 radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders,
2873 &found_in_application_cache) &&
2874 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
2875 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2876 return VK_SUCCESS;
2877 }
2878
2879 if (flags & VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_EXT) {
2880 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2881 return VK_PIPELINE_COMPILE_REQUIRED_EXT;
2882 }
2883
2884 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
2885 nir_builder fs_b;
2886 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2887 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2888 fs_m.nir = fs_b.shader;
2889 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2890 }
2891
2892 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2893 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
2894 unsigned subgroup_size = 64, ballot_bit_size = 64;
2895
2896 if (!modules[i])
2897 continue;
2898
2899 radv_start_feedback(stage_feedbacks[i]);
2900
2901 if (key->compute_subgroup_size) {
2902 /* Only compute shaders currently support requiring a
2903 * specific subgroup size.
2904 */
2905 assert(i == MESA_SHADER_COMPUTE);
2906 subgroup_size = key->compute_subgroup_size;
2907 ballot_bit_size = key->compute_subgroup_size;
2908 }
2909
2910 nir[i] = radv_shader_compile_to_nir(device, modules[i],
2911 stage ? stage->pName : "main", i,
2912 stage ? stage->pSpecializationInfo : NULL,
2913 flags, pipeline->layout,
2914 subgroup_size, ballot_bit_size);
2915
2916 /* We don't want to alter meta shaders IR directly so clone it
2917 * first.
2918 */
2919 if (nir[i]->info.name) {
2920 nir[i] = nir_shader_clone(NULL, nir[i]);
2921 }
2922
2923 radv_stop_feedback(stage_feedbacks[i], false);
2924 }
2925
2926 if (nir[MESA_SHADER_TESS_CTRL]) {
2927 nir_lower_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
2928 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
2929 }
2930
2931 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
2932 radv_link_shaders(pipeline, nir);
2933
2934 radv_set_linked_driver_locations(pipeline, nir, infos);
2935
2936 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2937 if (nir[i]) {
2938 /* do this again since information such as outputs_read can be out-of-date */
2939 nir_shader_gather_info(nir[i], nir_shader_get_entrypoint(nir[i]));
2940
2941 if (radv_use_llvm_for_stage(device, i)) {
2942 NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
2943 } else {
2944 NIR_PASS_V(nir[i], nir_lower_non_uniform_access,
2945 nir_lower_non_uniform_ubo_access |
2946 nir_lower_non_uniform_ssbo_access |
2947 nir_lower_non_uniform_texture_access |
2948 nir_lower_non_uniform_image_access);
2949 }
2950 NIR_PASS_V(nir[i], nir_lower_memory_model);
2951 }
2952 }
2953
2954 if (nir[MESA_SHADER_FRAGMENT])
2955 radv_lower_fs_io(nir[MESA_SHADER_FRAGMENT]);
2956
2957 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2958 if (radv_can_dump_shader(device, modules[i], false))
2959 nir_print_shader(nir[i], stderr);
2960 }
2961
2962 radv_fill_shader_keys(device, keys, key, nir);
2963
2964 radv_fill_shader_info(pipeline, pStages, keys, infos, nir);
2965
2966 if ((nir[MESA_SHADER_VERTEX] &&
2967 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) ||
2968 (nir[MESA_SHADER_TESS_EVAL] &&
2969 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg)) {
2970 struct gfx10_ngg_info *ngg_info;
2971
2972 if (nir[MESA_SHADER_GEOMETRY])
2973 ngg_info = &infos[MESA_SHADER_GEOMETRY].ngg_info;
2974 else if (nir[MESA_SHADER_TESS_CTRL])
2975 ngg_info = &infos[MESA_SHADER_TESS_EVAL].ngg_info;
2976 else
2977 ngg_info = &infos[MESA_SHADER_VERTEX].ngg_info;
2978
2979 gfx10_get_ngg_info(key, pipeline, nir, infos, ngg_info);
2980 } else if (nir[MESA_SHADER_GEOMETRY]) {
2981 struct gfx9_gs_info *gs_info =
2982 &infos[MESA_SHADER_GEOMETRY].gs_ring_info;
2983
2984 gfx9_get_gs_info(key, pipeline, nir, infos, gs_info);
2985 }
2986
2987 if(modules[MESA_SHADER_GEOMETRY]) {
2988 struct radv_shader_binary *gs_copy_binary = NULL;
2989 if (!pipeline->gs_copy_shader &&
2990 !radv_pipeline_has_ngg(pipeline)) {
2991 struct radv_shader_info info = {};
2992 struct radv_shader_variant_key key = {};
2993
2994 key.has_multiview_view_index =
2995 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index;
2996
2997 radv_nir_shader_info_pass(nir[MESA_SHADER_GEOMETRY],
2998 pipeline->layout, &key,
2999 &info,
3000 radv_use_llvm_for_stage(pipeline->device, MESA_SHADER_GEOMETRY));
3001 info.wave_size = 64; /* Wave32 not supported. */
3002 info.ballot_bit_size = 64;
3003
3004 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
3005 device, nir[MESA_SHADER_GEOMETRY], &info,
3006 &gs_copy_binary, keep_executable_info, keep_statistic_info,
3007 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index,
3008 disable_optimizations);
3009 }
3010
3011 if (!keep_executable_info && !keep_statistic_info && pipeline->gs_copy_shader) {
3012 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
3013 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
3014
3015 binaries[MESA_SHADER_GEOMETRY] = gs_copy_binary;
3016 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
3017
3018 radv_pipeline_cache_insert_shaders(device, cache,
3019 gs_copy_hash,
3020 variants,
3021 binaries);
3022 }
3023 free(gs_copy_binary);
3024 }
3025
3026 if (nir[MESA_SHADER_FRAGMENT]) {
3027 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
3028 radv_start_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT]);
3029
3030 pipeline->shaders[MESA_SHADER_FRAGMENT] =
3031 radv_shader_variant_compile(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
3032 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
3033 infos + MESA_SHADER_FRAGMENT,
3034 keep_executable_info, keep_statistic_info,
3035 disable_optimizations,
3036 &binaries[MESA_SHADER_FRAGMENT]);
3037
3038 radv_stop_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT], false);
3039 }
3040 }
3041
3042 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
3043 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
3044 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
3045 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
3046 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
3047
3048 radv_start_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL]);
3049
3050 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
3051 pipeline->layout,
3052 &key, &infos[MESA_SHADER_TESS_CTRL], keep_executable_info,
3053 keep_statistic_info,
3054 disable_optimizations,
3055 &binaries[MESA_SHADER_TESS_CTRL]);
3056
3057 radv_stop_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL], false);
3058 }
3059 modules[MESA_SHADER_VERTEX] = NULL;
3060 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
3061 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
3062 }
3063
3064 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
3065 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
3066 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
3067 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
3068
3069 radv_start_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY]);
3070
3071 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
3072 pipeline->layout,
3073 &keys[pre_stage], &infos[MESA_SHADER_GEOMETRY], keep_executable_info,
3074 keep_statistic_info,
3075 disable_optimizations,
3076 &binaries[MESA_SHADER_GEOMETRY]);
3077
3078 radv_stop_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY], false);
3079 }
3080 modules[pre_stage] = NULL;
3081 }
3082
3083 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
3084 if(modules[i] && !pipeline->shaders[i]) {
3085 if (i == MESA_SHADER_TESS_CTRL) {
3086 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.ls_outputs_written);
3087 }
3088 if (i == MESA_SHADER_TESS_EVAL) {
3089 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
3090 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
3091 }
3092
3093 radv_start_feedback(stage_feedbacks[i]);
3094
3095 pipeline->shaders[i] = radv_shader_variant_compile(device, modules[i], &nir[i], 1,
3096 pipeline->layout,
3097 keys + i, infos + i, keep_executable_info,
3098 keep_statistic_info,
3099 disable_optimizations,
3100 &binaries[i]);
3101
3102 radv_stop_feedback(stage_feedbacks[i], false);
3103 }
3104 }
3105
3106 if (!keep_executable_info && !keep_statistic_info) {
3107 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
3108 binaries);
3109 }
3110
3111 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
3112 free(binaries[i]);
3113 if (nir[i]) {
3114 ralloc_free(nir[i]);
3115
3116 if (radv_can_dump_shader_stats(device, modules[i])) {
3117 radv_dump_shader_stats(device, pipeline, i, stderr);
3118 }
3119 }
3120 }
3121
3122 if (fs_m.nir)
3123 ralloc_free(fs_m.nir);
3124
3125 radv_stop_feedback(pipeline_feedback, false);
3126 return VK_SUCCESS;
3127 }
3128
3129 static uint32_t
3130 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
3131 gl_shader_stage stage, enum chip_class chip_class)
3132 {
3133 bool has_gs = radv_pipeline_has_gs(pipeline);
3134 bool has_tess = radv_pipeline_has_tess(pipeline);
3135 bool has_ngg = radv_pipeline_has_ngg(pipeline);
3136
3137 switch (stage) {
3138 case MESA_SHADER_FRAGMENT:
3139 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
3140 case MESA_SHADER_VERTEX:
3141 if (has_tess) {
3142 if (chip_class >= GFX10) {
3143 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
3144 } else if (chip_class == GFX9) {
3145 return R_00B430_SPI_SHADER_USER_DATA_LS_0;
3146 } else {
3147 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
3148 }
3149
3150 }
3151
3152 if (has_gs) {
3153 if (chip_class >= GFX10) {
3154 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3155 } else {
3156 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
3157 }
3158 }
3159
3160 if (has_ngg)
3161 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3162
3163 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
3164 case MESA_SHADER_GEOMETRY:
3165 return chip_class == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
3166 R_00B230_SPI_SHADER_USER_DATA_GS_0;
3167 case MESA_SHADER_COMPUTE:
3168 return R_00B900_COMPUTE_USER_DATA_0;
3169 case MESA_SHADER_TESS_CTRL:
3170 return chip_class == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
3171 R_00B430_SPI_SHADER_USER_DATA_HS_0;
3172 case MESA_SHADER_TESS_EVAL:
3173 if (has_gs) {
3174 return chip_class >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0 :
3175 R_00B330_SPI_SHADER_USER_DATA_ES_0;
3176 } else if (has_ngg) {
3177 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3178 } else {
3179 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
3180 }
3181 default:
3182 unreachable("unknown shader");
3183 }
3184 }
3185
3186 struct radv_bin_size_entry {
3187 unsigned bpp;
3188 VkExtent2D extent;
3189 };
3190
3191 static VkExtent2D
3192 radv_gfx9_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3193 {
3194 static const struct radv_bin_size_entry color_size_table[][3][9] = {
3195 {
3196 /* One RB / SE */
3197 {
3198 /* One shader engine */
3199 { 0, {128, 128}},
3200 { 1, { 64, 128}},
3201 { 2, { 32, 128}},
3202 { 3, { 16, 128}},
3203 { 17, { 0, 0}},
3204 { UINT_MAX, { 0, 0}},
3205 },
3206 {
3207 /* Two shader engines */
3208 { 0, {128, 128}},
3209 { 2, { 64, 128}},
3210 { 3, { 32, 128}},
3211 { 5, { 16, 128}},
3212 { 17, { 0, 0}},
3213 { UINT_MAX, { 0, 0}},
3214 },
3215 {
3216 /* Four shader engines */
3217 { 0, {128, 128}},
3218 { 3, { 64, 128}},
3219 { 5, { 16, 128}},
3220 { 17, { 0, 0}},
3221 { UINT_MAX, { 0, 0}},
3222 },
3223 },
3224 {
3225 /* Two RB / SE */
3226 {
3227 /* One shader engine */
3228 { 0, {128, 128}},
3229 { 2, { 64, 128}},
3230 { 3, { 32, 128}},
3231 { 5, { 16, 128}},
3232 { 33, { 0, 0}},
3233 { UINT_MAX, { 0, 0}},
3234 },
3235 {
3236 /* Two shader engines */
3237 { 0, {128, 128}},
3238 { 3, { 64, 128}},
3239 { 5, { 32, 128}},
3240 { 9, { 16, 128}},
3241 { 33, { 0, 0}},
3242 { UINT_MAX, { 0, 0}},
3243 },
3244 {
3245 /* Four shader engines */
3246 { 0, {256, 256}},
3247 { 2, {128, 256}},
3248 { 3, {128, 128}},
3249 { 5, { 64, 128}},
3250 { 9, { 16, 128}},
3251 { 33, { 0, 0}},
3252 { UINT_MAX, { 0, 0}},
3253 },
3254 },
3255 {
3256 /* Four RB / SE */
3257 {
3258 /* One shader engine */
3259 { 0, {128, 256}},
3260 { 2, {128, 128}},
3261 { 3, { 64, 128}},
3262 { 5, { 32, 128}},
3263 { 9, { 16, 128}},
3264 { 33, { 0, 0}},
3265 { UINT_MAX, { 0, 0}},
3266 },
3267 {
3268 /* Two shader engines */
3269 { 0, {256, 256}},
3270 { 2, {128, 256}},
3271 { 3, {128, 128}},
3272 { 5, { 64, 128}},
3273 { 9, { 32, 128}},
3274 { 17, { 16, 128}},
3275 { 33, { 0, 0}},
3276 { UINT_MAX, { 0, 0}},
3277 },
3278 {
3279 /* Four shader engines */
3280 { 0, {256, 512}},
3281 { 2, {256, 256}},
3282 { 3, {128, 256}},
3283 { 5, {128, 128}},
3284 { 9, { 64, 128}},
3285 { 17, { 16, 128}},
3286 { 33, { 0, 0}},
3287 { UINT_MAX, { 0, 0}},
3288 },
3289 },
3290 };
3291 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
3292 {
3293 // One RB / SE
3294 {
3295 // One shader engine
3296 { 0, {128, 256}},
3297 { 2, {128, 128}},
3298 { 4, { 64, 128}},
3299 { 7, { 32, 128}},
3300 { 13, { 16, 128}},
3301 { 49, { 0, 0}},
3302 { UINT_MAX, { 0, 0}},
3303 },
3304 {
3305 // Two shader engines
3306 { 0, {256, 256}},
3307 { 2, {128, 256}},
3308 { 4, {128, 128}},
3309 { 7, { 64, 128}},
3310 { 13, { 32, 128}},
3311 { 25, { 16, 128}},
3312 { 49, { 0, 0}},
3313 { UINT_MAX, { 0, 0}},
3314 },
3315 {
3316 // Four shader engines
3317 { 0, {256, 512}},
3318 { 2, {256, 256}},
3319 { 4, {128, 256}},
3320 { 7, {128, 128}},
3321 { 13, { 64, 128}},
3322 { 25, { 16, 128}},
3323 { 49, { 0, 0}},
3324 { UINT_MAX, { 0, 0}},
3325 },
3326 },
3327 {
3328 // Two RB / SE
3329 {
3330 // One shader engine
3331 { 0, {256, 256}},
3332 { 2, {128, 256}},
3333 { 4, {128, 128}},
3334 { 7, { 64, 128}},
3335 { 13, { 32, 128}},
3336 { 25, { 16, 128}},
3337 { 97, { 0, 0}},
3338 { UINT_MAX, { 0, 0}},
3339 },
3340 {
3341 // Two shader engines
3342 { 0, {256, 512}},
3343 { 2, {256, 256}},
3344 { 4, {128, 256}},
3345 { 7, {128, 128}},
3346 { 13, { 64, 128}},
3347 { 25, { 32, 128}},
3348 { 49, { 16, 128}},
3349 { 97, { 0, 0}},
3350 { UINT_MAX, { 0, 0}},
3351 },
3352 {
3353 // Four shader engines
3354 { 0, {512, 512}},
3355 { 2, {256, 512}},
3356 { 4, {256, 256}},
3357 { 7, {128, 256}},
3358 { 13, {128, 128}},
3359 { 25, { 64, 128}},
3360 { 49, { 16, 128}},
3361 { 97, { 0, 0}},
3362 { UINT_MAX, { 0, 0}},
3363 },
3364 },
3365 {
3366 // Four RB / SE
3367 {
3368 // One shader engine
3369 { 0, {256, 512}},
3370 { 2, {256, 256}},
3371 { 4, {128, 256}},
3372 { 7, {128, 128}},
3373 { 13, { 64, 128}},
3374 { 25, { 32, 128}},
3375 { 49, { 16, 128}},
3376 { UINT_MAX, { 0, 0}},
3377 },
3378 {
3379 // Two shader engines
3380 { 0, {512, 512}},
3381 { 2, {256, 512}},
3382 { 4, {256, 256}},
3383 { 7, {128, 256}},
3384 { 13, {128, 128}},
3385 { 25, { 64, 128}},
3386 { 49, { 32, 128}},
3387 { 97, { 16, 128}},
3388 { UINT_MAX, { 0, 0}},
3389 },
3390 {
3391 // Four shader engines
3392 { 0, {512, 512}},
3393 { 4, {256, 512}},
3394 { 7, {256, 256}},
3395 { 13, {128, 256}},
3396 { 25, {128, 128}},
3397 { 49, { 64, 128}},
3398 { 97, { 16, 128}},
3399 { UINT_MAX, { 0, 0}},
3400 },
3401 },
3402 };
3403
3404 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3405 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3406 VkExtent2D extent = {512, 512};
3407
3408 unsigned log_num_rb_per_se =
3409 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
3410 pipeline->device->physical_device->rad_info.max_se);
3411 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
3412
3413 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3414 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
3415 unsigned effective_samples = total_samples;
3416 unsigned color_bytes_per_pixel = 0;
3417
3418 const VkPipelineColorBlendStateCreateInfo *vkblend =
3419 radv_pipeline_get_color_blend_state(pCreateInfo);
3420 if (vkblend) {
3421 for (unsigned i = 0; i < subpass->color_count; i++) {
3422 if (!vkblend->pAttachments[i].colorWriteMask)
3423 continue;
3424
3425 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3426 continue;
3427
3428 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3429 color_bytes_per_pixel += vk_format_get_blocksize(format);
3430 }
3431
3432 /* MSAA images typically don't use all samples all the time. */
3433 if (effective_samples >= 2 && ps_iter_samples <= 1)
3434 effective_samples = 2;
3435 color_bytes_per_pixel *= effective_samples;
3436 }
3437
3438 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
3439 while(color_entry[1].bpp <= color_bytes_per_pixel)
3440 ++color_entry;
3441
3442 extent = color_entry->extent;
3443
3444 if (subpass->depth_stencil_attachment) {
3445 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3446
3447 /* Coefficients taken from AMDVLK */
3448 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3449 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3450 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
3451
3452 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
3453 while(ds_entry[1].bpp <= ds_bytes_per_pixel)
3454 ++ds_entry;
3455
3456 if (ds_entry->extent.width * ds_entry->extent.height < extent.width * extent.height)
3457 extent = ds_entry->extent;
3458 }
3459
3460 return extent;
3461 }
3462
3463 static VkExtent2D
3464 radv_gfx10_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3465 {
3466 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3467 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3468 VkExtent2D extent = {512, 512};
3469
3470 const unsigned db_tag_size = 64;
3471 const unsigned db_tag_count = 312;
3472 const unsigned color_tag_size = 1024;
3473 const unsigned color_tag_count = 31;
3474 const unsigned fmask_tag_size = 256;
3475 const unsigned fmask_tag_count = 44;
3476
3477 const unsigned rb_count = pipeline->device->physical_device->rad_info.num_render_backends;
3478 const unsigned pipe_count = MAX2(rb_count, pipeline->device->physical_device->rad_info.num_sdp_interfaces);
3479
3480 const unsigned db_tag_part = (db_tag_count * rb_count / pipe_count) * db_tag_size * pipe_count;
3481 const unsigned color_tag_part = (color_tag_count * rb_count / pipe_count) * color_tag_size * pipe_count;
3482 const unsigned fmask_tag_part = (fmask_tag_count * rb_count / pipe_count) * fmask_tag_size * pipe_count;
3483
3484 const unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3485 const unsigned samples_log = util_logbase2_ceil(total_samples);
3486
3487 unsigned color_bytes_per_pixel = 0;
3488 unsigned fmask_bytes_per_pixel = 0;
3489
3490 const VkPipelineColorBlendStateCreateInfo *vkblend =
3491 radv_pipeline_get_color_blend_state(pCreateInfo);
3492 if (vkblend) {
3493 for (unsigned i = 0; i < subpass->color_count; i++) {
3494 if (!vkblend->pAttachments[i].colorWriteMask)
3495 continue;
3496
3497 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3498 continue;
3499
3500 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3501 color_bytes_per_pixel += vk_format_get_blocksize(format);
3502
3503 if (total_samples > 1) {
3504 assert(samples_log <= 3);
3505 const unsigned fmask_array[] = {0, 1, 1, 4};
3506 fmask_bytes_per_pixel += fmask_array[samples_log];
3507 }
3508 }
3509
3510 color_bytes_per_pixel *= total_samples;
3511 }
3512 color_bytes_per_pixel = MAX2(color_bytes_per_pixel, 1);
3513
3514 const unsigned color_pixel_count_log = util_logbase2(color_tag_part / color_bytes_per_pixel);
3515 extent.width = 1ull << ((color_pixel_count_log + 1) / 2);
3516 extent.height = 1ull << (color_pixel_count_log / 2);
3517
3518 if (fmask_bytes_per_pixel) {
3519 const unsigned fmask_pixel_count_log = util_logbase2(fmask_tag_part / fmask_bytes_per_pixel);
3520
3521 const VkExtent2D fmask_extent = (VkExtent2D){
3522 .width = 1ull << ((fmask_pixel_count_log + 1) / 2),
3523 .height = 1ull << (color_pixel_count_log / 2)
3524 };
3525
3526 if (fmask_extent.width * fmask_extent.height < extent.width * extent.height)
3527 extent = fmask_extent;
3528 }
3529
3530 if (subpass->depth_stencil_attachment) {
3531 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3532
3533 /* Coefficients taken from AMDVLK */
3534 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3535 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3536 unsigned db_bytes_per_pixel = (depth_coeff + stencil_coeff) * total_samples;
3537
3538 const unsigned db_pixel_count_log = util_logbase2(db_tag_part / db_bytes_per_pixel);
3539
3540 const VkExtent2D db_extent = (VkExtent2D){
3541 .width = 1ull << ((db_pixel_count_log + 1) / 2),
3542 .height = 1ull << (color_pixel_count_log / 2)
3543 };
3544
3545 if (db_extent.width * db_extent.height < extent.width * extent.height)
3546 extent = db_extent;
3547 }
3548
3549 extent.width = MAX2(extent.width, 128);
3550 extent.height = MAX2(extent.width, 64);
3551
3552 return extent;
3553 }
3554
3555 static void
3556 radv_pipeline_init_disabled_binning_state(struct radv_pipeline *pipeline,
3557 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3558 {
3559 uint32_t pa_sc_binner_cntl_0 =
3560 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
3561 S_028C44_DISABLE_START_OF_PRIM(1);
3562 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3563
3564 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3565 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3566 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3567 const VkPipelineColorBlendStateCreateInfo *vkblend =
3568 radv_pipeline_get_color_blend_state(pCreateInfo);
3569 unsigned min_bytes_per_pixel = 0;
3570
3571 if (vkblend) {
3572 for (unsigned i = 0; i < subpass->color_count; i++) {
3573 if (!vkblend->pAttachments[i].colorWriteMask)
3574 continue;
3575
3576 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3577 continue;
3578
3579 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3580 unsigned bytes = vk_format_get_blocksize(format);
3581 if (!min_bytes_per_pixel || bytes < min_bytes_per_pixel)
3582 min_bytes_per_pixel = bytes;
3583 }
3584 }
3585
3586 pa_sc_binner_cntl_0 =
3587 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) |
3588 S_028C44_BIN_SIZE_X(0) |
3589 S_028C44_BIN_SIZE_Y(0) |
3590 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3591 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel <= 4 ? 2 : 1) | /* 128 or 64 */
3592 S_028C44_DISABLE_START_OF_PRIM(1);
3593 }
3594
3595 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3596 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3597 }
3598
3599 struct radv_binning_settings
3600 radv_get_binning_settings(const struct radv_physical_device *pdev)
3601 {
3602 struct radv_binning_settings settings;
3603 if (pdev->rad_info.has_dedicated_vram) {
3604 if (pdev->rad_info.num_render_backends > 4) {
3605 settings.context_states_per_bin = 1;
3606 settings.persistent_states_per_bin = 1;
3607 } else {
3608 settings.context_states_per_bin = 3;
3609 settings.persistent_states_per_bin = 8;
3610 }
3611 settings.fpovs_per_batch = 63;
3612 } else {
3613 /* The context states are affected by the scissor bug. */
3614 settings.context_states_per_bin = 6;
3615 /* 32 causes hangs for RAVEN. */
3616 settings.persistent_states_per_bin = 16;
3617 settings.fpovs_per_batch = 63;
3618 }
3619
3620 if (pdev->rad_info.has_gfx9_scissor_bug)
3621 settings.context_states_per_bin = 1;
3622
3623 return settings;
3624 }
3625
3626 static void
3627 radv_pipeline_init_binning_state(struct radv_pipeline *pipeline,
3628 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3629 const struct radv_blend_state *blend)
3630 {
3631 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
3632 return;
3633
3634 VkExtent2D bin_size;
3635 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3636 bin_size = radv_gfx10_compute_bin_size(pipeline, pCreateInfo);
3637 } else if (pipeline->device->physical_device->rad_info.chip_class == GFX9) {
3638 bin_size = radv_gfx9_compute_bin_size(pipeline, pCreateInfo);
3639 } else
3640 unreachable("Unhandled generation for binning bin size calculation");
3641
3642 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
3643 struct radv_binning_settings settings =
3644 radv_get_binning_settings(pipeline->device->physical_device);
3645
3646 bool disable_start_of_prim = true;
3647 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3648
3649 const struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3650
3651 if (pipeline->device->dfsm_allowed && ps &&
3652 !ps->info.ps.can_discard &&
3653 !ps->info.ps.writes_memory &&
3654 blend->cb_target_enabled_4bit) {
3655 db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_AUTO);
3656 disable_start_of_prim = (blend->blend_enable_4bit & blend->cb_target_enabled_4bit) != 0;
3657 }
3658
3659 const uint32_t pa_sc_binner_cntl_0 =
3660 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
3661 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
3662 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
3663 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
3664 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
3665 S_028C44_CONTEXT_STATES_PER_BIN(settings.context_states_per_bin - 1) |
3666 S_028C44_PERSISTENT_STATES_PER_BIN(settings.persistent_states_per_bin - 1) |
3667 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim) |
3668 S_028C44_FPOVS_PER_BATCH(settings.fpovs_per_batch) |
3669 S_028C44_OPTIMAL_BIN_SELECTION(1);
3670
3671 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3672 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3673 } else
3674 radv_pipeline_init_disabled_binning_state(pipeline, pCreateInfo);
3675 }
3676
3677
3678 static void
3679 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs,
3680 const struct radv_pipeline *pipeline,
3681 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3682 const struct radv_graphics_pipeline_create_info *extra)
3683 {
3684 const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
3685 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3686 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3687 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3688 struct radv_render_pass_attachment *attachment = NULL;
3689 uint32_t db_render_control = 0, db_render_override2 = 0;
3690 uint32_t db_render_override = 0;
3691
3692 if (subpass->depth_stencil_attachment)
3693 attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3694
3695 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
3696
3697 if (vkds && has_depth_attachment) {
3698 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3699 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
3700
3701 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10_3)
3702 db_render_override2 |= S_028010_CENTROID_COMPUTATION_MODE(2);
3703 }
3704
3705 if (attachment && extra) {
3706 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
3707 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
3708
3709 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->resummarize_enable);
3710 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->depth_compress_disable);
3711 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->stencil_compress_disable);
3712 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
3713 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
3714 }
3715
3716 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3717 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
3718
3719 if (!pCreateInfo->pRasterizationState->depthClampEnable &&
3720 ps->info.ps.writes_z) {
3721 /* From VK_EXT_depth_range_unrestricted spec:
3722 *
3723 * "The behavior described in Primitive Clipping still applies.
3724 * If depth clamping is disabled the depth values are still
3725 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3726 * depth clamping is enabled the above equation is ignored and
3727 * the depth values are instead clamped to the VkViewport
3728 * minDepth and maxDepth values, which in the case of this
3729 * extension can be outside of the 0.0 to 1.0 range."
3730 */
3731 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3732 }
3733
3734 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control);
3735 radeon_set_context_reg(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
3736 radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
3737 }
3738
3739 static void
3740 radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
3741 const struct radv_pipeline *pipeline,
3742 const struct radv_blend_state *blend)
3743 {
3744 radeon_set_context_reg_seq(ctx_cs, R_028780_CB_BLEND0_CONTROL, 8);
3745 radeon_emit_array(ctx_cs, blend->cb_blend_control,
3746 8);
3747 radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
3748 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
3749
3750 if (pipeline->device->physical_device->rad_info.has_rbplus) {
3751
3752 radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
3753 radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
3754 }
3755
3756 radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
3757
3758 radeon_set_context_reg(ctx_cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
3759 radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
3760 }
3761
3762 static void
3763 radv_pipeline_generate_raster_state(struct radeon_cmdbuf *ctx_cs,
3764 const struct radv_pipeline *pipeline,
3765 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3766 {
3767 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
3768 const VkConservativeRasterizationModeEXT mode =
3769 radv_get_conservative_raster_mode(vkraster);
3770 uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3771 bool depth_clip_disable = vkraster->depthClampEnable;
3772
3773 const VkPipelineRasterizationDepthClipStateCreateInfoEXT *depth_clip_state =
3774 vk_find_struct_const(vkraster->pNext, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT);
3775 if (depth_clip_state) {
3776 depth_clip_disable = !depth_clip_state->depthClipEnable;
3777 }
3778
3779 radeon_set_context_reg(ctx_cs, R_028810_PA_CL_CLIP_CNTL,
3780 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3781 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable ? 1 : 0) |
3782 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable ? 1 : 0) |
3783 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
3784 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3785
3786 radeon_set_context_reg(ctx_cs, R_028BDC_PA_SC_LINE_CNTL,
3787 S_028BDC_DX10_DIAMOND_TEST_ENA(1));
3788
3789 /* Conservative rasterization. */
3790 if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
3791 pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3792 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3793 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3794
3795 if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) {
3796 pa_sc_conservative_rast |=
3797 S_028C4C_OVER_RAST_ENABLE(1) |
3798 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3799 S_028C4C_UNDER_RAST_ENABLE(0) |
3800 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3801 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3802 } else {
3803 assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT);
3804 pa_sc_conservative_rast |=
3805 S_028C4C_OVER_RAST_ENABLE(0) |
3806 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3807 S_028C4C_UNDER_RAST_ENABLE(1) |
3808 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3809 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3810 }
3811 }
3812
3813 radeon_set_context_reg(ctx_cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
3814 pa_sc_conservative_rast);
3815 }
3816
3817
3818 static void
3819 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
3820 const struct radv_pipeline *pipeline)
3821 {
3822 const struct radv_multisample_state *ms = &pipeline->graphics.ms;
3823
3824 radeon_set_context_reg_seq(ctx_cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3825 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[0]);
3826 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]);
3827
3828 radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa);
3829 radeon_set_context_reg(ctx_cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
3830 radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
3831 radeon_set_context_reg(ctx_cs, R_028BE0_PA_SC_AA_CONFIG, ms->pa_sc_aa_config);
3832
3833 /* The exclusion bits can be set to improve rasterization efficiency
3834 * if no sample lies on the pixel boundary (-8 sample offset). It's
3835 * currently always TRUE because the driver doesn't support 16 samples.
3836 */
3837 bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= GFX7;
3838 radeon_set_context_reg(ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3839 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3840 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3841
3842 /* GFX9: Flush DFSM when the AA mode changes. */
3843 if (pipeline->device->dfsm_allowed) {
3844 radeon_emit(ctx_cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3845 radeon_emit(ctx_cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3846 }
3847 }
3848
3849 static void
3850 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
3851 const struct radv_pipeline *pipeline)
3852 {
3853 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3854 const struct radv_shader_variant *vs =
3855 pipeline->shaders[MESA_SHADER_TESS_EVAL] ?
3856 pipeline->shaders[MESA_SHADER_TESS_EVAL] :
3857 pipeline->shaders[MESA_SHADER_VERTEX];
3858 unsigned vgt_primitiveid_en = 0;
3859 uint32_t vgt_gs_mode = 0;
3860
3861 if (radv_pipeline_has_ngg(pipeline))
3862 return;
3863
3864 if (radv_pipeline_has_gs(pipeline)) {
3865 const struct radv_shader_variant *gs =
3866 pipeline->shaders[MESA_SHADER_GEOMETRY];
3867
3868 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
3869 pipeline->device->physical_device->rad_info.chip_class);
3870 } else if (outinfo->export_prim_id || vs->info.uses_prim_id) {
3871 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
3872 vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(1);
3873 }
3874
3875 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
3876 radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
3877 }
3878
3879 static void
3880 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
3881 struct radeon_cmdbuf *cs,
3882 const struct radv_pipeline *pipeline,
3883 const struct radv_shader_variant *shader)
3884 {
3885 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3886
3887 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
3888 radeon_emit(cs, va >> 8);
3889 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
3890 radeon_emit(cs, shader->config.rsrc1);
3891 radeon_emit(cs, shader->config.rsrc2);
3892
3893 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3894 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3895 clip_dist_mask = outinfo->clip_dist_mask;
3896 cull_dist_mask = outinfo->cull_dist_mask;
3897 total_mask = clip_dist_mask | cull_dist_mask;
3898 bool misc_vec_ena = outinfo->writes_pointsize ||
3899 outinfo->writes_layer ||
3900 outinfo->writes_viewport_index;
3901 unsigned spi_vs_out_config, nparams;
3902
3903 /* VS is required to export at least one param. */
3904 nparams = MAX2(outinfo->param_exports, 1);
3905 spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
3906
3907 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3908 spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0);
3909 }
3910
3911 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, spi_vs_out_config);
3912
3913 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3914 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3915 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3916 V_02870C_SPI_SHADER_4COMP :
3917 V_02870C_SPI_SHADER_NONE) |
3918 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3919 V_02870C_SPI_SHADER_4COMP :
3920 V_02870C_SPI_SHADER_NONE) |
3921 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3922 V_02870C_SPI_SHADER_4COMP :
3923 V_02870C_SPI_SHADER_NONE));
3924
3925 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3926 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3927 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3928 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3929 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3930 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3931 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3932 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3933 S_02881C_BYPASS_PRIM_RATE_COMBINER(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) |
3934 S_02881C_BYPASS_VTX_RATE_COMBINER(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) |
3935 cull_dist_mask << 8 |
3936 clip_dist_mask);
3937
3938 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
3939 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
3940 outinfo->writes_viewport_index);
3941 }
3942
3943 static void
3944 radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs,
3945 const struct radv_pipeline *pipeline,
3946 const struct radv_shader_variant *shader)
3947 {
3948 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3949
3950 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
3951 radeon_emit(cs, va >> 8);
3952 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3953 radeon_emit(cs, shader->config.rsrc1);
3954 radeon_emit(cs, shader->config.rsrc2);
3955 }
3956
3957 static void
3958 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs,
3959 const struct radv_pipeline *pipeline,
3960 const struct radv_shader_variant *shader)
3961 {
3962 unsigned num_lds_blocks = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_lds_blocks;
3963 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3964 uint32_t rsrc2 = shader->config.rsrc2;
3965
3966 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3967 radeon_emit(cs, va >> 8);
3968 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3969
3970 rsrc2 |= S_00B52C_LDS_SIZE(num_lds_blocks);
3971 if (pipeline->device->physical_device->rad_info.chip_class == GFX7 &&
3972 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
3973 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
3974
3975 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
3976 radeon_emit(cs, shader->config.rsrc1);
3977 radeon_emit(cs, rsrc2);
3978 }
3979
3980 static void
3981 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
3982 struct radeon_cmdbuf *cs,
3983 const struct radv_pipeline *pipeline,
3984 const struct radv_shader_variant *shader)
3985 {
3986 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3987 gl_shader_stage es_type =
3988 radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
3989 struct radv_shader_variant *es =
3990 es_type == MESA_SHADER_TESS_EVAL ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX];
3991 const struct gfx10_ngg_info *ngg_state = &shader->info.ngg_info;
3992
3993 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
3994 radeon_emit(cs, va >> 8);
3995 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3996 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
3997 radeon_emit(cs, shader->config.rsrc1);
3998 radeon_emit(cs, shader->config.rsrc2);
3999
4000 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
4001 unsigned clip_dist_mask, cull_dist_mask, total_mask;
4002 clip_dist_mask = outinfo->clip_dist_mask;
4003 cull_dist_mask = outinfo->cull_dist_mask;
4004 total_mask = clip_dist_mask | cull_dist_mask;
4005 bool misc_vec_ena = outinfo->writes_pointsize ||
4006 outinfo->writes_layer ||
4007 outinfo->writes_viewport_index;
4008 bool es_enable_prim_id = outinfo->export_prim_id ||
4009 (es && es->info.uses_prim_id);
4010 bool break_wave_at_eoi = false;
4011 unsigned ge_cntl;
4012 unsigned nparams;
4013
4014 if (es_type == MESA_SHADER_TESS_EVAL) {
4015 struct radv_shader_variant *gs =
4016 pipeline->shaders[MESA_SHADER_GEOMETRY];
4017
4018 if (es_enable_prim_id || (gs && gs->info.uses_prim_id))
4019 break_wave_at_eoi = true;
4020 }
4021
4022 nparams = MAX2(outinfo->param_exports, 1);
4023 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG,
4024 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
4025 S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0));
4026
4027 radeon_set_context_reg(ctx_cs, R_028708_SPI_SHADER_IDX_FORMAT,
4028 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP));
4029 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
4030 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
4031 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
4032 V_02870C_SPI_SHADER_4COMP :
4033 V_02870C_SPI_SHADER_NONE) |
4034 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
4035 V_02870C_SPI_SHADER_4COMP :
4036 V_02870C_SPI_SHADER_NONE) |
4037 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
4038 V_02870C_SPI_SHADER_4COMP :
4039 V_02870C_SPI_SHADER_NONE));
4040
4041 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
4042 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
4043 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
4044 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
4045 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
4046 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
4047 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
4048 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
4049 S_02881C_BYPASS_PRIM_RATE_COMBINER(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) |
4050 S_02881C_BYPASS_VTX_RATE_COMBINER(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) |
4051 cull_dist_mask << 8 |
4052 clip_dist_mask);
4053
4054 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN,
4055 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
4056 S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo->export_prim_id));
4057
4058 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
4059 ngg_state->vgt_esgs_ring_itemsize);
4060
4061 /* NGG specific registers. */
4062 struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
4063 uint32_t gs_num_invocations = gs ? gs->info.gs.invocations : 1;
4064
4065 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
4066 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state->hw_max_esverts) |
4067 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state->max_gsprims) |
4068 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state->max_gsprims * gs_num_invocations));
4069 radeon_set_context_reg(ctx_cs, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
4070 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state->max_out_verts));
4071 radeon_set_context_reg(ctx_cs, R_028B4C_GE_NGG_SUBGRP_CNTL,
4072 S_028B4C_PRIM_AMP_FACTOR(ngg_state->prim_amp_factor) |
4073 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
4074 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
4075 S_028B90_CNT(gs_num_invocations) |
4076 S_028B90_ENABLE(gs_num_invocations > 1) |
4077 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state->max_vert_out_per_gs_instance));
4078
4079 /* User edge flags are set by the pos exports. If user edge flags are
4080 * not used, we must use hw-generated edge flags and pass them via
4081 * the prim export to prevent drawing lines on internal edges of
4082 * decomposed primitives (such as quads) with polygon mode = lines.
4083 *
4084 * TODO: We should combine hw-generated edge flags with user edge
4085 * flags in the shader.
4086 */
4087 radeon_set_context_reg(ctx_cs, R_028838_PA_CL_NGG_CNTL,
4088 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) &&
4089 !radv_pipeline_has_gs(pipeline)) |
4090 /* Reuse for NGG. */
4091 S_028838_VERTEX_REUSE_DEPTH(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3 ? 30 : 0));
4092
4093 ge_cntl = S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) |
4094 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
4095 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
4096
4097 /* Bug workaround for a possible hang with non-tessellation cases.
4098 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
4099 *
4100 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
4101 */
4102 if (pipeline->device->physical_device->rad_info.chip_class == GFX10 &&
4103 !radv_pipeline_has_tess(pipeline) &&
4104 ngg_state->hw_max_esverts != 256) {
4105 ge_cntl &= C_03096C_VERT_GRP_SIZE;
4106
4107 if (ngg_state->hw_max_esverts > 5) {
4108 ge_cntl |= S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts - 5);
4109 }
4110 }
4111
4112 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, ge_cntl);
4113 }
4114
4115 static void
4116 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
4117 const struct radv_pipeline *pipeline,
4118 const struct radv_shader_variant *shader)
4119 {
4120 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
4121
4122 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4123 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4124 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
4125 radeon_emit(cs, va >> 8);
4126 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
4127 } else {
4128 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
4129 radeon_emit(cs, va >> 8);
4130 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
4131 }
4132
4133 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
4134 radeon_emit(cs, shader->config.rsrc1);
4135 radeon_emit(cs, shader->config.rsrc2);
4136 } else {
4137 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
4138 radeon_emit(cs, va >> 8);
4139 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
4140 radeon_emit(cs, shader->config.rsrc1);
4141 radeon_emit(cs, shader->config.rsrc2);
4142 }
4143 }
4144
4145 static void
4146 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *ctx_cs,
4147 struct radeon_cmdbuf *cs,
4148 const struct radv_pipeline *pipeline)
4149 {
4150 struct radv_shader_variant *vs;
4151
4152 /* Skip shaders merged into HS/GS */
4153 vs = pipeline->shaders[MESA_SHADER_VERTEX];
4154 if (!vs)
4155 return;
4156
4157 if (vs->info.vs.as_ls)
4158 radv_pipeline_generate_hw_ls(cs, pipeline, vs);
4159 else if (vs->info.vs.as_es)
4160 radv_pipeline_generate_hw_es(cs, pipeline, vs);
4161 else if (vs->info.is_ngg)
4162 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, vs);
4163 else
4164 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, vs);
4165 }
4166
4167 static void
4168 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs,
4169 struct radeon_cmdbuf *cs,
4170 const struct radv_pipeline *pipeline)
4171 {
4172 struct radv_shader_variant *tes, *tcs;
4173
4174 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
4175 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
4176
4177 if (tes) {
4178 if (tes->info.is_ngg) {
4179 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, tes);
4180 } else if (tes->info.tes.as_es)
4181 radv_pipeline_generate_hw_es(cs, pipeline, tes);
4182 else
4183 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes);
4184 }
4185
4186 radv_pipeline_generate_hw_hs(cs, pipeline, tcs);
4187
4188 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 &&
4189 !radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
4190 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
4191 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4192 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4193 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4194 }
4195 }
4196
4197 static void
4198 radv_pipeline_generate_tess_state(struct radeon_cmdbuf *ctx_cs,
4199 const struct radv_pipeline *pipeline,
4200 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4201 {
4202 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
4203 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
4204 unsigned num_tcs_input_cp, num_tcs_output_cp, num_patches;
4205 unsigned ls_hs_config;
4206
4207 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
4208 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
4209 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
4210
4211 ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
4212 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
4213 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
4214
4215 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
4216 radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG,
4217 2, ls_hs_config);
4218 } else {
4219 radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG,
4220 ls_hs_config);
4221 }
4222
4223 switch (tes->info.tes.primitive_mode) {
4224 case GL_TRIANGLES:
4225 type = V_028B6C_TESS_TRIANGLE;
4226 break;
4227 case GL_QUADS:
4228 type = V_028B6C_TESS_QUAD;
4229 break;
4230 case GL_ISOLINES:
4231 type = V_028B6C_TESS_ISOLINE;
4232 break;
4233 }
4234
4235 switch (tes->info.tes.spacing) {
4236 case TESS_SPACING_EQUAL:
4237 partitioning = V_028B6C_PART_INTEGER;
4238 break;
4239 case TESS_SPACING_FRACTIONAL_ODD:
4240 partitioning = V_028B6C_PART_FRAC_ODD;
4241 break;
4242 case TESS_SPACING_FRACTIONAL_EVEN:
4243 partitioning = V_028B6C_PART_FRAC_EVEN;
4244 break;
4245 default:
4246 break;
4247 }
4248
4249 bool ccw = tes->info.tes.ccw;
4250 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_origin_state =
4251 vk_find_struct_const(pCreateInfo->pTessellationState,
4252 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
4253
4254 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT)
4255 ccw = !ccw;
4256
4257 if (tes->info.tes.point_mode)
4258 topology = V_028B6C_OUTPUT_POINT;
4259 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
4260 topology = V_028B6C_OUTPUT_LINE;
4261 else if (ccw)
4262 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
4263 else
4264 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
4265
4266 if (pipeline->device->physical_device->rad_info.has_distributed_tess) {
4267 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
4268 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
4269 distribution_mode = V_028B6C_TRAPEZOIDS;
4270 else
4271 distribution_mode = V_028B6C_DONUTS;
4272 } else
4273 distribution_mode = V_028B6C_NO_DIST;
4274
4275 radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM,
4276 S_028B6C_TYPE(type) |
4277 S_028B6C_PARTITIONING(partitioning) |
4278 S_028B6C_TOPOLOGY(topology) |
4279 S_028B6C_DISTRIBUTION_MODE(distribution_mode));
4280 }
4281
4282 static void
4283 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs,
4284 struct radeon_cmdbuf *cs,
4285 const struct radv_pipeline *pipeline,
4286 const struct radv_shader_variant *gs)
4287 {
4288 const struct gfx9_gs_info *gs_state = &gs->info.gs_ring_info;
4289 unsigned gs_max_out_vertices;
4290 const uint8_t *num_components;
4291 uint8_t max_stream;
4292 unsigned offset;
4293 uint64_t va;
4294
4295 gs_max_out_vertices = gs->info.gs.vertices_out;
4296 max_stream = gs->info.gs.max_stream;
4297 num_components = gs->info.gs.num_stream_output_components;
4298
4299 offset = num_components[0] * gs_max_out_vertices;
4300
4301 radeon_set_context_reg_seq(ctx_cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
4302 radeon_emit(ctx_cs, offset);
4303 if (max_stream >= 1)
4304 offset += num_components[1] * gs_max_out_vertices;
4305 radeon_emit(ctx_cs, offset);
4306 if (max_stream >= 2)
4307 offset += num_components[2] * gs_max_out_vertices;
4308 radeon_emit(ctx_cs, offset);
4309 if (max_stream >= 3)
4310 offset += num_components[3] * gs_max_out_vertices;
4311 radeon_set_context_reg(ctx_cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
4312
4313 radeon_set_context_reg_seq(ctx_cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
4314 radeon_emit(ctx_cs, num_components[0]);
4315 radeon_emit(ctx_cs, (max_stream >= 1) ? num_components[1] : 0);
4316 radeon_emit(ctx_cs, (max_stream >= 2) ? num_components[2] : 0);
4317 radeon_emit(ctx_cs, (max_stream >= 3) ? num_components[3] : 0);
4318
4319 uint32_t gs_num_invocations = gs->info.gs.invocations;
4320 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
4321 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
4322 S_028B90_ENABLE(gs_num_invocations > 0));
4323
4324 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
4325 gs_state->vgt_esgs_ring_itemsize);
4326
4327 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
4328
4329 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4330 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4331 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
4332 radeon_emit(cs, va >> 8);
4333 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
4334 } else {
4335 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
4336 radeon_emit(cs, va >> 8);
4337 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
4338 }
4339
4340 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
4341 radeon_emit(cs, gs->config.rsrc1);
4342 radeon_emit(cs, gs->config.rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
4343
4344 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
4345 radeon_set_context_reg(ctx_cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
4346 } else {
4347 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
4348 radeon_emit(cs, va >> 8);
4349 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
4350 radeon_emit(cs, gs->config.rsrc1);
4351 radeon_emit(cs, gs->config.rsrc2);
4352 }
4353
4354 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, pipeline->gs_copy_shader);
4355 }
4356
4357 static void
4358 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
4359 struct radeon_cmdbuf *cs,
4360 const struct radv_pipeline *pipeline)
4361 {
4362 struct radv_shader_variant *gs;
4363
4364 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
4365 if (!gs)
4366 return;
4367
4368 if (gs->info.is_ngg)
4369 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, gs);
4370 else
4371 radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs);
4372
4373 radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT,
4374 gs->info.gs.vertices_out);
4375 }
4376
4377 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade,
4378 bool explicit, bool float16)
4379 {
4380 uint32_t ps_input_cntl;
4381 if (offset <= AC_EXP_PARAM_OFFSET_31) {
4382 ps_input_cntl = S_028644_OFFSET(offset);
4383 if (flat_shade || explicit)
4384 ps_input_cntl |= S_028644_FLAT_SHADE(1);
4385 if (explicit) {
4386 /* Force parameter cache to be read in passthrough
4387 * mode.
4388 */
4389 ps_input_cntl |= S_028644_OFFSET(1 << 5);
4390 }
4391 if (float16) {
4392 ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) |
4393 S_028644_ATTR0_VALID(1);
4394 }
4395 } else {
4396 /* The input is a DEFAULT_VAL constant. */
4397 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
4398 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
4399 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
4400 ps_input_cntl = S_028644_OFFSET(0x20) |
4401 S_028644_DEFAULT_VAL(offset);
4402 }
4403 return ps_input_cntl;
4404 }
4405
4406 static void
4407 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
4408 const struct radv_pipeline *pipeline)
4409 {
4410 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4411 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
4412 uint32_t ps_input_cntl[32];
4413
4414 unsigned ps_offset = 0;
4415
4416 if (ps->info.ps.prim_id_input) {
4417 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
4418 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4419 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4420 ++ps_offset;
4421 }
4422 }
4423
4424 if (ps->info.ps.layer_input ||
4425 ps->info.needs_multiview_view_index) {
4426 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
4427 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4428 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4429 else
4430 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false, false);
4431 ++ps_offset;
4432 }
4433
4434 if (ps->info.ps.viewport_index_input) {
4435 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VIEWPORT];
4436 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4437 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4438 else
4439 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false, false);
4440 ++ps_offset;
4441 }
4442
4443 if (ps->info.ps.has_pcoord) {
4444 unsigned val;
4445 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4446 ps_input_cntl[ps_offset] = val;
4447 ps_offset++;
4448 }
4449
4450 if (ps->info.ps.num_input_clips_culls) {
4451 unsigned vs_offset;
4452
4453 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
4454 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4455 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false, false);
4456 ++ps_offset;
4457 }
4458
4459 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
4460 if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
4461 ps->info.ps.num_input_clips_culls > 4) {
4462 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false, false);
4463 ++ps_offset;
4464 }
4465 }
4466
4467 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.ps.input_mask; ++i) {
4468 unsigned vs_offset;
4469 bool flat_shade;
4470 bool explicit;
4471 bool float16;
4472 if (!(ps->info.ps.input_mask & (1u << i)))
4473 continue;
4474
4475 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
4476 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
4477 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
4478 ++ps_offset;
4479 continue;
4480 }
4481
4482 flat_shade = !!(ps->info.ps.flat_shaded_mask & (1u << ps_offset));
4483 explicit = !!(ps->info.ps.explicit_shaded_mask & (1u << ps_offset));
4484 float16 = !!(ps->info.ps.float16_shaded_mask & (1u << ps_offset));
4485
4486 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade, explicit, float16);
4487 ++ps_offset;
4488 }
4489
4490 if (ps_offset) {
4491 radeon_set_context_reg_seq(ctx_cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
4492 for (unsigned i = 0; i < ps_offset; i++) {
4493 radeon_emit(ctx_cs, ps_input_cntl[i]);
4494 }
4495 }
4496 }
4497
4498 static uint32_t
4499 radv_compute_db_shader_control(const struct radv_device *device,
4500 const struct radv_pipeline *pipeline,
4501 const struct radv_shader_variant *ps)
4502 {
4503 unsigned conservative_z_export = V_02880C_EXPORT_ANY_Z;
4504 unsigned z_order;
4505 if (ps->info.ps.early_fragment_test || !ps->info.ps.writes_memory)
4506 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
4507 else
4508 z_order = V_02880C_LATE_Z;
4509
4510 if (ps->info.ps.depth_layout == FRAG_DEPTH_LAYOUT_GREATER)
4511 conservative_z_export = V_02880C_EXPORT_GREATER_THAN_Z;
4512 else if (ps->info.ps.depth_layout == FRAG_DEPTH_LAYOUT_LESS)
4513 conservative_z_export = V_02880C_EXPORT_LESS_THAN_Z;
4514
4515 bool disable_rbplus = device->physical_device->rad_info.has_rbplus &&
4516 !device->physical_device->rad_info.rbplus_allowed;
4517
4518 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4519 * but this appears to break Project Cars (DXVK). See
4520 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4521 */
4522 bool mask_export_enable = ps->info.ps.writes_sample_mask;
4523
4524 return S_02880C_Z_EXPORT_ENABLE(ps->info.ps.writes_z) |
4525 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.ps.writes_stencil) |
4526 S_02880C_KILL_ENABLE(!!ps->info.ps.can_discard) |
4527 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
4528 S_02880C_CONSERVATIVE_Z_EXPORT(conservative_z_export) |
4529 S_02880C_Z_ORDER(z_order) |
4530 S_02880C_DEPTH_BEFORE_SHADER(ps->info.ps.early_fragment_test) |
4531 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps->info.ps.post_depth_coverage) |
4532 S_02880C_EXEC_ON_HIER_FAIL(ps->info.ps.writes_memory) |
4533 S_02880C_EXEC_ON_NOOP(ps->info.ps.writes_memory) |
4534 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
4535 }
4536
4537 static void
4538 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs,
4539 struct radeon_cmdbuf *cs,
4540 struct radv_pipeline *pipeline)
4541 {
4542 struct radv_shader_variant *ps;
4543 uint64_t va;
4544 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
4545
4546 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4547 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
4548
4549 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
4550 radeon_emit(cs, va >> 8);
4551 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
4552 radeon_emit(cs, ps->config.rsrc1);
4553 radeon_emit(cs, ps->config.rsrc2);
4554
4555 radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL,
4556 radv_compute_db_shader_control(pipeline->device,
4557 pipeline, ps));
4558
4559 radeon_set_context_reg(ctx_cs, R_0286CC_SPI_PS_INPUT_ENA,
4560 ps->config.spi_ps_input_ena);
4561
4562 radeon_set_context_reg(ctx_cs, R_0286D0_SPI_PS_INPUT_ADDR,
4563 ps->config.spi_ps_input_addr);
4564
4565 radeon_set_context_reg(ctx_cs, R_0286D8_SPI_PS_IN_CONTROL,
4566 S_0286D8_NUM_INTERP(ps->info.ps.num_interp) |
4567 S_0286D8_PS_W32_EN(ps->info.wave_size == 32));
4568
4569 radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
4570
4571 radeon_set_context_reg(ctx_cs, R_028710_SPI_SHADER_Z_FORMAT,
4572 ac_get_spi_shader_z_format(ps->info.ps.writes_z,
4573 ps->info.ps.writes_stencil,
4574 ps->info.ps.writes_sample_mask));
4575
4576 if (pipeline->device->dfsm_allowed) {
4577 /* optimise this? */
4578 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4579 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
4580 }
4581 }
4582
4583 static void
4584 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs,
4585 const struct radv_pipeline *pipeline)
4586 {
4587 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4588 pipeline->device->physical_device->rad_info.chip_class >= GFX10)
4589 return;
4590
4591 unsigned vtx_reuse_depth = 30;
4592 if (radv_pipeline_has_tess(pipeline) &&
4593 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
4594 vtx_reuse_depth = 14;
4595 }
4596 radeon_set_context_reg(ctx_cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
4597 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
4598 }
4599
4600 static void
4601 radv_pipeline_generate_vgt_shader_config(struct radeon_cmdbuf *ctx_cs,
4602 const struct radv_pipeline *pipeline)
4603 {
4604 uint32_t stages = 0;
4605 if (radv_pipeline_has_tess(pipeline)) {
4606 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
4607 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4608
4609 if (radv_pipeline_has_gs(pipeline))
4610 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
4611 S_028B54_GS_EN(1);
4612 else if (radv_pipeline_has_ngg(pipeline))
4613 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
4614 else
4615 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
4616 } else if (radv_pipeline_has_gs(pipeline)) {
4617 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
4618 S_028B54_GS_EN(1);
4619 } else if (radv_pipeline_has_ngg(pipeline)) {
4620 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
4621 }
4622
4623 if (radv_pipeline_has_ngg(pipeline)) {
4624 stages |= S_028B54_PRIMGEN_EN(1);
4625 if (pipeline->streamout_shader)
4626 stages |= S_028B54_NGG_WAVE_ID_EN(1);
4627 if (radv_pipeline_has_ngg_passthrough(pipeline))
4628 stages |= S_028B54_PRIMGEN_PASSTHRU_EN(1);
4629 } else if (radv_pipeline_has_gs(pipeline)) {
4630 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
4631 }
4632
4633 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
4634 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4635
4636 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4637 uint8_t hs_size = 64, gs_size = 64, vs_size = 64;
4638
4639 if (radv_pipeline_has_tess(pipeline))
4640 hs_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.wave_size;
4641
4642 if (pipeline->shaders[MESA_SHADER_GEOMETRY]) {
4643 vs_size = gs_size = pipeline->shaders[MESA_SHADER_GEOMETRY]->info.wave_size;
4644 if (pipeline->gs_copy_shader)
4645 vs_size = pipeline->gs_copy_shader->info.wave_size;
4646 } else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
4647 vs_size = pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.wave_size;
4648 else if (pipeline->shaders[MESA_SHADER_VERTEX])
4649 vs_size = pipeline->shaders[MESA_SHADER_VERTEX]->info.wave_size;
4650
4651 if (radv_pipeline_has_ngg(pipeline))
4652 gs_size = vs_size;
4653
4654 /* legacy GS only supports Wave64 */
4655 stages |= S_028B54_HS_W32_EN(hs_size == 32 ? 1 : 0) |
4656 S_028B54_GS_W32_EN(gs_size == 32 ? 1 : 0) |
4657 S_028B54_VS_W32_EN(vs_size == 32 ? 1 : 0);
4658 }
4659
4660 radeon_set_context_reg(ctx_cs, R_028B54_VGT_SHADER_STAGES_EN, stages);
4661 }
4662
4663 static void
4664 radv_pipeline_generate_cliprect_rule(struct radeon_cmdbuf *ctx_cs,
4665 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4666 {
4667 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
4668 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
4669 uint32_t cliprect_rule = 0;
4670
4671 if (!discard_rectangle_info) {
4672 cliprect_rule = 0xffff;
4673 } else {
4674 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
4675 /* Interpret i as a bitmask, and then set the bit in
4676 * the mask if that combination of rectangles in which
4677 * the pixel is contained should pass the cliprect
4678 * test.
4679 */
4680 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
4681
4682 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
4683 !relevant_subset)
4684 continue;
4685
4686 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
4687 relevant_subset)
4688 continue;
4689
4690 cliprect_rule |= 1u << i;
4691 }
4692 }
4693
4694 radeon_set_context_reg(ctx_cs, R_02820C_PA_SC_CLIPRECT_RULE, cliprect_rule);
4695 }
4696
4697 static void
4698 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf *ctx_cs,
4699 struct radv_pipeline *pipeline)
4700 {
4701 bool break_wave_at_eoi = false;
4702 unsigned primgroup_size;
4703 unsigned vertgroup_size = 256; /* 256 = disable vertex grouping */
4704
4705 if (radv_pipeline_has_tess(pipeline)) {
4706 primgroup_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
4707 } else if (radv_pipeline_has_gs(pipeline)) {
4708 const struct gfx9_gs_info *gs_state =
4709 &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs_ring_info;
4710 unsigned vgt_gs_onchip_cntl = gs_state->vgt_gs_onchip_cntl;
4711 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
4712 } else {
4713 primgroup_size = 128; /* recommended without a GS and tess */
4714 }
4715
4716 if (radv_pipeline_has_tess(pipeline)) {
4717 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4718 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4719 break_wave_at_eoi = true;
4720 }
4721
4722 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL,
4723 S_03096C_PRIM_GRP_SIZE(primgroup_size) |
4724 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
4725 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4726 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi));
4727 }
4728
4729 static void
4730 radv_pipeline_generate_vgt_gs_out(struct radeon_cmdbuf *ctx_cs,
4731 const struct radv_pipeline *pipeline,
4732 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4733 const struct radv_graphics_pipeline_create_info *extra)
4734 {
4735 uint32_t gs_out;
4736
4737 if (radv_pipeline_has_gs(pipeline)) {
4738 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
4739 } else if (radv_pipeline_has_tess(pipeline)) {
4740 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode) {
4741 gs_out = V_028A6C_POINTLIST;
4742 } else {
4743 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.primitive_mode);
4744 }
4745 } else {
4746 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
4747 }
4748
4749 if (extra && extra->use_rectlist) {
4750 gs_out = V_028A6C_TRISTRIP;
4751 if (radv_pipeline_has_ngg(pipeline))
4752 gs_out = V_028A6C_RECTLIST;
4753 }
4754
4755 radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
4756 }
4757
4758 static void
4759 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
4760 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4761 const struct radv_graphics_pipeline_create_info *extra,
4762 const struct radv_blend_state *blend)
4763 {
4764 struct radeon_cmdbuf *ctx_cs = &pipeline->ctx_cs;
4765 struct radeon_cmdbuf *cs = &pipeline->cs;
4766
4767 cs->max_dw = 64;
4768 ctx_cs->max_dw = 256;
4769 cs->buf = malloc(4 * (cs->max_dw + ctx_cs->max_dw));
4770 ctx_cs->buf = cs->buf + cs->max_dw;
4771
4772 radv_pipeline_generate_depth_stencil_state(ctx_cs, pipeline, pCreateInfo, extra);
4773 radv_pipeline_generate_blend_state(ctx_cs, pipeline, blend);
4774 radv_pipeline_generate_raster_state(ctx_cs, pipeline, pCreateInfo);
4775 radv_pipeline_generate_multisample_state(ctx_cs, pipeline);
4776 radv_pipeline_generate_vgt_gs_mode(ctx_cs, pipeline);
4777 radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline);
4778
4779 if (radv_pipeline_has_tess(pipeline)) {
4780 radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline);
4781 radv_pipeline_generate_tess_state(ctx_cs, pipeline, pCreateInfo);
4782 }
4783
4784 radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline);
4785 radv_pipeline_generate_fragment_shader(ctx_cs, cs, pipeline);
4786 radv_pipeline_generate_ps_inputs(ctx_cs, pipeline);
4787 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline);
4788 radv_pipeline_generate_vgt_shader_config(ctx_cs, pipeline);
4789 radv_pipeline_generate_cliprect_rule(ctx_cs, pCreateInfo);
4790 radv_pipeline_generate_vgt_gs_out(ctx_cs, pipeline, pCreateInfo, extra);
4791
4792 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && !radv_pipeline_has_ngg(pipeline))
4793 gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline);
4794
4795 pipeline->ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4);
4796
4797 assert(ctx_cs->cdw <= ctx_cs->max_dw);
4798 assert(cs->cdw <= cs->max_dw);
4799 }
4800
4801 static void
4802 radv_pipeline_init_vertex_input_state(struct radv_pipeline *pipeline,
4803 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4804 {
4805 const VkPipelineVertexInputStateCreateInfo *vi_info =
4806 pCreateInfo->pVertexInputState;
4807
4808 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
4809 const VkVertexInputBindingDescription *desc =
4810 &vi_info->pVertexBindingDescriptions[i];
4811
4812 pipeline->binding_stride[desc->binding] = desc->stride;
4813 pipeline->num_vertex_bindings =
4814 MAX2(pipeline->num_vertex_bindings, desc->binding + 1);
4815 }
4816 }
4817
4818 static struct radv_shader_variant *
4819 radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline)
4820 {
4821 int i;
4822
4823 for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) {
4824 struct radv_shader_variant *shader =
4825 radv_get_shader(pipeline, i);
4826
4827 if (shader && shader->info.so.num_outputs > 0)
4828 return shader;
4829 }
4830
4831 return NULL;
4832 }
4833
4834 static void
4835 radv_pipeline_init_shader_stages_state(struct radv_pipeline *pipeline)
4836 {
4837 struct radv_device *device = pipeline->device;
4838
4839 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
4840 pipeline->user_data_0[i] =
4841 radv_pipeline_stage_to_user_data_0(pipeline, i,
4842 device->physical_device->rad_info.chip_class);
4843
4844 if (pipeline->shaders[i]) {
4845 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
4846 }
4847 }
4848
4849 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
4850 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
4851 if (loc->sgpr_idx != -1) {
4852 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
4853 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
4854 if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id)
4855 pipeline->graphics.vtx_emit_num = 3;
4856 else
4857 pipeline->graphics.vtx_emit_num = 2;
4858 }
4859 }
4860
4861 static VkResult
4862 radv_pipeline_init(struct radv_pipeline *pipeline,
4863 struct radv_device *device,
4864 struct radv_pipeline_cache *cache,
4865 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4866 const struct radv_graphics_pipeline_create_info *extra)
4867 {
4868 VkResult result;
4869
4870 pipeline->device = device;
4871 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
4872 assert(pipeline->layout);
4873
4874 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
4875
4876 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
4877 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
4878 radv_init_feedback(creation_feedback);
4879
4880 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
4881
4882 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
4883 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
4884 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
4885 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
4886 pStages[stage] = &pCreateInfo->pStages[i];
4887 if(creation_feedback)
4888 stage_feedbacks[stage] = &creation_feedback->pPipelineStageCreationFeedbacks[i];
4889 }
4890
4891 struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend);
4892
4893 result = radv_create_shaders(pipeline, device, cache, &key, pStages,
4894 pCreateInfo->flags, pipeline_feedback,
4895 stage_feedbacks);
4896 if (result != VK_SUCCESS)
4897 return result;
4898
4899 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
4900 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
4901 radv_pipeline_init_input_assembly_state(pipeline, pCreateInfo, extra);
4902 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo, extra);
4903 radv_pipeline_init_raster_state(pipeline, pCreateInfo);
4904 radv_pipeline_init_depth_stencil_state(pipeline, pCreateInfo);
4905
4906 /* Ensure that some export memory is always allocated, for two reasons:
4907 *
4908 * 1) Correctness: The hardware ignores the EXEC mask if no export
4909 * memory is allocated, so KILL and alpha test do not work correctly
4910 * without this.
4911 * 2) Performance: Every shader needs at least a NULL export, even when
4912 * it writes no color/depth output. The NULL export instruction
4913 * stalls without this setting.
4914 *
4915 * Don't add this to CB_SHADER_MASK.
4916 *
4917 * GFX10 supports pixel shaders without exports by setting both the
4918 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
4919 * instructions if any are present.
4920 */
4921 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4922 if ((pipeline->device->physical_device->rad_info.chip_class <= GFX9 ||
4923 ps->info.ps.can_discard) &&
4924 !blend.spi_shader_col_format) {
4925 if (!ps->info.ps.writes_z &&
4926 !ps->info.ps.writes_stencil &&
4927 !ps->info.ps.writes_sample_mask)
4928 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
4929 }
4930
4931 blend.cb_shader_mask = ps->info.ps.cb_shader_mask;
4932
4933 if (extra &&
4934 (extra->custom_blend_mode == V_028808_CB_ELIMINATE_FAST_CLEAR ||
4935 extra->custom_blend_mode == V_028808_CB_FMASK_DECOMPRESS ||
4936 extra->custom_blend_mode == V_028808_CB_DCC_DECOMPRESS ||
4937 extra->custom_blend_mode == V_028808_CB_RESOLVE)) {
4938 /* According to the CB spec states, CB_SHADER_MASK should be
4939 * set to enable writes to all four channels of MRT0.
4940 */
4941 blend.cb_shader_mask = 0xf;
4942 }
4943
4944 pipeline->graphics.col_format = blend.spi_shader_col_format;
4945 pipeline->graphics.cb_target_mask = blend.cb_target_mask;
4946
4947 if (radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
4948 struct radv_shader_variant *gs =
4949 pipeline->shaders[MESA_SHADER_GEOMETRY];
4950
4951 radv_pipeline_init_gs_ring_state(pipeline, &gs->info.gs_ring_info);
4952 }
4953
4954 if (radv_pipeline_has_tess(pipeline)) {
4955 pipeline->graphics.tess_patch_control_points =
4956 pCreateInfo->pTessellationState->patchControlPoints;
4957 }
4958
4959 radv_pipeline_init_vertex_input_state(pipeline, pCreateInfo);
4960 radv_pipeline_init_binning_state(pipeline, pCreateInfo, &blend);
4961 radv_pipeline_init_shader_stages_state(pipeline);
4962 radv_pipeline_init_scratch(device, pipeline);
4963
4964 /* Find the last vertex shader stage that eventually uses streamout. */
4965 pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline);
4966
4967 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend);
4968
4969 return result;
4970 }
4971
4972 VkResult
4973 radv_graphics_pipeline_create(
4974 VkDevice _device,
4975 VkPipelineCache _cache,
4976 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4977 const struct radv_graphics_pipeline_create_info *extra,
4978 const VkAllocationCallbacks *pAllocator,
4979 VkPipeline *pPipeline)
4980 {
4981 RADV_FROM_HANDLE(radv_device, device, _device);
4982 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
4983 struct radv_pipeline *pipeline;
4984 VkResult result;
4985
4986 pipeline = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8,
4987 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4988 if (pipeline == NULL)
4989 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4990
4991 vk_object_base_init(&device->vk, &pipeline->base,
4992 VK_OBJECT_TYPE_PIPELINE);
4993
4994 result = radv_pipeline_init(pipeline, device, cache,
4995 pCreateInfo, extra);
4996 if (result != VK_SUCCESS) {
4997 radv_pipeline_destroy(device, pipeline, pAllocator);
4998 return result;
4999 }
5000
5001 *pPipeline = radv_pipeline_to_handle(pipeline);
5002
5003 return VK_SUCCESS;
5004 }
5005
5006 VkResult radv_CreateGraphicsPipelines(
5007 VkDevice _device,
5008 VkPipelineCache pipelineCache,
5009 uint32_t count,
5010 const VkGraphicsPipelineCreateInfo* pCreateInfos,
5011 const VkAllocationCallbacks* pAllocator,
5012 VkPipeline* pPipelines)
5013 {
5014 VkResult result = VK_SUCCESS;
5015 unsigned i = 0;
5016
5017 for (; i < count; i++) {
5018 VkResult r;
5019 r = radv_graphics_pipeline_create(_device,
5020 pipelineCache,
5021 &pCreateInfos[i],
5022 NULL, pAllocator, &pPipelines[i]);
5023 if (r != VK_SUCCESS) {
5024 result = r;
5025 pPipelines[i] = VK_NULL_HANDLE;
5026
5027 if (pCreateInfos[i].flags & VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT)
5028 break;
5029 }
5030 }
5031
5032 for (; i < count; ++i)
5033 pPipelines[i] = VK_NULL_HANDLE;
5034
5035 return result;
5036 }
5037
5038 static void
5039 radv_pipeline_generate_hw_cs(struct radeon_cmdbuf *cs,
5040 const struct radv_pipeline *pipeline)
5041 {
5042 struct radv_shader_variant *shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5043 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
5044 struct radv_device *device = pipeline->device;
5045
5046 radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
5047 radeon_emit(cs, va >> 8);
5048 radeon_emit(cs, S_00B834_DATA(va >> 40));
5049
5050 radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
5051 radeon_emit(cs, shader->config.rsrc1);
5052 radeon_emit(cs, shader->config.rsrc2);
5053 if (device->physical_device->rad_info.chip_class >= GFX10) {
5054 radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, shader->config.rsrc3);
5055 }
5056 }
5057
5058 static void
5059 radv_pipeline_generate_compute_state(struct radeon_cmdbuf *cs,
5060 const struct radv_pipeline *pipeline)
5061 {
5062 struct radv_shader_variant *shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5063 struct radv_device *device = pipeline->device;
5064 unsigned threads_per_threadgroup;
5065 unsigned threadgroups_per_cu = 1;
5066 unsigned waves_per_threadgroup;
5067 unsigned max_waves_per_sh = 0;
5068
5069 /* Calculate best compute resource limits. */
5070 threads_per_threadgroup = shader->info.cs.block_size[0] *
5071 shader->info.cs.block_size[1] *
5072 shader->info.cs.block_size[2];
5073 waves_per_threadgroup = DIV_ROUND_UP(threads_per_threadgroup,
5074 shader->info.wave_size);
5075
5076 if (device->physical_device->rad_info.chip_class >= GFX10 &&
5077 waves_per_threadgroup == 1)
5078 threadgroups_per_cu = 2;
5079
5080 radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
5081 ac_get_compute_resource_limits(&device->physical_device->rad_info,
5082 waves_per_threadgroup,
5083 max_waves_per_sh,
5084 threadgroups_per_cu));
5085
5086 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5087 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(shader->info.cs.block_size[0]));
5088 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(shader->info.cs.block_size[1]));
5089 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(shader->info.cs.block_size[2]));
5090 }
5091
5092 static void
5093 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
5094 {
5095 struct radv_device *device = pipeline->device;
5096 struct radeon_cmdbuf *cs = &pipeline->cs;
5097
5098 cs->max_dw = device->physical_device->rad_info.chip_class >= GFX10 ? 19 : 16;
5099 cs->buf = malloc(cs->max_dw * 4);
5100
5101 radv_pipeline_generate_hw_cs(cs, pipeline);
5102 radv_pipeline_generate_compute_state(cs, pipeline);
5103
5104 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
5105 }
5106
5107 static struct radv_pipeline_key
5108 radv_generate_compute_pipeline_key(struct radv_pipeline *pipeline,
5109 const VkComputePipelineCreateInfo *pCreateInfo)
5110 {
5111 const VkPipelineShaderStageCreateInfo *stage = &pCreateInfo->stage;
5112 struct radv_pipeline_key key;
5113 memset(&key, 0, sizeof(key));
5114
5115 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
5116 key.optimisations_disabled = 1;
5117
5118 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT *subgroup_size =
5119 vk_find_struct_const(stage->pNext,
5120 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT);
5121
5122 if (subgroup_size) {
5123 assert(subgroup_size->requiredSubgroupSize == 32 ||
5124 subgroup_size->requiredSubgroupSize == 64);
5125 key.compute_subgroup_size = subgroup_size->requiredSubgroupSize;
5126 }
5127
5128 return key;
5129 }
5130
5131 static VkResult radv_compute_pipeline_create(
5132 VkDevice _device,
5133 VkPipelineCache _cache,
5134 const VkComputePipelineCreateInfo* pCreateInfo,
5135 const VkAllocationCallbacks* pAllocator,
5136 VkPipeline* pPipeline)
5137 {
5138 RADV_FROM_HANDLE(radv_device, device, _device);
5139 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
5140 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
5141 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
5142 struct radv_pipeline *pipeline;
5143 VkResult result;
5144
5145 pipeline = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8,
5146 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5147 if (pipeline == NULL)
5148 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5149
5150 vk_object_base_init(&device->vk, &pipeline->base,
5151 VK_OBJECT_TYPE_PIPELINE);
5152
5153 pipeline->device = device;
5154 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
5155 assert(pipeline->layout);
5156
5157 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
5158 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
5159 radv_init_feedback(creation_feedback);
5160
5161 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
5162 if (creation_feedback)
5163 stage_feedbacks[MESA_SHADER_COMPUTE] = &creation_feedback->pPipelineStageCreationFeedbacks[0];
5164
5165 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
5166
5167 struct radv_pipeline_key key =
5168 radv_generate_compute_pipeline_key(pipeline, pCreateInfo);
5169
5170 result = radv_create_shaders(pipeline, device, cache, &key, pStages,
5171 pCreateInfo->flags, pipeline_feedback,
5172 stage_feedbacks);
5173 if (result != VK_SUCCESS) {
5174 radv_pipeline_destroy(device, pipeline, pAllocator);
5175 return result;
5176 }
5177
5178 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
5179 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
5180 radv_pipeline_init_scratch(device, pipeline);
5181
5182 radv_compute_generate_pm4(pipeline);
5183
5184 *pPipeline = radv_pipeline_to_handle(pipeline);
5185
5186 return VK_SUCCESS;
5187 }
5188
5189 VkResult radv_CreateComputePipelines(
5190 VkDevice _device,
5191 VkPipelineCache pipelineCache,
5192 uint32_t count,
5193 const VkComputePipelineCreateInfo* pCreateInfos,
5194 const VkAllocationCallbacks* pAllocator,
5195 VkPipeline* pPipelines)
5196 {
5197 VkResult result = VK_SUCCESS;
5198
5199 unsigned i = 0;
5200 for (; i < count; i++) {
5201 VkResult r;
5202 r = radv_compute_pipeline_create(_device, pipelineCache,
5203 &pCreateInfos[i],
5204 pAllocator, &pPipelines[i]);
5205 if (r != VK_SUCCESS) {
5206 result = r;
5207 pPipelines[i] = VK_NULL_HANDLE;
5208
5209 if (pCreateInfos[i].flags & VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT)
5210 break;
5211 }
5212 }
5213
5214 for (; i < count; ++i)
5215 pPipelines[i] = VK_NULL_HANDLE;
5216
5217 return result;
5218 }
5219
5220
5221 static uint32_t radv_get_executable_count(const struct radv_pipeline *pipeline)
5222 {
5223 uint32_t ret = 0;
5224 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5225 if (!pipeline->shaders[i])
5226 continue;
5227
5228 if (i == MESA_SHADER_GEOMETRY &&
5229 !radv_pipeline_has_ngg(pipeline)) {
5230 ret += 2u;
5231 } else {
5232 ret += 1u;
5233 }
5234
5235 }
5236 return ret;
5237 }
5238
5239 static struct radv_shader_variant *
5240 radv_get_shader_from_executable_index(const struct radv_pipeline *pipeline, int index, gl_shader_stage *stage)
5241 {
5242 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5243 if (!pipeline->shaders[i])
5244 continue;
5245 if (!index) {
5246 *stage = i;
5247 return pipeline->shaders[i];
5248 }
5249
5250 --index;
5251
5252 if (i == MESA_SHADER_GEOMETRY &&
5253 !radv_pipeline_has_ngg(pipeline)) {
5254 if (!index) {
5255 *stage = i;
5256 return pipeline->gs_copy_shader;
5257 }
5258 --index;
5259 }
5260 }
5261
5262 *stage = -1;
5263 return NULL;
5264 }
5265
5266 /* Basically strlcpy (which does not exist on linux) specialized for
5267 * descriptions. */
5268 static void desc_copy(char *desc, const char *src) {
5269 int len = strlen(src);
5270 assert(len < VK_MAX_DESCRIPTION_SIZE);
5271 memcpy(desc, src, len);
5272 memset(desc + len, 0, VK_MAX_DESCRIPTION_SIZE - len);
5273 }
5274
5275 VkResult radv_GetPipelineExecutablePropertiesKHR(
5276 VkDevice _device,
5277 const VkPipelineInfoKHR* pPipelineInfo,
5278 uint32_t* pExecutableCount,
5279 VkPipelineExecutablePropertiesKHR* pProperties)
5280 {
5281 RADV_FROM_HANDLE(radv_pipeline, pipeline, pPipelineInfo->pipeline);
5282 const uint32_t total_count = radv_get_executable_count(pipeline);
5283
5284 if (!pProperties) {
5285 *pExecutableCount = total_count;
5286 return VK_SUCCESS;
5287 }
5288
5289 const uint32_t count = MIN2(total_count, *pExecutableCount);
5290 for (unsigned i = 0, executable_idx = 0;
5291 i < MESA_SHADER_STAGES && executable_idx < count; ++i) {
5292 if (!pipeline->shaders[i])
5293 continue;
5294 pProperties[executable_idx].stages = mesa_to_vk_shader_stage(i);
5295 const char *name = NULL;
5296 const char *description = NULL;
5297 switch(i) {
5298 case MESA_SHADER_VERTEX:
5299 name = "Vertex Shader";
5300 description = "Vulkan Vertex Shader";
5301 break;
5302 case MESA_SHADER_TESS_CTRL:
5303 if (!pipeline->shaders[MESA_SHADER_VERTEX]) {
5304 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5305 name = "Vertex + Tessellation Control Shaders";
5306 description = "Combined Vulkan Vertex and Tessellation Control Shaders";
5307 } else {
5308 name = "Tessellation Control Shader";
5309 description = "Vulkan Tessellation Control Shader";
5310 }
5311 break;
5312 case MESA_SHADER_TESS_EVAL:
5313 name = "Tessellation Evaluation Shader";
5314 description = "Vulkan Tessellation Evaluation Shader";
5315 break;
5316 case MESA_SHADER_GEOMETRY:
5317 if (radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
5318 pProperties[executable_idx].stages |= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT;
5319 name = "Tessellation Evaluation + Geometry Shaders";
5320 description = "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5321 } else if (!radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_VERTEX]) {
5322 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5323 name = "Vertex + Geometry Shader";
5324 description = "Combined Vulkan Vertex and Geometry Shaders";
5325 } else {
5326 name = "Geometry Shader";
5327 description = "Vulkan Geometry Shader";
5328 }
5329 break;
5330 case MESA_SHADER_FRAGMENT:
5331 name = "Fragment Shader";
5332 description = "Vulkan Fragment Shader";
5333 break;
5334 case MESA_SHADER_COMPUTE:
5335 name = "Compute Shader";
5336 description = "Vulkan Compute Shader";
5337 break;
5338 }
5339
5340 pProperties[executable_idx].subgroupSize = pipeline->shaders[i]->info.wave_size;
5341 desc_copy(pProperties[executable_idx].name, name);
5342 desc_copy(pProperties[executable_idx].description, description);
5343
5344 ++executable_idx;
5345 if (i == MESA_SHADER_GEOMETRY &&
5346 !radv_pipeline_has_ngg(pipeline)) {
5347 assert(pipeline->gs_copy_shader);
5348 if (executable_idx >= count)
5349 break;
5350
5351 pProperties[executable_idx].stages = VK_SHADER_STAGE_GEOMETRY_BIT;
5352 pProperties[executable_idx].subgroupSize = 64;
5353 desc_copy(pProperties[executable_idx].name, "GS Copy Shader");
5354 desc_copy(pProperties[executable_idx].description,
5355 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5356
5357 ++executable_idx;
5358 }
5359 }
5360
5361 VkResult result = *pExecutableCount < total_count ? VK_INCOMPLETE : VK_SUCCESS;
5362 *pExecutableCount = count;
5363 return result;
5364 }
5365
5366 VkResult radv_GetPipelineExecutableStatisticsKHR(
5367 VkDevice _device,
5368 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5369 uint32_t* pStatisticCount,
5370 VkPipelineExecutableStatisticKHR* pStatistics)
5371 {
5372 RADV_FROM_HANDLE(radv_device, device, _device);
5373 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5374 gl_shader_stage stage;
5375 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5376
5377 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
5378 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
5379 unsigned max_waves = radv_get_max_waves(device, shader, stage);
5380
5381 VkPipelineExecutableStatisticKHR *s = pStatistics;
5382 VkPipelineExecutableStatisticKHR *end = s + (pStatistics ? *pStatisticCount : 0);
5383 VkResult result = VK_SUCCESS;
5384
5385 if (s < end) {
5386 desc_copy(s->name, "SGPRs");
5387 desc_copy(s->description, "Number of SGPR registers allocated per subgroup");
5388 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5389 s->value.u64 = shader->config.num_sgprs;
5390 }
5391 ++s;
5392
5393 if (s < end) {
5394 desc_copy(s->name, "VGPRs");
5395 desc_copy(s->description, "Number of VGPR registers allocated per subgroup");
5396 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5397 s->value.u64 = shader->config.num_vgprs;
5398 }
5399 ++s;
5400
5401 if (s < end) {
5402 desc_copy(s->name, "Spilled SGPRs");
5403 desc_copy(s->description, "Number of SGPR registers spilled per subgroup");
5404 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5405 s->value.u64 = shader->config.spilled_sgprs;
5406 }
5407 ++s;
5408
5409 if (s < end) {
5410 desc_copy(s->name, "Spilled VGPRs");
5411 desc_copy(s->description, "Number of VGPR registers spilled per subgroup");
5412 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5413 s->value.u64 = shader->config.spilled_vgprs;
5414 }
5415 ++s;
5416
5417 if (s < end) {
5418 desc_copy(s->name, "PrivMem VGPRs");
5419 desc_copy(s->description, "Number of VGPRs stored in private memory per subgroup");
5420 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5421 s->value.u64 = shader->info.private_mem_vgprs;
5422 }
5423 ++s;
5424
5425 if (s < end) {
5426 desc_copy(s->name, "Code size");
5427 desc_copy(s->description, "Code size in bytes");
5428 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5429 s->value.u64 = shader->exec_size;
5430 }
5431 ++s;
5432
5433 if (s < end) {
5434 desc_copy(s->name, "LDS size");
5435 desc_copy(s->description, "LDS size in bytes per workgroup");
5436 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5437 s->value.u64 = shader->config.lds_size * lds_increment;
5438 }
5439 ++s;
5440
5441 if (s < end) {
5442 desc_copy(s->name, "Scratch size");
5443 desc_copy(s->description, "Private memory in bytes per subgroup");
5444 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5445 s->value.u64 = shader->config.scratch_bytes_per_wave;
5446 }
5447 ++s;
5448
5449 if (s < end) {
5450 desc_copy(s->name, "Subgroups per SIMD");
5451 desc_copy(s->description, "The maximum number of subgroups in flight on a SIMD unit");
5452 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5453 s->value.u64 = max_waves;
5454 }
5455 ++s;
5456
5457 if (shader->statistics) {
5458 for (unsigned i = 0; i < shader->statistics->count; i++) {
5459 struct radv_compiler_statistic_info *info = &shader->statistics->infos[i];
5460 uint32_t value = shader->statistics->values[i];
5461 if (s < end) {
5462 desc_copy(s->name, info->name);
5463 desc_copy(s->description, info->desc);
5464 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5465 s->value.u64 = value;
5466 }
5467 ++s;
5468 }
5469 }
5470
5471 if (!pStatistics)
5472 *pStatisticCount = s - pStatistics;
5473 else if (s > end) {
5474 *pStatisticCount = end - pStatistics;
5475 result = VK_INCOMPLETE;
5476 } else {
5477 *pStatisticCount = s - pStatistics;
5478 }
5479
5480 return result;
5481 }
5482
5483 static VkResult radv_copy_representation(void *data, size_t *data_size, const char *src)
5484 {
5485 size_t total_size = strlen(src) + 1;
5486
5487 if (!data) {
5488 *data_size = total_size;
5489 return VK_SUCCESS;
5490 }
5491
5492 size_t size = MIN2(total_size, *data_size);
5493
5494 memcpy(data, src, size);
5495 if (size)
5496 *((char*)data + size - 1) = 0;
5497 return size < total_size ? VK_INCOMPLETE : VK_SUCCESS;
5498 }
5499
5500 VkResult radv_GetPipelineExecutableInternalRepresentationsKHR(
5501 VkDevice device,
5502 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5503 uint32_t* pInternalRepresentationCount,
5504 VkPipelineExecutableInternalRepresentationKHR* pInternalRepresentations)
5505 {
5506 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5507 gl_shader_stage stage;
5508 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5509
5510 VkPipelineExecutableInternalRepresentationKHR *p = pInternalRepresentations;
5511 VkPipelineExecutableInternalRepresentationKHR *end = p + (pInternalRepresentations ? *pInternalRepresentationCount : 0);
5512 VkResult result = VK_SUCCESS;
5513 /* optimized NIR */
5514 if (p < end) {
5515 p->isText = true;
5516 desc_copy(p->name, "NIR Shader(s)");
5517 desc_copy(p->description, "The optimized NIR shader(s)");
5518 if (radv_copy_representation(p->pData, &p->dataSize, shader->nir_string) != VK_SUCCESS)
5519 result = VK_INCOMPLETE;
5520 }
5521 ++p;
5522
5523 /* backend IR */
5524 if (p < end) {
5525 p->isText = true;
5526 if (radv_use_llvm_for_stage(pipeline->device, stage)) {
5527 desc_copy(p->name, "LLVM IR");
5528 desc_copy(p->description, "The LLVM IR after some optimizations");
5529 } else {
5530 desc_copy(p->name, "ACO IR");
5531 desc_copy(p->description, "The ACO IR after some optimizations");
5532 }
5533 if (radv_copy_representation(p->pData, &p->dataSize, shader->ir_string) != VK_SUCCESS)
5534 result = VK_INCOMPLETE;
5535 }
5536 ++p;
5537
5538 /* Disassembler */
5539 if (p < end) {
5540 p->isText = true;
5541 desc_copy(p->name, "Assembly");
5542 desc_copy(p->description, "Final Assembly");
5543 if (radv_copy_representation(p->pData, &p->dataSize, shader->disasm_string) != VK_SUCCESS)
5544 result = VK_INCOMPLETE;
5545 }
5546 ++p;
5547
5548 if (!pInternalRepresentations)
5549 *pInternalRepresentationCount = p - pInternalRepresentations;
5550 else if(p > end) {
5551 result = VK_INCOMPLETE;
5552 *pInternalRepresentationCount = end - pInternalRepresentations;
5553 } else {
5554 *pInternalRepresentationCount = p - pInternalRepresentations;
5555 }
5556
5557 return result;
5558 }