2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
34 #include "radv_shader.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
48 #include "ac_shader_util.h"
50 struct radv_blend_state
{
51 uint32_t blend_enable_4bit
;
52 uint32_t need_src_alpha
;
54 uint32_t cb_color_control
;
55 uint32_t cb_target_mask
;
56 uint32_t cb_target_enabled_4bit
;
57 uint32_t sx_mrt_blend_opt
[8];
58 uint32_t cb_blend_control
[8];
60 uint32_t spi_shader_col_format
;
61 uint32_t col_format_is_int8
;
62 uint32_t col_format_is_int10
;
63 uint32_t cb_shader_mask
;
64 uint32_t db_alpha_to_mask
;
66 uint32_t commutative_4bit
;
68 bool single_cb_enable
;
69 bool mrt0_is_dual_src
;
72 struct radv_dsa_order_invariance
{
73 /* Whether the final result in Z/S buffers is guaranteed to be
74 * invariant under changes to the order in which fragments arrive.
78 /* Whether the set of fragments that pass the combined Z/S test is
79 * guaranteed to be invariant under changes to the order in which
85 struct radv_tessellation_state
{
86 uint32_t ls_hs_config
;
87 unsigned num_lds_blocks
;
91 static const VkPipelineMultisampleStateCreateInfo
*
92 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
94 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
95 return pCreateInfo
->pMultisampleState
;
99 static const VkPipelineTessellationStateCreateInfo
*
100 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
102 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
103 if (pCreateInfo
->pStages
[i
].stage
== VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
||
104 pCreateInfo
->pStages
[i
].stage
== VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
) {
105 return pCreateInfo
->pTessellationState
;
111 static const VkPipelineDepthStencilStateCreateInfo
*
112 radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
114 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
115 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
117 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
118 subpass
->depth_stencil_attachment
)
119 return pCreateInfo
->pDepthStencilState
;
123 static const VkPipelineColorBlendStateCreateInfo
*
124 radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
126 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
127 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
129 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
130 subpass
->has_color_att
)
131 return pCreateInfo
->pColorBlendState
;
135 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
)
137 struct radv_shader_variant
*variant
= NULL
;
138 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
139 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
140 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
141 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
142 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
143 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
146 return variant
->info
.is_ngg
;
149 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline
*pipeline
)
151 assert(radv_pipeline_has_ngg(pipeline
));
153 struct radv_shader_variant
*variant
= NULL
;
154 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
155 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
156 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
157 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
158 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
159 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
162 return variant
->info
.is_ngg_passthrough
;
165 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
)
167 if (!radv_pipeline_has_gs(pipeline
))
170 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
171 * On GFX10, it might be required in rare cases if it's not possible to
174 if (radv_pipeline_has_ngg(pipeline
))
177 assert(pipeline
->gs_copy_shader
);
182 radv_pipeline_destroy(struct radv_device
*device
,
183 struct radv_pipeline
*pipeline
,
184 const VkAllocationCallbacks
* allocator
)
186 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
187 if (pipeline
->shaders
[i
])
188 radv_shader_variant_destroy(device
, pipeline
->shaders
[i
]);
190 if (pipeline
->gs_copy_shader
)
191 radv_shader_variant_destroy(device
, pipeline
->gs_copy_shader
);
194 free(pipeline
->cs
.buf
);
196 vk_object_base_finish(&pipeline
->base
);
197 vk_free2(&device
->vk
.alloc
, allocator
, pipeline
);
200 void radv_DestroyPipeline(
202 VkPipeline _pipeline
,
203 const VkAllocationCallbacks
* pAllocator
)
205 RADV_FROM_HANDLE(radv_device
, device
, _device
);
206 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
211 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
214 static uint32_t get_hash_flags(struct radv_device
*device
)
216 uint32_t hash_flags
= 0;
218 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_NGG
)
219 hash_flags
|= RADV_HASH_SHADER_NO_NGG
;
220 if (device
->physical_device
->cs_wave_size
== 32)
221 hash_flags
|= RADV_HASH_SHADER_CS_WAVE32
;
222 if (device
->physical_device
->ps_wave_size
== 32)
223 hash_flags
|= RADV_HASH_SHADER_PS_WAVE32
;
224 if (device
->physical_device
->ge_wave_size
== 32)
225 hash_flags
|= RADV_HASH_SHADER_GE_WAVE32
;
226 if (device
->physical_device
->use_llvm
)
227 hash_flags
|= RADV_HASH_SHADER_LLVM
;
232 radv_pipeline_scratch_init(struct radv_device
*device
,
233 struct radv_pipeline
*pipeline
)
235 unsigned scratch_bytes_per_wave
= 0;
236 unsigned max_waves
= 0;
237 unsigned min_waves
= 1;
239 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
240 if (pipeline
->shaders
[i
] &&
241 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
) {
242 unsigned max_stage_waves
= device
->scratch_waves
;
244 scratch_bytes_per_wave
= MAX2(scratch_bytes_per_wave
,
245 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
);
247 max_stage_waves
= MIN2(max_stage_waves
,
248 4 * device
->physical_device
->rad_info
.num_good_compute_units
*
249 (256 / pipeline
->shaders
[i
]->config
.num_vgprs
));
250 max_waves
= MAX2(max_waves
, max_stage_waves
);
254 if (pipeline
->shaders
[MESA_SHADER_COMPUTE
]) {
255 unsigned group_size
= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[0] *
256 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[1] *
257 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[2];
258 min_waves
= MAX2(min_waves
, round_up_u32(group_size
, 64));
261 pipeline
->scratch_bytes_per_wave
= scratch_bytes_per_wave
;
262 pipeline
->max_waves
= max_waves
;
266 static uint32_t si_translate_blend_logic_op(VkLogicOp op
)
269 case VK_LOGIC_OP_CLEAR
:
270 return V_028808_ROP3_CLEAR
;
271 case VK_LOGIC_OP_AND
:
272 return V_028808_ROP3_AND
;
273 case VK_LOGIC_OP_AND_REVERSE
:
274 return V_028808_ROP3_AND_REVERSE
;
275 case VK_LOGIC_OP_COPY
:
276 return V_028808_ROP3_COPY
;
277 case VK_LOGIC_OP_AND_INVERTED
:
278 return V_028808_ROP3_AND_INVERTED
;
279 case VK_LOGIC_OP_NO_OP
:
280 return V_028808_ROP3_NO_OP
;
281 case VK_LOGIC_OP_XOR
:
282 return V_028808_ROP3_XOR
;
284 return V_028808_ROP3_OR
;
285 case VK_LOGIC_OP_NOR
:
286 return V_028808_ROP3_NOR
;
287 case VK_LOGIC_OP_EQUIVALENT
:
288 return V_028808_ROP3_EQUIVALENT
;
289 case VK_LOGIC_OP_INVERT
:
290 return V_028808_ROP3_INVERT
;
291 case VK_LOGIC_OP_OR_REVERSE
:
292 return V_028808_ROP3_OR_REVERSE
;
293 case VK_LOGIC_OP_COPY_INVERTED
:
294 return V_028808_ROP3_COPY_INVERTED
;
295 case VK_LOGIC_OP_OR_INVERTED
:
296 return V_028808_ROP3_OR_INVERTED
;
297 case VK_LOGIC_OP_NAND
:
298 return V_028808_ROP3_NAND
;
299 case VK_LOGIC_OP_SET
:
300 return V_028808_ROP3_SET
;
302 unreachable("Unhandled logic op");
307 static uint32_t si_translate_blend_function(VkBlendOp op
)
310 case VK_BLEND_OP_ADD
:
311 return V_028780_COMB_DST_PLUS_SRC
;
312 case VK_BLEND_OP_SUBTRACT
:
313 return V_028780_COMB_SRC_MINUS_DST
;
314 case VK_BLEND_OP_REVERSE_SUBTRACT
:
315 return V_028780_COMB_DST_MINUS_SRC
;
316 case VK_BLEND_OP_MIN
:
317 return V_028780_COMB_MIN_DST_SRC
;
318 case VK_BLEND_OP_MAX
:
319 return V_028780_COMB_MAX_DST_SRC
;
325 static uint32_t si_translate_blend_factor(VkBlendFactor factor
)
328 case VK_BLEND_FACTOR_ZERO
:
329 return V_028780_BLEND_ZERO
;
330 case VK_BLEND_FACTOR_ONE
:
331 return V_028780_BLEND_ONE
;
332 case VK_BLEND_FACTOR_SRC_COLOR
:
333 return V_028780_BLEND_SRC_COLOR
;
334 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
335 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
336 case VK_BLEND_FACTOR_DST_COLOR
:
337 return V_028780_BLEND_DST_COLOR
;
338 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
339 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
340 case VK_BLEND_FACTOR_SRC_ALPHA
:
341 return V_028780_BLEND_SRC_ALPHA
;
342 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
343 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
344 case VK_BLEND_FACTOR_DST_ALPHA
:
345 return V_028780_BLEND_DST_ALPHA
;
346 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
347 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
348 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
349 return V_028780_BLEND_CONSTANT_COLOR
;
350 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
351 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
352 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
353 return V_028780_BLEND_CONSTANT_ALPHA
;
354 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
355 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
356 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
357 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
358 case VK_BLEND_FACTOR_SRC1_COLOR
:
359 return V_028780_BLEND_SRC1_COLOR
;
360 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
361 return V_028780_BLEND_INV_SRC1_COLOR
;
362 case VK_BLEND_FACTOR_SRC1_ALPHA
:
363 return V_028780_BLEND_SRC1_ALPHA
;
364 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
365 return V_028780_BLEND_INV_SRC1_ALPHA
;
371 static uint32_t si_translate_blend_opt_function(VkBlendOp op
)
374 case VK_BLEND_OP_ADD
:
375 return V_028760_OPT_COMB_ADD
;
376 case VK_BLEND_OP_SUBTRACT
:
377 return V_028760_OPT_COMB_SUBTRACT
;
378 case VK_BLEND_OP_REVERSE_SUBTRACT
:
379 return V_028760_OPT_COMB_REVSUBTRACT
;
380 case VK_BLEND_OP_MIN
:
381 return V_028760_OPT_COMB_MIN
;
382 case VK_BLEND_OP_MAX
:
383 return V_028760_OPT_COMB_MAX
;
385 return V_028760_OPT_COMB_BLEND_DISABLED
;
389 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor
, bool is_alpha
)
392 case VK_BLEND_FACTOR_ZERO
:
393 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
394 case VK_BLEND_FACTOR_ONE
:
395 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
396 case VK_BLEND_FACTOR_SRC_COLOR
:
397 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
398 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
399 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
400 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
401 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
402 case VK_BLEND_FACTOR_SRC_ALPHA
:
403 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
404 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
405 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
406 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
407 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
408 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
410 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
415 * Get rid of DST in the blend factors by commuting the operands:
416 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
418 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
419 unsigned *dst_factor
, unsigned expected_dst
,
420 unsigned replacement_src
)
422 if (*src_factor
== expected_dst
&&
423 *dst_factor
== VK_BLEND_FACTOR_ZERO
) {
424 *src_factor
= VK_BLEND_FACTOR_ZERO
;
425 *dst_factor
= replacement_src
;
427 /* Commuting the operands requires reversing subtractions. */
428 if (*func
== VK_BLEND_OP_SUBTRACT
)
429 *func
= VK_BLEND_OP_REVERSE_SUBTRACT
;
430 else if (*func
== VK_BLEND_OP_REVERSE_SUBTRACT
)
431 *func
= VK_BLEND_OP_SUBTRACT
;
435 static bool si_blend_factor_uses_dst(unsigned factor
)
437 return factor
== VK_BLEND_FACTOR_DST_COLOR
||
438 factor
== VK_BLEND_FACTOR_DST_ALPHA
||
439 factor
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
440 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
||
441 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
;
444 static bool is_dual_src(VkBlendFactor factor
)
447 case VK_BLEND_FACTOR_SRC1_COLOR
:
448 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
449 case VK_BLEND_FACTOR_SRC1_ALPHA
:
450 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
457 static unsigned radv_choose_spi_color_format(VkFormat vk_format
,
459 bool blend_need_alpha
)
461 const struct vk_format_description
*desc
= vk_format_description(vk_format
);
462 struct ac_spi_color_formats formats
= {};
463 unsigned format
, ntype
, swap
;
465 format
= radv_translate_colorformat(vk_format
);
466 ntype
= radv_translate_color_numformat(vk_format
, desc
,
467 vk_format_get_first_non_void_channel(vk_format
));
468 swap
= radv_translate_colorswap(vk_format
, false);
470 ac_choose_spi_color_formats(format
, swap
, ntype
, false, &formats
);
472 if (blend_enable
&& blend_need_alpha
)
473 return formats
.blend_alpha
;
474 else if(blend_need_alpha
)
475 return formats
.alpha
;
476 else if(blend_enable
)
477 return formats
.blend
;
479 return formats
.normal
;
483 format_is_int8(VkFormat format
)
485 const struct vk_format_description
*desc
= vk_format_description(format
);
486 int channel
= vk_format_get_first_non_void_channel(format
);
488 return channel
>= 0 && desc
->channel
[channel
].pure_integer
&&
489 desc
->channel
[channel
].size
== 8;
493 format_is_int10(VkFormat format
)
495 const struct vk_format_description
*desc
= vk_format_description(format
);
497 if (desc
->nr_channels
!= 4)
499 for (unsigned i
= 0; i
< 4; i
++) {
500 if (desc
->channel
[i
].pure_integer
&& desc
->channel
[i
].size
== 10)
507 radv_pipeline_compute_spi_color_formats(struct radv_pipeline
*pipeline
,
508 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
509 struct radv_blend_state
*blend
)
511 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
512 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
513 unsigned col_format
= 0, is_int8
= 0, is_int10
= 0;
514 unsigned num_targets
;
516 for (unsigned i
= 0; i
< (blend
->single_cb_enable
? 1 : subpass
->color_count
); ++i
) {
519 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
||
520 !(blend
->cb_target_mask
& (0xfu
<< (i
* 4)))) {
521 cf
= V_028714_SPI_SHADER_ZERO
;
523 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
525 blend
->blend_enable_4bit
& (0xfu
<< (i
* 4));
527 cf
= radv_choose_spi_color_format(attachment
->format
,
529 blend
->need_src_alpha
& (1 << i
));
531 if (format_is_int8(attachment
->format
))
533 if (format_is_int10(attachment
->format
))
537 col_format
|= cf
<< (4 * i
);
540 if (!(col_format
& 0xf) && blend
->need_src_alpha
& (1 << 0)) {
541 /* When a subpass doesn't have any color attachments, write the
542 * alpha channel of MRT0 when alpha coverage is enabled because
543 * the depth attachment needs it.
545 col_format
|= V_028714_SPI_SHADER_32_AR
;
548 /* If the i-th target format is set, all previous target formats must
549 * be non-zero to avoid hangs.
551 num_targets
= (util_last_bit(col_format
) + 3) / 4;
552 for (unsigned i
= 0; i
< num_targets
; i
++) {
553 if (!(col_format
& (0xf << (i
* 4)))) {
554 col_format
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
558 /* The output for dual source blending should have the same format as
561 if (blend
->mrt0_is_dual_src
)
562 col_format
|= (col_format
& 0xf) << 4;
564 blend
->spi_shader_col_format
= col_format
;
565 blend
->col_format_is_int8
= is_int8
;
566 blend
->col_format_is_int10
= is_int10
;
570 * Ordered so that for each i,
571 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
573 const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
] = {
574 VK_FORMAT_R32_SFLOAT
,
575 VK_FORMAT_R32G32_SFLOAT
,
576 VK_FORMAT_R8G8B8A8_UNORM
,
577 VK_FORMAT_R16G16B16A16_UNORM
,
578 VK_FORMAT_R16G16B16A16_SNORM
,
579 VK_FORMAT_R16G16B16A16_UINT
,
580 VK_FORMAT_R16G16B16A16_SINT
,
581 VK_FORMAT_R32G32B32A32_SFLOAT
,
582 VK_FORMAT_R8G8B8A8_UINT
,
583 VK_FORMAT_R8G8B8A8_SINT
,
584 VK_FORMAT_A2R10G10B10_UINT_PACK32
,
585 VK_FORMAT_A2R10G10B10_SINT_PACK32
,
588 unsigned radv_format_meta_fs_key(VkFormat format
)
590 unsigned col_format
= radv_choose_spi_color_format(format
, false, false);
592 assert(col_format
!= V_028714_SPI_SHADER_32_AR
);
593 if (col_format
>= V_028714_SPI_SHADER_32_AR
)
594 --col_format
; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
596 --col_format
; /* Skip V_028714_SPI_SHADER_ZERO */
597 bool is_int8
= format_is_int8(format
);
598 bool is_int10
= format_is_int10(format
);
600 return col_format
+ (is_int8
? 3 : is_int10
? 5 : 0);
604 radv_blend_check_commutativity(struct radv_blend_state
*blend
,
605 VkBlendOp op
, VkBlendFactor src
,
606 VkBlendFactor dst
, unsigned chanmask
)
608 /* Src factor is allowed when it does not depend on Dst. */
609 static const uint32_t src_allowed
=
610 (1u << VK_BLEND_FACTOR_ONE
) |
611 (1u << VK_BLEND_FACTOR_SRC_COLOR
) |
612 (1u << VK_BLEND_FACTOR_SRC_ALPHA
) |
613 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
) |
614 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR
) |
615 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA
) |
616 (1u << VK_BLEND_FACTOR_SRC1_COLOR
) |
617 (1u << VK_BLEND_FACTOR_SRC1_ALPHA
) |
618 (1u << VK_BLEND_FACTOR_ZERO
) |
619 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
) |
620 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
) |
621 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
) |
622 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
) |
623 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
) |
624 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
);
626 if (dst
== VK_BLEND_FACTOR_ONE
&&
627 (src_allowed
& (1u << src
))) {
628 /* Addition is commutative, but floating point addition isn't
629 * associative: subtle changes can be introduced via different
630 * rounding. Be conservative, only enable for min and max.
632 if (op
== VK_BLEND_OP_MAX
|| op
== VK_BLEND_OP_MIN
)
633 blend
->commutative_4bit
|= chanmask
;
637 static struct radv_blend_state
638 radv_pipeline_init_blend_state(struct radv_pipeline
*pipeline
,
639 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
640 const struct radv_graphics_pipeline_create_info
*extra
)
642 const VkPipelineColorBlendStateCreateInfo
*vkblend
= radv_pipeline_get_color_blend_state(pCreateInfo
);
643 const VkPipelineMultisampleStateCreateInfo
*vkms
= radv_pipeline_get_multisample_state(pCreateInfo
);
644 struct radv_blend_state blend
= {0};
645 unsigned mode
= V_028808_CB_NORMAL
;
648 if (extra
&& extra
->custom_blend_mode
) {
649 blend
.single_cb_enable
= true;
650 mode
= extra
->custom_blend_mode
;
653 blend
.cb_color_control
= 0;
655 if (vkblend
->logicOpEnable
)
656 blend
.cb_color_control
|= S_028808_ROP3(si_translate_blend_logic_op(vkblend
->logicOp
));
658 blend
.cb_color_control
|= S_028808_ROP3(V_028808_ROP3_COPY
);
661 blend
.db_alpha_to_mask
= S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
662 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
663 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
664 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
665 S_028B70_OFFSET_ROUND(1);
667 if (vkms
&& vkms
->alphaToCoverageEnable
) {
668 blend
.db_alpha_to_mask
|= S_028B70_ALPHA_TO_MASK_ENABLE(1);
669 blend
.need_src_alpha
|= 0x1;
672 blend
.cb_target_mask
= 0;
674 for (i
= 0; i
< vkblend
->attachmentCount
; i
++) {
675 const VkPipelineColorBlendAttachmentState
*att
= &vkblend
->pAttachments
[i
];
676 unsigned blend_cntl
= 0;
677 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
678 VkBlendOp eqRGB
= att
->colorBlendOp
;
679 VkBlendFactor srcRGB
= att
->srcColorBlendFactor
;
680 VkBlendFactor dstRGB
= att
->dstColorBlendFactor
;
681 VkBlendOp eqA
= att
->alphaBlendOp
;
682 VkBlendFactor srcA
= att
->srcAlphaBlendFactor
;
683 VkBlendFactor dstA
= att
->dstAlphaBlendFactor
;
685 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
687 if (!att
->colorWriteMask
)
690 blend
.cb_target_mask
|= (unsigned)att
->colorWriteMask
<< (4 * i
);
691 blend
.cb_target_enabled_4bit
|= 0xf << (4 * i
);
692 if (!att
->blendEnable
) {
693 blend
.cb_blend_control
[i
] = blend_cntl
;
697 if (is_dual_src(srcRGB
) || is_dual_src(dstRGB
) || is_dual_src(srcA
) || is_dual_src(dstA
))
699 blend
.mrt0_is_dual_src
= true;
701 if (eqRGB
== VK_BLEND_OP_MIN
|| eqRGB
== VK_BLEND_OP_MAX
) {
702 srcRGB
= VK_BLEND_FACTOR_ONE
;
703 dstRGB
= VK_BLEND_FACTOR_ONE
;
705 if (eqA
== VK_BLEND_OP_MIN
|| eqA
== VK_BLEND_OP_MAX
) {
706 srcA
= VK_BLEND_FACTOR_ONE
;
707 dstA
= VK_BLEND_FACTOR_ONE
;
710 radv_blend_check_commutativity(&blend
, eqRGB
, srcRGB
, dstRGB
,
712 radv_blend_check_commutativity(&blend
, eqA
, srcA
, dstA
,
715 /* Blending optimizations for RB+.
716 * These transformations don't change the behavior.
718 * First, get rid of DST in the blend factors:
719 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
721 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
722 VK_BLEND_FACTOR_DST_COLOR
,
723 VK_BLEND_FACTOR_SRC_COLOR
);
725 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
726 VK_BLEND_FACTOR_DST_COLOR
,
727 VK_BLEND_FACTOR_SRC_COLOR
);
729 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
730 VK_BLEND_FACTOR_DST_ALPHA
,
731 VK_BLEND_FACTOR_SRC_ALPHA
);
733 /* Look up the ideal settings from tables. */
734 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
735 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
736 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
737 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
739 /* Handle interdependencies. */
740 if (si_blend_factor_uses_dst(srcRGB
))
741 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
742 if (si_blend_factor_uses_dst(srcA
))
743 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
745 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
&&
746 (dstRGB
== VK_BLEND_FACTOR_ZERO
||
747 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
748 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
))
749 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
751 /* Set the final value. */
752 blend
.sx_mrt_blend_opt
[i
] =
753 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
754 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
755 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
756 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
757 S_028760_ALPHA_DST_OPT(dstA_opt
) |
758 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
759 blend_cntl
|= S_028780_ENABLE(1);
761 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
762 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
763 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
764 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
765 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
766 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
767 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
768 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
770 blend
.cb_blend_control
[i
] = blend_cntl
;
772 blend
.blend_enable_4bit
|= 0xfu
<< (i
* 4);
774 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
775 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
776 srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
777 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
778 srcRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
||
779 dstRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
)
780 blend
.need_src_alpha
|= 1 << i
;
782 for (i
= vkblend
->attachmentCount
; i
< 8; i
++) {
783 blend
.cb_blend_control
[i
] = 0;
784 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
788 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
789 /* Disable RB+ blend optimizations for dual source blending. */
790 if (blend
.mrt0_is_dual_src
) {
791 for (i
= 0; i
< 8; i
++) {
792 blend
.sx_mrt_blend_opt
[i
] =
793 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
794 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
798 /* RB+ doesn't work with dual source blending, logic op and
801 if (blend
.mrt0_is_dual_src
||
802 (vkblend
&& vkblend
->logicOpEnable
) ||
803 mode
== V_028808_CB_RESOLVE
)
804 blend
.cb_color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
807 if (blend
.cb_target_mask
)
808 blend
.cb_color_control
|= S_028808_MODE(mode
);
810 blend
.cb_color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
812 radv_pipeline_compute_spi_color_formats(pipeline
, pCreateInfo
, &blend
);
816 static uint32_t si_translate_fill(VkPolygonMode func
)
819 case VK_POLYGON_MODE_FILL
:
820 return V_028814_X_DRAW_TRIANGLES
;
821 case VK_POLYGON_MODE_LINE
:
822 return V_028814_X_DRAW_LINES
;
823 case VK_POLYGON_MODE_POINT
:
824 return V_028814_X_DRAW_POINTS
;
827 return V_028814_X_DRAW_POINTS
;
831 static uint8_t radv_pipeline_get_ps_iter_samples(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
833 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
834 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
835 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
836 uint32_t ps_iter_samples
= 1;
837 uint32_t num_samples
;
839 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
841 * "If the VK_AMD_mixed_attachment_samples extension is enabled and the
842 * subpass uses color attachments, totalSamples is the number of
843 * samples of the color attachments. Otherwise, totalSamples is the
844 * value of VkPipelineMultisampleStateCreateInfo::rasterizationSamples
845 * specified at pipeline creation time."
847 if (subpass
->has_color_att
) {
848 num_samples
= subpass
->color_sample_count
;
850 num_samples
= vkms
->rasterizationSamples
;
853 if (vkms
->sampleShadingEnable
) {
854 ps_iter_samples
= ceilf(vkms
->minSampleShading
* num_samples
);
855 ps_iter_samples
= util_next_power_of_two(ps_iter_samples
);
857 return ps_iter_samples
;
861 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
863 return pCreateInfo
->depthTestEnable
&&
864 pCreateInfo
->depthWriteEnable
&&
865 pCreateInfo
->depthCompareOp
!= VK_COMPARE_OP_NEVER
;
869 radv_writes_stencil(const VkStencilOpState
*state
)
871 return state
->writeMask
&&
872 (state
->failOp
!= VK_STENCIL_OP_KEEP
||
873 state
->passOp
!= VK_STENCIL_OP_KEEP
||
874 state
->depthFailOp
!= VK_STENCIL_OP_KEEP
);
878 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
880 return pCreateInfo
->stencilTestEnable
&&
881 (radv_writes_stencil(&pCreateInfo
->front
) ||
882 radv_writes_stencil(&pCreateInfo
->back
));
886 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
888 return radv_is_depth_write_enabled(pCreateInfo
) ||
889 radv_is_stencil_write_enabled(pCreateInfo
);
893 radv_order_invariant_stencil_op(VkStencilOp op
)
895 /* REPLACE is normally order invariant, except when the stencil
896 * reference value is written by the fragment shader. Tracking this
897 * interaction does not seem worth the effort, so be conservative.
899 return op
!= VK_STENCIL_OP_INCREMENT_AND_CLAMP
&&
900 op
!= VK_STENCIL_OP_DECREMENT_AND_CLAMP
&&
901 op
!= VK_STENCIL_OP_REPLACE
;
905 radv_order_invariant_stencil_state(const VkStencilOpState
*state
)
907 /* Compute whether, assuming Z writes are disabled, this stencil state
908 * is order invariant in the sense that the set of passing fragments as
909 * well as the final stencil buffer result does not depend on the order
912 return !state
->writeMask
||
913 /* The following assumes that Z writes are disabled. */
914 (state
->compareOp
== VK_COMPARE_OP_ALWAYS
&&
915 radv_order_invariant_stencil_op(state
->passOp
) &&
916 radv_order_invariant_stencil_op(state
->depthFailOp
)) ||
917 (state
->compareOp
== VK_COMPARE_OP_NEVER
&&
918 radv_order_invariant_stencil_op(state
->failOp
));
922 radv_pipeline_has_dynamic_ds_states(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
924 VkDynamicState ds_states
[] = {
925 VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT
,
926 VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT
,
927 VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT
,
928 VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT
,
929 VK_DYNAMIC_STATE_STENCIL_OP_EXT
,
932 if (pCreateInfo
->pDynamicState
) {
933 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
934 for (uint32_t i
= 0; i
< count
; i
++) {
935 for (uint32_t j
= 0; j
< ARRAY_SIZE(ds_states
); j
++) {
936 if (pCreateInfo
->pDynamicState
->pDynamicStates
[i
] == ds_states
[j
])
946 radv_pipeline_out_of_order_rast(struct radv_pipeline
*pipeline
,
947 struct radv_blend_state
*blend
,
948 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
950 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
951 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
952 const VkPipelineDepthStencilStateCreateInfo
*vkds
= radv_pipeline_get_depth_stencil_state(pCreateInfo
);
953 const VkPipelineColorBlendStateCreateInfo
*vkblend
= radv_pipeline_get_color_blend_state(pCreateInfo
);
954 unsigned colormask
= blend
->cb_target_enabled_4bit
;
956 if (!pipeline
->device
->physical_device
->out_of_order_rast_allowed
)
959 /* Be conservative if a logic operation is enabled with color buffers. */
960 if (colormask
&& vkblend
&& vkblend
->logicOpEnable
)
963 /* Be conservative if an extended dynamic depth/stencil state is
964 * enabled because the driver can't update out-of-order rasterization
967 if (radv_pipeline_has_dynamic_ds_states(pCreateInfo
))
970 /* Default depth/stencil invariance when no attachment is bound. */
971 struct radv_dsa_order_invariance dsa_order_invariant
= {
972 .zs
= true, .pass_set
= true
976 struct radv_render_pass_attachment
*attachment
=
977 pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
978 bool has_stencil
= vk_format_is_stencil(attachment
->format
);
979 struct radv_dsa_order_invariance order_invariance
[2];
980 struct radv_shader_variant
*ps
=
981 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
983 /* Compute depth/stencil order invariance in order to know if
984 * it's safe to enable out-of-order.
986 bool zfunc_is_ordered
=
987 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
||
988 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS
||
989 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS_OR_EQUAL
||
990 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER
||
991 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER_OR_EQUAL
;
993 bool nozwrite_and_order_invariant_stencil
=
994 !radv_is_ds_write_enabled(vkds
) ||
995 (!radv_is_depth_write_enabled(vkds
) &&
996 radv_order_invariant_stencil_state(&vkds
->front
) &&
997 radv_order_invariant_stencil_state(&vkds
->back
));
999 order_invariance
[1].zs
=
1000 nozwrite_and_order_invariant_stencil
||
1001 (!radv_is_stencil_write_enabled(vkds
) &&
1003 order_invariance
[0].zs
=
1004 !radv_is_depth_write_enabled(vkds
) || zfunc_is_ordered
;
1006 order_invariance
[1].pass_set
=
1007 nozwrite_and_order_invariant_stencil
||
1008 (!radv_is_stencil_write_enabled(vkds
) &&
1009 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1010 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
));
1011 order_invariance
[0].pass_set
=
1012 !radv_is_depth_write_enabled(vkds
) ||
1013 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1014 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
);
1016 dsa_order_invariant
= order_invariance
[has_stencil
];
1017 if (!dsa_order_invariant
.zs
)
1020 /* The set of PS invocations is always order invariant,
1021 * except when early Z/S tests are requested.
1024 ps
->info
.ps
.writes_memory
&&
1025 ps
->info
.ps
.early_fragment_test
&&
1026 !dsa_order_invariant
.pass_set
)
1029 /* Determine if out-of-order rasterization should be disabled
1030 * when occlusion queries are used.
1032 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
=
1033 !dsa_order_invariant
.pass_set
;
1036 /* No color buffers are enabled for writing. */
1040 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
1043 /* Only commutative blending. */
1044 if (blendmask
& ~blend
->commutative_4bit
)
1047 if (!dsa_order_invariant
.pass_set
)
1051 if (colormask
& ~blendmask
)
1058 radv_pipeline_init_multisample_state(struct radv_pipeline
*pipeline
,
1059 struct radv_blend_state
*blend
,
1060 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1062 const VkPipelineMultisampleStateCreateInfo
*vkms
= radv_pipeline_get_multisample_state(pCreateInfo
);
1063 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
1064 unsigned num_tile_pipes
= pipeline
->device
->physical_device
->rad_info
.num_tile_pipes
;
1065 bool out_of_order_rast
= false;
1066 int ps_iter_samples
= 1;
1067 uint32_t mask
= 0xffff;
1070 ms
->num_samples
= vkms
->rasterizationSamples
;
1072 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1074 * "Sample shading is enabled for a graphics pipeline:
1076 * - If the interface of the fragment shader entry point of the
1077 * graphics pipeline includes an input variable decorated
1078 * with SampleId or SamplePosition. In this case
1079 * minSampleShadingFactor takes the value 1.0.
1080 * - Else if the sampleShadingEnable member of the
1081 * VkPipelineMultisampleStateCreateInfo structure specified
1082 * when creating the graphics pipeline is set to VK_TRUE. In
1083 * this case minSampleShadingFactor takes the value of
1084 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1086 * Otherwise, sample shading is considered disabled."
1088 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.force_persample
) {
1089 ps_iter_samples
= ms
->num_samples
;
1091 ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
);
1094 ms
->num_samples
= 1;
1097 const struct VkPipelineRasterizationStateRasterizationOrderAMD
*raster_order
=
1098 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD
);
1099 if (raster_order
&& raster_order
->rasterizationOrder
== VK_RASTERIZATION_ORDER_RELAXED_AMD
) {
1100 /* Out-of-order rasterization is explicitly enabled by the
1103 out_of_order_rast
= true;
1105 /* Determine if the driver can enable out-of-order
1106 * rasterization internally.
1109 radv_pipeline_out_of_order_rast(pipeline
, blend
, pCreateInfo
);
1112 ms
->pa_sc_aa_config
= 0;
1113 ms
->db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1114 S_028804_INCOHERENT_EQAA_READS(1) |
1115 S_028804_INTERPOLATE_COMP_Z(1) |
1116 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1117 ms
->pa_sc_mode_cntl_1
=
1118 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1119 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
1120 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
1121 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1123 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1124 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1125 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1126 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1127 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1128 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1129 ms
->pa_sc_mode_cntl_0
= S_028A48_ALTERNATE_RBS_PER_TILE(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
1130 S_028A48_VPORT_SCISSOR_ENABLE(1);
1132 const VkPipelineRasterizationLineStateCreateInfoEXT
*rast_line
=
1133 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1134 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1136 ms
->pa_sc_mode_cntl_0
|= S_028A48_LINE_STIPPLE_ENABLE(rast_line
->stippledLineEnable
);
1137 if (rast_line
->lineRasterizationMode
== VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT
) {
1138 /* From the Vulkan spec 1.1.129:
1140 * "When VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT lines
1141 * are being rasterized, sample locations may all be
1142 * treated as being at the pixel center (this may
1143 * affect attribute and depth interpolation)."
1145 ms
->num_samples
= 1;
1149 if (ms
->num_samples
> 1) {
1150 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1151 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1152 uint32_t z_samples
= subpass
->depth_stencil_attachment
? subpass
->depth_sample_count
: ms
->num_samples
;
1153 unsigned log_samples
= util_logbase2(ms
->num_samples
);
1154 unsigned log_z_samples
= util_logbase2(z_samples
);
1155 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
1156 ms
->pa_sc_mode_cntl_0
|= S_028A48_MSAA_ENABLE(1);
1157 ms
->db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples
) |
1158 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
1159 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
1160 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
1161 ms
->pa_sc_aa_config
|= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
1162 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples
)) |
1163 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
) | /* CM_R_028BE0_PA_SC_AA_CONFIG */
1164 S_028BE0_COVERED_CENTROID_IS_CENTER_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
);
1165 ms
->pa_sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
1166 if (ps_iter_samples
> 1)
1167 pipeline
->graphics
.spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1170 if (vkms
&& vkms
->pSampleMask
) {
1171 mask
= vkms
->pSampleMask
[0] & 0xffff;
1174 ms
->pa_sc_aa_mask
[0] = mask
| (mask
<< 16);
1175 ms
->pa_sc_aa_mask
[1] = mask
| (mask
<< 16);
1179 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology
)
1182 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1183 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1184 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1185 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1186 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1188 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1189 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1190 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1191 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1192 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1193 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1196 unreachable("unhandled primitive type");
1201 si_conv_gl_prim_to_gs_out(unsigned gl_prim
)
1204 case 0: /* GL_POINTS */
1205 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1206 case 1: /* GL_LINES */
1207 case 3: /* GL_LINE_STRIP */
1208 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1209 case 0x8E7A: /* GL_ISOLINES */
1210 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1212 case 4: /* GL_TRIANGLES */
1213 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1214 case 5: /* GL_TRIANGLE_STRIP */
1215 case 7: /* GL_QUADS */
1216 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1224 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology
)
1227 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1228 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1229 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1230 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1231 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1232 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1233 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1234 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1235 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1236 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1237 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1238 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1239 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1240 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1247 static unsigned radv_dynamic_state_mask(VkDynamicState state
)
1250 case VK_DYNAMIC_STATE_VIEWPORT
:
1251 case VK_DYNAMIC_STATE_VIEWPORT_WITH_COUNT_EXT
:
1252 return RADV_DYNAMIC_VIEWPORT
;
1253 case VK_DYNAMIC_STATE_SCISSOR
:
1254 case VK_DYNAMIC_STATE_SCISSOR_WITH_COUNT_EXT
:
1255 return RADV_DYNAMIC_SCISSOR
;
1256 case VK_DYNAMIC_STATE_LINE_WIDTH
:
1257 return RADV_DYNAMIC_LINE_WIDTH
;
1258 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
1259 return RADV_DYNAMIC_DEPTH_BIAS
;
1260 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
1261 return RADV_DYNAMIC_BLEND_CONSTANTS
;
1262 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
1263 return RADV_DYNAMIC_DEPTH_BOUNDS
;
1264 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
1265 return RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
1266 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
1267 return RADV_DYNAMIC_STENCIL_WRITE_MASK
;
1268 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
1269 return RADV_DYNAMIC_STENCIL_REFERENCE
;
1270 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT
:
1271 return RADV_DYNAMIC_DISCARD_RECTANGLE
;
1272 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT
:
1273 return RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1274 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
1275 return RADV_DYNAMIC_LINE_STIPPLE
;
1276 case VK_DYNAMIC_STATE_CULL_MODE_EXT
:
1277 return RADV_DYNAMIC_CULL_MODE
;
1278 case VK_DYNAMIC_STATE_FRONT_FACE_EXT
:
1279 return RADV_DYNAMIC_FRONT_FACE
;
1280 case VK_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY_EXT
:
1281 return RADV_DYNAMIC_PRIMITIVE_TOPOLOGY
;
1282 case VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT
:
1283 return RADV_DYNAMIC_DEPTH_TEST_ENABLE
;
1284 case VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT
:
1285 return RADV_DYNAMIC_DEPTH_WRITE_ENABLE
;
1286 case VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT
:
1287 return RADV_DYNAMIC_DEPTH_COMPARE_OP
;
1288 case VK_DYNAMIC_STATE_DEPTH_BOUNDS_TEST_ENABLE_EXT
:
1289 return RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE
;
1290 case VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT
:
1291 return RADV_DYNAMIC_STENCIL_TEST_ENABLE
;
1292 case VK_DYNAMIC_STATE_STENCIL_OP_EXT
:
1293 return RADV_DYNAMIC_STENCIL_OP
;
1294 case VK_DYNAMIC_STATE_VERTEX_INPUT_BINDING_STRIDE_EXT
:
1295 return RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE
;
1297 unreachable("Unhandled dynamic state");
1301 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1303 uint32_t states
= RADV_DYNAMIC_ALL
;
1305 /* If rasterization is disabled we do not care about any of the
1306 * dynamic states, since they are all rasterization related only,
1307 * except primitive topology and vertex binding stride.
1309 if (pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
1310 return RADV_DYNAMIC_PRIMITIVE_TOPOLOGY
|
1311 RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE
;
1313 if (!pCreateInfo
->pRasterizationState
->depthBiasEnable
)
1314 states
&= ~RADV_DYNAMIC_DEPTH_BIAS
;
1316 if (!pCreateInfo
->pDepthStencilState
||
1317 !pCreateInfo
->pDepthStencilState
->depthBoundsTestEnable
)
1318 states
&= ~RADV_DYNAMIC_DEPTH_BOUNDS
;
1320 if (!pCreateInfo
->pDepthStencilState
||
1321 !pCreateInfo
->pDepthStencilState
->stencilTestEnable
)
1322 states
&= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK
|
1323 RADV_DYNAMIC_STENCIL_WRITE_MASK
|
1324 RADV_DYNAMIC_STENCIL_REFERENCE
);
1326 if (!vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
))
1327 states
&= ~RADV_DYNAMIC_DISCARD_RECTANGLE
;
1329 if (!pCreateInfo
->pMultisampleState
||
1330 !vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1331 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
))
1332 states
&= ~RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1334 if (!pCreateInfo
->pRasterizationState
||
1335 !vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1336 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
))
1337 states
&= ~RADV_DYNAMIC_LINE_STIPPLE
;
1339 /* TODO: blend constants & line width. */
1346 radv_pipeline_init_dynamic_state(struct radv_pipeline
*pipeline
,
1347 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1348 const struct radv_graphics_pipeline_create_info
*extra
)
1350 uint32_t needed_states
= radv_pipeline_needed_dynamic_state(pCreateInfo
);
1351 uint32_t states
= needed_states
;
1352 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1353 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1355 pipeline
->dynamic_state
= default_dynamic_state
;
1356 pipeline
->graphics
.needed_dynamic_state
= needed_states
;
1358 if (pCreateInfo
->pDynamicState
) {
1359 /* Remove all of the states that are marked as dynamic */
1360 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1361 for (uint32_t s
= 0; s
< count
; s
++)
1362 states
&= ~radv_dynamic_state_mask(pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1365 struct radv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1367 if (needed_states
& RADV_DYNAMIC_VIEWPORT
) {
1368 assert(pCreateInfo
->pViewportState
);
1370 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1371 if (states
& RADV_DYNAMIC_VIEWPORT
) {
1372 typed_memcpy(dynamic
->viewport
.viewports
,
1373 pCreateInfo
->pViewportState
->pViewports
,
1374 pCreateInfo
->pViewportState
->viewportCount
);
1378 if (needed_states
& RADV_DYNAMIC_SCISSOR
) {
1379 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1380 if (states
& RADV_DYNAMIC_SCISSOR
) {
1381 typed_memcpy(dynamic
->scissor
.scissors
,
1382 pCreateInfo
->pViewportState
->pScissors
,
1383 pCreateInfo
->pViewportState
->scissorCount
);
1387 if (states
& RADV_DYNAMIC_LINE_WIDTH
) {
1388 assert(pCreateInfo
->pRasterizationState
);
1389 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1392 if (states
& RADV_DYNAMIC_DEPTH_BIAS
) {
1393 assert(pCreateInfo
->pRasterizationState
);
1394 dynamic
->depth_bias
.bias
=
1395 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1396 dynamic
->depth_bias
.clamp
=
1397 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1398 dynamic
->depth_bias
.slope
=
1399 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1402 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1404 * pColorBlendState is [...] NULL if the pipeline has rasterization
1405 * disabled or if the subpass of the render pass the pipeline is
1406 * created against does not use any color attachments.
1408 if (subpass
->has_color_att
&& states
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
1409 assert(pCreateInfo
->pColorBlendState
);
1410 typed_memcpy(dynamic
->blend_constants
,
1411 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1414 if (states
& RADV_DYNAMIC_CULL_MODE
) {
1415 dynamic
->cull_mode
=
1416 pCreateInfo
->pRasterizationState
->cullMode
;
1419 if (states
& RADV_DYNAMIC_FRONT_FACE
) {
1420 dynamic
->front_face
=
1421 pCreateInfo
->pRasterizationState
->frontFace
;
1424 if (states
& RADV_DYNAMIC_PRIMITIVE_TOPOLOGY
) {
1425 dynamic
->primitive_topology
=
1426 si_translate_prim(pCreateInfo
->pInputAssemblyState
->topology
);
1427 if (extra
&& extra
->use_rectlist
) {
1428 dynamic
->primitive_topology
= V_008958_DI_PT_RECTLIST
;
1432 /* If there is no depthstencil attachment, then don't read
1433 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1434 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1435 * no need to override the depthstencil defaults in
1436 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1438 * Section 9.2 of the Vulkan 1.0.15 spec says:
1440 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1441 * disabled or if the subpass of the render pass the pipeline is created
1442 * against does not use a depth/stencil attachment.
1444 if (needed_states
&& subpass
->depth_stencil_attachment
) {
1445 assert(pCreateInfo
->pDepthStencilState
);
1447 if (states
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
1448 dynamic
->depth_bounds
.min
=
1449 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1450 dynamic
->depth_bounds
.max
=
1451 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1454 if (states
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
1455 dynamic
->stencil_compare_mask
.front
=
1456 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1457 dynamic
->stencil_compare_mask
.back
=
1458 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1461 if (states
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
1462 dynamic
->stencil_write_mask
.front
=
1463 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1464 dynamic
->stencil_write_mask
.back
=
1465 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1468 if (states
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
1469 dynamic
->stencil_reference
.front
=
1470 pCreateInfo
->pDepthStencilState
->front
.reference
;
1471 dynamic
->stencil_reference
.back
=
1472 pCreateInfo
->pDepthStencilState
->back
.reference
;
1475 if (states
& RADV_DYNAMIC_DEPTH_TEST_ENABLE
) {
1476 dynamic
->depth_test_enable
=
1477 pCreateInfo
->pDepthStencilState
->depthTestEnable
;
1480 if (states
& RADV_DYNAMIC_DEPTH_WRITE_ENABLE
) {
1481 dynamic
->depth_write_enable
=
1482 pCreateInfo
->pDepthStencilState
->depthWriteEnable
;
1485 if (states
& RADV_DYNAMIC_DEPTH_COMPARE_OP
) {
1486 dynamic
->depth_compare_op
=
1487 pCreateInfo
->pDepthStencilState
->depthCompareOp
;
1490 if (states
& RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE
) {
1491 dynamic
->depth_bounds_test_enable
=
1492 pCreateInfo
->pDepthStencilState
->depthBoundsTestEnable
;
1495 if (states
& RADV_DYNAMIC_STENCIL_TEST_ENABLE
) {
1496 dynamic
->stencil_test_enable
=
1497 pCreateInfo
->pDepthStencilState
->stencilTestEnable
;
1500 if (states
& RADV_DYNAMIC_STENCIL_OP
) {
1501 dynamic
->stencil_op
.front
.compare_op
=
1502 pCreateInfo
->pDepthStencilState
->front
.compareOp
;
1503 dynamic
->stencil_op
.front
.fail_op
=
1504 pCreateInfo
->pDepthStencilState
->front
.failOp
;
1505 dynamic
->stencil_op
.front
.pass_op
=
1506 pCreateInfo
->pDepthStencilState
->front
.passOp
;
1507 dynamic
->stencil_op
.front
.depth_fail_op
=
1508 pCreateInfo
->pDepthStencilState
->front
.depthFailOp
;
1510 dynamic
->stencil_op
.back
.compare_op
=
1511 pCreateInfo
->pDepthStencilState
->back
.compareOp
;
1512 dynamic
->stencil_op
.back
.fail_op
=
1513 pCreateInfo
->pDepthStencilState
->back
.failOp
;
1514 dynamic
->stencil_op
.back
.pass_op
=
1515 pCreateInfo
->pDepthStencilState
->back
.passOp
;
1516 dynamic
->stencil_op
.back
.depth_fail_op
=
1517 pCreateInfo
->pDepthStencilState
->back
.depthFailOp
;
1521 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
1522 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
1523 if (needed_states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1524 dynamic
->discard_rectangle
.count
= discard_rectangle_info
->discardRectangleCount
;
1525 if (states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1526 typed_memcpy(dynamic
->discard_rectangle
.rectangles
,
1527 discard_rectangle_info
->pDiscardRectangles
,
1528 discard_rectangle_info
->discardRectangleCount
);
1532 if (needed_states
& RADV_DYNAMIC_SAMPLE_LOCATIONS
) {
1533 const VkPipelineSampleLocationsStateCreateInfoEXT
*sample_location_info
=
1534 vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1535 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
);
1536 /* If sampleLocationsEnable is VK_FALSE, the default sample
1537 * locations are used and the values specified in
1538 * sampleLocationsInfo are ignored.
1540 if (sample_location_info
->sampleLocationsEnable
) {
1541 const VkSampleLocationsInfoEXT
*pSampleLocationsInfo
=
1542 &sample_location_info
->sampleLocationsInfo
;
1544 assert(pSampleLocationsInfo
->sampleLocationsCount
<= MAX_SAMPLE_LOCATIONS
);
1546 dynamic
->sample_location
.per_pixel
= pSampleLocationsInfo
->sampleLocationsPerPixel
;
1547 dynamic
->sample_location
.grid_size
= pSampleLocationsInfo
->sampleLocationGridSize
;
1548 dynamic
->sample_location
.count
= pSampleLocationsInfo
->sampleLocationsCount
;
1549 typed_memcpy(&dynamic
->sample_location
.locations
[0],
1550 pSampleLocationsInfo
->pSampleLocations
,
1551 pSampleLocationsInfo
->sampleLocationsCount
);
1555 const VkPipelineRasterizationLineStateCreateInfoEXT
*rast_line_info
=
1556 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1557 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1558 if (needed_states
& RADV_DYNAMIC_LINE_STIPPLE
) {
1559 dynamic
->line_stipple
.factor
= rast_line_info
->lineStippleFactor
;
1560 dynamic
->line_stipple
.pattern
= rast_line_info
->lineStipplePattern
;
1563 if (!(states
& RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE
))
1564 pipeline
->graphics
.uses_dynamic_stride
= true;
1566 pipeline
->dynamic_state
.mask
= states
;
1570 gfx9_get_gs_info(const struct radv_pipeline_key
*key
,
1571 const struct radv_pipeline
*pipeline
,
1573 struct radv_shader_info
*infos
,
1574 struct gfx9_gs_info
*out
)
1576 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1577 struct radv_es_output_info
*es_info
;
1578 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1579 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1581 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ?
1582 &infos
[MESA_SHADER_TESS_EVAL
].tes
.es_info
:
1583 &infos
[MESA_SHADER_VERTEX
].vs
.es_info
;
1585 unsigned gs_num_invocations
= MAX2(gs_info
->gs
.invocations
, 1);
1586 bool uses_adjacency
;
1587 switch(key
->topology
) {
1588 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1589 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1590 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1591 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1592 uses_adjacency
= true;
1595 uses_adjacency
= false;
1599 /* All these are in dwords: */
1600 /* We can't allow using the whole LDS, because GS waves compete with
1601 * other shader stages for LDS space. */
1602 const unsigned max_lds_size
= 8 * 1024;
1603 const unsigned esgs_itemsize
= es_info
->esgs_itemsize
/ 4;
1604 unsigned esgs_lds_size
;
1606 /* All these are per subgroup: */
1607 const unsigned max_out_prims
= 32 * 1024;
1608 const unsigned max_es_verts
= 255;
1609 const unsigned ideal_gs_prims
= 64;
1610 unsigned max_gs_prims
, gs_prims
;
1611 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
1613 if (uses_adjacency
|| gs_num_invocations
> 1)
1614 max_gs_prims
= 127 / gs_num_invocations
;
1618 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1619 * Make sure we don't go over the maximum value.
1621 if (gs_info
->gs
.vertices_out
> 0) {
1622 max_gs_prims
= MIN2(max_gs_prims
,
1624 (gs_info
->gs
.vertices_out
* gs_num_invocations
));
1626 assert(max_gs_prims
> 0);
1628 /* If the primitive has adjacency, halve the number of vertices
1629 * that will be reused in multiple primitives.
1631 min_es_verts
= gs_info
->gs
.vertices_in
/ (uses_adjacency
? 2 : 1);
1633 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
1634 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
1636 /* Compute ESGS LDS size based on the worst case number of ES vertices
1637 * needed to create the target number of GS prims per subgroup.
1639 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1641 /* If total LDS usage is too big, refactor partitions based on ratio
1642 * of ESGS item sizes.
1644 if (esgs_lds_size
> max_lds_size
) {
1645 /* Our target GS Prims Per Subgroup was too large. Calculate
1646 * the maximum number of GS Prims Per Subgroup that will fit
1647 * into LDS, capped by the maximum that the hardware can support.
1649 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
1651 assert(gs_prims
> 0);
1652 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
1655 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1656 assert(esgs_lds_size
<= max_lds_size
);
1659 /* Now calculate remaining ESGS information. */
1661 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
1663 es_verts
= max_es_verts
;
1665 /* Vertices for adjacency primitives are not always reused, so restore
1666 * it for ES_VERTS_PER_SUBGRP.
1668 min_es_verts
= gs_info
->gs
.vertices_in
;
1670 /* For normal primitives, the VGT only checks if they are past the ES
1671 * verts per subgroup after allocating a full GS primitive and if they
1672 * are, kick off a new subgroup. But if those additional ES verts are
1673 * unique (e.g. not reused) we need to make sure there is enough LDS
1674 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1676 es_verts
-= min_es_verts
- 1;
1678 uint32_t es_verts_per_subgroup
= es_verts
;
1679 uint32_t gs_prims_per_subgroup
= gs_prims
;
1680 uint32_t gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
1681 uint32_t max_prims_per_subgroup
= gs_inst_prims_in_subgroup
* gs_info
->gs
.vertices_out
;
1682 out
->lds_size
= align(esgs_lds_size
, 128) / 128;
1683 out
->vgt_gs_onchip_cntl
= S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup
) |
1684 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup
) |
1685 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup
);
1686 out
->vgt_gs_max_prims_per_subgroup
= S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup
);
1687 out
->vgt_esgs_ring_itemsize
= esgs_itemsize
;
1688 assert(max_prims_per_subgroup
<= max_out_prims
);
1691 static void clamp_gsprims_to_esverts(unsigned *max_gsprims
, unsigned max_esverts
,
1692 unsigned min_verts_per_prim
, bool use_adjacency
)
1694 unsigned max_reuse
= max_esverts
- min_verts_per_prim
;
1697 *max_gsprims
= MIN2(*max_gsprims
, 1 + max_reuse
);
1701 radv_get_num_input_vertices(nir_shader
**nir
)
1703 if (nir
[MESA_SHADER_GEOMETRY
]) {
1704 nir_shader
*gs
= nir
[MESA_SHADER_GEOMETRY
];
1706 return gs
->info
.gs
.vertices_in
;
1709 if (nir
[MESA_SHADER_TESS_CTRL
]) {
1710 nir_shader
*tes
= nir
[MESA_SHADER_TESS_EVAL
];
1712 if (tes
->info
.tess
.point_mode
)
1714 if (tes
->info
.tess
.primitive_mode
== GL_ISOLINES
)
1723 gfx10_get_ngg_info(const struct radv_pipeline_key
*key
,
1724 struct radv_pipeline
*pipeline
,
1726 struct radv_shader_info
*infos
,
1727 struct gfx10_ngg_info
*ngg
)
1729 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1730 struct radv_es_output_info
*es_info
=
1731 nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1732 unsigned gs_type
= nir
[MESA_SHADER_GEOMETRY
] ? MESA_SHADER_GEOMETRY
: MESA_SHADER_VERTEX
;
1733 unsigned max_verts_per_prim
= radv_get_num_input_vertices(nir
);
1734 unsigned min_verts_per_prim
=
1735 gs_type
== MESA_SHADER_GEOMETRY
? max_verts_per_prim
: 1;
1736 unsigned gs_num_invocations
= nir
[MESA_SHADER_GEOMETRY
] ? MAX2(gs_info
->gs
.invocations
, 1) : 1;
1737 bool uses_adjacency
;
1738 switch(key
->topology
) {
1739 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1740 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1741 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1742 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1743 uses_adjacency
= true;
1746 uses_adjacency
= false;
1750 /* All these are in dwords: */
1751 /* We can't allow using the whole LDS, because GS waves compete with
1752 * other shader stages for LDS space.
1754 * TODO: We should really take the shader's internal LDS use into
1755 * account. The linker will fail if the size is greater than
1758 const unsigned max_lds_size
= 8 * 1024 - 768;
1759 const unsigned target_lds_size
= max_lds_size
;
1760 unsigned esvert_lds_size
= 0;
1761 unsigned gsprim_lds_size
= 0;
1763 /* All these are per subgroup: */
1764 bool max_vert_out_per_gs_instance
= false;
1765 unsigned max_esverts_base
= 256;
1766 unsigned max_gsprims_base
= 128; /* default prim group size clamp */
1768 /* Hardware has the following non-natural restrictions on the value
1769 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1771 * - at most 252 for any line input primitive type
1772 * - at most 251 for any quad input primitive type
1773 * - at most 251 for triangle strips with adjacency (this happens to
1774 * be the natural limit for triangle *lists* with adjacency)
1776 max_esverts_base
= MIN2(max_esverts_base
, 251 + max_verts_per_prim
- 1);
1778 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1779 unsigned max_out_verts_per_gsprim
=
1780 gs_info
->gs
.vertices_out
* gs_num_invocations
;
1782 if (max_out_verts_per_gsprim
<= 256) {
1783 if (max_out_verts_per_gsprim
) {
1784 max_gsprims_base
= MIN2(max_gsprims_base
,
1785 256 / max_out_verts_per_gsprim
);
1788 /* Use special multi-cycling mode in which each GS
1789 * instance gets its own subgroup. Does not work with
1791 max_vert_out_per_gs_instance
= true;
1792 max_gsprims_base
= 1;
1793 max_out_verts_per_gsprim
= gs_info
->gs
.vertices_out
;
1796 esvert_lds_size
= es_info
->esgs_itemsize
/ 4;
1797 gsprim_lds_size
= (gs_info
->gs
.gsvs_vertex_size
/ 4 + 1) * max_out_verts_per_gsprim
;
1800 /* LDS size for passing data from GS to ES. */
1801 struct radv_streamout_info
*so_info
= nir
[MESA_SHADER_TESS_CTRL
]
1802 ? &infos
[MESA_SHADER_TESS_EVAL
].so
1803 : &infos
[MESA_SHADER_VERTEX
].so
;
1805 if (so_info
->num_outputs
)
1806 esvert_lds_size
= 4 * so_info
->num_outputs
+ 1;
1808 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1809 * corresponding to the ES thread of the provoking vertex. All
1810 * ES threads load and export PrimitiveID for their thread.
1812 if (!nir
[MESA_SHADER_TESS_CTRL
] &&
1813 infos
[MESA_SHADER_VERTEX
].vs
.outinfo
.export_prim_id
)
1814 esvert_lds_size
= MAX2(esvert_lds_size
, 1);
1817 unsigned max_gsprims
= max_gsprims_base
;
1818 unsigned max_esverts
= max_esverts_base
;
1820 if (esvert_lds_size
)
1821 max_esverts
= MIN2(max_esverts
, target_lds_size
/ esvert_lds_size
);
1822 if (gsprim_lds_size
)
1823 max_gsprims
= MIN2(max_gsprims
, target_lds_size
/ gsprim_lds_size
);
1825 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1826 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
, min_verts_per_prim
, uses_adjacency
);
1827 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1829 if (esvert_lds_size
|| gsprim_lds_size
) {
1830 /* Now that we have a rough proportionality between esverts
1831 * and gsprims based on the primitive type, scale both of them
1832 * down simultaneously based on required LDS space.
1834 * We could be smarter about this if we knew how much vertex
1837 unsigned lds_total
= max_esverts
* esvert_lds_size
+
1838 max_gsprims
* gsprim_lds_size
;
1839 if (lds_total
> target_lds_size
) {
1840 max_esverts
= max_esverts
* target_lds_size
/ lds_total
;
1841 max_gsprims
= max_gsprims
* target_lds_size
/ lds_total
;
1843 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1844 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1845 min_verts_per_prim
, uses_adjacency
);
1846 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1850 /* Round up towards full wave sizes for better ALU utilization. */
1851 if (!max_vert_out_per_gs_instance
) {
1852 unsigned orig_max_esverts
;
1853 unsigned orig_max_gsprims
;
1856 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1857 wavesize
= gs_info
->wave_size
;
1859 wavesize
= nir
[MESA_SHADER_TESS_CTRL
]
1860 ? infos
[MESA_SHADER_TESS_EVAL
].wave_size
1861 : infos
[MESA_SHADER_VERTEX
].wave_size
;
1865 orig_max_esverts
= max_esverts
;
1866 orig_max_gsprims
= max_gsprims
;
1868 max_esverts
= align(max_esverts
, wavesize
);
1869 max_esverts
= MIN2(max_esverts
, max_esverts_base
);
1870 if (esvert_lds_size
)
1871 max_esverts
= MIN2(max_esverts
,
1872 (max_lds_size
- max_gsprims
* gsprim_lds_size
) /
1874 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1876 max_gsprims
= align(max_gsprims
, wavesize
);
1877 max_gsprims
= MIN2(max_gsprims
, max_gsprims_base
);
1878 if (gsprim_lds_size
)
1879 max_gsprims
= MIN2(max_gsprims
,
1880 (max_lds_size
- max_esverts
* esvert_lds_size
) /
1882 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1883 min_verts_per_prim
, uses_adjacency
);
1884 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1885 } while (orig_max_esverts
!= max_esverts
|| orig_max_gsprims
!= max_gsprims
);
1888 /* Hardware restriction: minimum value of max_esverts */
1889 max_esverts
= MAX2(max_esverts
, 23 + max_verts_per_prim
);
1891 unsigned max_out_vertices
=
1892 max_vert_out_per_gs_instance
? gs_info
->gs
.vertices_out
:
1893 gs_type
== MESA_SHADER_GEOMETRY
?
1894 max_gsprims
* gs_num_invocations
* gs_info
->gs
.vertices_out
:
1896 assert(max_out_vertices
<= 256);
1898 unsigned prim_amp_factor
= 1;
1899 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1900 /* Number of output primitives per GS input primitive after
1902 prim_amp_factor
= gs_info
->gs
.vertices_out
;
1905 /* The GE only checks against the maximum number of ES verts after
1906 * allocating a full GS primitive. So we need to ensure that whenever
1907 * this check passes, there is enough space for a full primitive without
1910 ngg
->hw_max_esverts
= max_esverts
- max_verts_per_prim
+ 1;
1911 ngg
->max_gsprims
= max_gsprims
;
1912 ngg
->max_out_verts
= max_out_vertices
;
1913 ngg
->prim_amp_factor
= prim_amp_factor
;
1914 ngg
->max_vert_out_per_gs_instance
= max_vert_out_per_gs_instance
;
1915 ngg
->ngg_emit_size
= max_gsprims
* gsprim_lds_size
;
1916 ngg
->esgs_ring_size
= 4 * max_esverts
* esvert_lds_size
;
1918 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1919 ngg
->vgt_esgs_ring_itemsize
= es_info
->esgs_itemsize
/ 4;
1921 ngg
->vgt_esgs_ring_itemsize
= 1;
1924 pipeline
->graphics
.esgs_ring_size
= ngg
->esgs_ring_size
;
1926 assert(ngg
->hw_max_esverts
>= 24); /* HW limitation */
1930 calculate_gs_ring_sizes(struct radv_pipeline
*pipeline
,
1931 const struct gfx9_gs_info
*gs
)
1933 struct radv_device
*device
= pipeline
->device
;
1934 unsigned num_se
= device
->physical_device
->rad_info
.max_se
;
1935 unsigned wave_size
= 64;
1936 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
1937 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1938 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1940 unsigned gs_vertex_reuse
=
1941 (device
->physical_device
->rad_info
.chip_class
>= GFX8
? 32 : 16) * num_se
;
1942 unsigned alignment
= 256 * num_se
;
1943 /* The maximum size is 63.999 MB per SE. */
1944 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
1945 struct radv_shader_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
1947 /* Calculate the minimum size. */
1948 unsigned min_esgs_ring_size
= align(gs
->vgt_esgs_ring_itemsize
* 4 * gs_vertex_reuse
*
1949 wave_size
, alignment
);
1950 /* These are recommended sizes, not minimum sizes. */
1951 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
1952 gs
->vgt_esgs_ring_itemsize
* 4 * gs_info
->gs
.vertices_in
;
1953 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
1954 gs_info
->gs
.max_gsvs_emit_size
;
1956 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
1957 esgs_ring_size
= align(esgs_ring_size
, alignment
);
1958 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
1960 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
1961 pipeline
->graphics
.esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
1963 pipeline
->graphics
.gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
1966 struct radv_shader_variant
*
1967 radv_get_shader(struct radv_pipeline
*pipeline
,
1968 gl_shader_stage stage
)
1970 if (stage
== MESA_SHADER_VERTEX
) {
1971 if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
1972 return pipeline
->shaders
[MESA_SHADER_VERTEX
];
1973 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
])
1974 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
1975 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1976 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1977 } else if (stage
== MESA_SHADER_TESS_EVAL
) {
1978 if (!radv_pipeline_has_tess(pipeline
))
1980 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
1981 return pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
1982 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1983 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1985 return pipeline
->shaders
[stage
];
1988 static struct radv_tessellation_state
1989 calculate_tess_state(struct radv_pipeline
*pipeline
,
1990 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1992 unsigned num_tcs_input_cp
;
1993 unsigned num_tcs_output_cp
;
1994 unsigned num_patches
;
1995 struct radv_tessellation_state tess
= {0};
1997 num_tcs_input_cp
= pCreateInfo
->pTessellationState
->patchControlPoints
;
1998 num_tcs_output_cp
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.tcs_vertices_out
; //TCS VERTICES OUT
1999 num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2001 tess
.num_lds_blocks
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_lds_blocks
;
2003 tess
.ls_hs_config
= S_028B58_NUM_PATCHES(num_patches
) |
2004 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
2005 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
2007 struct radv_shader_variant
*tes
= radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
);
2008 unsigned type
= 0, partitioning
= 0, topology
= 0, distribution_mode
= 0;
2010 switch (tes
->info
.tes
.primitive_mode
) {
2012 type
= V_028B6C_TESS_TRIANGLE
;
2015 type
= V_028B6C_TESS_QUAD
;
2018 type
= V_028B6C_TESS_ISOLINE
;
2022 switch (tes
->info
.tes
.spacing
) {
2023 case TESS_SPACING_EQUAL
:
2024 partitioning
= V_028B6C_PART_INTEGER
;
2026 case TESS_SPACING_FRACTIONAL_ODD
:
2027 partitioning
= V_028B6C_PART_FRAC_ODD
;
2029 case TESS_SPACING_FRACTIONAL_EVEN
:
2030 partitioning
= V_028B6C_PART_FRAC_EVEN
;
2036 bool ccw
= tes
->info
.tes
.ccw
;
2037 const VkPipelineTessellationDomainOriginStateCreateInfo
*domain_origin_state
=
2038 vk_find_struct_const(pCreateInfo
->pTessellationState
,
2039 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO
);
2041 if (domain_origin_state
&& domain_origin_state
->domainOrigin
!= VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT
)
2044 if (tes
->info
.tes
.point_mode
)
2045 topology
= V_028B6C_OUTPUT_POINT
;
2046 else if (tes
->info
.tes
.primitive_mode
== GL_ISOLINES
)
2047 topology
= V_028B6C_OUTPUT_LINE
;
2049 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
2051 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
2053 if (pipeline
->device
->physical_device
->rad_info
.has_distributed_tess
) {
2054 if (pipeline
->device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
2055 pipeline
->device
->physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
2056 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
2058 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
2060 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
2062 tess
.tf_param
= S_028B6C_TYPE(type
) |
2063 S_028B6C_PARTITIONING(partitioning
) |
2064 S_028B6C_TOPOLOGY(topology
) |
2065 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
2070 static const struct radv_vs_output_info
*get_vs_output_info(const struct radv_pipeline
*pipeline
)
2072 if (radv_pipeline_has_gs(pipeline
))
2073 if (radv_pipeline_has_ngg(pipeline
))
2074 return &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.vs
.outinfo
;
2076 return &pipeline
->gs_copy_shader
->info
.vs
.outinfo
;
2077 else if (radv_pipeline_has_tess(pipeline
))
2078 return &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.outinfo
;
2080 return &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.outinfo
;
2084 radv_link_shaders(struct radv_pipeline
*pipeline
, nir_shader
**shaders
)
2086 nir_shader
* ordered_shaders
[MESA_SHADER_STAGES
];
2087 int shader_count
= 0;
2089 if(shaders
[MESA_SHADER_FRAGMENT
]) {
2090 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_FRAGMENT
];
2092 if(shaders
[MESA_SHADER_GEOMETRY
]) {
2093 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_GEOMETRY
];
2095 if(shaders
[MESA_SHADER_TESS_EVAL
]) {
2096 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_EVAL
];
2098 if(shaders
[MESA_SHADER_TESS_CTRL
]) {
2099 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_CTRL
];
2101 if(shaders
[MESA_SHADER_VERTEX
]) {
2102 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_VERTEX
];
2105 if (shader_count
> 1) {
2106 unsigned first
= ordered_shaders
[shader_count
- 1]->info
.stage
;
2107 unsigned last
= ordered_shaders
[0]->info
.stage
;
2109 if (ordered_shaders
[0]->info
.stage
== MESA_SHADER_FRAGMENT
&&
2110 ordered_shaders
[1]->info
.has_transform_feedback_varyings
)
2111 nir_link_xfb_varyings(ordered_shaders
[1], ordered_shaders
[0]);
2113 for (int i
= 0; i
< shader_count
; ++i
) {
2114 nir_variable_mode mask
= 0;
2116 if (ordered_shaders
[i
]->info
.stage
!= first
)
2117 mask
= mask
| nir_var_shader_in
;
2119 if (ordered_shaders
[i
]->info
.stage
!= last
)
2120 mask
= mask
| nir_var_shader_out
;
2122 nir_lower_io_to_scalar_early(ordered_shaders
[i
], mask
);
2123 radv_optimize_nir(ordered_shaders
[i
], false, false);
2127 for (int i
= 1; i
< shader_count
; ++i
) {
2128 nir_lower_io_arrays_to_elements(ordered_shaders
[i
],
2129 ordered_shaders
[i
- 1]);
2131 if (nir_link_opt_varyings(ordered_shaders
[i
],
2132 ordered_shaders
[i
- 1]))
2133 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2135 nir_remove_dead_variables(ordered_shaders
[i
],
2136 nir_var_shader_out
, NULL
);
2137 nir_remove_dead_variables(ordered_shaders
[i
- 1],
2138 nir_var_shader_in
, NULL
);
2140 bool progress
= nir_remove_unused_varyings(ordered_shaders
[i
],
2141 ordered_shaders
[i
- 1]);
2143 nir_compact_varyings(ordered_shaders
[i
],
2144 ordered_shaders
[i
- 1], true);
2147 if (nir_lower_global_vars_to_local(ordered_shaders
[i
])) {
2148 ac_lower_indirect_derefs(ordered_shaders
[i
],
2149 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2151 radv_optimize_nir(ordered_shaders
[i
], false, false);
2153 if (nir_lower_global_vars_to_local(ordered_shaders
[i
- 1])) {
2154 ac_lower_indirect_derefs(ordered_shaders
[i
- 1],
2155 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2157 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2163 radv_set_linked_driver_locations(struct radv_pipeline
*pipeline
, nir_shader
**shaders
,
2164 struct radv_shader_info infos
[MESA_SHADER_STAGES
])
2166 bool has_tess
= shaders
[MESA_SHADER_TESS_CTRL
];
2167 bool has_gs
= shaders
[MESA_SHADER_GEOMETRY
];
2169 if (!has_tess
&& !has_gs
)
2172 unsigned vs_info_idx
= MESA_SHADER_VERTEX
;
2173 unsigned tes_info_idx
= MESA_SHADER_TESS_EVAL
;
2175 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2176 /* These are merged into the next stage */
2177 vs_info_idx
= has_tess
? MESA_SHADER_TESS_CTRL
: MESA_SHADER_GEOMETRY
;
2178 tes_info_idx
= has_gs
? MESA_SHADER_GEOMETRY
: MESA_SHADER_TESS_EVAL
;
2182 nir_linked_io_var_info vs2tcs
=
2183 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_VERTEX
], shaders
[MESA_SHADER_TESS_CTRL
]);
2184 nir_linked_io_var_info tcs2tes
=
2185 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_TESS_CTRL
], shaders
[MESA_SHADER_TESS_EVAL
]);
2187 infos
[vs_info_idx
].vs
.num_linked_outputs
= vs2tcs
.num_linked_io_vars
;
2188 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_inputs
= vs2tcs
.num_linked_io_vars
;
2189 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_outputs
= tcs2tes
.num_linked_io_vars
;
2190 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_patch_outputs
= tcs2tes
.num_linked_patch_io_vars
;
2191 infos
[tes_info_idx
].tes
.num_linked_inputs
= tcs2tes
.num_linked_io_vars
;
2192 infos
[tes_info_idx
].tes
.num_linked_patch_inputs
= tcs2tes
.num_linked_patch_io_vars
;
2195 nir_linked_io_var_info tes2gs
=
2196 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_TESS_EVAL
], shaders
[MESA_SHADER_GEOMETRY
]);
2198 infos
[tes_info_idx
].tes
.num_linked_outputs
= tes2gs
.num_linked_io_vars
;
2199 infos
[MESA_SHADER_GEOMETRY
].gs
.num_linked_inputs
= tes2gs
.num_linked_io_vars
;
2201 } else if (has_gs
) {
2202 nir_linked_io_var_info vs2gs
=
2203 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_VERTEX
], shaders
[MESA_SHADER_GEOMETRY
]);
2205 infos
[vs_info_idx
].vs
.num_linked_outputs
= vs2gs
.num_linked_io_vars
;
2206 infos
[MESA_SHADER_GEOMETRY
].gs
.num_linked_inputs
= vs2gs
.num_linked_io_vars
;
2211 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo
*input_state
,
2212 uint32_t attrib_binding
)
2214 for (uint32_t i
= 0; i
< input_state
->vertexBindingDescriptionCount
; i
++) {
2215 const VkVertexInputBindingDescription
*input_binding
=
2216 &input_state
->pVertexBindingDescriptions
[i
];
2218 if (input_binding
->binding
== attrib_binding
)
2219 return input_binding
->stride
;
2225 static struct radv_pipeline_key
2226 radv_generate_graphics_pipeline_key(struct radv_pipeline
*pipeline
,
2227 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2228 const struct radv_blend_state
*blend
)
2230 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
2231 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
2232 const VkPipelineVertexInputStateCreateInfo
*input_state
=
2233 pCreateInfo
->pVertexInputState
;
2234 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*divisor_state
=
2235 vk_find_struct_const(input_state
->pNext
, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
2237 struct radv_pipeline_key key
;
2238 memset(&key
, 0, sizeof(key
));
2240 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
2241 key
.optimisations_disabled
= 1;
2243 key
.has_multiview_view_index
= !!subpass
->view_mask
;
2245 uint32_t binding_input_rate
= 0;
2246 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
2247 for (unsigned i
= 0; i
< input_state
->vertexBindingDescriptionCount
; ++i
) {
2248 if (input_state
->pVertexBindingDescriptions
[i
].inputRate
) {
2249 unsigned binding
= input_state
->pVertexBindingDescriptions
[i
].binding
;
2250 binding_input_rate
|= 1u << binding
;
2251 instance_rate_divisors
[binding
] = 1;
2254 if (divisor_state
) {
2255 for (unsigned i
= 0; i
< divisor_state
->vertexBindingDivisorCount
; ++i
) {
2256 instance_rate_divisors
[divisor_state
->pVertexBindingDivisors
[i
].binding
] =
2257 divisor_state
->pVertexBindingDivisors
[i
].divisor
;
2261 for (unsigned i
= 0; i
< input_state
->vertexAttributeDescriptionCount
; ++i
) {
2262 const VkVertexInputAttributeDescription
*desc
=
2263 &input_state
->pVertexAttributeDescriptions
[i
];
2264 const struct vk_format_description
*format_desc
;
2265 unsigned location
= desc
->location
;
2266 unsigned binding
= desc
->binding
;
2267 unsigned num_format
, data_format
;
2270 if (binding_input_rate
& (1u << binding
)) {
2271 key
.instance_rate_inputs
|= 1u << location
;
2272 key
.instance_rate_divisors
[location
] = instance_rate_divisors
[binding
];
2275 format_desc
= vk_format_description(desc
->format
);
2276 first_non_void
= vk_format_get_first_non_void_channel(desc
->format
);
2278 num_format
= radv_translate_buffer_numformat(format_desc
, first_non_void
);
2279 data_format
= radv_translate_buffer_dataformat(format_desc
, first_non_void
);
2281 key
.vertex_attribute_formats
[location
] = data_format
| (num_format
<< 4);
2282 key
.vertex_attribute_bindings
[location
] = desc
->binding
;
2283 key
.vertex_attribute_offsets
[location
] = desc
->offset
;
2284 key
.vertex_attribute_strides
[location
] = radv_get_attrib_stride(input_state
, desc
->binding
);
2286 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
&&
2287 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_STONEY
) {
2288 VkFormat format
= input_state
->pVertexAttributeDescriptions
[i
].format
;
2291 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2292 case VK_FORMAT_A2B10G10R10_SNORM_PACK32
:
2293 adjust
= RADV_ALPHA_ADJUST_SNORM
;
2295 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2296 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32
:
2297 adjust
= RADV_ALPHA_ADJUST_SSCALED
;
2299 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2300 case VK_FORMAT_A2B10G10R10_SINT_PACK32
:
2301 adjust
= RADV_ALPHA_ADJUST_SINT
;
2307 key
.vertex_alpha_adjust
|= adjust
<< (2 * location
);
2310 switch (desc
->format
) {
2311 case VK_FORMAT_B8G8R8A8_UNORM
:
2312 case VK_FORMAT_B8G8R8A8_SNORM
:
2313 case VK_FORMAT_B8G8R8A8_USCALED
:
2314 case VK_FORMAT_B8G8R8A8_SSCALED
:
2315 case VK_FORMAT_B8G8R8A8_UINT
:
2316 case VK_FORMAT_B8G8R8A8_SINT
:
2317 case VK_FORMAT_B8G8R8A8_SRGB
:
2318 case VK_FORMAT_A2R10G10B10_UNORM_PACK32
:
2319 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2320 case VK_FORMAT_A2R10G10B10_USCALED_PACK32
:
2321 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2322 case VK_FORMAT_A2R10G10B10_UINT_PACK32
:
2323 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2324 key
.vertex_post_shuffle
|= 1 << location
;
2331 const VkPipelineTessellationStateCreateInfo
*tess
=
2332 radv_pipeline_get_tessellation_state(pCreateInfo
);
2334 key
.tess_input_vertices
= tess
->patchControlPoints
;
2336 const VkPipelineMultisampleStateCreateInfo
*vkms
=
2337 radv_pipeline_get_multisample_state(pCreateInfo
);
2338 if (vkms
&& vkms
->rasterizationSamples
> 1) {
2339 uint32_t num_samples
= vkms
->rasterizationSamples
;
2340 uint32_t ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
);
2341 key
.num_samples
= num_samples
;
2342 key
.log2_ps_iter_samples
= util_logbase2(ps_iter_samples
);
2345 key
.col_format
= blend
->spi_shader_col_format
;
2346 key
.is_dual_src
= blend
->mrt0_is_dual_src
;
2347 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX8
) {
2348 key
.is_int8
= blend
->col_format_is_int8
;
2349 key
.is_int10
= blend
->col_format_is_int10
;
2352 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
2353 key
.topology
= pCreateInfo
->pInputAssemblyState
->topology
;
2359 radv_nir_stage_uses_xfb(const nir_shader
*nir
)
2361 nir_xfb_info
*xfb
= nir_gather_xfb_info(nir
, NULL
);
2362 bool uses_xfb
= !!xfb
;
2369 radv_fill_shader_keys(struct radv_device
*device
,
2370 struct radv_shader_variant_key
*keys
,
2371 const struct radv_pipeline_key
*key
,
2374 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_inputs
= key
->instance_rate_inputs
;
2375 keys
[MESA_SHADER_VERTEX
].vs
.alpha_adjust
= key
->vertex_alpha_adjust
;
2376 keys
[MESA_SHADER_VERTEX
].vs
.post_shuffle
= key
->vertex_post_shuffle
;
2377 for (unsigned i
= 0; i
< MAX_VERTEX_ATTRIBS
; ++i
) {
2378 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_divisors
[i
] = key
->instance_rate_divisors
[i
];
2379 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_formats
[i
] = key
->vertex_attribute_formats
[i
];
2380 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_bindings
[i
] = key
->vertex_attribute_bindings
[i
];
2381 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_offsets
[i
] = key
->vertex_attribute_offsets
[i
];
2382 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_strides
[i
] = key
->vertex_attribute_strides
[i
];
2384 keys
[MESA_SHADER_VERTEX
].vs
.outprim
= si_conv_prim_to_gs_out(key
->topology
);
2386 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2387 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ls
= true;
2388 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= 0;
2389 keys
[MESA_SHADER_TESS_CTRL
].tcs
.input_vertices
= key
->tess_input_vertices
;
2390 keys
[MESA_SHADER_TESS_CTRL
].tcs
.primitive_mode
= nir
[MESA_SHADER_TESS_EVAL
]->info
.tess
.primitive_mode
;
2392 keys
[MESA_SHADER_TESS_CTRL
].tcs
.tes_reads_tess_factors
= !!(nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
& (VARYING_BIT_TESS_LEVEL_INNER
| VARYING_BIT_TESS_LEVEL_OUTER
));
2395 if (nir
[MESA_SHADER_GEOMETRY
]) {
2396 if (nir
[MESA_SHADER_TESS_CTRL
])
2397 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_es
= true;
2399 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_es
= true;
2402 if (device
->physical_device
->use_ngg
) {
2403 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2404 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= true;
2406 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= true;
2409 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2410 nir
[MESA_SHADER_GEOMETRY
] &&
2411 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.invocations
*
2412 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.vertices_out
> 256) {
2413 /* Fallback to the legacy path if tessellation is
2414 * enabled with extreme geometry because
2415 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2418 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2421 if (!device
->physical_device
->use_ngg_gs
) {
2422 if (nir
[MESA_SHADER_GEOMETRY
]) {
2423 if (nir
[MESA_SHADER_TESS_CTRL
])
2424 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2426 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2430 gl_shader_stage last_xfb_stage
= MESA_SHADER_VERTEX
;
2432 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2437 bool uses_xfb
= nir
[last_xfb_stage
] &&
2438 radv_nir_stage_uses_xfb(nir
[last_xfb_stage
]);
2440 if (!device
->physical_device
->use_ngg_streamout
&& uses_xfb
) {
2441 if (nir
[MESA_SHADER_TESS_CTRL
])
2442 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2444 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2447 /* Determine if the pipeline is eligible for the NGG passthrough
2448 * mode. It can't be enabled for geometry shaders, for NGG
2449 * streamout or for vertex shaders that export the primitive ID
2450 * (this is checked later because we don't have the info here.)
2452 if (!nir
[MESA_SHADER_GEOMETRY
] && !uses_xfb
) {
2453 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2454 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
) {
2455 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg_passthrough
= true;
2456 } else if (nir
[MESA_SHADER_VERTEX
] &&
2457 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) {
2458 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg_passthrough
= true;
2463 for(int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
2464 keys
[i
].has_multiview_view_index
= key
->has_multiview_view_index
;
2466 keys
[MESA_SHADER_FRAGMENT
].fs
.col_format
= key
->col_format
;
2467 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int8
= key
->is_int8
;
2468 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int10
= key
->is_int10
;
2469 keys
[MESA_SHADER_FRAGMENT
].fs
.log2_ps_iter_samples
= key
->log2_ps_iter_samples
;
2470 keys
[MESA_SHADER_FRAGMENT
].fs
.num_samples
= key
->num_samples
;
2471 keys
[MESA_SHADER_FRAGMENT
].fs
.is_dual_src
= key
->is_dual_src
;
2473 if (nir
[MESA_SHADER_COMPUTE
]) {
2474 keys
[MESA_SHADER_COMPUTE
].cs
.subgroup_size
= key
->compute_subgroup_size
;
2479 radv_get_wave_size(struct radv_device
*device
,
2480 const VkPipelineShaderStageCreateInfo
*pStage
,
2481 gl_shader_stage stage
,
2482 const struct radv_shader_variant_key
*key
)
2484 if (stage
== MESA_SHADER_GEOMETRY
&& !key
->vs_common_out
.as_ngg
)
2486 else if (stage
== MESA_SHADER_COMPUTE
) {
2487 if (key
->cs
.subgroup_size
) {
2488 /* Return the required subgroup size if specified. */
2489 return key
->cs
.subgroup_size
;
2491 return device
->physical_device
->cs_wave_size
;
2493 else if (stage
== MESA_SHADER_FRAGMENT
)
2494 return device
->physical_device
->ps_wave_size
;
2496 return device
->physical_device
->ge_wave_size
;
2500 radv_get_ballot_bit_size(struct radv_device
*device
,
2501 const VkPipelineShaderStageCreateInfo
*pStage
,
2502 gl_shader_stage stage
,
2503 const struct radv_shader_variant_key
*key
)
2505 if (stage
== MESA_SHADER_COMPUTE
&& key
->cs
.subgroup_size
)
2506 return key
->cs
.subgroup_size
;
2511 radv_fill_shader_info(struct radv_pipeline
*pipeline
,
2512 const VkPipelineShaderStageCreateInfo
**pStages
,
2513 struct radv_shader_variant_key
*keys
,
2514 struct radv_shader_info
*infos
,
2517 unsigned active_stages
= 0;
2518 unsigned filled_stages
= 0;
2520 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2522 active_stages
|= (1 << i
);
2525 if (nir
[MESA_SHADER_FRAGMENT
]) {
2526 radv_nir_shader_info_init(&infos
[MESA_SHADER_FRAGMENT
]);
2527 radv_nir_shader_info_pass(nir
[MESA_SHADER_FRAGMENT
],
2529 &keys
[MESA_SHADER_FRAGMENT
],
2530 &infos
[MESA_SHADER_FRAGMENT
],
2531 pipeline
->device
->physical_device
->use_llvm
);
2533 /* TODO: These are no longer used as keys we should refactor this */
2534 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
=
2535 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2536 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_layer_id
=
2537 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2538 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_clip_dists
=
2539 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2540 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_viewport_index
=
2541 infos
[MESA_SHADER_FRAGMENT
].ps
.viewport_index_input
;
2542 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_prim_id
=
2543 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2544 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_layer_id
=
2545 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2546 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_clip_dists
=
2547 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2548 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_viewport_index
=
2549 infos
[MESA_SHADER_FRAGMENT
].ps
.viewport_index_input
;
2551 /* NGG passthrough mode can't be enabled for vertex shaders
2552 * that export the primitive ID.
2554 * TODO: I should really refactor the keys logic.
2556 if (nir
[MESA_SHADER_VERTEX
] &&
2557 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
) {
2558 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg_passthrough
= false;
2561 filled_stages
|= (1 << MESA_SHADER_FRAGMENT
);
2564 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2565 infos
[MESA_SHADER_TESS_CTRL
].tcs
.tes_inputs_read
=
2566 nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
;
2567 infos
[MESA_SHADER_TESS_CTRL
].tcs
.tes_patch_inputs_read
=
2568 nir
[MESA_SHADER_TESS_EVAL
]->info
.patch_inputs_read
;
2571 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2572 nir
[MESA_SHADER_TESS_CTRL
]) {
2573 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2574 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2575 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2577 radv_nir_shader_info_init(&infos
[MESA_SHADER_TESS_CTRL
]);
2579 for (int i
= 0; i
< 2; i
++) {
2580 radv_nir_shader_info_pass(combined_nir
[i
],
2581 pipeline
->layout
, &key
,
2582 &infos
[MESA_SHADER_TESS_CTRL
],
2583 pipeline
->device
->physical_device
->use_llvm
);
2586 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2587 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2588 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2589 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2591 filled_stages
|= (1 << MESA_SHADER_VERTEX
);
2592 filled_stages
|= (1 << MESA_SHADER_TESS_CTRL
);
2595 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2596 nir
[MESA_SHADER_GEOMETRY
]) {
2597 gl_shader_stage pre_stage
= nir
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2598 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2600 radv_nir_shader_info_init(&infos
[MESA_SHADER_GEOMETRY
]);
2602 for (int i
= 0; i
< 2; i
++) {
2603 radv_nir_shader_info_pass(combined_nir
[i
],
2606 &infos
[MESA_SHADER_GEOMETRY
],
2607 pipeline
->device
->physical_device
->use_llvm
);
2610 filled_stages
|= (1 << pre_stage
);
2611 filled_stages
|= (1 << MESA_SHADER_GEOMETRY
);
2614 active_stages
^= filled_stages
;
2615 while (active_stages
) {
2616 int i
= u_bit_scan(&active_stages
);
2618 if (i
== MESA_SHADER_TESS_CTRL
) {
2619 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
=
2620 util_last_bit64(infos
[MESA_SHADER_VERTEX
].vs
.ls_outputs_written
);
2623 if (i
== MESA_SHADER_TESS_EVAL
) {
2624 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2625 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2626 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2627 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2630 radv_nir_shader_info_init(&infos
[i
]);
2631 radv_nir_shader_info_pass(nir
[i
], pipeline
->layout
,
2632 &keys
[i
], &infos
[i
], pipeline
->device
->physical_device
->use_llvm
);
2635 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2637 infos
[i
].wave_size
=
2638 radv_get_wave_size(pipeline
->device
, pStages
[i
],
2640 infos
[i
].ballot_bit_size
=
2641 radv_get_ballot_bit_size(pipeline
->device
,
2649 merge_tess_info(struct shader_info
*tes_info
,
2650 const struct shader_info
*tcs_info
)
2652 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2654 * "PointMode. Controls generation of points rather than triangles
2655 * or lines. This functionality defaults to disabled, and is
2656 * enabled if either shader stage includes the execution mode.
2658 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2659 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2660 * and OutputVertices, it says:
2662 * "One mode must be set in at least one of the tessellation
2665 * So, the fields can be set in either the TCS or TES, but they must
2666 * agree if set in both. Our backend looks at TES, so bitwise-or in
2667 * the values from the TCS.
2669 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
2670 tes_info
->tess
.tcs_vertices_out
== 0 ||
2671 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
2672 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
2674 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2675 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2676 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
2677 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
2679 assert(tcs_info
->tess
.primitive_mode
== 0 ||
2680 tes_info
->tess
.primitive_mode
== 0 ||
2681 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
2682 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
2683 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
2684 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
2688 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT
*ext
)
2693 if (ext
->pPipelineCreationFeedback
) {
2694 ext
->pPipelineCreationFeedback
->flags
= 0;
2695 ext
->pPipelineCreationFeedback
->duration
= 0;
2698 for (unsigned i
= 0; i
< ext
->pipelineStageCreationFeedbackCount
; ++i
) {
2699 ext
->pPipelineStageCreationFeedbacks
[i
].flags
= 0;
2700 ext
->pPipelineStageCreationFeedbacks
[i
].duration
= 0;
2705 void radv_start_feedback(VkPipelineCreationFeedbackEXT
*feedback
)
2710 feedback
->duration
-= radv_get_current_time();
2711 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
2715 void radv_stop_feedback(VkPipelineCreationFeedbackEXT
*feedback
, bool cache_hit
)
2720 feedback
->duration
+= radv_get_current_time();
2721 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
|
2722 (cache_hit
? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
: 0);
2725 VkResult
radv_create_shaders(struct radv_pipeline
*pipeline
,
2726 struct radv_device
*device
,
2727 struct radv_pipeline_cache
*cache
,
2728 const struct radv_pipeline_key
*key
,
2729 const VkPipelineShaderStageCreateInfo
**pStages
,
2730 const VkPipelineCreateFlags flags
,
2731 VkPipelineCreationFeedbackEXT
*pipeline_feedback
,
2732 VkPipelineCreationFeedbackEXT
**stage_feedbacks
)
2734 struct radv_shader_module fs_m
= {0};
2735 struct radv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
2736 nir_shader
*nir
[MESA_SHADER_STAGES
] = {0};
2737 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2738 struct radv_shader_variant_key keys
[MESA_SHADER_STAGES
] = {{{{{0}}}}};
2739 struct radv_shader_info infos
[MESA_SHADER_STAGES
] = {0};
2740 unsigned char hash
[20], gs_copy_hash
[20];
2741 bool keep_executable_info
= (flags
& VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
) || device
->keep_shader_info
;
2742 bool keep_statistic_info
= (flags
& VK_PIPELINE_CREATE_CAPTURE_STATISTICS_BIT_KHR
) ||
2743 (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SHADER_STATS
) ||
2744 device
->keep_shader_info
;
2746 radv_start_feedback(pipeline_feedback
);
2748 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2750 modules
[i
] = radv_shader_module_from_handle(pStages
[i
]->module
);
2751 if (modules
[i
]->nir
)
2752 _mesa_sha1_compute(modules
[i
]->nir
->info
.name
,
2753 strlen(modules
[i
]->nir
->info
.name
),
2756 pipeline
->active_stages
|= mesa_to_vk_shader_stage(i
);
2760 radv_hash_shaders(hash
, pStages
, pipeline
->layout
, key
, get_hash_flags(device
));
2761 memcpy(gs_copy_hash
, hash
, 20);
2762 gs_copy_hash
[0] ^= 1;
2764 bool found_in_application_cache
= true;
2765 if (modules
[MESA_SHADER_GEOMETRY
] && !keep_executable_info
&& !keep_statistic_info
) {
2766 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2767 radv_create_shader_variants_from_pipeline_cache(device
, cache
, gs_copy_hash
, variants
,
2768 &found_in_application_cache
);
2769 pipeline
->gs_copy_shader
= variants
[MESA_SHADER_GEOMETRY
];
2772 if (!keep_executable_info
&& !keep_statistic_info
&&
2773 radv_create_shader_variants_from_pipeline_cache(device
, cache
, hash
, pipeline
->shaders
,
2774 &found_in_application_cache
) &&
2775 (!modules
[MESA_SHADER_GEOMETRY
] || pipeline
->gs_copy_shader
)) {
2776 radv_stop_feedback(pipeline_feedback
, found_in_application_cache
);
2780 if (flags
& VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_EXT
) {
2781 radv_stop_feedback(pipeline_feedback
, found_in_application_cache
);
2782 return VK_PIPELINE_COMPILE_REQUIRED_EXT
;
2785 if (!modules
[MESA_SHADER_FRAGMENT
] && !modules
[MESA_SHADER_COMPUTE
]) {
2787 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
2788 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "noop_fs");
2789 fs_m
.nir
= fs_b
.shader
;
2790 modules
[MESA_SHADER_FRAGMENT
] = &fs_m
;
2793 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2794 const VkPipelineShaderStageCreateInfo
*stage
= pStages
[i
];
2795 unsigned subgroup_size
= 64, ballot_bit_size
= 64;
2800 radv_start_feedback(stage_feedbacks
[i
]);
2802 if (key
->compute_subgroup_size
) {
2803 /* Only compute shaders currently support requiring a
2804 * specific subgroup size.
2806 assert(i
== MESA_SHADER_COMPUTE
);
2807 subgroup_size
= key
->compute_subgroup_size
;
2808 ballot_bit_size
= key
->compute_subgroup_size
;
2811 nir
[i
] = radv_shader_compile_to_nir(device
, modules
[i
],
2812 stage
? stage
->pName
: "main", i
,
2813 stage
? stage
->pSpecializationInfo
: NULL
,
2814 flags
, pipeline
->layout
,
2815 subgroup_size
, ballot_bit_size
);
2817 /* We don't want to alter meta shaders IR directly so clone it
2820 if (nir
[i
]->info
.name
) {
2821 nir
[i
] = nir_shader_clone(NULL
, nir
[i
]);
2824 radv_stop_feedback(stage_feedbacks
[i
], false);
2827 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2828 nir_lower_patch_vertices(nir
[MESA_SHADER_TESS_EVAL
], nir
[MESA_SHADER_TESS_CTRL
]->info
.tess
.tcs_vertices_out
, NULL
);
2829 merge_tess_info(&nir
[MESA_SHADER_TESS_EVAL
]->info
, &nir
[MESA_SHADER_TESS_CTRL
]->info
);
2832 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
2833 radv_link_shaders(pipeline
, nir
);
2835 radv_set_linked_driver_locations(pipeline
, nir
, infos
);
2837 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2839 /* do this again since information such as outputs_read can be out-of-date */
2840 nir_shader_gather_info(nir
[i
], nir_shader_get_entrypoint(nir
[i
]));
2842 if (device
->physical_device
->use_llvm
) {
2843 NIR_PASS_V(nir
[i
], nir_lower_bool_to_int32
);
2845 NIR_PASS_V(nir
[i
], nir_lower_non_uniform_access
,
2846 nir_lower_non_uniform_ubo_access
|
2847 nir_lower_non_uniform_ssbo_access
|
2848 nir_lower_non_uniform_texture_access
|
2849 nir_lower_non_uniform_image_access
);
2854 if (nir
[MESA_SHADER_FRAGMENT
])
2855 radv_lower_fs_io(nir
[MESA_SHADER_FRAGMENT
]);
2857 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2858 if (radv_can_dump_shader(device
, modules
[i
], false))
2859 nir_print_shader(nir
[i
], stderr
);
2862 radv_fill_shader_keys(device
, keys
, key
, nir
);
2864 radv_fill_shader_info(pipeline
, pStages
, keys
, infos
, nir
);
2866 if ((nir
[MESA_SHADER_VERTEX
] &&
2867 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) ||
2868 (nir
[MESA_SHADER_TESS_EVAL
] &&
2869 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
)) {
2870 struct gfx10_ngg_info
*ngg_info
;
2872 if (nir
[MESA_SHADER_GEOMETRY
])
2873 ngg_info
= &infos
[MESA_SHADER_GEOMETRY
].ngg_info
;
2874 else if (nir
[MESA_SHADER_TESS_CTRL
])
2875 ngg_info
= &infos
[MESA_SHADER_TESS_EVAL
].ngg_info
;
2877 ngg_info
= &infos
[MESA_SHADER_VERTEX
].ngg_info
;
2879 gfx10_get_ngg_info(key
, pipeline
, nir
, infos
, ngg_info
);
2880 } else if (nir
[MESA_SHADER_GEOMETRY
]) {
2881 struct gfx9_gs_info
*gs_info
=
2882 &infos
[MESA_SHADER_GEOMETRY
].gs_ring_info
;
2884 gfx9_get_gs_info(key
, pipeline
, nir
, infos
, gs_info
);
2887 if(modules
[MESA_SHADER_GEOMETRY
]) {
2888 struct radv_shader_binary
*gs_copy_binary
= NULL
;
2889 if (!pipeline
->gs_copy_shader
&&
2890 !radv_pipeline_has_ngg(pipeline
)) {
2891 struct radv_shader_info info
= {};
2892 struct radv_shader_variant_key key
= {};
2894 key
.has_multiview_view_index
=
2895 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
;
2897 radv_nir_shader_info_pass(nir
[MESA_SHADER_GEOMETRY
],
2898 pipeline
->layout
, &key
,
2899 &info
, pipeline
->device
->physical_device
->use_llvm
);
2900 info
.wave_size
= 64; /* Wave32 not supported. */
2901 info
.ballot_bit_size
= 64;
2903 pipeline
->gs_copy_shader
= radv_create_gs_copy_shader(
2904 device
, nir
[MESA_SHADER_GEOMETRY
], &info
,
2905 &gs_copy_binary
, keep_executable_info
, keep_statistic_info
,
2906 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
);
2909 if (!keep_executable_info
&& !keep_statistic_info
&& pipeline
->gs_copy_shader
) {
2910 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2911 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2913 binaries
[MESA_SHADER_GEOMETRY
] = gs_copy_binary
;
2914 variants
[MESA_SHADER_GEOMETRY
] = pipeline
->gs_copy_shader
;
2916 radv_pipeline_cache_insert_shaders(device
, cache
,
2921 free(gs_copy_binary
);
2924 if (nir
[MESA_SHADER_FRAGMENT
]) {
2925 if (!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]) {
2926 radv_start_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
]);
2928 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] =
2929 radv_shader_variant_compile(device
, modules
[MESA_SHADER_FRAGMENT
], &nir
[MESA_SHADER_FRAGMENT
], 1,
2930 pipeline
->layout
, keys
+ MESA_SHADER_FRAGMENT
,
2931 infos
+ MESA_SHADER_FRAGMENT
,
2932 keep_executable_info
, keep_statistic_info
,
2933 &binaries
[MESA_SHADER_FRAGMENT
]);
2935 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
], false);
2939 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_TESS_CTRL
]) {
2940 if (!pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]) {
2941 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2942 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2943 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2945 radv_start_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
]);
2947 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_TESS_CTRL
], combined_nir
, 2,
2949 &key
, &infos
[MESA_SHADER_TESS_CTRL
], keep_executable_info
,
2950 keep_statistic_info
, &binaries
[MESA_SHADER_TESS_CTRL
]);
2952 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
], false);
2954 modules
[MESA_SHADER_VERTEX
] = NULL
;
2955 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2956 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2959 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_GEOMETRY
]) {
2960 gl_shader_stage pre_stage
= modules
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2961 if (!pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
2962 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2964 radv_start_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
]);
2966 pipeline
->shaders
[MESA_SHADER_GEOMETRY
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_GEOMETRY
], combined_nir
, 2,
2968 &keys
[pre_stage
], &infos
[MESA_SHADER_GEOMETRY
], keep_executable_info
,
2969 keep_statistic_info
, &binaries
[MESA_SHADER_GEOMETRY
]);
2971 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
], false);
2973 modules
[pre_stage
] = NULL
;
2976 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2977 if(modules
[i
] && !pipeline
->shaders
[i
]) {
2978 if (i
== MESA_SHADER_TESS_CTRL
) {
2979 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.ls_outputs_written
);
2981 if (i
== MESA_SHADER_TESS_EVAL
) {
2982 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2983 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2986 radv_start_feedback(stage_feedbacks
[i
]);
2988 pipeline
->shaders
[i
] = radv_shader_variant_compile(device
, modules
[i
], &nir
[i
], 1,
2990 keys
+ i
, infos
+ i
, keep_executable_info
,
2991 keep_statistic_info
, &binaries
[i
]);
2993 radv_stop_feedback(stage_feedbacks
[i
], false);
2997 if (!keep_executable_info
&& !keep_statistic_info
) {
2998 radv_pipeline_cache_insert_shaders(device
, cache
, hash
, pipeline
->shaders
,
3002 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
3005 ralloc_free(nir
[i
]);
3007 if (radv_can_dump_shader_stats(device
, modules
[i
]))
3008 radv_shader_dump_stats(device
,
3009 pipeline
->shaders
[i
],
3015 ralloc_free(fs_m
.nir
);
3017 radv_stop_feedback(pipeline_feedback
, false);
3022 radv_pipeline_stage_to_user_data_0(struct radv_pipeline
*pipeline
,
3023 gl_shader_stage stage
, enum chip_class chip_class
)
3025 bool has_gs
= radv_pipeline_has_gs(pipeline
);
3026 bool has_tess
= radv_pipeline_has_tess(pipeline
);
3027 bool has_ngg
= radv_pipeline_has_ngg(pipeline
);
3030 case MESA_SHADER_FRAGMENT
:
3031 return R_00B030_SPI_SHADER_USER_DATA_PS_0
;
3032 case MESA_SHADER_VERTEX
:
3034 if (chip_class
>= GFX10
) {
3035 return R_00B430_SPI_SHADER_USER_DATA_HS_0
;
3036 } else if (chip_class
== GFX9
) {
3037 return R_00B430_SPI_SHADER_USER_DATA_LS_0
;
3039 return R_00B530_SPI_SHADER_USER_DATA_LS_0
;
3045 if (chip_class
>= GFX10
) {
3046 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3048 return R_00B330_SPI_SHADER_USER_DATA_ES_0
;
3053 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3055 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3056 case MESA_SHADER_GEOMETRY
:
3057 return chip_class
== GFX9
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
3058 R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3059 case MESA_SHADER_COMPUTE
:
3060 return R_00B900_COMPUTE_USER_DATA_0
;
3061 case MESA_SHADER_TESS_CTRL
:
3062 return chip_class
== GFX9
? R_00B430_SPI_SHADER_USER_DATA_LS_0
:
3063 R_00B430_SPI_SHADER_USER_DATA_HS_0
;
3064 case MESA_SHADER_TESS_EVAL
:
3066 return chip_class
>= GFX10
? R_00B230_SPI_SHADER_USER_DATA_GS_0
:
3067 R_00B330_SPI_SHADER_USER_DATA_ES_0
;
3068 } else if (has_ngg
) {
3069 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3071 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3074 unreachable("unknown shader");
3078 struct radv_bin_size_entry
{
3084 radv_gfx9_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3086 static const struct radv_bin_size_entry color_size_table
[][3][9] = {
3090 /* One shader engine */
3096 { UINT_MAX
, { 0, 0}},
3099 /* Two shader engines */
3105 { UINT_MAX
, { 0, 0}},
3108 /* Four shader engines */
3113 { UINT_MAX
, { 0, 0}},
3119 /* One shader engine */
3125 { UINT_MAX
, { 0, 0}},
3128 /* Two shader engines */
3134 { UINT_MAX
, { 0, 0}},
3137 /* Four shader engines */
3144 { UINT_MAX
, { 0, 0}},
3150 /* One shader engine */
3157 { UINT_MAX
, { 0, 0}},
3160 /* Two shader engines */
3168 { UINT_MAX
, { 0, 0}},
3171 /* Four shader engines */
3179 { UINT_MAX
, { 0, 0}},
3183 static const struct radv_bin_size_entry ds_size_table
[][3][9] = {
3187 // One shader engine
3194 { UINT_MAX
, { 0, 0}},
3197 // Two shader engines
3205 { UINT_MAX
, { 0, 0}},
3208 // Four shader engines
3216 { UINT_MAX
, { 0, 0}},
3222 // One shader engine
3230 { UINT_MAX
, { 0, 0}},
3233 // Two shader engines
3242 { UINT_MAX
, { 0, 0}},
3245 // Four shader engines
3254 { UINT_MAX
, { 0, 0}},
3260 // One shader engine
3268 { UINT_MAX
, { 0, 0}},
3271 // Two shader engines
3280 { UINT_MAX
, { 0, 0}},
3283 // Four shader engines
3291 { UINT_MAX
, { 0, 0}},
3296 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3297 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3298 VkExtent2D extent
= {512, 512};
3300 unsigned log_num_rb_per_se
=
3301 util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.num_render_backends
/
3302 pipeline
->device
->physical_device
->rad_info
.max_se
);
3303 unsigned log_num_se
= util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.max_se
);
3305 unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3306 unsigned ps_iter_samples
= 1u << G_028804_PS_ITER_SAMPLES(pipeline
->graphics
.ms
.db_eqaa
);
3307 unsigned effective_samples
= total_samples
;
3308 unsigned color_bytes_per_pixel
= 0;
3310 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3311 radv_pipeline_get_color_blend_state(pCreateInfo
);
3313 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3314 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3317 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3320 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3321 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3324 /* MSAA images typically don't use all samples all the time. */
3325 if (effective_samples
>= 2 && ps_iter_samples
<= 1)
3326 effective_samples
= 2;
3327 color_bytes_per_pixel
*= effective_samples
;
3330 const struct radv_bin_size_entry
*color_entry
= color_size_table
[log_num_rb_per_se
][log_num_se
];
3331 while(color_entry
[1].bpp
<= color_bytes_per_pixel
)
3334 extent
= color_entry
->extent
;
3336 if (subpass
->depth_stencil_attachment
) {
3337 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3339 /* Coefficients taken from AMDVLK */
3340 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3341 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3342 unsigned ds_bytes_per_pixel
= 4 * (depth_coeff
+ stencil_coeff
) * total_samples
;
3344 const struct radv_bin_size_entry
*ds_entry
= ds_size_table
[log_num_rb_per_se
][log_num_se
];
3345 while(ds_entry
[1].bpp
<= ds_bytes_per_pixel
)
3348 if (ds_entry
->extent
.width
* ds_entry
->extent
.height
< extent
.width
* extent
.height
)
3349 extent
= ds_entry
->extent
;
3356 radv_gfx10_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3358 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3359 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3360 VkExtent2D extent
= {512, 512};
3362 const unsigned db_tag_size
= 64;
3363 const unsigned db_tag_count
= 312;
3364 const unsigned color_tag_size
= 1024;
3365 const unsigned color_tag_count
= 31;
3366 const unsigned fmask_tag_size
= 256;
3367 const unsigned fmask_tag_count
= 44;
3369 const unsigned rb_count
= pipeline
->device
->physical_device
->rad_info
.num_render_backends
;
3370 const unsigned pipe_count
= MAX2(rb_count
, pipeline
->device
->physical_device
->rad_info
.num_sdp_interfaces
);
3372 const unsigned db_tag_part
= (db_tag_count
* rb_count
/ pipe_count
) * db_tag_size
* pipe_count
;
3373 const unsigned color_tag_part
= (color_tag_count
* rb_count
/ pipe_count
) * color_tag_size
* pipe_count
;
3374 const unsigned fmask_tag_part
= (fmask_tag_count
* rb_count
/ pipe_count
) * fmask_tag_size
* pipe_count
;
3376 const unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3377 const unsigned samples_log
= util_logbase2_ceil(total_samples
);
3379 unsigned color_bytes_per_pixel
= 0;
3380 unsigned fmask_bytes_per_pixel
= 0;
3382 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3383 radv_pipeline_get_color_blend_state(pCreateInfo
);
3385 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3386 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3389 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3392 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3393 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3395 if (total_samples
> 1) {
3396 assert(samples_log
<= 3);
3397 const unsigned fmask_array
[] = {0, 1, 1, 4};
3398 fmask_bytes_per_pixel
+= fmask_array
[samples_log
];
3402 color_bytes_per_pixel
*= total_samples
;
3404 color_bytes_per_pixel
= MAX2(color_bytes_per_pixel
, 1);
3406 const unsigned color_pixel_count_log
= util_logbase2(color_tag_part
/ color_bytes_per_pixel
);
3407 extent
.width
= 1ull << ((color_pixel_count_log
+ 1) / 2);
3408 extent
.height
= 1ull << (color_pixel_count_log
/ 2);
3410 if (fmask_bytes_per_pixel
) {
3411 const unsigned fmask_pixel_count_log
= util_logbase2(fmask_tag_part
/ fmask_bytes_per_pixel
);
3413 const VkExtent2D fmask_extent
= (VkExtent2D
){
3414 .width
= 1ull << ((fmask_pixel_count_log
+ 1) / 2),
3415 .height
= 1ull << (color_pixel_count_log
/ 2)
3418 if (fmask_extent
.width
* fmask_extent
.height
< extent
.width
* extent
.height
)
3419 extent
= fmask_extent
;
3422 if (subpass
->depth_stencil_attachment
) {
3423 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3425 /* Coefficients taken from AMDVLK */
3426 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3427 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3428 unsigned db_bytes_per_pixel
= (depth_coeff
+ stencil_coeff
) * total_samples
;
3430 const unsigned db_pixel_count_log
= util_logbase2(db_tag_part
/ db_bytes_per_pixel
);
3432 const VkExtent2D db_extent
= (VkExtent2D
){
3433 .width
= 1ull << ((db_pixel_count_log
+ 1) / 2),
3434 .height
= 1ull << (color_pixel_count_log
/ 2)
3437 if (db_extent
.width
* db_extent
.height
< extent
.width
* extent
.height
)
3441 extent
.width
= MAX2(extent
.width
, 128);
3442 extent
.height
= MAX2(extent
.width
, 64);
3448 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3449 struct radv_pipeline
*pipeline
,
3450 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3452 uint32_t pa_sc_binner_cntl_0
=
3453 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC
) |
3454 S_028C44_DISABLE_START_OF_PRIM(1);
3455 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3457 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3458 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3459 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3460 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3461 radv_pipeline_get_color_blend_state(pCreateInfo
);
3462 unsigned min_bytes_per_pixel
= 0;
3465 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3466 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3469 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3472 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3473 unsigned bytes
= vk_format_get_blocksize(format
);
3474 if (!min_bytes_per_pixel
|| bytes
< min_bytes_per_pixel
)
3475 min_bytes_per_pixel
= bytes
;
3479 pa_sc_binner_cntl_0
=
3480 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC
) |
3481 S_028C44_BIN_SIZE_X(0) |
3482 S_028C44_BIN_SIZE_Y(0) |
3483 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3484 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel
<= 4 ? 2 : 1) | /* 128 or 64 */
3485 S_028C44_DISABLE_START_OF_PRIM(1);
3488 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3489 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3492 struct radv_binning_settings
3493 radv_get_binning_settings(const struct radv_physical_device
*pdev
)
3495 struct radv_binning_settings settings
;
3496 if (pdev
->rad_info
.has_dedicated_vram
) {
3497 if (pdev
->rad_info
.num_render_backends
> 4) {
3498 settings
.context_states_per_bin
= 1;
3499 settings
.persistent_states_per_bin
= 1;
3501 settings
.context_states_per_bin
= 3;
3502 settings
.persistent_states_per_bin
= 8;
3504 settings
.fpovs_per_batch
= 63;
3506 /* The context states are affected by the scissor bug. */
3507 settings
.context_states_per_bin
= 6;
3508 /* 32 causes hangs for RAVEN. */
3509 settings
.persistent_states_per_bin
= 16;
3510 settings
.fpovs_per_batch
= 63;
3513 if (pdev
->rad_info
.has_gfx9_scissor_bug
)
3514 settings
.context_states_per_bin
= 1;
3520 radv_pipeline_generate_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3521 struct radv_pipeline
*pipeline
,
3522 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3523 const struct radv_blend_state
*blend
)
3525 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
3528 VkExtent2D bin_size
;
3529 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3530 bin_size
= radv_gfx10_compute_bin_size(pipeline
, pCreateInfo
);
3531 } else if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3532 bin_size
= radv_gfx9_compute_bin_size(pipeline
, pCreateInfo
);
3534 unreachable("Unhandled generation for binning bin size calculation");
3536 if (pipeline
->device
->pbb_allowed
&& bin_size
.width
&& bin_size
.height
) {
3537 struct radv_binning_settings settings
=
3538 radv_get_binning_settings(pipeline
->device
->physical_device
);
3540 bool disable_start_of_prim
= true;
3541 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3543 const struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3545 if (pipeline
->device
->dfsm_allowed
&& ps
&&
3546 !ps
->info
.ps
.can_discard
&&
3547 !ps
->info
.ps
.writes_memory
&&
3548 blend
->cb_target_enabled_4bit
) {
3549 db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_AUTO
);
3550 disable_start_of_prim
= (blend
->blend_enable_4bit
& blend
->cb_target_enabled_4bit
) != 0;
3553 const uint32_t pa_sc_binner_cntl_0
=
3554 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED
) |
3555 S_028C44_BIN_SIZE_X(bin_size
.width
== 16) |
3556 S_028C44_BIN_SIZE_Y(bin_size
.height
== 16) |
3557 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size
.width
, 32)) - 5) |
3558 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size
.height
, 32)) - 5) |
3559 S_028C44_CONTEXT_STATES_PER_BIN(settings
.context_states_per_bin
- 1) |
3560 S_028C44_PERSISTENT_STATES_PER_BIN(settings
.persistent_states_per_bin
- 1) |
3561 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim
) |
3562 S_028C44_FPOVS_PER_BATCH(settings
.fpovs_per_batch
) |
3563 S_028C44_OPTIMAL_BIN_SELECTION(1);
3565 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3566 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3568 radv_pipeline_generate_disabled_binning_state(ctx_cs
, pipeline
, pCreateInfo
);
3573 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf
*ctx_cs
,
3574 struct radv_pipeline
*pipeline
,
3575 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3576 const struct radv_graphics_pipeline_create_info
*extra
)
3578 const VkPipelineDepthStencilStateCreateInfo
*vkds
= radv_pipeline_get_depth_stencil_state(pCreateInfo
);
3579 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3580 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3581 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3582 struct radv_render_pass_attachment
*attachment
= NULL
;
3583 uint32_t db_depth_control
= 0;
3584 uint32_t db_render_control
= 0, db_render_override2
= 0;
3585 uint32_t db_render_override
= 0;
3587 if (subpass
->depth_stencil_attachment
)
3588 attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3590 bool has_depth_attachment
= attachment
&& vk_format_is_depth(attachment
->format
);
3591 bool has_stencil_attachment
= attachment
&& vk_format_is_stencil(attachment
->format
);
3593 if (vkds
&& has_depth_attachment
) {
3594 db_depth_control
= S_028800_Z_ENABLE(vkds
->depthTestEnable
? 1 : 0) |
3595 S_028800_Z_WRITE_ENABLE(vkds
->depthWriteEnable
? 1 : 0) |
3596 S_028800_ZFUNC(vkds
->depthCompareOp
) |
3597 S_028800_DEPTH_BOUNDS_ENABLE(vkds
->depthBoundsTestEnable
? 1 : 0);
3599 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3600 db_render_override2
|= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment
->samples
> 2);
3602 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
)
3603 db_render_override2
|= S_028010_CENTROID_COMPUTATION_MODE_GFX103(2);
3606 if (has_stencil_attachment
&& vkds
&& vkds
->stencilTestEnable
) {
3607 db_depth_control
|= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3608 db_depth_control
|= S_028800_STENCILFUNC(vkds
->front
.compareOp
);
3610 db_depth_control
|= S_028800_STENCILFUNC_BF(vkds
->back
.compareOp
);
3613 if (attachment
&& extra
) {
3614 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(extra
->db_depth_clear
);
3615 db_render_control
|= S_028000_STENCIL_CLEAR_ENABLE(extra
->db_stencil_clear
);
3617 db_render_control
|= S_028000_RESUMMARIZE_ENABLE(extra
->resummarize_enable
);
3618 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(extra
->depth_compress_disable
);
3619 db_render_control
|= S_028000_STENCIL_COMPRESS_DISABLE(extra
->stencil_compress_disable
);
3620 db_render_override2
|= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra
->db_depth_disable_expclear
);
3621 db_render_override2
|= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra
->db_stencil_disable_expclear
);
3624 db_render_override
|= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
3625 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
3627 if (!pCreateInfo
->pRasterizationState
->depthClampEnable
&&
3628 ps
->info
.ps
.writes_z
) {
3629 /* From VK_EXT_depth_range_unrestricted spec:
3631 * "The behavior described in Primitive Clipping still applies.
3632 * If depth clamping is disabled the depth values are still
3633 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3634 * depth clamping is enabled the above equation is ignored and
3635 * the depth values are instead clamped to the VkViewport
3636 * minDepth and maxDepth values, which in the case of this
3637 * extension can be outside of the 0.0 to 1.0 range."
3639 db_render_override
|= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3642 radeon_set_context_reg(ctx_cs
, R_028000_DB_RENDER_CONTROL
, db_render_control
);
3643 radeon_set_context_reg(ctx_cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
3644 radeon_set_context_reg(ctx_cs
, R_028010_DB_RENDER_OVERRIDE2
, db_render_override2
);
3646 pipeline
->graphics
.db_depth_control
= db_depth_control
;
3650 radv_pipeline_generate_blend_state(struct radeon_cmdbuf
*ctx_cs
,
3651 struct radv_pipeline
*pipeline
,
3652 const struct radv_blend_state
*blend
)
3654 radeon_set_context_reg_seq(ctx_cs
, R_028780_CB_BLEND0_CONTROL
, 8);
3655 radeon_emit_array(ctx_cs
, blend
->cb_blend_control
,
3657 radeon_set_context_reg(ctx_cs
, R_028808_CB_COLOR_CONTROL
, blend
->cb_color_control
);
3658 radeon_set_context_reg(ctx_cs
, R_028B70_DB_ALPHA_TO_MASK
, blend
->db_alpha_to_mask
);
3660 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
3662 radeon_set_context_reg_seq(ctx_cs
, R_028760_SX_MRT0_BLEND_OPT
, 8);
3663 radeon_emit_array(ctx_cs
, blend
->sx_mrt_blend_opt
, 8);
3666 radeon_set_context_reg(ctx_cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
3668 radeon_set_context_reg(ctx_cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
3669 radeon_set_context_reg(ctx_cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
3671 pipeline
->graphics
.col_format
= blend
->spi_shader_col_format
;
3672 pipeline
->graphics
.cb_target_mask
= blend
->cb_target_mask
;
3675 static const VkConservativeRasterizationModeEXT
3676 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo
*pCreateInfo
)
3678 const VkPipelineRasterizationConservativeStateCreateInfoEXT
*conservative_raster
=
3679 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT
);
3681 if (!conservative_raster
)
3682 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
;
3683 return conservative_raster
->conservativeRasterizationMode
;
3687 radv_pipeline_generate_raster_state(struct radeon_cmdbuf
*ctx_cs
,
3688 struct radv_pipeline
*pipeline
,
3689 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3691 const VkPipelineRasterizationStateCreateInfo
*vkraster
= pCreateInfo
->pRasterizationState
;
3692 const VkConservativeRasterizationModeEXT mode
=
3693 radv_get_conservative_raster_mode(vkraster
);
3694 uint32_t pa_sc_conservative_rast
= S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3695 bool depth_clip_disable
= vkraster
->depthClampEnable
;
3697 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*depth_clip_state
=
3698 vk_find_struct_const(vkraster
->pNext
, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
3699 if (depth_clip_state
) {
3700 depth_clip_disable
= !depth_clip_state
->depthClipEnable
;
3703 radeon_set_context_reg(ctx_cs
, R_028810_PA_CL_CLIP_CNTL
,
3704 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3705 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable
? 1 : 0) |
3706 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable
? 1 : 0) |
3707 S_028810_DX_RASTERIZATION_KILL(vkraster
->rasterizerDiscardEnable
? 1 : 0) |
3708 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3710 pipeline
->graphics
.pa_su_sc_mode_cntl
=
3711 S_028814_FACE(vkraster
->frontFace
) |
3712 S_028814_CULL_FRONT(!!(vkraster
->cullMode
& VK_CULL_MODE_FRONT_BIT
)) |
3713 S_028814_CULL_BACK(!!(vkraster
->cullMode
& VK_CULL_MODE_BACK_BIT
)) |
3714 S_028814_POLY_MODE(vkraster
->polygonMode
!= VK_POLYGON_MODE_FILL
) |
3715 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3716 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3717 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3718 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3719 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster
->depthBiasEnable
? 1 : 0);
3721 radeon_set_context_reg(ctx_cs
, R_028BDC_PA_SC_LINE_CNTL
,
3722 S_028BDC_DX10_DIAMOND_TEST_ENA(1));
3724 /* Conservative rasterization. */
3725 if (mode
!= VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
) {
3726 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3728 ms
->pa_sc_aa_config
|= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3729 ms
->db_eqaa
|= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3730 S_028804_OVERRASTERIZATION_AMOUNT(4);
3732 pa_sc_conservative_rast
= S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3733 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3734 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3736 if (mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT
) {
3737 pa_sc_conservative_rast
|=
3738 S_028C4C_OVER_RAST_ENABLE(1) |
3739 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3740 S_028C4C_UNDER_RAST_ENABLE(0) |
3741 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3742 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3744 assert(mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT
);
3745 pa_sc_conservative_rast
|=
3746 S_028C4C_OVER_RAST_ENABLE(0) |
3747 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3748 S_028C4C_UNDER_RAST_ENABLE(1) |
3749 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3750 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3754 radeon_set_context_reg(ctx_cs
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
3755 pa_sc_conservative_rast
);
3760 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf
*ctx_cs
,
3761 struct radv_pipeline
*pipeline
)
3763 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3765 radeon_set_context_reg_seq(ctx_cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
3766 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[0]);
3767 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[1]);
3769 radeon_set_context_reg(ctx_cs
, R_028804_DB_EQAA
, ms
->db_eqaa
);
3770 radeon_set_context_reg(ctx_cs
, R_028A48_PA_SC_MODE_CNTL_0
, ms
->pa_sc_mode_cntl_0
);
3771 radeon_set_context_reg(ctx_cs
, R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
3772 radeon_set_context_reg(ctx_cs
, R_028BE0_PA_SC_AA_CONFIG
, ms
->pa_sc_aa_config
);
3774 /* The exclusion bits can be set to improve rasterization efficiency
3775 * if no sample lies on the pixel boundary (-8 sample offset). It's
3776 * currently always TRUE because the driver doesn't support 16 samples.
3778 bool exclusion
= pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
3779 radeon_set_context_reg(ctx_cs
, R_02882C_PA_SU_PRIM_FILTER_CNTL
,
3780 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) |
3781 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3783 /* GFX9: Flush DFSM when the AA mode changes. */
3784 if (pipeline
->device
->dfsm_allowed
) {
3785 radeon_emit(ctx_cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3786 radeon_emit(ctx_cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3791 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf
*ctx_cs
,
3792 struct radv_pipeline
*pipeline
)
3794 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3795 const struct radv_shader_variant
*vs
=
3796 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] ?
3797 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] :
3798 pipeline
->shaders
[MESA_SHADER_VERTEX
];
3799 unsigned vgt_primitiveid_en
= 0;
3800 uint32_t vgt_gs_mode
= 0;
3802 if (radv_pipeline_has_ngg(pipeline
))
3805 if (radv_pipeline_has_gs(pipeline
)) {
3806 const struct radv_shader_variant
*gs
=
3807 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3809 vgt_gs_mode
= ac_vgt_gs_mode(gs
->info
.gs
.vertices_out
,
3810 pipeline
->device
->physical_device
->rad_info
.chip_class
);
3811 } else if (outinfo
->export_prim_id
|| vs
->info
.uses_prim_id
) {
3812 vgt_gs_mode
= S_028A40_MODE(V_028A40_GS_SCENARIO_A
);
3813 vgt_primitiveid_en
|= S_028A84_PRIMITIVEID_EN(1);
3816 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
, vgt_primitiveid_en
);
3817 radeon_set_context_reg(ctx_cs
, R_028A40_VGT_GS_MODE
, vgt_gs_mode
);
3821 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf
*ctx_cs
,
3822 struct radeon_cmdbuf
*cs
,
3823 struct radv_pipeline
*pipeline
,
3824 struct radv_shader_variant
*shader
)
3826 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3828 radeon_set_sh_reg_seq(cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
3829 radeon_emit(cs
, va
>> 8);
3830 radeon_emit(cs
, S_00B124_MEM_BASE(va
>> 40));
3831 radeon_emit(cs
, shader
->config
.rsrc1
);
3832 radeon_emit(cs
, shader
->config
.rsrc2
);
3834 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3835 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3836 clip_dist_mask
= outinfo
->clip_dist_mask
;
3837 cull_dist_mask
= outinfo
->cull_dist_mask
;
3838 total_mask
= clip_dist_mask
| cull_dist_mask
;
3839 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3840 outinfo
->writes_layer
||
3841 outinfo
->writes_viewport_index
;
3842 unsigned spi_vs_out_config
, nparams
;
3844 /* VS is required to export at least one param. */
3845 nparams
= MAX2(outinfo
->param_exports
, 1);
3846 spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
3848 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3849 spi_vs_out_config
|= S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0);
3852 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
, spi_vs_out_config
);
3854 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3855 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3856 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3857 V_02870C_SPI_SHADER_4COMP
:
3858 V_02870C_SPI_SHADER_NONE
) |
3859 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3860 V_02870C_SPI_SHADER_4COMP
:
3861 V_02870C_SPI_SHADER_NONE
) |
3862 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3863 V_02870C_SPI_SHADER_4COMP
:
3864 V_02870C_SPI_SHADER_NONE
));
3866 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3867 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3868 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3869 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3870 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3871 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3872 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3873 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3874 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
) |
3875 cull_dist_mask
<< 8 |
3878 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
3879 radeon_set_context_reg(ctx_cs
, R_028AB4_VGT_REUSE_OFF
,
3880 outinfo
->writes_viewport_index
);
3884 radv_pipeline_generate_hw_es(struct radeon_cmdbuf
*cs
,
3885 struct radv_pipeline
*pipeline
,
3886 struct radv_shader_variant
*shader
)
3888 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3890 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
3891 radeon_emit(cs
, va
>> 8);
3892 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3893 radeon_emit(cs
, shader
->config
.rsrc1
);
3894 radeon_emit(cs
, shader
->config
.rsrc2
);
3898 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf
*cs
,
3899 struct radv_pipeline
*pipeline
,
3900 struct radv_shader_variant
*shader
,
3901 const struct radv_tessellation_state
*tess
)
3903 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3904 uint32_t rsrc2
= shader
->config
.rsrc2
;
3906 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
3907 radeon_emit(cs
, va
>> 8);
3908 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
3910 rsrc2
|= S_00B52C_LDS_SIZE(tess
->num_lds_blocks
);
3911 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX7
&&
3912 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
3913 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
3915 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
3916 radeon_emit(cs
, shader
->config
.rsrc1
);
3917 radeon_emit(cs
, rsrc2
);
3921 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf
*ctx_cs
,
3922 struct radeon_cmdbuf
*cs
,
3923 struct radv_pipeline
*pipeline
,
3924 struct radv_shader_variant
*shader
)
3926 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3927 gl_shader_stage es_type
=
3928 radv_pipeline_has_tess(pipeline
) ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
3929 struct radv_shader_variant
*es
=
3930 es_type
== MESA_SHADER_TESS_EVAL
? pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] : pipeline
->shaders
[MESA_SHADER_VERTEX
];
3931 const struct gfx10_ngg_info
*ngg_state
= &shader
->info
.ngg_info
;
3933 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
3934 radeon_emit(cs
, va
>> 8);
3935 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3936 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
3937 radeon_emit(cs
, shader
->config
.rsrc1
);
3938 radeon_emit(cs
, shader
->config
.rsrc2
);
3940 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3941 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3942 clip_dist_mask
= outinfo
->clip_dist_mask
;
3943 cull_dist_mask
= outinfo
->cull_dist_mask
;
3944 total_mask
= clip_dist_mask
| cull_dist_mask
;
3945 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3946 outinfo
->writes_layer
||
3947 outinfo
->writes_viewport_index
;
3948 bool es_enable_prim_id
= outinfo
->export_prim_id
||
3949 (es
&& es
->info
.uses_prim_id
);
3950 bool break_wave_at_eoi
= false;
3954 if (es_type
== MESA_SHADER_TESS_EVAL
) {
3955 struct radv_shader_variant
*gs
=
3956 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3958 if (es_enable_prim_id
|| (gs
&& gs
->info
.uses_prim_id
))
3959 break_wave_at_eoi
= true;
3962 nparams
= MAX2(outinfo
->param_exports
, 1);
3963 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
3964 S_0286C4_VS_EXPORT_COUNT(nparams
- 1) |
3965 S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0));
3967 radeon_set_context_reg(ctx_cs
, R_028708_SPI_SHADER_IDX_FORMAT
,
3968 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP
));
3969 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3970 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3971 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3972 V_02870C_SPI_SHADER_4COMP
:
3973 V_02870C_SPI_SHADER_NONE
) |
3974 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3975 V_02870C_SPI_SHADER_4COMP
:
3976 V_02870C_SPI_SHADER_NONE
) |
3977 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3978 V_02870C_SPI_SHADER_4COMP
:
3979 V_02870C_SPI_SHADER_NONE
));
3981 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3982 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3983 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3984 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3985 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3986 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3987 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3988 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3989 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
) |
3990 cull_dist_mask
<< 8 |
3993 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
,
3994 S_028A84_PRIMITIVEID_EN(es_enable_prim_id
) |
3995 S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo
->export_prim_id
));
3997 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
3998 ngg_state
->vgt_esgs_ring_itemsize
);
4000 /* NGG specific registers. */
4001 struct radv_shader_variant
*gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4002 uint32_t gs_num_invocations
= gs
? gs
->info
.gs
.invocations
: 1;
4004 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4005 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state
->hw_max_esverts
) |
4006 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state
->max_gsprims
) |
4007 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state
->max_gsprims
* gs_num_invocations
));
4008 radeon_set_context_reg(ctx_cs
, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP
,
4009 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state
->max_out_verts
));
4010 radeon_set_context_reg(ctx_cs
, R_028B4C_GE_NGG_SUBGRP_CNTL
,
4011 S_028B4C_PRIM_AMP_FACTOR(ngg_state
->prim_amp_factor
) |
4012 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
4013 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
4014 S_028B90_CNT(gs_num_invocations
) |
4015 S_028B90_ENABLE(gs_num_invocations
> 1) |
4016 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state
->max_vert_out_per_gs_instance
));
4018 /* User edge flags are set by the pos exports. If user edge flags are
4019 * not used, we must use hw-generated edge flags and pass them via
4020 * the prim export to prevent drawing lines on internal edges of
4021 * decomposed primitives (such as quads) with polygon mode = lines.
4023 * TODO: We should combine hw-generated edge flags with user edge
4024 * flags in the shader.
4026 radeon_set_context_reg(ctx_cs
, R_028838_PA_CL_NGG_CNTL
,
4027 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline
) &&
4028 !radv_pipeline_has_gs(pipeline
)) |
4029 /* Reuse for NGG. */
4030 S_028838_VERTEX_REUSE_DEPTH_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
? 30 : 0));
4032 ge_cntl
= S_03096C_PRIM_GRP_SIZE(ngg_state
->max_gsprims
) |
4033 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
4034 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
);
4036 /* Bug workaround for a possible hang with non-tessellation cases.
4037 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
4039 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
4041 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX10
&&
4042 !radv_pipeline_has_tess(pipeline
) &&
4043 ngg_state
->hw_max_esverts
!= 256) {
4044 ge_cntl
&= C_03096C_VERT_GRP_SIZE
;
4046 if (ngg_state
->hw_max_esverts
> 5) {
4047 ge_cntl
|= S_03096C_VERT_GRP_SIZE(ngg_state
->hw_max_esverts
- 5);
4051 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
, ge_cntl
);
4055 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf
*cs
,
4056 struct radv_pipeline
*pipeline
,
4057 struct radv_shader_variant
*shader
,
4058 const struct radv_tessellation_state
*tess
)
4060 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
4062 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4063 unsigned hs_rsrc2
= shader
->config
.rsrc2
;
4065 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4066 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX10(tess
->num_lds_blocks
);
4068 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX9(tess
->num_lds_blocks
);
4071 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4072 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
4073 radeon_emit(cs
, va
>> 8);
4074 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
4076 radeon_set_sh_reg_seq(cs
, R_00B410_SPI_SHADER_PGM_LO_LS
, 2);
4077 radeon_emit(cs
, va
>> 8);
4078 radeon_emit(cs
, S_00B414_MEM_BASE(va
>> 40));
4081 radeon_set_sh_reg_seq(cs
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
, 2);
4082 radeon_emit(cs
, shader
->config
.rsrc1
);
4083 radeon_emit(cs
, hs_rsrc2
);
4085 radeon_set_sh_reg_seq(cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
4086 radeon_emit(cs
, va
>> 8);
4087 radeon_emit(cs
, S_00B424_MEM_BASE(va
>> 40));
4088 radeon_emit(cs
, shader
->config
.rsrc1
);
4089 radeon_emit(cs
, shader
->config
.rsrc2
);
4094 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf
*ctx_cs
,
4095 struct radeon_cmdbuf
*cs
,
4096 struct radv_pipeline
*pipeline
,
4097 const struct radv_tessellation_state
*tess
)
4099 struct radv_shader_variant
*vs
;
4101 /* Skip shaders merged into HS/GS */
4102 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
4106 if (vs
->info
.vs
.as_ls
)
4107 radv_pipeline_generate_hw_ls(cs
, pipeline
, vs
, tess
);
4108 else if (vs
->info
.vs
.as_es
)
4109 radv_pipeline_generate_hw_es(cs
, pipeline
, vs
);
4110 else if (vs
->info
.is_ngg
)
4111 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, vs
);
4113 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, vs
);
4117 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf
*ctx_cs
,
4118 struct radeon_cmdbuf
*cs
,
4119 struct radv_pipeline
*pipeline
,
4120 const struct radv_tessellation_state
*tess
)
4122 if (!radv_pipeline_has_tess(pipeline
))
4125 struct radv_shader_variant
*tes
, *tcs
;
4127 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
4128 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
4131 if (tes
->info
.is_ngg
) {
4132 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, tes
);
4133 } else if (tes
->info
.tes
.as_es
)
4134 radv_pipeline_generate_hw_es(cs
, pipeline
, tes
);
4136 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, tes
);
4139 radv_pipeline_generate_hw_hs(cs
, pipeline
, tcs
, tess
);
4141 radeon_set_context_reg(ctx_cs
, R_028B6C_VGT_TF_PARAM
,
4144 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
)
4145 radeon_set_context_reg_idx(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
4146 tess
->ls_hs_config
);
4148 radeon_set_context_reg(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
,
4149 tess
->ls_hs_config
);
4151 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
4152 !radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
4153 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4154 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4155 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4156 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4161 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf
*ctx_cs
,
4162 struct radeon_cmdbuf
*cs
,
4163 struct radv_pipeline
*pipeline
,
4164 struct radv_shader_variant
*gs
)
4166 const struct gfx9_gs_info
*gs_state
= &gs
->info
.gs_ring_info
;
4167 unsigned gs_max_out_vertices
;
4168 uint8_t *num_components
;
4173 gs_max_out_vertices
= gs
->info
.gs
.vertices_out
;
4174 max_stream
= gs
->info
.gs
.max_stream
;
4175 num_components
= gs
->info
.gs
.num_stream_output_components
;
4177 offset
= num_components
[0] * gs_max_out_vertices
;
4179 radeon_set_context_reg_seq(ctx_cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
4180 radeon_emit(ctx_cs
, offset
);
4181 if (max_stream
>= 1)
4182 offset
+= num_components
[1] * gs_max_out_vertices
;
4183 radeon_emit(ctx_cs
, offset
);
4184 if (max_stream
>= 2)
4185 offset
+= num_components
[2] * gs_max_out_vertices
;
4186 radeon_emit(ctx_cs
, offset
);
4187 if (max_stream
>= 3)
4188 offset
+= num_components
[3] * gs_max_out_vertices
;
4189 radeon_set_context_reg(ctx_cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
4191 radeon_set_context_reg_seq(ctx_cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
4192 radeon_emit(ctx_cs
, num_components
[0]);
4193 radeon_emit(ctx_cs
, (max_stream
>= 1) ? num_components
[1] : 0);
4194 radeon_emit(ctx_cs
, (max_stream
>= 2) ? num_components
[2] : 0);
4195 radeon_emit(ctx_cs
, (max_stream
>= 3) ? num_components
[3] : 0);
4197 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
4198 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
4199 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
4200 S_028B90_ENABLE(gs_num_invocations
> 0));
4202 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
4203 gs_state
->vgt_esgs_ring_itemsize
);
4205 va
= radv_buffer_get_va(gs
->bo
) + gs
->bo_offset
;
4207 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4208 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4209 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
4210 radeon_emit(cs
, va
>> 8);
4211 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
4213 radeon_set_sh_reg_seq(cs
, R_00B210_SPI_SHADER_PGM_LO_ES
, 2);
4214 radeon_emit(cs
, va
>> 8);
4215 radeon_emit(cs
, S_00B214_MEM_BASE(va
>> 40));
4218 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
4219 radeon_emit(cs
, gs
->config
.rsrc1
);
4220 radeon_emit(cs
, gs
->config
.rsrc2
| S_00B22C_LDS_SIZE(gs_state
->lds_size
));
4222 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
, gs_state
->vgt_gs_onchip_cntl
);
4223 radeon_set_context_reg(ctx_cs
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
, gs_state
->vgt_gs_max_prims_per_subgroup
);
4225 radeon_set_sh_reg_seq(cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
4226 radeon_emit(cs
, va
>> 8);
4227 radeon_emit(cs
, S_00B224_MEM_BASE(va
>> 40));
4228 radeon_emit(cs
, gs
->config
.rsrc1
);
4229 radeon_emit(cs
, gs
->config
.rsrc2
);
4232 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, pipeline
->gs_copy_shader
);
4236 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf
*ctx_cs
,
4237 struct radeon_cmdbuf
*cs
,
4238 struct radv_pipeline
*pipeline
)
4240 struct radv_shader_variant
*gs
;
4242 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4246 if (gs
->info
.is_ngg
)
4247 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, gs
);
4249 radv_pipeline_generate_hw_gs(ctx_cs
, cs
, pipeline
, gs
);
4251 radeon_set_context_reg(ctx_cs
, R_028B38_VGT_GS_MAX_VERT_OUT
,
4252 gs
->info
.gs
.vertices_out
);
4255 static uint32_t offset_to_ps_input(uint32_t offset
, bool flat_shade
,
4256 bool explicit, bool float16
)
4258 uint32_t ps_input_cntl
;
4259 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
4260 ps_input_cntl
= S_028644_OFFSET(offset
);
4261 if (flat_shade
|| explicit)
4262 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
4264 /* Force parameter cache to be read in passthrough
4267 ps_input_cntl
|= S_028644_OFFSET(1 << 5);
4270 ps_input_cntl
|= S_028644_FP16_INTERP_MODE(1) |
4271 S_028644_ATTR0_VALID(1);
4274 /* The input is a DEFAULT_VAL constant. */
4275 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
4276 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
4277 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
4278 ps_input_cntl
= S_028644_OFFSET(0x20) |
4279 S_028644_DEFAULT_VAL(offset
);
4281 return ps_input_cntl
;
4285 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf
*ctx_cs
,
4286 struct radv_pipeline
*pipeline
)
4288 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4289 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
4290 uint32_t ps_input_cntl
[32];
4292 unsigned ps_offset
= 0;
4294 if (ps
->info
.ps
.prim_id_input
) {
4295 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
];
4296 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4297 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4302 if (ps
->info
.ps
.layer_input
||
4303 ps
->info
.needs_multiview_view_index
) {
4304 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
];
4305 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
4306 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4308 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false, false);
4312 if (ps
->info
.ps
.viewport_index_input
) {
4313 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VIEWPORT
];
4314 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
4315 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4317 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false, false);
4321 if (ps
->info
.ps
.has_pcoord
) {
4323 val
= S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4324 ps_input_cntl
[ps_offset
] = val
;
4328 if (ps
->info
.ps
.num_input_clips_culls
) {
4331 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST0
];
4332 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4333 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false, false);
4337 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST1
];
4338 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
&&
4339 ps
->info
.ps
.num_input_clips_culls
> 4) {
4340 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false, false);
4345 for (unsigned i
= 0; i
< 32 && (1u << i
) <= ps
->info
.ps
.input_mask
; ++i
) {
4350 if (!(ps
->info
.ps
.input_mask
& (1u << i
)))
4353 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VAR0
+ i
];
4354 if (vs_offset
== AC_EXP_PARAM_UNDEFINED
) {
4355 ps_input_cntl
[ps_offset
] = S_028644_OFFSET(0x20);
4360 flat_shade
= !!(ps
->info
.ps
.flat_shaded_mask
& (1u << ps_offset
));
4361 explicit = !!(ps
->info
.ps
.explicit_shaded_mask
& (1u << ps_offset
));
4362 float16
= !!(ps
->info
.ps
.float16_shaded_mask
& (1u << ps_offset
));
4364 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, flat_shade
, explicit, float16
);
4369 radeon_set_context_reg_seq(ctx_cs
, R_028644_SPI_PS_INPUT_CNTL_0
, ps_offset
);
4370 for (unsigned i
= 0; i
< ps_offset
; i
++) {
4371 radeon_emit(ctx_cs
, ps_input_cntl
[i
]);
4377 radv_compute_db_shader_control(const struct radv_device
*device
,
4378 const struct radv_pipeline
*pipeline
,
4379 const struct radv_shader_variant
*ps
)
4381 unsigned conservative_z_export
= V_02880C_EXPORT_ANY_Z
;
4383 if (ps
->info
.ps
.early_fragment_test
|| !ps
->info
.ps
.writes_memory
)
4384 z_order
= V_02880C_EARLY_Z_THEN_LATE_Z
;
4386 z_order
= V_02880C_LATE_Z
;
4388 if (ps
->info
.ps
.depth_layout
== FRAG_DEPTH_LAYOUT_GREATER
)
4389 conservative_z_export
= V_02880C_EXPORT_GREATER_THAN_Z
;
4390 else if (ps
->info
.ps
.depth_layout
== FRAG_DEPTH_LAYOUT_LESS
)
4391 conservative_z_export
= V_02880C_EXPORT_LESS_THAN_Z
;
4393 bool disable_rbplus
= device
->physical_device
->rad_info
.has_rbplus
&&
4394 !device
->physical_device
->rad_info
.rbplus_allowed
;
4396 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4397 * but this appears to break Project Cars (DXVK). See
4398 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4400 bool mask_export_enable
= ps
->info
.ps
.writes_sample_mask
;
4402 return S_02880C_Z_EXPORT_ENABLE(ps
->info
.ps
.writes_z
) |
4403 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps
->info
.ps
.writes_stencil
) |
4404 S_02880C_KILL_ENABLE(!!ps
->info
.ps
.can_discard
) |
4405 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable
) |
4406 S_02880C_CONSERVATIVE_Z_EXPORT(conservative_z_export
) |
4407 S_02880C_Z_ORDER(z_order
) |
4408 S_02880C_DEPTH_BEFORE_SHADER(ps
->info
.ps
.early_fragment_test
) |
4409 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps
->info
.ps
.post_depth_coverage
) |
4410 S_02880C_EXEC_ON_HIER_FAIL(ps
->info
.ps
.writes_memory
) |
4411 S_02880C_EXEC_ON_NOOP(ps
->info
.ps
.writes_memory
) |
4412 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus
);
4416 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf
*ctx_cs
,
4417 struct radeon_cmdbuf
*cs
,
4418 struct radv_pipeline
*pipeline
)
4420 struct radv_shader_variant
*ps
;
4422 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
4424 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4425 va
= radv_buffer_get_va(ps
->bo
) + ps
->bo_offset
;
4427 radeon_set_sh_reg_seq(cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
4428 radeon_emit(cs
, va
>> 8);
4429 radeon_emit(cs
, S_00B024_MEM_BASE(va
>> 40));
4430 radeon_emit(cs
, ps
->config
.rsrc1
);
4431 radeon_emit(cs
, ps
->config
.rsrc2
);
4433 radeon_set_context_reg(ctx_cs
, R_02880C_DB_SHADER_CONTROL
,
4434 radv_compute_db_shader_control(pipeline
->device
,
4437 radeon_set_context_reg(ctx_cs
, R_0286CC_SPI_PS_INPUT_ENA
,
4438 ps
->config
.spi_ps_input_ena
);
4440 radeon_set_context_reg(ctx_cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
4441 ps
->config
.spi_ps_input_addr
);
4443 radeon_set_context_reg(ctx_cs
, R_0286D8_SPI_PS_IN_CONTROL
,
4444 S_0286D8_NUM_INTERP(ps
->info
.ps
.num_interp
) |
4445 S_0286D8_PS_W32_EN(ps
->info
.wave_size
== 32));
4447 radeon_set_context_reg(ctx_cs
, R_0286E0_SPI_BARYC_CNTL
, pipeline
->graphics
.spi_baryc_cntl
);
4449 radeon_set_context_reg(ctx_cs
, R_028710_SPI_SHADER_Z_FORMAT
,
4450 ac_get_spi_shader_z_format(ps
->info
.ps
.writes_z
,
4451 ps
->info
.ps
.writes_stencil
,
4452 ps
->info
.ps
.writes_sample_mask
));
4454 if (pipeline
->device
->dfsm_allowed
) {
4455 /* optimise this? */
4456 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
4457 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
4462 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf
*ctx_cs
,
4463 struct radv_pipeline
*pipeline
)
4465 if (pipeline
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4466 pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
4469 unsigned vtx_reuse_depth
= 30;
4470 if (radv_pipeline_has_tess(pipeline
) &&
4471 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.tes
.spacing
== TESS_SPACING_FRACTIONAL_ODD
) {
4472 vtx_reuse_depth
= 14;
4474 radeon_set_context_reg(ctx_cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
4475 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth
));
4479 radv_pipeline_generate_vgt_shader_config(struct radeon_cmdbuf
*ctx_cs
,
4480 const struct radv_pipeline
*pipeline
)
4482 uint32_t stages
= 0;
4483 if (radv_pipeline_has_tess(pipeline
)) {
4484 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
4485 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4487 if (radv_pipeline_has_gs(pipeline
))
4488 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
4490 else if (radv_pipeline_has_ngg(pipeline
))
4491 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
4493 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
4494 } else if (radv_pipeline_has_gs(pipeline
)) {
4495 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
4497 } else if (radv_pipeline_has_ngg(pipeline
)) {
4498 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
4501 if (radv_pipeline_has_ngg(pipeline
)) {
4502 stages
|= S_028B54_PRIMGEN_EN(1);
4503 if (pipeline
->streamout_shader
)
4504 stages
|= S_028B54_NGG_WAVE_ID_EN(1);
4505 if (radv_pipeline_has_ngg_passthrough(pipeline
))
4506 stages
|= S_028B54_PRIMGEN_PASSTHRU_EN(1);
4507 } else if (radv_pipeline_has_gs(pipeline
)) {
4508 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
4511 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
4512 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4514 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4515 uint8_t hs_size
= 64, gs_size
= 64, vs_size
= 64;
4517 if (radv_pipeline_has_tess(pipeline
))
4518 hs_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.wave_size
;
4520 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
4521 vs_size
= gs_size
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.wave_size
;
4522 if (pipeline
->gs_copy_shader
)
4523 vs_size
= pipeline
->gs_copy_shader
->info
.wave_size
;
4524 } else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
4525 vs_size
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.wave_size
;
4526 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
4527 vs_size
= pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.wave_size
;
4529 if (radv_pipeline_has_ngg(pipeline
))
4532 /* legacy GS only supports Wave64 */
4533 stages
|= S_028B54_HS_W32_EN(hs_size
== 32 ? 1 : 0) |
4534 S_028B54_GS_W32_EN(gs_size
== 32 ? 1 : 0) |
4535 S_028B54_VS_W32_EN(vs_size
== 32 ? 1 : 0);
4538 radeon_set_context_reg(ctx_cs
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
4542 radv_pipeline_generate_cliprect_rule(struct radeon_cmdbuf
*ctx_cs
,
4543 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4545 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
4546 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
4547 uint32_t cliprect_rule
= 0;
4549 if (!discard_rectangle_info
) {
4550 cliprect_rule
= 0xffff;
4552 for (unsigned i
= 0; i
< (1u << MAX_DISCARD_RECTANGLES
); ++i
) {
4553 /* Interpret i as a bitmask, and then set the bit in
4554 * the mask if that combination of rectangles in which
4555 * the pixel is contained should pass the cliprect
4558 unsigned relevant_subset
= i
& ((1u << discard_rectangle_info
->discardRectangleCount
) - 1);
4560 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT
&&
4564 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT
&&
4568 cliprect_rule
|= 1u << i
;
4572 radeon_set_context_reg(ctx_cs
, R_02820C_PA_SC_CLIPRECT_RULE
, cliprect_rule
);
4576 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf
*ctx_cs
,
4577 struct radv_pipeline
*pipeline
)
4579 bool break_wave_at_eoi
= false;
4580 unsigned primgroup_size
;
4581 unsigned vertgroup_size
= 256; /* 256 = disable vertex grouping */
4583 if (radv_pipeline_has_tess(pipeline
)) {
4584 primgroup_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
4585 } else if (radv_pipeline_has_gs(pipeline
)) {
4586 const struct gfx9_gs_info
*gs_state
=
4587 &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs_ring_info
;
4588 unsigned vgt_gs_onchip_cntl
= gs_state
->vgt_gs_onchip_cntl
;
4589 primgroup_size
= G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl
);
4591 primgroup_size
= 128; /* recommended without a GS and tess */
4594 if (radv_pipeline_has_tess(pipeline
)) {
4595 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4596 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4597 break_wave_at_eoi
= true;
4600 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
,
4601 S_03096C_PRIM_GRP_SIZE(primgroup_size
) |
4602 S_03096C_VERT_GRP_SIZE(vertgroup_size
) |
4603 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4604 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
));
4608 radv_pipeline_generate_pm4(struct radv_pipeline
*pipeline
,
4609 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4610 const struct radv_graphics_pipeline_create_info
*extra
,
4611 const struct radv_blend_state
*blend
,
4612 const struct radv_tessellation_state
*tess
,
4615 struct radeon_cmdbuf
*ctx_cs
= &pipeline
->ctx_cs
;
4616 struct radeon_cmdbuf
*cs
= &pipeline
->cs
;
4619 ctx_cs
->max_dw
= 256;
4620 cs
->buf
= malloc(4 * (cs
->max_dw
+ ctx_cs
->max_dw
));
4621 ctx_cs
->buf
= cs
->buf
+ cs
->max_dw
;
4623 radv_pipeline_generate_depth_stencil_state(ctx_cs
, pipeline
, pCreateInfo
, extra
);
4624 radv_pipeline_generate_blend_state(ctx_cs
, pipeline
, blend
);
4625 radv_pipeline_generate_raster_state(ctx_cs
, pipeline
, pCreateInfo
);
4626 radv_pipeline_generate_multisample_state(ctx_cs
, pipeline
);
4627 radv_pipeline_generate_vgt_gs_mode(ctx_cs
, pipeline
);
4628 radv_pipeline_generate_vertex_shader(ctx_cs
, cs
, pipeline
, tess
);
4629 radv_pipeline_generate_tess_shaders(ctx_cs
, cs
, pipeline
, tess
);
4630 radv_pipeline_generate_geometry_shader(ctx_cs
, cs
, pipeline
);
4631 radv_pipeline_generate_fragment_shader(ctx_cs
, cs
, pipeline
);
4632 radv_pipeline_generate_ps_inputs(ctx_cs
, pipeline
);
4633 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs
, pipeline
);
4634 radv_pipeline_generate_binning_state(ctx_cs
, pipeline
, pCreateInfo
, blend
);
4635 radv_pipeline_generate_vgt_shader_config(ctx_cs
, pipeline
);
4636 radv_pipeline_generate_cliprect_rule(ctx_cs
, pCreateInfo
);
4638 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&& !radv_pipeline_has_ngg(pipeline
))
4639 gfx10_pipeline_generate_ge_cntl(ctx_cs
, pipeline
);
4641 radeon_set_context_reg(ctx_cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, gs_out
);
4643 pipeline
->ctx_cs_hash
= _mesa_hash_data(ctx_cs
->buf
, ctx_cs
->cdw
* 4);
4645 assert(ctx_cs
->cdw
<= ctx_cs
->max_dw
);
4646 assert(cs
->cdw
<= cs
->max_dw
);
4649 static struct radv_ia_multi_vgt_param_helpers
4650 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline
*pipeline
)
4652 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
= {0};
4653 const struct radv_device
*device
= pipeline
->device
;
4655 if (radv_pipeline_has_tess(pipeline
))
4656 ia_multi_vgt_param
.primgroup_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
4657 else if (radv_pipeline_has_gs(pipeline
))
4658 ia_multi_vgt_param
.primgroup_size
= 64;
4660 ia_multi_vgt_param
.primgroup_size
= 128; /* recommended without a GS */
4662 /* GS requirement. */
4663 ia_multi_vgt_param
.partial_es_wave
= false;
4664 if (radv_pipeline_has_gs(pipeline
) && device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4665 if (SI_GS_PER_ES
/ ia_multi_vgt_param
.primgroup_size
>= pipeline
->device
->gs_table_depth
- 3)
4666 ia_multi_vgt_param
.partial_es_wave
= true;
4668 ia_multi_vgt_param
.ia_switch_on_eoi
= false;
4669 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.prim_id_input
)
4670 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4671 if (radv_pipeline_has_gs(pipeline
) &&
4672 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.uses_prim_id
)
4673 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4674 if (radv_pipeline_has_tess(pipeline
)) {
4675 /* SWITCH_ON_EOI must be set if PrimID is used. */
4676 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4677 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4678 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4681 ia_multi_vgt_param
.partial_vs_wave
= false;
4682 if (radv_pipeline_has_tess(pipeline
)) {
4683 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4684 if ((device
->physical_device
->rad_info
.family
== CHIP_TAHITI
||
4685 device
->physical_device
->rad_info
.family
== CHIP_PITCAIRN
||
4686 device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
) &&
4687 radv_pipeline_has_gs(pipeline
))
4688 ia_multi_vgt_param
.partial_vs_wave
= true;
4689 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4690 if (device
->physical_device
->rad_info
.has_distributed_tess
) {
4691 if (radv_pipeline_has_gs(pipeline
)) {
4692 if (device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4693 ia_multi_vgt_param
.partial_es_wave
= true;
4695 ia_multi_vgt_param
.partial_vs_wave
= true;
4700 if (radv_pipeline_has_gs(pipeline
)) {
4701 /* On these chips there is the possibility of a hang if the
4702 * pipeline uses a GS and partial_vs_wave is not set.
4704 * This mostly does not hit 4-SE chips, as those typically set
4705 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4706 * with GS due to another workaround.
4708 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4710 if (device
->physical_device
->rad_info
.family
== CHIP_TONGA
||
4711 device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
4712 device
->physical_device
->rad_info
.family
== CHIP_POLARIS10
||
4713 device
->physical_device
->rad_info
.family
== CHIP_POLARIS11
||
4714 device
->physical_device
->rad_info
.family
== CHIP_POLARIS12
||
4715 device
->physical_device
->rad_info
.family
== CHIP_VEGAM
) {
4716 ia_multi_vgt_param
.partial_vs_wave
= true;
4720 ia_multi_vgt_param
.base
=
4721 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param
.primgroup_size
- 1) |
4722 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4723 S_028AA8_MAX_PRIMGRP_IN_WAVE(device
->physical_device
->rad_info
.chip_class
== GFX8
? 2 : 0) |
4724 S_030960_EN_INST_OPT_BASIC(device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
4725 S_030960_EN_INST_OPT_ADV(device
->physical_device
->rad_info
.chip_class
>= GFX9
);
4727 return ia_multi_vgt_param
;
4732 radv_compute_vertex_input_state(struct radv_pipeline
*pipeline
,
4733 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4735 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
4736 pCreateInfo
->pVertexInputState
;
4738 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
4739 const VkVertexInputBindingDescription
*desc
=
4740 &vi_info
->pVertexBindingDescriptions
[i
];
4742 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
4743 pipeline
->num_vertex_bindings
=
4744 MAX2(pipeline
->num_vertex_bindings
, desc
->binding
+ 1);
4748 static struct radv_shader_variant
*
4749 radv_pipeline_get_streamout_shader(struct radv_pipeline
*pipeline
)
4753 for (i
= MESA_SHADER_GEOMETRY
; i
>= MESA_SHADER_VERTEX
; i
--) {
4754 struct radv_shader_variant
*shader
=
4755 radv_get_shader(pipeline
, i
);
4757 if (shader
&& shader
->info
.so
.num_outputs
> 0)
4765 radv_pipeline_init(struct radv_pipeline
*pipeline
,
4766 struct radv_device
*device
,
4767 struct radv_pipeline_cache
*cache
,
4768 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4769 const struct radv_graphics_pipeline_create_info
*extra
)
4773 pipeline
->device
= device
;
4774 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
4775 assert(pipeline
->layout
);
4777 struct radv_blend_state blend
= radv_pipeline_init_blend_state(pipeline
, pCreateInfo
, extra
);
4779 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
4780 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
4781 radv_init_feedback(creation_feedback
);
4783 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
4785 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
4786 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
4787 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
4788 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
4789 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
4790 if(creation_feedback
)
4791 stage_feedbacks
[stage
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[i
];
4794 struct radv_pipeline_key key
= radv_generate_graphics_pipeline_key(pipeline
, pCreateInfo
, &blend
);
4796 result
= radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
,
4797 pCreateInfo
->flags
, pipeline_feedback
,
4799 if (result
!= VK_SUCCESS
)
4802 pipeline
->graphics
.spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
4803 radv_pipeline_init_multisample_state(pipeline
, &blend
, pCreateInfo
);
4806 pipeline
->graphics
.can_use_guardband
= radv_prim_can_use_guardband(pCreateInfo
->pInputAssemblyState
->topology
);
4808 if (radv_pipeline_has_gs(pipeline
)) {
4809 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs
.output_prim
);
4810 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4811 } else if (radv_pipeline_has_tess(pipeline
)) {
4812 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.point_mode
)
4813 gs_out
= V_028A6C_OUTPRIM_TYPE_POINTLIST
;
4815 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.primitive_mode
);
4816 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4818 gs_out
= si_conv_prim_to_gs_out(pCreateInfo
->pInputAssemblyState
->topology
);
4820 if (extra
&& extra
->use_rectlist
) {
4821 gs_out
= V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4822 pipeline
->graphics
.can_use_guardband
= true;
4823 if (radv_pipeline_has_ngg(pipeline
))
4824 gs_out
= V_028A6C_VGT_OUT_RECT_V0
;
4826 pipeline
->graphics
.prim_restart_enable
= !!pCreateInfo
->pInputAssemblyState
->primitiveRestartEnable
;
4828 radv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
, extra
);
4830 /* Ensure that some export memory is always allocated, for two reasons:
4832 * 1) Correctness: The hardware ignores the EXEC mask if no export
4833 * memory is allocated, so KILL and alpha test do not work correctly
4835 * 2) Performance: Every shader needs at least a NULL export, even when
4836 * it writes no color/depth output. The NULL export instruction
4837 * stalls without this setting.
4839 * Don't add this to CB_SHADER_MASK.
4841 * GFX10 supports pixel shaders without exports by setting both the
4842 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
4843 * instructions if any are present.
4845 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4846 if ((pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX9
||
4847 ps
->info
.ps
.can_discard
) &&
4848 !blend
.spi_shader_col_format
) {
4849 if (!ps
->info
.ps
.writes_z
&&
4850 !ps
->info
.ps
.writes_stencil
&&
4851 !ps
->info
.ps
.writes_sample_mask
)
4852 blend
.spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
4855 blend
.cb_shader_mask
= ps
->info
.ps
.cb_shader_mask
;
4858 (extra
->custom_blend_mode
== V_028808_CB_ELIMINATE_FAST_CLEAR
||
4859 extra
->custom_blend_mode
== V_028808_CB_FMASK_DECOMPRESS
||
4860 extra
->custom_blend_mode
== V_028808_CB_DCC_DECOMPRESS
||
4861 extra
->custom_blend_mode
== V_028808_CB_RESOLVE
)) {
4862 /* According to the CB spec states, CB_SHADER_MASK should be
4863 * set to enable writes to all four channels of MRT0.
4865 blend
.cb_shader_mask
= 0xf;
4868 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
4869 if (pipeline
->shaders
[i
]) {
4870 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[i
]->info
.need_indirect_descriptor_sets
;
4874 if (radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
4875 struct radv_shader_variant
*gs
=
4876 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4878 calculate_gs_ring_sizes(pipeline
, &gs
->info
.gs_ring_info
);
4881 struct radv_tessellation_state tess
= {0};
4882 if (radv_pipeline_has_tess(pipeline
)) {
4883 pipeline
->graphics
.tess_patch_control_points
=
4884 pCreateInfo
->pTessellationState
->patchControlPoints
;
4885 tess
= calculate_tess_state(pipeline
, pCreateInfo
);
4888 pipeline
->graphics
.ia_multi_vgt_param
= radv_compute_ia_multi_vgt_param_helpers(pipeline
);
4890 radv_compute_vertex_input_state(pipeline
, pCreateInfo
);
4892 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++)
4893 pipeline
->user_data_0
[i
] = radv_pipeline_stage_to_user_data_0(pipeline
, i
, device
->physical_device
->rad_info
.chip_class
);
4895 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
,
4896 AC_UD_VS_BASE_VERTEX_START_INSTANCE
);
4897 if (loc
->sgpr_idx
!= -1) {
4898 pipeline
->graphics
.vtx_base_sgpr
= pipeline
->user_data_0
[MESA_SHADER_VERTEX
];
4899 pipeline
->graphics
.vtx_base_sgpr
+= loc
->sgpr_idx
* 4;
4900 if (radv_get_shader(pipeline
, MESA_SHADER_VERTEX
)->info
.vs
.needs_draw_id
)
4901 pipeline
->graphics
.vtx_emit_num
= 3;
4903 pipeline
->graphics
.vtx_emit_num
= 2;
4906 /* Find the last vertex shader stage that eventually uses streamout. */
4907 pipeline
->streamout_shader
= radv_pipeline_get_streamout_shader(pipeline
);
4909 result
= radv_pipeline_scratch_init(device
, pipeline
);
4910 radv_pipeline_generate_pm4(pipeline
, pCreateInfo
, extra
, &blend
, &tess
, gs_out
);
4916 radv_graphics_pipeline_create(
4918 VkPipelineCache _cache
,
4919 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4920 const struct radv_graphics_pipeline_create_info
*extra
,
4921 const VkAllocationCallbacks
*pAllocator
,
4922 VkPipeline
*pPipeline
)
4924 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4925 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
4926 struct radv_pipeline
*pipeline
;
4929 pipeline
= vk_zalloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*pipeline
), 8,
4930 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4931 if (pipeline
== NULL
)
4932 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4934 vk_object_base_init(&device
->vk
, &pipeline
->base
,
4935 VK_OBJECT_TYPE_PIPELINE
);
4937 result
= radv_pipeline_init(pipeline
, device
, cache
,
4938 pCreateInfo
, extra
);
4939 if (result
!= VK_SUCCESS
) {
4940 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
4944 *pPipeline
= radv_pipeline_to_handle(pipeline
);
4949 VkResult
radv_CreateGraphicsPipelines(
4951 VkPipelineCache pipelineCache
,
4953 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
4954 const VkAllocationCallbacks
* pAllocator
,
4955 VkPipeline
* pPipelines
)
4957 VkResult result
= VK_SUCCESS
;
4960 for (; i
< count
; i
++) {
4962 r
= radv_graphics_pipeline_create(_device
,
4965 NULL
, pAllocator
, &pPipelines
[i
]);
4966 if (r
!= VK_SUCCESS
) {
4968 pPipelines
[i
] = VK_NULL_HANDLE
;
4970 if (pCreateInfos
[i
].flags
& VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT
)
4975 for (; i
< count
; ++i
)
4976 pPipelines
[i
] = VK_NULL_HANDLE
;
4982 radv_pipeline_generate_hw_cs(struct radeon_cmdbuf
*cs
,
4983 struct radv_pipeline
*pipeline
)
4985 struct radv_shader_variant
*shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
4986 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
4987 struct radv_device
*device
= pipeline
->device
;
4989 radeon_set_sh_reg_seq(cs
, R_00B830_COMPUTE_PGM_LO
, 2);
4990 radeon_emit(cs
, va
>> 8);
4991 radeon_emit(cs
, S_00B834_DATA(va
>> 40));
4993 radeon_set_sh_reg_seq(cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
4994 radeon_emit(cs
, shader
->config
.rsrc1
);
4995 radeon_emit(cs
, shader
->config
.rsrc2
);
4996 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4997 radeon_set_sh_reg(cs
, R_00B8A0_COMPUTE_PGM_RSRC3
, shader
->config
.rsrc3
);
5002 radv_pipeline_generate_compute_state(struct radeon_cmdbuf
*cs
,
5003 struct radv_pipeline
*pipeline
)
5005 struct radv_shader_variant
*shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
5006 struct radv_device
*device
= pipeline
->device
;
5007 unsigned threads_per_threadgroup
;
5008 unsigned threadgroups_per_cu
= 1;
5009 unsigned waves_per_threadgroup
;
5010 unsigned max_waves_per_sh
= 0;
5012 /* Calculate best compute resource limits. */
5013 threads_per_threadgroup
= shader
->info
.cs
.block_size
[0] *
5014 shader
->info
.cs
.block_size
[1] *
5015 shader
->info
.cs
.block_size
[2];
5016 waves_per_threadgroup
= DIV_ROUND_UP(threads_per_threadgroup
,
5017 shader
->info
.wave_size
);
5019 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
5020 waves_per_threadgroup
== 1)
5021 threadgroups_per_cu
= 2;
5023 radeon_set_sh_reg(cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
5024 ac_get_compute_resource_limits(&device
->physical_device
->rad_info
,
5025 waves_per_threadgroup
,
5027 threadgroups_per_cu
));
5029 radeon_set_sh_reg_seq(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
5030 radeon_emit(cs
, S_00B81C_NUM_THREAD_FULL(shader
->info
.cs
.block_size
[0]));
5031 radeon_emit(cs
, S_00B81C_NUM_THREAD_FULL(shader
->info
.cs
.block_size
[1]));
5032 radeon_emit(cs
, S_00B81C_NUM_THREAD_FULL(shader
->info
.cs
.block_size
[2]));
5036 radv_compute_generate_pm4(struct radv_pipeline
*pipeline
)
5038 struct radv_device
*device
= pipeline
->device
;
5039 struct radeon_cmdbuf
*cs
= &pipeline
->cs
;
5041 cs
->max_dw
= device
->physical_device
->rad_info
.chip_class
>= GFX10
? 19 : 16;
5042 cs
->buf
= malloc(cs
->max_dw
* 4);
5044 radv_pipeline_generate_hw_cs(cs
, pipeline
);
5045 radv_pipeline_generate_compute_state(cs
, pipeline
);
5047 assert(pipeline
->cs
.cdw
<= pipeline
->cs
.max_dw
);
5050 static struct radv_pipeline_key
5051 radv_generate_compute_pipeline_key(struct radv_pipeline
*pipeline
,
5052 const VkComputePipelineCreateInfo
*pCreateInfo
)
5054 const VkPipelineShaderStageCreateInfo
*stage
= &pCreateInfo
->stage
;
5055 struct radv_pipeline_key key
;
5056 memset(&key
, 0, sizeof(key
));
5058 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
5059 key
.optimisations_disabled
= 1;
5061 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*subgroup_size
=
5062 vk_find_struct_const(stage
->pNext
,
5063 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT
);
5065 if (subgroup_size
) {
5066 assert(subgroup_size
->requiredSubgroupSize
== 32 ||
5067 subgroup_size
->requiredSubgroupSize
== 64);
5068 key
.compute_subgroup_size
= subgroup_size
->requiredSubgroupSize
;
5074 static VkResult
radv_compute_pipeline_create(
5076 VkPipelineCache _cache
,
5077 const VkComputePipelineCreateInfo
* pCreateInfo
,
5078 const VkAllocationCallbacks
* pAllocator
,
5079 VkPipeline
* pPipeline
)
5081 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5082 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
5083 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
5084 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
5085 struct radv_pipeline
*pipeline
;
5088 pipeline
= vk_zalloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*pipeline
), 8,
5089 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5090 if (pipeline
== NULL
)
5091 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5093 vk_object_base_init(&device
->vk
, &pipeline
->base
,
5094 VK_OBJECT_TYPE_PIPELINE
);
5096 pipeline
->device
= device
;
5097 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
5098 assert(pipeline
->layout
);
5100 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
5101 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
5102 radv_init_feedback(creation_feedback
);
5104 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
5105 if (creation_feedback
)
5106 stage_feedbacks
[MESA_SHADER_COMPUTE
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[0];
5108 pStages
[MESA_SHADER_COMPUTE
] = &pCreateInfo
->stage
;
5110 struct radv_pipeline_key key
=
5111 radv_generate_compute_pipeline_key(pipeline
, pCreateInfo
);
5113 result
= radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
,
5114 pCreateInfo
->flags
, pipeline_feedback
,
5116 if (result
!= VK_SUCCESS
) {
5117 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5121 pipeline
->user_data_0
[MESA_SHADER_COMPUTE
] = radv_pipeline_stage_to_user_data_0(pipeline
, MESA_SHADER_COMPUTE
, device
->physical_device
->rad_info
.chip_class
);
5122 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.need_indirect_descriptor_sets
;
5123 result
= radv_pipeline_scratch_init(device
, pipeline
);
5124 if (result
!= VK_SUCCESS
) {
5125 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5129 radv_compute_generate_pm4(pipeline
);
5131 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5136 VkResult
radv_CreateComputePipelines(
5138 VkPipelineCache pipelineCache
,
5140 const VkComputePipelineCreateInfo
* pCreateInfos
,
5141 const VkAllocationCallbacks
* pAllocator
,
5142 VkPipeline
* pPipelines
)
5144 VkResult result
= VK_SUCCESS
;
5147 for (; i
< count
; i
++) {
5149 r
= radv_compute_pipeline_create(_device
, pipelineCache
,
5151 pAllocator
, &pPipelines
[i
]);
5152 if (r
!= VK_SUCCESS
) {
5154 pPipelines
[i
] = VK_NULL_HANDLE
;
5156 if (pCreateInfos
[i
].flags
& VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT
)
5161 for (; i
< count
; ++i
)
5162 pPipelines
[i
] = VK_NULL_HANDLE
;
5168 static uint32_t radv_get_executable_count(const struct radv_pipeline
*pipeline
)
5171 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5172 if (!pipeline
->shaders
[i
])
5175 if (i
== MESA_SHADER_GEOMETRY
&&
5176 !radv_pipeline_has_ngg(pipeline
)) {
5186 static struct radv_shader_variant
*
5187 radv_get_shader_from_executable_index(const struct radv_pipeline
*pipeline
, int index
, gl_shader_stage
*stage
)
5189 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5190 if (!pipeline
->shaders
[i
])
5194 return pipeline
->shaders
[i
];
5199 if (i
== MESA_SHADER_GEOMETRY
&&
5200 !radv_pipeline_has_ngg(pipeline
)) {
5203 return pipeline
->gs_copy_shader
;
5213 /* Basically strlcpy (which does not exist on linux) specialized for
5215 static void desc_copy(char *desc
, const char *src
) {
5216 int len
= strlen(src
);
5217 assert(len
< VK_MAX_DESCRIPTION_SIZE
);
5218 memcpy(desc
, src
, len
);
5219 memset(desc
+ len
, 0, VK_MAX_DESCRIPTION_SIZE
- len
);
5222 VkResult
radv_GetPipelineExecutablePropertiesKHR(
5224 const VkPipelineInfoKHR
* pPipelineInfo
,
5225 uint32_t* pExecutableCount
,
5226 VkPipelineExecutablePropertiesKHR
* pProperties
)
5228 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pPipelineInfo
->pipeline
);
5229 const uint32_t total_count
= radv_get_executable_count(pipeline
);
5232 *pExecutableCount
= total_count
;
5236 const uint32_t count
= MIN2(total_count
, *pExecutableCount
);
5237 for (unsigned i
= 0, executable_idx
= 0;
5238 i
< MESA_SHADER_STAGES
&& executable_idx
< count
; ++i
) {
5239 if (!pipeline
->shaders
[i
])
5241 pProperties
[executable_idx
].stages
= mesa_to_vk_shader_stage(i
);
5242 const char *name
= NULL
;
5243 const char *description
= NULL
;
5245 case MESA_SHADER_VERTEX
:
5246 name
= "Vertex Shader";
5247 description
= "Vulkan Vertex Shader";
5249 case MESA_SHADER_TESS_CTRL
:
5250 if (!pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5251 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5252 name
= "Vertex + Tessellation Control Shaders";
5253 description
= "Combined Vulkan Vertex and Tessellation Control Shaders";
5255 name
= "Tessellation Control Shader";
5256 description
= "Vulkan Tessellation Control Shader";
5259 case MESA_SHADER_TESS_EVAL
:
5260 name
= "Tessellation Evaluation Shader";
5261 description
= "Vulkan Tessellation Evaluation Shader";
5263 case MESA_SHADER_GEOMETRY
:
5264 if (radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]) {
5265 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
;
5266 name
= "Tessellation Evaluation + Geometry Shaders";
5267 description
= "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5268 } else if (!radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5269 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5270 name
= "Vertex + Geometry Shader";
5271 description
= "Combined Vulkan Vertex and Geometry Shaders";
5273 name
= "Geometry Shader";
5274 description
= "Vulkan Geometry Shader";
5277 case MESA_SHADER_FRAGMENT
:
5278 name
= "Fragment Shader";
5279 description
= "Vulkan Fragment Shader";
5281 case MESA_SHADER_COMPUTE
:
5282 name
= "Compute Shader";
5283 description
= "Vulkan Compute Shader";
5287 pProperties
[executable_idx
].subgroupSize
= pipeline
->shaders
[i
]->info
.wave_size
;
5288 desc_copy(pProperties
[executable_idx
].name
, name
);
5289 desc_copy(pProperties
[executable_idx
].description
, description
);
5292 if (i
== MESA_SHADER_GEOMETRY
&&
5293 !radv_pipeline_has_ngg(pipeline
)) {
5294 assert(pipeline
->gs_copy_shader
);
5295 if (executable_idx
>= count
)
5298 pProperties
[executable_idx
].stages
= VK_SHADER_STAGE_GEOMETRY_BIT
;
5299 pProperties
[executable_idx
].subgroupSize
= 64;
5300 desc_copy(pProperties
[executable_idx
].name
, "GS Copy Shader");
5301 desc_copy(pProperties
[executable_idx
].description
,
5302 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5308 VkResult result
= *pExecutableCount
< total_count
? VK_INCOMPLETE
: VK_SUCCESS
;
5309 *pExecutableCount
= count
;
5313 VkResult
radv_GetPipelineExecutableStatisticsKHR(
5315 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5316 uint32_t* pStatisticCount
,
5317 VkPipelineExecutableStatisticKHR
* pStatistics
)
5319 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5320 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5321 gl_shader_stage stage
;
5322 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5324 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
5325 unsigned lds_increment
= chip_class
>= GFX7
? 512 : 256;
5326 unsigned max_waves
= radv_get_max_waves(device
, shader
, stage
);
5328 VkPipelineExecutableStatisticKHR
*s
= pStatistics
;
5329 VkPipelineExecutableStatisticKHR
*end
= s
+ (pStatistics
? *pStatisticCount
: 0);
5330 VkResult result
= VK_SUCCESS
;
5333 desc_copy(s
->name
, "SGPRs");
5334 desc_copy(s
->description
, "Number of SGPR registers allocated per subgroup");
5335 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5336 s
->value
.u64
= shader
->config
.num_sgprs
;
5341 desc_copy(s
->name
, "VGPRs");
5342 desc_copy(s
->description
, "Number of VGPR registers allocated per subgroup");
5343 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5344 s
->value
.u64
= shader
->config
.num_vgprs
;
5349 desc_copy(s
->name
, "Spilled SGPRs");
5350 desc_copy(s
->description
, "Number of SGPR registers spilled per subgroup");
5351 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5352 s
->value
.u64
= shader
->config
.spilled_sgprs
;
5357 desc_copy(s
->name
, "Spilled VGPRs");
5358 desc_copy(s
->description
, "Number of VGPR registers spilled per subgroup");
5359 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5360 s
->value
.u64
= shader
->config
.spilled_vgprs
;
5365 desc_copy(s
->name
, "PrivMem VGPRs");
5366 desc_copy(s
->description
, "Number of VGPRs stored in private memory per subgroup");
5367 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5368 s
->value
.u64
= shader
->info
.private_mem_vgprs
;
5373 desc_copy(s
->name
, "Code size");
5374 desc_copy(s
->description
, "Code size in bytes");
5375 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5376 s
->value
.u64
= shader
->exec_size
;
5381 desc_copy(s
->name
, "LDS size");
5382 desc_copy(s
->description
, "LDS size in bytes per workgroup");
5383 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5384 s
->value
.u64
= shader
->config
.lds_size
* lds_increment
;
5389 desc_copy(s
->name
, "Scratch size");
5390 desc_copy(s
->description
, "Private memory in bytes per subgroup");
5391 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5392 s
->value
.u64
= shader
->config
.scratch_bytes_per_wave
;
5397 desc_copy(s
->name
, "Subgroups per SIMD");
5398 desc_copy(s
->description
, "The maximum number of subgroups in flight on a SIMD unit");
5399 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5400 s
->value
.u64
= max_waves
;
5404 if (shader
->statistics
) {
5405 for (unsigned i
= 0; i
< shader
->statistics
->count
; i
++) {
5406 struct radv_compiler_statistic_info
*info
= &shader
->statistics
->infos
[i
];
5407 uint32_t value
= shader
->statistics
->values
[i
];
5409 desc_copy(s
->name
, info
->name
);
5410 desc_copy(s
->description
, info
->desc
);
5411 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5412 s
->value
.u64
= value
;
5419 *pStatisticCount
= s
- pStatistics
;
5421 *pStatisticCount
= end
- pStatistics
;
5422 result
= VK_INCOMPLETE
;
5424 *pStatisticCount
= s
- pStatistics
;
5430 static VkResult
radv_copy_representation(void *data
, size_t *data_size
, const char *src
)
5432 size_t total_size
= strlen(src
) + 1;
5435 *data_size
= total_size
;
5439 size_t size
= MIN2(total_size
, *data_size
);
5441 memcpy(data
, src
, size
);
5443 *((char*)data
+ size
- 1) = 0;
5444 return size
< total_size
? VK_INCOMPLETE
: VK_SUCCESS
;
5447 VkResult
radv_GetPipelineExecutableInternalRepresentationsKHR(
5449 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5450 uint32_t* pInternalRepresentationCount
,
5451 VkPipelineExecutableInternalRepresentationKHR
* pInternalRepresentations
)
5453 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5454 gl_shader_stage stage
;
5455 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5457 VkPipelineExecutableInternalRepresentationKHR
*p
= pInternalRepresentations
;
5458 VkPipelineExecutableInternalRepresentationKHR
*end
= p
+ (pInternalRepresentations
? *pInternalRepresentationCount
: 0);
5459 VkResult result
= VK_SUCCESS
;
5463 desc_copy(p
->name
, "NIR Shader(s)");
5464 desc_copy(p
->description
, "The optimized NIR shader(s)");
5465 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->nir_string
) != VK_SUCCESS
)
5466 result
= VK_INCOMPLETE
;
5473 if (pipeline
->device
->physical_device
->use_llvm
) {
5474 desc_copy(p
->name
, "LLVM IR");
5475 desc_copy(p
->description
, "The LLVM IR after some optimizations");
5477 desc_copy(p
->name
, "ACO IR");
5478 desc_copy(p
->description
, "The ACO IR after some optimizations");
5480 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->ir_string
) != VK_SUCCESS
)
5481 result
= VK_INCOMPLETE
;
5488 desc_copy(p
->name
, "Assembly");
5489 desc_copy(p
->description
, "Final Assembly");
5490 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->disasm_string
) != VK_SUCCESS
)
5491 result
= VK_INCOMPLETE
;
5495 if (!pInternalRepresentations
)
5496 *pInternalRepresentationCount
= p
- pInternalRepresentations
;
5498 result
= VK_INCOMPLETE
;
5499 *pInternalRepresentationCount
= end
- pInternalRepresentations
;
5501 *pInternalRepresentationCount
= p
- pInternalRepresentations
;