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radv: fix possibly wrong PA_SC_AA_CONFIG value for conservative rast
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
33 #include "radv_cs.h"
34 #include "radv_shader.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
39 #include "vk_util.h"
40
41 #include <llvm-c/Core.h>
42 #include <llvm-c/TargetMachine.h>
43
44 #include "sid.h"
45 #include "ac_binary.h"
46 #include "ac_llvm_util.h"
47 #include "ac_nir_to_llvm.h"
48 #include "vk_format.h"
49 #include "util/debug.h"
50 #include "ac_exp_param.h"
51 #include "ac_shader_util.h"
52 #include "main/menums.h"
53
54 struct radv_blend_state {
55 uint32_t blend_enable_4bit;
56 uint32_t need_src_alpha;
57
58 uint32_t cb_color_control;
59 uint32_t cb_target_mask;
60 uint32_t cb_target_enabled_4bit;
61 uint32_t sx_mrt_blend_opt[8];
62 uint32_t cb_blend_control[8];
63
64 uint32_t spi_shader_col_format;
65 uint32_t cb_shader_mask;
66 uint32_t db_alpha_to_mask;
67
68 uint32_t commutative_4bit;
69
70 bool single_cb_enable;
71 bool mrt0_is_dual_src;
72 };
73
74 struct radv_dsa_order_invariance {
75 /* Whether the final result in Z/S buffers is guaranteed to be
76 * invariant under changes to the order in which fragments arrive.
77 */
78 bool zs;
79
80 /* Whether the set of fragments that pass the combined Z/S test is
81 * guaranteed to be invariant under changes to the order in which
82 * fragments arrive.
83 */
84 bool pass_set;
85 };
86
87 struct radv_tessellation_state {
88 uint32_t ls_hs_config;
89 unsigned num_patches;
90 unsigned lds_size;
91 uint32_t tf_param;
92 };
93
94 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline)
95 {
96 struct radv_shader_variant *variant = NULL;
97 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
98 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
99 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
100 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
101 else if (pipeline->shaders[MESA_SHADER_VERTEX])
102 variant = pipeline->shaders[MESA_SHADER_VERTEX];
103 else
104 return false;
105 return variant->info.is_ngg;
106 }
107
108 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline)
109 {
110 if (!radv_pipeline_has_gs(pipeline))
111 return false;
112
113 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
114 * On GFX10, it might be required in rare cases if it's not possible to
115 * enable NGG.
116 */
117 if (radv_pipeline_has_ngg(pipeline))
118 return false;
119
120 assert(pipeline->gs_copy_shader);
121 return true;
122 }
123
124 static void
125 radv_pipeline_destroy(struct radv_device *device,
126 struct radv_pipeline *pipeline,
127 const VkAllocationCallbacks* allocator)
128 {
129 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
130 if (pipeline->shaders[i])
131 radv_shader_variant_destroy(device, pipeline->shaders[i]);
132
133 if (pipeline->gs_copy_shader)
134 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
135
136 if(pipeline->cs.buf)
137 free(pipeline->cs.buf);
138 vk_free2(&device->alloc, allocator, pipeline);
139 }
140
141 void radv_DestroyPipeline(
142 VkDevice _device,
143 VkPipeline _pipeline,
144 const VkAllocationCallbacks* pAllocator)
145 {
146 RADV_FROM_HANDLE(radv_device, device, _device);
147 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
148
149 if (!_pipeline)
150 return;
151
152 radv_pipeline_destroy(device, pipeline, pAllocator);
153 }
154
155 static uint32_t get_hash_flags(struct radv_device *device)
156 {
157 uint32_t hash_flags = 0;
158
159 if (device->instance->debug_flags & RADV_DEBUG_NO_NGG)
160 hash_flags |= RADV_HASH_SHADER_NO_NGG;
161 if (device->instance->perftest_flags & RADV_PERFTEST_SISCHED)
162 hash_flags |= RADV_HASH_SHADER_SISCHED;
163 if (device->physical_device->cs_wave_size == 32)
164 hash_flags |= RADV_HASH_SHADER_CS_WAVE32;
165 if (device->physical_device->ps_wave_size == 32)
166 hash_flags |= RADV_HASH_SHADER_PS_WAVE32;
167 if (device->physical_device->ge_wave_size == 32)
168 hash_flags |= RADV_HASH_SHADER_GE_WAVE32;
169 if (device->physical_device->use_aco)
170 hash_flags |= RADV_HASH_SHADER_ACO;
171 return hash_flags;
172 }
173
174 static VkResult
175 radv_pipeline_scratch_init(struct radv_device *device,
176 struct radv_pipeline *pipeline)
177 {
178 unsigned scratch_bytes_per_wave = 0;
179 unsigned max_waves = 0;
180 unsigned min_waves = 1;
181
182 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
183 if (pipeline->shaders[i] &&
184 pipeline->shaders[i]->config.scratch_bytes_per_wave) {
185 unsigned max_stage_waves = device->scratch_waves;
186
187 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
188 pipeline->shaders[i]->config.scratch_bytes_per_wave);
189
190 max_stage_waves = MIN2(max_stage_waves,
191 4 * device->physical_device->rad_info.num_good_compute_units *
192 (256 / pipeline->shaders[i]->config.num_vgprs));
193 max_waves = MAX2(max_waves, max_stage_waves);
194 }
195 }
196
197 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
198 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
199 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
200 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
201 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
202 }
203
204 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
205 pipeline->max_waves = max_waves;
206 return VK_SUCCESS;
207 }
208
209 static uint32_t si_translate_blend_logic_op(VkLogicOp op)
210 {
211 switch (op) {
212 case VK_LOGIC_OP_CLEAR:
213 return V_028808_ROP3_CLEAR;
214 case VK_LOGIC_OP_AND:
215 return V_028808_ROP3_AND;
216 case VK_LOGIC_OP_AND_REVERSE:
217 return V_028808_ROP3_AND_REVERSE;
218 case VK_LOGIC_OP_COPY:
219 return V_028808_ROP3_COPY;
220 case VK_LOGIC_OP_AND_INVERTED:
221 return V_028808_ROP3_AND_INVERTED;
222 case VK_LOGIC_OP_NO_OP:
223 return V_028808_ROP3_NO_OP;
224 case VK_LOGIC_OP_XOR:
225 return V_028808_ROP3_XOR;
226 case VK_LOGIC_OP_OR:
227 return V_028808_ROP3_OR;
228 case VK_LOGIC_OP_NOR:
229 return V_028808_ROP3_NOR;
230 case VK_LOGIC_OP_EQUIVALENT:
231 return V_028808_ROP3_EQUIVALENT;
232 case VK_LOGIC_OP_INVERT:
233 return V_028808_ROP3_INVERT;
234 case VK_LOGIC_OP_OR_REVERSE:
235 return V_028808_ROP3_OR_REVERSE;
236 case VK_LOGIC_OP_COPY_INVERTED:
237 return V_028808_ROP3_COPY_INVERTED;
238 case VK_LOGIC_OP_OR_INVERTED:
239 return V_028808_ROP3_OR_INVERTED;
240 case VK_LOGIC_OP_NAND:
241 return V_028808_ROP3_NAND;
242 case VK_LOGIC_OP_SET:
243 return V_028808_ROP3_SET;
244 default:
245 unreachable("Unhandled logic op");
246 }
247 }
248
249
250 static uint32_t si_translate_blend_function(VkBlendOp op)
251 {
252 switch (op) {
253 case VK_BLEND_OP_ADD:
254 return V_028780_COMB_DST_PLUS_SRC;
255 case VK_BLEND_OP_SUBTRACT:
256 return V_028780_COMB_SRC_MINUS_DST;
257 case VK_BLEND_OP_REVERSE_SUBTRACT:
258 return V_028780_COMB_DST_MINUS_SRC;
259 case VK_BLEND_OP_MIN:
260 return V_028780_COMB_MIN_DST_SRC;
261 case VK_BLEND_OP_MAX:
262 return V_028780_COMB_MAX_DST_SRC;
263 default:
264 return 0;
265 }
266 }
267
268 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
269 {
270 switch (factor) {
271 case VK_BLEND_FACTOR_ZERO:
272 return V_028780_BLEND_ZERO;
273 case VK_BLEND_FACTOR_ONE:
274 return V_028780_BLEND_ONE;
275 case VK_BLEND_FACTOR_SRC_COLOR:
276 return V_028780_BLEND_SRC_COLOR;
277 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
278 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
279 case VK_BLEND_FACTOR_DST_COLOR:
280 return V_028780_BLEND_DST_COLOR;
281 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
282 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
283 case VK_BLEND_FACTOR_SRC_ALPHA:
284 return V_028780_BLEND_SRC_ALPHA;
285 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
286 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
287 case VK_BLEND_FACTOR_DST_ALPHA:
288 return V_028780_BLEND_DST_ALPHA;
289 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
290 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
291 case VK_BLEND_FACTOR_CONSTANT_COLOR:
292 return V_028780_BLEND_CONSTANT_COLOR;
293 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
294 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
295 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
296 return V_028780_BLEND_CONSTANT_ALPHA;
297 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
298 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
299 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
300 return V_028780_BLEND_SRC_ALPHA_SATURATE;
301 case VK_BLEND_FACTOR_SRC1_COLOR:
302 return V_028780_BLEND_SRC1_COLOR;
303 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
304 return V_028780_BLEND_INV_SRC1_COLOR;
305 case VK_BLEND_FACTOR_SRC1_ALPHA:
306 return V_028780_BLEND_SRC1_ALPHA;
307 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
308 return V_028780_BLEND_INV_SRC1_ALPHA;
309 default:
310 return 0;
311 }
312 }
313
314 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
315 {
316 switch (op) {
317 case VK_BLEND_OP_ADD:
318 return V_028760_OPT_COMB_ADD;
319 case VK_BLEND_OP_SUBTRACT:
320 return V_028760_OPT_COMB_SUBTRACT;
321 case VK_BLEND_OP_REVERSE_SUBTRACT:
322 return V_028760_OPT_COMB_REVSUBTRACT;
323 case VK_BLEND_OP_MIN:
324 return V_028760_OPT_COMB_MIN;
325 case VK_BLEND_OP_MAX:
326 return V_028760_OPT_COMB_MAX;
327 default:
328 return V_028760_OPT_COMB_BLEND_DISABLED;
329 }
330 }
331
332 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
333 {
334 switch (factor) {
335 case VK_BLEND_FACTOR_ZERO:
336 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
337 case VK_BLEND_FACTOR_ONE:
338 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
339 case VK_BLEND_FACTOR_SRC_COLOR:
340 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
341 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
342 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
343 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
344 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
345 case VK_BLEND_FACTOR_SRC_ALPHA:
346 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
347 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
348 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
349 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
350 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
351 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
352 default:
353 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
354 }
355 }
356
357 /**
358 * Get rid of DST in the blend factors by commuting the operands:
359 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
360 */
361 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
362 unsigned *dst_factor, unsigned expected_dst,
363 unsigned replacement_src)
364 {
365 if (*src_factor == expected_dst &&
366 *dst_factor == VK_BLEND_FACTOR_ZERO) {
367 *src_factor = VK_BLEND_FACTOR_ZERO;
368 *dst_factor = replacement_src;
369
370 /* Commuting the operands requires reversing subtractions. */
371 if (*func == VK_BLEND_OP_SUBTRACT)
372 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
373 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
374 *func = VK_BLEND_OP_SUBTRACT;
375 }
376 }
377
378 static bool si_blend_factor_uses_dst(unsigned factor)
379 {
380 return factor == VK_BLEND_FACTOR_DST_COLOR ||
381 factor == VK_BLEND_FACTOR_DST_ALPHA ||
382 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
383 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
384 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
385 }
386
387 static bool is_dual_src(VkBlendFactor factor)
388 {
389 switch (factor) {
390 case VK_BLEND_FACTOR_SRC1_COLOR:
391 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
392 case VK_BLEND_FACTOR_SRC1_ALPHA:
393 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
394 return true;
395 default:
396 return false;
397 }
398 }
399
400 static unsigned si_choose_spi_color_format(VkFormat vk_format,
401 bool blend_enable,
402 bool blend_need_alpha)
403 {
404 const struct vk_format_description *desc = vk_format_description(vk_format);
405 unsigned format, ntype, swap;
406
407 /* Alpha is needed for alpha-to-coverage.
408 * Blending may be with or without alpha.
409 */
410 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
411 unsigned alpha = 0; /* exports alpha, but may not support blending */
412 unsigned blend = 0; /* supports blending, but may not export alpha */
413 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
414
415 format = radv_translate_colorformat(vk_format);
416 ntype = radv_translate_color_numformat(vk_format, desc,
417 vk_format_get_first_non_void_channel(vk_format));
418 swap = radv_translate_colorswap(vk_format, false);
419
420 /* Choose the SPI color formats. These are required values for Stoney/RB+.
421 * Other chips have multiple choices, though they are not necessarily better.
422 */
423 switch (format) {
424 case V_028C70_COLOR_5_6_5:
425 case V_028C70_COLOR_1_5_5_5:
426 case V_028C70_COLOR_5_5_5_1:
427 case V_028C70_COLOR_4_4_4_4:
428 case V_028C70_COLOR_10_11_11:
429 case V_028C70_COLOR_11_11_10:
430 case V_028C70_COLOR_8:
431 case V_028C70_COLOR_8_8:
432 case V_028C70_COLOR_8_8_8_8:
433 case V_028C70_COLOR_10_10_10_2:
434 case V_028C70_COLOR_2_10_10_10:
435 if (ntype == V_028C70_NUMBER_UINT)
436 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
437 else if (ntype == V_028C70_NUMBER_SINT)
438 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
439 else
440 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
441 break;
442
443 case V_028C70_COLOR_16:
444 case V_028C70_COLOR_16_16:
445 case V_028C70_COLOR_16_16_16_16:
446 if (ntype == V_028C70_NUMBER_UNORM ||
447 ntype == V_028C70_NUMBER_SNORM) {
448 /* UNORM16 and SNORM16 don't support blending */
449 if (ntype == V_028C70_NUMBER_UNORM)
450 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
451 else
452 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
453
454 /* Use 32 bits per channel for blending. */
455 if (format == V_028C70_COLOR_16) {
456 if (swap == V_028C70_SWAP_STD) { /* R */
457 blend = V_028714_SPI_SHADER_32_R;
458 blend_alpha = V_028714_SPI_SHADER_32_AR;
459 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
460 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
461 else
462 assert(0);
463 } else if (format == V_028C70_COLOR_16_16) {
464 if (swap == V_028C70_SWAP_STD) { /* RG */
465 blend = V_028714_SPI_SHADER_32_GR;
466 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
467 } else if (swap == V_028C70_SWAP_ALT) /* RA */
468 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
469 else
470 assert(0);
471 } else /* 16_16_16_16 */
472 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
473 } else if (ntype == V_028C70_NUMBER_UINT)
474 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
475 else if (ntype == V_028C70_NUMBER_SINT)
476 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
477 else if (ntype == V_028C70_NUMBER_FLOAT)
478 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
479 else
480 assert(0);
481 break;
482
483 case V_028C70_COLOR_32:
484 if (swap == V_028C70_SWAP_STD) { /* R */
485 blend = normal = V_028714_SPI_SHADER_32_R;
486 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
487 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
488 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
489 else
490 assert(0);
491 break;
492
493 case V_028C70_COLOR_32_32:
494 if (swap == V_028C70_SWAP_STD) { /* RG */
495 blend = normal = V_028714_SPI_SHADER_32_GR;
496 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
497 } else if (swap == V_028C70_SWAP_ALT) /* RA */
498 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
499 else
500 assert(0);
501 break;
502
503 case V_028C70_COLOR_32_32_32_32:
504 case V_028C70_COLOR_8_24:
505 case V_028C70_COLOR_24_8:
506 case V_028C70_COLOR_X24_8_32_FLOAT:
507 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
508 break;
509
510 default:
511 unreachable("unhandled blend format");
512 }
513
514 if (blend_enable && blend_need_alpha)
515 return blend_alpha;
516 else if(blend_need_alpha)
517 return alpha;
518 else if(blend_enable)
519 return blend;
520 else
521 return normal;
522 }
523
524 static void
525 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
526 const VkGraphicsPipelineCreateInfo *pCreateInfo,
527 struct radv_blend_state *blend)
528 {
529 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
530 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
531 unsigned col_format = 0;
532 unsigned num_targets;
533
534 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
535 unsigned cf;
536
537 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
538 cf = V_028714_SPI_SHADER_ZERO;
539 } else {
540 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
541 bool blend_enable =
542 blend->blend_enable_4bit & (0xfu << (i * 4));
543
544 cf = si_choose_spi_color_format(attachment->format,
545 blend_enable,
546 blend->need_src_alpha & (1 << i));
547 }
548
549 col_format |= cf << (4 * i);
550 }
551
552 if (!(col_format & 0xf) && blend->need_src_alpha & (1 << 0)) {
553 /* When a subpass doesn't have any color attachments, write the
554 * alpha channel of MRT0 when alpha coverage is enabled because
555 * the depth attachment needs it.
556 */
557 col_format |= V_028714_SPI_SHADER_32_AR;
558 }
559
560 /* If the i-th target format is set, all previous target formats must
561 * be non-zero to avoid hangs.
562 */
563 num_targets = (util_last_bit(col_format) + 3) / 4;
564 for (unsigned i = 0; i < num_targets; i++) {
565 if (!(col_format & (0xf << (i * 4)))) {
566 col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
567 }
568 }
569
570 /* The output for dual source blending should have the same format as
571 * the first output.
572 */
573 if (blend->mrt0_is_dual_src)
574 col_format |= (col_format & 0xf) << 4;
575
576 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
577 blend->spi_shader_col_format = col_format;
578 }
579
580 static bool
581 format_is_int8(VkFormat format)
582 {
583 const struct vk_format_description *desc = vk_format_description(format);
584 int channel = vk_format_get_first_non_void_channel(format);
585
586 return channel >= 0 && desc->channel[channel].pure_integer &&
587 desc->channel[channel].size == 8;
588 }
589
590 static bool
591 format_is_int10(VkFormat format)
592 {
593 const struct vk_format_description *desc = vk_format_description(format);
594
595 if (desc->nr_channels != 4)
596 return false;
597 for (unsigned i = 0; i < 4; i++) {
598 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
599 return true;
600 }
601 return false;
602 }
603
604 /*
605 * Ordered so that for each i,
606 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
607 */
608 const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = {
609 VK_FORMAT_R32_SFLOAT,
610 VK_FORMAT_R32G32_SFLOAT,
611 VK_FORMAT_R8G8B8A8_UNORM,
612 VK_FORMAT_R16G16B16A16_UNORM,
613 VK_FORMAT_R16G16B16A16_SNORM,
614 VK_FORMAT_R16G16B16A16_UINT,
615 VK_FORMAT_R16G16B16A16_SINT,
616 VK_FORMAT_R32G32B32A32_SFLOAT,
617 VK_FORMAT_R8G8B8A8_UINT,
618 VK_FORMAT_R8G8B8A8_SINT,
619 VK_FORMAT_A2R10G10B10_UINT_PACK32,
620 VK_FORMAT_A2R10G10B10_SINT_PACK32,
621 };
622
623 unsigned radv_format_meta_fs_key(VkFormat format)
624 {
625 unsigned col_format = si_choose_spi_color_format(format, false, false);
626
627 assert(col_format != V_028714_SPI_SHADER_32_AR);
628 if (col_format >= V_028714_SPI_SHADER_32_AR)
629 --col_format; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
630
631 --col_format; /* Skip V_028714_SPI_SHADER_ZERO */
632 bool is_int8 = format_is_int8(format);
633 bool is_int10 = format_is_int10(format);
634
635 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
636 }
637
638 static void
639 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
640 unsigned *is_int8, unsigned *is_int10)
641 {
642 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
643 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
644 *is_int8 = 0;
645 *is_int10 = 0;
646
647 for (unsigned i = 0; i < subpass->color_count; ++i) {
648 struct radv_render_pass_attachment *attachment;
649
650 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
651 continue;
652
653 attachment = pass->attachments + subpass->color_attachments[i].attachment;
654
655 if (format_is_int8(attachment->format))
656 *is_int8 |= 1 << i;
657 if (format_is_int10(attachment->format))
658 *is_int10 |= 1 << i;
659 }
660 }
661
662 static void
663 radv_blend_check_commutativity(struct radv_blend_state *blend,
664 VkBlendOp op, VkBlendFactor src,
665 VkBlendFactor dst, unsigned chanmask)
666 {
667 /* Src factor is allowed when it does not depend on Dst. */
668 static const uint32_t src_allowed =
669 (1u << VK_BLEND_FACTOR_ONE) |
670 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
671 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
672 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
673 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
674 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
675 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
676 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
677 (1u << VK_BLEND_FACTOR_ZERO) |
678 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
679 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
680 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
681 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
682 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
683 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
684
685 if (dst == VK_BLEND_FACTOR_ONE &&
686 (src_allowed & (1u << src))) {
687 /* Addition is commutative, but floating point addition isn't
688 * associative: subtle changes can be introduced via different
689 * rounding. Be conservative, only enable for min and max.
690 */
691 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
692 blend->commutative_4bit |= chanmask;
693 }
694 }
695
696 static struct radv_blend_state
697 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
698 const VkGraphicsPipelineCreateInfo *pCreateInfo,
699 const struct radv_graphics_pipeline_create_info *extra)
700 {
701 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
702 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
703 struct radv_blend_state blend = {0};
704 unsigned mode = V_028808_CB_NORMAL;
705 int i;
706
707 if (!vkblend)
708 return blend;
709
710 if (extra && extra->custom_blend_mode) {
711 blend.single_cb_enable = true;
712 mode = extra->custom_blend_mode;
713 }
714 blend.cb_color_control = 0;
715 if (vkblend->logicOpEnable)
716 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
717 else
718 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
719
720 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
721 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
722 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
723 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
724 S_028B70_OFFSET_ROUND(1);
725
726 if (vkms && vkms->alphaToCoverageEnable) {
727 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
728 blend.need_src_alpha |= 0x1;
729 }
730
731 blend.cb_target_mask = 0;
732 for (i = 0; i < vkblend->attachmentCount; i++) {
733 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
734 unsigned blend_cntl = 0;
735 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
736 VkBlendOp eqRGB = att->colorBlendOp;
737 VkBlendFactor srcRGB = att->srcColorBlendFactor;
738 VkBlendFactor dstRGB = att->dstColorBlendFactor;
739 VkBlendOp eqA = att->alphaBlendOp;
740 VkBlendFactor srcA = att->srcAlphaBlendFactor;
741 VkBlendFactor dstA = att->dstAlphaBlendFactor;
742
743 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
744
745 if (!att->colorWriteMask)
746 continue;
747
748 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
749 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
750 if (!att->blendEnable) {
751 blend.cb_blend_control[i] = blend_cntl;
752 continue;
753 }
754
755 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
756 if (i == 0)
757 blend.mrt0_is_dual_src = true;
758
759 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
760 srcRGB = VK_BLEND_FACTOR_ONE;
761 dstRGB = VK_BLEND_FACTOR_ONE;
762 }
763 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
764 srcA = VK_BLEND_FACTOR_ONE;
765 dstA = VK_BLEND_FACTOR_ONE;
766 }
767
768 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
769 0x7 << (4 * i));
770 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
771 0x8 << (4 * i));
772
773 /* Blending optimizations for RB+.
774 * These transformations don't change the behavior.
775 *
776 * First, get rid of DST in the blend factors:
777 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
778 */
779 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
780 VK_BLEND_FACTOR_DST_COLOR,
781 VK_BLEND_FACTOR_SRC_COLOR);
782
783 si_blend_remove_dst(&eqA, &srcA, &dstA,
784 VK_BLEND_FACTOR_DST_COLOR,
785 VK_BLEND_FACTOR_SRC_COLOR);
786
787 si_blend_remove_dst(&eqA, &srcA, &dstA,
788 VK_BLEND_FACTOR_DST_ALPHA,
789 VK_BLEND_FACTOR_SRC_ALPHA);
790
791 /* Look up the ideal settings from tables. */
792 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
793 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
794 srcA_opt = si_translate_blend_opt_factor(srcA, true);
795 dstA_opt = si_translate_blend_opt_factor(dstA, true);
796
797 /* Handle interdependencies. */
798 if (si_blend_factor_uses_dst(srcRGB))
799 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
800 if (si_blend_factor_uses_dst(srcA))
801 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
802
803 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
804 (dstRGB == VK_BLEND_FACTOR_ZERO ||
805 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
806 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
807 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
808
809 /* Set the final value. */
810 blend.sx_mrt_blend_opt[i] =
811 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
812 S_028760_COLOR_DST_OPT(dstRGB_opt) |
813 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
814 S_028760_ALPHA_SRC_OPT(srcA_opt) |
815 S_028760_ALPHA_DST_OPT(dstA_opt) |
816 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
817 blend_cntl |= S_028780_ENABLE(1);
818
819 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
820 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
821 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
822 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
823 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
824 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
825 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
826 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
827 }
828 blend.cb_blend_control[i] = blend_cntl;
829
830 blend.blend_enable_4bit |= 0xfu << (i * 4);
831
832 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
833 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
834 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
835 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
836 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
837 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
838 blend.need_src_alpha |= 1 << i;
839 }
840 for (i = vkblend->attachmentCount; i < 8; i++) {
841 blend.cb_blend_control[i] = 0;
842 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
843 }
844
845 if (pipeline->device->physical_device->rad_info.has_rbplus) {
846 /* Disable RB+ blend optimizations for dual source blending. */
847 if (blend.mrt0_is_dual_src) {
848 for (i = 0; i < 8; i++) {
849 blend.sx_mrt_blend_opt[i] =
850 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
851 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
852 }
853 }
854
855 /* RB+ doesn't work with dual source blending, logic op and
856 * RESOLVE.
857 */
858 if (blend.mrt0_is_dual_src || vkblend->logicOpEnable ||
859 mode == V_028808_CB_RESOLVE)
860 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
861 }
862
863 if (blend.cb_target_mask)
864 blend.cb_color_control |= S_028808_MODE(mode);
865 else
866 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
867
868 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
869 return blend;
870 }
871
872 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
873 {
874 switch (op) {
875 case VK_STENCIL_OP_KEEP:
876 return V_02842C_STENCIL_KEEP;
877 case VK_STENCIL_OP_ZERO:
878 return V_02842C_STENCIL_ZERO;
879 case VK_STENCIL_OP_REPLACE:
880 return V_02842C_STENCIL_REPLACE_TEST;
881 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
882 return V_02842C_STENCIL_ADD_CLAMP;
883 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
884 return V_02842C_STENCIL_SUB_CLAMP;
885 case VK_STENCIL_OP_INVERT:
886 return V_02842C_STENCIL_INVERT;
887 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
888 return V_02842C_STENCIL_ADD_WRAP;
889 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
890 return V_02842C_STENCIL_SUB_WRAP;
891 default:
892 return 0;
893 }
894 }
895
896 static uint32_t si_translate_fill(VkPolygonMode func)
897 {
898 switch(func) {
899 case VK_POLYGON_MODE_FILL:
900 return V_028814_X_DRAW_TRIANGLES;
901 case VK_POLYGON_MODE_LINE:
902 return V_028814_X_DRAW_LINES;
903 case VK_POLYGON_MODE_POINT:
904 return V_028814_X_DRAW_POINTS;
905 default:
906 assert(0);
907 return V_028814_X_DRAW_POINTS;
908 }
909 }
910
911 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo *vkms)
912 {
913 uint32_t num_samples = vkms->rasterizationSamples;
914 uint32_t ps_iter_samples = 1;
915
916 if (vkms->sampleShadingEnable) {
917 ps_iter_samples = ceil(vkms->minSampleShading * num_samples);
918 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
919 }
920 return ps_iter_samples;
921 }
922
923 static bool
924 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
925 {
926 return pCreateInfo->depthTestEnable &&
927 pCreateInfo->depthWriteEnable &&
928 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
929 }
930
931 static bool
932 radv_writes_stencil(const VkStencilOpState *state)
933 {
934 return state->writeMask &&
935 (state->failOp != VK_STENCIL_OP_KEEP ||
936 state->passOp != VK_STENCIL_OP_KEEP ||
937 state->depthFailOp != VK_STENCIL_OP_KEEP);
938 }
939
940 static bool
941 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
942 {
943 return pCreateInfo->stencilTestEnable &&
944 (radv_writes_stencil(&pCreateInfo->front) ||
945 radv_writes_stencil(&pCreateInfo->back));
946 }
947
948 static bool
949 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
950 {
951 return radv_is_depth_write_enabled(pCreateInfo) ||
952 radv_is_stencil_write_enabled(pCreateInfo);
953 }
954
955 static bool
956 radv_order_invariant_stencil_op(VkStencilOp op)
957 {
958 /* REPLACE is normally order invariant, except when the stencil
959 * reference value is written by the fragment shader. Tracking this
960 * interaction does not seem worth the effort, so be conservative.
961 */
962 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
963 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
964 op != VK_STENCIL_OP_REPLACE;
965 }
966
967 static bool
968 radv_order_invariant_stencil_state(const VkStencilOpState *state)
969 {
970 /* Compute whether, assuming Z writes are disabled, this stencil state
971 * is order invariant in the sense that the set of passing fragments as
972 * well as the final stencil buffer result does not depend on the order
973 * of fragments.
974 */
975 return !state->writeMask ||
976 /* The following assumes that Z writes are disabled. */
977 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
978 radv_order_invariant_stencil_op(state->passOp) &&
979 radv_order_invariant_stencil_op(state->depthFailOp)) ||
980 (state->compareOp == VK_COMPARE_OP_NEVER &&
981 radv_order_invariant_stencil_op(state->failOp));
982 }
983
984 static bool
985 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
986 struct radv_blend_state *blend,
987 const VkGraphicsPipelineCreateInfo *pCreateInfo)
988 {
989 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
990 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
991 unsigned colormask = blend->cb_target_enabled_4bit;
992
993 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
994 return false;
995
996 /* Be conservative if a logic operation is enabled with color buffers. */
997 if (colormask && pCreateInfo->pColorBlendState->logicOpEnable)
998 return false;
999
1000 /* Default depth/stencil invariance when no attachment is bound. */
1001 struct radv_dsa_order_invariance dsa_order_invariant = {
1002 .zs = true, .pass_set = true
1003 };
1004
1005 if (pCreateInfo->pDepthStencilState &&
1006 subpass->depth_stencil_attachment) {
1007 const VkPipelineDepthStencilStateCreateInfo *vkds =
1008 pCreateInfo->pDepthStencilState;
1009 struct radv_render_pass_attachment *attachment =
1010 pass->attachments + subpass->depth_stencil_attachment->attachment;
1011 bool has_stencil = vk_format_is_stencil(attachment->format);
1012 struct radv_dsa_order_invariance order_invariance[2];
1013 struct radv_shader_variant *ps =
1014 pipeline->shaders[MESA_SHADER_FRAGMENT];
1015
1016 /* Compute depth/stencil order invariance in order to know if
1017 * it's safe to enable out-of-order.
1018 */
1019 bool zfunc_is_ordered =
1020 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
1021 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
1022 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
1023 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
1024 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
1025
1026 bool nozwrite_and_order_invariant_stencil =
1027 !radv_is_ds_write_enabled(vkds) ||
1028 (!radv_is_depth_write_enabled(vkds) &&
1029 radv_order_invariant_stencil_state(&vkds->front) &&
1030 radv_order_invariant_stencil_state(&vkds->back));
1031
1032 order_invariance[1].zs =
1033 nozwrite_and_order_invariant_stencil ||
1034 (!radv_is_stencil_write_enabled(vkds) &&
1035 zfunc_is_ordered);
1036 order_invariance[0].zs =
1037 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
1038
1039 order_invariance[1].pass_set =
1040 nozwrite_and_order_invariant_stencil ||
1041 (!radv_is_stencil_write_enabled(vkds) &&
1042 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1043 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
1044 order_invariance[0].pass_set =
1045 !radv_is_depth_write_enabled(vkds) ||
1046 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1047 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
1048
1049 dsa_order_invariant = order_invariance[has_stencil];
1050 if (!dsa_order_invariant.zs)
1051 return false;
1052
1053 /* The set of PS invocations is always order invariant,
1054 * except when early Z/S tests are requested.
1055 */
1056 if (ps &&
1057 ps->info.ps.writes_memory &&
1058 ps->info.ps.early_fragment_test &&
1059 !dsa_order_invariant.pass_set)
1060 return false;
1061
1062 /* Determine if out-of-order rasterization should be disabled
1063 * when occlusion queries are used.
1064 */
1065 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
1066 !dsa_order_invariant.pass_set;
1067 }
1068
1069 /* No color buffers are enabled for writing. */
1070 if (!colormask)
1071 return true;
1072
1073 unsigned blendmask = colormask & blend->blend_enable_4bit;
1074
1075 if (blendmask) {
1076 /* Only commutative blending. */
1077 if (blendmask & ~blend->commutative_4bit)
1078 return false;
1079
1080 if (!dsa_order_invariant.pass_set)
1081 return false;
1082 }
1083
1084 if (colormask & ~blendmask)
1085 return false;
1086
1087 return true;
1088 }
1089
1090 static void
1091 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1092 struct radv_blend_state *blend,
1093 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1094 {
1095 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
1096 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1097 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1098 bool out_of_order_rast = false;
1099 int ps_iter_samples = 1;
1100 uint32_t mask = 0xffff;
1101
1102 if (vkms) {
1103 ms->num_samples = vkms->rasterizationSamples;
1104
1105 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1106 *
1107 * "Sample shading is enabled for a graphics pipeline:
1108 *
1109 * - If the interface of the fragment shader entry point of the
1110 * graphics pipeline includes an input variable decorated
1111 * with SampleId or SamplePosition. In this case
1112 * minSampleShadingFactor takes the value 1.0.
1113 * - Else if the sampleShadingEnable member of the
1114 * VkPipelineMultisampleStateCreateInfo structure specified
1115 * when creating the graphics pipeline is set to VK_TRUE. In
1116 * this case minSampleShadingFactor takes the value of
1117 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1118 *
1119 * Otherwise, sample shading is considered disabled."
1120 */
1121 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.force_persample) {
1122 ps_iter_samples = ms->num_samples;
1123 } else {
1124 ps_iter_samples = radv_pipeline_get_ps_iter_samples(vkms);
1125 }
1126 } else {
1127 ms->num_samples = 1;
1128 }
1129
1130 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1131 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1132 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1133 /* Out-of-order rasterization is explicitly enabled by the
1134 * application.
1135 */
1136 out_of_order_rast = true;
1137 } else {
1138 /* Determine if the driver can enable out-of-order
1139 * rasterization internally.
1140 */
1141 out_of_order_rast =
1142 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1143 }
1144
1145 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1146 ms->pa_sc_aa_config = 0;
1147 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1148 S_028804_INCOHERENT_EQAA_READS(1) |
1149 S_028804_INTERPOLATE_COMP_Z(1) |
1150 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1151 ms->pa_sc_mode_cntl_1 =
1152 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1153 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1154 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
1155 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1156 /* always 1: */
1157 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1158 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1159 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1160 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1161 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1162 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1163 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1164 S_028A48_VPORT_SCISSOR_ENABLE(1);
1165
1166 if (ms->num_samples > 1) {
1167 unsigned log_samples = util_logbase2(ms->num_samples);
1168 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1169 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1170 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1171 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_samples) |
1172 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1173 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1174 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1175 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1176 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) |
1177 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1178 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1179 if (ps_iter_samples > 1)
1180 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1181 }
1182
1183 if (vkms && vkms->pSampleMask) {
1184 mask = vkms->pSampleMask[0] & 0xffff;
1185 }
1186
1187 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1188 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1189 }
1190
1191 static bool
1192 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1193 {
1194 switch (topology) {
1195 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1196 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1197 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1198 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1199 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1200 return false;
1201 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1202 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1203 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1204 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1205 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1206 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1207 return true;
1208 default:
1209 unreachable("unhandled primitive type");
1210 }
1211 }
1212
1213 static uint32_t
1214 si_translate_prim(enum VkPrimitiveTopology topology)
1215 {
1216 switch (topology) {
1217 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1218 return V_008958_DI_PT_POINTLIST;
1219 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1220 return V_008958_DI_PT_LINELIST;
1221 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1222 return V_008958_DI_PT_LINESTRIP;
1223 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1224 return V_008958_DI_PT_TRILIST;
1225 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1226 return V_008958_DI_PT_TRISTRIP;
1227 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1228 return V_008958_DI_PT_TRIFAN;
1229 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1230 return V_008958_DI_PT_LINELIST_ADJ;
1231 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1232 return V_008958_DI_PT_LINESTRIP_ADJ;
1233 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1234 return V_008958_DI_PT_TRILIST_ADJ;
1235 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1236 return V_008958_DI_PT_TRISTRIP_ADJ;
1237 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1238 return V_008958_DI_PT_PATCH;
1239 default:
1240 assert(0);
1241 return 0;
1242 }
1243 }
1244
1245 static uint32_t
1246 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1247 {
1248 switch (gl_prim) {
1249 case 0: /* GL_POINTS */
1250 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1251 case 1: /* GL_LINES */
1252 case 3: /* GL_LINE_STRIP */
1253 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1254 case 0x8E7A: /* GL_ISOLINES */
1255 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1256
1257 case 4: /* GL_TRIANGLES */
1258 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1259 case 5: /* GL_TRIANGLE_STRIP */
1260 case 7: /* GL_QUADS */
1261 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1262 default:
1263 assert(0);
1264 return 0;
1265 }
1266 }
1267
1268 static uint32_t
1269 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1270 {
1271 switch (topology) {
1272 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1273 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1274 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1275 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1276 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1277 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1278 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1279 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1280 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1281 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1282 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1283 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1284 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1285 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1286 default:
1287 assert(0);
1288 return 0;
1289 }
1290 }
1291
1292 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1293 {
1294 switch(state) {
1295 case VK_DYNAMIC_STATE_VIEWPORT:
1296 return RADV_DYNAMIC_VIEWPORT;
1297 case VK_DYNAMIC_STATE_SCISSOR:
1298 return RADV_DYNAMIC_SCISSOR;
1299 case VK_DYNAMIC_STATE_LINE_WIDTH:
1300 return RADV_DYNAMIC_LINE_WIDTH;
1301 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1302 return RADV_DYNAMIC_DEPTH_BIAS;
1303 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1304 return RADV_DYNAMIC_BLEND_CONSTANTS;
1305 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1306 return RADV_DYNAMIC_DEPTH_BOUNDS;
1307 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1308 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1309 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1310 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1311 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1312 return RADV_DYNAMIC_STENCIL_REFERENCE;
1313 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1314 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1315 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
1316 return RADV_DYNAMIC_SAMPLE_LOCATIONS;
1317 default:
1318 unreachable("Unhandled dynamic state");
1319 }
1320 }
1321
1322 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1323 {
1324 uint32_t states = RADV_DYNAMIC_ALL;
1325
1326 /* If rasterization is disabled we do not care about any of the dynamic states,
1327 * since they are all rasterization related only. */
1328 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1329 return 0;
1330
1331 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1332 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1333
1334 if (!pCreateInfo->pDepthStencilState ||
1335 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1336 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1337
1338 if (!pCreateInfo->pDepthStencilState ||
1339 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1340 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1341 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1342 RADV_DYNAMIC_STENCIL_REFERENCE);
1343
1344 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1345 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1346
1347 if (!pCreateInfo->pMultisampleState ||
1348 !vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1349 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT))
1350 states &= ~RADV_DYNAMIC_SAMPLE_LOCATIONS;
1351
1352 /* TODO: blend constants & line width. */
1353
1354 return states;
1355 }
1356
1357
1358 static void
1359 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1360 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1361 {
1362 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1363 uint32_t states = needed_states;
1364 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1365 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1366
1367 pipeline->dynamic_state = default_dynamic_state;
1368 pipeline->graphics.needed_dynamic_state = needed_states;
1369
1370 if (pCreateInfo->pDynamicState) {
1371 /* Remove all of the states that are marked as dynamic */
1372 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1373 for (uint32_t s = 0; s < count; s++)
1374 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1375 }
1376
1377 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1378
1379 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1380 assert(pCreateInfo->pViewportState);
1381
1382 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1383 if (states & RADV_DYNAMIC_VIEWPORT) {
1384 typed_memcpy(dynamic->viewport.viewports,
1385 pCreateInfo->pViewportState->pViewports,
1386 pCreateInfo->pViewportState->viewportCount);
1387 }
1388 }
1389
1390 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1391 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1392 if (states & RADV_DYNAMIC_SCISSOR) {
1393 typed_memcpy(dynamic->scissor.scissors,
1394 pCreateInfo->pViewportState->pScissors,
1395 pCreateInfo->pViewportState->scissorCount);
1396 }
1397 }
1398
1399 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1400 assert(pCreateInfo->pRasterizationState);
1401 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1402 }
1403
1404 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1405 assert(pCreateInfo->pRasterizationState);
1406 dynamic->depth_bias.bias =
1407 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1408 dynamic->depth_bias.clamp =
1409 pCreateInfo->pRasterizationState->depthBiasClamp;
1410 dynamic->depth_bias.slope =
1411 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1412 }
1413
1414 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1415 *
1416 * pColorBlendState is [...] NULL if the pipeline has rasterization
1417 * disabled or if the subpass of the render pass the pipeline is
1418 * created against does not use any color attachments.
1419 */
1420 if (subpass->has_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1421 assert(pCreateInfo->pColorBlendState);
1422 typed_memcpy(dynamic->blend_constants,
1423 pCreateInfo->pColorBlendState->blendConstants, 4);
1424 }
1425
1426 /* If there is no depthstencil attachment, then don't read
1427 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1428 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1429 * no need to override the depthstencil defaults in
1430 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1431 *
1432 * Section 9.2 of the Vulkan 1.0.15 spec says:
1433 *
1434 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1435 * disabled or if the subpass of the render pass the pipeline is created
1436 * against does not use a depth/stencil attachment.
1437 */
1438 if (needed_states && subpass->depth_stencil_attachment) {
1439 assert(pCreateInfo->pDepthStencilState);
1440
1441 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1442 dynamic->depth_bounds.min =
1443 pCreateInfo->pDepthStencilState->minDepthBounds;
1444 dynamic->depth_bounds.max =
1445 pCreateInfo->pDepthStencilState->maxDepthBounds;
1446 }
1447
1448 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1449 dynamic->stencil_compare_mask.front =
1450 pCreateInfo->pDepthStencilState->front.compareMask;
1451 dynamic->stencil_compare_mask.back =
1452 pCreateInfo->pDepthStencilState->back.compareMask;
1453 }
1454
1455 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1456 dynamic->stencil_write_mask.front =
1457 pCreateInfo->pDepthStencilState->front.writeMask;
1458 dynamic->stencil_write_mask.back =
1459 pCreateInfo->pDepthStencilState->back.writeMask;
1460 }
1461
1462 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1463 dynamic->stencil_reference.front =
1464 pCreateInfo->pDepthStencilState->front.reference;
1465 dynamic->stencil_reference.back =
1466 pCreateInfo->pDepthStencilState->back.reference;
1467 }
1468 }
1469
1470 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1471 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1472 if (needed_states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1473 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1474 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1475 typed_memcpy(dynamic->discard_rectangle.rectangles,
1476 discard_rectangle_info->pDiscardRectangles,
1477 discard_rectangle_info->discardRectangleCount);
1478 }
1479 }
1480
1481 if (needed_states & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
1482 const VkPipelineSampleLocationsStateCreateInfoEXT *sample_location_info =
1483 vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1484 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1485 /* If sampleLocationsEnable is VK_FALSE, the default sample
1486 * locations are used and the values specified in
1487 * sampleLocationsInfo are ignored.
1488 */
1489 if (sample_location_info->sampleLocationsEnable) {
1490 const VkSampleLocationsInfoEXT *pSampleLocationsInfo =
1491 &sample_location_info->sampleLocationsInfo;
1492
1493 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
1494
1495 dynamic->sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
1496 dynamic->sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
1497 dynamic->sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
1498 typed_memcpy(&dynamic->sample_location.locations[0],
1499 pSampleLocationsInfo->pSampleLocations,
1500 pSampleLocationsInfo->sampleLocationsCount);
1501 }
1502 }
1503
1504 pipeline->dynamic_state.mask = states;
1505 }
1506
1507 static void
1508 gfx9_get_gs_info(const struct radv_pipeline_key *key,
1509 const struct radv_pipeline *pipeline,
1510 nir_shader **nir,
1511 struct radv_shader_info *infos,
1512 struct gfx9_gs_info *out)
1513 {
1514 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1515 struct radv_es_output_info *es_info;
1516 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1517 es_info = nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1518 else
1519 es_info = nir[MESA_SHADER_TESS_CTRL] ?
1520 &infos[MESA_SHADER_TESS_EVAL].tes.es_info :
1521 &infos[MESA_SHADER_VERTEX].vs.es_info;
1522
1523 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1524 bool uses_adjacency;
1525 switch(key->topology) {
1526 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1527 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1528 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1529 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1530 uses_adjacency = true;
1531 break;
1532 default:
1533 uses_adjacency = false;
1534 break;
1535 }
1536
1537 /* All these are in dwords: */
1538 /* We can't allow using the whole LDS, because GS waves compete with
1539 * other shader stages for LDS space. */
1540 const unsigned max_lds_size = 8 * 1024;
1541 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1542 unsigned esgs_lds_size;
1543
1544 /* All these are per subgroup: */
1545 const unsigned max_out_prims = 32 * 1024;
1546 const unsigned max_es_verts = 255;
1547 const unsigned ideal_gs_prims = 64;
1548 unsigned max_gs_prims, gs_prims;
1549 unsigned min_es_verts, es_verts, worst_case_es_verts;
1550
1551 if (uses_adjacency || gs_num_invocations > 1)
1552 max_gs_prims = 127 / gs_num_invocations;
1553 else
1554 max_gs_prims = 255;
1555
1556 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1557 * Make sure we don't go over the maximum value.
1558 */
1559 if (gs_info->gs.vertices_out > 0) {
1560 max_gs_prims = MIN2(max_gs_prims,
1561 max_out_prims /
1562 (gs_info->gs.vertices_out * gs_num_invocations));
1563 }
1564 assert(max_gs_prims > 0);
1565
1566 /* If the primitive has adjacency, halve the number of vertices
1567 * that will be reused in multiple primitives.
1568 */
1569 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1570
1571 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1572 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1573
1574 /* Compute ESGS LDS size based on the worst case number of ES vertices
1575 * needed to create the target number of GS prims per subgroup.
1576 */
1577 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1578
1579 /* If total LDS usage is too big, refactor partitions based on ratio
1580 * of ESGS item sizes.
1581 */
1582 if (esgs_lds_size > max_lds_size) {
1583 /* Our target GS Prims Per Subgroup was too large. Calculate
1584 * the maximum number of GS Prims Per Subgroup that will fit
1585 * into LDS, capped by the maximum that the hardware can support.
1586 */
1587 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1588 max_gs_prims);
1589 assert(gs_prims > 0);
1590 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1591 max_es_verts);
1592
1593 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1594 assert(esgs_lds_size <= max_lds_size);
1595 }
1596
1597 /* Now calculate remaining ESGS information. */
1598 if (esgs_lds_size)
1599 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1600 else
1601 es_verts = max_es_verts;
1602
1603 /* Vertices for adjacency primitives are not always reused, so restore
1604 * it for ES_VERTS_PER_SUBGRP.
1605 */
1606 min_es_verts = gs_info->gs.vertices_in;
1607
1608 /* For normal primitives, the VGT only checks if they are past the ES
1609 * verts per subgroup after allocating a full GS primitive and if they
1610 * are, kick off a new subgroup. But if those additional ES verts are
1611 * unique (e.g. not reused) we need to make sure there is enough LDS
1612 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1613 */
1614 es_verts -= min_es_verts - 1;
1615
1616 uint32_t es_verts_per_subgroup = es_verts;
1617 uint32_t gs_prims_per_subgroup = gs_prims;
1618 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1619 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1620 out->lds_size = align(esgs_lds_size, 128) / 128;
1621 out->vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1622 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1623 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1624 out->vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1625 out->vgt_esgs_ring_itemsize = esgs_itemsize;
1626 assert(max_prims_per_subgroup <= max_out_prims);
1627 }
1628
1629 static void clamp_gsprims_to_esverts(unsigned *max_gsprims, unsigned max_esverts,
1630 unsigned min_verts_per_prim, bool use_adjacency)
1631 {
1632 unsigned max_reuse = max_esverts - min_verts_per_prim;
1633 if (use_adjacency)
1634 max_reuse /= 2;
1635 *max_gsprims = MIN2(*max_gsprims, 1 + max_reuse);
1636 }
1637
1638 static unsigned
1639 radv_get_num_input_vertices(nir_shader **nir)
1640 {
1641 if (nir[MESA_SHADER_GEOMETRY]) {
1642 nir_shader *gs = nir[MESA_SHADER_GEOMETRY];
1643
1644 return gs->info.gs.vertices_in;
1645 }
1646
1647 if (nir[MESA_SHADER_TESS_CTRL]) {
1648 nir_shader *tes = nir[MESA_SHADER_TESS_EVAL];
1649
1650 if (tes->info.tess.point_mode)
1651 return 1;
1652 if (tes->info.tess.primitive_mode == GL_ISOLINES)
1653 return 2;
1654 return 3;
1655 }
1656
1657 return 3;
1658 }
1659
1660 static void
1661 gfx10_get_ngg_info(const struct radv_pipeline_key *key,
1662 struct radv_pipeline *pipeline,
1663 nir_shader **nir,
1664 struct radv_shader_info *infos,
1665 struct gfx10_ngg_info *ngg)
1666 {
1667 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1668 struct radv_es_output_info *es_info =
1669 nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1670 unsigned gs_type = nir[MESA_SHADER_GEOMETRY] ? MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX;
1671 unsigned max_verts_per_prim = radv_get_num_input_vertices(nir);
1672 unsigned min_verts_per_prim =
1673 gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1;
1674 unsigned gs_num_invocations = nir[MESA_SHADER_GEOMETRY] ? MAX2(gs_info->gs.invocations, 1) : 1;
1675 bool uses_adjacency;
1676 switch(key->topology) {
1677 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1678 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1679 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1680 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1681 uses_adjacency = true;
1682 break;
1683 default:
1684 uses_adjacency = false;
1685 break;
1686 }
1687
1688 /* All these are in dwords: */
1689 /* We can't allow using the whole LDS, because GS waves compete with
1690 * other shader stages for LDS space.
1691 *
1692 * TODO: We should really take the shader's internal LDS use into
1693 * account. The linker will fail if the size is greater than
1694 * 8K dwords.
1695 */
1696 const unsigned max_lds_size = 8 * 1024 - 768;
1697 const unsigned target_lds_size = max_lds_size;
1698 unsigned esvert_lds_size = 0;
1699 unsigned gsprim_lds_size = 0;
1700
1701 /* All these are per subgroup: */
1702 bool max_vert_out_per_gs_instance = false;
1703 unsigned max_esverts_base = 256;
1704 unsigned max_gsprims_base = 128; /* default prim group size clamp */
1705
1706 /* Hardware has the following non-natural restrictions on the value
1707 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1708 * the draw:
1709 * - at most 252 for any line input primitive type
1710 * - at most 251 for any quad input primitive type
1711 * - at most 251 for triangle strips with adjacency (this happens to
1712 * be the natural limit for triangle *lists* with adjacency)
1713 */
1714 max_esverts_base = MIN2(max_esverts_base, 251 + max_verts_per_prim - 1);
1715
1716 if (gs_type == MESA_SHADER_GEOMETRY) {
1717 unsigned max_out_verts_per_gsprim =
1718 gs_info->gs.vertices_out * gs_num_invocations;
1719
1720 if (max_out_verts_per_gsprim <= 256) {
1721 if (max_out_verts_per_gsprim) {
1722 max_gsprims_base = MIN2(max_gsprims_base,
1723 256 / max_out_verts_per_gsprim);
1724 }
1725 } else {
1726 /* Use special multi-cycling mode in which each GS
1727 * instance gets its own subgroup. Does not work with
1728 * tessellation. */
1729 max_vert_out_per_gs_instance = true;
1730 max_gsprims_base = 1;
1731 max_out_verts_per_gsprim = gs_info->gs.vertices_out;
1732 }
1733
1734 esvert_lds_size = es_info->esgs_itemsize / 4;
1735 gsprim_lds_size = (gs_info->gs.gsvs_vertex_size / 4 + 1) * max_out_verts_per_gsprim;
1736 } else {
1737 /* VS and TES. */
1738 /* LDS size for passing data from GS to ES. */
1739 struct radv_streamout_info *so_info = nir[MESA_SHADER_TESS_CTRL]
1740 ? &infos[MESA_SHADER_TESS_EVAL].so
1741 : &infos[MESA_SHADER_VERTEX].so;
1742
1743 if (so_info->num_outputs)
1744 esvert_lds_size = 4 * so_info->num_outputs + 1;
1745
1746 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1747 * corresponding to the ES thread of the provoking vertex. All
1748 * ES threads load and export PrimitiveID for their thread.
1749 */
1750 if (!nir[MESA_SHADER_TESS_CTRL] &&
1751 infos[MESA_SHADER_VERTEX].vs.outinfo.export_prim_id)
1752 esvert_lds_size = MAX2(esvert_lds_size, 1);
1753 }
1754
1755 unsigned max_gsprims = max_gsprims_base;
1756 unsigned max_esverts = max_esverts_base;
1757
1758 if (esvert_lds_size)
1759 max_esverts = MIN2(max_esverts, target_lds_size / esvert_lds_size);
1760 if (gsprim_lds_size)
1761 max_gsprims = MIN2(max_gsprims, target_lds_size / gsprim_lds_size);
1762
1763 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1764 clamp_gsprims_to_esverts(&max_gsprims, max_esverts, min_verts_per_prim, uses_adjacency);
1765 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1766
1767 if (esvert_lds_size || gsprim_lds_size) {
1768 /* Now that we have a rough proportionality between esverts
1769 * and gsprims based on the primitive type, scale both of them
1770 * down simultaneously based on required LDS space.
1771 *
1772 * We could be smarter about this if we knew how much vertex
1773 * reuse to expect.
1774 */
1775 unsigned lds_total = max_esverts * esvert_lds_size +
1776 max_gsprims * gsprim_lds_size;
1777 if (lds_total > target_lds_size) {
1778 max_esverts = max_esverts * target_lds_size / lds_total;
1779 max_gsprims = max_gsprims * target_lds_size / lds_total;
1780
1781 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1782 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1783 min_verts_per_prim, uses_adjacency);
1784 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1785 }
1786 }
1787
1788 /* Round up towards full wave sizes for better ALU utilization. */
1789 if (!max_vert_out_per_gs_instance) {
1790 unsigned orig_max_esverts;
1791 unsigned orig_max_gsprims;
1792 unsigned wavesize;
1793
1794 if (gs_type == MESA_SHADER_GEOMETRY) {
1795 wavesize = gs_info->wave_size;
1796 } else {
1797 wavesize = nir[MESA_SHADER_TESS_CTRL]
1798 ? infos[MESA_SHADER_TESS_EVAL].wave_size
1799 : infos[MESA_SHADER_VERTEX].wave_size;
1800 }
1801
1802 do {
1803 orig_max_esverts = max_esverts;
1804 orig_max_gsprims = max_gsprims;
1805
1806 max_esverts = align(max_esverts, wavesize);
1807 max_esverts = MIN2(max_esverts, max_esverts_base);
1808 if (esvert_lds_size)
1809 max_esverts = MIN2(max_esverts,
1810 (max_lds_size - max_gsprims * gsprim_lds_size) /
1811 esvert_lds_size);
1812 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1813
1814 max_gsprims = align(max_gsprims, wavesize);
1815 max_gsprims = MIN2(max_gsprims, max_gsprims_base);
1816 if (gsprim_lds_size)
1817 max_gsprims = MIN2(max_gsprims,
1818 (max_lds_size - max_esverts * esvert_lds_size) /
1819 gsprim_lds_size);
1820 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1821 min_verts_per_prim, uses_adjacency);
1822 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1823 } while (orig_max_esverts != max_esverts || orig_max_gsprims != max_gsprims);
1824 }
1825
1826 /* Hardware restriction: minimum value of max_esverts */
1827 max_esverts = MAX2(max_esverts, 23 + max_verts_per_prim);
1828
1829 unsigned max_out_vertices =
1830 max_vert_out_per_gs_instance ? gs_info->gs.vertices_out :
1831 gs_type == MESA_SHADER_GEOMETRY ?
1832 max_gsprims * gs_num_invocations * gs_info->gs.vertices_out :
1833 max_esverts;
1834 assert(max_out_vertices <= 256);
1835
1836 unsigned prim_amp_factor = 1;
1837 if (gs_type == MESA_SHADER_GEOMETRY) {
1838 /* Number of output primitives per GS input primitive after
1839 * GS instancing. */
1840 prim_amp_factor = gs_info->gs.vertices_out;
1841 }
1842
1843 /* The GE only checks against the maximum number of ES verts after
1844 * allocating a full GS primitive. So we need to ensure that whenever
1845 * this check passes, there is enough space for a full primitive without
1846 * vertex reuse.
1847 */
1848 ngg->hw_max_esverts = max_esverts - max_verts_per_prim + 1;
1849 ngg->max_gsprims = max_gsprims;
1850 ngg->max_out_verts = max_out_vertices;
1851 ngg->prim_amp_factor = prim_amp_factor;
1852 ngg->max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
1853 ngg->ngg_emit_size = max_gsprims * gsprim_lds_size;
1854 ngg->esgs_ring_size = 4 * max_esverts * esvert_lds_size;
1855
1856 if (gs_type == MESA_SHADER_GEOMETRY) {
1857 ngg->vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
1858 } else {
1859 ngg->vgt_esgs_ring_itemsize = 1;
1860 }
1861
1862 pipeline->graphics.esgs_ring_size = ngg->esgs_ring_size;
1863
1864 assert(ngg->hw_max_esverts >= 24); /* HW limitation */
1865 }
1866
1867 static void
1868 calculate_gs_ring_sizes(struct radv_pipeline *pipeline,
1869 const struct gfx9_gs_info *gs)
1870 {
1871 struct radv_device *device = pipeline->device;
1872 unsigned num_se = device->physical_device->rad_info.max_se;
1873 unsigned wave_size = 64;
1874 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1875 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1876 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1877 */
1878 unsigned gs_vertex_reuse =
1879 (device->physical_device->rad_info.chip_class >= GFX8 ? 32 : 16) * num_se;
1880 unsigned alignment = 256 * num_se;
1881 /* The maximum size is 63.999 MB per SE. */
1882 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1883 struct radv_shader_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1884
1885 /* Calculate the minimum size. */
1886 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1887 wave_size, alignment);
1888 /* These are recommended sizes, not minimum sizes. */
1889 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1890 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1891 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1892 gs_info->gs.max_gsvs_emit_size;
1893
1894 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1895 esgs_ring_size = align(esgs_ring_size, alignment);
1896 gsvs_ring_size = align(gsvs_ring_size, alignment);
1897
1898 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
1899 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1900
1901 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1902 }
1903
1904 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1905 unsigned *lds_size)
1906 {
1907 /* If tessellation is all offchip and on-chip GS isn't used, this
1908 * workaround is not needed.
1909 */
1910 return;
1911
1912 /* SPI barrier management bug:
1913 * Make sure we have at least 4k of LDS in use to avoid the bug.
1914 * It applies to workgroup sizes of more than one wavefront.
1915 */
1916 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1917 device->physical_device->rad_info.family == CHIP_KABINI)
1918 *lds_size = MAX2(*lds_size, 8);
1919 }
1920
1921 struct radv_shader_variant *
1922 radv_get_shader(struct radv_pipeline *pipeline,
1923 gl_shader_stage stage)
1924 {
1925 if (stage == MESA_SHADER_VERTEX) {
1926 if (pipeline->shaders[MESA_SHADER_VERTEX])
1927 return pipeline->shaders[MESA_SHADER_VERTEX];
1928 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1929 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1930 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1931 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1932 } else if (stage == MESA_SHADER_TESS_EVAL) {
1933 if (!radv_pipeline_has_tess(pipeline))
1934 return NULL;
1935 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1936 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1937 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1938 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1939 }
1940 return pipeline->shaders[stage];
1941 }
1942
1943 static struct radv_tessellation_state
1944 calculate_tess_state(struct radv_pipeline *pipeline,
1945 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1946 {
1947 unsigned num_tcs_input_cp;
1948 unsigned num_tcs_output_cp;
1949 unsigned lds_size;
1950 unsigned num_patches;
1951 struct radv_tessellation_state tess = {0};
1952
1953 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1954 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1955 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1956
1957 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
1958
1959 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
1960 assert(lds_size <= 65536);
1961 lds_size = align(lds_size, 512) / 512;
1962 } else {
1963 assert(lds_size <= 32768);
1964 lds_size = align(lds_size, 256) / 256;
1965 }
1966 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1967
1968 tess.lds_size = lds_size;
1969
1970 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1971 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1972 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1973 tess.num_patches = num_patches;
1974
1975 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
1976 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1977
1978 switch (tes->info.tes.primitive_mode) {
1979 case GL_TRIANGLES:
1980 type = V_028B6C_TESS_TRIANGLE;
1981 break;
1982 case GL_QUADS:
1983 type = V_028B6C_TESS_QUAD;
1984 break;
1985 case GL_ISOLINES:
1986 type = V_028B6C_TESS_ISOLINE;
1987 break;
1988 }
1989
1990 switch (tes->info.tes.spacing) {
1991 case TESS_SPACING_EQUAL:
1992 partitioning = V_028B6C_PART_INTEGER;
1993 break;
1994 case TESS_SPACING_FRACTIONAL_ODD:
1995 partitioning = V_028B6C_PART_FRAC_ODD;
1996 break;
1997 case TESS_SPACING_FRACTIONAL_EVEN:
1998 partitioning = V_028B6C_PART_FRAC_EVEN;
1999 break;
2000 default:
2001 break;
2002 }
2003
2004 bool ccw = tes->info.tes.ccw;
2005 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_origin_state =
2006 vk_find_struct_const(pCreateInfo->pTessellationState,
2007 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
2008
2009 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT)
2010 ccw = !ccw;
2011
2012 if (tes->info.tes.point_mode)
2013 topology = V_028B6C_OUTPUT_POINT;
2014 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
2015 topology = V_028B6C_OUTPUT_LINE;
2016 else if (ccw)
2017 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2018 else
2019 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2020
2021 if (pipeline->device->physical_device->rad_info.has_distributed_tess) {
2022 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
2023 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
2024 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
2025 else
2026 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
2027 } else
2028 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
2029
2030 tess.tf_param = S_028B6C_TYPE(type) |
2031 S_028B6C_PARTITIONING(partitioning) |
2032 S_028B6C_TOPOLOGY(topology) |
2033 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
2034
2035 return tess;
2036 }
2037
2038 static const struct radv_prim_vertex_count prim_size_table[] = {
2039 [V_008958_DI_PT_NONE] = {0, 0},
2040 [V_008958_DI_PT_POINTLIST] = {1, 1},
2041 [V_008958_DI_PT_LINELIST] = {2, 2},
2042 [V_008958_DI_PT_LINESTRIP] = {2, 1},
2043 [V_008958_DI_PT_TRILIST] = {3, 3},
2044 [V_008958_DI_PT_TRIFAN] = {3, 1},
2045 [V_008958_DI_PT_TRISTRIP] = {3, 1},
2046 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
2047 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
2048 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
2049 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
2050 [V_008958_DI_PT_RECTLIST] = {3, 3},
2051 [V_008958_DI_PT_LINELOOP] = {2, 1},
2052 [V_008958_DI_PT_POLYGON] = {3, 1},
2053 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
2054 };
2055
2056 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
2057 {
2058 if (radv_pipeline_has_gs(pipeline))
2059 if (radv_pipeline_has_ngg(pipeline))
2060 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
2061 else
2062 return &pipeline->gs_copy_shader->info.vs.outinfo;
2063 else if (radv_pipeline_has_tess(pipeline))
2064 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
2065 else
2066 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
2067 }
2068
2069 static void
2070 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
2071 {
2072 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
2073 int shader_count = 0;
2074
2075 if(shaders[MESA_SHADER_FRAGMENT]) {
2076 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
2077 }
2078 if(shaders[MESA_SHADER_GEOMETRY]) {
2079 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
2080 }
2081 if(shaders[MESA_SHADER_TESS_EVAL]) {
2082 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
2083 }
2084 if(shaders[MESA_SHADER_TESS_CTRL]) {
2085 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
2086 }
2087 if(shaders[MESA_SHADER_VERTEX]) {
2088 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
2089 }
2090
2091 if (shader_count > 1) {
2092 unsigned first = ordered_shaders[shader_count - 1]->info.stage;
2093 unsigned last = ordered_shaders[0]->info.stage;
2094
2095 if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
2096 ordered_shaders[1]->info.has_transform_feedback_varyings)
2097 nir_link_xfb_varyings(ordered_shaders[1], ordered_shaders[0]);
2098
2099 for (int i = 0; i < shader_count; ++i) {
2100 nir_variable_mode mask = 0;
2101
2102 if (ordered_shaders[i]->info.stage != first)
2103 mask = mask | nir_var_shader_in;
2104
2105 if (ordered_shaders[i]->info.stage != last)
2106 mask = mask | nir_var_shader_out;
2107
2108 nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
2109 radv_optimize_nir(ordered_shaders[i], false, false);
2110 }
2111 }
2112
2113 for (int i = 1; i < shader_count; ++i) {
2114 nir_lower_io_arrays_to_elements(ordered_shaders[i],
2115 ordered_shaders[i - 1]);
2116
2117 if (nir_link_opt_varyings(ordered_shaders[i],
2118 ordered_shaders[i - 1]))
2119 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2120
2121 nir_remove_dead_variables(ordered_shaders[i],
2122 nir_var_shader_out);
2123 nir_remove_dead_variables(ordered_shaders[i - 1],
2124 nir_var_shader_in);
2125
2126 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
2127 ordered_shaders[i - 1]);
2128
2129 nir_compact_varyings(ordered_shaders[i],
2130 ordered_shaders[i - 1], true);
2131
2132 if (progress) {
2133 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
2134 ac_lower_indirect_derefs(ordered_shaders[i],
2135 pipeline->device->physical_device->rad_info.chip_class);
2136 }
2137 radv_optimize_nir(ordered_shaders[i], false, false);
2138
2139 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
2140 ac_lower_indirect_derefs(ordered_shaders[i - 1],
2141 pipeline->device->physical_device->rad_info.chip_class);
2142 }
2143 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2144 }
2145 }
2146 }
2147
2148 static uint32_t
2149 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo *input_state,
2150 uint32_t attrib_binding)
2151 {
2152 for (uint32_t i = 0; i < input_state->vertexBindingDescriptionCount; i++) {
2153 const VkVertexInputBindingDescription *input_binding =
2154 &input_state->pVertexBindingDescriptions[i];
2155
2156 if (input_binding->binding == attrib_binding)
2157 return input_binding->stride;
2158 }
2159
2160 return 0;
2161 }
2162
2163 static struct radv_pipeline_key
2164 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
2165 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2166 const struct radv_blend_state *blend,
2167 bool has_view_index)
2168 {
2169 const VkPipelineVertexInputStateCreateInfo *input_state =
2170 pCreateInfo->pVertexInputState;
2171 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
2172 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
2173
2174 struct radv_pipeline_key key;
2175 memset(&key, 0, sizeof(key));
2176
2177 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
2178 key.optimisations_disabled = 1;
2179
2180 key.has_multiview_view_index = has_view_index;
2181
2182 uint32_t binding_input_rate = 0;
2183 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
2184 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
2185 if (input_state->pVertexBindingDescriptions[i].inputRate) {
2186 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
2187 binding_input_rate |= 1u << binding;
2188 instance_rate_divisors[binding] = 1;
2189 }
2190 }
2191 if (divisor_state) {
2192 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
2193 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
2194 divisor_state->pVertexBindingDivisors[i].divisor;
2195 }
2196 }
2197
2198 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
2199 const VkVertexInputAttributeDescription *desc =
2200 &input_state->pVertexAttributeDescriptions[i];
2201 const struct vk_format_description *format_desc;
2202 unsigned location = desc->location;
2203 unsigned binding = desc->binding;
2204 unsigned num_format, data_format;
2205 int first_non_void;
2206
2207 if (binding_input_rate & (1u << binding)) {
2208 key.instance_rate_inputs |= 1u << location;
2209 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
2210 }
2211
2212 format_desc = vk_format_description(desc->format);
2213 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2214
2215 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2216 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2217
2218 key.vertex_attribute_formats[location] = data_format | (num_format << 4);
2219 key.vertex_attribute_bindings[location] = desc->binding;
2220 key.vertex_attribute_offsets[location] = desc->offset;
2221 key.vertex_attribute_strides[location] = radv_get_attrib_stride(input_state, desc->binding);
2222
2223 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8 &&
2224 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
2225 VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
2226 uint64_t adjust;
2227 switch(format) {
2228 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2229 case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
2230 adjust = RADV_ALPHA_ADJUST_SNORM;
2231 break;
2232 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2233 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
2234 adjust = RADV_ALPHA_ADJUST_SSCALED;
2235 break;
2236 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2237 case VK_FORMAT_A2B10G10R10_SINT_PACK32:
2238 adjust = RADV_ALPHA_ADJUST_SINT;
2239 break;
2240 default:
2241 adjust = 0;
2242 break;
2243 }
2244 key.vertex_alpha_adjust |= adjust << (2 * location);
2245 }
2246
2247 switch (desc->format) {
2248 case VK_FORMAT_B8G8R8A8_UNORM:
2249 case VK_FORMAT_B8G8R8A8_SNORM:
2250 case VK_FORMAT_B8G8R8A8_USCALED:
2251 case VK_FORMAT_B8G8R8A8_SSCALED:
2252 case VK_FORMAT_B8G8R8A8_UINT:
2253 case VK_FORMAT_B8G8R8A8_SINT:
2254 case VK_FORMAT_B8G8R8A8_SRGB:
2255 case VK_FORMAT_A2R10G10B10_UNORM_PACK32:
2256 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2257 case VK_FORMAT_A2R10G10B10_USCALED_PACK32:
2258 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2259 case VK_FORMAT_A2R10G10B10_UINT_PACK32:
2260 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2261 key.vertex_post_shuffle |= 1 << location;
2262 break;
2263 default:
2264 break;
2265 }
2266 }
2267
2268 if (pCreateInfo->pTessellationState)
2269 key.tess_input_vertices = pCreateInfo->pTessellationState->patchControlPoints;
2270
2271
2272 if (pCreateInfo->pMultisampleState &&
2273 pCreateInfo->pMultisampleState->rasterizationSamples > 1) {
2274 uint32_t num_samples = pCreateInfo->pMultisampleState->rasterizationSamples;
2275 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo->pMultisampleState);
2276 key.num_samples = num_samples;
2277 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
2278 }
2279
2280 key.col_format = blend->spi_shader_col_format;
2281 if (pipeline->device->physical_device->rad_info.chip_class < GFX8)
2282 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
2283
2284 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10)
2285 key.topology = pCreateInfo->pInputAssemblyState->topology;
2286
2287 return key;
2288 }
2289
2290 static bool
2291 radv_nir_stage_uses_xfb(const nir_shader *nir)
2292 {
2293 nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
2294 bool uses_xfb = !!xfb;
2295
2296 ralloc_free(xfb);
2297 return uses_xfb;
2298 }
2299
2300 static void
2301 radv_fill_shader_keys(struct radv_device *device,
2302 struct radv_shader_variant_key *keys,
2303 const struct radv_pipeline_key *key,
2304 nir_shader **nir)
2305 {
2306 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
2307 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
2308 keys[MESA_SHADER_VERTEX].vs.post_shuffle = key->vertex_post_shuffle;
2309 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) {
2310 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
2311 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_formats[i] = key->vertex_attribute_formats[i];
2312 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_bindings[i] = key->vertex_attribute_bindings[i];
2313 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i];
2314 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i];
2315 }
2316 keys[MESA_SHADER_VERTEX].vs.outprim = si_conv_prim_to_gs_out(key->topology);
2317
2318 if (nir[MESA_SHADER_TESS_CTRL]) {
2319 keys[MESA_SHADER_VERTEX].vs_common_out.as_ls = true;
2320 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
2321 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
2322 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
2323
2324 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
2325 }
2326
2327 if (nir[MESA_SHADER_GEOMETRY]) {
2328 if (nir[MESA_SHADER_TESS_CTRL])
2329 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_es = true;
2330 else
2331 keys[MESA_SHADER_VERTEX].vs_common_out.as_es = true;
2332 }
2333
2334 if (device->physical_device->use_ngg) {
2335 if (nir[MESA_SHADER_TESS_CTRL]) {
2336 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = true;
2337 } else {
2338 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = true;
2339 }
2340
2341 if (nir[MESA_SHADER_TESS_CTRL] &&
2342 nir[MESA_SHADER_GEOMETRY] &&
2343 nir[MESA_SHADER_GEOMETRY]->info.gs.invocations *
2344 nir[MESA_SHADER_GEOMETRY]->info.gs.vertices_out > 256) {
2345 /* Fallback to the legacy path if tessellation is
2346 * enabled with extreme geometry because
2347 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2348 * might hang.
2349 */
2350 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2351 }
2352
2353 /*
2354 * Disable NGG with geometry shaders. There are a bunch of
2355 * issues still:
2356 * * GS primitives in pipeline statistic queries do not get
2357 * updates. See dEQP-VK.query_pool.statistics_query.geometry_shader_primitives
2358 *
2359 * Furthermore, XGL/AMDVLK also disables this as of 9b632ef.
2360 */
2361 if (nir[MESA_SHADER_GEOMETRY]) {
2362 if (nir[MESA_SHADER_TESS_CTRL])
2363 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2364 else
2365 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2366 }
2367
2368 if (!device->physical_device->use_ngg_streamout) {
2369 gl_shader_stage last_xfb_stage = MESA_SHADER_VERTEX;
2370
2371 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
2372 if (nir[i])
2373 last_xfb_stage = i;
2374 }
2375
2376 if (nir[last_xfb_stage] &&
2377 radv_nir_stage_uses_xfb(nir[last_xfb_stage])) {
2378 if (nir[MESA_SHADER_TESS_CTRL])
2379 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2380 else
2381 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2382 }
2383 }
2384 }
2385
2386 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
2387 keys[i].has_multiview_view_index = key->has_multiview_view_index;
2388
2389 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
2390 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
2391 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
2392 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
2393 keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples;
2394
2395 if (nir[MESA_SHADER_COMPUTE]) {
2396 keys[MESA_SHADER_COMPUTE].cs.subgroup_size = key->compute_subgroup_size;
2397 }
2398 }
2399
2400 static uint8_t
2401 radv_get_wave_size(struct radv_device *device,
2402 const VkPipelineShaderStageCreateInfo *pStage,
2403 gl_shader_stage stage,
2404 const struct radv_shader_variant_key *key)
2405 {
2406 if (stage == MESA_SHADER_GEOMETRY && !key->vs_common_out.as_ngg)
2407 return 64;
2408 else if (stage == MESA_SHADER_COMPUTE) {
2409 if (key->cs.subgroup_size) {
2410 /* Return the required subgroup size if specified. */
2411 return key->cs.subgroup_size;
2412 }
2413 return device->physical_device->cs_wave_size;
2414 }
2415 else if (stage == MESA_SHADER_FRAGMENT)
2416 return device->physical_device->ps_wave_size;
2417 else
2418 return device->physical_device->ge_wave_size;
2419 }
2420
2421 static void
2422 radv_fill_shader_info(struct radv_pipeline *pipeline,
2423 const VkPipelineShaderStageCreateInfo **pStages,
2424 struct radv_shader_variant_key *keys,
2425 struct radv_shader_info *infos,
2426 nir_shader **nir)
2427 {
2428 unsigned active_stages = 0;
2429 unsigned filled_stages = 0;
2430
2431 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2432 if (nir[i])
2433 active_stages |= (1 << i);
2434 }
2435
2436 if (nir[MESA_SHADER_FRAGMENT]) {
2437 radv_nir_shader_info_init(&infos[MESA_SHADER_FRAGMENT]);
2438 radv_nir_shader_info_pass(nir[MESA_SHADER_FRAGMENT],
2439 pipeline->layout,
2440 &keys[MESA_SHADER_FRAGMENT],
2441 &infos[MESA_SHADER_FRAGMENT]);
2442
2443 /* TODO: These are no longer used as keys we should refactor this */
2444 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2445 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2446 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2447 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2448 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2449 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2450 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2451 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2452 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2453 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2454 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2455 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2456
2457 filled_stages |= (1 << MESA_SHADER_FRAGMENT);
2458 }
2459
2460 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2461 nir[MESA_SHADER_TESS_CTRL]) {
2462 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2463 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2464 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2465
2466 radv_nir_shader_info_init(&infos[MESA_SHADER_TESS_CTRL]);
2467
2468 for (int i = 0; i < 2; i++) {
2469 radv_nir_shader_info_pass(combined_nir[i],
2470 pipeline->layout, &key,
2471 &infos[MESA_SHADER_TESS_CTRL]);
2472 }
2473
2474 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2475 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2476 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2477 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2478
2479 filled_stages |= (1 << MESA_SHADER_VERTEX);
2480 filled_stages |= (1 << MESA_SHADER_TESS_CTRL);
2481 }
2482
2483 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2484 nir[MESA_SHADER_GEOMETRY]) {
2485 gl_shader_stage pre_stage = nir[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2486 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2487
2488 radv_nir_shader_info_init(&infos[MESA_SHADER_GEOMETRY]);
2489
2490 for (int i = 0; i < 2; i++) {
2491 radv_nir_shader_info_pass(combined_nir[i],
2492 pipeline->layout,
2493 &keys[pre_stage],
2494 &infos[MESA_SHADER_GEOMETRY]);
2495 }
2496
2497 filled_stages |= (1 << pre_stage);
2498 filled_stages |= (1 << MESA_SHADER_GEOMETRY);
2499 }
2500
2501 active_stages ^= filled_stages;
2502 while (active_stages) {
2503 int i = u_bit_scan(&active_stages);
2504
2505 if (i == MESA_SHADER_TESS_CTRL) {
2506 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs =
2507 util_last_bit64(infos[MESA_SHADER_VERTEX].vs.ls_outputs_written);
2508 }
2509
2510 if (i == MESA_SHADER_TESS_EVAL) {
2511 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2512 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2513 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2514 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2515 }
2516
2517 radv_nir_shader_info_init(&infos[i]);
2518 radv_nir_shader_info_pass(nir[i], pipeline->layout,
2519 &keys[i], &infos[i]);
2520 }
2521
2522 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2523 if (nir[i])
2524 infos[i].wave_size =
2525 radv_get_wave_size(pipeline->device, pStages[i],
2526 i, &keys[i]);
2527 }
2528 }
2529
2530 static void
2531 merge_tess_info(struct shader_info *tes_info,
2532 const struct shader_info *tcs_info)
2533 {
2534 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2535 *
2536 * "PointMode. Controls generation of points rather than triangles
2537 * or lines. This functionality defaults to disabled, and is
2538 * enabled if either shader stage includes the execution mode.
2539 *
2540 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2541 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2542 * and OutputVertices, it says:
2543 *
2544 * "One mode must be set in at least one of the tessellation
2545 * shader stages."
2546 *
2547 * So, the fields can be set in either the TCS or TES, but they must
2548 * agree if set in both. Our backend looks at TES, so bitwise-or in
2549 * the values from the TCS.
2550 */
2551 assert(tcs_info->tess.tcs_vertices_out == 0 ||
2552 tes_info->tess.tcs_vertices_out == 0 ||
2553 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
2554 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
2555
2556 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2557 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2558 tcs_info->tess.spacing == tes_info->tess.spacing);
2559 tes_info->tess.spacing |= tcs_info->tess.spacing;
2560
2561 assert(tcs_info->tess.primitive_mode == 0 ||
2562 tes_info->tess.primitive_mode == 0 ||
2563 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
2564 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
2565 tes_info->tess.ccw |= tcs_info->tess.ccw;
2566 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
2567 }
2568
2569 static
2570 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT *ext)
2571 {
2572 if (!ext)
2573 return;
2574
2575 if (ext->pPipelineCreationFeedback) {
2576 ext->pPipelineCreationFeedback->flags = 0;
2577 ext->pPipelineCreationFeedback->duration = 0;
2578 }
2579
2580 for (unsigned i = 0; i < ext->pipelineStageCreationFeedbackCount; ++i) {
2581 ext->pPipelineStageCreationFeedbacks[i].flags = 0;
2582 ext->pPipelineStageCreationFeedbacks[i].duration = 0;
2583 }
2584 }
2585
2586 static
2587 void radv_start_feedback(VkPipelineCreationFeedbackEXT *feedback)
2588 {
2589 if (!feedback)
2590 return;
2591
2592 feedback->duration -= radv_get_current_time();
2593 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT;
2594 }
2595
2596 static
2597 void radv_stop_feedback(VkPipelineCreationFeedbackEXT *feedback, bool cache_hit)
2598 {
2599 if (!feedback)
2600 return;
2601
2602 feedback->duration += radv_get_current_time();
2603 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT |
2604 (cache_hit ? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT : 0);
2605 }
2606
2607 static
2608 bool radv_aco_supported_stage(gl_shader_stage stage, bool has_gs, bool has_ts)
2609 {
2610 return (stage == MESA_SHADER_VERTEX && !has_gs && !has_ts) ||
2611 stage == MESA_SHADER_FRAGMENT ||
2612 stage == MESA_SHADER_COMPUTE;
2613 }
2614
2615 void radv_create_shaders(struct radv_pipeline *pipeline,
2616 struct radv_device *device,
2617 struct radv_pipeline_cache *cache,
2618 const struct radv_pipeline_key *key,
2619 const VkPipelineShaderStageCreateInfo **pStages,
2620 const VkPipelineCreateFlags flags,
2621 VkPipelineCreationFeedbackEXT *pipeline_feedback,
2622 VkPipelineCreationFeedbackEXT **stage_feedbacks)
2623 {
2624 struct radv_shader_module fs_m = {0};
2625 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2626 nir_shader *nir[MESA_SHADER_STAGES] = {0};
2627 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2628 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{{0}}}}};
2629 struct radv_shader_info infos[MESA_SHADER_STAGES] = {0};
2630 unsigned char hash[20], gs_copy_hash[20];
2631 bool keep_executable_info = (flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR) || device->keep_shader_info;
2632
2633 radv_start_feedback(pipeline_feedback);
2634
2635 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2636 if (pStages[i]) {
2637 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
2638 if (modules[i]->nir)
2639 _mesa_sha1_compute(modules[i]->nir->info.name,
2640 strlen(modules[i]->nir->info.name),
2641 modules[i]->sha1);
2642
2643 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
2644 }
2645 }
2646
2647 radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device));
2648 memcpy(gs_copy_hash, hash, 20);
2649 gs_copy_hash[0] ^= 1;
2650
2651 bool found_in_application_cache = true;
2652 if (modules[MESA_SHADER_GEOMETRY] && !keep_executable_info) {
2653 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2654 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants,
2655 &found_in_application_cache);
2656 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
2657 }
2658
2659 if (!keep_executable_info &&
2660 radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders,
2661 &found_in_application_cache) &&
2662 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
2663 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2664 return;
2665 }
2666
2667 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
2668 nir_builder fs_b;
2669 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2670 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2671 fs_m.nir = fs_b.shader;
2672 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2673 }
2674
2675 bool has_gs = modules[MESA_SHADER_GEOMETRY];
2676 bool has_ts = modules[MESA_SHADER_TESS_CTRL] || modules[MESA_SHADER_TESS_EVAL];
2677 bool use_aco = device->physical_device->use_aco;
2678
2679 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2680 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
2681
2682 if (!modules[i])
2683 continue;
2684
2685 radv_start_feedback(stage_feedbacks[i]);
2686
2687 bool aco = use_aco && radv_aco_supported_stage(i, has_gs, has_ts);
2688 nir[i] = radv_shader_compile_to_nir(device, modules[i],
2689 stage ? stage->pName : "main", i,
2690 stage ? stage->pSpecializationInfo : NULL,
2691 flags, pipeline->layout, aco);
2692
2693 /* We don't want to alter meta shaders IR directly so clone it
2694 * first.
2695 */
2696 if (nir[i]->info.name) {
2697 nir[i] = nir_shader_clone(NULL, nir[i]);
2698 }
2699
2700 radv_stop_feedback(stage_feedbacks[i], false);
2701 }
2702
2703 if (nir[MESA_SHADER_TESS_CTRL]) {
2704 nir_lower_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
2705 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
2706 }
2707
2708 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
2709 radv_link_shaders(pipeline, nir);
2710
2711 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2712 if (nir[i]) {
2713 NIR_PASS_V(nir[i], nir_lower_non_uniform_access,
2714 nir_lower_non_uniform_ubo_access |
2715 nir_lower_non_uniform_ssbo_access |
2716 nir_lower_non_uniform_texture_access |
2717 nir_lower_non_uniform_image_access);
2718
2719 bool aco = use_aco && radv_aco_supported_stage(i, has_gs, has_ts);
2720 if (!aco)
2721 NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
2722 }
2723
2724 if (radv_can_dump_shader(device, modules[i], false))
2725 nir_print_shader(nir[i], stderr);
2726 }
2727
2728 if (nir[MESA_SHADER_FRAGMENT])
2729 radv_lower_fs_io(nir[MESA_SHADER_FRAGMENT]);
2730
2731 radv_fill_shader_keys(device, keys, key, nir);
2732
2733 radv_fill_shader_info(pipeline, pStages, keys, infos, nir);
2734
2735 if ((nir[MESA_SHADER_VERTEX] &&
2736 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) ||
2737 (nir[MESA_SHADER_TESS_EVAL] &&
2738 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg)) {
2739 struct gfx10_ngg_info *ngg_info;
2740
2741 if (nir[MESA_SHADER_GEOMETRY])
2742 ngg_info = &infos[MESA_SHADER_GEOMETRY].ngg_info;
2743 else if (nir[MESA_SHADER_TESS_CTRL])
2744 ngg_info = &infos[MESA_SHADER_TESS_EVAL].ngg_info;
2745 else
2746 ngg_info = &infos[MESA_SHADER_VERTEX].ngg_info;
2747
2748 gfx10_get_ngg_info(key, pipeline, nir, infos, ngg_info);
2749 } else if (nir[MESA_SHADER_GEOMETRY]) {
2750 struct gfx9_gs_info *gs_info =
2751 &infos[MESA_SHADER_GEOMETRY].gs_ring_info;
2752
2753 gfx9_get_gs_info(key, pipeline, nir, infos, gs_info);
2754 }
2755
2756 if (nir[MESA_SHADER_FRAGMENT]) {
2757 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
2758 radv_start_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT]);
2759
2760 bool aco = use_aco && radv_aco_supported_stage(MESA_SHADER_FRAGMENT, has_gs, has_ts);
2761 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2762 radv_shader_variant_compile(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
2763 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
2764 infos + MESA_SHADER_FRAGMENT,
2765 keep_executable_info, aco,
2766 &binaries[MESA_SHADER_FRAGMENT]);
2767
2768 radv_stop_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT], false);
2769 }
2770
2771 /* TODO: These are no longer used as keys we should refactor this */
2772 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2773 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input;
2774 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2775 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.layer_input;
2776 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2777 !!pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.num_input_clips_culls;
2778 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2779 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input;
2780 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2781 pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.layer_input;
2782 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2783 !!pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.num_input_clips_culls;
2784 }
2785
2786 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
2787 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
2788 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2789 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2790 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2791
2792 radv_start_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL]);
2793
2794 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
2795 pipeline->layout,
2796 &key, &infos[MESA_SHADER_TESS_CTRL], keep_executable_info,
2797 false, &binaries[MESA_SHADER_TESS_CTRL]);
2798
2799 radv_stop_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL], false);
2800 }
2801 modules[MESA_SHADER_VERTEX] = NULL;
2802 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2803 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2804 }
2805
2806 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
2807 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2808 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
2809 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2810
2811 radv_start_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY]);
2812
2813 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2814 pipeline->layout,
2815 &keys[pre_stage], &infos[MESA_SHADER_GEOMETRY], keep_executable_info,
2816 false, &binaries[MESA_SHADER_GEOMETRY]);
2817
2818 radv_stop_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY], false);
2819 }
2820 modules[pre_stage] = NULL;
2821 }
2822
2823 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2824 if(modules[i] && !pipeline->shaders[i]) {
2825 if (i == MESA_SHADER_TESS_CTRL) {
2826 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.ls_outputs_written);
2827 }
2828 if (i == MESA_SHADER_TESS_EVAL) {
2829 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2830 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2831 }
2832
2833 radv_start_feedback(stage_feedbacks[i]);
2834
2835 bool aco = use_aco && radv_aco_supported_stage(i, has_gs, has_ts);
2836 pipeline->shaders[i] = radv_shader_variant_compile(device, modules[i], &nir[i], 1,
2837 pipeline->layout,
2838 keys + i, infos + i,keep_executable_info,
2839 aco, &binaries[i]);
2840
2841 radv_stop_feedback(stage_feedbacks[i], false);
2842 }
2843 }
2844
2845 if(modules[MESA_SHADER_GEOMETRY]) {
2846 struct radv_shader_binary *gs_copy_binary = NULL;
2847 if (!pipeline->gs_copy_shader &&
2848 !radv_pipeline_has_ngg(pipeline)) {
2849 struct radv_shader_info info = {};
2850 struct radv_shader_variant_key key = {};
2851
2852 key.has_multiview_view_index =
2853 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index;
2854
2855 radv_nir_shader_info_pass(nir[MESA_SHADER_GEOMETRY],
2856 pipeline->layout, &key,
2857 &info);
2858 info.wave_size = 64; /* Wave32 not supported. */
2859
2860 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2861 device, nir[MESA_SHADER_GEOMETRY], &info,
2862 &gs_copy_binary, keep_executable_info,
2863 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2864 }
2865
2866 if (!keep_executable_info && pipeline->gs_copy_shader) {
2867 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2868 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2869
2870 binaries[MESA_SHADER_GEOMETRY] = gs_copy_binary;
2871 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2872
2873 radv_pipeline_cache_insert_shaders(device, cache,
2874 gs_copy_hash,
2875 variants,
2876 binaries);
2877 }
2878 free(gs_copy_binary);
2879 }
2880
2881 if (!keep_executable_info) {
2882 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
2883 binaries);
2884 }
2885
2886 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2887 free(binaries[i]);
2888 if (nir[i]) {
2889 ralloc_free(nir[i]);
2890
2891 if (radv_can_dump_shader_stats(device, modules[i]))
2892 radv_shader_dump_stats(device,
2893 pipeline->shaders[i],
2894 i, stderr);
2895 }
2896 }
2897
2898 if (fs_m.nir)
2899 ralloc_free(fs_m.nir);
2900
2901 radv_stop_feedback(pipeline_feedback, false);
2902 }
2903
2904 static uint32_t
2905 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
2906 gl_shader_stage stage, enum chip_class chip_class)
2907 {
2908 bool has_gs = radv_pipeline_has_gs(pipeline);
2909 bool has_tess = radv_pipeline_has_tess(pipeline);
2910 bool has_ngg = radv_pipeline_has_ngg(pipeline);
2911
2912 switch (stage) {
2913 case MESA_SHADER_FRAGMENT:
2914 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
2915 case MESA_SHADER_VERTEX:
2916 if (has_tess) {
2917 if (chip_class >= GFX10) {
2918 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
2919 } else if (chip_class == GFX9) {
2920 return R_00B430_SPI_SHADER_USER_DATA_LS_0;
2921 } else {
2922 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
2923 }
2924
2925 }
2926
2927 if (has_gs) {
2928 if (chip_class >= GFX10) {
2929 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2930 } else {
2931 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
2932 }
2933 }
2934
2935 if (has_ngg)
2936 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2937
2938 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2939 case MESA_SHADER_GEOMETRY:
2940 return chip_class == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2941 R_00B230_SPI_SHADER_USER_DATA_GS_0;
2942 case MESA_SHADER_COMPUTE:
2943 return R_00B900_COMPUTE_USER_DATA_0;
2944 case MESA_SHADER_TESS_CTRL:
2945 return chip_class == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
2946 R_00B430_SPI_SHADER_USER_DATA_HS_0;
2947 case MESA_SHADER_TESS_EVAL:
2948 if (has_gs) {
2949 return chip_class >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0 :
2950 R_00B330_SPI_SHADER_USER_DATA_ES_0;
2951 } else if (has_ngg) {
2952 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2953 } else {
2954 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2955 }
2956 default:
2957 unreachable("unknown shader");
2958 }
2959 }
2960
2961 struct radv_bin_size_entry {
2962 unsigned bpp;
2963 VkExtent2D extent;
2964 };
2965
2966 static VkExtent2D
2967 radv_gfx9_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
2968 {
2969 static const struct radv_bin_size_entry color_size_table[][3][9] = {
2970 {
2971 /* One RB / SE */
2972 {
2973 /* One shader engine */
2974 { 0, {128, 128}},
2975 { 1, { 64, 128}},
2976 { 2, { 32, 128}},
2977 { 3, { 16, 128}},
2978 { 17, { 0, 0}},
2979 { UINT_MAX, { 0, 0}},
2980 },
2981 {
2982 /* Two shader engines */
2983 { 0, {128, 128}},
2984 { 2, { 64, 128}},
2985 { 3, { 32, 128}},
2986 { 5, { 16, 128}},
2987 { 17, { 0, 0}},
2988 { UINT_MAX, { 0, 0}},
2989 },
2990 {
2991 /* Four shader engines */
2992 { 0, {128, 128}},
2993 { 3, { 64, 128}},
2994 { 5, { 16, 128}},
2995 { 17, { 0, 0}},
2996 { UINT_MAX, { 0, 0}},
2997 },
2998 },
2999 {
3000 /* Two RB / SE */
3001 {
3002 /* One shader engine */
3003 { 0, {128, 128}},
3004 { 2, { 64, 128}},
3005 { 3, { 32, 128}},
3006 { 5, { 16, 128}},
3007 { 33, { 0, 0}},
3008 { UINT_MAX, { 0, 0}},
3009 },
3010 {
3011 /* Two shader engines */
3012 { 0, {128, 128}},
3013 { 3, { 64, 128}},
3014 { 5, { 32, 128}},
3015 { 9, { 16, 128}},
3016 { 33, { 0, 0}},
3017 { UINT_MAX, { 0, 0}},
3018 },
3019 {
3020 /* Four shader engines */
3021 { 0, {256, 256}},
3022 { 2, {128, 256}},
3023 { 3, {128, 128}},
3024 { 5, { 64, 128}},
3025 { 9, { 16, 128}},
3026 { 33, { 0, 0}},
3027 { UINT_MAX, { 0, 0}},
3028 },
3029 },
3030 {
3031 /* Four RB / SE */
3032 {
3033 /* One shader engine */
3034 { 0, {128, 256}},
3035 { 2, {128, 128}},
3036 { 3, { 64, 128}},
3037 { 5, { 32, 128}},
3038 { 9, { 16, 128}},
3039 { 33, { 0, 0}},
3040 { UINT_MAX, { 0, 0}},
3041 },
3042 {
3043 /* Two shader engines */
3044 { 0, {256, 256}},
3045 { 2, {128, 256}},
3046 { 3, {128, 128}},
3047 { 5, { 64, 128}},
3048 { 9, { 32, 128}},
3049 { 17, { 16, 128}},
3050 { 33, { 0, 0}},
3051 { UINT_MAX, { 0, 0}},
3052 },
3053 {
3054 /* Four shader engines */
3055 { 0, {256, 512}},
3056 { 2, {256, 256}},
3057 { 3, {128, 256}},
3058 { 5, {128, 128}},
3059 { 9, { 64, 128}},
3060 { 17, { 16, 128}},
3061 { 33, { 0, 0}},
3062 { UINT_MAX, { 0, 0}},
3063 },
3064 },
3065 };
3066 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
3067 {
3068 // One RB / SE
3069 {
3070 // One shader engine
3071 { 0, {128, 256}},
3072 { 2, {128, 128}},
3073 { 4, { 64, 128}},
3074 { 7, { 32, 128}},
3075 { 13, { 16, 128}},
3076 { 49, { 0, 0}},
3077 { UINT_MAX, { 0, 0}},
3078 },
3079 {
3080 // Two shader engines
3081 { 0, {256, 256}},
3082 { 2, {128, 256}},
3083 { 4, {128, 128}},
3084 { 7, { 64, 128}},
3085 { 13, { 32, 128}},
3086 { 25, { 16, 128}},
3087 { 49, { 0, 0}},
3088 { UINT_MAX, { 0, 0}},
3089 },
3090 {
3091 // Four shader engines
3092 { 0, {256, 512}},
3093 { 2, {256, 256}},
3094 { 4, {128, 256}},
3095 { 7, {128, 128}},
3096 { 13, { 64, 128}},
3097 { 25, { 16, 128}},
3098 { 49, { 0, 0}},
3099 { UINT_MAX, { 0, 0}},
3100 },
3101 },
3102 {
3103 // Two RB / SE
3104 {
3105 // One shader engine
3106 { 0, {256, 256}},
3107 { 2, {128, 256}},
3108 { 4, {128, 128}},
3109 { 7, { 64, 128}},
3110 { 13, { 32, 128}},
3111 { 25, { 16, 128}},
3112 { 97, { 0, 0}},
3113 { UINT_MAX, { 0, 0}},
3114 },
3115 {
3116 // Two shader engines
3117 { 0, {256, 512}},
3118 { 2, {256, 256}},
3119 { 4, {128, 256}},
3120 { 7, {128, 128}},
3121 { 13, { 64, 128}},
3122 { 25, { 32, 128}},
3123 { 49, { 16, 128}},
3124 { 97, { 0, 0}},
3125 { UINT_MAX, { 0, 0}},
3126 },
3127 {
3128 // Four shader engines
3129 { 0, {512, 512}},
3130 { 2, {256, 512}},
3131 { 4, {256, 256}},
3132 { 7, {128, 256}},
3133 { 13, {128, 128}},
3134 { 25, { 64, 128}},
3135 { 49, { 16, 128}},
3136 { 97, { 0, 0}},
3137 { UINT_MAX, { 0, 0}},
3138 },
3139 },
3140 {
3141 // Four RB / SE
3142 {
3143 // One shader engine
3144 { 0, {256, 512}},
3145 { 2, {256, 256}},
3146 { 4, {128, 256}},
3147 { 7, {128, 128}},
3148 { 13, { 64, 128}},
3149 { 25, { 32, 128}},
3150 { 49, { 16, 128}},
3151 { UINT_MAX, { 0, 0}},
3152 },
3153 {
3154 // Two shader engines
3155 { 0, {512, 512}},
3156 { 2, {256, 512}},
3157 { 4, {256, 256}},
3158 { 7, {128, 256}},
3159 { 13, {128, 128}},
3160 { 25, { 64, 128}},
3161 { 49, { 32, 128}},
3162 { 97, { 16, 128}},
3163 { UINT_MAX, { 0, 0}},
3164 },
3165 {
3166 // Four shader engines
3167 { 0, {512, 512}},
3168 { 4, {256, 512}},
3169 { 7, {256, 256}},
3170 { 13, {128, 256}},
3171 { 25, {128, 128}},
3172 { 49, { 64, 128}},
3173 { 97, { 16, 128}},
3174 { UINT_MAX, { 0, 0}},
3175 },
3176 },
3177 };
3178
3179 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3180 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3181 VkExtent2D extent = {512, 512};
3182
3183 unsigned log_num_rb_per_se =
3184 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
3185 pipeline->device->physical_device->rad_info.max_se);
3186 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
3187
3188 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3189 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
3190 unsigned effective_samples = total_samples;
3191 unsigned color_bytes_per_pixel = 0;
3192
3193 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
3194 if (vkblend) {
3195 for (unsigned i = 0; i < subpass->color_count; i++) {
3196 if (!vkblend->pAttachments[i].colorWriteMask)
3197 continue;
3198
3199 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3200 continue;
3201
3202 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3203 color_bytes_per_pixel += vk_format_get_blocksize(format);
3204 }
3205
3206 /* MSAA images typically don't use all samples all the time. */
3207 if (effective_samples >= 2 && ps_iter_samples <= 1)
3208 effective_samples = 2;
3209 color_bytes_per_pixel *= effective_samples;
3210 }
3211
3212 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
3213 while(color_entry[1].bpp <= color_bytes_per_pixel)
3214 ++color_entry;
3215
3216 extent = color_entry->extent;
3217
3218 if (subpass->depth_stencil_attachment) {
3219 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3220
3221 /* Coefficients taken from AMDVLK */
3222 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3223 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3224 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
3225
3226 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
3227 while(ds_entry[1].bpp <= ds_bytes_per_pixel)
3228 ++ds_entry;
3229
3230 if (ds_entry->extent.width * ds_entry->extent.height < extent.width * extent.height)
3231 extent = ds_entry->extent;
3232 }
3233
3234 return extent;
3235 }
3236
3237 static VkExtent2D
3238 radv_gfx10_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3239 {
3240 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3241 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3242 VkExtent2D extent = {512, 512};
3243
3244 const unsigned db_tag_size = 64;
3245 const unsigned db_tag_count = 312;
3246 const unsigned color_tag_size = 1024;
3247 const unsigned color_tag_count = 31;
3248 const unsigned fmask_tag_size = 256;
3249 const unsigned fmask_tag_count = 44;
3250
3251 const unsigned rb_count = pipeline->device->physical_device->rad_info.num_render_backends;
3252 const unsigned pipe_count = MAX2(rb_count, pipeline->device->physical_device->rad_info.num_sdp_interfaces);
3253
3254 const unsigned db_tag_part = (db_tag_count * rb_count / pipe_count) * db_tag_size * pipe_count;
3255 const unsigned color_tag_part = (color_tag_count * rb_count / pipe_count) * color_tag_size * pipe_count;
3256 const unsigned fmask_tag_part = (fmask_tag_count * rb_count / pipe_count) * fmask_tag_size * pipe_count;
3257
3258 const unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3259 const unsigned samples_log = util_logbase2_ceil(total_samples);
3260
3261 unsigned color_bytes_per_pixel = 0;
3262 unsigned fmask_bytes_per_pixel = 0;
3263
3264 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
3265 if (vkblend) {
3266 for (unsigned i = 0; i < subpass->color_count; i++) {
3267 if (!vkblend->pAttachments[i].colorWriteMask)
3268 continue;
3269
3270 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3271 continue;
3272
3273 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3274 color_bytes_per_pixel += vk_format_get_blocksize(format);
3275
3276 if (total_samples > 1) {
3277 assert(samples_log <= 3);
3278 const unsigned fmask_array[] = {0, 1, 1, 4};
3279 fmask_bytes_per_pixel += fmask_array[samples_log];
3280 }
3281 }
3282
3283 color_bytes_per_pixel *= total_samples;
3284 }
3285 color_bytes_per_pixel = MAX2(color_bytes_per_pixel, 1);
3286
3287 const unsigned color_pixel_count_log = util_logbase2(color_tag_part / color_bytes_per_pixel);
3288 extent.width = 1ull << ((color_pixel_count_log + 1) / 2);
3289 extent.height = 1ull << (color_pixel_count_log / 2);
3290
3291 if (fmask_bytes_per_pixel) {
3292 const unsigned fmask_pixel_count_log = util_logbase2(fmask_tag_part / fmask_bytes_per_pixel);
3293
3294 const VkExtent2D fmask_extent = (VkExtent2D){
3295 .width = 1ull << ((fmask_pixel_count_log + 1) / 2),
3296 .height = 1ull << (color_pixel_count_log / 2)
3297 };
3298
3299 if (fmask_extent.width * fmask_extent.height < extent.width * extent.height)
3300 extent = fmask_extent;
3301 }
3302
3303 if (subpass->depth_stencil_attachment) {
3304 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3305
3306 /* Coefficients taken from AMDVLK */
3307 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3308 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3309 unsigned db_bytes_per_pixel = (depth_coeff + stencil_coeff) * total_samples;
3310
3311 const unsigned db_pixel_count_log = util_logbase2(db_tag_part / db_bytes_per_pixel);
3312
3313 const VkExtent2D db_extent = (VkExtent2D){
3314 .width = 1ull << ((db_pixel_count_log + 1) / 2),
3315 .height = 1ull << (color_pixel_count_log / 2)
3316 };
3317
3318 if (db_extent.width * db_extent.height < extent.width * extent.height)
3319 extent = db_extent;
3320 }
3321
3322 extent.width = MAX2(extent.width, 128);
3323 extent.height = MAX2(extent.width, 64);
3324
3325 return extent;
3326 }
3327
3328 static void
3329 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf *ctx_cs,
3330 struct radv_pipeline *pipeline,
3331 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3332 {
3333 uint32_t pa_sc_binner_cntl_0 =
3334 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
3335 S_028C44_DISABLE_START_OF_PRIM(1);
3336 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3337
3338 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3339 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3340 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3341 const VkPipelineColorBlendStateCreateInfo *vkblend = pCreateInfo->pColorBlendState;
3342 unsigned min_bytes_per_pixel = 0;
3343
3344 if (vkblend) {
3345 for (unsigned i = 0; i < subpass->color_count; i++) {
3346 if (!vkblend->pAttachments[i].colorWriteMask)
3347 continue;
3348
3349 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3350 continue;
3351
3352 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3353 unsigned bytes = vk_format_get_blocksize(format);
3354 if (!min_bytes_per_pixel || bytes < min_bytes_per_pixel)
3355 min_bytes_per_pixel = bytes;
3356 }
3357 }
3358
3359 pa_sc_binner_cntl_0 =
3360 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) |
3361 S_028C44_BIN_SIZE_X(0) |
3362 S_028C44_BIN_SIZE_Y(0) |
3363 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3364 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel <= 4 ? 2 : 1) | /* 128 or 64 */
3365 S_028C44_DISABLE_START_OF_PRIM(1);
3366 }
3367
3368 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3369 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3370 }
3371
3372 static void
3373 radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs,
3374 struct radv_pipeline *pipeline,
3375 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3376 const struct radv_blend_state *blend)
3377 {
3378 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
3379 return;
3380
3381 VkExtent2D bin_size;
3382 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3383 bin_size = radv_gfx10_compute_bin_size(pipeline, pCreateInfo);
3384 } else if (pipeline->device->physical_device->rad_info.chip_class == GFX9) {
3385 bin_size = radv_gfx9_compute_bin_size(pipeline, pCreateInfo);
3386 } else
3387 unreachable("Unhandled generation for binning bin size calculation");
3388
3389 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
3390 unsigned context_states_per_bin; /* allowed range: [1, 6] */
3391 unsigned persistent_states_per_bin; /* allowed range: [1, 32] */
3392 unsigned fpovs_per_batch; /* allowed range: [0, 255], 0 = unlimited */
3393
3394 if (pipeline->device->physical_device->rad_info.has_dedicated_vram) {
3395 context_states_per_bin = 1;
3396 persistent_states_per_bin = 1;
3397 fpovs_per_batch = 63;
3398 } else {
3399 /* The context states are affected by the scissor bug. */
3400 context_states_per_bin = pipeline->device->physical_device->rad_info.has_gfx9_scissor_bug ? 1 : 6;
3401 /* 32 causes hangs for RAVEN. */
3402 persistent_states_per_bin = 16;
3403 fpovs_per_batch = 63;
3404 }
3405
3406 bool disable_start_of_prim = true;
3407 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3408
3409 const struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3410
3411 if (pipeline->device->dfsm_allowed && ps &&
3412 !ps->info.ps.can_discard &&
3413 !ps->info.ps.writes_memory &&
3414 blend->cb_target_enabled_4bit) {
3415 db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_AUTO);
3416 disable_start_of_prim = (blend->blend_enable_4bit & blend->cb_target_enabled_4bit) != 0;
3417 }
3418
3419 const uint32_t pa_sc_binner_cntl_0 =
3420 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
3421 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
3422 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
3423 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
3424 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
3425 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin - 1) |
3426 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin - 1) |
3427 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim) |
3428 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch) |
3429 S_028C44_OPTIMAL_BIN_SELECTION(1);
3430
3431 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3432 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3433 } else
3434 radv_pipeline_generate_disabled_binning_state(ctx_cs, pipeline, pCreateInfo);
3435 }
3436
3437
3438 static void
3439 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs,
3440 struct radv_pipeline *pipeline,
3441 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3442 const struct radv_graphics_pipeline_create_info *extra)
3443 {
3444 const VkPipelineDepthStencilStateCreateInfo *vkds = pCreateInfo->pDepthStencilState;
3445 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3446 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3447 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3448 struct radv_render_pass_attachment *attachment = NULL;
3449 uint32_t db_depth_control = 0, db_stencil_control = 0;
3450 uint32_t db_render_control = 0, db_render_override2 = 0;
3451 uint32_t db_render_override = 0;
3452
3453 if (subpass->depth_stencil_attachment)
3454 attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3455
3456 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
3457 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
3458
3459 if (vkds && has_depth_attachment) {
3460 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
3461 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
3462 S_028800_ZFUNC(vkds->depthCompareOp) |
3463 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
3464
3465 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3466 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
3467 }
3468
3469 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
3470 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3471 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
3472 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
3473 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
3474 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
3475
3476 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
3477 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
3478 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
3479 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
3480 }
3481
3482 if (attachment && extra) {
3483 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
3484 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
3485
3486 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
3487 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
3488 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
3489 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
3490 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
3491 }
3492
3493 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3494 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
3495
3496 if (!pCreateInfo->pRasterizationState->depthClampEnable &&
3497 ps->info.ps.writes_z) {
3498 /* From VK_EXT_depth_range_unrestricted spec:
3499 *
3500 * "The behavior described in Primitive Clipping still applies.
3501 * If depth clamping is disabled the depth values are still
3502 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3503 * depth clamping is enabled the above equation is ignored and
3504 * the depth values are instead clamped to the VkViewport
3505 * minDepth and maxDepth values, which in the case of this
3506 * extension can be outside of the 0.0 to 1.0 range."
3507 */
3508 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3509 }
3510
3511 radeon_set_context_reg(ctx_cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
3512 radeon_set_context_reg(ctx_cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
3513
3514 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control);
3515 radeon_set_context_reg(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
3516 radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
3517 }
3518
3519 static void
3520 radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
3521 struct radv_pipeline *pipeline,
3522 const struct radv_blend_state *blend)
3523 {
3524 radeon_set_context_reg_seq(ctx_cs, R_028780_CB_BLEND0_CONTROL, 8);
3525 radeon_emit_array(ctx_cs, blend->cb_blend_control,
3526 8);
3527 radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
3528 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
3529
3530 if (pipeline->device->physical_device->rad_info.has_rbplus) {
3531
3532 radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
3533 radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
3534 }
3535
3536 radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
3537
3538 radeon_set_context_reg(ctx_cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
3539 radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
3540
3541 pipeline->graphics.col_format = blend->spi_shader_col_format;
3542 pipeline->graphics.cb_target_mask = blend->cb_target_mask;
3543 }
3544
3545 static const VkConservativeRasterizationModeEXT
3546 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo)
3547 {
3548 const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster =
3549 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT);
3550
3551 if (!conservative_raster)
3552 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT;
3553 return conservative_raster->conservativeRasterizationMode;
3554 }
3555
3556 static void
3557 radv_pipeline_generate_raster_state(struct radeon_cmdbuf *ctx_cs,
3558 struct radv_pipeline *pipeline,
3559 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3560 {
3561 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
3562 const VkConservativeRasterizationModeEXT mode =
3563 radv_get_conservative_raster_mode(vkraster);
3564 uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3565 bool depth_clip_disable = vkraster->depthClampEnable;
3566
3567 const VkPipelineRasterizationDepthClipStateCreateInfoEXT *depth_clip_state =
3568 vk_find_struct_const(vkraster->pNext, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT);
3569 if (depth_clip_state) {
3570 depth_clip_disable = !depth_clip_state->depthClipEnable;
3571 }
3572
3573 radeon_set_context_reg(ctx_cs, R_028810_PA_CL_CLIP_CNTL,
3574 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3575 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable ? 1 : 0) |
3576 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable ? 1 : 0) |
3577 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
3578 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3579
3580 radeon_set_context_reg(ctx_cs, R_0286D4_SPI_INTERP_CONTROL_0,
3581 S_0286D4_FLAT_SHADE_ENA(1) |
3582 S_0286D4_PNT_SPRITE_ENA(1) |
3583 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
3584 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
3585 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
3586 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
3587 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3588
3589 radeon_set_context_reg(ctx_cs, R_028BE4_PA_SU_VTX_CNTL,
3590 S_028BE4_PIX_CENTER(1) | // TODO verify
3591 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
3592 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
3593
3594 radeon_set_context_reg(ctx_cs, R_028814_PA_SU_SC_MODE_CNTL,
3595 S_028814_FACE(vkraster->frontFace) |
3596 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
3597 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
3598 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
3599 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3600 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3601 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3602 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3603 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
3604
3605 /* Conservative rasterization. */
3606 if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
3607 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3608
3609 ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3610 ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3611 S_028804_OVERRASTERIZATION_AMOUNT(4);
3612
3613 pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3614 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3615 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3616
3617 if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) {
3618 pa_sc_conservative_rast |=
3619 S_028C4C_OVER_RAST_ENABLE(1) |
3620 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3621 S_028C4C_UNDER_RAST_ENABLE(0) |
3622 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3623 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3624 } else {
3625 assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT);
3626 pa_sc_conservative_rast |=
3627 S_028C4C_OVER_RAST_ENABLE(0) |
3628 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3629 S_028C4C_UNDER_RAST_ENABLE(1) |
3630 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3631 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3632 }
3633 }
3634
3635 radeon_set_context_reg(ctx_cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
3636 pa_sc_conservative_rast);
3637 }
3638
3639
3640 static void
3641 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
3642 struct radv_pipeline *pipeline)
3643 {
3644 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3645
3646 radeon_set_context_reg_seq(ctx_cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3647 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[0]);
3648 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]);
3649
3650 radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa);
3651 radeon_set_context_reg(ctx_cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
3652 radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
3653 radeon_set_context_reg(ctx_cs, R_028BDC_PA_SC_LINE_CNTL, ms->pa_sc_line_cntl);
3654 radeon_set_context_reg(ctx_cs, R_028BE0_PA_SC_AA_CONFIG, ms->pa_sc_aa_config);
3655
3656 /* The exclusion bits can be set to improve rasterization efficiency
3657 * if no sample lies on the pixel boundary (-8 sample offset). It's
3658 * currently always TRUE because the driver doesn't support 16 samples.
3659 */
3660 bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= GFX7;
3661 radeon_set_context_reg(ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3662 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3663 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3664
3665 /* GFX9: Flush DFSM when the AA mode changes. */
3666 if (pipeline->device->dfsm_allowed) {
3667 radeon_emit(ctx_cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3668 radeon_emit(ctx_cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3669 }
3670 }
3671
3672 static void
3673 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
3674 struct radv_pipeline *pipeline)
3675 {
3676 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3677 const struct radv_shader_variant *vs =
3678 pipeline->shaders[MESA_SHADER_TESS_EVAL] ?
3679 pipeline->shaders[MESA_SHADER_TESS_EVAL] :
3680 pipeline->shaders[MESA_SHADER_VERTEX];
3681 unsigned vgt_primitiveid_en = 0;
3682 uint32_t vgt_gs_mode = 0;
3683
3684 if (radv_pipeline_has_ngg(pipeline))
3685 return;
3686
3687 if (radv_pipeline_has_gs(pipeline)) {
3688 const struct radv_shader_variant *gs =
3689 pipeline->shaders[MESA_SHADER_GEOMETRY];
3690
3691 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
3692 pipeline->device->physical_device->rad_info.chip_class);
3693 } else if (outinfo->export_prim_id || vs->info.uses_prim_id) {
3694 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
3695 vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(1);
3696 }
3697
3698 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
3699 radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
3700 }
3701
3702 static void
3703 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
3704 struct radeon_cmdbuf *cs,
3705 struct radv_pipeline *pipeline,
3706 struct radv_shader_variant *shader)
3707 {
3708 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3709
3710 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
3711 radeon_emit(cs, va >> 8);
3712 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
3713 radeon_emit(cs, shader->config.rsrc1);
3714 radeon_emit(cs, shader->config.rsrc2);
3715
3716 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3717 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3718 clip_dist_mask = outinfo->clip_dist_mask;
3719 cull_dist_mask = outinfo->cull_dist_mask;
3720 total_mask = clip_dist_mask | cull_dist_mask;
3721 bool misc_vec_ena = outinfo->writes_pointsize ||
3722 outinfo->writes_layer ||
3723 outinfo->writes_viewport_index;
3724 unsigned spi_vs_out_config, nparams;
3725
3726 /* VS is required to export at least one param. */
3727 nparams = MAX2(outinfo->param_exports, 1);
3728 spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
3729
3730 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3731 spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0);
3732 }
3733
3734 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, spi_vs_out_config);
3735
3736 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3737 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3738 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3739 V_02870C_SPI_SHADER_4COMP :
3740 V_02870C_SPI_SHADER_NONE) |
3741 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3742 V_02870C_SPI_SHADER_4COMP :
3743 V_02870C_SPI_SHADER_NONE) |
3744 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3745 V_02870C_SPI_SHADER_4COMP :
3746 V_02870C_SPI_SHADER_NONE));
3747
3748 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3749 S_028818_VTX_W0_FMT(1) |
3750 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3751 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3752 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3753
3754 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3755 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3756 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3757 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3758 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3759 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3760 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3761 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3762 cull_dist_mask << 8 |
3763 clip_dist_mask);
3764
3765 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
3766 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
3767 outinfo->writes_viewport_index);
3768 }
3769
3770 static void
3771 radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs,
3772 struct radv_pipeline *pipeline,
3773 struct radv_shader_variant *shader)
3774 {
3775 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3776
3777 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
3778 radeon_emit(cs, va >> 8);
3779 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3780 radeon_emit(cs, shader->config.rsrc1);
3781 radeon_emit(cs, shader->config.rsrc2);
3782 }
3783
3784 static void
3785 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs,
3786 struct radv_pipeline *pipeline,
3787 struct radv_shader_variant *shader,
3788 const struct radv_tessellation_state *tess)
3789 {
3790 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3791 uint32_t rsrc2 = shader->config.rsrc2;
3792
3793 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3794 radeon_emit(cs, va >> 8);
3795 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3796
3797 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
3798 if (pipeline->device->physical_device->rad_info.chip_class == GFX7 &&
3799 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
3800 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
3801
3802 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
3803 radeon_emit(cs, shader->config.rsrc1);
3804 radeon_emit(cs, rsrc2);
3805 }
3806
3807 static void
3808 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
3809 struct radeon_cmdbuf *cs,
3810 struct radv_pipeline *pipeline,
3811 struct radv_shader_variant *shader)
3812 {
3813 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3814 gl_shader_stage es_type =
3815 radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
3816 struct radv_shader_variant *es =
3817 es_type == MESA_SHADER_TESS_EVAL ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX];
3818 const struct gfx10_ngg_info *ngg_state = &shader->info.ngg_info;
3819
3820 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
3821 radeon_emit(cs, va >> 8);
3822 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3823 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
3824 radeon_emit(cs, shader->config.rsrc1);
3825 radeon_emit(cs, shader->config.rsrc2);
3826
3827 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3828 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3829 clip_dist_mask = outinfo->clip_dist_mask;
3830 cull_dist_mask = outinfo->cull_dist_mask;
3831 total_mask = clip_dist_mask | cull_dist_mask;
3832 bool misc_vec_ena = outinfo->writes_pointsize ||
3833 outinfo->writes_layer ||
3834 outinfo->writes_viewport_index;
3835 bool es_enable_prim_id = outinfo->export_prim_id ||
3836 (es && es->info.uses_prim_id);
3837 bool break_wave_at_eoi = false;
3838 unsigned ge_cntl;
3839 unsigned nparams;
3840
3841 if (es_type == MESA_SHADER_TESS_EVAL) {
3842 struct radv_shader_variant *gs =
3843 pipeline->shaders[MESA_SHADER_GEOMETRY];
3844
3845 if (es_enable_prim_id || (gs && gs->info.uses_prim_id))
3846 break_wave_at_eoi = true;
3847 }
3848
3849 nparams = MAX2(outinfo->param_exports, 1);
3850 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG,
3851 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
3852 S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0));
3853
3854 radeon_set_context_reg(ctx_cs, R_028708_SPI_SHADER_IDX_FORMAT,
3855 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP));
3856 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3857 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3858 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3859 V_02870C_SPI_SHADER_4COMP :
3860 V_02870C_SPI_SHADER_NONE) |
3861 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3862 V_02870C_SPI_SHADER_4COMP :
3863 V_02870C_SPI_SHADER_NONE) |
3864 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3865 V_02870C_SPI_SHADER_4COMP :
3866 V_02870C_SPI_SHADER_NONE));
3867
3868 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3869 S_028818_VTX_W0_FMT(1) |
3870 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3871 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3872 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3873 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3874 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3875 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3876 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3877 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3878 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3879 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3880 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3881 cull_dist_mask << 8 |
3882 clip_dist_mask);
3883
3884 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN,
3885 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
3886 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id));
3887
3888 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
3889 ngg_state->vgt_esgs_ring_itemsize);
3890
3891 /* NGG specific registers. */
3892 struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
3893 uint32_t gs_num_invocations = gs ? gs->info.gs.invocations : 1;
3894
3895 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
3896 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state->hw_max_esverts) |
3897 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state->max_gsprims) |
3898 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state->max_gsprims * gs_num_invocations));
3899 radeon_set_context_reg(ctx_cs, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
3900 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state->max_out_verts));
3901 radeon_set_context_reg(ctx_cs, R_028B4C_GE_NGG_SUBGRP_CNTL,
3902 S_028B4C_PRIM_AMP_FACTOR(ngg_state->prim_amp_factor) |
3903 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
3904 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
3905 S_028B90_CNT(gs_num_invocations) |
3906 S_028B90_ENABLE(gs_num_invocations > 1) |
3907 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state->max_vert_out_per_gs_instance));
3908
3909 /* User edge flags are set by the pos exports. If user edge flags are
3910 * not used, we must use hw-generated edge flags and pass them via
3911 * the prim export to prevent drawing lines on internal edges of
3912 * decomposed primitives (such as quads) with polygon mode = lines.
3913 *
3914 * TODO: We should combine hw-generated edge flags with user edge
3915 * flags in the shader.
3916 */
3917 radeon_set_context_reg(ctx_cs, R_028838_PA_CL_NGG_CNTL,
3918 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) &&
3919 !radv_pipeline_has_gs(pipeline)));
3920
3921 ge_cntl = S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) |
3922 S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts) |
3923 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
3924
3925 /* Bug workaround for a possible hang with non-tessellation cases.
3926 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
3927 *
3928 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
3929 */
3930 if ((pipeline->device->physical_device->rad_info.family == CHIP_NAVI10 ||
3931 pipeline->device->physical_device->rad_info.family == CHIP_NAVI12 ||
3932 pipeline->device->physical_device->rad_info.family == CHIP_NAVI14) &&
3933 !radv_pipeline_has_tess(pipeline) &&
3934 ngg_state->hw_max_esverts != 256) {
3935 ge_cntl &= C_03096C_VERT_GRP_SIZE;
3936
3937 if (ngg_state->hw_max_esverts > 5) {
3938 ge_cntl |= S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts - 5);
3939 }
3940 }
3941
3942 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, ge_cntl);
3943 }
3944
3945 static void
3946 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
3947 struct radv_pipeline *pipeline,
3948 struct radv_shader_variant *shader,
3949 const struct radv_tessellation_state *tess)
3950 {
3951 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3952
3953 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
3954 unsigned hs_rsrc2 = shader->config.rsrc2;
3955
3956 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3957 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(tess->lds_size);
3958 } else {
3959 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(tess->lds_size);
3960 }
3961
3962 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3963 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3964 radeon_emit(cs, va >> 8);
3965 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3966 } else {
3967 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
3968 radeon_emit(cs, va >> 8);
3969 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
3970 }
3971
3972 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
3973 radeon_emit(cs, shader->config.rsrc1);
3974 radeon_emit(cs, hs_rsrc2);
3975 } else {
3976 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
3977 radeon_emit(cs, va >> 8);
3978 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
3979 radeon_emit(cs, shader->config.rsrc1);
3980 radeon_emit(cs, shader->config.rsrc2);
3981 }
3982 }
3983
3984 static void
3985 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *ctx_cs,
3986 struct radeon_cmdbuf *cs,
3987 struct radv_pipeline *pipeline,
3988 const struct radv_tessellation_state *tess)
3989 {
3990 struct radv_shader_variant *vs;
3991
3992 /* Skip shaders merged into HS/GS */
3993 vs = pipeline->shaders[MESA_SHADER_VERTEX];
3994 if (!vs)
3995 return;
3996
3997 if (vs->info.vs.as_ls)
3998 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
3999 else if (vs->info.vs.as_es)
4000 radv_pipeline_generate_hw_es(cs, pipeline, vs);
4001 else if (vs->info.is_ngg)
4002 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, vs);
4003 else
4004 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, vs);
4005 }
4006
4007 static void
4008 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs,
4009 struct radeon_cmdbuf *cs,
4010 struct radv_pipeline *pipeline,
4011 const struct radv_tessellation_state *tess)
4012 {
4013 if (!radv_pipeline_has_tess(pipeline))
4014 return;
4015
4016 struct radv_shader_variant *tes, *tcs;
4017
4018 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
4019 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
4020
4021 if (tes) {
4022 if (tes->info.is_ngg) {
4023 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, tes);
4024 } else if (tes->info.tes.as_es)
4025 radv_pipeline_generate_hw_es(cs, pipeline, tes);
4026 else
4027 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes);
4028 }
4029
4030 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
4031
4032 radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM,
4033 tess->tf_param);
4034
4035 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7)
4036 radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, 2,
4037 tess->ls_hs_config);
4038 else
4039 radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG,
4040 tess->ls_hs_config);
4041
4042 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 &&
4043 !radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
4044 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
4045 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4046 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4047 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4048 }
4049 }
4050
4051 static void
4052 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs,
4053 struct radeon_cmdbuf *cs,
4054 struct radv_pipeline *pipeline,
4055 struct radv_shader_variant *gs)
4056 {
4057 const struct gfx9_gs_info *gs_state = &gs->info.gs_ring_info;
4058 unsigned gs_max_out_vertices;
4059 uint8_t *num_components;
4060 uint8_t max_stream;
4061 unsigned offset;
4062 uint64_t va;
4063
4064 gs_max_out_vertices = gs->info.gs.vertices_out;
4065 max_stream = gs->info.gs.max_stream;
4066 num_components = gs->info.gs.num_stream_output_components;
4067
4068 offset = num_components[0] * gs_max_out_vertices;
4069
4070 radeon_set_context_reg_seq(ctx_cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
4071 radeon_emit(ctx_cs, offset);
4072 if (max_stream >= 1)
4073 offset += num_components[1] * gs_max_out_vertices;
4074 radeon_emit(ctx_cs, offset);
4075 if (max_stream >= 2)
4076 offset += num_components[2] * gs_max_out_vertices;
4077 radeon_emit(ctx_cs, offset);
4078 if (max_stream >= 3)
4079 offset += num_components[3] * gs_max_out_vertices;
4080 radeon_set_context_reg(ctx_cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
4081
4082 radeon_set_context_reg_seq(ctx_cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
4083 radeon_emit(ctx_cs, num_components[0]);
4084 radeon_emit(ctx_cs, (max_stream >= 1) ? num_components[1] : 0);
4085 radeon_emit(ctx_cs, (max_stream >= 2) ? num_components[2] : 0);
4086 radeon_emit(ctx_cs, (max_stream >= 3) ? num_components[3] : 0);
4087
4088 uint32_t gs_num_invocations = gs->info.gs.invocations;
4089 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
4090 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
4091 S_028B90_ENABLE(gs_num_invocations > 0));
4092
4093 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
4094 gs_state->vgt_esgs_ring_itemsize);
4095
4096 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
4097
4098 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4099 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4100 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
4101 radeon_emit(cs, va >> 8);
4102 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
4103 } else {
4104 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
4105 radeon_emit(cs, va >> 8);
4106 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
4107 }
4108
4109 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
4110 radeon_emit(cs, gs->config.rsrc1);
4111 radeon_emit(cs, gs->config.rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
4112
4113 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
4114 radeon_set_context_reg(ctx_cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
4115 } else {
4116 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
4117 radeon_emit(cs, va >> 8);
4118 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
4119 radeon_emit(cs, gs->config.rsrc1);
4120 radeon_emit(cs, gs->config.rsrc2);
4121 }
4122
4123 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, pipeline->gs_copy_shader);
4124 }
4125
4126 static void
4127 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
4128 struct radeon_cmdbuf *cs,
4129 struct radv_pipeline *pipeline)
4130 {
4131 struct radv_shader_variant *gs;
4132
4133 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
4134 if (!gs)
4135 return;
4136
4137 if (gs->info.is_ngg)
4138 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, gs);
4139 else
4140 radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs);
4141
4142 radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT,
4143 gs->info.gs.vertices_out);
4144 }
4145
4146 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade, bool float16)
4147 {
4148 uint32_t ps_input_cntl;
4149 if (offset <= AC_EXP_PARAM_OFFSET_31) {
4150 ps_input_cntl = S_028644_OFFSET(offset);
4151 if (flat_shade)
4152 ps_input_cntl |= S_028644_FLAT_SHADE(1);
4153 if (float16) {
4154 ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) |
4155 S_028644_ATTR0_VALID(1);
4156 }
4157 } else {
4158 /* The input is a DEFAULT_VAL constant. */
4159 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
4160 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
4161 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
4162 ps_input_cntl = S_028644_OFFSET(0x20) |
4163 S_028644_DEFAULT_VAL(offset);
4164 }
4165 return ps_input_cntl;
4166 }
4167
4168 static void
4169 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
4170 struct radv_pipeline *pipeline)
4171 {
4172 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4173 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
4174 uint32_t ps_input_cntl[32];
4175
4176 unsigned ps_offset = 0;
4177
4178 if (ps->info.ps.prim_id_input) {
4179 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
4180 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4181 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false);
4182 ++ps_offset;
4183 }
4184 }
4185
4186 if (ps->info.ps.layer_input ||
4187 ps->info.needs_multiview_view_index) {
4188 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
4189 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4190 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false);
4191 else
4192 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false);
4193 ++ps_offset;
4194 }
4195
4196 if (ps->info.ps.has_pcoord) {
4197 unsigned val;
4198 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4199 ps_input_cntl[ps_offset] = val;
4200 ps_offset++;
4201 }
4202
4203 if (ps->info.ps.num_input_clips_culls) {
4204 unsigned vs_offset;
4205
4206 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
4207 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4208 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false);
4209 ++ps_offset;
4210 }
4211
4212 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
4213 if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
4214 ps->info.ps.num_input_clips_culls > 4) {
4215 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false);
4216 ++ps_offset;
4217 }
4218 }
4219
4220 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.ps.input_mask; ++i) {
4221 unsigned vs_offset;
4222 bool flat_shade;
4223 bool float16;
4224 if (!(ps->info.ps.input_mask & (1u << i)))
4225 continue;
4226
4227 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
4228 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
4229 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
4230 ++ps_offset;
4231 continue;
4232 }
4233
4234 flat_shade = !!(ps->info.ps.flat_shaded_mask & (1u << ps_offset));
4235 float16 = !!(ps->info.ps.float16_shaded_mask & (1u << ps_offset));
4236
4237 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade, float16);
4238 ++ps_offset;
4239 }
4240
4241 if (ps_offset) {
4242 radeon_set_context_reg_seq(ctx_cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
4243 for (unsigned i = 0; i < ps_offset; i++) {
4244 radeon_emit(ctx_cs, ps_input_cntl[i]);
4245 }
4246 }
4247 }
4248
4249 static uint32_t
4250 radv_compute_db_shader_control(const struct radv_device *device,
4251 const struct radv_pipeline *pipeline,
4252 const struct radv_shader_variant *ps)
4253 {
4254 unsigned z_order;
4255 if (ps->info.ps.early_fragment_test || !ps->info.ps.writes_memory)
4256 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
4257 else
4258 z_order = V_02880C_LATE_Z;
4259
4260 bool disable_rbplus = device->physical_device->rad_info.has_rbplus &&
4261 !device->physical_device->rad_info.rbplus_allowed;
4262
4263 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4264 * but this appears to break Project Cars (DXVK). See
4265 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4266 */
4267 bool mask_export_enable = ps->info.ps.writes_sample_mask;
4268
4269 return S_02880C_Z_EXPORT_ENABLE(ps->info.ps.writes_z) |
4270 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.ps.writes_stencil) |
4271 S_02880C_KILL_ENABLE(!!ps->info.ps.can_discard) |
4272 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
4273 S_02880C_Z_ORDER(z_order) |
4274 S_02880C_DEPTH_BEFORE_SHADER(ps->info.ps.early_fragment_test) |
4275 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps->info.ps.post_depth_coverage) |
4276 S_02880C_EXEC_ON_HIER_FAIL(ps->info.ps.writes_memory) |
4277 S_02880C_EXEC_ON_NOOP(ps->info.ps.writes_memory) |
4278 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
4279 }
4280
4281 static void
4282 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs,
4283 struct radeon_cmdbuf *cs,
4284 struct radv_pipeline *pipeline)
4285 {
4286 struct radv_shader_variant *ps;
4287 uint64_t va;
4288 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
4289
4290 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4291 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
4292
4293 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
4294 radeon_emit(cs, va >> 8);
4295 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
4296 radeon_emit(cs, ps->config.rsrc1);
4297 radeon_emit(cs, ps->config.rsrc2);
4298
4299 radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL,
4300 radv_compute_db_shader_control(pipeline->device,
4301 pipeline, ps));
4302
4303 radeon_set_context_reg(ctx_cs, R_0286CC_SPI_PS_INPUT_ENA,
4304 ps->config.spi_ps_input_ena);
4305
4306 radeon_set_context_reg(ctx_cs, R_0286D0_SPI_PS_INPUT_ADDR,
4307 ps->config.spi_ps_input_addr);
4308
4309 radeon_set_context_reg(ctx_cs, R_0286D8_SPI_PS_IN_CONTROL,
4310 S_0286D8_NUM_INTERP(ps->info.ps.num_interp) |
4311 S_0286D8_PS_W32_EN(ps->info.wave_size == 32));
4312
4313 radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
4314
4315 radeon_set_context_reg(ctx_cs, R_028710_SPI_SHADER_Z_FORMAT,
4316 ac_get_spi_shader_z_format(ps->info.ps.writes_z,
4317 ps->info.ps.writes_stencil,
4318 ps->info.ps.writes_sample_mask));
4319
4320 if (pipeline->device->dfsm_allowed) {
4321 /* optimise this? */
4322 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4323 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
4324 }
4325 }
4326
4327 static void
4328 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs,
4329 struct radv_pipeline *pipeline)
4330 {
4331 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4332 pipeline->device->physical_device->rad_info.chip_class >= GFX10)
4333 return;
4334
4335 unsigned vtx_reuse_depth = 30;
4336 if (radv_pipeline_has_tess(pipeline) &&
4337 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
4338 vtx_reuse_depth = 14;
4339 }
4340 radeon_set_context_reg(ctx_cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
4341 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
4342 }
4343
4344 static uint32_t
4345 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
4346 {
4347 uint32_t stages = 0;
4348 if (radv_pipeline_has_tess(pipeline)) {
4349 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
4350 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4351
4352 if (radv_pipeline_has_gs(pipeline))
4353 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
4354 S_028B54_GS_EN(1);
4355 else if (radv_pipeline_has_ngg(pipeline))
4356 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
4357 else
4358 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
4359 } else if (radv_pipeline_has_gs(pipeline)) {
4360 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
4361 S_028B54_GS_EN(1);
4362 } else if (radv_pipeline_has_ngg(pipeline)) {
4363 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
4364 }
4365
4366 if (radv_pipeline_has_ngg(pipeline)) {
4367 stages |= S_028B54_PRIMGEN_EN(1);
4368 if (pipeline->streamout_shader)
4369 stages |= S_028B54_NGG_WAVE_ID_EN(1);
4370 } else if (radv_pipeline_has_gs(pipeline)) {
4371 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
4372 }
4373
4374 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
4375 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4376
4377 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4378 uint8_t hs_size = 64, gs_size = 64, vs_size = 64;
4379
4380 if (radv_pipeline_has_tess(pipeline))
4381 hs_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.wave_size;
4382
4383 if (pipeline->shaders[MESA_SHADER_GEOMETRY]) {
4384 vs_size = gs_size = pipeline->shaders[MESA_SHADER_GEOMETRY]->info.wave_size;
4385 if (pipeline->gs_copy_shader)
4386 vs_size = pipeline->gs_copy_shader->info.wave_size;
4387 } else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
4388 vs_size = pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.wave_size;
4389 else if (pipeline->shaders[MESA_SHADER_VERTEX])
4390 vs_size = pipeline->shaders[MESA_SHADER_VERTEX]->info.wave_size;
4391
4392 if (radv_pipeline_has_ngg(pipeline))
4393 gs_size = vs_size;
4394
4395 /* legacy GS only supports Wave64 */
4396 stages |= S_028B54_HS_W32_EN(hs_size == 32 ? 1 : 0) |
4397 S_028B54_GS_W32_EN(gs_size == 32 ? 1 : 0) |
4398 S_028B54_VS_W32_EN(vs_size == 32 ? 1 : 0);
4399 }
4400
4401 return stages;
4402 }
4403
4404 static uint32_t
4405 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
4406 {
4407 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
4408 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
4409
4410 if (!discard_rectangle_info)
4411 return 0xffff;
4412
4413 unsigned mask = 0;
4414
4415 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
4416 /* Interpret i as a bitmask, and then set the bit in the mask if
4417 * that combination of rectangles in which the pixel is contained
4418 * should pass the cliprect test. */
4419 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
4420
4421 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
4422 !relevant_subset)
4423 continue;
4424
4425 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
4426 relevant_subset)
4427 continue;
4428
4429 mask |= 1u << i;
4430 }
4431
4432 return mask;
4433 }
4434
4435 static void
4436 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf *ctx_cs,
4437 struct radv_pipeline *pipeline,
4438 const struct radv_tessellation_state *tess)
4439 {
4440 bool break_wave_at_eoi = false;
4441 unsigned primgroup_size;
4442 unsigned vertgroup_size;
4443
4444 if (radv_pipeline_has_tess(pipeline)) {
4445 primgroup_size = tess->num_patches; /* must be a multiple of NUM_PATCHES */
4446 vertgroup_size = 0;
4447 } else if (radv_pipeline_has_gs(pipeline)) {
4448 const struct gfx9_gs_info *gs_state =
4449 &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs_ring_info;
4450 unsigned vgt_gs_onchip_cntl = gs_state->vgt_gs_onchip_cntl;
4451 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
4452 vertgroup_size = G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl);
4453 } else {
4454 primgroup_size = 128; /* recommended without a GS and tess */
4455 vertgroup_size = 0;
4456 }
4457
4458 if (radv_pipeline_has_tess(pipeline)) {
4459 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4460 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4461 break_wave_at_eoi = true;
4462 }
4463
4464 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL,
4465 S_03096C_PRIM_GRP_SIZE(primgroup_size) |
4466 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
4467 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4468 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi));
4469 }
4470
4471 static void
4472 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
4473 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4474 const struct radv_graphics_pipeline_create_info *extra,
4475 const struct radv_blend_state *blend,
4476 const struct radv_tessellation_state *tess,
4477 unsigned prim, unsigned gs_out)
4478 {
4479 struct radeon_cmdbuf *ctx_cs = &pipeline->ctx_cs;
4480 struct radeon_cmdbuf *cs = &pipeline->cs;
4481
4482 cs->max_dw = 64;
4483 ctx_cs->max_dw = 256;
4484 cs->buf = malloc(4 * (cs->max_dw + ctx_cs->max_dw));
4485 ctx_cs->buf = cs->buf + cs->max_dw;
4486
4487 radv_pipeline_generate_depth_stencil_state(ctx_cs, pipeline, pCreateInfo, extra);
4488 radv_pipeline_generate_blend_state(ctx_cs, pipeline, blend);
4489 radv_pipeline_generate_raster_state(ctx_cs, pipeline, pCreateInfo);
4490 radv_pipeline_generate_multisample_state(ctx_cs, pipeline);
4491 radv_pipeline_generate_vgt_gs_mode(ctx_cs, pipeline);
4492 radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline, tess);
4493 radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline, tess);
4494 radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline);
4495 radv_pipeline_generate_fragment_shader(ctx_cs, cs, pipeline);
4496 radv_pipeline_generate_ps_inputs(ctx_cs, pipeline);
4497 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline);
4498 radv_pipeline_generate_binning_state(ctx_cs, pipeline, pCreateInfo, blend);
4499
4500 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && !radv_pipeline_has_ngg(pipeline))
4501 gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline, tess);
4502
4503 radeon_set_context_reg(ctx_cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
4504
4505 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
4506 radeon_set_uconfig_reg_idx(pipeline->device->physical_device,
4507 cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
4508 } else {
4509 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
4510 }
4511 radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
4512
4513 radeon_set_context_reg(ctx_cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
4514
4515 pipeline->ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4);
4516
4517 assert(ctx_cs->cdw <= ctx_cs->max_dw);
4518 assert(cs->cdw <= cs->max_dw);
4519 }
4520
4521 static struct radv_ia_multi_vgt_param_helpers
4522 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
4523 const struct radv_tessellation_state *tess,
4524 uint32_t prim)
4525 {
4526 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
4527 const struct radv_device *device = pipeline->device;
4528
4529 if (radv_pipeline_has_tess(pipeline))
4530 ia_multi_vgt_param.primgroup_size = tess->num_patches;
4531 else if (radv_pipeline_has_gs(pipeline))
4532 ia_multi_vgt_param.primgroup_size = 64;
4533 else
4534 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
4535
4536 /* GS requirement. */
4537 ia_multi_vgt_param.partial_es_wave = false;
4538 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= GFX8)
4539 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
4540 ia_multi_vgt_param.partial_es_wave = true;
4541
4542 ia_multi_vgt_param.wd_switch_on_eop = false;
4543 if (device->physical_device->rad_info.chip_class >= GFX7) {
4544 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
4545 * 4 shader engines. Set 1 to pass the assertion below.
4546 * The other cases are hardware requirements. */
4547 if (device->physical_device->rad_info.max_se < 4 ||
4548 prim == V_008958_DI_PT_POLYGON ||
4549 prim == V_008958_DI_PT_LINELOOP ||
4550 prim == V_008958_DI_PT_TRIFAN ||
4551 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
4552 (pipeline->graphics.prim_restart_enable &&
4553 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4554 (prim != V_008958_DI_PT_POINTLIST &&
4555 prim != V_008958_DI_PT_LINESTRIP))))
4556 ia_multi_vgt_param.wd_switch_on_eop = true;
4557 }
4558
4559 ia_multi_vgt_param.ia_switch_on_eoi = false;
4560 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input)
4561 ia_multi_vgt_param.ia_switch_on_eoi = true;
4562 if (radv_pipeline_has_gs(pipeline) &&
4563 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.uses_prim_id)
4564 ia_multi_vgt_param.ia_switch_on_eoi = true;
4565 if (radv_pipeline_has_tess(pipeline)) {
4566 /* SWITCH_ON_EOI must be set if PrimID is used. */
4567 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4568 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4569 ia_multi_vgt_param.ia_switch_on_eoi = true;
4570 }
4571
4572 ia_multi_vgt_param.partial_vs_wave = false;
4573 if (radv_pipeline_has_tess(pipeline)) {
4574 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4575 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
4576 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
4577 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
4578 radv_pipeline_has_gs(pipeline))
4579 ia_multi_vgt_param.partial_vs_wave = true;
4580 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4581 if (device->physical_device->rad_info.has_distributed_tess) {
4582 if (radv_pipeline_has_gs(pipeline)) {
4583 if (device->physical_device->rad_info.chip_class <= GFX8)
4584 ia_multi_vgt_param.partial_es_wave = true;
4585 } else {
4586 ia_multi_vgt_param.partial_vs_wave = true;
4587 }
4588 }
4589 }
4590
4591 /* Workaround for a VGT hang when strip primitive types are used with
4592 * primitive restart.
4593 */
4594 if (pipeline->graphics.prim_restart_enable &&
4595 (prim == V_008958_DI_PT_LINESTRIP ||
4596 prim == V_008958_DI_PT_TRISTRIP ||
4597 prim == V_008958_DI_PT_LINESTRIP_ADJ ||
4598 prim == V_008958_DI_PT_TRISTRIP_ADJ)) {
4599 ia_multi_vgt_param.partial_vs_wave = true;
4600 }
4601
4602 if (radv_pipeline_has_gs(pipeline)) {
4603 /* On these chips there is the possibility of a hang if the
4604 * pipeline uses a GS and partial_vs_wave is not set.
4605 *
4606 * This mostly does not hit 4-SE chips, as those typically set
4607 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4608 * with GS due to another workaround.
4609 *
4610 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4611 */
4612 if (device->physical_device->rad_info.family == CHIP_TONGA ||
4613 device->physical_device->rad_info.family == CHIP_FIJI ||
4614 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
4615 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
4616 device->physical_device->rad_info.family == CHIP_POLARIS12 ||
4617 device->physical_device->rad_info.family == CHIP_VEGAM) {
4618 ia_multi_vgt_param.partial_vs_wave = true;
4619 }
4620 }
4621
4622 ia_multi_vgt_param.base =
4623 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
4624 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4625 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == GFX8 ? 2 : 0) |
4626 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
4627 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
4628
4629 return ia_multi_vgt_param;
4630 }
4631
4632
4633 static void
4634 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
4635 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4636 {
4637 const VkPipelineVertexInputStateCreateInfo *vi_info =
4638 pCreateInfo->pVertexInputState;
4639 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
4640
4641 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
4642 const VkVertexInputAttributeDescription *desc =
4643 &vi_info->pVertexAttributeDescriptions[i];
4644 unsigned loc = desc->location;
4645 const struct vk_format_description *format_desc;
4646
4647 format_desc = vk_format_description(desc->format);
4648
4649 velems->format_size[loc] = format_desc->block.bits / 8;
4650 }
4651
4652 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
4653 const VkVertexInputBindingDescription *desc =
4654 &vi_info->pVertexBindingDescriptions[i];
4655
4656 pipeline->binding_stride[desc->binding] = desc->stride;
4657 pipeline->num_vertex_bindings =
4658 MAX2(pipeline->num_vertex_bindings, desc->binding + 1);
4659 }
4660 }
4661
4662 static struct radv_shader_variant *
4663 radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline)
4664 {
4665 int i;
4666
4667 for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) {
4668 struct radv_shader_variant *shader =
4669 radv_get_shader(pipeline, i);
4670
4671 if (shader && shader->info.so.num_outputs > 0)
4672 return shader;
4673 }
4674
4675 return NULL;
4676 }
4677
4678 static VkResult
4679 radv_secure_compile(struct radv_pipeline *pipeline,
4680 struct radv_device *device,
4681 const struct radv_pipeline_key *key,
4682 const VkPipelineShaderStageCreateInfo **pStages,
4683 const VkPipelineCreateFlags flags,
4684 unsigned num_stages)
4685 {
4686 uint8_t allowed_pipeline_hashes[2][20];
4687 radv_hash_shaders(allowed_pipeline_hashes[0], pStages,
4688 pipeline->layout, key, get_hash_flags(device));
4689
4690 /* Generate the GC copy hash */
4691 memcpy(allowed_pipeline_hashes[1], allowed_pipeline_hashes[0], 20);
4692 allowed_pipeline_hashes[1][0] ^= 1;
4693
4694 uint8_t allowed_hashes[2][20];
4695 for (unsigned i = 0; i < 2; ++i) {
4696 disk_cache_compute_key(device->physical_device->disk_cache,
4697 allowed_pipeline_hashes[i], 20,
4698 allowed_hashes[i]);
4699 }
4700
4701 /* Do an early exit if all cache entries are already there. */
4702 bool may_need_copy_shader = pStages[MESA_SHADER_GEOMETRY];
4703 void *main_entry = disk_cache_get(device->physical_device->disk_cache, allowed_hashes[0], NULL);
4704 void *copy_entry = NULL;
4705 if (may_need_copy_shader)
4706 copy_entry = disk_cache_get(device->physical_device->disk_cache, allowed_hashes[1], NULL);
4707
4708 bool has_all_cache_entries = main_entry && (!may_need_copy_shader || copy_entry);
4709 free(main_entry);
4710 free(copy_entry);
4711
4712 if(has_all_cache_entries)
4713 return VK_SUCCESS;
4714
4715 unsigned process = 0;
4716 uint8_t sc_threads = device->instance->num_sc_threads;
4717 while (true) {
4718 mtx_lock(&device->sc_state->secure_compile_mutex);
4719 if (device->sc_state->secure_compile_thread_counter < sc_threads) {
4720 device->sc_state->secure_compile_thread_counter++;
4721 for (unsigned i = 0; i < sc_threads; i++) {
4722 if (!device->sc_state->secure_compile_processes[i].in_use) {
4723 device->sc_state->secure_compile_processes[i].in_use = true;
4724 process = i;
4725 break;
4726 }
4727 }
4728 mtx_unlock(&device->sc_state->secure_compile_mutex);
4729 break;
4730 }
4731 mtx_unlock(&device->sc_state->secure_compile_mutex);
4732 }
4733
4734 int fd_secure_input = device->sc_state->secure_compile_processes[process].fd_secure_input;
4735 int fd_secure_output = device->sc_state->secure_compile_processes[process].fd_secure_output;
4736
4737 /* Fork a copy of the slim untainted secure compile process */
4738 enum radv_secure_compile_type sc_type = RADV_SC_TYPE_FORK_DEVICE;
4739 write(fd_secure_input, &sc_type, sizeof(sc_type));
4740
4741 if (!radv_sc_read(fd_secure_output, &sc_type, sizeof(sc_type), true) ||
4742 sc_type != RADV_SC_TYPE_INIT_SUCCESS)
4743 return VK_ERROR_DEVICE_LOST;
4744
4745 fd_secure_input = device->sc_state->secure_compile_processes[process].fd_server;
4746 fd_secure_output = device->sc_state->secure_compile_processes[process].fd_client;
4747
4748 /* Write pipeline / shader module out to secure process via pipe */
4749 sc_type = RADV_SC_TYPE_COMPILE_PIPELINE;
4750 write(fd_secure_input, &sc_type, sizeof(sc_type));
4751
4752 /* Write pipeline layout out to secure process */
4753 struct radv_pipeline_layout *layout = pipeline->layout;
4754 write(fd_secure_input, layout, sizeof(struct radv_pipeline_layout));
4755 write(fd_secure_input, &layout->num_sets, sizeof(uint32_t));
4756 for (uint32_t set = 0; set < layout->num_sets; set++) {
4757 write(fd_secure_input, &layout->set[set].layout->layout_size, sizeof(uint32_t));
4758 write(fd_secure_input, layout->set[set].layout, layout->set[set].layout->layout_size);
4759 }
4760
4761 /* Write pipeline key out to secure process */
4762 write(fd_secure_input, key, sizeof(struct radv_pipeline_key));
4763
4764 /* Write pipeline create flags out to secure process */
4765 write(fd_secure_input, &flags, sizeof(VkPipelineCreateFlags));
4766
4767 /* Write stage and shader information out to secure process */
4768 write(fd_secure_input, &num_stages, sizeof(uint32_t));
4769 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
4770 if (!pStages[i])
4771 continue;
4772
4773 /* Write stage out to secure process */
4774 gl_shader_stage stage = ffs(pStages[i]->stage) - 1;
4775 write(fd_secure_input, &stage, sizeof(gl_shader_stage));
4776
4777 /* Write entry point name out to secure process */
4778 size_t name_size = strlen(pStages[i]->pName) + 1;
4779 write(fd_secure_input, &name_size, sizeof(size_t));
4780 write(fd_secure_input, pStages[i]->pName, name_size);
4781
4782 /* Write shader module out to secure process */
4783 struct radv_shader_module *module = radv_shader_module_from_handle(pStages[i]->module);
4784 assert(!module->nir);
4785 size_t module_size = sizeof(struct radv_shader_module) + module->size;
4786 write(fd_secure_input, &module_size, sizeof(size_t));
4787 write(fd_secure_input, module, module_size);
4788
4789 /* Write specialization info out to secure process */
4790 const VkSpecializationInfo *specInfo = pStages[i]->pSpecializationInfo;
4791 bool has_spec_info = specInfo ? true : false;
4792 write(fd_secure_input, &has_spec_info, sizeof(bool));
4793 if (specInfo) {
4794 write(fd_secure_input, &specInfo->dataSize, sizeof(size_t));
4795 write(fd_secure_input, specInfo->pData, specInfo->dataSize);
4796
4797 write(fd_secure_input, &specInfo->mapEntryCount, sizeof(uint32_t));
4798 for (uint32_t j = 0; j < specInfo->mapEntryCount; j++)
4799 write(fd_secure_input, &specInfo->pMapEntries[j], sizeof(VkSpecializationMapEntry));
4800 }
4801 }
4802
4803 /* Read the data returned from the secure process */
4804 while (sc_type != RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED) {
4805 if (!radv_sc_read(fd_secure_output, &sc_type, sizeof(sc_type), true))
4806 return VK_ERROR_DEVICE_LOST;
4807
4808 if (sc_type == RADV_SC_TYPE_WRITE_DISK_CACHE) {
4809 assert(device->physical_device->disk_cache);
4810
4811 uint8_t disk_sha1[20];
4812 if (!radv_sc_read(fd_secure_output, disk_sha1, sizeof(uint8_t) * 20, true))
4813 return VK_ERROR_DEVICE_LOST;
4814
4815 if (memcmp(disk_sha1, allowed_hashes[0], 20) &&
4816 memcmp(disk_sha1, allowed_hashes[1], 20))
4817 return VK_ERROR_DEVICE_LOST;
4818
4819 uint32_t entry_size;
4820 if (!radv_sc_read(fd_secure_output, &entry_size, sizeof(uint32_t), true))
4821 return VK_ERROR_DEVICE_LOST;
4822
4823 struct cache_entry *entry = malloc(entry_size);
4824 if (!radv_sc_read(fd_secure_output, entry, entry_size, true))
4825 return VK_ERROR_DEVICE_LOST;
4826
4827 disk_cache_put(device->physical_device->disk_cache,
4828 disk_sha1, entry, entry_size,
4829 NULL);
4830
4831 free(entry);
4832 } else if (sc_type == RADV_SC_TYPE_READ_DISK_CACHE) {
4833 uint8_t disk_sha1[20];
4834 if (!radv_sc_read(fd_secure_output, disk_sha1, sizeof(uint8_t) * 20, true))
4835 return VK_ERROR_DEVICE_LOST;
4836
4837 if (memcmp(disk_sha1, allowed_hashes[0], 20) &&
4838 memcmp(disk_sha1, allowed_hashes[1], 20))
4839 return VK_ERROR_DEVICE_LOST;
4840
4841 size_t size;
4842 struct cache_entry *entry = (struct cache_entry *)
4843 disk_cache_get(device->physical_device->disk_cache,
4844 disk_sha1, &size);
4845
4846 uint8_t found = entry ? 1 : 0;
4847 write(fd_secure_input, &found, sizeof(uint8_t));
4848
4849 if (found) {
4850 write(fd_secure_input, &size, sizeof(size_t));
4851 write(fd_secure_input, entry, size);
4852 }
4853
4854 free(entry);
4855 }
4856 }
4857
4858 sc_type = RADV_SC_TYPE_DESTROY_DEVICE;
4859 write(fd_secure_input, &sc_type, sizeof(sc_type));
4860
4861 mtx_lock(&device->sc_state->secure_compile_mutex);
4862 device->sc_state->secure_compile_thread_counter--;
4863 device->sc_state->secure_compile_processes[process].in_use = false;
4864 mtx_unlock(&device->sc_state->secure_compile_mutex);
4865
4866 return VK_SUCCESS;
4867 }
4868
4869 static VkResult
4870 radv_pipeline_init(struct radv_pipeline *pipeline,
4871 struct radv_device *device,
4872 struct radv_pipeline_cache *cache,
4873 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4874 const struct radv_graphics_pipeline_create_info *extra)
4875 {
4876 VkResult result;
4877 bool has_view_index = false;
4878
4879 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
4880 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
4881 if (subpass->view_mask)
4882 has_view_index = true;
4883
4884 pipeline->device = device;
4885 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
4886 assert(pipeline->layout);
4887
4888 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
4889
4890 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
4891 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
4892 radv_init_feedback(creation_feedback);
4893
4894 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
4895
4896 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
4897 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
4898 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
4899 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
4900 pStages[stage] = &pCreateInfo->pStages[i];
4901 if(creation_feedback)
4902 stage_feedbacks[stage] = &creation_feedback->pPipelineStageCreationFeedbacks[i];
4903 }
4904
4905 struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index);
4906 if (radv_device_use_secure_compile(device->instance)) {
4907 return radv_secure_compile(pipeline, device, &key, pStages, pCreateInfo->flags, pCreateInfo->stageCount);
4908 } else {
4909 radv_create_shaders(pipeline, device, cache, &key, pStages, pCreateInfo->flags, pipeline_feedback, stage_feedbacks);
4910 }
4911
4912 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
4913 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
4914 uint32_t gs_out;
4915 uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
4916
4917 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
4918
4919 if (radv_pipeline_has_gs(pipeline)) {
4920 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
4921 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4922 } else if (radv_pipeline_has_tess(pipeline)) {
4923 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode)
4924 gs_out = V_028A6C_OUTPRIM_TYPE_POINTLIST;
4925 else
4926 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.primitive_mode);
4927 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4928 } else {
4929 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
4930 }
4931 if (extra && extra->use_rectlist) {
4932 prim = V_008958_DI_PT_RECTLIST;
4933 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4934 pipeline->graphics.can_use_guardband = true;
4935 if (radv_pipeline_has_ngg(pipeline))
4936 gs_out = V_028A6C_VGT_OUT_RECT_V0;
4937 }
4938 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
4939 /* prim vertex count will need TESS changes */
4940 pipeline->graphics.prim_vertex_count = prim_size_table[prim];
4941
4942 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
4943
4944 /* Ensure that some export memory is always allocated, for two reasons:
4945 *
4946 * 1) Correctness: The hardware ignores the EXEC mask if no export
4947 * memory is allocated, so KILL and alpha test do not work correctly
4948 * without this.
4949 * 2) Performance: Every shader needs at least a NULL export, even when
4950 * it writes no color/depth output. The NULL export instruction
4951 * stalls without this setting.
4952 *
4953 * Don't add this to CB_SHADER_MASK.
4954 *
4955 * GFX10 supports pixel shaders without exports by setting both the
4956 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
4957 * instructions if any are present.
4958 */
4959 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4960 if ((pipeline->device->physical_device->rad_info.chip_class <= GFX9 ||
4961 ps->info.ps.can_discard) &&
4962 !blend.spi_shader_col_format) {
4963 if (!ps->info.ps.writes_z &&
4964 !ps->info.ps.writes_stencil &&
4965 !ps->info.ps.writes_sample_mask)
4966 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
4967 }
4968
4969 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
4970 if (pipeline->shaders[i]) {
4971 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
4972 }
4973 }
4974
4975 if (radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
4976 struct radv_shader_variant *gs =
4977 pipeline->shaders[MESA_SHADER_GEOMETRY];
4978
4979 calculate_gs_ring_sizes(pipeline, &gs->info.gs_ring_info);
4980 }
4981
4982 struct radv_tessellation_state tess = {0};
4983 if (radv_pipeline_has_tess(pipeline)) {
4984 if (prim == V_008958_DI_PT_PATCH) {
4985 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
4986 pipeline->graphics.prim_vertex_count.incr = 1;
4987 }
4988 tess = calculate_tess_state(pipeline, pCreateInfo);
4989 }
4990
4991 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim);
4992
4993 radv_compute_vertex_input_state(pipeline, pCreateInfo);
4994
4995 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
4996 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
4997
4998 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
4999 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
5000 if (loc->sgpr_idx != -1) {
5001 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
5002 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
5003 if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id)
5004 pipeline->graphics.vtx_emit_num = 3;
5005 else
5006 pipeline->graphics.vtx_emit_num = 2;
5007 }
5008
5009 /* Find the last vertex shader stage that eventually uses streamout. */
5010 pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline);
5011
5012 result = radv_pipeline_scratch_init(device, pipeline);
5013 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, prim, gs_out);
5014
5015 return result;
5016 }
5017
5018 VkResult
5019 radv_graphics_pipeline_create(
5020 VkDevice _device,
5021 VkPipelineCache _cache,
5022 const VkGraphicsPipelineCreateInfo *pCreateInfo,
5023 const struct radv_graphics_pipeline_create_info *extra,
5024 const VkAllocationCallbacks *pAllocator,
5025 VkPipeline *pPipeline)
5026 {
5027 RADV_FROM_HANDLE(radv_device, device, _device);
5028 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
5029 struct radv_pipeline *pipeline;
5030 VkResult result;
5031
5032 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
5033 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5034 if (pipeline == NULL)
5035 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5036
5037 result = radv_pipeline_init(pipeline, device, cache,
5038 pCreateInfo, extra);
5039 if (result != VK_SUCCESS) {
5040 radv_pipeline_destroy(device, pipeline, pAllocator);
5041 return result;
5042 }
5043
5044 *pPipeline = radv_pipeline_to_handle(pipeline);
5045
5046 return VK_SUCCESS;
5047 }
5048
5049 VkResult radv_CreateGraphicsPipelines(
5050 VkDevice _device,
5051 VkPipelineCache pipelineCache,
5052 uint32_t count,
5053 const VkGraphicsPipelineCreateInfo* pCreateInfos,
5054 const VkAllocationCallbacks* pAllocator,
5055 VkPipeline* pPipelines)
5056 {
5057 VkResult result = VK_SUCCESS;
5058 unsigned i = 0;
5059
5060 for (; i < count; i++) {
5061 VkResult r;
5062 r = radv_graphics_pipeline_create(_device,
5063 pipelineCache,
5064 &pCreateInfos[i],
5065 NULL, pAllocator, &pPipelines[i]);
5066 if (r != VK_SUCCESS) {
5067 result = r;
5068 pPipelines[i] = VK_NULL_HANDLE;
5069 }
5070 }
5071
5072 return result;
5073 }
5074
5075
5076 static void
5077 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
5078 {
5079 struct radv_shader_variant *compute_shader;
5080 struct radv_device *device = pipeline->device;
5081 unsigned threads_per_threadgroup;
5082 unsigned threadgroups_per_cu = 1;
5083 unsigned waves_per_threadgroup;
5084 unsigned max_waves_per_sh = 0;
5085 uint64_t va;
5086
5087 pipeline->cs.max_dw = device->physical_device->rad_info.chip_class >= GFX10 ? 22 : 20;
5088 pipeline->cs.buf = malloc(pipeline->cs.max_dw * 4);
5089
5090 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5091 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
5092
5093 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
5094 radeon_emit(&pipeline->cs, va >> 8);
5095 radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40));
5096
5097 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
5098 radeon_emit(&pipeline->cs, compute_shader->config.rsrc1);
5099 radeon_emit(&pipeline->cs, compute_shader->config.rsrc2);
5100 if (device->physical_device->rad_info.chip_class >= GFX10) {
5101 radeon_set_sh_reg(&pipeline->cs, R_00B8A0_COMPUTE_PGM_RSRC3, compute_shader->config.rsrc3);
5102 }
5103
5104 /* Calculate best compute resource limits. */
5105 threads_per_threadgroup = compute_shader->info.cs.block_size[0] *
5106 compute_shader->info.cs.block_size[1] *
5107 compute_shader->info.cs.block_size[2];
5108 waves_per_threadgroup = DIV_ROUND_UP(threads_per_threadgroup,
5109 compute_shader->info.wave_size);
5110
5111 if (device->physical_device->rad_info.chip_class >= GFX10 &&
5112 waves_per_threadgroup == 1)
5113 threadgroups_per_cu = 2;
5114
5115 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
5116 ac_get_compute_resource_limits(&device->physical_device->rad_info,
5117 waves_per_threadgroup,
5118 max_waves_per_sh,
5119 threadgroups_per_cu));
5120
5121 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5122 radeon_emit(&pipeline->cs,
5123 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
5124 radeon_emit(&pipeline->cs,
5125 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
5126 radeon_emit(&pipeline->cs,
5127 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
5128
5129 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
5130 }
5131
5132 static struct radv_pipeline_key
5133 radv_generate_compute_pipeline_key(struct radv_pipeline *pipeline,
5134 const VkComputePipelineCreateInfo *pCreateInfo)
5135 {
5136 const VkPipelineShaderStageCreateInfo *stage = &pCreateInfo->stage;
5137 struct radv_pipeline_key key;
5138 memset(&key, 0, sizeof(key));
5139
5140 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
5141 key.optimisations_disabled = 1;
5142
5143 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT *subgroup_size =
5144 vk_find_struct_const(stage->pNext,
5145 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT);
5146
5147 if (subgroup_size) {
5148 assert(subgroup_size->requiredSubgroupSize == 32 ||
5149 subgroup_size->requiredSubgroupSize == 64);
5150 key.compute_subgroup_size = subgroup_size->requiredSubgroupSize;
5151 }
5152
5153 return key;
5154 }
5155
5156 static VkResult radv_compute_pipeline_create(
5157 VkDevice _device,
5158 VkPipelineCache _cache,
5159 const VkComputePipelineCreateInfo* pCreateInfo,
5160 const VkAllocationCallbacks* pAllocator,
5161 VkPipeline* pPipeline)
5162 {
5163 RADV_FROM_HANDLE(radv_device, device, _device);
5164 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
5165 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
5166 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
5167 struct radv_pipeline *pipeline;
5168 VkResult result;
5169
5170 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
5171 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5172 if (pipeline == NULL)
5173 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5174
5175 pipeline->device = device;
5176 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
5177 assert(pipeline->layout);
5178
5179 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
5180 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
5181 radv_init_feedback(creation_feedback);
5182
5183 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
5184 if (creation_feedback)
5185 stage_feedbacks[MESA_SHADER_COMPUTE] = &creation_feedback->pPipelineStageCreationFeedbacks[0];
5186
5187 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
5188
5189 struct radv_pipeline_key key =
5190 radv_generate_compute_pipeline_key(pipeline, pCreateInfo);
5191
5192 if (radv_device_use_secure_compile(device->instance)) {
5193 result = radv_secure_compile(pipeline, device, &key, pStages, pCreateInfo->flags, 1);
5194 *pPipeline = radv_pipeline_to_handle(pipeline);
5195
5196 return result;
5197 } else {
5198 radv_create_shaders(pipeline, device, cache, &key, pStages, pCreateInfo->flags, pipeline_feedback, stage_feedbacks);
5199 }
5200
5201 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
5202 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
5203 result = radv_pipeline_scratch_init(device, pipeline);
5204 if (result != VK_SUCCESS) {
5205 radv_pipeline_destroy(device, pipeline, pAllocator);
5206 return result;
5207 }
5208
5209 radv_compute_generate_pm4(pipeline);
5210
5211 *pPipeline = radv_pipeline_to_handle(pipeline);
5212
5213 return VK_SUCCESS;
5214 }
5215
5216 VkResult radv_CreateComputePipelines(
5217 VkDevice _device,
5218 VkPipelineCache pipelineCache,
5219 uint32_t count,
5220 const VkComputePipelineCreateInfo* pCreateInfos,
5221 const VkAllocationCallbacks* pAllocator,
5222 VkPipeline* pPipelines)
5223 {
5224 VkResult result = VK_SUCCESS;
5225
5226 unsigned i = 0;
5227 for (; i < count; i++) {
5228 VkResult r;
5229 r = radv_compute_pipeline_create(_device, pipelineCache,
5230 &pCreateInfos[i],
5231 pAllocator, &pPipelines[i]);
5232 if (r != VK_SUCCESS) {
5233 result = r;
5234 pPipelines[i] = VK_NULL_HANDLE;
5235 }
5236 }
5237
5238 return result;
5239 }
5240
5241
5242 static uint32_t radv_get_executable_count(const struct radv_pipeline *pipeline)
5243 {
5244 uint32_t ret = 0;
5245 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5246 if (!pipeline->shaders[i])
5247 continue;
5248
5249 if (i == MESA_SHADER_GEOMETRY &&
5250 !radv_pipeline_has_ngg(pipeline)) {
5251 ret += 2u;
5252 } else {
5253 ret += 1u;
5254 }
5255
5256 }
5257 return ret;
5258 }
5259
5260 static struct radv_shader_variant *
5261 radv_get_shader_from_executable_index(const struct radv_pipeline *pipeline, int index, gl_shader_stage *stage)
5262 {
5263 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5264 if (!pipeline->shaders[i])
5265 continue;
5266 if (!index) {
5267 *stage = i;
5268 return pipeline->shaders[i];
5269 }
5270
5271 --index;
5272
5273 if (i == MESA_SHADER_GEOMETRY &&
5274 !radv_pipeline_has_ngg(pipeline)) {
5275 if (!index) {
5276 *stage = i;
5277 return pipeline->gs_copy_shader;
5278 }
5279 --index;
5280 }
5281 }
5282
5283 *stage = -1;
5284 return NULL;
5285 }
5286
5287 /* Basically strlcpy (which does not exist on linux) specialized for
5288 * descriptions. */
5289 static void desc_copy(char *desc, const char *src) {
5290 int len = strlen(src);
5291 assert(len < VK_MAX_DESCRIPTION_SIZE);
5292 memcpy(desc, src, len);
5293 memset(desc + len, 0, VK_MAX_DESCRIPTION_SIZE - len);
5294 }
5295
5296 VkResult radv_GetPipelineExecutablePropertiesKHR(
5297 VkDevice _device,
5298 const VkPipelineInfoKHR* pPipelineInfo,
5299 uint32_t* pExecutableCount,
5300 VkPipelineExecutablePropertiesKHR* pProperties)
5301 {
5302 RADV_FROM_HANDLE(radv_pipeline, pipeline, pPipelineInfo->pipeline);
5303 const uint32_t total_count = radv_get_executable_count(pipeline);
5304
5305 if (!pProperties) {
5306 *pExecutableCount = total_count;
5307 return VK_SUCCESS;
5308 }
5309
5310 const uint32_t count = MIN2(total_count, *pExecutableCount);
5311 for (unsigned i = 0, executable_idx = 0;
5312 i < MESA_SHADER_STAGES && executable_idx < count; ++i) {
5313 if (!pipeline->shaders[i])
5314 continue;
5315 pProperties[executable_idx].stages = mesa_to_vk_shader_stage(i);
5316 const char *name = NULL;
5317 const char *description = NULL;
5318 switch(i) {
5319 case MESA_SHADER_VERTEX:
5320 name = "Vertex Shader";
5321 description = "Vulkan Vertex Shader";
5322 break;
5323 case MESA_SHADER_TESS_CTRL:
5324 if (!pipeline->shaders[MESA_SHADER_VERTEX]) {
5325 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5326 name = "Vertex + Tessellation Control Shaders";
5327 description = "Combined Vulkan Vertex and Tessellation Control Shaders";
5328 } else {
5329 name = "Tessellation Control Shader";
5330 description = "Vulkan Tessellation Control Shader";
5331 }
5332 break;
5333 case MESA_SHADER_TESS_EVAL:
5334 name = "Tessellation Evaluation Shader";
5335 description = "Vulkan Tessellation Evaluation Shader";
5336 break;
5337 case MESA_SHADER_GEOMETRY:
5338 if (radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
5339 pProperties[executable_idx].stages |= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT;
5340 name = "Tessellation Evaluation + Geometry Shaders";
5341 description = "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5342 } else if (!radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_VERTEX]) {
5343 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5344 name = "Vertex + Geometry Shader";
5345 description = "Combined Vulkan Vertex and Geometry Shaders";
5346 } else {
5347 name = "Geometry Shader";
5348 description = "Vulkan Geometry Shader";
5349 }
5350 break;
5351 case MESA_SHADER_FRAGMENT:
5352 name = "Fragment Shader";
5353 description = "Vulkan Fragment Shader";
5354 break;
5355 case MESA_SHADER_COMPUTE:
5356 name = "Compute Shader";
5357 description = "Vulkan Compute Shader";
5358 break;
5359 }
5360
5361 pProperties[executable_idx].subgroupSize = pipeline->shaders[i]->info.wave_size;
5362 desc_copy(pProperties[executable_idx].name, name);
5363 desc_copy(pProperties[executable_idx].description, description);
5364
5365 ++executable_idx;
5366 if (i == MESA_SHADER_GEOMETRY &&
5367 !radv_pipeline_has_ngg(pipeline)) {
5368 assert(pipeline->gs_copy_shader);
5369 if (executable_idx >= count)
5370 break;
5371
5372 pProperties[executable_idx].stages = VK_SHADER_STAGE_GEOMETRY_BIT;
5373 pProperties[executable_idx].subgroupSize = 64;
5374 desc_copy(pProperties[executable_idx].name, "GS Copy Shader");
5375 desc_copy(pProperties[executable_idx].description,
5376 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5377
5378 ++executable_idx;
5379 }
5380 }
5381
5382 VkResult result = *pExecutableCount < total_count ? VK_INCOMPLETE : VK_SUCCESS;
5383 *pExecutableCount = count;
5384 return result;
5385 }
5386
5387 VkResult radv_GetPipelineExecutableStatisticsKHR(
5388 VkDevice _device,
5389 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5390 uint32_t* pStatisticCount,
5391 VkPipelineExecutableStatisticKHR* pStatistics)
5392 {
5393 RADV_FROM_HANDLE(radv_device, device, _device);
5394 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5395 gl_shader_stage stage;
5396 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5397
5398 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
5399 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
5400 unsigned max_waves = radv_get_max_waves(device, shader, stage);
5401
5402 VkPipelineExecutableStatisticKHR *s = pStatistics;
5403 VkPipelineExecutableStatisticKHR *end = s + (pStatistics ? *pStatisticCount : 0);
5404 VkResult result = VK_SUCCESS;
5405
5406 if (s < end) {
5407 desc_copy(s->name, "SGPRs");
5408 desc_copy(s->description, "Number of SGPR registers allocated per subgroup");
5409 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5410 s->value.u64 = shader->config.num_sgprs;
5411 }
5412 ++s;
5413
5414 if (s < end) {
5415 desc_copy(s->name, "VGPRs");
5416 desc_copy(s->description, "Number of VGPR registers allocated per subgroup");
5417 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5418 s->value.u64 = shader->config.num_vgprs;
5419 }
5420 ++s;
5421
5422 if (s < end) {
5423 desc_copy(s->name, "Spilled SGPRs");
5424 desc_copy(s->description, "Number of SGPR registers spilled per subgroup");
5425 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5426 s->value.u64 = shader->config.spilled_sgprs;
5427 }
5428 ++s;
5429
5430 if (s < end) {
5431 desc_copy(s->name, "Spilled VGPRs");
5432 desc_copy(s->description, "Number of VGPR registers spilled per subgroup");
5433 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5434 s->value.u64 = shader->config.spilled_vgprs;
5435 }
5436 ++s;
5437
5438 if (s < end) {
5439 desc_copy(s->name, "PrivMem VGPRs");
5440 desc_copy(s->description, "Number of VGPRs stored in private memory per subgroup");
5441 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5442 s->value.u64 = shader->info.private_mem_vgprs;
5443 }
5444 ++s;
5445
5446 if (s < end) {
5447 desc_copy(s->name, "Code size");
5448 desc_copy(s->description, "Code size in bytes");
5449 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5450 s->value.u64 = shader->exec_size;
5451 }
5452 ++s;
5453
5454 if (s < end) {
5455 desc_copy(s->name, "LDS size");
5456 desc_copy(s->description, "LDS size in bytes per workgroup");
5457 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5458 s->value.u64 = shader->config.lds_size * lds_increment;
5459 }
5460 ++s;
5461
5462 if (s < end) {
5463 desc_copy(s->name, "Scratch size");
5464 desc_copy(s->description, "Private memory in bytes per subgroup");
5465 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5466 s->value.u64 = shader->config.scratch_bytes_per_wave;
5467 }
5468 ++s;
5469
5470 if (s < end) {
5471 desc_copy(s->name, "Subgroups per SIMD");
5472 desc_copy(s->description, "The maximum number of subgroups in flight on a SIMD unit");
5473 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5474 s->value.u64 = max_waves;
5475 }
5476 ++s;
5477
5478 if (!pStatistics)
5479 *pStatisticCount = s - pStatistics;
5480 else if (s > end) {
5481 *pStatisticCount = end - pStatistics;
5482 result = VK_INCOMPLETE;
5483 } else {
5484 *pStatisticCount = s - pStatistics;
5485 }
5486
5487 return result;
5488 }
5489
5490 static VkResult radv_copy_representation(void *data, size_t *data_size, const char *src)
5491 {
5492 size_t total_size = strlen(src) + 1;
5493
5494 if (!data) {
5495 *data_size = total_size;
5496 return VK_SUCCESS;
5497 }
5498
5499 size_t size = MIN2(total_size, *data_size);
5500
5501 memcpy(data, src, size);
5502 if (size)
5503 *((char*)data + size - 1) = 0;
5504 return size < total_size ? VK_INCOMPLETE : VK_SUCCESS;
5505 }
5506
5507 VkResult radv_GetPipelineExecutableInternalRepresentationsKHR(
5508 VkDevice device,
5509 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5510 uint32_t* pInternalRepresentationCount,
5511 VkPipelineExecutableInternalRepresentationKHR* pInternalRepresentations)
5512 {
5513 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5514 gl_shader_stage stage;
5515 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5516
5517 VkPipelineExecutableInternalRepresentationKHR *p = pInternalRepresentations;
5518 VkPipelineExecutableInternalRepresentationKHR *end = p + (pInternalRepresentations ? *pInternalRepresentationCount : 0);
5519 VkResult result = VK_SUCCESS;
5520 /* optimized NIR */
5521 if (p < end) {
5522 p->isText = true;
5523 desc_copy(p->name, "NIR Shader(s)");
5524 desc_copy(p->description, "The optimized NIR shader(s)");
5525 if (radv_copy_representation(p->pData, &p->dataSize, shader->nir_string) != VK_SUCCESS)
5526 result = VK_INCOMPLETE;
5527 }
5528 ++p;
5529
5530 /* backend IR */
5531 if (p < end) {
5532 p->isText = true;
5533 if (shader->aco_used) {
5534 desc_copy(p->name, "ACO IR");
5535 desc_copy(p->description, "The ACO IR after some optimizations");
5536 } else {
5537 desc_copy(p->name, "LLVM IR");
5538 desc_copy(p->description, "The LLVM IR after some optimizations");
5539 }
5540 if (radv_copy_representation(p->pData, &p->dataSize, shader->ir_string) != VK_SUCCESS)
5541 result = VK_INCOMPLETE;
5542 }
5543 ++p;
5544
5545 /* Disassembler */
5546 if (p < end) {
5547 p->isText = true;
5548 desc_copy(p->name, "Assembly");
5549 desc_copy(p->description, "Final Assembly");
5550 if (radv_copy_representation(p->pData, &p->dataSize, shader->disasm_string) != VK_SUCCESS)
5551 result = VK_INCOMPLETE;
5552 }
5553 ++p;
5554
5555 if (!pInternalRepresentations)
5556 *pInternalRepresentationCount = p - pInternalRepresentations;
5557 else if(p > end) {
5558 result = VK_INCOMPLETE;
5559 *pInternalRepresentationCount = end - pInternalRepresentations;
5560 } else {
5561 *pInternalRepresentationCount = p - pInternalRepresentations;
5562 }
5563
5564 return result;
5565 }