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radv: add radv_pipeline_generate_vgt_gs_out()
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
33 #include "radv_cs.h"
34 #include "radv_shader.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
39 #include "vk_util.h"
40
41 #include "sid.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
48 #include "ac_shader_util.h"
49
50 struct radv_blend_state {
51 uint32_t blend_enable_4bit;
52 uint32_t need_src_alpha;
53
54 uint32_t cb_color_control;
55 uint32_t cb_target_mask;
56 uint32_t cb_target_enabled_4bit;
57 uint32_t sx_mrt_blend_opt[8];
58 uint32_t cb_blend_control[8];
59
60 uint32_t spi_shader_col_format;
61 uint32_t col_format_is_int8;
62 uint32_t col_format_is_int10;
63 uint32_t cb_shader_mask;
64 uint32_t db_alpha_to_mask;
65
66 uint32_t commutative_4bit;
67
68 bool single_cb_enable;
69 bool mrt0_is_dual_src;
70 };
71
72 struct radv_dsa_order_invariance {
73 /* Whether the final result in Z/S buffers is guaranteed to be
74 * invariant under changes to the order in which fragments arrive.
75 */
76 bool zs;
77
78 /* Whether the set of fragments that pass the combined Z/S test is
79 * guaranteed to be invariant under changes to the order in which
80 * fragments arrive.
81 */
82 bool pass_set;
83 };
84
85 static const VkPipelineMultisampleStateCreateInfo *
86 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
87 {
88 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
89 return pCreateInfo->pMultisampleState;
90 return NULL;
91 }
92
93 static const VkPipelineTessellationStateCreateInfo *
94 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
95 {
96 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
97 if (pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT ||
98 pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) {
99 return pCreateInfo->pTessellationState;
100 }
101 }
102 return NULL;
103 }
104
105 static const VkPipelineDepthStencilStateCreateInfo *
106 radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
107 {
108 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
109 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
110
111 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
112 subpass->depth_stencil_attachment)
113 return pCreateInfo->pDepthStencilState;
114 return NULL;
115 }
116
117 static const VkPipelineColorBlendStateCreateInfo *
118 radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
119 {
120 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
121 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
122
123 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
124 subpass->has_color_att)
125 return pCreateInfo->pColorBlendState;
126 return NULL;
127 }
128
129 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline)
130 {
131 struct radv_shader_variant *variant = NULL;
132 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
133 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
134 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
135 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
136 else if (pipeline->shaders[MESA_SHADER_VERTEX])
137 variant = pipeline->shaders[MESA_SHADER_VERTEX];
138 else
139 return false;
140 return variant->info.is_ngg;
141 }
142
143 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline *pipeline)
144 {
145 assert(radv_pipeline_has_ngg(pipeline));
146
147 struct radv_shader_variant *variant = NULL;
148 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
149 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
150 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
151 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
152 else if (pipeline->shaders[MESA_SHADER_VERTEX])
153 variant = pipeline->shaders[MESA_SHADER_VERTEX];
154 else
155 return false;
156 return variant->info.is_ngg_passthrough;
157 }
158
159 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline)
160 {
161 if (!radv_pipeline_has_gs(pipeline))
162 return false;
163
164 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
165 * On GFX10, it might be required in rare cases if it's not possible to
166 * enable NGG.
167 */
168 if (radv_pipeline_has_ngg(pipeline))
169 return false;
170
171 assert(pipeline->gs_copy_shader);
172 return true;
173 }
174
175 static void
176 radv_pipeline_destroy(struct radv_device *device,
177 struct radv_pipeline *pipeline,
178 const VkAllocationCallbacks* allocator)
179 {
180 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
181 if (pipeline->shaders[i])
182 radv_shader_variant_destroy(device, pipeline->shaders[i]);
183
184 if (pipeline->gs_copy_shader)
185 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
186
187 if(pipeline->cs.buf)
188 free(pipeline->cs.buf);
189
190 vk_object_base_finish(&pipeline->base);
191 vk_free2(&device->vk.alloc, allocator, pipeline);
192 }
193
194 void radv_DestroyPipeline(
195 VkDevice _device,
196 VkPipeline _pipeline,
197 const VkAllocationCallbacks* pAllocator)
198 {
199 RADV_FROM_HANDLE(radv_device, device, _device);
200 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
201
202 if (!_pipeline)
203 return;
204
205 radv_pipeline_destroy(device, pipeline, pAllocator);
206 }
207
208 static uint32_t get_hash_flags(struct radv_device *device)
209 {
210 uint32_t hash_flags = 0;
211
212 if (device->instance->debug_flags & RADV_DEBUG_NO_NGG)
213 hash_flags |= RADV_HASH_SHADER_NO_NGG;
214 if (device->physical_device->cs_wave_size == 32)
215 hash_flags |= RADV_HASH_SHADER_CS_WAVE32;
216 if (device->physical_device->ps_wave_size == 32)
217 hash_flags |= RADV_HASH_SHADER_PS_WAVE32;
218 if (device->physical_device->ge_wave_size == 32)
219 hash_flags |= RADV_HASH_SHADER_GE_WAVE32;
220 if (device->physical_device->use_llvm)
221 hash_flags |= RADV_HASH_SHADER_LLVM;
222 return hash_flags;
223 }
224
225 static VkResult
226 radv_pipeline_scratch_init(struct radv_device *device,
227 struct radv_pipeline *pipeline)
228 {
229 unsigned scratch_bytes_per_wave = 0;
230 unsigned max_waves = 0;
231 unsigned min_waves = 1;
232
233 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
234 if (pipeline->shaders[i] &&
235 pipeline->shaders[i]->config.scratch_bytes_per_wave) {
236 unsigned max_stage_waves = device->scratch_waves;
237
238 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
239 pipeline->shaders[i]->config.scratch_bytes_per_wave);
240
241 max_stage_waves = MIN2(max_stage_waves,
242 4 * device->physical_device->rad_info.num_good_compute_units *
243 (256 / pipeline->shaders[i]->config.num_vgprs));
244 max_waves = MAX2(max_waves, max_stage_waves);
245 }
246 }
247
248 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
249 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
250 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
251 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
252 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
253 }
254
255 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
256 pipeline->max_waves = max_waves;
257 return VK_SUCCESS;
258 }
259
260 static uint32_t si_translate_blend_logic_op(VkLogicOp op)
261 {
262 switch (op) {
263 case VK_LOGIC_OP_CLEAR:
264 return V_028808_ROP3_CLEAR;
265 case VK_LOGIC_OP_AND:
266 return V_028808_ROP3_AND;
267 case VK_LOGIC_OP_AND_REVERSE:
268 return V_028808_ROP3_AND_REVERSE;
269 case VK_LOGIC_OP_COPY:
270 return V_028808_ROP3_COPY;
271 case VK_LOGIC_OP_AND_INVERTED:
272 return V_028808_ROP3_AND_INVERTED;
273 case VK_LOGIC_OP_NO_OP:
274 return V_028808_ROP3_NO_OP;
275 case VK_LOGIC_OP_XOR:
276 return V_028808_ROP3_XOR;
277 case VK_LOGIC_OP_OR:
278 return V_028808_ROP3_OR;
279 case VK_LOGIC_OP_NOR:
280 return V_028808_ROP3_NOR;
281 case VK_LOGIC_OP_EQUIVALENT:
282 return V_028808_ROP3_EQUIVALENT;
283 case VK_LOGIC_OP_INVERT:
284 return V_028808_ROP3_INVERT;
285 case VK_LOGIC_OP_OR_REVERSE:
286 return V_028808_ROP3_OR_REVERSE;
287 case VK_LOGIC_OP_COPY_INVERTED:
288 return V_028808_ROP3_COPY_INVERTED;
289 case VK_LOGIC_OP_OR_INVERTED:
290 return V_028808_ROP3_OR_INVERTED;
291 case VK_LOGIC_OP_NAND:
292 return V_028808_ROP3_NAND;
293 case VK_LOGIC_OP_SET:
294 return V_028808_ROP3_SET;
295 default:
296 unreachable("Unhandled logic op");
297 }
298 }
299
300
301 static uint32_t si_translate_blend_function(VkBlendOp op)
302 {
303 switch (op) {
304 case VK_BLEND_OP_ADD:
305 return V_028780_COMB_DST_PLUS_SRC;
306 case VK_BLEND_OP_SUBTRACT:
307 return V_028780_COMB_SRC_MINUS_DST;
308 case VK_BLEND_OP_REVERSE_SUBTRACT:
309 return V_028780_COMB_DST_MINUS_SRC;
310 case VK_BLEND_OP_MIN:
311 return V_028780_COMB_MIN_DST_SRC;
312 case VK_BLEND_OP_MAX:
313 return V_028780_COMB_MAX_DST_SRC;
314 default:
315 return 0;
316 }
317 }
318
319 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
320 {
321 switch (factor) {
322 case VK_BLEND_FACTOR_ZERO:
323 return V_028780_BLEND_ZERO;
324 case VK_BLEND_FACTOR_ONE:
325 return V_028780_BLEND_ONE;
326 case VK_BLEND_FACTOR_SRC_COLOR:
327 return V_028780_BLEND_SRC_COLOR;
328 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
329 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
330 case VK_BLEND_FACTOR_DST_COLOR:
331 return V_028780_BLEND_DST_COLOR;
332 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
333 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
334 case VK_BLEND_FACTOR_SRC_ALPHA:
335 return V_028780_BLEND_SRC_ALPHA;
336 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
337 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
338 case VK_BLEND_FACTOR_DST_ALPHA:
339 return V_028780_BLEND_DST_ALPHA;
340 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
341 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
342 case VK_BLEND_FACTOR_CONSTANT_COLOR:
343 return V_028780_BLEND_CONSTANT_COLOR;
344 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
345 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
346 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
347 return V_028780_BLEND_CONSTANT_ALPHA;
348 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
349 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
350 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
351 return V_028780_BLEND_SRC_ALPHA_SATURATE;
352 case VK_BLEND_FACTOR_SRC1_COLOR:
353 return V_028780_BLEND_SRC1_COLOR;
354 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
355 return V_028780_BLEND_INV_SRC1_COLOR;
356 case VK_BLEND_FACTOR_SRC1_ALPHA:
357 return V_028780_BLEND_SRC1_ALPHA;
358 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
359 return V_028780_BLEND_INV_SRC1_ALPHA;
360 default:
361 return 0;
362 }
363 }
364
365 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
366 {
367 switch (op) {
368 case VK_BLEND_OP_ADD:
369 return V_028760_OPT_COMB_ADD;
370 case VK_BLEND_OP_SUBTRACT:
371 return V_028760_OPT_COMB_SUBTRACT;
372 case VK_BLEND_OP_REVERSE_SUBTRACT:
373 return V_028760_OPT_COMB_REVSUBTRACT;
374 case VK_BLEND_OP_MIN:
375 return V_028760_OPT_COMB_MIN;
376 case VK_BLEND_OP_MAX:
377 return V_028760_OPT_COMB_MAX;
378 default:
379 return V_028760_OPT_COMB_BLEND_DISABLED;
380 }
381 }
382
383 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
384 {
385 switch (factor) {
386 case VK_BLEND_FACTOR_ZERO:
387 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
388 case VK_BLEND_FACTOR_ONE:
389 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
390 case VK_BLEND_FACTOR_SRC_COLOR:
391 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
392 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
393 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
394 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
395 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
396 case VK_BLEND_FACTOR_SRC_ALPHA:
397 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
398 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
399 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
400 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
401 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
402 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
403 default:
404 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
405 }
406 }
407
408 /**
409 * Get rid of DST in the blend factors by commuting the operands:
410 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
411 */
412 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
413 unsigned *dst_factor, unsigned expected_dst,
414 unsigned replacement_src)
415 {
416 if (*src_factor == expected_dst &&
417 *dst_factor == VK_BLEND_FACTOR_ZERO) {
418 *src_factor = VK_BLEND_FACTOR_ZERO;
419 *dst_factor = replacement_src;
420
421 /* Commuting the operands requires reversing subtractions. */
422 if (*func == VK_BLEND_OP_SUBTRACT)
423 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
424 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
425 *func = VK_BLEND_OP_SUBTRACT;
426 }
427 }
428
429 static bool si_blend_factor_uses_dst(unsigned factor)
430 {
431 return factor == VK_BLEND_FACTOR_DST_COLOR ||
432 factor == VK_BLEND_FACTOR_DST_ALPHA ||
433 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
434 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
435 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
436 }
437
438 static bool is_dual_src(VkBlendFactor factor)
439 {
440 switch (factor) {
441 case VK_BLEND_FACTOR_SRC1_COLOR:
442 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
443 case VK_BLEND_FACTOR_SRC1_ALPHA:
444 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
445 return true;
446 default:
447 return false;
448 }
449 }
450
451 static unsigned radv_choose_spi_color_format(VkFormat vk_format,
452 bool blend_enable,
453 bool blend_need_alpha)
454 {
455 const struct vk_format_description *desc = vk_format_description(vk_format);
456 struct ac_spi_color_formats formats = {};
457 unsigned format, ntype, swap;
458
459 format = radv_translate_colorformat(vk_format);
460 ntype = radv_translate_color_numformat(vk_format, desc,
461 vk_format_get_first_non_void_channel(vk_format));
462 swap = radv_translate_colorswap(vk_format, false);
463
464 ac_choose_spi_color_formats(format, swap, ntype, false, &formats);
465
466 if (blend_enable && blend_need_alpha)
467 return formats.blend_alpha;
468 else if(blend_need_alpha)
469 return formats.alpha;
470 else if(blend_enable)
471 return formats.blend;
472 else
473 return formats.normal;
474 }
475
476 static bool
477 format_is_int8(VkFormat format)
478 {
479 const struct vk_format_description *desc = vk_format_description(format);
480 int channel = vk_format_get_first_non_void_channel(format);
481
482 return channel >= 0 && desc->channel[channel].pure_integer &&
483 desc->channel[channel].size == 8;
484 }
485
486 static bool
487 format_is_int10(VkFormat format)
488 {
489 const struct vk_format_description *desc = vk_format_description(format);
490
491 if (desc->nr_channels != 4)
492 return false;
493 for (unsigned i = 0; i < 4; i++) {
494 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
495 return true;
496 }
497 return false;
498 }
499
500 static void
501 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
502 const VkGraphicsPipelineCreateInfo *pCreateInfo,
503 struct radv_blend_state *blend)
504 {
505 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
506 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
507 unsigned col_format = 0, is_int8 = 0, is_int10 = 0;
508 unsigned num_targets;
509
510 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
511 unsigned cf;
512
513 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED ||
514 !(blend->cb_target_mask & (0xfu << (i * 4)))) {
515 cf = V_028714_SPI_SHADER_ZERO;
516 } else {
517 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
518 bool blend_enable =
519 blend->blend_enable_4bit & (0xfu << (i * 4));
520
521 cf = radv_choose_spi_color_format(attachment->format,
522 blend_enable,
523 blend->need_src_alpha & (1 << i));
524
525 if (format_is_int8(attachment->format))
526 is_int8 |= 1 << i;
527 if (format_is_int10(attachment->format))
528 is_int10 |= 1 << i;
529 }
530
531 col_format |= cf << (4 * i);
532 }
533
534 if (!(col_format & 0xf) && blend->need_src_alpha & (1 << 0)) {
535 /* When a subpass doesn't have any color attachments, write the
536 * alpha channel of MRT0 when alpha coverage is enabled because
537 * the depth attachment needs it.
538 */
539 col_format |= V_028714_SPI_SHADER_32_AR;
540 }
541
542 /* If the i-th target format is set, all previous target formats must
543 * be non-zero to avoid hangs.
544 */
545 num_targets = (util_last_bit(col_format) + 3) / 4;
546 for (unsigned i = 0; i < num_targets; i++) {
547 if (!(col_format & (0xf << (i * 4)))) {
548 col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
549 }
550 }
551
552 /* The output for dual source blending should have the same format as
553 * the first output.
554 */
555 if (blend->mrt0_is_dual_src)
556 col_format |= (col_format & 0xf) << 4;
557
558 blend->spi_shader_col_format = col_format;
559 blend->col_format_is_int8 = is_int8;
560 blend->col_format_is_int10 = is_int10;
561 }
562
563 /*
564 * Ordered so that for each i,
565 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
566 */
567 const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = {
568 VK_FORMAT_R32_SFLOAT,
569 VK_FORMAT_R32G32_SFLOAT,
570 VK_FORMAT_R8G8B8A8_UNORM,
571 VK_FORMAT_R16G16B16A16_UNORM,
572 VK_FORMAT_R16G16B16A16_SNORM,
573 VK_FORMAT_R16G16B16A16_UINT,
574 VK_FORMAT_R16G16B16A16_SINT,
575 VK_FORMAT_R32G32B32A32_SFLOAT,
576 VK_FORMAT_R8G8B8A8_UINT,
577 VK_FORMAT_R8G8B8A8_SINT,
578 VK_FORMAT_A2R10G10B10_UINT_PACK32,
579 VK_FORMAT_A2R10G10B10_SINT_PACK32,
580 };
581
582 unsigned radv_format_meta_fs_key(VkFormat format)
583 {
584 unsigned col_format = radv_choose_spi_color_format(format, false, false);
585
586 assert(col_format != V_028714_SPI_SHADER_32_AR);
587 if (col_format >= V_028714_SPI_SHADER_32_AR)
588 --col_format; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
589
590 --col_format; /* Skip V_028714_SPI_SHADER_ZERO */
591 bool is_int8 = format_is_int8(format);
592 bool is_int10 = format_is_int10(format);
593
594 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
595 }
596
597 static void
598 radv_blend_check_commutativity(struct radv_blend_state *blend,
599 VkBlendOp op, VkBlendFactor src,
600 VkBlendFactor dst, unsigned chanmask)
601 {
602 /* Src factor is allowed when it does not depend on Dst. */
603 static const uint32_t src_allowed =
604 (1u << VK_BLEND_FACTOR_ONE) |
605 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
606 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
607 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
608 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
609 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
610 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
611 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
612 (1u << VK_BLEND_FACTOR_ZERO) |
613 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
614 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
615 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
616 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
617 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
618 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
619
620 if (dst == VK_BLEND_FACTOR_ONE &&
621 (src_allowed & (1u << src))) {
622 /* Addition is commutative, but floating point addition isn't
623 * associative: subtle changes can be introduced via different
624 * rounding. Be conservative, only enable for min and max.
625 */
626 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
627 blend->commutative_4bit |= chanmask;
628 }
629 }
630
631 static struct radv_blend_state
632 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
633 const VkGraphicsPipelineCreateInfo *pCreateInfo,
634 const struct radv_graphics_pipeline_create_info *extra)
635 {
636 const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
637 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
638 struct radv_blend_state blend = {0};
639 unsigned mode = V_028808_CB_NORMAL;
640 int i;
641
642 if (extra && extra->custom_blend_mode) {
643 blend.single_cb_enable = true;
644 mode = extra->custom_blend_mode;
645 }
646
647 blend.cb_color_control = 0;
648 if (vkblend) {
649 if (vkblend->logicOpEnable)
650 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
651 else
652 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
653 }
654
655 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
656 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
657 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
658 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
659 S_028B70_OFFSET_ROUND(1);
660
661 if (vkms && vkms->alphaToCoverageEnable) {
662 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
663 blend.need_src_alpha |= 0x1;
664 }
665
666 blend.cb_target_mask = 0;
667 if (vkblend) {
668 for (i = 0; i < vkblend->attachmentCount; i++) {
669 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
670 unsigned blend_cntl = 0;
671 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
672 VkBlendOp eqRGB = att->colorBlendOp;
673 VkBlendFactor srcRGB = att->srcColorBlendFactor;
674 VkBlendFactor dstRGB = att->dstColorBlendFactor;
675 VkBlendOp eqA = att->alphaBlendOp;
676 VkBlendFactor srcA = att->srcAlphaBlendFactor;
677 VkBlendFactor dstA = att->dstAlphaBlendFactor;
678
679 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
680
681 if (!att->colorWriteMask)
682 continue;
683
684 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
685 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
686 if (!att->blendEnable) {
687 blend.cb_blend_control[i] = blend_cntl;
688 continue;
689 }
690
691 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
692 if (i == 0)
693 blend.mrt0_is_dual_src = true;
694
695 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
696 srcRGB = VK_BLEND_FACTOR_ONE;
697 dstRGB = VK_BLEND_FACTOR_ONE;
698 }
699 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
700 srcA = VK_BLEND_FACTOR_ONE;
701 dstA = VK_BLEND_FACTOR_ONE;
702 }
703
704 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
705 0x7 << (4 * i));
706 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
707 0x8 << (4 * i));
708
709 /* Blending optimizations for RB+.
710 * These transformations don't change the behavior.
711 *
712 * First, get rid of DST in the blend factors:
713 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
714 */
715 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
716 VK_BLEND_FACTOR_DST_COLOR,
717 VK_BLEND_FACTOR_SRC_COLOR);
718
719 si_blend_remove_dst(&eqA, &srcA, &dstA,
720 VK_BLEND_FACTOR_DST_COLOR,
721 VK_BLEND_FACTOR_SRC_COLOR);
722
723 si_blend_remove_dst(&eqA, &srcA, &dstA,
724 VK_BLEND_FACTOR_DST_ALPHA,
725 VK_BLEND_FACTOR_SRC_ALPHA);
726
727 /* Look up the ideal settings from tables. */
728 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
729 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
730 srcA_opt = si_translate_blend_opt_factor(srcA, true);
731 dstA_opt = si_translate_blend_opt_factor(dstA, true);
732
733 /* Handle interdependencies. */
734 if (si_blend_factor_uses_dst(srcRGB))
735 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
736 if (si_blend_factor_uses_dst(srcA))
737 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
738
739 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
740 (dstRGB == VK_BLEND_FACTOR_ZERO ||
741 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
742 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
743 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
744
745 /* Set the final value. */
746 blend.sx_mrt_blend_opt[i] =
747 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
748 S_028760_COLOR_DST_OPT(dstRGB_opt) |
749 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
750 S_028760_ALPHA_SRC_OPT(srcA_opt) |
751 S_028760_ALPHA_DST_OPT(dstA_opt) |
752 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
753 blend_cntl |= S_028780_ENABLE(1);
754
755 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
756 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
757 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
758 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
759 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
760 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
761 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
762 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
763 }
764 blend.cb_blend_control[i] = blend_cntl;
765
766 blend.blend_enable_4bit |= 0xfu << (i * 4);
767
768 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
769 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
770 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
771 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
772 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
773 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
774 blend.need_src_alpha |= 1 << i;
775 }
776 for (i = vkblend->attachmentCount; i < 8; i++) {
777 blend.cb_blend_control[i] = 0;
778 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
779 }
780 }
781
782 if (pipeline->device->physical_device->rad_info.has_rbplus) {
783 /* Disable RB+ blend optimizations for dual source blending. */
784 if (blend.mrt0_is_dual_src) {
785 for (i = 0; i < 8; i++) {
786 blend.sx_mrt_blend_opt[i] =
787 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
788 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
789 }
790 }
791
792 /* RB+ doesn't work with dual source blending, logic op and
793 * RESOLVE.
794 */
795 if (blend.mrt0_is_dual_src ||
796 (vkblend && vkblend->logicOpEnable) ||
797 mode == V_028808_CB_RESOLVE)
798 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
799 }
800
801 if (blend.cb_target_mask)
802 blend.cb_color_control |= S_028808_MODE(mode);
803 else
804 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
805
806 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
807 return blend;
808 }
809
810 static uint32_t si_translate_fill(VkPolygonMode func)
811 {
812 switch(func) {
813 case VK_POLYGON_MODE_FILL:
814 return V_028814_X_DRAW_TRIANGLES;
815 case VK_POLYGON_MODE_LINE:
816 return V_028814_X_DRAW_LINES;
817 case VK_POLYGON_MODE_POINT:
818 return V_028814_X_DRAW_POINTS;
819 default:
820 assert(0);
821 return V_028814_X_DRAW_POINTS;
822 }
823 }
824
825 static uint8_t radv_pipeline_get_ps_iter_samples(const VkGraphicsPipelineCreateInfo *pCreateInfo)
826 {
827 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
828 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
829 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
830 uint32_t ps_iter_samples = 1;
831 uint32_t num_samples;
832
833 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
834 *
835 * "If the VK_AMD_mixed_attachment_samples extension is enabled and the
836 * subpass uses color attachments, totalSamples is the number of
837 * samples of the color attachments. Otherwise, totalSamples is the
838 * value of VkPipelineMultisampleStateCreateInfo::rasterizationSamples
839 * specified at pipeline creation time."
840 */
841 if (subpass->has_color_att) {
842 num_samples = subpass->color_sample_count;
843 } else {
844 num_samples = vkms->rasterizationSamples;
845 }
846
847 if (vkms->sampleShadingEnable) {
848 ps_iter_samples = ceilf(vkms->minSampleShading * num_samples);
849 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
850 }
851 return ps_iter_samples;
852 }
853
854 static bool
855 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
856 {
857 return pCreateInfo->depthTestEnable &&
858 pCreateInfo->depthWriteEnable &&
859 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
860 }
861
862 static bool
863 radv_writes_stencil(const VkStencilOpState *state)
864 {
865 return state->writeMask &&
866 (state->failOp != VK_STENCIL_OP_KEEP ||
867 state->passOp != VK_STENCIL_OP_KEEP ||
868 state->depthFailOp != VK_STENCIL_OP_KEEP);
869 }
870
871 static bool
872 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
873 {
874 return pCreateInfo->stencilTestEnable &&
875 (radv_writes_stencil(&pCreateInfo->front) ||
876 radv_writes_stencil(&pCreateInfo->back));
877 }
878
879 static bool
880 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
881 {
882 return radv_is_depth_write_enabled(pCreateInfo) ||
883 radv_is_stencil_write_enabled(pCreateInfo);
884 }
885
886 static bool
887 radv_order_invariant_stencil_op(VkStencilOp op)
888 {
889 /* REPLACE is normally order invariant, except when the stencil
890 * reference value is written by the fragment shader. Tracking this
891 * interaction does not seem worth the effort, so be conservative.
892 */
893 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
894 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
895 op != VK_STENCIL_OP_REPLACE;
896 }
897
898 static bool
899 radv_order_invariant_stencil_state(const VkStencilOpState *state)
900 {
901 /* Compute whether, assuming Z writes are disabled, this stencil state
902 * is order invariant in the sense that the set of passing fragments as
903 * well as the final stencil buffer result does not depend on the order
904 * of fragments.
905 */
906 return !state->writeMask ||
907 /* The following assumes that Z writes are disabled. */
908 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
909 radv_order_invariant_stencil_op(state->passOp) &&
910 radv_order_invariant_stencil_op(state->depthFailOp)) ||
911 (state->compareOp == VK_COMPARE_OP_NEVER &&
912 radv_order_invariant_stencil_op(state->failOp));
913 }
914
915 static bool
916 radv_pipeline_has_dynamic_ds_states(const VkGraphicsPipelineCreateInfo *pCreateInfo)
917 {
918 VkDynamicState ds_states[] = {
919 VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT,
920 VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT,
921 VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT,
922 VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT,
923 VK_DYNAMIC_STATE_STENCIL_OP_EXT,
924 };
925
926 if (pCreateInfo->pDynamicState) {
927 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
928 for (uint32_t i = 0; i < count; i++) {
929 for (uint32_t j = 0; j < ARRAY_SIZE(ds_states); j++) {
930 if (pCreateInfo->pDynamicState->pDynamicStates[i] == ds_states[j])
931 return true;
932 }
933 }
934 }
935
936 return false;
937 }
938
939 static bool
940 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
941 struct radv_blend_state *blend,
942 const VkGraphicsPipelineCreateInfo *pCreateInfo)
943 {
944 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
945 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
946 const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
947 const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
948 unsigned colormask = blend->cb_target_enabled_4bit;
949
950 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
951 return false;
952
953 /* Be conservative if a logic operation is enabled with color buffers. */
954 if (colormask && vkblend && vkblend->logicOpEnable)
955 return false;
956
957 /* Be conservative if an extended dynamic depth/stencil state is
958 * enabled because the driver can't update out-of-order rasterization
959 * dynamically.
960 */
961 if (radv_pipeline_has_dynamic_ds_states(pCreateInfo))
962 return false;
963
964 /* Default depth/stencil invariance when no attachment is bound. */
965 struct radv_dsa_order_invariance dsa_order_invariant = {
966 .zs = true, .pass_set = true
967 };
968
969 if (vkds) {
970 struct radv_render_pass_attachment *attachment =
971 pass->attachments + subpass->depth_stencil_attachment->attachment;
972 bool has_stencil = vk_format_is_stencil(attachment->format);
973 struct radv_dsa_order_invariance order_invariance[2];
974 struct radv_shader_variant *ps =
975 pipeline->shaders[MESA_SHADER_FRAGMENT];
976
977 /* Compute depth/stencil order invariance in order to know if
978 * it's safe to enable out-of-order.
979 */
980 bool zfunc_is_ordered =
981 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
982 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
983 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
984 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
985 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
986
987 bool nozwrite_and_order_invariant_stencil =
988 !radv_is_ds_write_enabled(vkds) ||
989 (!radv_is_depth_write_enabled(vkds) &&
990 radv_order_invariant_stencil_state(&vkds->front) &&
991 radv_order_invariant_stencil_state(&vkds->back));
992
993 order_invariance[1].zs =
994 nozwrite_and_order_invariant_stencil ||
995 (!radv_is_stencil_write_enabled(vkds) &&
996 zfunc_is_ordered);
997 order_invariance[0].zs =
998 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
999
1000 order_invariance[1].pass_set =
1001 nozwrite_and_order_invariant_stencil ||
1002 (!radv_is_stencil_write_enabled(vkds) &&
1003 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1004 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
1005 order_invariance[0].pass_set =
1006 !radv_is_depth_write_enabled(vkds) ||
1007 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1008 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
1009
1010 dsa_order_invariant = order_invariance[has_stencil];
1011 if (!dsa_order_invariant.zs)
1012 return false;
1013
1014 /* The set of PS invocations is always order invariant,
1015 * except when early Z/S tests are requested.
1016 */
1017 if (ps &&
1018 ps->info.ps.writes_memory &&
1019 ps->info.ps.early_fragment_test &&
1020 !dsa_order_invariant.pass_set)
1021 return false;
1022
1023 /* Determine if out-of-order rasterization should be disabled
1024 * when occlusion queries are used.
1025 */
1026 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
1027 !dsa_order_invariant.pass_set;
1028 }
1029
1030 /* No color buffers are enabled for writing. */
1031 if (!colormask)
1032 return true;
1033
1034 unsigned blendmask = colormask & blend->blend_enable_4bit;
1035
1036 if (blendmask) {
1037 /* Only commutative blending. */
1038 if (blendmask & ~blend->commutative_4bit)
1039 return false;
1040
1041 if (!dsa_order_invariant.pass_set)
1042 return false;
1043 }
1044
1045 if (colormask & ~blendmask)
1046 return false;
1047
1048 return true;
1049 }
1050
1051 static void
1052 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1053 struct radv_blend_state *blend,
1054 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1055 {
1056 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
1057 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1058 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1059 bool out_of_order_rast = false;
1060 int ps_iter_samples = 1;
1061 uint32_t mask = 0xffff;
1062
1063 if (vkms) {
1064 ms->num_samples = vkms->rasterizationSamples;
1065
1066 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1067 *
1068 * "Sample shading is enabled for a graphics pipeline:
1069 *
1070 * - If the interface of the fragment shader entry point of the
1071 * graphics pipeline includes an input variable decorated
1072 * with SampleId or SamplePosition. In this case
1073 * minSampleShadingFactor takes the value 1.0.
1074 * - Else if the sampleShadingEnable member of the
1075 * VkPipelineMultisampleStateCreateInfo structure specified
1076 * when creating the graphics pipeline is set to VK_TRUE. In
1077 * this case minSampleShadingFactor takes the value of
1078 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1079 *
1080 * Otherwise, sample shading is considered disabled."
1081 */
1082 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.force_persample) {
1083 ps_iter_samples = ms->num_samples;
1084 } else {
1085 ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
1086 }
1087 } else {
1088 ms->num_samples = 1;
1089 }
1090
1091 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1092 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1093 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1094 /* Out-of-order rasterization is explicitly enabled by the
1095 * application.
1096 */
1097 out_of_order_rast = true;
1098 } else {
1099 /* Determine if the driver can enable out-of-order
1100 * rasterization internally.
1101 */
1102 out_of_order_rast =
1103 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1104 }
1105
1106 ms->pa_sc_aa_config = 0;
1107 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1108 S_028804_INCOHERENT_EQAA_READS(1) |
1109 S_028804_INTERPOLATE_COMP_Z(1) |
1110 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1111 ms->pa_sc_mode_cntl_1 =
1112 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1113 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1114 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
1115 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1116 /* always 1: */
1117 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1118 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1119 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1120 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1121 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1122 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1123 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1124 S_028A48_VPORT_SCISSOR_ENABLE(1);
1125
1126 const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line =
1127 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1128 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
1129 if (rast_line) {
1130 ms->pa_sc_mode_cntl_0 |= S_028A48_LINE_STIPPLE_ENABLE(rast_line->stippledLineEnable);
1131 if (rast_line->lineRasterizationMode == VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT) {
1132 /* From the Vulkan spec 1.1.129:
1133 *
1134 * "When VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT lines
1135 * are being rasterized, sample locations may all be
1136 * treated as being at the pixel center (this may
1137 * affect attribute and depth interpolation)."
1138 */
1139 ms->num_samples = 1;
1140 }
1141 }
1142
1143 if (ms->num_samples > 1) {
1144 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1145 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1146 uint32_t z_samples = subpass->depth_stencil_attachment ? subpass->depth_sample_count : ms->num_samples;
1147 unsigned log_samples = util_logbase2(ms->num_samples);
1148 unsigned log_z_samples = util_logbase2(z_samples);
1149 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1150 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1151 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
1152 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1153 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1154 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1155 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1156 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) |
1157 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples) | /* CM_R_028BE0_PA_SC_AA_CONFIG */
1158 S_028BE0_COVERED_CENTROID_IS_CENTER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3);
1159 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1160 if (ps_iter_samples > 1)
1161 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1162 }
1163
1164 if (vkms && vkms->pSampleMask) {
1165 mask = vkms->pSampleMask[0] & 0xffff;
1166 }
1167
1168 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1169 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1170 }
1171
1172 static bool
1173 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1174 {
1175 switch (topology) {
1176 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1177 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1178 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1179 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1180 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1181 return false;
1182 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1183 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1184 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1185 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1186 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1187 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1188 return true;
1189 default:
1190 unreachable("unhandled primitive type");
1191 }
1192 }
1193
1194 static uint32_t
1195 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1196 {
1197 switch (gl_prim) {
1198 case 0: /* GL_POINTS */
1199 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1200 case 1: /* GL_LINES */
1201 case 3: /* GL_LINE_STRIP */
1202 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1203 case 0x8E7A: /* GL_ISOLINES */
1204 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1205
1206 case 4: /* GL_TRIANGLES */
1207 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1208 case 5: /* GL_TRIANGLE_STRIP */
1209 case 7: /* GL_QUADS */
1210 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1211 default:
1212 assert(0);
1213 return 0;
1214 }
1215 }
1216
1217 static uint32_t
1218 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1219 {
1220 switch (topology) {
1221 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1222 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1223 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1224 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1225 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1226 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1227 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1228 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1229 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1230 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1231 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1232 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1233 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1234 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1235 default:
1236 assert(0);
1237 return 0;
1238 }
1239 }
1240
1241 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1242 {
1243 switch(state) {
1244 case VK_DYNAMIC_STATE_VIEWPORT:
1245 case VK_DYNAMIC_STATE_VIEWPORT_WITH_COUNT_EXT:
1246 return RADV_DYNAMIC_VIEWPORT;
1247 case VK_DYNAMIC_STATE_SCISSOR:
1248 case VK_DYNAMIC_STATE_SCISSOR_WITH_COUNT_EXT:
1249 return RADV_DYNAMIC_SCISSOR;
1250 case VK_DYNAMIC_STATE_LINE_WIDTH:
1251 return RADV_DYNAMIC_LINE_WIDTH;
1252 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1253 return RADV_DYNAMIC_DEPTH_BIAS;
1254 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1255 return RADV_DYNAMIC_BLEND_CONSTANTS;
1256 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1257 return RADV_DYNAMIC_DEPTH_BOUNDS;
1258 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1259 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1260 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1261 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1262 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1263 return RADV_DYNAMIC_STENCIL_REFERENCE;
1264 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1265 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1266 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
1267 return RADV_DYNAMIC_SAMPLE_LOCATIONS;
1268 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT:
1269 return RADV_DYNAMIC_LINE_STIPPLE;
1270 case VK_DYNAMIC_STATE_CULL_MODE_EXT:
1271 return RADV_DYNAMIC_CULL_MODE;
1272 case VK_DYNAMIC_STATE_FRONT_FACE_EXT:
1273 return RADV_DYNAMIC_FRONT_FACE;
1274 case VK_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY_EXT:
1275 return RADV_DYNAMIC_PRIMITIVE_TOPOLOGY;
1276 case VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT:
1277 return RADV_DYNAMIC_DEPTH_TEST_ENABLE;
1278 case VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT:
1279 return RADV_DYNAMIC_DEPTH_WRITE_ENABLE;
1280 case VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT:
1281 return RADV_DYNAMIC_DEPTH_COMPARE_OP;
1282 case VK_DYNAMIC_STATE_DEPTH_BOUNDS_TEST_ENABLE_EXT:
1283 return RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE;
1284 case VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT:
1285 return RADV_DYNAMIC_STENCIL_TEST_ENABLE;
1286 case VK_DYNAMIC_STATE_STENCIL_OP_EXT:
1287 return RADV_DYNAMIC_STENCIL_OP;
1288 case VK_DYNAMIC_STATE_VERTEX_INPUT_BINDING_STRIDE_EXT:
1289 return RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE;
1290 default:
1291 unreachable("Unhandled dynamic state");
1292 }
1293 }
1294
1295 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1296 {
1297 uint32_t states = RADV_DYNAMIC_ALL;
1298
1299 /* If rasterization is disabled we do not care about any of the
1300 * dynamic states, since they are all rasterization related only,
1301 * except primitive topology and vertex binding stride.
1302 */
1303 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1304 return RADV_DYNAMIC_PRIMITIVE_TOPOLOGY |
1305 RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE;
1306
1307 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1308 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1309
1310 if (!pCreateInfo->pDepthStencilState ||
1311 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1312 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1313
1314 if (!pCreateInfo->pDepthStencilState ||
1315 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1316 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1317 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1318 RADV_DYNAMIC_STENCIL_REFERENCE);
1319
1320 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1321 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1322
1323 if (!pCreateInfo->pMultisampleState ||
1324 !vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1325 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT))
1326 states &= ~RADV_DYNAMIC_SAMPLE_LOCATIONS;
1327
1328 if (!pCreateInfo->pRasterizationState ||
1329 !vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1330 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT))
1331 states &= ~RADV_DYNAMIC_LINE_STIPPLE;
1332
1333 /* TODO: blend constants & line width. */
1334
1335 return states;
1336 }
1337
1338 static void
1339 radv_pipeline_init_input_assembly_state(struct radv_pipeline *pipeline,
1340 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1341 const struct radv_graphics_pipeline_create_info *extra)
1342 {
1343 const VkPipelineInputAssemblyStateCreateInfo *ia_state = pCreateInfo->pInputAssemblyState;
1344 struct radv_shader_variant *tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
1345 struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
1346
1347 pipeline->graphics.prim_restart_enable = !!ia_state->primitiveRestartEnable;
1348 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(ia_state->topology);
1349
1350 if (radv_pipeline_has_gs(pipeline)) {
1351 if (si_conv_gl_prim_to_gs_out(gs->info.gs.output_prim) == V_028A6C_OUTPRIM_TYPE_TRISTRIP)
1352 pipeline->graphics.can_use_guardband = true;
1353 } else if (radv_pipeline_has_tess(pipeline)) {
1354 if (!tes->info.tes.point_mode &&
1355 si_conv_gl_prim_to_gs_out(tes->info.tes.primitive_mode) == V_028A6C_OUTPRIM_TYPE_TRISTRIP)
1356 pipeline->graphics.can_use_guardband = true;
1357 }
1358
1359 if (extra && extra->use_rectlist) {
1360 pipeline->graphics.can_use_guardband = true;
1361 }
1362 }
1363
1364 static void
1365 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1366 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1367 const struct radv_graphics_pipeline_create_info *extra)
1368 {
1369 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1370 uint32_t states = needed_states;
1371 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1372 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1373
1374 pipeline->dynamic_state = default_dynamic_state;
1375 pipeline->graphics.needed_dynamic_state = needed_states;
1376
1377 if (pCreateInfo->pDynamicState) {
1378 /* Remove all of the states that are marked as dynamic */
1379 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1380 for (uint32_t s = 0; s < count; s++)
1381 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1382 }
1383
1384 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1385
1386 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1387 assert(pCreateInfo->pViewportState);
1388
1389 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1390 if (states & RADV_DYNAMIC_VIEWPORT) {
1391 typed_memcpy(dynamic->viewport.viewports,
1392 pCreateInfo->pViewportState->pViewports,
1393 pCreateInfo->pViewportState->viewportCount);
1394 }
1395 }
1396
1397 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1398 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1399 if (states & RADV_DYNAMIC_SCISSOR) {
1400 typed_memcpy(dynamic->scissor.scissors,
1401 pCreateInfo->pViewportState->pScissors,
1402 pCreateInfo->pViewportState->scissorCount);
1403 }
1404 }
1405
1406 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1407 assert(pCreateInfo->pRasterizationState);
1408 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1409 }
1410
1411 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1412 assert(pCreateInfo->pRasterizationState);
1413 dynamic->depth_bias.bias =
1414 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1415 dynamic->depth_bias.clamp =
1416 pCreateInfo->pRasterizationState->depthBiasClamp;
1417 dynamic->depth_bias.slope =
1418 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1419 }
1420
1421 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1422 *
1423 * pColorBlendState is [...] NULL if the pipeline has rasterization
1424 * disabled or if the subpass of the render pass the pipeline is
1425 * created against does not use any color attachments.
1426 */
1427 if (subpass->has_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1428 assert(pCreateInfo->pColorBlendState);
1429 typed_memcpy(dynamic->blend_constants,
1430 pCreateInfo->pColorBlendState->blendConstants, 4);
1431 }
1432
1433 if (states & RADV_DYNAMIC_CULL_MODE) {
1434 dynamic->cull_mode =
1435 pCreateInfo->pRasterizationState->cullMode;
1436 }
1437
1438 if (states & RADV_DYNAMIC_FRONT_FACE) {
1439 dynamic->front_face =
1440 pCreateInfo->pRasterizationState->frontFace;
1441 }
1442
1443 if (states & RADV_DYNAMIC_PRIMITIVE_TOPOLOGY) {
1444 dynamic->primitive_topology =
1445 si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
1446 if (extra && extra->use_rectlist) {
1447 dynamic->primitive_topology = V_008958_DI_PT_RECTLIST;
1448 }
1449 }
1450
1451 /* If there is no depthstencil attachment, then don't read
1452 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1453 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1454 * no need to override the depthstencil defaults in
1455 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1456 *
1457 * Section 9.2 of the Vulkan 1.0.15 spec says:
1458 *
1459 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1460 * disabled or if the subpass of the render pass the pipeline is created
1461 * against does not use a depth/stencil attachment.
1462 */
1463 if (needed_states && subpass->depth_stencil_attachment) {
1464 assert(pCreateInfo->pDepthStencilState);
1465
1466 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1467 dynamic->depth_bounds.min =
1468 pCreateInfo->pDepthStencilState->minDepthBounds;
1469 dynamic->depth_bounds.max =
1470 pCreateInfo->pDepthStencilState->maxDepthBounds;
1471 }
1472
1473 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1474 dynamic->stencil_compare_mask.front =
1475 pCreateInfo->pDepthStencilState->front.compareMask;
1476 dynamic->stencil_compare_mask.back =
1477 pCreateInfo->pDepthStencilState->back.compareMask;
1478 }
1479
1480 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1481 dynamic->stencil_write_mask.front =
1482 pCreateInfo->pDepthStencilState->front.writeMask;
1483 dynamic->stencil_write_mask.back =
1484 pCreateInfo->pDepthStencilState->back.writeMask;
1485 }
1486
1487 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1488 dynamic->stencil_reference.front =
1489 pCreateInfo->pDepthStencilState->front.reference;
1490 dynamic->stencil_reference.back =
1491 pCreateInfo->pDepthStencilState->back.reference;
1492 }
1493
1494 if (states & RADV_DYNAMIC_DEPTH_TEST_ENABLE) {
1495 dynamic->depth_test_enable =
1496 pCreateInfo->pDepthStencilState->depthTestEnable;
1497 }
1498
1499 if (states & RADV_DYNAMIC_DEPTH_WRITE_ENABLE) {
1500 dynamic->depth_write_enable =
1501 pCreateInfo->pDepthStencilState->depthWriteEnable;
1502 }
1503
1504 if (states & RADV_DYNAMIC_DEPTH_COMPARE_OP) {
1505 dynamic->depth_compare_op =
1506 pCreateInfo->pDepthStencilState->depthCompareOp;
1507 }
1508
1509 if (states & RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE) {
1510 dynamic->depth_bounds_test_enable =
1511 pCreateInfo->pDepthStencilState->depthBoundsTestEnable;
1512 }
1513
1514 if (states & RADV_DYNAMIC_STENCIL_TEST_ENABLE) {
1515 dynamic->stencil_test_enable =
1516 pCreateInfo->pDepthStencilState->stencilTestEnable;
1517 }
1518
1519 if (states & RADV_DYNAMIC_STENCIL_OP) {
1520 dynamic->stencil_op.front.compare_op =
1521 pCreateInfo->pDepthStencilState->front.compareOp;
1522 dynamic->stencil_op.front.fail_op =
1523 pCreateInfo->pDepthStencilState->front.failOp;
1524 dynamic->stencil_op.front.pass_op =
1525 pCreateInfo->pDepthStencilState->front.passOp;
1526 dynamic->stencil_op.front.depth_fail_op =
1527 pCreateInfo->pDepthStencilState->front.depthFailOp;
1528
1529 dynamic->stencil_op.back.compare_op =
1530 pCreateInfo->pDepthStencilState->back.compareOp;
1531 dynamic->stencil_op.back.fail_op =
1532 pCreateInfo->pDepthStencilState->back.failOp;
1533 dynamic->stencil_op.back.pass_op =
1534 pCreateInfo->pDepthStencilState->back.passOp;
1535 dynamic->stencil_op.back.depth_fail_op =
1536 pCreateInfo->pDepthStencilState->back.depthFailOp;
1537 }
1538 }
1539
1540 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1541 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1542 if (needed_states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1543 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1544 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1545 typed_memcpy(dynamic->discard_rectangle.rectangles,
1546 discard_rectangle_info->pDiscardRectangles,
1547 discard_rectangle_info->discardRectangleCount);
1548 }
1549 }
1550
1551 if (needed_states & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
1552 const VkPipelineSampleLocationsStateCreateInfoEXT *sample_location_info =
1553 vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1554 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1555 /* If sampleLocationsEnable is VK_FALSE, the default sample
1556 * locations are used and the values specified in
1557 * sampleLocationsInfo are ignored.
1558 */
1559 if (sample_location_info->sampleLocationsEnable) {
1560 const VkSampleLocationsInfoEXT *pSampleLocationsInfo =
1561 &sample_location_info->sampleLocationsInfo;
1562
1563 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
1564
1565 dynamic->sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
1566 dynamic->sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
1567 dynamic->sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
1568 typed_memcpy(&dynamic->sample_location.locations[0],
1569 pSampleLocationsInfo->pSampleLocations,
1570 pSampleLocationsInfo->sampleLocationsCount);
1571 }
1572 }
1573
1574 const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line_info =
1575 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1576 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
1577 if (needed_states & RADV_DYNAMIC_LINE_STIPPLE) {
1578 dynamic->line_stipple.factor = rast_line_info->lineStippleFactor;
1579 dynamic->line_stipple.pattern = rast_line_info->lineStipplePattern;
1580 }
1581
1582 if (!(states & RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE))
1583 pipeline->graphics.uses_dynamic_stride = true;
1584
1585 pipeline->dynamic_state.mask = states;
1586 }
1587
1588 static void
1589 gfx9_get_gs_info(const struct radv_pipeline_key *key,
1590 const struct radv_pipeline *pipeline,
1591 nir_shader **nir,
1592 struct radv_shader_info *infos,
1593 struct gfx9_gs_info *out)
1594 {
1595 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1596 struct radv_es_output_info *es_info;
1597 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1598 es_info = nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1599 else
1600 es_info = nir[MESA_SHADER_TESS_CTRL] ?
1601 &infos[MESA_SHADER_TESS_EVAL].tes.es_info :
1602 &infos[MESA_SHADER_VERTEX].vs.es_info;
1603
1604 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1605 bool uses_adjacency;
1606 switch(key->topology) {
1607 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1608 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1609 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1610 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1611 uses_adjacency = true;
1612 break;
1613 default:
1614 uses_adjacency = false;
1615 break;
1616 }
1617
1618 /* All these are in dwords: */
1619 /* We can't allow using the whole LDS, because GS waves compete with
1620 * other shader stages for LDS space. */
1621 const unsigned max_lds_size = 8 * 1024;
1622 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1623 unsigned esgs_lds_size;
1624
1625 /* All these are per subgroup: */
1626 const unsigned max_out_prims = 32 * 1024;
1627 const unsigned max_es_verts = 255;
1628 const unsigned ideal_gs_prims = 64;
1629 unsigned max_gs_prims, gs_prims;
1630 unsigned min_es_verts, es_verts, worst_case_es_verts;
1631
1632 if (uses_adjacency || gs_num_invocations > 1)
1633 max_gs_prims = 127 / gs_num_invocations;
1634 else
1635 max_gs_prims = 255;
1636
1637 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1638 * Make sure we don't go over the maximum value.
1639 */
1640 if (gs_info->gs.vertices_out > 0) {
1641 max_gs_prims = MIN2(max_gs_prims,
1642 max_out_prims /
1643 (gs_info->gs.vertices_out * gs_num_invocations));
1644 }
1645 assert(max_gs_prims > 0);
1646
1647 /* If the primitive has adjacency, halve the number of vertices
1648 * that will be reused in multiple primitives.
1649 */
1650 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1651
1652 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1653 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1654
1655 /* Compute ESGS LDS size based on the worst case number of ES vertices
1656 * needed to create the target number of GS prims per subgroup.
1657 */
1658 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1659
1660 /* If total LDS usage is too big, refactor partitions based on ratio
1661 * of ESGS item sizes.
1662 */
1663 if (esgs_lds_size > max_lds_size) {
1664 /* Our target GS Prims Per Subgroup was too large. Calculate
1665 * the maximum number of GS Prims Per Subgroup that will fit
1666 * into LDS, capped by the maximum that the hardware can support.
1667 */
1668 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1669 max_gs_prims);
1670 assert(gs_prims > 0);
1671 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1672 max_es_verts);
1673
1674 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1675 assert(esgs_lds_size <= max_lds_size);
1676 }
1677
1678 /* Now calculate remaining ESGS information. */
1679 if (esgs_lds_size)
1680 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1681 else
1682 es_verts = max_es_verts;
1683
1684 /* Vertices for adjacency primitives are not always reused, so restore
1685 * it for ES_VERTS_PER_SUBGRP.
1686 */
1687 min_es_verts = gs_info->gs.vertices_in;
1688
1689 /* For normal primitives, the VGT only checks if they are past the ES
1690 * verts per subgroup after allocating a full GS primitive and if they
1691 * are, kick off a new subgroup. But if those additional ES verts are
1692 * unique (e.g. not reused) we need to make sure there is enough LDS
1693 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1694 */
1695 es_verts -= min_es_verts - 1;
1696
1697 uint32_t es_verts_per_subgroup = es_verts;
1698 uint32_t gs_prims_per_subgroup = gs_prims;
1699 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1700 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1701 out->lds_size = align(esgs_lds_size, 128) / 128;
1702 out->vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1703 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1704 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1705 out->vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1706 out->vgt_esgs_ring_itemsize = esgs_itemsize;
1707 assert(max_prims_per_subgroup <= max_out_prims);
1708 }
1709
1710 static void clamp_gsprims_to_esverts(unsigned *max_gsprims, unsigned max_esverts,
1711 unsigned min_verts_per_prim, bool use_adjacency)
1712 {
1713 unsigned max_reuse = max_esverts - min_verts_per_prim;
1714 if (use_adjacency)
1715 max_reuse /= 2;
1716 *max_gsprims = MIN2(*max_gsprims, 1 + max_reuse);
1717 }
1718
1719 static unsigned
1720 radv_get_num_input_vertices(nir_shader **nir)
1721 {
1722 if (nir[MESA_SHADER_GEOMETRY]) {
1723 nir_shader *gs = nir[MESA_SHADER_GEOMETRY];
1724
1725 return gs->info.gs.vertices_in;
1726 }
1727
1728 if (nir[MESA_SHADER_TESS_CTRL]) {
1729 nir_shader *tes = nir[MESA_SHADER_TESS_EVAL];
1730
1731 if (tes->info.tess.point_mode)
1732 return 1;
1733 if (tes->info.tess.primitive_mode == GL_ISOLINES)
1734 return 2;
1735 return 3;
1736 }
1737
1738 return 3;
1739 }
1740
1741 static void
1742 gfx10_get_ngg_info(const struct radv_pipeline_key *key,
1743 struct radv_pipeline *pipeline,
1744 nir_shader **nir,
1745 struct radv_shader_info *infos,
1746 struct gfx10_ngg_info *ngg)
1747 {
1748 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1749 struct radv_es_output_info *es_info =
1750 nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1751 unsigned gs_type = nir[MESA_SHADER_GEOMETRY] ? MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX;
1752 unsigned max_verts_per_prim = radv_get_num_input_vertices(nir);
1753 unsigned min_verts_per_prim =
1754 gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1;
1755 unsigned gs_num_invocations = nir[MESA_SHADER_GEOMETRY] ? MAX2(gs_info->gs.invocations, 1) : 1;
1756 bool uses_adjacency;
1757 switch(key->topology) {
1758 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1759 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1760 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1761 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1762 uses_adjacency = true;
1763 break;
1764 default:
1765 uses_adjacency = false;
1766 break;
1767 }
1768
1769 /* All these are in dwords: */
1770 /* We can't allow using the whole LDS, because GS waves compete with
1771 * other shader stages for LDS space.
1772 *
1773 * TODO: We should really take the shader's internal LDS use into
1774 * account. The linker will fail if the size is greater than
1775 * 8K dwords.
1776 */
1777 const unsigned max_lds_size = 8 * 1024 - 768;
1778 const unsigned target_lds_size = max_lds_size;
1779 unsigned esvert_lds_size = 0;
1780 unsigned gsprim_lds_size = 0;
1781
1782 /* All these are per subgroup: */
1783 bool max_vert_out_per_gs_instance = false;
1784 unsigned max_esverts_base = 256;
1785 unsigned max_gsprims_base = 128; /* default prim group size clamp */
1786
1787 /* Hardware has the following non-natural restrictions on the value
1788 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1789 * the draw:
1790 * - at most 252 for any line input primitive type
1791 * - at most 251 for any quad input primitive type
1792 * - at most 251 for triangle strips with adjacency (this happens to
1793 * be the natural limit for triangle *lists* with adjacency)
1794 */
1795 max_esverts_base = MIN2(max_esverts_base, 251 + max_verts_per_prim - 1);
1796
1797 if (gs_type == MESA_SHADER_GEOMETRY) {
1798 unsigned max_out_verts_per_gsprim =
1799 gs_info->gs.vertices_out * gs_num_invocations;
1800
1801 if (max_out_verts_per_gsprim <= 256) {
1802 if (max_out_verts_per_gsprim) {
1803 max_gsprims_base = MIN2(max_gsprims_base,
1804 256 / max_out_verts_per_gsprim);
1805 }
1806 } else {
1807 /* Use special multi-cycling mode in which each GS
1808 * instance gets its own subgroup. Does not work with
1809 * tessellation. */
1810 max_vert_out_per_gs_instance = true;
1811 max_gsprims_base = 1;
1812 max_out_verts_per_gsprim = gs_info->gs.vertices_out;
1813 }
1814
1815 esvert_lds_size = es_info->esgs_itemsize / 4;
1816 gsprim_lds_size = (gs_info->gs.gsvs_vertex_size / 4 + 1) * max_out_verts_per_gsprim;
1817 } else {
1818 /* VS and TES. */
1819 /* LDS size for passing data from GS to ES. */
1820 struct radv_streamout_info *so_info = nir[MESA_SHADER_TESS_CTRL]
1821 ? &infos[MESA_SHADER_TESS_EVAL].so
1822 : &infos[MESA_SHADER_VERTEX].so;
1823
1824 if (so_info->num_outputs)
1825 esvert_lds_size = 4 * so_info->num_outputs + 1;
1826
1827 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1828 * corresponding to the ES thread of the provoking vertex. All
1829 * ES threads load and export PrimitiveID for their thread.
1830 */
1831 if (!nir[MESA_SHADER_TESS_CTRL] &&
1832 infos[MESA_SHADER_VERTEX].vs.outinfo.export_prim_id)
1833 esvert_lds_size = MAX2(esvert_lds_size, 1);
1834 }
1835
1836 unsigned max_gsprims = max_gsprims_base;
1837 unsigned max_esverts = max_esverts_base;
1838
1839 if (esvert_lds_size)
1840 max_esverts = MIN2(max_esverts, target_lds_size / esvert_lds_size);
1841 if (gsprim_lds_size)
1842 max_gsprims = MIN2(max_gsprims, target_lds_size / gsprim_lds_size);
1843
1844 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1845 clamp_gsprims_to_esverts(&max_gsprims, max_esverts, min_verts_per_prim, uses_adjacency);
1846 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1847
1848 if (esvert_lds_size || gsprim_lds_size) {
1849 /* Now that we have a rough proportionality between esverts
1850 * and gsprims based on the primitive type, scale both of them
1851 * down simultaneously based on required LDS space.
1852 *
1853 * We could be smarter about this if we knew how much vertex
1854 * reuse to expect.
1855 */
1856 unsigned lds_total = max_esverts * esvert_lds_size +
1857 max_gsprims * gsprim_lds_size;
1858 if (lds_total > target_lds_size) {
1859 max_esverts = max_esverts * target_lds_size / lds_total;
1860 max_gsprims = max_gsprims * target_lds_size / lds_total;
1861
1862 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1863 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1864 min_verts_per_prim, uses_adjacency);
1865 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1866 }
1867 }
1868
1869 /* Round up towards full wave sizes for better ALU utilization. */
1870 if (!max_vert_out_per_gs_instance) {
1871 unsigned orig_max_esverts;
1872 unsigned orig_max_gsprims;
1873 unsigned wavesize;
1874
1875 if (gs_type == MESA_SHADER_GEOMETRY) {
1876 wavesize = gs_info->wave_size;
1877 } else {
1878 wavesize = nir[MESA_SHADER_TESS_CTRL]
1879 ? infos[MESA_SHADER_TESS_EVAL].wave_size
1880 : infos[MESA_SHADER_VERTEX].wave_size;
1881 }
1882
1883 do {
1884 orig_max_esverts = max_esverts;
1885 orig_max_gsprims = max_gsprims;
1886
1887 max_esverts = align(max_esverts, wavesize);
1888 max_esverts = MIN2(max_esverts, max_esverts_base);
1889 if (esvert_lds_size)
1890 max_esverts = MIN2(max_esverts,
1891 (max_lds_size - max_gsprims * gsprim_lds_size) /
1892 esvert_lds_size);
1893 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1894
1895 max_gsprims = align(max_gsprims, wavesize);
1896 max_gsprims = MIN2(max_gsprims, max_gsprims_base);
1897 if (gsprim_lds_size)
1898 max_gsprims = MIN2(max_gsprims,
1899 (max_lds_size - max_esverts * esvert_lds_size) /
1900 gsprim_lds_size);
1901 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1902 min_verts_per_prim, uses_adjacency);
1903 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1904 } while (orig_max_esverts != max_esverts || orig_max_gsprims != max_gsprims);
1905 }
1906
1907 /* Hardware restriction: minimum value of max_esverts */
1908 max_esverts = MAX2(max_esverts, 23 + max_verts_per_prim);
1909
1910 unsigned max_out_vertices =
1911 max_vert_out_per_gs_instance ? gs_info->gs.vertices_out :
1912 gs_type == MESA_SHADER_GEOMETRY ?
1913 max_gsprims * gs_num_invocations * gs_info->gs.vertices_out :
1914 max_esverts;
1915 assert(max_out_vertices <= 256);
1916
1917 unsigned prim_amp_factor = 1;
1918 if (gs_type == MESA_SHADER_GEOMETRY) {
1919 /* Number of output primitives per GS input primitive after
1920 * GS instancing. */
1921 prim_amp_factor = gs_info->gs.vertices_out;
1922 }
1923
1924 /* The GE only checks against the maximum number of ES verts after
1925 * allocating a full GS primitive. So we need to ensure that whenever
1926 * this check passes, there is enough space for a full primitive without
1927 * vertex reuse.
1928 */
1929 ngg->hw_max_esverts = max_esverts - max_verts_per_prim + 1;
1930 ngg->max_gsprims = max_gsprims;
1931 ngg->max_out_verts = max_out_vertices;
1932 ngg->prim_amp_factor = prim_amp_factor;
1933 ngg->max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
1934 ngg->ngg_emit_size = max_gsprims * gsprim_lds_size;
1935 ngg->esgs_ring_size = 4 * max_esverts * esvert_lds_size;
1936
1937 if (gs_type == MESA_SHADER_GEOMETRY) {
1938 ngg->vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
1939 } else {
1940 ngg->vgt_esgs_ring_itemsize = 1;
1941 }
1942
1943 pipeline->graphics.esgs_ring_size = ngg->esgs_ring_size;
1944
1945 assert(ngg->hw_max_esverts >= 24); /* HW limitation */
1946 }
1947
1948 static void
1949 calculate_gs_ring_sizes(struct radv_pipeline *pipeline,
1950 const struct gfx9_gs_info *gs)
1951 {
1952 struct radv_device *device = pipeline->device;
1953 unsigned num_se = device->physical_device->rad_info.max_se;
1954 unsigned wave_size = 64;
1955 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1956 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1957 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1958 */
1959 unsigned gs_vertex_reuse =
1960 (device->physical_device->rad_info.chip_class >= GFX8 ? 32 : 16) * num_se;
1961 unsigned alignment = 256 * num_se;
1962 /* The maximum size is 63.999 MB per SE. */
1963 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1964 struct radv_shader_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1965
1966 /* Calculate the minimum size. */
1967 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1968 wave_size, alignment);
1969 /* These are recommended sizes, not minimum sizes. */
1970 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1971 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1972 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1973 gs_info->gs.max_gsvs_emit_size;
1974
1975 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1976 esgs_ring_size = align(esgs_ring_size, alignment);
1977 gsvs_ring_size = align(gsvs_ring_size, alignment);
1978
1979 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
1980 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1981
1982 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1983 }
1984
1985 struct radv_shader_variant *
1986 radv_get_shader(struct radv_pipeline *pipeline,
1987 gl_shader_stage stage)
1988 {
1989 if (stage == MESA_SHADER_VERTEX) {
1990 if (pipeline->shaders[MESA_SHADER_VERTEX])
1991 return pipeline->shaders[MESA_SHADER_VERTEX];
1992 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1993 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1994 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1995 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1996 } else if (stage == MESA_SHADER_TESS_EVAL) {
1997 if (!radv_pipeline_has_tess(pipeline))
1998 return NULL;
1999 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
2000 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
2001 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
2002 return pipeline->shaders[MESA_SHADER_GEOMETRY];
2003 }
2004 return pipeline->shaders[stage];
2005 }
2006
2007 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
2008 {
2009 if (radv_pipeline_has_gs(pipeline))
2010 if (radv_pipeline_has_ngg(pipeline))
2011 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
2012 else
2013 return &pipeline->gs_copy_shader->info.vs.outinfo;
2014 else if (radv_pipeline_has_tess(pipeline))
2015 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
2016 else
2017 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
2018 }
2019
2020 static void
2021 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
2022 {
2023 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
2024 int shader_count = 0;
2025
2026 if(shaders[MESA_SHADER_FRAGMENT]) {
2027 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
2028 }
2029 if(shaders[MESA_SHADER_GEOMETRY]) {
2030 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
2031 }
2032 if(shaders[MESA_SHADER_TESS_EVAL]) {
2033 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
2034 }
2035 if(shaders[MESA_SHADER_TESS_CTRL]) {
2036 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
2037 }
2038 if(shaders[MESA_SHADER_VERTEX]) {
2039 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
2040 }
2041
2042 if (shader_count > 1) {
2043 unsigned first = ordered_shaders[shader_count - 1]->info.stage;
2044 unsigned last = ordered_shaders[0]->info.stage;
2045
2046 if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
2047 ordered_shaders[1]->info.has_transform_feedback_varyings)
2048 nir_link_xfb_varyings(ordered_shaders[1], ordered_shaders[0]);
2049
2050 for (int i = 0; i < shader_count; ++i) {
2051 nir_variable_mode mask = 0;
2052
2053 if (ordered_shaders[i]->info.stage != first)
2054 mask = mask | nir_var_shader_in;
2055
2056 if (ordered_shaders[i]->info.stage != last)
2057 mask = mask | nir_var_shader_out;
2058
2059 nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
2060 radv_optimize_nir(ordered_shaders[i], false, false);
2061 }
2062 }
2063
2064 for (int i = 1; i < shader_count; ++i) {
2065 nir_lower_io_arrays_to_elements(ordered_shaders[i],
2066 ordered_shaders[i - 1]);
2067
2068 if (nir_link_opt_varyings(ordered_shaders[i],
2069 ordered_shaders[i - 1]))
2070 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2071
2072 nir_remove_dead_variables(ordered_shaders[i],
2073 nir_var_shader_out, NULL);
2074 nir_remove_dead_variables(ordered_shaders[i - 1],
2075 nir_var_shader_in, NULL);
2076
2077 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
2078 ordered_shaders[i - 1]);
2079
2080 nir_compact_varyings(ordered_shaders[i],
2081 ordered_shaders[i - 1], true);
2082
2083 if (progress) {
2084 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
2085 ac_lower_indirect_derefs(ordered_shaders[i],
2086 pipeline->device->physical_device->rad_info.chip_class);
2087 }
2088 radv_optimize_nir(ordered_shaders[i], false, false);
2089
2090 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
2091 ac_lower_indirect_derefs(ordered_shaders[i - 1],
2092 pipeline->device->physical_device->rad_info.chip_class);
2093 }
2094 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2095 }
2096 }
2097 }
2098
2099 static void
2100 radv_set_linked_driver_locations(struct radv_pipeline *pipeline, nir_shader **shaders,
2101 struct radv_shader_info infos[MESA_SHADER_STAGES])
2102 {
2103 bool has_tess = shaders[MESA_SHADER_TESS_CTRL];
2104 bool has_gs = shaders[MESA_SHADER_GEOMETRY];
2105
2106 if (!has_tess && !has_gs)
2107 return;
2108
2109 unsigned vs_info_idx = MESA_SHADER_VERTEX;
2110 unsigned tes_info_idx = MESA_SHADER_TESS_EVAL;
2111
2112 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2113 /* These are merged into the next stage */
2114 vs_info_idx = has_tess ? MESA_SHADER_TESS_CTRL : MESA_SHADER_GEOMETRY;
2115 tes_info_idx = has_gs ? MESA_SHADER_GEOMETRY : MESA_SHADER_TESS_EVAL;
2116 }
2117
2118 if (has_tess) {
2119 nir_linked_io_var_info vs2tcs =
2120 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_VERTEX], shaders[MESA_SHADER_TESS_CTRL]);
2121 nir_linked_io_var_info tcs2tes =
2122 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_TESS_CTRL], shaders[MESA_SHADER_TESS_EVAL]);
2123
2124 infos[vs_info_idx].vs.num_linked_outputs = vs2tcs.num_linked_io_vars;
2125 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_inputs = vs2tcs.num_linked_io_vars;
2126 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_outputs = tcs2tes.num_linked_io_vars;
2127 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_patch_outputs = tcs2tes.num_linked_patch_io_vars;
2128 infos[tes_info_idx].tes.num_linked_inputs = tcs2tes.num_linked_io_vars;
2129 infos[tes_info_idx].tes.num_linked_patch_inputs = tcs2tes.num_linked_patch_io_vars;
2130
2131 if (has_gs) {
2132 nir_linked_io_var_info tes2gs =
2133 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_TESS_EVAL], shaders[MESA_SHADER_GEOMETRY]);
2134
2135 infos[tes_info_idx].tes.num_linked_outputs = tes2gs.num_linked_io_vars;
2136 infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = tes2gs.num_linked_io_vars;
2137 }
2138 } else if (has_gs) {
2139 nir_linked_io_var_info vs2gs =
2140 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_VERTEX], shaders[MESA_SHADER_GEOMETRY]);
2141
2142 infos[vs_info_idx].vs.num_linked_outputs = vs2gs.num_linked_io_vars;
2143 infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = vs2gs.num_linked_io_vars;
2144 }
2145 }
2146
2147 static uint32_t
2148 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo *input_state,
2149 uint32_t attrib_binding)
2150 {
2151 for (uint32_t i = 0; i < input_state->vertexBindingDescriptionCount; i++) {
2152 const VkVertexInputBindingDescription *input_binding =
2153 &input_state->pVertexBindingDescriptions[i];
2154
2155 if (input_binding->binding == attrib_binding)
2156 return input_binding->stride;
2157 }
2158
2159 return 0;
2160 }
2161
2162 static struct radv_pipeline_key
2163 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
2164 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2165 const struct radv_blend_state *blend)
2166 {
2167 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2168 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2169 const VkPipelineVertexInputStateCreateInfo *input_state =
2170 pCreateInfo->pVertexInputState;
2171 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
2172 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
2173
2174 struct radv_pipeline_key key;
2175 memset(&key, 0, sizeof(key));
2176
2177 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
2178 key.optimisations_disabled = 1;
2179
2180 key.has_multiview_view_index = !!subpass->view_mask;
2181
2182 uint32_t binding_input_rate = 0;
2183 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
2184 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
2185 if (input_state->pVertexBindingDescriptions[i].inputRate) {
2186 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
2187 binding_input_rate |= 1u << binding;
2188 instance_rate_divisors[binding] = 1;
2189 }
2190 }
2191 if (divisor_state) {
2192 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
2193 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
2194 divisor_state->pVertexBindingDivisors[i].divisor;
2195 }
2196 }
2197
2198 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
2199 const VkVertexInputAttributeDescription *desc =
2200 &input_state->pVertexAttributeDescriptions[i];
2201 const struct vk_format_description *format_desc;
2202 unsigned location = desc->location;
2203 unsigned binding = desc->binding;
2204 unsigned num_format, data_format;
2205 int first_non_void;
2206
2207 if (binding_input_rate & (1u << binding)) {
2208 key.instance_rate_inputs |= 1u << location;
2209 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
2210 }
2211
2212 format_desc = vk_format_description(desc->format);
2213 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2214
2215 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2216 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2217
2218 key.vertex_attribute_formats[location] = data_format | (num_format << 4);
2219 key.vertex_attribute_bindings[location] = desc->binding;
2220 key.vertex_attribute_offsets[location] = desc->offset;
2221 key.vertex_attribute_strides[location] = radv_get_attrib_stride(input_state, desc->binding);
2222
2223 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8 &&
2224 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
2225 VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
2226 uint64_t adjust;
2227 switch(format) {
2228 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2229 case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
2230 adjust = RADV_ALPHA_ADJUST_SNORM;
2231 break;
2232 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2233 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
2234 adjust = RADV_ALPHA_ADJUST_SSCALED;
2235 break;
2236 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2237 case VK_FORMAT_A2B10G10R10_SINT_PACK32:
2238 adjust = RADV_ALPHA_ADJUST_SINT;
2239 break;
2240 default:
2241 adjust = 0;
2242 break;
2243 }
2244 key.vertex_alpha_adjust |= adjust << (2 * location);
2245 }
2246
2247 switch (desc->format) {
2248 case VK_FORMAT_B8G8R8A8_UNORM:
2249 case VK_FORMAT_B8G8R8A8_SNORM:
2250 case VK_FORMAT_B8G8R8A8_USCALED:
2251 case VK_FORMAT_B8G8R8A8_SSCALED:
2252 case VK_FORMAT_B8G8R8A8_UINT:
2253 case VK_FORMAT_B8G8R8A8_SINT:
2254 case VK_FORMAT_B8G8R8A8_SRGB:
2255 case VK_FORMAT_A2R10G10B10_UNORM_PACK32:
2256 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2257 case VK_FORMAT_A2R10G10B10_USCALED_PACK32:
2258 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2259 case VK_FORMAT_A2R10G10B10_UINT_PACK32:
2260 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2261 key.vertex_post_shuffle |= 1 << location;
2262 break;
2263 default:
2264 break;
2265 }
2266 }
2267
2268 const VkPipelineTessellationStateCreateInfo *tess =
2269 radv_pipeline_get_tessellation_state(pCreateInfo);
2270 if (tess)
2271 key.tess_input_vertices = tess->patchControlPoints;
2272
2273 const VkPipelineMultisampleStateCreateInfo *vkms =
2274 radv_pipeline_get_multisample_state(pCreateInfo);
2275 if (vkms && vkms->rasterizationSamples > 1) {
2276 uint32_t num_samples = vkms->rasterizationSamples;
2277 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
2278 key.num_samples = num_samples;
2279 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
2280 }
2281
2282 key.col_format = blend->spi_shader_col_format;
2283 key.is_dual_src = blend->mrt0_is_dual_src;
2284 if (pipeline->device->physical_device->rad_info.chip_class < GFX8) {
2285 key.is_int8 = blend->col_format_is_int8;
2286 key.is_int10 = blend->col_format_is_int10;
2287 }
2288
2289 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10)
2290 key.topology = pCreateInfo->pInputAssemblyState->topology;
2291
2292 return key;
2293 }
2294
2295 static bool
2296 radv_nir_stage_uses_xfb(const nir_shader *nir)
2297 {
2298 nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
2299 bool uses_xfb = !!xfb;
2300
2301 ralloc_free(xfb);
2302 return uses_xfb;
2303 }
2304
2305 static void
2306 radv_fill_shader_keys(struct radv_device *device,
2307 struct radv_shader_variant_key *keys,
2308 const struct radv_pipeline_key *key,
2309 nir_shader **nir)
2310 {
2311 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
2312 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
2313 keys[MESA_SHADER_VERTEX].vs.post_shuffle = key->vertex_post_shuffle;
2314 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) {
2315 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
2316 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_formats[i] = key->vertex_attribute_formats[i];
2317 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_bindings[i] = key->vertex_attribute_bindings[i];
2318 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i];
2319 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i];
2320 }
2321 keys[MESA_SHADER_VERTEX].vs.outprim = si_conv_prim_to_gs_out(key->topology);
2322
2323 if (nir[MESA_SHADER_TESS_CTRL]) {
2324 keys[MESA_SHADER_VERTEX].vs_common_out.as_ls = true;
2325 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
2326 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
2327 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
2328
2329 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
2330 }
2331
2332 if (nir[MESA_SHADER_GEOMETRY]) {
2333 if (nir[MESA_SHADER_TESS_CTRL])
2334 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_es = true;
2335 else
2336 keys[MESA_SHADER_VERTEX].vs_common_out.as_es = true;
2337 }
2338
2339 if (device->physical_device->use_ngg) {
2340 if (nir[MESA_SHADER_TESS_CTRL]) {
2341 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = true;
2342 } else {
2343 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = true;
2344 }
2345
2346 if (nir[MESA_SHADER_TESS_CTRL] &&
2347 nir[MESA_SHADER_GEOMETRY] &&
2348 nir[MESA_SHADER_GEOMETRY]->info.gs.invocations *
2349 nir[MESA_SHADER_GEOMETRY]->info.gs.vertices_out > 256) {
2350 /* Fallback to the legacy path if tessellation is
2351 * enabled with extreme geometry because
2352 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2353 * might hang.
2354 */
2355 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2356 }
2357
2358 if (!device->physical_device->use_ngg_gs) {
2359 if (nir[MESA_SHADER_GEOMETRY]) {
2360 if (nir[MESA_SHADER_TESS_CTRL])
2361 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2362 else
2363 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2364 }
2365 }
2366
2367 gl_shader_stage last_xfb_stage = MESA_SHADER_VERTEX;
2368
2369 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
2370 if (nir[i])
2371 last_xfb_stage = i;
2372 }
2373
2374 bool uses_xfb = nir[last_xfb_stage] &&
2375 radv_nir_stage_uses_xfb(nir[last_xfb_stage]);
2376
2377 if (!device->physical_device->use_ngg_streamout && uses_xfb) {
2378 if (nir[MESA_SHADER_TESS_CTRL])
2379 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2380 else
2381 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2382 }
2383
2384 /* Determine if the pipeline is eligible for the NGG passthrough
2385 * mode. It can't be enabled for geometry shaders, for NGG
2386 * streamout or for vertex shaders that export the primitive ID
2387 * (this is checked later because we don't have the info here.)
2388 */
2389 if (!nir[MESA_SHADER_GEOMETRY] && !uses_xfb) {
2390 if (nir[MESA_SHADER_TESS_CTRL] &&
2391 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg) {
2392 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg_passthrough = true;
2393 } else if (nir[MESA_SHADER_VERTEX] &&
2394 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) {
2395 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = true;
2396 }
2397 }
2398 }
2399
2400 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
2401 keys[i].has_multiview_view_index = key->has_multiview_view_index;
2402
2403 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
2404 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
2405 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
2406 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
2407 keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples;
2408 keys[MESA_SHADER_FRAGMENT].fs.is_dual_src = key->is_dual_src;
2409
2410 if (nir[MESA_SHADER_COMPUTE]) {
2411 keys[MESA_SHADER_COMPUTE].cs.subgroup_size = key->compute_subgroup_size;
2412 }
2413 }
2414
2415 static uint8_t
2416 radv_get_wave_size(struct radv_device *device,
2417 const VkPipelineShaderStageCreateInfo *pStage,
2418 gl_shader_stage stage,
2419 const struct radv_shader_variant_key *key)
2420 {
2421 if (stage == MESA_SHADER_GEOMETRY && !key->vs_common_out.as_ngg)
2422 return 64;
2423 else if (stage == MESA_SHADER_COMPUTE) {
2424 if (key->cs.subgroup_size) {
2425 /* Return the required subgroup size if specified. */
2426 return key->cs.subgroup_size;
2427 }
2428 return device->physical_device->cs_wave_size;
2429 }
2430 else if (stage == MESA_SHADER_FRAGMENT)
2431 return device->physical_device->ps_wave_size;
2432 else
2433 return device->physical_device->ge_wave_size;
2434 }
2435
2436 static uint8_t
2437 radv_get_ballot_bit_size(struct radv_device *device,
2438 const VkPipelineShaderStageCreateInfo *pStage,
2439 gl_shader_stage stage,
2440 const struct radv_shader_variant_key *key)
2441 {
2442 if (stage == MESA_SHADER_COMPUTE && key->cs.subgroup_size)
2443 return key->cs.subgroup_size;
2444 return 64;
2445 }
2446
2447 static void
2448 radv_fill_shader_info(struct radv_pipeline *pipeline,
2449 const VkPipelineShaderStageCreateInfo **pStages,
2450 struct radv_shader_variant_key *keys,
2451 struct radv_shader_info *infos,
2452 nir_shader **nir)
2453 {
2454 unsigned active_stages = 0;
2455 unsigned filled_stages = 0;
2456
2457 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2458 if (nir[i])
2459 active_stages |= (1 << i);
2460 }
2461
2462 if (nir[MESA_SHADER_FRAGMENT]) {
2463 radv_nir_shader_info_init(&infos[MESA_SHADER_FRAGMENT]);
2464 radv_nir_shader_info_pass(nir[MESA_SHADER_FRAGMENT],
2465 pipeline->layout,
2466 &keys[MESA_SHADER_FRAGMENT],
2467 &infos[MESA_SHADER_FRAGMENT],
2468 pipeline->device->physical_device->use_llvm);
2469
2470 /* TODO: These are no longer used as keys we should refactor this */
2471 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2472 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2473 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2474 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2475 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2476 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2477 keys[MESA_SHADER_VERTEX].vs_common_out.export_viewport_index =
2478 infos[MESA_SHADER_FRAGMENT].ps.viewport_index_input;
2479 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2480 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2481 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2482 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2483 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2484 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2485 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_viewport_index =
2486 infos[MESA_SHADER_FRAGMENT].ps.viewport_index_input;
2487
2488 /* NGG passthrough mode can't be enabled for vertex shaders
2489 * that export the primitive ID.
2490 *
2491 * TODO: I should really refactor the keys logic.
2492 */
2493 if (nir[MESA_SHADER_VERTEX] &&
2494 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id) {
2495 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = false;
2496 }
2497
2498 filled_stages |= (1 << MESA_SHADER_FRAGMENT);
2499 }
2500
2501 if (nir[MESA_SHADER_TESS_CTRL]) {
2502 infos[MESA_SHADER_TESS_CTRL].tcs.tes_inputs_read =
2503 nir[MESA_SHADER_TESS_EVAL]->info.inputs_read;
2504 infos[MESA_SHADER_TESS_CTRL].tcs.tes_patch_inputs_read =
2505 nir[MESA_SHADER_TESS_EVAL]->info.patch_inputs_read;
2506 }
2507
2508 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2509 nir[MESA_SHADER_TESS_CTRL]) {
2510 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2511 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2512 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2513
2514 radv_nir_shader_info_init(&infos[MESA_SHADER_TESS_CTRL]);
2515
2516 for (int i = 0; i < 2; i++) {
2517 radv_nir_shader_info_pass(combined_nir[i],
2518 pipeline->layout, &key,
2519 &infos[MESA_SHADER_TESS_CTRL],
2520 pipeline->device->physical_device->use_llvm);
2521 }
2522
2523 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2524 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2525 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2526 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2527
2528 filled_stages |= (1 << MESA_SHADER_VERTEX);
2529 filled_stages |= (1 << MESA_SHADER_TESS_CTRL);
2530 }
2531
2532 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2533 nir[MESA_SHADER_GEOMETRY]) {
2534 gl_shader_stage pre_stage = nir[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2535 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2536
2537 radv_nir_shader_info_init(&infos[MESA_SHADER_GEOMETRY]);
2538
2539 for (int i = 0; i < 2; i++) {
2540 radv_nir_shader_info_pass(combined_nir[i],
2541 pipeline->layout,
2542 &keys[pre_stage],
2543 &infos[MESA_SHADER_GEOMETRY],
2544 pipeline->device->physical_device->use_llvm);
2545 }
2546
2547 filled_stages |= (1 << pre_stage);
2548 filled_stages |= (1 << MESA_SHADER_GEOMETRY);
2549 }
2550
2551 active_stages ^= filled_stages;
2552 while (active_stages) {
2553 int i = u_bit_scan(&active_stages);
2554
2555 if (i == MESA_SHADER_TESS_CTRL) {
2556 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs =
2557 util_last_bit64(infos[MESA_SHADER_VERTEX].vs.ls_outputs_written);
2558 }
2559
2560 if (i == MESA_SHADER_TESS_EVAL) {
2561 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2562 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2563 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2564 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2565 }
2566
2567 radv_nir_shader_info_init(&infos[i]);
2568 radv_nir_shader_info_pass(nir[i], pipeline->layout,
2569 &keys[i], &infos[i], pipeline->device->physical_device->use_llvm);
2570 }
2571
2572 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2573 if (nir[i]) {
2574 infos[i].wave_size =
2575 radv_get_wave_size(pipeline->device, pStages[i],
2576 i, &keys[i]);
2577 infos[i].ballot_bit_size =
2578 radv_get_ballot_bit_size(pipeline->device,
2579 pStages[i], i,
2580 &keys[i]);
2581 }
2582 }
2583 }
2584
2585 static void
2586 merge_tess_info(struct shader_info *tes_info,
2587 const struct shader_info *tcs_info)
2588 {
2589 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2590 *
2591 * "PointMode. Controls generation of points rather than triangles
2592 * or lines. This functionality defaults to disabled, and is
2593 * enabled if either shader stage includes the execution mode.
2594 *
2595 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2596 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2597 * and OutputVertices, it says:
2598 *
2599 * "One mode must be set in at least one of the tessellation
2600 * shader stages."
2601 *
2602 * So, the fields can be set in either the TCS or TES, but they must
2603 * agree if set in both. Our backend looks at TES, so bitwise-or in
2604 * the values from the TCS.
2605 */
2606 assert(tcs_info->tess.tcs_vertices_out == 0 ||
2607 tes_info->tess.tcs_vertices_out == 0 ||
2608 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
2609 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
2610
2611 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2612 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2613 tcs_info->tess.spacing == tes_info->tess.spacing);
2614 tes_info->tess.spacing |= tcs_info->tess.spacing;
2615
2616 assert(tcs_info->tess.primitive_mode == 0 ||
2617 tes_info->tess.primitive_mode == 0 ||
2618 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
2619 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
2620 tes_info->tess.ccw |= tcs_info->tess.ccw;
2621 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
2622 }
2623
2624 static
2625 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT *ext)
2626 {
2627 if (!ext)
2628 return;
2629
2630 if (ext->pPipelineCreationFeedback) {
2631 ext->pPipelineCreationFeedback->flags = 0;
2632 ext->pPipelineCreationFeedback->duration = 0;
2633 }
2634
2635 for (unsigned i = 0; i < ext->pipelineStageCreationFeedbackCount; ++i) {
2636 ext->pPipelineStageCreationFeedbacks[i].flags = 0;
2637 ext->pPipelineStageCreationFeedbacks[i].duration = 0;
2638 }
2639 }
2640
2641 static
2642 void radv_start_feedback(VkPipelineCreationFeedbackEXT *feedback)
2643 {
2644 if (!feedback)
2645 return;
2646
2647 feedback->duration -= radv_get_current_time();
2648 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT;
2649 }
2650
2651 static
2652 void radv_stop_feedback(VkPipelineCreationFeedbackEXT *feedback, bool cache_hit)
2653 {
2654 if (!feedback)
2655 return;
2656
2657 feedback->duration += radv_get_current_time();
2658 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT |
2659 (cache_hit ? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT : 0);
2660 }
2661
2662 VkResult radv_create_shaders(struct radv_pipeline *pipeline,
2663 struct radv_device *device,
2664 struct radv_pipeline_cache *cache,
2665 const struct radv_pipeline_key *key,
2666 const VkPipelineShaderStageCreateInfo **pStages,
2667 const VkPipelineCreateFlags flags,
2668 VkPipelineCreationFeedbackEXT *pipeline_feedback,
2669 VkPipelineCreationFeedbackEXT **stage_feedbacks)
2670 {
2671 struct radv_shader_module fs_m = {0};
2672 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2673 nir_shader *nir[MESA_SHADER_STAGES] = {0};
2674 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2675 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{{0}}}}};
2676 struct radv_shader_info infos[MESA_SHADER_STAGES] = {0};
2677 unsigned char hash[20], gs_copy_hash[20];
2678 bool keep_executable_info = (flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR) || device->keep_shader_info;
2679 bool keep_statistic_info = (flags & VK_PIPELINE_CREATE_CAPTURE_STATISTICS_BIT_KHR) ||
2680 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) ||
2681 device->keep_shader_info;
2682
2683 radv_start_feedback(pipeline_feedback);
2684
2685 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2686 if (pStages[i]) {
2687 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
2688 if (modules[i]->nir)
2689 _mesa_sha1_compute(modules[i]->nir->info.name,
2690 strlen(modules[i]->nir->info.name),
2691 modules[i]->sha1);
2692
2693 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
2694 }
2695 }
2696
2697 radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device));
2698 memcpy(gs_copy_hash, hash, 20);
2699 gs_copy_hash[0] ^= 1;
2700
2701 bool found_in_application_cache = true;
2702 if (modules[MESA_SHADER_GEOMETRY] && !keep_executable_info && !keep_statistic_info) {
2703 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2704 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants,
2705 &found_in_application_cache);
2706 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
2707 }
2708
2709 if (!keep_executable_info && !keep_statistic_info &&
2710 radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders,
2711 &found_in_application_cache) &&
2712 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
2713 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2714 return VK_SUCCESS;
2715 }
2716
2717 if (flags & VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_EXT) {
2718 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2719 return VK_PIPELINE_COMPILE_REQUIRED_EXT;
2720 }
2721
2722 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
2723 nir_builder fs_b;
2724 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2725 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2726 fs_m.nir = fs_b.shader;
2727 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2728 }
2729
2730 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2731 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
2732 unsigned subgroup_size = 64, ballot_bit_size = 64;
2733
2734 if (!modules[i])
2735 continue;
2736
2737 radv_start_feedback(stage_feedbacks[i]);
2738
2739 if (key->compute_subgroup_size) {
2740 /* Only compute shaders currently support requiring a
2741 * specific subgroup size.
2742 */
2743 assert(i == MESA_SHADER_COMPUTE);
2744 subgroup_size = key->compute_subgroup_size;
2745 ballot_bit_size = key->compute_subgroup_size;
2746 }
2747
2748 nir[i] = radv_shader_compile_to_nir(device, modules[i],
2749 stage ? stage->pName : "main", i,
2750 stage ? stage->pSpecializationInfo : NULL,
2751 flags, pipeline->layout,
2752 subgroup_size, ballot_bit_size);
2753
2754 /* We don't want to alter meta shaders IR directly so clone it
2755 * first.
2756 */
2757 if (nir[i]->info.name) {
2758 nir[i] = nir_shader_clone(NULL, nir[i]);
2759 }
2760
2761 radv_stop_feedback(stage_feedbacks[i], false);
2762 }
2763
2764 if (nir[MESA_SHADER_TESS_CTRL]) {
2765 nir_lower_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
2766 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
2767 }
2768
2769 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
2770 radv_link_shaders(pipeline, nir);
2771
2772 radv_set_linked_driver_locations(pipeline, nir, infos);
2773
2774 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2775 if (nir[i]) {
2776 /* do this again since information such as outputs_read can be out-of-date */
2777 nir_shader_gather_info(nir[i], nir_shader_get_entrypoint(nir[i]));
2778
2779 if (device->physical_device->use_llvm) {
2780 NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
2781 } else {
2782 NIR_PASS_V(nir[i], nir_lower_non_uniform_access,
2783 nir_lower_non_uniform_ubo_access |
2784 nir_lower_non_uniform_ssbo_access |
2785 nir_lower_non_uniform_texture_access |
2786 nir_lower_non_uniform_image_access);
2787 }
2788 }
2789 }
2790
2791 if (nir[MESA_SHADER_FRAGMENT])
2792 radv_lower_fs_io(nir[MESA_SHADER_FRAGMENT]);
2793
2794 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2795 if (radv_can_dump_shader(device, modules[i], false))
2796 nir_print_shader(nir[i], stderr);
2797 }
2798
2799 radv_fill_shader_keys(device, keys, key, nir);
2800
2801 radv_fill_shader_info(pipeline, pStages, keys, infos, nir);
2802
2803 if ((nir[MESA_SHADER_VERTEX] &&
2804 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) ||
2805 (nir[MESA_SHADER_TESS_EVAL] &&
2806 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg)) {
2807 struct gfx10_ngg_info *ngg_info;
2808
2809 if (nir[MESA_SHADER_GEOMETRY])
2810 ngg_info = &infos[MESA_SHADER_GEOMETRY].ngg_info;
2811 else if (nir[MESA_SHADER_TESS_CTRL])
2812 ngg_info = &infos[MESA_SHADER_TESS_EVAL].ngg_info;
2813 else
2814 ngg_info = &infos[MESA_SHADER_VERTEX].ngg_info;
2815
2816 gfx10_get_ngg_info(key, pipeline, nir, infos, ngg_info);
2817 } else if (nir[MESA_SHADER_GEOMETRY]) {
2818 struct gfx9_gs_info *gs_info =
2819 &infos[MESA_SHADER_GEOMETRY].gs_ring_info;
2820
2821 gfx9_get_gs_info(key, pipeline, nir, infos, gs_info);
2822 }
2823
2824 if(modules[MESA_SHADER_GEOMETRY]) {
2825 struct radv_shader_binary *gs_copy_binary = NULL;
2826 if (!pipeline->gs_copy_shader &&
2827 !radv_pipeline_has_ngg(pipeline)) {
2828 struct radv_shader_info info = {};
2829 struct radv_shader_variant_key key = {};
2830
2831 key.has_multiview_view_index =
2832 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index;
2833
2834 radv_nir_shader_info_pass(nir[MESA_SHADER_GEOMETRY],
2835 pipeline->layout, &key,
2836 &info, pipeline->device->physical_device->use_llvm);
2837 info.wave_size = 64; /* Wave32 not supported. */
2838 info.ballot_bit_size = 64;
2839
2840 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2841 device, nir[MESA_SHADER_GEOMETRY], &info,
2842 &gs_copy_binary, keep_executable_info, keep_statistic_info,
2843 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2844 }
2845
2846 if (!keep_executable_info && !keep_statistic_info && pipeline->gs_copy_shader) {
2847 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2848 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2849
2850 binaries[MESA_SHADER_GEOMETRY] = gs_copy_binary;
2851 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2852
2853 radv_pipeline_cache_insert_shaders(device, cache,
2854 gs_copy_hash,
2855 variants,
2856 binaries);
2857 }
2858 free(gs_copy_binary);
2859 }
2860
2861 if (nir[MESA_SHADER_FRAGMENT]) {
2862 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
2863 radv_start_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT]);
2864
2865 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2866 radv_shader_variant_compile(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
2867 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
2868 infos + MESA_SHADER_FRAGMENT,
2869 keep_executable_info, keep_statistic_info,
2870 &binaries[MESA_SHADER_FRAGMENT]);
2871
2872 radv_stop_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT], false);
2873 }
2874 }
2875
2876 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
2877 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
2878 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2879 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2880 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2881
2882 radv_start_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL]);
2883
2884 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
2885 pipeline->layout,
2886 &key, &infos[MESA_SHADER_TESS_CTRL], keep_executable_info,
2887 keep_statistic_info, &binaries[MESA_SHADER_TESS_CTRL]);
2888
2889 radv_stop_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL], false);
2890 }
2891 modules[MESA_SHADER_VERTEX] = NULL;
2892 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2893 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2894 }
2895
2896 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
2897 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2898 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
2899 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2900
2901 radv_start_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY]);
2902
2903 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2904 pipeline->layout,
2905 &keys[pre_stage], &infos[MESA_SHADER_GEOMETRY], keep_executable_info,
2906 keep_statistic_info, &binaries[MESA_SHADER_GEOMETRY]);
2907
2908 radv_stop_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY], false);
2909 }
2910 modules[pre_stage] = NULL;
2911 }
2912
2913 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2914 if(modules[i] && !pipeline->shaders[i]) {
2915 if (i == MESA_SHADER_TESS_CTRL) {
2916 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.ls_outputs_written);
2917 }
2918 if (i == MESA_SHADER_TESS_EVAL) {
2919 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2920 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2921 }
2922
2923 radv_start_feedback(stage_feedbacks[i]);
2924
2925 pipeline->shaders[i] = radv_shader_variant_compile(device, modules[i], &nir[i], 1,
2926 pipeline->layout,
2927 keys + i, infos + i, keep_executable_info,
2928 keep_statistic_info, &binaries[i]);
2929
2930 radv_stop_feedback(stage_feedbacks[i], false);
2931 }
2932 }
2933
2934 if (!keep_executable_info && !keep_statistic_info) {
2935 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
2936 binaries);
2937 }
2938
2939 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2940 free(binaries[i]);
2941 if (nir[i]) {
2942 ralloc_free(nir[i]);
2943
2944 if (radv_can_dump_shader_stats(device, modules[i]))
2945 radv_shader_dump_stats(device,
2946 pipeline->shaders[i],
2947 i, stderr);
2948 }
2949 }
2950
2951 if (fs_m.nir)
2952 ralloc_free(fs_m.nir);
2953
2954 radv_stop_feedback(pipeline_feedback, false);
2955 return VK_SUCCESS;
2956 }
2957
2958 static uint32_t
2959 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
2960 gl_shader_stage stage, enum chip_class chip_class)
2961 {
2962 bool has_gs = radv_pipeline_has_gs(pipeline);
2963 bool has_tess = radv_pipeline_has_tess(pipeline);
2964 bool has_ngg = radv_pipeline_has_ngg(pipeline);
2965
2966 switch (stage) {
2967 case MESA_SHADER_FRAGMENT:
2968 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
2969 case MESA_SHADER_VERTEX:
2970 if (has_tess) {
2971 if (chip_class >= GFX10) {
2972 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
2973 } else if (chip_class == GFX9) {
2974 return R_00B430_SPI_SHADER_USER_DATA_LS_0;
2975 } else {
2976 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
2977 }
2978
2979 }
2980
2981 if (has_gs) {
2982 if (chip_class >= GFX10) {
2983 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2984 } else {
2985 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
2986 }
2987 }
2988
2989 if (has_ngg)
2990 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
2991
2992 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
2993 case MESA_SHADER_GEOMETRY:
2994 return chip_class == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
2995 R_00B230_SPI_SHADER_USER_DATA_GS_0;
2996 case MESA_SHADER_COMPUTE:
2997 return R_00B900_COMPUTE_USER_DATA_0;
2998 case MESA_SHADER_TESS_CTRL:
2999 return chip_class == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
3000 R_00B430_SPI_SHADER_USER_DATA_HS_0;
3001 case MESA_SHADER_TESS_EVAL:
3002 if (has_gs) {
3003 return chip_class >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0 :
3004 R_00B330_SPI_SHADER_USER_DATA_ES_0;
3005 } else if (has_ngg) {
3006 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3007 } else {
3008 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
3009 }
3010 default:
3011 unreachable("unknown shader");
3012 }
3013 }
3014
3015 struct radv_bin_size_entry {
3016 unsigned bpp;
3017 VkExtent2D extent;
3018 };
3019
3020 static VkExtent2D
3021 radv_gfx9_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3022 {
3023 static const struct radv_bin_size_entry color_size_table[][3][9] = {
3024 {
3025 /* One RB / SE */
3026 {
3027 /* One shader engine */
3028 { 0, {128, 128}},
3029 { 1, { 64, 128}},
3030 { 2, { 32, 128}},
3031 { 3, { 16, 128}},
3032 { 17, { 0, 0}},
3033 { UINT_MAX, { 0, 0}},
3034 },
3035 {
3036 /* Two shader engines */
3037 { 0, {128, 128}},
3038 { 2, { 64, 128}},
3039 { 3, { 32, 128}},
3040 { 5, { 16, 128}},
3041 { 17, { 0, 0}},
3042 { UINT_MAX, { 0, 0}},
3043 },
3044 {
3045 /* Four shader engines */
3046 { 0, {128, 128}},
3047 { 3, { 64, 128}},
3048 { 5, { 16, 128}},
3049 { 17, { 0, 0}},
3050 { UINT_MAX, { 0, 0}},
3051 },
3052 },
3053 {
3054 /* Two RB / SE */
3055 {
3056 /* One shader engine */
3057 { 0, {128, 128}},
3058 { 2, { 64, 128}},
3059 { 3, { 32, 128}},
3060 { 5, { 16, 128}},
3061 { 33, { 0, 0}},
3062 { UINT_MAX, { 0, 0}},
3063 },
3064 {
3065 /* Two shader engines */
3066 { 0, {128, 128}},
3067 { 3, { 64, 128}},
3068 { 5, { 32, 128}},
3069 { 9, { 16, 128}},
3070 { 33, { 0, 0}},
3071 { UINT_MAX, { 0, 0}},
3072 },
3073 {
3074 /* Four shader engines */
3075 { 0, {256, 256}},
3076 { 2, {128, 256}},
3077 { 3, {128, 128}},
3078 { 5, { 64, 128}},
3079 { 9, { 16, 128}},
3080 { 33, { 0, 0}},
3081 { UINT_MAX, { 0, 0}},
3082 },
3083 },
3084 {
3085 /* Four RB / SE */
3086 {
3087 /* One shader engine */
3088 { 0, {128, 256}},
3089 { 2, {128, 128}},
3090 { 3, { 64, 128}},
3091 { 5, { 32, 128}},
3092 { 9, { 16, 128}},
3093 { 33, { 0, 0}},
3094 { UINT_MAX, { 0, 0}},
3095 },
3096 {
3097 /* Two shader engines */
3098 { 0, {256, 256}},
3099 { 2, {128, 256}},
3100 { 3, {128, 128}},
3101 { 5, { 64, 128}},
3102 { 9, { 32, 128}},
3103 { 17, { 16, 128}},
3104 { 33, { 0, 0}},
3105 { UINT_MAX, { 0, 0}},
3106 },
3107 {
3108 /* Four shader engines */
3109 { 0, {256, 512}},
3110 { 2, {256, 256}},
3111 { 3, {128, 256}},
3112 { 5, {128, 128}},
3113 { 9, { 64, 128}},
3114 { 17, { 16, 128}},
3115 { 33, { 0, 0}},
3116 { UINT_MAX, { 0, 0}},
3117 },
3118 },
3119 };
3120 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
3121 {
3122 // One RB / SE
3123 {
3124 // One shader engine
3125 { 0, {128, 256}},
3126 { 2, {128, 128}},
3127 { 4, { 64, 128}},
3128 { 7, { 32, 128}},
3129 { 13, { 16, 128}},
3130 { 49, { 0, 0}},
3131 { UINT_MAX, { 0, 0}},
3132 },
3133 {
3134 // Two shader engines
3135 { 0, {256, 256}},
3136 { 2, {128, 256}},
3137 { 4, {128, 128}},
3138 { 7, { 64, 128}},
3139 { 13, { 32, 128}},
3140 { 25, { 16, 128}},
3141 { 49, { 0, 0}},
3142 { UINT_MAX, { 0, 0}},
3143 },
3144 {
3145 // Four shader engines
3146 { 0, {256, 512}},
3147 { 2, {256, 256}},
3148 { 4, {128, 256}},
3149 { 7, {128, 128}},
3150 { 13, { 64, 128}},
3151 { 25, { 16, 128}},
3152 { 49, { 0, 0}},
3153 { UINT_MAX, { 0, 0}},
3154 },
3155 },
3156 {
3157 // Two RB / SE
3158 {
3159 // One shader engine
3160 { 0, {256, 256}},
3161 { 2, {128, 256}},
3162 { 4, {128, 128}},
3163 { 7, { 64, 128}},
3164 { 13, { 32, 128}},
3165 { 25, { 16, 128}},
3166 { 97, { 0, 0}},
3167 { UINT_MAX, { 0, 0}},
3168 },
3169 {
3170 // Two shader engines
3171 { 0, {256, 512}},
3172 { 2, {256, 256}},
3173 { 4, {128, 256}},
3174 { 7, {128, 128}},
3175 { 13, { 64, 128}},
3176 { 25, { 32, 128}},
3177 { 49, { 16, 128}},
3178 { 97, { 0, 0}},
3179 { UINT_MAX, { 0, 0}},
3180 },
3181 {
3182 // Four shader engines
3183 { 0, {512, 512}},
3184 { 2, {256, 512}},
3185 { 4, {256, 256}},
3186 { 7, {128, 256}},
3187 { 13, {128, 128}},
3188 { 25, { 64, 128}},
3189 { 49, { 16, 128}},
3190 { 97, { 0, 0}},
3191 { UINT_MAX, { 0, 0}},
3192 },
3193 },
3194 {
3195 // Four RB / SE
3196 {
3197 // One shader engine
3198 { 0, {256, 512}},
3199 { 2, {256, 256}},
3200 { 4, {128, 256}},
3201 { 7, {128, 128}},
3202 { 13, { 64, 128}},
3203 { 25, { 32, 128}},
3204 { 49, { 16, 128}},
3205 { UINT_MAX, { 0, 0}},
3206 },
3207 {
3208 // Two shader engines
3209 { 0, {512, 512}},
3210 { 2, {256, 512}},
3211 { 4, {256, 256}},
3212 { 7, {128, 256}},
3213 { 13, {128, 128}},
3214 { 25, { 64, 128}},
3215 { 49, { 32, 128}},
3216 { 97, { 16, 128}},
3217 { UINT_MAX, { 0, 0}},
3218 },
3219 {
3220 // Four shader engines
3221 { 0, {512, 512}},
3222 { 4, {256, 512}},
3223 { 7, {256, 256}},
3224 { 13, {128, 256}},
3225 { 25, {128, 128}},
3226 { 49, { 64, 128}},
3227 { 97, { 16, 128}},
3228 { UINT_MAX, { 0, 0}},
3229 },
3230 },
3231 };
3232
3233 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3234 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3235 VkExtent2D extent = {512, 512};
3236
3237 unsigned log_num_rb_per_se =
3238 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
3239 pipeline->device->physical_device->rad_info.max_se);
3240 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
3241
3242 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3243 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
3244 unsigned effective_samples = total_samples;
3245 unsigned color_bytes_per_pixel = 0;
3246
3247 const VkPipelineColorBlendStateCreateInfo *vkblend =
3248 radv_pipeline_get_color_blend_state(pCreateInfo);
3249 if (vkblend) {
3250 for (unsigned i = 0; i < subpass->color_count; i++) {
3251 if (!vkblend->pAttachments[i].colorWriteMask)
3252 continue;
3253
3254 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3255 continue;
3256
3257 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3258 color_bytes_per_pixel += vk_format_get_blocksize(format);
3259 }
3260
3261 /* MSAA images typically don't use all samples all the time. */
3262 if (effective_samples >= 2 && ps_iter_samples <= 1)
3263 effective_samples = 2;
3264 color_bytes_per_pixel *= effective_samples;
3265 }
3266
3267 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
3268 while(color_entry[1].bpp <= color_bytes_per_pixel)
3269 ++color_entry;
3270
3271 extent = color_entry->extent;
3272
3273 if (subpass->depth_stencil_attachment) {
3274 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3275
3276 /* Coefficients taken from AMDVLK */
3277 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3278 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3279 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
3280
3281 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
3282 while(ds_entry[1].bpp <= ds_bytes_per_pixel)
3283 ++ds_entry;
3284
3285 if (ds_entry->extent.width * ds_entry->extent.height < extent.width * extent.height)
3286 extent = ds_entry->extent;
3287 }
3288
3289 return extent;
3290 }
3291
3292 static VkExtent2D
3293 radv_gfx10_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3294 {
3295 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3296 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3297 VkExtent2D extent = {512, 512};
3298
3299 const unsigned db_tag_size = 64;
3300 const unsigned db_tag_count = 312;
3301 const unsigned color_tag_size = 1024;
3302 const unsigned color_tag_count = 31;
3303 const unsigned fmask_tag_size = 256;
3304 const unsigned fmask_tag_count = 44;
3305
3306 const unsigned rb_count = pipeline->device->physical_device->rad_info.num_render_backends;
3307 const unsigned pipe_count = MAX2(rb_count, pipeline->device->physical_device->rad_info.num_sdp_interfaces);
3308
3309 const unsigned db_tag_part = (db_tag_count * rb_count / pipe_count) * db_tag_size * pipe_count;
3310 const unsigned color_tag_part = (color_tag_count * rb_count / pipe_count) * color_tag_size * pipe_count;
3311 const unsigned fmask_tag_part = (fmask_tag_count * rb_count / pipe_count) * fmask_tag_size * pipe_count;
3312
3313 const unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3314 const unsigned samples_log = util_logbase2_ceil(total_samples);
3315
3316 unsigned color_bytes_per_pixel = 0;
3317 unsigned fmask_bytes_per_pixel = 0;
3318
3319 const VkPipelineColorBlendStateCreateInfo *vkblend =
3320 radv_pipeline_get_color_blend_state(pCreateInfo);
3321 if (vkblend) {
3322 for (unsigned i = 0; i < subpass->color_count; i++) {
3323 if (!vkblend->pAttachments[i].colorWriteMask)
3324 continue;
3325
3326 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3327 continue;
3328
3329 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3330 color_bytes_per_pixel += vk_format_get_blocksize(format);
3331
3332 if (total_samples > 1) {
3333 assert(samples_log <= 3);
3334 const unsigned fmask_array[] = {0, 1, 1, 4};
3335 fmask_bytes_per_pixel += fmask_array[samples_log];
3336 }
3337 }
3338
3339 color_bytes_per_pixel *= total_samples;
3340 }
3341 color_bytes_per_pixel = MAX2(color_bytes_per_pixel, 1);
3342
3343 const unsigned color_pixel_count_log = util_logbase2(color_tag_part / color_bytes_per_pixel);
3344 extent.width = 1ull << ((color_pixel_count_log + 1) / 2);
3345 extent.height = 1ull << (color_pixel_count_log / 2);
3346
3347 if (fmask_bytes_per_pixel) {
3348 const unsigned fmask_pixel_count_log = util_logbase2(fmask_tag_part / fmask_bytes_per_pixel);
3349
3350 const VkExtent2D fmask_extent = (VkExtent2D){
3351 .width = 1ull << ((fmask_pixel_count_log + 1) / 2),
3352 .height = 1ull << (color_pixel_count_log / 2)
3353 };
3354
3355 if (fmask_extent.width * fmask_extent.height < extent.width * extent.height)
3356 extent = fmask_extent;
3357 }
3358
3359 if (subpass->depth_stencil_attachment) {
3360 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3361
3362 /* Coefficients taken from AMDVLK */
3363 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3364 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3365 unsigned db_bytes_per_pixel = (depth_coeff + stencil_coeff) * total_samples;
3366
3367 const unsigned db_pixel_count_log = util_logbase2(db_tag_part / db_bytes_per_pixel);
3368
3369 const VkExtent2D db_extent = (VkExtent2D){
3370 .width = 1ull << ((db_pixel_count_log + 1) / 2),
3371 .height = 1ull << (color_pixel_count_log / 2)
3372 };
3373
3374 if (db_extent.width * db_extent.height < extent.width * extent.height)
3375 extent = db_extent;
3376 }
3377
3378 extent.width = MAX2(extent.width, 128);
3379 extent.height = MAX2(extent.width, 64);
3380
3381 return extent;
3382 }
3383
3384 static void
3385 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf *ctx_cs,
3386 struct radv_pipeline *pipeline,
3387 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3388 {
3389 uint32_t pa_sc_binner_cntl_0 =
3390 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
3391 S_028C44_DISABLE_START_OF_PRIM(1);
3392 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3393
3394 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3395 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3396 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3397 const VkPipelineColorBlendStateCreateInfo *vkblend =
3398 radv_pipeline_get_color_blend_state(pCreateInfo);
3399 unsigned min_bytes_per_pixel = 0;
3400
3401 if (vkblend) {
3402 for (unsigned i = 0; i < subpass->color_count; i++) {
3403 if (!vkblend->pAttachments[i].colorWriteMask)
3404 continue;
3405
3406 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3407 continue;
3408
3409 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3410 unsigned bytes = vk_format_get_blocksize(format);
3411 if (!min_bytes_per_pixel || bytes < min_bytes_per_pixel)
3412 min_bytes_per_pixel = bytes;
3413 }
3414 }
3415
3416 pa_sc_binner_cntl_0 =
3417 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) |
3418 S_028C44_BIN_SIZE_X(0) |
3419 S_028C44_BIN_SIZE_Y(0) |
3420 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3421 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel <= 4 ? 2 : 1) | /* 128 or 64 */
3422 S_028C44_DISABLE_START_OF_PRIM(1);
3423 }
3424
3425 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3426 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3427 }
3428
3429 struct radv_binning_settings
3430 radv_get_binning_settings(const struct radv_physical_device *pdev)
3431 {
3432 struct radv_binning_settings settings;
3433 if (pdev->rad_info.has_dedicated_vram) {
3434 if (pdev->rad_info.num_render_backends > 4) {
3435 settings.context_states_per_bin = 1;
3436 settings.persistent_states_per_bin = 1;
3437 } else {
3438 settings.context_states_per_bin = 3;
3439 settings.persistent_states_per_bin = 8;
3440 }
3441 settings.fpovs_per_batch = 63;
3442 } else {
3443 /* The context states are affected by the scissor bug. */
3444 settings.context_states_per_bin = 6;
3445 /* 32 causes hangs for RAVEN. */
3446 settings.persistent_states_per_bin = 16;
3447 settings.fpovs_per_batch = 63;
3448 }
3449
3450 if (pdev->rad_info.has_gfx9_scissor_bug)
3451 settings.context_states_per_bin = 1;
3452
3453 return settings;
3454 }
3455
3456 static void
3457 radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs,
3458 struct radv_pipeline *pipeline,
3459 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3460 const struct radv_blend_state *blend)
3461 {
3462 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
3463 return;
3464
3465 VkExtent2D bin_size;
3466 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3467 bin_size = radv_gfx10_compute_bin_size(pipeline, pCreateInfo);
3468 } else if (pipeline->device->physical_device->rad_info.chip_class == GFX9) {
3469 bin_size = radv_gfx9_compute_bin_size(pipeline, pCreateInfo);
3470 } else
3471 unreachable("Unhandled generation for binning bin size calculation");
3472
3473 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
3474 struct radv_binning_settings settings =
3475 radv_get_binning_settings(pipeline->device->physical_device);
3476
3477 bool disable_start_of_prim = true;
3478 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3479
3480 const struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3481
3482 if (pipeline->device->dfsm_allowed && ps &&
3483 !ps->info.ps.can_discard &&
3484 !ps->info.ps.writes_memory &&
3485 blend->cb_target_enabled_4bit) {
3486 db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_AUTO);
3487 disable_start_of_prim = (blend->blend_enable_4bit & blend->cb_target_enabled_4bit) != 0;
3488 }
3489
3490 const uint32_t pa_sc_binner_cntl_0 =
3491 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
3492 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
3493 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
3494 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
3495 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
3496 S_028C44_CONTEXT_STATES_PER_BIN(settings.context_states_per_bin - 1) |
3497 S_028C44_PERSISTENT_STATES_PER_BIN(settings.persistent_states_per_bin - 1) |
3498 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim) |
3499 S_028C44_FPOVS_PER_BATCH(settings.fpovs_per_batch) |
3500 S_028C44_OPTIMAL_BIN_SELECTION(1);
3501
3502 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3503 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3504 } else
3505 radv_pipeline_generate_disabled_binning_state(ctx_cs, pipeline, pCreateInfo);
3506 }
3507
3508
3509 static void
3510 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs,
3511 struct radv_pipeline *pipeline,
3512 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3513 const struct radv_graphics_pipeline_create_info *extra)
3514 {
3515 const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
3516 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3517 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3518 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3519 struct radv_render_pass_attachment *attachment = NULL;
3520 uint32_t db_depth_control = 0;
3521 uint32_t db_render_control = 0, db_render_override2 = 0;
3522 uint32_t db_render_override = 0;
3523
3524 if (subpass->depth_stencil_attachment)
3525 attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3526
3527 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
3528 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
3529
3530 if (vkds && has_depth_attachment) {
3531 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
3532 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
3533 S_028800_ZFUNC(vkds->depthCompareOp) |
3534 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
3535
3536 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3537 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
3538
3539 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10_3)
3540 db_render_override2 |= S_028010_CENTROID_COMPUTATION_MODE_GFX103(2);
3541 }
3542
3543 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
3544 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3545 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
3546
3547 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
3548 }
3549
3550 if (attachment && extra) {
3551 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
3552 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
3553
3554 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->resummarize_enable);
3555 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->depth_compress_disable);
3556 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->stencil_compress_disable);
3557 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
3558 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
3559 }
3560
3561 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3562 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
3563
3564 if (!pCreateInfo->pRasterizationState->depthClampEnable &&
3565 ps->info.ps.writes_z) {
3566 /* From VK_EXT_depth_range_unrestricted spec:
3567 *
3568 * "The behavior described in Primitive Clipping still applies.
3569 * If depth clamping is disabled the depth values are still
3570 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3571 * depth clamping is enabled the above equation is ignored and
3572 * the depth values are instead clamped to the VkViewport
3573 * minDepth and maxDepth values, which in the case of this
3574 * extension can be outside of the 0.0 to 1.0 range."
3575 */
3576 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3577 }
3578
3579 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control);
3580 radeon_set_context_reg(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
3581 radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
3582
3583 pipeline->graphics.db_depth_control = db_depth_control;
3584 }
3585
3586 static void
3587 radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
3588 struct radv_pipeline *pipeline,
3589 const struct radv_blend_state *blend)
3590 {
3591 radeon_set_context_reg_seq(ctx_cs, R_028780_CB_BLEND0_CONTROL, 8);
3592 radeon_emit_array(ctx_cs, blend->cb_blend_control,
3593 8);
3594 radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
3595 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
3596
3597 if (pipeline->device->physical_device->rad_info.has_rbplus) {
3598
3599 radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
3600 radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
3601 }
3602
3603 radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
3604
3605 radeon_set_context_reg(ctx_cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
3606 radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
3607
3608 pipeline->graphics.col_format = blend->spi_shader_col_format;
3609 pipeline->graphics.cb_target_mask = blend->cb_target_mask;
3610 }
3611
3612 static const VkConservativeRasterizationModeEXT
3613 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo)
3614 {
3615 const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster =
3616 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT);
3617
3618 if (!conservative_raster)
3619 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT;
3620 return conservative_raster->conservativeRasterizationMode;
3621 }
3622
3623 static void
3624 radv_pipeline_generate_raster_state(struct radeon_cmdbuf *ctx_cs,
3625 struct radv_pipeline *pipeline,
3626 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3627 {
3628 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
3629 const VkConservativeRasterizationModeEXT mode =
3630 radv_get_conservative_raster_mode(vkraster);
3631 uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3632 bool depth_clip_disable = vkraster->depthClampEnable;
3633
3634 const VkPipelineRasterizationDepthClipStateCreateInfoEXT *depth_clip_state =
3635 vk_find_struct_const(vkraster->pNext, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT);
3636 if (depth_clip_state) {
3637 depth_clip_disable = !depth_clip_state->depthClipEnable;
3638 }
3639
3640 radeon_set_context_reg(ctx_cs, R_028810_PA_CL_CLIP_CNTL,
3641 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3642 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable ? 1 : 0) |
3643 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable ? 1 : 0) |
3644 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
3645 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3646
3647 pipeline->graphics.pa_su_sc_mode_cntl =
3648 S_028814_FACE(vkraster->frontFace) |
3649 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
3650 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
3651 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
3652 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3653 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3654 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3655 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3656 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
3657
3658 radeon_set_context_reg(ctx_cs, R_028BDC_PA_SC_LINE_CNTL,
3659 S_028BDC_DX10_DIAMOND_TEST_ENA(1));
3660
3661 /* Conservative rasterization. */
3662 if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
3663 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3664
3665 ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3666 ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3667 S_028804_OVERRASTERIZATION_AMOUNT(4);
3668
3669 pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3670 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3671 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3672
3673 if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) {
3674 pa_sc_conservative_rast |=
3675 S_028C4C_OVER_RAST_ENABLE(1) |
3676 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3677 S_028C4C_UNDER_RAST_ENABLE(0) |
3678 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3679 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3680 } else {
3681 assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT);
3682 pa_sc_conservative_rast |=
3683 S_028C4C_OVER_RAST_ENABLE(0) |
3684 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3685 S_028C4C_UNDER_RAST_ENABLE(1) |
3686 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3687 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3688 }
3689 }
3690
3691 radeon_set_context_reg(ctx_cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
3692 pa_sc_conservative_rast);
3693 }
3694
3695
3696 static void
3697 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
3698 struct radv_pipeline *pipeline)
3699 {
3700 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3701
3702 radeon_set_context_reg_seq(ctx_cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3703 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[0]);
3704 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]);
3705
3706 radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa);
3707 radeon_set_context_reg(ctx_cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
3708 radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
3709 radeon_set_context_reg(ctx_cs, R_028BE0_PA_SC_AA_CONFIG, ms->pa_sc_aa_config);
3710
3711 /* The exclusion bits can be set to improve rasterization efficiency
3712 * if no sample lies on the pixel boundary (-8 sample offset). It's
3713 * currently always TRUE because the driver doesn't support 16 samples.
3714 */
3715 bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= GFX7;
3716 radeon_set_context_reg(ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3717 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3718 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3719
3720 /* GFX9: Flush DFSM when the AA mode changes. */
3721 if (pipeline->device->dfsm_allowed) {
3722 radeon_emit(ctx_cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3723 radeon_emit(ctx_cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3724 }
3725 }
3726
3727 static void
3728 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
3729 struct radv_pipeline *pipeline)
3730 {
3731 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3732 const struct radv_shader_variant *vs =
3733 pipeline->shaders[MESA_SHADER_TESS_EVAL] ?
3734 pipeline->shaders[MESA_SHADER_TESS_EVAL] :
3735 pipeline->shaders[MESA_SHADER_VERTEX];
3736 unsigned vgt_primitiveid_en = 0;
3737 uint32_t vgt_gs_mode = 0;
3738
3739 if (radv_pipeline_has_ngg(pipeline))
3740 return;
3741
3742 if (radv_pipeline_has_gs(pipeline)) {
3743 const struct radv_shader_variant *gs =
3744 pipeline->shaders[MESA_SHADER_GEOMETRY];
3745
3746 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
3747 pipeline->device->physical_device->rad_info.chip_class);
3748 } else if (outinfo->export_prim_id || vs->info.uses_prim_id) {
3749 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
3750 vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(1);
3751 }
3752
3753 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
3754 radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
3755 }
3756
3757 static void
3758 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
3759 struct radeon_cmdbuf *cs,
3760 struct radv_pipeline *pipeline,
3761 struct radv_shader_variant *shader)
3762 {
3763 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3764
3765 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
3766 radeon_emit(cs, va >> 8);
3767 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
3768 radeon_emit(cs, shader->config.rsrc1);
3769 radeon_emit(cs, shader->config.rsrc2);
3770
3771 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3772 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3773 clip_dist_mask = outinfo->clip_dist_mask;
3774 cull_dist_mask = outinfo->cull_dist_mask;
3775 total_mask = clip_dist_mask | cull_dist_mask;
3776 bool misc_vec_ena = outinfo->writes_pointsize ||
3777 outinfo->writes_layer ||
3778 outinfo->writes_viewport_index;
3779 unsigned spi_vs_out_config, nparams;
3780
3781 /* VS is required to export at least one param. */
3782 nparams = MAX2(outinfo->param_exports, 1);
3783 spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
3784
3785 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3786 spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0);
3787 }
3788
3789 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, spi_vs_out_config);
3790
3791 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3792 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3793 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3794 V_02870C_SPI_SHADER_4COMP :
3795 V_02870C_SPI_SHADER_NONE) |
3796 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3797 V_02870C_SPI_SHADER_4COMP :
3798 V_02870C_SPI_SHADER_NONE) |
3799 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3800 V_02870C_SPI_SHADER_4COMP :
3801 V_02870C_SPI_SHADER_NONE));
3802
3803 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3804 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3805 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3806 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3807 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3808 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3809 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3810 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3811 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) |
3812 cull_dist_mask << 8 |
3813 clip_dist_mask);
3814
3815 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
3816 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
3817 outinfo->writes_viewport_index);
3818 }
3819
3820 static void
3821 radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs,
3822 struct radv_pipeline *pipeline,
3823 struct radv_shader_variant *shader)
3824 {
3825 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3826
3827 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
3828 radeon_emit(cs, va >> 8);
3829 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3830 radeon_emit(cs, shader->config.rsrc1);
3831 radeon_emit(cs, shader->config.rsrc2);
3832 }
3833
3834 static void
3835 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs,
3836 struct radv_pipeline *pipeline,
3837 struct radv_shader_variant *shader)
3838 {
3839 unsigned num_lds_blocks = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_lds_blocks;
3840 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3841 uint32_t rsrc2 = shader->config.rsrc2;
3842
3843 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3844 radeon_emit(cs, va >> 8);
3845 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3846
3847 rsrc2 |= S_00B52C_LDS_SIZE(num_lds_blocks);
3848 if (pipeline->device->physical_device->rad_info.chip_class == GFX7 &&
3849 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
3850 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
3851
3852 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
3853 radeon_emit(cs, shader->config.rsrc1);
3854 radeon_emit(cs, rsrc2);
3855 }
3856
3857 static void
3858 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
3859 struct radeon_cmdbuf *cs,
3860 struct radv_pipeline *pipeline,
3861 struct radv_shader_variant *shader)
3862 {
3863 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3864 gl_shader_stage es_type =
3865 radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
3866 struct radv_shader_variant *es =
3867 es_type == MESA_SHADER_TESS_EVAL ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX];
3868 const struct gfx10_ngg_info *ngg_state = &shader->info.ngg_info;
3869
3870 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
3871 radeon_emit(cs, va >> 8);
3872 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3873 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
3874 radeon_emit(cs, shader->config.rsrc1);
3875 radeon_emit(cs, shader->config.rsrc2);
3876
3877 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3878 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3879 clip_dist_mask = outinfo->clip_dist_mask;
3880 cull_dist_mask = outinfo->cull_dist_mask;
3881 total_mask = clip_dist_mask | cull_dist_mask;
3882 bool misc_vec_ena = outinfo->writes_pointsize ||
3883 outinfo->writes_layer ||
3884 outinfo->writes_viewport_index;
3885 bool es_enable_prim_id = outinfo->export_prim_id ||
3886 (es && es->info.uses_prim_id);
3887 bool break_wave_at_eoi = false;
3888 unsigned ge_cntl;
3889 unsigned nparams;
3890
3891 if (es_type == MESA_SHADER_TESS_EVAL) {
3892 struct radv_shader_variant *gs =
3893 pipeline->shaders[MESA_SHADER_GEOMETRY];
3894
3895 if (es_enable_prim_id || (gs && gs->info.uses_prim_id))
3896 break_wave_at_eoi = true;
3897 }
3898
3899 nparams = MAX2(outinfo->param_exports, 1);
3900 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG,
3901 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
3902 S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0));
3903
3904 radeon_set_context_reg(ctx_cs, R_028708_SPI_SHADER_IDX_FORMAT,
3905 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP));
3906 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3907 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3908 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3909 V_02870C_SPI_SHADER_4COMP :
3910 V_02870C_SPI_SHADER_NONE) |
3911 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3912 V_02870C_SPI_SHADER_4COMP :
3913 V_02870C_SPI_SHADER_NONE) |
3914 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3915 V_02870C_SPI_SHADER_4COMP :
3916 V_02870C_SPI_SHADER_NONE));
3917
3918 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3919 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3920 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3921 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3922 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3923 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3924 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3925 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3926 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) |
3927 cull_dist_mask << 8 |
3928 clip_dist_mask);
3929
3930 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN,
3931 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
3932 S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo->export_prim_id));
3933
3934 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
3935 ngg_state->vgt_esgs_ring_itemsize);
3936
3937 /* NGG specific registers. */
3938 struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
3939 uint32_t gs_num_invocations = gs ? gs->info.gs.invocations : 1;
3940
3941 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
3942 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state->hw_max_esverts) |
3943 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state->max_gsprims) |
3944 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state->max_gsprims * gs_num_invocations));
3945 radeon_set_context_reg(ctx_cs, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
3946 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state->max_out_verts));
3947 radeon_set_context_reg(ctx_cs, R_028B4C_GE_NGG_SUBGRP_CNTL,
3948 S_028B4C_PRIM_AMP_FACTOR(ngg_state->prim_amp_factor) |
3949 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
3950 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
3951 S_028B90_CNT(gs_num_invocations) |
3952 S_028B90_ENABLE(gs_num_invocations > 1) |
3953 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state->max_vert_out_per_gs_instance));
3954
3955 /* User edge flags are set by the pos exports. If user edge flags are
3956 * not used, we must use hw-generated edge flags and pass them via
3957 * the prim export to prevent drawing lines on internal edges of
3958 * decomposed primitives (such as quads) with polygon mode = lines.
3959 *
3960 * TODO: We should combine hw-generated edge flags with user edge
3961 * flags in the shader.
3962 */
3963 radeon_set_context_reg(ctx_cs, R_028838_PA_CL_NGG_CNTL,
3964 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) &&
3965 !radv_pipeline_has_gs(pipeline)) |
3966 /* Reuse for NGG. */
3967 S_028838_VERTEX_REUSE_DEPTH_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3 ? 30 : 0));
3968
3969 ge_cntl = S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) |
3970 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
3971 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
3972
3973 /* Bug workaround for a possible hang with non-tessellation cases.
3974 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
3975 *
3976 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
3977 */
3978 if (pipeline->device->physical_device->rad_info.chip_class == GFX10 &&
3979 !radv_pipeline_has_tess(pipeline) &&
3980 ngg_state->hw_max_esverts != 256) {
3981 ge_cntl &= C_03096C_VERT_GRP_SIZE;
3982
3983 if (ngg_state->hw_max_esverts > 5) {
3984 ge_cntl |= S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts - 5);
3985 }
3986 }
3987
3988 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, ge_cntl);
3989 }
3990
3991 static void
3992 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
3993 struct radv_pipeline *pipeline,
3994 struct radv_shader_variant *shader)
3995 {
3996 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3997
3998 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
3999 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4000 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
4001 radeon_emit(cs, va >> 8);
4002 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
4003 } else {
4004 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
4005 radeon_emit(cs, va >> 8);
4006 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
4007 }
4008
4009 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
4010 radeon_emit(cs, shader->config.rsrc1);
4011 radeon_emit(cs, shader->config.rsrc2);
4012 } else {
4013 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
4014 radeon_emit(cs, va >> 8);
4015 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
4016 radeon_emit(cs, shader->config.rsrc1);
4017 radeon_emit(cs, shader->config.rsrc2);
4018 }
4019 }
4020
4021 static void
4022 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *ctx_cs,
4023 struct radeon_cmdbuf *cs,
4024 struct radv_pipeline *pipeline)
4025 {
4026 struct radv_shader_variant *vs;
4027
4028 /* Skip shaders merged into HS/GS */
4029 vs = pipeline->shaders[MESA_SHADER_VERTEX];
4030 if (!vs)
4031 return;
4032
4033 if (vs->info.vs.as_ls)
4034 radv_pipeline_generate_hw_ls(cs, pipeline, vs);
4035 else if (vs->info.vs.as_es)
4036 radv_pipeline_generate_hw_es(cs, pipeline, vs);
4037 else if (vs->info.is_ngg)
4038 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, vs);
4039 else
4040 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, vs);
4041 }
4042
4043 static void
4044 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs,
4045 struct radeon_cmdbuf *cs,
4046 struct radv_pipeline *pipeline)
4047 {
4048 struct radv_shader_variant *tes, *tcs;
4049
4050 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
4051 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
4052
4053 if (tes) {
4054 if (tes->info.is_ngg) {
4055 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, tes);
4056 } else if (tes->info.tes.as_es)
4057 radv_pipeline_generate_hw_es(cs, pipeline, tes);
4058 else
4059 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes);
4060 }
4061
4062 radv_pipeline_generate_hw_hs(cs, pipeline, tcs);
4063
4064 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 &&
4065 !radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
4066 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
4067 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4068 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4069 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4070 }
4071 }
4072
4073 static void
4074 radv_pipeline_generate_tess_state(struct radeon_cmdbuf *ctx_cs,
4075 struct radv_pipeline *pipeline,
4076 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4077 {
4078 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
4079 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
4080 unsigned num_tcs_input_cp, num_tcs_output_cp, num_patches;
4081 unsigned ls_hs_config;
4082
4083 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
4084 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
4085 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
4086
4087 ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
4088 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
4089 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
4090
4091 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
4092 radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG,
4093 2, ls_hs_config);
4094 } else {
4095 radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG,
4096 ls_hs_config);
4097 }
4098
4099 switch (tes->info.tes.primitive_mode) {
4100 case GL_TRIANGLES:
4101 type = V_028B6C_TESS_TRIANGLE;
4102 break;
4103 case GL_QUADS:
4104 type = V_028B6C_TESS_QUAD;
4105 break;
4106 case GL_ISOLINES:
4107 type = V_028B6C_TESS_ISOLINE;
4108 break;
4109 }
4110
4111 switch (tes->info.tes.spacing) {
4112 case TESS_SPACING_EQUAL:
4113 partitioning = V_028B6C_PART_INTEGER;
4114 break;
4115 case TESS_SPACING_FRACTIONAL_ODD:
4116 partitioning = V_028B6C_PART_FRAC_ODD;
4117 break;
4118 case TESS_SPACING_FRACTIONAL_EVEN:
4119 partitioning = V_028B6C_PART_FRAC_EVEN;
4120 break;
4121 default:
4122 break;
4123 }
4124
4125 bool ccw = tes->info.tes.ccw;
4126 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_origin_state =
4127 vk_find_struct_const(pCreateInfo->pTessellationState,
4128 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
4129
4130 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT)
4131 ccw = !ccw;
4132
4133 if (tes->info.tes.point_mode)
4134 topology = V_028B6C_OUTPUT_POINT;
4135 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
4136 topology = V_028B6C_OUTPUT_LINE;
4137 else if (ccw)
4138 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
4139 else
4140 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
4141
4142 if (pipeline->device->physical_device->rad_info.has_distributed_tess) {
4143 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
4144 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
4145 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
4146 else
4147 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
4148 } else
4149 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
4150
4151 radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM,
4152 S_028B6C_TYPE(type) |
4153 S_028B6C_PARTITIONING(partitioning) |
4154 S_028B6C_TOPOLOGY(topology) |
4155 S_028B6C_DISTRIBUTION_MODE(distribution_mode));
4156 }
4157
4158 static void
4159 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs,
4160 struct radeon_cmdbuf *cs,
4161 struct radv_pipeline *pipeline,
4162 struct radv_shader_variant *gs)
4163 {
4164 const struct gfx9_gs_info *gs_state = &gs->info.gs_ring_info;
4165 unsigned gs_max_out_vertices;
4166 uint8_t *num_components;
4167 uint8_t max_stream;
4168 unsigned offset;
4169 uint64_t va;
4170
4171 gs_max_out_vertices = gs->info.gs.vertices_out;
4172 max_stream = gs->info.gs.max_stream;
4173 num_components = gs->info.gs.num_stream_output_components;
4174
4175 offset = num_components[0] * gs_max_out_vertices;
4176
4177 radeon_set_context_reg_seq(ctx_cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
4178 radeon_emit(ctx_cs, offset);
4179 if (max_stream >= 1)
4180 offset += num_components[1] * gs_max_out_vertices;
4181 radeon_emit(ctx_cs, offset);
4182 if (max_stream >= 2)
4183 offset += num_components[2] * gs_max_out_vertices;
4184 radeon_emit(ctx_cs, offset);
4185 if (max_stream >= 3)
4186 offset += num_components[3] * gs_max_out_vertices;
4187 radeon_set_context_reg(ctx_cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
4188
4189 radeon_set_context_reg_seq(ctx_cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
4190 radeon_emit(ctx_cs, num_components[0]);
4191 radeon_emit(ctx_cs, (max_stream >= 1) ? num_components[1] : 0);
4192 radeon_emit(ctx_cs, (max_stream >= 2) ? num_components[2] : 0);
4193 radeon_emit(ctx_cs, (max_stream >= 3) ? num_components[3] : 0);
4194
4195 uint32_t gs_num_invocations = gs->info.gs.invocations;
4196 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
4197 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
4198 S_028B90_ENABLE(gs_num_invocations > 0));
4199
4200 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
4201 gs_state->vgt_esgs_ring_itemsize);
4202
4203 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
4204
4205 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4206 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4207 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
4208 radeon_emit(cs, va >> 8);
4209 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
4210 } else {
4211 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
4212 radeon_emit(cs, va >> 8);
4213 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
4214 }
4215
4216 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
4217 radeon_emit(cs, gs->config.rsrc1);
4218 radeon_emit(cs, gs->config.rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
4219
4220 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
4221 radeon_set_context_reg(ctx_cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
4222 } else {
4223 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
4224 radeon_emit(cs, va >> 8);
4225 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
4226 radeon_emit(cs, gs->config.rsrc1);
4227 radeon_emit(cs, gs->config.rsrc2);
4228 }
4229
4230 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, pipeline->gs_copy_shader);
4231 }
4232
4233 static void
4234 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
4235 struct radeon_cmdbuf *cs,
4236 struct radv_pipeline *pipeline)
4237 {
4238 struct radv_shader_variant *gs;
4239
4240 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
4241 if (!gs)
4242 return;
4243
4244 if (gs->info.is_ngg)
4245 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, gs);
4246 else
4247 radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs);
4248
4249 radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT,
4250 gs->info.gs.vertices_out);
4251 }
4252
4253 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade,
4254 bool explicit, bool float16)
4255 {
4256 uint32_t ps_input_cntl;
4257 if (offset <= AC_EXP_PARAM_OFFSET_31) {
4258 ps_input_cntl = S_028644_OFFSET(offset);
4259 if (flat_shade || explicit)
4260 ps_input_cntl |= S_028644_FLAT_SHADE(1);
4261 if (explicit) {
4262 /* Force parameter cache to be read in passthrough
4263 * mode.
4264 */
4265 ps_input_cntl |= S_028644_OFFSET(1 << 5);
4266 }
4267 if (float16) {
4268 ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) |
4269 S_028644_ATTR0_VALID(1);
4270 }
4271 } else {
4272 /* The input is a DEFAULT_VAL constant. */
4273 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
4274 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
4275 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
4276 ps_input_cntl = S_028644_OFFSET(0x20) |
4277 S_028644_DEFAULT_VAL(offset);
4278 }
4279 return ps_input_cntl;
4280 }
4281
4282 static void
4283 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
4284 struct radv_pipeline *pipeline)
4285 {
4286 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4287 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
4288 uint32_t ps_input_cntl[32];
4289
4290 unsigned ps_offset = 0;
4291
4292 if (ps->info.ps.prim_id_input) {
4293 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
4294 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4295 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4296 ++ps_offset;
4297 }
4298 }
4299
4300 if (ps->info.ps.layer_input ||
4301 ps->info.needs_multiview_view_index) {
4302 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
4303 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4304 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4305 else
4306 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false, false);
4307 ++ps_offset;
4308 }
4309
4310 if (ps->info.ps.viewport_index_input) {
4311 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VIEWPORT];
4312 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4313 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4314 else
4315 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false, false);
4316 ++ps_offset;
4317 }
4318
4319 if (ps->info.ps.has_pcoord) {
4320 unsigned val;
4321 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4322 ps_input_cntl[ps_offset] = val;
4323 ps_offset++;
4324 }
4325
4326 if (ps->info.ps.num_input_clips_culls) {
4327 unsigned vs_offset;
4328
4329 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
4330 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4331 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false, false);
4332 ++ps_offset;
4333 }
4334
4335 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
4336 if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
4337 ps->info.ps.num_input_clips_culls > 4) {
4338 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false, false);
4339 ++ps_offset;
4340 }
4341 }
4342
4343 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.ps.input_mask; ++i) {
4344 unsigned vs_offset;
4345 bool flat_shade;
4346 bool explicit;
4347 bool float16;
4348 if (!(ps->info.ps.input_mask & (1u << i)))
4349 continue;
4350
4351 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
4352 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
4353 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
4354 ++ps_offset;
4355 continue;
4356 }
4357
4358 flat_shade = !!(ps->info.ps.flat_shaded_mask & (1u << ps_offset));
4359 explicit = !!(ps->info.ps.explicit_shaded_mask & (1u << ps_offset));
4360 float16 = !!(ps->info.ps.float16_shaded_mask & (1u << ps_offset));
4361
4362 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade, explicit, float16);
4363 ++ps_offset;
4364 }
4365
4366 if (ps_offset) {
4367 radeon_set_context_reg_seq(ctx_cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
4368 for (unsigned i = 0; i < ps_offset; i++) {
4369 radeon_emit(ctx_cs, ps_input_cntl[i]);
4370 }
4371 }
4372 }
4373
4374 static uint32_t
4375 radv_compute_db_shader_control(const struct radv_device *device,
4376 const struct radv_pipeline *pipeline,
4377 const struct radv_shader_variant *ps)
4378 {
4379 unsigned conservative_z_export = V_02880C_EXPORT_ANY_Z;
4380 unsigned z_order;
4381 if (ps->info.ps.early_fragment_test || !ps->info.ps.writes_memory)
4382 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
4383 else
4384 z_order = V_02880C_LATE_Z;
4385
4386 if (ps->info.ps.depth_layout == FRAG_DEPTH_LAYOUT_GREATER)
4387 conservative_z_export = V_02880C_EXPORT_GREATER_THAN_Z;
4388 else if (ps->info.ps.depth_layout == FRAG_DEPTH_LAYOUT_LESS)
4389 conservative_z_export = V_02880C_EXPORT_LESS_THAN_Z;
4390
4391 bool disable_rbplus = device->physical_device->rad_info.has_rbplus &&
4392 !device->physical_device->rad_info.rbplus_allowed;
4393
4394 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4395 * but this appears to break Project Cars (DXVK). See
4396 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4397 */
4398 bool mask_export_enable = ps->info.ps.writes_sample_mask;
4399
4400 return S_02880C_Z_EXPORT_ENABLE(ps->info.ps.writes_z) |
4401 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.ps.writes_stencil) |
4402 S_02880C_KILL_ENABLE(!!ps->info.ps.can_discard) |
4403 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
4404 S_02880C_CONSERVATIVE_Z_EXPORT(conservative_z_export) |
4405 S_02880C_Z_ORDER(z_order) |
4406 S_02880C_DEPTH_BEFORE_SHADER(ps->info.ps.early_fragment_test) |
4407 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps->info.ps.post_depth_coverage) |
4408 S_02880C_EXEC_ON_HIER_FAIL(ps->info.ps.writes_memory) |
4409 S_02880C_EXEC_ON_NOOP(ps->info.ps.writes_memory) |
4410 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
4411 }
4412
4413 static void
4414 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs,
4415 struct radeon_cmdbuf *cs,
4416 struct radv_pipeline *pipeline)
4417 {
4418 struct radv_shader_variant *ps;
4419 uint64_t va;
4420 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
4421
4422 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4423 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
4424
4425 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
4426 radeon_emit(cs, va >> 8);
4427 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
4428 radeon_emit(cs, ps->config.rsrc1);
4429 radeon_emit(cs, ps->config.rsrc2);
4430
4431 radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL,
4432 radv_compute_db_shader_control(pipeline->device,
4433 pipeline, ps));
4434
4435 radeon_set_context_reg(ctx_cs, R_0286CC_SPI_PS_INPUT_ENA,
4436 ps->config.spi_ps_input_ena);
4437
4438 radeon_set_context_reg(ctx_cs, R_0286D0_SPI_PS_INPUT_ADDR,
4439 ps->config.spi_ps_input_addr);
4440
4441 radeon_set_context_reg(ctx_cs, R_0286D8_SPI_PS_IN_CONTROL,
4442 S_0286D8_NUM_INTERP(ps->info.ps.num_interp) |
4443 S_0286D8_PS_W32_EN(ps->info.wave_size == 32));
4444
4445 radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
4446
4447 radeon_set_context_reg(ctx_cs, R_028710_SPI_SHADER_Z_FORMAT,
4448 ac_get_spi_shader_z_format(ps->info.ps.writes_z,
4449 ps->info.ps.writes_stencil,
4450 ps->info.ps.writes_sample_mask));
4451
4452 if (pipeline->device->dfsm_allowed) {
4453 /* optimise this? */
4454 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4455 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
4456 }
4457 }
4458
4459 static void
4460 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs,
4461 struct radv_pipeline *pipeline)
4462 {
4463 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4464 pipeline->device->physical_device->rad_info.chip_class >= GFX10)
4465 return;
4466
4467 unsigned vtx_reuse_depth = 30;
4468 if (radv_pipeline_has_tess(pipeline) &&
4469 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
4470 vtx_reuse_depth = 14;
4471 }
4472 radeon_set_context_reg(ctx_cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
4473 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
4474 }
4475
4476 static void
4477 radv_pipeline_generate_vgt_shader_config(struct radeon_cmdbuf *ctx_cs,
4478 const struct radv_pipeline *pipeline)
4479 {
4480 uint32_t stages = 0;
4481 if (radv_pipeline_has_tess(pipeline)) {
4482 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
4483 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4484
4485 if (radv_pipeline_has_gs(pipeline))
4486 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
4487 S_028B54_GS_EN(1);
4488 else if (radv_pipeline_has_ngg(pipeline))
4489 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
4490 else
4491 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
4492 } else if (radv_pipeline_has_gs(pipeline)) {
4493 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
4494 S_028B54_GS_EN(1);
4495 } else if (radv_pipeline_has_ngg(pipeline)) {
4496 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
4497 }
4498
4499 if (radv_pipeline_has_ngg(pipeline)) {
4500 stages |= S_028B54_PRIMGEN_EN(1);
4501 if (pipeline->streamout_shader)
4502 stages |= S_028B54_NGG_WAVE_ID_EN(1);
4503 if (radv_pipeline_has_ngg_passthrough(pipeline))
4504 stages |= S_028B54_PRIMGEN_PASSTHRU_EN(1);
4505 } else if (radv_pipeline_has_gs(pipeline)) {
4506 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
4507 }
4508
4509 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
4510 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4511
4512 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4513 uint8_t hs_size = 64, gs_size = 64, vs_size = 64;
4514
4515 if (radv_pipeline_has_tess(pipeline))
4516 hs_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.wave_size;
4517
4518 if (pipeline->shaders[MESA_SHADER_GEOMETRY]) {
4519 vs_size = gs_size = pipeline->shaders[MESA_SHADER_GEOMETRY]->info.wave_size;
4520 if (pipeline->gs_copy_shader)
4521 vs_size = pipeline->gs_copy_shader->info.wave_size;
4522 } else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
4523 vs_size = pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.wave_size;
4524 else if (pipeline->shaders[MESA_SHADER_VERTEX])
4525 vs_size = pipeline->shaders[MESA_SHADER_VERTEX]->info.wave_size;
4526
4527 if (radv_pipeline_has_ngg(pipeline))
4528 gs_size = vs_size;
4529
4530 /* legacy GS only supports Wave64 */
4531 stages |= S_028B54_HS_W32_EN(hs_size == 32 ? 1 : 0) |
4532 S_028B54_GS_W32_EN(gs_size == 32 ? 1 : 0) |
4533 S_028B54_VS_W32_EN(vs_size == 32 ? 1 : 0);
4534 }
4535
4536 radeon_set_context_reg(ctx_cs, R_028B54_VGT_SHADER_STAGES_EN, stages);
4537 }
4538
4539 static void
4540 radv_pipeline_generate_cliprect_rule(struct radeon_cmdbuf *ctx_cs,
4541 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4542 {
4543 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
4544 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
4545 uint32_t cliprect_rule = 0;
4546
4547 if (!discard_rectangle_info) {
4548 cliprect_rule = 0xffff;
4549 } else {
4550 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
4551 /* Interpret i as a bitmask, and then set the bit in
4552 * the mask if that combination of rectangles in which
4553 * the pixel is contained should pass the cliprect
4554 * test.
4555 */
4556 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
4557
4558 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
4559 !relevant_subset)
4560 continue;
4561
4562 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
4563 relevant_subset)
4564 continue;
4565
4566 cliprect_rule |= 1u << i;
4567 }
4568 }
4569
4570 radeon_set_context_reg(ctx_cs, R_02820C_PA_SC_CLIPRECT_RULE, cliprect_rule);
4571 }
4572
4573 static void
4574 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf *ctx_cs,
4575 struct radv_pipeline *pipeline)
4576 {
4577 bool break_wave_at_eoi = false;
4578 unsigned primgroup_size;
4579 unsigned vertgroup_size = 256; /* 256 = disable vertex grouping */
4580
4581 if (radv_pipeline_has_tess(pipeline)) {
4582 primgroup_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
4583 } else if (radv_pipeline_has_gs(pipeline)) {
4584 const struct gfx9_gs_info *gs_state =
4585 &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs_ring_info;
4586 unsigned vgt_gs_onchip_cntl = gs_state->vgt_gs_onchip_cntl;
4587 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
4588 } else {
4589 primgroup_size = 128; /* recommended without a GS and tess */
4590 }
4591
4592 if (radv_pipeline_has_tess(pipeline)) {
4593 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4594 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4595 break_wave_at_eoi = true;
4596 }
4597
4598 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL,
4599 S_03096C_PRIM_GRP_SIZE(primgroup_size) |
4600 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
4601 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4602 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi));
4603 }
4604
4605 static void
4606 radv_pipeline_generate_vgt_gs_out(struct radeon_cmdbuf *ctx_cs,
4607 struct radv_pipeline *pipeline,
4608 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4609 const struct radv_graphics_pipeline_create_info *extra)
4610 {
4611 uint32_t gs_out;
4612
4613 if (radv_pipeline_has_gs(pipeline)) {
4614 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
4615 } else if (radv_pipeline_has_tess(pipeline)) {
4616 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode) {
4617 gs_out = V_028A6C_OUTPRIM_TYPE_POINTLIST;
4618 } else {
4619 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.primitive_mode);
4620 }
4621 } else {
4622 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
4623 }
4624
4625 if (extra && extra->use_rectlist) {
4626 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4627 if (radv_pipeline_has_ngg(pipeline))
4628 gs_out = V_028A6C_VGT_OUT_RECT_V0;
4629 }
4630
4631 radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
4632 }
4633
4634 static void
4635 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
4636 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4637 const struct radv_graphics_pipeline_create_info *extra,
4638 const struct radv_blend_state *blend)
4639 {
4640 struct radeon_cmdbuf *ctx_cs = &pipeline->ctx_cs;
4641 struct radeon_cmdbuf *cs = &pipeline->cs;
4642
4643 cs->max_dw = 64;
4644 ctx_cs->max_dw = 256;
4645 cs->buf = malloc(4 * (cs->max_dw + ctx_cs->max_dw));
4646 ctx_cs->buf = cs->buf + cs->max_dw;
4647
4648 radv_pipeline_generate_depth_stencil_state(ctx_cs, pipeline, pCreateInfo, extra);
4649 radv_pipeline_generate_blend_state(ctx_cs, pipeline, blend);
4650 radv_pipeline_generate_raster_state(ctx_cs, pipeline, pCreateInfo);
4651 radv_pipeline_generate_multisample_state(ctx_cs, pipeline);
4652 radv_pipeline_generate_vgt_gs_mode(ctx_cs, pipeline);
4653 radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline);
4654
4655 if (radv_pipeline_has_tess(pipeline)) {
4656 radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline);
4657 radv_pipeline_generate_tess_state(ctx_cs, pipeline, pCreateInfo);
4658 }
4659
4660 radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline);
4661 radv_pipeline_generate_fragment_shader(ctx_cs, cs, pipeline);
4662 radv_pipeline_generate_ps_inputs(ctx_cs, pipeline);
4663 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline);
4664 radv_pipeline_generate_binning_state(ctx_cs, pipeline, pCreateInfo, blend);
4665 radv_pipeline_generate_vgt_shader_config(ctx_cs, pipeline);
4666 radv_pipeline_generate_cliprect_rule(ctx_cs, pCreateInfo);
4667 radv_pipeline_generate_vgt_gs_out(ctx_cs, pipeline, pCreateInfo, extra);
4668
4669 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && !radv_pipeline_has_ngg(pipeline))
4670 gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline);
4671
4672 pipeline->ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4);
4673
4674 assert(ctx_cs->cdw <= ctx_cs->max_dw);
4675 assert(cs->cdw <= cs->max_dw);
4676 }
4677
4678 static struct radv_ia_multi_vgt_param_helpers
4679 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline)
4680 {
4681 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
4682 const struct radv_device *device = pipeline->device;
4683
4684 if (radv_pipeline_has_tess(pipeline))
4685 ia_multi_vgt_param.primgroup_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
4686 else if (radv_pipeline_has_gs(pipeline))
4687 ia_multi_vgt_param.primgroup_size = 64;
4688 else
4689 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
4690
4691 /* GS requirement. */
4692 ia_multi_vgt_param.partial_es_wave = false;
4693 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= GFX8)
4694 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
4695 ia_multi_vgt_param.partial_es_wave = true;
4696
4697 ia_multi_vgt_param.ia_switch_on_eoi = false;
4698 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input)
4699 ia_multi_vgt_param.ia_switch_on_eoi = true;
4700 if (radv_pipeline_has_gs(pipeline) &&
4701 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.uses_prim_id)
4702 ia_multi_vgt_param.ia_switch_on_eoi = true;
4703 if (radv_pipeline_has_tess(pipeline)) {
4704 /* SWITCH_ON_EOI must be set if PrimID is used. */
4705 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4706 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4707 ia_multi_vgt_param.ia_switch_on_eoi = true;
4708 }
4709
4710 ia_multi_vgt_param.partial_vs_wave = false;
4711 if (radv_pipeline_has_tess(pipeline)) {
4712 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4713 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
4714 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
4715 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
4716 radv_pipeline_has_gs(pipeline))
4717 ia_multi_vgt_param.partial_vs_wave = true;
4718 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4719 if (device->physical_device->rad_info.has_distributed_tess) {
4720 if (radv_pipeline_has_gs(pipeline)) {
4721 if (device->physical_device->rad_info.chip_class <= GFX8)
4722 ia_multi_vgt_param.partial_es_wave = true;
4723 } else {
4724 ia_multi_vgt_param.partial_vs_wave = true;
4725 }
4726 }
4727 }
4728
4729 if (radv_pipeline_has_gs(pipeline)) {
4730 /* On these chips there is the possibility of a hang if the
4731 * pipeline uses a GS and partial_vs_wave is not set.
4732 *
4733 * This mostly does not hit 4-SE chips, as those typically set
4734 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4735 * with GS due to another workaround.
4736 *
4737 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4738 */
4739 if (device->physical_device->rad_info.family == CHIP_TONGA ||
4740 device->physical_device->rad_info.family == CHIP_FIJI ||
4741 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
4742 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
4743 device->physical_device->rad_info.family == CHIP_POLARIS12 ||
4744 device->physical_device->rad_info.family == CHIP_VEGAM) {
4745 ia_multi_vgt_param.partial_vs_wave = true;
4746 }
4747 }
4748
4749 ia_multi_vgt_param.base =
4750 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
4751 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4752 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == GFX8 ? 2 : 0) |
4753 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
4754 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
4755
4756 return ia_multi_vgt_param;
4757 }
4758
4759
4760 static void
4761 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
4762 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4763 {
4764 const VkPipelineVertexInputStateCreateInfo *vi_info =
4765 pCreateInfo->pVertexInputState;
4766
4767 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
4768 const VkVertexInputBindingDescription *desc =
4769 &vi_info->pVertexBindingDescriptions[i];
4770
4771 pipeline->binding_stride[desc->binding] = desc->stride;
4772 pipeline->num_vertex_bindings =
4773 MAX2(pipeline->num_vertex_bindings, desc->binding + 1);
4774 }
4775 }
4776
4777 static struct radv_shader_variant *
4778 radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline)
4779 {
4780 int i;
4781
4782 for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) {
4783 struct radv_shader_variant *shader =
4784 radv_get_shader(pipeline, i);
4785
4786 if (shader && shader->info.so.num_outputs > 0)
4787 return shader;
4788 }
4789
4790 return NULL;
4791 }
4792
4793 static VkResult
4794 radv_pipeline_init(struct radv_pipeline *pipeline,
4795 struct radv_device *device,
4796 struct radv_pipeline_cache *cache,
4797 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4798 const struct radv_graphics_pipeline_create_info *extra)
4799 {
4800 VkResult result;
4801
4802 pipeline->device = device;
4803 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
4804 assert(pipeline->layout);
4805
4806 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
4807
4808 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
4809 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
4810 radv_init_feedback(creation_feedback);
4811
4812 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
4813
4814 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
4815 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
4816 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
4817 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
4818 pStages[stage] = &pCreateInfo->pStages[i];
4819 if(creation_feedback)
4820 stage_feedbacks[stage] = &creation_feedback->pPipelineStageCreationFeedbacks[i];
4821 }
4822
4823 struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend);
4824
4825 result = radv_create_shaders(pipeline, device, cache, &key, pStages,
4826 pCreateInfo->flags, pipeline_feedback,
4827 stage_feedbacks);
4828 if (result != VK_SUCCESS)
4829 return result;
4830
4831 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
4832 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
4833 radv_pipeline_init_input_assembly_state(pipeline, pCreateInfo, extra);
4834 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo, extra);
4835
4836 /* Ensure that some export memory is always allocated, for two reasons:
4837 *
4838 * 1) Correctness: The hardware ignores the EXEC mask if no export
4839 * memory is allocated, so KILL and alpha test do not work correctly
4840 * without this.
4841 * 2) Performance: Every shader needs at least a NULL export, even when
4842 * it writes no color/depth output. The NULL export instruction
4843 * stalls without this setting.
4844 *
4845 * Don't add this to CB_SHADER_MASK.
4846 *
4847 * GFX10 supports pixel shaders without exports by setting both the
4848 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
4849 * instructions if any are present.
4850 */
4851 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4852 if ((pipeline->device->physical_device->rad_info.chip_class <= GFX9 ||
4853 ps->info.ps.can_discard) &&
4854 !blend.spi_shader_col_format) {
4855 if (!ps->info.ps.writes_z &&
4856 !ps->info.ps.writes_stencil &&
4857 !ps->info.ps.writes_sample_mask)
4858 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
4859 }
4860
4861 blend.cb_shader_mask = ps->info.ps.cb_shader_mask;
4862
4863 if (extra &&
4864 (extra->custom_blend_mode == V_028808_CB_ELIMINATE_FAST_CLEAR ||
4865 extra->custom_blend_mode == V_028808_CB_FMASK_DECOMPRESS ||
4866 extra->custom_blend_mode == V_028808_CB_DCC_DECOMPRESS ||
4867 extra->custom_blend_mode == V_028808_CB_RESOLVE)) {
4868 /* According to the CB spec states, CB_SHADER_MASK should be
4869 * set to enable writes to all four channels of MRT0.
4870 */
4871 blend.cb_shader_mask = 0xf;
4872 }
4873
4874 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
4875 if (pipeline->shaders[i]) {
4876 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
4877 }
4878 }
4879
4880 if (radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
4881 struct radv_shader_variant *gs =
4882 pipeline->shaders[MESA_SHADER_GEOMETRY];
4883
4884 calculate_gs_ring_sizes(pipeline, &gs->info.gs_ring_info);
4885 }
4886
4887 if (radv_pipeline_has_tess(pipeline)) {
4888 pipeline->graphics.tess_patch_control_points =
4889 pCreateInfo->pTessellationState->patchControlPoints;
4890 }
4891
4892 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline);
4893
4894 radv_compute_vertex_input_state(pipeline, pCreateInfo);
4895
4896 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
4897 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
4898
4899 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
4900 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
4901 if (loc->sgpr_idx != -1) {
4902 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
4903 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
4904 if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id)
4905 pipeline->graphics.vtx_emit_num = 3;
4906 else
4907 pipeline->graphics.vtx_emit_num = 2;
4908 }
4909
4910 /* Find the last vertex shader stage that eventually uses streamout. */
4911 pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline);
4912
4913 result = radv_pipeline_scratch_init(device, pipeline);
4914 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend);
4915
4916 return result;
4917 }
4918
4919 VkResult
4920 radv_graphics_pipeline_create(
4921 VkDevice _device,
4922 VkPipelineCache _cache,
4923 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4924 const struct radv_graphics_pipeline_create_info *extra,
4925 const VkAllocationCallbacks *pAllocator,
4926 VkPipeline *pPipeline)
4927 {
4928 RADV_FROM_HANDLE(radv_device, device, _device);
4929 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
4930 struct radv_pipeline *pipeline;
4931 VkResult result;
4932
4933 pipeline = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8,
4934 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4935 if (pipeline == NULL)
4936 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4937
4938 vk_object_base_init(&device->vk, &pipeline->base,
4939 VK_OBJECT_TYPE_PIPELINE);
4940
4941 result = radv_pipeline_init(pipeline, device, cache,
4942 pCreateInfo, extra);
4943 if (result != VK_SUCCESS) {
4944 radv_pipeline_destroy(device, pipeline, pAllocator);
4945 return result;
4946 }
4947
4948 *pPipeline = radv_pipeline_to_handle(pipeline);
4949
4950 return VK_SUCCESS;
4951 }
4952
4953 VkResult radv_CreateGraphicsPipelines(
4954 VkDevice _device,
4955 VkPipelineCache pipelineCache,
4956 uint32_t count,
4957 const VkGraphicsPipelineCreateInfo* pCreateInfos,
4958 const VkAllocationCallbacks* pAllocator,
4959 VkPipeline* pPipelines)
4960 {
4961 VkResult result = VK_SUCCESS;
4962 unsigned i = 0;
4963
4964 for (; i < count; i++) {
4965 VkResult r;
4966 r = radv_graphics_pipeline_create(_device,
4967 pipelineCache,
4968 &pCreateInfos[i],
4969 NULL, pAllocator, &pPipelines[i]);
4970 if (r != VK_SUCCESS) {
4971 result = r;
4972 pPipelines[i] = VK_NULL_HANDLE;
4973
4974 if (pCreateInfos[i].flags & VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT)
4975 break;
4976 }
4977 }
4978
4979 for (; i < count; ++i)
4980 pPipelines[i] = VK_NULL_HANDLE;
4981
4982 return result;
4983 }
4984
4985 static void
4986 radv_pipeline_generate_hw_cs(struct radeon_cmdbuf *cs,
4987 struct radv_pipeline *pipeline)
4988 {
4989 struct radv_shader_variant *shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4990 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
4991 struct radv_device *device = pipeline->device;
4992
4993 radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
4994 radeon_emit(cs, va >> 8);
4995 radeon_emit(cs, S_00B834_DATA(va >> 40));
4996
4997 radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
4998 radeon_emit(cs, shader->config.rsrc1);
4999 radeon_emit(cs, shader->config.rsrc2);
5000 if (device->physical_device->rad_info.chip_class >= GFX10) {
5001 radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, shader->config.rsrc3);
5002 }
5003 }
5004
5005 static void
5006 radv_pipeline_generate_compute_state(struct radeon_cmdbuf *cs,
5007 struct radv_pipeline *pipeline)
5008 {
5009 struct radv_shader_variant *shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5010 struct radv_device *device = pipeline->device;
5011 unsigned threads_per_threadgroup;
5012 unsigned threadgroups_per_cu = 1;
5013 unsigned waves_per_threadgroup;
5014 unsigned max_waves_per_sh = 0;
5015
5016 /* Calculate best compute resource limits. */
5017 threads_per_threadgroup = shader->info.cs.block_size[0] *
5018 shader->info.cs.block_size[1] *
5019 shader->info.cs.block_size[2];
5020 waves_per_threadgroup = DIV_ROUND_UP(threads_per_threadgroup,
5021 shader->info.wave_size);
5022
5023 if (device->physical_device->rad_info.chip_class >= GFX10 &&
5024 waves_per_threadgroup == 1)
5025 threadgroups_per_cu = 2;
5026
5027 radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
5028 ac_get_compute_resource_limits(&device->physical_device->rad_info,
5029 waves_per_threadgroup,
5030 max_waves_per_sh,
5031 threadgroups_per_cu));
5032
5033 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5034 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(shader->info.cs.block_size[0]));
5035 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(shader->info.cs.block_size[1]));
5036 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(shader->info.cs.block_size[2]));
5037 }
5038
5039 static void
5040 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
5041 {
5042 struct radv_device *device = pipeline->device;
5043 struct radeon_cmdbuf *cs = &pipeline->cs;
5044
5045 cs->max_dw = device->physical_device->rad_info.chip_class >= GFX10 ? 19 : 16;
5046 cs->buf = malloc(cs->max_dw * 4);
5047
5048 radv_pipeline_generate_hw_cs(cs, pipeline);
5049 radv_pipeline_generate_compute_state(cs, pipeline);
5050
5051 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
5052 }
5053
5054 static struct radv_pipeline_key
5055 radv_generate_compute_pipeline_key(struct radv_pipeline *pipeline,
5056 const VkComputePipelineCreateInfo *pCreateInfo)
5057 {
5058 const VkPipelineShaderStageCreateInfo *stage = &pCreateInfo->stage;
5059 struct radv_pipeline_key key;
5060 memset(&key, 0, sizeof(key));
5061
5062 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
5063 key.optimisations_disabled = 1;
5064
5065 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT *subgroup_size =
5066 vk_find_struct_const(stage->pNext,
5067 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT);
5068
5069 if (subgroup_size) {
5070 assert(subgroup_size->requiredSubgroupSize == 32 ||
5071 subgroup_size->requiredSubgroupSize == 64);
5072 key.compute_subgroup_size = subgroup_size->requiredSubgroupSize;
5073 }
5074
5075 return key;
5076 }
5077
5078 static VkResult radv_compute_pipeline_create(
5079 VkDevice _device,
5080 VkPipelineCache _cache,
5081 const VkComputePipelineCreateInfo* pCreateInfo,
5082 const VkAllocationCallbacks* pAllocator,
5083 VkPipeline* pPipeline)
5084 {
5085 RADV_FROM_HANDLE(radv_device, device, _device);
5086 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
5087 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
5088 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
5089 struct radv_pipeline *pipeline;
5090 VkResult result;
5091
5092 pipeline = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8,
5093 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5094 if (pipeline == NULL)
5095 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5096
5097 vk_object_base_init(&device->vk, &pipeline->base,
5098 VK_OBJECT_TYPE_PIPELINE);
5099
5100 pipeline->device = device;
5101 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
5102 assert(pipeline->layout);
5103
5104 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
5105 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
5106 radv_init_feedback(creation_feedback);
5107
5108 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
5109 if (creation_feedback)
5110 stage_feedbacks[MESA_SHADER_COMPUTE] = &creation_feedback->pPipelineStageCreationFeedbacks[0];
5111
5112 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
5113
5114 struct radv_pipeline_key key =
5115 radv_generate_compute_pipeline_key(pipeline, pCreateInfo);
5116
5117 result = radv_create_shaders(pipeline, device, cache, &key, pStages,
5118 pCreateInfo->flags, pipeline_feedback,
5119 stage_feedbacks);
5120 if (result != VK_SUCCESS) {
5121 radv_pipeline_destroy(device, pipeline, pAllocator);
5122 return result;
5123 }
5124
5125 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
5126 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
5127 result = radv_pipeline_scratch_init(device, pipeline);
5128 if (result != VK_SUCCESS) {
5129 radv_pipeline_destroy(device, pipeline, pAllocator);
5130 return result;
5131 }
5132
5133 radv_compute_generate_pm4(pipeline);
5134
5135 *pPipeline = radv_pipeline_to_handle(pipeline);
5136
5137 return VK_SUCCESS;
5138 }
5139
5140 VkResult radv_CreateComputePipelines(
5141 VkDevice _device,
5142 VkPipelineCache pipelineCache,
5143 uint32_t count,
5144 const VkComputePipelineCreateInfo* pCreateInfos,
5145 const VkAllocationCallbacks* pAllocator,
5146 VkPipeline* pPipelines)
5147 {
5148 VkResult result = VK_SUCCESS;
5149
5150 unsigned i = 0;
5151 for (; i < count; i++) {
5152 VkResult r;
5153 r = radv_compute_pipeline_create(_device, pipelineCache,
5154 &pCreateInfos[i],
5155 pAllocator, &pPipelines[i]);
5156 if (r != VK_SUCCESS) {
5157 result = r;
5158 pPipelines[i] = VK_NULL_HANDLE;
5159
5160 if (pCreateInfos[i].flags & VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT)
5161 break;
5162 }
5163 }
5164
5165 for (; i < count; ++i)
5166 pPipelines[i] = VK_NULL_HANDLE;
5167
5168 return result;
5169 }
5170
5171
5172 static uint32_t radv_get_executable_count(const struct radv_pipeline *pipeline)
5173 {
5174 uint32_t ret = 0;
5175 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5176 if (!pipeline->shaders[i])
5177 continue;
5178
5179 if (i == MESA_SHADER_GEOMETRY &&
5180 !radv_pipeline_has_ngg(pipeline)) {
5181 ret += 2u;
5182 } else {
5183 ret += 1u;
5184 }
5185
5186 }
5187 return ret;
5188 }
5189
5190 static struct radv_shader_variant *
5191 radv_get_shader_from_executable_index(const struct radv_pipeline *pipeline, int index, gl_shader_stage *stage)
5192 {
5193 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5194 if (!pipeline->shaders[i])
5195 continue;
5196 if (!index) {
5197 *stage = i;
5198 return pipeline->shaders[i];
5199 }
5200
5201 --index;
5202
5203 if (i == MESA_SHADER_GEOMETRY &&
5204 !radv_pipeline_has_ngg(pipeline)) {
5205 if (!index) {
5206 *stage = i;
5207 return pipeline->gs_copy_shader;
5208 }
5209 --index;
5210 }
5211 }
5212
5213 *stage = -1;
5214 return NULL;
5215 }
5216
5217 /* Basically strlcpy (which does not exist on linux) specialized for
5218 * descriptions. */
5219 static void desc_copy(char *desc, const char *src) {
5220 int len = strlen(src);
5221 assert(len < VK_MAX_DESCRIPTION_SIZE);
5222 memcpy(desc, src, len);
5223 memset(desc + len, 0, VK_MAX_DESCRIPTION_SIZE - len);
5224 }
5225
5226 VkResult radv_GetPipelineExecutablePropertiesKHR(
5227 VkDevice _device,
5228 const VkPipelineInfoKHR* pPipelineInfo,
5229 uint32_t* pExecutableCount,
5230 VkPipelineExecutablePropertiesKHR* pProperties)
5231 {
5232 RADV_FROM_HANDLE(radv_pipeline, pipeline, pPipelineInfo->pipeline);
5233 const uint32_t total_count = radv_get_executable_count(pipeline);
5234
5235 if (!pProperties) {
5236 *pExecutableCount = total_count;
5237 return VK_SUCCESS;
5238 }
5239
5240 const uint32_t count = MIN2(total_count, *pExecutableCount);
5241 for (unsigned i = 0, executable_idx = 0;
5242 i < MESA_SHADER_STAGES && executable_idx < count; ++i) {
5243 if (!pipeline->shaders[i])
5244 continue;
5245 pProperties[executable_idx].stages = mesa_to_vk_shader_stage(i);
5246 const char *name = NULL;
5247 const char *description = NULL;
5248 switch(i) {
5249 case MESA_SHADER_VERTEX:
5250 name = "Vertex Shader";
5251 description = "Vulkan Vertex Shader";
5252 break;
5253 case MESA_SHADER_TESS_CTRL:
5254 if (!pipeline->shaders[MESA_SHADER_VERTEX]) {
5255 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5256 name = "Vertex + Tessellation Control Shaders";
5257 description = "Combined Vulkan Vertex and Tessellation Control Shaders";
5258 } else {
5259 name = "Tessellation Control Shader";
5260 description = "Vulkan Tessellation Control Shader";
5261 }
5262 break;
5263 case MESA_SHADER_TESS_EVAL:
5264 name = "Tessellation Evaluation Shader";
5265 description = "Vulkan Tessellation Evaluation Shader";
5266 break;
5267 case MESA_SHADER_GEOMETRY:
5268 if (radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
5269 pProperties[executable_idx].stages |= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT;
5270 name = "Tessellation Evaluation + Geometry Shaders";
5271 description = "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5272 } else if (!radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_VERTEX]) {
5273 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5274 name = "Vertex + Geometry Shader";
5275 description = "Combined Vulkan Vertex and Geometry Shaders";
5276 } else {
5277 name = "Geometry Shader";
5278 description = "Vulkan Geometry Shader";
5279 }
5280 break;
5281 case MESA_SHADER_FRAGMENT:
5282 name = "Fragment Shader";
5283 description = "Vulkan Fragment Shader";
5284 break;
5285 case MESA_SHADER_COMPUTE:
5286 name = "Compute Shader";
5287 description = "Vulkan Compute Shader";
5288 break;
5289 }
5290
5291 pProperties[executable_idx].subgroupSize = pipeline->shaders[i]->info.wave_size;
5292 desc_copy(pProperties[executable_idx].name, name);
5293 desc_copy(pProperties[executable_idx].description, description);
5294
5295 ++executable_idx;
5296 if (i == MESA_SHADER_GEOMETRY &&
5297 !radv_pipeline_has_ngg(pipeline)) {
5298 assert(pipeline->gs_copy_shader);
5299 if (executable_idx >= count)
5300 break;
5301
5302 pProperties[executable_idx].stages = VK_SHADER_STAGE_GEOMETRY_BIT;
5303 pProperties[executable_idx].subgroupSize = 64;
5304 desc_copy(pProperties[executable_idx].name, "GS Copy Shader");
5305 desc_copy(pProperties[executable_idx].description,
5306 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5307
5308 ++executable_idx;
5309 }
5310 }
5311
5312 VkResult result = *pExecutableCount < total_count ? VK_INCOMPLETE : VK_SUCCESS;
5313 *pExecutableCount = count;
5314 return result;
5315 }
5316
5317 VkResult radv_GetPipelineExecutableStatisticsKHR(
5318 VkDevice _device,
5319 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5320 uint32_t* pStatisticCount,
5321 VkPipelineExecutableStatisticKHR* pStatistics)
5322 {
5323 RADV_FROM_HANDLE(radv_device, device, _device);
5324 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5325 gl_shader_stage stage;
5326 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5327
5328 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
5329 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
5330 unsigned max_waves = radv_get_max_waves(device, shader, stage);
5331
5332 VkPipelineExecutableStatisticKHR *s = pStatistics;
5333 VkPipelineExecutableStatisticKHR *end = s + (pStatistics ? *pStatisticCount : 0);
5334 VkResult result = VK_SUCCESS;
5335
5336 if (s < end) {
5337 desc_copy(s->name, "SGPRs");
5338 desc_copy(s->description, "Number of SGPR registers allocated per subgroup");
5339 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5340 s->value.u64 = shader->config.num_sgprs;
5341 }
5342 ++s;
5343
5344 if (s < end) {
5345 desc_copy(s->name, "VGPRs");
5346 desc_copy(s->description, "Number of VGPR registers allocated per subgroup");
5347 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5348 s->value.u64 = shader->config.num_vgprs;
5349 }
5350 ++s;
5351
5352 if (s < end) {
5353 desc_copy(s->name, "Spilled SGPRs");
5354 desc_copy(s->description, "Number of SGPR registers spilled per subgroup");
5355 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5356 s->value.u64 = shader->config.spilled_sgprs;
5357 }
5358 ++s;
5359
5360 if (s < end) {
5361 desc_copy(s->name, "Spilled VGPRs");
5362 desc_copy(s->description, "Number of VGPR registers spilled per subgroup");
5363 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5364 s->value.u64 = shader->config.spilled_vgprs;
5365 }
5366 ++s;
5367
5368 if (s < end) {
5369 desc_copy(s->name, "PrivMem VGPRs");
5370 desc_copy(s->description, "Number of VGPRs stored in private memory per subgroup");
5371 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5372 s->value.u64 = shader->info.private_mem_vgprs;
5373 }
5374 ++s;
5375
5376 if (s < end) {
5377 desc_copy(s->name, "Code size");
5378 desc_copy(s->description, "Code size in bytes");
5379 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5380 s->value.u64 = shader->exec_size;
5381 }
5382 ++s;
5383
5384 if (s < end) {
5385 desc_copy(s->name, "LDS size");
5386 desc_copy(s->description, "LDS size in bytes per workgroup");
5387 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5388 s->value.u64 = shader->config.lds_size * lds_increment;
5389 }
5390 ++s;
5391
5392 if (s < end) {
5393 desc_copy(s->name, "Scratch size");
5394 desc_copy(s->description, "Private memory in bytes per subgroup");
5395 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5396 s->value.u64 = shader->config.scratch_bytes_per_wave;
5397 }
5398 ++s;
5399
5400 if (s < end) {
5401 desc_copy(s->name, "Subgroups per SIMD");
5402 desc_copy(s->description, "The maximum number of subgroups in flight on a SIMD unit");
5403 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5404 s->value.u64 = max_waves;
5405 }
5406 ++s;
5407
5408 if (shader->statistics) {
5409 for (unsigned i = 0; i < shader->statistics->count; i++) {
5410 struct radv_compiler_statistic_info *info = &shader->statistics->infos[i];
5411 uint32_t value = shader->statistics->values[i];
5412 if (s < end) {
5413 desc_copy(s->name, info->name);
5414 desc_copy(s->description, info->desc);
5415 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5416 s->value.u64 = value;
5417 }
5418 ++s;
5419 }
5420 }
5421
5422 if (!pStatistics)
5423 *pStatisticCount = s - pStatistics;
5424 else if (s > end) {
5425 *pStatisticCount = end - pStatistics;
5426 result = VK_INCOMPLETE;
5427 } else {
5428 *pStatisticCount = s - pStatistics;
5429 }
5430
5431 return result;
5432 }
5433
5434 static VkResult radv_copy_representation(void *data, size_t *data_size, const char *src)
5435 {
5436 size_t total_size = strlen(src) + 1;
5437
5438 if (!data) {
5439 *data_size = total_size;
5440 return VK_SUCCESS;
5441 }
5442
5443 size_t size = MIN2(total_size, *data_size);
5444
5445 memcpy(data, src, size);
5446 if (size)
5447 *((char*)data + size - 1) = 0;
5448 return size < total_size ? VK_INCOMPLETE : VK_SUCCESS;
5449 }
5450
5451 VkResult radv_GetPipelineExecutableInternalRepresentationsKHR(
5452 VkDevice device,
5453 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5454 uint32_t* pInternalRepresentationCount,
5455 VkPipelineExecutableInternalRepresentationKHR* pInternalRepresentations)
5456 {
5457 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5458 gl_shader_stage stage;
5459 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5460
5461 VkPipelineExecutableInternalRepresentationKHR *p = pInternalRepresentations;
5462 VkPipelineExecutableInternalRepresentationKHR *end = p + (pInternalRepresentations ? *pInternalRepresentationCount : 0);
5463 VkResult result = VK_SUCCESS;
5464 /* optimized NIR */
5465 if (p < end) {
5466 p->isText = true;
5467 desc_copy(p->name, "NIR Shader(s)");
5468 desc_copy(p->description, "The optimized NIR shader(s)");
5469 if (radv_copy_representation(p->pData, &p->dataSize, shader->nir_string) != VK_SUCCESS)
5470 result = VK_INCOMPLETE;
5471 }
5472 ++p;
5473
5474 /* backend IR */
5475 if (p < end) {
5476 p->isText = true;
5477 if (pipeline->device->physical_device->use_llvm) {
5478 desc_copy(p->name, "LLVM IR");
5479 desc_copy(p->description, "The LLVM IR after some optimizations");
5480 } else {
5481 desc_copy(p->name, "ACO IR");
5482 desc_copy(p->description, "The ACO IR after some optimizations");
5483 }
5484 if (radv_copy_representation(p->pData, &p->dataSize, shader->ir_string) != VK_SUCCESS)
5485 result = VK_INCOMPLETE;
5486 }
5487 ++p;
5488
5489 /* Disassembler */
5490 if (p < end) {
5491 p->isText = true;
5492 desc_copy(p->name, "Assembly");
5493 desc_copy(p->description, "Final Assembly");
5494 if (radv_copy_representation(p->pData, &p->dataSize, shader->disasm_string) != VK_SUCCESS)
5495 result = VK_INCOMPLETE;
5496 }
5497 ++p;
5498
5499 if (!pInternalRepresentations)
5500 *pInternalRepresentationCount = p - pInternalRepresentations;
5501 else if(p > end) {
5502 result = VK_INCOMPLETE;
5503 *pInternalRepresentationCount = end - pInternalRepresentations;
5504 } else {
5505 *pInternalRepresentationCount = p - pInternalRepresentations;
5506 }
5507
5508 return result;
5509 }