2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
34 #include "radv_shader.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
48 #include "ac_shader_util.h"
50 struct radv_blend_state
{
51 uint32_t blend_enable_4bit
;
52 uint32_t need_src_alpha
;
54 uint32_t cb_color_control
;
55 uint32_t cb_target_mask
;
56 uint32_t cb_target_enabled_4bit
;
57 uint32_t sx_mrt_blend_opt
[8];
58 uint32_t cb_blend_control
[8];
60 uint32_t spi_shader_col_format
;
61 uint32_t col_format_is_int8
;
62 uint32_t col_format_is_int10
;
63 uint32_t cb_shader_mask
;
64 uint32_t db_alpha_to_mask
;
66 uint32_t commutative_4bit
;
68 bool single_cb_enable
;
69 bool mrt0_is_dual_src
;
72 struct radv_dsa_order_invariance
{
73 /* Whether the final result in Z/S buffers is guaranteed to be
74 * invariant under changes to the order in which fragments arrive.
78 /* Whether the set of fragments that pass the combined Z/S test is
79 * guaranteed to be invariant under changes to the order in which
85 static const VkPipelineMultisampleStateCreateInfo
*
86 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
88 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
89 return pCreateInfo
->pMultisampleState
;
93 static const VkPipelineTessellationStateCreateInfo
*
94 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
96 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
97 if (pCreateInfo
->pStages
[i
].stage
== VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
||
98 pCreateInfo
->pStages
[i
].stage
== VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
) {
99 return pCreateInfo
->pTessellationState
;
105 static const VkPipelineDepthStencilStateCreateInfo
*
106 radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
108 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
109 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
111 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
112 subpass
->depth_stencil_attachment
)
113 return pCreateInfo
->pDepthStencilState
;
117 static const VkPipelineColorBlendStateCreateInfo
*
118 radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
120 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
121 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
123 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
124 subpass
->has_color_att
)
125 return pCreateInfo
->pColorBlendState
;
129 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
)
131 struct radv_shader_variant
*variant
= NULL
;
132 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
133 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
134 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
135 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
136 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
137 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
140 return variant
->info
.is_ngg
;
143 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline
*pipeline
)
145 assert(radv_pipeline_has_ngg(pipeline
));
147 struct radv_shader_variant
*variant
= NULL
;
148 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
149 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
150 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
151 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
152 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
153 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
156 return variant
->info
.is_ngg_passthrough
;
159 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
)
161 if (!radv_pipeline_has_gs(pipeline
))
164 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
165 * On GFX10, it might be required in rare cases if it's not possible to
168 if (radv_pipeline_has_ngg(pipeline
))
171 assert(pipeline
->gs_copy_shader
);
176 radv_pipeline_destroy(struct radv_device
*device
,
177 struct radv_pipeline
*pipeline
,
178 const VkAllocationCallbacks
* allocator
)
180 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
181 if (pipeline
->shaders
[i
])
182 radv_shader_variant_destroy(device
, pipeline
->shaders
[i
]);
184 if (pipeline
->gs_copy_shader
)
185 radv_shader_variant_destroy(device
, pipeline
->gs_copy_shader
);
188 free(pipeline
->cs
.buf
);
190 vk_object_base_finish(&pipeline
->base
);
191 vk_free2(&device
->vk
.alloc
, allocator
, pipeline
);
194 void radv_DestroyPipeline(
196 VkPipeline _pipeline
,
197 const VkAllocationCallbacks
* pAllocator
)
199 RADV_FROM_HANDLE(radv_device
, device
, _device
);
200 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
205 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
208 static uint32_t get_hash_flags(struct radv_device
*device
)
210 uint32_t hash_flags
= 0;
212 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_NGG
)
213 hash_flags
|= RADV_HASH_SHADER_NO_NGG
;
214 if (device
->physical_device
->cs_wave_size
== 32)
215 hash_flags
|= RADV_HASH_SHADER_CS_WAVE32
;
216 if (device
->physical_device
->ps_wave_size
== 32)
217 hash_flags
|= RADV_HASH_SHADER_PS_WAVE32
;
218 if (device
->physical_device
->ge_wave_size
== 32)
219 hash_flags
|= RADV_HASH_SHADER_GE_WAVE32
;
220 if (device
->physical_device
->use_llvm
)
221 hash_flags
|= RADV_HASH_SHADER_LLVM
;
226 radv_pipeline_scratch_init(struct radv_device
*device
,
227 struct radv_pipeline
*pipeline
)
229 unsigned scratch_bytes_per_wave
= 0;
230 unsigned max_waves
= 0;
231 unsigned min_waves
= 1;
233 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
234 if (pipeline
->shaders
[i
] &&
235 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
) {
236 unsigned max_stage_waves
= device
->scratch_waves
;
238 scratch_bytes_per_wave
= MAX2(scratch_bytes_per_wave
,
239 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
);
241 max_stage_waves
= MIN2(max_stage_waves
,
242 4 * device
->physical_device
->rad_info
.num_good_compute_units
*
243 (256 / pipeline
->shaders
[i
]->config
.num_vgprs
));
244 max_waves
= MAX2(max_waves
, max_stage_waves
);
248 if (pipeline
->shaders
[MESA_SHADER_COMPUTE
]) {
249 unsigned group_size
= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[0] *
250 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[1] *
251 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[2];
252 min_waves
= MAX2(min_waves
, round_up_u32(group_size
, 64));
255 pipeline
->scratch_bytes_per_wave
= scratch_bytes_per_wave
;
256 pipeline
->max_waves
= max_waves
;
260 static uint32_t si_translate_blend_logic_op(VkLogicOp op
)
263 case VK_LOGIC_OP_CLEAR
:
264 return V_028808_ROP3_CLEAR
;
265 case VK_LOGIC_OP_AND
:
266 return V_028808_ROP3_AND
;
267 case VK_LOGIC_OP_AND_REVERSE
:
268 return V_028808_ROP3_AND_REVERSE
;
269 case VK_LOGIC_OP_COPY
:
270 return V_028808_ROP3_COPY
;
271 case VK_LOGIC_OP_AND_INVERTED
:
272 return V_028808_ROP3_AND_INVERTED
;
273 case VK_LOGIC_OP_NO_OP
:
274 return V_028808_ROP3_NO_OP
;
275 case VK_LOGIC_OP_XOR
:
276 return V_028808_ROP3_XOR
;
278 return V_028808_ROP3_OR
;
279 case VK_LOGIC_OP_NOR
:
280 return V_028808_ROP3_NOR
;
281 case VK_LOGIC_OP_EQUIVALENT
:
282 return V_028808_ROP3_EQUIVALENT
;
283 case VK_LOGIC_OP_INVERT
:
284 return V_028808_ROP3_INVERT
;
285 case VK_LOGIC_OP_OR_REVERSE
:
286 return V_028808_ROP3_OR_REVERSE
;
287 case VK_LOGIC_OP_COPY_INVERTED
:
288 return V_028808_ROP3_COPY_INVERTED
;
289 case VK_LOGIC_OP_OR_INVERTED
:
290 return V_028808_ROP3_OR_INVERTED
;
291 case VK_LOGIC_OP_NAND
:
292 return V_028808_ROP3_NAND
;
293 case VK_LOGIC_OP_SET
:
294 return V_028808_ROP3_SET
;
296 unreachable("Unhandled logic op");
301 static uint32_t si_translate_blend_function(VkBlendOp op
)
304 case VK_BLEND_OP_ADD
:
305 return V_028780_COMB_DST_PLUS_SRC
;
306 case VK_BLEND_OP_SUBTRACT
:
307 return V_028780_COMB_SRC_MINUS_DST
;
308 case VK_BLEND_OP_REVERSE_SUBTRACT
:
309 return V_028780_COMB_DST_MINUS_SRC
;
310 case VK_BLEND_OP_MIN
:
311 return V_028780_COMB_MIN_DST_SRC
;
312 case VK_BLEND_OP_MAX
:
313 return V_028780_COMB_MAX_DST_SRC
;
319 static uint32_t si_translate_blend_factor(VkBlendFactor factor
)
322 case VK_BLEND_FACTOR_ZERO
:
323 return V_028780_BLEND_ZERO
;
324 case VK_BLEND_FACTOR_ONE
:
325 return V_028780_BLEND_ONE
;
326 case VK_BLEND_FACTOR_SRC_COLOR
:
327 return V_028780_BLEND_SRC_COLOR
;
328 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
329 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
330 case VK_BLEND_FACTOR_DST_COLOR
:
331 return V_028780_BLEND_DST_COLOR
;
332 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
333 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
334 case VK_BLEND_FACTOR_SRC_ALPHA
:
335 return V_028780_BLEND_SRC_ALPHA
;
336 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
337 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
338 case VK_BLEND_FACTOR_DST_ALPHA
:
339 return V_028780_BLEND_DST_ALPHA
;
340 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
341 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
342 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
343 return V_028780_BLEND_CONSTANT_COLOR
;
344 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
345 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
346 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
347 return V_028780_BLEND_CONSTANT_ALPHA
;
348 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
349 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
350 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
351 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
352 case VK_BLEND_FACTOR_SRC1_COLOR
:
353 return V_028780_BLEND_SRC1_COLOR
;
354 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
355 return V_028780_BLEND_INV_SRC1_COLOR
;
356 case VK_BLEND_FACTOR_SRC1_ALPHA
:
357 return V_028780_BLEND_SRC1_ALPHA
;
358 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
359 return V_028780_BLEND_INV_SRC1_ALPHA
;
365 static uint32_t si_translate_blend_opt_function(VkBlendOp op
)
368 case VK_BLEND_OP_ADD
:
369 return V_028760_OPT_COMB_ADD
;
370 case VK_BLEND_OP_SUBTRACT
:
371 return V_028760_OPT_COMB_SUBTRACT
;
372 case VK_BLEND_OP_REVERSE_SUBTRACT
:
373 return V_028760_OPT_COMB_REVSUBTRACT
;
374 case VK_BLEND_OP_MIN
:
375 return V_028760_OPT_COMB_MIN
;
376 case VK_BLEND_OP_MAX
:
377 return V_028760_OPT_COMB_MAX
;
379 return V_028760_OPT_COMB_BLEND_DISABLED
;
383 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor
, bool is_alpha
)
386 case VK_BLEND_FACTOR_ZERO
:
387 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
388 case VK_BLEND_FACTOR_ONE
:
389 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
390 case VK_BLEND_FACTOR_SRC_COLOR
:
391 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
392 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
393 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
394 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
395 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
396 case VK_BLEND_FACTOR_SRC_ALPHA
:
397 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
398 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
399 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
400 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
401 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
402 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
404 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
409 * Get rid of DST in the blend factors by commuting the operands:
410 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
412 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
413 unsigned *dst_factor
, unsigned expected_dst
,
414 unsigned replacement_src
)
416 if (*src_factor
== expected_dst
&&
417 *dst_factor
== VK_BLEND_FACTOR_ZERO
) {
418 *src_factor
= VK_BLEND_FACTOR_ZERO
;
419 *dst_factor
= replacement_src
;
421 /* Commuting the operands requires reversing subtractions. */
422 if (*func
== VK_BLEND_OP_SUBTRACT
)
423 *func
= VK_BLEND_OP_REVERSE_SUBTRACT
;
424 else if (*func
== VK_BLEND_OP_REVERSE_SUBTRACT
)
425 *func
= VK_BLEND_OP_SUBTRACT
;
429 static bool si_blend_factor_uses_dst(unsigned factor
)
431 return factor
== VK_BLEND_FACTOR_DST_COLOR
||
432 factor
== VK_BLEND_FACTOR_DST_ALPHA
||
433 factor
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
434 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
||
435 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
;
438 static bool is_dual_src(VkBlendFactor factor
)
441 case VK_BLEND_FACTOR_SRC1_COLOR
:
442 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
443 case VK_BLEND_FACTOR_SRC1_ALPHA
:
444 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
451 static unsigned radv_choose_spi_color_format(VkFormat vk_format
,
453 bool blend_need_alpha
)
455 const struct vk_format_description
*desc
= vk_format_description(vk_format
);
456 struct ac_spi_color_formats formats
= {};
457 unsigned format
, ntype
, swap
;
459 format
= radv_translate_colorformat(vk_format
);
460 ntype
= radv_translate_color_numformat(vk_format
, desc
,
461 vk_format_get_first_non_void_channel(vk_format
));
462 swap
= radv_translate_colorswap(vk_format
, false);
464 ac_choose_spi_color_formats(format
, swap
, ntype
, false, &formats
);
466 if (blend_enable
&& blend_need_alpha
)
467 return formats
.blend_alpha
;
468 else if(blend_need_alpha
)
469 return formats
.alpha
;
470 else if(blend_enable
)
471 return formats
.blend
;
473 return formats
.normal
;
477 format_is_int8(VkFormat format
)
479 const struct vk_format_description
*desc
= vk_format_description(format
);
480 int channel
= vk_format_get_first_non_void_channel(format
);
482 return channel
>= 0 && desc
->channel
[channel
].pure_integer
&&
483 desc
->channel
[channel
].size
== 8;
487 format_is_int10(VkFormat format
)
489 const struct vk_format_description
*desc
= vk_format_description(format
);
491 if (desc
->nr_channels
!= 4)
493 for (unsigned i
= 0; i
< 4; i
++) {
494 if (desc
->channel
[i
].pure_integer
&& desc
->channel
[i
].size
== 10)
501 radv_pipeline_compute_spi_color_formats(struct radv_pipeline
*pipeline
,
502 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
503 struct radv_blend_state
*blend
)
505 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
506 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
507 unsigned col_format
= 0, is_int8
= 0, is_int10
= 0;
508 unsigned num_targets
;
510 for (unsigned i
= 0; i
< (blend
->single_cb_enable
? 1 : subpass
->color_count
); ++i
) {
513 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
||
514 !(blend
->cb_target_mask
& (0xfu
<< (i
* 4)))) {
515 cf
= V_028714_SPI_SHADER_ZERO
;
517 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
519 blend
->blend_enable_4bit
& (0xfu
<< (i
* 4));
521 cf
= radv_choose_spi_color_format(attachment
->format
,
523 blend
->need_src_alpha
& (1 << i
));
525 if (format_is_int8(attachment
->format
))
527 if (format_is_int10(attachment
->format
))
531 col_format
|= cf
<< (4 * i
);
534 if (!(col_format
& 0xf) && blend
->need_src_alpha
& (1 << 0)) {
535 /* When a subpass doesn't have any color attachments, write the
536 * alpha channel of MRT0 when alpha coverage is enabled because
537 * the depth attachment needs it.
539 col_format
|= V_028714_SPI_SHADER_32_AR
;
542 /* If the i-th target format is set, all previous target formats must
543 * be non-zero to avoid hangs.
545 num_targets
= (util_last_bit(col_format
) + 3) / 4;
546 for (unsigned i
= 0; i
< num_targets
; i
++) {
547 if (!(col_format
& (0xf << (i
* 4)))) {
548 col_format
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
552 /* The output for dual source blending should have the same format as
555 if (blend
->mrt0_is_dual_src
)
556 col_format
|= (col_format
& 0xf) << 4;
558 blend
->spi_shader_col_format
= col_format
;
559 blend
->col_format_is_int8
= is_int8
;
560 blend
->col_format_is_int10
= is_int10
;
564 * Ordered so that for each i,
565 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
567 const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
] = {
568 VK_FORMAT_R32_SFLOAT
,
569 VK_FORMAT_R32G32_SFLOAT
,
570 VK_FORMAT_R8G8B8A8_UNORM
,
571 VK_FORMAT_R16G16B16A16_UNORM
,
572 VK_FORMAT_R16G16B16A16_SNORM
,
573 VK_FORMAT_R16G16B16A16_UINT
,
574 VK_FORMAT_R16G16B16A16_SINT
,
575 VK_FORMAT_R32G32B32A32_SFLOAT
,
576 VK_FORMAT_R8G8B8A8_UINT
,
577 VK_FORMAT_R8G8B8A8_SINT
,
578 VK_FORMAT_A2R10G10B10_UINT_PACK32
,
579 VK_FORMAT_A2R10G10B10_SINT_PACK32
,
582 unsigned radv_format_meta_fs_key(VkFormat format
)
584 unsigned col_format
= radv_choose_spi_color_format(format
, false, false);
586 assert(col_format
!= V_028714_SPI_SHADER_32_AR
);
587 if (col_format
>= V_028714_SPI_SHADER_32_AR
)
588 --col_format
; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
590 --col_format
; /* Skip V_028714_SPI_SHADER_ZERO */
591 bool is_int8
= format_is_int8(format
);
592 bool is_int10
= format_is_int10(format
);
594 return col_format
+ (is_int8
? 3 : is_int10
? 5 : 0);
598 radv_blend_check_commutativity(struct radv_blend_state
*blend
,
599 VkBlendOp op
, VkBlendFactor src
,
600 VkBlendFactor dst
, unsigned chanmask
)
602 /* Src factor is allowed when it does not depend on Dst. */
603 static const uint32_t src_allowed
=
604 (1u << VK_BLEND_FACTOR_ONE
) |
605 (1u << VK_BLEND_FACTOR_SRC_COLOR
) |
606 (1u << VK_BLEND_FACTOR_SRC_ALPHA
) |
607 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
) |
608 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR
) |
609 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA
) |
610 (1u << VK_BLEND_FACTOR_SRC1_COLOR
) |
611 (1u << VK_BLEND_FACTOR_SRC1_ALPHA
) |
612 (1u << VK_BLEND_FACTOR_ZERO
) |
613 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
) |
614 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
) |
615 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
) |
616 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
) |
617 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
) |
618 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
);
620 if (dst
== VK_BLEND_FACTOR_ONE
&&
621 (src_allowed
& (1u << src
))) {
622 /* Addition is commutative, but floating point addition isn't
623 * associative: subtle changes can be introduced via different
624 * rounding. Be conservative, only enable for min and max.
626 if (op
== VK_BLEND_OP_MAX
|| op
== VK_BLEND_OP_MIN
)
627 blend
->commutative_4bit
|= chanmask
;
631 static struct radv_blend_state
632 radv_pipeline_init_blend_state(struct radv_pipeline
*pipeline
,
633 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
634 const struct radv_graphics_pipeline_create_info
*extra
)
636 const VkPipelineColorBlendStateCreateInfo
*vkblend
= radv_pipeline_get_color_blend_state(pCreateInfo
);
637 const VkPipelineMultisampleStateCreateInfo
*vkms
= radv_pipeline_get_multisample_state(pCreateInfo
);
638 struct radv_blend_state blend
= {0};
639 unsigned mode
= V_028808_CB_NORMAL
;
642 if (extra
&& extra
->custom_blend_mode
) {
643 blend
.single_cb_enable
= true;
644 mode
= extra
->custom_blend_mode
;
647 blend
.cb_color_control
= 0;
649 if (vkblend
->logicOpEnable
)
650 blend
.cb_color_control
|= S_028808_ROP3(si_translate_blend_logic_op(vkblend
->logicOp
));
652 blend
.cb_color_control
|= S_028808_ROP3(V_028808_ROP3_COPY
);
655 blend
.db_alpha_to_mask
= S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
656 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
657 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
658 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
659 S_028B70_OFFSET_ROUND(1);
661 if (vkms
&& vkms
->alphaToCoverageEnable
) {
662 blend
.db_alpha_to_mask
|= S_028B70_ALPHA_TO_MASK_ENABLE(1);
663 blend
.need_src_alpha
|= 0x1;
666 blend
.cb_target_mask
= 0;
668 for (i
= 0; i
< vkblend
->attachmentCount
; i
++) {
669 const VkPipelineColorBlendAttachmentState
*att
= &vkblend
->pAttachments
[i
];
670 unsigned blend_cntl
= 0;
671 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
672 VkBlendOp eqRGB
= att
->colorBlendOp
;
673 VkBlendFactor srcRGB
= att
->srcColorBlendFactor
;
674 VkBlendFactor dstRGB
= att
->dstColorBlendFactor
;
675 VkBlendOp eqA
= att
->alphaBlendOp
;
676 VkBlendFactor srcA
= att
->srcAlphaBlendFactor
;
677 VkBlendFactor dstA
= att
->dstAlphaBlendFactor
;
679 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
681 if (!att
->colorWriteMask
)
684 blend
.cb_target_mask
|= (unsigned)att
->colorWriteMask
<< (4 * i
);
685 blend
.cb_target_enabled_4bit
|= 0xf << (4 * i
);
686 if (!att
->blendEnable
) {
687 blend
.cb_blend_control
[i
] = blend_cntl
;
691 if (is_dual_src(srcRGB
) || is_dual_src(dstRGB
) || is_dual_src(srcA
) || is_dual_src(dstA
))
693 blend
.mrt0_is_dual_src
= true;
695 if (eqRGB
== VK_BLEND_OP_MIN
|| eqRGB
== VK_BLEND_OP_MAX
) {
696 srcRGB
= VK_BLEND_FACTOR_ONE
;
697 dstRGB
= VK_BLEND_FACTOR_ONE
;
699 if (eqA
== VK_BLEND_OP_MIN
|| eqA
== VK_BLEND_OP_MAX
) {
700 srcA
= VK_BLEND_FACTOR_ONE
;
701 dstA
= VK_BLEND_FACTOR_ONE
;
704 radv_blend_check_commutativity(&blend
, eqRGB
, srcRGB
, dstRGB
,
706 radv_blend_check_commutativity(&blend
, eqA
, srcA
, dstA
,
709 /* Blending optimizations for RB+.
710 * These transformations don't change the behavior.
712 * First, get rid of DST in the blend factors:
713 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
715 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
716 VK_BLEND_FACTOR_DST_COLOR
,
717 VK_BLEND_FACTOR_SRC_COLOR
);
719 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
720 VK_BLEND_FACTOR_DST_COLOR
,
721 VK_BLEND_FACTOR_SRC_COLOR
);
723 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
724 VK_BLEND_FACTOR_DST_ALPHA
,
725 VK_BLEND_FACTOR_SRC_ALPHA
);
727 /* Look up the ideal settings from tables. */
728 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
729 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
730 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
731 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
733 /* Handle interdependencies. */
734 if (si_blend_factor_uses_dst(srcRGB
))
735 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
736 if (si_blend_factor_uses_dst(srcA
))
737 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
739 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
&&
740 (dstRGB
== VK_BLEND_FACTOR_ZERO
||
741 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
742 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
))
743 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
745 /* Set the final value. */
746 blend
.sx_mrt_blend_opt
[i
] =
747 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
748 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
749 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
750 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
751 S_028760_ALPHA_DST_OPT(dstA_opt
) |
752 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
753 blend_cntl
|= S_028780_ENABLE(1);
755 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
756 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
757 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
758 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
759 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
760 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
761 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
762 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
764 blend
.cb_blend_control
[i
] = blend_cntl
;
766 blend
.blend_enable_4bit
|= 0xfu
<< (i
* 4);
768 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
769 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
770 srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
771 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
772 srcRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
||
773 dstRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
)
774 blend
.need_src_alpha
|= 1 << i
;
776 for (i
= vkblend
->attachmentCount
; i
< 8; i
++) {
777 blend
.cb_blend_control
[i
] = 0;
778 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
782 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
783 /* Disable RB+ blend optimizations for dual source blending. */
784 if (blend
.mrt0_is_dual_src
) {
785 for (i
= 0; i
< 8; i
++) {
786 blend
.sx_mrt_blend_opt
[i
] =
787 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
788 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
792 /* RB+ doesn't work with dual source blending, logic op and
795 if (blend
.mrt0_is_dual_src
||
796 (vkblend
&& vkblend
->logicOpEnable
) ||
797 mode
== V_028808_CB_RESOLVE
)
798 blend
.cb_color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
801 if (blend
.cb_target_mask
)
802 blend
.cb_color_control
|= S_028808_MODE(mode
);
804 blend
.cb_color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
806 radv_pipeline_compute_spi_color_formats(pipeline
, pCreateInfo
, &blend
);
810 static uint32_t si_translate_fill(VkPolygonMode func
)
813 case VK_POLYGON_MODE_FILL
:
814 return V_028814_X_DRAW_TRIANGLES
;
815 case VK_POLYGON_MODE_LINE
:
816 return V_028814_X_DRAW_LINES
;
817 case VK_POLYGON_MODE_POINT
:
818 return V_028814_X_DRAW_POINTS
;
821 return V_028814_X_DRAW_POINTS
;
825 static uint8_t radv_pipeline_get_ps_iter_samples(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
827 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
828 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
829 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
830 uint32_t ps_iter_samples
= 1;
831 uint32_t num_samples
;
833 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
835 * "If the VK_AMD_mixed_attachment_samples extension is enabled and the
836 * subpass uses color attachments, totalSamples is the number of
837 * samples of the color attachments. Otherwise, totalSamples is the
838 * value of VkPipelineMultisampleStateCreateInfo::rasterizationSamples
839 * specified at pipeline creation time."
841 if (subpass
->has_color_att
) {
842 num_samples
= subpass
->color_sample_count
;
844 num_samples
= vkms
->rasterizationSamples
;
847 if (vkms
->sampleShadingEnable
) {
848 ps_iter_samples
= ceilf(vkms
->minSampleShading
* num_samples
);
849 ps_iter_samples
= util_next_power_of_two(ps_iter_samples
);
851 return ps_iter_samples
;
855 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
857 return pCreateInfo
->depthTestEnable
&&
858 pCreateInfo
->depthWriteEnable
&&
859 pCreateInfo
->depthCompareOp
!= VK_COMPARE_OP_NEVER
;
863 radv_writes_stencil(const VkStencilOpState
*state
)
865 return state
->writeMask
&&
866 (state
->failOp
!= VK_STENCIL_OP_KEEP
||
867 state
->passOp
!= VK_STENCIL_OP_KEEP
||
868 state
->depthFailOp
!= VK_STENCIL_OP_KEEP
);
872 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
874 return pCreateInfo
->stencilTestEnable
&&
875 (radv_writes_stencil(&pCreateInfo
->front
) ||
876 radv_writes_stencil(&pCreateInfo
->back
));
880 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
882 return radv_is_depth_write_enabled(pCreateInfo
) ||
883 radv_is_stencil_write_enabled(pCreateInfo
);
887 radv_order_invariant_stencil_op(VkStencilOp op
)
889 /* REPLACE is normally order invariant, except when the stencil
890 * reference value is written by the fragment shader. Tracking this
891 * interaction does not seem worth the effort, so be conservative.
893 return op
!= VK_STENCIL_OP_INCREMENT_AND_CLAMP
&&
894 op
!= VK_STENCIL_OP_DECREMENT_AND_CLAMP
&&
895 op
!= VK_STENCIL_OP_REPLACE
;
899 radv_order_invariant_stencil_state(const VkStencilOpState
*state
)
901 /* Compute whether, assuming Z writes are disabled, this stencil state
902 * is order invariant in the sense that the set of passing fragments as
903 * well as the final stencil buffer result does not depend on the order
906 return !state
->writeMask
||
907 /* The following assumes that Z writes are disabled. */
908 (state
->compareOp
== VK_COMPARE_OP_ALWAYS
&&
909 radv_order_invariant_stencil_op(state
->passOp
) &&
910 radv_order_invariant_stencil_op(state
->depthFailOp
)) ||
911 (state
->compareOp
== VK_COMPARE_OP_NEVER
&&
912 radv_order_invariant_stencil_op(state
->failOp
));
916 radv_pipeline_has_dynamic_ds_states(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
918 VkDynamicState ds_states
[] = {
919 VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT
,
920 VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT
,
921 VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT
,
922 VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT
,
923 VK_DYNAMIC_STATE_STENCIL_OP_EXT
,
926 if (pCreateInfo
->pDynamicState
) {
927 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
928 for (uint32_t i
= 0; i
< count
; i
++) {
929 for (uint32_t j
= 0; j
< ARRAY_SIZE(ds_states
); j
++) {
930 if (pCreateInfo
->pDynamicState
->pDynamicStates
[i
] == ds_states
[j
])
940 radv_pipeline_out_of_order_rast(struct radv_pipeline
*pipeline
,
941 struct radv_blend_state
*blend
,
942 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
944 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
945 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
946 const VkPipelineDepthStencilStateCreateInfo
*vkds
= radv_pipeline_get_depth_stencil_state(pCreateInfo
);
947 const VkPipelineColorBlendStateCreateInfo
*vkblend
= radv_pipeline_get_color_blend_state(pCreateInfo
);
948 unsigned colormask
= blend
->cb_target_enabled_4bit
;
950 if (!pipeline
->device
->physical_device
->out_of_order_rast_allowed
)
953 /* Be conservative if a logic operation is enabled with color buffers. */
954 if (colormask
&& vkblend
&& vkblend
->logicOpEnable
)
957 /* Be conservative if an extended dynamic depth/stencil state is
958 * enabled because the driver can't update out-of-order rasterization
961 if (radv_pipeline_has_dynamic_ds_states(pCreateInfo
))
964 /* Default depth/stencil invariance when no attachment is bound. */
965 struct radv_dsa_order_invariance dsa_order_invariant
= {
966 .zs
= true, .pass_set
= true
970 struct radv_render_pass_attachment
*attachment
=
971 pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
972 bool has_stencil
= vk_format_is_stencil(attachment
->format
);
973 struct radv_dsa_order_invariance order_invariance
[2];
974 struct radv_shader_variant
*ps
=
975 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
977 /* Compute depth/stencil order invariance in order to know if
978 * it's safe to enable out-of-order.
980 bool zfunc_is_ordered
=
981 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
||
982 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS
||
983 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS_OR_EQUAL
||
984 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER
||
985 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER_OR_EQUAL
;
987 bool nozwrite_and_order_invariant_stencil
=
988 !radv_is_ds_write_enabled(vkds
) ||
989 (!radv_is_depth_write_enabled(vkds
) &&
990 radv_order_invariant_stencil_state(&vkds
->front
) &&
991 radv_order_invariant_stencil_state(&vkds
->back
));
993 order_invariance
[1].zs
=
994 nozwrite_and_order_invariant_stencil
||
995 (!radv_is_stencil_write_enabled(vkds
) &&
997 order_invariance
[0].zs
=
998 !radv_is_depth_write_enabled(vkds
) || zfunc_is_ordered
;
1000 order_invariance
[1].pass_set
=
1001 nozwrite_and_order_invariant_stencil
||
1002 (!radv_is_stencil_write_enabled(vkds
) &&
1003 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1004 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
));
1005 order_invariance
[0].pass_set
=
1006 !radv_is_depth_write_enabled(vkds
) ||
1007 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1008 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
);
1010 dsa_order_invariant
= order_invariance
[has_stencil
];
1011 if (!dsa_order_invariant
.zs
)
1014 /* The set of PS invocations is always order invariant,
1015 * except when early Z/S tests are requested.
1018 ps
->info
.ps
.writes_memory
&&
1019 ps
->info
.ps
.early_fragment_test
&&
1020 !dsa_order_invariant
.pass_set
)
1023 /* Determine if out-of-order rasterization should be disabled
1024 * when occlusion queries are used.
1026 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
=
1027 !dsa_order_invariant
.pass_set
;
1030 /* No color buffers are enabled for writing. */
1034 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
1037 /* Only commutative blending. */
1038 if (blendmask
& ~blend
->commutative_4bit
)
1041 if (!dsa_order_invariant
.pass_set
)
1045 if (colormask
& ~blendmask
)
1051 static const VkConservativeRasterizationModeEXT
1052 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo
*pCreateInfo
)
1054 const VkPipelineRasterizationConservativeStateCreateInfoEXT
*conservative_raster
=
1055 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT
);
1057 if (!conservative_raster
)
1058 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
;
1059 return conservative_raster
->conservativeRasterizationMode
;
1063 radv_pipeline_init_multisample_state(struct radv_pipeline
*pipeline
,
1064 struct radv_blend_state
*blend
,
1065 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1067 const VkPipelineMultisampleStateCreateInfo
*vkms
= radv_pipeline_get_multisample_state(pCreateInfo
);
1068 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
1069 unsigned num_tile_pipes
= pipeline
->device
->physical_device
->rad_info
.num_tile_pipes
;
1070 const VkConservativeRasterizationModeEXT mode
=
1071 radv_get_conservative_raster_mode(pCreateInfo
->pRasterizationState
);
1072 bool out_of_order_rast
= false;
1073 int ps_iter_samples
= 1;
1074 uint32_t mask
= 0xffff;
1077 ms
->num_samples
= vkms
->rasterizationSamples
;
1079 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1081 * "Sample shading is enabled for a graphics pipeline:
1083 * - If the interface of the fragment shader entry point of the
1084 * graphics pipeline includes an input variable decorated
1085 * with SampleId or SamplePosition. In this case
1086 * minSampleShadingFactor takes the value 1.0.
1087 * - Else if the sampleShadingEnable member of the
1088 * VkPipelineMultisampleStateCreateInfo structure specified
1089 * when creating the graphics pipeline is set to VK_TRUE. In
1090 * this case minSampleShadingFactor takes the value of
1091 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1093 * Otherwise, sample shading is considered disabled."
1095 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.force_persample
) {
1096 ps_iter_samples
= ms
->num_samples
;
1098 ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
);
1101 ms
->num_samples
= 1;
1104 const struct VkPipelineRasterizationStateRasterizationOrderAMD
*raster_order
=
1105 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD
);
1106 if (raster_order
&& raster_order
->rasterizationOrder
== VK_RASTERIZATION_ORDER_RELAXED_AMD
) {
1107 /* Out-of-order rasterization is explicitly enabled by the
1110 out_of_order_rast
= true;
1112 /* Determine if the driver can enable out-of-order
1113 * rasterization internally.
1116 radv_pipeline_out_of_order_rast(pipeline
, blend
, pCreateInfo
);
1119 ms
->pa_sc_aa_config
= 0;
1120 ms
->db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1121 S_028804_INCOHERENT_EQAA_READS(1) |
1122 S_028804_INTERPOLATE_COMP_Z(1) |
1123 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1125 /* Adjust MSAA state if conservative rasterization is enabled. */
1126 if (mode
!= VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
) {
1127 ms
->pa_sc_aa_config
|= S_028BE0_AA_MASK_CENTROID_DTMN(1);
1129 ms
->db_eqaa
|= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
1130 S_028804_OVERRASTERIZATION_AMOUNT(4);
1133 ms
->pa_sc_mode_cntl_1
=
1134 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1135 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
1136 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
1137 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1139 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1140 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1141 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1142 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1143 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1144 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1145 ms
->pa_sc_mode_cntl_0
= S_028A48_ALTERNATE_RBS_PER_TILE(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
1146 S_028A48_VPORT_SCISSOR_ENABLE(1);
1148 const VkPipelineRasterizationLineStateCreateInfoEXT
*rast_line
=
1149 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1150 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1152 ms
->pa_sc_mode_cntl_0
|= S_028A48_LINE_STIPPLE_ENABLE(rast_line
->stippledLineEnable
);
1153 if (rast_line
->lineRasterizationMode
== VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT
) {
1154 /* From the Vulkan spec 1.1.129:
1156 * "When VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT lines
1157 * are being rasterized, sample locations may all be
1158 * treated as being at the pixel center (this may
1159 * affect attribute and depth interpolation)."
1161 ms
->num_samples
= 1;
1165 if (ms
->num_samples
> 1) {
1166 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1167 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1168 uint32_t z_samples
= subpass
->depth_stencil_attachment
? subpass
->depth_sample_count
: ms
->num_samples
;
1169 unsigned log_samples
= util_logbase2(ms
->num_samples
);
1170 unsigned log_z_samples
= util_logbase2(z_samples
);
1171 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
1172 ms
->pa_sc_mode_cntl_0
|= S_028A48_MSAA_ENABLE(1);
1173 ms
->db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples
) |
1174 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
1175 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
1176 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
1177 ms
->pa_sc_aa_config
|= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
1178 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples
)) |
1179 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
) | /* CM_R_028BE0_PA_SC_AA_CONFIG */
1180 S_028BE0_COVERED_CENTROID_IS_CENTER_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
);
1181 ms
->pa_sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
1182 if (ps_iter_samples
> 1)
1183 pipeline
->graphics
.spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1186 if (vkms
&& vkms
->pSampleMask
) {
1187 mask
= vkms
->pSampleMask
[0] & 0xffff;
1190 ms
->pa_sc_aa_mask
[0] = mask
| (mask
<< 16);
1191 ms
->pa_sc_aa_mask
[1] = mask
| (mask
<< 16);
1195 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology
)
1198 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1199 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1200 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1201 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1202 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1204 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1205 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1206 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1207 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1208 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1209 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1212 unreachable("unhandled primitive type");
1217 si_conv_gl_prim_to_gs_out(unsigned gl_prim
)
1220 case 0: /* GL_POINTS */
1221 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1222 case 1: /* GL_LINES */
1223 case 3: /* GL_LINE_STRIP */
1224 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1225 case 0x8E7A: /* GL_ISOLINES */
1226 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1228 case 4: /* GL_TRIANGLES */
1229 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1230 case 5: /* GL_TRIANGLE_STRIP */
1231 case 7: /* GL_QUADS */
1232 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1240 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology
)
1243 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1244 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1245 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1246 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1247 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1248 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1249 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1250 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1251 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1252 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1253 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1254 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1255 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1256 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1263 static unsigned radv_dynamic_state_mask(VkDynamicState state
)
1266 case VK_DYNAMIC_STATE_VIEWPORT
:
1267 case VK_DYNAMIC_STATE_VIEWPORT_WITH_COUNT_EXT
:
1268 return RADV_DYNAMIC_VIEWPORT
;
1269 case VK_DYNAMIC_STATE_SCISSOR
:
1270 case VK_DYNAMIC_STATE_SCISSOR_WITH_COUNT_EXT
:
1271 return RADV_DYNAMIC_SCISSOR
;
1272 case VK_DYNAMIC_STATE_LINE_WIDTH
:
1273 return RADV_DYNAMIC_LINE_WIDTH
;
1274 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
1275 return RADV_DYNAMIC_DEPTH_BIAS
;
1276 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
1277 return RADV_DYNAMIC_BLEND_CONSTANTS
;
1278 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
1279 return RADV_DYNAMIC_DEPTH_BOUNDS
;
1280 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
1281 return RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
1282 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
1283 return RADV_DYNAMIC_STENCIL_WRITE_MASK
;
1284 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
1285 return RADV_DYNAMIC_STENCIL_REFERENCE
;
1286 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT
:
1287 return RADV_DYNAMIC_DISCARD_RECTANGLE
;
1288 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT
:
1289 return RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1290 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
1291 return RADV_DYNAMIC_LINE_STIPPLE
;
1292 case VK_DYNAMIC_STATE_CULL_MODE_EXT
:
1293 return RADV_DYNAMIC_CULL_MODE
;
1294 case VK_DYNAMIC_STATE_FRONT_FACE_EXT
:
1295 return RADV_DYNAMIC_FRONT_FACE
;
1296 case VK_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY_EXT
:
1297 return RADV_DYNAMIC_PRIMITIVE_TOPOLOGY
;
1298 case VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT
:
1299 return RADV_DYNAMIC_DEPTH_TEST_ENABLE
;
1300 case VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT
:
1301 return RADV_DYNAMIC_DEPTH_WRITE_ENABLE
;
1302 case VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT
:
1303 return RADV_DYNAMIC_DEPTH_COMPARE_OP
;
1304 case VK_DYNAMIC_STATE_DEPTH_BOUNDS_TEST_ENABLE_EXT
:
1305 return RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE
;
1306 case VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT
:
1307 return RADV_DYNAMIC_STENCIL_TEST_ENABLE
;
1308 case VK_DYNAMIC_STATE_STENCIL_OP_EXT
:
1309 return RADV_DYNAMIC_STENCIL_OP
;
1310 case VK_DYNAMIC_STATE_VERTEX_INPUT_BINDING_STRIDE_EXT
:
1311 return RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE
;
1313 unreachable("Unhandled dynamic state");
1317 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1319 uint32_t states
= RADV_DYNAMIC_ALL
;
1321 /* If rasterization is disabled we do not care about any of the
1322 * dynamic states, since they are all rasterization related only,
1323 * except primitive topology and vertex binding stride.
1325 if (pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
1326 return RADV_DYNAMIC_PRIMITIVE_TOPOLOGY
|
1327 RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE
;
1329 if (!pCreateInfo
->pRasterizationState
->depthBiasEnable
)
1330 states
&= ~RADV_DYNAMIC_DEPTH_BIAS
;
1332 if (!pCreateInfo
->pDepthStencilState
||
1333 !pCreateInfo
->pDepthStencilState
->depthBoundsTestEnable
)
1334 states
&= ~RADV_DYNAMIC_DEPTH_BOUNDS
;
1336 if (!pCreateInfo
->pDepthStencilState
||
1337 !pCreateInfo
->pDepthStencilState
->stencilTestEnable
)
1338 states
&= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK
|
1339 RADV_DYNAMIC_STENCIL_WRITE_MASK
|
1340 RADV_DYNAMIC_STENCIL_REFERENCE
);
1342 if (!vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
))
1343 states
&= ~RADV_DYNAMIC_DISCARD_RECTANGLE
;
1345 if (!pCreateInfo
->pMultisampleState
||
1346 !vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1347 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
))
1348 states
&= ~RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1350 if (!pCreateInfo
->pRasterizationState
||
1351 !vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1352 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
))
1353 states
&= ~RADV_DYNAMIC_LINE_STIPPLE
;
1355 /* TODO: blend constants & line width. */
1361 radv_pipeline_init_input_assembly_state(struct radv_pipeline
*pipeline
,
1362 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1363 const struct radv_graphics_pipeline_create_info
*extra
)
1365 const VkPipelineInputAssemblyStateCreateInfo
*ia_state
= pCreateInfo
->pInputAssemblyState
;
1366 struct radv_shader_variant
*tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
1367 struct radv_shader_variant
*gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1369 pipeline
->graphics
.prim_restart_enable
= !!ia_state
->primitiveRestartEnable
;
1370 pipeline
->graphics
.can_use_guardband
= radv_prim_can_use_guardband(ia_state
->topology
);
1372 if (radv_pipeline_has_gs(pipeline
)) {
1373 if (si_conv_gl_prim_to_gs_out(gs
->info
.gs
.output_prim
) == V_028A6C_OUTPRIM_TYPE_TRISTRIP
)
1374 pipeline
->graphics
.can_use_guardband
= true;
1375 } else if (radv_pipeline_has_tess(pipeline
)) {
1376 if (!tes
->info
.tes
.point_mode
&&
1377 si_conv_gl_prim_to_gs_out(tes
->info
.tes
.primitive_mode
) == V_028A6C_OUTPRIM_TYPE_TRISTRIP
)
1378 pipeline
->graphics
.can_use_guardband
= true;
1381 if (extra
&& extra
->use_rectlist
) {
1382 pipeline
->graphics
.can_use_guardband
= true;
1387 radv_pipeline_init_dynamic_state(struct radv_pipeline
*pipeline
,
1388 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1389 const struct radv_graphics_pipeline_create_info
*extra
)
1391 uint32_t needed_states
= radv_pipeline_needed_dynamic_state(pCreateInfo
);
1392 uint32_t states
= needed_states
;
1393 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1394 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1396 pipeline
->dynamic_state
= default_dynamic_state
;
1397 pipeline
->graphics
.needed_dynamic_state
= needed_states
;
1399 if (pCreateInfo
->pDynamicState
) {
1400 /* Remove all of the states that are marked as dynamic */
1401 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1402 for (uint32_t s
= 0; s
< count
; s
++)
1403 states
&= ~radv_dynamic_state_mask(pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1406 struct radv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1408 if (needed_states
& RADV_DYNAMIC_VIEWPORT
) {
1409 assert(pCreateInfo
->pViewportState
);
1411 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1412 if (states
& RADV_DYNAMIC_VIEWPORT
) {
1413 typed_memcpy(dynamic
->viewport
.viewports
,
1414 pCreateInfo
->pViewportState
->pViewports
,
1415 pCreateInfo
->pViewportState
->viewportCount
);
1419 if (needed_states
& RADV_DYNAMIC_SCISSOR
) {
1420 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1421 if (states
& RADV_DYNAMIC_SCISSOR
) {
1422 typed_memcpy(dynamic
->scissor
.scissors
,
1423 pCreateInfo
->pViewportState
->pScissors
,
1424 pCreateInfo
->pViewportState
->scissorCount
);
1428 if (states
& RADV_DYNAMIC_LINE_WIDTH
) {
1429 assert(pCreateInfo
->pRasterizationState
);
1430 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1433 if (states
& RADV_DYNAMIC_DEPTH_BIAS
) {
1434 assert(pCreateInfo
->pRasterizationState
);
1435 dynamic
->depth_bias
.bias
=
1436 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1437 dynamic
->depth_bias
.clamp
=
1438 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1439 dynamic
->depth_bias
.slope
=
1440 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1443 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1445 * pColorBlendState is [...] NULL if the pipeline has rasterization
1446 * disabled or if the subpass of the render pass the pipeline is
1447 * created against does not use any color attachments.
1449 if (subpass
->has_color_att
&& states
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
1450 assert(pCreateInfo
->pColorBlendState
);
1451 typed_memcpy(dynamic
->blend_constants
,
1452 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1455 if (states
& RADV_DYNAMIC_CULL_MODE
) {
1456 dynamic
->cull_mode
=
1457 pCreateInfo
->pRasterizationState
->cullMode
;
1460 if (states
& RADV_DYNAMIC_FRONT_FACE
) {
1461 dynamic
->front_face
=
1462 pCreateInfo
->pRasterizationState
->frontFace
;
1465 if (states
& RADV_DYNAMIC_PRIMITIVE_TOPOLOGY
) {
1466 dynamic
->primitive_topology
=
1467 si_translate_prim(pCreateInfo
->pInputAssemblyState
->topology
);
1468 if (extra
&& extra
->use_rectlist
) {
1469 dynamic
->primitive_topology
= V_008958_DI_PT_RECTLIST
;
1473 /* If there is no depthstencil attachment, then don't read
1474 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1475 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1476 * no need to override the depthstencil defaults in
1477 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1479 * Section 9.2 of the Vulkan 1.0.15 spec says:
1481 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1482 * disabled or if the subpass of the render pass the pipeline is created
1483 * against does not use a depth/stencil attachment.
1485 if (needed_states
&& subpass
->depth_stencil_attachment
) {
1486 assert(pCreateInfo
->pDepthStencilState
);
1488 if (states
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
1489 dynamic
->depth_bounds
.min
=
1490 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1491 dynamic
->depth_bounds
.max
=
1492 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1495 if (states
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
1496 dynamic
->stencil_compare_mask
.front
=
1497 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1498 dynamic
->stencil_compare_mask
.back
=
1499 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1502 if (states
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
1503 dynamic
->stencil_write_mask
.front
=
1504 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1505 dynamic
->stencil_write_mask
.back
=
1506 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1509 if (states
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
1510 dynamic
->stencil_reference
.front
=
1511 pCreateInfo
->pDepthStencilState
->front
.reference
;
1512 dynamic
->stencil_reference
.back
=
1513 pCreateInfo
->pDepthStencilState
->back
.reference
;
1516 if (states
& RADV_DYNAMIC_DEPTH_TEST_ENABLE
) {
1517 dynamic
->depth_test_enable
=
1518 pCreateInfo
->pDepthStencilState
->depthTestEnable
;
1521 if (states
& RADV_DYNAMIC_DEPTH_WRITE_ENABLE
) {
1522 dynamic
->depth_write_enable
=
1523 pCreateInfo
->pDepthStencilState
->depthWriteEnable
;
1526 if (states
& RADV_DYNAMIC_DEPTH_COMPARE_OP
) {
1527 dynamic
->depth_compare_op
=
1528 pCreateInfo
->pDepthStencilState
->depthCompareOp
;
1531 if (states
& RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE
) {
1532 dynamic
->depth_bounds_test_enable
=
1533 pCreateInfo
->pDepthStencilState
->depthBoundsTestEnable
;
1536 if (states
& RADV_DYNAMIC_STENCIL_TEST_ENABLE
) {
1537 dynamic
->stencil_test_enable
=
1538 pCreateInfo
->pDepthStencilState
->stencilTestEnable
;
1541 if (states
& RADV_DYNAMIC_STENCIL_OP
) {
1542 dynamic
->stencil_op
.front
.compare_op
=
1543 pCreateInfo
->pDepthStencilState
->front
.compareOp
;
1544 dynamic
->stencil_op
.front
.fail_op
=
1545 pCreateInfo
->pDepthStencilState
->front
.failOp
;
1546 dynamic
->stencil_op
.front
.pass_op
=
1547 pCreateInfo
->pDepthStencilState
->front
.passOp
;
1548 dynamic
->stencil_op
.front
.depth_fail_op
=
1549 pCreateInfo
->pDepthStencilState
->front
.depthFailOp
;
1551 dynamic
->stencil_op
.back
.compare_op
=
1552 pCreateInfo
->pDepthStencilState
->back
.compareOp
;
1553 dynamic
->stencil_op
.back
.fail_op
=
1554 pCreateInfo
->pDepthStencilState
->back
.failOp
;
1555 dynamic
->stencil_op
.back
.pass_op
=
1556 pCreateInfo
->pDepthStencilState
->back
.passOp
;
1557 dynamic
->stencil_op
.back
.depth_fail_op
=
1558 pCreateInfo
->pDepthStencilState
->back
.depthFailOp
;
1562 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
1563 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
1564 if (needed_states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1565 dynamic
->discard_rectangle
.count
= discard_rectangle_info
->discardRectangleCount
;
1566 if (states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1567 typed_memcpy(dynamic
->discard_rectangle
.rectangles
,
1568 discard_rectangle_info
->pDiscardRectangles
,
1569 discard_rectangle_info
->discardRectangleCount
);
1573 if (needed_states
& RADV_DYNAMIC_SAMPLE_LOCATIONS
) {
1574 const VkPipelineSampleLocationsStateCreateInfoEXT
*sample_location_info
=
1575 vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1576 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
);
1577 /* If sampleLocationsEnable is VK_FALSE, the default sample
1578 * locations are used and the values specified in
1579 * sampleLocationsInfo are ignored.
1581 if (sample_location_info
->sampleLocationsEnable
) {
1582 const VkSampleLocationsInfoEXT
*pSampleLocationsInfo
=
1583 &sample_location_info
->sampleLocationsInfo
;
1585 assert(pSampleLocationsInfo
->sampleLocationsCount
<= MAX_SAMPLE_LOCATIONS
);
1587 dynamic
->sample_location
.per_pixel
= pSampleLocationsInfo
->sampleLocationsPerPixel
;
1588 dynamic
->sample_location
.grid_size
= pSampleLocationsInfo
->sampleLocationGridSize
;
1589 dynamic
->sample_location
.count
= pSampleLocationsInfo
->sampleLocationsCount
;
1590 typed_memcpy(&dynamic
->sample_location
.locations
[0],
1591 pSampleLocationsInfo
->pSampleLocations
,
1592 pSampleLocationsInfo
->sampleLocationsCount
);
1596 const VkPipelineRasterizationLineStateCreateInfoEXT
*rast_line_info
=
1597 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1598 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1599 if (needed_states
& RADV_DYNAMIC_LINE_STIPPLE
) {
1600 dynamic
->line_stipple
.factor
= rast_line_info
->lineStippleFactor
;
1601 dynamic
->line_stipple
.pattern
= rast_line_info
->lineStipplePattern
;
1604 if (!(states
& RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE
))
1605 pipeline
->graphics
.uses_dynamic_stride
= true;
1607 pipeline
->dynamic_state
.mask
= states
;
1611 radv_pipeline_init_raster_state(struct radv_pipeline
*pipeline
,
1612 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1614 const VkPipelineRasterizationStateCreateInfo
*raster_info
=
1615 pCreateInfo
->pRasterizationState
;
1617 pipeline
->graphics
.pa_su_sc_mode_cntl
=
1618 S_028814_FACE(raster_info
->frontFace
) |
1619 S_028814_CULL_FRONT(!!(raster_info
->cullMode
& VK_CULL_MODE_FRONT_BIT
)) |
1620 S_028814_CULL_BACK(!!(raster_info
->cullMode
& VK_CULL_MODE_BACK_BIT
)) |
1621 S_028814_POLY_MODE(raster_info
->polygonMode
!= VK_POLYGON_MODE_FILL
) |
1622 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(raster_info
->polygonMode
)) |
1623 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(raster_info
->polygonMode
)) |
1624 S_028814_POLY_OFFSET_FRONT_ENABLE(raster_info
->depthBiasEnable
? 1 : 0) |
1625 S_028814_POLY_OFFSET_BACK_ENABLE(raster_info
->depthBiasEnable
? 1 : 0) |
1626 S_028814_POLY_OFFSET_PARA_ENABLE(raster_info
->depthBiasEnable
? 1 : 0);
1630 radv_pipeline_init_depth_stencil_state(struct radv_pipeline
*pipeline
,
1631 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1633 const VkPipelineDepthStencilStateCreateInfo
*ds_info
1634 = radv_pipeline_get_depth_stencil_state(pCreateInfo
);
1635 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1636 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
1637 struct radv_render_pass_attachment
*attachment
= NULL
;
1638 uint32_t db_depth_control
= 0;
1640 if (subpass
->depth_stencil_attachment
)
1641 attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
1643 bool has_depth_attachment
= attachment
&& vk_format_is_depth(attachment
->format
);
1644 bool has_stencil_attachment
= attachment
&& vk_format_is_stencil(attachment
->format
);
1647 if (has_depth_attachment
) {
1648 db_depth_control
= S_028800_Z_ENABLE(ds_info
->depthTestEnable
? 1 : 0) |
1649 S_028800_Z_WRITE_ENABLE(ds_info
->depthWriteEnable
? 1 : 0) |
1650 S_028800_ZFUNC(ds_info
->depthCompareOp
) |
1651 S_028800_DEPTH_BOUNDS_ENABLE(ds_info
->depthBoundsTestEnable
? 1 : 0);
1654 if (has_stencil_attachment
&& ds_info
->stencilTestEnable
) {
1655 db_depth_control
|= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
1656 db_depth_control
|= S_028800_STENCILFUNC(ds_info
->front
.compareOp
);
1657 db_depth_control
|= S_028800_STENCILFUNC_BF(ds_info
->back
.compareOp
);
1661 pipeline
->graphics
.db_depth_control
= db_depth_control
;
1665 gfx9_get_gs_info(const struct radv_pipeline_key
*key
,
1666 const struct radv_pipeline
*pipeline
,
1668 struct radv_shader_info
*infos
,
1669 struct gfx9_gs_info
*out
)
1671 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1672 struct radv_es_output_info
*es_info
;
1673 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1674 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1676 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ?
1677 &infos
[MESA_SHADER_TESS_EVAL
].tes
.es_info
:
1678 &infos
[MESA_SHADER_VERTEX
].vs
.es_info
;
1680 unsigned gs_num_invocations
= MAX2(gs_info
->gs
.invocations
, 1);
1681 bool uses_adjacency
;
1682 switch(key
->topology
) {
1683 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1684 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1685 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1686 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1687 uses_adjacency
= true;
1690 uses_adjacency
= false;
1694 /* All these are in dwords: */
1695 /* We can't allow using the whole LDS, because GS waves compete with
1696 * other shader stages for LDS space. */
1697 const unsigned max_lds_size
= 8 * 1024;
1698 const unsigned esgs_itemsize
= es_info
->esgs_itemsize
/ 4;
1699 unsigned esgs_lds_size
;
1701 /* All these are per subgroup: */
1702 const unsigned max_out_prims
= 32 * 1024;
1703 const unsigned max_es_verts
= 255;
1704 const unsigned ideal_gs_prims
= 64;
1705 unsigned max_gs_prims
, gs_prims
;
1706 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
1708 if (uses_adjacency
|| gs_num_invocations
> 1)
1709 max_gs_prims
= 127 / gs_num_invocations
;
1713 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1714 * Make sure we don't go over the maximum value.
1716 if (gs_info
->gs
.vertices_out
> 0) {
1717 max_gs_prims
= MIN2(max_gs_prims
,
1719 (gs_info
->gs
.vertices_out
* gs_num_invocations
));
1721 assert(max_gs_prims
> 0);
1723 /* If the primitive has adjacency, halve the number of vertices
1724 * that will be reused in multiple primitives.
1726 min_es_verts
= gs_info
->gs
.vertices_in
/ (uses_adjacency
? 2 : 1);
1728 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
1729 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
1731 /* Compute ESGS LDS size based on the worst case number of ES vertices
1732 * needed to create the target number of GS prims per subgroup.
1734 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1736 /* If total LDS usage is too big, refactor partitions based on ratio
1737 * of ESGS item sizes.
1739 if (esgs_lds_size
> max_lds_size
) {
1740 /* Our target GS Prims Per Subgroup was too large. Calculate
1741 * the maximum number of GS Prims Per Subgroup that will fit
1742 * into LDS, capped by the maximum that the hardware can support.
1744 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
1746 assert(gs_prims
> 0);
1747 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
1750 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1751 assert(esgs_lds_size
<= max_lds_size
);
1754 /* Now calculate remaining ESGS information. */
1756 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
1758 es_verts
= max_es_verts
;
1760 /* Vertices for adjacency primitives are not always reused, so restore
1761 * it for ES_VERTS_PER_SUBGRP.
1763 min_es_verts
= gs_info
->gs
.vertices_in
;
1765 /* For normal primitives, the VGT only checks if they are past the ES
1766 * verts per subgroup after allocating a full GS primitive and if they
1767 * are, kick off a new subgroup. But if those additional ES verts are
1768 * unique (e.g. not reused) we need to make sure there is enough LDS
1769 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1771 es_verts
-= min_es_verts
- 1;
1773 uint32_t es_verts_per_subgroup
= es_verts
;
1774 uint32_t gs_prims_per_subgroup
= gs_prims
;
1775 uint32_t gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
1776 uint32_t max_prims_per_subgroup
= gs_inst_prims_in_subgroup
* gs_info
->gs
.vertices_out
;
1777 out
->lds_size
= align(esgs_lds_size
, 128) / 128;
1778 out
->vgt_gs_onchip_cntl
= S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup
) |
1779 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup
) |
1780 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup
);
1781 out
->vgt_gs_max_prims_per_subgroup
= S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup
);
1782 out
->vgt_esgs_ring_itemsize
= esgs_itemsize
;
1783 assert(max_prims_per_subgroup
<= max_out_prims
);
1786 static void clamp_gsprims_to_esverts(unsigned *max_gsprims
, unsigned max_esverts
,
1787 unsigned min_verts_per_prim
, bool use_adjacency
)
1789 unsigned max_reuse
= max_esverts
- min_verts_per_prim
;
1792 *max_gsprims
= MIN2(*max_gsprims
, 1 + max_reuse
);
1796 radv_get_num_input_vertices(nir_shader
**nir
)
1798 if (nir
[MESA_SHADER_GEOMETRY
]) {
1799 nir_shader
*gs
= nir
[MESA_SHADER_GEOMETRY
];
1801 return gs
->info
.gs
.vertices_in
;
1804 if (nir
[MESA_SHADER_TESS_CTRL
]) {
1805 nir_shader
*tes
= nir
[MESA_SHADER_TESS_EVAL
];
1807 if (tes
->info
.tess
.point_mode
)
1809 if (tes
->info
.tess
.primitive_mode
== GL_ISOLINES
)
1818 gfx10_get_ngg_info(const struct radv_pipeline_key
*key
,
1819 struct radv_pipeline
*pipeline
,
1821 struct radv_shader_info
*infos
,
1822 struct gfx10_ngg_info
*ngg
)
1824 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1825 struct radv_es_output_info
*es_info
=
1826 nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1827 unsigned gs_type
= nir
[MESA_SHADER_GEOMETRY
] ? MESA_SHADER_GEOMETRY
: MESA_SHADER_VERTEX
;
1828 unsigned max_verts_per_prim
= radv_get_num_input_vertices(nir
);
1829 unsigned min_verts_per_prim
=
1830 gs_type
== MESA_SHADER_GEOMETRY
? max_verts_per_prim
: 1;
1831 unsigned gs_num_invocations
= nir
[MESA_SHADER_GEOMETRY
] ? MAX2(gs_info
->gs
.invocations
, 1) : 1;
1832 bool uses_adjacency
;
1833 switch(key
->topology
) {
1834 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1835 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1836 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1837 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1838 uses_adjacency
= true;
1841 uses_adjacency
= false;
1845 /* All these are in dwords: */
1846 /* We can't allow using the whole LDS, because GS waves compete with
1847 * other shader stages for LDS space.
1849 * TODO: We should really take the shader's internal LDS use into
1850 * account. The linker will fail if the size is greater than
1853 const unsigned max_lds_size
= 8 * 1024 - 768;
1854 const unsigned target_lds_size
= max_lds_size
;
1855 unsigned esvert_lds_size
= 0;
1856 unsigned gsprim_lds_size
= 0;
1858 /* All these are per subgroup: */
1859 bool max_vert_out_per_gs_instance
= false;
1860 unsigned max_esverts_base
= 256;
1861 unsigned max_gsprims_base
= 128; /* default prim group size clamp */
1863 /* Hardware has the following non-natural restrictions on the value
1864 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1866 * - at most 252 for any line input primitive type
1867 * - at most 251 for any quad input primitive type
1868 * - at most 251 for triangle strips with adjacency (this happens to
1869 * be the natural limit for triangle *lists* with adjacency)
1871 max_esverts_base
= MIN2(max_esverts_base
, 251 + max_verts_per_prim
- 1);
1873 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1874 unsigned max_out_verts_per_gsprim
=
1875 gs_info
->gs
.vertices_out
* gs_num_invocations
;
1877 if (max_out_verts_per_gsprim
<= 256) {
1878 if (max_out_verts_per_gsprim
) {
1879 max_gsprims_base
= MIN2(max_gsprims_base
,
1880 256 / max_out_verts_per_gsprim
);
1883 /* Use special multi-cycling mode in which each GS
1884 * instance gets its own subgroup. Does not work with
1886 max_vert_out_per_gs_instance
= true;
1887 max_gsprims_base
= 1;
1888 max_out_verts_per_gsprim
= gs_info
->gs
.vertices_out
;
1891 esvert_lds_size
= es_info
->esgs_itemsize
/ 4;
1892 gsprim_lds_size
= (gs_info
->gs
.gsvs_vertex_size
/ 4 + 1) * max_out_verts_per_gsprim
;
1895 /* LDS size for passing data from GS to ES. */
1896 struct radv_streamout_info
*so_info
= nir
[MESA_SHADER_TESS_CTRL
]
1897 ? &infos
[MESA_SHADER_TESS_EVAL
].so
1898 : &infos
[MESA_SHADER_VERTEX
].so
;
1900 if (so_info
->num_outputs
)
1901 esvert_lds_size
= 4 * so_info
->num_outputs
+ 1;
1903 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1904 * corresponding to the ES thread of the provoking vertex. All
1905 * ES threads load and export PrimitiveID for their thread.
1907 if (!nir
[MESA_SHADER_TESS_CTRL
] &&
1908 infos
[MESA_SHADER_VERTEX
].vs
.outinfo
.export_prim_id
)
1909 esvert_lds_size
= MAX2(esvert_lds_size
, 1);
1912 unsigned max_gsprims
= max_gsprims_base
;
1913 unsigned max_esverts
= max_esverts_base
;
1915 if (esvert_lds_size
)
1916 max_esverts
= MIN2(max_esverts
, target_lds_size
/ esvert_lds_size
);
1917 if (gsprim_lds_size
)
1918 max_gsprims
= MIN2(max_gsprims
, target_lds_size
/ gsprim_lds_size
);
1920 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1921 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
, min_verts_per_prim
, uses_adjacency
);
1922 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1924 if (esvert_lds_size
|| gsprim_lds_size
) {
1925 /* Now that we have a rough proportionality between esverts
1926 * and gsprims based on the primitive type, scale both of them
1927 * down simultaneously based on required LDS space.
1929 * We could be smarter about this if we knew how much vertex
1932 unsigned lds_total
= max_esverts
* esvert_lds_size
+
1933 max_gsprims
* gsprim_lds_size
;
1934 if (lds_total
> target_lds_size
) {
1935 max_esverts
= max_esverts
* target_lds_size
/ lds_total
;
1936 max_gsprims
= max_gsprims
* target_lds_size
/ lds_total
;
1938 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1939 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1940 min_verts_per_prim
, uses_adjacency
);
1941 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1945 /* Round up towards full wave sizes for better ALU utilization. */
1946 if (!max_vert_out_per_gs_instance
) {
1947 unsigned orig_max_esverts
;
1948 unsigned orig_max_gsprims
;
1951 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1952 wavesize
= gs_info
->wave_size
;
1954 wavesize
= nir
[MESA_SHADER_TESS_CTRL
]
1955 ? infos
[MESA_SHADER_TESS_EVAL
].wave_size
1956 : infos
[MESA_SHADER_VERTEX
].wave_size
;
1960 orig_max_esverts
= max_esverts
;
1961 orig_max_gsprims
= max_gsprims
;
1963 max_esverts
= align(max_esverts
, wavesize
);
1964 max_esverts
= MIN2(max_esverts
, max_esverts_base
);
1965 if (esvert_lds_size
)
1966 max_esverts
= MIN2(max_esverts
,
1967 (max_lds_size
- max_gsprims
* gsprim_lds_size
) /
1969 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1971 max_gsprims
= align(max_gsprims
, wavesize
);
1972 max_gsprims
= MIN2(max_gsprims
, max_gsprims_base
);
1973 if (gsprim_lds_size
)
1974 max_gsprims
= MIN2(max_gsprims
,
1975 (max_lds_size
- max_esverts
* esvert_lds_size
) /
1977 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1978 min_verts_per_prim
, uses_adjacency
);
1979 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1980 } while (orig_max_esverts
!= max_esverts
|| orig_max_gsprims
!= max_gsprims
);
1983 /* Hardware restriction: minimum value of max_esverts */
1984 max_esverts
= MAX2(max_esverts
, 23 + max_verts_per_prim
);
1986 unsigned max_out_vertices
=
1987 max_vert_out_per_gs_instance
? gs_info
->gs
.vertices_out
:
1988 gs_type
== MESA_SHADER_GEOMETRY
?
1989 max_gsprims
* gs_num_invocations
* gs_info
->gs
.vertices_out
:
1991 assert(max_out_vertices
<= 256);
1993 unsigned prim_amp_factor
= 1;
1994 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1995 /* Number of output primitives per GS input primitive after
1997 prim_amp_factor
= gs_info
->gs
.vertices_out
;
2000 /* The GE only checks against the maximum number of ES verts after
2001 * allocating a full GS primitive. So we need to ensure that whenever
2002 * this check passes, there is enough space for a full primitive without
2005 ngg
->hw_max_esverts
= max_esverts
- max_verts_per_prim
+ 1;
2006 ngg
->max_gsprims
= max_gsprims
;
2007 ngg
->max_out_verts
= max_out_vertices
;
2008 ngg
->prim_amp_factor
= prim_amp_factor
;
2009 ngg
->max_vert_out_per_gs_instance
= max_vert_out_per_gs_instance
;
2010 ngg
->ngg_emit_size
= max_gsprims
* gsprim_lds_size
;
2011 ngg
->esgs_ring_size
= 4 * max_esverts
* esvert_lds_size
;
2013 if (gs_type
== MESA_SHADER_GEOMETRY
) {
2014 ngg
->vgt_esgs_ring_itemsize
= es_info
->esgs_itemsize
/ 4;
2016 ngg
->vgt_esgs_ring_itemsize
= 1;
2019 pipeline
->graphics
.esgs_ring_size
= ngg
->esgs_ring_size
;
2021 assert(ngg
->hw_max_esverts
>= 24); /* HW limitation */
2025 calculate_gs_ring_sizes(struct radv_pipeline
*pipeline
,
2026 const struct gfx9_gs_info
*gs
)
2028 struct radv_device
*device
= pipeline
->device
;
2029 unsigned num_se
= device
->physical_device
->rad_info
.max_se
;
2030 unsigned wave_size
= 64;
2031 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
2032 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
2033 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
2035 unsigned gs_vertex_reuse
=
2036 (device
->physical_device
->rad_info
.chip_class
>= GFX8
? 32 : 16) * num_se
;
2037 unsigned alignment
= 256 * num_se
;
2038 /* The maximum size is 63.999 MB per SE. */
2039 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
2040 struct radv_shader_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
2042 /* Calculate the minimum size. */
2043 unsigned min_esgs_ring_size
= align(gs
->vgt_esgs_ring_itemsize
* 4 * gs_vertex_reuse
*
2044 wave_size
, alignment
);
2045 /* These are recommended sizes, not minimum sizes. */
2046 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
2047 gs
->vgt_esgs_ring_itemsize
* 4 * gs_info
->gs
.vertices_in
;
2048 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
2049 gs_info
->gs
.max_gsvs_emit_size
;
2051 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
2052 esgs_ring_size
= align(esgs_ring_size
, alignment
);
2053 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
2055 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
2056 pipeline
->graphics
.esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
2058 pipeline
->graphics
.gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
2061 struct radv_shader_variant
*
2062 radv_get_shader(const struct radv_pipeline
*pipeline
,
2063 gl_shader_stage stage
)
2065 if (stage
== MESA_SHADER_VERTEX
) {
2066 if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
2067 return pipeline
->shaders
[MESA_SHADER_VERTEX
];
2068 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
])
2069 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
2070 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
2071 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
2072 } else if (stage
== MESA_SHADER_TESS_EVAL
) {
2073 if (!radv_pipeline_has_tess(pipeline
))
2075 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
2076 return pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
2077 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
2078 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
2080 return pipeline
->shaders
[stage
];
2083 static const struct radv_vs_output_info
*get_vs_output_info(const struct radv_pipeline
*pipeline
)
2085 if (radv_pipeline_has_gs(pipeline
))
2086 if (radv_pipeline_has_ngg(pipeline
))
2087 return &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.vs
.outinfo
;
2089 return &pipeline
->gs_copy_shader
->info
.vs
.outinfo
;
2090 else if (radv_pipeline_has_tess(pipeline
))
2091 return &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.outinfo
;
2093 return &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.outinfo
;
2097 radv_link_shaders(struct radv_pipeline
*pipeline
, nir_shader
**shaders
)
2099 nir_shader
* ordered_shaders
[MESA_SHADER_STAGES
];
2100 int shader_count
= 0;
2102 if(shaders
[MESA_SHADER_FRAGMENT
]) {
2103 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_FRAGMENT
];
2105 if(shaders
[MESA_SHADER_GEOMETRY
]) {
2106 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_GEOMETRY
];
2108 if(shaders
[MESA_SHADER_TESS_EVAL
]) {
2109 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_EVAL
];
2111 if(shaders
[MESA_SHADER_TESS_CTRL
]) {
2112 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_CTRL
];
2114 if(shaders
[MESA_SHADER_VERTEX
]) {
2115 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_VERTEX
];
2118 if (shader_count
> 1) {
2119 unsigned first
= ordered_shaders
[shader_count
- 1]->info
.stage
;
2120 unsigned last
= ordered_shaders
[0]->info
.stage
;
2122 if (ordered_shaders
[0]->info
.stage
== MESA_SHADER_FRAGMENT
&&
2123 ordered_shaders
[1]->info
.has_transform_feedback_varyings
)
2124 nir_link_xfb_varyings(ordered_shaders
[1], ordered_shaders
[0]);
2126 for (int i
= 0; i
< shader_count
; ++i
) {
2127 nir_variable_mode mask
= 0;
2129 if (ordered_shaders
[i
]->info
.stage
!= first
)
2130 mask
= mask
| nir_var_shader_in
;
2132 if (ordered_shaders
[i
]->info
.stage
!= last
)
2133 mask
= mask
| nir_var_shader_out
;
2135 nir_lower_io_to_scalar_early(ordered_shaders
[i
], mask
);
2136 radv_optimize_nir(ordered_shaders
[i
], false, false);
2140 for (int i
= 1; i
< shader_count
; ++i
) {
2141 nir_lower_io_arrays_to_elements(ordered_shaders
[i
],
2142 ordered_shaders
[i
- 1]);
2144 if (nir_link_opt_varyings(ordered_shaders
[i
],
2145 ordered_shaders
[i
- 1]))
2146 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2148 nir_remove_dead_variables(ordered_shaders
[i
],
2149 nir_var_shader_out
, NULL
);
2150 nir_remove_dead_variables(ordered_shaders
[i
- 1],
2151 nir_var_shader_in
, NULL
);
2153 bool progress
= nir_remove_unused_varyings(ordered_shaders
[i
],
2154 ordered_shaders
[i
- 1]);
2156 nir_compact_varyings(ordered_shaders
[i
],
2157 ordered_shaders
[i
- 1], true);
2160 if (nir_lower_global_vars_to_local(ordered_shaders
[i
])) {
2161 ac_lower_indirect_derefs(ordered_shaders
[i
],
2162 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2164 radv_optimize_nir(ordered_shaders
[i
], false, false);
2166 if (nir_lower_global_vars_to_local(ordered_shaders
[i
- 1])) {
2167 ac_lower_indirect_derefs(ordered_shaders
[i
- 1],
2168 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2170 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2176 radv_set_linked_driver_locations(struct radv_pipeline
*pipeline
, nir_shader
**shaders
,
2177 struct radv_shader_info infos
[MESA_SHADER_STAGES
])
2179 bool has_tess
= shaders
[MESA_SHADER_TESS_CTRL
];
2180 bool has_gs
= shaders
[MESA_SHADER_GEOMETRY
];
2182 if (!has_tess
&& !has_gs
)
2185 unsigned vs_info_idx
= MESA_SHADER_VERTEX
;
2186 unsigned tes_info_idx
= MESA_SHADER_TESS_EVAL
;
2188 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2189 /* These are merged into the next stage */
2190 vs_info_idx
= has_tess
? MESA_SHADER_TESS_CTRL
: MESA_SHADER_GEOMETRY
;
2191 tes_info_idx
= has_gs
? MESA_SHADER_GEOMETRY
: MESA_SHADER_TESS_EVAL
;
2195 nir_linked_io_var_info vs2tcs
=
2196 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_VERTEX
], shaders
[MESA_SHADER_TESS_CTRL
]);
2197 nir_linked_io_var_info tcs2tes
=
2198 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_TESS_CTRL
], shaders
[MESA_SHADER_TESS_EVAL
]);
2200 infos
[vs_info_idx
].vs
.num_linked_outputs
= vs2tcs
.num_linked_io_vars
;
2201 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_inputs
= vs2tcs
.num_linked_io_vars
;
2202 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_outputs
= tcs2tes
.num_linked_io_vars
;
2203 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_patch_outputs
= tcs2tes
.num_linked_patch_io_vars
;
2204 infos
[tes_info_idx
].tes
.num_linked_inputs
= tcs2tes
.num_linked_io_vars
;
2205 infos
[tes_info_idx
].tes
.num_linked_patch_inputs
= tcs2tes
.num_linked_patch_io_vars
;
2208 nir_linked_io_var_info tes2gs
=
2209 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_TESS_EVAL
], shaders
[MESA_SHADER_GEOMETRY
]);
2211 infos
[tes_info_idx
].tes
.num_linked_outputs
= tes2gs
.num_linked_io_vars
;
2212 infos
[MESA_SHADER_GEOMETRY
].gs
.num_linked_inputs
= tes2gs
.num_linked_io_vars
;
2214 } else if (has_gs
) {
2215 nir_linked_io_var_info vs2gs
=
2216 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_VERTEX
], shaders
[MESA_SHADER_GEOMETRY
]);
2218 infos
[vs_info_idx
].vs
.num_linked_outputs
= vs2gs
.num_linked_io_vars
;
2219 infos
[MESA_SHADER_GEOMETRY
].gs
.num_linked_inputs
= vs2gs
.num_linked_io_vars
;
2224 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo
*input_state
,
2225 uint32_t attrib_binding
)
2227 for (uint32_t i
= 0; i
< input_state
->vertexBindingDescriptionCount
; i
++) {
2228 const VkVertexInputBindingDescription
*input_binding
=
2229 &input_state
->pVertexBindingDescriptions
[i
];
2231 if (input_binding
->binding
== attrib_binding
)
2232 return input_binding
->stride
;
2238 static struct radv_pipeline_key
2239 radv_generate_graphics_pipeline_key(struct radv_pipeline
*pipeline
,
2240 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2241 const struct radv_blend_state
*blend
)
2243 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
2244 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
2245 const VkPipelineVertexInputStateCreateInfo
*input_state
=
2246 pCreateInfo
->pVertexInputState
;
2247 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*divisor_state
=
2248 vk_find_struct_const(input_state
->pNext
, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
2250 struct radv_pipeline_key key
;
2251 memset(&key
, 0, sizeof(key
));
2253 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
2254 key
.optimisations_disabled
= 1;
2256 key
.has_multiview_view_index
= !!subpass
->view_mask
;
2258 uint32_t binding_input_rate
= 0;
2259 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
2260 for (unsigned i
= 0; i
< input_state
->vertexBindingDescriptionCount
; ++i
) {
2261 if (input_state
->pVertexBindingDescriptions
[i
].inputRate
) {
2262 unsigned binding
= input_state
->pVertexBindingDescriptions
[i
].binding
;
2263 binding_input_rate
|= 1u << binding
;
2264 instance_rate_divisors
[binding
] = 1;
2267 if (divisor_state
) {
2268 for (unsigned i
= 0; i
< divisor_state
->vertexBindingDivisorCount
; ++i
) {
2269 instance_rate_divisors
[divisor_state
->pVertexBindingDivisors
[i
].binding
] =
2270 divisor_state
->pVertexBindingDivisors
[i
].divisor
;
2274 for (unsigned i
= 0; i
< input_state
->vertexAttributeDescriptionCount
; ++i
) {
2275 const VkVertexInputAttributeDescription
*desc
=
2276 &input_state
->pVertexAttributeDescriptions
[i
];
2277 const struct vk_format_description
*format_desc
;
2278 unsigned location
= desc
->location
;
2279 unsigned binding
= desc
->binding
;
2280 unsigned num_format
, data_format
;
2283 if (binding_input_rate
& (1u << binding
)) {
2284 key
.instance_rate_inputs
|= 1u << location
;
2285 key
.instance_rate_divisors
[location
] = instance_rate_divisors
[binding
];
2288 format_desc
= vk_format_description(desc
->format
);
2289 first_non_void
= vk_format_get_first_non_void_channel(desc
->format
);
2291 num_format
= radv_translate_buffer_numformat(format_desc
, first_non_void
);
2292 data_format
= radv_translate_buffer_dataformat(format_desc
, first_non_void
);
2294 key
.vertex_attribute_formats
[location
] = data_format
| (num_format
<< 4);
2295 key
.vertex_attribute_bindings
[location
] = desc
->binding
;
2296 key
.vertex_attribute_offsets
[location
] = desc
->offset
;
2297 key
.vertex_attribute_strides
[location
] = radv_get_attrib_stride(input_state
, desc
->binding
);
2299 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
&&
2300 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_STONEY
) {
2301 VkFormat format
= input_state
->pVertexAttributeDescriptions
[i
].format
;
2304 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2305 case VK_FORMAT_A2B10G10R10_SNORM_PACK32
:
2306 adjust
= RADV_ALPHA_ADJUST_SNORM
;
2308 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2309 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32
:
2310 adjust
= RADV_ALPHA_ADJUST_SSCALED
;
2312 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2313 case VK_FORMAT_A2B10G10R10_SINT_PACK32
:
2314 adjust
= RADV_ALPHA_ADJUST_SINT
;
2320 key
.vertex_alpha_adjust
|= adjust
<< (2 * location
);
2323 switch (desc
->format
) {
2324 case VK_FORMAT_B8G8R8A8_UNORM
:
2325 case VK_FORMAT_B8G8R8A8_SNORM
:
2326 case VK_FORMAT_B8G8R8A8_USCALED
:
2327 case VK_FORMAT_B8G8R8A8_SSCALED
:
2328 case VK_FORMAT_B8G8R8A8_UINT
:
2329 case VK_FORMAT_B8G8R8A8_SINT
:
2330 case VK_FORMAT_B8G8R8A8_SRGB
:
2331 case VK_FORMAT_A2R10G10B10_UNORM_PACK32
:
2332 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2333 case VK_FORMAT_A2R10G10B10_USCALED_PACK32
:
2334 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2335 case VK_FORMAT_A2R10G10B10_UINT_PACK32
:
2336 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2337 key
.vertex_post_shuffle
|= 1 << location
;
2344 const VkPipelineTessellationStateCreateInfo
*tess
=
2345 radv_pipeline_get_tessellation_state(pCreateInfo
);
2347 key
.tess_input_vertices
= tess
->patchControlPoints
;
2349 const VkPipelineMultisampleStateCreateInfo
*vkms
=
2350 radv_pipeline_get_multisample_state(pCreateInfo
);
2351 if (vkms
&& vkms
->rasterizationSamples
> 1) {
2352 uint32_t num_samples
= vkms
->rasterizationSamples
;
2353 uint32_t ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
);
2354 key
.num_samples
= num_samples
;
2355 key
.log2_ps_iter_samples
= util_logbase2(ps_iter_samples
);
2358 key
.col_format
= blend
->spi_shader_col_format
;
2359 key
.is_dual_src
= blend
->mrt0_is_dual_src
;
2360 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX8
) {
2361 key
.is_int8
= blend
->col_format_is_int8
;
2362 key
.is_int10
= blend
->col_format_is_int10
;
2365 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
2366 key
.topology
= pCreateInfo
->pInputAssemblyState
->topology
;
2372 radv_nir_stage_uses_xfb(const nir_shader
*nir
)
2374 nir_xfb_info
*xfb
= nir_gather_xfb_info(nir
, NULL
);
2375 bool uses_xfb
= !!xfb
;
2382 radv_fill_shader_keys(struct radv_device
*device
,
2383 struct radv_shader_variant_key
*keys
,
2384 const struct radv_pipeline_key
*key
,
2387 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_inputs
= key
->instance_rate_inputs
;
2388 keys
[MESA_SHADER_VERTEX
].vs
.alpha_adjust
= key
->vertex_alpha_adjust
;
2389 keys
[MESA_SHADER_VERTEX
].vs
.post_shuffle
= key
->vertex_post_shuffle
;
2390 for (unsigned i
= 0; i
< MAX_VERTEX_ATTRIBS
; ++i
) {
2391 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_divisors
[i
] = key
->instance_rate_divisors
[i
];
2392 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_formats
[i
] = key
->vertex_attribute_formats
[i
];
2393 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_bindings
[i
] = key
->vertex_attribute_bindings
[i
];
2394 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_offsets
[i
] = key
->vertex_attribute_offsets
[i
];
2395 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_strides
[i
] = key
->vertex_attribute_strides
[i
];
2397 keys
[MESA_SHADER_VERTEX
].vs
.outprim
= si_conv_prim_to_gs_out(key
->topology
);
2399 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2400 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ls
= true;
2401 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= 0;
2402 keys
[MESA_SHADER_TESS_CTRL
].tcs
.input_vertices
= key
->tess_input_vertices
;
2403 keys
[MESA_SHADER_TESS_CTRL
].tcs
.primitive_mode
= nir
[MESA_SHADER_TESS_EVAL
]->info
.tess
.primitive_mode
;
2405 keys
[MESA_SHADER_TESS_CTRL
].tcs
.tes_reads_tess_factors
= !!(nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
& (VARYING_BIT_TESS_LEVEL_INNER
| VARYING_BIT_TESS_LEVEL_OUTER
));
2408 if (nir
[MESA_SHADER_GEOMETRY
]) {
2409 if (nir
[MESA_SHADER_TESS_CTRL
])
2410 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_es
= true;
2412 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_es
= true;
2415 if (device
->physical_device
->use_ngg
) {
2416 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2417 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= true;
2419 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= true;
2422 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2423 nir
[MESA_SHADER_GEOMETRY
] &&
2424 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.invocations
*
2425 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.vertices_out
> 256) {
2426 /* Fallback to the legacy path if tessellation is
2427 * enabled with extreme geometry because
2428 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2431 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2434 if (!device
->physical_device
->use_ngg_gs
) {
2435 if (nir
[MESA_SHADER_GEOMETRY
]) {
2436 if (nir
[MESA_SHADER_TESS_CTRL
])
2437 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2439 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2443 gl_shader_stage last_xfb_stage
= MESA_SHADER_VERTEX
;
2445 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2450 bool uses_xfb
= nir
[last_xfb_stage
] &&
2451 radv_nir_stage_uses_xfb(nir
[last_xfb_stage
]);
2453 if (!device
->physical_device
->use_ngg_streamout
&& uses_xfb
) {
2454 if (nir
[MESA_SHADER_TESS_CTRL
])
2455 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2457 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2460 /* Determine if the pipeline is eligible for the NGG passthrough
2461 * mode. It can't be enabled for geometry shaders, for NGG
2462 * streamout or for vertex shaders that export the primitive ID
2463 * (this is checked later because we don't have the info here.)
2465 if (!nir
[MESA_SHADER_GEOMETRY
] && !uses_xfb
) {
2466 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2467 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
) {
2468 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg_passthrough
= true;
2469 } else if (nir
[MESA_SHADER_VERTEX
] &&
2470 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) {
2471 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg_passthrough
= true;
2476 for(int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
2477 keys
[i
].has_multiview_view_index
= key
->has_multiview_view_index
;
2479 keys
[MESA_SHADER_FRAGMENT
].fs
.col_format
= key
->col_format
;
2480 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int8
= key
->is_int8
;
2481 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int10
= key
->is_int10
;
2482 keys
[MESA_SHADER_FRAGMENT
].fs
.log2_ps_iter_samples
= key
->log2_ps_iter_samples
;
2483 keys
[MESA_SHADER_FRAGMENT
].fs
.num_samples
= key
->num_samples
;
2484 keys
[MESA_SHADER_FRAGMENT
].fs
.is_dual_src
= key
->is_dual_src
;
2486 if (nir
[MESA_SHADER_COMPUTE
]) {
2487 keys
[MESA_SHADER_COMPUTE
].cs
.subgroup_size
= key
->compute_subgroup_size
;
2492 radv_get_wave_size(struct radv_device
*device
,
2493 const VkPipelineShaderStageCreateInfo
*pStage
,
2494 gl_shader_stage stage
,
2495 const struct radv_shader_variant_key
*key
)
2497 if (stage
== MESA_SHADER_GEOMETRY
&& !key
->vs_common_out
.as_ngg
)
2499 else if (stage
== MESA_SHADER_COMPUTE
) {
2500 if (key
->cs
.subgroup_size
) {
2501 /* Return the required subgroup size if specified. */
2502 return key
->cs
.subgroup_size
;
2504 return device
->physical_device
->cs_wave_size
;
2506 else if (stage
== MESA_SHADER_FRAGMENT
)
2507 return device
->physical_device
->ps_wave_size
;
2509 return device
->physical_device
->ge_wave_size
;
2513 radv_get_ballot_bit_size(struct radv_device
*device
,
2514 const VkPipelineShaderStageCreateInfo
*pStage
,
2515 gl_shader_stage stage
,
2516 const struct radv_shader_variant_key
*key
)
2518 if (stage
== MESA_SHADER_COMPUTE
&& key
->cs
.subgroup_size
)
2519 return key
->cs
.subgroup_size
;
2524 radv_fill_shader_info(struct radv_pipeline
*pipeline
,
2525 const VkPipelineShaderStageCreateInfo
**pStages
,
2526 struct radv_shader_variant_key
*keys
,
2527 struct radv_shader_info
*infos
,
2530 unsigned active_stages
= 0;
2531 unsigned filled_stages
= 0;
2533 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2535 active_stages
|= (1 << i
);
2538 if (nir
[MESA_SHADER_FRAGMENT
]) {
2539 radv_nir_shader_info_init(&infos
[MESA_SHADER_FRAGMENT
]);
2540 radv_nir_shader_info_pass(nir
[MESA_SHADER_FRAGMENT
],
2542 &keys
[MESA_SHADER_FRAGMENT
],
2543 &infos
[MESA_SHADER_FRAGMENT
],
2544 pipeline
->device
->physical_device
->use_llvm
);
2546 /* TODO: These are no longer used as keys we should refactor this */
2547 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
=
2548 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2549 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_layer_id
=
2550 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2551 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_clip_dists
=
2552 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2553 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_viewport_index
=
2554 infos
[MESA_SHADER_FRAGMENT
].ps
.viewport_index_input
;
2555 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_prim_id
=
2556 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2557 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_layer_id
=
2558 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2559 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_clip_dists
=
2560 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2561 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_viewport_index
=
2562 infos
[MESA_SHADER_FRAGMENT
].ps
.viewport_index_input
;
2564 /* NGG passthrough mode can't be enabled for vertex shaders
2565 * that export the primitive ID.
2567 * TODO: I should really refactor the keys logic.
2569 if (nir
[MESA_SHADER_VERTEX
] &&
2570 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
) {
2571 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg_passthrough
= false;
2574 filled_stages
|= (1 << MESA_SHADER_FRAGMENT
);
2577 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2578 infos
[MESA_SHADER_TESS_CTRL
].tcs
.tes_inputs_read
=
2579 nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
;
2580 infos
[MESA_SHADER_TESS_CTRL
].tcs
.tes_patch_inputs_read
=
2581 nir
[MESA_SHADER_TESS_EVAL
]->info
.patch_inputs_read
;
2584 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2585 nir
[MESA_SHADER_TESS_CTRL
]) {
2586 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2587 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2588 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2590 radv_nir_shader_info_init(&infos
[MESA_SHADER_TESS_CTRL
]);
2592 for (int i
= 0; i
< 2; i
++) {
2593 radv_nir_shader_info_pass(combined_nir
[i
],
2594 pipeline
->layout
, &key
,
2595 &infos
[MESA_SHADER_TESS_CTRL
],
2596 pipeline
->device
->physical_device
->use_llvm
);
2599 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2600 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2601 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2602 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2604 filled_stages
|= (1 << MESA_SHADER_VERTEX
);
2605 filled_stages
|= (1 << MESA_SHADER_TESS_CTRL
);
2608 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2609 nir
[MESA_SHADER_GEOMETRY
]) {
2610 gl_shader_stage pre_stage
= nir
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2611 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2613 radv_nir_shader_info_init(&infos
[MESA_SHADER_GEOMETRY
]);
2615 for (int i
= 0; i
< 2; i
++) {
2616 radv_nir_shader_info_pass(combined_nir
[i
],
2619 &infos
[MESA_SHADER_GEOMETRY
],
2620 pipeline
->device
->physical_device
->use_llvm
);
2623 filled_stages
|= (1 << pre_stage
);
2624 filled_stages
|= (1 << MESA_SHADER_GEOMETRY
);
2627 active_stages
^= filled_stages
;
2628 while (active_stages
) {
2629 int i
= u_bit_scan(&active_stages
);
2631 if (i
== MESA_SHADER_TESS_CTRL
) {
2632 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
=
2633 util_last_bit64(infos
[MESA_SHADER_VERTEX
].vs
.ls_outputs_written
);
2636 if (i
== MESA_SHADER_TESS_EVAL
) {
2637 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2638 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2639 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2640 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2643 radv_nir_shader_info_init(&infos
[i
]);
2644 radv_nir_shader_info_pass(nir
[i
], pipeline
->layout
,
2645 &keys
[i
], &infos
[i
], pipeline
->device
->physical_device
->use_llvm
);
2648 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2650 infos
[i
].wave_size
=
2651 radv_get_wave_size(pipeline
->device
, pStages
[i
],
2653 infos
[i
].ballot_bit_size
=
2654 radv_get_ballot_bit_size(pipeline
->device
,
2662 merge_tess_info(struct shader_info
*tes_info
,
2663 const struct shader_info
*tcs_info
)
2665 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2667 * "PointMode. Controls generation of points rather than triangles
2668 * or lines. This functionality defaults to disabled, and is
2669 * enabled if either shader stage includes the execution mode.
2671 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2672 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2673 * and OutputVertices, it says:
2675 * "One mode must be set in at least one of the tessellation
2678 * So, the fields can be set in either the TCS or TES, but they must
2679 * agree if set in both. Our backend looks at TES, so bitwise-or in
2680 * the values from the TCS.
2682 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
2683 tes_info
->tess
.tcs_vertices_out
== 0 ||
2684 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
2685 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
2687 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2688 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2689 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
2690 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
2692 assert(tcs_info
->tess
.primitive_mode
== 0 ||
2693 tes_info
->tess
.primitive_mode
== 0 ||
2694 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
2695 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
2696 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
2697 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
2701 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT
*ext
)
2706 if (ext
->pPipelineCreationFeedback
) {
2707 ext
->pPipelineCreationFeedback
->flags
= 0;
2708 ext
->pPipelineCreationFeedback
->duration
= 0;
2711 for (unsigned i
= 0; i
< ext
->pipelineStageCreationFeedbackCount
; ++i
) {
2712 ext
->pPipelineStageCreationFeedbacks
[i
].flags
= 0;
2713 ext
->pPipelineStageCreationFeedbacks
[i
].duration
= 0;
2718 void radv_start_feedback(VkPipelineCreationFeedbackEXT
*feedback
)
2723 feedback
->duration
-= radv_get_current_time();
2724 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
2728 void radv_stop_feedback(VkPipelineCreationFeedbackEXT
*feedback
, bool cache_hit
)
2733 feedback
->duration
+= radv_get_current_time();
2734 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
|
2735 (cache_hit
? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
: 0);
2738 VkResult
radv_create_shaders(struct radv_pipeline
*pipeline
,
2739 struct radv_device
*device
,
2740 struct radv_pipeline_cache
*cache
,
2741 const struct radv_pipeline_key
*key
,
2742 const VkPipelineShaderStageCreateInfo
**pStages
,
2743 const VkPipelineCreateFlags flags
,
2744 VkPipelineCreationFeedbackEXT
*pipeline_feedback
,
2745 VkPipelineCreationFeedbackEXT
**stage_feedbacks
)
2747 struct radv_shader_module fs_m
= {0};
2748 struct radv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
2749 nir_shader
*nir
[MESA_SHADER_STAGES
] = {0};
2750 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2751 struct radv_shader_variant_key keys
[MESA_SHADER_STAGES
] = {{{{{0}}}}};
2752 struct radv_shader_info infos
[MESA_SHADER_STAGES
] = {0};
2753 unsigned char hash
[20], gs_copy_hash
[20];
2754 bool keep_executable_info
= (flags
& VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
) || device
->keep_shader_info
;
2755 bool keep_statistic_info
= (flags
& VK_PIPELINE_CREATE_CAPTURE_STATISTICS_BIT_KHR
) ||
2756 (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SHADER_STATS
) ||
2757 device
->keep_shader_info
;
2759 radv_start_feedback(pipeline_feedback
);
2761 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2763 modules
[i
] = radv_shader_module_from_handle(pStages
[i
]->module
);
2764 if (modules
[i
]->nir
)
2765 _mesa_sha1_compute(modules
[i
]->nir
->info
.name
,
2766 strlen(modules
[i
]->nir
->info
.name
),
2769 pipeline
->active_stages
|= mesa_to_vk_shader_stage(i
);
2773 radv_hash_shaders(hash
, pStages
, pipeline
->layout
, key
, get_hash_flags(device
));
2774 memcpy(gs_copy_hash
, hash
, 20);
2775 gs_copy_hash
[0] ^= 1;
2777 bool found_in_application_cache
= true;
2778 if (modules
[MESA_SHADER_GEOMETRY
] && !keep_executable_info
&& !keep_statistic_info
) {
2779 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2780 radv_create_shader_variants_from_pipeline_cache(device
, cache
, gs_copy_hash
, variants
,
2781 &found_in_application_cache
);
2782 pipeline
->gs_copy_shader
= variants
[MESA_SHADER_GEOMETRY
];
2785 if (!keep_executable_info
&& !keep_statistic_info
&&
2786 radv_create_shader_variants_from_pipeline_cache(device
, cache
, hash
, pipeline
->shaders
,
2787 &found_in_application_cache
) &&
2788 (!modules
[MESA_SHADER_GEOMETRY
] || pipeline
->gs_copy_shader
)) {
2789 radv_stop_feedback(pipeline_feedback
, found_in_application_cache
);
2793 if (flags
& VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_EXT
) {
2794 radv_stop_feedback(pipeline_feedback
, found_in_application_cache
);
2795 return VK_PIPELINE_COMPILE_REQUIRED_EXT
;
2798 if (!modules
[MESA_SHADER_FRAGMENT
] && !modules
[MESA_SHADER_COMPUTE
]) {
2800 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
2801 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "noop_fs");
2802 fs_m
.nir
= fs_b
.shader
;
2803 modules
[MESA_SHADER_FRAGMENT
] = &fs_m
;
2806 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2807 const VkPipelineShaderStageCreateInfo
*stage
= pStages
[i
];
2808 unsigned subgroup_size
= 64, ballot_bit_size
= 64;
2813 radv_start_feedback(stage_feedbacks
[i
]);
2815 if (key
->compute_subgroup_size
) {
2816 /* Only compute shaders currently support requiring a
2817 * specific subgroup size.
2819 assert(i
== MESA_SHADER_COMPUTE
);
2820 subgroup_size
= key
->compute_subgroup_size
;
2821 ballot_bit_size
= key
->compute_subgroup_size
;
2824 nir
[i
] = radv_shader_compile_to_nir(device
, modules
[i
],
2825 stage
? stage
->pName
: "main", i
,
2826 stage
? stage
->pSpecializationInfo
: NULL
,
2827 flags
, pipeline
->layout
,
2828 subgroup_size
, ballot_bit_size
);
2830 /* We don't want to alter meta shaders IR directly so clone it
2833 if (nir
[i
]->info
.name
) {
2834 nir
[i
] = nir_shader_clone(NULL
, nir
[i
]);
2837 radv_stop_feedback(stage_feedbacks
[i
], false);
2840 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2841 nir_lower_patch_vertices(nir
[MESA_SHADER_TESS_EVAL
], nir
[MESA_SHADER_TESS_CTRL
]->info
.tess
.tcs_vertices_out
, NULL
);
2842 merge_tess_info(&nir
[MESA_SHADER_TESS_EVAL
]->info
, &nir
[MESA_SHADER_TESS_CTRL
]->info
);
2845 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
2846 radv_link_shaders(pipeline
, nir
);
2848 radv_set_linked_driver_locations(pipeline
, nir
, infos
);
2850 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2852 /* do this again since information such as outputs_read can be out-of-date */
2853 nir_shader_gather_info(nir
[i
], nir_shader_get_entrypoint(nir
[i
]));
2855 if (device
->physical_device
->use_llvm
) {
2856 NIR_PASS_V(nir
[i
], nir_lower_bool_to_int32
);
2858 NIR_PASS_V(nir
[i
], nir_lower_non_uniform_access
,
2859 nir_lower_non_uniform_ubo_access
|
2860 nir_lower_non_uniform_ssbo_access
|
2861 nir_lower_non_uniform_texture_access
|
2862 nir_lower_non_uniform_image_access
);
2867 if (nir
[MESA_SHADER_FRAGMENT
])
2868 radv_lower_fs_io(nir
[MESA_SHADER_FRAGMENT
]);
2870 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2871 if (radv_can_dump_shader(device
, modules
[i
], false))
2872 nir_print_shader(nir
[i
], stderr
);
2875 radv_fill_shader_keys(device
, keys
, key
, nir
);
2877 radv_fill_shader_info(pipeline
, pStages
, keys
, infos
, nir
);
2879 if ((nir
[MESA_SHADER_VERTEX
] &&
2880 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) ||
2881 (nir
[MESA_SHADER_TESS_EVAL
] &&
2882 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
)) {
2883 struct gfx10_ngg_info
*ngg_info
;
2885 if (nir
[MESA_SHADER_GEOMETRY
])
2886 ngg_info
= &infos
[MESA_SHADER_GEOMETRY
].ngg_info
;
2887 else if (nir
[MESA_SHADER_TESS_CTRL
])
2888 ngg_info
= &infos
[MESA_SHADER_TESS_EVAL
].ngg_info
;
2890 ngg_info
= &infos
[MESA_SHADER_VERTEX
].ngg_info
;
2892 gfx10_get_ngg_info(key
, pipeline
, nir
, infos
, ngg_info
);
2893 } else if (nir
[MESA_SHADER_GEOMETRY
]) {
2894 struct gfx9_gs_info
*gs_info
=
2895 &infos
[MESA_SHADER_GEOMETRY
].gs_ring_info
;
2897 gfx9_get_gs_info(key
, pipeline
, nir
, infos
, gs_info
);
2900 if(modules
[MESA_SHADER_GEOMETRY
]) {
2901 struct radv_shader_binary
*gs_copy_binary
= NULL
;
2902 if (!pipeline
->gs_copy_shader
&&
2903 !radv_pipeline_has_ngg(pipeline
)) {
2904 struct radv_shader_info info
= {};
2905 struct radv_shader_variant_key key
= {};
2907 key
.has_multiview_view_index
=
2908 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
;
2910 radv_nir_shader_info_pass(nir
[MESA_SHADER_GEOMETRY
],
2911 pipeline
->layout
, &key
,
2912 &info
, pipeline
->device
->physical_device
->use_llvm
);
2913 info
.wave_size
= 64; /* Wave32 not supported. */
2914 info
.ballot_bit_size
= 64;
2916 pipeline
->gs_copy_shader
= radv_create_gs_copy_shader(
2917 device
, nir
[MESA_SHADER_GEOMETRY
], &info
,
2918 &gs_copy_binary
, keep_executable_info
, keep_statistic_info
,
2919 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
);
2922 if (!keep_executable_info
&& !keep_statistic_info
&& pipeline
->gs_copy_shader
) {
2923 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2924 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2926 binaries
[MESA_SHADER_GEOMETRY
] = gs_copy_binary
;
2927 variants
[MESA_SHADER_GEOMETRY
] = pipeline
->gs_copy_shader
;
2929 radv_pipeline_cache_insert_shaders(device
, cache
,
2934 free(gs_copy_binary
);
2937 if (nir
[MESA_SHADER_FRAGMENT
]) {
2938 if (!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]) {
2939 radv_start_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
]);
2941 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] =
2942 radv_shader_variant_compile(device
, modules
[MESA_SHADER_FRAGMENT
], &nir
[MESA_SHADER_FRAGMENT
], 1,
2943 pipeline
->layout
, keys
+ MESA_SHADER_FRAGMENT
,
2944 infos
+ MESA_SHADER_FRAGMENT
,
2945 keep_executable_info
, keep_statistic_info
,
2946 &binaries
[MESA_SHADER_FRAGMENT
]);
2948 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
], false);
2952 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_TESS_CTRL
]) {
2953 if (!pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]) {
2954 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2955 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2956 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2958 radv_start_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
]);
2960 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_TESS_CTRL
], combined_nir
, 2,
2962 &key
, &infos
[MESA_SHADER_TESS_CTRL
], keep_executable_info
,
2963 keep_statistic_info
, &binaries
[MESA_SHADER_TESS_CTRL
]);
2965 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
], false);
2967 modules
[MESA_SHADER_VERTEX
] = NULL
;
2968 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2969 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2972 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_GEOMETRY
]) {
2973 gl_shader_stage pre_stage
= modules
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2974 if (!pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
2975 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2977 radv_start_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
]);
2979 pipeline
->shaders
[MESA_SHADER_GEOMETRY
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_GEOMETRY
], combined_nir
, 2,
2981 &keys
[pre_stage
], &infos
[MESA_SHADER_GEOMETRY
], keep_executable_info
,
2982 keep_statistic_info
, &binaries
[MESA_SHADER_GEOMETRY
]);
2984 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
], false);
2986 modules
[pre_stage
] = NULL
;
2989 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2990 if(modules
[i
] && !pipeline
->shaders
[i
]) {
2991 if (i
== MESA_SHADER_TESS_CTRL
) {
2992 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.ls_outputs_written
);
2994 if (i
== MESA_SHADER_TESS_EVAL
) {
2995 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2996 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2999 radv_start_feedback(stage_feedbacks
[i
]);
3001 pipeline
->shaders
[i
] = radv_shader_variant_compile(device
, modules
[i
], &nir
[i
], 1,
3003 keys
+ i
, infos
+ i
, keep_executable_info
,
3004 keep_statistic_info
, &binaries
[i
]);
3006 radv_stop_feedback(stage_feedbacks
[i
], false);
3010 if (!keep_executable_info
&& !keep_statistic_info
) {
3011 radv_pipeline_cache_insert_shaders(device
, cache
, hash
, pipeline
->shaders
,
3015 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
3018 ralloc_free(nir
[i
]);
3020 if (radv_can_dump_shader_stats(device
, modules
[i
]))
3021 radv_shader_dump_stats(device
,
3022 pipeline
->shaders
[i
],
3028 ralloc_free(fs_m
.nir
);
3030 radv_stop_feedback(pipeline_feedback
, false);
3035 radv_pipeline_stage_to_user_data_0(struct radv_pipeline
*pipeline
,
3036 gl_shader_stage stage
, enum chip_class chip_class
)
3038 bool has_gs
= radv_pipeline_has_gs(pipeline
);
3039 bool has_tess
= radv_pipeline_has_tess(pipeline
);
3040 bool has_ngg
= radv_pipeline_has_ngg(pipeline
);
3043 case MESA_SHADER_FRAGMENT
:
3044 return R_00B030_SPI_SHADER_USER_DATA_PS_0
;
3045 case MESA_SHADER_VERTEX
:
3047 if (chip_class
>= GFX10
) {
3048 return R_00B430_SPI_SHADER_USER_DATA_HS_0
;
3049 } else if (chip_class
== GFX9
) {
3050 return R_00B430_SPI_SHADER_USER_DATA_LS_0
;
3052 return R_00B530_SPI_SHADER_USER_DATA_LS_0
;
3058 if (chip_class
>= GFX10
) {
3059 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3061 return R_00B330_SPI_SHADER_USER_DATA_ES_0
;
3066 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3068 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3069 case MESA_SHADER_GEOMETRY
:
3070 return chip_class
== GFX9
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
3071 R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3072 case MESA_SHADER_COMPUTE
:
3073 return R_00B900_COMPUTE_USER_DATA_0
;
3074 case MESA_SHADER_TESS_CTRL
:
3075 return chip_class
== GFX9
? R_00B430_SPI_SHADER_USER_DATA_LS_0
:
3076 R_00B430_SPI_SHADER_USER_DATA_HS_0
;
3077 case MESA_SHADER_TESS_EVAL
:
3079 return chip_class
>= GFX10
? R_00B230_SPI_SHADER_USER_DATA_GS_0
:
3080 R_00B330_SPI_SHADER_USER_DATA_ES_0
;
3081 } else if (has_ngg
) {
3082 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3084 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3087 unreachable("unknown shader");
3091 struct radv_bin_size_entry
{
3097 radv_gfx9_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3099 static const struct radv_bin_size_entry color_size_table
[][3][9] = {
3103 /* One shader engine */
3109 { UINT_MAX
, { 0, 0}},
3112 /* Two shader engines */
3118 { UINT_MAX
, { 0, 0}},
3121 /* Four shader engines */
3126 { UINT_MAX
, { 0, 0}},
3132 /* One shader engine */
3138 { UINT_MAX
, { 0, 0}},
3141 /* Two shader engines */
3147 { UINT_MAX
, { 0, 0}},
3150 /* Four shader engines */
3157 { UINT_MAX
, { 0, 0}},
3163 /* One shader engine */
3170 { UINT_MAX
, { 0, 0}},
3173 /* Two shader engines */
3181 { UINT_MAX
, { 0, 0}},
3184 /* Four shader engines */
3192 { UINT_MAX
, { 0, 0}},
3196 static const struct radv_bin_size_entry ds_size_table
[][3][9] = {
3200 // One shader engine
3207 { UINT_MAX
, { 0, 0}},
3210 // Two shader engines
3218 { UINT_MAX
, { 0, 0}},
3221 // Four shader engines
3229 { UINT_MAX
, { 0, 0}},
3235 // One shader engine
3243 { UINT_MAX
, { 0, 0}},
3246 // Two shader engines
3255 { UINT_MAX
, { 0, 0}},
3258 // Four shader engines
3267 { UINT_MAX
, { 0, 0}},
3273 // One shader engine
3281 { UINT_MAX
, { 0, 0}},
3284 // Two shader engines
3293 { UINT_MAX
, { 0, 0}},
3296 // Four shader engines
3304 { UINT_MAX
, { 0, 0}},
3309 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3310 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3311 VkExtent2D extent
= {512, 512};
3313 unsigned log_num_rb_per_se
=
3314 util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.num_render_backends
/
3315 pipeline
->device
->physical_device
->rad_info
.max_se
);
3316 unsigned log_num_se
= util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.max_se
);
3318 unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3319 unsigned ps_iter_samples
= 1u << G_028804_PS_ITER_SAMPLES(pipeline
->graphics
.ms
.db_eqaa
);
3320 unsigned effective_samples
= total_samples
;
3321 unsigned color_bytes_per_pixel
= 0;
3323 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3324 radv_pipeline_get_color_blend_state(pCreateInfo
);
3326 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3327 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3330 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3333 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3334 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3337 /* MSAA images typically don't use all samples all the time. */
3338 if (effective_samples
>= 2 && ps_iter_samples
<= 1)
3339 effective_samples
= 2;
3340 color_bytes_per_pixel
*= effective_samples
;
3343 const struct radv_bin_size_entry
*color_entry
= color_size_table
[log_num_rb_per_se
][log_num_se
];
3344 while(color_entry
[1].bpp
<= color_bytes_per_pixel
)
3347 extent
= color_entry
->extent
;
3349 if (subpass
->depth_stencil_attachment
) {
3350 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3352 /* Coefficients taken from AMDVLK */
3353 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3354 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3355 unsigned ds_bytes_per_pixel
= 4 * (depth_coeff
+ stencil_coeff
) * total_samples
;
3357 const struct radv_bin_size_entry
*ds_entry
= ds_size_table
[log_num_rb_per_se
][log_num_se
];
3358 while(ds_entry
[1].bpp
<= ds_bytes_per_pixel
)
3361 if (ds_entry
->extent
.width
* ds_entry
->extent
.height
< extent
.width
* extent
.height
)
3362 extent
= ds_entry
->extent
;
3369 radv_gfx10_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3371 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3372 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3373 VkExtent2D extent
= {512, 512};
3375 const unsigned db_tag_size
= 64;
3376 const unsigned db_tag_count
= 312;
3377 const unsigned color_tag_size
= 1024;
3378 const unsigned color_tag_count
= 31;
3379 const unsigned fmask_tag_size
= 256;
3380 const unsigned fmask_tag_count
= 44;
3382 const unsigned rb_count
= pipeline
->device
->physical_device
->rad_info
.num_render_backends
;
3383 const unsigned pipe_count
= MAX2(rb_count
, pipeline
->device
->physical_device
->rad_info
.num_sdp_interfaces
);
3385 const unsigned db_tag_part
= (db_tag_count
* rb_count
/ pipe_count
) * db_tag_size
* pipe_count
;
3386 const unsigned color_tag_part
= (color_tag_count
* rb_count
/ pipe_count
) * color_tag_size
* pipe_count
;
3387 const unsigned fmask_tag_part
= (fmask_tag_count
* rb_count
/ pipe_count
) * fmask_tag_size
* pipe_count
;
3389 const unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3390 const unsigned samples_log
= util_logbase2_ceil(total_samples
);
3392 unsigned color_bytes_per_pixel
= 0;
3393 unsigned fmask_bytes_per_pixel
= 0;
3395 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3396 radv_pipeline_get_color_blend_state(pCreateInfo
);
3398 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3399 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3402 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3405 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3406 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3408 if (total_samples
> 1) {
3409 assert(samples_log
<= 3);
3410 const unsigned fmask_array
[] = {0, 1, 1, 4};
3411 fmask_bytes_per_pixel
+= fmask_array
[samples_log
];
3415 color_bytes_per_pixel
*= total_samples
;
3417 color_bytes_per_pixel
= MAX2(color_bytes_per_pixel
, 1);
3419 const unsigned color_pixel_count_log
= util_logbase2(color_tag_part
/ color_bytes_per_pixel
);
3420 extent
.width
= 1ull << ((color_pixel_count_log
+ 1) / 2);
3421 extent
.height
= 1ull << (color_pixel_count_log
/ 2);
3423 if (fmask_bytes_per_pixel
) {
3424 const unsigned fmask_pixel_count_log
= util_logbase2(fmask_tag_part
/ fmask_bytes_per_pixel
);
3426 const VkExtent2D fmask_extent
= (VkExtent2D
){
3427 .width
= 1ull << ((fmask_pixel_count_log
+ 1) / 2),
3428 .height
= 1ull << (color_pixel_count_log
/ 2)
3431 if (fmask_extent
.width
* fmask_extent
.height
< extent
.width
* extent
.height
)
3432 extent
= fmask_extent
;
3435 if (subpass
->depth_stencil_attachment
) {
3436 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3438 /* Coefficients taken from AMDVLK */
3439 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3440 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3441 unsigned db_bytes_per_pixel
= (depth_coeff
+ stencil_coeff
) * total_samples
;
3443 const unsigned db_pixel_count_log
= util_logbase2(db_tag_part
/ db_bytes_per_pixel
);
3445 const VkExtent2D db_extent
= (VkExtent2D
){
3446 .width
= 1ull << ((db_pixel_count_log
+ 1) / 2),
3447 .height
= 1ull << (color_pixel_count_log
/ 2)
3450 if (db_extent
.width
* db_extent
.height
< extent
.width
* extent
.height
)
3454 extent
.width
= MAX2(extent
.width
, 128);
3455 extent
.height
= MAX2(extent
.width
, 64);
3461 radv_pipeline_init_disabled_binning_state(struct radv_pipeline
*pipeline
,
3462 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3464 uint32_t pa_sc_binner_cntl_0
=
3465 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC
) |
3466 S_028C44_DISABLE_START_OF_PRIM(1);
3467 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3469 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3470 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3471 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3472 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3473 radv_pipeline_get_color_blend_state(pCreateInfo
);
3474 unsigned min_bytes_per_pixel
= 0;
3477 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3478 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3481 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3484 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3485 unsigned bytes
= vk_format_get_blocksize(format
);
3486 if (!min_bytes_per_pixel
|| bytes
< min_bytes_per_pixel
)
3487 min_bytes_per_pixel
= bytes
;
3491 pa_sc_binner_cntl_0
=
3492 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC
) |
3493 S_028C44_BIN_SIZE_X(0) |
3494 S_028C44_BIN_SIZE_Y(0) |
3495 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3496 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel
<= 4 ? 2 : 1) | /* 128 or 64 */
3497 S_028C44_DISABLE_START_OF_PRIM(1);
3500 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3501 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3504 struct radv_binning_settings
3505 radv_get_binning_settings(const struct radv_physical_device
*pdev
)
3507 struct radv_binning_settings settings
;
3508 if (pdev
->rad_info
.has_dedicated_vram
) {
3509 if (pdev
->rad_info
.num_render_backends
> 4) {
3510 settings
.context_states_per_bin
= 1;
3511 settings
.persistent_states_per_bin
= 1;
3513 settings
.context_states_per_bin
= 3;
3514 settings
.persistent_states_per_bin
= 8;
3516 settings
.fpovs_per_batch
= 63;
3518 /* The context states are affected by the scissor bug. */
3519 settings
.context_states_per_bin
= 6;
3520 /* 32 causes hangs for RAVEN. */
3521 settings
.persistent_states_per_bin
= 16;
3522 settings
.fpovs_per_batch
= 63;
3525 if (pdev
->rad_info
.has_gfx9_scissor_bug
)
3526 settings
.context_states_per_bin
= 1;
3532 radv_pipeline_init_binning_state(struct radv_pipeline
*pipeline
,
3533 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3534 const struct radv_blend_state
*blend
)
3536 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
3539 VkExtent2D bin_size
;
3540 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3541 bin_size
= radv_gfx10_compute_bin_size(pipeline
, pCreateInfo
);
3542 } else if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3543 bin_size
= radv_gfx9_compute_bin_size(pipeline
, pCreateInfo
);
3545 unreachable("Unhandled generation for binning bin size calculation");
3547 if (pipeline
->device
->pbb_allowed
&& bin_size
.width
&& bin_size
.height
) {
3548 struct radv_binning_settings settings
=
3549 radv_get_binning_settings(pipeline
->device
->physical_device
);
3551 bool disable_start_of_prim
= true;
3552 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3554 const struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3556 if (pipeline
->device
->dfsm_allowed
&& ps
&&
3557 !ps
->info
.ps
.can_discard
&&
3558 !ps
->info
.ps
.writes_memory
&&
3559 blend
->cb_target_enabled_4bit
) {
3560 db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_AUTO
);
3561 disable_start_of_prim
= (blend
->blend_enable_4bit
& blend
->cb_target_enabled_4bit
) != 0;
3564 const uint32_t pa_sc_binner_cntl_0
=
3565 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED
) |
3566 S_028C44_BIN_SIZE_X(bin_size
.width
== 16) |
3567 S_028C44_BIN_SIZE_Y(bin_size
.height
== 16) |
3568 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size
.width
, 32)) - 5) |
3569 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size
.height
, 32)) - 5) |
3570 S_028C44_CONTEXT_STATES_PER_BIN(settings
.context_states_per_bin
- 1) |
3571 S_028C44_PERSISTENT_STATES_PER_BIN(settings
.persistent_states_per_bin
- 1) |
3572 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim
) |
3573 S_028C44_FPOVS_PER_BATCH(settings
.fpovs_per_batch
) |
3574 S_028C44_OPTIMAL_BIN_SELECTION(1);
3576 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3577 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3579 radv_pipeline_init_disabled_binning_state(pipeline
, pCreateInfo
);
3584 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf
*ctx_cs
,
3585 const struct radv_pipeline
*pipeline
,
3586 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3587 const struct radv_graphics_pipeline_create_info
*extra
)
3589 const VkPipelineDepthStencilStateCreateInfo
*vkds
= radv_pipeline_get_depth_stencil_state(pCreateInfo
);
3590 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3591 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3592 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3593 struct radv_render_pass_attachment
*attachment
= NULL
;
3594 uint32_t db_render_control
= 0, db_render_override2
= 0;
3595 uint32_t db_render_override
= 0;
3597 if (subpass
->depth_stencil_attachment
)
3598 attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3600 bool has_depth_attachment
= attachment
&& vk_format_is_depth(attachment
->format
);
3602 if (vkds
&& has_depth_attachment
) {
3603 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3604 db_render_override2
|= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment
->samples
> 2);
3606 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
)
3607 db_render_override2
|= S_028010_CENTROID_COMPUTATION_MODE_GFX103(2);
3610 if (attachment
&& extra
) {
3611 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(extra
->db_depth_clear
);
3612 db_render_control
|= S_028000_STENCIL_CLEAR_ENABLE(extra
->db_stencil_clear
);
3614 db_render_control
|= S_028000_RESUMMARIZE_ENABLE(extra
->resummarize_enable
);
3615 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(extra
->depth_compress_disable
);
3616 db_render_control
|= S_028000_STENCIL_COMPRESS_DISABLE(extra
->stencil_compress_disable
);
3617 db_render_override2
|= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra
->db_depth_disable_expclear
);
3618 db_render_override2
|= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra
->db_stencil_disable_expclear
);
3621 db_render_override
|= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
3622 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
3624 if (!pCreateInfo
->pRasterizationState
->depthClampEnable
&&
3625 ps
->info
.ps
.writes_z
) {
3626 /* From VK_EXT_depth_range_unrestricted spec:
3628 * "The behavior described in Primitive Clipping still applies.
3629 * If depth clamping is disabled the depth values are still
3630 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3631 * depth clamping is enabled the above equation is ignored and
3632 * the depth values are instead clamped to the VkViewport
3633 * minDepth and maxDepth values, which in the case of this
3634 * extension can be outside of the 0.0 to 1.0 range."
3636 db_render_override
|= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3639 radeon_set_context_reg(ctx_cs
, R_028000_DB_RENDER_CONTROL
, db_render_control
);
3640 radeon_set_context_reg(ctx_cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
3641 radeon_set_context_reg(ctx_cs
, R_028010_DB_RENDER_OVERRIDE2
, db_render_override2
);
3645 radv_pipeline_generate_blend_state(struct radeon_cmdbuf
*ctx_cs
,
3646 const struct radv_pipeline
*pipeline
,
3647 const struct radv_blend_state
*blend
)
3649 radeon_set_context_reg_seq(ctx_cs
, R_028780_CB_BLEND0_CONTROL
, 8);
3650 radeon_emit_array(ctx_cs
, blend
->cb_blend_control
,
3652 radeon_set_context_reg(ctx_cs
, R_028808_CB_COLOR_CONTROL
, blend
->cb_color_control
);
3653 radeon_set_context_reg(ctx_cs
, R_028B70_DB_ALPHA_TO_MASK
, blend
->db_alpha_to_mask
);
3655 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
3657 radeon_set_context_reg_seq(ctx_cs
, R_028760_SX_MRT0_BLEND_OPT
, 8);
3658 radeon_emit_array(ctx_cs
, blend
->sx_mrt_blend_opt
, 8);
3661 radeon_set_context_reg(ctx_cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
3663 radeon_set_context_reg(ctx_cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
3664 radeon_set_context_reg(ctx_cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
3668 radv_pipeline_generate_raster_state(struct radeon_cmdbuf
*ctx_cs
,
3669 const struct radv_pipeline
*pipeline
,
3670 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3672 const VkPipelineRasterizationStateCreateInfo
*vkraster
= pCreateInfo
->pRasterizationState
;
3673 const VkConservativeRasterizationModeEXT mode
=
3674 radv_get_conservative_raster_mode(vkraster
);
3675 uint32_t pa_sc_conservative_rast
= S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3676 bool depth_clip_disable
= vkraster
->depthClampEnable
;
3678 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*depth_clip_state
=
3679 vk_find_struct_const(vkraster
->pNext
, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
3680 if (depth_clip_state
) {
3681 depth_clip_disable
= !depth_clip_state
->depthClipEnable
;
3684 radeon_set_context_reg(ctx_cs
, R_028810_PA_CL_CLIP_CNTL
,
3685 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3686 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable
? 1 : 0) |
3687 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable
? 1 : 0) |
3688 S_028810_DX_RASTERIZATION_KILL(vkraster
->rasterizerDiscardEnable
? 1 : 0) |
3689 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3691 radeon_set_context_reg(ctx_cs
, R_028BDC_PA_SC_LINE_CNTL
,
3692 S_028BDC_DX10_DIAMOND_TEST_ENA(1));
3694 /* Conservative rasterization. */
3695 if (mode
!= VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
) {
3696 pa_sc_conservative_rast
= S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3697 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3698 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3700 if (mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT
) {
3701 pa_sc_conservative_rast
|=
3702 S_028C4C_OVER_RAST_ENABLE(1) |
3703 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3704 S_028C4C_UNDER_RAST_ENABLE(0) |
3705 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3706 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3708 assert(mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT
);
3709 pa_sc_conservative_rast
|=
3710 S_028C4C_OVER_RAST_ENABLE(0) |
3711 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3712 S_028C4C_UNDER_RAST_ENABLE(1) |
3713 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3714 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3718 radeon_set_context_reg(ctx_cs
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
3719 pa_sc_conservative_rast
);
3724 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf
*ctx_cs
,
3725 const struct radv_pipeline
*pipeline
)
3727 const struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3729 radeon_set_context_reg_seq(ctx_cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
3730 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[0]);
3731 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[1]);
3733 radeon_set_context_reg(ctx_cs
, R_028804_DB_EQAA
, ms
->db_eqaa
);
3734 radeon_set_context_reg(ctx_cs
, R_028A48_PA_SC_MODE_CNTL_0
, ms
->pa_sc_mode_cntl_0
);
3735 radeon_set_context_reg(ctx_cs
, R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
3736 radeon_set_context_reg(ctx_cs
, R_028BE0_PA_SC_AA_CONFIG
, ms
->pa_sc_aa_config
);
3738 /* The exclusion bits can be set to improve rasterization efficiency
3739 * if no sample lies on the pixel boundary (-8 sample offset). It's
3740 * currently always TRUE because the driver doesn't support 16 samples.
3742 bool exclusion
= pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
3743 radeon_set_context_reg(ctx_cs
, R_02882C_PA_SU_PRIM_FILTER_CNTL
,
3744 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) |
3745 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3747 /* GFX9: Flush DFSM when the AA mode changes. */
3748 if (pipeline
->device
->dfsm_allowed
) {
3749 radeon_emit(ctx_cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3750 radeon_emit(ctx_cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3755 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf
*ctx_cs
,
3756 const struct radv_pipeline
*pipeline
)
3758 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3759 const struct radv_shader_variant
*vs
=
3760 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] ?
3761 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] :
3762 pipeline
->shaders
[MESA_SHADER_VERTEX
];
3763 unsigned vgt_primitiveid_en
= 0;
3764 uint32_t vgt_gs_mode
= 0;
3766 if (radv_pipeline_has_ngg(pipeline
))
3769 if (radv_pipeline_has_gs(pipeline
)) {
3770 const struct radv_shader_variant
*gs
=
3771 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3773 vgt_gs_mode
= ac_vgt_gs_mode(gs
->info
.gs
.vertices_out
,
3774 pipeline
->device
->physical_device
->rad_info
.chip_class
);
3775 } else if (outinfo
->export_prim_id
|| vs
->info
.uses_prim_id
) {
3776 vgt_gs_mode
= S_028A40_MODE(V_028A40_GS_SCENARIO_A
);
3777 vgt_primitiveid_en
|= S_028A84_PRIMITIVEID_EN(1);
3780 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
, vgt_primitiveid_en
);
3781 radeon_set_context_reg(ctx_cs
, R_028A40_VGT_GS_MODE
, vgt_gs_mode
);
3785 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf
*ctx_cs
,
3786 struct radeon_cmdbuf
*cs
,
3787 const struct radv_pipeline
*pipeline
,
3788 const struct radv_shader_variant
*shader
)
3790 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3792 radeon_set_sh_reg_seq(cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
3793 radeon_emit(cs
, va
>> 8);
3794 radeon_emit(cs
, S_00B124_MEM_BASE(va
>> 40));
3795 radeon_emit(cs
, shader
->config
.rsrc1
);
3796 radeon_emit(cs
, shader
->config
.rsrc2
);
3798 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3799 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3800 clip_dist_mask
= outinfo
->clip_dist_mask
;
3801 cull_dist_mask
= outinfo
->cull_dist_mask
;
3802 total_mask
= clip_dist_mask
| cull_dist_mask
;
3803 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3804 outinfo
->writes_layer
||
3805 outinfo
->writes_viewport_index
;
3806 unsigned spi_vs_out_config
, nparams
;
3808 /* VS is required to export at least one param. */
3809 nparams
= MAX2(outinfo
->param_exports
, 1);
3810 spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
3812 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3813 spi_vs_out_config
|= S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0);
3816 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
, spi_vs_out_config
);
3818 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3819 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3820 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3821 V_02870C_SPI_SHADER_4COMP
:
3822 V_02870C_SPI_SHADER_NONE
) |
3823 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3824 V_02870C_SPI_SHADER_4COMP
:
3825 V_02870C_SPI_SHADER_NONE
) |
3826 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3827 V_02870C_SPI_SHADER_4COMP
:
3828 V_02870C_SPI_SHADER_NONE
));
3830 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3831 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3832 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3833 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3834 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3835 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3836 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3837 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3838 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
) |
3839 cull_dist_mask
<< 8 |
3842 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
3843 radeon_set_context_reg(ctx_cs
, R_028AB4_VGT_REUSE_OFF
,
3844 outinfo
->writes_viewport_index
);
3848 radv_pipeline_generate_hw_es(struct radeon_cmdbuf
*cs
,
3849 const struct radv_pipeline
*pipeline
,
3850 const struct radv_shader_variant
*shader
)
3852 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3854 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
3855 radeon_emit(cs
, va
>> 8);
3856 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3857 radeon_emit(cs
, shader
->config
.rsrc1
);
3858 radeon_emit(cs
, shader
->config
.rsrc2
);
3862 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf
*cs
,
3863 const struct radv_pipeline
*pipeline
,
3864 const struct radv_shader_variant
*shader
)
3866 unsigned num_lds_blocks
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_lds_blocks
;
3867 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3868 uint32_t rsrc2
= shader
->config
.rsrc2
;
3870 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
3871 radeon_emit(cs
, va
>> 8);
3872 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
3874 rsrc2
|= S_00B52C_LDS_SIZE(num_lds_blocks
);
3875 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX7
&&
3876 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
3877 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
3879 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
3880 radeon_emit(cs
, shader
->config
.rsrc1
);
3881 radeon_emit(cs
, rsrc2
);
3885 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf
*ctx_cs
,
3886 struct radeon_cmdbuf
*cs
,
3887 const struct radv_pipeline
*pipeline
,
3888 const struct radv_shader_variant
*shader
)
3890 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3891 gl_shader_stage es_type
=
3892 radv_pipeline_has_tess(pipeline
) ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
3893 struct radv_shader_variant
*es
=
3894 es_type
== MESA_SHADER_TESS_EVAL
? pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] : pipeline
->shaders
[MESA_SHADER_VERTEX
];
3895 const struct gfx10_ngg_info
*ngg_state
= &shader
->info
.ngg_info
;
3897 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
3898 radeon_emit(cs
, va
>> 8);
3899 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3900 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
3901 radeon_emit(cs
, shader
->config
.rsrc1
);
3902 radeon_emit(cs
, shader
->config
.rsrc2
);
3904 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3905 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3906 clip_dist_mask
= outinfo
->clip_dist_mask
;
3907 cull_dist_mask
= outinfo
->cull_dist_mask
;
3908 total_mask
= clip_dist_mask
| cull_dist_mask
;
3909 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3910 outinfo
->writes_layer
||
3911 outinfo
->writes_viewport_index
;
3912 bool es_enable_prim_id
= outinfo
->export_prim_id
||
3913 (es
&& es
->info
.uses_prim_id
);
3914 bool break_wave_at_eoi
= false;
3918 if (es_type
== MESA_SHADER_TESS_EVAL
) {
3919 struct radv_shader_variant
*gs
=
3920 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3922 if (es_enable_prim_id
|| (gs
&& gs
->info
.uses_prim_id
))
3923 break_wave_at_eoi
= true;
3926 nparams
= MAX2(outinfo
->param_exports
, 1);
3927 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
3928 S_0286C4_VS_EXPORT_COUNT(nparams
- 1) |
3929 S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0));
3931 radeon_set_context_reg(ctx_cs
, R_028708_SPI_SHADER_IDX_FORMAT
,
3932 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP
));
3933 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3934 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3935 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3936 V_02870C_SPI_SHADER_4COMP
:
3937 V_02870C_SPI_SHADER_NONE
) |
3938 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3939 V_02870C_SPI_SHADER_4COMP
:
3940 V_02870C_SPI_SHADER_NONE
) |
3941 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3942 V_02870C_SPI_SHADER_4COMP
:
3943 V_02870C_SPI_SHADER_NONE
));
3945 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3946 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3947 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3948 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3949 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3950 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3951 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3952 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3953 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
) |
3954 cull_dist_mask
<< 8 |
3957 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
,
3958 S_028A84_PRIMITIVEID_EN(es_enable_prim_id
) |
3959 S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo
->export_prim_id
));
3961 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
3962 ngg_state
->vgt_esgs_ring_itemsize
);
3964 /* NGG specific registers. */
3965 struct radv_shader_variant
*gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3966 uint32_t gs_num_invocations
= gs
? gs
->info
.gs
.invocations
: 1;
3968 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
3969 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state
->hw_max_esverts
) |
3970 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state
->max_gsprims
) |
3971 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state
->max_gsprims
* gs_num_invocations
));
3972 radeon_set_context_reg(ctx_cs
, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP
,
3973 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state
->max_out_verts
));
3974 radeon_set_context_reg(ctx_cs
, R_028B4C_GE_NGG_SUBGRP_CNTL
,
3975 S_028B4C_PRIM_AMP_FACTOR(ngg_state
->prim_amp_factor
) |
3976 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
3977 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
3978 S_028B90_CNT(gs_num_invocations
) |
3979 S_028B90_ENABLE(gs_num_invocations
> 1) |
3980 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state
->max_vert_out_per_gs_instance
));
3982 /* User edge flags are set by the pos exports. If user edge flags are
3983 * not used, we must use hw-generated edge flags and pass them via
3984 * the prim export to prevent drawing lines on internal edges of
3985 * decomposed primitives (such as quads) with polygon mode = lines.
3987 * TODO: We should combine hw-generated edge flags with user edge
3988 * flags in the shader.
3990 radeon_set_context_reg(ctx_cs
, R_028838_PA_CL_NGG_CNTL
,
3991 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline
) &&
3992 !radv_pipeline_has_gs(pipeline
)) |
3993 /* Reuse for NGG. */
3994 S_028838_VERTEX_REUSE_DEPTH_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
? 30 : 0));
3996 ge_cntl
= S_03096C_PRIM_GRP_SIZE(ngg_state
->max_gsprims
) |
3997 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
3998 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
);
4000 /* Bug workaround for a possible hang with non-tessellation cases.
4001 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
4003 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
4005 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX10
&&
4006 !radv_pipeline_has_tess(pipeline
) &&
4007 ngg_state
->hw_max_esverts
!= 256) {
4008 ge_cntl
&= C_03096C_VERT_GRP_SIZE
;
4010 if (ngg_state
->hw_max_esverts
> 5) {
4011 ge_cntl
|= S_03096C_VERT_GRP_SIZE(ngg_state
->hw_max_esverts
- 5);
4015 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
, ge_cntl
);
4019 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf
*cs
,
4020 const struct radv_pipeline
*pipeline
,
4021 const struct radv_shader_variant
*shader
)
4023 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
4025 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4026 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4027 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
4028 radeon_emit(cs
, va
>> 8);
4029 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
4031 radeon_set_sh_reg_seq(cs
, R_00B410_SPI_SHADER_PGM_LO_LS
, 2);
4032 radeon_emit(cs
, va
>> 8);
4033 radeon_emit(cs
, S_00B414_MEM_BASE(va
>> 40));
4036 radeon_set_sh_reg_seq(cs
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
, 2);
4037 radeon_emit(cs
, shader
->config
.rsrc1
);
4038 radeon_emit(cs
, shader
->config
.rsrc2
);
4040 radeon_set_sh_reg_seq(cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
4041 radeon_emit(cs
, va
>> 8);
4042 radeon_emit(cs
, S_00B424_MEM_BASE(va
>> 40));
4043 radeon_emit(cs
, shader
->config
.rsrc1
);
4044 radeon_emit(cs
, shader
->config
.rsrc2
);
4049 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf
*ctx_cs
,
4050 struct radeon_cmdbuf
*cs
,
4051 const struct radv_pipeline
*pipeline
)
4053 struct radv_shader_variant
*vs
;
4055 /* Skip shaders merged into HS/GS */
4056 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
4060 if (vs
->info
.vs
.as_ls
)
4061 radv_pipeline_generate_hw_ls(cs
, pipeline
, vs
);
4062 else if (vs
->info
.vs
.as_es
)
4063 radv_pipeline_generate_hw_es(cs
, pipeline
, vs
);
4064 else if (vs
->info
.is_ngg
)
4065 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, vs
);
4067 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, vs
);
4071 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf
*ctx_cs
,
4072 struct radeon_cmdbuf
*cs
,
4073 const struct radv_pipeline
*pipeline
)
4075 struct radv_shader_variant
*tes
, *tcs
;
4077 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
4078 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
4081 if (tes
->info
.is_ngg
) {
4082 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, tes
);
4083 } else if (tes
->info
.tes
.as_es
)
4084 radv_pipeline_generate_hw_es(cs
, pipeline
, tes
);
4086 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, tes
);
4089 radv_pipeline_generate_hw_hs(cs
, pipeline
, tcs
);
4091 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
4092 !radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
4093 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4094 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4095 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4096 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4101 radv_pipeline_generate_tess_state(struct radeon_cmdbuf
*ctx_cs
,
4102 const struct radv_pipeline
*pipeline
,
4103 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4105 struct radv_shader_variant
*tes
= radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
);
4106 unsigned type
= 0, partitioning
= 0, topology
= 0, distribution_mode
= 0;
4107 unsigned num_tcs_input_cp
, num_tcs_output_cp
, num_patches
;
4108 unsigned ls_hs_config
;
4110 num_tcs_input_cp
= pCreateInfo
->pTessellationState
->patchControlPoints
;
4111 num_tcs_output_cp
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.tcs_vertices_out
; //TCS VERTICES OUT
4112 num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
4114 ls_hs_config
= S_028B58_NUM_PATCHES(num_patches
) |
4115 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
4116 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
4118 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4119 radeon_set_context_reg_idx(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
,
4122 radeon_set_context_reg(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
,
4126 switch (tes
->info
.tes
.primitive_mode
) {
4128 type
= V_028B6C_TESS_TRIANGLE
;
4131 type
= V_028B6C_TESS_QUAD
;
4134 type
= V_028B6C_TESS_ISOLINE
;
4138 switch (tes
->info
.tes
.spacing
) {
4139 case TESS_SPACING_EQUAL
:
4140 partitioning
= V_028B6C_PART_INTEGER
;
4142 case TESS_SPACING_FRACTIONAL_ODD
:
4143 partitioning
= V_028B6C_PART_FRAC_ODD
;
4145 case TESS_SPACING_FRACTIONAL_EVEN
:
4146 partitioning
= V_028B6C_PART_FRAC_EVEN
;
4152 bool ccw
= tes
->info
.tes
.ccw
;
4153 const VkPipelineTessellationDomainOriginStateCreateInfo
*domain_origin_state
=
4154 vk_find_struct_const(pCreateInfo
->pTessellationState
,
4155 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO
);
4157 if (domain_origin_state
&& domain_origin_state
->domainOrigin
!= VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT
)
4160 if (tes
->info
.tes
.point_mode
)
4161 topology
= V_028B6C_OUTPUT_POINT
;
4162 else if (tes
->info
.tes
.primitive_mode
== GL_ISOLINES
)
4163 topology
= V_028B6C_OUTPUT_LINE
;
4165 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
4167 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
4169 if (pipeline
->device
->physical_device
->rad_info
.has_distributed_tess
) {
4170 if (pipeline
->device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
4171 pipeline
->device
->physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
4172 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
4174 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
4176 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
4178 radeon_set_context_reg(ctx_cs
, R_028B6C_VGT_TF_PARAM
,
4179 S_028B6C_TYPE(type
) |
4180 S_028B6C_PARTITIONING(partitioning
) |
4181 S_028B6C_TOPOLOGY(topology
) |
4182 S_028B6C_DISTRIBUTION_MODE(distribution_mode
));
4186 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf
*ctx_cs
,
4187 struct radeon_cmdbuf
*cs
,
4188 const struct radv_pipeline
*pipeline
,
4189 const struct radv_shader_variant
*gs
)
4191 const struct gfx9_gs_info
*gs_state
= &gs
->info
.gs_ring_info
;
4192 unsigned gs_max_out_vertices
;
4193 const uint8_t *num_components
;
4198 gs_max_out_vertices
= gs
->info
.gs
.vertices_out
;
4199 max_stream
= gs
->info
.gs
.max_stream
;
4200 num_components
= gs
->info
.gs
.num_stream_output_components
;
4202 offset
= num_components
[0] * gs_max_out_vertices
;
4204 radeon_set_context_reg_seq(ctx_cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
4205 radeon_emit(ctx_cs
, offset
);
4206 if (max_stream
>= 1)
4207 offset
+= num_components
[1] * gs_max_out_vertices
;
4208 radeon_emit(ctx_cs
, offset
);
4209 if (max_stream
>= 2)
4210 offset
+= num_components
[2] * gs_max_out_vertices
;
4211 radeon_emit(ctx_cs
, offset
);
4212 if (max_stream
>= 3)
4213 offset
+= num_components
[3] * gs_max_out_vertices
;
4214 radeon_set_context_reg(ctx_cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
4216 radeon_set_context_reg_seq(ctx_cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
4217 radeon_emit(ctx_cs
, num_components
[0]);
4218 radeon_emit(ctx_cs
, (max_stream
>= 1) ? num_components
[1] : 0);
4219 radeon_emit(ctx_cs
, (max_stream
>= 2) ? num_components
[2] : 0);
4220 radeon_emit(ctx_cs
, (max_stream
>= 3) ? num_components
[3] : 0);
4222 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
4223 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
4224 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
4225 S_028B90_ENABLE(gs_num_invocations
> 0));
4227 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
4228 gs_state
->vgt_esgs_ring_itemsize
);
4230 va
= radv_buffer_get_va(gs
->bo
) + gs
->bo_offset
;
4232 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4233 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4234 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
4235 radeon_emit(cs
, va
>> 8);
4236 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
4238 radeon_set_sh_reg_seq(cs
, R_00B210_SPI_SHADER_PGM_LO_ES
, 2);
4239 radeon_emit(cs
, va
>> 8);
4240 radeon_emit(cs
, S_00B214_MEM_BASE(va
>> 40));
4243 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
4244 radeon_emit(cs
, gs
->config
.rsrc1
);
4245 radeon_emit(cs
, gs
->config
.rsrc2
| S_00B22C_LDS_SIZE(gs_state
->lds_size
));
4247 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
, gs_state
->vgt_gs_onchip_cntl
);
4248 radeon_set_context_reg(ctx_cs
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
, gs_state
->vgt_gs_max_prims_per_subgroup
);
4250 radeon_set_sh_reg_seq(cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
4251 radeon_emit(cs
, va
>> 8);
4252 radeon_emit(cs
, S_00B224_MEM_BASE(va
>> 40));
4253 radeon_emit(cs
, gs
->config
.rsrc1
);
4254 radeon_emit(cs
, gs
->config
.rsrc2
);
4257 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, pipeline
->gs_copy_shader
);
4261 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf
*ctx_cs
,
4262 struct radeon_cmdbuf
*cs
,
4263 const struct radv_pipeline
*pipeline
)
4265 struct radv_shader_variant
*gs
;
4267 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4271 if (gs
->info
.is_ngg
)
4272 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, gs
);
4274 radv_pipeline_generate_hw_gs(ctx_cs
, cs
, pipeline
, gs
);
4276 radeon_set_context_reg(ctx_cs
, R_028B38_VGT_GS_MAX_VERT_OUT
,
4277 gs
->info
.gs
.vertices_out
);
4280 static uint32_t offset_to_ps_input(uint32_t offset
, bool flat_shade
,
4281 bool explicit, bool float16
)
4283 uint32_t ps_input_cntl
;
4284 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
4285 ps_input_cntl
= S_028644_OFFSET(offset
);
4286 if (flat_shade
|| explicit)
4287 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
4289 /* Force parameter cache to be read in passthrough
4292 ps_input_cntl
|= S_028644_OFFSET(1 << 5);
4295 ps_input_cntl
|= S_028644_FP16_INTERP_MODE(1) |
4296 S_028644_ATTR0_VALID(1);
4299 /* The input is a DEFAULT_VAL constant. */
4300 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
4301 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
4302 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
4303 ps_input_cntl
= S_028644_OFFSET(0x20) |
4304 S_028644_DEFAULT_VAL(offset
);
4306 return ps_input_cntl
;
4310 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf
*ctx_cs
,
4311 const struct radv_pipeline
*pipeline
)
4313 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4314 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
4315 uint32_t ps_input_cntl
[32];
4317 unsigned ps_offset
= 0;
4319 if (ps
->info
.ps
.prim_id_input
) {
4320 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
];
4321 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4322 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4327 if (ps
->info
.ps
.layer_input
||
4328 ps
->info
.needs_multiview_view_index
) {
4329 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
];
4330 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
4331 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4333 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false, false);
4337 if (ps
->info
.ps
.viewport_index_input
) {
4338 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VIEWPORT
];
4339 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
4340 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4342 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false, false);
4346 if (ps
->info
.ps
.has_pcoord
) {
4348 val
= S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4349 ps_input_cntl
[ps_offset
] = val
;
4353 if (ps
->info
.ps
.num_input_clips_culls
) {
4356 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST0
];
4357 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4358 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false, false);
4362 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST1
];
4363 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
&&
4364 ps
->info
.ps
.num_input_clips_culls
> 4) {
4365 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false, false);
4370 for (unsigned i
= 0; i
< 32 && (1u << i
) <= ps
->info
.ps
.input_mask
; ++i
) {
4375 if (!(ps
->info
.ps
.input_mask
& (1u << i
)))
4378 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VAR0
+ i
];
4379 if (vs_offset
== AC_EXP_PARAM_UNDEFINED
) {
4380 ps_input_cntl
[ps_offset
] = S_028644_OFFSET(0x20);
4385 flat_shade
= !!(ps
->info
.ps
.flat_shaded_mask
& (1u << ps_offset
));
4386 explicit = !!(ps
->info
.ps
.explicit_shaded_mask
& (1u << ps_offset
));
4387 float16
= !!(ps
->info
.ps
.float16_shaded_mask
& (1u << ps_offset
));
4389 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, flat_shade
, explicit, float16
);
4394 radeon_set_context_reg_seq(ctx_cs
, R_028644_SPI_PS_INPUT_CNTL_0
, ps_offset
);
4395 for (unsigned i
= 0; i
< ps_offset
; i
++) {
4396 radeon_emit(ctx_cs
, ps_input_cntl
[i
]);
4402 radv_compute_db_shader_control(const struct radv_device
*device
,
4403 const struct radv_pipeline
*pipeline
,
4404 const struct radv_shader_variant
*ps
)
4406 unsigned conservative_z_export
= V_02880C_EXPORT_ANY_Z
;
4408 if (ps
->info
.ps
.early_fragment_test
|| !ps
->info
.ps
.writes_memory
)
4409 z_order
= V_02880C_EARLY_Z_THEN_LATE_Z
;
4411 z_order
= V_02880C_LATE_Z
;
4413 if (ps
->info
.ps
.depth_layout
== FRAG_DEPTH_LAYOUT_GREATER
)
4414 conservative_z_export
= V_02880C_EXPORT_GREATER_THAN_Z
;
4415 else if (ps
->info
.ps
.depth_layout
== FRAG_DEPTH_LAYOUT_LESS
)
4416 conservative_z_export
= V_02880C_EXPORT_LESS_THAN_Z
;
4418 bool disable_rbplus
= device
->physical_device
->rad_info
.has_rbplus
&&
4419 !device
->physical_device
->rad_info
.rbplus_allowed
;
4421 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4422 * but this appears to break Project Cars (DXVK). See
4423 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4425 bool mask_export_enable
= ps
->info
.ps
.writes_sample_mask
;
4427 return S_02880C_Z_EXPORT_ENABLE(ps
->info
.ps
.writes_z
) |
4428 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps
->info
.ps
.writes_stencil
) |
4429 S_02880C_KILL_ENABLE(!!ps
->info
.ps
.can_discard
) |
4430 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable
) |
4431 S_02880C_CONSERVATIVE_Z_EXPORT(conservative_z_export
) |
4432 S_02880C_Z_ORDER(z_order
) |
4433 S_02880C_DEPTH_BEFORE_SHADER(ps
->info
.ps
.early_fragment_test
) |
4434 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps
->info
.ps
.post_depth_coverage
) |
4435 S_02880C_EXEC_ON_HIER_FAIL(ps
->info
.ps
.writes_memory
) |
4436 S_02880C_EXEC_ON_NOOP(ps
->info
.ps
.writes_memory
) |
4437 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus
);
4441 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf
*ctx_cs
,
4442 struct radeon_cmdbuf
*cs
,
4443 struct radv_pipeline
*pipeline
)
4445 struct radv_shader_variant
*ps
;
4447 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
4449 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4450 va
= radv_buffer_get_va(ps
->bo
) + ps
->bo_offset
;
4452 radeon_set_sh_reg_seq(cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
4453 radeon_emit(cs
, va
>> 8);
4454 radeon_emit(cs
, S_00B024_MEM_BASE(va
>> 40));
4455 radeon_emit(cs
, ps
->config
.rsrc1
);
4456 radeon_emit(cs
, ps
->config
.rsrc2
);
4458 radeon_set_context_reg(ctx_cs
, R_02880C_DB_SHADER_CONTROL
,
4459 radv_compute_db_shader_control(pipeline
->device
,
4462 radeon_set_context_reg(ctx_cs
, R_0286CC_SPI_PS_INPUT_ENA
,
4463 ps
->config
.spi_ps_input_ena
);
4465 radeon_set_context_reg(ctx_cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
4466 ps
->config
.spi_ps_input_addr
);
4468 radeon_set_context_reg(ctx_cs
, R_0286D8_SPI_PS_IN_CONTROL
,
4469 S_0286D8_NUM_INTERP(ps
->info
.ps
.num_interp
) |
4470 S_0286D8_PS_W32_EN(ps
->info
.wave_size
== 32));
4472 radeon_set_context_reg(ctx_cs
, R_0286E0_SPI_BARYC_CNTL
, pipeline
->graphics
.spi_baryc_cntl
);
4474 radeon_set_context_reg(ctx_cs
, R_028710_SPI_SHADER_Z_FORMAT
,
4475 ac_get_spi_shader_z_format(ps
->info
.ps
.writes_z
,
4476 ps
->info
.ps
.writes_stencil
,
4477 ps
->info
.ps
.writes_sample_mask
));
4479 if (pipeline
->device
->dfsm_allowed
) {
4480 /* optimise this? */
4481 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
4482 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
4487 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf
*ctx_cs
,
4488 const struct radv_pipeline
*pipeline
)
4490 if (pipeline
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4491 pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
4494 unsigned vtx_reuse_depth
= 30;
4495 if (radv_pipeline_has_tess(pipeline
) &&
4496 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.tes
.spacing
== TESS_SPACING_FRACTIONAL_ODD
) {
4497 vtx_reuse_depth
= 14;
4499 radeon_set_context_reg(ctx_cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
4500 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth
));
4504 radv_pipeline_generate_vgt_shader_config(struct radeon_cmdbuf
*ctx_cs
,
4505 const struct radv_pipeline
*pipeline
)
4507 uint32_t stages
= 0;
4508 if (radv_pipeline_has_tess(pipeline
)) {
4509 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
4510 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4512 if (radv_pipeline_has_gs(pipeline
))
4513 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
4515 else if (radv_pipeline_has_ngg(pipeline
))
4516 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
4518 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
4519 } else if (radv_pipeline_has_gs(pipeline
)) {
4520 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
4522 } else if (radv_pipeline_has_ngg(pipeline
)) {
4523 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
4526 if (radv_pipeline_has_ngg(pipeline
)) {
4527 stages
|= S_028B54_PRIMGEN_EN(1);
4528 if (pipeline
->streamout_shader
)
4529 stages
|= S_028B54_NGG_WAVE_ID_EN(1);
4530 if (radv_pipeline_has_ngg_passthrough(pipeline
))
4531 stages
|= S_028B54_PRIMGEN_PASSTHRU_EN(1);
4532 } else if (radv_pipeline_has_gs(pipeline
)) {
4533 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
4536 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
4537 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4539 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4540 uint8_t hs_size
= 64, gs_size
= 64, vs_size
= 64;
4542 if (radv_pipeline_has_tess(pipeline
))
4543 hs_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.wave_size
;
4545 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
4546 vs_size
= gs_size
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.wave_size
;
4547 if (pipeline
->gs_copy_shader
)
4548 vs_size
= pipeline
->gs_copy_shader
->info
.wave_size
;
4549 } else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
4550 vs_size
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.wave_size
;
4551 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
4552 vs_size
= pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.wave_size
;
4554 if (radv_pipeline_has_ngg(pipeline
))
4557 /* legacy GS only supports Wave64 */
4558 stages
|= S_028B54_HS_W32_EN(hs_size
== 32 ? 1 : 0) |
4559 S_028B54_GS_W32_EN(gs_size
== 32 ? 1 : 0) |
4560 S_028B54_VS_W32_EN(vs_size
== 32 ? 1 : 0);
4563 radeon_set_context_reg(ctx_cs
, R_028B54_VGT_SHADER_STAGES_EN
, stages
);
4567 radv_pipeline_generate_cliprect_rule(struct radeon_cmdbuf
*ctx_cs
,
4568 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4570 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
4571 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
4572 uint32_t cliprect_rule
= 0;
4574 if (!discard_rectangle_info
) {
4575 cliprect_rule
= 0xffff;
4577 for (unsigned i
= 0; i
< (1u << MAX_DISCARD_RECTANGLES
); ++i
) {
4578 /* Interpret i as a bitmask, and then set the bit in
4579 * the mask if that combination of rectangles in which
4580 * the pixel is contained should pass the cliprect
4583 unsigned relevant_subset
= i
& ((1u << discard_rectangle_info
->discardRectangleCount
) - 1);
4585 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT
&&
4589 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT
&&
4593 cliprect_rule
|= 1u << i
;
4597 radeon_set_context_reg(ctx_cs
, R_02820C_PA_SC_CLIPRECT_RULE
, cliprect_rule
);
4601 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf
*ctx_cs
,
4602 struct radv_pipeline
*pipeline
)
4604 bool break_wave_at_eoi
= false;
4605 unsigned primgroup_size
;
4606 unsigned vertgroup_size
= 256; /* 256 = disable vertex grouping */
4608 if (radv_pipeline_has_tess(pipeline
)) {
4609 primgroup_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
4610 } else if (radv_pipeline_has_gs(pipeline
)) {
4611 const struct gfx9_gs_info
*gs_state
=
4612 &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs_ring_info
;
4613 unsigned vgt_gs_onchip_cntl
= gs_state
->vgt_gs_onchip_cntl
;
4614 primgroup_size
= G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl
);
4616 primgroup_size
= 128; /* recommended without a GS and tess */
4619 if (radv_pipeline_has_tess(pipeline
)) {
4620 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4621 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4622 break_wave_at_eoi
= true;
4625 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
,
4626 S_03096C_PRIM_GRP_SIZE(primgroup_size
) |
4627 S_03096C_VERT_GRP_SIZE(vertgroup_size
) |
4628 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4629 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
));
4633 radv_pipeline_generate_vgt_gs_out(struct radeon_cmdbuf
*ctx_cs
,
4634 const struct radv_pipeline
*pipeline
,
4635 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4636 const struct radv_graphics_pipeline_create_info
*extra
)
4640 if (radv_pipeline_has_gs(pipeline
)) {
4641 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs
.output_prim
);
4642 } else if (radv_pipeline_has_tess(pipeline
)) {
4643 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.point_mode
) {
4644 gs_out
= V_028A6C_OUTPRIM_TYPE_POINTLIST
;
4646 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.primitive_mode
);
4649 gs_out
= si_conv_prim_to_gs_out(pCreateInfo
->pInputAssemblyState
->topology
);
4652 if (extra
&& extra
->use_rectlist
) {
4653 gs_out
= V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4654 if (radv_pipeline_has_ngg(pipeline
))
4655 gs_out
= V_028A6C_VGT_OUT_RECT_V0
;
4658 radeon_set_context_reg(ctx_cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, gs_out
);
4662 radv_pipeline_generate_pm4(struct radv_pipeline
*pipeline
,
4663 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4664 const struct radv_graphics_pipeline_create_info
*extra
,
4665 const struct radv_blend_state
*blend
)
4667 struct radeon_cmdbuf
*ctx_cs
= &pipeline
->ctx_cs
;
4668 struct radeon_cmdbuf
*cs
= &pipeline
->cs
;
4671 ctx_cs
->max_dw
= 256;
4672 cs
->buf
= malloc(4 * (cs
->max_dw
+ ctx_cs
->max_dw
));
4673 ctx_cs
->buf
= cs
->buf
+ cs
->max_dw
;
4675 radv_pipeline_generate_depth_stencil_state(ctx_cs
, pipeline
, pCreateInfo
, extra
);
4676 radv_pipeline_generate_blend_state(ctx_cs
, pipeline
, blend
);
4677 radv_pipeline_generate_raster_state(ctx_cs
, pipeline
, pCreateInfo
);
4678 radv_pipeline_generate_multisample_state(ctx_cs
, pipeline
);
4679 radv_pipeline_generate_vgt_gs_mode(ctx_cs
, pipeline
);
4680 radv_pipeline_generate_vertex_shader(ctx_cs
, cs
, pipeline
);
4682 if (radv_pipeline_has_tess(pipeline
)) {
4683 radv_pipeline_generate_tess_shaders(ctx_cs
, cs
, pipeline
);
4684 radv_pipeline_generate_tess_state(ctx_cs
, pipeline
, pCreateInfo
);
4687 radv_pipeline_generate_geometry_shader(ctx_cs
, cs
, pipeline
);
4688 radv_pipeline_generate_fragment_shader(ctx_cs
, cs
, pipeline
);
4689 radv_pipeline_generate_ps_inputs(ctx_cs
, pipeline
);
4690 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs
, pipeline
);
4691 radv_pipeline_generate_vgt_shader_config(ctx_cs
, pipeline
);
4692 radv_pipeline_generate_cliprect_rule(ctx_cs
, pCreateInfo
);
4693 radv_pipeline_generate_vgt_gs_out(ctx_cs
, pipeline
, pCreateInfo
, extra
);
4695 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&& !radv_pipeline_has_ngg(pipeline
))
4696 gfx10_pipeline_generate_ge_cntl(ctx_cs
, pipeline
);
4698 pipeline
->ctx_cs_hash
= _mesa_hash_data(ctx_cs
->buf
, ctx_cs
->cdw
* 4);
4700 assert(ctx_cs
->cdw
<= ctx_cs
->max_dw
);
4701 assert(cs
->cdw
<= cs
->max_dw
);
4704 static struct radv_ia_multi_vgt_param_helpers
4705 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline
*pipeline
)
4707 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
= {0};
4708 const struct radv_device
*device
= pipeline
->device
;
4710 if (radv_pipeline_has_tess(pipeline
))
4711 ia_multi_vgt_param
.primgroup_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
4712 else if (radv_pipeline_has_gs(pipeline
))
4713 ia_multi_vgt_param
.primgroup_size
= 64;
4715 ia_multi_vgt_param
.primgroup_size
= 128; /* recommended without a GS */
4717 /* GS requirement. */
4718 ia_multi_vgt_param
.partial_es_wave
= false;
4719 if (radv_pipeline_has_gs(pipeline
) && device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4720 if (SI_GS_PER_ES
/ ia_multi_vgt_param
.primgroup_size
>= pipeline
->device
->gs_table_depth
- 3)
4721 ia_multi_vgt_param
.partial_es_wave
= true;
4723 ia_multi_vgt_param
.ia_switch_on_eoi
= false;
4724 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.prim_id_input
)
4725 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4726 if (radv_pipeline_has_gs(pipeline
) &&
4727 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.uses_prim_id
)
4728 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4729 if (radv_pipeline_has_tess(pipeline
)) {
4730 /* SWITCH_ON_EOI must be set if PrimID is used. */
4731 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4732 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4733 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4736 ia_multi_vgt_param
.partial_vs_wave
= false;
4737 if (radv_pipeline_has_tess(pipeline
)) {
4738 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4739 if ((device
->physical_device
->rad_info
.family
== CHIP_TAHITI
||
4740 device
->physical_device
->rad_info
.family
== CHIP_PITCAIRN
||
4741 device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
) &&
4742 radv_pipeline_has_gs(pipeline
))
4743 ia_multi_vgt_param
.partial_vs_wave
= true;
4744 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4745 if (device
->physical_device
->rad_info
.has_distributed_tess
) {
4746 if (radv_pipeline_has_gs(pipeline
)) {
4747 if (device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4748 ia_multi_vgt_param
.partial_es_wave
= true;
4750 ia_multi_vgt_param
.partial_vs_wave
= true;
4755 if (radv_pipeline_has_gs(pipeline
)) {
4756 /* On these chips there is the possibility of a hang if the
4757 * pipeline uses a GS and partial_vs_wave is not set.
4759 * This mostly does not hit 4-SE chips, as those typically set
4760 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4761 * with GS due to another workaround.
4763 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4765 if (device
->physical_device
->rad_info
.family
== CHIP_TONGA
||
4766 device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
4767 device
->physical_device
->rad_info
.family
== CHIP_POLARIS10
||
4768 device
->physical_device
->rad_info
.family
== CHIP_POLARIS11
||
4769 device
->physical_device
->rad_info
.family
== CHIP_POLARIS12
||
4770 device
->physical_device
->rad_info
.family
== CHIP_VEGAM
) {
4771 ia_multi_vgt_param
.partial_vs_wave
= true;
4775 ia_multi_vgt_param
.base
=
4776 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param
.primgroup_size
- 1) |
4777 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4778 S_028AA8_MAX_PRIMGRP_IN_WAVE(device
->physical_device
->rad_info
.chip_class
== GFX8
? 2 : 0) |
4779 S_030960_EN_INST_OPT_BASIC(device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
4780 S_030960_EN_INST_OPT_ADV(device
->physical_device
->rad_info
.chip_class
>= GFX9
);
4782 return ia_multi_vgt_param
;
4787 radv_compute_vertex_input_state(struct radv_pipeline
*pipeline
,
4788 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4790 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
4791 pCreateInfo
->pVertexInputState
;
4793 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
4794 const VkVertexInputBindingDescription
*desc
=
4795 &vi_info
->pVertexBindingDescriptions
[i
];
4797 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
4798 pipeline
->num_vertex_bindings
=
4799 MAX2(pipeline
->num_vertex_bindings
, desc
->binding
+ 1);
4803 static struct radv_shader_variant
*
4804 radv_pipeline_get_streamout_shader(struct radv_pipeline
*pipeline
)
4808 for (i
= MESA_SHADER_GEOMETRY
; i
>= MESA_SHADER_VERTEX
; i
--) {
4809 struct radv_shader_variant
*shader
=
4810 radv_get_shader(pipeline
, i
);
4812 if (shader
&& shader
->info
.so
.num_outputs
> 0)
4820 radv_pipeline_init_shader_stages_state(struct radv_pipeline
*pipeline
)
4822 struct radv_device
*device
= pipeline
->device
;
4824 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
4825 pipeline
->user_data_0
[i
] =
4826 radv_pipeline_stage_to_user_data_0(pipeline
, i
,
4827 device
->physical_device
->rad_info
.chip_class
);
4829 if (pipeline
->shaders
[i
]) {
4830 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[i
]->info
.need_indirect_descriptor_sets
;
4834 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
,
4835 AC_UD_VS_BASE_VERTEX_START_INSTANCE
);
4836 if (loc
->sgpr_idx
!= -1) {
4837 pipeline
->graphics
.vtx_base_sgpr
= pipeline
->user_data_0
[MESA_SHADER_VERTEX
];
4838 pipeline
->graphics
.vtx_base_sgpr
+= loc
->sgpr_idx
* 4;
4839 if (radv_get_shader(pipeline
, MESA_SHADER_VERTEX
)->info
.vs
.needs_draw_id
)
4840 pipeline
->graphics
.vtx_emit_num
= 3;
4842 pipeline
->graphics
.vtx_emit_num
= 2;
4847 radv_pipeline_init(struct radv_pipeline
*pipeline
,
4848 struct radv_device
*device
,
4849 struct radv_pipeline_cache
*cache
,
4850 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4851 const struct radv_graphics_pipeline_create_info
*extra
)
4855 pipeline
->device
= device
;
4856 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
4857 assert(pipeline
->layout
);
4859 struct radv_blend_state blend
= radv_pipeline_init_blend_state(pipeline
, pCreateInfo
, extra
);
4861 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
4862 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
4863 radv_init_feedback(creation_feedback
);
4865 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
4867 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
4868 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
4869 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
4870 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
4871 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
4872 if(creation_feedback
)
4873 stage_feedbacks
[stage
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[i
];
4876 struct radv_pipeline_key key
= radv_generate_graphics_pipeline_key(pipeline
, pCreateInfo
, &blend
);
4878 result
= radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
,
4879 pCreateInfo
->flags
, pipeline_feedback
,
4881 if (result
!= VK_SUCCESS
)
4884 pipeline
->graphics
.spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
4885 radv_pipeline_init_multisample_state(pipeline
, &blend
, pCreateInfo
);
4886 radv_pipeline_init_input_assembly_state(pipeline
, pCreateInfo
, extra
);
4887 radv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
, extra
);
4888 radv_pipeline_init_raster_state(pipeline
, pCreateInfo
);
4889 radv_pipeline_init_depth_stencil_state(pipeline
, pCreateInfo
);
4891 /* Ensure that some export memory is always allocated, for two reasons:
4893 * 1) Correctness: The hardware ignores the EXEC mask if no export
4894 * memory is allocated, so KILL and alpha test do not work correctly
4896 * 2) Performance: Every shader needs at least a NULL export, even when
4897 * it writes no color/depth output. The NULL export instruction
4898 * stalls without this setting.
4900 * Don't add this to CB_SHADER_MASK.
4902 * GFX10 supports pixel shaders without exports by setting both the
4903 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
4904 * instructions if any are present.
4906 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4907 if ((pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX9
||
4908 ps
->info
.ps
.can_discard
) &&
4909 !blend
.spi_shader_col_format
) {
4910 if (!ps
->info
.ps
.writes_z
&&
4911 !ps
->info
.ps
.writes_stencil
&&
4912 !ps
->info
.ps
.writes_sample_mask
)
4913 blend
.spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
4916 blend
.cb_shader_mask
= ps
->info
.ps
.cb_shader_mask
;
4919 (extra
->custom_blend_mode
== V_028808_CB_ELIMINATE_FAST_CLEAR
||
4920 extra
->custom_blend_mode
== V_028808_CB_FMASK_DECOMPRESS
||
4921 extra
->custom_blend_mode
== V_028808_CB_DCC_DECOMPRESS
||
4922 extra
->custom_blend_mode
== V_028808_CB_RESOLVE
)) {
4923 /* According to the CB spec states, CB_SHADER_MASK should be
4924 * set to enable writes to all four channels of MRT0.
4926 blend
.cb_shader_mask
= 0xf;
4929 pipeline
->graphics
.col_format
= blend
.spi_shader_col_format
;
4930 pipeline
->graphics
.cb_target_mask
= blend
.cb_target_mask
;
4932 if (radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
4933 struct radv_shader_variant
*gs
=
4934 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4936 calculate_gs_ring_sizes(pipeline
, &gs
->info
.gs_ring_info
);
4939 if (radv_pipeline_has_tess(pipeline
)) {
4940 pipeline
->graphics
.tess_patch_control_points
=
4941 pCreateInfo
->pTessellationState
->patchControlPoints
;
4944 pipeline
->graphics
.ia_multi_vgt_param
= radv_compute_ia_multi_vgt_param_helpers(pipeline
);
4946 radv_compute_vertex_input_state(pipeline
, pCreateInfo
);
4948 radv_pipeline_init_binning_state(pipeline
, pCreateInfo
, &blend
);
4949 radv_pipeline_init_shader_stages_state(pipeline
);
4951 /* Find the last vertex shader stage that eventually uses streamout. */
4952 pipeline
->streamout_shader
= radv_pipeline_get_streamout_shader(pipeline
);
4954 result
= radv_pipeline_scratch_init(device
, pipeline
);
4955 radv_pipeline_generate_pm4(pipeline
, pCreateInfo
, extra
, &blend
);
4961 radv_graphics_pipeline_create(
4963 VkPipelineCache _cache
,
4964 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4965 const struct radv_graphics_pipeline_create_info
*extra
,
4966 const VkAllocationCallbacks
*pAllocator
,
4967 VkPipeline
*pPipeline
)
4969 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4970 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
4971 struct radv_pipeline
*pipeline
;
4974 pipeline
= vk_zalloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*pipeline
), 8,
4975 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4976 if (pipeline
== NULL
)
4977 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4979 vk_object_base_init(&device
->vk
, &pipeline
->base
,
4980 VK_OBJECT_TYPE_PIPELINE
);
4982 result
= radv_pipeline_init(pipeline
, device
, cache
,
4983 pCreateInfo
, extra
);
4984 if (result
!= VK_SUCCESS
) {
4985 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
4989 *pPipeline
= radv_pipeline_to_handle(pipeline
);
4994 VkResult
radv_CreateGraphicsPipelines(
4996 VkPipelineCache pipelineCache
,
4998 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
4999 const VkAllocationCallbacks
* pAllocator
,
5000 VkPipeline
* pPipelines
)
5002 VkResult result
= VK_SUCCESS
;
5005 for (; i
< count
; i
++) {
5007 r
= radv_graphics_pipeline_create(_device
,
5010 NULL
, pAllocator
, &pPipelines
[i
]);
5011 if (r
!= VK_SUCCESS
) {
5013 pPipelines
[i
] = VK_NULL_HANDLE
;
5015 if (pCreateInfos
[i
].flags
& VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT
)
5020 for (; i
< count
; ++i
)
5021 pPipelines
[i
] = VK_NULL_HANDLE
;
5027 radv_pipeline_generate_hw_cs(struct radeon_cmdbuf
*cs
,
5028 const struct radv_pipeline
*pipeline
)
5030 struct radv_shader_variant
*shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
5031 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
5032 struct radv_device
*device
= pipeline
->device
;
5034 radeon_set_sh_reg_seq(cs
, R_00B830_COMPUTE_PGM_LO
, 2);
5035 radeon_emit(cs
, va
>> 8);
5036 radeon_emit(cs
, S_00B834_DATA(va
>> 40));
5038 radeon_set_sh_reg_seq(cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
5039 radeon_emit(cs
, shader
->config
.rsrc1
);
5040 radeon_emit(cs
, shader
->config
.rsrc2
);
5041 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
5042 radeon_set_sh_reg(cs
, R_00B8A0_COMPUTE_PGM_RSRC3
, shader
->config
.rsrc3
);
5047 radv_pipeline_generate_compute_state(struct radeon_cmdbuf
*cs
,
5048 const struct radv_pipeline
*pipeline
)
5050 struct radv_shader_variant
*shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
5051 struct radv_device
*device
= pipeline
->device
;
5052 unsigned threads_per_threadgroup
;
5053 unsigned threadgroups_per_cu
= 1;
5054 unsigned waves_per_threadgroup
;
5055 unsigned max_waves_per_sh
= 0;
5057 /* Calculate best compute resource limits. */
5058 threads_per_threadgroup
= shader
->info
.cs
.block_size
[0] *
5059 shader
->info
.cs
.block_size
[1] *
5060 shader
->info
.cs
.block_size
[2];
5061 waves_per_threadgroup
= DIV_ROUND_UP(threads_per_threadgroup
,
5062 shader
->info
.wave_size
);
5064 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
5065 waves_per_threadgroup
== 1)
5066 threadgroups_per_cu
= 2;
5068 radeon_set_sh_reg(cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
5069 ac_get_compute_resource_limits(&device
->physical_device
->rad_info
,
5070 waves_per_threadgroup
,
5072 threadgroups_per_cu
));
5074 radeon_set_sh_reg_seq(cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
5075 radeon_emit(cs
, S_00B81C_NUM_THREAD_FULL(shader
->info
.cs
.block_size
[0]));
5076 radeon_emit(cs
, S_00B81C_NUM_THREAD_FULL(shader
->info
.cs
.block_size
[1]));
5077 radeon_emit(cs
, S_00B81C_NUM_THREAD_FULL(shader
->info
.cs
.block_size
[2]));
5081 radv_compute_generate_pm4(struct radv_pipeline
*pipeline
)
5083 struct radv_device
*device
= pipeline
->device
;
5084 struct radeon_cmdbuf
*cs
= &pipeline
->cs
;
5086 cs
->max_dw
= device
->physical_device
->rad_info
.chip_class
>= GFX10
? 19 : 16;
5087 cs
->buf
= malloc(cs
->max_dw
* 4);
5089 radv_pipeline_generate_hw_cs(cs
, pipeline
);
5090 radv_pipeline_generate_compute_state(cs
, pipeline
);
5092 assert(pipeline
->cs
.cdw
<= pipeline
->cs
.max_dw
);
5095 static struct radv_pipeline_key
5096 radv_generate_compute_pipeline_key(struct radv_pipeline
*pipeline
,
5097 const VkComputePipelineCreateInfo
*pCreateInfo
)
5099 const VkPipelineShaderStageCreateInfo
*stage
= &pCreateInfo
->stage
;
5100 struct radv_pipeline_key key
;
5101 memset(&key
, 0, sizeof(key
));
5103 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
5104 key
.optimisations_disabled
= 1;
5106 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*subgroup_size
=
5107 vk_find_struct_const(stage
->pNext
,
5108 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT
);
5110 if (subgroup_size
) {
5111 assert(subgroup_size
->requiredSubgroupSize
== 32 ||
5112 subgroup_size
->requiredSubgroupSize
== 64);
5113 key
.compute_subgroup_size
= subgroup_size
->requiredSubgroupSize
;
5119 static VkResult
radv_compute_pipeline_create(
5121 VkPipelineCache _cache
,
5122 const VkComputePipelineCreateInfo
* pCreateInfo
,
5123 const VkAllocationCallbacks
* pAllocator
,
5124 VkPipeline
* pPipeline
)
5126 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5127 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
5128 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
5129 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
5130 struct radv_pipeline
*pipeline
;
5133 pipeline
= vk_zalloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*pipeline
), 8,
5134 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5135 if (pipeline
== NULL
)
5136 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5138 vk_object_base_init(&device
->vk
, &pipeline
->base
,
5139 VK_OBJECT_TYPE_PIPELINE
);
5141 pipeline
->device
= device
;
5142 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
5143 assert(pipeline
->layout
);
5145 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
5146 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
5147 radv_init_feedback(creation_feedback
);
5149 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
5150 if (creation_feedback
)
5151 stage_feedbacks
[MESA_SHADER_COMPUTE
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[0];
5153 pStages
[MESA_SHADER_COMPUTE
] = &pCreateInfo
->stage
;
5155 struct radv_pipeline_key key
=
5156 radv_generate_compute_pipeline_key(pipeline
, pCreateInfo
);
5158 result
= radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
,
5159 pCreateInfo
->flags
, pipeline_feedback
,
5161 if (result
!= VK_SUCCESS
) {
5162 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5166 pipeline
->user_data_0
[MESA_SHADER_COMPUTE
] = radv_pipeline_stage_to_user_data_0(pipeline
, MESA_SHADER_COMPUTE
, device
->physical_device
->rad_info
.chip_class
);
5167 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.need_indirect_descriptor_sets
;
5168 result
= radv_pipeline_scratch_init(device
, pipeline
);
5169 if (result
!= VK_SUCCESS
) {
5170 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5174 radv_compute_generate_pm4(pipeline
);
5176 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5181 VkResult
radv_CreateComputePipelines(
5183 VkPipelineCache pipelineCache
,
5185 const VkComputePipelineCreateInfo
* pCreateInfos
,
5186 const VkAllocationCallbacks
* pAllocator
,
5187 VkPipeline
* pPipelines
)
5189 VkResult result
= VK_SUCCESS
;
5192 for (; i
< count
; i
++) {
5194 r
= radv_compute_pipeline_create(_device
, pipelineCache
,
5196 pAllocator
, &pPipelines
[i
]);
5197 if (r
!= VK_SUCCESS
) {
5199 pPipelines
[i
] = VK_NULL_HANDLE
;
5201 if (pCreateInfos
[i
].flags
& VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT
)
5206 for (; i
< count
; ++i
)
5207 pPipelines
[i
] = VK_NULL_HANDLE
;
5213 static uint32_t radv_get_executable_count(const struct radv_pipeline
*pipeline
)
5216 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5217 if (!pipeline
->shaders
[i
])
5220 if (i
== MESA_SHADER_GEOMETRY
&&
5221 !radv_pipeline_has_ngg(pipeline
)) {
5231 static struct radv_shader_variant
*
5232 radv_get_shader_from_executable_index(const struct radv_pipeline
*pipeline
, int index
, gl_shader_stage
*stage
)
5234 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5235 if (!pipeline
->shaders
[i
])
5239 return pipeline
->shaders
[i
];
5244 if (i
== MESA_SHADER_GEOMETRY
&&
5245 !radv_pipeline_has_ngg(pipeline
)) {
5248 return pipeline
->gs_copy_shader
;
5258 /* Basically strlcpy (which does not exist on linux) specialized for
5260 static void desc_copy(char *desc
, const char *src
) {
5261 int len
= strlen(src
);
5262 assert(len
< VK_MAX_DESCRIPTION_SIZE
);
5263 memcpy(desc
, src
, len
);
5264 memset(desc
+ len
, 0, VK_MAX_DESCRIPTION_SIZE
- len
);
5267 VkResult
radv_GetPipelineExecutablePropertiesKHR(
5269 const VkPipelineInfoKHR
* pPipelineInfo
,
5270 uint32_t* pExecutableCount
,
5271 VkPipelineExecutablePropertiesKHR
* pProperties
)
5273 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pPipelineInfo
->pipeline
);
5274 const uint32_t total_count
= radv_get_executable_count(pipeline
);
5277 *pExecutableCount
= total_count
;
5281 const uint32_t count
= MIN2(total_count
, *pExecutableCount
);
5282 for (unsigned i
= 0, executable_idx
= 0;
5283 i
< MESA_SHADER_STAGES
&& executable_idx
< count
; ++i
) {
5284 if (!pipeline
->shaders
[i
])
5286 pProperties
[executable_idx
].stages
= mesa_to_vk_shader_stage(i
);
5287 const char *name
= NULL
;
5288 const char *description
= NULL
;
5290 case MESA_SHADER_VERTEX
:
5291 name
= "Vertex Shader";
5292 description
= "Vulkan Vertex Shader";
5294 case MESA_SHADER_TESS_CTRL
:
5295 if (!pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5296 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5297 name
= "Vertex + Tessellation Control Shaders";
5298 description
= "Combined Vulkan Vertex and Tessellation Control Shaders";
5300 name
= "Tessellation Control Shader";
5301 description
= "Vulkan Tessellation Control Shader";
5304 case MESA_SHADER_TESS_EVAL
:
5305 name
= "Tessellation Evaluation Shader";
5306 description
= "Vulkan Tessellation Evaluation Shader";
5308 case MESA_SHADER_GEOMETRY
:
5309 if (radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]) {
5310 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
;
5311 name
= "Tessellation Evaluation + Geometry Shaders";
5312 description
= "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5313 } else if (!radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5314 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5315 name
= "Vertex + Geometry Shader";
5316 description
= "Combined Vulkan Vertex and Geometry Shaders";
5318 name
= "Geometry Shader";
5319 description
= "Vulkan Geometry Shader";
5322 case MESA_SHADER_FRAGMENT
:
5323 name
= "Fragment Shader";
5324 description
= "Vulkan Fragment Shader";
5326 case MESA_SHADER_COMPUTE
:
5327 name
= "Compute Shader";
5328 description
= "Vulkan Compute Shader";
5332 pProperties
[executable_idx
].subgroupSize
= pipeline
->shaders
[i
]->info
.wave_size
;
5333 desc_copy(pProperties
[executable_idx
].name
, name
);
5334 desc_copy(pProperties
[executable_idx
].description
, description
);
5337 if (i
== MESA_SHADER_GEOMETRY
&&
5338 !radv_pipeline_has_ngg(pipeline
)) {
5339 assert(pipeline
->gs_copy_shader
);
5340 if (executable_idx
>= count
)
5343 pProperties
[executable_idx
].stages
= VK_SHADER_STAGE_GEOMETRY_BIT
;
5344 pProperties
[executable_idx
].subgroupSize
= 64;
5345 desc_copy(pProperties
[executable_idx
].name
, "GS Copy Shader");
5346 desc_copy(pProperties
[executable_idx
].description
,
5347 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5353 VkResult result
= *pExecutableCount
< total_count
? VK_INCOMPLETE
: VK_SUCCESS
;
5354 *pExecutableCount
= count
;
5358 VkResult
radv_GetPipelineExecutableStatisticsKHR(
5360 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5361 uint32_t* pStatisticCount
,
5362 VkPipelineExecutableStatisticKHR
* pStatistics
)
5364 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5365 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5366 gl_shader_stage stage
;
5367 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5369 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
5370 unsigned lds_increment
= chip_class
>= GFX7
? 512 : 256;
5371 unsigned max_waves
= radv_get_max_waves(device
, shader
, stage
);
5373 VkPipelineExecutableStatisticKHR
*s
= pStatistics
;
5374 VkPipelineExecutableStatisticKHR
*end
= s
+ (pStatistics
? *pStatisticCount
: 0);
5375 VkResult result
= VK_SUCCESS
;
5378 desc_copy(s
->name
, "SGPRs");
5379 desc_copy(s
->description
, "Number of SGPR registers allocated per subgroup");
5380 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5381 s
->value
.u64
= shader
->config
.num_sgprs
;
5386 desc_copy(s
->name
, "VGPRs");
5387 desc_copy(s
->description
, "Number of VGPR registers allocated per subgroup");
5388 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5389 s
->value
.u64
= shader
->config
.num_vgprs
;
5394 desc_copy(s
->name
, "Spilled SGPRs");
5395 desc_copy(s
->description
, "Number of SGPR registers spilled per subgroup");
5396 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5397 s
->value
.u64
= shader
->config
.spilled_sgprs
;
5402 desc_copy(s
->name
, "Spilled VGPRs");
5403 desc_copy(s
->description
, "Number of VGPR registers spilled per subgroup");
5404 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5405 s
->value
.u64
= shader
->config
.spilled_vgprs
;
5410 desc_copy(s
->name
, "PrivMem VGPRs");
5411 desc_copy(s
->description
, "Number of VGPRs stored in private memory per subgroup");
5412 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5413 s
->value
.u64
= shader
->info
.private_mem_vgprs
;
5418 desc_copy(s
->name
, "Code size");
5419 desc_copy(s
->description
, "Code size in bytes");
5420 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5421 s
->value
.u64
= shader
->exec_size
;
5426 desc_copy(s
->name
, "LDS size");
5427 desc_copy(s
->description
, "LDS size in bytes per workgroup");
5428 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5429 s
->value
.u64
= shader
->config
.lds_size
* lds_increment
;
5434 desc_copy(s
->name
, "Scratch size");
5435 desc_copy(s
->description
, "Private memory in bytes per subgroup");
5436 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5437 s
->value
.u64
= shader
->config
.scratch_bytes_per_wave
;
5442 desc_copy(s
->name
, "Subgroups per SIMD");
5443 desc_copy(s
->description
, "The maximum number of subgroups in flight on a SIMD unit");
5444 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5445 s
->value
.u64
= max_waves
;
5449 if (shader
->statistics
) {
5450 for (unsigned i
= 0; i
< shader
->statistics
->count
; i
++) {
5451 struct radv_compiler_statistic_info
*info
= &shader
->statistics
->infos
[i
];
5452 uint32_t value
= shader
->statistics
->values
[i
];
5454 desc_copy(s
->name
, info
->name
);
5455 desc_copy(s
->description
, info
->desc
);
5456 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5457 s
->value
.u64
= value
;
5464 *pStatisticCount
= s
- pStatistics
;
5466 *pStatisticCount
= end
- pStatistics
;
5467 result
= VK_INCOMPLETE
;
5469 *pStatisticCount
= s
- pStatistics
;
5475 static VkResult
radv_copy_representation(void *data
, size_t *data_size
, const char *src
)
5477 size_t total_size
= strlen(src
) + 1;
5480 *data_size
= total_size
;
5484 size_t size
= MIN2(total_size
, *data_size
);
5486 memcpy(data
, src
, size
);
5488 *((char*)data
+ size
- 1) = 0;
5489 return size
< total_size
? VK_INCOMPLETE
: VK_SUCCESS
;
5492 VkResult
radv_GetPipelineExecutableInternalRepresentationsKHR(
5494 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5495 uint32_t* pInternalRepresentationCount
,
5496 VkPipelineExecutableInternalRepresentationKHR
* pInternalRepresentations
)
5498 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5499 gl_shader_stage stage
;
5500 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5502 VkPipelineExecutableInternalRepresentationKHR
*p
= pInternalRepresentations
;
5503 VkPipelineExecutableInternalRepresentationKHR
*end
= p
+ (pInternalRepresentations
? *pInternalRepresentationCount
: 0);
5504 VkResult result
= VK_SUCCESS
;
5508 desc_copy(p
->name
, "NIR Shader(s)");
5509 desc_copy(p
->description
, "The optimized NIR shader(s)");
5510 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->nir_string
) != VK_SUCCESS
)
5511 result
= VK_INCOMPLETE
;
5518 if (pipeline
->device
->physical_device
->use_llvm
) {
5519 desc_copy(p
->name
, "LLVM IR");
5520 desc_copy(p
->description
, "The LLVM IR after some optimizations");
5522 desc_copy(p
->name
, "ACO IR");
5523 desc_copy(p
->description
, "The ACO IR after some optimizations");
5525 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->ir_string
) != VK_SUCCESS
)
5526 result
= VK_INCOMPLETE
;
5533 desc_copy(p
->name
, "Assembly");
5534 desc_copy(p
->description
, "Final Assembly");
5535 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->disasm_string
) != VK_SUCCESS
)
5536 result
= VK_INCOMPLETE
;
5540 if (!pInternalRepresentations
)
5541 *pInternalRepresentationCount
= p
- pInternalRepresentations
;
5543 result
= VK_INCOMPLETE
;
5544 *pInternalRepresentationCount
= end
- pInternalRepresentations
;
5546 *pInternalRepresentationCount
= p
- pInternalRepresentations
;