2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
34 #include "radv_shader.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
41 #include <llvm-c/Core.h>
42 #include <llvm-c/TargetMachine.h>
45 #include "ac_binary.h"
46 #include "ac_llvm_util.h"
47 #include "ac_nir_to_llvm.h"
48 #include "vk_format.h"
49 #include "util/debug.h"
50 #include "ac_exp_param.h"
51 #include "ac_shader_util.h"
52 #include "main/menums.h"
54 struct radv_blend_state
{
55 uint32_t blend_enable_4bit
;
56 uint32_t need_src_alpha
;
58 uint32_t cb_color_control
;
59 uint32_t cb_target_mask
;
60 uint32_t cb_target_enabled_4bit
;
61 uint32_t sx_mrt_blend_opt
[8];
62 uint32_t cb_blend_control
[8];
64 uint32_t spi_shader_col_format
;
65 uint32_t cb_shader_mask
;
66 uint32_t db_alpha_to_mask
;
68 uint32_t commutative_4bit
;
70 bool single_cb_enable
;
71 bool mrt0_is_dual_src
;
74 struct radv_dsa_order_invariance
{
75 /* Whether the final result in Z/S buffers is guaranteed to be
76 * invariant under changes to the order in which fragments arrive.
80 /* Whether the set of fragments that pass the combined Z/S test is
81 * guaranteed to be invariant under changes to the order in which
87 struct radv_tessellation_state
{
88 uint32_t ls_hs_config
;
94 static const VkPipelineMultisampleStateCreateInfo
*
95 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
97 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
98 return pCreateInfo
->pMultisampleState
;
102 static const VkPipelineTessellationStateCreateInfo
*
103 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
105 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
106 if (pCreateInfo
->pStages
[i
].stage
== VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
||
107 pCreateInfo
->pStages
[i
].stage
== VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
) {
108 return pCreateInfo
->pTessellationState
;
114 static const VkPipelineDepthStencilStateCreateInfo
*
115 radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
117 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
118 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
120 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
121 subpass
->depth_stencil_attachment
)
122 return pCreateInfo
->pDepthStencilState
;
126 static const VkPipelineColorBlendStateCreateInfo
*
127 radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
129 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
130 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
132 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
133 subpass
->has_color_att
)
134 return pCreateInfo
->pColorBlendState
;
138 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
)
140 struct radv_shader_variant
*variant
= NULL
;
141 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
142 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
143 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
144 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
145 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
146 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
149 return variant
->info
.is_ngg
;
152 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
)
154 if (!radv_pipeline_has_gs(pipeline
))
157 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
158 * On GFX10, it might be required in rare cases if it's not possible to
161 if (radv_pipeline_has_ngg(pipeline
))
164 assert(pipeline
->gs_copy_shader
);
169 radv_pipeline_destroy(struct radv_device
*device
,
170 struct radv_pipeline
*pipeline
,
171 const VkAllocationCallbacks
* allocator
)
173 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
174 if (pipeline
->shaders
[i
])
175 radv_shader_variant_destroy(device
, pipeline
->shaders
[i
]);
177 if (pipeline
->gs_copy_shader
)
178 radv_shader_variant_destroy(device
, pipeline
->gs_copy_shader
);
181 free(pipeline
->cs
.buf
);
182 vk_free2(&device
->alloc
, allocator
, pipeline
);
185 void radv_DestroyPipeline(
187 VkPipeline _pipeline
,
188 const VkAllocationCallbacks
* pAllocator
)
190 RADV_FROM_HANDLE(radv_device
, device
, _device
);
191 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
196 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
199 static uint32_t get_hash_flags(struct radv_device
*device
)
201 uint32_t hash_flags
= 0;
203 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_NGG
)
204 hash_flags
|= RADV_HASH_SHADER_NO_NGG
;
205 if (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
)
206 hash_flags
|= RADV_HASH_SHADER_SISCHED
;
207 if (device
->physical_device
->cs_wave_size
== 32)
208 hash_flags
|= RADV_HASH_SHADER_CS_WAVE32
;
209 if (device
->physical_device
->ps_wave_size
== 32)
210 hash_flags
|= RADV_HASH_SHADER_PS_WAVE32
;
211 if (device
->physical_device
->ge_wave_size
== 32)
212 hash_flags
|= RADV_HASH_SHADER_GE_WAVE32
;
213 if (device
->physical_device
->use_aco
)
214 hash_flags
|= RADV_HASH_SHADER_ACO
;
219 radv_pipeline_scratch_init(struct radv_device
*device
,
220 struct radv_pipeline
*pipeline
)
222 unsigned scratch_bytes_per_wave
= 0;
223 unsigned max_waves
= 0;
224 unsigned min_waves
= 1;
226 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
227 if (pipeline
->shaders
[i
] &&
228 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
) {
229 unsigned max_stage_waves
= device
->scratch_waves
;
231 scratch_bytes_per_wave
= MAX2(scratch_bytes_per_wave
,
232 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
);
234 max_stage_waves
= MIN2(max_stage_waves
,
235 4 * device
->physical_device
->rad_info
.num_good_compute_units
*
236 (256 / pipeline
->shaders
[i
]->config
.num_vgprs
));
237 max_waves
= MAX2(max_waves
, max_stage_waves
);
241 if (pipeline
->shaders
[MESA_SHADER_COMPUTE
]) {
242 unsigned group_size
= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[0] *
243 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[1] *
244 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[2];
245 min_waves
= MAX2(min_waves
, round_up_u32(group_size
, 64));
248 pipeline
->scratch_bytes_per_wave
= scratch_bytes_per_wave
;
249 pipeline
->max_waves
= max_waves
;
253 static uint32_t si_translate_blend_logic_op(VkLogicOp op
)
256 case VK_LOGIC_OP_CLEAR
:
257 return V_028808_ROP3_CLEAR
;
258 case VK_LOGIC_OP_AND
:
259 return V_028808_ROP3_AND
;
260 case VK_LOGIC_OP_AND_REVERSE
:
261 return V_028808_ROP3_AND_REVERSE
;
262 case VK_LOGIC_OP_COPY
:
263 return V_028808_ROP3_COPY
;
264 case VK_LOGIC_OP_AND_INVERTED
:
265 return V_028808_ROP3_AND_INVERTED
;
266 case VK_LOGIC_OP_NO_OP
:
267 return V_028808_ROP3_NO_OP
;
268 case VK_LOGIC_OP_XOR
:
269 return V_028808_ROP3_XOR
;
271 return V_028808_ROP3_OR
;
272 case VK_LOGIC_OP_NOR
:
273 return V_028808_ROP3_NOR
;
274 case VK_LOGIC_OP_EQUIVALENT
:
275 return V_028808_ROP3_EQUIVALENT
;
276 case VK_LOGIC_OP_INVERT
:
277 return V_028808_ROP3_INVERT
;
278 case VK_LOGIC_OP_OR_REVERSE
:
279 return V_028808_ROP3_OR_REVERSE
;
280 case VK_LOGIC_OP_COPY_INVERTED
:
281 return V_028808_ROP3_COPY_INVERTED
;
282 case VK_LOGIC_OP_OR_INVERTED
:
283 return V_028808_ROP3_OR_INVERTED
;
284 case VK_LOGIC_OP_NAND
:
285 return V_028808_ROP3_NAND
;
286 case VK_LOGIC_OP_SET
:
287 return V_028808_ROP3_SET
;
289 unreachable("Unhandled logic op");
294 static uint32_t si_translate_blend_function(VkBlendOp op
)
297 case VK_BLEND_OP_ADD
:
298 return V_028780_COMB_DST_PLUS_SRC
;
299 case VK_BLEND_OP_SUBTRACT
:
300 return V_028780_COMB_SRC_MINUS_DST
;
301 case VK_BLEND_OP_REVERSE_SUBTRACT
:
302 return V_028780_COMB_DST_MINUS_SRC
;
303 case VK_BLEND_OP_MIN
:
304 return V_028780_COMB_MIN_DST_SRC
;
305 case VK_BLEND_OP_MAX
:
306 return V_028780_COMB_MAX_DST_SRC
;
312 static uint32_t si_translate_blend_factor(VkBlendFactor factor
)
315 case VK_BLEND_FACTOR_ZERO
:
316 return V_028780_BLEND_ZERO
;
317 case VK_BLEND_FACTOR_ONE
:
318 return V_028780_BLEND_ONE
;
319 case VK_BLEND_FACTOR_SRC_COLOR
:
320 return V_028780_BLEND_SRC_COLOR
;
321 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
322 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
323 case VK_BLEND_FACTOR_DST_COLOR
:
324 return V_028780_BLEND_DST_COLOR
;
325 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
326 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
327 case VK_BLEND_FACTOR_SRC_ALPHA
:
328 return V_028780_BLEND_SRC_ALPHA
;
329 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
330 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
331 case VK_BLEND_FACTOR_DST_ALPHA
:
332 return V_028780_BLEND_DST_ALPHA
;
333 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
334 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
335 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
336 return V_028780_BLEND_CONSTANT_COLOR
;
337 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
338 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
339 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
340 return V_028780_BLEND_CONSTANT_ALPHA
;
341 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
342 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
343 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
344 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
345 case VK_BLEND_FACTOR_SRC1_COLOR
:
346 return V_028780_BLEND_SRC1_COLOR
;
347 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
348 return V_028780_BLEND_INV_SRC1_COLOR
;
349 case VK_BLEND_FACTOR_SRC1_ALPHA
:
350 return V_028780_BLEND_SRC1_ALPHA
;
351 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
352 return V_028780_BLEND_INV_SRC1_ALPHA
;
358 static uint32_t si_translate_blend_opt_function(VkBlendOp op
)
361 case VK_BLEND_OP_ADD
:
362 return V_028760_OPT_COMB_ADD
;
363 case VK_BLEND_OP_SUBTRACT
:
364 return V_028760_OPT_COMB_SUBTRACT
;
365 case VK_BLEND_OP_REVERSE_SUBTRACT
:
366 return V_028760_OPT_COMB_REVSUBTRACT
;
367 case VK_BLEND_OP_MIN
:
368 return V_028760_OPT_COMB_MIN
;
369 case VK_BLEND_OP_MAX
:
370 return V_028760_OPT_COMB_MAX
;
372 return V_028760_OPT_COMB_BLEND_DISABLED
;
376 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor
, bool is_alpha
)
379 case VK_BLEND_FACTOR_ZERO
:
380 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
381 case VK_BLEND_FACTOR_ONE
:
382 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
383 case VK_BLEND_FACTOR_SRC_COLOR
:
384 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
385 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
386 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
387 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
388 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
389 case VK_BLEND_FACTOR_SRC_ALPHA
:
390 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
391 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
392 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
393 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
394 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
395 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
397 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
402 * Get rid of DST in the blend factors by commuting the operands:
403 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
405 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
406 unsigned *dst_factor
, unsigned expected_dst
,
407 unsigned replacement_src
)
409 if (*src_factor
== expected_dst
&&
410 *dst_factor
== VK_BLEND_FACTOR_ZERO
) {
411 *src_factor
= VK_BLEND_FACTOR_ZERO
;
412 *dst_factor
= replacement_src
;
414 /* Commuting the operands requires reversing subtractions. */
415 if (*func
== VK_BLEND_OP_SUBTRACT
)
416 *func
= VK_BLEND_OP_REVERSE_SUBTRACT
;
417 else if (*func
== VK_BLEND_OP_REVERSE_SUBTRACT
)
418 *func
= VK_BLEND_OP_SUBTRACT
;
422 static bool si_blend_factor_uses_dst(unsigned factor
)
424 return factor
== VK_BLEND_FACTOR_DST_COLOR
||
425 factor
== VK_BLEND_FACTOR_DST_ALPHA
||
426 factor
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
427 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
||
428 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
;
431 static bool is_dual_src(VkBlendFactor factor
)
434 case VK_BLEND_FACTOR_SRC1_COLOR
:
435 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
436 case VK_BLEND_FACTOR_SRC1_ALPHA
:
437 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
444 static unsigned si_choose_spi_color_format(VkFormat vk_format
,
446 bool blend_need_alpha
)
448 const struct vk_format_description
*desc
= vk_format_description(vk_format
);
449 unsigned format
, ntype
, swap
;
451 /* Alpha is needed for alpha-to-coverage.
452 * Blending may be with or without alpha.
454 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
455 unsigned alpha
= 0; /* exports alpha, but may not support blending */
456 unsigned blend
= 0; /* supports blending, but may not export alpha */
457 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
459 format
= radv_translate_colorformat(vk_format
);
460 ntype
= radv_translate_color_numformat(vk_format
, desc
,
461 vk_format_get_first_non_void_channel(vk_format
));
462 swap
= radv_translate_colorswap(vk_format
, false);
464 /* Choose the SPI color formats. These are required values for Stoney/RB+.
465 * Other chips have multiple choices, though they are not necessarily better.
468 case V_028C70_COLOR_5_6_5
:
469 case V_028C70_COLOR_1_5_5_5
:
470 case V_028C70_COLOR_5_5_5_1
:
471 case V_028C70_COLOR_4_4_4_4
:
472 case V_028C70_COLOR_10_11_11
:
473 case V_028C70_COLOR_11_11_10
:
474 case V_028C70_COLOR_8
:
475 case V_028C70_COLOR_8_8
:
476 case V_028C70_COLOR_8_8_8_8
:
477 case V_028C70_COLOR_10_10_10_2
:
478 case V_028C70_COLOR_2_10_10_10
:
479 if (ntype
== V_028C70_NUMBER_UINT
)
480 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
481 else if (ntype
== V_028C70_NUMBER_SINT
)
482 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
484 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
487 case V_028C70_COLOR_16
:
488 case V_028C70_COLOR_16_16
:
489 case V_028C70_COLOR_16_16_16_16
:
490 if (ntype
== V_028C70_NUMBER_UNORM
||
491 ntype
== V_028C70_NUMBER_SNORM
) {
492 /* UNORM16 and SNORM16 don't support blending */
493 if (ntype
== V_028C70_NUMBER_UNORM
)
494 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
496 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
498 /* Use 32 bits per channel for blending. */
499 if (format
== V_028C70_COLOR_16
) {
500 if (swap
== V_028C70_SWAP_STD
) { /* R */
501 blend
= V_028714_SPI_SHADER_32_R
;
502 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
503 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
504 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
507 } else if (format
== V_028C70_COLOR_16_16
) {
508 if (swap
== V_028C70_SWAP_STD
) { /* RG */
509 blend
= V_028714_SPI_SHADER_32_GR
;
510 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
511 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
512 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
515 } else /* 16_16_16_16 */
516 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
517 } else if (ntype
== V_028C70_NUMBER_UINT
)
518 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
519 else if (ntype
== V_028C70_NUMBER_SINT
)
520 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
521 else if (ntype
== V_028C70_NUMBER_FLOAT
)
522 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
527 case V_028C70_COLOR_32
:
528 if (swap
== V_028C70_SWAP_STD
) { /* R */
529 blend
= normal
= V_028714_SPI_SHADER_32_R
;
530 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
531 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
532 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
537 case V_028C70_COLOR_32_32
:
538 if (swap
== V_028C70_SWAP_STD
) { /* RG */
539 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
540 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
541 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
542 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
547 case V_028C70_COLOR_32_32_32_32
:
548 case V_028C70_COLOR_8_24
:
549 case V_028C70_COLOR_24_8
:
550 case V_028C70_COLOR_X24_8_32_FLOAT
:
551 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
555 unreachable("unhandled blend format");
558 if (blend_enable
&& blend_need_alpha
)
560 else if(blend_need_alpha
)
562 else if(blend_enable
)
569 radv_pipeline_compute_spi_color_formats(struct radv_pipeline
*pipeline
,
570 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
571 struct radv_blend_state
*blend
)
573 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
574 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
575 unsigned col_format
= 0;
576 unsigned num_targets
;
578 for (unsigned i
= 0; i
< (blend
->single_cb_enable
? 1 : subpass
->color_count
); ++i
) {
581 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
582 cf
= V_028714_SPI_SHADER_ZERO
;
584 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
586 blend
->blend_enable_4bit
& (0xfu
<< (i
* 4));
588 cf
= si_choose_spi_color_format(attachment
->format
,
590 blend
->need_src_alpha
& (1 << i
));
593 col_format
|= cf
<< (4 * i
);
596 if (!(col_format
& 0xf) && blend
->need_src_alpha
& (1 << 0)) {
597 /* When a subpass doesn't have any color attachments, write the
598 * alpha channel of MRT0 when alpha coverage is enabled because
599 * the depth attachment needs it.
601 col_format
|= V_028714_SPI_SHADER_32_AR
;
604 /* If the i-th target format is set, all previous target formats must
605 * be non-zero to avoid hangs.
607 num_targets
= (util_last_bit(col_format
) + 3) / 4;
608 for (unsigned i
= 0; i
< num_targets
; i
++) {
609 if (!(col_format
& (0xf << (i
* 4)))) {
610 col_format
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
614 /* The output for dual source blending should have the same format as
617 if (blend
->mrt0_is_dual_src
)
618 col_format
|= (col_format
& 0xf) << 4;
620 blend
->cb_shader_mask
= ac_get_cb_shader_mask(col_format
);
621 blend
->spi_shader_col_format
= col_format
;
625 format_is_int8(VkFormat format
)
627 const struct vk_format_description
*desc
= vk_format_description(format
);
628 int channel
= vk_format_get_first_non_void_channel(format
);
630 return channel
>= 0 && desc
->channel
[channel
].pure_integer
&&
631 desc
->channel
[channel
].size
== 8;
635 format_is_int10(VkFormat format
)
637 const struct vk_format_description
*desc
= vk_format_description(format
);
639 if (desc
->nr_channels
!= 4)
641 for (unsigned i
= 0; i
< 4; i
++) {
642 if (desc
->channel
[i
].pure_integer
&& desc
->channel
[i
].size
== 10)
649 * Ordered so that for each i,
650 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
652 const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
] = {
653 VK_FORMAT_R32_SFLOAT
,
654 VK_FORMAT_R32G32_SFLOAT
,
655 VK_FORMAT_R8G8B8A8_UNORM
,
656 VK_FORMAT_R16G16B16A16_UNORM
,
657 VK_FORMAT_R16G16B16A16_SNORM
,
658 VK_FORMAT_R16G16B16A16_UINT
,
659 VK_FORMAT_R16G16B16A16_SINT
,
660 VK_FORMAT_R32G32B32A32_SFLOAT
,
661 VK_FORMAT_R8G8B8A8_UINT
,
662 VK_FORMAT_R8G8B8A8_SINT
,
663 VK_FORMAT_A2R10G10B10_UINT_PACK32
,
664 VK_FORMAT_A2R10G10B10_SINT_PACK32
,
667 unsigned radv_format_meta_fs_key(VkFormat format
)
669 unsigned col_format
= si_choose_spi_color_format(format
, false, false);
671 assert(col_format
!= V_028714_SPI_SHADER_32_AR
);
672 if (col_format
>= V_028714_SPI_SHADER_32_AR
)
673 --col_format
; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
675 --col_format
; /* Skip V_028714_SPI_SHADER_ZERO */
676 bool is_int8
= format_is_int8(format
);
677 bool is_int10
= format_is_int10(format
);
679 return col_format
+ (is_int8
? 3 : is_int10
? 5 : 0);
683 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
684 unsigned *is_int8
, unsigned *is_int10
)
686 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
687 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
691 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
692 struct radv_render_pass_attachment
*attachment
;
694 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
697 attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
699 if (format_is_int8(attachment
->format
))
701 if (format_is_int10(attachment
->format
))
707 radv_blend_check_commutativity(struct radv_blend_state
*blend
,
708 VkBlendOp op
, VkBlendFactor src
,
709 VkBlendFactor dst
, unsigned chanmask
)
711 /* Src factor is allowed when it does not depend on Dst. */
712 static const uint32_t src_allowed
=
713 (1u << VK_BLEND_FACTOR_ONE
) |
714 (1u << VK_BLEND_FACTOR_SRC_COLOR
) |
715 (1u << VK_BLEND_FACTOR_SRC_ALPHA
) |
716 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
) |
717 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR
) |
718 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA
) |
719 (1u << VK_BLEND_FACTOR_SRC1_COLOR
) |
720 (1u << VK_BLEND_FACTOR_SRC1_ALPHA
) |
721 (1u << VK_BLEND_FACTOR_ZERO
) |
722 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
) |
723 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
) |
724 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
) |
725 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
) |
726 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
) |
727 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
);
729 if (dst
== VK_BLEND_FACTOR_ONE
&&
730 (src_allowed
& (1u << src
))) {
731 /* Addition is commutative, but floating point addition isn't
732 * associative: subtle changes can be introduced via different
733 * rounding. Be conservative, only enable for min and max.
735 if (op
== VK_BLEND_OP_MAX
|| op
== VK_BLEND_OP_MIN
)
736 blend
->commutative_4bit
|= chanmask
;
740 static struct radv_blend_state
741 radv_pipeline_init_blend_state(struct radv_pipeline
*pipeline
,
742 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
743 const struct radv_graphics_pipeline_create_info
*extra
)
745 const VkPipelineColorBlendStateCreateInfo
*vkblend
= radv_pipeline_get_color_blend_state(pCreateInfo
);
746 const VkPipelineMultisampleStateCreateInfo
*vkms
= radv_pipeline_get_multisample_state(pCreateInfo
);
747 struct radv_blend_state blend
= {0};
748 unsigned mode
= V_028808_CB_NORMAL
;
751 if (extra
&& extra
->custom_blend_mode
) {
752 blend
.single_cb_enable
= true;
753 mode
= extra
->custom_blend_mode
;
756 blend
.cb_color_control
= 0;
758 if (vkblend
->logicOpEnable
)
759 blend
.cb_color_control
|= S_028808_ROP3(si_translate_blend_logic_op(vkblend
->logicOp
));
761 blend
.cb_color_control
|= S_028808_ROP3(V_028808_ROP3_COPY
);
764 blend
.db_alpha_to_mask
= S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
765 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
766 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
767 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
768 S_028B70_OFFSET_ROUND(1);
770 if (vkms
&& vkms
->alphaToCoverageEnable
) {
771 blend
.db_alpha_to_mask
|= S_028B70_ALPHA_TO_MASK_ENABLE(1);
772 blend
.need_src_alpha
|= 0x1;
775 blend
.cb_target_mask
= 0;
777 for (i
= 0; i
< vkblend
->attachmentCount
; i
++) {
778 const VkPipelineColorBlendAttachmentState
*att
= &vkblend
->pAttachments
[i
];
779 unsigned blend_cntl
= 0;
780 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
781 VkBlendOp eqRGB
= att
->colorBlendOp
;
782 VkBlendFactor srcRGB
= att
->srcColorBlendFactor
;
783 VkBlendFactor dstRGB
= att
->dstColorBlendFactor
;
784 VkBlendOp eqA
= att
->alphaBlendOp
;
785 VkBlendFactor srcA
= att
->srcAlphaBlendFactor
;
786 VkBlendFactor dstA
= att
->dstAlphaBlendFactor
;
788 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
790 if (!att
->colorWriteMask
)
793 blend
.cb_target_mask
|= (unsigned)att
->colorWriteMask
<< (4 * i
);
794 blend
.cb_target_enabled_4bit
|= 0xf << (4 * i
);
795 if (!att
->blendEnable
) {
796 blend
.cb_blend_control
[i
] = blend_cntl
;
800 if (is_dual_src(srcRGB
) || is_dual_src(dstRGB
) || is_dual_src(srcA
) || is_dual_src(dstA
))
802 blend
.mrt0_is_dual_src
= true;
804 if (eqRGB
== VK_BLEND_OP_MIN
|| eqRGB
== VK_BLEND_OP_MAX
) {
805 srcRGB
= VK_BLEND_FACTOR_ONE
;
806 dstRGB
= VK_BLEND_FACTOR_ONE
;
808 if (eqA
== VK_BLEND_OP_MIN
|| eqA
== VK_BLEND_OP_MAX
) {
809 srcA
= VK_BLEND_FACTOR_ONE
;
810 dstA
= VK_BLEND_FACTOR_ONE
;
813 radv_blend_check_commutativity(&blend
, eqRGB
, srcRGB
, dstRGB
,
815 radv_blend_check_commutativity(&blend
, eqA
, srcA
, dstA
,
818 /* Blending optimizations for RB+.
819 * These transformations don't change the behavior.
821 * First, get rid of DST in the blend factors:
822 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
824 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
825 VK_BLEND_FACTOR_DST_COLOR
,
826 VK_BLEND_FACTOR_SRC_COLOR
);
828 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
829 VK_BLEND_FACTOR_DST_COLOR
,
830 VK_BLEND_FACTOR_SRC_COLOR
);
832 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
833 VK_BLEND_FACTOR_DST_ALPHA
,
834 VK_BLEND_FACTOR_SRC_ALPHA
);
836 /* Look up the ideal settings from tables. */
837 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
838 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
839 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
840 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
842 /* Handle interdependencies. */
843 if (si_blend_factor_uses_dst(srcRGB
))
844 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
845 if (si_blend_factor_uses_dst(srcA
))
846 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
848 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
&&
849 (dstRGB
== VK_BLEND_FACTOR_ZERO
||
850 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
851 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
))
852 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
854 /* Set the final value. */
855 blend
.sx_mrt_blend_opt
[i
] =
856 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
857 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
858 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
859 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
860 S_028760_ALPHA_DST_OPT(dstA_opt
) |
861 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
862 blend_cntl
|= S_028780_ENABLE(1);
864 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
865 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
866 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
867 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
868 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
869 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
870 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
871 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
873 blend
.cb_blend_control
[i
] = blend_cntl
;
875 blend
.blend_enable_4bit
|= 0xfu
<< (i
* 4);
877 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
878 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
879 srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
880 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
881 srcRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
||
882 dstRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
)
883 blend
.need_src_alpha
|= 1 << i
;
885 for (i
= vkblend
->attachmentCount
; i
< 8; i
++) {
886 blend
.cb_blend_control
[i
] = 0;
887 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
891 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
892 /* Disable RB+ blend optimizations for dual source blending. */
893 if (blend
.mrt0_is_dual_src
) {
894 for (i
= 0; i
< 8; i
++) {
895 blend
.sx_mrt_blend_opt
[i
] =
896 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
897 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
901 /* RB+ doesn't work with dual source blending, logic op and
904 if (blend
.mrt0_is_dual_src
||
905 (vkblend
&& vkblend
->logicOpEnable
) ||
906 mode
== V_028808_CB_RESOLVE
)
907 blend
.cb_color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
910 if (blend
.cb_target_mask
)
911 blend
.cb_color_control
|= S_028808_MODE(mode
);
913 blend
.cb_color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
915 radv_pipeline_compute_spi_color_formats(pipeline
, pCreateInfo
, &blend
);
919 static uint32_t si_translate_stencil_op(enum VkStencilOp op
)
922 case VK_STENCIL_OP_KEEP
:
923 return V_02842C_STENCIL_KEEP
;
924 case VK_STENCIL_OP_ZERO
:
925 return V_02842C_STENCIL_ZERO
;
926 case VK_STENCIL_OP_REPLACE
:
927 return V_02842C_STENCIL_REPLACE_TEST
;
928 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
929 return V_02842C_STENCIL_ADD_CLAMP
;
930 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
931 return V_02842C_STENCIL_SUB_CLAMP
;
932 case VK_STENCIL_OP_INVERT
:
933 return V_02842C_STENCIL_INVERT
;
934 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
935 return V_02842C_STENCIL_ADD_WRAP
;
936 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
937 return V_02842C_STENCIL_SUB_WRAP
;
943 static uint32_t si_translate_fill(VkPolygonMode func
)
946 case VK_POLYGON_MODE_FILL
:
947 return V_028814_X_DRAW_TRIANGLES
;
948 case VK_POLYGON_MODE_LINE
:
949 return V_028814_X_DRAW_LINES
;
950 case VK_POLYGON_MODE_POINT
:
951 return V_028814_X_DRAW_POINTS
;
954 return V_028814_X_DRAW_POINTS
;
958 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo
*vkms
)
960 uint32_t num_samples
= vkms
->rasterizationSamples
;
961 uint32_t ps_iter_samples
= 1;
963 if (vkms
->sampleShadingEnable
) {
964 ps_iter_samples
= ceil(vkms
->minSampleShading
* num_samples
);
965 ps_iter_samples
= util_next_power_of_two(ps_iter_samples
);
967 return ps_iter_samples
;
971 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
973 return pCreateInfo
->depthTestEnable
&&
974 pCreateInfo
->depthWriteEnable
&&
975 pCreateInfo
->depthCompareOp
!= VK_COMPARE_OP_NEVER
;
979 radv_writes_stencil(const VkStencilOpState
*state
)
981 return state
->writeMask
&&
982 (state
->failOp
!= VK_STENCIL_OP_KEEP
||
983 state
->passOp
!= VK_STENCIL_OP_KEEP
||
984 state
->depthFailOp
!= VK_STENCIL_OP_KEEP
);
988 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
990 return pCreateInfo
->stencilTestEnable
&&
991 (radv_writes_stencil(&pCreateInfo
->front
) ||
992 radv_writes_stencil(&pCreateInfo
->back
));
996 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
998 return radv_is_depth_write_enabled(pCreateInfo
) ||
999 radv_is_stencil_write_enabled(pCreateInfo
);
1003 radv_order_invariant_stencil_op(VkStencilOp op
)
1005 /* REPLACE is normally order invariant, except when the stencil
1006 * reference value is written by the fragment shader. Tracking this
1007 * interaction does not seem worth the effort, so be conservative.
1009 return op
!= VK_STENCIL_OP_INCREMENT_AND_CLAMP
&&
1010 op
!= VK_STENCIL_OP_DECREMENT_AND_CLAMP
&&
1011 op
!= VK_STENCIL_OP_REPLACE
;
1015 radv_order_invariant_stencil_state(const VkStencilOpState
*state
)
1017 /* Compute whether, assuming Z writes are disabled, this stencil state
1018 * is order invariant in the sense that the set of passing fragments as
1019 * well as the final stencil buffer result does not depend on the order
1022 return !state
->writeMask
||
1023 /* The following assumes that Z writes are disabled. */
1024 (state
->compareOp
== VK_COMPARE_OP_ALWAYS
&&
1025 radv_order_invariant_stencil_op(state
->passOp
) &&
1026 radv_order_invariant_stencil_op(state
->depthFailOp
)) ||
1027 (state
->compareOp
== VK_COMPARE_OP_NEVER
&&
1028 radv_order_invariant_stencil_op(state
->failOp
));
1032 radv_pipeline_out_of_order_rast(struct radv_pipeline
*pipeline
,
1033 struct radv_blend_state
*blend
,
1034 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1036 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1037 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
1038 const VkPipelineDepthStencilStateCreateInfo
*vkds
= radv_pipeline_get_depth_stencil_state(pCreateInfo
);
1039 const VkPipelineColorBlendStateCreateInfo
*vkblend
= radv_pipeline_get_color_blend_state(pCreateInfo
);
1040 unsigned colormask
= blend
->cb_target_enabled_4bit
;
1042 if (!pipeline
->device
->physical_device
->out_of_order_rast_allowed
)
1045 /* Be conservative if a logic operation is enabled with color buffers. */
1046 if (colormask
&& vkblend
&& vkblend
->logicOpEnable
)
1049 /* Default depth/stencil invariance when no attachment is bound. */
1050 struct radv_dsa_order_invariance dsa_order_invariant
= {
1051 .zs
= true, .pass_set
= true
1055 struct radv_render_pass_attachment
*attachment
=
1056 pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
1057 bool has_stencil
= vk_format_is_stencil(attachment
->format
);
1058 struct radv_dsa_order_invariance order_invariance
[2];
1059 struct radv_shader_variant
*ps
=
1060 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
1062 /* Compute depth/stencil order invariance in order to know if
1063 * it's safe to enable out-of-order.
1065 bool zfunc_is_ordered
=
1066 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
||
1067 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS
||
1068 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS_OR_EQUAL
||
1069 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER
||
1070 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER_OR_EQUAL
;
1072 bool nozwrite_and_order_invariant_stencil
=
1073 !radv_is_ds_write_enabled(vkds
) ||
1074 (!radv_is_depth_write_enabled(vkds
) &&
1075 radv_order_invariant_stencil_state(&vkds
->front
) &&
1076 radv_order_invariant_stencil_state(&vkds
->back
));
1078 order_invariance
[1].zs
=
1079 nozwrite_and_order_invariant_stencil
||
1080 (!radv_is_stencil_write_enabled(vkds
) &&
1082 order_invariance
[0].zs
=
1083 !radv_is_depth_write_enabled(vkds
) || zfunc_is_ordered
;
1085 order_invariance
[1].pass_set
=
1086 nozwrite_and_order_invariant_stencil
||
1087 (!radv_is_stencil_write_enabled(vkds
) &&
1088 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1089 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
));
1090 order_invariance
[0].pass_set
=
1091 !radv_is_depth_write_enabled(vkds
) ||
1092 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1093 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
);
1095 dsa_order_invariant
= order_invariance
[has_stencil
];
1096 if (!dsa_order_invariant
.zs
)
1099 /* The set of PS invocations is always order invariant,
1100 * except when early Z/S tests are requested.
1103 ps
->info
.ps
.writes_memory
&&
1104 ps
->info
.ps
.early_fragment_test
&&
1105 !dsa_order_invariant
.pass_set
)
1108 /* Determine if out-of-order rasterization should be disabled
1109 * when occlusion queries are used.
1111 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
=
1112 !dsa_order_invariant
.pass_set
;
1115 /* No color buffers are enabled for writing. */
1119 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
1122 /* Only commutative blending. */
1123 if (blendmask
& ~blend
->commutative_4bit
)
1126 if (!dsa_order_invariant
.pass_set
)
1130 if (colormask
& ~blendmask
)
1137 radv_pipeline_init_multisample_state(struct radv_pipeline
*pipeline
,
1138 struct radv_blend_state
*blend
,
1139 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1141 const VkPipelineMultisampleStateCreateInfo
*vkms
= radv_pipeline_get_multisample_state(pCreateInfo
);
1142 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
1143 unsigned num_tile_pipes
= pipeline
->device
->physical_device
->rad_info
.num_tile_pipes
;
1144 bool out_of_order_rast
= false;
1145 int ps_iter_samples
= 1;
1146 uint32_t mask
= 0xffff;
1149 ms
->num_samples
= vkms
->rasterizationSamples
;
1151 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1153 * "Sample shading is enabled for a graphics pipeline:
1155 * - If the interface of the fragment shader entry point of the
1156 * graphics pipeline includes an input variable decorated
1157 * with SampleId or SamplePosition. In this case
1158 * minSampleShadingFactor takes the value 1.0.
1159 * - Else if the sampleShadingEnable member of the
1160 * VkPipelineMultisampleStateCreateInfo structure specified
1161 * when creating the graphics pipeline is set to VK_TRUE. In
1162 * this case minSampleShadingFactor takes the value of
1163 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1165 * Otherwise, sample shading is considered disabled."
1167 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.force_persample
) {
1168 ps_iter_samples
= ms
->num_samples
;
1170 ps_iter_samples
= radv_pipeline_get_ps_iter_samples(vkms
);
1173 ms
->num_samples
= 1;
1176 const struct VkPipelineRasterizationStateRasterizationOrderAMD
*raster_order
=
1177 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD
);
1178 if (raster_order
&& raster_order
->rasterizationOrder
== VK_RASTERIZATION_ORDER_RELAXED_AMD
) {
1179 /* Out-of-order rasterization is explicitly enabled by the
1182 out_of_order_rast
= true;
1184 /* Determine if the driver can enable out-of-order
1185 * rasterization internally.
1188 radv_pipeline_out_of_order_rast(pipeline
, blend
, pCreateInfo
);
1191 ms
->pa_sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1192 ms
->pa_sc_aa_config
= 0;
1193 ms
->db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1194 S_028804_INCOHERENT_EQAA_READS(1) |
1195 S_028804_INTERPOLATE_COMP_Z(1) |
1196 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1197 ms
->pa_sc_mode_cntl_1
=
1198 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1199 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
1200 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
1201 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1203 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1204 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1205 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1206 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1207 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1208 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1209 ms
->pa_sc_mode_cntl_0
= S_028A48_ALTERNATE_RBS_PER_TILE(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
1210 S_028A48_VPORT_SCISSOR_ENABLE(1);
1212 if (ms
->num_samples
> 1) {
1213 unsigned log_samples
= util_logbase2(ms
->num_samples
);
1214 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
1215 ms
->pa_sc_mode_cntl_0
|= S_028A48_MSAA_ENABLE(1);
1216 ms
->pa_sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1217 ms
->db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_samples
) |
1218 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
1219 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
1220 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
1221 ms
->pa_sc_aa_config
|= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
1222 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples
)) |
1223 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1224 ms
->pa_sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
1225 if (ps_iter_samples
> 1)
1226 pipeline
->graphics
.spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1229 if (vkms
&& vkms
->pSampleMask
) {
1230 mask
= vkms
->pSampleMask
[0] & 0xffff;
1233 ms
->pa_sc_aa_mask
[0] = mask
| (mask
<< 16);
1234 ms
->pa_sc_aa_mask
[1] = mask
| (mask
<< 16);
1238 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology
)
1241 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1242 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1243 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1244 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1245 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1247 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1248 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1249 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1250 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1251 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1252 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1255 unreachable("unhandled primitive type");
1260 si_translate_prim(enum VkPrimitiveTopology topology
)
1263 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1264 return V_008958_DI_PT_POINTLIST
;
1265 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1266 return V_008958_DI_PT_LINELIST
;
1267 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1268 return V_008958_DI_PT_LINESTRIP
;
1269 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1270 return V_008958_DI_PT_TRILIST
;
1271 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1272 return V_008958_DI_PT_TRISTRIP
;
1273 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1274 return V_008958_DI_PT_TRIFAN
;
1275 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1276 return V_008958_DI_PT_LINELIST_ADJ
;
1277 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1278 return V_008958_DI_PT_LINESTRIP_ADJ
;
1279 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1280 return V_008958_DI_PT_TRILIST_ADJ
;
1281 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1282 return V_008958_DI_PT_TRISTRIP_ADJ
;
1283 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1284 return V_008958_DI_PT_PATCH
;
1292 si_conv_gl_prim_to_gs_out(unsigned gl_prim
)
1295 case 0: /* GL_POINTS */
1296 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1297 case 1: /* GL_LINES */
1298 case 3: /* GL_LINE_STRIP */
1299 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1300 case 0x8E7A: /* GL_ISOLINES */
1301 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1303 case 4: /* GL_TRIANGLES */
1304 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1305 case 5: /* GL_TRIANGLE_STRIP */
1306 case 7: /* GL_QUADS */
1307 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1315 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology
)
1318 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1319 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1320 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1321 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1322 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1323 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1324 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1325 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1326 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1327 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1328 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1329 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1330 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1331 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1338 static unsigned radv_dynamic_state_mask(VkDynamicState state
)
1341 case VK_DYNAMIC_STATE_VIEWPORT
:
1342 return RADV_DYNAMIC_VIEWPORT
;
1343 case VK_DYNAMIC_STATE_SCISSOR
:
1344 return RADV_DYNAMIC_SCISSOR
;
1345 case VK_DYNAMIC_STATE_LINE_WIDTH
:
1346 return RADV_DYNAMIC_LINE_WIDTH
;
1347 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
1348 return RADV_DYNAMIC_DEPTH_BIAS
;
1349 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
1350 return RADV_DYNAMIC_BLEND_CONSTANTS
;
1351 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
1352 return RADV_DYNAMIC_DEPTH_BOUNDS
;
1353 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
1354 return RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
1355 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
1356 return RADV_DYNAMIC_STENCIL_WRITE_MASK
;
1357 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
1358 return RADV_DYNAMIC_STENCIL_REFERENCE
;
1359 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT
:
1360 return RADV_DYNAMIC_DISCARD_RECTANGLE
;
1361 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT
:
1362 return RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1364 unreachable("Unhandled dynamic state");
1368 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1370 uint32_t states
= RADV_DYNAMIC_ALL
;
1372 /* If rasterization is disabled we do not care about any of the dynamic states,
1373 * since they are all rasterization related only. */
1374 if (pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
1377 if (!pCreateInfo
->pRasterizationState
->depthBiasEnable
)
1378 states
&= ~RADV_DYNAMIC_DEPTH_BIAS
;
1380 if (!pCreateInfo
->pDepthStencilState
||
1381 !pCreateInfo
->pDepthStencilState
->depthBoundsTestEnable
)
1382 states
&= ~RADV_DYNAMIC_DEPTH_BOUNDS
;
1384 if (!pCreateInfo
->pDepthStencilState
||
1385 !pCreateInfo
->pDepthStencilState
->stencilTestEnable
)
1386 states
&= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK
|
1387 RADV_DYNAMIC_STENCIL_WRITE_MASK
|
1388 RADV_DYNAMIC_STENCIL_REFERENCE
);
1390 if (!vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
))
1391 states
&= ~RADV_DYNAMIC_DISCARD_RECTANGLE
;
1393 if (!pCreateInfo
->pMultisampleState
||
1394 !vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1395 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
))
1396 states
&= ~RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1398 /* TODO: blend constants & line width. */
1405 radv_pipeline_init_dynamic_state(struct radv_pipeline
*pipeline
,
1406 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1408 uint32_t needed_states
= radv_pipeline_needed_dynamic_state(pCreateInfo
);
1409 uint32_t states
= needed_states
;
1410 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1411 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1413 pipeline
->dynamic_state
= default_dynamic_state
;
1414 pipeline
->graphics
.needed_dynamic_state
= needed_states
;
1416 if (pCreateInfo
->pDynamicState
) {
1417 /* Remove all of the states that are marked as dynamic */
1418 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1419 for (uint32_t s
= 0; s
< count
; s
++)
1420 states
&= ~radv_dynamic_state_mask(pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1423 struct radv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1425 if (needed_states
& RADV_DYNAMIC_VIEWPORT
) {
1426 assert(pCreateInfo
->pViewportState
);
1428 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1429 if (states
& RADV_DYNAMIC_VIEWPORT
) {
1430 typed_memcpy(dynamic
->viewport
.viewports
,
1431 pCreateInfo
->pViewportState
->pViewports
,
1432 pCreateInfo
->pViewportState
->viewportCount
);
1436 if (needed_states
& RADV_DYNAMIC_SCISSOR
) {
1437 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1438 if (states
& RADV_DYNAMIC_SCISSOR
) {
1439 typed_memcpy(dynamic
->scissor
.scissors
,
1440 pCreateInfo
->pViewportState
->pScissors
,
1441 pCreateInfo
->pViewportState
->scissorCount
);
1445 if (states
& RADV_DYNAMIC_LINE_WIDTH
) {
1446 assert(pCreateInfo
->pRasterizationState
);
1447 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1450 if (states
& RADV_DYNAMIC_DEPTH_BIAS
) {
1451 assert(pCreateInfo
->pRasterizationState
);
1452 dynamic
->depth_bias
.bias
=
1453 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1454 dynamic
->depth_bias
.clamp
=
1455 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1456 dynamic
->depth_bias
.slope
=
1457 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1460 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1462 * pColorBlendState is [...] NULL if the pipeline has rasterization
1463 * disabled or if the subpass of the render pass the pipeline is
1464 * created against does not use any color attachments.
1466 if (subpass
->has_color_att
&& states
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
1467 assert(pCreateInfo
->pColorBlendState
);
1468 typed_memcpy(dynamic
->blend_constants
,
1469 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1472 /* If there is no depthstencil attachment, then don't read
1473 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1474 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1475 * no need to override the depthstencil defaults in
1476 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1478 * Section 9.2 of the Vulkan 1.0.15 spec says:
1480 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1481 * disabled or if the subpass of the render pass the pipeline is created
1482 * against does not use a depth/stencil attachment.
1484 if (needed_states
&& subpass
->depth_stencil_attachment
) {
1485 assert(pCreateInfo
->pDepthStencilState
);
1487 if (states
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
1488 dynamic
->depth_bounds
.min
=
1489 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1490 dynamic
->depth_bounds
.max
=
1491 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1494 if (states
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
1495 dynamic
->stencil_compare_mask
.front
=
1496 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1497 dynamic
->stencil_compare_mask
.back
=
1498 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1501 if (states
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
1502 dynamic
->stencil_write_mask
.front
=
1503 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1504 dynamic
->stencil_write_mask
.back
=
1505 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1508 if (states
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
1509 dynamic
->stencil_reference
.front
=
1510 pCreateInfo
->pDepthStencilState
->front
.reference
;
1511 dynamic
->stencil_reference
.back
=
1512 pCreateInfo
->pDepthStencilState
->back
.reference
;
1516 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
1517 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
1518 if (needed_states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1519 dynamic
->discard_rectangle
.count
= discard_rectangle_info
->discardRectangleCount
;
1520 if (states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1521 typed_memcpy(dynamic
->discard_rectangle
.rectangles
,
1522 discard_rectangle_info
->pDiscardRectangles
,
1523 discard_rectangle_info
->discardRectangleCount
);
1527 if (needed_states
& RADV_DYNAMIC_SAMPLE_LOCATIONS
) {
1528 const VkPipelineSampleLocationsStateCreateInfoEXT
*sample_location_info
=
1529 vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1530 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
);
1531 /* If sampleLocationsEnable is VK_FALSE, the default sample
1532 * locations are used and the values specified in
1533 * sampleLocationsInfo are ignored.
1535 if (sample_location_info
->sampleLocationsEnable
) {
1536 const VkSampleLocationsInfoEXT
*pSampleLocationsInfo
=
1537 &sample_location_info
->sampleLocationsInfo
;
1539 assert(pSampleLocationsInfo
->sampleLocationsCount
<= MAX_SAMPLE_LOCATIONS
);
1541 dynamic
->sample_location
.per_pixel
= pSampleLocationsInfo
->sampleLocationsPerPixel
;
1542 dynamic
->sample_location
.grid_size
= pSampleLocationsInfo
->sampleLocationGridSize
;
1543 dynamic
->sample_location
.count
= pSampleLocationsInfo
->sampleLocationsCount
;
1544 typed_memcpy(&dynamic
->sample_location
.locations
[0],
1545 pSampleLocationsInfo
->pSampleLocations
,
1546 pSampleLocationsInfo
->sampleLocationsCount
);
1550 pipeline
->dynamic_state
.mask
= states
;
1554 gfx9_get_gs_info(const struct radv_pipeline_key
*key
,
1555 const struct radv_pipeline
*pipeline
,
1557 struct radv_shader_info
*infos
,
1558 struct gfx9_gs_info
*out
)
1560 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1561 struct radv_es_output_info
*es_info
;
1562 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1563 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1565 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ?
1566 &infos
[MESA_SHADER_TESS_EVAL
].tes
.es_info
:
1567 &infos
[MESA_SHADER_VERTEX
].vs
.es_info
;
1569 unsigned gs_num_invocations
= MAX2(gs_info
->gs
.invocations
, 1);
1570 bool uses_adjacency
;
1571 switch(key
->topology
) {
1572 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1573 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1574 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1575 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1576 uses_adjacency
= true;
1579 uses_adjacency
= false;
1583 /* All these are in dwords: */
1584 /* We can't allow using the whole LDS, because GS waves compete with
1585 * other shader stages for LDS space. */
1586 const unsigned max_lds_size
= 8 * 1024;
1587 const unsigned esgs_itemsize
= es_info
->esgs_itemsize
/ 4;
1588 unsigned esgs_lds_size
;
1590 /* All these are per subgroup: */
1591 const unsigned max_out_prims
= 32 * 1024;
1592 const unsigned max_es_verts
= 255;
1593 const unsigned ideal_gs_prims
= 64;
1594 unsigned max_gs_prims
, gs_prims
;
1595 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
1597 if (uses_adjacency
|| gs_num_invocations
> 1)
1598 max_gs_prims
= 127 / gs_num_invocations
;
1602 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1603 * Make sure we don't go over the maximum value.
1605 if (gs_info
->gs
.vertices_out
> 0) {
1606 max_gs_prims
= MIN2(max_gs_prims
,
1608 (gs_info
->gs
.vertices_out
* gs_num_invocations
));
1610 assert(max_gs_prims
> 0);
1612 /* If the primitive has adjacency, halve the number of vertices
1613 * that will be reused in multiple primitives.
1615 min_es_verts
= gs_info
->gs
.vertices_in
/ (uses_adjacency
? 2 : 1);
1617 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
1618 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
1620 /* Compute ESGS LDS size based on the worst case number of ES vertices
1621 * needed to create the target number of GS prims per subgroup.
1623 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1625 /* If total LDS usage is too big, refactor partitions based on ratio
1626 * of ESGS item sizes.
1628 if (esgs_lds_size
> max_lds_size
) {
1629 /* Our target GS Prims Per Subgroup was too large. Calculate
1630 * the maximum number of GS Prims Per Subgroup that will fit
1631 * into LDS, capped by the maximum that the hardware can support.
1633 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
1635 assert(gs_prims
> 0);
1636 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
1639 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1640 assert(esgs_lds_size
<= max_lds_size
);
1643 /* Now calculate remaining ESGS information. */
1645 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
1647 es_verts
= max_es_verts
;
1649 /* Vertices for adjacency primitives are not always reused, so restore
1650 * it for ES_VERTS_PER_SUBGRP.
1652 min_es_verts
= gs_info
->gs
.vertices_in
;
1654 /* For normal primitives, the VGT only checks if they are past the ES
1655 * verts per subgroup after allocating a full GS primitive and if they
1656 * are, kick off a new subgroup. But if those additional ES verts are
1657 * unique (e.g. not reused) we need to make sure there is enough LDS
1658 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1660 es_verts
-= min_es_verts
- 1;
1662 uint32_t es_verts_per_subgroup
= es_verts
;
1663 uint32_t gs_prims_per_subgroup
= gs_prims
;
1664 uint32_t gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
1665 uint32_t max_prims_per_subgroup
= gs_inst_prims_in_subgroup
* gs_info
->gs
.vertices_out
;
1666 out
->lds_size
= align(esgs_lds_size
, 128) / 128;
1667 out
->vgt_gs_onchip_cntl
= S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup
) |
1668 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup
) |
1669 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup
);
1670 out
->vgt_gs_max_prims_per_subgroup
= S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup
);
1671 out
->vgt_esgs_ring_itemsize
= esgs_itemsize
;
1672 assert(max_prims_per_subgroup
<= max_out_prims
);
1675 static void clamp_gsprims_to_esverts(unsigned *max_gsprims
, unsigned max_esverts
,
1676 unsigned min_verts_per_prim
, bool use_adjacency
)
1678 unsigned max_reuse
= max_esverts
- min_verts_per_prim
;
1681 *max_gsprims
= MIN2(*max_gsprims
, 1 + max_reuse
);
1685 radv_get_num_input_vertices(nir_shader
**nir
)
1687 if (nir
[MESA_SHADER_GEOMETRY
]) {
1688 nir_shader
*gs
= nir
[MESA_SHADER_GEOMETRY
];
1690 return gs
->info
.gs
.vertices_in
;
1693 if (nir
[MESA_SHADER_TESS_CTRL
]) {
1694 nir_shader
*tes
= nir
[MESA_SHADER_TESS_EVAL
];
1696 if (tes
->info
.tess
.point_mode
)
1698 if (tes
->info
.tess
.primitive_mode
== GL_ISOLINES
)
1707 gfx10_get_ngg_info(const struct radv_pipeline_key
*key
,
1708 struct radv_pipeline
*pipeline
,
1710 struct radv_shader_info
*infos
,
1711 struct gfx10_ngg_info
*ngg
)
1713 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1714 struct radv_es_output_info
*es_info
=
1715 nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1716 unsigned gs_type
= nir
[MESA_SHADER_GEOMETRY
] ? MESA_SHADER_GEOMETRY
: MESA_SHADER_VERTEX
;
1717 unsigned max_verts_per_prim
= radv_get_num_input_vertices(nir
);
1718 unsigned min_verts_per_prim
=
1719 gs_type
== MESA_SHADER_GEOMETRY
? max_verts_per_prim
: 1;
1720 unsigned gs_num_invocations
= nir
[MESA_SHADER_GEOMETRY
] ? MAX2(gs_info
->gs
.invocations
, 1) : 1;
1721 bool uses_adjacency
;
1722 switch(key
->topology
) {
1723 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1724 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1725 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1726 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1727 uses_adjacency
= true;
1730 uses_adjacency
= false;
1734 /* All these are in dwords: */
1735 /* We can't allow using the whole LDS, because GS waves compete with
1736 * other shader stages for LDS space.
1738 * TODO: We should really take the shader's internal LDS use into
1739 * account. The linker will fail if the size is greater than
1742 const unsigned max_lds_size
= 8 * 1024 - 768;
1743 const unsigned target_lds_size
= max_lds_size
;
1744 unsigned esvert_lds_size
= 0;
1745 unsigned gsprim_lds_size
= 0;
1747 /* All these are per subgroup: */
1748 bool max_vert_out_per_gs_instance
= false;
1749 unsigned max_esverts_base
= 256;
1750 unsigned max_gsprims_base
= 128; /* default prim group size clamp */
1752 /* Hardware has the following non-natural restrictions on the value
1753 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1755 * - at most 252 for any line input primitive type
1756 * - at most 251 for any quad input primitive type
1757 * - at most 251 for triangle strips with adjacency (this happens to
1758 * be the natural limit for triangle *lists* with adjacency)
1760 max_esverts_base
= MIN2(max_esverts_base
, 251 + max_verts_per_prim
- 1);
1762 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1763 unsigned max_out_verts_per_gsprim
=
1764 gs_info
->gs
.vertices_out
* gs_num_invocations
;
1766 if (max_out_verts_per_gsprim
<= 256) {
1767 if (max_out_verts_per_gsprim
) {
1768 max_gsprims_base
= MIN2(max_gsprims_base
,
1769 256 / max_out_verts_per_gsprim
);
1772 /* Use special multi-cycling mode in which each GS
1773 * instance gets its own subgroup. Does not work with
1775 max_vert_out_per_gs_instance
= true;
1776 max_gsprims_base
= 1;
1777 max_out_verts_per_gsprim
= gs_info
->gs
.vertices_out
;
1780 esvert_lds_size
= es_info
->esgs_itemsize
/ 4;
1781 gsprim_lds_size
= (gs_info
->gs
.gsvs_vertex_size
/ 4 + 1) * max_out_verts_per_gsprim
;
1784 /* LDS size for passing data from GS to ES. */
1785 struct radv_streamout_info
*so_info
= nir
[MESA_SHADER_TESS_CTRL
]
1786 ? &infos
[MESA_SHADER_TESS_EVAL
].so
1787 : &infos
[MESA_SHADER_VERTEX
].so
;
1789 if (so_info
->num_outputs
)
1790 esvert_lds_size
= 4 * so_info
->num_outputs
+ 1;
1792 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1793 * corresponding to the ES thread of the provoking vertex. All
1794 * ES threads load and export PrimitiveID for their thread.
1796 if (!nir
[MESA_SHADER_TESS_CTRL
] &&
1797 infos
[MESA_SHADER_VERTEX
].vs
.outinfo
.export_prim_id
)
1798 esvert_lds_size
= MAX2(esvert_lds_size
, 1);
1801 unsigned max_gsprims
= max_gsprims_base
;
1802 unsigned max_esverts
= max_esverts_base
;
1804 if (esvert_lds_size
)
1805 max_esverts
= MIN2(max_esverts
, target_lds_size
/ esvert_lds_size
);
1806 if (gsprim_lds_size
)
1807 max_gsprims
= MIN2(max_gsprims
, target_lds_size
/ gsprim_lds_size
);
1809 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1810 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
, min_verts_per_prim
, uses_adjacency
);
1811 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1813 if (esvert_lds_size
|| gsprim_lds_size
) {
1814 /* Now that we have a rough proportionality between esverts
1815 * and gsprims based on the primitive type, scale both of them
1816 * down simultaneously based on required LDS space.
1818 * We could be smarter about this if we knew how much vertex
1821 unsigned lds_total
= max_esverts
* esvert_lds_size
+
1822 max_gsprims
* gsprim_lds_size
;
1823 if (lds_total
> target_lds_size
) {
1824 max_esverts
= max_esverts
* target_lds_size
/ lds_total
;
1825 max_gsprims
= max_gsprims
* target_lds_size
/ lds_total
;
1827 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1828 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1829 min_verts_per_prim
, uses_adjacency
);
1830 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1834 /* Round up towards full wave sizes for better ALU utilization. */
1835 if (!max_vert_out_per_gs_instance
) {
1836 unsigned orig_max_esverts
;
1837 unsigned orig_max_gsprims
;
1840 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1841 wavesize
= gs_info
->wave_size
;
1843 wavesize
= nir
[MESA_SHADER_TESS_CTRL
]
1844 ? infos
[MESA_SHADER_TESS_EVAL
].wave_size
1845 : infos
[MESA_SHADER_VERTEX
].wave_size
;
1849 orig_max_esverts
= max_esverts
;
1850 orig_max_gsprims
= max_gsprims
;
1852 max_esverts
= align(max_esverts
, wavesize
);
1853 max_esverts
= MIN2(max_esverts
, max_esverts_base
);
1854 if (esvert_lds_size
)
1855 max_esverts
= MIN2(max_esverts
,
1856 (max_lds_size
- max_gsprims
* gsprim_lds_size
) /
1858 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1860 max_gsprims
= align(max_gsprims
, wavesize
);
1861 max_gsprims
= MIN2(max_gsprims
, max_gsprims_base
);
1862 if (gsprim_lds_size
)
1863 max_gsprims
= MIN2(max_gsprims
,
1864 (max_lds_size
- max_esverts
* esvert_lds_size
) /
1866 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1867 min_verts_per_prim
, uses_adjacency
);
1868 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1869 } while (orig_max_esverts
!= max_esverts
|| orig_max_gsprims
!= max_gsprims
);
1872 /* Hardware restriction: minimum value of max_esverts */
1873 max_esverts
= MAX2(max_esverts
, 23 + max_verts_per_prim
);
1875 unsigned max_out_vertices
=
1876 max_vert_out_per_gs_instance
? gs_info
->gs
.vertices_out
:
1877 gs_type
== MESA_SHADER_GEOMETRY
?
1878 max_gsprims
* gs_num_invocations
* gs_info
->gs
.vertices_out
:
1880 assert(max_out_vertices
<= 256);
1882 unsigned prim_amp_factor
= 1;
1883 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1884 /* Number of output primitives per GS input primitive after
1886 prim_amp_factor
= gs_info
->gs
.vertices_out
;
1889 /* The GE only checks against the maximum number of ES verts after
1890 * allocating a full GS primitive. So we need to ensure that whenever
1891 * this check passes, there is enough space for a full primitive without
1894 ngg
->hw_max_esverts
= max_esverts
- max_verts_per_prim
+ 1;
1895 ngg
->max_gsprims
= max_gsprims
;
1896 ngg
->max_out_verts
= max_out_vertices
;
1897 ngg
->prim_amp_factor
= prim_amp_factor
;
1898 ngg
->max_vert_out_per_gs_instance
= max_vert_out_per_gs_instance
;
1899 ngg
->ngg_emit_size
= max_gsprims
* gsprim_lds_size
;
1900 ngg
->esgs_ring_size
= 4 * max_esverts
* esvert_lds_size
;
1902 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1903 ngg
->vgt_esgs_ring_itemsize
= es_info
->esgs_itemsize
/ 4;
1905 ngg
->vgt_esgs_ring_itemsize
= 1;
1908 pipeline
->graphics
.esgs_ring_size
= ngg
->esgs_ring_size
;
1910 assert(ngg
->hw_max_esverts
>= 24); /* HW limitation */
1914 calculate_gs_ring_sizes(struct radv_pipeline
*pipeline
,
1915 const struct gfx9_gs_info
*gs
)
1917 struct radv_device
*device
= pipeline
->device
;
1918 unsigned num_se
= device
->physical_device
->rad_info
.max_se
;
1919 unsigned wave_size
= 64;
1920 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
1921 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1922 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1924 unsigned gs_vertex_reuse
=
1925 (device
->physical_device
->rad_info
.chip_class
>= GFX8
? 32 : 16) * num_se
;
1926 unsigned alignment
= 256 * num_se
;
1927 /* The maximum size is 63.999 MB per SE. */
1928 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
1929 struct radv_shader_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
1931 /* Calculate the minimum size. */
1932 unsigned min_esgs_ring_size
= align(gs
->vgt_esgs_ring_itemsize
* 4 * gs_vertex_reuse
*
1933 wave_size
, alignment
);
1934 /* These are recommended sizes, not minimum sizes. */
1935 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
1936 gs
->vgt_esgs_ring_itemsize
* 4 * gs_info
->gs
.vertices_in
;
1937 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
1938 gs_info
->gs
.max_gsvs_emit_size
;
1940 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
1941 esgs_ring_size
= align(esgs_ring_size
, alignment
);
1942 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
1944 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
1945 pipeline
->graphics
.esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
1947 pipeline
->graphics
.gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
1950 static void si_multiwave_lds_size_workaround(struct radv_device
*device
,
1953 /* If tessellation is all offchip and on-chip GS isn't used, this
1954 * workaround is not needed.
1958 /* SPI barrier management bug:
1959 * Make sure we have at least 4k of LDS in use to avoid the bug.
1960 * It applies to workgroup sizes of more than one wavefront.
1962 if (device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
||
1963 device
->physical_device
->rad_info
.family
== CHIP_KABINI
)
1964 *lds_size
= MAX2(*lds_size
, 8);
1967 struct radv_shader_variant
*
1968 radv_get_shader(struct radv_pipeline
*pipeline
,
1969 gl_shader_stage stage
)
1971 if (stage
== MESA_SHADER_VERTEX
) {
1972 if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
1973 return pipeline
->shaders
[MESA_SHADER_VERTEX
];
1974 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
])
1975 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
1976 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1977 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1978 } else if (stage
== MESA_SHADER_TESS_EVAL
) {
1979 if (!radv_pipeline_has_tess(pipeline
))
1981 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
1982 return pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
1983 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1984 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1986 return pipeline
->shaders
[stage
];
1989 static struct radv_tessellation_state
1990 calculate_tess_state(struct radv_pipeline
*pipeline
,
1991 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1993 unsigned num_tcs_input_cp
;
1994 unsigned num_tcs_output_cp
;
1996 unsigned num_patches
;
1997 struct radv_tessellation_state tess
= {0};
1999 num_tcs_input_cp
= pCreateInfo
->pTessellationState
->patchControlPoints
;
2000 num_tcs_output_cp
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.tcs_vertices_out
; //TCS VERTICES OUT
2001 num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2003 lds_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.lds_size
;
2005 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2006 assert(lds_size
<= 65536);
2007 lds_size
= align(lds_size
, 512) / 512;
2009 assert(lds_size
<= 32768);
2010 lds_size
= align(lds_size
, 256) / 256;
2012 si_multiwave_lds_size_workaround(pipeline
->device
, &lds_size
);
2014 tess
.lds_size
= lds_size
;
2016 tess
.ls_hs_config
= S_028B58_NUM_PATCHES(num_patches
) |
2017 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
2018 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
2019 tess
.num_patches
= num_patches
;
2021 struct radv_shader_variant
*tes
= radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
);
2022 unsigned type
= 0, partitioning
= 0, topology
= 0, distribution_mode
= 0;
2024 switch (tes
->info
.tes
.primitive_mode
) {
2026 type
= V_028B6C_TESS_TRIANGLE
;
2029 type
= V_028B6C_TESS_QUAD
;
2032 type
= V_028B6C_TESS_ISOLINE
;
2036 switch (tes
->info
.tes
.spacing
) {
2037 case TESS_SPACING_EQUAL
:
2038 partitioning
= V_028B6C_PART_INTEGER
;
2040 case TESS_SPACING_FRACTIONAL_ODD
:
2041 partitioning
= V_028B6C_PART_FRAC_ODD
;
2043 case TESS_SPACING_FRACTIONAL_EVEN
:
2044 partitioning
= V_028B6C_PART_FRAC_EVEN
;
2050 bool ccw
= tes
->info
.tes
.ccw
;
2051 const VkPipelineTessellationDomainOriginStateCreateInfo
*domain_origin_state
=
2052 vk_find_struct_const(pCreateInfo
->pTessellationState
,
2053 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO
);
2055 if (domain_origin_state
&& domain_origin_state
->domainOrigin
!= VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT
)
2058 if (tes
->info
.tes
.point_mode
)
2059 topology
= V_028B6C_OUTPUT_POINT
;
2060 else if (tes
->info
.tes
.primitive_mode
== GL_ISOLINES
)
2061 topology
= V_028B6C_OUTPUT_LINE
;
2063 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
2065 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
2067 if (pipeline
->device
->physical_device
->rad_info
.has_distributed_tess
) {
2068 if (pipeline
->device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
2069 pipeline
->device
->physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
2070 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
2072 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
2074 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
2076 tess
.tf_param
= S_028B6C_TYPE(type
) |
2077 S_028B6C_PARTITIONING(partitioning
) |
2078 S_028B6C_TOPOLOGY(topology
) |
2079 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
2084 static const struct radv_prim_vertex_count prim_size_table
[] = {
2085 [V_008958_DI_PT_NONE
] = {0, 0},
2086 [V_008958_DI_PT_POINTLIST
] = {1, 1},
2087 [V_008958_DI_PT_LINELIST
] = {2, 2},
2088 [V_008958_DI_PT_LINESTRIP
] = {2, 1},
2089 [V_008958_DI_PT_TRILIST
] = {3, 3},
2090 [V_008958_DI_PT_TRIFAN
] = {3, 1},
2091 [V_008958_DI_PT_TRISTRIP
] = {3, 1},
2092 [V_008958_DI_PT_LINELIST_ADJ
] = {4, 4},
2093 [V_008958_DI_PT_LINESTRIP_ADJ
] = {4, 1},
2094 [V_008958_DI_PT_TRILIST_ADJ
] = {6, 6},
2095 [V_008958_DI_PT_TRISTRIP_ADJ
] = {6, 2},
2096 [V_008958_DI_PT_RECTLIST
] = {3, 3},
2097 [V_008958_DI_PT_LINELOOP
] = {2, 1},
2098 [V_008958_DI_PT_POLYGON
] = {3, 1},
2099 [V_008958_DI_PT_2D_TRI_STRIP
] = {0, 0},
2102 static const struct radv_vs_output_info
*get_vs_output_info(const struct radv_pipeline
*pipeline
)
2104 if (radv_pipeline_has_gs(pipeline
))
2105 if (radv_pipeline_has_ngg(pipeline
))
2106 return &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.vs
.outinfo
;
2108 return &pipeline
->gs_copy_shader
->info
.vs
.outinfo
;
2109 else if (radv_pipeline_has_tess(pipeline
))
2110 return &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.outinfo
;
2112 return &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.outinfo
;
2116 radv_link_shaders(struct radv_pipeline
*pipeline
, nir_shader
**shaders
)
2118 nir_shader
* ordered_shaders
[MESA_SHADER_STAGES
];
2119 int shader_count
= 0;
2121 if(shaders
[MESA_SHADER_FRAGMENT
]) {
2122 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_FRAGMENT
];
2124 if(shaders
[MESA_SHADER_GEOMETRY
]) {
2125 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_GEOMETRY
];
2127 if(shaders
[MESA_SHADER_TESS_EVAL
]) {
2128 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_EVAL
];
2130 if(shaders
[MESA_SHADER_TESS_CTRL
]) {
2131 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_CTRL
];
2133 if(shaders
[MESA_SHADER_VERTEX
]) {
2134 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_VERTEX
];
2137 if (shader_count
> 1) {
2138 unsigned first
= ordered_shaders
[shader_count
- 1]->info
.stage
;
2139 unsigned last
= ordered_shaders
[0]->info
.stage
;
2141 if (ordered_shaders
[0]->info
.stage
== MESA_SHADER_FRAGMENT
&&
2142 ordered_shaders
[1]->info
.has_transform_feedback_varyings
)
2143 nir_link_xfb_varyings(ordered_shaders
[1], ordered_shaders
[0]);
2145 for (int i
= 0; i
< shader_count
; ++i
) {
2146 nir_variable_mode mask
= 0;
2148 if (ordered_shaders
[i
]->info
.stage
!= first
)
2149 mask
= mask
| nir_var_shader_in
;
2151 if (ordered_shaders
[i
]->info
.stage
!= last
)
2152 mask
= mask
| nir_var_shader_out
;
2154 nir_lower_io_to_scalar_early(ordered_shaders
[i
], mask
);
2155 radv_optimize_nir(ordered_shaders
[i
], false, false);
2159 for (int i
= 1; i
< shader_count
; ++i
) {
2160 nir_lower_io_arrays_to_elements(ordered_shaders
[i
],
2161 ordered_shaders
[i
- 1]);
2163 if (nir_link_opt_varyings(ordered_shaders
[i
],
2164 ordered_shaders
[i
- 1]))
2165 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2167 nir_remove_dead_variables(ordered_shaders
[i
],
2168 nir_var_shader_out
);
2169 nir_remove_dead_variables(ordered_shaders
[i
- 1],
2172 bool progress
= nir_remove_unused_varyings(ordered_shaders
[i
],
2173 ordered_shaders
[i
- 1]);
2175 nir_compact_varyings(ordered_shaders
[i
],
2176 ordered_shaders
[i
- 1], true);
2179 if (nir_lower_global_vars_to_local(ordered_shaders
[i
])) {
2180 ac_lower_indirect_derefs(ordered_shaders
[i
],
2181 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2183 radv_optimize_nir(ordered_shaders
[i
], false, false);
2185 if (nir_lower_global_vars_to_local(ordered_shaders
[i
- 1])) {
2186 ac_lower_indirect_derefs(ordered_shaders
[i
- 1],
2187 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2189 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2195 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo
*input_state
,
2196 uint32_t attrib_binding
)
2198 for (uint32_t i
= 0; i
< input_state
->vertexBindingDescriptionCount
; i
++) {
2199 const VkVertexInputBindingDescription
*input_binding
=
2200 &input_state
->pVertexBindingDescriptions
[i
];
2202 if (input_binding
->binding
== attrib_binding
)
2203 return input_binding
->stride
;
2209 static struct radv_pipeline_key
2210 radv_generate_graphics_pipeline_key(struct radv_pipeline
*pipeline
,
2211 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2212 const struct radv_blend_state
*blend
,
2213 bool has_view_index
)
2215 const VkPipelineVertexInputStateCreateInfo
*input_state
=
2216 pCreateInfo
->pVertexInputState
;
2217 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*divisor_state
=
2218 vk_find_struct_const(input_state
->pNext
, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
2220 struct radv_pipeline_key key
;
2221 memset(&key
, 0, sizeof(key
));
2223 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
2224 key
.optimisations_disabled
= 1;
2226 key
.has_multiview_view_index
= has_view_index
;
2228 uint32_t binding_input_rate
= 0;
2229 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
2230 for (unsigned i
= 0; i
< input_state
->vertexBindingDescriptionCount
; ++i
) {
2231 if (input_state
->pVertexBindingDescriptions
[i
].inputRate
) {
2232 unsigned binding
= input_state
->pVertexBindingDescriptions
[i
].binding
;
2233 binding_input_rate
|= 1u << binding
;
2234 instance_rate_divisors
[binding
] = 1;
2237 if (divisor_state
) {
2238 for (unsigned i
= 0; i
< divisor_state
->vertexBindingDivisorCount
; ++i
) {
2239 instance_rate_divisors
[divisor_state
->pVertexBindingDivisors
[i
].binding
] =
2240 divisor_state
->pVertexBindingDivisors
[i
].divisor
;
2244 for (unsigned i
= 0; i
< input_state
->vertexAttributeDescriptionCount
; ++i
) {
2245 const VkVertexInputAttributeDescription
*desc
=
2246 &input_state
->pVertexAttributeDescriptions
[i
];
2247 const struct vk_format_description
*format_desc
;
2248 unsigned location
= desc
->location
;
2249 unsigned binding
= desc
->binding
;
2250 unsigned num_format
, data_format
;
2253 if (binding_input_rate
& (1u << binding
)) {
2254 key
.instance_rate_inputs
|= 1u << location
;
2255 key
.instance_rate_divisors
[location
] = instance_rate_divisors
[binding
];
2258 format_desc
= vk_format_description(desc
->format
);
2259 first_non_void
= vk_format_get_first_non_void_channel(desc
->format
);
2261 num_format
= radv_translate_buffer_numformat(format_desc
, first_non_void
);
2262 data_format
= radv_translate_buffer_dataformat(format_desc
, first_non_void
);
2264 key
.vertex_attribute_formats
[location
] = data_format
| (num_format
<< 4);
2265 key
.vertex_attribute_bindings
[location
] = desc
->binding
;
2266 key
.vertex_attribute_offsets
[location
] = desc
->offset
;
2267 key
.vertex_attribute_strides
[location
] = radv_get_attrib_stride(input_state
, desc
->binding
);
2269 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
&&
2270 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_STONEY
) {
2271 VkFormat format
= input_state
->pVertexAttributeDescriptions
[i
].format
;
2274 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2275 case VK_FORMAT_A2B10G10R10_SNORM_PACK32
:
2276 adjust
= RADV_ALPHA_ADJUST_SNORM
;
2278 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2279 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32
:
2280 adjust
= RADV_ALPHA_ADJUST_SSCALED
;
2282 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2283 case VK_FORMAT_A2B10G10R10_SINT_PACK32
:
2284 adjust
= RADV_ALPHA_ADJUST_SINT
;
2290 key
.vertex_alpha_adjust
|= adjust
<< (2 * location
);
2293 switch (desc
->format
) {
2294 case VK_FORMAT_B8G8R8A8_UNORM
:
2295 case VK_FORMAT_B8G8R8A8_SNORM
:
2296 case VK_FORMAT_B8G8R8A8_USCALED
:
2297 case VK_FORMAT_B8G8R8A8_SSCALED
:
2298 case VK_FORMAT_B8G8R8A8_UINT
:
2299 case VK_FORMAT_B8G8R8A8_SINT
:
2300 case VK_FORMAT_B8G8R8A8_SRGB
:
2301 case VK_FORMAT_A2R10G10B10_UNORM_PACK32
:
2302 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2303 case VK_FORMAT_A2R10G10B10_USCALED_PACK32
:
2304 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2305 case VK_FORMAT_A2R10G10B10_UINT_PACK32
:
2306 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2307 key
.vertex_post_shuffle
|= 1 << location
;
2314 const VkPipelineTessellationStateCreateInfo
*tess
=
2315 radv_pipeline_get_tessellation_state(pCreateInfo
);
2317 key
.tess_input_vertices
= tess
->patchControlPoints
;
2319 const VkPipelineMultisampleStateCreateInfo
*vkms
=
2320 radv_pipeline_get_multisample_state(pCreateInfo
);
2321 if (vkms
&& vkms
->rasterizationSamples
> 1) {
2322 uint32_t num_samples
= vkms
->rasterizationSamples
;
2323 uint32_t ps_iter_samples
= radv_pipeline_get_ps_iter_samples(vkms
);
2324 key
.num_samples
= num_samples
;
2325 key
.log2_ps_iter_samples
= util_logbase2(ps_iter_samples
);
2328 key
.col_format
= blend
->spi_shader_col_format
;
2329 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX8
)
2330 radv_pipeline_compute_get_int_clamp(pCreateInfo
, &key
.is_int8
, &key
.is_int10
);
2332 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
2333 key
.topology
= pCreateInfo
->pInputAssemblyState
->topology
;
2339 radv_nir_stage_uses_xfb(const nir_shader
*nir
)
2341 nir_xfb_info
*xfb
= nir_gather_xfb_info(nir
, NULL
);
2342 bool uses_xfb
= !!xfb
;
2349 radv_fill_shader_keys(struct radv_device
*device
,
2350 struct radv_shader_variant_key
*keys
,
2351 const struct radv_pipeline_key
*key
,
2354 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_inputs
= key
->instance_rate_inputs
;
2355 keys
[MESA_SHADER_VERTEX
].vs
.alpha_adjust
= key
->vertex_alpha_adjust
;
2356 keys
[MESA_SHADER_VERTEX
].vs
.post_shuffle
= key
->vertex_post_shuffle
;
2357 for (unsigned i
= 0; i
< MAX_VERTEX_ATTRIBS
; ++i
) {
2358 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_divisors
[i
] = key
->instance_rate_divisors
[i
];
2359 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_formats
[i
] = key
->vertex_attribute_formats
[i
];
2360 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_bindings
[i
] = key
->vertex_attribute_bindings
[i
];
2361 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_offsets
[i
] = key
->vertex_attribute_offsets
[i
];
2362 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_strides
[i
] = key
->vertex_attribute_strides
[i
];
2364 keys
[MESA_SHADER_VERTEX
].vs
.outprim
= si_conv_prim_to_gs_out(key
->topology
);
2366 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2367 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ls
= true;
2368 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= 0;
2369 keys
[MESA_SHADER_TESS_CTRL
].tcs
.input_vertices
= key
->tess_input_vertices
;
2370 keys
[MESA_SHADER_TESS_CTRL
].tcs
.primitive_mode
= nir
[MESA_SHADER_TESS_EVAL
]->info
.tess
.primitive_mode
;
2372 keys
[MESA_SHADER_TESS_CTRL
].tcs
.tes_reads_tess_factors
= !!(nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
& (VARYING_BIT_TESS_LEVEL_INNER
| VARYING_BIT_TESS_LEVEL_OUTER
));
2375 if (nir
[MESA_SHADER_GEOMETRY
]) {
2376 if (nir
[MESA_SHADER_TESS_CTRL
])
2377 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_es
= true;
2379 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_es
= true;
2382 if (device
->physical_device
->use_ngg
) {
2383 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2384 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= true;
2386 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= true;
2389 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2390 nir
[MESA_SHADER_GEOMETRY
] &&
2391 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.invocations
*
2392 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.vertices_out
> 256) {
2393 /* Fallback to the legacy path if tessellation is
2394 * enabled with extreme geometry because
2395 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2398 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2402 * Disable NGG with geometry shaders. There are a bunch of
2404 * * GS primitives in pipeline statistic queries do not get
2405 * updates. See dEQP-VK.query_pool.statistics_query.geometry_shader_primitives
2407 * Furthermore, XGL/AMDVLK also disables this as of 9b632ef.
2409 if (nir
[MESA_SHADER_GEOMETRY
]) {
2410 if (nir
[MESA_SHADER_TESS_CTRL
])
2411 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2413 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2416 if (!device
->physical_device
->use_ngg_streamout
) {
2417 gl_shader_stage last_xfb_stage
= MESA_SHADER_VERTEX
;
2419 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2424 if (nir
[last_xfb_stage
] &&
2425 radv_nir_stage_uses_xfb(nir
[last_xfb_stage
])) {
2426 if (nir
[MESA_SHADER_TESS_CTRL
])
2427 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2429 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2434 for(int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
2435 keys
[i
].has_multiview_view_index
= key
->has_multiview_view_index
;
2437 keys
[MESA_SHADER_FRAGMENT
].fs
.col_format
= key
->col_format
;
2438 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int8
= key
->is_int8
;
2439 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int10
= key
->is_int10
;
2440 keys
[MESA_SHADER_FRAGMENT
].fs
.log2_ps_iter_samples
= key
->log2_ps_iter_samples
;
2441 keys
[MESA_SHADER_FRAGMENT
].fs
.num_samples
= key
->num_samples
;
2443 if (nir
[MESA_SHADER_COMPUTE
]) {
2444 keys
[MESA_SHADER_COMPUTE
].cs
.subgroup_size
= key
->compute_subgroup_size
;
2449 radv_get_wave_size(struct radv_device
*device
,
2450 const VkPipelineShaderStageCreateInfo
*pStage
,
2451 gl_shader_stage stage
,
2452 const struct radv_shader_variant_key
*key
)
2454 if (stage
== MESA_SHADER_GEOMETRY
&& !key
->vs_common_out
.as_ngg
)
2456 else if (stage
== MESA_SHADER_COMPUTE
) {
2457 if (key
->cs
.subgroup_size
) {
2458 /* Return the required subgroup size if specified. */
2459 return key
->cs
.subgroup_size
;
2461 return device
->physical_device
->cs_wave_size
;
2463 else if (stage
== MESA_SHADER_FRAGMENT
)
2464 return device
->physical_device
->ps_wave_size
;
2466 return device
->physical_device
->ge_wave_size
;
2470 radv_fill_shader_info(struct radv_pipeline
*pipeline
,
2471 const VkPipelineShaderStageCreateInfo
**pStages
,
2472 struct radv_shader_variant_key
*keys
,
2473 struct radv_shader_info
*infos
,
2476 unsigned active_stages
= 0;
2477 unsigned filled_stages
= 0;
2479 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2481 active_stages
|= (1 << i
);
2484 if (nir
[MESA_SHADER_FRAGMENT
]) {
2485 radv_nir_shader_info_init(&infos
[MESA_SHADER_FRAGMENT
]);
2486 radv_nir_shader_info_pass(nir
[MESA_SHADER_FRAGMENT
],
2488 &keys
[MESA_SHADER_FRAGMENT
],
2489 &infos
[MESA_SHADER_FRAGMENT
]);
2491 /* TODO: These are no longer used as keys we should refactor this */
2492 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
=
2493 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2494 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_layer_id
=
2495 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2496 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_clip_dists
=
2497 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2498 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_prim_id
=
2499 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2500 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_layer_id
=
2501 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2502 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_clip_dists
=
2503 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2505 filled_stages
|= (1 << MESA_SHADER_FRAGMENT
);
2508 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2509 nir
[MESA_SHADER_TESS_CTRL
]) {
2510 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2511 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2512 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2514 radv_nir_shader_info_init(&infos
[MESA_SHADER_TESS_CTRL
]);
2516 for (int i
= 0; i
< 2; i
++) {
2517 radv_nir_shader_info_pass(combined_nir
[i
],
2518 pipeline
->layout
, &key
,
2519 &infos
[MESA_SHADER_TESS_CTRL
]);
2522 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2523 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2524 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2525 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2527 filled_stages
|= (1 << MESA_SHADER_VERTEX
);
2528 filled_stages
|= (1 << MESA_SHADER_TESS_CTRL
);
2531 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2532 nir
[MESA_SHADER_GEOMETRY
]) {
2533 gl_shader_stage pre_stage
= nir
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2534 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2536 radv_nir_shader_info_init(&infos
[MESA_SHADER_GEOMETRY
]);
2538 for (int i
= 0; i
< 2; i
++) {
2539 radv_nir_shader_info_pass(combined_nir
[i
],
2542 &infos
[MESA_SHADER_GEOMETRY
]);
2545 filled_stages
|= (1 << pre_stage
);
2546 filled_stages
|= (1 << MESA_SHADER_GEOMETRY
);
2549 active_stages
^= filled_stages
;
2550 while (active_stages
) {
2551 int i
= u_bit_scan(&active_stages
);
2553 if (i
== MESA_SHADER_TESS_CTRL
) {
2554 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
=
2555 util_last_bit64(infos
[MESA_SHADER_VERTEX
].vs
.ls_outputs_written
);
2558 if (i
== MESA_SHADER_TESS_EVAL
) {
2559 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2560 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2561 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2562 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2565 radv_nir_shader_info_init(&infos
[i
]);
2566 radv_nir_shader_info_pass(nir
[i
], pipeline
->layout
,
2567 &keys
[i
], &infos
[i
]);
2570 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2572 infos
[i
].wave_size
=
2573 radv_get_wave_size(pipeline
->device
, pStages
[i
],
2579 merge_tess_info(struct shader_info
*tes_info
,
2580 const struct shader_info
*tcs_info
)
2582 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2584 * "PointMode. Controls generation of points rather than triangles
2585 * or lines. This functionality defaults to disabled, and is
2586 * enabled if either shader stage includes the execution mode.
2588 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2589 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2590 * and OutputVertices, it says:
2592 * "One mode must be set in at least one of the tessellation
2595 * So, the fields can be set in either the TCS or TES, but they must
2596 * agree if set in both. Our backend looks at TES, so bitwise-or in
2597 * the values from the TCS.
2599 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
2600 tes_info
->tess
.tcs_vertices_out
== 0 ||
2601 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
2602 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
2604 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2605 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2606 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
2607 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
2609 assert(tcs_info
->tess
.primitive_mode
== 0 ||
2610 tes_info
->tess
.primitive_mode
== 0 ||
2611 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
2612 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
2613 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
2614 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
2618 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT
*ext
)
2623 if (ext
->pPipelineCreationFeedback
) {
2624 ext
->pPipelineCreationFeedback
->flags
= 0;
2625 ext
->pPipelineCreationFeedback
->duration
= 0;
2628 for (unsigned i
= 0; i
< ext
->pipelineStageCreationFeedbackCount
; ++i
) {
2629 ext
->pPipelineStageCreationFeedbacks
[i
].flags
= 0;
2630 ext
->pPipelineStageCreationFeedbacks
[i
].duration
= 0;
2635 void radv_start_feedback(VkPipelineCreationFeedbackEXT
*feedback
)
2640 feedback
->duration
-= radv_get_current_time();
2641 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
2645 void radv_stop_feedback(VkPipelineCreationFeedbackEXT
*feedback
, bool cache_hit
)
2650 feedback
->duration
+= radv_get_current_time();
2651 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
|
2652 (cache_hit
? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
: 0);
2656 bool radv_aco_supported_stage(gl_shader_stage stage
, bool has_gs
, bool has_ts
)
2658 return (stage
== MESA_SHADER_VERTEX
&& !has_gs
&& !has_ts
) ||
2659 stage
== MESA_SHADER_FRAGMENT
||
2660 stage
== MESA_SHADER_COMPUTE
;
2663 void radv_create_shaders(struct radv_pipeline
*pipeline
,
2664 struct radv_device
*device
,
2665 struct radv_pipeline_cache
*cache
,
2666 const struct radv_pipeline_key
*key
,
2667 const VkPipelineShaderStageCreateInfo
**pStages
,
2668 const VkPipelineCreateFlags flags
,
2669 VkPipelineCreationFeedbackEXT
*pipeline_feedback
,
2670 VkPipelineCreationFeedbackEXT
**stage_feedbacks
)
2672 struct radv_shader_module fs_m
= {0};
2673 struct radv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
2674 nir_shader
*nir
[MESA_SHADER_STAGES
] = {0};
2675 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2676 struct radv_shader_variant_key keys
[MESA_SHADER_STAGES
] = {{{{{0}}}}};
2677 struct radv_shader_info infos
[MESA_SHADER_STAGES
] = {0};
2678 unsigned char hash
[20], gs_copy_hash
[20];
2679 bool keep_executable_info
= (flags
& VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
) || device
->keep_shader_info
;
2681 radv_start_feedback(pipeline_feedback
);
2683 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2685 modules
[i
] = radv_shader_module_from_handle(pStages
[i
]->module
);
2686 if (modules
[i
]->nir
)
2687 _mesa_sha1_compute(modules
[i
]->nir
->info
.name
,
2688 strlen(modules
[i
]->nir
->info
.name
),
2691 pipeline
->active_stages
|= mesa_to_vk_shader_stage(i
);
2695 radv_hash_shaders(hash
, pStages
, pipeline
->layout
, key
, get_hash_flags(device
));
2696 memcpy(gs_copy_hash
, hash
, 20);
2697 gs_copy_hash
[0] ^= 1;
2699 bool found_in_application_cache
= true;
2700 if (modules
[MESA_SHADER_GEOMETRY
] && !keep_executable_info
) {
2701 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2702 radv_create_shader_variants_from_pipeline_cache(device
, cache
, gs_copy_hash
, variants
,
2703 &found_in_application_cache
);
2704 pipeline
->gs_copy_shader
= variants
[MESA_SHADER_GEOMETRY
];
2707 if (!keep_executable_info
&&
2708 radv_create_shader_variants_from_pipeline_cache(device
, cache
, hash
, pipeline
->shaders
,
2709 &found_in_application_cache
) &&
2710 (!modules
[MESA_SHADER_GEOMETRY
] || pipeline
->gs_copy_shader
)) {
2711 radv_stop_feedback(pipeline_feedback
, found_in_application_cache
);
2715 if (!modules
[MESA_SHADER_FRAGMENT
] && !modules
[MESA_SHADER_COMPUTE
]) {
2717 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
2718 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "noop_fs");
2719 fs_m
.nir
= fs_b
.shader
;
2720 modules
[MESA_SHADER_FRAGMENT
] = &fs_m
;
2723 bool has_gs
= modules
[MESA_SHADER_GEOMETRY
];
2724 bool has_ts
= modules
[MESA_SHADER_TESS_CTRL
] || modules
[MESA_SHADER_TESS_EVAL
];
2725 bool use_aco
= device
->physical_device
->use_aco
;
2727 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2728 const VkPipelineShaderStageCreateInfo
*stage
= pStages
[i
];
2733 radv_start_feedback(stage_feedbacks
[i
]);
2735 bool aco
= use_aco
&& radv_aco_supported_stage(i
, has_gs
, has_ts
);
2736 nir
[i
] = radv_shader_compile_to_nir(device
, modules
[i
],
2737 stage
? stage
->pName
: "main", i
,
2738 stage
? stage
->pSpecializationInfo
: NULL
,
2739 flags
, pipeline
->layout
, aco
);
2741 /* We don't want to alter meta shaders IR directly so clone it
2744 if (nir
[i
]->info
.name
) {
2745 nir
[i
] = nir_shader_clone(NULL
, nir
[i
]);
2748 radv_stop_feedback(stage_feedbacks
[i
], false);
2751 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2752 nir_lower_patch_vertices(nir
[MESA_SHADER_TESS_EVAL
], nir
[MESA_SHADER_TESS_CTRL
]->info
.tess
.tcs_vertices_out
, NULL
);
2753 merge_tess_info(&nir
[MESA_SHADER_TESS_EVAL
]->info
, &nir
[MESA_SHADER_TESS_CTRL
]->info
);
2756 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
2757 radv_link_shaders(pipeline
, nir
);
2759 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2761 NIR_PASS_V(nir
[i
], nir_lower_non_uniform_access
,
2762 nir_lower_non_uniform_ubo_access
|
2763 nir_lower_non_uniform_ssbo_access
|
2764 nir_lower_non_uniform_texture_access
|
2765 nir_lower_non_uniform_image_access
);
2767 bool aco
= use_aco
&& radv_aco_supported_stage(i
, has_gs
, has_ts
);
2769 NIR_PASS_V(nir
[i
], nir_lower_bool_to_int32
);
2772 if (radv_can_dump_shader(device
, modules
[i
], false))
2773 nir_print_shader(nir
[i
], stderr
);
2776 if (nir
[MESA_SHADER_FRAGMENT
])
2777 radv_lower_fs_io(nir
[MESA_SHADER_FRAGMENT
]);
2779 radv_fill_shader_keys(device
, keys
, key
, nir
);
2781 radv_fill_shader_info(pipeline
, pStages
, keys
, infos
, nir
);
2783 if ((nir
[MESA_SHADER_VERTEX
] &&
2784 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) ||
2785 (nir
[MESA_SHADER_TESS_EVAL
] &&
2786 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
)) {
2787 struct gfx10_ngg_info
*ngg_info
;
2789 if (nir
[MESA_SHADER_GEOMETRY
])
2790 ngg_info
= &infos
[MESA_SHADER_GEOMETRY
].ngg_info
;
2791 else if (nir
[MESA_SHADER_TESS_CTRL
])
2792 ngg_info
= &infos
[MESA_SHADER_TESS_EVAL
].ngg_info
;
2794 ngg_info
= &infos
[MESA_SHADER_VERTEX
].ngg_info
;
2796 gfx10_get_ngg_info(key
, pipeline
, nir
, infos
, ngg_info
);
2797 } else if (nir
[MESA_SHADER_GEOMETRY
]) {
2798 struct gfx9_gs_info
*gs_info
=
2799 &infos
[MESA_SHADER_GEOMETRY
].gs_ring_info
;
2801 gfx9_get_gs_info(key
, pipeline
, nir
, infos
, gs_info
);
2804 if (nir
[MESA_SHADER_FRAGMENT
]) {
2805 if (!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]) {
2806 radv_start_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
]);
2808 bool aco
= use_aco
&& radv_aco_supported_stage(MESA_SHADER_FRAGMENT
, has_gs
, has_ts
);
2809 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] =
2810 radv_shader_variant_compile(device
, modules
[MESA_SHADER_FRAGMENT
], &nir
[MESA_SHADER_FRAGMENT
], 1,
2811 pipeline
->layout
, keys
+ MESA_SHADER_FRAGMENT
,
2812 infos
+ MESA_SHADER_FRAGMENT
,
2813 keep_executable_info
, aco
,
2814 &binaries
[MESA_SHADER_FRAGMENT
]);
2816 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
], false);
2819 /* TODO: These are no longer used as keys we should refactor this */
2820 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
=
2821 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.prim_id_input
;
2822 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_layer_id
=
2823 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.layer_input
;
2824 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_clip_dists
=
2825 !!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.num_input_clips_culls
;
2826 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_prim_id
=
2827 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.prim_id_input
;
2828 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_layer_id
=
2829 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.layer_input
;
2830 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_clip_dists
=
2831 !!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.num_input_clips_culls
;
2834 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_TESS_CTRL
]) {
2835 if (!pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]) {
2836 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2837 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2838 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2840 radv_start_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
]);
2842 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_TESS_CTRL
], combined_nir
, 2,
2844 &key
, &infos
[MESA_SHADER_TESS_CTRL
], keep_executable_info
,
2845 false, &binaries
[MESA_SHADER_TESS_CTRL
]);
2847 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
], false);
2849 modules
[MESA_SHADER_VERTEX
] = NULL
;
2850 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2851 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2854 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_GEOMETRY
]) {
2855 gl_shader_stage pre_stage
= modules
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2856 if (!pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
2857 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2859 radv_start_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
]);
2861 pipeline
->shaders
[MESA_SHADER_GEOMETRY
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_GEOMETRY
], combined_nir
, 2,
2863 &keys
[pre_stage
], &infos
[MESA_SHADER_GEOMETRY
], keep_executable_info
,
2864 false, &binaries
[MESA_SHADER_GEOMETRY
]);
2866 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
], false);
2868 modules
[pre_stage
] = NULL
;
2871 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2872 if(modules
[i
] && !pipeline
->shaders
[i
]) {
2873 if (i
== MESA_SHADER_TESS_CTRL
) {
2874 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.ls_outputs_written
);
2876 if (i
== MESA_SHADER_TESS_EVAL
) {
2877 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2878 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2881 radv_start_feedback(stage_feedbacks
[i
]);
2883 bool aco
= use_aco
&& radv_aco_supported_stage(i
, has_gs
, has_ts
);
2884 pipeline
->shaders
[i
] = radv_shader_variant_compile(device
, modules
[i
], &nir
[i
], 1,
2886 keys
+ i
, infos
+ i
,keep_executable_info
,
2889 radv_stop_feedback(stage_feedbacks
[i
], false);
2893 if(modules
[MESA_SHADER_GEOMETRY
]) {
2894 struct radv_shader_binary
*gs_copy_binary
= NULL
;
2895 if (!pipeline
->gs_copy_shader
&&
2896 !radv_pipeline_has_ngg(pipeline
)) {
2897 struct radv_shader_info info
= {};
2898 struct radv_shader_variant_key key
= {};
2900 key
.has_multiview_view_index
=
2901 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
;
2903 radv_nir_shader_info_pass(nir
[MESA_SHADER_GEOMETRY
],
2904 pipeline
->layout
, &key
,
2906 info
.wave_size
= 64; /* Wave32 not supported. */
2908 pipeline
->gs_copy_shader
= radv_create_gs_copy_shader(
2909 device
, nir
[MESA_SHADER_GEOMETRY
], &info
,
2910 &gs_copy_binary
, keep_executable_info
,
2911 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
);
2914 if (!keep_executable_info
&& pipeline
->gs_copy_shader
) {
2915 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2916 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2918 binaries
[MESA_SHADER_GEOMETRY
] = gs_copy_binary
;
2919 variants
[MESA_SHADER_GEOMETRY
] = pipeline
->gs_copy_shader
;
2921 radv_pipeline_cache_insert_shaders(device
, cache
,
2926 free(gs_copy_binary
);
2929 if (!keep_executable_info
) {
2930 radv_pipeline_cache_insert_shaders(device
, cache
, hash
, pipeline
->shaders
,
2934 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2937 ralloc_free(nir
[i
]);
2939 if (radv_can_dump_shader_stats(device
, modules
[i
]))
2940 radv_shader_dump_stats(device
,
2941 pipeline
->shaders
[i
],
2947 ralloc_free(fs_m
.nir
);
2949 radv_stop_feedback(pipeline_feedback
, false);
2953 radv_pipeline_stage_to_user_data_0(struct radv_pipeline
*pipeline
,
2954 gl_shader_stage stage
, enum chip_class chip_class
)
2956 bool has_gs
= radv_pipeline_has_gs(pipeline
);
2957 bool has_tess
= radv_pipeline_has_tess(pipeline
);
2958 bool has_ngg
= radv_pipeline_has_ngg(pipeline
);
2961 case MESA_SHADER_FRAGMENT
:
2962 return R_00B030_SPI_SHADER_USER_DATA_PS_0
;
2963 case MESA_SHADER_VERTEX
:
2965 if (chip_class
>= GFX10
) {
2966 return R_00B430_SPI_SHADER_USER_DATA_HS_0
;
2967 } else if (chip_class
== GFX9
) {
2968 return R_00B430_SPI_SHADER_USER_DATA_LS_0
;
2970 return R_00B530_SPI_SHADER_USER_DATA_LS_0
;
2976 if (chip_class
>= GFX10
) {
2977 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
2979 return R_00B330_SPI_SHADER_USER_DATA_ES_0
;
2984 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
2986 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2987 case MESA_SHADER_GEOMETRY
:
2988 return chip_class
== GFX9
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
2989 R_00B230_SPI_SHADER_USER_DATA_GS_0
;
2990 case MESA_SHADER_COMPUTE
:
2991 return R_00B900_COMPUTE_USER_DATA_0
;
2992 case MESA_SHADER_TESS_CTRL
:
2993 return chip_class
== GFX9
? R_00B430_SPI_SHADER_USER_DATA_LS_0
:
2994 R_00B430_SPI_SHADER_USER_DATA_HS_0
;
2995 case MESA_SHADER_TESS_EVAL
:
2997 return chip_class
>= GFX10
? R_00B230_SPI_SHADER_USER_DATA_GS_0
:
2998 R_00B330_SPI_SHADER_USER_DATA_ES_0
;
2999 } else if (has_ngg
) {
3000 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3002 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3005 unreachable("unknown shader");
3009 struct radv_bin_size_entry
{
3015 radv_gfx9_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3017 static const struct radv_bin_size_entry color_size_table
[][3][9] = {
3021 /* One shader engine */
3027 { UINT_MAX
, { 0, 0}},
3030 /* Two shader engines */
3036 { UINT_MAX
, { 0, 0}},
3039 /* Four shader engines */
3044 { UINT_MAX
, { 0, 0}},
3050 /* One shader engine */
3056 { UINT_MAX
, { 0, 0}},
3059 /* Two shader engines */
3065 { UINT_MAX
, { 0, 0}},
3068 /* Four shader engines */
3075 { UINT_MAX
, { 0, 0}},
3081 /* One shader engine */
3088 { UINT_MAX
, { 0, 0}},
3091 /* Two shader engines */
3099 { UINT_MAX
, { 0, 0}},
3102 /* Four shader engines */
3110 { UINT_MAX
, { 0, 0}},
3114 static const struct radv_bin_size_entry ds_size_table
[][3][9] = {
3118 // One shader engine
3125 { UINT_MAX
, { 0, 0}},
3128 // Two shader engines
3136 { UINT_MAX
, { 0, 0}},
3139 // Four shader engines
3147 { UINT_MAX
, { 0, 0}},
3153 // One shader engine
3161 { UINT_MAX
, { 0, 0}},
3164 // Two shader engines
3173 { UINT_MAX
, { 0, 0}},
3176 // Four shader engines
3185 { UINT_MAX
, { 0, 0}},
3191 // One shader engine
3199 { UINT_MAX
, { 0, 0}},
3202 // Two shader engines
3211 { UINT_MAX
, { 0, 0}},
3214 // Four shader engines
3222 { UINT_MAX
, { 0, 0}},
3227 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3228 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3229 VkExtent2D extent
= {512, 512};
3231 unsigned log_num_rb_per_se
=
3232 util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.num_render_backends
/
3233 pipeline
->device
->physical_device
->rad_info
.max_se
);
3234 unsigned log_num_se
= util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.max_se
);
3236 unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3237 unsigned ps_iter_samples
= 1u << G_028804_PS_ITER_SAMPLES(pipeline
->graphics
.ms
.db_eqaa
);
3238 unsigned effective_samples
= total_samples
;
3239 unsigned color_bytes_per_pixel
= 0;
3241 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3242 radv_pipeline_get_color_blend_state(pCreateInfo
);
3244 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3245 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3248 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3251 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3252 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3255 /* MSAA images typically don't use all samples all the time. */
3256 if (effective_samples
>= 2 && ps_iter_samples
<= 1)
3257 effective_samples
= 2;
3258 color_bytes_per_pixel
*= effective_samples
;
3261 const struct radv_bin_size_entry
*color_entry
= color_size_table
[log_num_rb_per_se
][log_num_se
];
3262 while(color_entry
[1].bpp
<= color_bytes_per_pixel
)
3265 extent
= color_entry
->extent
;
3267 if (subpass
->depth_stencil_attachment
) {
3268 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3270 /* Coefficients taken from AMDVLK */
3271 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3272 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3273 unsigned ds_bytes_per_pixel
= 4 * (depth_coeff
+ stencil_coeff
) * total_samples
;
3275 const struct radv_bin_size_entry
*ds_entry
= ds_size_table
[log_num_rb_per_se
][log_num_se
];
3276 while(ds_entry
[1].bpp
<= ds_bytes_per_pixel
)
3279 if (ds_entry
->extent
.width
* ds_entry
->extent
.height
< extent
.width
* extent
.height
)
3280 extent
= ds_entry
->extent
;
3287 radv_gfx10_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3289 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3290 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3291 VkExtent2D extent
= {512, 512};
3293 const unsigned db_tag_size
= 64;
3294 const unsigned db_tag_count
= 312;
3295 const unsigned color_tag_size
= 1024;
3296 const unsigned color_tag_count
= 31;
3297 const unsigned fmask_tag_size
= 256;
3298 const unsigned fmask_tag_count
= 44;
3300 const unsigned rb_count
= pipeline
->device
->physical_device
->rad_info
.num_render_backends
;
3301 const unsigned pipe_count
= MAX2(rb_count
, pipeline
->device
->physical_device
->rad_info
.num_sdp_interfaces
);
3303 const unsigned db_tag_part
= (db_tag_count
* rb_count
/ pipe_count
) * db_tag_size
* pipe_count
;
3304 const unsigned color_tag_part
= (color_tag_count
* rb_count
/ pipe_count
) * color_tag_size
* pipe_count
;
3305 const unsigned fmask_tag_part
= (fmask_tag_count
* rb_count
/ pipe_count
) * fmask_tag_size
* pipe_count
;
3307 const unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3308 const unsigned samples_log
= util_logbase2_ceil(total_samples
);
3310 unsigned color_bytes_per_pixel
= 0;
3311 unsigned fmask_bytes_per_pixel
= 0;
3313 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3314 radv_pipeline_get_color_blend_state(pCreateInfo
);
3316 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3317 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3320 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3323 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3324 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3326 if (total_samples
> 1) {
3327 assert(samples_log
<= 3);
3328 const unsigned fmask_array
[] = {0, 1, 1, 4};
3329 fmask_bytes_per_pixel
+= fmask_array
[samples_log
];
3333 color_bytes_per_pixel
*= total_samples
;
3335 color_bytes_per_pixel
= MAX2(color_bytes_per_pixel
, 1);
3337 const unsigned color_pixel_count_log
= util_logbase2(color_tag_part
/ color_bytes_per_pixel
);
3338 extent
.width
= 1ull << ((color_pixel_count_log
+ 1) / 2);
3339 extent
.height
= 1ull << (color_pixel_count_log
/ 2);
3341 if (fmask_bytes_per_pixel
) {
3342 const unsigned fmask_pixel_count_log
= util_logbase2(fmask_tag_part
/ fmask_bytes_per_pixel
);
3344 const VkExtent2D fmask_extent
= (VkExtent2D
){
3345 .width
= 1ull << ((fmask_pixel_count_log
+ 1) / 2),
3346 .height
= 1ull << (color_pixel_count_log
/ 2)
3349 if (fmask_extent
.width
* fmask_extent
.height
< extent
.width
* extent
.height
)
3350 extent
= fmask_extent
;
3353 if (subpass
->depth_stencil_attachment
) {
3354 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3356 /* Coefficients taken from AMDVLK */
3357 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3358 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3359 unsigned db_bytes_per_pixel
= (depth_coeff
+ stencil_coeff
) * total_samples
;
3361 const unsigned db_pixel_count_log
= util_logbase2(db_tag_part
/ db_bytes_per_pixel
);
3363 const VkExtent2D db_extent
= (VkExtent2D
){
3364 .width
= 1ull << ((db_pixel_count_log
+ 1) / 2),
3365 .height
= 1ull << (color_pixel_count_log
/ 2)
3368 if (db_extent
.width
* db_extent
.height
< extent
.width
* extent
.height
)
3372 extent
.width
= MAX2(extent
.width
, 128);
3373 extent
.height
= MAX2(extent
.width
, 64);
3379 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3380 struct radv_pipeline
*pipeline
,
3381 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3383 uint32_t pa_sc_binner_cntl_0
=
3384 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC
) |
3385 S_028C44_DISABLE_START_OF_PRIM(1);
3386 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3388 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3389 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3390 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3391 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3392 radv_pipeline_get_color_blend_state(pCreateInfo
);
3393 unsigned min_bytes_per_pixel
= 0;
3396 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3397 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3400 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3403 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3404 unsigned bytes
= vk_format_get_blocksize(format
);
3405 if (!min_bytes_per_pixel
|| bytes
< min_bytes_per_pixel
)
3406 min_bytes_per_pixel
= bytes
;
3410 pa_sc_binner_cntl_0
=
3411 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC
) |
3412 S_028C44_BIN_SIZE_X(0) |
3413 S_028C44_BIN_SIZE_Y(0) |
3414 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3415 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel
<= 4 ? 2 : 1) | /* 128 or 64 */
3416 S_028C44_DISABLE_START_OF_PRIM(1);
3419 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3420 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3424 radv_pipeline_generate_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3425 struct radv_pipeline
*pipeline
,
3426 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3427 const struct radv_blend_state
*blend
)
3429 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
3432 VkExtent2D bin_size
;
3433 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3434 bin_size
= radv_gfx10_compute_bin_size(pipeline
, pCreateInfo
);
3435 } else if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3436 bin_size
= radv_gfx9_compute_bin_size(pipeline
, pCreateInfo
);
3438 unreachable("Unhandled generation for binning bin size calculation");
3440 if (pipeline
->device
->pbb_allowed
&& bin_size
.width
&& bin_size
.height
) {
3441 unsigned context_states_per_bin
; /* allowed range: [1, 6] */
3442 unsigned persistent_states_per_bin
; /* allowed range: [1, 32] */
3443 unsigned fpovs_per_batch
; /* allowed range: [0, 255], 0 = unlimited */
3445 if (pipeline
->device
->physical_device
->rad_info
.has_dedicated_vram
) {
3446 context_states_per_bin
= 1;
3447 persistent_states_per_bin
= 1;
3448 fpovs_per_batch
= 63;
3450 /* The context states are affected by the scissor bug. */
3451 context_states_per_bin
= pipeline
->device
->physical_device
->rad_info
.has_gfx9_scissor_bug
? 1 : 6;
3452 /* 32 causes hangs for RAVEN. */
3453 persistent_states_per_bin
= 16;
3454 fpovs_per_batch
= 63;
3457 bool disable_start_of_prim
= true;
3458 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3460 const struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3462 if (pipeline
->device
->dfsm_allowed
&& ps
&&
3463 !ps
->info
.ps
.can_discard
&&
3464 !ps
->info
.ps
.writes_memory
&&
3465 blend
->cb_target_enabled_4bit
) {
3466 db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_AUTO
);
3467 disable_start_of_prim
= (blend
->blend_enable_4bit
& blend
->cb_target_enabled_4bit
) != 0;
3470 const uint32_t pa_sc_binner_cntl_0
=
3471 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED
) |
3472 S_028C44_BIN_SIZE_X(bin_size
.width
== 16) |
3473 S_028C44_BIN_SIZE_Y(bin_size
.height
== 16) |
3474 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size
.width
, 32)) - 5) |
3475 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size
.height
, 32)) - 5) |
3476 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin
- 1) |
3477 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin
- 1) |
3478 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim
) |
3479 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch
) |
3480 S_028C44_OPTIMAL_BIN_SELECTION(1);
3482 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3483 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3485 radv_pipeline_generate_disabled_binning_state(ctx_cs
, pipeline
, pCreateInfo
);
3490 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf
*ctx_cs
,
3491 struct radv_pipeline
*pipeline
,
3492 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3493 const struct radv_graphics_pipeline_create_info
*extra
)
3495 const VkPipelineDepthStencilStateCreateInfo
*vkds
= radv_pipeline_get_depth_stencil_state(pCreateInfo
);
3496 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3497 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3498 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3499 struct radv_render_pass_attachment
*attachment
= NULL
;
3500 uint32_t db_depth_control
= 0, db_stencil_control
= 0;
3501 uint32_t db_render_control
= 0, db_render_override2
= 0;
3502 uint32_t db_render_override
= 0;
3504 if (subpass
->depth_stencil_attachment
)
3505 attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3507 bool has_depth_attachment
= attachment
&& vk_format_is_depth(attachment
->format
);
3508 bool has_stencil_attachment
= attachment
&& vk_format_is_stencil(attachment
->format
);
3510 if (vkds
&& has_depth_attachment
) {
3511 db_depth_control
= S_028800_Z_ENABLE(vkds
->depthTestEnable
? 1 : 0) |
3512 S_028800_Z_WRITE_ENABLE(vkds
->depthWriteEnable
? 1 : 0) |
3513 S_028800_ZFUNC(vkds
->depthCompareOp
) |
3514 S_028800_DEPTH_BOUNDS_ENABLE(vkds
->depthBoundsTestEnable
? 1 : 0);
3516 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3517 db_render_override2
|= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment
->samples
> 2);
3520 if (has_stencil_attachment
&& vkds
&& vkds
->stencilTestEnable
) {
3521 db_depth_control
|= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3522 db_depth_control
|= S_028800_STENCILFUNC(vkds
->front
.compareOp
);
3523 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds
->front
.failOp
));
3524 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds
->front
.passOp
));
3525 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds
->front
.depthFailOp
));
3527 db_depth_control
|= S_028800_STENCILFUNC_BF(vkds
->back
.compareOp
);
3528 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds
->back
.failOp
));
3529 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds
->back
.passOp
));
3530 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds
->back
.depthFailOp
));
3533 if (attachment
&& extra
) {
3534 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(extra
->db_depth_clear
);
3535 db_render_control
|= S_028000_STENCIL_CLEAR_ENABLE(extra
->db_stencil_clear
);
3537 db_render_control
|= S_028000_RESUMMARIZE_ENABLE(extra
->db_resummarize
);
3538 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(extra
->db_flush_depth_inplace
);
3539 db_render_control
|= S_028000_STENCIL_COMPRESS_DISABLE(extra
->db_flush_stencil_inplace
);
3540 db_render_override2
|= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra
->db_depth_disable_expclear
);
3541 db_render_override2
|= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra
->db_stencil_disable_expclear
);
3544 db_render_override
|= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
3545 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
3547 if (!pCreateInfo
->pRasterizationState
->depthClampEnable
&&
3548 ps
->info
.ps
.writes_z
) {
3549 /* From VK_EXT_depth_range_unrestricted spec:
3551 * "The behavior described in Primitive Clipping still applies.
3552 * If depth clamping is disabled the depth values are still
3553 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3554 * depth clamping is enabled the above equation is ignored and
3555 * the depth values are instead clamped to the VkViewport
3556 * minDepth and maxDepth values, which in the case of this
3557 * extension can be outside of the 0.0 to 1.0 range."
3559 db_render_override
|= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3562 radeon_set_context_reg(ctx_cs
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
3563 radeon_set_context_reg(ctx_cs
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
3565 radeon_set_context_reg(ctx_cs
, R_028000_DB_RENDER_CONTROL
, db_render_control
);
3566 radeon_set_context_reg(ctx_cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
3567 radeon_set_context_reg(ctx_cs
, R_028010_DB_RENDER_OVERRIDE2
, db_render_override2
);
3571 radv_pipeline_generate_blend_state(struct radeon_cmdbuf
*ctx_cs
,
3572 struct radv_pipeline
*pipeline
,
3573 const struct radv_blend_state
*blend
)
3575 radeon_set_context_reg_seq(ctx_cs
, R_028780_CB_BLEND0_CONTROL
, 8);
3576 radeon_emit_array(ctx_cs
, blend
->cb_blend_control
,
3578 radeon_set_context_reg(ctx_cs
, R_028808_CB_COLOR_CONTROL
, blend
->cb_color_control
);
3579 radeon_set_context_reg(ctx_cs
, R_028B70_DB_ALPHA_TO_MASK
, blend
->db_alpha_to_mask
);
3581 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
3583 radeon_set_context_reg_seq(ctx_cs
, R_028760_SX_MRT0_BLEND_OPT
, 8);
3584 radeon_emit_array(ctx_cs
, blend
->sx_mrt_blend_opt
, 8);
3587 radeon_set_context_reg(ctx_cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
3589 radeon_set_context_reg(ctx_cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
3590 radeon_set_context_reg(ctx_cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
3592 pipeline
->graphics
.col_format
= blend
->spi_shader_col_format
;
3593 pipeline
->graphics
.cb_target_mask
= blend
->cb_target_mask
;
3596 static const VkConservativeRasterizationModeEXT
3597 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo
*pCreateInfo
)
3599 const VkPipelineRasterizationConservativeStateCreateInfoEXT
*conservative_raster
=
3600 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT
);
3602 if (!conservative_raster
)
3603 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
;
3604 return conservative_raster
->conservativeRasterizationMode
;
3608 radv_pipeline_generate_raster_state(struct radeon_cmdbuf
*ctx_cs
,
3609 struct radv_pipeline
*pipeline
,
3610 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3612 const VkPipelineRasterizationStateCreateInfo
*vkraster
= pCreateInfo
->pRasterizationState
;
3613 const VkConservativeRasterizationModeEXT mode
=
3614 radv_get_conservative_raster_mode(vkraster
);
3615 uint32_t pa_sc_conservative_rast
= S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3616 bool depth_clip_disable
= vkraster
->depthClampEnable
;
3618 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*depth_clip_state
=
3619 vk_find_struct_const(vkraster
->pNext
, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
3620 if (depth_clip_state
) {
3621 depth_clip_disable
= !depth_clip_state
->depthClipEnable
;
3624 radeon_set_context_reg(ctx_cs
, R_028810_PA_CL_CLIP_CNTL
,
3625 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3626 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable
? 1 : 0) |
3627 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable
? 1 : 0) |
3628 S_028810_DX_RASTERIZATION_KILL(vkraster
->rasterizerDiscardEnable
? 1 : 0) |
3629 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3631 radeon_set_context_reg(ctx_cs
, R_0286D4_SPI_INTERP_CONTROL_0
,
3632 S_0286D4_FLAT_SHADE_ENA(1) |
3633 S_0286D4_PNT_SPRITE_ENA(1) |
3634 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
3635 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
3636 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
3637 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
3638 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3640 radeon_set_context_reg(ctx_cs
, R_028BE4_PA_SU_VTX_CNTL
,
3641 S_028BE4_PIX_CENTER(1) | // TODO verify
3642 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN
) |
3643 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
3645 radeon_set_context_reg(ctx_cs
, R_028814_PA_SU_SC_MODE_CNTL
,
3646 S_028814_FACE(vkraster
->frontFace
) |
3647 S_028814_CULL_FRONT(!!(vkraster
->cullMode
& VK_CULL_MODE_FRONT_BIT
)) |
3648 S_028814_CULL_BACK(!!(vkraster
->cullMode
& VK_CULL_MODE_BACK_BIT
)) |
3649 S_028814_POLY_MODE(vkraster
->polygonMode
!= VK_POLYGON_MODE_FILL
) |
3650 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3651 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3652 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3653 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3654 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster
->depthBiasEnable
? 1 : 0));
3656 /* Conservative rasterization. */
3657 if (mode
!= VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
) {
3658 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3660 ms
->pa_sc_aa_config
|= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3661 ms
->db_eqaa
|= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3662 S_028804_OVERRASTERIZATION_AMOUNT(4);
3664 pa_sc_conservative_rast
= S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3665 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3666 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3668 if (mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT
) {
3669 pa_sc_conservative_rast
|=
3670 S_028C4C_OVER_RAST_ENABLE(1) |
3671 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3672 S_028C4C_UNDER_RAST_ENABLE(0) |
3673 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3674 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3676 assert(mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT
);
3677 pa_sc_conservative_rast
|=
3678 S_028C4C_OVER_RAST_ENABLE(0) |
3679 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3680 S_028C4C_UNDER_RAST_ENABLE(1) |
3681 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3682 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3686 radeon_set_context_reg(ctx_cs
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
3687 pa_sc_conservative_rast
);
3692 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf
*ctx_cs
,
3693 struct radv_pipeline
*pipeline
)
3695 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3697 radeon_set_context_reg_seq(ctx_cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
3698 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[0]);
3699 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[1]);
3701 radeon_set_context_reg(ctx_cs
, R_028804_DB_EQAA
, ms
->db_eqaa
);
3702 radeon_set_context_reg(ctx_cs
, R_028A48_PA_SC_MODE_CNTL_0
, ms
->pa_sc_mode_cntl_0
);
3703 radeon_set_context_reg(ctx_cs
, R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
3704 radeon_set_context_reg(ctx_cs
, R_028BDC_PA_SC_LINE_CNTL
, ms
->pa_sc_line_cntl
);
3705 radeon_set_context_reg(ctx_cs
, R_028BE0_PA_SC_AA_CONFIG
, ms
->pa_sc_aa_config
);
3707 /* The exclusion bits can be set to improve rasterization efficiency
3708 * if no sample lies on the pixel boundary (-8 sample offset). It's
3709 * currently always TRUE because the driver doesn't support 16 samples.
3711 bool exclusion
= pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
3712 radeon_set_context_reg(ctx_cs
, R_02882C_PA_SU_PRIM_FILTER_CNTL
,
3713 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) |
3714 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3716 /* GFX9: Flush DFSM when the AA mode changes. */
3717 if (pipeline
->device
->dfsm_allowed
) {
3718 radeon_emit(ctx_cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3719 radeon_emit(ctx_cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3724 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf
*ctx_cs
,
3725 struct radv_pipeline
*pipeline
)
3727 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3728 const struct radv_shader_variant
*vs
=
3729 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] ?
3730 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] :
3731 pipeline
->shaders
[MESA_SHADER_VERTEX
];
3732 unsigned vgt_primitiveid_en
= 0;
3733 uint32_t vgt_gs_mode
= 0;
3735 if (radv_pipeline_has_ngg(pipeline
))
3738 if (radv_pipeline_has_gs(pipeline
)) {
3739 const struct radv_shader_variant
*gs
=
3740 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3742 vgt_gs_mode
= ac_vgt_gs_mode(gs
->info
.gs
.vertices_out
,
3743 pipeline
->device
->physical_device
->rad_info
.chip_class
);
3744 } else if (outinfo
->export_prim_id
|| vs
->info
.uses_prim_id
) {
3745 vgt_gs_mode
= S_028A40_MODE(V_028A40_GS_SCENARIO_A
);
3746 vgt_primitiveid_en
|= S_028A84_PRIMITIVEID_EN(1);
3749 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
, vgt_primitiveid_en
);
3750 radeon_set_context_reg(ctx_cs
, R_028A40_VGT_GS_MODE
, vgt_gs_mode
);
3754 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf
*ctx_cs
,
3755 struct radeon_cmdbuf
*cs
,
3756 struct radv_pipeline
*pipeline
,
3757 struct radv_shader_variant
*shader
)
3759 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3761 radeon_set_sh_reg_seq(cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
3762 radeon_emit(cs
, va
>> 8);
3763 radeon_emit(cs
, S_00B124_MEM_BASE(va
>> 40));
3764 radeon_emit(cs
, shader
->config
.rsrc1
);
3765 radeon_emit(cs
, shader
->config
.rsrc2
);
3767 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3768 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3769 clip_dist_mask
= outinfo
->clip_dist_mask
;
3770 cull_dist_mask
= outinfo
->cull_dist_mask
;
3771 total_mask
= clip_dist_mask
| cull_dist_mask
;
3772 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3773 outinfo
->writes_layer
||
3774 outinfo
->writes_viewport_index
;
3775 unsigned spi_vs_out_config
, nparams
;
3777 /* VS is required to export at least one param. */
3778 nparams
= MAX2(outinfo
->param_exports
, 1);
3779 spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
3781 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3782 spi_vs_out_config
|= S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0);
3785 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
, spi_vs_out_config
);
3787 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3788 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3789 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3790 V_02870C_SPI_SHADER_4COMP
:
3791 V_02870C_SPI_SHADER_NONE
) |
3792 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3793 V_02870C_SPI_SHADER_4COMP
:
3794 V_02870C_SPI_SHADER_NONE
) |
3795 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3796 V_02870C_SPI_SHADER_4COMP
:
3797 V_02870C_SPI_SHADER_NONE
));
3799 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
3800 S_028818_VTX_W0_FMT(1) |
3801 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3802 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3803 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3805 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3806 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3807 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3808 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3809 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3810 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3811 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3812 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3813 cull_dist_mask
<< 8 |
3816 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
3817 radeon_set_context_reg(ctx_cs
, R_028AB4_VGT_REUSE_OFF
,
3818 outinfo
->writes_viewport_index
);
3822 radv_pipeline_generate_hw_es(struct radeon_cmdbuf
*cs
,
3823 struct radv_pipeline
*pipeline
,
3824 struct radv_shader_variant
*shader
)
3826 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3828 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
3829 radeon_emit(cs
, va
>> 8);
3830 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3831 radeon_emit(cs
, shader
->config
.rsrc1
);
3832 radeon_emit(cs
, shader
->config
.rsrc2
);
3836 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf
*cs
,
3837 struct radv_pipeline
*pipeline
,
3838 struct radv_shader_variant
*shader
,
3839 const struct radv_tessellation_state
*tess
)
3841 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3842 uint32_t rsrc2
= shader
->config
.rsrc2
;
3844 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
3845 radeon_emit(cs
, va
>> 8);
3846 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
3848 rsrc2
|= S_00B52C_LDS_SIZE(tess
->lds_size
);
3849 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX7
&&
3850 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
3851 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
3853 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
3854 radeon_emit(cs
, shader
->config
.rsrc1
);
3855 radeon_emit(cs
, rsrc2
);
3859 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf
*ctx_cs
,
3860 struct radeon_cmdbuf
*cs
,
3861 struct radv_pipeline
*pipeline
,
3862 struct radv_shader_variant
*shader
)
3864 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3865 gl_shader_stage es_type
=
3866 radv_pipeline_has_tess(pipeline
) ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
3867 struct radv_shader_variant
*es
=
3868 es_type
== MESA_SHADER_TESS_EVAL
? pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] : pipeline
->shaders
[MESA_SHADER_VERTEX
];
3869 const struct gfx10_ngg_info
*ngg_state
= &shader
->info
.ngg_info
;
3871 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
3872 radeon_emit(cs
, va
>> 8);
3873 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3874 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
3875 radeon_emit(cs
, shader
->config
.rsrc1
);
3876 radeon_emit(cs
, shader
->config
.rsrc2
);
3878 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3879 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3880 clip_dist_mask
= outinfo
->clip_dist_mask
;
3881 cull_dist_mask
= outinfo
->cull_dist_mask
;
3882 total_mask
= clip_dist_mask
| cull_dist_mask
;
3883 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3884 outinfo
->writes_layer
||
3885 outinfo
->writes_viewport_index
;
3886 bool es_enable_prim_id
= outinfo
->export_prim_id
||
3887 (es
&& es
->info
.uses_prim_id
);
3888 bool break_wave_at_eoi
= false;
3892 if (es_type
== MESA_SHADER_TESS_EVAL
) {
3893 struct radv_shader_variant
*gs
=
3894 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3896 if (es_enable_prim_id
|| (gs
&& gs
->info
.uses_prim_id
))
3897 break_wave_at_eoi
= true;
3900 nparams
= MAX2(outinfo
->param_exports
, 1);
3901 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
3902 S_0286C4_VS_EXPORT_COUNT(nparams
- 1) |
3903 S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0));
3905 radeon_set_context_reg(ctx_cs
, R_028708_SPI_SHADER_IDX_FORMAT
,
3906 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP
));
3907 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3908 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3909 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3910 V_02870C_SPI_SHADER_4COMP
:
3911 V_02870C_SPI_SHADER_NONE
) |
3912 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3913 V_02870C_SPI_SHADER_4COMP
:
3914 V_02870C_SPI_SHADER_NONE
) |
3915 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3916 V_02870C_SPI_SHADER_4COMP
:
3917 V_02870C_SPI_SHADER_NONE
));
3919 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
3920 S_028818_VTX_W0_FMT(1) |
3921 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3922 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3923 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3924 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3925 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3926 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3927 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3928 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3929 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3930 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3931 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3932 cull_dist_mask
<< 8 |
3935 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
,
3936 S_028A84_PRIMITIVEID_EN(es_enable_prim_id
) |
3937 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id
));
3939 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
3940 ngg_state
->vgt_esgs_ring_itemsize
);
3942 /* NGG specific registers. */
3943 struct radv_shader_variant
*gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3944 uint32_t gs_num_invocations
= gs
? gs
->info
.gs
.invocations
: 1;
3946 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
3947 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state
->hw_max_esverts
) |
3948 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state
->max_gsprims
) |
3949 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state
->max_gsprims
* gs_num_invocations
));
3950 radeon_set_context_reg(ctx_cs
, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP
,
3951 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state
->max_out_verts
));
3952 radeon_set_context_reg(ctx_cs
, R_028B4C_GE_NGG_SUBGRP_CNTL
,
3953 S_028B4C_PRIM_AMP_FACTOR(ngg_state
->prim_amp_factor
) |
3954 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
3955 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
3956 S_028B90_CNT(gs_num_invocations
) |
3957 S_028B90_ENABLE(gs_num_invocations
> 1) |
3958 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state
->max_vert_out_per_gs_instance
));
3960 /* User edge flags are set by the pos exports. If user edge flags are
3961 * not used, we must use hw-generated edge flags and pass them via
3962 * the prim export to prevent drawing lines on internal edges of
3963 * decomposed primitives (such as quads) with polygon mode = lines.
3965 * TODO: We should combine hw-generated edge flags with user edge
3966 * flags in the shader.
3968 radeon_set_context_reg(ctx_cs
, R_028838_PA_CL_NGG_CNTL
,
3969 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline
) &&
3970 !radv_pipeline_has_gs(pipeline
)));
3972 ge_cntl
= S_03096C_PRIM_GRP_SIZE(ngg_state
->max_gsprims
) |
3973 S_03096C_VERT_GRP_SIZE(ngg_state
->hw_max_esverts
) |
3974 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
);
3976 /* Bug workaround for a possible hang with non-tessellation cases.
3977 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
3979 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
3981 if ((pipeline
->device
->physical_device
->rad_info
.family
== CHIP_NAVI10
||
3982 pipeline
->device
->physical_device
->rad_info
.family
== CHIP_NAVI12
||
3983 pipeline
->device
->physical_device
->rad_info
.family
== CHIP_NAVI14
) &&
3984 !radv_pipeline_has_tess(pipeline
) &&
3985 ngg_state
->hw_max_esverts
!= 256) {
3986 ge_cntl
&= C_03096C_VERT_GRP_SIZE
;
3988 if (ngg_state
->hw_max_esverts
> 5) {
3989 ge_cntl
|= S_03096C_VERT_GRP_SIZE(ngg_state
->hw_max_esverts
- 5);
3993 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
, ge_cntl
);
3997 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf
*cs
,
3998 struct radv_pipeline
*pipeline
,
3999 struct radv_shader_variant
*shader
,
4000 const struct radv_tessellation_state
*tess
)
4002 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
4004 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4005 unsigned hs_rsrc2
= shader
->config
.rsrc2
;
4007 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4008 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX10(tess
->lds_size
);
4010 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX9(tess
->lds_size
);
4013 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4014 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
4015 radeon_emit(cs
, va
>> 8);
4016 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
4018 radeon_set_sh_reg_seq(cs
, R_00B410_SPI_SHADER_PGM_LO_LS
, 2);
4019 radeon_emit(cs
, va
>> 8);
4020 radeon_emit(cs
, S_00B414_MEM_BASE(va
>> 40));
4023 radeon_set_sh_reg_seq(cs
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
, 2);
4024 radeon_emit(cs
, shader
->config
.rsrc1
);
4025 radeon_emit(cs
, hs_rsrc2
);
4027 radeon_set_sh_reg_seq(cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
4028 radeon_emit(cs
, va
>> 8);
4029 radeon_emit(cs
, S_00B424_MEM_BASE(va
>> 40));
4030 radeon_emit(cs
, shader
->config
.rsrc1
);
4031 radeon_emit(cs
, shader
->config
.rsrc2
);
4036 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf
*ctx_cs
,
4037 struct radeon_cmdbuf
*cs
,
4038 struct radv_pipeline
*pipeline
,
4039 const struct radv_tessellation_state
*tess
)
4041 struct radv_shader_variant
*vs
;
4043 /* Skip shaders merged into HS/GS */
4044 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
4048 if (vs
->info
.vs
.as_ls
)
4049 radv_pipeline_generate_hw_ls(cs
, pipeline
, vs
, tess
);
4050 else if (vs
->info
.vs
.as_es
)
4051 radv_pipeline_generate_hw_es(cs
, pipeline
, vs
);
4052 else if (vs
->info
.is_ngg
)
4053 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, vs
);
4055 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, vs
);
4059 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf
*ctx_cs
,
4060 struct radeon_cmdbuf
*cs
,
4061 struct radv_pipeline
*pipeline
,
4062 const struct radv_tessellation_state
*tess
)
4064 if (!radv_pipeline_has_tess(pipeline
))
4067 struct radv_shader_variant
*tes
, *tcs
;
4069 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
4070 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
4073 if (tes
->info
.is_ngg
) {
4074 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, tes
);
4075 } else if (tes
->info
.tes
.as_es
)
4076 radv_pipeline_generate_hw_es(cs
, pipeline
, tes
);
4078 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, tes
);
4081 radv_pipeline_generate_hw_hs(cs
, pipeline
, tcs
, tess
);
4083 radeon_set_context_reg(ctx_cs
, R_028B6C_VGT_TF_PARAM
,
4086 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
)
4087 radeon_set_context_reg_idx(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
4088 tess
->ls_hs_config
);
4090 radeon_set_context_reg(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
,
4091 tess
->ls_hs_config
);
4093 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
4094 !radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
4095 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4096 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4097 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4098 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4103 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf
*ctx_cs
,
4104 struct radeon_cmdbuf
*cs
,
4105 struct radv_pipeline
*pipeline
,
4106 struct radv_shader_variant
*gs
)
4108 const struct gfx9_gs_info
*gs_state
= &gs
->info
.gs_ring_info
;
4109 unsigned gs_max_out_vertices
;
4110 uint8_t *num_components
;
4115 gs_max_out_vertices
= gs
->info
.gs
.vertices_out
;
4116 max_stream
= gs
->info
.gs
.max_stream
;
4117 num_components
= gs
->info
.gs
.num_stream_output_components
;
4119 offset
= num_components
[0] * gs_max_out_vertices
;
4121 radeon_set_context_reg_seq(ctx_cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
4122 radeon_emit(ctx_cs
, offset
);
4123 if (max_stream
>= 1)
4124 offset
+= num_components
[1] * gs_max_out_vertices
;
4125 radeon_emit(ctx_cs
, offset
);
4126 if (max_stream
>= 2)
4127 offset
+= num_components
[2] * gs_max_out_vertices
;
4128 radeon_emit(ctx_cs
, offset
);
4129 if (max_stream
>= 3)
4130 offset
+= num_components
[3] * gs_max_out_vertices
;
4131 radeon_set_context_reg(ctx_cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
4133 radeon_set_context_reg_seq(ctx_cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
4134 radeon_emit(ctx_cs
, num_components
[0]);
4135 radeon_emit(ctx_cs
, (max_stream
>= 1) ? num_components
[1] : 0);
4136 radeon_emit(ctx_cs
, (max_stream
>= 2) ? num_components
[2] : 0);
4137 radeon_emit(ctx_cs
, (max_stream
>= 3) ? num_components
[3] : 0);
4139 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
4140 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
4141 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
4142 S_028B90_ENABLE(gs_num_invocations
> 0));
4144 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
4145 gs_state
->vgt_esgs_ring_itemsize
);
4147 va
= radv_buffer_get_va(gs
->bo
) + gs
->bo_offset
;
4149 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4150 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4151 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
4152 radeon_emit(cs
, va
>> 8);
4153 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
4155 radeon_set_sh_reg_seq(cs
, R_00B210_SPI_SHADER_PGM_LO_ES
, 2);
4156 radeon_emit(cs
, va
>> 8);
4157 radeon_emit(cs
, S_00B214_MEM_BASE(va
>> 40));
4160 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
4161 radeon_emit(cs
, gs
->config
.rsrc1
);
4162 radeon_emit(cs
, gs
->config
.rsrc2
| S_00B22C_LDS_SIZE(gs_state
->lds_size
));
4164 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
, gs_state
->vgt_gs_onchip_cntl
);
4165 radeon_set_context_reg(ctx_cs
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
, gs_state
->vgt_gs_max_prims_per_subgroup
);
4167 radeon_set_sh_reg_seq(cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
4168 radeon_emit(cs
, va
>> 8);
4169 radeon_emit(cs
, S_00B224_MEM_BASE(va
>> 40));
4170 radeon_emit(cs
, gs
->config
.rsrc1
);
4171 radeon_emit(cs
, gs
->config
.rsrc2
);
4174 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, pipeline
->gs_copy_shader
);
4178 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf
*ctx_cs
,
4179 struct radeon_cmdbuf
*cs
,
4180 struct radv_pipeline
*pipeline
)
4182 struct radv_shader_variant
*gs
;
4184 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4188 if (gs
->info
.is_ngg
)
4189 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, gs
);
4191 radv_pipeline_generate_hw_gs(ctx_cs
, cs
, pipeline
, gs
);
4193 radeon_set_context_reg(ctx_cs
, R_028B38_VGT_GS_MAX_VERT_OUT
,
4194 gs
->info
.gs
.vertices_out
);
4197 static uint32_t offset_to_ps_input(uint32_t offset
, bool flat_shade
, bool float16
)
4199 uint32_t ps_input_cntl
;
4200 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
4201 ps_input_cntl
= S_028644_OFFSET(offset
);
4203 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
4205 ps_input_cntl
|= S_028644_FP16_INTERP_MODE(1) |
4206 S_028644_ATTR0_VALID(1);
4209 /* The input is a DEFAULT_VAL constant. */
4210 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
4211 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
4212 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
4213 ps_input_cntl
= S_028644_OFFSET(0x20) |
4214 S_028644_DEFAULT_VAL(offset
);
4216 return ps_input_cntl
;
4220 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf
*ctx_cs
,
4221 struct radv_pipeline
*pipeline
)
4223 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4224 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
4225 uint32_t ps_input_cntl
[32];
4227 unsigned ps_offset
= 0;
4229 if (ps
->info
.ps
.prim_id_input
) {
4230 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
];
4231 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4232 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false);
4237 if (ps
->info
.ps
.layer_input
||
4238 ps
->info
.needs_multiview_view_index
) {
4239 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
];
4240 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
4241 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false);
4243 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false);
4247 if (ps
->info
.ps
.has_pcoord
) {
4249 val
= S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4250 ps_input_cntl
[ps_offset
] = val
;
4254 if (ps
->info
.ps
.num_input_clips_culls
) {
4257 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST0
];
4258 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4259 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false);
4263 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST1
];
4264 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
&&
4265 ps
->info
.ps
.num_input_clips_culls
> 4) {
4266 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false);
4271 for (unsigned i
= 0; i
< 32 && (1u << i
) <= ps
->info
.ps
.input_mask
; ++i
) {
4275 if (!(ps
->info
.ps
.input_mask
& (1u << i
)))
4278 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VAR0
+ i
];
4279 if (vs_offset
== AC_EXP_PARAM_UNDEFINED
) {
4280 ps_input_cntl
[ps_offset
] = S_028644_OFFSET(0x20);
4285 flat_shade
= !!(ps
->info
.ps
.flat_shaded_mask
& (1u << ps_offset
));
4286 float16
= !!(ps
->info
.ps
.float16_shaded_mask
& (1u << ps_offset
));
4288 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, flat_shade
, float16
);
4293 radeon_set_context_reg_seq(ctx_cs
, R_028644_SPI_PS_INPUT_CNTL_0
, ps_offset
);
4294 for (unsigned i
= 0; i
< ps_offset
; i
++) {
4295 radeon_emit(ctx_cs
, ps_input_cntl
[i
]);
4301 radv_compute_db_shader_control(const struct radv_device
*device
,
4302 const struct radv_pipeline
*pipeline
,
4303 const struct radv_shader_variant
*ps
)
4306 if (ps
->info
.ps
.early_fragment_test
|| !ps
->info
.ps
.writes_memory
)
4307 z_order
= V_02880C_EARLY_Z_THEN_LATE_Z
;
4309 z_order
= V_02880C_LATE_Z
;
4311 bool disable_rbplus
= device
->physical_device
->rad_info
.has_rbplus
&&
4312 !device
->physical_device
->rad_info
.rbplus_allowed
;
4314 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4315 * but this appears to break Project Cars (DXVK). See
4316 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4318 bool mask_export_enable
= ps
->info
.ps
.writes_sample_mask
;
4320 return S_02880C_Z_EXPORT_ENABLE(ps
->info
.ps
.writes_z
) |
4321 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps
->info
.ps
.writes_stencil
) |
4322 S_02880C_KILL_ENABLE(!!ps
->info
.ps
.can_discard
) |
4323 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable
) |
4324 S_02880C_Z_ORDER(z_order
) |
4325 S_02880C_DEPTH_BEFORE_SHADER(ps
->info
.ps
.early_fragment_test
) |
4326 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps
->info
.ps
.post_depth_coverage
) |
4327 S_02880C_EXEC_ON_HIER_FAIL(ps
->info
.ps
.writes_memory
) |
4328 S_02880C_EXEC_ON_NOOP(ps
->info
.ps
.writes_memory
) |
4329 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus
);
4333 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf
*ctx_cs
,
4334 struct radeon_cmdbuf
*cs
,
4335 struct radv_pipeline
*pipeline
)
4337 struct radv_shader_variant
*ps
;
4339 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
4341 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4342 va
= radv_buffer_get_va(ps
->bo
) + ps
->bo_offset
;
4344 radeon_set_sh_reg_seq(cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
4345 radeon_emit(cs
, va
>> 8);
4346 radeon_emit(cs
, S_00B024_MEM_BASE(va
>> 40));
4347 radeon_emit(cs
, ps
->config
.rsrc1
);
4348 radeon_emit(cs
, ps
->config
.rsrc2
);
4350 radeon_set_context_reg(ctx_cs
, R_02880C_DB_SHADER_CONTROL
,
4351 radv_compute_db_shader_control(pipeline
->device
,
4354 radeon_set_context_reg(ctx_cs
, R_0286CC_SPI_PS_INPUT_ENA
,
4355 ps
->config
.spi_ps_input_ena
);
4357 radeon_set_context_reg(ctx_cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
4358 ps
->config
.spi_ps_input_addr
);
4360 radeon_set_context_reg(ctx_cs
, R_0286D8_SPI_PS_IN_CONTROL
,
4361 S_0286D8_NUM_INTERP(ps
->info
.ps
.num_interp
) |
4362 S_0286D8_PS_W32_EN(ps
->info
.wave_size
== 32));
4364 radeon_set_context_reg(ctx_cs
, R_0286E0_SPI_BARYC_CNTL
, pipeline
->graphics
.spi_baryc_cntl
);
4366 radeon_set_context_reg(ctx_cs
, R_028710_SPI_SHADER_Z_FORMAT
,
4367 ac_get_spi_shader_z_format(ps
->info
.ps
.writes_z
,
4368 ps
->info
.ps
.writes_stencil
,
4369 ps
->info
.ps
.writes_sample_mask
));
4371 if (pipeline
->device
->dfsm_allowed
) {
4372 /* optimise this? */
4373 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
4374 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
4379 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf
*ctx_cs
,
4380 struct radv_pipeline
*pipeline
)
4382 if (pipeline
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4383 pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
4386 unsigned vtx_reuse_depth
= 30;
4387 if (radv_pipeline_has_tess(pipeline
) &&
4388 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.tes
.spacing
== TESS_SPACING_FRACTIONAL_ODD
) {
4389 vtx_reuse_depth
= 14;
4391 radeon_set_context_reg(ctx_cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
4392 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth
));
4396 radv_compute_vgt_shader_stages_en(const struct radv_pipeline
*pipeline
)
4398 uint32_t stages
= 0;
4399 if (radv_pipeline_has_tess(pipeline
)) {
4400 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
4401 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4403 if (radv_pipeline_has_gs(pipeline
))
4404 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
4406 else if (radv_pipeline_has_ngg(pipeline
))
4407 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
4409 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
4410 } else if (radv_pipeline_has_gs(pipeline
)) {
4411 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
4413 } else if (radv_pipeline_has_ngg(pipeline
)) {
4414 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
4417 if (radv_pipeline_has_ngg(pipeline
)) {
4418 stages
|= S_028B54_PRIMGEN_EN(1);
4419 if (pipeline
->streamout_shader
)
4420 stages
|= S_028B54_NGG_WAVE_ID_EN(1);
4421 } else if (radv_pipeline_has_gs(pipeline
)) {
4422 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
4425 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
4426 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4428 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4429 uint8_t hs_size
= 64, gs_size
= 64, vs_size
= 64;
4431 if (radv_pipeline_has_tess(pipeline
))
4432 hs_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.wave_size
;
4434 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
4435 vs_size
= gs_size
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.wave_size
;
4436 if (pipeline
->gs_copy_shader
)
4437 vs_size
= pipeline
->gs_copy_shader
->info
.wave_size
;
4438 } else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
4439 vs_size
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.wave_size
;
4440 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
4441 vs_size
= pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.wave_size
;
4443 if (radv_pipeline_has_ngg(pipeline
))
4446 /* legacy GS only supports Wave64 */
4447 stages
|= S_028B54_HS_W32_EN(hs_size
== 32 ? 1 : 0) |
4448 S_028B54_GS_W32_EN(gs_size
== 32 ? 1 : 0) |
4449 S_028B54_VS_W32_EN(vs_size
== 32 ? 1 : 0);
4456 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4458 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
4459 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
4461 if (!discard_rectangle_info
)
4466 for (unsigned i
= 0; i
< (1u << MAX_DISCARD_RECTANGLES
); ++i
) {
4467 /* Interpret i as a bitmask, and then set the bit in the mask if
4468 * that combination of rectangles in which the pixel is contained
4469 * should pass the cliprect test. */
4470 unsigned relevant_subset
= i
& ((1u << discard_rectangle_info
->discardRectangleCount
) - 1);
4472 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT
&&
4476 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT
&&
4487 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf
*ctx_cs
,
4488 struct radv_pipeline
*pipeline
,
4489 const struct radv_tessellation_state
*tess
)
4491 bool break_wave_at_eoi
= false;
4492 unsigned primgroup_size
;
4493 unsigned vertgroup_size
;
4495 if (radv_pipeline_has_tess(pipeline
)) {
4496 primgroup_size
= tess
->num_patches
; /* must be a multiple of NUM_PATCHES */
4498 } else if (radv_pipeline_has_gs(pipeline
)) {
4499 const struct gfx9_gs_info
*gs_state
=
4500 &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs_ring_info
;
4501 unsigned vgt_gs_onchip_cntl
= gs_state
->vgt_gs_onchip_cntl
;
4502 primgroup_size
= G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl
);
4503 vertgroup_size
= G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl
);
4505 primgroup_size
= 128; /* recommended without a GS and tess */
4509 if (radv_pipeline_has_tess(pipeline
)) {
4510 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4511 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4512 break_wave_at_eoi
= true;
4515 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
,
4516 S_03096C_PRIM_GRP_SIZE(primgroup_size
) |
4517 S_03096C_VERT_GRP_SIZE(vertgroup_size
) |
4518 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4519 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
));
4523 radv_pipeline_generate_pm4(struct radv_pipeline
*pipeline
,
4524 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4525 const struct radv_graphics_pipeline_create_info
*extra
,
4526 const struct radv_blend_state
*blend
,
4527 const struct radv_tessellation_state
*tess
,
4528 unsigned prim
, unsigned gs_out
)
4530 struct radeon_cmdbuf
*ctx_cs
= &pipeline
->ctx_cs
;
4531 struct radeon_cmdbuf
*cs
= &pipeline
->cs
;
4534 ctx_cs
->max_dw
= 256;
4535 cs
->buf
= malloc(4 * (cs
->max_dw
+ ctx_cs
->max_dw
));
4536 ctx_cs
->buf
= cs
->buf
+ cs
->max_dw
;
4538 radv_pipeline_generate_depth_stencil_state(ctx_cs
, pipeline
, pCreateInfo
, extra
);
4539 radv_pipeline_generate_blend_state(ctx_cs
, pipeline
, blend
);
4540 radv_pipeline_generate_raster_state(ctx_cs
, pipeline
, pCreateInfo
);
4541 radv_pipeline_generate_multisample_state(ctx_cs
, pipeline
);
4542 radv_pipeline_generate_vgt_gs_mode(ctx_cs
, pipeline
);
4543 radv_pipeline_generate_vertex_shader(ctx_cs
, cs
, pipeline
, tess
);
4544 radv_pipeline_generate_tess_shaders(ctx_cs
, cs
, pipeline
, tess
);
4545 radv_pipeline_generate_geometry_shader(ctx_cs
, cs
, pipeline
);
4546 radv_pipeline_generate_fragment_shader(ctx_cs
, cs
, pipeline
);
4547 radv_pipeline_generate_ps_inputs(ctx_cs
, pipeline
);
4548 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs
, pipeline
);
4549 radv_pipeline_generate_binning_state(ctx_cs
, pipeline
, pCreateInfo
, blend
);
4551 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&& !radv_pipeline_has_ngg(pipeline
))
4552 gfx10_pipeline_generate_ge_cntl(ctx_cs
, pipeline
, tess
);
4554 radeon_set_context_reg(ctx_cs
, R_028B54_VGT_SHADER_STAGES_EN
, radv_compute_vgt_shader_stages_en(pipeline
));
4556 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4557 radeon_set_uconfig_reg_idx(pipeline
->device
->physical_device
,
4558 cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, prim
);
4560 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
4562 radeon_set_context_reg(ctx_cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, gs_out
);
4564 radeon_set_context_reg(ctx_cs
, R_02820C_PA_SC_CLIPRECT_RULE
, radv_compute_cliprect_rule(pCreateInfo
));
4566 pipeline
->ctx_cs_hash
= _mesa_hash_data(ctx_cs
->buf
, ctx_cs
->cdw
* 4);
4568 assert(ctx_cs
->cdw
<= ctx_cs
->max_dw
);
4569 assert(cs
->cdw
<= cs
->max_dw
);
4572 static struct radv_ia_multi_vgt_param_helpers
4573 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline
*pipeline
,
4574 const struct radv_tessellation_state
*tess
,
4577 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
= {0};
4578 const struct radv_device
*device
= pipeline
->device
;
4580 if (radv_pipeline_has_tess(pipeline
))
4581 ia_multi_vgt_param
.primgroup_size
= tess
->num_patches
;
4582 else if (radv_pipeline_has_gs(pipeline
))
4583 ia_multi_vgt_param
.primgroup_size
= 64;
4585 ia_multi_vgt_param
.primgroup_size
= 128; /* recommended without a GS */
4587 /* GS requirement. */
4588 ia_multi_vgt_param
.partial_es_wave
= false;
4589 if (radv_pipeline_has_gs(pipeline
) && device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4590 if (SI_GS_PER_ES
/ ia_multi_vgt_param
.primgroup_size
>= pipeline
->device
->gs_table_depth
- 3)
4591 ia_multi_vgt_param
.partial_es_wave
= true;
4593 ia_multi_vgt_param
.wd_switch_on_eop
= false;
4594 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4595 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
4596 * 4 shader engines. Set 1 to pass the assertion below.
4597 * The other cases are hardware requirements. */
4598 if (device
->physical_device
->rad_info
.max_se
< 4 ||
4599 prim
== V_008958_DI_PT_POLYGON
||
4600 prim
== V_008958_DI_PT_LINELOOP
||
4601 prim
== V_008958_DI_PT_TRIFAN
||
4602 prim
== V_008958_DI_PT_TRISTRIP_ADJ
||
4603 (pipeline
->graphics
.prim_restart_enable
&&
4604 (device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4605 (prim
!= V_008958_DI_PT_POINTLIST
&&
4606 prim
!= V_008958_DI_PT_LINESTRIP
))))
4607 ia_multi_vgt_param
.wd_switch_on_eop
= true;
4610 ia_multi_vgt_param
.ia_switch_on_eoi
= false;
4611 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.prim_id_input
)
4612 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4613 if (radv_pipeline_has_gs(pipeline
) &&
4614 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.uses_prim_id
)
4615 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4616 if (radv_pipeline_has_tess(pipeline
)) {
4617 /* SWITCH_ON_EOI must be set if PrimID is used. */
4618 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4619 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4620 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4623 ia_multi_vgt_param
.partial_vs_wave
= false;
4624 if (radv_pipeline_has_tess(pipeline
)) {
4625 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4626 if ((device
->physical_device
->rad_info
.family
== CHIP_TAHITI
||
4627 device
->physical_device
->rad_info
.family
== CHIP_PITCAIRN
||
4628 device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
) &&
4629 radv_pipeline_has_gs(pipeline
))
4630 ia_multi_vgt_param
.partial_vs_wave
= true;
4631 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4632 if (device
->physical_device
->rad_info
.has_distributed_tess
) {
4633 if (radv_pipeline_has_gs(pipeline
)) {
4634 if (device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4635 ia_multi_vgt_param
.partial_es_wave
= true;
4637 ia_multi_vgt_param
.partial_vs_wave
= true;
4642 /* Workaround for a VGT hang when strip primitive types are used with
4643 * primitive restart.
4645 if (pipeline
->graphics
.prim_restart_enable
&&
4646 (prim
== V_008958_DI_PT_LINESTRIP
||
4647 prim
== V_008958_DI_PT_TRISTRIP
||
4648 prim
== V_008958_DI_PT_LINESTRIP_ADJ
||
4649 prim
== V_008958_DI_PT_TRISTRIP_ADJ
)) {
4650 ia_multi_vgt_param
.partial_vs_wave
= true;
4653 if (radv_pipeline_has_gs(pipeline
)) {
4654 /* On these chips there is the possibility of a hang if the
4655 * pipeline uses a GS and partial_vs_wave is not set.
4657 * This mostly does not hit 4-SE chips, as those typically set
4658 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4659 * with GS due to another workaround.
4661 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4663 if (device
->physical_device
->rad_info
.family
== CHIP_TONGA
||
4664 device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
4665 device
->physical_device
->rad_info
.family
== CHIP_POLARIS10
||
4666 device
->physical_device
->rad_info
.family
== CHIP_POLARIS11
||
4667 device
->physical_device
->rad_info
.family
== CHIP_POLARIS12
||
4668 device
->physical_device
->rad_info
.family
== CHIP_VEGAM
) {
4669 ia_multi_vgt_param
.partial_vs_wave
= true;
4673 ia_multi_vgt_param
.base
=
4674 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param
.primgroup_size
- 1) |
4675 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4676 S_028AA8_MAX_PRIMGRP_IN_WAVE(device
->physical_device
->rad_info
.chip_class
== GFX8
? 2 : 0) |
4677 S_030960_EN_INST_OPT_BASIC(device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
4678 S_030960_EN_INST_OPT_ADV(device
->physical_device
->rad_info
.chip_class
>= GFX9
);
4680 return ia_multi_vgt_param
;
4685 radv_compute_vertex_input_state(struct radv_pipeline
*pipeline
,
4686 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4688 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
4689 pCreateInfo
->pVertexInputState
;
4690 struct radv_vertex_elements_info
*velems
= &pipeline
->vertex_elements
;
4692 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
4693 const VkVertexInputAttributeDescription
*desc
=
4694 &vi_info
->pVertexAttributeDescriptions
[i
];
4695 unsigned loc
= desc
->location
;
4696 const struct vk_format_description
*format_desc
;
4698 format_desc
= vk_format_description(desc
->format
);
4700 velems
->format_size
[loc
] = format_desc
->block
.bits
/ 8;
4703 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
4704 const VkVertexInputBindingDescription
*desc
=
4705 &vi_info
->pVertexBindingDescriptions
[i
];
4707 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
4708 pipeline
->num_vertex_bindings
=
4709 MAX2(pipeline
->num_vertex_bindings
, desc
->binding
+ 1);
4713 static struct radv_shader_variant
*
4714 radv_pipeline_get_streamout_shader(struct radv_pipeline
*pipeline
)
4718 for (i
= MESA_SHADER_GEOMETRY
; i
>= MESA_SHADER_VERTEX
; i
--) {
4719 struct radv_shader_variant
*shader
=
4720 radv_get_shader(pipeline
, i
);
4722 if (shader
&& shader
->info
.so
.num_outputs
> 0)
4730 radv_secure_compile(struct radv_pipeline
*pipeline
,
4731 struct radv_device
*device
,
4732 const struct radv_pipeline_key
*key
,
4733 const VkPipelineShaderStageCreateInfo
**pStages
,
4734 const VkPipelineCreateFlags flags
,
4735 unsigned num_stages
)
4737 uint8_t allowed_pipeline_hashes
[2][20];
4738 radv_hash_shaders(allowed_pipeline_hashes
[0], pStages
,
4739 pipeline
->layout
, key
, get_hash_flags(device
));
4741 /* Generate the GC copy hash */
4742 memcpy(allowed_pipeline_hashes
[1], allowed_pipeline_hashes
[0], 20);
4743 allowed_pipeline_hashes
[1][0] ^= 1;
4745 uint8_t allowed_hashes
[2][20];
4746 for (unsigned i
= 0; i
< 2; ++i
) {
4747 disk_cache_compute_key(device
->physical_device
->disk_cache
,
4748 allowed_pipeline_hashes
[i
], 20,
4752 /* Do an early exit if all cache entries are already there. */
4753 bool may_need_copy_shader
= pStages
[MESA_SHADER_GEOMETRY
];
4754 void *main_entry
= disk_cache_get(device
->physical_device
->disk_cache
, allowed_hashes
[0], NULL
);
4755 void *copy_entry
= NULL
;
4756 if (may_need_copy_shader
)
4757 copy_entry
= disk_cache_get(device
->physical_device
->disk_cache
, allowed_hashes
[1], NULL
);
4759 bool has_all_cache_entries
= main_entry
&& (!may_need_copy_shader
|| copy_entry
);
4763 if(has_all_cache_entries
)
4766 unsigned process
= 0;
4767 uint8_t sc_threads
= device
->instance
->num_sc_threads
;
4769 mtx_lock(&device
->sc_state
->secure_compile_mutex
);
4770 if (device
->sc_state
->secure_compile_thread_counter
< sc_threads
) {
4771 device
->sc_state
->secure_compile_thread_counter
++;
4772 for (unsigned i
= 0; i
< sc_threads
; i
++) {
4773 if (!device
->sc_state
->secure_compile_processes
[i
].in_use
) {
4774 device
->sc_state
->secure_compile_processes
[i
].in_use
= true;
4779 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
4782 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
4785 int fd_secure_input
= device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
;
4786 int fd_secure_output
= device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
;
4788 /* Fork a copy of the slim untainted secure compile process */
4789 enum radv_secure_compile_type sc_type
= RADV_SC_TYPE_FORK_DEVICE
;
4790 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
4792 if (!radv_sc_read(fd_secure_output
, &sc_type
, sizeof(sc_type
), true) ||
4793 sc_type
!= RADV_SC_TYPE_INIT_SUCCESS
)
4794 return VK_ERROR_DEVICE_LOST
;
4796 fd_secure_input
= device
->sc_state
->secure_compile_processes
[process
].fd_server
;
4797 fd_secure_output
= device
->sc_state
->secure_compile_processes
[process
].fd_client
;
4799 /* Write pipeline / shader module out to secure process via pipe */
4800 sc_type
= RADV_SC_TYPE_COMPILE_PIPELINE
;
4801 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
4803 /* Write pipeline layout out to secure process */
4804 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
4805 write(fd_secure_input
, layout
, sizeof(struct radv_pipeline_layout
));
4806 write(fd_secure_input
, &layout
->num_sets
, sizeof(uint32_t));
4807 for (uint32_t set
= 0; set
< layout
->num_sets
; set
++) {
4808 write(fd_secure_input
, &layout
->set
[set
].layout
->layout_size
, sizeof(uint32_t));
4809 write(fd_secure_input
, layout
->set
[set
].layout
, layout
->set
[set
].layout
->layout_size
);
4812 /* Write pipeline key out to secure process */
4813 write(fd_secure_input
, key
, sizeof(struct radv_pipeline_key
));
4815 /* Write pipeline create flags out to secure process */
4816 write(fd_secure_input
, &flags
, sizeof(VkPipelineCreateFlags
));
4818 /* Write stage and shader information out to secure process */
4819 write(fd_secure_input
, &num_stages
, sizeof(uint32_t));
4820 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
4824 /* Write stage out to secure process */
4825 gl_shader_stage stage
= ffs(pStages
[i
]->stage
) - 1;
4826 write(fd_secure_input
, &stage
, sizeof(gl_shader_stage
));
4828 /* Write entry point name out to secure process */
4829 size_t name_size
= strlen(pStages
[i
]->pName
) + 1;
4830 write(fd_secure_input
, &name_size
, sizeof(size_t));
4831 write(fd_secure_input
, pStages
[i
]->pName
, name_size
);
4833 /* Write shader module out to secure process */
4834 struct radv_shader_module
*module
= radv_shader_module_from_handle(pStages
[i
]->module
);
4835 assert(!module
->nir
);
4836 size_t module_size
= sizeof(struct radv_shader_module
) + module
->size
;
4837 write(fd_secure_input
, &module_size
, sizeof(size_t));
4838 write(fd_secure_input
, module
, module_size
);
4840 /* Write specialization info out to secure process */
4841 const VkSpecializationInfo
*specInfo
= pStages
[i
]->pSpecializationInfo
;
4842 bool has_spec_info
= specInfo
? true : false;
4843 write(fd_secure_input
, &has_spec_info
, sizeof(bool));
4845 write(fd_secure_input
, &specInfo
->dataSize
, sizeof(size_t));
4846 write(fd_secure_input
, specInfo
->pData
, specInfo
->dataSize
);
4848 write(fd_secure_input
, &specInfo
->mapEntryCount
, sizeof(uint32_t));
4849 for (uint32_t j
= 0; j
< specInfo
->mapEntryCount
; j
++)
4850 write(fd_secure_input
, &specInfo
->pMapEntries
[j
], sizeof(VkSpecializationMapEntry
));
4854 /* Read the data returned from the secure process */
4855 while (sc_type
!= RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED
) {
4856 if (!radv_sc_read(fd_secure_output
, &sc_type
, sizeof(sc_type
), true))
4857 return VK_ERROR_DEVICE_LOST
;
4859 if (sc_type
== RADV_SC_TYPE_WRITE_DISK_CACHE
) {
4860 assert(device
->physical_device
->disk_cache
);
4862 uint8_t disk_sha1
[20];
4863 if (!radv_sc_read(fd_secure_output
, disk_sha1
, sizeof(uint8_t) * 20, true))
4864 return VK_ERROR_DEVICE_LOST
;
4866 if (memcmp(disk_sha1
, allowed_hashes
[0], 20) &&
4867 memcmp(disk_sha1
, allowed_hashes
[1], 20))
4868 return VK_ERROR_DEVICE_LOST
;
4870 uint32_t entry_size
;
4871 if (!radv_sc_read(fd_secure_output
, &entry_size
, sizeof(uint32_t), true))
4872 return VK_ERROR_DEVICE_LOST
;
4874 struct cache_entry
*entry
= malloc(entry_size
);
4875 if (!radv_sc_read(fd_secure_output
, entry
, entry_size
, true))
4876 return VK_ERROR_DEVICE_LOST
;
4878 disk_cache_put(device
->physical_device
->disk_cache
,
4879 disk_sha1
, entry
, entry_size
,
4883 } else if (sc_type
== RADV_SC_TYPE_READ_DISK_CACHE
) {
4884 uint8_t disk_sha1
[20];
4885 if (!radv_sc_read(fd_secure_output
, disk_sha1
, sizeof(uint8_t) * 20, true))
4886 return VK_ERROR_DEVICE_LOST
;
4888 if (memcmp(disk_sha1
, allowed_hashes
[0], 20) &&
4889 memcmp(disk_sha1
, allowed_hashes
[1], 20))
4890 return VK_ERROR_DEVICE_LOST
;
4893 struct cache_entry
*entry
= (struct cache_entry
*)
4894 disk_cache_get(device
->physical_device
->disk_cache
,
4897 uint8_t found
= entry
? 1 : 0;
4898 write(fd_secure_input
, &found
, sizeof(uint8_t));
4901 write(fd_secure_input
, &size
, sizeof(size_t));
4902 write(fd_secure_input
, entry
, size
);
4909 sc_type
= RADV_SC_TYPE_DESTROY_DEVICE
;
4910 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
4912 mtx_lock(&device
->sc_state
->secure_compile_mutex
);
4913 device
->sc_state
->secure_compile_thread_counter
--;
4914 device
->sc_state
->secure_compile_processes
[process
].in_use
= false;
4915 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
4921 radv_pipeline_init(struct radv_pipeline
*pipeline
,
4922 struct radv_device
*device
,
4923 struct radv_pipeline_cache
*cache
,
4924 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4925 const struct radv_graphics_pipeline_create_info
*extra
)
4928 bool has_view_index
= false;
4930 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
4931 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
4932 if (subpass
->view_mask
)
4933 has_view_index
= true;
4935 pipeline
->device
= device
;
4936 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
4937 assert(pipeline
->layout
);
4939 struct radv_blend_state blend
= radv_pipeline_init_blend_state(pipeline
, pCreateInfo
, extra
);
4941 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
4942 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
4943 radv_init_feedback(creation_feedback
);
4945 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
4947 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
4948 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
4949 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
4950 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
4951 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
4952 if(creation_feedback
)
4953 stage_feedbacks
[stage
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[i
];
4956 struct radv_pipeline_key key
= radv_generate_graphics_pipeline_key(pipeline
, pCreateInfo
, &blend
, has_view_index
);
4957 if (radv_device_use_secure_compile(device
->instance
)) {
4958 return radv_secure_compile(pipeline
, device
, &key
, pStages
, pCreateInfo
->flags
, pCreateInfo
->stageCount
);
4960 radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
, pCreateInfo
->flags
, pipeline_feedback
, stage_feedbacks
);
4963 pipeline
->graphics
.spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
4964 radv_pipeline_init_multisample_state(pipeline
, &blend
, pCreateInfo
);
4966 uint32_t prim
= si_translate_prim(pCreateInfo
->pInputAssemblyState
->topology
);
4968 pipeline
->graphics
.can_use_guardband
= radv_prim_can_use_guardband(pCreateInfo
->pInputAssemblyState
->topology
);
4970 if (radv_pipeline_has_gs(pipeline
)) {
4971 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs
.output_prim
);
4972 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4973 } else if (radv_pipeline_has_tess(pipeline
)) {
4974 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.point_mode
)
4975 gs_out
= V_028A6C_OUTPRIM_TYPE_POINTLIST
;
4977 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.primitive_mode
);
4978 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4980 gs_out
= si_conv_prim_to_gs_out(pCreateInfo
->pInputAssemblyState
->topology
);
4982 if (extra
&& extra
->use_rectlist
) {
4983 prim
= V_008958_DI_PT_RECTLIST
;
4984 gs_out
= V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4985 pipeline
->graphics
.can_use_guardband
= true;
4986 if (radv_pipeline_has_ngg(pipeline
))
4987 gs_out
= V_028A6C_VGT_OUT_RECT_V0
;
4989 pipeline
->graphics
.prim_restart_enable
= !!pCreateInfo
->pInputAssemblyState
->primitiveRestartEnable
;
4990 /* prim vertex count will need TESS changes */
4991 pipeline
->graphics
.prim_vertex_count
= prim_size_table
[prim
];
4993 radv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
);
4995 /* Ensure that some export memory is always allocated, for two reasons:
4997 * 1) Correctness: The hardware ignores the EXEC mask if no export
4998 * memory is allocated, so KILL and alpha test do not work correctly
5000 * 2) Performance: Every shader needs at least a NULL export, even when
5001 * it writes no color/depth output. The NULL export instruction
5002 * stalls without this setting.
5004 * Don't add this to CB_SHADER_MASK.
5006 * GFX10 supports pixel shaders without exports by setting both the
5007 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
5008 * instructions if any are present.
5010 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
5011 if ((pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX9
||
5012 ps
->info
.ps
.can_discard
) &&
5013 !blend
.spi_shader_col_format
) {
5014 if (!ps
->info
.ps
.writes_z
&&
5015 !ps
->info
.ps
.writes_stencil
&&
5016 !ps
->info
.ps
.writes_sample_mask
)
5017 blend
.spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
5020 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
5021 if (pipeline
->shaders
[i
]) {
5022 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[i
]->info
.need_indirect_descriptor_sets
;
5026 if (radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
5027 struct radv_shader_variant
*gs
=
5028 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
5030 calculate_gs_ring_sizes(pipeline
, &gs
->info
.gs_ring_info
);
5033 struct radv_tessellation_state tess
= {0};
5034 if (radv_pipeline_has_tess(pipeline
)) {
5035 if (prim
== V_008958_DI_PT_PATCH
) {
5036 pipeline
->graphics
.prim_vertex_count
.min
= pCreateInfo
->pTessellationState
->patchControlPoints
;
5037 pipeline
->graphics
.prim_vertex_count
.incr
= 1;
5039 tess
= calculate_tess_state(pipeline
, pCreateInfo
);
5042 pipeline
->graphics
.ia_multi_vgt_param
= radv_compute_ia_multi_vgt_param_helpers(pipeline
, &tess
, prim
);
5044 radv_compute_vertex_input_state(pipeline
, pCreateInfo
);
5046 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++)
5047 pipeline
->user_data_0
[i
] = radv_pipeline_stage_to_user_data_0(pipeline
, i
, device
->physical_device
->rad_info
.chip_class
);
5049 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
,
5050 AC_UD_VS_BASE_VERTEX_START_INSTANCE
);
5051 if (loc
->sgpr_idx
!= -1) {
5052 pipeline
->graphics
.vtx_base_sgpr
= pipeline
->user_data_0
[MESA_SHADER_VERTEX
];
5053 pipeline
->graphics
.vtx_base_sgpr
+= loc
->sgpr_idx
* 4;
5054 if (radv_get_shader(pipeline
, MESA_SHADER_VERTEX
)->info
.vs
.needs_draw_id
)
5055 pipeline
->graphics
.vtx_emit_num
= 3;
5057 pipeline
->graphics
.vtx_emit_num
= 2;
5060 /* Find the last vertex shader stage that eventually uses streamout. */
5061 pipeline
->streamout_shader
= radv_pipeline_get_streamout_shader(pipeline
);
5063 result
= radv_pipeline_scratch_init(device
, pipeline
);
5064 radv_pipeline_generate_pm4(pipeline
, pCreateInfo
, extra
, &blend
, &tess
, prim
, gs_out
);
5070 radv_graphics_pipeline_create(
5072 VkPipelineCache _cache
,
5073 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
5074 const struct radv_graphics_pipeline_create_info
*extra
,
5075 const VkAllocationCallbacks
*pAllocator
,
5076 VkPipeline
*pPipeline
)
5078 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5079 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
5080 struct radv_pipeline
*pipeline
;
5083 pipeline
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
5084 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5085 if (pipeline
== NULL
)
5086 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5088 result
= radv_pipeline_init(pipeline
, device
, cache
,
5089 pCreateInfo
, extra
);
5090 if (result
!= VK_SUCCESS
) {
5091 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5095 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5100 VkResult
radv_CreateGraphicsPipelines(
5102 VkPipelineCache pipelineCache
,
5104 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
5105 const VkAllocationCallbacks
* pAllocator
,
5106 VkPipeline
* pPipelines
)
5108 VkResult result
= VK_SUCCESS
;
5111 for (; i
< count
; i
++) {
5113 r
= radv_graphics_pipeline_create(_device
,
5116 NULL
, pAllocator
, &pPipelines
[i
]);
5117 if (r
!= VK_SUCCESS
) {
5119 pPipelines
[i
] = VK_NULL_HANDLE
;
5128 radv_compute_generate_pm4(struct radv_pipeline
*pipeline
)
5130 struct radv_shader_variant
*compute_shader
;
5131 struct radv_device
*device
= pipeline
->device
;
5132 unsigned threads_per_threadgroup
;
5133 unsigned threadgroups_per_cu
= 1;
5134 unsigned waves_per_threadgroup
;
5135 unsigned max_waves_per_sh
= 0;
5138 pipeline
->cs
.max_dw
= device
->physical_device
->rad_info
.chip_class
>= GFX10
? 22 : 20;
5139 pipeline
->cs
.buf
= malloc(pipeline
->cs
.max_dw
* 4);
5141 compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
5142 va
= radv_buffer_get_va(compute_shader
->bo
) + compute_shader
->bo_offset
;
5144 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B830_COMPUTE_PGM_LO
, 2);
5145 radeon_emit(&pipeline
->cs
, va
>> 8);
5146 radeon_emit(&pipeline
->cs
, S_00B834_DATA(va
>> 40));
5148 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
5149 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc1
);
5150 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc2
);
5151 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
5152 radeon_set_sh_reg(&pipeline
->cs
, R_00B8A0_COMPUTE_PGM_RSRC3
, compute_shader
->config
.rsrc3
);
5155 /* Calculate best compute resource limits. */
5156 threads_per_threadgroup
= compute_shader
->info
.cs
.block_size
[0] *
5157 compute_shader
->info
.cs
.block_size
[1] *
5158 compute_shader
->info
.cs
.block_size
[2];
5159 waves_per_threadgroup
= DIV_ROUND_UP(threads_per_threadgroup
,
5160 compute_shader
->info
.wave_size
);
5162 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
5163 waves_per_threadgroup
== 1)
5164 threadgroups_per_cu
= 2;
5166 radeon_set_sh_reg(&pipeline
->cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
5167 ac_get_compute_resource_limits(&device
->physical_device
->rad_info
,
5168 waves_per_threadgroup
,
5170 threadgroups_per_cu
));
5172 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
5173 radeon_emit(&pipeline
->cs
,
5174 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]));
5175 radeon_emit(&pipeline
->cs
,
5176 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]));
5177 radeon_emit(&pipeline
->cs
,
5178 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]));
5180 assert(pipeline
->cs
.cdw
<= pipeline
->cs
.max_dw
);
5183 static struct radv_pipeline_key
5184 radv_generate_compute_pipeline_key(struct radv_pipeline
*pipeline
,
5185 const VkComputePipelineCreateInfo
*pCreateInfo
)
5187 const VkPipelineShaderStageCreateInfo
*stage
= &pCreateInfo
->stage
;
5188 struct radv_pipeline_key key
;
5189 memset(&key
, 0, sizeof(key
));
5191 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
5192 key
.optimisations_disabled
= 1;
5194 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*subgroup_size
=
5195 vk_find_struct_const(stage
->pNext
,
5196 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT
);
5198 if (subgroup_size
) {
5199 assert(subgroup_size
->requiredSubgroupSize
== 32 ||
5200 subgroup_size
->requiredSubgroupSize
== 64);
5201 key
.compute_subgroup_size
= subgroup_size
->requiredSubgroupSize
;
5207 static VkResult
radv_compute_pipeline_create(
5209 VkPipelineCache _cache
,
5210 const VkComputePipelineCreateInfo
* pCreateInfo
,
5211 const VkAllocationCallbacks
* pAllocator
,
5212 VkPipeline
* pPipeline
)
5214 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5215 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
5216 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
5217 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
5218 struct radv_pipeline
*pipeline
;
5221 pipeline
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
5222 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5223 if (pipeline
== NULL
)
5224 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5226 pipeline
->device
= device
;
5227 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
5228 assert(pipeline
->layout
);
5230 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
5231 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
5232 radv_init_feedback(creation_feedback
);
5234 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
5235 if (creation_feedback
)
5236 stage_feedbacks
[MESA_SHADER_COMPUTE
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[0];
5238 pStages
[MESA_SHADER_COMPUTE
] = &pCreateInfo
->stage
;
5240 struct radv_pipeline_key key
=
5241 radv_generate_compute_pipeline_key(pipeline
, pCreateInfo
);
5243 if (radv_device_use_secure_compile(device
->instance
)) {
5244 result
= radv_secure_compile(pipeline
, device
, &key
, pStages
, pCreateInfo
->flags
, 1);
5245 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5249 radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
, pCreateInfo
->flags
, pipeline_feedback
, stage_feedbacks
);
5252 pipeline
->user_data_0
[MESA_SHADER_COMPUTE
] = radv_pipeline_stage_to_user_data_0(pipeline
, MESA_SHADER_COMPUTE
, device
->physical_device
->rad_info
.chip_class
);
5253 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.need_indirect_descriptor_sets
;
5254 result
= radv_pipeline_scratch_init(device
, pipeline
);
5255 if (result
!= VK_SUCCESS
) {
5256 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5260 radv_compute_generate_pm4(pipeline
);
5262 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5267 VkResult
radv_CreateComputePipelines(
5269 VkPipelineCache pipelineCache
,
5271 const VkComputePipelineCreateInfo
* pCreateInfos
,
5272 const VkAllocationCallbacks
* pAllocator
,
5273 VkPipeline
* pPipelines
)
5275 VkResult result
= VK_SUCCESS
;
5278 for (; i
< count
; i
++) {
5280 r
= radv_compute_pipeline_create(_device
, pipelineCache
,
5282 pAllocator
, &pPipelines
[i
]);
5283 if (r
!= VK_SUCCESS
) {
5285 pPipelines
[i
] = VK_NULL_HANDLE
;
5293 static uint32_t radv_get_executable_count(const struct radv_pipeline
*pipeline
)
5296 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5297 if (!pipeline
->shaders
[i
])
5300 if (i
== MESA_SHADER_GEOMETRY
&&
5301 !radv_pipeline_has_ngg(pipeline
)) {
5311 static struct radv_shader_variant
*
5312 radv_get_shader_from_executable_index(const struct radv_pipeline
*pipeline
, int index
, gl_shader_stage
*stage
)
5314 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5315 if (!pipeline
->shaders
[i
])
5319 return pipeline
->shaders
[i
];
5324 if (i
== MESA_SHADER_GEOMETRY
&&
5325 !radv_pipeline_has_ngg(pipeline
)) {
5328 return pipeline
->gs_copy_shader
;
5338 /* Basically strlcpy (which does not exist on linux) specialized for
5340 static void desc_copy(char *desc
, const char *src
) {
5341 int len
= strlen(src
);
5342 assert(len
< VK_MAX_DESCRIPTION_SIZE
);
5343 memcpy(desc
, src
, len
);
5344 memset(desc
+ len
, 0, VK_MAX_DESCRIPTION_SIZE
- len
);
5347 VkResult
radv_GetPipelineExecutablePropertiesKHR(
5349 const VkPipelineInfoKHR
* pPipelineInfo
,
5350 uint32_t* pExecutableCount
,
5351 VkPipelineExecutablePropertiesKHR
* pProperties
)
5353 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pPipelineInfo
->pipeline
);
5354 const uint32_t total_count
= radv_get_executable_count(pipeline
);
5357 *pExecutableCount
= total_count
;
5361 const uint32_t count
= MIN2(total_count
, *pExecutableCount
);
5362 for (unsigned i
= 0, executable_idx
= 0;
5363 i
< MESA_SHADER_STAGES
&& executable_idx
< count
; ++i
) {
5364 if (!pipeline
->shaders
[i
])
5366 pProperties
[executable_idx
].stages
= mesa_to_vk_shader_stage(i
);
5367 const char *name
= NULL
;
5368 const char *description
= NULL
;
5370 case MESA_SHADER_VERTEX
:
5371 name
= "Vertex Shader";
5372 description
= "Vulkan Vertex Shader";
5374 case MESA_SHADER_TESS_CTRL
:
5375 if (!pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5376 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5377 name
= "Vertex + Tessellation Control Shaders";
5378 description
= "Combined Vulkan Vertex and Tessellation Control Shaders";
5380 name
= "Tessellation Control Shader";
5381 description
= "Vulkan Tessellation Control Shader";
5384 case MESA_SHADER_TESS_EVAL
:
5385 name
= "Tessellation Evaluation Shader";
5386 description
= "Vulkan Tessellation Evaluation Shader";
5388 case MESA_SHADER_GEOMETRY
:
5389 if (radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]) {
5390 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
;
5391 name
= "Tessellation Evaluation + Geometry Shaders";
5392 description
= "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5393 } else if (!radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5394 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5395 name
= "Vertex + Geometry Shader";
5396 description
= "Combined Vulkan Vertex and Geometry Shaders";
5398 name
= "Geometry Shader";
5399 description
= "Vulkan Geometry Shader";
5402 case MESA_SHADER_FRAGMENT
:
5403 name
= "Fragment Shader";
5404 description
= "Vulkan Fragment Shader";
5406 case MESA_SHADER_COMPUTE
:
5407 name
= "Compute Shader";
5408 description
= "Vulkan Compute Shader";
5412 pProperties
[executable_idx
].subgroupSize
= pipeline
->shaders
[i
]->info
.wave_size
;
5413 desc_copy(pProperties
[executable_idx
].name
, name
);
5414 desc_copy(pProperties
[executable_idx
].description
, description
);
5417 if (i
== MESA_SHADER_GEOMETRY
&&
5418 !radv_pipeline_has_ngg(pipeline
)) {
5419 assert(pipeline
->gs_copy_shader
);
5420 if (executable_idx
>= count
)
5423 pProperties
[executable_idx
].stages
= VK_SHADER_STAGE_GEOMETRY_BIT
;
5424 pProperties
[executable_idx
].subgroupSize
= 64;
5425 desc_copy(pProperties
[executable_idx
].name
, "GS Copy Shader");
5426 desc_copy(pProperties
[executable_idx
].description
,
5427 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5433 VkResult result
= *pExecutableCount
< total_count
? VK_INCOMPLETE
: VK_SUCCESS
;
5434 *pExecutableCount
= count
;
5438 VkResult
radv_GetPipelineExecutableStatisticsKHR(
5440 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5441 uint32_t* pStatisticCount
,
5442 VkPipelineExecutableStatisticKHR
* pStatistics
)
5444 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5445 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5446 gl_shader_stage stage
;
5447 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5449 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
5450 unsigned lds_increment
= chip_class
>= GFX7
? 512 : 256;
5451 unsigned max_waves
= radv_get_max_waves(device
, shader
, stage
);
5453 VkPipelineExecutableStatisticKHR
*s
= pStatistics
;
5454 VkPipelineExecutableStatisticKHR
*end
= s
+ (pStatistics
? *pStatisticCount
: 0);
5455 VkResult result
= VK_SUCCESS
;
5458 desc_copy(s
->name
, "SGPRs");
5459 desc_copy(s
->description
, "Number of SGPR registers allocated per subgroup");
5460 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5461 s
->value
.u64
= shader
->config
.num_sgprs
;
5466 desc_copy(s
->name
, "VGPRs");
5467 desc_copy(s
->description
, "Number of VGPR registers allocated per subgroup");
5468 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5469 s
->value
.u64
= shader
->config
.num_vgprs
;
5474 desc_copy(s
->name
, "Spilled SGPRs");
5475 desc_copy(s
->description
, "Number of SGPR registers spilled per subgroup");
5476 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5477 s
->value
.u64
= shader
->config
.spilled_sgprs
;
5482 desc_copy(s
->name
, "Spilled VGPRs");
5483 desc_copy(s
->description
, "Number of VGPR registers spilled per subgroup");
5484 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5485 s
->value
.u64
= shader
->config
.spilled_vgprs
;
5490 desc_copy(s
->name
, "PrivMem VGPRs");
5491 desc_copy(s
->description
, "Number of VGPRs stored in private memory per subgroup");
5492 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5493 s
->value
.u64
= shader
->info
.private_mem_vgprs
;
5498 desc_copy(s
->name
, "Code size");
5499 desc_copy(s
->description
, "Code size in bytes");
5500 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5501 s
->value
.u64
= shader
->exec_size
;
5506 desc_copy(s
->name
, "LDS size");
5507 desc_copy(s
->description
, "LDS size in bytes per workgroup");
5508 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5509 s
->value
.u64
= shader
->config
.lds_size
* lds_increment
;
5514 desc_copy(s
->name
, "Scratch size");
5515 desc_copy(s
->description
, "Private memory in bytes per subgroup");
5516 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5517 s
->value
.u64
= shader
->config
.scratch_bytes_per_wave
;
5522 desc_copy(s
->name
, "Subgroups per SIMD");
5523 desc_copy(s
->description
, "The maximum number of subgroups in flight on a SIMD unit");
5524 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5525 s
->value
.u64
= max_waves
;
5530 *pStatisticCount
= s
- pStatistics
;
5532 *pStatisticCount
= end
- pStatistics
;
5533 result
= VK_INCOMPLETE
;
5535 *pStatisticCount
= s
- pStatistics
;
5541 static VkResult
radv_copy_representation(void *data
, size_t *data_size
, const char *src
)
5543 size_t total_size
= strlen(src
) + 1;
5546 *data_size
= total_size
;
5550 size_t size
= MIN2(total_size
, *data_size
);
5552 memcpy(data
, src
, size
);
5554 *((char*)data
+ size
- 1) = 0;
5555 return size
< total_size
? VK_INCOMPLETE
: VK_SUCCESS
;
5558 VkResult
radv_GetPipelineExecutableInternalRepresentationsKHR(
5560 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5561 uint32_t* pInternalRepresentationCount
,
5562 VkPipelineExecutableInternalRepresentationKHR
* pInternalRepresentations
)
5564 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5565 gl_shader_stage stage
;
5566 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5568 VkPipelineExecutableInternalRepresentationKHR
*p
= pInternalRepresentations
;
5569 VkPipelineExecutableInternalRepresentationKHR
*end
= p
+ (pInternalRepresentations
? *pInternalRepresentationCount
: 0);
5570 VkResult result
= VK_SUCCESS
;
5574 desc_copy(p
->name
, "NIR Shader(s)");
5575 desc_copy(p
->description
, "The optimized NIR shader(s)");
5576 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->nir_string
) != VK_SUCCESS
)
5577 result
= VK_INCOMPLETE
;
5584 if (shader
->aco_used
) {
5585 desc_copy(p
->name
, "ACO IR");
5586 desc_copy(p
->description
, "The ACO IR after some optimizations");
5588 desc_copy(p
->name
, "LLVM IR");
5589 desc_copy(p
->description
, "The LLVM IR after some optimizations");
5591 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->ir_string
) != VK_SUCCESS
)
5592 result
= VK_INCOMPLETE
;
5599 desc_copy(p
->name
, "Assembly");
5600 desc_copy(p
->description
, "Final Assembly");
5601 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->disasm_string
) != VK_SUCCESS
)
5602 result
= VK_INCOMPLETE
;
5606 if (!pInternalRepresentations
)
5607 *pInternalRepresentationCount
= p
- pInternalRepresentations
;
5609 result
= VK_INCOMPLETE
;
5610 *pInternalRepresentationCount
= end
- pInternalRepresentations
;
5612 *pInternalRepresentationCount
= p
- pInternalRepresentations
;