2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
34 #include "radv_shader.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
41 #include <llvm-c/Core.h>
42 #include <llvm-c/TargetMachine.h>
45 #include "ac_binary.h"
46 #include "ac_llvm_util.h"
47 #include "ac_nir_to_llvm.h"
48 #include "vk_format.h"
49 #include "util/debug.h"
50 #include "ac_exp_param.h"
51 #include "ac_shader_util.h"
52 #include "main/menums.h"
54 struct radv_blend_state
{
55 uint32_t blend_enable_4bit
;
56 uint32_t need_src_alpha
;
58 uint32_t cb_color_control
;
59 uint32_t cb_target_mask
;
60 uint32_t cb_target_enabled_4bit
;
61 uint32_t sx_mrt_blend_opt
[8];
62 uint32_t cb_blend_control
[8];
64 uint32_t spi_shader_col_format
;
65 uint32_t cb_shader_mask
;
66 uint32_t db_alpha_to_mask
;
68 uint32_t commutative_4bit
;
70 bool single_cb_enable
;
71 bool mrt0_is_dual_src
;
74 struct radv_dsa_order_invariance
{
75 /* Whether the final result in Z/S buffers is guaranteed to be
76 * invariant under changes to the order in which fragments arrive.
80 /* Whether the set of fragments that pass the combined Z/S test is
81 * guaranteed to be invariant under changes to the order in which
87 struct radv_tessellation_state
{
88 uint32_t ls_hs_config
;
94 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
)
96 struct radv_shader_variant
*variant
= NULL
;
97 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
98 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
99 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
100 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
101 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
102 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
105 return variant
->info
.is_ngg
;
108 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
)
110 if (!radv_pipeline_has_gs(pipeline
))
113 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
114 * On GFX10, it might be required in rare cases if it's not possible to
117 if (radv_pipeline_has_ngg(pipeline
))
120 assert(pipeline
->gs_copy_shader
);
125 radv_pipeline_destroy(struct radv_device
*device
,
126 struct radv_pipeline
*pipeline
,
127 const VkAllocationCallbacks
* allocator
)
129 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
130 if (pipeline
->shaders
[i
])
131 radv_shader_variant_destroy(device
, pipeline
->shaders
[i
]);
133 if (pipeline
->gs_copy_shader
)
134 radv_shader_variant_destroy(device
, pipeline
->gs_copy_shader
);
137 free(pipeline
->cs
.buf
);
138 vk_free2(&device
->alloc
, allocator
, pipeline
);
141 void radv_DestroyPipeline(
143 VkPipeline _pipeline
,
144 const VkAllocationCallbacks
* pAllocator
)
146 RADV_FROM_HANDLE(radv_device
, device
, _device
);
147 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
152 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
155 static uint32_t get_hash_flags(struct radv_device
*device
)
157 uint32_t hash_flags
= 0;
159 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_NGG
)
160 hash_flags
|= RADV_HASH_SHADER_NO_NGG
;
161 if (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
)
162 hash_flags
|= RADV_HASH_SHADER_SISCHED
;
163 if (device
->physical_device
->cs_wave_size
== 32)
164 hash_flags
|= RADV_HASH_SHADER_CS_WAVE32
;
165 if (device
->physical_device
->ps_wave_size
== 32)
166 hash_flags
|= RADV_HASH_SHADER_PS_WAVE32
;
167 if (device
->physical_device
->ge_wave_size
== 32)
168 hash_flags
|= RADV_HASH_SHADER_GE_WAVE32
;
169 if (device
->physical_device
->use_aco
)
170 hash_flags
|= RADV_HASH_SHADER_ACO
;
175 radv_pipeline_scratch_init(struct radv_device
*device
,
176 struct radv_pipeline
*pipeline
)
178 unsigned scratch_bytes_per_wave
= 0;
179 unsigned max_waves
= 0;
180 unsigned min_waves
= 1;
182 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
183 if (pipeline
->shaders
[i
] &&
184 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
) {
185 unsigned max_stage_waves
= device
->scratch_waves
;
187 scratch_bytes_per_wave
= MAX2(scratch_bytes_per_wave
,
188 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
);
190 max_stage_waves
= MIN2(max_stage_waves
,
191 4 * device
->physical_device
->rad_info
.num_good_compute_units
*
192 (256 / pipeline
->shaders
[i
]->config
.num_vgprs
));
193 max_waves
= MAX2(max_waves
, max_stage_waves
);
197 if (pipeline
->shaders
[MESA_SHADER_COMPUTE
]) {
198 unsigned group_size
= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[0] *
199 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[1] *
200 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[2];
201 min_waves
= MAX2(min_waves
, round_up_u32(group_size
, 64));
204 pipeline
->scratch_bytes_per_wave
= scratch_bytes_per_wave
;
205 pipeline
->max_waves
= max_waves
;
209 static uint32_t si_translate_blend_logic_op(VkLogicOp op
)
212 case VK_LOGIC_OP_CLEAR
:
213 return V_028808_ROP3_CLEAR
;
214 case VK_LOGIC_OP_AND
:
215 return V_028808_ROP3_AND
;
216 case VK_LOGIC_OP_AND_REVERSE
:
217 return V_028808_ROP3_AND_REVERSE
;
218 case VK_LOGIC_OP_COPY
:
219 return V_028808_ROP3_COPY
;
220 case VK_LOGIC_OP_AND_INVERTED
:
221 return V_028808_ROP3_AND_INVERTED
;
222 case VK_LOGIC_OP_NO_OP
:
223 return V_028808_ROP3_NO_OP
;
224 case VK_LOGIC_OP_XOR
:
225 return V_028808_ROP3_XOR
;
227 return V_028808_ROP3_OR
;
228 case VK_LOGIC_OP_NOR
:
229 return V_028808_ROP3_NOR
;
230 case VK_LOGIC_OP_EQUIVALENT
:
231 return V_028808_ROP3_EQUIVALENT
;
232 case VK_LOGIC_OP_INVERT
:
233 return V_028808_ROP3_INVERT
;
234 case VK_LOGIC_OP_OR_REVERSE
:
235 return V_028808_ROP3_OR_REVERSE
;
236 case VK_LOGIC_OP_COPY_INVERTED
:
237 return V_028808_ROP3_COPY_INVERTED
;
238 case VK_LOGIC_OP_OR_INVERTED
:
239 return V_028808_ROP3_OR_INVERTED
;
240 case VK_LOGIC_OP_NAND
:
241 return V_028808_ROP3_NAND
;
242 case VK_LOGIC_OP_SET
:
243 return V_028808_ROP3_SET
;
245 unreachable("Unhandled logic op");
250 static uint32_t si_translate_blend_function(VkBlendOp op
)
253 case VK_BLEND_OP_ADD
:
254 return V_028780_COMB_DST_PLUS_SRC
;
255 case VK_BLEND_OP_SUBTRACT
:
256 return V_028780_COMB_SRC_MINUS_DST
;
257 case VK_BLEND_OP_REVERSE_SUBTRACT
:
258 return V_028780_COMB_DST_MINUS_SRC
;
259 case VK_BLEND_OP_MIN
:
260 return V_028780_COMB_MIN_DST_SRC
;
261 case VK_BLEND_OP_MAX
:
262 return V_028780_COMB_MAX_DST_SRC
;
268 static uint32_t si_translate_blend_factor(VkBlendFactor factor
)
271 case VK_BLEND_FACTOR_ZERO
:
272 return V_028780_BLEND_ZERO
;
273 case VK_BLEND_FACTOR_ONE
:
274 return V_028780_BLEND_ONE
;
275 case VK_BLEND_FACTOR_SRC_COLOR
:
276 return V_028780_BLEND_SRC_COLOR
;
277 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
278 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
279 case VK_BLEND_FACTOR_DST_COLOR
:
280 return V_028780_BLEND_DST_COLOR
;
281 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
282 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
283 case VK_BLEND_FACTOR_SRC_ALPHA
:
284 return V_028780_BLEND_SRC_ALPHA
;
285 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
286 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
287 case VK_BLEND_FACTOR_DST_ALPHA
:
288 return V_028780_BLEND_DST_ALPHA
;
289 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
290 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
291 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
292 return V_028780_BLEND_CONSTANT_COLOR
;
293 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
294 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
295 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
296 return V_028780_BLEND_CONSTANT_ALPHA
;
297 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
298 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
299 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
300 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
301 case VK_BLEND_FACTOR_SRC1_COLOR
:
302 return V_028780_BLEND_SRC1_COLOR
;
303 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
304 return V_028780_BLEND_INV_SRC1_COLOR
;
305 case VK_BLEND_FACTOR_SRC1_ALPHA
:
306 return V_028780_BLEND_SRC1_ALPHA
;
307 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
308 return V_028780_BLEND_INV_SRC1_ALPHA
;
314 static uint32_t si_translate_blend_opt_function(VkBlendOp op
)
317 case VK_BLEND_OP_ADD
:
318 return V_028760_OPT_COMB_ADD
;
319 case VK_BLEND_OP_SUBTRACT
:
320 return V_028760_OPT_COMB_SUBTRACT
;
321 case VK_BLEND_OP_REVERSE_SUBTRACT
:
322 return V_028760_OPT_COMB_REVSUBTRACT
;
323 case VK_BLEND_OP_MIN
:
324 return V_028760_OPT_COMB_MIN
;
325 case VK_BLEND_OP_MAX
:
326 return V_028760_OPT_COMB_MAX
;
328 return V_028760_OPT_COMB_BLEND_DISABLED
;
332 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor
, bool is_alpha
)
335 case VK_BLEND_FACTOR_ZERO
:
336 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
337 case VK_BLEND_FACTOR_ONE
:
338 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
339 case VK_BLEND_FACTOR_SRC_COLOR
:
340 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
341 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
342 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
343 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
344 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
345 case VK_BLEND_FACTOR_SRC_ALPHA
:
346 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
347 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
348 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
349 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
350 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
351 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
353 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
358 * Get rid of DST in the blend factors by commuting the operands:
359 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
361 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
362 unsigned *dst_factor
, unsigned expected_dst
,
363 unsigned replacement_src
)
365 if (*src_factor
== expected_dst
&&
366 *dst_factor
== VK_BLEND_FACTOR_ZERO
) {
367 *src_factor
= VK_BLEND_FACTOR_ZERO
;
368 *dst_factor
= replacement_src
;
370 /* Commuting the operands requires reversing subtractions. */
371 if (*func
== VK_BLEND_OP_SUBTRACT
)
372 *func
= VK_BLEND_OP_REVERSE_SUBTRACT
;
373 else if (*func
== VK_BLEND_OP_REVERSE_SUBTRACT
)
374 *func
= VK_BLEND_OP_SUBTRACT
;
378 static bool si_blend_factor_uses_dst(unsigned factor
)
380 return factor
== VK_BLEND_FACTOR_DST_COLOR
||
381 factor
== VK_BLEND_FACTOR_DST_ALPHA
||
382 factor
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
383 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
||
384 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
;
387 static bool is_dual_src(VkBlendFactor factor
)
390 case VK_BLEND_FACTOR_SRC1_COLOR
:
391 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
392 case VK_BLEND_FACTOR_SRC1_ALPHA
:
393 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
400 static unsigned si_choose_spi_color_format(VkFormat vk_format
,
402 bool blend_need_alpha
)
404 const struct vk_format_description
*desc
= vk_format_description(vk_format
);
405 unsigned format
, ntype
, swap
;
407 /* Alpha is needed for alpha-to-coverage.
408 * Blending may be with or without alpha.
410 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
411 unsigned alpha
= 0; /* exports alpha, but may not support blending */
412 unsigned blend
= 0; /* supports blending, but may not export alpha */
413 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
415 format
= radv_translate_colorformat(vk_format
);
416 ntype
= radv_translate_color_numformat(vk_format
, desc
,
417 vk_format_get_first_non_void_channel(vk_format
));
418 swap
= radv_translate_colorswap(vk_format
, false);
420 /* Choose the SPI color formats. These are required values for Stoney/RB+.
421 * Other chips have multiple choices, though they are not necessarily better.
424 case V_028C70_COLOR_5_6_5
:
425 case V_028C70_COLOR_1_5_5_5
:
426 case V_028C70_COLOR_5_5_5_1
:
427 case V_028C70_COLOR_4_4_4_4
:
428 case V_028C70_COLOR_10_11_11
:
429 case V_028C70_COLOR_11_11_10
:
430 case V_028C70_COLOR_8
:
431 case V_028C70_COLOR_8_8
:
432 case V_028C70_COLOR_8_8_8_8
:
433 case V_028C70_COLOR_10_10_10_2
:
434 case V_028C70_COLOR_2_10_10_10
:
435 if (ntype
== V_028C70_NUMBER_UINT
)
436 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
437 else if (ntype
== V_028C70_NUMBER_SINT
)
438 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
440 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
443 case V_028C70_COLOR_16
:
444 case V_028C70_COLOR_16_16
:
445 case V_028C70_COLOR_16_16_16_16
:
446 if (ntype
== V_028C70_NUMBER_UNORM
||
447 ntype
== V_028C70_NUMBER_SNORM
) {
448 /* UNORM16 and SNORM16 don't support blending */
449 if (ntype
== V_028C70_NUMBER_UNORM
)
450 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
452 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
454 /* Use 32 bits per channel for blending. */
455 if (format
== V_028C70_COLOR_16
) {
456 if (swap
== V_028C70_SWAP_STD
) { /* R */
457 blend
= V_028714_SPI_SHADER_32_R
;
458 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
459 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
460 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
463 } else if (format
== V_028C70_COLOR_16_16
) {
464 if (swap
== V_028C70_SWAP_STD
) { /* RG */
465 blend
= V_028714_SPI_SHADER_32_GR
;
466 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
467 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
468 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
471 } else /* 16_16_16_16 */
472 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
473 } else if (ntype
== V_028C70_NUMBER_UINT
)
474 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
475 else if (ntype
== V_028C70_NUMBER_SINT
)
476 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
477 else if (ntype
== V_028C70_NUMBER_FLOAT
)
478 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
483 case V_028C70_COLOR_32
:
484 if (swap
== V_028C70_SWAP_STD
) { /* R */
485 blend
= normal
= V_028714_SPI_SHADER_32_R
;
486 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
487 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
488 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
493 case V_028C70_COLOR_32_32
:
494 if (swap
== V_028C70_SWAP_STD
) { /* RG */
495 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
496 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
497 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
498 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
503 case V_028C70_COLOR_32_32_32_32
:
504 case V_028C70_COLOR_8_24
:
505 case V_028C70_COLOR_24_8
:
506 case V_028C70_COLOR_X24_8_32_FLOAT
:
507 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
511 unreachable("unhandled blend format");
514 if (blend_enable
&& blend_need_alpha
)
516 else if(blend_need_alpha
)
518 else if(blend_enable
)
525 radv_pipeline_compute_spi_color_formats(struct radv_pipeline
*pipeline
,
526 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
527 struct radv_blend_state
*blend
)
529 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
530 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
531 unsigned col_format
= 0;
532 unsigned num_targets
;
534 for (unsigned i
= 0; i
< (blend
->single_cb_enable
? 1 : subpass
->color_count
); ++i
) {
537 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
538 cf
= V_028714_SPI_SHADER_ZERO
;
540 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
542 blend
->blend_enable_4bit
& (0xfu
<< (i
* 4));
544 cf
= si_choose_spi_color_format(attachment
->format
,
546 blend
->need_src_alpha
& (1 << i
));
549 col_format
|= cf
<< (4 * i
);
552 if (!(col_format
& 0xf) && blend
->need_src_alpha
& (1 << 0)) {
553 /* When a subpass doesn't have any color attachments, write the
554 * alpha channel of MRT0 when alpha coverage is enabled because
555 * the depth attachment needs it.
557 col_format
|= V_028714_SPI_SHADER_32_AR
;
560 /* If the i-th target format is set, all previous target formats must
561 * be non-zero to avoid hangs.
563 num_targets
= (util_last_bit(col_format
) + 3) / 4;
564 for (unsigned i
= 0; i
< num_targets
; i
++) {
565 if (!(col_format
& (0xf << (i
* 4)))) {
566 col_format
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
570 /* The output for dual source blending should have the same format as
573 if (blend
->mrt0_is_dual_src
)
574 col_format
|= (col_format
& 0xf) << 4;
576 blend
->cb_shader_mask
= ac_get_cb_shader_mask(col_format
);
577 blend
->spi_shader_col_format
= col_format
;
581 format_is_int8(VkFormat format
)
583 const struct vk_format_description
*desc
= vk_format_description(format
);
584 int channel
= vk_format_get_first_non_void_channel(format
);
586 return channel
>= 0 && desc
->channel
[channel
].pure_integer
&&
587 desc
->channel
[channel
].size
== 8;
591 format_is_int10(VkFormat format
)
593 const struct vk_format_description
*desc
= vk_format_description(format
);
595 if (desc
->nr_channels
!= 4)
597 for (unsigned i
= 0; i
< 4; i
++) {
598 if (desc
->channel
[i
].pure_integer
&& desc
->channel
[i
].size
== 10)
605 * Ordered so that for each i,
606 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
608 const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
] = {
609 VK_FORMAT_R32_SFLOAT
,
610 VK_FORMAT_R32G32_SFLOAT
,
611 VK_FORMAT_R8G8B8A8_UNORM
,
612 VK_FORMAT_R16G16B16A16_UNORM
,
613 VK_FORMAT_R16G16B16A16_SNORM
,
614 VK_FORMAT_R16G16B16A16_UINT
,
615 VK_FORMAT_R16G16B16A16_SINT
,
616 VK_FORMAT_R32G32B32A32_SFLOAT
,
617 VK_FORMAT_R8G8B8A8_UINT
,
618 VK_FORMAT_R8G8B8A8_SINT
,
619 VK_FORMAT_A2R10G10B10_UINT_PACK32
,
620 VK_FORMAT_A2R10G10B10_SINT_PACK32
,
623 unsigned radv_format_meta_fs_key(VkFormat format
)
625 unsigned col_format
= si_choose_spi_color_format(format
, false, false);
627 assert(col_format
!= V_028714_SPI_SHADER_32_AR
);
628 if (col_format
>= V_028714_SPI_SHADER_32_AR
)
629 --col_format
; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
631 --col_format
; /* Skip V_028714_SPI_SHADER_ZERO */
632 bool is_int8
= format_is_int8(format
);
633 bool is_int10
= format_is_int10(format
);
635 return col_format
+ (is_int8
? 3 : is_int10
? 5 : 0);
639 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
640 unsigned *is_int8
, unsigned *is_int10
)
642 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
643 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
647 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
648 struct radv_render_pass_attachment
*attachment
;
650 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
653 attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
655 if (format_is_int8(attachment
->format
))
657 if (format_is_int10(attachment
->format
))
663 radv_blend_check_commutativity(struct radv_blend_state
*blend
,
664 VkBlendOp op
, VkBlendFactor src
,
665 VkBlendFactor dst
, unsigned chanmask
)
667 /* Src factor is allowed when it does not depend on Dst. */
668 static const uint32_t src_allowed
=
669 (1u << VK_BLEND_FACTOR_ONE
) |
670 (1u << VK_BLEND_FACTOR_SRC_COLOR
) |
671 (1u << VK_BLEND_FACTOR_SRC_ALPHA
) |
672 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
) |
673 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR
) |
674 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA
) |
675 (1u << VK_BLEND_FACTOR_SRC1_COLOR
) |
676 (1u << VK_BLEND_FACTOR_SRC1_ALPHA
) |
677 (1u << VK_BLEND_FACTOR_ZERO
) |
678 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
) |
679 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
) |
680 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
) |
681 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
) |
682 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
) |
683 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
);
685 if (dst
== VK_BLEND_FACTOR_ONE
&&
686 (src_allowed
& (1u << src
))) {
687 /* Addition is commutative, but floating point addition isn't
688 * associative: subtle changes can be introduced via different
689 * rounding. Be conservative, only enable for min and max.
691 if (op
== VK_BLEND_OP_MAX
|| op
== VK_BLEND_OP_MIN
)
692 blend
->commutative_4bit
|= chanmask
;
696 static struct radv_blend_state
697 radv_pipeline_init_blend_state(struct radv_pipeline
*pipeline
,
698 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
699 const struct radv_graphics_pipeline_create_info
*extra
)
701 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
702 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
703 struct radv_blend_state blend
= {0};
704 unsigned mode
= V_028808_CB_NORMAL
;
710 if (extra
&& extra
->custom_blend_mode
) {
711 blend
.single_cb_enable
= true;
712 mode
= extra
->custom_blend_mode
;
714 blend
.cb_color_control
= 0;
715 if (vkblend
->logicOpEnable
)
716 blend
.cb_color_control
|= S_028808_ROP3(si_translate_blend_logic_op(vkblend
->logicOp
));
718 blend
.cb_color_control
|= S_028808_ROP3(V_028808_ROP3_COPY
);
720 blend
.db_alpha_to_mask
= S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
721 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
722 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
723 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
724 S_028B70_OFFSET_ROUND(1);
726 if (vkms
&& vkms
->alphaToCoverageEnable
) {
727 blend
.db_alpha_to_mask
|= S_028B70_ALPHA_TO_MASK_ENABLE(1);
728 blend
.need_src_alpha
|= 0x1;
731 blend
.cb_target_mask
= 0;
732 for (i
= 0; i
< vkblend
->attachmentCount
; i
++) {
733 const VkPipelineColorBlendAttachmentState
*att
= &vkblend
->pAttachments
[i
];
734 unsigned blend_cntl
= 0;
735 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
736 VkBlendOp eqRGB
= att
->colorBlendOp
;
737 VkBlendFactor srcRGB
= att
->srcColorBlendFactor
;
738 VkBlendFactor dstRGB
= att
->dstColorBlendFactor
;
739 VkBlendOp eqA
= att
->alphaBlendOp
;
740 VkBlendFactor srcA
= att
->srcAlphaBlendFactor
;
741 VkBlendFactor dstA
= att
->dstAlphaBlendFactor
;
743 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
745 if (!att
->colorWriteMask
)
748 blend
.cb_target_mask
|= (unsigned)att
->colorWriteMask
<< (4 * i
);
749 blend
.cb_target_enabled_4bit
|= 0xf << (4 * i
);
750 if (!att
->blendEnable
) {
751 blend
.cb_blend_control
[i
] = blend_cntl
;
755 if (is_dual_src(srcRGB
) || is_dual_src(dstRGB
) || is_dual_src(srcA
) || is_dual_src(dstA
))
757 blend
.mrt0_is_dual_src
= true;
759 if (eqRGB
== VK_BLEND_OP_MIN
|| eqRGB
== VK_BLEND_OP_MAX
) {
760 srcRGB
= VK_BLEND_FACTOR_ONE
;
761 dstRGB
= VK_BLEND_FACTOR_ONE
;
763 if (eqA
== VK_BLEND_OP_MIN
|| eqA
== VK_BLEND_OP_MAX
) {
764 srcA
= VK_BLEND_FACTOR_ONE
;
765 dstA
= VK_BLEND_FACTOR_ONE
;
768 radv_blend_check_commutativity(&blend
, eqRGB
, srcRGB
, dstRGB
,
770 radv_blend_check_commutativity(&blend
, eqA
, srcA
, dstA
,
773 /* Blending optimizations for RB+.
774 * These transformations don't change the behavior.
776 * First, get rid of DST in the blend factors:
777 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
779 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
780 VK_BLEND_FACTOR_DST_COLOR
,
781 VK_BLEND_FACTOR_SRC_COLOR
);
783 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
784 VK_BLEND_FACTOR_DST_COLOR
,
785 VK_BLEND_FACTOR_SRC_COLOR
);
787 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
788 VK_BLEND_FACTOR_DST_ALPHA
,
789 VK_BLEND_FACTOR_SRC_ALPHA
);
791 /* Look up the ideal settings from tables. */
792 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
793 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
794 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
795 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
797 /* Handle interdependencies. */
798 if (si_blend_factor_uses_dst(srcRGB
))
799 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
800 if (si_blend_factor_uses_dst(srcA
))
801 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
803 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
&&
804 (dstRGB
== VK_BLEND_FACTOR_ZERO
||
805 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
806 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
))
807 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
809 /* Set the final value. */
810 blend
.sx_mrt_blend_opt
[i
] =
811 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
812 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
813 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
814 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
815 S_028760_ALPHA_DST_OPT(dstA_opt
) |
816 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
817 blend_cntl
|= S_028780_ENABLE(1);
819 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
820 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
821 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
822 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
823 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
824 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
825 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
826 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
828 blend
.cb_blend_control
[i
] = blend_cntl
;
830 blend
.blend_enable_4bit
|= 0xfu
<< (i
* 4);
832 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
833 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
834 srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
835 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
836 srcRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
||
837 dstRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
)
838 blend
.need_src_alpha
|= 1 << i
;
840 for (i
= vkblend
->attachmentCount
; i
< 8; i
++) {
841 blend
.cb_blend_control
[i
] = 0;
842 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
845 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
846 /* Disable RB+ blend optimizations for dual source blending. */
847 if (blend
.mrt0_is_dual_src
) {
848 for (i
= 0; i
< 8; i
++) {
849 blend
.sx_mrt_blend_opt
[i
] =
850 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
851 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
855 /* RB+ doesn't work with dual source blending, logic op and
858 if (blend
.mrt0_is_dual_src
|| vkblend
->logicOpEnable
||
859 mode
== V_028808_CB_RESOLVE
)
860 blend
.cb_color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
863 if (blend
.cb_target_mask
)
864 blend
.cb_color_control
|= S_028808_MODE(mode
);
866 blend
.cb_color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
868 radv_pipeline_compute_spi_color_formats(pipeline
, pCreateInfo
, &blend
);
872 static uint32_t si_translate_stencil_op(enum VkStencilOp op
)
875 case VK_STENCIL_OP_KEEP
:
876 return V_02842C_STENCIL_KEEP
;
877 case VK_STENCIL_OP_ZERO
:
878 return V_02842C_STENCIL_ZERO
;
879 case VK_STENCIL_OP_REPLACE
:
880 return V_02842C_STENCIL_REPLACE_TEST
;
881 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
882 return V_02842C_STENCIL_ADD_CLAMP
;
883 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
884 return V_02842C_STENCIL_SUB_CLAMP
;
885 case VK_STENCIL_OP_INVERT
:
886 return V_02842C_STENCIL_INVERT
;
887 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
888 return V_02842C_STENCIL_ADD_WRAP
;
889 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
890 return V_02842C_STENCIL_SUB_WRAP
;
896 static uint32_t si_translate_fill(VkPolygonMode func
)
899 case VK_POLYGON_MODE_FILL
:
900 return V_028814_X_DRAW_TRIANGLES
;
901 case VK_POLYGON_MODE_LINE
:
902 return V_028814_X_DRAW_LINES
;
903 case VK_POLYGON_MODE_POINT
:
904 return V_028814_X_DRAW_POINTS
;
907 return V_028814_X_DRAW_POINTS
;
911 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo
*vkms
)
913 uint32_t num_samples
= vkms
->rasterizationSamples
;
914 uint32_t ps_iter_samples
= 1;
916 if (vkms
->sampleShadingEnable
) {
917 ps_iter_samples
= ceil(vkms
->minSampleShading
* num_samples
);
918 ps_iter_samples
= util_next_power_of_two(ps_iter_samples
);
920 return ps_iter_samples
;
924 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
926 return pCreateInfo
->depthTestEnable
&&
927 pCreateInfo
->depthWriteEnable
&&
928 pCreateInfo
->depthCompareOp
!= VK_COMPARE_OP_NEVER
;
932 radv_writes_stencil(const VkStencilOpState
*state
)
934 return state
->writeMask
&&
935 (state
->failOp
!= VK_STENCIL_OP_KEEP
||
936 state
->passOp
!= VK_STENCIL_OP_KEEP
||
937 state
->depthFailOp
!= VK_STENCIL_OP_KEEP
);
941 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
943 return pCreateInfo
->stencilTestEnable
&&
944 (radv_writes_stencil(&pCreateInfo
->front
) ||
945 radv_writes_stencil(&pCreateInfo
->back
));
949 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
951 return radv_is_depth_write_enabled(pCreateInfo
) ||
952 radv_is_stencil_write_enabled(pCreateInfo
);
956 radv_order_invariant_stencil_op(VkStencilOp op
)
958 /* REPLACE is normally order invariant, except when the stencil
959 * reference value is written by the fragment shader. Tracking this
960 * interaction does not seem worth the effort, so be conservative.
962 return op
!= VK_STENCIL_OP_INCREMENT_AND_CLAMP
&&
963 op
!= VK_STENCIL_OP_DECREMENT_AND_CLAMP
&&
964 op
!= VK_STENCIL_OP_REPLACE
;
968 radv_order_invariant_stencil_state(const VkStencilOpState
*state
)
970 /* Compute whether, assuming Z writes are disabled, this stencil state
971 * is order invariant in the sense that the set of passing fragments as
972 * well as the final stencil buffer result does not depend on the order
975 return !state
->writeMask
||
976 /* The following assumes that Z writes are disabled. */
977 (state
->compareOp
== VK_COMPARE_OP_ALWAYS
&&
978 radv_order_invariant_stencil_op(state
->passOp
) &&
979 radv_order_invariant_stencil_op(state
->depthFailOp
)) ||
980 (state
->compareOp
== VK_COMPARE_OP_NEVER
&&
981 radv_order_invariant_stencil_op(state
->failOp
));
985 radv_pipeline_out_of_order_rast(struct radv_pipeline
*pipeline
,
986 struct radv_blend_state
*blend
,
987 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
989 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
990 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
991 unsigned colormask
= blend
->cb_target_enabled_4bit
;
993 if (!pipeline
->device
->physical_device
->out_of_order_rast_allowed
)
996 /* Be conservative if a logic operation is enabled with color buffers. */
997 if (colormask
&& pCreateInfo
->pColorBlendState
->logicOpEnable
)
1000 /* Default depth/stencil invariance when no attachment is bound. */
1001 struct radv_dsa_order_invariance dsa_order_invariant
= {
1002 .zs
= true, .pass_set
= true
1005 if (pCreateInfo
->pDepthStencilState
&&
1006 subpass
->depth_stencil_attachment
) {
1007 const VkPipelineDepthStencilStateCreateInfo
*vkds
=
1008 pCreateInfo
->pDepthStencilState
;
1009 struct radv_render_pass_attachment
*attachment
=
1010 pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
1011 bool has_stencil
= vk_format_is_stencil(attachment
->format
);
1012 struct radv_dsa_order_invariance order_invariance
[2];
1013 struct radv_shader_variant
*ps
=
1014 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
1016 /* Compute depth/stencil order invariance in order to know if
1017 * it's safe to enable out-of-order.
1019 bool zfunc_is_ordered
=
1020 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
||
1021 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS
||
1022 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS_OR_EQUAL
||
1023 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER
||
1024 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER_OR_EQUAL
;
1026 bool nozwrite_and_order_invariant_stencil
=
1027 !radv_is_ds_write_enabled(vkds
) ||
1028 (!radv_is_depth_write_enabled(vkds
) &&
1029 radv_order_invariant_stencil_state(&vkds
->front
) &&
1030 radv_order_invariant_stencil_state(&vkds
->back
));
1032 order_invariance
[1].zs
=
1033 nozwrite_and_order_invariant_stencil
||
1034 (!radv_is_stencil_write_enabled(vkds
) &&
1036 order_invariance
[0].zs
=
1037 !radv_is_depth_write_enabled(vkds
) || zfunc_is_ordered
;
1039 order_invariance
[1].pass_set
=
1040 nozwrite_and_order_invariant_stencil
||
1041 (!radv_is_stencil_write_enabled(vkds
) &&
1042 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1043 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
));
1044 order_invariance
[0].pass_set
=
1045 !radv_is_depth_write_enabled(vkds
) ||
1046 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1047 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
);
1049 dsa_order_invariant
= order_invariance
[has_stencil
];
1050 if (!dsa_order_invariant
.zs
)
1053 /* The set of PS invocations is always order invariant,
1054 * except when early Z/S tests are requested.
1057 ps
->info
.ps
.writes_memory
&&
1058 ps
->info
.ps
.early_fragment_test
&&
1059 !dsa_order_invariant
.pass_set
)
1062 /* Determine if out-of-order rasterization should be disabled
1063 * when occlusion queries are used.
1065 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
=
1066 !dsa_order_invariant
.pass_set
;
1069 /* No color buffers are enabled for writing. */
1073 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
1076 /* Only commutative blending. */
1077 if (blendmask
& ~blend
->commutative_4bit
)
1080 if (!dsa_order_invariant
.pass_set
)
1084 if (colormask
& ~blendmask
)
1091 radv_pipeline_init_multisample_state(struct radv_pipeline
*pipeline
,
1092 struct radv_blend_state
*blend
,
1093 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1095 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
1096 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
1097 unsigned num_tile_pipes
= pipeline
->device
->physical_device
->rad_info
.num_tile_pipes
;
1098 bool out_of_order_rast
= false;
1099 int ps_iter_samples
= 1;
1100 uint32_t mask
= 0xffff;
1103 ms
->num_samples
= vkms
->rasterizationSamples
;
1105 ms
->num_samples
= 1;
1108 ps_iter_samples
= radv_pipeline_get_ps_iter_samples(vkms
);
1109 if (vkms
&& !vkms
->sampleShadingEnable
&& pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.force_persample
) {
1110 ps_iter_samples
= ms
->num_samples
;
1113 const struct VkPipelineRasterizationStateRasterizationOrderAMD
*raster_order
=
1114 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD
);
1115 if (raster_order
&& raster_order
->rasterizationOrder
== VK_RASTERIZATION_ORDER_RELAXED_AMD
) {
1116 /* Out-of-order rasterization is explicitly enabled by the
1119 out_of_order_rast
= true;
1121 /* Determine if the driver can enable out-of-order
1122 * rasterization internally.
1125 radv_pipeline_out_of_order_rast(pipeline
, blend
, pCreateInfo
);
1128 ms
->pa_sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1129 ms
->pa_sc_aa_config
= 0;
1130 ms
->db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1131 S_028804_INCOHERENT_EQAA_READS(1) |
1132 S_028804_INTERPOLATE_COMP_Z(1) |
1133 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1134 ms
->pa_sc_mode_cntl_1
=
1135 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1136 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
1137 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
1138 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1140 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1141 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1142 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1143 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1144 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1145 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1146 ms
->pa_sc_mode_cntl_0
= S_028A48_ALTERNATE_RBS_PER_TILE(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
1147 S_028A48_VPORT_SCISSOR_ENABLE(1);
1149 if (ms
->num_samples
> 1) {
1150 unsigned log_samples
= util_logbase2(ms
->num_samples
);
1151 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
1152 ms
->pa_sc_mode_cntl_0
|= S_028A48_MSAA_ENABLE(1);
1153 ms
->pa_sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1154 ms
->db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_samples
) |
1155 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
1156 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
1157 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
1158 ms
->pa_sc_aa_config
|= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
1159 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples
)) |
1160 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1161 ms
->pa_sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
1162 if (ps_iter_samples
> 1)
1163 pipeline
->graphics
.spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1166 if (vkms
&& vkms
->pSampleMask
) {
1167 mask
= vkms
->pSampleMask
[0] & 0xffff;
1170 ms
->pa_sc_aa_mask
[0] = mask
| (mask
<< 16);
1171 ms
->pa_sc_aa_mask
[1] = mask
| (mask
<< 16);
1175 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology
)
1178 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1179 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1180 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1181 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1182 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1184 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1185 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1186 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1187 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1188 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1189 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1192 unreachable("unhandled primitive type");
1197 si_translate_prim(enum VkPrimitiveTopology topology
)
1200 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1201 return V_008958_DI_PT_POINTLIST
;
1202 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1203 return V_008958_DI_PT_LINELIST
;
1204 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1205 return V_008958_DI_PT_LINESTRIP
;
1206 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1207 return V_008958_DI_PT_TRILIST
;
1208 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1209 return V_008958_DI_PT_TRISTRIP
;
1210 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1211 return V_008958_DI_PT_TRIFAN
;
1212 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1213 return V_008958_DI_PT_LINELIST_ADJ
;
1214 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1215 return V_008958_DI_PT_LINESTRIP_ADJ
;
1216 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1217 return V_008958_DI_PT_TRILIST_ADJ
;
1218 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1219 return V_008958_DI_PT_TRISTRIP_ADJ
;
1220 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1221 return V_008958_DI_PT_PATCH
;
1229 si_conv_gl_prim_to_gs_out(unsigned gl_prim
)
1232 case 0: /* GL_POINTS */
1233 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1234 case 1: /* GL_LINES */
1235 case 3: /* GL_LINE_STRIP */
1236 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1237 case 0x8E7A: /* GL_ISOLINES */
1238 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1240 case 4: /* GL_TRIANGLES */
1241 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1242 case 5: /* GL_TRIANGLE_STRIP */
1243 case 7: /* GL_QUADS */
1244 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1252 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology
)
1255 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1256 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1257 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1258 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1259 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1260 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1261 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1262 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1263 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1264 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1265 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1266 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1267 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1268 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1275 static unsigned radv_dynamic_state_mask(VkDynamicState state
)
1278 case VK_DYNAMIC_STATE_VIEWPORT
:
1279 return RADV_DYNAMIC_VIEWPORT
;
1280 case VK_DYNAMIC_STATE_SCISSOR
:
1281 return RADV_DYNAMIC_SCISSOR
;
1282 case VK_DYNAMIC_STATE_LINE_WIDTH
:
1283 return RADV_DYNAMIC_LINE_WIDTH
;
1284 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
1285 return RADV_DYNAMIC_DEPTH_BIAS
;
1286 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
1287 return RADV_DYNAMIC_BLEND_CONSTANTS
;
1288 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
1289 return RADV_DYNAMIC_DEPTH_BOUNDS
;
1290 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
1291 return RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
1292 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
1293 return RADV_DYNAMIC_STENCIL_WRITE_MASK
;
1294 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
1295 return RADV_DYNAMIC_STENCIL_REFERENCE
;
1296 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT
:
1297 return RADV_DYNAMIC_DISCARD_RECTANGLE
;
1298 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT
:
1299 return RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1301 unreachable("Unhandled dynamic state");
1305 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1307 uint32_t states
= RADV_DYNAMIC_ALL
;
1309 /* If rasterization is disabled we do not care about any of the dynamic states,
1310 * since they are all rasterization related only. */
1311 if (pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
1314 if (!pCreateInfo
->pRasterizationState
->depthBiasEnable
)
1315 states
&= ~RADV_DYNAMIC_DEPTH_BIAS
;
1317 if (!pCreateInfo
->pDepthStencilState
||
1318 !pCreateInfo
->pDepthStencilState
->depthBoundsTestEnable
)
1319 states
&= ~RADV_DYNAMIC_DEPTH_BOUNDS
;
1321 if (!pCreateInfo
->pDepthStencilState
||
1322 !pCreateInfo
->pDepthStencilState
->stencilTestEnable
)
1323 states
&= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK
|
1324 RADV_DYNAMIC_STENCIL_WRITE_MASK
|
1325 RADV_DYNAMIC_STENCIL_REFERENCE
);
1327 if (!vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
))
1328 states
&= ~RADV_DYNAMIC_DISCARD_RECTANGLE
;
1330 if (!pCreateInfo
->pMultisampleState
||
1331 !vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1332 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
))
1333 states
&= ~RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1335 /* TODO: blend constants & line width. */
1342 radv_pipeline_init_dynamic_state(struct radv_pipeline
*pipeline
,
1343 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1345 uint32_t needed_states
= radv_pipeline_needed_dynamic_state(pCreateInfo
);
1346 uint32_t states
= needed_states
;
1347 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1348 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1350 pipeline
->dynamic_state
= default_dynamic_state
;
1351 pipeline
->graphics
.needed_dynamic_state
= needed_states
;
1353 if (pCreateInfo
->pDynamicState
) {
1354 /* Remove all of the states that are marked as dynamic */
1355 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1356 for (uint32_t s
= 0; s
< count
; s
++)
1357 states
&= ~radv_dynamic_state_mask(pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1360 struct radv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1362 if (needed_states
& RADV_DYNAMIC_VIEWPORT
) {
1363 assert(pCreateInfo
->pViewportState
);
1365 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1366 if (states
& RADV_DYNAMIC_VIEWPORT
) {
1367 typed_memcpy(dynamic
->viewport
.viewports
,
1368 pCreateInfo
->pViewportState
->pViewports
,
1369 pCreateInfo
->pViewportState
->viewportCount
);
1373 if (needed_states
& RADV_DYNAMIC_SCISSOR
) {
1374 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1375 if (states
& RADV_DYNAMIC_SCISSOR
) {
1376 typed_memcpy(dynamic
->scissor
.scissors
,
1377 pCreateInfo
->pViewportState
->pScissors
,
1378 pCreateInfo
->pViewportState
->scissorCount
);
1382 if (states
& RADV_DYNAMIC_LINE_WIDTH
) {
1383 assert(pCreateInfo
->pRasterizationState
);
1384 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1387 if (states
& RADV_DYNAMIC_DEPTH_BIAS
) {
1388 assert(pCreateInfo
->pRasterizationState
);
1389 dynamic
->depth_bias
.bias
=
1390 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1391 dynamic
->depth_bias
.clamp
=
1392 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1393 dynamic
->depth_bias
.slope
=
1394 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1397 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1399 * pColorBlendState is [...] NULL if the pipeline has rasterization
1400 * disabled or if the subpass of the render pass the pipeline is
1401 * created against does not use any color attachments.
1403 if (subpass
->has_color_att
&& states
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
1404 assert(pCreateInfo
->pColorBlendState
);
1405 typed_memcpy(dynamic
->blend_constants
,
1406 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1409 /* If there is no depthstencil attachment, then don't read
1410 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1411 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1412 * no need to override the depthstencil defaults in
1413 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1415 * Section 9.2 of the Vulkan 1.0.15 spec says:
1417 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1418 * disabled or if the subpass of the render pass the pipeline is created
1419 * against does not use a depth/stencil attachment.
1421 if (needed_states
&& subpass
->depth_stencil_attachment
) {
1422 assert(pCreateInfo
->pDepthStencilState
);
1424 if (states
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
1425 dynamic
->depth_bounds
.min
=
1426 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1427 dynamic
->depth_bounds
.max
=
1428 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1431 if (states
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
1432 dynamic
->stencil_compare_mask
.front
=
1433 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1434 dynamic
->stencil_compare_mask
.back
=
1435 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1438 if (states
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
1439 dynamic
->stencil_write_mask
.front
=
1440 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1441 dynamic
->stencil_write_mask
.back
=
1442 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1445 if (states
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
1446 dynamic
->stencil_reference
.front
=
1447 pCreateInfo
->pDepthStencilState
->front
.reference
;
1448 dynamic
->stencil_reference
.back
=
1449 pCreateInfo
->pDepthStencilState
->back
.reference
;
1453 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
1454 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
1455 if (needed_states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1456 dynamic
->discard_rectangle
.count
= discard_rectangle_info
->discardRectangleCount
;
1457 if (states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1458 typed_memcpy(dynamic
->discard_rectangle
.rectangles
,
1459 discard_rectangle_info
->pDiscardRectangles
,
1460 discard_rectangle_info
->discardRectangleCount
);
1464 if (needed_states
& RADV_DYNAMIC_SAMPLE_LOCATIONS
) {
1465 const VkPipelineSampleLocationsStateCreateInfoEXT
*sample_location_info
=
1466 vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1467 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
);
1468 /* If sampleLocationsEnable is VK_FALSE, the default sample
1469 * locations are used and the values specified in
1470 * sampleLocationsInfo are ignored.
1472 if (sample_location_info
->sampleLocationsEnable
) {
1473 const VkSampleLocationsInfoEXT
*pSampleLocationsInfo
=
1474 &sample_location_info
->sampleLocationsInfo
;
1476 assert(pSampleLocationsInfo
->sampleLocationsCount
<= MAX_SAMPLE_LOCATIONS
);
1478 dynamic
->sample_location
.per_pixel
= pSampleLocationsInfo
->sampleLocationsPerPixel
;
1479 dynamic
->sample_location
.grid_size
= pSampleLocationsInfo
->sampleLocationGridSize
;
1480 dynamic
->sample_location
.count
= pSampleLocationsInfo
->sampleLocationsCount
;
1481 typed_memcpy(&dynamic
->sample_location
.locations
[0],
1482 pSampleLocationsInfo
->pSampleLocations
,
1483 pSampleLocationsInfo
->sampleLocationsCount
);
1487 pipeline
->dynamic_state
.mask
= states
;
1491 gfx9_get_gs_info(const struct radv_pipeline_key
*key
,
1492 const struct radv_pipeline
*pipeline
,
1494 struct radv_shader_info
*infos
,
1495 struct gfx9_gs_info
*out
)
1497 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1498 struct radv_es_output_info
*es_info
;
1499 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1500 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1502 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ?
1503 &infos
[MESA_SHADER_TESS_EVAL
].tes
.es_info
:
1504 &infos
[MESA_SHADER_VERTEX
].vs
.es_info
;
1506 unsigned gs_num_invocations
= MAX2(gs_info
->gs
.invocations
, 1);
1507 bool uses_adjacency
;
1508 switch(key
->topology
) {
1509 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1510 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1511 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1512 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1513 uses_adjacency
= true;
1516 uses_adjacency
= false;
1520 /* All these are in dwords: */
1521 /* We can't allow using the whole LDS, because GS waves compete with
1522 * other shader stages for LDS space. */
1523 const unsigned max_lds_size
= 8 * 1024;
1524 const unsigned esgs_itemsize
= es_info
->esgs_itemsize
/ 4;
1525 unsigned esgs_lds_size
;
1527 /* All these are per subgroup: */
1528 const unsigned max_out_prims
= 32 * 1024;
1529 const unsigned max_es_verts
= 255;
1530 const unsigned ideal_gs_prims
= 64;
1531 unsigned max_gs_prims
, gs_prims
;
1532 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
1534 if (uses_adjacency
|| gs_num_invocations
> 1)
1535 max_gs_prims
= 127 / gs_num_invocations
;
1539 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1540 * Make sure we don't go over the maximum value.
1542 if (gs_info
->gs
.vertices_out
> 0) {
1543 max_gs_prims
= MIN2(max_gs_prims
,
1545 (gs_info
->gs
.vertices_out
* gs_num_invocations
));
1547 assert(max_gs_prims
> 0);
1549 /* If the primitive has adjacency, halve the number of vertices
1550 * that will be reused in multiple primitives.
1552 min_es_verts
= gs_info
->gs
.vertices_in
/ (uses_adjacency
? 2 : 1);
1554 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
1555 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
1557 /* Compute ESGS LDS size based on the worst case number of ES vertices
1558 * needed to create the target number of GS prims per subgroup.
1560 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1562 /* If total LDS usage is too big, refactor partitions based on ratio
1563 * of ESGS item sizes.
1565 if (esgs_lds_size
> max_lds_size
) {
1566 /* Our target GS Prims Per Subgroup was too large. Calculate
1567 * the maximum number of GS Prims Per Subgroup that will fit
1568 * into LDS, capped by the maximum that the hardware can support.
1570 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
1572 assert(gs_prims
> 0);
1573 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
1576 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1577 assert(esgs_lds_size
<= max_lds_size
);
1580 /* Now calculate remaining ESGS information. */
1582 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
1584 es_verts
= max_es_verts
;
1586 /* Vertices for adjacency primitives are not always reused, so restore
1587 * it for ES_VERTS_PER_SUBGRP.
1589 min_es_verts
= gs_info
->gs
.vertices_in
;
1591 /* For normal primitives, the VGT only checks if they are past the ES
1592 * verts per subgroup after allocating a full GS primitive and if they
1593 * are, kick off a new subgroup. But if those additional ES verts are
1594 * unique (e.g. not reused) we need to make sure there is enough LDS
1595 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1597 es_verts
-= min_es_verts
- 1;
1599 uint32_t es_verts_per_subgroup
= es_verts
;
1600 uint32_t gs_prims_per_subgroup
= gs_prims
;
1601 uint32_t gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
1602 uint32_t max_prims_per_subgroup
= gs_inst_prims_in_subgroup
* gs_info
->gs
.vertices_out
;
1603 out
->lds_size
= align(esgs_lds_size
, 128) / 128;
1604 out
->vgt_gs_onchip_cntl
= S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup
) |
1605 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup
) |
1606 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup
);
1607 out
->vgt_gs_max_prims_per_subgroup
= S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup
);
1608 out
->vgt_esgs_ring_itemsize
= esgs_itemsize
;
1609 assert(max_prims_per_subgroup
<= max_out_prims
);
1612 static void clamp_gsprims_to_esverts(unsigned *max_gsprims
, unsigned max_esverts
,
1613 unsigned min_verts_per_prim
, bool use_adjacency
)
1615 unsigned max_reuse
= max_esverts
- min_verts_per_prim
;
1618 *max_gsprims
= MIN2(*max_gsprims
, 1 + max_reuse
);
1622 radv_get_num_input_vertices(nir_shader
**nir
)
1624 if (nir
[MESA_SHADER_GEOMETRY
]) {
1625 nir_shader
*gs
= nir
[MESA_SHADER_GEOMETRY
];
1627 return gs
->info
.gs
.vertices_in
;
1630 if (nir
[MESA_SHADER_TESS_CTRL
]) {
1631 nir_shader
*tes
= nir
[MESA_SHADER_TESS_EVAL
];
1633 if (tes
->info
.tess
.point_mode
)
1635 if (tes
->info
.tess
.primitive_mode
== GL_ISOLINES
)
1644 gfx10_get_ngg_info(const struct radv_pipeline_key
*key
,
1645 struct radv_pipeline
*pipeline
,
1647 struct radv_shader_info
*infos
,
1648 struct gfx10_ngg_info
*ngg
)
1650 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1651 struct radv_es_output_info
*es_info
=
1652 nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1653 unsigned gs_type
= nir
[MESA_SHADER_GEOMETRY
] ? MESA_SHADER_GEOMETRY
: MESA_SHADER_VERTEX
;
1654 unsigned max_verts_per_prim
= radv_get_num_input_vertices(nir
);
1655 unsigned min_verts_per_prim
=
1656 gs_type
== MESA_SHADER_GEOMETRY
? max_verts_per_prim
: 1;
1657 unsigned gs_num_invocations
= nir
[MESA_SHADER_GEOMETRY
] ? MAX2(gs_info
->gs
.invocations
, 1) : 1;
1658 bool uses_adjacency
;
1659 switch(key
->topology
) {
1660 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1661 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1662 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1663 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1664 uses_adjacency
= true;
1667 uses_adjacency
= false;
1671 /* All these are in dwords: */
1672 /* We can't allow using the whole LDS, because GS waves compete with
1673 * other shader stages for LDS space.
1675 * TODO: We should really take the shader's internal LDS use into
1676 * account. The linker will fail if the size is greater than
1679 const unsigned max_lds_size
= 8 * 1024 - 768;
1680 const unsigned target_lds_size
= max_lds_size
;
1681 unsigned esvert_lds_size
= 0;
1682 unsigned gsprim_lds_size
= 0;
1684 /* All these are per subgroup: */
1685 bool max_vert_out_per_gs_instance
= false;
1686 unsigned max_esverts_base
= 256;
1687 unsigned max_gsprims_base
= 128; /* default prim group size clamp */
1689 /* Hardware has the following non-natural restrictions on the value
1690 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1692 * - at most 252 for any line input primitive type
1693 * - at most 251 for any quad input primitive type
1694 * - at most 251 for triangle strips with adjacency (this happens to
1695 * be the natural limit for triangle *lists* with adjacency)
1697 max_esverts_base
= MIN2(max_esverts_base
, 251 + max_verts_per_prim
- 1);
1699 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1700 unsigned max_out_verts_per_gsprim
=
1701 gs_info
->gs
.vertices_out
* gs_num_invocations
;
1703 if (max_out_verts_per_gsprim
<= 256) {
1704 if (max_out_verts_per_gsprim
) {
1705 max_gsprims_base
= MIN2(max_gsprims_base
,
1706 256 / max_out_verts_per_gsprim
);
1709 /* Use special multi-cycling mode in which each GS
1710 * instance gets its own subgroup. Does not work with
1712 max_vert_out_per_gs_instance
= true;
1713 max_gsprims_base
= 1;
1714 max_out_verts_per_gsprim
= gs_info
->gs
.vertices_out
;
1717 esvert_lds_size
= es_info
->esgs_itemsize
/ 4;
1718 gsprim_lds_size
= (gs_info
->gs
.gsvs_vertex_size
/ 4 + 1) * max_out_verts_per_gsprim
;
1721 /* LDS size for passing data from GS to ES. */
1722 struct radv_streamout_info
*so_info
= nir
[MESA_SHADER_TESS_CTRL
]
1723 ? &infos
[MESA_SHADER_TESS_EVAL
].so
1724 : &infos
[MESA_SHADER_VERTEX
].so
;
1726 if (so_info
->num_outputs
)
1727 esvert_lds_size
= 4 * so_info
->num_outputs
+ 1;
1729 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1730 * corresponding to the ES thread of the provoking vertex. All
1731 * ES threads load and export PrimitiveID for their thread.
1733 if (!nir
[MESA_SHADER_TESS_CTRL
] &&
1734 infos
[MESA_SHADER_VERTEX
].vs
.outinfo
.export_prim_id
)
1735 esvert_lds_size
= MAX2(esvert_lds_size
, 1);
1738 unsigned max_gsprims
= max_gsprims_base
;
1739 unsigned max_esverts
= max_esverts_base
;
1741 if (esvert_lds_size
)
1742 max_esverts
= MIN2(max_esverts
, target_lds_size
/ esvert_lds_size
);
1743 if (gsprim_lds_size
)
1744 max_gsprims
= MIN2(max_gsprims
, target_lds_size
/ gsprim_lds_size
);
1746 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1747 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
, min_verts_per_prim
, uses_adjacency
);
1748 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1750 if (esvert_lds_size
|| gsprim_lds_size
) {
1751 /* Now that we have a rough proportionality between esverts
1752 * and gsprims based on the primitive type, scale both of them
1753 * down simultaneously based on required LDS space.
1755 * We could be smarter about this if we knew how much vertex
1758 unsigned lds_total
= max_esverts
* esvert_lds_size
+
1759 max_gsprims
* gsprim_lds_size
;
1760 if (lds_total
> target_lds_size
) {
1761 max_esverts
= max_esverts
* target_lds_size
/ lds_total
;
1762 max_gsprims
= max_gsprims
* target_lds_size
/ lds_total
;
1764 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1765 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1766 min_verts_per_prim
, uses_adjacency
);
1767 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1771 /* Round up towards full wave sizes for better ALU utilization. */
1772 if (!max_vert_out_per_gs_instance
) {
1773 unsigned orig_max_esverts
;
1774 unsigned orig_max_gsprims
;
1777 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1778 wavesize
= gs_info
->wave_size
;
1780 wavesize
= nir
[MESA_SHADER_TESS_CTRL
]
1781 ? infos
[MESA_SHADER_TESS_EVAL
].wave_size
1782 : infos
[MESA_SHADER_VERTEX
].wave_size
;
1786 orig_max_esverts
= max_esverts
;
1787 orig_max_gsprims
= max_gsprims
;
1789 max_esverts
= align(max_esverts
, wavesize
);
1790 max_esverts
= MIN2(max_esverts
, max_esverts_base
);
1791 if (esvert_lds_size
)
1792 max_esverts
= MIN2(max_esverts
,
1793 (max_lds_size
- max_gsprims
* gsprim_lds_size
) /
1795 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1797 max_gsprims
= align(max_gsprims
, wavesize
);
1798 max_gsprims
= MIN2(max_gsprims
, max_gsprims_base
);
1799 if (gsprim_lds_size
)
1800 max_gsprims
= MIN2(max_gsprims
,
1801 (max_lds_size
- max_esverts
* esvert_lds_size
) /
1803 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1804 min_verts_per_prim
, uses_adjacency
);
1805 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1806 } while (orig_max_esverts
!= max_esverts
|| orig_max_gsprims
!= max_gsprims
);
1809 /* Hardware restriction: minimum value of max_esverts */
1810 max_esverts
= MAX2(max_esverts
, 23 + max_verts_per_prim
);
1812 unsigned max_out_vertices
=
1813 max_vert_out_per_gs_instance
? gs_info
->gs
.vertices_out
:
1814 gs_type
== MESA_SHADER_GEOMETRY
?
1815 max_gsprims
* gs_num_invocations
* gs_info
->gs
.vertices_out
:
1817 assert(max_out_vertices
<= 256);
1819 unsigned prim_amp_factor
= 1;
1820 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1821 /* Number of output primitives per GS input primitive after
1823 prim_amp_factor
= gs_info
->gs
.vertices_out
;
1826 /* The GE only checks against the maximum number of ES verts after
1827 * allocating a full GS primitive. So we need to ensure that whenever
1828 * this check passes, there is enough space for a full primitive without
1831 ngg
->hw_max_esverts
= max_esverts
- max_verts_per_prim
+ 1;
1832 ngg
->max_gsprims
= max_gsprims
;
1833 ngg
->max_out_verts
= max_out_vertices
;
1834 ngg
->prim_amp_factor
= prim_amp_factor
;
1835 ngg
->max_vert_out_per_gs_instance
= max_vert_out_per_gs_instance
;
1836 ngg
->ngg_emit_size
= max_gsprims
* gsprim_lds_size
;
1837 ngg
->esgs_ring_size
= 4 * max_esverts
* esvert_lds_size
;
1839 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1840 ngg
->vgt_esgs_ring_itemsize
= es_info
->esgs_itemsize
/ 4;
1842 ngg
->vgt_esgs_ring_itemsize
= 1;
1845 pipeline
->graphics
.esgs_ring_size
= ngg
->esgs_ring_size
;
1847 assert(ngg
->hw_max_esverts
>= 24); /* HW limitation */
1851 calculate_gs_ring_sizes(struct radv_pipeline
*pipeline
,
1852 const struct gfx9_gs_info
*gs
)
1854 struct radv_device
*device
= pipeline
->device
;
1855 unsigned num_se
= device
->physical_device
->rad_info
.max_se
;
1856 unsigned wave_size
= 64;
1857 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
1858 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1859 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1861 unsigned gs_vertex_reuse
=
1862 (device
->physical_device
->rad_info
.chip_class
>= GFX8
? 32 : 16) * num_se
;
1863 unsigned alignment
= 256 * num_se
;
1864 /* The maximum size is 63.999 MB per SE. */
1865 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
1866 struct radv_shader_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
1868 /* Calculate the minimum size. */
1869 unsigned min_esgs_ring_size
= align(gs
->vgt_esgs_ring_itemsize
* 4 * gs_vertex_reuse
*
1870 wave_size
, alignment
);
1871 /* These are recommended sizes, not minimum sizes. */
1872 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
1873 gs
->vgt_esgs_ring_itemsize
* 4 * gs_info
->gs
.vertices_in
;
1874 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
1875 gs_info
->gs
.max_gsvs_emit_size
;
1877 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
1878 esgs_ring_size
= align(esgs_ring_size
, alignment
);
1879 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
1881 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
1882 pipeline
->graphics
.esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
1884 pipeline
->graphics
.gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
1887 static void si_multiwave_lds_size_workaround(struct radv_device
*device
,
1890 /* If tessellation is all offchip and on-chip GS isn't used, this
1891 * workaround is not needed.
1895 /* SPI barrier management bug:
1896 * Make sure we have at least 4k of LDS in use to avoid the bug.
1897 * It applies to workgroup sizes of more than one wavefront.
1899 if (device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
||
1900 device
->physical_device
->rad_info
.family
== CHIP_KABINI
)
1901 *lds_size
= MAX2(*lds_size
, 8);
1904 struct radv_shader_variant
*
1905 radv_get_shader(struct radv_pipeline
*pipeline
,
1906 gl_shader_stage stage
)
1908 if (stage
== MESA_SHADER_VERTEX
) {
1909 if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
1910 return pipeline
->shaders
[MESA_SHADER_VERTEX
];
1911 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
])
1912 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
1913 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1914 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1915 } else if (stage
== MESA_SHADER_TESS_EVAL
) {
1916 if (!radv_pipeline_has_tess(pipeline
))
1918 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
1919 return pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
1920 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1921 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1923 return pipeline
->shaders
[stage
];
1926 static struct radv_tessellation_state
1927 calculate_tess_state(struct radv_pipeline
*pipeline
,
1928 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1930 unsigned num_tcs_input_cp
;
1931 unsigned num_tcs_output_cp
;
1933 unsigned num_patches
;
1934 struct radv_tessellation_state tess
= {0};
1936 num_tcs_input_cp
= pCreateInfo
->pTessellationState
->patchControlPoints
;
1937 num_tcs_output_cp
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.tcs_vertices_out
; //TCS VERTICES OUT
1938 num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
1940 lds_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.lds_size
;
1942 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
1943 assert(lds_size
<= 65536);
1944 lds_size
= align(lds_size
, 512) / 512;
1946 assert(lds_size
<= 32768);
1947 lds_size
= align(lds_size
, 256) / 256;
1949 si_multiwave_lds_size_workaround(pipeline
->device
, &lds_size
);
1951 tess
.lds_size
= lds_size
;
1953 tess
.ls_hs_config
= S_028B58_NUM_PATCHES(num_patches
) |
1954 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
1955 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
1956 tess
.num_patches
= num_patches
;
1958 struct radv_shader_variant
*tes
= radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
);
1959 unsigned type
= 0, partitioning
= 0, topology
= 0, distribution_mode
= 0;
1961 switch (tes
->info
.tes
.primitive_mode
) {
1963 type
= V_028B6C_TESS_TRIANGLE
;
1966 type
= V_028B6C_TESS_QUAD
;
1969 type
= V_028B6C_TESS_ISOLINE
;
1973 switch (tes
->info
.tes
.spacing
) {
1974 case TESS_SPACING_EQUAL
:
1975 partitioning
= V_028B6C_PART_INTEGER
;
1977 case TESS_SPACING_FRACTIONAL_ODD
:
1978 partitioning
= V_028B6C_PART_FRAC_ODD
;
1980 case TESS_SPACING_FRACTIONAL_EVEN
:
1981 partitioning
= V_028B6C_PART_FRAC_EVEN
;
1987 bool ccw
= tes
->info
.tes
.ccw
;
1988 const VkPipelineTessellationDomainOriginStateCreateInfo
*domain_origin_state
=
1989 vk_find_struct_const(pCreateInfo
->pTessellationState
,
1990 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO
);
1992 if (domain_origin_state
&& domain_origin_state
->domainOrigin
!= VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT
)
1995 if (tes
->info
.tes
.point_mode
)
1996 topology
= V_028B6C_OUTPUT_POINT
;
1997 else if (tes
->info
.tes
.primitive_mode
== GL_ISOLINES
)
1998 topology
= V_028B6C_OUTPUT_LINE
;
2000 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
2002 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
2004 if (pipeline
->device
->physical_device
->rad_info
.has_distributed_tess
) {
2005 if (pipeline
->device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
2006 pipeline
->device
->physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
2007 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
2009 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
2011 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
2013 tess
.tf_param
= S_028B6C_TYPE(type
) |
2014 S_028B6C_PARTITIONING(partitioning
) |
2015 S_028B6C_TOPOLOGY(topology
) |
2016 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
2021 static const struct radv_prim_vertex_count prim_size_table
[] = {
2022 [V_008958_DI_PT_NONE
] = {0, 0},
2023 [V_008958_DI_PT_POINTLIST
] = {1, 1},
2024 [V_008958_DI_PT_LINELIST
] = {2, 2},
2025 [V_008958_DI_PT_LINESTRIP
] = {2, 1},
2026 [V_008958_DI_PT_TRILIST
] = {3, 3},
2027 [V_008958_DI_PT_TRIFAN
] = {3, 1},
2028 [V_008958_DI_PT_TRISTRIP
] = {3, 1},
2029 [V_008958_DI_PT_LINELIST_ADJ
] = {4, 4},
2030 [V_008958_DI_PT_LINESTRIP_ADJ
] = {4, 1},
2031 [V_008958_DI_PT_TRILIST_ADJ
] = {6, 6},
2032 [V_008958_DI_PT_TRISTRIP_ADJ
] = {6, 2},
2033 [V_008958_DI_PT_RECTLIST
] = {3, 3},
2034 [V_008958_DI_PT_LINELOOP
] = {2, 1},
2035 [V_008958_DI_PT_POLYGON
] = {3, 1},
2036 [V_008958_DI_PT_2D_TRI_STRIP
] = {0, 0},
2039 static const struct radv_vs_output_info
*get_vs_output_info(const struct radv_pipeline
*pipeline
)
2041 if (radv_pipeline_has_gs(pipeline
))
2042 if (radv_pipeline_has_ngg(pipeline
))
2043 return &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.vs
.outinfo
;
2045 return &pipeline
->gs_copy_shader
->info
.vs
.outinfo
;
2046 else if (radv_pipeline_has_tess(pipeline
))
2047 return &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.outinfo
;
2049 return &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.outinfo
;
2053 radv_link_shaders(struct radv_pipeline
*pipeline
, nir_shader
**shaders
)
2055 nir_shader
* ordered_shaders
[MESA_SHADER_STAGES
];
2056 int shader_count
= 0;
2058 if(shaders
[MESA_SHADER_FRAGMENT
]) {
2059 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_FRAGMENT
];
2061 if(shaders
[MESA_SHADER_GEOMETRY
]) {
2062 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_GEOMETRY
];
2064 if(shaders
[MESA_SHADER_TESS_EVAL
]) {
2065 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_EVAL
];
2067 if(shaders
[MESA_SHADER_TESS_CTRL
]) {
2068 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_CTRL
];
2070 if(shaders
[MESA_SHADER_VERTEX
]) {
2071 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_VERTEX
];
2074 if (shader_count
> 1) {
2075 unsigned first
= ordered_shaders
[shader_count
- 1]->info
.stage
;
2076 unsigned last
= ordered_shaders
[0]->info
.stage
;
2078 if (ordered_shaders
[0]->info
.stage
== MESA_SHADER_FRAGMENT
&&
2079 ordered_shaders
[1]->info
.has_transform_feedback_varyings
)
2080 nir_link_xfb_varyings(ordered_shaders
[1], ordered_shaders
[0]);
2082 for (int i
= 0; i
< shader_count
; ++i
) {
2083 nir_variable_mode mask
= 0;
2085 if (ordered_shaders
[i
]->info
.stage
!= first
)
2086 mask
= mask
| nir_var_shader_in
;
2088 if (ordered_shaders
[i
]->info
.stage
!= last
)
2089 mask
= mask
| nir_var_shader_out
;
2091 nir_lower_io_to_scalar_early(ordered_shaders
[i
], mask
);
2092 radv_optimize_nir(ordered_shaders
[i
], false, false);
2096 for (int i
= 1; i
< shader_count
; ++i
) {
2097 nir_lower_io_arrays_to_elements(ordered_shaders
[i
],
2098 ordered_shaders
[i
- 1]);
2100 if (nir_link_opt_varyings(ordered_shaders
[i
],
2101 ordered_shaders
[i
- 1]))
2102 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2104 nir_remove_dead_variables(ordered_shaders
[i
],
2105 nir_var_shader_out
);
2106 nir_remove_dead_variables(ordered_shaders
[i
- 1],
2109 bool progress
= nir_remove_unused_varyings(ordered_shaders
[i
],
2110 ordered_shaders
[i
- 1]);
2112 nir_compact_varyings(ordered_shaders
[i
],
2113 ordered_shaders
[i
- 1], true);
2116 if (nir_lower_global_vars_to_local(ordered_shaders
[i
])) {
2117 ac_lower_indirect_derefs(ordered_shaders
[i
],
2118 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2120 radv_optimize_nir(ordered_shaders
[i
], false, false);
2122 if (nir_lower_global_vars_to_local(ordered_shaders
[i
- 1])) {
2123 ac_lower_indirect_derefs(ordered_shaders
[i
- 1],
2124 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2126 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2132 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo
*input_state
,
2133 uint32_t attrib_binding
)
2135 for (uint32_t i
= 0; i
< input_state
->vertexBindingDescriptionCount
; i
++) {
2136 const VkVertexInputBindingDescription
*input_binding
=
2137 &input_state
->pVertexBindingDescriptions
[i
];
2139 if (input_binding
->binding
== attrib_binding
)
2140 return input_binding
->stride
;
2146 static struct radv_pipeline_key
2147 radv_generate_graphics_pipeline_key(struct radv_pipeline
*pipeline
,
2148 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2149 const struct radv_blend_state
*blend
,
2150 bool has_view_index
)
2152 const VkPipelineVertexInputStateCreateInfo
*input_state
=
2153 pCreateInfo
->pVertexInputState
;
2154 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*divisor_state
=
2155 vk_find_struct_const(input_state
->pNext
, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
2157 struct radv_pipeline_key key
;
2158 memset(&key
, 0, sizeof(key
));
2160 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
2161 key
.optimisations_disabled
= 1;
2163 key
.has_multiview_view_index
= has_view_index
;
2165 uint32_t binding_input_rate
= 0;
2166 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
2167 for (unsigned i
= 0; i
< input_state
->vertexBindingDescriptionCount
; ++i
) {
2168 if (input_state
->pVertexBindingDescriptions
[i
].inputRate
) {
2169 unsigned binding
= input_state
->pVertexBindingDescriptions
[i
].binding
;
2170 binding_input_rate
|= 1u << binding
;
2171 instance_rate_divisors
[binding
] = 1;
2174 if (divisor_state
) {
2175 for (unsigned i
= 0; i
< divisor_state
->vertexBindingDivisorCount
; ++i
) {
2176 instance_rate_divisors
[divisor_state
->pVertexBindingDivisors
[i
].binding
] =
2177 divisor_state
->pVertexBindingDivisors
[i
].divisor
;
2181 for (unsigned i
= 0; i
< input_state
->vertexAttributeDescriptionCount
; ++i
) {
2182 const VkVertexInputAttributeDescription
*desc
=
2183 &input_state
->pVertexAttributeDescriptions
[i
];
2184 const struct vk_format_description
*format_desc
;
2185 unsigned location
= desc
->location
;
2186 unsigned binding
= desc
->binding
;
2187 unsigned num_format
, data_format
;
2190 if (binding_input_rate
& (1u << binding
)) {
2191 key
.instance_rate_inputs
|= 1u << location
;
2192 key
.instance_rate_divisors
[location
] = instance_rate_divisors
[binding
];
2195 format_desc
= vk_format_description(desc
->format
);
2196 first_non_void
= vk_format_get_first_non_void_channel(desc
->format
);
2198 num_format
= radv_translate_buffer_numformat(format_desc
, first_non_void
);
2199 data_format
= radv_translate_buffer_dataformat(format_desc
, first_non_void
);
2201 key
.vertex_attribute_formats
[location
] = data_format
| (num_format
<< 4);
2202 key
.vertex_attribute_bindings
[location
] = desc
->binding
;
2203 key
.vertex_attribute_offsets
[location
] = desc
->offset
;
2204 key
.vertex_attribute_strides
[location
] = radv_get_attrib_stride(input_state
, desc
->binding
);
2206 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
&&
2207 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_STONEY
) {
2208 VkFormat format
= input_state
->pVertexAttributeDescriptions
[i
].format
;
2211 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2212 case VK_FORMAT_A2B10G10R10_SNORM_PACK32
:
2213 adjust
= RADV_ALPHA_ADJUST_SNORM
;
2215 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2216 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32
:
2217 adjust
= RADV_ALPHA_ADJUST_SSCALED
;
2219 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2220 case VK_FORMAT_A2B10G10R10_SINT_PACK32
:
2221 adjust
= RADV_ALPHA_ADJUST_SINT
;
2227 key
.vertex_alpha_adjust
|= adjust
<< (2 * location
);
2230 switch (desc
->format
) {
2231 case VK_FORMAT_B8G8R8A8_UNORM
:
2232 case VK_FORMAT_B8G8R8A8_SNORM
:
2233 case VK_FORMAT_B8G8R8A8_USCALED
:
2234 case VK_FORMAT_B8G8R8A8_SSCALED
:
2235 case VK_FORMAT_B8G8R8A8_UINT
:
2236 case VK_FORMAT_B8G8R8A8_SINT
:
2237 case VK_FORMAT_B8G8R8A8_SRGB
:
2238 case VK_FORMAT_A2R10G10B10_UNORM_PACK32
:
2239 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2240 case VK_FORMAT_A2R10G10B10_USCALED_PACK32
:
2241 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2242 case VK_FORMAT_A2R10G10B10_UINT_PACK32
:
2243 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2244 key
.vertex_post_shuffle
|= 1 << location
;
2251 if (pCreateInfo
->pTessellationState
)
2252 key
.tess_input_vertices
= pCreateInfo
->pTessellationState
->patchControlPoints
;
2255 if (pCreateInfo
->pMultisampleState
&&
2256 pCreateInfo
->pMultisampleState
->rasterizationSamples
> 1) {
2257 uint32_t num_samples
= pCreateInfo
->pMultisampleState
->rasterizationSamples
;
2258 uint32_t ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
->pMultisampleState
);
2259 key
.num_samples
= num_samples
;
2260 key
.log2_ps_iter_samples
= util_logbase2(ps_iter_samples
);
2263 key
.col_format
= blend
->spi_shader_col_format
;
2264 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX8
)
2265 radv_pipeline_compute_get_int_clamp(pCreateInfo
, &key
.is_int8
, &key
.is_int10
);
2267 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
2268 key
.topology
= pCreateInfo
->pInputAssemblyState
->topology
;
2274 radv_nir_stage_uses_xfb(const nir_shader
*nir
)
2276 nir_xfb_info
*xfb
= nir_gather_xfb_info(nir
, NULL
);
2277 bool uses_xfb
= !!xfb
;
2284 radv_fill_shader_keys(struct radv_device
*device
,
2285 struct radv_shader_variant_key
*keys
,
2286 const struct radv_pipeline_key
*key
,
2289 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_inputs
= key
->instance_rate_inputs
;
2290 keys
[MESA_SHADER_VERTEX
].vs
.alpha_adjust
= key
->vertex_alpha_adjust
;
2291 keys
[MESA_SHADER_VERTEX
].vs
.post_shuffle
= key
->vertex_post_shuffle
;
2292 for (unsigned i
= 0; i
< MAX_VERTEX_ATTRIBS
; ++i
) {
2293 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_divisors
[i
] = key
->instance_rate_divisors
[i
];
2294 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_formats
[i
] = key
->vertex_attribute_formats
[i
];
2295 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_bindings
[i
] = key
->vertex_attribute_bindings
[i
];
2296 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_offsets
[i
] = key
->vertex_attribute_offsets
[i
];
2297 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_strides
[i
] = key
->vertex_attribute_strides
[i
];
2299 keys
[MESA_SHADER_VERTEX
].vs
.outprim
= si_conv_prim_to_gs_out(key
->topology
);
2301 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2302 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ls
= true;
2303 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= 0;
2304 keys
[MESA_SHADER_TESS_CTRL
].tcs
.input_vertices
= key
->tess_input_vertices
;
2305 keys
[MESA_SHADER_TESS_CTRL
].tcs
.primitive_mode
= nir
[MESA_SHADER_TESS_EVAL
]->info
.tess
.primitive_mode
;
2307 keys
[MESA_SHADER_TESS_CTRL
].tcs
.tes_reads_tess_factors
= !!(nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
& (VARYING_BIT_TESS_LEVEL_INNER
| VARYING_BIT_TESS_LEVEL_OUTER
));
2310 if (nir
[MESA_SHADER_GEOMETRY
]) {
2311 if (nir
[MESA_SHADER_TESS_CTRL
])
2312 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_es
= true;
2314 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_es
= true;
2317 if (device
->physical_device
->use_ngg
) {
2318 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2319 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= true;
2321 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= true;
2324 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2325 nir
[MESA_SHADER_GEOMETRY
] &&
2326 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.invocations
*
2327 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.vertices_out
> 256) {
2328 /* Fallback to the legacy path if tessellation is
2329 * enabled with extreme geometry because
2330 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2333 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2337 * Disable NGG with geometry shaders. There are a bunch of
2339 * * GS primitives in pipeline statistic queries do not get
2340 * updates. See dEQP-VK.query_pool.statistics_query.geometry_shader_primitives
2342 * Furthermore, XGL/AMDVLK also disables this as of 9b632ef.
2344 if (nir
[MESA_SHADER_GEOMETRY
]) {
2345 if (nir
[MESA_SHADER_TESS_CTRL
])
2346 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2348 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2351 if (!device
->physical_device
->use_ngg_streamout
) {
2352 gl_shader_stage last_xfb_stage
= MESA_SHADER_VERTEX
;
2354 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2359 if (nir
[last_xfb_stage
] &&
2360 radv_nir_stage_uses_xfb(nir
[last_xfb_stage
])) {
2361 if (nir
[MESA_SHADER_TESS_CTRL
])
2362 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2364 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2369 for(int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
2370 keys
[i
].has_multiview_view_index
= key
->has_multiview_view_index
;
2372 keys
[MESA_SHADER_FRAGMENT
].fs
.col_format
= key
->col_format
;
2373 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int8
= key
->is_int8
;
2374 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int10
= key
->is_int10
;
2375 keys
[MESA_SHADER_FRAGMENT
].fs
.log2_ps_iter_samples
= key
->log2_ps_iter_samples
;
2376 keys
[MESA_SHADER_FRAGMENT
].fs
.num_samples
= key
->num_samples
;
2378 if (nir
[MESA_SHADER_COMPUTE
]) {
2379 keys
[MESA_SHADER_COMPUTE
].cs
.subgroup_size
= key
->compute_subgroup_size
;
2384 radv_get_wave_size(struct radv_device
*device
,
2385 const VkPipelineShaderStageCreateInfo
*pStage
,
2386 gl_shader_stage stage
,
2387 const struct radv_shader_variant_key
*key
)
2389 if (stage
== MESA_SHADER_GEOMETRY
&& !key
->vs_common_out
.as_ngg
)
2391 else if (stage
== MESA_SHADER_COMPUTE
) {
2392 if (key
->cs
.subgroup_size
) {
2393 /* Return the required subgroup size if specified. */
2394 return key
->cs
.subgroup_size
;
2396 return device
->physical_device
->cs_wave_size
;
2398 else if (stage
== MESA_SHADER_FRAGMENT
)
2399 return device
->physical_device
->ps_wave_size
;
2401 return device
->physical_device
->ge_wave_size
;
2405 radv_fill_shader_info(struct radv_pipeline
*pipeline
,
2406 const VkPipelineShaderStageCreateInfo
**pStages
,
2407 struct radv_shader_variant_key
*keys
,
2408 struct radv_shader_info
*infos
,
2411 unsigned active_stages
= 0;
2412 unsigned filled_stages
= 0;
2414 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2416 active_stages
|= (1 << i
);
2419 if (nir
[MESA_SHADER_FRAGMENT
]) {
2420 radv_nir_shader_info_init(&infos
[MESA_SHADER_FRAGMENT
]);
2421 radv_nir_shader_info_pass(nir
[MESA_SHADER_FRAGMENT
],
2423 &keys
[MESA_SHADER_FRAGMENT
],
2424 &infos
[MESA_SHADER_FRAGMENT
]);
2426 /* TODO: These are no longer used as keys we should refactor this */
2427 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
=
2428 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2429 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_layer_id
=
2430 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2431 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_clip_dists
=
2432 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2433 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_prim_id
=
2434 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2435 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_layer_id
=
2436 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2437 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_clip_dists
=
2438 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2440 filled_stages
|= (1 << MESA_SHADER_FRAGMENT
);
2443 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2444 nir
[MESA_SHADER_TESS_CTRL
]) {
2445 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2446 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2447 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2449 radv_nir_shader_info_init(&infos
[MESA_SHADER_TESS_CTRL
]);
2451 for (int i
= 0; i
< 2; i
++) {
2452 radv_nir_shader_info_pass(combined_nir
[i
],
2453 pipeline
->layout
, &key
,
2454 &infos
[MESA_SHADER_TESS_CTRL
]);
2457 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2458 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2459 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2460 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2462 filled_stages
|= (1 << MESA_SHADER_VERTEX
);
2463 filled_stages
|= (1 << MESA_SHADER_TESS_CTRL
);
2466 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2467 nir
[MESA_SHADER_GEOMETRY
]) {
2468 gl_shader_stage pre_stage
= nir
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2469 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2471 radv_nir_shader_info_init(&infos
[MESA_SHADER_GEOMETRY
]);
2473 for (int i
= 0; i
< 2; i
++) {
2474 radv_nir_shader_info_pass(combined_nir
[i
],
2477 &infos
[MESA_SHADER_GEOMETRY
]);
2480 filled_stages
|= (1 << pre_stage
);
2481 filled_stages
|= (1 << MESA_SHADER_GEOMETRY
);
2484 active_stages
^= filled_stages
;
2485 while (active_stages
) {
2486 int i
= u_bit_scan(&active_stages
);
2488 if (i
== MESA_SHADER_TESS_CTRL
) {
2489 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
=
2490 util_last_bit64(infos
[MESA_SHADER_VERTEX
].vs
.ls_outputs_written
);
2493 if (i
== MESA_SHADER_TESS_EVAL
) {
2494 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2495 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2496 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2497 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2500 radv_nir_shader_info_init(&infos
[i
]);
2501 radv_nir_shader_info_pass(nir
[i
], pipeline
->layout
,
2502 &keys
[i
], &infos
[i
]);
2505 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2507 infos
[i
].wave_size
=
2508 radv_get_wave_size(pipeline
->device
, pStages
[i
],
2514 merge_tess_info(struct shader_info
*tes_info
,
2515 const struct shader_info
*tcs_info
)
2517 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2519 * "PointMode. Controls generation of points rather than triangles
2520 * or lines. This functionality defaults to disabled, and is
2521 * enabled if either shader stage includes the execution mode.
2523 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2524 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2525 * and OutputVertices, it says:
2527 * "One mode must be set in at least one of the tessellation
2530 * So, the fields can be set in either the TCS or TES, but they must
2531 * agree if set in both. Our backend looks at TES, so bitwise-or in
2532 * the values from the TCS.
2534 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
2535 tes_info
->tess
.tcs_vertices_out
== 0 ||
2536 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
2537 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
2539 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2540 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2541 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
2542 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
2544 assert(tcs_info
->tess
.primitive_mode
== 0 ||
2545 tes_info
->tess
.primitive_mode
== 0 ||
2546 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
2547 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
2548 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
2549 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
2553 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT
*ext
)
2558 if (ext
->pPipelineCreationFeedback
) {
2559 ext
->pPipelineCreationFeedback
->flags
= 0;
2560 ext
->pPipelineCreationFeedback
->duration
= 0;
2563 for (unsigned i
= 0; i
< ext
->pipelineStageCreationFeedbackCount
; ++i
) {
2564 ext
->pPipelineStageCreationFeedbacks
[i
].flags
= 0;
2565 ext
->pPipelineStageCreationFeedbacks
[i
].duration
= 0;
2570 void radv_start_feedback(VkPipelineCreationFeedbackEXT
*feedback
)
2575 feedback
->duration
-= radv_get_current_time();
2576 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
2580 void radv_stop_feedback(VkPipelineCreationFeedbackEXT
*feedback
, bool cache_hit
)
2585 feedback
->duration
+= radv_get_current_time();
2586 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
|
2587 (cache_hit
? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
: 0);
2591 bool radv_aco_supported_stage(gl_shader_stage stage
, bool has_gs
, bool has_ts
)
2593 return (stage
== MESA_SHADER_VERTEX
&& !has_gs
&& !has_ts
) ||
2594 stage
== MESA_SHADER_FRAGMENT
||
2595 stage
== MESA_SHADER_COMPUTE
;
2598 void radv_create_shaders(struct radv_pipeline
*pipeline
,
2599 struct radv_device
*device
,
2600 struct radv_pipeline_cache
*cache
,
2601 const struct radv_pipeline_key
*key
,
2602 const VkPipelineShaderStageCreateInfo
**pStages
,
2603 const VkPipelineCreateFlags flags
,
2604 VkPipelineCreationFeedbackEXT
*pipeline_feedback
,
2605 VkPipelineCreationFeedbackEXT
**stage_feedbacks
)
2607 struct radv_shader_module fs_m
= {0};
2608 struct radv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
2609 nir_shader
*nir
[MESA_SHADER_STAGES
] = {0};
2610 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2611 struct radv_shader_variant_key keys
[MESA_SHADER_STAGES
] = {{{{{0}}}}};
2612 struct radv_shader_info infos
[MESA_SHADER_STAGES
] = {0};
2613 unsigned char hash
[20], gs_copy_hash
[20];
2614 bool keep_executable_info
= (flags
& VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
) || device
->keep_shader_info
;
2616 radv_start_feedback(pipeline_feedback
);
2618 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2620 modules
[i
] = radv_shader_module_from_handle(pStages
[i
]->module
);
2621 if (modules
[i
]->nir
)
2622 _mesa_sha1_compute(modules
[i
]->nir
->info
.name
,
2623 strlen(modules
[i
]->nir
->info
.name
),
2626 pipeline
->active_stages
|= mesa_to_vk_shader_stage(i
);
2630 radv_hash_shaders(hash
, pStages
, pipeline
->layout
, key
, get_hash_flags(device
));
2631 memcpy(gs_copy_hash
, hash
, 20);
2632 gs_copy_hash
[0] ^= 1;
2634 bool found_in_application_cache
= true;
2635 if (modules
[MESA_SHADER_GEOMETRY
] && !keep_executable_info
) {
2636 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2637 radv_create_shader_variants_from_pipeline_cache(device
, cache
, gs_copy_hash
, variants
,
2638 &found_in_application_cache
);
2639 pipeline
->gs_copy_shader
= variants
[MESA_SHADER_GEOMETRY
];
2642 if (!keep_executable_info
&&
2643 radv_create_shader_variants_from_pipeline_cache(device
, cache
, hash
, pipeline
->shaders
,
2644 &found_in_application_cache
) &&
2645 (!modules
[MESA_SHADER_GEOMETRY
] || pipeline
->gs_copy_shader
)) {
2646 radv_stop_feedback(pipeline_feedback
, found_in_application_cache
);
2650 if (!modules
[MESA_SHADER_FRAGMENT
] && !modules
[MESA_SHADER_COMPUTE
]) {
2652 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
2653 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "noop_fs");
2654 fs_m
.nir
= fs_b
.shader
;
2655 modules
[MESA_SHADER_FRAGMENT
] = &fs_m
;
2658 bool has_gs
= modules
[MESA_SHADER_GEOMETRY
];
2659 bool has_ts
= modules
[MESA_SHADER_TESS_CTRL
] || modules
[MESA_SHADER_TESS_EVAL
];
2660 bool use_aco
= device
->physical_device
->use_aco
;
2662 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2663 const VkPipelineShaderStageCreateInfo
*stage
= pStages
[i
];
2668 radv_start_feedback(stage_feedbacks
[i
]);
2670 bool aco
= use_aco
&& radv_aco_supported_stage(i
, has_gs
, has_ts
);
2671 nir
[i
] = radv_shader_compile_to_nir(device
, modules
[i
],
2672 stage
? stage
->pName
: "main", i
,
2673 stage
? stage
->pSpecializationInfo
: NULL
,
2674 flags
, pipeline
->layout
, aco
);
2676 /* We don't want to alter meta shaders IR directly so clone it
2679 if (nir
[i
]->info
.name
) {
2680 nir
[i
] = nir_shader_clone(NULL
, nir
[i
]);
2683 radv_stop_feedback(stage_feedbacks
[i
], false);
2686 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2687 nir_lower_patch_vertices(nir
[MESA_SHADER_TESS_EVAL
], nir
[MESA_SHADER_TESS_CTRL
]->info
.tess
.tcs_vertices_out
, NULL
);
2688 merge_tess_info(&nir
[MESA_SHADER_TESS_EVAL
]->info
, &nir
[MESA_SHADER_TESS_CTRL
]->info
);
2691 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
2692 radv_link_shaders(pipeline
, nir
);
2694 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2696 NIR_PASS_V(nir
[i
], nir_lower_non_uniform_access
,
2697 nir_lower_non_uniform_ubo_access
|
2698 nir_lower_non_uniform_ssbo_access
|
2699 nir_lower_non_uniform_texture_access
|
2700 nir_lower_non_uniform_image_access
);
2702 bool aco
= use_aco
&& radv_aco_supported_stage(i
, has_gs
, has_ts
);
2704 NIR_PASS_V(nir
[i
], nir_lower_bool_to_int32
);
2707 if (radv_can_dump_shader(device
, modules
[i
], false))
2708 nir_print_shader(nir
[i
], stderr
);
2711 if (nir
[MESA_SHADER_FRAGMENT
])
2712 radv_lower_fs_io(nir
[MESA_SHADER_FRAGMENT
]);
2714 radv_fill_shader_keys(device
, keys
, key
, nir
);
2716 radv_fill_shader_info(pipeline
, pStages
, keys
, infos
, nir
);
2718 if ((nir
[MESA_SHADER_VERTEX
] &&
2719 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) ||
2720 (nir
[MESA_SHADER_TESS_EVAL
] &&
2721 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
)) {
2722 struct gfx10_ngg_info
*ngg_info
;
2724 if (nir
[MESA_SHADER_GEOMETRY
])
2725 ngg_info
= &infos
[MESA_SHADER_GEOMETRY
].ngg_info
;
2726 else if (nir
[MESA_SHADER_TESS_CTRL
])
2727 ngg_info
= &infos
[MESA_SHADER_TESS_EVAL
].ngg_info
;
2729 ngg_info
= &infos
[MESA_SHADER_VERTEX
].ngg_info
;
2731 gfx10_get_ngg_info(key
, pipeline
, nir
, infos
, ngg_info
);
2732 } else if (nir
[MESA_SHADER_GEOMETRY
]) {
2733 struct gfx9_gs_info
*gs_info
=
2734 &infos
[MESA_SHADER_GEOMETRY
].gs_ring_info
;
2736 gfx9_get_gs_info(key
, pipeline
, nir
, infos
, gs_info
);
2739 if (nir
[MESA_SHADER_FRAGMENT
]) {
2740 if (!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]) {
2741 radv_start_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
]);
2743 bool aco
= use_aco
&& radv_aco_supported_stage(MESA_SHADER_FRAGMENT
, has_gs
, has_ts
);
2744 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] =
2745 radv_shader_variant_compile(device
, modules
[MESA_SHADER_FRAGMENT
], &nir
[MESA_SHADER_FRAGMENT
], 1,
2746 pipeline
->layout
, keys
+ MESA_SHADER_FRAGMENT
,
2747 infos
+ MESA_SHADER_FRAGMENT
,
2748 keep_executable_info
, aco
,
2749 &binaries
[MESA_SHADER_FRAGMENT
]);
2751 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
], false);
2754 /* TODO: These are no longer used as keys we should refactor this */
2755 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
=
2756 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.prim_id_input
;
2757 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_layer_id
=
2758 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.layer_input
;
2759 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_clip_dists
=
2760 !!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.num_input_clips_culls
;
2761 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_prim_id
=
2762 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.prim_id_input
;
2763 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_layer_id
=
2764 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.layer_input
;
2765 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_clip_dists
=
2766 !!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.num_input_clips_culls
;
2769 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_TESS_CTRL
]) {
2770 if (!pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]) {
2771 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2772 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2773 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2775 radv_start_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
]);
2777 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_TESS_CTRL
], combined_nir
, 2,
2779 &key
, &infos
[MESA_SHADER_TESS_CTRL
], keep_executable_info
,
2780 false, &binaries
[MESA_SHADER_TESS_CTRL
]);
2782 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
], false);
2784 modules
[MESA_SHADER_VERTEX
] = NULL
;
2785 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2786 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2789 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_GEOMETRY
]) {
2790 gl_shader_stage pre_stage
= modules
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2791 if (!pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
2792 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2794 radv_start_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
]);
2796 pipeline
->shaders
[MESA_SHADER_GEOMETRY
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_GEOMETRY
], combined_nir
, 2,
2798 &keys
[pre_stage
], &infos
[MESA_SHADER_GEOMETRY
], keep_executable_info
,
2799 false, &binaries
[MESA_SHADER_GEOMETRY
]);
2801 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
], false);
2803 modules
[pre_stage
] = NULL
;
2806 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2807 if(modules
[i
] && !pipeline
->shaders
[i
]) {
2808 if (i
== MESA_SHADER_TESS_CTRL
) {
2809 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.ls_outputs_written
);
2811 if (i
== MESA_SHADER_TESS_EVAL
) {
2812 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2813 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2816 radv_start_feedback(stage_feedbacks
[i
]);
2818 bool aco
= use_aco
&& radv_aco_supported_stage(i
, has_gs
, has_ts
);
2819 pipeline
->shaders
[i
] = radv_shader_variant_compile(device
, modules
[i
], &nir
[i
], 1,
2821 keys
+ i
, infos
+ i
,keep_executable_info
,
2824 radv_stop_feedback(stage_feedbacks
[i
], false);
2828 if(modules
[MESA_SHADER_GEOMETRY
]) {
2829 struct radv_shader_binary
*gs_copy_binary
= NULL
;
2830 if (!pipeline
->gs_copy_shader
&&
2831 !radv_pipeline_has_ngg(pipeline
)) {
2832 struct radv_shader_info info
= {};
2833 struct radv_shader_variant_key key
= {};
2835 key
.has_multiview_view_index
=
2836 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
;
2838 radv_nir_shader_info_pass(nir
[MESA_SHADER_GEOMETRY
],
2839 pipeline
->layout
, &key
,
2841 info
.wave_size
= 64; /* Wave32 not supported. */
2843 pipeline
->gs_copy_shader
= radv_create_gs_copy_shader(
2844 device
, nir
[MESA_SHADER_GEOMETRY
], &info
,
2845 &gs_copy_binary
, keep_executable_info
,
2846 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
);
2849 if (!keep_executable_info
&& pipeline
->gs_copy_shader
) {
2850 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2851 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2853 binaries
[MESA_SHADER_GEOMETRY
] = gs_copy_binary
;
2854 variants
[MESA_SHADER_GEOMETRY
] = pipeline
->gs_copy_shader
;
2856 radv_pipeline_cache_insert_shaders(device
, cache
,
2861 free(gs_copy_binary
);
2864 if (!keep_executable_info
) {
2865 radv_pipeline_cache_insert_shaders(device
, cache
, hash
, pipeline
->shaders
,
2869 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2872 ralloc_free(nir
[i
]);
2874 if (radv_can_dump_shader_stats(device
, modules
[i
]))
2875 radv_shader_dump_stats(device
,
2876 pipeline
->shaders
[i
],
2882 ralloc_free(fs_m
.nir
);
2884 radv_stop_feedback(pipeline_feedback
, false);
2888 radv_pipeline_stage_to_user_data_0(struct radv_pipeline
*pipeline
,
2889 gl_shader_stage stage
, enum chip_class chip_class
)
2891 bool has_gs
= radv_pipeline_has_gs(pipeline
);
2892 bool has_tess
= radv_pipeline_has_tess(pipeline
);
2893 bool has_ngg
= radv_pipeline_has_ngg(pipeline
);
2896 case MESA_SHADER_FRAGMENT
:
2897 return R_00B030_SPI_SHADER_USER_DATA_PS_0
;
2898 case MESA_SHADER_VERTEX
:
2900 if (chip_class
>= GFX10
) {
2901 return R_00B430_SPI_SHADER_USER_DATA_HS_0
;
2902 } else if (chip_class
== GFX9
) {
2903 return R_00B430_SPI_SHADER_USER_DATA_LS_0
;
2905 return R_00B530_SPI_SHADER_USER_DATA_LS_0
;
2911 if (chip_class
>= GFX10
) {
2912 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
2914 return R_00B330_SPI_SHADER_USER_DATA_ES_0
;
2919 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
2921 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2922 case MESA_SHADER_GEOMETRY
:
2923 return chip_class
== GFX9
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
2924 R_00B230_SPI_SHADER_USER_DATA_GS_0
;
2925 case MESA_SHADER_COMPUTE
:
2926 return R_00B900_COMPUTE_USER_DATA_0
;
2927 case MESA_SHADER_TESS_CTRL
:
2928 return chip_class
== GFX9
? R_00B430_SPI_SHADER_USER_DATA_LS_0
:
2929 R_00B430_SPI_SHADER_USER_DATA_HS_0
;
2930 case MESA_SHADER_TESS_EVAL
:
2932 return chip_class
>= GFX10
? R_00B230_SPI_SHADER_USER_DATA_GS_0
:
2933 R_00B330_SPI_SHADER_USER_DATA_ES_0
;
2934 } else if (has_ngg
) {
2935 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
2937 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2940 unreachable("unknown shader");
2944 struct radv_bin_size_entry
{
2950 radv_gfx9_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
2952 static const struct radv_bin_size_entry color_size_table
[][3][9] = {
2956 /* One shader engine */
2962 { UINT_MAX
, { 0, 0}},
2965 /* Two shader engines */
2971 { UINT_MAX
, { 0, 0}},
2974 /* Four shader engines */
2979 { UINT_MAX
, { 0, 0}},
2985 /* One shader engine */
2991 { UINT_MAX
, { 0, 0}},
2994 /* Two shader engines */
3000 { UINT_MAX
, { 0, 0}},
3003 /* Four shader engines */
3010 { UINT_MAX
, { 0, 0}},
3016 /* One shader engine */
3023 { UINT_MAX
, { 0, 0}},
3026 /* Two shader engines */
3034 { UINT_MAX
, { 0, 0}},
3037 /* Four shader engines */
3045 { UINT_MAX
, { 0, 0}},
3049 static const struct radv_bin_size_entry ds_size_table
[][3][9] = {
3053 // One shader engine
3060 { UINT_MAX
, { 0, 0}},
3063 // Two shader engines
3071 { UINT_MAX
, { 0, 0}},
3074 // Four shader engines
3082 { UINT_MAX
, { 0, 0}},
3088 // One shader engine
3096 { UINT_MAX
, { 0, 0}},
3099 // Two shader engines
3108 { UINT_MAX
, { 0, 0}},
3111 // Four shader engines
3120 { UINT_MAX
, { 0, 0}},
3126 // One shader engine
3134 { UINT_MAX
, { 0, 0}},
3137 // Two shader engines
3146 { UINT_MAX
, { 0, 0}},
3149 // Four shader engines
3157 { UINT_MAX
, { 0, 0}},
3162 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3163 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3164 VkExtent2D extent
= {512, 512};
3166 unsigned log_num_rb_per_se
=
3167 util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.num_render_backends
/
3168 pipeline
->device
->physical_device
->rad_info
.max_se
);
3169 unsigned log_num_se
= util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.max_se
);
3171 unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3172 unsigned ps_iter_samples
= 1u << G_028804_PS_ITER_SAMPLES(pipeline
->graphics
.ms
.db_eqaa
);
3173 unsigned effective_samples
= total_samples
;
3174 unsigned color_bytes_per_pixel
= 0;
3176 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
3178 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3179 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3182 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3185 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3186 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3189 /* MSAA images typically don't use all samples all the time. */
3190 if (effective_samples
>= 2 && ps_iter_samples
<= 1)
3191 effective_samples
= 2;
3192 color_bytes_per_pixel
*= effective_samples
;
3195 const struct radv_bin_size_entry
*color_entry
= color_size_table
[log_num_rb_per_se
][log_num_se
];
3196 while(color_entry
[1].bpp
<= color_bytes_per_pixel
)
3199 extent
= color_entry
->extent
;
3201 if (subpass
->depth_stencil_attachment
) {
3202 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3204 /* Coefficients taken from AMDVLK */
3205 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3206 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3207 unsigned ds_bytes_per_pixel
= 4 * (depth_coeff
+ stencil_coeff
) * total_samples
;
3209 const struct radv_bin_size_entry
*ds_entry
= ds_size_table
[log_num_rb_per_se
][log_num_se
];
3210 while(ds_entry
[1].bpp
<= ds_bytes_per_pixel
)
3213 if (ds_entry
->extent
.width
* ds_entry
->extent
.height
< extent
.width
* extent
.height
)
3214 extent
= ds_entry
->extent
;
3221 radv_gfx10_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3223 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3224 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3225 VkExtent2D extent
= {512, 512};
3227 const unsigned db_tag_size
= 64;
3228 const unsigned db_tag_count
= 312;
3229 const unsigned color_tag_size
= 1024;
3230 const unsigned color_tag_count
= 31;
3231 const unsigned fmask_tag_size
= 256;
3232 const unsigned fmask_tag_count
= 44;
3234 const unsigned rb_count
= pipeline
->device
->physical_device
->rad_info
.num_render_backends
;
3235 const unsigned pipe_count
= MAX2(rb_count
, pipeline
->device
->physical_device
->rad_info
.num_sdp_interfaces
);
3237 const unsigned db_tag_part
= (db_tag_count
* rb_count
/ pipe_count
) * db_tag_size
* pipe_count
;
3238 const unsigned color_tag_part
= (color_tag_count
* rb_count
/ pipe_count
) * color_tag_size
* pipe_count
;
3239 const unsigned fmask_tag_part
= (fmask_tag_count
* rb_count
/ pipe_count
) * fmask_tag_size
* pipe_count
;
3241 const unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3242 const unsigned samples_log
= util_logbase2_ceil(total_samples
);
3244 unsigned color_bytes_per_pixel
= 0;
3245 unsigned fmask_bytes_per_pixel
= 0;
3247 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
3249 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3250 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3253 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3256 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3257 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3259 if (total_samples
> 1) {
3260 assert(samples_log
<= 3);
3261 const unsigned fmask_array
[] = {0, 1, 1, 4};
3262 fmask_bytes_per_pixel
+= fmask_array
[samples_log
];
3266 color_bytes_per_pixel
*= total_samples
;
3268 color_bytes_per_pixel
= MAX2(color_bytes_per_pixel
, 1);
3270 const unsigned color_pixel_count_log
= util_logbase2(color_tag_part
/ color_bytes_per_pixel
);
3271 extent
.width
= 1ull << ((color_pixel_count_log
+ 1) / 2);
3272 extent
.height
= 1ull << (color_pixel_count_log
/ 2);
3274 if (fmask_bytes_per_pixel
) {
3275 const unsigned fmask_pixel_count_log
= util_logbase2(fmask_tag_part
/ fmask_bytes_per_pixel
);
3277 const VkExtent2D fmask_extent
= (VkExtent2D
){
3278 .width
= 1ull << ((fmask_pixel_count_log
+ 1) / 2),
3279 .height
= 1ull << (color_pixel_count_log
/ 2)
3282 if (fmask_extent
.width
* fmask_extent
.height
< extent
.width
* extent
.height
)
3283 extent
= fmask_extent
;
3286 if (subpass
->depth_stencil_attachment
) {
3287 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3289 /* Coefficients taken from AMDVLK */
3290 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3291 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3292 unsigned db_bytes_per_pixel
= (depth_coeff
+ stencil_coeff
) * total_samples
;
3294 const unsigned db_pixel_count_log
= util_logbase2(db_tag_part
/ db_bytes_per_pixel
);
3296 const VkExtent2D db_extent
= (VkExtent2D
){
3297 .width
= 1ull << ((db_pixel_count_log
+ 1) / 2),
3298 .height
= 1ull << (color_pixel_count_log
/ 2)
3301 if (db_extent
.width
* db_extent
.height
< extent
.width
* extent
.height
)
3305 extent
.width
= MAX2(extent
.width
, 128);
3306 extent
.height
= MAX2(extent
.width
, 64);
3312 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3313 struct radv_pipeline
*pipeline
,
3314 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3316 uint32_t pa_sc_binner_cntl_0
=
3317 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC
) |
3318 S_028C44_DISABLE_START_OF_PRIM(1);
3319 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3321 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3322 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3323 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3324 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
3325 unsigned min_bytes_per_pixel
= 0;
3328 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3329 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3332 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3335 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3336 unsigned bytes
= vk_format_get_blocksize(format
);
3337 if (!min_bytes_per_pixel
|| bytes
< min_bytes_per_pixel
)
3338 min_bytes_per_pixel
= bytes
;
3342 pa_sc_binner_cntl_0
=
3343 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC
) |
3344 S_028C44_BIN_SIZE_X(0) |
3345 S_028C44_BIN_SIZE_Y(0) |
3346 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3347 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel
<= 4 ? 2 : 1) | /* 128 or 64 */
3348 S_028C44_DISABLE_START_OF_PRIM(1);
3351 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3352 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3356 radv_pipeline_generate_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3357 struct radv_pipeline
*pipeline
,
3358 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3359 const struct radv_blend_state
*blend
)
3361 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
3364 VkExtent2D bin_size
;
3365 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3366 bin_size
= radv_gfx10_compute_bin_size(pipeline
, pCreateInfo
);
3367 } else if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3368 bin_size
= radv_gfx9_compute_bin_size(pipeline
, pCreateInfo
);
3370 unreachable("Unhandled generation for binning bin size calculation");
3372 if (pipeline
->device
->pbb_allowed
&& bin_size
.width
&& bin_size
.height
) {
3373 unsigned context_states_per_bin
; /* allowed range: [1, 6] */
3374 unsigned persistent_states_per_bin
; /* allowed range: [1, 32] */
3375 unsigned fpovs_per_batch
; /* allowed range: [0, 255], 0 = unlimited */
3377 if (pipeline
->device
->physical_device
->rad_info
.has_dedicated_vram
) {
3378 context_states_per_bin
= 1;
3379 persistent_states_per_bin
= 1;
3380 fpovs_per_batch
= 63;
3382 /* The context states are affected by the scissor bug. */
3383 context_states_per_bin
= pipeline
->device
->physical_device
->rad_info
.has_gfx9_scissor_bug
? 1 : 6;
3384 /* 32 causes hangs for RAVEN. */
3385 persistent_states_per_bin
= 16;
3386 fpovs_per_batch
= 63;
3389 bool disable_start_of_prim
= true;
3390 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3392 const struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3394 if (pipeline
->device
->dfsm_allowed
&& ps
&&
3395 !ps
->info
.ps
.can_discard
&&
3396 !ps
->info
.ps
.writes_memory
&&
3397 blend
->cb_target_enabled_4bit
) {
3398 db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_AUTO
);
3399 disable_start_of_prim
= (blend
->blend_enable_4bit
& blend
->cb_target_enabled_4bit
) != 0;
3402 const uint32_t pa_sc_binner_cntl_0
=
3403 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED
) |
3404 S_028C44_BIN_SIZE_X(bin_size
.width
== 16) |
3405 S_028C44_BIN_SIZE_Y(bin_size
.height
== 16) |
3406 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size
.width
, 32)) - 5) |
3407 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size
.height
, 32)) - 5) |
3408 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin
- 1) |
3409 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin
- 1) |
3410 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim
) |
3411 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch
) |
3412 S_028C44_OPTIMAL_BIN_SELECTION(1);
3414 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3415 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3417 radv_pipeline_generate_disabled_binning_state(ctx_cs
, pipeline
, pCreateInfo
);
3422 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf
*ctx_cs
,
3423 struct radv_pipeline
*pipeline
,
3424 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3425 const struct radv_graphics_pipeline_create_info
*extra
)
3427 const VkPipelineDepthStencilStateCreateInfo
*vkds
= pCreateInfo
->pDepthStencilState
;
3428 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3429 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3430 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3431 struct radv_render_pass_attachment
*attachment
= NULL
;
3432 uint32_t db_depth_control
= 0, db_stencil_control
= 0;
3433 uint32_t db_render_control
= 0, db_render_override2
= 0;
3434 uint32_t db_render_override
= 0;
3436 if (subpass
->depth_stencil_attachment
)
3437 attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3439 bool has_depth_attachment
= attachment
&& vk_format_is_depth(attachment
->format
);
3440 bool has_stencil_attachment
= attachment
&& vk_format_is_stencil(attachment
->format
);
3442 if (vkds
&& has_depth_attachment
) {
3443 db_depth_control
= S_028800_Z_ENABLE(vkds
->depthTestEnable
? 1 : 0) |
3444 S_028800_Z_WRITE_ENABLE(vkds
->depthWriteEnable
? 1 : 0) |
3445 S_028800_ZFUNC(vkds
->depthCompareOp
) |
3446 S_028800_DEPTH_BOUNDS_ENABLE(vkds
->depthBoundsTestEnable
? 1 : 0);
3448 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3449 db_render_override2
|= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment
->samples
> 2);
3452 if (has_stencil_attachment
&& vkds
&& vkds
->stencilTestEnable
) {
3453 db_depth_control
|= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3454 db_depth_control
|= S_028800_STENCILFUNC(vkds
->front
.compareOp
);
3455 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds
->front
.failOp
));
3456 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds
->front
.passOp
));
3457 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds
->front
.depthFailOp
));
3459 db_depth_control
|= S_028800_STENCILFUNC_BF(vkds
->back
.compareOp
);
3460 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds
->back
.failOp
));
3461 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds
->back
.passOp
));
3462 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds
->back
.depthFailOp
));
3465 if (attachment
&& extra
) {
3466 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(extra
->db_depth_clear
);
3467 db_render_control
|= S_028000_STENCIL_CLEAR_ENABLE(extra
->db_stencil_clear
);
3469 db_render_control
|= S_028000_RESUMMARIZE_ENABLE(extra
->db_resummarize
);
3470 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(extra
->db_flush_depth_inplace
);
3471 db_render_control
|= S_028000_STENCIL_COMPRESS_DISABLE(extra
->db_flush_stencil_inplace
);
3472 db_render_override2
|= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra
->db_depth_disable_expclear
);
3473 db_render_override2
|= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra
->db_stencil_disable_expclear
);
3476 db_render_override
|= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
3477 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
3479 if (!pCreateInfo
->pRasterizationState
->depthClampEnable
&&
3480 ps
->info
.ps
.writes_z
) {
3481 /* From VK_EXT_depth_range_unrestricted spec:
3483 * "The behavior described in Primitive Clipping still applies.
3484 * If depth clamping is disabled the depth values are still
3485 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3486 * depth clamping is enabled the above equation is ignored and
3487 * the depth values are instead clamped to the VkViewport
3488 * minDepth and maxDepth values, which in the case of this
3489 * extension can be outside of the 0.0 to 1.0 range."
3491 db_render_override
|= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3494 radeon_set_context_reg(ctx_cs
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
3495 radeon_set_context_reg(ctx_cs
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
3497 radeon_set_context_reg(ctx_cs
, R_028000_DB_RENDER_CONTROL
, db_render_control
);
3498 radeon_set_context_reg(ctx_cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
3499 radeon_set_context_reg(ctx_cs
, R_028010_DB_RENDER_OVERRIDE2
, db_render_override2
);
3503 radv_pipeline_generate_blend_state(struct radeon_cmdbuf
*ctx_cs
,
3504 struct radv_pipeline
*pipeline
,
3505 const struct radv_blend_state
*blend
)
3507 radeon_set_context_reg_seq(ctx_cs
, R_028780_CB_BLEND0_CONTROL
, 8);
3508 radeon_emit_array(ctx_cs
, blend
->cb_blend_control
,
3510 radeon_set_context_reg(ctx_cs
, R_028808_CB_COLOR_CONTROL
, blend
->cb_color_control
);
3511 radeon_set_context_reg(ctx_cs
, R_028B70_DB_ALPHA_TO_MASK
, blend
->db_alpha_to_mask
);
3513 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
3515 radeon_set_context_reg_seq(ctx_cs
, R_028760_SX_MRT0_BLEND_OPT
, 8);
3516 radeon_emit_array(ctx_cs
, blend
->sx_mrt_blend_opt
, 8);
3519 radeon_set_context_reg(ctx_cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
3521 radeon_set_context_reg(ctx_cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
3522 radeon_set_context_reg(ctx_cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
3524 pipeline
->graphics
.col_format
= blend
->spi_shader_col_format
;
3525 pipeline
->graphics
.cb_target_mask
= blend
->cb_target_mask
;
3528 static const VkConservativeRasterizationModeEXT
3529 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo
*pCreateInfo
)
3531 const VkPipelineRasterizationConservativeStateCreateInfoEXT
*conservative_raster
=
3532 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT
);
3534 if (!conservative_raster
)
3535 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
;
3536 return conservative_raster
->conservativeRasterizationMode
;
3540 radv_pipeline_generate_raster_state(struct radeon_cmdbuf
*ctx_cs
,
3541 struct radv_pipeline
*pipeline
,
3542 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3544 const VkPipelineRasterizationStateCreateInfo
*vkraster
= pCreateInfo
->pRasterizationState
;
3545 const VkConservativeRasterizationModeEXT mode
=
3546 radv_get_conservative_raster_mode(vkraster
);
3547 uint32_t pa_sc_conservative_rast
= S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3548 bool depth_clip_disable
= vkraster
->depthClampEnable
;
3550 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*depth_clip_state
=
3551 vk_find_struct_const(vkraster
->pNext
, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
3552 if (depth_clip_state
) {
3553 depth_clip_disable
= !depth_clip_state
->depthClipEnable
;
3556 radeon_set_context_reg(ctx_cs
, R_028810_PA_CL_CLIP_CNTL
,
3557 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3558 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable
? 1 : 0) |
3559 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable
? 1 : 0) |
3560 S_028810_DX_RASTERIZATION_KILL(vkraster
->rasterizerDiscardEnable
? 1 : 0) |
3561 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3563 radeon_set_context_reg(ctx_cs
, R_0286D4_SPI_INTERP_CONTROL_0
,
3564 S_0286D4_FLAT_SHADE_ENA(1) |
3565 S_0286D4_PNT_SPRITE_ENA(1) |
3566 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
3567 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
3568 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
3569 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
3570 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3572 radeon_set_context_reg(ctx_cs
, R_028BE4_PA_SU_VTX_CNTL
,
3573 S_028BE4_PIX_CENTER(1) | // TODO verify
3574 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN
) |
3575 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
3577 radeon_set_context_reg(ctx_cs
, R_028814_PA_SU_SC_MODE_CNTL
,
3578 S_028814_FACE(vkraster
->frontFace
) |
3579 S_028814_CULL_FRONT(!!(vkraster
->cullMode
& VK_CULL_MODE_FRONT_BIT
)) |
3580 S_028814_CULL_BACK(!!(vkraster
->cullMode
& VK_CULL_MODE_BACK_BIT
)) |
3581 S_028814_POLY_MODE(vkraster
->polygonMode
!= VK_POLYGON_MODE_FILL
) |
3582 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3583 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3584 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3585 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3586 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster
->depthBiasEnable
? 1 : 0));
3588 /* Conservative rasterization. */
3589 if (mode
!= VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
) {
3590 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3592 ms
->pa_sc_aa_config
|= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3593 ms
->db_eqaa
|= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3594 S_028804_OVERRASTERIZATION_AMOUNT(4);
3596 pa_sc_conservative_rast
= S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3597 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3598 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3600 if (mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT
) {
3601 pa_sc_conservative_rast
|=
3602 S_028C4C_OVER_RAST_ENABLE(1) |
3603 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3604 S_028C4C_UNDER_RAST_ENABLE(0) |
3605 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3606 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3608 assert(mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT
);
3609 pa_sc_conservative_rast
|=
3610 S_028C4C_OVER_RAST_ENABLE(0) |
3611 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3612 S_028C4C_UNDER_RAST_ENABLE(1) |
3613 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3614 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3618 radeon_set_context_reg(ctx_cs
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
3619 pa_sc_conservative_rast
);
3624 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf
*ctx_cs
,
3625 struct radv_pipeline
*pipeline
)
3627 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3629 radeon_set_context_reg_seq(ctx_cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
3630 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[0]);
3631 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[1]);
3633 radeon_set_context_reg(ctx_cs
, R_028804_DB_EQAA
, ms
->db_eqaa
);
3634 radeon_set_context_reg(ctx_cs
, R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
3636 /* The exclusion bits can be set to improve rasterization efficiency
3637 * if no sample lies on the pixel boundary (-8 sample offset). It's
3638 * currently always TRUE because the driver doesn't support 16 samples.
3640 bool exclusion
= pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
3641 radeon_set_context_reg(ctx_cs
, R_02882C_PA_SU_PRIM_FILTER_CNTL
,
3642 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) |
3643 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3647 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf
*ctx_cs
,
3648 struct radv_pipeline
*pipeline
)
3650 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3651 const struct radv_shader_variant
*vs
=
3652 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] ?
3653 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] :
3654 pipeline
->shaders
[MESA_SHADER_VERTEX
];
3655 unsigned vgt_primitiveid_en
= 0;
3656 uint32_t vgt_gs_mode
= 0;
3658 if (radv_pipeline_has_ngg(pipeline
))
3661 if (radv_pipeline_has_gs(pipeline
)) {
3662 const struct radv_shader_variant
*gs
=
3663 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3665 vgt_gs_mode
= ac_vgt_gs_mode(gs
->info
.gs
.vertices_out
,
3666 pipeline
->device
->physical_device
->rad_info
.chip_class
);
3667 } else if (outinfo
->export_prim_id
|| vs
->info
.uses_prim_id
) {
3668 vgt_gs_mode
= S_028A40_MODE(V_028A40_GS_SCENARIO_A
);
3669 vgt_primitiveid_en
|= S_028A84_PRIMITIVEID_EN(1);
3672 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
, vgt_primitiveid_en
);
3673 radeon_set_context_reg(ctx_cs
, R_028A40_VGT_GS_MODE
, vgt_gs_mode
);
3677 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf
*ctx_cs
,
3678 struct radeon_cmdbuf
*cs
,
3679 struct radv_pipeline
*pipeline
,
3680 struct radv_shader_variant
*shader
)
3682 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3684 radeon_set_sh_reg_seq(cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
3685 radeon_emit(cs
, va
>> 8);
3686 radeon_emit(cs
, S_00B124_MEM_BASE(va
>> 40));
3687 radeon_emit(cs
, shader
->config
.rsrc1
);
3688 radeon_emit(cs
, shader
->config
.rsrc2
);
3690 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3691 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3692 clip_dist_mask
= outinfo
->clip_dist_mask
;
3693 cull_dist_mask
= outinfo
->cull_dist_mask
;
3694 total_mask
= clip_dist_mask
| cull_dist_mask
;
3695 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3696 outinfo
->writes_layer
||
3697 outinfo
->writes_viewport_index
;
3698 unsigned spi_vs_out_config
, nparams
;
3700 /* VS is required to export at least one param. */
3701 nparams
= MAX2(outinfo
->param_exports
, 1);
3702 spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
3704 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3705 spi_vs_out_config
|= S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0);
3708 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
, spi_vs_out_config
);
3710 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3711 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3712 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3713 V_02870C_SPI_SHADER_4COMP
:
3714 V_02870C_SPI_SHADER_NONE
) |
3715 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3716 V_02870C_SPI_SHADER_4COMP
:
3717 V_02870C_SPI_SHADER_NONE
) |
3718 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3719 V_02870C_SPI_SHADER_4COMP
:
3720 V_02870C_SPI_SHADER_NONE
));
3722 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
3723 S_028818_VTX_W0_FMT(1) |
3724 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3725 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3726 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3728 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3729 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3730 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3731 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3732 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3733 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3734 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3735 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3736 cull_dist_mask
<< 8 |
3739 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
3740 radeon_set_context_reg(ctx_cs
, R_028AB4_VGT_REUSE_OFF
,
3741 outinfo
->writes_viewport_index
);
3745 radv_pipeline_generate_hw_es(struct radeon_cmdbuf
*cs
,
3746 struct radv_pipeline
*pipeline
,
3747 struct radv_shader_variant
*shader
)
3749 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3751 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
3752 radeon_emit(cs
, va
>> 8);
3753 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3754 radeon_emit(cs
, shader
->config
.rsrc1
);
3755 radeon_emit(cs
, shader
->config
.rsrc2
);
3759 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf
*cs
,
3760 struct radv_pipeline
*pipeline
,
3761 struct radv_shader_variant
*shader
,
3762 const struct radv_tessellation_state
*tess
)
3764 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3765 uint32_t rsrc2
= shader
->config
.rsrc2
;
3767 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
3768 radeon_emit(cs
, va
>> 8);
3769 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
3771 rsrc2
|= S_00B52C_LDS_SIZE(tess
->lds_size
);
3772 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX7
&&
3773 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
3774 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
3776 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
3777 radeon_emit(cs
, shader
->config
.rsrc1
);
3778 radeon_emit(cs
, rsrc2
);
3782 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf
*ctx_cs
,
3783 struct radeon_cmdbuf
*cs
,
3784 struct radv_pipeline
*pipeline
,
3785 struct radv_shader_variant
*shader
)
3787 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3788 gl_shader_stage es_type
=
3789 radv_pipeline_has_tess(pipeline
) ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
3790 struct radv_shader_variant
*es
=
3791 es_type
== MESA_SHADER_TESS_EVAL
? pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] : pipeline
->shaders
[MESA_SHADER_VERTEX
];
3792 const struct gfx10_ngg_info
*ngg_state
= &shader
->info
.ngg_info
;
3794 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
3795 radeon_emit(cs
, va
>> 8);
3796 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3797 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
3798 radeon_emit(cs
, shader
->config
.rsrc1
);
3799 radeon_emit(cs
, shader
->config
.rsrc2
);
3801 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3802 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3803 clip_dist_mask
= outinfo
->clip_dist_mask
;
3804 cull_dist_mask
= outinfo
->cull_dist_mask
;
3805 total_mask
= clip_dist_mask
| cull_dist_mask
;
3806 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3807 outinfo
->writes_layer
||
3808 outinfo
->writes_viewport_index
;
3809 bool es_enable_prim_id
= outinfo
->export_prim_id
||
3810 (es
&& es
->info
.uses_prim_id
);
3811 bool break_wave_at_eoi
= false;
3815 if (es_type
== MESA_SHADER_TESS_EVAL
) {
3816 struct radv_shader_variant
*gs
=
3817 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3819 if (es_enable_prim_id
|| (gs
&& gs
->info
.uses_prim_id
))
3820 break_wave_at_eoi
= true;
3823 nparams
= MAX2(outinfo
->param_exports
, 1);
3824 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
3825 S_0286C4_VS_EXPORT_COUNT(nparams
- 1) |
3826 S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0));
3828 radeon_set_context_reg(ctx_cs
, R_028708_SPI_SHADER_IDX_FORMAT
,
3829 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP
));
3830 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3831 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3832 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3833 V_02870C_SPI_SHADER_4COMP
:
3834 V_02870C_SPI_SHADER_NONE
) |
3835 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3836 V_02870C_SPI_SHADER_4COMP
:
3837 V_02870C_SPI_SHADER_NONE
) |
3838 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3839 V_02870C_SPI_SHADER_4COMP
:
3840 V_02870C_SPI_SHADER_NONE
));
3842 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
3843 S_028818_VTX_W0_FMT(1) |
3844 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3845 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3846 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3847 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3848 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3849 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3850 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3851 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3852 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3853 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3854 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3855 cull_dist_mask
<< 8 |
3858 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
,
3859 S_028A84_PRIMITIVEID_EN(es_enable_prim_id
) |
3860 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id
));
3862 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
3863 ngg_state
->vgt_esgs_ring_itemsize
);
3865 /* NGG specific registers. */
3866 struct radv_shader_variant
*gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3867 uint32_t gs_num_invocations
= gs
? gs
->info
.gs
.invocations
: 1;
3869 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
3870 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state
->hw_max_esverts
) |
3871 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state
->max_gsprims
) |
3872 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state
->max_gsprims
* gs_num_invocations
));
3873 radeon_set_context_reg(ctx_cs
, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP
,
3874 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state
->max_out_verts
));
3875 radeon_set_context_reg(ctx_cs
, R_028B4C_GE_NGG_SUBGRP_CNTL
,
3876 S_028B4C_PRIM_AMP_FACTOR(ngg_state
->prim_amp_factor
) |
3877 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
3878 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
3879 S_028B90_CNT(gs_num_invocations
) |
3880 S_028B90_ENABLE(gs_num_invocations
> 1) |
3881 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state
->max_vert_out_per_gs_instance
));
3883 /* User edge flags are set by the pos exports. If user edge flags are
3884 * not used, we must use hw-generated edge flags and pass them via
3885 * the prim export to prevent drawing lines on internal edges of
3886 * decomposed primitives (such as quads) with polygon mode = lines.
3888 * TODO: We should combine hw-generated edge flags with user edge
3889 * flags in the shader.
3891 radeon_set_context_reg(ctx_cs
, R_028838_PA_CL_NGG_CNTL
,
3892 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline
) &&
3893 !radv_pipeline_has_gs(pipeline
)));
3895 ge_cntl
= S_03096C_PRIM_GRP_SIZE(ngg_state
->max_gsprims
) |
3896 S_03096C_VERT_GRP_SIZE(ngg_state
->hw_max_esverts
) |
3897 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
);
3899 /* Bug workaround for a possible hang with non-tessellation cases.
3900 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
3902 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
3904 if ((pipeline
->device
->physical_device
->rad_info
.family
== CHIP_NAVI10
||
3905 pipeline
->device
->physical_device
->rad_info
.family
== CHIP_NAVI12
||
3906 pipeline
->device
->physical_device
->rad_info
.family
== CHIP_NAVI14
) &&
3907 !radv_pipeline_has_tess(pipeline
) &&
3908 ngg_state
->hw_max_esverts
!= 256) {
3909 ge_cntl
&= C_03096C_VERT_GRP_SIZE
;
3911 if (ngg_state
->hw_max_esverts
> 5) {
3912 ge_cntl
|= S_03096C_VERT_GRP_SIZE(ngg_state
->hw_max_esverts
- 5);
3916 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
, ge_cntl
);
3920 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf
*cs
,
3921 struct radv_pipeline
*pipeline
,
3922 struct radv_shader_variant
*shader
,
3923 const struct radv_tessellation_state
*tess
)
3925 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3927 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
3928 unsigned hs_rsrc2
= shader
->config
.rsrc2
;
3930 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3931 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX10(tess
->lds_size
);
3933 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX9(tess
->lds_size
);
3936 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3937 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
3938 radeon_emit(cs
, va
>> 8);
3939 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
3941 radeon_set_sh_reg_seq(cs
, R_00B410_SPI_SHADER_PGM_LO_LS
, 2);
3942 radeon_emit(cs
, va
>> 8);
3943 radeon_emit(cs
, S_00B414_MEM_BASE(va
>> 40));
3946 radeon_set_sh_reg_seq(cs
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
, 2);
3947 radeon_emit(cs
, shader
->config
.rsrc1
);
3948 radeon_emit(cs
, hs_rsrc2
);
3950 radeon_set_sh_reg_seq(cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
3951 radeon_emit(cs
, va
>> 8);
3952 radeon_emit(cs
, S_00B424_MEM_BASE(va
>> 40));
3953 radeon_emit(cs
, shader
->config
.rsrc1
);
3954 radeon_emit(cs
, shader
->config
.rsrc2
);
3959 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf
*ctx_cs
,
3960 struct radeon_cmdbuf
*cs
,
3961 struct radv_pipeline
*pipeline
,
3962 const struct radv_tessellation_state
*tess
)
3964 struct radv_shader_variant
*vs
;
3966 /* Skip shaders merged into HS/GS */
3967 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
3971 if (vs
->info
.vs
.as_ls
)
3972 radv_pipeline_generate_hw_ls(cs
, pipeline
, vs
, tess
);
3973 else if (vs
->info
.vs
.as_es
)
3974 radv_pipeline_generate_hw_es(cs
, pipeline
, vs
);
3975 else if (vs
->info
.is_ngg
)
3976 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, vs
);
3978 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, vs
);
3982 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf
*ctx_cs
,
3983 struct radeon_cmdbuf
*cs
,
3984 struct radv_pipeline
*pipeline
,
3985 const struct radv_tessellation_state
*tess
)
3987 if (!radv_pipeline_has_tess(pipeline
))
3990 struct radv_shader_variant
*tes
, *tcs
;
3992 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
3993 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
3996 if (tes
->info
.is_ngg
) {
3997 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, tes
);
3998 } else if (tes
->info
.tes
.as_es
)
3999 radv_pipeline_generate_hw_es(cs
, pipeline
, tes
);
4001 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, tes
);
4004 radv_pipeline_generate_hw_hs(cs
, pipeline
, tcs
, tess
);
4006 radeon_set_context_reg(ctx_cs
, R_028B6C_VGT_TF_PARAM
,
4009 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
)
4010 radeon_set_context_reg_idx(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
4011 tess
->ls_hs_config
);
4013 radeon_set_context_reg(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
,
4014 tess
->ls_hs_config
);
4016 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
4017 !radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
4018 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4019 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4020 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4021 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4026 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf
*ctx_cs
,
4027 struct radeon_cmdbuf
*cs
,
4028 struct radv_pipeline
*pipeline
,
4029 struct radv_shader_variant
*gs
)
4031 const struct gfx9_gs_info
*gs_state
= &gs
->info
.gs_ring_info
;
4032 unsigned gs_max_out_vertices
;
4033 uint8_t *num_components
;
4038 gs_max_out_vertices
= gs
->info
.gs
.vertices_out
;
4039 max_stream
= gs
->info
.gs
.max_stream
;
4040 num_components
= gs
->info
.gs
.num_stream_output_components
;
4042 offset
= num_components
[0] * gs_max_out_vertices
;
4044 radeon_set_context_reg_seq(ctx_cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
4045 radeon_emit(ctx_cs
, offset
);
4046 if (max_stream
>= 1)
4047 offset
+= num_components
[1] * gs_max_out_vertices
;
4048 radeon_emit(ctx_cs
, offset
);
4049 if (max_stream
>= 2)
4050 offset
+= num_components
[2] * gs_max_out_vertices
;
4051 radeon_emit(ctx_cs
, offset
);
4052 if (max_stream
>= 3)
4053 offset
+= num_components
[3] * gs_max_out_vertices
;
4054 radeon_set_context_reg(ctx_cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
4056 radeon_set_context_reg_seq(ctx_cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
4057 radeon_emit(ctx_cs
, num_components
[0]);
4058 radeon_emit(ctx_cs
, (max_stream
>= 1) ? num_components
[1] : 0);
4059 radeon_emit(ctx_cs
, (max_stream
>= 2) ? num_components
[2] : 0);
4060 radeon_emit(ctx_cs
, (max_stream
>= 3) ? num_components
[3] : 0);
4062 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
4063 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
4064 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
4065 S_028B90_ENABLE(gs_num_invocations
> 0));
4067 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
4068 gs_state
->vgt_esgs_ring_itemsize
);
4070 va
= radv_buffer_get_va(gs
->bo
) + gs
->bo_offset
;
4072 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4073 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4074 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
4075 radeon_emit(cs
, va
>> 8);
4076 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
4078 radeon_set_sh_reg_seq(cs
, R_00B210_SPI_SHADER_PGM_LO_ES
, 2);
4079 radeon_emit(cs
, va
>> 8);
4080 radeon_emit(cs
, S_00B214_MEM_BASE(va
>> 40));
4083 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
4084 radeon_emit(cs
, gs
->config
.rsrc1
);
4085 radeon_emit(cs
, gs
->config
.rsrc2
| S_00B22C_LDS_SIZE(gs_state
->lds_size
));
4087 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
, gs_state
->vgt_gs_onchip_cntl
);
4088 radeon_set_context_reg(ctx_cs
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
, gs_state
->vgt_gs_max_prims_per_subgroup
);
4090 radeon_set_sh_reg_seq(cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
4091 radeon_emit(cs
, va
>> 8);
4092 radeon_emit(cs
, S_00B224_MEM_BASE(va
>> 40));
4093 radeon_emit(cs
, gs
->config
.rsrc1
);
4094 radeon_emit(cs
, gs
->config
.rsrc2
);
4097 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, pipeline
->gs_copy_shader
);
4101 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf
*ctx_cs
,
4102 struct radeon_cmdbuf
*cs
,
4103 struct radv_pipeline
*pipeline
)
4105 struct radv_shader_variant
*gs
;
4107 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4111 if (gs
->info
.is_ngg
)
4112 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, gs
);
4114 radv_pipeline_generate_hw_gs(ctx_cs
, cs
, pipeline
, gs
);
4116 radeon_set_context_reg(ctx_cs
, R_028B38_VGT_GS_MAX_VERT_OUT
,
4117 gs
->info
.gs
.vertices_out
);
4120 static uint32_t offset_to_ps_input(uint32_t offset
, bool flat_shade
, bool float16
)
4122 uint32_t ps_input_cntl
;
4123 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
4124 ps_input_cntl
= S_028644_OFFSET(offset
);
4126 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
4128 ps_input_cntl
|= S_028644_FP16_INTERP_MODE(1) |
4129 S_028644_ATTR0_VALID(1);
4132 /* The input is a DEFAULT_VAL constant. */
4133 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
4134 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
4135 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
4136 ps_input_cntl
= S_028644_OFFSET(0x20) |
4137 S_028644_DEFAULT_VAL(offset
);
4139 return ps_input_cntl
;
4143 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf
*ctx_cs
,
4144 struct radv_pipeline
*pipeline
)
4146 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4147 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
4148 uint32_t ps_input_cntl
[32];
4150 unsigned ps_offset
= 0;
4152 if (ps
->info
.ps
.prim_id_input
) {
4153 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
];
4154 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4155 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false);
4160 if (ps
->info
.ps
.layer_input
||
4161 ps
->info
.needs_multiview_view_index
) {
4162 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
];
4163 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
4164 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false);
4166 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false);
4170 if (ps
->info
.ps
.has_pcoord
) {
4172 val
= S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4173 ps_input_cntl
[ps_offset
] = val
;
4177 if (ps
->info
.ps
.num_input_clips_culls
) {
4180 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST0
];
4181 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4182 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false);
4186 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST1
];
4187 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
&&
4188 ps
->info
.ps
.num_input_clips_culls
> 4) {
4189 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false);
4194 for (unsigned i
= 0; i
< 32 && (1u << i
) <= ps
->info
.ps
.input_mask
; ++i
) {
4198 if (!(ps
->info
.ps
.input_mask
& (1u << i
)))
4201 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VAR0
+ i
];
4202 if (vs_offset
== AC_EXP_PARAM_UNDEFINED
) {
4203 ps_input_cntl
[ps_offset
] = S_028644_OFFSET(0x20);
4208 flat_shade
= !!(ps
->info
.ps
.flat_shaded_mask
& (1u << ps_offset
));
4209 float16
= !!(ps
->info
.ps
.float16_shaded_mask
& (1u << ps_offset
));
4211 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, flat_shade
, float16
);
4216 radeon_set_context_reg_seq(ctx_cs
, R_028644_SPI_PS_INPUT_CNTL_0
, ps_offset
);
4217 for (unsigned i
= 0; i
< ps_offset
; i
++) {
4218 radeon_emit(ctx_cs
, ps_input_cntl
[i
]);
4224 radv_compute_db_shader_control(const struct radv_device
*device
,
4225 const struct radv_pipeline
*pipeline
,
4226 const struct radv_shader_variant
*ps
)
4229 if (ps
->info
.ps
.early_fragment_test
|| !ps
->info
.ps
.writes_memory
)
4230 z_order
= V_02880C_EARLY_Z_THEN_LATE_Z
;
4232 z_order
= V_02880C_LATE_Z
;
4234 bool disable_rbplus
= device
->physical_device
->rad_info
.has_rbplus
&&
4235 !device
->physical_device
->rad_info
.rbplus_allowed
;
4237 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4238 * but this appears to break Project Cars (DXVK). See
4239 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4241 bool mask_export_enable
= ps
->info
.ps
.writes_sample_mask
;
4243 return S_02880C_Z_EXPORT_ENABLE(ps
->info
.ps
.writes_z
) |
4244 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps
->info
.ps
.writes_stencil
) |
4245 S_02880C_KILL_ENABLE(!!ps
->info
.ps
.can_discard
) |
4246 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable
) |
4247 S_02880C_Z_ORDER(z_order
) |
4248 S_02880C_DEPTH_BEFORE_SHADER(ps
->info
.ps
.early_fragment_test
) |
4249 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps
->info
.ps
.post_depth_coverage
) |
4250 S_02880C_EXEC_ON_HIER_FAIL(ps
->info
.ps
.writes_memory
) |
4251 S_02880C_EXEC_ON_NOOP(ps
->info
.ps
.writes_memory
) |
4252 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus
);
4256 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf
*ctx_cs
,
4257 struct radeon_cmdbuf
*cs
,
4258 struct radv_pipeline
*pipeline
)
4260 struct radv_shader_variant
*ps
;
4262 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
4264 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4265 va
= radv_buffer_get_va(ps
->bo
) + ps
->bo_offset
;
4267 radeon_set_sh_reg_seq(cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
4268 radeon_emit(cs
, va
>> 8);
4269 radeon_emit(cs
, S_00B024_MEM_BASE(va
>> 40));
4270 radeon_emit(cs
, ps
->config
.rsrc1
);
4271 radeon_emit(cs
, ps
->config
.rsrc2
);
4273 radeon_set_context_reg(ctx_cs
, R_02880C_DB_SHADER_CONTROL
,
4274 radv_compute_db_shader_control(pipeline
->device
,
4277 radeon_set_context_reg(ctx_cs
, R_0286CC_SPI_PS_INPUT_ENA
,
4278 ps
->config
.spi_ps_input_ena
);
4280 radeon_set_context_reg(ctx_cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
4281 ps
->config
.spi_ps_input_addr
);
4283 radeon_set_context_reg(ctx_cs
, R_0286D8_SPI_PS_IN_CONTROL
,
4284 S_0286D8_NUM_INTERP(ps
->info
.ps
.num_interp
) |
4285 S_0286D8_PS_W32_EN(ps
->info
.wave_size
== 32));
4287 radeon_set_context_reg(ctx_cs
, R_0286E0_SPI_BARYC_CNTL
, pipeline
->graphics
.spi_baryc_cntl
);
4289 radeon_set_context_reg(ctx_cs
, R_028710_SPI_SHADER_Z_FORMAT
,
4290 ac_get_spi_shader_z_format(ps
->info
.ps
.writes_z
,
4291 ps
->info
.ps
.writes_stencil
,
4292 ps
->info
.ps
.writes_sample_mask
));
4294 if (pipeline
->device
->dfsm_allowed
) {
4295 /* optimise this? */
4296 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
4297 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
4302 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf
*ctx_cs
,
4303 struct radv_pipeline
*pipeline
)
4305 if (pipeline
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4306 pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
4309 unsigned vtx_reuse_depth
= 30;
4310 if (radv_pipeline_has_tess(pipeline
) &&
4311 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.tes
.spacing
== TESS_SPACING_FRACTIONAL_ODD
) {
4312 vtx_reuse_depth
= 14;
4314 radeon_set_context_reg(ctx_cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
4315 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth
));
4319 radv_compute_vgt_shader_stages_en(const struct radv_pipeline
*pipeline
)
4321 uint32_t stages
= 0;
4322 if (radv_pipeline_has_tess(pipeline
)) {
4323 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
4324 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4326 if (radv_pipeline_has_gs(pipeline
))
4327 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
4329 else if (radv_pipeline_has_ngg(pipeline
))
4330 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
4332 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
4333 } else if (radv_pipeline_has_gs(pipeline
)) {
4334 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
4336 } else if (radv_pipeline_has_ngg(pipeline
)) {
4337 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
4340 if (radv_pipeline_has_ngg(pipeline
)) {
4341 stages
|= S_028B54_PRIMGEN_EN(1);
4342 if (pipeline
->streamout_shader
)
4343 stages
|= S_028B54_NGG_WAVE_ID_EN(1);
4344 } else if (radv_pipeline_has_gs(pipeline
)) {
4345 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
4348 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
4349 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4351 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4352 uint8_t hs_size
= 64, gs_size
= 64, vs_size
= 64;
4354 if (radv_pipeline_has_tess(pipeline
))
4355 hs_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.wave_size
;
4357 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
4358 vs_size
= gs_size
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.wave_size
;
4359 if (pipeline
->gs_copy_shader
)
4360 vs_size
= pipeline
->gs_copy_shader
->info
.wave_size
;
4361 } else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
4362 vs_size
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.wave_size
;
4363 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
4364 vs_size
= pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.wave_size
;
4366 if (radv_pipeline_has_ngg(pipeline
))
4369 /* legacy GS only supports Wave64 */
4370 stages
|= S_028B54_HS_W32_EN(hs_size
== 32 ? 1 : 0) |
4371 S_028B54_GS_W32_EN(gs_size
== 32 ? 1 : 0) |
4372 S_028B54_VS_W32_EN(vs_size
== 32 ? 1 : 0);
4379 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4381 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
4382 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
4384 if (!discard_rectangle_info
)
4389 for (unsigned i
= 0; i
< (1u << MAX_DISCARD_RECTANGLES
); ++i
) {
4390 /* Interpret i as a bitmask, and then set the bit in the mask if
4391 * that combination of rectangles in which the pixel is contained
4392 * should pass the cliprect test. */
4393 unsigned relevant_subset
= i
& ((1u << discard_rectangle_info
->discardRectangleCount
) - 1);
4395 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT
&&
4399 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT
&&
4410 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf
*ctx_cs
,
4411 struct radv_pipeline
*pipeline
,
4412 const struct radv_tessellation_state
*tess
)
4414 bool break_wave_at_eoi
= false;
4415 unsigned primgroup_size
;
4416 unsigned vertgroup_size
;
4418 if (radv_pipeline_has_tess(pipeline
)) {
4419 primgroup_size
= tess
->num_patches
; /* must be a multiple of NUM_PATCHES */
4421 } else if (radv_pipeline_has_gs(pipeline
)) {
4422 const struct gfx9_gs_info
*gs_state
=
4423 &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs_ring_info
;
4424 unsigned vgt_gs_onchip_cntl
= gs_state
->vgt_gs_onchip_cntl
;
4425 primgroup_size
= G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl
);
4426 vertgroup_size
= G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl
);
4428 primgroup_size
= 128; /* recommended without a GS and tess */
4432 if (radv_pipeline_has_tess(pipeline
)) {
4433 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4434 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4435 break_wave_at_eoi
= true;
4438 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
,
4439 S_03096C_PRIM_GRP_SIZE(primgroup_size
) |
4440 S_03096C_VERT_GRP_SIZE(vertgroup_size
) |
4441 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4442 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
));
4446 radv_pipeline_generate_pm4(struct radv_pipeline
*pipeline
,
4447 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4448 const struct radv_graphics_pipeline_create_info
*extra
,
4449 const struct radv_blend_state
*blend
,
4450 const struct radv_tessellation_state
*tess
,
4451 unsigned prim
, unsigned gs_out
)
4453 struct radeon_cmdbuf
*ctx_cs
= &pipeline
->ctx_cs
;
4454 struct radeon_cmdbuf
*cs
= &pipeline
->cs
;
4457 ctx_cs
->max_dw
= 256;
4458 cs
->buf
= malloc(4 * (cs
->max_dw
+ ctx_cs
->max_dw
));
4459 ctx_cs
->buf
= cs
->buf
+ cs
->max_dw
;
4461 radv_pipeline_generate_depth_stencil_state(ctx_cs
, pipeline
, pCreateInfo
, extra
);
4462 radv_pipeline_generate_blend_state(ctx_cs
, pipeline
, blend
);
4463 radv_pipeline_generate_raster_state(ctx_cs
, pipeline
, pCreateInfo
);
4464 radv_pipeline_generate_multisample_state(ctx_cs
, pipeline
);
4465 radv_pipeline_generate_vgt_gs_mode(ctx_cs
, pipeline
);
4466 radv_pipeline_generate_vertex_shader(ctx_cs
, cs
, pipeline
, tess
);
4467 radv_pipeline_generate_tess_shaders(ctx_cs
, cs
, pipeline
, tess
);
4468 radv_pipeline_generate_geometry_shader(ctx_cs
, cs
, pipeline
);
4469 radv_pipeline_generate_fragment_shader(ctx_cs
, cs
, pipeline
);
4470 radv_pipeline_generate_ps_inputs(ctx_cs
, pipeline
);
4471 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs
, pipeline
);
4472 radv_pipeline_generate_binning_state(ctx_cs
, pipeline
, pCreateInfo
, blend
);
4474 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&& !radv_pipeline_has_ngg(pipeline
))
4475 gfx10_pipeline_generate_ge_cntl(ctx_cs
, pipeline
, tess
);
4477 radeon_set_context_reg(ctx_cs
, R_028B54_VGT_SHADER_STAGES_EN
, radv_compute_vgt_shader_stages_en(pipeline
));
4479 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4480 radeon_set_uconfig_reg_idx(pipeline
->device
->physical_device
,
4481 cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, prim
);
4483 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
4485 radeon_set_context_reg(ctx_cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, gs_out
);
4487 radeon_set_context_reg(ctx_cs
, R_02820C_PA_SC_CLIPRECT_RULE
, radv_compute_cliprect_rule(pCreateInfo
));
4489 pipeline
->ctx_cs_hash
= _mesa_hash_data(ctx_cs
->buf
, ctx_cs
->cdw
* 4);
4491 assert(ctx_cs
->cdw
<= ctx_cs
->max_dw
);
4492 assert(cs
->cdw
<= cs
->max_dw
);
4495 static struct radv_ia_multi_vgt_param_helpers
4496 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline
*pipeline
,
4497 const struct radv_tessellation_state
*tess
,
4500 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
= {0};
4501 const struct radv_device
*device
= pipeline
->device
;
4503 if (radv_pipeline_has_tess(pipeline
))
4504 ia_multi_vgt_param
.primgroup_size
= tess
->num_patches
;
4505 else if (radv_pipeline_has_gs(pipeline
))
4506 ia_multi_vgt_param
.primgroup_size
= 64;
4508 ia_multi_vgt_param
.primgroup_size
= 128; /* recommended without a GS */
4510 /* GS requirement. */
4511 ia_multi_vgt_param
.partial_es_wave
= false;
4512 if (radv_pipeline_has_gs(pipeline
) && device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4513 if (SI_GS_PER_ES
/ ia_multi_vgt_param
.primgroup_size
>= pipeline
->device
->gs_table_depth
- 3)
4514 ia_multi_vgt_param
.partial_es_wave
= true;
4516 ia_multi_vgt_param
.wd_switch_on_eop
= false;
4517 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4518 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
4519 * 4 shader engines. Set 1 to pass the assertion below.
4520 * The other cases are hardware requirements. */
4521 if (device
->physical_device
->rad_info
.max_se
< 4 ||
4522 prim
== V_008958_DI_PT_POLYGON
||
4523 prim
== V_008958_DI_PT_LINELOOP
||
4524 prim
== V_008958_DI_PT_TRIFAN
||
4525 prim
== V_008958_DI_PT_TRISTRIP_ADJ
||
4526 (pipeline
->graphics
.prim_restart_enable
&&
4527 (device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4528 (prim
!= V_008958_DI_PT_POINTLIST
&&
4529 prim
!= V_008958_DI_PT_LINESTRIP
))))
4530 ia_multi_vgt_param
.wd_switch_on_eop
= true;
4533 ia_multi_vgt_param
.ia_switch_on_eoi
= false;
4534 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.prim_id_input
)
4535 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4536 if (radv_pipeline_has_gs(pipeline
) &&
4537 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.uses_prim_id
)
4538 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4539 if (radv_pipeline_has_tess(pipeline
)) {
4540 /* SWITCH_ON_EOI must be set if PrimID is used. */
4541 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4542 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4543 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4546 ia_multi_vgt_param
.partial_vs_wave
= false;
4547 if (radv_pipeline_has_tess(pipeline
)) {
4548 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4549 if ((device
->physical_device
->rad_info
.family
== CHIP_TAHITI
||
4550 device
->physical_device
->rad_info
.family
== CHIP_PITCAIRN
||
4551 device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
) &&
4552 radv_pipeline_has_gs(pipeline
))
4553 ia_multi_vgt_param
.partial_vs_wave
= true;
4554 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4555 if (device
->physical_device
->rad_info
.has_distributed_tess
) {
4556 if (radv_pipeline_has_gs(pipeline
)) {
4557 if (device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4558 ia_multi_vgt_param
.partial_es_wave
= true;
4560 ia_multi_vgt_param
.partial_vs_wave
= true;
4565 /* Workaround for a VGT hang when strip primitive types are used with
4566 * primitive restart.
4568 if (pipeline
->graphics
.prim_restart_enable
&&
4569 (prim
== V_008958_DI_PT_LINESTRIP
||
4570 prim
== V_008958_DI_PT_TRISTRIP
||
4571 prim
== V_008958_DI_PT_LINESTRIP_ADJ
||
4572 prim
== V_008958_DI_PT_TRISTRIP_ADJ
)) {
4573 ia_multi_vgt_param
.partial_vs_wave
= true;
4576 if (radv_pipeline_has_gs(pipeline
)) {
4577 /* On these chips there is the possibility of a hang if the
4578 * pipeline uses a GS and partial_vs_wave is not set.
4580 * This mostly does not hit 4-SE chips, as those typically set
4581 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4582 * with GS due to another workaround.
4584 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4586 if (device
->physical_device
->rad_info
.family
== CHIP_TONGA
||
4587 device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
4588 device
->physical_device
->rad_info
.family
== CHIP_POLARIS10
||
4589 device
->physical_device
->rad_info
.family
== CHIP_POLARIS11
||
4590 device
->physical_device
->rad_info
.family
== CHIP_POLARIS12
||
4591 device
->physical_device
->rad_info
.family
== CHIP_VEGAM
) {
4592 ia_multi_vgt_param
.partial_vs_wave
= true;
4596 ia_multi_vgt_param
.base
=
4597 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param
.primgroup_size
- 1) |
4598 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4599 S_028AA8_MAX_PRIMGRP_IN_WAVE(device
->physical_device
->rad_info
.chip_class
== GFX8
? 2 : 0) |
4600 S_030960_EN_INST_OPT_BASIC(device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
4601 S_030960_EN_INST_OPT_ADV(device
->physical_device
->rad_info
.chip_class
>= GFX9
);
4603 return ia_multi_vgt_param
;
4608 radv_compute_vertex_input_state(struct radv_pipeline
*pipeline
,
4609 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4611 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
4612 pCreateInfo
->pVertexInputState
;
4613 struct radv_vertex_elements_info
*velems
= &pipeline
->vertex_elements
;
4615 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
4616 const VkVertexInputAttributeDescription
*desc
=
4617 &vi_info
->pVertexAttributeDescriptions
[i
];
4618 unsigned loc
= desc
->location
;
4619 const struct vk_format_description
*format_desc
;
4621 format_desc
= vk_format_description(desc
->format
);
4623 velems
->format_size
[loc
] = format_desc
->block
.bits
/ 8;
4626 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
4627 const VkVertexInputBindingDescription
*desc
=
4628 &vi_info
->pVertexBindingDescriptions
[i
];
4630 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
4631 pipeline
->num_vertex_bindings
=
4632 MAX2(pipeline
->num_vertex_bindings
, desc
->binding
+ 1);
4636 static struct radv_shader_variant
*
4637 radv_pipeline_get_streamout_shader(struct radv_pipeline
*pipeline
)
4641 for (i
= MESA_SHADER_GEOMETRY
; i
>= MESA_SHADER_VERTEX
; i
--) {
4642 struct radv_shader_variant
*shader
=
4643 radv_get_shader(pipeline
, i
);
4645 if (shader
&& shader
->info
.so
.num_outputs
> 0)
4653 radv_secure_compile(struct radv_pipeline
*pipeline
,
4654 struct radv_device
*device
,
4655 const struct radv_pipeline_key
*key
,
4656 const VkPipelineShaderStageCreateInfo
**pStages
,
4657 const VkPipelineCreateFlags flags
,
4658 unsigned num_stages
)
4660 uint8_t allowed_pipeline_hashes
[2][20];
4661 radv_hash_shaders(allowed_pipeline_hashes
[0], pStages
,
4662 pipeline
->layout
, key
, get_hash_flags(device
));
4664 /* Generate the GC copy hash */
4665 memcpy(allowed_pipeline_hashes
[1], allowed_pipeline_hashes
[0], 20);
4666 allowed_pipeline_hashes
[1][0] ^= 1;
4668 uint8_t allowed_hashes
[2][20];
4669 for (unsigned i
= 0; i
< 2; ++i
) {
4670 disk_cache_compute_key(device
->physical_device
->disk_cache
,
4671 allowed_pipeline_hashes
[i
], 20,
4675 /* Do an early exit if all cache entries are already there. */
4676 bool may_need_copy_shader
= pStages
[MESA_SHADER_GEOMETRY
];
4677 void *main_entry
= disk_cache_get(device
->physical_device
->disk_cache
, allowed_hashes
[0], NULL
);
4678 void *copy_entry
= NULL
;
4679 if (may_need_copy_shader
)
4680 copy_entry
= disk_cache_get(device
->physical_device
->disk_cache
, allowed_hashes
[1], NULL
);
4682 bool has_all_cache_entries
= main_entry
&& (!may_need_copy_shader
|| copy_entry
);
4686 if(has_all_cache_entries
)
4689 unsigned process
= 0;
4690 uint8_t sc_threads
= device
->instance
->num_sc_threads
;
4692 mtx_lock(&device
->sc_state
->secure_compile_mutex
);
4693 if (device
->sc_state
->secure_compile_thread_counter
< sc_threads
) {
4694 device
->sc_state
->secure_compile_thread_counter
++;
4695 for (unsigned i
= 0; i
< sc_threads
; i
++) {
4696 if (!device
->sc_state
->secure_compile_processes
[i
].in_use
) {
4697 device
->sc_state
->secure_compile_processes
[i
].in_use
= true;
4702 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
4705 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
4708 int fd_secure_input
= device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
;
4709 int fd_secure_output
= device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
;
4711 /* Write pipeline / shader module out to secure process via pipe */
4712 enum radv_secure_compile_type sc_type
= RADV_SC_TYPE_COMPILE_PIPELINE
;
4713 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
4715 /* Write pipeline layout out to secure process */
4716 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
4717 write(fd_secure_input
, layout
, sizeof(struct radv_pipeline_layout
));
4718 write(fd_secure_input
, &layout
->num_sets
, sizeof(uint32_t));
4719 for (uint32_t set
= 0; set
< layout
->num_sets
; set
++) {
4720 write(fd_secure_input
, &layout
->set
[set
].layout
->layout_size
, sizeof(uint32_t));
4721 write(fd_secure_input
, layout
->set
[set
].layout
, layout
->set
[set
].layout
->layout_size
);
4724 /* Write pipeline key out to secure process */
4725 write(fd_secure_input
, key
, sizeof(struct radv_pipeline_key
));
4727 /* Write pipeline create flags out to secure process */
4728 write(fd_secure_input
, &flags
, sizeof(VkPipelineCreateFlags
));
4730 /* Write stage and shader information out to secure process */
4731 write(fd_secure_input
, &num_stages
, sizeof(uint32_t));
4732 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
4736 /* Write stage out to secure process */
4737 gl_shader_stage stage
= ffs(pStages
[i
]->stage
) - 1;
4738 write(fd_secure_input
, &stage
, sizeof(gl_shader_stage
));
4740 /* Write entry point name out to secure process */
4741 size_t name_size
= strlen(pStages
[i
]->pName
) + 1;
4742 write(fd_secure_input
, &name_size
, sizeof(size_t));
4743 write(fd_secure_input
, pStages
[i
]->pName
, name_size
);
4745 /* Write shader module out to secure process */
4746 struct radv_shader_module
*module
= radv_shader_module_from_handle(pStages
[i
]->module
);
4747 assert(!module
->nir
);
4748 size_t module_size
= sizeof(struct radv_shader_module
) + module
->size
;
4749 write(fd_secure_input
, &module_size
, sizeof(size_t));
4750 write(fd_secure_input
, module
, module_size
);
4752 /* Write specialization info out to secure process */
4753 const VkSpecializationInfo
*specInfo
= pStages
[i
]->pSpecializationInfo
;
4754 bool has_spec_info
= specInfo
? true : false;
4755 write(fd_secure_input
, &has_spec_info
, sizeof(bool));
4757 write(fd_secure_input
, &specInfo
->dataSize
, sizeof(size_t));
4758 write(fd_secure_input
, specInfo
->pData
, specInfo
->dataSize
);
4760 write(fd_secure_input
, &specInfo
->mapEntryCount
, sizeof(uint32_t));
4761 for (uint32_t j
= 0; j
< specInfo
->mapEntryCount
; j
++)
4762 write(fd_secure_input
, &specInfo
->pMapEntries
[j
], sizeof(VkSpecializationMapEntry
));
4766 /* Read the data returned from the secure process */
4767 while (sc_type
!= RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED
) {
4768 if (!radv_sc_read(fd_secure_output
, &sc_type
, sizeof(sc_type
), true))
4769 return VK_ERROR_DEVICE_LOST
;
4771 if (sc_type
== RADV_SC_TYPE_WRITE_DISK_CACHE
) {
4772 assert(device
->physical_device
->disk_cache
);
4774 uint8_t disk_sha1
[20];
4775 if (!radv_sc_read(fd_secure_output
, disk_sha1
, sizeof(uint8_t) * 20, true))
4776 return VK_ERROR_DEVICE_LOST
;
4778 if (memcmp(disk_sha1
, allowed_hashes
[0], 20) &&
4779 memcmp(disk_sha1
, allowed_hashes
[1], 20))
4780 return VK_ERROR_DEVICE_LOST
;
4782 uint32_t entry_size
;
4783 if (!radv_sc_read(fd_secure_output
, &entry_size
, sizeof(uint32_t), true))
4784 return VK_ERROR_DEVICE_LOST
;
4786 struct cache_entry
*entry
= malloc(entry_size
);
4787 if (!radv_sc_read(fd_secure_output
, entry
, entry_size
, true))
4788 return VK_ERROR_DEVICE_LOST
;
4790 disk_cache_put(device
->physical_device
->disk_cache
,
4791 disk_sha1
, entry
, entry_size
,
4795 } else if (sc_type
== RADV_SC_TYPE_READ_DISK_CACHE
) {
4796 uint8_t disk_sha1
[20];
4797 if (!radv_sc_read(fd_secure_output
, disk_sha1
, sizeof(uint8_t) * 20, true))
4798 return VK_ERROR_DEVICE_LOST
;
4800 if (memcmp(disk_sha1
, allowed_hashes
[0], 20) &&
4801 memcmp(disk_sha1
, allowed_hashes
[1], 20))
4802 return VK_ERROR_DEVICE_LOST
;
4805 struct cache_entry
*entry
= (struct cache_entry
*)
4806 disk_cache_get(device
->physical_device
->disk_cache
,
4809 uint8_t found
= entry
? 1 : 0;
4810 write(fd_secure_input
, &found
, sizeof(uint8_t));
4813 write(fd_secure_input
, &size
, sizeof(size_t));
4814 write(fd_secure_input
, entry
, size
);
4821 mtx_lock(&device
->sc_state
->secure_compile_mutex
);
4822 device
->sc_state
->secure_compile_thread_counter
--;
4823 device
->sc_state
->secure_compile_processes
[process
].in_use
= false;
4824 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
4830 radv_pipeline_init(struct radv_pipeline
*pipeline
,
4831 struct radv_device
*device
,
4832 struct radv_pipeline_cache
*cache
,
4833 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4834 const struct radv_graphics_pipeline_create_info
*extra
)
4837 bool has_view_index
= false;
4839 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
4840 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
4841 if (subpass
->view_mask
)
4842 has_view_index
= true;
4844 pipeline
->device
= device
;
4845 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
4846 assert(pipeline
->layout
);
4848 struct radv_blend_state blend
= radv_pipeline_init_blend_state(pipeline
, pCreateInfo
, extra
);
4850 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
4851 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
4852 radv_init_feedback(creation_feedback
);
4854 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
4856 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
4857 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
4858 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
4859 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
4860 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
4861 if(creation_feedback
)
4862 stage_feedbacks
[stage
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[i
];
4865 struct radv_pipeline_key key
= radv_generate_graphics_pipeline_key(pipeline
, pCreateInfo
, &blend
, has_view_index
);
4866 if (radv_device_use_secure_compile(device
->instance
)) {
4867 return radv_secure_compile(pipeline
, device
, &key
, pStages
, pCreateInfo
->flags
, pCreateInfo
->stageCount
);
4869 radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
, pCreateInfo
->flags
, pipeline_feedback
, stage_feedbacks
);
4872 pipeline
->graphics
.spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
4873 radv_pipeline_init_multisample_state(pipeline
, &blend
, pCreateInfo
);
4875 uint32_t prim
= si_translate_prim(pCreateInfo
->pInputAssemblyState
->topology
);
4877 pipeline
->graphics
.can_use_guardband
= radv_prim_can_use_guardband(pCreateInfo
->pInputAssemblyState
->topology
);
4879 if (radv_pipeline_has_gs(pipeline
)) {
4880 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs
.output_prim
);
4881 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4882 } else if (radv_pipeline_has_tess(pipeline
)) {
4883 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.point_mode
)
4884 gs_out
= V_028A6C_OUTPRIM_TYPE_POINTLIST
;
4886 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.primitive_mode
);
4887 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4889 gs_out
= si_conv_prim_to_gs_out(pCreateInfo
->pInputAssemblyState
->topology
);
4891 if (extra
&& extra
->use_rectlist
) {
4892 prim
= V_008958_DI_PT_RECTLIST
;
4893 gs_out
= V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4894 pipeline
->graphics
.can_use_guardband
= true;
4895 if (radv_pipeline_has_ngg(pipeline
))
4896 gs_out
= V_028A6C_VGT_OUT_RECT_V0
;
4898 pipeline
->graphics
.prim_restart_enable
= !!pCreateInfo
->pInputAssemblyState
->primitiveRestartEnable
;
4899 /* prim vertex count will need TESS changes */
4900 pipeline
->graphics
.prim_vertex_count
= prim_size_table
[prim
];
4902 radv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
);
4904 /* Ensure that some export memory is always allocated, for two reasons:
4906 * 1) Correctness: The hardware ignores the EXEC mask if no export
4907 * memory is allocated, so KILL and alpha test do not work correctly
4909 * 2) Performance: Every shader needs at least a NULL export, even when
4910 * it writes no color/depth output. The NULL export instruction
4911 * stalls without this setting.
4913 * Don't add this to CB_SHADER_MASK.
4915 * GFX10 supports pixel shaders without exports by setting both the
4916 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
4917 * instructions if any are present.
4919 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4920 if ((pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX9
||
4921 ps
->info
.ps
.can_discard
) &&
4922 !blend
.spi_shader_col_format
) {
4923 if (!ps
->info
.ps
.writes_z
&&
4924 !ps
->info
.ps
.writes_stencil
&&
4925 !ps
->info
.ps
.writes_sample_mask
)
4926 blend
.spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
4929 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
4930 if (pipeline
->shaders
[i
]) {
4931 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[i
]->info
.need_indirect_descriptor_sets
;
4935 if (radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
4936 struct radv_shader_variant
*gs
=
4937 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4939 calculate_gs_ring_sizes(pipeline
, &gs
->info
.gs_ring_info
);
4942 struct radv_tessellation_state tess
= {0};
4943 if (radv_pipeline_has_tess(pipeline
)) {
4944 if (prim
== V_008958_DI_PT_PATCH
) {
4945 pipeline
->graphics
.prim_vertex_count
.min
= pCreateInfo
->pTessellationState
->patchControlPoints
;
4946 pipeline
->graphics
.prim_vertex_count
.incr
= 1;
4948 tess
= calculate_tess_state(pipeline
, pCreateInfo
);
4951 pipeline
->graphics
.ia_multi_vgt_param
= radv_compute_ia_multi_vgt_param_helpers(pipeline
, &tess
, prim
);
4953 radv_compute_vertex_input_state(pipeline
, pCreateInfo
);
4955 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++)
4956 pipeline
->user_data_0
[i
] = radv_pipeline_stage_to_user_data_0(pipeline
, i
, device
->physical_device
->rad_info
.chip_class
);
4958 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
,
4959 AC_UD_VS_BASE_VERTEX_START_INSTANCE
);
4960 if (loc
->sgpr_idx
!= -1) {
4961 pipeline
->graphics
.vtx_base_sgpr
= pipeline
->user_data_0
[MESA_SHADER_VERTEX
];
4962 pipeline
->graphics
.vtx_base_sgpr
+= loc
->sgpr_idx
* 4;
4963 if (radv_get_shader(pipeline
, MESA_SHADER_VERTEX
)->info
.vs
.needs_draw_id
)
4964 pipeline
->graphics
.vtx_emit_num
= 3;
4966 pipeline
->graphics
.vtx_emit_num
= 2;
4969 /* Find the last vertex shader stage that eventually uses streamout. */
4970 pipeline
->streamout_shader
= radv_pipeline_get_streamout_shader(pipeline
);
4972 result
= radv_pipeline_scratch_init(device
, pipeline
);
4973 radv_pipeline_generate_pm4(pipeline
, pCreateInfo
, extra
, &blend
, &tess
, prim
, gs_out
);
4979 radv_graphics_pipeline_create(
4981 VkPipelineCache _cache
,
4982 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4983 const struct radv_graphics_pipeline_create_info
*extra
,
4984 const VkAllocationCallbacks
*pAllocator
,
4985 VkPipeline
*pPipeline
)
4987 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4988 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
4989 struct radv_pipeline
*pipeline
;
4992 pipeline
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
4993 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4994 if (pipeline
== NULL
)
4995 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4997 result
= radv_pipeline_init(pipeline
, device
, cache
,
4998 pCreateInfo
, extra
);
4999 if (result
!= VK_SUCCESS
) {
5000 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5004 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5009 VkResult
radv_CreateGraphicsPipelines(
5011 VkPipelineCache pipelineCache
,
5013 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
5014 const VkAllocationCallbacks
* pAllocator
,
5015 VkPipeline
* pPipelines
)
5017 VkResult result
= VK_SUCCESS
;
5020 for (; i
< count
; i
++) {
5022 r
= radv_graphics_pipeline_create(_device
,
5025 NULL
, pAllocator
, &pPipelines
[i
]);
5026 if (r
!= VK_SUCCESS
) {
5028 pPipelines
[i
] = VK_NULL_HANDLE
;
5037 radv_compute_generate_pm4(struct radv_pipeline
*pipeline
)
5039 struct radv_shader_variant
*compute_shader
;
5040 struct radv_device
*device
= pipeline
->device
;
5041 unsigned threads_per_threadgroup
;
5042 unsigned threadgroups_per_cu
= 1;
5043 unsigned waves_per_threadgroup
;
5044 unsigned max_waves_per_sh
= 0;
5047 pipeline
->cs
.max_dw
= device
->physical_device
->rad_info
.chip_class
>= GFX10
? 22 : 20;
5048 pipeline
->cs
.buf
= malloc(pipeline
->cs
.max_dw
* 4);
5050 compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
5051 va
= radv_buffer_get_va(compute_shader
->bo
) + compute_shader
->bo_offset
;
5053 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B830_COMPUTE_PGM_LO
, 2);
5054 radeon_emit(&pipeline
->cs
, va
>> 8);
5055 radeon_emit(&pipeline
->cs
, S_00B834_DATA(va
>> 40));
5057 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
5058 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc1
);
5059 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc2
);
5060 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
5061 radeon_set_sh_reg(&pipeline
->cs
, R_00B8A0_COMPUTE_PGM_RSRC3
, compute_shader
->config
.rsrc3
);
5064 /* Calculate best compute resource limits. */
5065 threads_per_threadgroup
= compute_shader
->info
.cs
.block_size
[0] *
5066 compute_shader
->info
.cs
.block_size
[1] *
5067 compute_shader
->info
.cs
.block_size
[2];
5068 waves_per_threadgroup
= DIV_ROUND_UP(threads_per_threadgroup
,
5069 compute_shader
->info
.wave_size
);
5071 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
5072 waves_per_threadgroup
== 1)
5073 threadgroups_per_cu
= 2;
5075 radeon_set_sh_reg(&pipeline
->cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
5076 ac_get_compute_resource_limits(&device
->physical_device
->rad_info
,
5077 waves_per_threadgroup
,
5079 threadgroups_per_cu
));
5081 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
5082 radeon_emit(&pipeline
->cs
,
5083 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]));
5084 radeon_emit(&pipeline
->cs
,
5085 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]));
5086 radeon_emit(&pipeline
->cs
,
5087 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]));
5089 assert(pipeline
->cs
.cdw
<= pipeline
->cs
.max_dw
);
5092 static struct radv_pipeline_key
5093 radv_generate_compute_pipeline_key(struct radv_pipeline
*pipeline
,
5094 const VkComputePipelineCreateInfo
*pCreateInfo
)
5096 const VkPipelineShaderStageCreateInfo
*stage
= &pCreateInfo
->stage
;
5097 struct radv_pipeline_key key
;
5098 memset(&key
, 0, sizeof(key
));
5100 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
5101 key
.optimisations_disabled
= 1;
5103 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*subgroup_size
=
5104 vk_find_struct_const(stage
->pNext
,
5105 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT
);
5107 if (subgroup_size
) {
5108 assert(subgroup_size
->requiredSubgroupSize
== 32 ||
5109 subgroup_size
->requiredSubgroupSize
== 64);
5110 key
.compute_subgroup_size
= subgroup_size
->requiredSubgroupSize
;
5116 static VkResult
radv_compute_pipeline_create(
5118 VkPipelineCache _cache
,
5119 const VkComputePipelineCreateInfo
* pCreateInfo
,
5120 const VkAllocationCallbacks
* pAllocator
,
5121 VkPipeline
* pPipeline
)
5123 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5124 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
5125 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
5126 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
5127 struct radv_pipeline
*pipeline
;
5130 pipeline
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
5131 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5132 if (pipeline
== NULL
)
5133 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5135 pipeline
->device
= device
;
5136 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
5137 assert(pipeline
->layout
);
5139 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
5140 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
5141 radv_init_feedback(creation_feedback
);
5143 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
5144 if (creation_feedback
)
5145 stage_feedbacks
[MESA_SHADER_COMPUTE
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[0];
5147 pStages
[MESA_SHADER_COMPUTE
] = &pCreateInfo
->stage
;
5149 struct radv_pipeline_key key
=
5150 radv_generate_compute_pipeline_key(pipeline
, pCreateInfo
);
5152 if (radv_device_use_secure_compile(device
->instance
)) {
5153 result
= radv_secure_compile(pipeline
, device
, &key
, pStages
, pCreateInfo
->flags
, 1);
5154 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5158 radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
, pCreateInfo
->flags
, pipeline_feedback
, stage_feedbacks
);
5161 pipeline
->user_data_0
[MESA_SHADER_COMPUTE
] = radv_pipeline_stage_to_user_data_0(pipeline
, MESA_SHADER_COMPUTE
, device
->physical_device
->rad_info
.chip_class
);
5162 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.need_indirect_descriptor_sets
;
5163 result
= radv_pipeline_scratch_init(device
, pipeline
);
5164 if (result
!= VK_SUCCESS
) {
5165 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5169 radv_compute_generate_pm4(pipeline
);
5171 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5176 VkResult
radv_CreateComputePipelines(
5178 VkPipelineCache pipelineCache
,
5180 const VkComputePipelineCreateInfo
* pCreateInfos
,
5181 const VkAllocationCallbacks
* pAllocator
,
5182 VkPipeline
* pPipelines
)
5184 VkResult result
= VK_SUCCESS
;
5187 for (; i
< count
; i
++) {
5189 r
= radv_compute_pipeline_create(_device
, pipelineCache
,
5191 pAllocator
, &pPipelines
[i
]);
5192 if (r
!= VK_SUCCESS
) {
5194 pPipelines
[i
] = VK_NULL_HANDLE
;
5202 static uint32_t radv_get_executable_count(const struct radv_pipeline
*pipeline
)
5205 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5206 if (!pipeline
->shaders
[i
])
5209 if (i
== MESA_SHADER_GEOMETRY
&&
5210 !radv_pipeline_has_ngg(pipeline
)) {
5220 static struct radv_shader_variant
*
5221 radv_get_shader_from_executable_index(const struct radv_pipeline
*pipeline
, int index
, gl_shader_stage
*stage
)
5223 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5224 if (!pipeline
->shaders
[i
])
5228 return pipeline
->shaders
[i
];
5233 if (i
== MESA_SHADER_GEOMETRY
&&
5234 !radv_pipeline_has_ngg(pipeline
)) {
5237 return pipeline
->gs_copy_shader
;
5247 /* Basically strlcpy (which does not exist on linux) specialized for
5249 static void desc_copy(char *desc
, const char *src
) {
5250 int len
= strlen(src
);
5251 assert(len
< VK_MAX_DESCRIPTION_SIZE
);
5252 memcpy(desc
, src
, len
);
5253 memset(desc
+ len
, 0, VK_MAX_DESCRIPTION_SIZE
- len
);
5256 VkResult
radv_GetPipelineExecutablePropertiesKHR(
5258 const VkPipelineInfoKHR
* pPipelineInfo
,
5259 uint32_t* pExecutableCount
,
5260 VkPipelineExecutablePropertiesKHR
* pProperties
)
5262 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pPipelineInfo
->pipeline
);
5263 const uint32_t total_count
= radv_get_executable_count(pipeline
);
5266 *pExecutableCount
= total_count
;
5270 const uint32_t count
= MIN2(total_count
, *pExecutableCount
);
5271 for (unsigned i
= 0, executable_idx
= 0;
5272 i
< MESA_SHADER_STAGES
&& executable_idx
< count
; ++i
) {
5273 if (!pipeline
->shaders
[i
])
5275 pProperties
[executable_idx
].stages
= mesa_to_vk_shader_stage(i
);
5276 const char *name
= NULL
;
5277 const char *description
= NULL
;
5279 case MESA_SHADER_VERTEX
:
5280 name
= "Vertex Shader";
5281 description
= "Vulkan Vertex Shader";
5283 case MESA_SHADER_TESS_CTRL
:
5284 if (!pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5285 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5286 name
= "Vertex + Tessellation Control Shaders";
5287 description
= "Combined Vulkan Vertex and Tessellation Control Shaders";
5289 name
= "Tessellation Control Shader";
5290 description
= "Vulkan Tessellation Control Shader";
5293 case MESA_SHADER_TESS_EVAL
:
5294 name
= "Tessellation Evaluation Shader";
5295 description
= "Vulkan Tessellation Evaluation Shader";
5297 case MESA_SHADER_GEOMETRY
:
5298 if (radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]) {
5299 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
;
5300 name
= "Tessellation Evaluation + Geometry Shaders";
5301 description
= "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5302 } else if (!radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5303 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5304 name
= "Vertex + Geometry Shader";
5305 description
= "Combined Vulkan Vertex and Geometry Shaders";
5307 name
= "Geometry Shader";
5308 description
= "Vulkan Geometry Shader";
5311 case MESA_SHADER_FRAGMENT
:
5312 name
= "Fragment Shader";
5313 description
= "Vulkan Fragment Shader";
5315 case MESA_SHADER_COMPUTE
:
5316 name
= "Compute Shader";
5317 description
= "Vulkan Compute Shader";
5321 desc_copy(pProperties
[executable_idx
].name
, name
);
5322 desc_copy(pProperties
[executable_idx
].description
, description
);
5325 if (i
== MESA_SHADER_GEOMETRY
&&
5326 !radv_pipeline_has_ngg(pipeline
)) {
5327 assert(pipeline
->gs_copy_shader
);
5328 if (executable_idx
>= count
)
5331 pProperties
[executable_idx
].stages
= VK_SHADER_STAGE_GEOMETRY_BIT
;
5332 desc_copy(pProperties
[executable_idx
].name
, "GS Copy Shader");
5333 desc_copy(pProperties
[executable_idx
].description
,
5334 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5340 for (unsigned i
= 0; i
< count
; ++i
)
5341 pProperties
[i
].subgroupSize
= 64;
5343 VkResult result
= *pExecutableCount
< total_count
? VK_INCOMPLETE
: VK_SUCCESS
;
5344 *pExecutableCount
= count
;
5348 VkResult
radv_GetPipelineExecutableStatisticsKHR(
5350 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5351 uint32_t* pStatisticCount
,
5352 VkPipelineExecutableStatisticKHR
* pStatistics
)
5354 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5355 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5356 gl_shader_stage stage
;
5357 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5359 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
5360 unsigned lds_increment
= chip_class
>= GFX7
? 512 : 256;
5361 unsigned max_waves
= radv_get_max_waves(device
, shader
, stage
);
5363 VkPipelineExecutableStatisticKHR
*s
= pStatistics
;
5364 VkPipelineExecutableStatisticKHR
*end
= s
+ (pStatistics
? *pStatisticCount
: 0);
5365 VkResult result
= VK_SUCCESS
;
5368 desc_copy(s
->name
, "SGPRs");
5369 desc_copy(s
->description
, "Number of SGPR registers allocated per subgroup");
5370 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5371 s
->value
.u64
= shader
->config
.num_sgprs
;
5376 desc_copy(s
->name
, "VGPRs");
5377 desc_copy(s
->description
, "Number of VGPR registers allocated per subgroup");
5378 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5379 s
->value
.u64
= shader
->config
.num_vgprs
;
5384 desc_copy(s
->name
, "Spilled SGPRs");
5385 desc_copy(s
->description
, "Number of SGPR registers spilled per subgroup");
5386 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5387 s
->value
.u64
= shader
->config
.spilled_sgprs
;
5392 desc_copy(s
->name
, "Spilled VGPRs");
5393 desc_copy(s
->description
, "Number of VGPR registers spilled per subgroup");
5394 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5395 s
->value
.u64
= shader
->config
.spilled_vgprs
;
5400 desc_copy(s
->name
, "PrivMem VGPRs");
5401 desc_copy(s
->description
, "Number of VGPRs stored in private memory per subgroup");
5402 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5403 s
->value
.u64
= shader
->info
.private_mem_vgprs
;
5408 desc_copy(s
->name
, "Code size");
5409 desc_copy(s
->description
, "Code size in bytes");
5410 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5411 s
->value
.u64
= shader
->exec_size
;
5416 desc_copy(s
->name
, "LDS size");
5417 desc_copy(s
->description
, "LDS size in bytes per workgroup");
5418 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5419 s
->value
.u64
= shader
->config
.lds_size
* lds_increment
;
5424 desc_copy(s
->name
, "Scratch size");
5425 desc_copy(s
->description
, "Private memory in bytes per subgroup");
5426 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5427 s
->value
.u64
= shader
->config
.scratch_bytes_per_wave
;
5432 desc_copy(s
->name
, "Subgroups per SIMD");
5433 desc_copy(s
->description
, "The maximum number of subgroups in flight on a SIMD unit");
5434 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5435 s
->value
.u64
= max_waves
;
5440 *pStatisticCount
= s
- pStatistics
;
5442 *pStatisticCount
= end
- pStatistics
;
5443 result
= VK_INCOMPLETE
;
5445 *pStatisticCount
= s
- pStatistics
;
5451 static VkResult
radv_copy_representation(void *data
, size_t *data_size
, const char *src
)
5453 size_t total_size
= strlen(src
) + 1;
5456 *data_size
= total_size
;
5460 size_t size
= MIN2(total_size
, *data_size
);
5462 memcpy(data
, src
, size
);
5464 *((char*)data
+ size
- 1) = 0;
5465 return size
< total_size
? VK_INCOMPLETE
: VK_SUCCESS
;
5468 VkResult
radv_GetPipelineExecutableInternalRepresentationsKHR(
5470 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5471 uint32_t* pInternalRepresentationCount
,
5472 VkPipelineExecutableInternalRepresentationKHR
* pInternalRepresentations
)
5474 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5475 gl_shader_stage stage
;
5476 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5478 VkPipelineExecutableInternalRepresentationKHR
*p
= pInternalRepresentations
;
5479 VkPipelineExecutableInternalRepresentationKHR
*end
= p
+ (pInternalRepresentations
? *pInternalRepresentationCount
: 0);
5480 VkResult result
= VK_SUCCESS
;
5484 desc_copy(p
->name
, "NIR Shader(s)");
5485 desc_copy(p
->description
, "The optimized NIR shader(s)");
5486 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->nir_string
) != VK_SUCCESS
)
5487 result
= VK_INCOMPLETE
;
5494 if (shader
->aco_used
) {
5495 desc_copy(p
->name
, "ACO IR");
5496 desc_copy(p
->description
, "The ACO IR after some optimizations");
5498 desc_copy(p
->name
, "LLVM IR");
5499 desc_copy(p
->description
, "The LLVM IR after some optimizations");
5501 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->ir_string
) != VK_SUCCESS
)
5502 result
= VK_INCOMPLETE
;
5509 desc_copy(p
->name
, "Assembly");
5510 desc_copy(p
->description
, "Final Assembly");
5511 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->disasm_string
) != VK_SUCCESS
)
5512 result
= VK_INCOMPLETE
;
5516 if (!pInternalRepresentations
)
5517 *pInternalRepresentationCount
= p
- pInternalRepresentations
;
5519 result
= VK_INCOMPLETE
;
5520 *pInternalRepresentationCount
= end
- pInternalRepresentations
;
5522 *pInternalRepresentationCount
= p
- pInternalRepresentations
;