2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
34 #include "radv_shader.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
41 #include <llvm-c/Core.h>
42 #include <llvm-c/TargetMachine.h>
45 #include "ac_binary.h"
46 #include "ac_llvm_util.h"
47 #include "ac_nir_to_llvm.h"
48 #include "vk_format.h"
49 #include "util/debug.h"
50 #include "ac_exp_param.h"
51 #include "ac_shader_util.h"
52 #include "main/menums.h"
54 struct radv_blend_state
{
55 uint32_t blend_enable_4bit
;
56 uint32_t need_src_alpha
;
58 uint32_t cb_color_control
;
59 uint32_t cb_target_mask
;
60 uint32_t cb_target_enabled_4bit
;
61 uint32_t sx_mrt_blend_opt
[8];
62 uint32_t cb_blend_control
[8];
64 uint32_t spi_shader_col_format
;
65 uint32_t cb_shader_mask
;
66 uint32_t db_alpha_to_mask
;
68 uint32_t commutative_4bit
;
70 bool single_cb_enable
;
71 bool mrt0_is_dual_src
;
74 struct radv_dsa_order_invariance
{
75 /* Whether the final result in Z/S buffers is guaranteed to be
76 * invariant under changes to the order in which fragments arrive.
80 /* Whether the set of fragments that pass the combined Z/S test is
81 * guaranteed to be invariant under changes to the order in which
87 struct radv_tessellation_state
{
88 uint32_t ls_hs_config
;
94 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
)
96 struct radv_shader_variant
*variant
= NULL
;
97 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
98 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
99 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
100 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
101 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
102 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
105 return variant
->info
.is_ngg
;
108 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
)
110 if (!radv_pipeline_has_gs(pipeline
))
113 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
114 * On GFX10, it might be required in rare cases if it's not possible to
117 if (radv_pipeline_has_ngg(pipeline
))
120 assert(pipeline
->gs_copy_shader
);
125 radv_pipeline_destroy(struct radv_device
*device
,
126 struct radv_pipeline
*pipeline
,
127 const VkAllocationCallbacks
* allocator
)
129 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
130 if (pipeline
->shaders
[i
])
131 radv_shader_variant_destroy(device
, pipeline
->shaders
[i
]);
133 if (pipeline
->gs_copy_shader
)
134 radv_shader_variant_destroy(device
, pipeline
->gs_copy_shader
);
137 free(pipeline
->cs
.buf
);
138 vk_free2(&device
->alloc
, allocator
, pipeline
);
141 void radv_DestroyPipeline(
143 VkPipeline _pipeline
,
144 const VkAllocationCallbacks
* pAllocator
)
146 RADV_FROM_HANDLE(radv_device
, device
, _device
);
147 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
152 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
155 static uint32_t get_hash_flags(struct radv_device
*device
)
157 uint32_t hash_flags
= 0;
159 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_NGG
)
160 hash_flags
|= RADV_HASH_SHADER_NO_NGG
;
161 if (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
)
162 hash_flags
|= RADV_HASH_SHADER_SISCHED
;
163 if (device
->physical_device
->cs_wave_size
== 32)
164 hash_flags
|= RADV_HASH_SHADER_CS_WAVE32
;
165 if (device
->physical_device
->ps_wave_size
== 32)
166 hash_flags
|= RADV_HASH_SHADER_PS_WAVE32
;
167 if (device
->physical_device
->ge_wave_size
== 32)
168 hash_flags
|= RADV_HASH_SHADER_GE_WAVE32
;
169 if (device
->physical_device
->use_aco
)
170 hash_flags
|= RADV_HASH_SHADER_ACO
;
175 radv_pipeline_scratch_init(struct radv_device
*device
,
176 struct radv_pipeline
*pipeline
)
178 unsigned scratch_bytes_per_wave
= 0;
179 unsigned max_waves
= 0;
180 unsigned min_waves
= 1;
182 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
183 if (pipeline
->shaders
[i
] &&
184 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
) {
185 unsigned max_stage_waves
= device
->scratch_waves
;
187 scratch_bytes_per_wave
= MAX2(scratch_bytes_per_wave
,
188 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
);
190 max_stage_waves
= MIN2(max_stage_waves
,
191 4 * device
->physical_device
->rad_info
.num_good_compute_units
*
192 (256 / pipeline
->shaders
[i
]->config
.num_vgprs
));
193 max_waves
= MAX2(max_waves
, max_stage_waves
);
197 if (pipeline
->shaders
[MESA_SHADER_COMPUTE
]) {
198 unsigned group_size
= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[0] *
199 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[1] *
200 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[2];
201 min_waves
= MAX2(min_waves
, round_up_u32(group_size
, 64));
204 pipeline
->scratch_bytes_per_wave
= scratch_bytes_per_wave
;
205 pipeline
->max_waves
= max_waves
;
209 static uint32_t si_translate_blend_logic_op(VkLogicOp op
)
212 case VK_LOGIC_OP_CLEAR
:
213 return V_028808_ROP3_CLEAR
;
214 case VK_LOGIC_OP_AND
:
215 return V_028808_ROP3_AND
;
216 case VK_LOGIC_OP_AND_REVERSE
:
217 return V_028808_ROP3_AND_REVERSE
;
218 case VK_LOGIC_OP_COPY
:
219 return V_028808_ROP3_COPY
;
220 case VK_LOGIC_OP_AND_INVERTED
:
221 return V_028808_ROP3_AND_INVERTED
;
222 case VK_LOGIC_OP_NO_OP
:
223 return V_028808_ROP3_NO_OP
;
224 case VK_LOGIC_OP_XOR
:
225 return V_028808_ROP3_XOR
;
227 return V_028808_ROP3_OR
;
228 case VK_LOGIC_OP_NOR
:
229 return V_028808_ROP3_NOR
;
230 case VK_LOGIC_OP_EQUIVALENT
:
231 return V_028808_ROP3_EQUIVALENT
;
232 case VK_LOGIC_OP_INVERT
:
233 return V_028808_ROP3_INVERT
;
234 case VK_LOGIC_OP_OR_REVERSE
:
235 return V_028808_ROP3_OR_REVERSE
;
236 case VK_LOGIC_OP_COPY_INVERTED
:
237 return V_028808_ROP3_COPY_INVERTED
;
238 case VK_LOGIC_OP_OR_INVERTED
:
239 return V_028808_ROP3_OR_INVERTED
;
240 case VK_LOGIC_OP_NAND
:
241 return V_028808_ROP3_NAND
;
242 case VK_LOGIC_OP_SET
:
243 return V_028808_ROP3_SET
;
245 unreachable("Unhandled logic op");
250 static uint32_t si_translate_blend_function(VkBlendOp op
)
253 case VK_BLEND_OP_ADD
:
254 return V_028780_COMB_DST_PLUS_SRC
;
255 case VK_BLEND_OP_SUBTRACT
:
256 return V_028780_COMB_SRC_MINUS_DST
;
257 case VK_BLEND_OP_REVERSE_SUBTRACT
:
258 return V_028780_COMB_DST_MINUS_SRC
;
259 case VK_BLEND_OP_MIN
:
260 return V_028780_COMB_MIN_DST_SRC
;
261 case VK_BLEND_OP_MAX
:
262 return V_028780_COMB_MAX_DST_SRC
;
268 static uint32_t si_translate_blend_factor(VkBlendFactor factor
)
271 case VK_BLEND_FACTOR_ZERO
:
272 return V_028780_BLEND_ZERO
;
273 case VK_BLEND_FACTOR_ONE
:
274 return V_028780_BLEND_ONE
;
275 case VK_BLEND_FACTOR_SRC_COLOR
:
276 return V_028780_BLEND_SRC_COLOR
;
277 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
278 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
279 case VK_BLEND_FACTOR_DST_COLOR
:
280 return V_028780_BLEND_DST_COLOR
;
281 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
282 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
283 case VK_BLEND_FACTOR_SRC_ALPHA
:
284 return V_028780_BLEND_SRC_ALPHA
;
285 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
286 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
287 case VK_BLEND_FACTOR_DST_ALPHA
:
288 return V_028780_BLEND_DST_ALPHA
;
289 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
290 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
291 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
292 return V_028780_BLEND_CONSTANT_COLOR
;
293 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
294 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
295 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
296 return V_028780_BLEND_CONSTANT_ALPHA
;
297 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
298 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
299 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
300 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
301 case VK_BLEND_FACTOR_SRC1_COLOR
:
302 return V_028780_BLEND_SRC1_COLOR
;
303 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
304 return V_028780_BLEND_INV_SRC1_COLOR
;
305 case VK_BLEND_FACTOR_SRC1_ALPHA
:
306 return V_028780_BLEND_SRC1_ALPHA
;
307 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
308 return V_028780_BLEND_INV_SRC1_ALPHA
;
314 static uint32_t si_translate_blend_opt_function(VkBlendOp op
)
317 case VK_BLEND_OP_ADD
:
318 return V_028760_OPT_COMB_ADD
;
319 case VK_BLEND_OP_SUBTRACT
:
320 return V_028760_OPT_COMB_SUBTRACT
;
321 case VK_BLEND_OP_REVERSE_SUBTRACT
:
322 return V_028760_OPT_COMB_REVSUBTRACT
;
323 case VK_BLEND_OP_MIN
:
324 return V_028760_OPT_COMB_MIN
;
325 case VK_BLEND_OP_MAX
:
326 return V_028760_OPT_COMB_MAX
;
328 return V_028760_OPT_COMB_BLEND_DISABLED
;
332 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor
, bool is_alpha
)
335 case VK_BLEND_FACTOR_ZERO
:
336 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
337 case VK_BLEND_FACTOR_ONE
:
338 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
339 case VK_BLEND_FACTOR_SRC_COLOR
:
340 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
341 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
342 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
343 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
344 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
345 case VK_BLEND_FACTOR_SRC_ALPHA
:
346 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
347 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
348 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
349 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
350 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
351 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
353 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
358 * Get rid of DST in the blend factors by commuting the operands:
359 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
361 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
362 unsigned *dst_factor
, unsigned expected_dst
,
363 unsigned replacement_src
)
365 if (*src_factor
== expected_dst
&&
366 *dst_factor
== VK_BLEND_FACTOR_ZERO
) {
367 *src_factor
= VK_BLEND_FACTOR_ZERO
;
368 *dst_factor
= replacement_src
;
370 /* Commuting the operands requires reversing subtractions. */
371 if (*func
== VK_BLEND_OP_SUBTRACT
)
372 *func
= VK_BLEND_OP_REVERSE_SUBTRACT
;
373 else if (*func
== VK_BLEND_OP_REVERSE_SUBTRACT
)
374 *func
= VK_BLEND_OP_SUBTRACT
;
378 static bool si_blend_factor_uses_dst(unsigned factor
)
380 return factor
== VK_BLEND_FACTOR_DST_COLOR
||
381 factor
== VK_BLEND_FACTOR_DST_ALPHA
||
382 factor
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
383 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
||
384 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
;
387 static bool is_dual_src(VkBlendFactor factor
)
390 case VK_BLEND_FACTOR_SRC1_COLOR
:
391 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
392 case VK_BLEND_FACTOR_SRC1_ALPHA
:
393 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
400 static unsigned si_choose_spi_color_format(VkFormat vk_format
,
402 bool blend_need_alpha
)
404 const struct vk_format_description
*desc
= vk_format_description(vk_format
);
405 unsigned format
, ntype
, swap
;
407 /* Alpha is needed for alpha-to-coverage.
408 * Blending may be with or without alpha.
410 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
411 unsigned alpha
= 0; /* exports alpha, but may not support blending */
412 unsigned blend
= 0; /* supports blending, but may not export alpha */
413 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
415 format
= radv_translate_colorformat(vk_format
);
416 ntype
= radv_translate_color_numformat(vk_format
, desc
,
417 vk_format_get_first_non_void_channel(vk_format
));
418 swap
= radv_translate_colorswap(vk_format
, false);
420 /* Choose the SPI color formats. These are required values for Stoney/RB+.
421 * Other chips have multiple choices, though they are not necessarily better.
424 case V_028C70_COLOR_5_6_5
:
425 case V_028C70_COLOR_1_5_5_5
:
426 case V_028C70_COLOR_5_5_5_1
:
427 case V_028C70_COLOR_4_4_4_4
:
428 case V_028C70_COLOR_10_11_11
:
429 case V_028C70_COLOR_11_11_10
:
430 case V_028C70_COLOR_8
:
431 case V_028C70_COLOR_8_8
:
432 case V_028C70_COLOR_8_8_8_8
:
433 case V_028C70_COLOR_10_10_10_2
:
434 case V_028C70_COLOR_2_10_10_10
:
435 if (ntype
== V_028C70_NUMBER_UINT
)
436 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
437 else if (ntype
== V_028C70_NUMBER_SINT
)
438 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
440 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
443 case V_028C70_COLOR_16
:
444 case V_028C70_COLOR_16_16
:
445 case V_028C70_COLOR_16_16_16_16
:
446 if (ntype
== V_028C70_NUMBER_UNORM
||
447 ntype
== V_028C70_NUMBER_SNORM
) {
448 /* UNORM16 and SNORM16 don't support blending */
449 if (ntype
== V_028C70_NUMBER_UNORM
)
450 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
452 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
454 /* Use 32 bits per channel for blending. */
455 if (format
== V_028C70_COLOR_16
) {
456 if (swap
== V_028C70_SWAP_STD
) { /* R */
457 blend
= V_028714_SPI_SHADER_32_R
;
458 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
459 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
460 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
463 } else if (format
== V_028C70_COLOR_16_16
) {
464 if (swap
== V_028C70_SWAP_STD
) { /* RG */
465 blend
= V_028714_SPI_SHADER_32_GR
;
466 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
467 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
468 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
471 } else /* 16_16_16_16 */
472 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
473 } else if (ntype
== V_028C70_NUMBER_UINT
)
474 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
475 else if (ntype
== V_028C70_NUMBER_SINT
)
476 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
477 else if (ntype
== V_028C70_NUMBER_FLOAT
)
478 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
483 case V_028C70_COLOR_32
:
484 if (swap
== V_028C70_SWAP_STD
) { /* R */
485 blend
= normal
= V_028714_SPI_SHADER_32_R
;
486 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
487 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
488 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
493 case V_028C70_COLOR_32_32
:
494 if (swap
== V_028C70_SWAP_STD
) { /* RG */
495 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
496 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
497 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
498 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
503 case V_028C70_COLOR_32_32_32_32
:
504 case V_028C70_COLOR_8_24
:
505 case V_028C70_COLOR_24_8
:
506 case V_028C70_COLOR_X24_8_32_FLOAT
:
507 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
511 unreachable("unhandled blend format");
514 if (blend_enable
&& blend_need_alpha
)
516 else if(blend_need_alpha
)
518 else if(blend_enable
)
525 radv_pipeline_compute_spi_color_formats(struct radv_pipeline
*pipeline
,
526 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
527 struct radv_blend_state
*blend
)
529 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
530 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
531 unsigned col_format
= 0;
532 unsigned num_targets
;
534 for (unsigned i
= 0; i
< (blend
->single_cb_enable
? 1 : subpass
->color_count
); ++i
) {
537 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
538 cf
= V_028714_SPI_SHADER_ZERO
;
540 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
542 blend
->blend_enable_4bit
& (0xfu
<< (i
* 4));
544 cf
= si_choose_spi_color_format(attachment
->format
,
546 blend
->need_src_alpha
& (1 << i
));
549 col_format
|= cf
<< (4 * i
);
552 if (!(col_format
& 0xf) && blend
->need_src_alpha
& (1 << 0)) {
553 /* When a subpass doesn't have any color attachments, write the
554 * alpha channel of MRT0 when alpha coverage is enabled because
555 * the depth attachment needs it.
557 col_format
|= V_028714_SPI_SHADER_32_AR
;
560 /* If the i-th target format is set, all previous target formats must
561 * be non-zero to avoid hangs.
563 num_targets
= (util_last_bit(col_format
) + 3) / 4;
564 for (unsigned i
= 0; i
< num_targets
; i
++) {
565 if (!(col_format
& (0xf << (i
* 4)))) {
566 col_format
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
570 /* The output for dual source blending should have the same format as
573 if (blend
->mrt0_is_dual_src
)
574 col_format
|= (col_format
& 0xf) << 4;
576 blend
->cb_shader_mask
= ac_get_cb_shader_mask(col_format
);
577 blend
->spi_shader_col_format
= col_format
;
581 format_is_int8(VkFormat format
)
583 const struct vk_format_description
*desc
= vk_format_description(format
);
584 int channel
= vk_format_get_first_non_void_channel(format
);
586 return channel
>= 0 && desc
->channel
[channel
].pure_integer
&&
587 desc
->channel
[channel
].size
== 8;
591 format_is_int10(VkFormat format
)
593 const struct vk_format_description
*desc
= vk_format_description(format
);
595 if (desc
->nr_channels
!= 4)
597 for (unsigned i
= 0; i
< 4; i
++) {
598 if (desc
->channel
[i
].pure_integer
&& desc
->channel
[i
].size
== 10)
605 * Ordered so that for each i,
606 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
608 const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
] = {
609 VK_FORMAT_R32_SFLOAT
,
610 VK_FORMAT_R32G32_SFLOAT
,
611 VK_FORMAT_R8G8B8A8_UNORM
,
612 VK_FORMAT_R16G16B16A16_UNORM
,
613 VK_FORMAT_R16G16B16A16_SNORM
,
614 VK_FORMAT_R16G16B16A16_UINT
,
615 VK_FORMAT_R16G16B16A16_SINT
,
616 VK_FORMAT_R32G32B32A32_SFLOAT
,
617 VK_FORMAT_R8G8B8A8_UINT
,
618 VK_FORMAT_R8G8B8A8_SINT
,
619 VK_FORMAT_A2R10G10B10_UINT_PACK32
,
620 VK_FORMAT_A2R10G10B10_SINT_PACK32
,
623 unsigned radv_format_meta_fs_key(VkFormat format
)
625 unsigned col_format
= si_choose_spi_color_format(format
, false, false);
627 assert(col_format
!= V_028714_SPI_SHADER_32_AR
);
628 if (col_format
>= V_028714_SPI_SHADER_32_AR
)
629 --col_format
; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
631 --col_format
; /* Skip V_028714_SPI_SHADER_ZERO */
632 bool is_int8
= format_is_int8(format
);
633 bool is_int10
= format_is_int10(format
);
635 return col_format
+ (is_int8
? 3 : is_int10
? 5 : 0);
639 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
640 unsigned *is_int8
, unsigned *is_int10
)
642 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
643 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
647 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
648 struct radv_render_pass_attachment
*attachment
;
650 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
653 attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
655 if (format_is_int8(attachment
->format
))
657 if (format_is_int10(attachment
->format
))
663 radv_blend_check_commutativity(struct radv_blend_state
*blend
,
664 VkBlendOp op
, VkBlendFactor src
,
665 VkBlendFactor dst
, unsigned chanmask
)
667 /* Src factor is allowed when it does not depend on Dst. */
668 static const uint32_t src_allowed
=
669 (1u << VK_BLEND_FACTOR_ONE
) |
670 (1u << VK_BLEND_FACTOR_SRC_COLOR
) |
671 (1u << VK_BLEND_FACTOR_SRC_ALPHA
) |
672 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
) |
673 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR
) |
674 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA
) |
675 (1u << VK_BLEND_FACTOR_SRC1_COLOR
) |
676 (1u << VK_BLEND_FACTOR_SRC1_ALPHA
) |
677 (1u << VK_BLEND_FACTOR_ZERO
) |
678 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
) |
679 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
) |
680 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
) |
681 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
) |
682 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
) |
683 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
);
685 if (dst
== VK_BLEND_FACTOR_ONE
&&
686 (src_allowed
& (1u << src
))) {
687 /* Addition is commutative, but floating point addition isn't
688 * associative: subtle changes can be introduced via different
689 * rounding. Be conservative, only enable for min and max.
691 if (op
== VK_BLEND_OP_MAX
|| op
== VK_BLEND_OP_MIN
)
692 blend
->commutative_4bit
|= chanmask
;
696 static struct radv_blend_state
697 radv_pipeline_init_blend_state(struct radv_pipeline
*pipeline
,
698 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
699 const struct radv_graphics_pipeline_create_info
*extra
)
701 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
702 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
703 struct radv_blend_state blend
= {0};
704 unsigned mode
= V_028808_CB_NORMAL
;
710 if (extra
&& extra
->custom_blend_mode
) {
711 blend
.single_cb_enable
= true;
712 mode
= extra
->custom_blend_mode
;
714 blend
.cb_color_control
= 0;
715 if (vkblend
->logicOpEnable
)
716 blend
.cb_color_control
|= S_028808_ROP3(si_translate_blend_logic_op(vkblend
->logicOp
));
718 blend
.cb_color_control
|= S_028808_ROP3(V_028808_ROP3_COPY
);
720 blend
.db_alpha_to_mask
= S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
721 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
722 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
723 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
724 S_028B70_OFFSET_ROUND(1);
726 if (vkms
&& vkms
->alphaToCoverageEnable
) {
727 blend
.db_alpha_to_mask
|= S_028B70_ALPHA_TO_MASK_ENABLE(1);
728 blend
.need_src_alpha
|= 0x1;
731 blend
.cb_target_mask
= 0;
732 for (i
= 0; i
< vkblend
->attachmentCount
; i
++) {
733 const VkPipelineColorBlendAttachmentState
*att
= &vkblend
->pAttachments
[i
];
734 unsigned blend_cntl
= 0;
735 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
736 VkBlendOp eqRGB
= att
->colorBlendOp
;
737 VkBlendFactor srcRGB
= att
->srcColorBlendFactor
;
738 VkBlendFactor dstRGB
= att
->dstColorBlendFactor
;
739 VkBlendOp eqA
= att
->alphaBlendOp
;
740 VkBlendFactor srcA
= att
->srcAlphaBlendFactor
;
741 VkBlendFactor dstA
= att
->dstAlphaBlendFactor
;
743 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
745 if (!att
->colorWriteMask
)
748 blend
.cb_target_mask
|= (unsigned)att
->colorWriteMask
<< (4 * i
);
749 blend
.cb_target_enabled_4bit
|= 0xf << (4 * i
);
750 if (!att
->blendEnable
) {
751 blend
.cb_blend_control
[i
] = blend_cntl
;
755 if (is_dual_src(srcRGB
) || is_dual_src(dstRGB
) || is_dual_src(srcA
) || is_dual_src(dstA
))
757 blend
.mrt0_is_dual_src
= true;
759 if (eqRGB
== VK_BLEND_OP_MIN
|| eqRGB
== VK_BLEND_OP_MAX
) {
760 srcRGB
= VK_BLEND_FACTOR_ONE
;
761 dstRGB
= VK_BLEND_FACTOR_ONE
;
763 if (eqA
== VK_BLEND_OP_MIN
|| eqA
== VK_BLEND_OP_MAX
) {
764 srcA
= VK_BLEND_FACTOR_ONE
;
765 dstA
= VK_BLEND_FACTOR_ONE
;
768 radv_blend_check_commutativity(&blend
, eqRGB
, srcRGB
, dstRGB
,
770 radv_blend_check_commutativity(&blend
, eqA
, srcA
, dstA
,
773 /* Blending optimizations for RB+.
774 * These transformations don't change the behavior.
776 * First, get rid of DST in the blend factors:
777 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
779 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
780 VK_BLEND_FACTOR_DST_COLOR
,
781 VK_BLEND_FACTOR_SRC_COLOR
);
783 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
784 VK_BLEND_FACTOR_DST_COLOR
,
785 VK_BLEND_FACTOR_SRC_COLOR
);
787 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
788 VK_BLEND_FACTOR_DST_ALPHA
,
789 VK_BLEND_FACTOR_SRC_ALPHA
);
791 /* Look up the ideal settings from tables. */
792 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
793 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
794 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
795 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
797 /* Handle interdependencies. */
798 if (si_blend_factor_uses_dst(srcRGB
))
799 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
800 if (si_blend_factor_uses_dst(srcA
))
801 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
803 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
&&
804 (dstRGB
== VK_BLEND_FACTOR_ZERO
||
805 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
806 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
))
807 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
809 /* Set the final value. */
810 blend
.sx_mrt_blend_opt
[i
] =
811 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
812 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
813 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
814 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
815 S_028760_ALPHA_DST_OPT(dstA_opt
) |
816 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
817 blend_cntl
|= S_028780_ENABLE(1);
819 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
820 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
821 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
822 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
823 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
824 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
825 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
826 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
828 blend
.cb_blend_control
[i
] = blend_cntl
;
830 blend
.blend_enable_4bit
|= 0xfu
<< (i
* 4);
832 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
833 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
834 srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
835 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
836 srcRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
||
837 dstRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
)
838 blend
.need_src_alpha
|= 1 << i
;
840 for (i
= vkblend
->attachmentCount
; i
< 8; i
++) {
841 blend
.cb_blend_control
[i
] = 0;
842 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
845 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
846 /* Disable RB+ blend optimizations for dual source blending. */
847 if (blend
.mrt0_is_dual_src
) {
848 for (i
= 0; i
< 8; i
++) {
849 blend
.sx_mrt_blend_opt
[i
] =
850 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
851 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
855 /* RB+ doesn't work with dual source blending, logic op and
858 if (blend
.mrt0_is_dual_src
|| vkblend
->logicOpEnable
||
859 mode
== V_028808_CB_RESOLVE
)
860 blend
.cb_color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
863 if (blend
.cb_target_mask
)
864 blend
.cb_color_control
|= S_028808_MODE(mode
);
866 blend
.cb_color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
868 radv_pipeline_compute_spi_color_formats(pipeline
, pCreateInfo
, &blend
);
872 static uint32_t si_translate_stencil_op(enum VkStencilOp op
)
875 case VK_STENCIL_OP_KEEP
:
876 return V_02842C_STENCIL_KEEP
;
877 case VK_STENCIL_OP_ZERO
:
878 return V_02842C_STENCIL_ZERO
;
879 case VK_STENCIL_OP_REPLACE
:
880 return V_02842C_STENCIL_REPLACE_TEST
;
881 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
882 return V_02842C_STENCIL_ADD_CLAMP
;
883 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
884 return V_02842C_STENCIL_SUB_CLAMP
;
885 case VK_STENCIL_OP_INVERT
:
886 return V_02842C_STENCIL_INVERT
;
887 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
888 return V_02842C_STENCIL_ADD_WRAP
;
889 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
890 return V_02842C_STENCIL_SUB_WRAP
;
896 static uint32_t si_translate_fill(VkPolygonMode func
)
899 case VK_POLYGON_MODE_FILL
:
900 return V_028814_X_DRAW_TRIANGLES
;
901 case VK_POLYGON_MODE_LINE
:
902 return V_028814_X_DRAW_LINES
;
903 case VK_POLYGON_MODE_POINT
:
904 return V_028814_X_DRAW_POINTS
;
907 return V_028814_X_DRAW_POINTS
;
911 static uint8_t radv_pipeline_get_ps_iter_samples(const VkPipelineMultisampleStateCreateInfo
*vkms
)
913 uint32_t num_samples
= vkms
->rasterizationSamples
;
914 uint32_t ps_iter_samples
= 1;
916 if (vkms
->sampleShadingEnable
) {
917 ps_iter_samples
= ceil(vkms
->minSampleShading
* num_samples
);
918 ps_iter_samples
= util_next_power_of_two(ps_iter_samples
);
920 return ps_iter_samples
;
924 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
926 return pCreateInfo
->depthTestEnable
&&
927 pCreateInfo
->depthWriteEnable
&&
928 pCreateInfo
->depthCompareOp
!= VK_COMPARE_OP_NEVER
;
932 radv_writes_stencil(const VkStencilOpState
*state
)
934 return state
->writeMask
&&
935 (state
->failOp
!= VK_STENCIL_OP_KEEP
||
936 state
->passOp
!= VK_STENCIL_OP_KEEP
||
937 state
->depthFailOp
!= VK_STENCIL_OP_KEEP
);
941 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
943 return pCreateInfo
->stencilTestEnable
&&
944 (radv_writes_stencil(&pCreateInfo
->front
) ||
945 radv_writes_stencil(&pCreateInfo
->back
));
949 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
951 return radv_is_depth_write_enabled(pCreateInfo
) ||
952 radv_is_stencil_write_enabled(pCreateInfo
);
956 radv_order_invariant_stencil_op(VkStencilOp op
)
958 /* REPLACE is normally order invariant, except when the stencil
959 * reference value is written by the fragment shader. Tracking this
960 * interaction does not seem worth the effort, so be conservative.
962 return op
!= VK_STENCIL_OP_INCREMENT_AND_CLAMP
&&
963 op
!= VK_STENCIL_OP_DECREMENT_AND_CLAMP
&&
964 op
!= VK_STENCIL_OP_REPLACE
;
968 radv_order_invariant_stencil_state(const VkStencilOpState
*state
)
970 /* Compute whether, assuming Z writes are disabled, this stencil state
971 * is order invariant in the sense that the set of passing fragments as
972 * well as the final stencil buffer result does not depend on the order
975 return !state
->writeMask
||
976 /* The following assumes that Z writes are disabled. */
977 (state
->compareOp
== VK_COMPARE_OP_ALWAYS
&&
978 radv_order_invariant_stencil_op(state
->passOp
) &&
979 radv_order_invariant_stencil_op(state
->depthFailOp
)) ||
980 (state
->compareOp
== VK_COMPARE_OP_NEVER
&&
981 radv_order_invariant_stencil_op(state
->failOp
));
985 radv_pipeline_out_of_order_rast(struct radv_pipeline
*pipeline
,
986 struct radv_blend_state
*blend
,
987 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
989 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
990 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
991 unsigned colormask
= blend
->cb_target_enabled_4bit
;
993 if (!pipeline
->device
->physical_device
->out_of_order_rast_allowed
)
996 /* Be conservative if a logic operation is enabled with color buffers. */
997 if (colormask
&& pCreateInfo
->pColorBlendState
->logicOpEnable
)
1000 /* Default depth/stencil invariance when no attachment is bound. */
1001 struct radv_dsa_order_invariance dsa_order_invariant
= {
1002 .zs
= true, .pass_set
= true
1005 if (pCreateInfo
->pDepthStencilState
&&
1006 subpass
->depth_stencil_attachment
) {
1007 const VkPipelineDepthStencilStateCreateInfo
*vkds
=
1008 pCreateInfo
->pDepthStencilState
;
1009 struct radv_render_pass_attachment
*attachment
=
1010 pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
1011 bool has_stencil
= vk_format_is_stencil(attachment
->format
);
1012 struct radv_dsa_order_invariance order_invariance
[2];
1013 struct radv_shader_variant
*ps
=
1014 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
1016 /* Compute depth/stencil order invariance in order to know if
1017 * it's safe to enable out-of-order.
1019 bool zfunc_is_ordered
=
1020 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
||
1021 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS
||
1022 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS_OR_EQUAL
||
1023 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER
||
1024 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER_OR_EQUAL
;
1026 bool nozwrite_and_order_invariant_stencil
=
1027 !radv_is_ds_write_enabled(vkds
) ||
1028 (!radv_is_depth_write_enabled(vkds
) &&
1029 radv_order_invariant_stencil_state(&vkds
->front
) &&
1030 radv_order_invariant_stencil_state(&vkds
->back
));
1032 order_invariance
[1].zs
=
1033 nozwrite_and_order_invariant_stencil
||
1034 (!radv_is_stencil_write_enabled(vkds
) &&
1036 order_invariance
[0].zs
=
1037 !radv_is_depth_write_enabled(vkds
) || zfunc_is_ordered
;
1039 order_invariance
[1].pass_set
=
1040 nozwrite_and_order_invariant_stencil
||
1041 (!radv_is_stencil_write_enabled(vkds
) &&
1042 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1043 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
));
1044 order_invariance
[0].pass_set
=
1045 !radv_is_depth_write_enabled(vkds
) ||
1046 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1047 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
);
1049 dsa_order_invariant
= order_invariance
[has_stencil
];
1050 if (!dsa_order_invariant
.zs
)
1053 /* The set of PS invocations is always order invariant,
1054 * except when early Z/S tests are requested.
1057 ps
->info
.ps
.writes_memory
&&
1058 ps
->info
.ps
.early_fragment_test
&&
1059 !dsa_order_invariant
.pass_set
)
1062 /* Determine if out-of-order rasterization should be disabled
1063 * when occlusion queries are used.
1065 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
=
1066 !dsa_order_invariant
.pass_set
;
1069 /* No color buffers are enabled for writing. */
1073 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
1076 /* Only commutative blending. */
1077 if (blendmask
& ~blend
->commutative_4bit
)
1080 if (!dsa_order_invariant
.pass_set
)
1084 if (colormask
& ~blendmask
)
1091 radv_pipeline_init_multisample_state(struct radv_pipeline
*pipeline
,
1092 struct radv_blend_state
*blend
,
1093 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1095 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
1096 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
1097 unsigned num_tile_pipes
= pipeline
->device
->physical_device
->rad_info
.num_tile_pipes
;
1098 bool out_of_order_rast
= false;
1099 int ps_iter_samples
= 1;
1100 uint32_t mask
= 0xffff;
1103 ms
->num_samples
= vkms
->rasterizationSamples
;
1105 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1107 * "Sample shading is enabled for a graphics pipeline:
1109 * - If the interface of the fragment shader entry point of the
1110 * graphics pipeline includes an input variable decorated
1111 * with SampleId or SamplePosition. In this case
1112 * minSampleShadingFactor takes the value 1.0.
1113 * - Else if the sampleShadingEnable member of the
1114 * VkPipelineMultisampleStateCreateInfo structure specified
1115 * when creating the graphics pipeline is set to VK_TRUE. In
1116 * this case minSampleShadingFactor takes the value of
1117 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1119 * Otherwise, sample shading is considered disabled."
1121 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.force_persample
) {
1122 ps_iter_samples
= ms
->num_samples
;
1124 ps_iter_samples
= radv_pipeline_get_ps_iter_samples(vkms
);
1127 ms
->num_samples
= 1;
1130 const struct VkPipelineRasterizationStateRasterizationOrderAMD
*raster_order
=
1131 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD
);
1132 if (raster_order
&& raster_order
->rasterizationOrder
== VK_RASTERIZATION_ORDER_RELAXED_AMD
) {
1133 /* Out-of-order rasterization is explicitly enabled by the
1136 out_of_order_rast
= true;
1138 /* Determine if the driver can enable out-of-order
1139 * rasterization internally.
1142 radv_pipeline_out_of_order_rast(pipeline
, blend
, pCreateInfo
);
1145 ms
->pa_sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1146 ms
->pa_sc_aa_config
= 0;
1147 ms
->db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1148 S_028804_INCOHERENT_EQAA_READS(1) |
1149 S_028804_INTERPOLATE_COMP_Z(1) |
1150 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1151 ms
->pa_sc_mode_cntl_1
=
1152 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1153 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
1154 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
1155 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1157 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1158 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1159 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1160 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1161 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1162 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1163 ms
->pa_sc_mode_cntl_0
= S_028A48_ALTERNATE_RBS_PER_TILE(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
1164 S_028A48_VPORT_SCISSOR_ENABLE(1);
1166 if (ms
->num_samples
> 1) {
1167 unsigned log_samples
= util_logbase2(ms
->num_samples
);
1168 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
1169 ms
->pa_sc_mode_cntl_0
|= S_028A48_MSAA_ENABLE(1);
1170 ms
->pa_sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1171 ms
->db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_samples
) |
1172 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
1173 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
1174 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
1175 ms
->pa_sc_aa_config
|= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
1176 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples
)) |
1177 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1178 ms
->pa_sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
1179 if (ps_iter_samples
> 1)
1180 pipeline
->graphics
.spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1183 if (vkms
&& vkms
->pSampleMask
) {
1184 mask
= vkms
->pSampleMask
[0] & 0xffff;
1187 ms
->pa_sc_aa_mask
[0] = mask
| (mask
<< 16);
1188 ms
->pa_sc_aa_mask
[1] = mask
| (mask
<< 16);
1192 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology
)
1195 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1196 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1197 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1198 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1199 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1201 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1202 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1203 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1204 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1205 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1206 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1209 unreachable("unhandled primitive type");
1214 si_translate_prim(enum VkPrimitiveTopology topology
)
1217 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1218 return V_008958_DI_PT_POINTLIST
;
1219 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1220 return V_008958_DI_PT_LINELIST
;
1221 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1222 return V_008958_DI_PT_LINESTRIP
;
1223 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1224 return V_008958_DI_PT_TRILIST
;
1225 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1226 return V_008958_DI_PT_TRISTRIP
;
1227 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1228 return V_008958_DI_PT_TRIFAN
;
1229 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1230 return V_008958_DI_PT_LINELIST_ADJ
;
1231 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1232 return V_008958_DI_PT_LINESTRIP_ADJ
;
1233 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1234 return V_008958_DI_PT_TRILIST_ADJ
;
1235 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1236 return V_008958_DI_PT_TRISTRIP_ADJ
;
1237 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1238 return V_008958_DI_PT_PATCH
;
1246 si_conv_gl_prim_to_gs_out(unsigned gl_prim
)
1249 case 0: /* GL_POINTS */
1250 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1251 case 1: /* GL_LINES */
1252 case 3: /* GL_LINE_STRIP */
1253 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1254 case 0x8E7A: /* GL_ISOLINES */
1255 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1257 case 4: /* GL_TRIANGLES */
1258 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1259 case 5: /* GL_TRIANGLE_STRIP */
1260 case 7: /* GL_QUADS */
1261 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1269 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology
)
1272 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1273 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1274 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1275 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1276 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1277 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1278 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1279 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1280 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1281 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1282 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1283 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1284 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1285 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1292 static unsigned radv_dynamic_state_mask(VkDynamicState state
)
1295 case VK_DYNAMIC_STATE_VIEWPORT
:
1296 return RADV_DYNAMIC_VIEWPORT
;
1297 case VK_DYNAMIC_STATE_SCISSOR
:
1298 return RADV_DYNAMIC_SCISSOR
;
1299 case VK_DYNAMIC_STATE_LINE_WIDTH
:
1300 return RADV_DYNAMIC_LINE_WIDTH
;
1301 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
1302 return RADV_DYNAMIC_DEPTH_BIAS
;
1303 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
1304 return RADV_DYNAMIC_BLEND_CONSTANTS
;
1305 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
1306 return RADV_DYNAMIC_DEPTH_BOUNDS
;
1307 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
1308 return RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
1309 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
1310 return RADV_DYNAMIC_STENCIL_WRITE_MASK
;
1311 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
1312 return RADV_DYNAMIC_STENCIL_REFERENCE
;
1313 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT
:
1314 return RADV_DYNAMIC_DISCARD_RECTANGLE
;
1315 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT
:
1316 return RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1318 unreachable("Unhandled dynamic state");
1322 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1324 uint32_t states
= RADV_DYNAMIC_ALL
;
1326 /* If rasterization is disabled we do not care about any of the dynamic states,
1327 * since they are all rasterization related only. */
1328 if (pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
1331 if (!pCreateInfo
->pRasterizationState
->depthBiasEnable
)
1332 states
&= ~RADV_DYNAMIC_DEPTH_BIAS
;
1334 if (!pCreateInfo
->pDepthStencilState
||
1335 !pCreateInfo
->pDepthStencilState
->depthBoundsTestEnable
)
1336 states
&= ~RADV_DYNAMIC_DEPTH_BOUNDS
;
1338 if (!pCreateInfo
->pDepthStencilState
||
1339 !pCreateInfo
->pDepthStencilState
->stencilTestEnable
)
1340 states
&= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK
|
1341 RADV_DYNAMIC_STENCIL_WRITE_MASK
|
1342 RADV_DYNAMIC_STENCIL_REFERENCE
);
1344 if (!vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
))
1345 states
&= ~RADV_DYNAMIC_DISCARD_RECTANGLE
;
1347 if (!pCreateInfo
->pMultisampleState
||
1348 !vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1349 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
))
1350 states
&= ~RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1352 /* TODO: blend constants & line width. */
1359 radv_pipeline_init_dynamic_state(struct radv_pipeline
*pipeline
,
1360 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1362 uint32_t needed_states
= radv_pipeline_needed_dynamic_state(pCreateInfo
);
1363 uint32_t states
= needed_states
;
1364 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1365 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1367 pipeline
->dynamic_state
= default_dynamic_state
;
1368 pipeline
->graphics
.needed_dynamic_state
= needed_states
;
1370 if (pCreateInfo
->pDynamicState
) {
1371 /* Remove all of the states that are marked as dynamic */
1372 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1373 for (uint32_t s
= 0; s
< count
; s
++)
1374 states
&= ~radv_dynamic_state_mask(pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1377 struct radv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1379 if (needed_states
& RADV_DYNAMIC_VIEWPORT
) {
1380 assert(pCreateInfo
->pViewportState
);
1382 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1383 if (states
& RADV_DYNAMIC_VIEWPORT
) {
1384 typed_memcpy(dynamic
->viewport
.viewports
,
1385 pCreateInfo
->pViewportState
->pViewports
,
1386 pCreateInfo
->pViewportState
->viewportCount
);
1390 if (needed_states
& RADV_DYNAMIC_SCISSOR
) {
1391 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1392 if (states
& RADV_DYNAMIC_SCISSOR
) {
1393 typed_memcpy(dynamic
->scissor
.scissors
,
1394 pCreateInfo
->pViewportState
->pScissors
,
1395 pCreateInfo
->pViewportState
->scissorCount
);
1399 if (states
& RADV_DYNAMIC_LINE_WIDTH
) {
1400 assert(pCreateInfo
->pRasterizationState
);
1401 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1404 if (states
& RADV_DYNAMIC_DEPTH_BIAS
) {
1405 assert(pCreateInfo
->pRasterizationState
);
1406 dynamic
->depth_bias
.bias
=
1407 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1408 dynamic
->depth_bias
.clamp
=
1409 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1410 dynamic
->depth_bias
.slope
=
1411 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1414 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1416 * pColorBlendState is [...] NULL if the pipeline has rasterization
1417 * disabled or if the subpass of the render pass the pipeline is
1418 * created against does not use any color attachments.
1420 if (subpass
->has_color_att
&& states
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
1421 assert(pCreateInfo
->pColorBlendState
);
1422 typed_memcpy(dynamic
->blend_constants
,
1423 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1426 /* If there is no depthstencil attachment, then don't read
1427 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1428 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1429 * no need to override the depthstencil defaults in
1430 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1432 * Section 9.2 of the Vulkan 1.0.15 spec says:
1434 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1435 * disabled or if the subpass of the render pass the pipeline is created
1436 * against does not use a depth/stencil attachment.
1438 if (needed_states
&& subpass
->depth_stencil_attachment
) {
1439 assert(pCreateInfo
->pDepthStencilState
);
1441 if (states
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
1442 dynamic
->depth_bounds
.min
=
1443 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1444 dynamic
->depth_bounds
.max
=
1445 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1448 if (states
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
1449 dynamic
->stencil_compare_mask
.front
=
1450 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1451 dynamic
->stencil_compare_mask
.back
=
1452 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1455 if (states
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
1456 dynamic
->stencil_write_mask
.front
=
1457 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1458 dynamic
->stencil_write_mask
.back
=
1459 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1462 if (states
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
1463 dynamic
->stencil_reference
.front
=
1464 pCreateInfo
->pDepthStencilState
->front
.reference
;
1465 dynamic
->stencil_reference
.back
=
1466 pCreateInfo
->pDepthStencilState
->back
.reference
;
1470 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
1471 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
1472 if (needed_states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1473 dynamic
->discard_rectangle
.count
= discard_rectangle_info
->discardRectangleCount
;
1474 if (states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1475 typed_memcpy(dynamic
->discard_rectangle
.rectangles
,
1476 discard_rectangle_info
->pDiscardRectangles
,
1477 discard_rectangle_info
->discardRectangleCount
);
1481 if (needed_states
& RADV_DYNAMIC_SAMPLE_LOCATIONS
) {
1482 const VkPipelineSampleLocationsStateCreateInfoEXT
*sample_location_info
=
1483 vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1484 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
);
1485 /* If sampleLocationsEnable is VK_FALSE, the default sample
1486 * locations are used and the values specified in
1487 * sampleLocationsInfo are ignored.
1489 if (sample_location_info
->sampleLocationsEnable
) {
1490 const VkSampleLocationsInfoEXT
*pSampleLocationsInfo
=
1491 &sample_location_info
->sampleLocationsInfo
;
1493 assert(pSampleLocationsInfo
->sampleLocationsCount
<= MAX_SAMPLE_LOCATIONS
);
1495 dynamic
->sample_location
.per_pixel
= pSampleLocationsInfo
->sampleLocationsPerPixel
;
1496 dynamic
->sample_location
.grid_size
= pSampleLocationsInfo
->sampleLocationGridSize
;
1497 dynamic
->sample_location
.count
= pSampleLocationsInfo
->sampleLocationsCount
;
1498 typed_memcpy(&dynamic
->sample_location
.locations
[0],
1499 pSampleLocationsInfo
->pSampleLocations
,
1500 pSampleLocationsInfo
->sampleLocationsCount
);
1504 pipeline
->dynamic_state
.mask
= states
;
1508 gfx9_get_gs_info(const struct radv_pipeline_key
*key
,
1509 const struct radv_pipeline
*pipeline
,
1511 struct radv_shader_info
*infos
,
1512 struct gfx9_gs_info
*out
)
1514 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1515 struct radv_es_output_info
*es_info
;
1516 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1517 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1519 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ?
1520 &infos
[MESA_SHADER_TESS_EVAL
].tes
.es_info
:
1521 &infos
[MESA_SHADER_VERTEX
].vs
.es_info
;
1523 unsigned gs_num_invocations
= MAX2(gs_info
->gs
.invocations
, 1);
1524 bool uses_adjacency
;
1525 switch(key
->topology
) {
1526 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1527 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1528 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1529 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1530 uses_adjacency
= true;
1533 uses_adjacency
= false;
1537 /* All these are in dwords: */
1538 /* We can't allow using the whole LDS, because GS waves compete with
1539 * other shader stages for LDS space. */
1540 const unsigned max_lds_size
= 8 * 1024;
1541 const unsigned esgs_itemsize
= es_info
->esgs_itemsize
/ 4;
1542 unsigned esgs_lds_size
;
1544 /* All these are per subgroup: */
1545 const unsigned max_out_prims
= 32 * 1024;
1546 const unsigned max_es_verts
= 255;
1547 const unsigned ideal_gs_prims
= 64;
1548 unsigned max_gs_prims
, gs_prims
;
1549 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
1551 if (uses_adjacency
|| gs_num_invocations
> 1)
1552 max_gs_prims
= 127 / gs_num_invocations
;
1556 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1557 * Make sure we don't go over the maximum value.
1559 if (gs_info
->gs
.vertices_out
> 0) {
1560 max_gs_prims
= MIN2(max_gs_prims
,
1562 (gs_info
->gs
.vertices_out
* gs_num_invocations
));
1564 assert(max_gs_prims
> 0);
1566 /* If the primitive has adjacency, halve the number of vertices
1567 * that will be reused in multiple primitives.
1569 min_es_verts
= gs_info
->gs
.vertices_in
/ (uses_adjacency
? 2 : 1);
1571 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
1572 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
1574 /* Compute ESGS LDS size based on the worst case number of ES vertices
1575 * needed to create the target number of GS prims per subgroup.
1577 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1579 /* If total LDS usage is too big, refactor partitions based on ratio
1580 * of ESGS item sizes.
1582 if (esgs_lds_size
> max_lds_size
) {
1583 /* Our target GS Prims Per Subgroup was too large. Calculate
1584 * the maximum number of GS Prims Per Subgroup that will fit
1585 * into LDS, capped by the maximum that the hardware can support.
1587 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
1589 assert(gs_prims
> 0);
1590 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
1593 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1594 assert(esgs_lds_size
<= max_lds_size
);
1597 /* Now calculate remaining ESGS information. */
1599 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
1601 es_verts
= max_es_verts
;
1603 /* Vertices for adjacency primitives are not always reused, so restore
1604 * it for ES_VERTS_PER_SUBGRP.
1606 min_es_verts
= gs_info
->gs
.vertices_in
;
1608 /* For normal primitives, the VGT only checks if they are past the ES
1609 * verts per subgroup after allocating a full GS primitive and if they
1610 * are, kick off a new subgroup. But if those additional ES verts are
1611 * unique (e.g. not reused) we need to make sure there is enough LDS
1612 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1614 es_verts
-= min_es_verts
- 1;
1616 uint32_t es_verts_per_subgroup
= es_verts
;
1617 uint32_t gs_prims_per_subgroup
= gs_prims
;
1618 uint32_t gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
1619 uint32_t max_prims_per_subgroup
= gs_inst_prims_in_subgroup
* gs_info
->gs
.vertices_out
;
1620 out
->lds_size
= align(esgs_lds_size
, 128) / 128;
1621 out
->vgt_gs_onchip_cntl
= S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup
) |
1622 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup
) |
1623 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup
);
1624 out
->vgt_gs_max_prims_per_subgroup
= S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup
);
1625 out
->vgt_esgs_ring_itemsize
= esgs_itemsize
;
1626 assert(max_prims_per_subgroup
<= max_out_prims
);
1629 static void clamp_gsprims_to_esverts(unsigned *max_gsprims
, unsigned max_esverts
,
1630 unsigned min_verts_per_prim
, bool use_adjacency
)
1632 unsigned max_reuse
= max_esverts
- min_verts_per_prim
;
1635 *max_gsprims
= MIN2(*max_gsprims
, 1 + max_reuse
);
1639 radv_get_num_input_vertices(nir_shader
**nir
)
1641 if (nir
[MESA_SHADER_GEOMETRY
]) {
1642 nir_shader
*gs
= nir
[MESA_SHADER_GEOMETRY
];
1644 return gs
->info
.gs
.vertices_in
;
1647 if (nir
[MESA_SHADER_TESS_CTRL
]) {
1648 nir_shader
*tes
= nir
[MESA_SHADER_TESS_EVAL
];
1650 if (tes
->info
.tess
.point_mode
)
1652 if (tes
->info
.tess
.primitive_mode
== GL_ISOLINES
)
1661 gfx10_get_ngg_info(const struct radv_pipeline_key
*key
,
1662 struct radv_pipeline
*pipeline
,
1664 struct radv_shader_info
*infos
,
1665 struct gfx10_ngg_info
*ngg
)
1667 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1668 struct radv_es_output_info
*es_info
=
1669 nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1670 unsigned gs_type
= nir
[MESA_SHADER_GEOMETRY
] ? MESA_SHADER_GEOMETRY
: MESA_SHADER_VERTEX
;
1671 unsigned max_verts_per_prim
= radv_get_num_input_vertices(nir
);
1672 unsigned min_verts_per_prim
=
1673 gs_type
== MESA_SHADER_GEOMETRY
? max_verts_per_prim
: 1;
1674 unsigned gs_num_invocations
= nir
[MESA_SHADER_GEOMETRY
] ? MAX2(gs_info
->gs
.invocations
, 1) : 1;
1675 bool uses_adjacency
;
1676 switch(key
->topology
) {
1677 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1678 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1679 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1680 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1681 uses_adjacency
= true;
1684 uses_adjacency
= false;
1688 /* All these are in dwords: */
1689 /* We can't allow using the whole LDS, because GS waves compete with
1690 * other shader stages for LDS space.
1692 * TODO: We should really take the shader's internal LDS use into
1693 * account. The linker will fail if the size is greater than
1696 const unsigned max_lds_size
= 8 * 1024 - 768;
1697 const unsigned target_lds_size
= max_lds_size
;
1698 unsigned esvert_lds_size
= 0;
1699 unsigned gsprim_lds_size
= 0;
1701 /* All these are per subgroup: */
1702 bool max_vert_out_per_gs_instance
= false;
1703 unsigned max_esverts_base
= 256;
1704 unsigned max_gsprims_base
= 128; /* default prim group size clamp */
1706 /* Hardware has the following non-natural restrictions on the value
1707 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1709 * - at most 252 for any line input primitive type
1710 * - at most 251 for any quad input primitive type
1711 * - at most 251 for triangle strips with adjacency (this happens to
1712 * be the natural limit for triangle *lists* with adjacency)
1714 max_esverts_base
= MIN2(max_esverts_base
, 251 + max_verts_per_prim
- 1);
1716 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1717 unsigned max_out_verts_per_gsprim
=
1718 gs_info
->gs
.vertices_out
* gs_num_invocations
;
1720 if (max_out_verts_per_gsprim
<= 256) {
1721 if (max_out_verts_per_gsprim
) {
1722 max_gsprims_base
= MIN2(max_gsprims_base
,
1723 256 / max_out_verts_per_gsprim
);
1726 /* Use special multi-cycling mode in which each GS
1727 * instance gets its own subgroup. Does not work with
1729 max_vert_out_per_gs_instance
= true;
1730 max_gsprims_base
= 1;
1731 max_out_verts_per_gsprim
= gs_info
->gs
.vertices_out
;
1734 esvert_lds_size
= es_info
->esgs_itemsize
/ 4;
1735 gsprim_lds_size
= (gs_info
->gs
.gsvs_vertex_size
/ 4 + 1) * max_out_verts_per_gsprim
;
1738 /* LDS size for passing data from GS to ES. */
1739 struct radv_streamout_info
*so_info
= nir
[MESA_SHADER_TESS_CTRL
]
1740 ? &infos
[MESA_SHADER_TESS_EVAL
].so
1741 : &infos
[MESA_SHADER_VERTEX
].so
;
1743 if (so_info
->num_outputs
)
1744 esvert_lds_size
= 4 * so_info
->num_outputs
+ 1;
1746 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1747 * corresponding to the ES thread of the provoking vertex. All
1748 * ES threads load and export PrimitiveID for their thread.
1750 if (!nir
[MESA_SHADER_TESS_CTRL
] &&
1751 infos
[MESA_SHADER_VERTEX
].vs
.outinfo
.export_prim_id
)
1752 esvert_lds_size
= MAX2(esvert_lds_size
, 1);
1755 unsigned max_gsprims
= max_gsprims_base
;
1756 unsigned max_esverts
= max_esverts_base
;
1758 if (esvert_lds_size
)
1759 max_esverts
= MIN2(max_esverts
, target_lds_size
/ esvert_lds_size
);
1760 if (gsprim_lds_size
)
1761 max_gsprims
= MIN2(max_gsprims
, target_lds_size
/ gsprim_lds_size
);
1763 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1764 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
, min_verts_per_prim
, uses_adjacency
);
1765 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1767 if (esvert_lds_size
|| gsprim_lds_size
) {
1768 /* Now that we have a rough proportionality between esverts
1769 * and gsprims based on the primitive type, scale both of them
1770 * down simultaneously based on required LDS space.
1772 * We could be smarter about this if we knew how much vertex
1775 unsigned lds_total
= max_esverts
* esvert_lds_size
+
1776 max_gsprims
* gsprim_lds_size
;
1777 if (lds_total
> target_lds_size
) {
1778 max_esverts
= max_esverts
* target_lds_size
/ lds_total
;
1779 max_gsprims
= max_gsprims
* target_lds_size
/ lds_total
;
1781 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1782 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1783 min_verts_per_prim
, uses_adjacency
);
1784 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1788 /* Round up towards full wave sizes for better ALU utilization. */
1789 if (!max_vert_out_per_gs_instance
) {
1790 unsigned orig_max_esverts
;
1791 unsigned orig_max_gsprims
;
1794 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1795 wavesize
= gs_info
->wave_size
;
1797 wavesize
= nir
[MESA_SHADER_TESS_CTRL
]
1798 ? infos
[MESA_SHADER_TESS_EVAL
].wave_size
1799 : infos
[MESA_SHADER_VERTEX
].wave_size
;
1803 orig_max_esverts
= max_esverts
;
1804 orig_max_gsprims
= max_gsprims
;
1806 max_esverts
= align(max_esverts
, wavesize
);
1807 max_esverts
= MIN2(max_esverts
, max_esverts_base
);
1808 if (esvert_lds_size
)
1809 max_esverts
= MIN2(max_esverts
,
1810 (max_lds_size
- max_gsprims
* gsprim_lds_size
) /
1812 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1814 max_gsprims
= align(max_gsprims
, wavesize
);
1815 max_gsprims
= MIN2(max_gsprims
, max_gsprims_base
);
1816 if (gsprim_lds_size
)
1817 max_gsprims
= MIN2(max_gsprims
,
1818 (max_lds_size
- max_esverts
* esvert_lds_size
) /
1820 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1821 min_verts_per_prim
, uses_adjacency
);
1822 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1823 } while (orig_max_esverts
!= max_esverts
|| orig_max_gsprims
!= max_gsprims
);
1826 /* Hardware restriction: minimum value of max_esverts */
1827 max_esverts
= MAX2(max_esverts
, 23 + max_verts_per_prim
);
1829 unsigned max_out_vertices
=
1830 max_vert_out_per_gs_instance
? gs_info
->gs
.vertices_out
:
1831 gs_type
== MESA_SHADER_GEOMETRY
?
1832 max_gsprims
* gs_num_invocations
* gs_info
->gs
.vertices_out
:
1834 assert(max_out_vertices
<= 256);
1836 unsigned prim_amp_factor
= 1;
1837 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1838 /* Number of output primitives per GS input primitive after
1840 prim_amp_factor
= gs_info
->gs
.vertices_out
;
1843 /* The GE only checks against the maximum number of ES verts after
1844 * allocating a full GS primitive. So we need to ensure that whenever
1845 * this check passes, there is enough space for a full primitive without
1848 ngg
->hw_max_esverts
= max_esverts
- max_verts_per_prim
+ 1;
1849 ngg
->max_gsprims
= max_gsprims
;
1850 ngg
->max_out_verts
= max_out_vertices
;
1851 ngg
->prim_amp_factor
= prim_amp_factor
;
1852 ngg
->max_vert_out_per_gs_instance
= max_vert_out_per_gs_instance
;
1853 ngg
->ngg_emit_size
= max_gsprims
* gsprim_lds_size
;
1854 ngg
->esgs_ring_size
= 4 * max_esverts
* esvert_lds_size
;
1856 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1857 ngg
->vgt_esgs_ring_itemsize
= es_info
->esgs_itemsize
/ 4;
1859 ngg
->vgt_esgs_ring_itemsize
= 1;
1862 pipeline
->graphics
.esgs_ring_size
= ngg
->esgs_ring_size
;
1864 assert(ngg
->hw_max_esverts
>= 24); /* HW limitation */
1868 calculate_gs_ring_sizes(struct radv_pipeline
*pipeline
,
1869 const struct gfx9_gs_info
*gs
)
1871 struct radv_device
*device
= pipeline
->device
;
1872 unsigned num_se
= device
->physical_device
->rad_info
.max_se
;
1873 unsigned wave_size
= 64;
1874 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
1875 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1876 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1878 unsigned gs_vertex_reuse
=
1879 (device
->physical_device
->rad_info
.chip_class
>= GFX8
? 32 : 16) * num_se
;
1880 unsigned alignment
= 256 * num_se
;
1881 /* The maximum size is 63.999 MB per SE. */
1882 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
1883 struct radv_shader_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
1885 /* Calculate the minimum size. */
1886 unsigned min_esgs_ring_size
= align(gs
->vgt_esgs_ring_itemsize
* 4 * gs_vertex_reuse
*
1887 wave_size
, alignment
);
1888 /* These are recommended sizes, not minimum sizes. */
1889 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
1890 gs
->vgt_esgs_ring_itemsize
* 4 * gs_info
->gs
.vertices_in
;
1891 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
1892 gs_info
->gs
.max_gsvs_emit_size
;
1894 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
1895 esgs_ring_size
= align(esgs_ring_size
, alignment
);
1896 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
1898 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
1899 pipeline
->graphics
.esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
1901 pipeline
->graphics
.gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
1904 static void si_multiwave_lds_size_workaround(struct radv_device
*device
,
1907 /* If tessellation is all offchip and on-chip GS isn't used, this
1908 * workaround is not needed.
1912 /* SPI barrier management bug:
1913 * Make sure we have at least 4k of LDS in use to avoid the bug.
1914 * It applies to workgroup sizes of more than one wavefront.
1916 if (device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
||
1917 device
->physical_device
->rad_info
.family
== CHIP_KABINI
)
1918 *lds_size
= MAX2(*lds_size
, 8);
1921 struct radv_shader_variant
*
1922 radv_get_shader(struct radv_pipeline
*pipeline
,
1923 gl_shader_stage stage
)
1925 if (stage
== MESA_SHADER_VERTEX
) {
1926 if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
1927 return pipeline
->shaders
[MESA_SHADER_VERTEX
];
1928 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
])
1929 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
1930 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1931 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1932 } else if (stage
== MESA_SHADER_TESS_EVAL
) {
1933 if (!radv_pipeline_has_tess(pipeline
))
1935 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
1936 return pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
1937 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1938 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1940 return pipeline
->shaders
[stage
];
1943 static struct radv_tessellation_state
1944 calculate_tess_state(struct radv_pipeline
*pipeline
,
1945 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1947 unsigned num_tcs_input_cp
;
1948 unsigned num_tcs_output_cp
;
1950 unsigned num_patches
;
1951 struct radv_tessellation_state tess
= {0};
1953 num_tcs_input_cp
= pCreateInfo
->pTessellationState
->patchControlPoints
;
1954 num_tcs_output_cp
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.tcs_vertices_out
; //TCS VERTICES OUT
1955 num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
1957 lds_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.lds_size
;
1959 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
1960 assert(lds_size
<= 65536);
1961 lds_size
= align(lds_size
, 512) / 512;
1963 assert(lds_size
<= 32768);
1964 lds_size
= align(lds_size
, 256) / 256;
1966 si_multiwave_lds_size_workaround(pipeline
->device
, &lds_size
);
1968 tess
.lds_size
= lds_size
;
1970 tess
.ls_hs_config
= S_028B58_NUM_PATCHES(num_patches
) |
1971 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
1972 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
1973 tess
.num_patches
= num_patches
;
1975 struct radv_shader_variant
*tes
= radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
);
1976 unsigned type
= 0, partitioning
= 0, topology
= 0, distribution_mode
= 0;
1978 switch (tes
->info
.tes
.primitive_mode
) {
1980 type
= V_028B6C_TESS_TRIANGLE
;
1983 type
= V_028B6C_TESS_QUAD
;
1986 type
= V_028B6C_TESS_ISOLINE
;
1990 switch (tes
->info
.tes
.spacing
) {
1991 case TESS_SPACING_EQUAL
:
1992 partitioning
= V_028B6C_PART_INTEGER
;
1994 case TESS_SPACING_FRACTIONAL_ODD
:
1995 partitioning
= V_028B6C_PART_FRAC_ODD
;
1997 case TESS_SPACING_FRACTIONAL_EVEN
:
1998 partitioning
= V_028B6C_PART_FRAC_EVEN
;
2004 bool ccw
= tes
->info
.tes
.ccw
;
2005 const VkPipelineTessellationDomainOriginStateCreateInfo
*domain_origin_state
=
2006 vk_find_struct_const(pCreateInfo
->pTessellationState
,
2007 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO
);
2009 if (domain_origin_state
&& domain_origin_state
->domainOrigin
!= VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT
)
2012 if (tes
->info
.tes
.point_mode
)
2013 topology
= V_028B6C_OUTPUT_POINT
;
2014 else if (tes
->info
.tes
.primitive_mode
== GL_ISOLINES
)
2015 topology
= V_028B6C_OUTPUT_LINE
;
2017 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
2019 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
2021 if (pipeline
->device
->physical_device
->rad_info
.has_distributed_tess
) {
2022 if (pipeline
->device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
2023 pipeline
->device
->physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
2024 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
2026 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
2028 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
2030 tess
.tf_param
= S_028B6C_TYPE(type
) |
2031 S_028B6C_PARTITIONING(partitioning
) |
2032 S_028B6C_TOPOLOGY(topology
) |
2033 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
2038 static const struct radv_prim_vertex_count prim_size_table
[] = {
2039 [V_008958_DI_PT_NONE
] = {0, 0},
2040 [V_008958_DI_PT_POINTLIST
] = {1, 1},
2041 [V_008958_DI_PT_LINELIST
] = {2, 2},
2042 [V_008958_DI_PT_LINESTRIP
] = {2, 1},
2043 [V_008958_DI_PT_TRILIST
] = {3, 3},
2044 [V_008958_DI_PT_TRIFAN
] = {3, 1},
2045 [V_008958_DI_PT_TRISTRIP
] = {3, 1},
2046 [V_008958_DI_PT_LINELIST_ADJ
] = {4, 4},
2047 [V_008958_DI_PT_LINESTRIP_ADJ
] = {4, 1},
2048 [V_008958_DI_PT_TRILIST_ADJ
] = {6, 6},
2049 [V_008958_DI_PT_TRISTRIP_ADJ
] = {6, 2},
2050 [V_008958_DI_PT_RECTLIST
] = {3, 3},
2051 [V_008958_DI_PT_LINELOOP
] = {2, 1},
2052 [V_008958_DI_PT_POLYGON
] = {3, 1},
2053 [V_008958_DI_PT_2D_TRI_STRIP
] = {0, 0},
2056 static const struct radv_vs_output_info
*get_vs_output_info(const struct radv_pipeline
*pipeline
)
2058 if (radv_pipeline_has_gs(pipeline
))
2059 if (radv_pipeline_has_ngg(pipeline
))
2060 return &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.vs
.outinfo
;
2062 return &pipeline
->gs_copy_shader
->info
.vs
.outinfo
;
2063 else if (radv_pipeline_has_tess(pipeline
))
2064 return &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.outinfo
;
2066 return &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.outinfo
;
2070 radv_link_shaders(struct radv_pipeline
*pipeline
, nir_shader
**shaders
)
2072 nir_shader
* ordered_shaders
[MESA_SHADER_STAGES
];
2073 int shader_count
= 0;
2075 if(shaders
[MESA_SHADER_FRAGMENT
]) {
2076 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_FRAGMENT
];
2078 if(shaders
[MESA_SHADER_GEOMETRY
]) {
2079 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_GEOMETRY
];
2081 if(shaders
[MESA_SHADER_TESS_EVAL
]) {
2082 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_EVAL
];
2084 if(shaders
[MESA_SHADER_TESS_CTRL
]) {
2085 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_CTRL
];
2087 if(shaders
[MESA_SHADER_VERTEX
]) {
2088 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_VERTEX
];
2091 if (shader_count
> 1) {
2092 unsigned first
= ordered_shaders
[shader_count
- 1]->info
.stage
;
2093 unsigned last
= ordered_shaders
[0]->info
.stage
;
2095 if (ordered_shaders
[0]->info
.stage
== MESA_SHADER_FRAGMENT
&&
2096 ordered_shaders
[1]->info
.has_transform_feedback_varyings
)
2097 nir_link_xfb_varyings(ordered_shaders
[1], ordered_shaders
[0]);
2099 for (int i
= 0; i
< shader_count
; ++i
) {
2100 nir_variable_mode mask
= 0;
2102 if (ordered_shaders
[i
]->info
.stage
!= first
)
2103 mask
= mask
| nir_var_shader_in
;
2105 if (ordered_shaders
[i
]->info
.stage
!= last
)
2106 mask
= mask
| nir_var_shader_out
;
2108 nir_lower_io_to_scalar_early(ordered_shaders
[i
], mask
);
2109 radv_optimize_nir(ordered_shaders
[i
], false, false);
2113 for (int i
= 1; i
< shader_count
; ++i
) {
2114 nir_lower_io_arrays_to_elements(ordered_shaders
[i
],
2115 ordered_shaders
[i
- 1]);
2117 if (nir_link_opt_varyings(ordered_shaders
[i
],
2118 ordered_shaders
[i
- 1]))
2119 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2121 nir_remove_dead_variables(ordered_shaders
[i
],
2122 nir_var_shader_out
);
2123 nir_remove_dead_variables(ordered_shaders
[i
- 1],
2126 bool progress
= nir_remove_unused_varyings(ordered_shaders
[i
],
2127 ordered_shaders
[i
- 1]);
2129 nir_compact_varyings(ordered_shaders
[i
],
2130 ordered_shaders
[i
- 1], true);
2133 if (nir_lower_global_vars_to_local(ordered_shaders
[i
])) {
2134 ac_lower_indirect_derefs(ordered_shaders
[i
],
2135 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2137 radv_optimize_nir(ordered_shaders
[i
], false, false);
2139 if (nir_lower_global_vars_to_local(ordered_shaders
[i
- 1])) {
2140 ac_lower_indirect_derefs(ordered_shaders
[i
- 1],
2141 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2143 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2149 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo
*input_state
,
2150 uint32_t attrib_binding
)
2152 for (uint32_t i
= 0; i
< input_state
->vertexBindingDescriptionCount
; i
++) {
2153 const VkVertexInputBindingDescription
*input_binding
=
2154 &input_state
->pVertexBindingDescriptions
[i
];
2156 if (input_binding
->binding
== attrib_binding
)
2157 return input_binding
->stride
;
2163 static struct radv_pipeline_key
2164 radv_generate_graphics_pipeline_key(struct radv_pipeline
*pipeline
,
2165 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2166 const struct radv_blend_state
*blend
,
2167 bool has_view_index
)
2169 const VkPipelineVertexInputStateCreateInfo
*input_state
=
2170 pCreateInfo
->pVertexInputState
;
2171 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*divisor_state
=
2172 vk_find_struct_const(input_state
->pNext
, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
2174 struct radv_pipeline_key key
;
2175 memset(&key
, 0, sizeof(key
));
2177 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
2178 key
.optimisations_disabled
= 1;
2180 key
.has_multiview_view_index
= has_view_index
;
2182 uint32_t binding_input_rate
= 0;
2183 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
2184 for (unsigned i
= 0; i
< input_state
->vertexBindingDescriptionCount
; ++i
) {
2185 if (input_state
->pVertexBindingDescriptions
[i
].inputRate
) {
2186 unsigned binding
= input_state
->pVertexBindingDescriptions
[i
].binding
;
2187 binding_input_rate
|= 1u << binding
;
2188 instance_rate_divisors
[binding
] = 1;
2191 if (divisor_state
) {
2192 for (unsigned i
= 0; i
< divisor_state
->vertexBindingDivisorCount
; ++i
) {
2193 instance_rate_divisors
[divisor_state
->pVertexBindingDivisors
[i
].binding
] =
2194 divisor_state
->pVertexBindingDivisors
[i
].divisor
;
2198 for (unsigned i
= 0; i
< input_state
->vertexAttributeDescriptionCount
; ++i
) {
2199 const VkVertexInputAttributeDescription
*desc
=
2200 &input_state
->pVertexAttributeDescriptions
[i
];
2201 const struct vk_format_description
*format_desc
;
2202 unsigned location
= desc
->location
;
2203 unsigned binding
= desc
->binding
;
2204 unsigned num_format
, data_format
;
2207 if (binding_input_rate
& (1u << binding
)) {
2208 key
.instance_rate_inputs
|= 1u << location
;
2209 key
.instance_rate_divisors
[location
] = instance_rate_divisors
[binding
];
2212 format_desc
= vk_format_description(desc
->format
);
2213 first_non_void
= vk_format_get_first_non_void_channel(desc
->format
);
2215 num_format
= radv_translate_buffer_numformat(format_desc
, first_non_void
);
2216 data_format
= radv_translate_buffer_dataformat(format_desc
, first_non_void
);
2218 key
.vertex_attribute_formats
[location
] = data_format
| (num_format
<< 4);
2219 key
.vertex_attribute_bindings
[location
] = desc
->binding
;
2220 key
.vertex_attribute_offsets
[location
] = desc
->offset
;
2221 key
.vertex_attribute_strides
[location
] = radv_get_attrib_stride(input_state
, desc
->binding
);
2223 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
&&
2224 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_STONEY
) {
2225 VkFormat format
= input_state
->pVertexAttributeDescriptions
[i
].format
;
2228 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2229 case VK_FORMAT_A2B10G10R10_SNORM_PACK32
:
2230 adjust
= RADV_ALPHA_ADJUST_SNORM
;
2232 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2233 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32
:
2234 adjust
= RADV_ALPHA_ADJUST_SSCALED
;
2236 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2237 case VK_FORMAT_A2B10G10R10_SINT_PACK32
:
2238 adjust
= RADV_ALPHA_ADJUST_SINT
;
2244 key
.vertex_alpha_adjust
|= adjust
<< (2 * location
);
2247 switch (desc
->format
) {
2248 case VK_FORMAT_B8G8R8A8_UNORM
:
2249 case VK_FORMAT_B8G8R8A8_SNORM
:
2250 case VK_FORMAT_B8G8R8A8_USCALED
:
2251 case VK_FORMAT_B8G8R8A8_SSCALED
:
2252 case VK_FORMAT_B8G8R8A8_UINT
:
2253 case VK_FORMAT_B8G8R8A8_SINT
:
2254 case VK_FORMAT_B8G8R8A8_SRGB
:
2255 case VK_FORMAT_A2R10G10B10_UNORM_PACK32
:
2256 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2257 case VK_FORMAT_A2R10G10B10_USCALED_PACK32
:
2258 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2259 case VK_FORMAT_A2R10G10B10_UINT_PACK32
:
2260 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2261 key
.vertex_post_shuffle
|= 1 << location
;
2268 if (pCreateInfo
->pTessellationState
)
2269 key
.tess_input_vertices
= pCreateInfo
->pTessellationState
->patchControlPoints
;
2272 if (pCreateInfo
->pMultisampleState
&&
2273 pCreateInfo
->pMultisampleState
->rasterizationSamples
> 1) {
2274 uint32_t num_samples
= pCreateInfo
->pMultisampleState
->rasterizationSamples
;
2275 uint32_t ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
->pMultisampleState
);
2276 key
.num_samples
= num_samples
;
2277 key
.log2_ps_iter_samples
= util_logbase2(ps_iter_samples
);
2280 key
.col_format
= blend
->spi_shader_col_format
;
2281 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX8
)
2282 radv_pipeline_compute_get_int_clamp(pCreateInfo
, &key
.is_int8
, &key
.is_int10
);
2284 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
2285 key
.topology
= pCreateInfo
->pInputAssemblyState
->topology
;
2291 radv_nir_stage_uses_xfb(const nir_shader
*nir
)
2293 nir_xfb_info
*xfb
= nir_gather_xfb_info(nir
, NULL
);
2294 bool uses_xfb
= !!xfb
;
2301 radv_fill_shader_keys(struct radv_device
*device
,
2302 struct radv_shader_variant_key
*keys
,
2303 const struct radv_pipeline_key
*key
,
2306 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_inputs
= key
->instance_rate_inputs
;
2307 keys
[MESA_SHADER_VERTEX
].vs
.alpha_adjust
= key
->vertex_alpha_adjust
;
2308 keys
[MESA_SHADER_VERTEX
].vs
.post_shuffle
= key
->vertex_post_shuffle
;
2309 for (unsigned i
= 0; i
< MAX_VERTEX_ATTRIBS
; ++i
) {
2310 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_divisors
[i
] = key
->instance_rate_divisors
[i
];
2311 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_formats
[i
] = key
->vertex_attribute_formats
[i
];
2312 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_bindings
[i
] = key
->vertex_attribute_bindings
[i
];
2313 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_offsets
[i
] = key
->vertex_attribute_offsets
[i
];
2314 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_strides
[i
] = key
->vertex_attribute_strides
[i
];
2316 keys
[MESA_SHADER_VERTEX
].vs
.outprim
= si_conv_prim_to_gs_out(key
->topology
);
2318 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2319 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ls
= true;
2320 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= 0;
2321 keys
[MESA_SHADER_TESS_CTRL
].tcs
.input_vertices
= key
->tess_input_vertices
;
2322 keys
[MESA_SHADER_TESS_CTRL
].tcs
.primitive_mode
= nir
[MESA_SHADER_TESS_EVAL
]->info
.tess
.primitive_mode
;
2324 keys
[MESA_SHADER_TESS_CTRL
].tcs
.tes_reads_tess_factors
= !!(nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
& (VARYING_BIT_TESS_LEVEL_INNER
| VARYING_BIT_TESS_LEVEL_OUTER
));
2327 if (nir
[MESA_SHADER_GEOMETRY
]) {
2328 if (nir
[MESA_SHADER_TESS_CTRL
])
2329 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_es
= true;
2331 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_es
= true;
2334 if (device
->physical_device
->use_ngg
) {
2335 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2336 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= true;
2338 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= true;
2341 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2342 nir
[MESA_SHADER_GEOMETRY
] &&
2343 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.invocations
*
2344 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.vertices_out
> 256) {
2345 /* Fallback to the legacy path if tessellation is
2346 * enabled with extreme geometry because
2347 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2350 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2354 * Disable NGG with geometry shaders. There are a bunch of
2356 * * GS primitives in pipeline statistic queries do not get
2357 * updates. See dEQP-VK.query_pool.statistics_query.geometry_shader_primitives
2359 * Furthermore, XGL/AMDVLK also disables this as of 9b632ef.
2361 if (nir
[MESA_SHADER_GEOMETRY
]) {
2362 if (nir
[MESA_SHADER_TESS_CTRL
])
2363 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2365 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2368 if (!device
->physical_device
->use_ngg_streamout
) {
2369 gl_shader_stage last_xfb_stage
= MESA_SHADER_VERTEX
;
2371 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2376 if (nir
[last_xfb_stage
] &&
2377 radv_nir_stage_uses_xfb(nir
[last_xfb_stage
])) {
2378 if (nir
[MESA_SHADER_TESS_CTRL
])
2379 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2381 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2386 for(int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
2387 keys
[i
].has_multiview_view_index
= key
->has_multiview_view_index
;
2389 keys
[MESA_SHADER_FRAGMENT
].fs
.col_format
= key
->col_format
;
2390 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int8
= key
->is_int8
;
2391 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int10
= key
->is_int10
;
2392 keys
[MESA_SHADER_FRAGMENT
].fs
.log2_ps_iter_samples
= key
->log2_ps_iter_samples
;
2393 keys
[MESA_SHADER_FRAGMENT
].fs
.num_samples
= key
->num_samples
;
2395 if (nir
[MESA_SHADER_COMPUTE
]) {
2396 keys
[MESA_SHADER_COMPUTE
].cs
.subgroup_size
= key
->compute_subgroup_size
;
2401 radv_get_wave_size(struct radv_device
*device
,
2402 const VkPipelineShaderStageCreateInfo
*pStage
,
2403 gl_shader_stage stage
,
2404 const struct radv_shader_variant_key
*key
)
2406 if (stage
== MESA_SHADER_GEOMETRY
&& !key
->vs_common_out
.as_ngg
)
2408 else if (stage
== MESA_SHADER_COMPUTE
) {
2409 if (key
->cs
.subgroup_size
) {
2410 /* Return the required subgroup size if specified. */
2411 return key
->cs
.subgroup_size
;
2413 return device
->physical_device
->cs_wave_size
;
2415 else if (stage
== MESA_SHADER_FRAGMENT
)
2416 return device
->physical_device
->ps_wave_size
;
2418 return device
->physical_device
->ge_wave_size
;
2422 radv_fill_shader_info(struct radv_pipeline
*pipeline
,
2423 const VkPipelineShaderStageCreateInfo
**pStages
,
2424 struct radv_shader_variant_key
*keys
,
2425 struct radv_shader_info
*infos
,
2428 unsigned active_stages
= 0;
2429 unsigned filled_stages
= 0;
2431 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2433 active_stages
|= (1 << i
);
2436 if (nir
[MESA_SHADER_FRAGMENT
]) {
2437 radv_nir_shader_info_init(&infos
[MESA_SHADER_FRAGMENT
]);
2438 radv_nir_shader_info_pass(nir
[MESA_SHADER_FRAGMENT
],
2440 &keys
[MESA_SHADER_FRAGMENT
],
2441 &infos
[MESA_SHADER_FRAGMENT
]);
2443 /* TODO: These are no longer used as keys we should refactor this */
2444 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
=
2445 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2446 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_layer_id
=
2447 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2448 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_clip_dists
=
2449 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2450 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_prim_id
=
2451 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2452 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_layer_id
=
2453 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2454 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_clip_dists
=
2455 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2457 filled_stages
|= (1 << MESA_SHADER_FRAGMENT
);
2460 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2461 nir
[MESA_SHADER_TESS_CTRL
]) {
2462 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2463 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2464 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2466 radv_nir_shader_info_init(&infos
[MESA_SHADER_TESS_CTRL
]);
2468 for (int i
= 0; i
< 2; i
++) {
2469 radv_nir_shader_info_pass(combined_nir
[i
],
2470 pipeline
->layout
, &key
,
2471 &infos
[MESA_SHADER_TESS_CTRL
]);
2474 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2475 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2476 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2477 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2479 filled_stages
|= (1 << MESA_SHADER_VERTEX
);
2480 filled_stages
|= (1 << MESA_SHADER_TESS_CTRL
);
2483 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2484 nir
[MESA_SHADER_GEOMETRY
]) {
2485 gl_shader_stage pre_stage
= nir
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2486 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2488 radv_nir_shader_info_init(&infos
[MESA_SHADER_GEOMETRY
]);
2490 for (int i
= 0; i
< 2; i
++) {
2491 radv_nir_shader_info_pass(combined_nir
[i
],
2494 &infos
[MESA_SHADER_GEOMETRY
]);
2497 filled_stages
|= (1 << pre_stage
);
2498 filled_stages
|= (1 << MESA_SHADER_GEOMETRY
);
2501 active_stages
^= filled_stages
;
2502 while (active_stages
) {
2503 int i
= u_bit_scan(&active_stages
);
2505 if (i
== MESA_SHADER_TESS_CTRL
) {
2506 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
=
2507 util_last_bit64(infos
[MESA_SHADER_VERTEX
].vs
.ls_outputs_written
);
2510 if (i
== MESA_SHADER_TESS_EVAL
) {
2511 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2512 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2513 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2514 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2517 radv_nir_shader_info_init(&infos
[i
]);
2518 radv_nir_shader_info_pass(nir
[i
], pipeline
->layout
,
2519 &keys
[i
], &infos
[i
]);
2522 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2524 infos
[i
].wave_size
=
2525 radv_get_wave_size(pipeline
->device
, pStages
[i
],
2531 merge_tess_info(struct shader_info
*tes_info
,
2532 const struct shader_info
*tcs_info
)
2534 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2536 * "PointMode. Controls generation of points rather than triangles
2537 * or lines. This functionality defaults to disabled, and is
2538 * enabled if either shader stage includes the execution mode.
2540 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2541 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2542 * and OutputVertices, it says:
2544 * "One mode must be set in at least one of the tessellation
2547 * So, the fields can be set in either the TCS or TES, but they must
2548 * agree if set in both. Our backend looks at TES, so bitwise-or in
2549 * the values from the TCS.
2551 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
2552 tes_info
->tess
.tcs_vertices_out
== 0 ||
2553 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
2554 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
2556 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2557 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2558 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
2559 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
2561 assert(tcs_info
->tess
.primitive_mode
== 0 ||
2562 tes_info
->tess
.primitive_mode
== 0 ||
2563 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
2564 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
2565 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
2566 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
2570 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT
*ext
)
2575 if (ext
->pPipelineCreationFeedback
) {
2576 ext
->pPipelineCreationFeedback
->flags
= 0;
2577 ext
->pPipelineCreationFeedback
->duration
= 0;
2580 for (unsigned i
= 0; i
< ext
->pipelineStageCreationFeedbackCount
; ++i
) {
2581 ext
->pPipelineStageCreationFeedbacks
[i
].flags
= 0;
2582 ext
->pPipelineStageCreationFeedbacks
[i
].duration
= 0;
2587 void radv_start_feedback(VkPipelineCreationFeedbackEXT
*feedback
)
2592 feedback
->duration
-= radv_get_current_time();
2593 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
2597 void radv_stop_feedback(VkPipelineCreationFeedbackEXT
*feedback
, bool cache_hit
)
2602 feedback
->duration
+= radv_get_current_time();
2603 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
|
2604 (cache_hit
? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
: 0);
2608 bool radv_aco_supported_stage(gl_shader_stage stage
, bool has_gs
, bool has_ts
)
2610 return (stage
== MESA_SHADER_VERTEX
&& !has_gs
&& !has_ts
) ||
2611 stage
== MESA_SHADER_FRAGMENT
||
2612 stage
== MESA_SHADER_COMPUTE
;
2615 void radv_create_shaders(struct radv_pipeline
*pipeline
,
2616 struct radv_device
*device
,
2617 struct radv_pipeline_cache
*cache
,
2618 const struct radv_pipeline_key
*key
,
2619 const VkPipelineShaderStageCreateInfo
**pStages
,
2620 const VkPipelineCreateFlags flags
,
2621 VkPipelineCreationFeedbackEXT
*pipeline_feedback
,
2622 VkPipelineCreationFeedbackEXT
**stage_feedbacks
)
2624 struct radv_shader_module fs_m
= {0};
2625 struct radv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
2626 nir_shader
*nir
[MESA_SHADER_STAGES
] = {0};
2627 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2628 struct radv_shader_variant_key keys
[MESA_SHADER_STAGES
] = {{{{{0}}}}};
2629 struct radv_shader_info infos
[MESA_SHADER_STAGES
] = {0};
2630 unsigned char hash
[20], gs_copy_hash
[20];
2631 bool keep_executable_info
= (flags
& VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
) || device
->keep_shader_info
;
2633 radv_start_feedback(pipeline_feedback
);
2635 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2637 modules
[i
] = radv_shader_module_from_handle(pStages
[i
]->module
);
2638 if (modules
[i
]->nir
)
2639 _mesa_sha1_compute(modules
[i
]->nir
->info
.name
,
2640 strlen(modules
[i
]->nir
->info
.name
),
2643 pipeline
->active_stages
|= mesa_to_vk_shader_stage(i
);
2647 radv_hash_shaders(hash
, pStages
, pipeline
->layout
, key
, get_hash_flags(device
));
2648 memcpy(gs_copy_hash
, hash
, 20);
2649 gs_copy_hash
[0] ^= 1;
2651 bool found_in_application_cache
= true;
2652 if (modules
[MESA_SHADER_GEOMETRY
] && !keep_executable_info
) {
2653 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2654 radv_create_shader_variants_from_pipeline_cache(device
, cache
, gs_copy_hash
, variants
,
2655 &found_in_application_cache
);
2656 pipeline
->gs_copy_shader
= variants
[MESA_SHADER_GEOMETRY
];
2659 if (!keep_executable_info
&&
2660 radv_create_shader_variants_from_pipeline_cache(device
, cache
, hash
, pipeline
->shaders
,
2661 &found_in_application_cache
) &&
2662 (!modules
[MESA_SHADER_GEOMETRY
] || pipeline
->gs_copy_shader
)) {
2663 radv_stop_feedback(pipeline_feedback
, found_in_application_cache
);
2667 if (!modules
[MESA_SHADER_FRAGMENT
] && !modules
[MESA_SHADER_COMPUTE
]) {
2669 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
2670 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "noop_fs");
2671 fs_m
.nir
= fs_b
.shader
;
2672 modules
[MESA_SHADER_FRAGMENT
] = &fs_m
;
2675 bool has_gs
= modules
[MESA_SHADER_GEOMETRY
];
2676 bool has_ts
= modules
[MESA_SHADER_TESS_CTRL
] || modules
[MESA_SHADER_TESS_EVAL
];
2677 bool use_aco
= device
->physical_device
->use_aco
;
2679 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2680 const VkPipelineShaderStageCreateInfo
*stage
= pStages
[i
];
2685 radv_start_feedback(stage_feedbacks
[i
]);
2687 bool aco
= use_aco
&& radv_aco_supported_stage(i
, has_gs
, has_ts
);
2688 nir
[i
] = radv_shader_compile_to_nir(device
, modules
[i
],
2689 stage
? stage
->pName
: "main", i
,
2690 stage
? stage
->pSpecializationInfo
: NULL
,
2691 flags
, pipeline
->layout
, aco
);
2693 /* We don't want to alter meta shaders IR directly so clone it
2696 if (nir
[i
]->info
.name
) {
2697 nir
[i
] = nir_shader_clone(NULL
, nir
[i
]);
2700 radv_stop_feedback(stage_feedbacks
[i
], false);
2703 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2704 nir_lower_patch_vertices(nir
[MESA_SHADER_TESS_EVAL
], nir
[MESA_SHADER_TESS_CTRL
]->info
.tess
.tcs_vertices_out
, NULL
);
2705 merge_tess_info(&nir
[MESA_SHADER_TESS_EVAL
]->info
, &nir
[MESA_SHADER_TESS_CTRL
]->info
);
2708 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
2709 radv_link_shaders(pipeline
, nir
);
2711 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2713 NIR_PASS_V(nir
[i
], nir_lower_non_uniform_access
,
2714 nir_lower_non_uniform_ubo_access
|
2715 nir_lower_non_uniform_ssbo_access
|
2716 nir_lower_non_uniform_texture_access
|
2717 nir_lower_non_uniform_image_access
);
2719 bool aco
= use_aco
&& radv_aco_supported_stage(i
, has_gs
, has_ts
);
2721 NIR_PASS_V(nir
[i
], nir_lower_bool_to_int32
);
2724 if (radv_can_dump_shader(device
, modules
[i
], false))
2725 nir_print_shader(nir
[i
], stderr
);
2728 if (nir
[MESA_SHADER_FRAGMENT
])
2729 radv_lower_fs_io(nir
[MESA_SHADER_FRAGMENT
]);
2731 radv_fill_shader_keys(device
, keys
, key
, nir
);
2733 radv_fill_shader_info(pipeline
, pStages
, keys
, infos
, nir
);
2735 if ((nir
[MESA_SHADER_VERTEX
] &&
2736 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) ||
2737 (nir
[MESA_SHADER_TESS_EVAL
] &&
2738 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
)) {
2739 struct gfx10_ngg_info
*ngg_info
;
2741 if (nir
[MESA_SHADER_GEOMETRY
])
2742 ngg_info
= &infos
[MESA_SHADER_GEOMETRY
].ngg_info
;
2743 else if (nir
[MESA_SHADER_TESS_CTRL
])
2744 ngg_info
= &infos
[MESA_SHADER_TESS_EVAL
].ngg_info
;
2746 ngg_info
= &infos
[MESA_SHADER_VERTEX
].ngg_info
;
2748 gfx10_get_ngg_info(key
, pipeline
, nir
, infos
, ngg_info
);
2749 } else if (nir
[MESA_SHADER_GEOMETRY
]) {
2750 struct gfx9_gs_info
*gs_info
=
2751 &infos
[MESA_SHADER_GEOMETRY
].gs_ring_info
;
2753 gfx9_get_gs_info(key
, pipeline
, nir
, infos
, gs_info
);
2756 if (nir
[MESA_SHADER_FRAGMENT
]) {
2757 if (!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]) {
2758 radv_start_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
]);
2760 bool aco
= use_aco
&& radv_aco_supported_stage(MESA_SHADER_FRAGMENT
, has_gs
, has_ts
);
2761 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] =
2762 radv_shader_variant_compile(device
, modules
[MESA_SHADER_FRAGMENT
], &nir
[MESA_SHADER_FRAGMENT
], 1,
2763 pipeline
->layout
, keys
+ MESA_SHADER_FRAGMENT
,
2764 infos
+ MESA_SHADER_FRAGMENT
,
2765 keep_executable_info
, aco
,
2766 &binaries
[MESA_SHADER_FRAGMENT
]);
2768 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
], false);
2771 /* TODO: These are no longer used as keys we should refactor this */
2772 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
=
2773 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.prim_id_input
;
2774 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_layer_id
=
2775 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.layer_input
;
2776 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_clip_dists
=
2777 !!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.num_input_clips_culls
;
2778 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_prim_id
=
2779 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.prim_id_input
;
2780 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_layer_id
=
2781 pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.layer_input
;
2782 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_clip_dists
=
2783 !!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.num_input_clips_culls
;
2786 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_TESS_CTRL
]) {
2787 if (!pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]) {
2788 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2789 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2790 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2792 radv_start_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
]);
2794 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_TESS_CTRL
], combined_nir
, 2,
2796 &key
, &infos
[MESA_SHADER_TESS_CTRL
], keep_executable_info
,
2797 false, &binaries
[MESA_SHADER_TESS_CTRL
]);
2799 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
], false);
2801 modules
[MESA_SHADER_VERTEX
] = NULL
;
2802 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2803 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2806 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_GEOMETRY
]) {
2807 gl_shader_stage pre_stage
= modules
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2808 if (!pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
2809 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2811 radv_start_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
]);
2813 pipeline
->shaders
[MESA_SHADER_GEOMETRY
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_GEOMETRY
], combined_nir
, 2,
2815 &keys
[pre_stage
], &infos
[MESA_SHADER_GEOMETRY
], keep_executable_info
,
2816 false, &binaries
[MESA_SHADER_GEOMETRY
]);
2818 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
], false);
2820 modules
[pre_stage
] = NULL
;
2823 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2824 if(modules
[i
] && !pipeline
->shaders
[i
]) {
2825 if (i
== MESA_SHADER_TESS_CTRL
) {
2826 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.ls_outputs_written
);
2828 if (i
== MESA_SHADER_TESS_EVAL
) {
2829 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2830 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2833 radv_start_feedback(stage_feedbacks
[i
]);
2835 bool aco
= use_aco
&& radv_aco_supported_stage(i
, has_gs
, has_ts
);
2836 pipeline
->shaders
[i
] = radv_shader_variant_compile(device
, modules
[i
], &nir
[i
], 1,
2838 keys
+ i
, infos
+ i
,keep_executable_info
,
2841 radv_stop_feedback(stage_feedbacks
[i
], false);
2845 if(modules
[MESA_SHADER_GEOMETRY
]) {
2846 struct radv_shader_binary
*gs_copy_binary
= NULL
;
2847 if (!pipeline
->gs_copy_shader
&&
2848 !radv_pipeline_has_ngg(pipeline
)) {
2849 struct radv_shader_info info
= {};
2850 struct radv_shader_variant_key key
= {};
2852 key
.has_multiview_view_index
=
2853 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
;
2855 radv_nir_shader_info_pass(nir
[MESA_SHADER_GEOMETRY
],
2856 pipeline
->layout
, &key
,
2858 info
.wave_size
= 64; /* Wave32 not supported. */
2860 pipeline
->gs_copy_shader
= radv_create_gs_copy_shader(
2861 device
, nir
[MESA_SHADER_GEOMETRY
], &info
,
2862 &gs_copy_binary
, keep_executable_info
,
2863 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
);
2866 if (!keep_executable_info
&& pipeline
->gs_copy_shader
) {
2867 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2868 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2870 binaries
[MESA_SHADER_GEOMETRY
] = gs_copy_binary
;
2871 variants
[MESA_SHADER_GEOMETRY
] = pipeline
->gs_copy_shader
;
2873 radv_pipeline_cache_insert_shaders(device
, cache
,
2878 free(gs_copy_binary
);
2881 if (!keep_executable_info
) {
2882 radv_pipeline_cache_insert_shaders(device
, cache
, hash
, pipeline
->shaders
,
2886 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2889 ralloc_free(nir
[i
]);
2891 if (radv_can_dump_shader_stats(device
, modules
[i
]))
2892 radv_shader_dump_stats(device
,
2893 pipeline
->shaders
[i
],
2899 ralloc_free(fs_m
.nir
);
2901 radv_stop_feedback(pipeline_feedback
, false);
2905 radv_pipeline_stage_to_user_data_0(struct radv_pipeline
*pipeline
,
2906 gl_shader_stage stage
, enum chip_class chip_class
)
2908 bool has_gs
= radv_pipeline_has_gs(pipeline
);
2909 bool has_tess
= radv_pipeline_has_tess(pipeline
);
2910 bool has_ngg
= radv_pipeline_has_ngg(pipeline
);
2913 case MESA_SHADER_FRAGMENT
:
2914 return R_00B030_SPI_SHADER_USER_DATA_PS_0
;
2915 case MESA_SHADER_VERTEX
:
2917 if (chip_class
>= GFX10
) {
2918 return R_00B430_SPI_SHADER_USER_DATA_HS_0
;
2919 } else if (chip_class
== GFX9
) {
2920 return R_00B430_SPI_SHADER_USER_DATA_LS_0
;
2922 return R_00B530_SPI_SHADER_USER_DATA_LS_0
;
2928 if (chip_class
>= GFX10
) {
2929 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
2931 return R_00B330_SPI_SHADER_USER_DATA_ES_0
;
2936 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
2938 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2939 case MESA_SHADER_GEOMETRY
:
2940 return chip_class
== GFX9
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
2941 R_00B230_SPI_SHADER_USER_DATA_GS_0
;
2942 case MESA_SHADER_COMPUTE
:
2943 return R_00B900_COMPUTE_USER_DATA_0
;
2944 case MESA_SHADER_TESS_CTRL
:
2945 return chip_class
== GFX9
? R_00B430_SPI_SHADER_USER_DATA_LS_0
:
2946 R_00B430_SPI_SHADER_USER_DATA_HS_0
;
2947 case MESA_SHADER_TESS_EVAL
:
2949 return chip_class
>= GFX10
? R_00B230_SPI_SHADER_USER_DATA_GS_0
:
2950 R_00B330_SPI_SHADER_USER_DATA_ES_0
;
2951 } else if (has_ngg
) {
2952 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
2954 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
2957 unreachable("unknown shader");
2961 struct radv_bin_size_entry
{
2967 radv_gfx9_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
2969 static const struct radv_bin_size_entry color_size_table
[][3][9] = {
2973 /* One shader engine */
2979 { UINT_MAX
, { 0, 0}},
2982 /* Two shader engines */
2988 { UINT_MAX
, { 0, 0}},
2991 /* Four shader engines */
2996 { UINT_MAX
, { 0, 0}},
3002 /* One shader engine */
3008 { UINT_MAX
, { 0, 0}},
3011 /* Two shader engines */
3017 { UINT_MAX
, { 0, 0}},
3020 /* Four shader engines */
3027 { UINT_MAX
, { 0, 0}},
3033 /* One shader engine */
3040 { UINT_MAX
, { 0, 0}},
3043 /* Two shader engines */
3051 { UINT_MAX
, { 0, 0}},
3054 /* Four shader engines */
3062 { UINT_MAX
, { 0, 0}},
3066 static const struct radv_bin_size_entry ds_size_table
[][3][9] = {
3070 // One shader engine
3077 { UINT_MAX
, { 0, 0}},
3080 // Two shader engines
3088 { UINT_MAX
, { 0, 0}},
3091 // Four shader engines
3099 { UINT_MAX
, { 0, 0}},
3105 // One shader engine
3113 { UINT_MAX
, { 0, 0}},
3116 // Two shader engines
3125 { UINT_MAX
, { 0, 0}},
3128 // Four shader engines
3137 { UINT_MAX
, { 0, 0}},
3143 // One shader engine
3151 { UINT_MAX
, { 0, 0}},
3154 // Two shader engines
3163 { UINT_MAX
, { 0, 0}},
3166 // Four shader engines
3174 { UINT_MAX
, { 0, 0}},
3179 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3180 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3181 VkExtent2D extent
= {512, 512};
3183 unsigned log_num_rb_per_se
=
3184 util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.num_render_backends
/
3185 pipeline
->device
->physical_device
->rad_info
.max_se
);
3186 unsigned log_num_se
= util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.max_se
);
3188 unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3189 unsigned ps_iter_samples
= 1u << G_028804_PS_ITER_SAMPLES(pipeline
->graphics
.ms
.db_eqaa
);
3190 unsigned effective_samples
= total_samples
;
3191 unsigned color_bytes_per_pixel
= 0;
3193 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
3195 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3196 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3199 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3202 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3203 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3206 /* MSAA images typically don't use all samples all the time. */
3207 if (effective_samples
>= 2 && ps_iter_samples
<= 1)
3208 effective_samples
= 2;
3209 color_bytes_per_pixel
*= effective_samples
;
3212 const struct radv_bin_size_entry
*color_entry
= color_size_table
[log_num_rb_per_se
][log_num_se
];
3213 while(color_entry
[1].bpp
<= color_bytes_per_pixel
)
3216 extent
= color_entry
->extent
;
3218 if (subpass
->depth_stencil_attachment
) {
3219 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3221 /* Coefficients taken from AMDVLK */
3222 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3223 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3224 unsigned ds_bytes_per_pixel
= 4 * (depth_coeff
+ stencil_coeff
) * total_samples
;
3226 const struct radv_bin_size_entry
*ds_entry
= ds_size_table
[log_num_rb_per_se
][log_num_se
];
3227 while(ds_entry
[1].bpp
<= ds_bytes_per_pixel
)
3230 if (ds_entry
->extent
.width
* ds_entry
->extent
.height
< extent
.width
* extent
.height
)
3231 extent
= ds_entry
->extent
;
3238 radv_gfx10_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3240 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3241 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3242 VkExtent2D extent
= {512, 512};
3244 const unsigned db_tag_size
= 64;
3245 const unsigned db_tag_count
= 312;
3246 const unsigned color_tag_size
= 1024;
3247 const unsigned color_tag_count
= 31;
3248 const unsigned fmask_tag_size
= 256;
3249 const unsigned fmask_tag_count
= 44;
3251 const unsigned rb_count
= pipeline
->device
->physical_device
->rad_info
.num_render_backends
;
3252 const unsigned pipe_count
= MAX2(rb_count
, pipeline
->device
->physical_device
->rad_info
.num_sdp_interfaces
);
3254 const unsigned db_tag_part
= (db_tag_count
* rb_count
/ pipe_count
) * db_tag_size
* pipe_count
;
3255 const unsigned color_tag_part
= (color_tag_count
* rb_count
/ pipe_count
) * color_tag_size
* pipe_count
;
3256 const unsigned fmask_tag_part
= (fmask_tag_count
* rb_count
/ pipe_count
) * fmask_tag_size
* pipe_count
;
3258 const unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3259 const unsigned samples_log
= util_logbase2_ceil(total_samples
);
3261 unsigned color_bytes_per_pixel
= 0;
3262 unsigned fmask_bytes_per_pixel
= 0;
3264 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
3266 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3267 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3270 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3273 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3274 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3276 if (total_samples
> 1) {
3277 assert(samples_log
<= 3);
3278 const unsigned fmask_array
[] = {0, 1, 1, 4};
3279 fmask_bytes_per_pixel
+= fmask_array
[samples_log
];
3283 color_bytes_per_pixel
*= total_samples
;
3285 color_bytes_per_pixel
= MAX2(color_bytes_per_pixel
, 1);
3287 const unsigned color_pixel_count_log
= util_logbase2(color_tag_part
/ color_bytes_per_pixel
);
3288 extent
.width
= 1ull << ((color_pixel_count_log
+ 1) / 2);
3289 extent
.height
= 1ull << (color_pixel_count_log
/ 2);
3291 if (fmask_bytes_per_pixel
) {
3292 const unsigned fmask_pixel_count_log
= util_logbase2(fmask_tag_part
/ fmask_bytes_per_pixel
);
3294 const VkExtent2D fmask_extent
= (VkExtent2D
){
3295 .width
= 1ull << ((fmask_pixel_count_log
+ 1) / 2),
3296 .height
= 1ull << (color_pixel_count_log
/ 2)
3299 if (fmask_extent
.width
* fmask_extent
.height
< extent
.width
* extent
.height
)
3300 extent
= fmask_extent
;
3303 if (subpass
->depth_stencil_attachment
) {
3304 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3306 /* Coefficients taken from AMDVLK */
3307 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3308 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3309 unsigned db_bytes_per_pixel
= (depth_coeff
+ stencil_coeff
) * total_samples
;
3311 const unsigned db_pixel_count_log
= util_logbase2(db_tag_part
/ db_bytes_per_pixel
);
3313 const VkExtent2D db_extent
= (VkExtent2D
){
3314 .width
= 1ull << ((db_pixel_count_log
+ 1) / 2),
3315 .height
= 1ull << (color_pixel_count_log
/ 2)
3318 if (db_extent
.width
* db_extent
.height
< extent
.width
* extent
.height
)
3322 extent
.width
= MAX2(extent
.width
, 128);
3323 extent
.height
= MAX2(extent
.width
, 64);
3329 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3330 struct radv_pipeline
*pipeline
,
3331 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3333 uint32_t pa_sc_binner_cntl_0
=
3334 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC
) |
3335 S_028C44_DISABLE_START_OF_PRIM(1);
3336 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3338 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3339 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3340 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3341 const VkPipelineColorBlendStateCreateInfo
*vkblend
= pCreateInfo
->pColorBlendState
;
3342 unsigned min_bytes_per_pixel
= 0;
3345 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3346 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3349 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3352 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3353 unsigned bytes
= vk_format_get_blocksize(format
);
3354 if (!min_bytes_per_pixel
|| bytes
< min_bytes_per_pixel
)
3355 min_bytes_per_pixel
= bytes
;
3359 pa_sc_binner_cntl_0
=
3360 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC
) |
3361 S_028C44_BIN_SIZE_X(0) |
3362 S_028C44_BIN_SIZE_Y(0) |
3363 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3364 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel
<= 4 ? 2 : 1) | /* 128 or 64 */
3365 S_028C44_DISABLE_START_OF_PRIM(1);
3368 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3369 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3373 radv_pipeline_generate_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3374 struct radv_pipeline
*pipeline
,
3375 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3376 const struct radv_blend_state
*blend
)
3378 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
3381 VkExtent2D bin_size
;
3382 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3383 bin_size
= radv_gfx10_compute_bin_size(pipeline
, pCreateInfo
);
3384 } else if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3385 bin_size
= radv_gfx9_compute_bin_size(pipeline
, pCreateInfo
);
3387 unreachable("Unhandled generation for binning bin size calculation");
3389 if (pipeline
->device
->pbb_allowed
&& bin_size
.width
&& bin_size
.height
) {
3390 unsigned context_states_per_bin
; /* allowed range: [1, 6] */
3391 unsigned persistent_states_per_bin
; /* allowed range: [1, 32] */
3392 unsigned fpovs_per_batch
; /* allowed range: [0, 255], 0 = unlimited */
3394 if (pipeline
->device
->physical_device
->rad_info
.has_dedicated_vram
) {
3395 context_states_per_bin
= 1;
3396 persistent_states_per_bin
= 1;
3397 fpovs_per_batch
= 63;
3399 /* The context states are affected by the scissor bug. */
3400 context_states_per_bin
= pipeline
->device
->physical_device
->rad_info
.has_gfx9_scissor_bug
? 1 : 6;
3401 /* 32 causes hangs for RAVEN. */
3402 persistent_states_per_bin
= 16;
3403 fpovs_per_batch
= 63;
3406 bool disable_start_of_prim
= true;
3407 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3409 const struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3411 if (pipeline
->device
->dfsm_allowed
&& ps
&&
3412 !ps
->info
.ps
.can_discard
&&
3413 !ps
->info
.ps
.writes_memory
&&
3414 blend
->cb_target_enabled_4bit
) {
3415 db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_AUTO
);
3416 disable_start_of_prim
= (blend
->blend_enable_4bit
& blend
->cb_target_enabled_4bit
) != 0;
3419 const uint32_t pa_sc_binner_cntl_0
=
3420 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED
) |
3421 S_028C44_BIN_SIZE_X(bin_size
.width
== 16) |
3422 S_028C44_BIN_SIZE_Y(bin_size
.height
== 16) |
3423 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size
.width
, 32)) - 5) |
3424 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size
.height
, 32)) - 5) |
3425 S_028C44_CONTEXT_STATES_PER_BIN(context_states_per_bin
- 1) |
3426 S_028C44_PERSISTENT_STATES_PER_BIN(persistent_states_per_bin
- 1) |
3427 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim
) |
3428 S_028C44_FPOVS_PER_BATCH(fpovs_per_batch
) |
3429 S_028C44_OPTIMAL_BIN_SELECTION(1);
3431 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3432 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3434 radv_pipeline_generate_disabled_binning_state(ctx_cs
, pipeline
, pCreateInfo
);
3439 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf
*ctx_cs
,
3440 struct radv_pipeline
*pipeline
,
3441 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3442 const struct radv_graphics_pipeline_create_info
*extra
)
3444 const VkPipelineDepthStencilStateCreateInfo
*vkds
= pCreateInfo
->pDepthStencilState
;
3445 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3446 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3447 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3448 struct radv_render_pass_attachment
*attachment
= NULL
;
3449 uint32_t db_depth_control
= 0, db_stencil_control
= 0;
3450 uint32_t db_render_control
= 0, db_render_override2
= 0;
3451 uint32_t db_render_override
= 0;
3453 if (subpass
->depth_stencil_attachment
)
3454 attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3456 bool has_depth_attachment
= attachment
&& vk_format_is_depth(attachment
->format
);
3457 bool has_stencil_attachment
= attachment
&& vk_format_is_stencil(attachment
->format
);
3459 if (vkds
&& has_depth_attachment
) {
3460 db_depth_control
= S_028800_Z_ENABLE(vkds
->depthTestEnable
? 1 : 0) |
3461 S_028800_Z_WRITE_ENABLE(vkds
->depthWriteEnable
? 1 : 0) |
3462 S_028800_ZFUNC(vkds
->depthCompareOp
) |
3463 S_028800_DEPTH_BOUNDS_ENABLE(vkds
->depthBoundsTestEnable
? 1 : 0);
3465 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3466 db_render_override2
|= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment
->samples
> 2);
3469 if (has_stencil_attachment
&& vkds
&& vkds
->stencilTestEnable
) {
3470 db_depth_control
|= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3471 db_depth_control
|= S_028800_STENCILFUNC(vkds
->front
.compareOp
);
3472 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds
->front
.failOp
));
3473 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds
->front
.passOp
));
3474 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds
->front
.depthFailOp
));
3476 db_depth_control
|= S_028800_STENCILFUNC_BF(vkds
->back
.compareOp
);
3477 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds
->back
.failOp
));
3478 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds
->back
.passOp
));
3479 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds
->back
.depthFailOp
));
3482 if (attachment
&& extra
) {
3483 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(extra
->db_depth_clear
);
3484 db_render_control
|= S_028000_STENCIL_CLEAR_ENABLE(extra
->db_stencil_clear
);
3486 db_render_control
|= S_028000_RESUMMARIZE_ENABLE(extra
->db_resummarize
);
3487 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(extra
->db_flush_depth_inplace
);
3488 db_render_control
|= S_028000_STENCIL_COMPRESS_DISABLE(extra
->db_flush_stencil_inplace
);
3489 db_render_override2
|= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra
->db_depth_disable_expclear
);
3490 db_render_override2
|= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra
->db_stencil_disable_expclear
);
3493 db_render_override
|= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
3494 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
3496 if (!pCreateInfo
->pRasterizationState
->depthClampEnable
&&
3497 ps
->info
.ps
.writes_z
) {
3498 /* From VK_EXT_depth_range_unrestricted spec:
3500 * "The behavior described in Primitive Clipping still applies.
3501 * If depth clamping is disabled the depth values are still
3502 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3503 * depth clamping is enabled the above equation is ignored and
3504 * the depth values are instead clamped to the VkViewport
3505 * minDepth and maxDepth values, which in the case of this
3506 * extension can be outside of the 0.0 to 1.0 range."
3508 db_render_override
|= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3511 radeon_set_context_reg(ctx_cs
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
3512 radeon_set_context_reg(ctx_cs
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
3514 radeon_set_context_reg(ctx_cs
, R_028000_DB_RENDER_CONTROL
, db_render_control
);
3515 radeon_set_context_reg(ctx_cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
3516 radeon_set_context_reg(ctx_cs
, R_028010_DB_RENDER_OVERRIDE2
, db_render_override2
);
3520 radv_pipeline_generate_blend_state(struct radeon_cmdbuf
*ctx_cs
,
3521 struct radv_pipeline
*pipeline
,
3522 const struct radv_blend_state
*blend
)
3524 radeon_set_context_reg_seq(ctx_cs
, R_028780_CB_BLEND0_CONTROL
, 8);
3525 radeon_emit_array(ctx_cs
, blend
->cb_blend_control
,
3527 radeon_set_context_reg(ctx_cs
, R_028808_CB_COLOR_CONTROL
, blend
->cb_color_control
);
3528 radeon_set_context_reg(ctx_cs
, R_028B70_DB_ALPHA_TO_MASK
, blend
->db_alpha_to_mask
);
3530 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
3532 radeon_set_context_reg_seq(ctx_cs
, R_028760_SX_MRT0_BLEND_OPT
, 8);
3533 radeon_emit_array(ctx_cs
, blend
->sx_mrt_blend_opt
, 8);
3536 radeon_set_context_reg(ctx_cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
3538 radeon_set_context_reg(ctx_cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
3539 radeon_set_context_reg(ctx_cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
3541 pipeline
->graphics
.col_format
= blend
->spi_shader_col_format
;
3542 pipeline
->graphics
.cb_target_mask
= blend
->cb_target_mask
;
3545 static const VkConservativeRasterizationModeEXT
3546 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo
*pCreateInfo
)
3548 const VkPipelineRasterizationConservativeStateCreateInfoEXT
*conservative_raster
=
3549 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT
);
3551 if (!conservative_raster
)
3552 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
;
3553 return conservative_raster
->conservativeRasterizationMode
;
3557 radv_pipeline_generate_raster_state(struct radeon_cmdbuf
*ctx_cs
,
3558 struct radv_pipeline
*pipeline
,
3559 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3561 const VkPipelineRasterizationStateCreateInfo
*vkraster
= pCreateInfo
->pRasterizationState
;
3562 const VkConservativeRasterizationModeEXT mode
=
3563 radv_get_conservative_raster_mode(vkraster
);
3564 uint32_t pa_sc_conservative_rast
= S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3565 bool depth_clip_disable
= vkraster
->depthClampEnable
;
3567 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*depth_clip_state
=
3568 vk_find_struct_const(vkraster
->pNext
, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
3569 if (depth_clip_state
) {
3570 depth_clip_disable
= !depth_clip_state
->depthClipEnable
;
3573 radeon_set_context_reg(ctx_cs
, R_028810_PA_CL_CLIP_CNTL
,
3574 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3575 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable
? 1 : 0) |
3576 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable
? 1 : 0) |
3577 S_028810_DX_RASTERIZATION_KILL(vkraster
->rasterizerDiscardEnable
? 1 : 0) |
3578 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3580 radeon_set_context_reg(ctx_cs
, R_0286D4_SPI_INTERP_CONTROL_0
,
3581 S_0286D4_FLAT_SHADE_ENA(1) |
3582 S_0286D4_PNT_SPRITE_ENA(1) |
3583 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
3584 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
3585 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
3586 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
3587 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3589 radeon_set_context_reg(ctx_cs
, R_028BE4_PA_SU_VTX_CNTL
,
3590 S_028BE4_PIX_CENTER(1) | // TODO verify
3591 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN
) |
3592 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
3594 radeon_set_context_reg(ctx_cs
, R_028814_PA_SU_SC_MODE_CNTL
,
3595 S_028814_FACE(vkraster
->frontFace
) |
3596 S_028814_CULL_FRONT(!!(vkraster
->cullMode
& VK_CULL_MODE_FRONT_BIT
)) |
3597 S_028814_CULL_BACK(!!(vkraster
->cullMode
& VK_CULL_MODE_BACK_BIT
)) |
3598 S_028814_POLY_MODE(vkraster
->polygonMode
!= VK_POLYGON_MODE_FILL
) |
3599 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3600 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3601 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3602 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3603 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster
->depthBiasEnable
? 1 : 0));
3605 /* Conservative rasterization. */
3606 if (mode
!= VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
) {
3607 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3609 ms
->pa_sc_aa_config
|= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3610 ms
->db_eqaa
|= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3611 S_028804_OVERRASTERIZATION_AMOUNT(4);
3613 pa_sc_conservative_rast
= S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3614 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3615 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3617 if (mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT
) {
3618 pa_sc_conservative_rast
|=
3619 S_028C4C_OVER_RAST_ENABLE(1) |
3620 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3621 S_028C4C_UNDER_RAST_ENABLE(0) |
3622 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3623 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3625 assert(mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT
);
3626 pa_sc_conservative_rast
|=
3627 S_028C4C_OVER_RAST_ENABLE(0) |
3628 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3629 S_028C4C_UNDER_RAST_ENABLE(1) |
3630 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3631 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3635 radeon_set_context_reg(ctx_cs
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
3636 pa_sc_conservative_rast
);
3641 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf
*ctx_cs
,
3642 struct radv_pipeline
*pipeline
)
3644 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3646 radeon_set_context_reg_seq(ctx_cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
3647 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[0]);
3648 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[1]);
3650 radeon_set_context_reg(ctx_cs
, R_028804_DB_EQAA
, ms
->db_eqaa
);
3651 radeon_set_context_reg(ctx_cs
, R_028A48_PA_SC_MODE_CNTL_0
, ms
->pa_sc_mode_cntl_0
);
3652 radeon_set_context_reg(ctx_cs
, R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
3653 radeon_set_context_reg(ctx_cs
, R_028BDC_PA_SC_LINE_CNTL
, ms
->pa_sc_line_cntl
);
3655 /* The exclusion bits can be set to improve rasterization efficiency
3656 * if no sample lies on the pixel boundary (-8 sample offset). It's
3657 * currently always TRUE because the driver doesn't support 16 samples.
3659 bool exclusion
= pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
3660 radeon_set_context_reg(ctx_cs
, R_02882C_PA_SU_PRIM_FILTER_CNTL
,
3661 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) |
3662 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3666 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf
*ctx_cs
,
3667 struct radv_pipeline
*pipeline
)
3669 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3670 const struct radv_shader_variant
*vs
=
3671 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] ?
3672 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] :
3673 pipeline
->shaders
[MESA_SHADER_VERTEX
];
3674 unsigned vgt_primitiveid_en
= 0;
3675 uint32_t vgt_gs_mode
= 0;
3677 if (radv_pipeline_has_ngg(pipeline
))
3680 if (radv_pipeline_has_gs(pipeline
)) {
3681 const struct radv_shader_variant
*gs
=
3682 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3684 vgt_gs_mode
= ac_vgt_gs_mode(gs
->info
.gs
.vertices_out
,
3685 pipeline
->device
->physical_device
->rad_info
.chip_class
);
3686 } else if (outinfo
->export_prim_id
|| vs
->info
.uses_prim_id
) {
3687 vgt_gs_mode
= S_028A40_MODE(V_028A40_GS_SCENARIO_A
);
3688 vgt_primitiveid_en
|= S_028A84_PRIMITIVEID_EN(1);
3691 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
, vgt_primitiveid_en
);
3692 radeon_set_context_reg(ctx_cs
, R_028A40_VGT_GS_MODE
, vgt_gs_mode
);
3696 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf
*ctx_cs
,
3697 struct radeon_cmdbuf
*cs
,
3698 struct radv_pipeline
*pipeline
,
3699 struct radv_shader_variant
*shader
)
3701 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3703 radeon_set_sh_reg_seq(cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
3704 radeon_emit(cs
, va
>> 8);
3705 radeon_emit(cs
, S_00B124_MEM_BASE(va
>> 40));
3706 radeon_emit(cs
, shader
->config
.rsrc1
);
3707 radeon_emit(cs
, shader
->config
.rsrc2
);
3709 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3710 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3711 clip_dist_mask
= outinfo
->clip_dist_mask
;
3712 cull_dist_mask
= outinfo
->cull_dist_mask
;
3713 total_mask
= clip_dist_mask
| cull_dist_mask
;
3714 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3715 outinfo
->writes_layer
||
3716 outinfo
->writes_viewport_index
;
3717 unsigned spi_vs_out_config
, nparams
;
3719 /* VS is required to export at least one param. */
3720 nparams
= MAX2(outinfo
->param_exports
, 1);
3721 spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
3723 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3724 spi_vs_out_config
|= S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0);
3727 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
, spi_vs_out_config
);
3729 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3730 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3731 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3732 V_02870C_SPI_SHADER_4COMP
:
3733 V_02870C_SPI_SHADER_NONE
) |
3734 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3735 V_02870C_SPI_SHADER_4COMP
:
3736 V_02870C_SPI_SHADER_NONE
) |
3737 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3738 V_02870C_SPI_SHADER_4COMP
:
3739 V_02870C_SPI_SHADER_NONE
));
3741 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
3742 S_028818_VTX_W0_FMT(1) |
3743 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3744 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3745 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3747 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3748 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3749 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3750 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3751 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3752 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3753 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3754 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3755 cull_dist_mask
<< 8 |
3758 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
3759 radeon_set_context_reg(ctx_cs
, R_028AB4_VGT_REUSE_OFF
,
3760 outinfo
->writes_viewport_index
);
3764 radv_pipeline_generate_hw_es(struct radeon_cmdbuf
*cs
,
3765 struct radv_pipeline
*pipeline
,
3766 struct radv_shader_variant
*shader
)
3768 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3770 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
3771 radeon_emit(cs
, va
>> 8);
3772 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3773 radeon_emit(cs
, shader
->config
.rsrc1
);
3774 radeon_emit(cs
, shader
->config
.rsrc2
);
3778 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf
*cs
,
3779 struct radv_pipeline
*pipeline
,
3780 struct radv_shader_variant
*shader
,
3781 const struct radv_tessellation_state
*tess
)
3783 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3784 uint32_t rsrc2
= shader
->config
.rsrc2
;
3786 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
3787 radeon_emit(cs
, va
>> 8);
3788 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
3790 rsrc2
|= S_00B52C_LDS_SIZE(tess
->lds_size
);
3791 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX7
&&
3792 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
3793 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
3795 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
3796 radeon_emit(cs
, shader
->config
.rsrc1
);
3797 radeon_emit(cs
, rsrc2
);
3801 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf
*ctx_cs
,
3802 struct radeon_cmdbuf
*cs
,
3803 struct radv_pipeline
*pipeline
,
3804 struct radv_shader_variant
*shader
)
3806 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3807 gl_shader_stage es_type
=
3808 radv_pipeline_has_tess(pipeline
) ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
3809 struct radv_shader_variant
*es
=
3810 es_type
== MESA_SHADER_TESS_EVAL
? pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] : pipeline
->shaders
[MESA_SHADER_VERTEX
];
3811 const struct gfx10_ngg_info
*ngg_state
= &shader
->info
.ngg_info
;
3813 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
3814 radeon_emit(cs
, va
>> 8);
3815 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3816 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
3817 radeon_emit(cs
, shader
->config
.rsrc1
);
3818 radeon_emit(cs
, shader
->config
.rsrc2
);
3820 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3821 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3822 clip_dist_mask
= outinfo
->clip_dist_mask
;
3823 cull_dist_mask
= outinfo
->cull_dist_mask
;
3824 total_mask
= clip_dist_mask
| cull_dist_mask
;
3825 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3826 outinfo
->writes_layer
||
3827 outinfo
->writes_viewport_index
;
3828 bool es_enable_prim_id
= outinfo
->export_prim_id
||
3829 (es
&& es
->info
.uses_prim_id
);
3830 bool break_wave_at_eoi
= false;
3834 if (es_type
== MESA_SHADER_TESS_EVAL
) {
3835 struct radv_shader_variant
*gs
=
3836 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3838 if (es_enable_prim_id
|| (gs
&& gs
->info
.uses_prim_id
))
3839 break_wave_at_eoi
= true;
3842 nparams
= MAX2(outinfo
->param_exports
, 1);
3843 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
3844 S_0286C4_VS_EXPORT_COUNT(nparams
- 1) |
3845 S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0));
3847 radeon_set_context_reg(ctx_cs
, R_028708_SPI_SHADER_IDX_FORMAT
,
3848 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP
));
3849 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3850 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3851 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3852 V_02870C_SPI_SHADER_4COMP
:
3853 V_02870C_SPI_SHADER_NONE
) |
3854 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3855 V_02870C_SPI_SHADER_4COMP
:
3856 V_02870C_SPI_SHADER_NONE
) |
3857 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3858 V_02870C_SPI_SHADER_4COMP
:
3859 V_02870C_SPI_SHADER_NONE
));
3861 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
3862 S_028818_VTX_W0_FMT(1) |
3863 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3864 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3865 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3866 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3867 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3868 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3869 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3870 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3871 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3872 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3873 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3874 cull_dist_mask
<< 8 |
3877 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
,
3878 S_028A84_PRIMITIVEID_EN(es_enable_prim_id
) |
3879 S_028A84_NGG_DISABLE_PROVOK_REUSE(es_enable_prim_id
));
3881 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
3882 ngg_state
->vgt_esgs_ring_itemsize
);
3884 /* NGG specific registers. */
3885 struct radv_shader_variant
*gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3886 uint32_t gs_num_invocations
= gs
? gs
->info
.gs
.invocations
: 1;
3888 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
3889 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state
->hw_max_esverts
) |
3890 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state
->max_gsprims
) |
3891 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state
->max_gsprims
* gs_num_invocations
));
3892 radeon_set_context_reg(ctx_cs
, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP
,
3893 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state
->max_out_verts
));
3894 radeon_set_context_reg(ctx_cs
, R_028B4C_GE_NGG_SUBGRP_CNTL
,
3895 S_028B4C_PRIM_AMP_FACTOR(ngg_state
->prim_amp_factor
) |
3896 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
3897 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
3898 S_028B90_CNT(gs_num_invocations
) |
3899 S_028B90_ENABLE(gs_num_invocations
> 1) |
3900 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state
->max_vert_out_per_gs_instance
));
3902 /* User edge flags are set by the pos exports. If user edge flags are
3903 * not used, we must use hw-generated edge flags and pass them via
3904 * the prim export to prevent drawing lines on internal edges of
3905 * decomposed primitives (such as quads) with polygon mode = lines.
3907 * TODO: We should combine hw-generated edge flags with user edge
3908 * flags in the shader.
3910 radeon_set_context_reg(ctx_cs
, R_028838_PA_CL_NGG_CNTL
,
3911 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline
) &&
3912 !radv_pipeline_has_gs(pipeline
)));
3914 ge_cntl
= S_03096C_PRIM_GRP_SIZE(ngg_state
->max_gsprims
) |
3915 S_03096C_VERT_GRP_SIZE(ngg_state
->hw_max_esverts
) |
3916 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
);
3918 /* Bug workaround for a possible hang with non-tessellation cases.
3919 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
3921 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
3923 if ((pipeline
->device
->physical_device
->rad_info
.family
== CHIP_NAVI10
||
3924 pipeline
->device
->physical_device
->rad_info
.family
== CHIP_NAVI12
||
3925 pipeline
->device
->physical_device
->rad_info
.family
== CHIP_NAVI14
) &&
3926 !radv_pipeline_has_tess(pipeline
) &&
3927 ngg_state
->hw_max_esverts
!= 256) {
3928 ge_cntl
&= C_03096C_VERT_GRP_SIZE
;
3930 if (ngg_state
->hw_max_esverts
> 5) {
3931 ge_cntl
|= S_03096C_VERT_GRP_SIZE(ngg_state
->hw_max_esverts
- 5);
3935 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
, ge_cntl
);
3939 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf
*cs
,
3940 struct radv_pipeline
*pipeline
,
3941 struct radv_shader_variant
*shader
,
3942 const struct radv_tessellation_state
*tess
)
3944 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3946 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
3947 unsigned hs_rsrc2
= shader
->config
.rsrc2
;
3949 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3950 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX10(tess
->lds_size
);
3952 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX9(tess
->lds_size
);
3955 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3956 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
3957 radeon_emit(cs
, va
>> 8);
3958 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
3960 radeon_set_sh_reg_seq(cs
, R_00B410_SPI_SHADER_PGM_LO_LS
, 2);
3961 radeon_emit(cs
, va
>> 8);
3962 radeon_emit(cs
, S_00B414_MEM_BASE(va
>> 40));
3965 radeon_set_sh_reg_seq(cs
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
, 2);
3966 radeon_emit(cs
, shader
->config
.rsrc1
);
3967 radeon_emit(cs
, hs_rsrc2
);
3969 radeon_set_sh_reg_seq(cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
3970 radeon_emit(cs
, va
>> 8);
3971 radeon_emit(cs
, S_00B424_MEM_BASE(va
>> 40));
3972 radeon_emit(cs
, shader
->config
.rsrc1
);
3973 radeon_emit(cs
, shader
->config
.rsrc2
);
3978 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf
*ctx_cs
,
3979 struct radeon_cmdbuf
*cs
,
3980 struct radv_pipeline
*pipeline
,
3981 const struct radv_tessellation_state
*tess
)
3983 struct radv_shader_variant
*vs
;
3985 /* Skip shaders merged into HS/GS */
3986 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
3990 if (vs
->info
.vs
.as_ls
)
3991 radv_pipeline_generate_hw_ls(cs
, pipeline
, vs
, tess
);
3992 else if (vs
->info
.vs
.as_es
)
3993 radv_pipeline_generate_hw_es(cs
, pipeline
, vs
);
3994 else if (vs
->info
.is_ngg
)
3995 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, vs
);
3997 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, vs
);
4001 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf
*ctx_cs
,
4002 struct radeon_cmdbuf
*cs
,
4003 struct radv_pipeline
*pipeline
,
4004 const struct radv_tessellation_state
*tess
)
4006 if (!radv_pipeline_has_tess(pipeline
))
4009 struct radv_shader_variant
*tes
, *tcs
;
4011 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
4012 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
4015 if (tes
->info
.is_ngg
) {
4016 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, tes
);
4017 } else if (tes
->info
.tes
.as_es
)
4018 radv_pipeline_generate_hw_es(cs
, pipeline
, tes
);
4020 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, tes
);
4023 radv_pipeline_generate_hw_hs(cs
, pipeline
, tcs
, tess
);
4025 radeon_set_context_reg(ctx_cs
, R_028B6C_VGT_TF_PARAM
,
4028 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
)
4029 radeon_set_context_reg_idx(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
4030 tess
->ls_hs_config
);
4032 radeon_set_context_reg(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
,
4033 tess
->ls_hs_config
);
4035 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
4036 !radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
4037 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4038 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4039 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4040 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4045 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf
*ctx_cs
,
4046 struct radeon_cmdbuf
*cs
,
4047 struct radv_pipeline
*pipeline
,
4048 struct radv_shader_variant
*gs
)
4050 const struct gfx9_gs_info
*gs_state
= &gs
->info
.gs_ring_info
;
4051 unsigned gs_max_out_vertices
;
4052 uint8_t *num_components
;
4057 gs_max_out_vertices
= gs
->info
.gs
.vertices_out
;
4058 max_stream
= gs
->info
.gs
.max_stream
;
4059 num_components
= gs
->info
.gs
.num_stream_output_components
;
4061 offset
= num_components
[0] * gs_max_out_vertices
;
4063 radeon_set_context_reg_seq(ctx_cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
4064 radeon_emit(ctx_cs
, offset
);
4065 if (max_stream
>= 1)
4066 offset
+= num_components
[1] * gs_max_out_vertices
;
4067 radeon_emit(ctx_cs
, offset
);
4068 if (max_stream
>= 2)
4069 offset
+= num_components
[2] * gs_max_out_vertices
;
4070 radeon_emit(ctx_cs
, offset
);
4071 if (max_stream
>= 3)
4072 offset
+= num_components
[3] * gs_max_out_vertices
;
4073 radeon_set_context_reg(ctx_cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
4075 radeon_set_context_reg_seq(ctx_cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
4076 radeon_emit(ctx_cs
, num_components
[0]);
4077 radeon_emit(ctx_cs
, (max_stream
>= 1) ? num_components
[1] : 0);
4078 radeon_emit(ctx_cs
, (max_stream
>= 2) ? num_components
[2] : 0);
4079 radeon_emit(ctx_cs
, (max_stream
>= 3) ? num_components
[3] : 0);
4081 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
4082 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
4083 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
4084 S_028B90_ENABLE(gs_num_invocations
> 0));
4086 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
4087 gs_state
->vgt_esgs_ring_itemsize
);
4089 va
= radv_buffer_get_va(gs
->bo
) + gs
->bo_offset
;
4091 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4092 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4093 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
4094 radeon_emit(cs
, va
>> 8);
4095 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
4097 radeon_set_sh_reg_seq(cs
, R_00B210_SPI_SHADER_PGM_LO_ES
, 2);
4098 radeon_emit(cs
, va
>> 8);
4099 radeon_emit(cs
, S_00B214_MEM_BASE(va
>> 40));
4102 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
4103 radeon_emit(cs
, gs
->config
.rsrc1
);
4104 radeon_emit(cs
, gs
->config
.rsrc2
| S_00B22C_LDS_SIZE(gs_state
->lds_size
));
4106 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
, gs_state
->vgt_gs_onchip_cntl
);
4107 radeon_set_context_reg(ctx_cs
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
, gs_state
->vgt_gs_max_prims_per_subgroup
);
4109 radeon_set_sh_reg_seq(cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
4110 radeon_emit(cs
, va
>> 8);
4111 radeon_emit(cs
, S_00B224_MEM_BASE(va
>> 40));
4112 radeon_emit(cs
, gs
->config
.rsrc1
);
4113 radeon_emit(cs
, gs
->config
.rsrc2
);
4116 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, pipeline
->gs_copy_shader
);
4120 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf
*ctx_cs
,
4121 struct radeon_cmdbuf
*cs
,
4122 struct radv_pipeline
*pipeline
)
4124 struct radv_shader_variant
*gs
;
4126 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4130 if (gs
->info
.is_ngg
)
4131 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, gs
);
4133 radv_pipeline_generate_hw_gs(ctx_cs
, cs
, pipeline
, gs
);
4135 radeon_set_context_reg(ctx_cs
, R_028B38_VGT_GS_MAX_VERT_OUT
,
4136 gs
->info
.gs
.vertices_out
);
4139 static uint32_t offset_to_ps_input(uint32_t offset
, bool flat_shade
, bool float16
)
4141 uint32_t ps_input_cntl
;
4142 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
4143 ps_input_cntl
= S_028644_OFFSET(offset
);
4145 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
4147 ps_input_cntl
|= S_028644_FP16_INTERP_MODE(1) |
4148 S_028644_ATTR0_VALID(1);
4151 /* The input is a DEFAULT_VAL constant. */
4152 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
4153 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
4154 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
4155 ps_input_cntl
= S_028644_OFFSET(0x20) |
4156 S_028644_DEFAULT_VAL(offset
);
4158 return ps_input_cntl
;
4162 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf
*ctx_cs
,
4163 struct radv_pipeline
*pipeline
)
4165 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4166 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
4167 uint32_t ps_input_cntl
[32];
4169 unsigned ps_offset
= 0;
4171 if (ps
->info
.ps
.prim_id_input
) {
4172 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
];
4173 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4174 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false);
4179 if (ps
->info
.ps
.layer_input
||
4180 ps
->info
.needs_multiview_view_index
) {
4181 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
];
4182 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
4183 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false);
4185 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false);
4189 if (ps
->info
.ps
.has_pcoord
) {
4191 val
= S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4192 ps_input_cntl
[ps_offset
] = val
;
4196 if (ps
->info
.ps
.num_input_clips_culls
) {
4199 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST0
];
4200 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4201 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false);
4205 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST1
];
4206 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
&&
4207 ps
->info
.ps
.num_input_clips_culls
> 4) {
4208 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false);
4213 for (unsigned i
= 0; i
< 32 && (1u << i
) <= ps
->info
.ps
.input_mask
; ++i
) {
4217 if (!(ps
->info
.ps
.input_mask
& (1u << i
)))
4220 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VAR0
+ i
];
4221 if (vs_offset
== AC_EXP_PARAM_UNDEFINED
) {
4222 ps_input_cntl
[ps_offset
] = S_028644_OFFSET(0x20);
4227 flat_shade
= !!(ps
->info
.ps
.flat_shaded_mask
& (1u << ps_offset
));
4228 float16
= !!(ps
->info
.ps
.float16_shaded_mask
& (1u << ps_offset
));
4230 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, flat_shade
, float16
);
4235 radeon_set_context_reg_seq(ctx_cs
, R_028644_SPI_PS_INPUT_CNTL_0
, ps_offset
);
4236 for (unsigned i
= 0; i
< ps_offset
; i
++) {
4237 radeon_emit(ctx_cs
, ps_input_cntl
[i
]);
4243 radv_compute_db_shader_control(const struct radv_device
*device
,
4244 const struct radv_pipeline
*pipeline
,
4245 const struct radv_shader_variant
*ps
)
4248 if (ps
->info
.ps
.early_fragment_test
|| !ps
->info
.ps
.writes_memory
)
4249 z_order
= V_02880C_EARLY_Z_THEN_LATE_Z
;
4251 z_order
= V_02880C_LATE_Z
;
4253 bool disable_rbplus
= device
->physical_device
->rad_info
.has_rbplus
&&
4254 !device
->physical_device
->rad_info
.rbplus_allowed
;
4256 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4257 * but this appears to break Project Cars (DXVK). See
4258 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4260 bool mask_export_enable
= ps
->info
.ps
.writes_sample_mask
;
4262 return S_02880C_Z_EXPORT_ENABLE(ps
->info
.ps
.writes_z
) |
4263 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps
->info
.ps
.writes_stencil
) |
4264 S_02880C_KILL_ENABLE(!!ps
->info
.ps
.can_discard
) |
4265 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable
) |
4266 S_02880C_Z_ORDER(z_order
) |
4267 S_02880C_DEPTH_BEFORE_SHADER(ps
->info
.ps
.early_fragment_test
) |
4268 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps
->info
.ps
.post_depth_coverage
) |
4269 S_02880C_EXEC_ON_HIER_FAIL(ps
->info
.ps
.writes_memory
) |
4270 S_02880C_EXEC_ON_NOOP(ps
->info
.ps
.writes_memory
) |
4271 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus
);
4275 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf
*ctx_cs
,
4276 struct radeon_cmdbuf
*cs
,
4277 struct radv_pipeline
*pipeline
)
4279 struct radv_shader_variant
*ps
;
4281 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
4283 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4284 va
= radv_buffer_get_va(ps
->bo
) + ps
->bo_offset
;
4286 radeon_set_sh_reg_seq(cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
4287 radeon_emit(cs
, va
>> 8);
4288 radeon_emit(cs
, S_00B024_MEM_BASE(va
>> 40));
4289 radeon_emit(cs
, ps
->config
.rsrc1
);
4290 radeon_emit(cs
, ps
->config
.rsrc2
);
4292 radeon_set_context_reg(ctx_cs
, R_02880C_DB_SHADER_CONTROL
,
4293 radv_compute_db_shader_control(pipeline
->device
,
4296 radeon_set_context_reg(ctx_cs
, R_0286CC_SPI_PS_INPUT_ENA
,
4297 ps
->config
.spi_ps_input_ena
);
4299 radeon_set_context_reg(ctx_cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
4300 ps
->config
.spi_ps_input_addr
);
4302 radeon_set_context_reg(ctx_cs
, R_0286D8_SPI_PS_IN_CONTROL
,
4303 S_0286D8_NUM_INTERP(ps
->info
.ps
.num_interp
) |
4304 S_0286D8_PS_W32_EN(ps
->info
.wave_size
== 32));
4306 radeon_set_context_reg(ctx_cs
, R_0286E0_SPI_BARYC_CNTL
, pipeline
->graphics
.spi_baryc_cntl
);
4308 radeon_set_context_reg(ctx_cs
, R_028710_SPI_SHADER_Z_FORMAT
,
4309 ac_get_spi_shader_z_format(ps
->info
.ps
.writes_z
,
4310 ps
->info
.ps
.writes_stencil
,
4311 ps
->info
.ps
.writes_sample_mask
));
4313 if (pipeline
->device
->dfsm_allowed
) {
4314 /* optimise this? */
4315 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
4316 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
4321 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf
*ctx_cs
,
4322 struct radv_pipeline
*pipeline
)
4324 if (pipeline
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4325 pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
4328 unsigned vtx_reuse_depth
= 30;
4329 if (radv_pipeline_has_tess(pipeline
) &&
4330 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.tes
.spacing
== TESS_SPACING_FRACTIONAL_ODD
) {
4331 vtx_reuse_depth
= 14;
4333 radeon_set_context_reg(ctx_cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
4334 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth
));
4338 radv_compute_vgt_shader_stages_en(const struct radv_pipeline
*pipeline
)
4340 uint32_t stages
= 0;
4341 if (radv_pipeline_has_tess(pipeline
)) {
4342 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
4343 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4345 if (radv_pipeline_has_gs(pipeline
))
4346 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
4348 else if (radv_pipeline_has_ngg(pipeline
))
4349 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
4351 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
4352 } else if (radv_pipeline_has_gs(pipeline
)) {
4353 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
4355 } else if (radv_pipeline_has_ngg(pipeline
)) {
4356 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
4359 if (radv_pipeline_has_ngg(pipeline
)) {
4360 stages
|= S_028B54_PRIMGEN_EN(1);
4361 if (pipeline
->streamout_shader
)
4362 stages
|= S_028B54_NGG_WAVE_ID_EN(1);
4363 } else if (radv_pipeline_has_gs(pipeline
)) {
4364 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
4367 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
4368 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4370 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4371 uint8_t hs_size
= 64, gs_size
= 64, vs_size
= 64;
4373 if (radv_pipeline_has_tess(pipeline
))
4374 hs_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.wave_size
;
4376 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
4377 vs_size
= gs_size
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.wave_size
;
4378 if (pipeline
->gs_copy_shader
)
4379 vs_size
= pipeline
->gs_copy_shader
->info
.wave_size
;
4380 } else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
4381 vs_size
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.wave_size
;
4382 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
4383 vs_size
= pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.wave_size
;
4385 if (radv_pipeline_has_ngg(pipeline
))
4388 /* legacy GS only supports Wave64 */
4389 stages
|= S_028B54_HS_W32_EN(hs_size
== 32 ? 1 : 0) |
4390 S_028B54_GS_W32_EN(gs_size
== 32 ? 1 : 0) |
4391 S_028B54_VS_W32_EN(vs_size
== 32 ? 1 : 0);
4398 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4400 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
4401 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
4403 if (!discard_rectangle_info
)
4408 for (unsigned i
= 0; i
< (1u << MAX_DISCARD_RECTANGLES
); ++i
) {
4409 /* Interpret i as a bitmask, and then set the bit in the mask if
4410 * that combination of rectangles in which the pixel is contained
4411 * should pass the cliprect test. */
4412 unsigned relevant_subset
= i
& ((1u << discard_rectangle_info
->discardRectangleCount
) - 1);
4414 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT
&&
4418 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT
&&
4429 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf
*ctx_cs
,
4430 struct radv_pipeline
*pipeline
,
4431 const struct radv_tessellation_state
*tess
)
4433 bool break_wave_at_eoi
= false;
4434 unsigned primgroup_size
;
4435 unsigned vertgroup_size
;
4437 if (radv_pipeline_has_tess(pipeline
)) {
4438 primgroup_size
= tess
->num_patches
; /* must be a multiple of NUM_PATCHES */
4440 } else if (radv_pipeline_has_gs(pipeline
)) {
4441 const struct gfx9_gs_info
*gs_state
=
4442 &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs_ring_info
;
4443 unsigned vgt_gs_onchip_cntl
= gs_state
->vgt_gs_onchip_cntl
;
4444 primgroup_size
= G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl
);
4445 vertgroup_size
= G_028A44_ES_VERTS_PER_SUBGRP(vgt_gs_onchip_cntl
);
4447 primgroup_size
= 128; /* recommended without a GS and tess */
4451 if (radv_pipeline_has_tess(pipeline
)) {
4452 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4453 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4454 break_wave_at_eoi
= true;
4457 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
,
4458 S_03096C_PRIM_GRP_SIZE(primgroup_size
) |
4459 S_03096C_VERT_GRP_SIZE(vertgroup_size
) |
4460 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4461 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
));
4465 radv_pipeline_generate_pm4(struct radv_pipeline
*pipeline
,
4466 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4467 const struct radv_graphics_pipeline_create_info
*extra
,
4468 const struct radv_blend_state
*blend
,
4469 const struct radv_tessellation_state
*tess
,
4470 unsigned prim
, unsigned gs_out
)
4472 struct radeon_cmdbuf
*ctx_cs
= &pipeline
->ctx_cs
;
4473 struct radeon_cmdbuf
*cs
= &pipeline
->cs
;
4476 ctx_cs
->max_dw
= 256;
4477 cs
->buf
= malloc(4 * (cs
->max_dw
+ ctx_cs
->max_dw
));
4478 ctx_cs
->buf
= cs
->buf
+ cs
->max_dw
;
4480 radv_pipeline_generate_depth_stencil_state(ctx_cs
, pipeline
, pCreateInfo
, extra
);
4481 radv_pipeline_generate_blend_state(ctx_cs
, pipeline
, blend
);
4482 radv_pipeline_generate_raster_state(ctx_cs
, pipeline
, pCreateInfo
);
4483 radv_pipeline_generate_multisample_state(ctx_cs
, pipeline
);
4484 radv_pipeline_generate_vgt_gs_mode(ctx_cs
, pipeline
);
4485 radv_pipeline_generate_vertex_shader(ctx_cs
, cs
, pipeline
, tess
);
4486 radv_pipeline_generate_tess_shaders(ctx_cs
, cs
, pipeline
, tess
);
4487 radv_pipeline_generate_geometry_shader(ctx_cs
, cs
, pipeline
);
4488 radv_pipeline_generate_fragment_shader(ctx_cs
, cs
, pipeline
);
4489 radv_pipeline_generate_ps_inputs(ctx_cs
, pipeline
);
4490 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs
, pipeline
);
4491 radv_pipeline_generate_binning_state(ctx_cs
, pipeline
, pCreateInfo
, blend
);
4493 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&& !radv_pipeline_has_ngg(pipeline
))
4494 gfx10_pipeline_generate_ge_cntl(ctx_cs
, pipeline
, tess
);
4496 radeon_set_context_reg(ctx_cs
, R_028B54_VGT_SHADER_STAGES_EN
, radv_compute_vgt_shader_stages_en(pipeline
));
4498 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4499 radeon_set_uconfig_reg_idx(pipeline
->device
->physical_device
,
4500 cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, prim
);
4502 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
4504 radeon_set_context_reg(ctx_cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, gs_out
);
4506 radeon_set_context_reg(ctx_cs
, R_02820C_PA_SC_CLIPRECT_RULE
, radv_compute_cliprect_rule(pCreateInfo
));
4508 pipeline
->ctx_cs_hash
= _mesa_hash_data(ctx_cs
->buf
, ctx_cs
->cdw
* 4);
4510 assert(ctx_cs
->cdw
<= ctx_cs
->max_dw
);
4511 assert(cs
->cdw
<= cs
->max_dw
);
4514 static struct radv_ia_multi_vgt_param_helpers
4515 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline
*pipeline
,
4516 const struct radv_tessellation_state
*tess
,
4519 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
= {0};
4520 const struct radv_device
*device
= pipeline
->device
;
4522 if (radv_pipeline_has_tess(pipeline
))
4523 ia_multi_vgt_param
.primgroup_size
= tess
->num_patches
;
4524 else if (radv_pipeline_has_gs(pipeline
))
4525 ia_multi_vgt_param
.primgroup_size
= 64;
4527 ia_multi_vgt_param
.primgroup_size
= 128; /* recommended without a GS */
4529 /* GS requirement. */
4530 ia_multi_vgt_param
.partial_es_wave
= false;
4531 if (radv_pipeline_has_gs(pipeline
) && device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4532 if (SI_GS_PER_ES
/ ia_multi_vgt_param
.primgroup_size
>= pipeline
->device
->gs_table_depth
- 3)
4533 ia_multi_vgt_param
.partial_es_wave
= true;
4535 ia_multi_vgt_param
.wd_switch_on_eop
= false;
4536 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4537 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
4538 * 4 shader engines. Set 1 to pass the assertion below.
4539 * The other cases are hardware requirements. */
4540 if (device
->physical_device
->rad_info
.max_se
< 4 ||
4541 prim
== V_008958_DI_PT_POLYGON
||
4542 prim
== V_008958_DI_PT_LINELOOP
||
4543 prim
== V_008958_DI_PT_TRIFAN
||
4544 prim
== V_008958_DI_PT_TRISTRIP_ADJ
||
4545 (pipeline
->graphics
.prim_restart_enable
&&
4546 (device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4547 (prim
!= V_008958_DI_PT_POINTLIST
&&
4548 prim
!= V_008958_DI_PT_LINESTRIP
))))
4549 ia_multi_vgt_param
.wd_switch_on_eop
= true;
4552 ia_multi_vgt_param
.ia_switch_on_eoi
= false;
4553 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.prim_id_input
)
4554 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4555 if (radv_pipeline_has_gs(pipeline
) &&
4556 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.uses_prim_id
)
4557 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4558 if (radv_pipeline_has_tess(pipeline
)) {
4559 /* SWITCH_ON_EOI must be set if PrimID is used. */
4560 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4561 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4562 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4565 ia_multi_vgt_param
.partial_vs_wave
= false;
4566 if (radv_pipeline_has_tess(pipeline
)) {
4567 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4568 if ((device
->physical_device
->rad_info
.family
== CHIP_TAHITI
||
4569 device
->physical_device
->rad_info
.family
== CHIP_PITCAIRN
||
4570 device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
) &&
4571 radv_pipeline_has_gs(pipeline
))
4572 ia_multi_vgt_param
.partial_vs_wave
= true;
4573 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4574 if (device
->physical_device
->rad_info
.has_distributed_tess
) {
4575 if (radv_pipeline_has_gs(pipeline
)) {
4576 if (device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4577 ia_multi_vgt_param
.partial_es_wave
= true;
4579 ia_multi_vgt_param
.partial_vs_wave
= true;
4584 /* Workaround for a VGT hang when strip primitive types are used with
4585 * primitive restart.
4587 if (pipeline
->graphics
.prim_restart_enable
&&
4588 (prim
== V_008958_DI_PT_LINESTRIP
||
4589 prim
== V_008958_DI_PT_TRISTRIP
||
4590 prim
== V_008958_DI_PT_LINESTRIP_ADJ
||
4591 prim
== V_008958_DI_PT_TRISTRIP_ADJ
)) {
4592 ia_multi_vgt_param
.partial_vs_wave
= true;
4595 if (radv_pipeline_has_gs(pipeline
)) {
4596 /* On these chips there is the possibility of a hang if the
4597 * pipeline uses a GS and partial_vs_wave is not set.
4599 * This mostly does not hit 4-SE chips, as those typically set
4600 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4601 * with GS due to another workaround.
4603 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4605 if (device
->physical_device
->rad_info
.family
== CHIP_TONGA
||
4606 device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
4607 device
->physical_device
->rad_info
.family
== CHIP_POLARIS10
||
4608 device
->physical_device
->rad_info
.family
== CHIP_POLARIS11
||
4609 device
->physical_device
->rad_info
.family
== CHIP_POLARIS12
||
4610 device
->physical_device
->rad_info
.family
== CHIP_VEGAM
) {
4611 ia_multi_vgt_param
.partial_vs_wave
= true;
4615 ia_multi_vgt_param
.base
=
4616 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param
.primgroup_size
- 1) |
4617 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4618 S_028AA8_MAX_PRIMGRP_IN_WAVE(device
->physical_device
->rad_info
.chip_class
== GFX8
? 2 : 0) |
4619 S_030960_EN_INST_OPT_BASIC(device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
4620 S_030960_EN_INST_OPT_ADV(device
->physical_device
->rad_info
.chip_class
>= GFX9
);
4622 return ia_multi_vgt_param
;
4627 radv_compute_vertex_input_state(struct radv_pipeline
*pipeline
,
4628 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4630 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
4631 pCreateInfo
->pVertexInputState
;
4632 struct radv_vertex_elements_info
*velems
= &pipeline
->vertex_elements
;
4634 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
4635 const VkVertexInputAttributeDescription
*desc
=
4636 &vi_info
->pVertexAttributeDescriptions
[i
];
4637 unsigned loc
= desc
->location
;
4638 const struct vk_format_description
*format_desc
;
4640 format_desc
= vk_format_description(desc
->format
);
4642 velems
->format_size
[loc
] = format_desc
->block
.bits
/ 8;
4645 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
4646 const VkVertexInputBindingDescription
*desc
=
4647 &vi_info
->pVertexBindingDescriptions
[i
];
4649 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
4650 pipeline
->num_vertex_bindings
=
4651 MAX2(pipeline
->num_vertex_bindings
, desc
->binding
+ 1);
4655 static struct radv_shader_variant
*
4656 radv_pipeline_get_streamout_shader(struct radv_pipeline
*pipeline
)
4660 for (i
= MESA_SHADER_GEOMETRY
; i
>= MESA_SHADER_VERTEX
; i
--) {
4661 struct radv_shader_variant
*shader
=
4662 radv_get_shader(pipeline
, i
);
4664 if (shader
&& shader
->info
.so
.num_outputs
> 0)
4672 radv_secure_compile(struct radv_pipeline
*pipeline
,
4673 struct radv_device
*device
,
4674 const struct radv_pipeline_key
*key
,
4675 const VkPipelineShaderStageCreateInfo
**pStages
,
4676 const VkPipelineCreateFlags flags
,
4677 unsigned num_stages
)
4679 uint8_t allowed_pipeline_hashes
[2][20];
4680 radv_hash_shaders(allowed_pipeline_hashes
[0], pStages
,
4681 pipeline
->layout
, key
, get_hash_flags(device
));
4683 /* Generate the GC copy hash */
4684 memcpy(allowed_pipeline_hashes
[1], allowed_pipeline_hashes
[0], 20);
4685 allowed_pipeline_hashes
[1][0] ^= 1;
4687 uint8_t allowed_hashes
[2][20];
4688 for (unsigned i
= 0; i
< 2; ++i
) {
4689 disk_cache_compute_key(device
->physical_device
->disk_cache
,
4690 allowed_pipeline_hashes
[i
], 20,
4694 /* Do an early exit if all cache entries are already there. */
4695 bool may_need_copy_shader
= pStages
[MESA_SHADER_GEOMETRY
];
4696 void *main_entry
= disk_cache_get(device
->physical_device
->disk_cache
, allowed_hashes
[0], NULL
);
4697 void *copy_entry
= NULL
;
4698 if (may_need_copy_shader
)
4699 copy_entry
= disk_cache_get(device
->physical_device
->disk_cache
, allowed_hashes
[1], NULL
);
4701 bool has_all_cache_entries
= main_entry
&& (!may_need_copy_shader
|| copy_entry
);
4705 if(has_all_cache_entries
)
4708 unsigned process
= 0;
4709 uint8_t sc_threads
= device
->instance
->num_sc_threads
;
4711 mtx_lock(&device
->sc_state
->secure_compile_mutex
);
4712 if (device
->sc_state
->secure_compile_thread_counter
< sc_threads
) {
4713 device
->sc_state
->secure_compile_thread_counter
++;
4714 for (unsigned i
= 0; i
< sc_threads
; i
++) {
4715 if (!device
->sc_state
->secure_compile_processes
[i
].in_use
) {
4716 device
->sc_state
->secure_compile_processes
[i
].in_use
= true;
4721 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
4724 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
4727 int fd_secure_input
= device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
;
4728 int fd_secure_output
= device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
;
4730 /* Fork a copy of the slim untainted secure compile process */
4731 enum radv_secure_compile_type sc_type
= RADV_SC_TYPE_FORK_DEVICE
;
4732 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
4734 if (!radv_sc_read(fd_secure_output
, &sc_type
, sizeof(sc_type
), true) ||
4735 sc_type
!= RADV_SC_TYPE_INIT_SUCCESS
)
4736 return VK_ERROR_DEVICE_LOST
;
4738 fd_secure_input
= device
->sc_state
->secure_compile_processes
[process
].fd_server
;
4739 fd_secure_output
= device
->sc_state
->secure_compile_processes
[process
].fd_client
;
4741 /* Write pipeline / shader module out to secure process via pipe */
4742 sc_type
= RADV_SC_TYPE_COMPILE_PIPELINE
;
4743 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
4745 /* Write pipeline layout out to secure process */
4746 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
4747 write(fd_secure_input
, layout
, sizeof(struct radv_pipeline_layout
));
4748 write(fd_secure_input
, &layout
->num_sets
, sizeof(uint32_t));
4749 for (uint32_t set
= 0; set
< layout
->num_sets
; set
++) {
4750 write(fd_secure_input
, &layout
->set
[set
].layout
->layout_size
, sizeof(uint32_t));
4751 write(fd_secure_input
, layout
->set
[set
].layout
, layout
->set
[set
].layout
->layout_size
);
4754 /* Write pipeline key out to secure process */
4755 write(fd_secure_input
, key
, sizeof(struct radv_pipeline_key
));
4757 /* Write pipeline create flags out to secure process */
4758 write(fd_secure_input
, &flags
, sizeof(VkPipelineCreateFlags
));
4760 /* Write stage and shader information out to secure process */
4761 write(fd_secure_input
, &num_stages
, sizeof(uint32_t));
4762 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
4766 /* Write stage out to secure process */
4767 gl_shader_stage stage
= ffs(pStages
[i
]->stage
) - 1;
4768 write(fd_secure_input
, &stage
, sizeof(gl_shader_stage
));
4770 /* Write entry point name out to secure process */
4771 size_t name_size
= strlen(pStages
[i
]->pName
) + 1;
4772 write(fd_secure_input
, &name_size
, sizeof(size_t));
4773 write(fd_secure_input
, pStages
[i
]->pName
, name_size
);
4775 /* Write shader module out to secure process */
4776 struct radv_shader_module
*module
= radv_shader_module_from_handle(pStages
[i
]->module
);
4777 assert(!module
->nir
);
4778 size_t module_size
= sizeof(struct radv_shader_module
) + module
->size
;
4779 write(fd_secure_input
, &module_size
, sizeof(size_t));
4780 write(fd_secure_input
, module
, module_size
);
4782 /* Write specialization info out to secure process */
4783 const VkSpecializationInfo
*specInfo
= pStages
[i
]->pSpecializationInfo
;
4784 bool has_spec_info
= specInfo
? true : false;
4785 write(fd_secure_input
, &has_spec_info
, sizeof(bool));
4787 write(fd_secure_input
, &specInfo
->dataSize
, sizeof(size_t));
4788 write(fd_secure_input
, specInfo
->pData
, specInfo
->dataSize
);
4790 write(fd_secure_input
, &specInfo
->mapEntryCount
, sizeof(uint32_t));
4791 for (uint32_t j
= 0; j
< specInfo
->mapEntryCount
; j
++)
4792 write(fd_secure_input
, &specInfo
->pMapEntries
[j
], sizeof(VkSpecializationMapEntry
));
4796 /* Read the data returned from the secure process */
4797 while (sc_type
!= RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED
) {
4798 if (!radv_sc_read(fd_secure_output
, &sc_type
, sizeof(sc_type
), true))
4799 return VK_ERROR_DEVICE_LOST
;
4801 if (sc_type
== RADV_SC_TYPE_WRITE_DISK_CACHE
) {
4802 assert(device
->physical_device
->disk_cache
);
4804 uint8_t disk_sha1
[20];
4805 if (!radv_sc_read(fd_secure_output
, disk_sha1
, sizeof(uint8_t) * 20, true))
4806 return VK_ERROR_DEVICE_LOST
;
4808 if (memcmp(disk_sha1
, allowed_hashes
[0], 20) &&
4809 memcmp(disk_sha1
, allowed_hashes
[1], 20))
4810 return VK_ERROR_DEVICE_LOST
;
4812 uint32_t entry_size
;
4813 if (!radv_sc_read(fd_secure_output
, &entry_size
, sizeof(uint32_t), true))
4814 return VK_ERROR_DEVICE_LOST
;
4816 struct cache_entry
*entry
= malloc(entry_size
);
4817 if (!radv_sc_read(fd_secure_output
, entry
, entry_size
, true))
4818 return VK_ERROR_DEVICE_LOST
;
4820 disk_cache_put(device
->physical_device
->disk_cache
,
4821 disk_sha1
, entry
, entry_size
,
4825 } else if (sc_type
== RADV_SC_TYPE_READ_DISK_CACHE
) {
4826 uint8_t disk_sha1
[20];
4827 if (!radv_sc_read(fd_secure_output
, disk_sha1
, sizeof(uint8_t) * 20, true))
4828 return VK_ERROR_DEVICE_LOST
;
4830 if (memcmp(disk_sha1
, allowed_hashes
[0], 20) &&
4831 memcmp(disk_sha1
, allowed_hashes
[1], 20))
4832 return VK_ERROR_DEVICE_LOST
;
4835 struct cache_entry
*entry
= (struct cache_entry
*)
4836 disk_cache_get(device
->physical_device
->disk_cache
,
4839 uint8_t found
= entry
? 1 : 0;
4840 write(fd_secure_input
, &found
, sizeof(uint8_t));
4843 write(fd_secure_input
, &size
, sizeof(size_t));
4844 write(fd_secure_input
, entry
, size
);
4851 sc_type
= RADV_SC_TYPE_DESTROY_DEVICE
;
4852 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
4854 mtx_lock(&device
->sc_state
->secure_compile_mutex
);
4855 device
->sc_state
->secure_compile_thread_counter
--;
4856 device
->sc_state
->secure_compile_processes
[process
].in_use
= false;
4857 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
4863 radv_pipeline_init(struct radv_pipeline
*pipeline
,
4864 struct radv_device
*device
,
4865 struct radv_pipeline_cache
*cache
,
4866 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4867 const struct radv_graphics_pipeline_create_info
*extra
)
4870 bool has_view_index
= false;
4872 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
4873 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
4874 if (subpass
->view_mask
)
4875 has_view_index
= true;
4877 pipeline
->device
= device
;
4878 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
4879 assert(pipeline
->layout
);
4881 struct radv_blend_state blend
= radv_pipeline_init_blend_state(pipeline
, pCreateInfo
, extra
);
4883 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
4884 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
4885 radv_init_feedback(creation_feedback
);
4887 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
4889 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
4890 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
4891 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
4892 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
4893 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
4894 if(creation_feedback
)
4895 stage_feedbacks
[stage
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[i
];
4898 struct radv_pipeline_key key
= radv_generate_graphics_pipeline_key(pipeline
, pCreateInfo
, &blend
, has_view_index
);
4899 if (radv_device_use_secure_compile(device
->instance
)) {
4900 return radv_secure_compile(pipeline
, device
, &key
, pStages
, pCreateInfo
->flags
, pCreateInfo
->stageCount
);
4902 radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
, pCreateInfo
->flags
, pipeline_feedback
, stage_feedbacks
);
4905 pipeline
->graphics
.spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
4906 radv_pipeline_init_multisample_state(pipeline
, &blend
, pCreateInfo
);
4908 uint32_t prim
= si_translate_prim(pCreateInfo
->pInputAssemblyState
->topology
);
4910 pipeline
->graphics
.can_use_guardband
= radv_prim_can_use_guardband(pCreateInfo
->pInputAssemblyState
->topology
);
4912 if (radv_pipeline_has_gs(pipeline
)) {
4913 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs
.output_prim
);
4914 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4915 } else if (radv_pipeline_has_tess(pipeline
)) {
4916 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.point_mode
)
4917 gs_out
= V_028A6C_OUTPRIM_TYPE_POINTLIST
;
4919 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.primitive_mode
);
4920 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4922 gs_out
= si_conv_prim_to_gs_out(pCreateInfo
->pInputAssemblyState
->topology
);
4924 if (extra
&& extra
->use_rectlist
) {
4925 prim
= V_008958_DI_PT_RECTLIST
;
4926 gs_out
= V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4927 pipeline
->graphics
.can_use_guardband
= true;
4928 if (radv_pipeline_has_ngg(pipeline
))
4929 gs_out
= V_028A6C_VGT_OUT_RECT_V0
;
4931 pipeline
->graphics
.prim_restart_enable
= !!pCreateInfo
->pInputAssemblyState
->primitiveRestartEnable
;
4932 /* prim vertex count will need TESS changes */
4933 pipeline
->graphics
.prim_vertex_count
= prim_size_table
[prim
];
4935 radv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
);
4937 /* Ensure that some export memory is always allocated, for two reasons:
4939 * 1) Correctness: The hardware ignores the EXEC mask if no export
4940 * memory is allocated, so KILL and alpha test do not work correctly
4942 * 2) Performance: Every shader needs at least a NULL export, even when
4943 * it writes no color/depth output. The NULL export instruction
4944 * stalls without this setting.
4946 * Don't add this to CB_SHADER_MASK.
4948 * GFX10 supports pixel shaders without exports by setting both the
4949 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
4950 * instructions if any are present.
4952 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4953 if ((pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX9
||
4954 ps
->info
.ps
.can_discard
) &&
4955 !blend
.spi_shader_col_format
) {
4956 if (!ps
->info
.ps
.writes_z
&&
4957 !ps
->info
.ps
.writes_stencil
&&
4958 !ps
->info
.ps
.writes_sample_mask
)
4959 blend
.spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
4962 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
4963 if (pipeline
->shaders
[i
]) {
4964 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[i
]->info
.need_indirect_descriptor_sets
;
4968 if (radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
4969 struct radv_shader_variant
*gs
=
4970 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4972 calculate_gs_ring_sizes(pipeline
, &gs
->info
.gs_ring_info
);
4975 struct radv_tessellation_state tess
= {0};
4976 if (radv_pipeline_has_tess(pipeline
)) {
4977 if (prim
== V_008958_DI_PT_PATCH
) {
4978 pipeline
->graphics
.prim_vertex_count
.min
= pCreateInfo
->pTessellationState
->patchControlPoints
;
4979 pipeline
->graphics
.prim_vertex_count
.incr
= 1;
4981 tess
= calculate_tess_state(pipeline
, pCreateInfo
);
4984 pipeline
->graphics
.ia_multi_vgt_param
= radv_compute_ia_multi_vgt_param_helpers(pipeline
, &tess
, prim
);
4986 radv_compute_vertex_input_state(pipeline
, pCreateInfo
);
4988 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++)
4989 pipeline
->user_data_0
[i
] = radv_pipeline_stage_to_user_data_0(pipeline
, i
, device
->physical_device
->rad_info
.chip_class
);
4991 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
,
4992 AC_UD_VS_BASE_VERTEX_START_INSTANCE
);
4993 if (loc
->sgpr_idx
!= -1) {
4994 pipeline
->graphics
.vtx_base_sgpr
= pipeline
->user_data_0
[MESA_SHADER_VERTEX
];
4995 pipeline
->graphics
.vtx_base_sgpr
+= loc
->sgpr_idx
* 4;
4996 if (radv_get_shader(pipeline
, MESA_SHADER_VERTEX
)->info
.vs
.needs_draw_id
)
4997 pipeline
->graphics
.vtx_emit_num
= 3;
4999 pipeline
->graphics
.vtx_emit_num
= 2;
5002 /* Find the last vertex shader stage that eventually uses streamout. */
5003 pipeline
->streamout_shader
= radv_pipeline_get_streamout_shader(pipeline
);
5005 result
= radv_pipeline_scratch_init(device
, pipeline
);
5006 radv_pipeline_generate_pm4(pipeline
, pCreateInfo
, extra
, &blend
, &tess
, prim
, gs_out
);
5012 radv_graphics_pipeline_create(
5014 VkPipelineCache _cache
,
5015 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
5016 const struct radv_graphics_pipeline_create_info
*extra
,
5017 const VkAllocationCallbacks
*pAllocator
,
5018 VkPipeline
*pPipeline
)
5020 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5021 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
5022 struct radv_pipeline
*pipeline
;
5025 pipeline
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
5026 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5027 if (pipeline
== NULL
)
5028 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5030 result
= radv_pipeline_init(pipeline
, device
, cache
,
5031 pCreateInfo
, extra
);
5032 if (result
!= VK_SUCCESS
) {
5033 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5037 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5042 VkResult
radv_CreateGraphicsPipelines(
5044 VkPipelineCache pipelineCache
,
5046 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
5047 const VkAllocationCallbacks
* pAllocator
,
5048 VkPipeline
* pPipelines
)
5050 VkResult result
= VK_SUCCESS
;
5053 for (; i
< count
; i
++) {
5055 r
= radv_graphics_pipeline_create(_device
,
5058 NULL
, pAllocator
, &pPipelines
[i
]);
5059 if (r
!= VK_SUCCESS
) {
5061 pPipelines
[i
] = VK_NULL_HANDLE
;
5070 radv_compute_generate_pm4(struct radv_pipeline
*pipeline
)
5072 struct radv_shader_variant
*compute_shader
;
5073 struct radv_device
*device
= pipeline
->device
;
5074 unsigned threads_per_threadgroup
;
5075 unsigned threadgroups_per_cu
= 1;
5076 unsigned waves_per_threadgroup
;
5077 unsigned max_waves_per_sh
= 0;
5080 pipeline
->cs
.max_dw
= device
->physical_device
->rad_info
.chip_class
>= GFX10
? 22 : 20;
5081 pipeline
->cs
.buf
= malloc(pipeline
->cs
.max_dw
* 4);
5083 compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
5084 va
= radv_buffer_get_va(compute_shader
->bo
) + compute_shader
->bo_offset
;
5086 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B830_COMPUTE_PGM_LO
, 2);
5087 radeon_emit(&pipeline
->cs
, va
>> 8);
5088 radeon_emit(&pipeline
->cs
, S_00B834_DATA(va
>> 40));
5090 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
5091 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc1
);
5092 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc2
);
5093 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
5094 radeon_set_sh_reg(&pipeline
->cs
, R_00B8A0_COMPUTE_PGM_RSRC3
, compute_shader
->config
.rsrc3
);
5097 /* Calculate best compute resource limits. */
5098 threads_per_threadgroup
= compute_shader
->info
.cs
.block_size
[0] *
5099 compute_shader
->info
.cs
.block_size
[1] *
5100 compute_shader
->info
.cs
.block_size
[2];
5101 waves_per_threadgroup
= DIV_ROUND_UP(threads_per_threadgroup
,
5102 compute_shader
->info
.wave_size
);
5104 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
5105 waves_per_threadgroup
== 1)
5106 threadgroups_per_cu
= 2;
5108 radeon_set_sh_reg(&pipeline
->cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
5109 ac_get_compute_resource_limits(&device
->physical_device
->rad_info
,
5110 waves_per_threadgroup
,
5112 threadgroups_per_cu
));
5114 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
5115 radeon_emit(&pipeline
->cs
,
5116 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]));
5117 radeon_emit(&pipeline
->cs
,
5118 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]));
5119 radeon_emit(&pipeline
->cs
,
5120 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]));
5122 assert(pipeline
->cs
.cdw
<= pipeline
->cs
.max_dw
);
5125 static struct radv_pipeline_key
5126 radv_generate_compute_pipeline_key(struct radv_pipeline
*pipeline
,
5127 const VkComputePipelineCreateInfo
*pCreateInfo
)
5129 const VkPipelineShaderStageCreateInfo
*stage
= &pCreateInfo
->stage
;
5130 struct radv_pipeline_key key
;
5131 memset(&key
, 0, sizeof(key
));
5133 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
5134 key
.optimisations_disabled
= 1;
5136 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*subgroup_size
=
5137 vk_find_struct_const(stage
->pNext
,
5138 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT
);
5140 if (subgroup_size
) {
5141 assert(subgroup_size
->requiredSubgroupSize
== 32 ||
5142 subgroup_size
->requiredSubgroupSize
== 64);
5143 key
.compute_subgroup_size
= subgroup_size
->requiredSubgroupSize
;
5149 static VkResult
radv_compute_pipeline_create(
5151 VkPipelineCache _cache
,
5152 const VkComputePipelineCreateInfo
* pCreateInfo
,
5153 const VkAllocationCallbacks
* pAllocator
,
5154 VkPipeline
* pPipeline
)
5156 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5157 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
5158 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
5159 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
5160 struct radv_pipeline
*pipeline
;
5163 pipeline
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
5164 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5165 if (pipeline
== NULL
)
5166 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5168 pipeline
->device
= device
;
5169 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
5170 assert(pipeline
->layout
);
5172 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
5173 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
5174 radv_init_feedback(creation_feedback
);
5176 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
5177 if (creation_feedback
)
5178 stage_feedbacks
[MESA_SHADER_COMPUTE
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[0];
5180 pStages
[MESA_SHADER_COMPUTE
] = &pCreateInfo
->stage
;
5182 struct radv_pipeline_key key
=
5183 radv_generate_compute_pipeline_key(pipeline
, pCreateInfo
);
5185 if (radv_device_use_secure_compile(device
->instance
)) {
5186 result
= radv_secure_compile(pipeline
, device
, &key
, pStages
, pCreateInfo
->flags
, 1);
5187 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5191 radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
, pCreateInfo
->flags
, pipeline_feedback
, stage_feedbacks
);
5194 pipeline
->user_data_0
[MESA_SHADER_COMPUTE
] = radv_pipeline_stage_to_user_data_0(pipeline
, MESA_SHADER_COMPUTE
, device
->physical_device
->rad_info
.chip_class
);
5195 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.need_indirect_descriptor_sets
;
5196 result
= radv_pipeline_scratch_init(device
, pipeline
);
5197 if (result
!= VK_SUCCESS
) {
5198 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5202 radv_compute_generate_pm4(pipeline
);
5204 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5209 VkResult
radv_CreateComputePipelines(
5211 VkPipelineCache pipelineCache
,
5213 const VkComputePipelineCreateInfo
* pCreateInfos
,
5214 const VkAllocationCallbacks
* pAllocator
,
5215 VkPipeline
* pPipelines
)
5217 VkResult result
= VK_SUCCESS
;
5220 for (; i
< count
; i
++) {
5222 r
= radv_compute_pipeline_create(_device
, pipelineCache
,
5224 pAllocator
, &pPipelines
[i
]);
5225 if (r
!= VK_SUCCESS
) {
5227 pPipelines
[i
] = VK_NULL_HANDLE
;
5235 static uint32_t radv_get_executable_count(const struct radv_pipeline
*pipeline
)
5238 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5239 if (!pipeline
->shaders
[i
])
5242 if (i
== MESA_SHADER_GEOMETRY
&&
5243 !radv_pipeline_has_ngg(pipeline
)) {
5253 static struct radv_shader_variant
*
5254 radv_get_shader_from_executable_index(const struct radv_pipeline
*pipeline
, int index
, gl_shader_stage
*stage
)
5256 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5257 if (!pipeline
->shaders
[i
])
5261 return pipeline
->shaders
[i
];
5266 if (i
== MESA_SHADER_GEOMETRY
&&
5267 !radv_pipeline_has_ngg(pipeline
)) {
5270 return pipeline
->gs_copy_shader
;
5280 /* Basically strlcpy (which does not exist on linux) specialized for
5282 static void desc_copy(char *desc
, const char *src
) {
5283 int len
= strlen(src
);
5284 assert(len
< VK_MAX_DESCRIPTION_SIZE
);
5285 memcpy(desc
, src
, len
);
5286 memset(desc
+ len
, 0, VK_MAX_DESCRIPTION_SIZE
- len
);
5289 VkResult
radv_GetPipelineExecutablePropertiesKHR(
5291 const VkPipelineInfoKHR
* pPipelineInfo
,
5292 uint32_t* pExecutableCount
,
5293 VkPipelineExecutablePropertiesKHR
* pProperties
)
5295 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pPipelineInfo
->pipeline
);
5296 const uint32_t total_count
= radv_get_executable_count(pipeline
);
5299 *pExecutableCount
= total_count
;
5303 const uint32_t count
= MIN2(total_count
, *pExecutableCount
);
5304 for (unsigned i
= 0, executable_idx
= 0;
5305 i
< MESA_SHADER_STAGES
&& executable_idx
< count
; ++i
) {
5306 if (!pipeline
->shaders
[i
])
5308 pProperties
[executable_idx
].stages
= mesa_to_vk_shader_stage(i
);
5309 const char *name
= NULL
;
5310 const char *description
= NULL
;
5312 case MESA_SHADER_VERTEX
:
5313 name
= "Vertex Shader";
5314 description
= "Vulkan Vertex Shader";
5316 case MESA_SHADER_TESS_CTRL
:
5317 if (!pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5318 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5319 name
= "Vertex + Tessellation Control Shaders";
5320 description
= "Combined Vulkan Vertex and Tessellation Control Shaders";
5322 name
= "Tessellation Control Shader";
5323 description
= "Vulkan Tessellation Control Shader";
5326 case MESA_SHADER_TESS_EVAL
:
5327 name
= "Tessellation Evaluation Shader";
5328 description
= "Vulkan Tessellation Evaluation Shader";
5330 case MESA_SHADER_GEOMETRY
:
5331 if (radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]) {
5332 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
;
5333 name
= "Tessellation Evaluation + Geometry Shaders";
5334 description
= "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5335 } else if (!radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5336 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5337 name
= "Vertex + Geometry Shader";
5338 description
= "Combined Vulkan Vertex and Geometry Shaders";
5340 name
= "Geometry Shader";
5341 description
= "Vulkan Geometry Shader";
5344 case MESA_SHADER_FRAGMENT
:
5345 name
= "Fragment Shader";
5346 description
= "Vulkan Fragment Shader";
5348 case MESA_SHADER_COMPUTE
:
5349 name
= "Compute Shader";
5350 description
= "Vulkan Compute Shader";
5354 pProperties
[executable_idx
].subgroupSize
= pipeline
->shaders
[i
]->info
.wave_size
;
5355 desc_copy(pProperties
[executable_idx
].name
, name
);
5356 desc_copy(pProperties
[executable_idx
].description
, description
);
5359 if (i
== MESA_SHADER_GEOMETRY
&&
5360 !radv_pipeline_has_ngg(pipeline
)) {
5361 assert(pipeline
->gs_copy_shader
);
5362 if (executable_idx
>= count
)
5365 pProperties
[executable_idx
].stages
= VK_SHADER_STAGE_GEOMETRY_BIT
;
5366 pProperties
[executable_idx
].subgroupSize
= 64;
5367 desc_copy(pProperties
[executable_idx
].name
, "GS Copy Shader");
5368 desc_copy(pProperties
[executable_idx
].description
,
5369 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5375 VkResult result
= *pExecutableCount
< total_count
? VK_INCOMPLETE
: VK_SUCCESS
;
5376 *pExecutableCount
= count
;
5380 VkResult
radv_GetPipelineExecutableStatisticsKHR(
5382 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5383 uint32_t* pStatisticCount
,
5384 VkPipelineExecutableStatisticKHR
* pStatistics
)
5386 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5387 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5388 gl_shader_stage stage
;
5389 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5391 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
5392 unsigned lds_increment
= chip_class
>= GFX7
? 512 : 256;
5393 unsigned max_waves
= radv_get_max_waves(device
, shader
, stage
);
5395 VkPipelineExecutableStatisticKHR
*s
= pStatistics
;
5396 VkPipelineExecutableStatisticKHR
*end
= s
+ (pStatistics
? *pStatisticCount
: 0);
5397 VkResult result
= VK_SUCCESS
;
5400 desc_copy(s
->name
, "SGPRs");
5401 desc_copy(s
->description
, "Number of SGPR registers allocated per subgroup");
5402 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5403 s
->value
.u64
= shader
->config
.num_sgprs
;
5408 desc_copy(s
->name
, "VGPRs");
5409 desc_copy(s
->description
, "Number of VGPR registers allocated per subgroup");
5410 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5411 s
->value
.u64
= shader
->config
.num_vgprs
;
5416 desc_copy(s
->name
, "Spilled SGPRs");
5417 desc_copy(s
->description
, "Number of SGPR registers spilled per subgroup");
5418 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5419 s
->value
.u64
= shader
->config
.spilled_sgprs
;
5424 desc_copy(s
->name
, "Spilled VGPRs");
5425 desc_copy(s
->description
, "Number of VGPR registers spilled per subgroup");
5426 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5427 s
->value
.u64
= shader
->config
.spilled_vgprs
;
5432 desc_copy(s
->name
, "PrivMem VGPRs");
5433 desc_copy(s
->description
, "Number of VGPRs stored in private memory per subgroup");
5434 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5435 s
->value
.u64
= shader
->info
.private_mem_vgprs
;
5440 desc_copy(s
->name
, "Code size");
5441 desc_copy(s
->description
, "Code size in bytes");
5442 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5443 s
->value
.u64
= shader
->exec_size
;
5448 desc_copy(s
->name
, "LDS size");
5449 desc_copy(s
->description
, "LDS size in bytes per workgroup");
5450 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5451 s
->value
.u64
= shader
->config
.lds_size
* lds_increment
;
5456 desc_copy(s
->name
, "Scratch size");
5457 desc_copy(s
->description
, "Private memory in bytes per subgroup");
5458 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5459 s
->value
.u64
= shader
->config
.scratch_bytes_per_wave
;
5464 desc_copy(s
->name
, "Subgroups per SIMD");
5465 desc_copy(s
->description
, "The maximum number of subgroups in flight on a SIMD unit");
5466 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5467 s
->value
.u64
= max_waves
;
5472 *pStatisticCount
= s
- pStatistics
;
5474 *pStatisticCount
= end
- pStatistics
;
5475 result
= VK_INCOMPLETE
;
5477 *pStatisticCount
= s
- pStatistics
;
5483 static VkResult
radv_copy_representation(void *data
, size_t *data_size
, const char *src
)
5485 size_t total_size
= strlen(src
) + 1;
5488 *data_size
= total_size
;
5492 size_t size
= MIN2(total_size
, *data_size
);
5494 memcpy(data
, src
, size
);
5496 *((char*)data
+ size
- 1) = 0;
5497 return size
< total_size
? VK_INCOMPLETE
: VK_SUCCESS
;
5500 VkResult
radv_GetPipelineExecutableInternalRepresentationsKHR(
5502 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5503 uint32_t* pInternalRepresentationCount
,
5504 VkPipelineExecutableInternalRepresentationKHR
* pInternalRepresentations
)
5506 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5507 gl_shader_stage stage
;
5508 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5510 VkPipelineExecutableInternalRepresentationKHR
*p
= pInternalRepresentations
;
5511 VkPipelineExecutableInternalRepresentationKHR
*end
= p
+ (pInternalRepresentations
? *pInternalRepresentationCount
: 0);
5512 VkResult result
= VK_SUCCESS
;
5516 desc_copy(p
->name
, "NIR Shader(s)");
5517 desc_copy(p
->description
, "The optimized NIR shader(s)");
5518 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->nir_string
) != VK_SUCCESS
)
5519 result
= VK_INCOMPLETE
;
5526 if (shader
->aco_used
) {
5527 desc_copy(p
->name
, "ACO IR");
5528 desc_copy(p
->description
, "The ACO IR after some optimizations");
5530 desc_copy(p
->name
, "LLVM IR");
5531 desc_copy(p
->description
, "The LLVM IR after some optimizations");
5533 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->ir_string
) != VK_SUCCESS
)
5534 result
= VK_INCOMPLETE
;
5541 desc_copy(p
->name
, "Assembly");
5542 desc_copy(p
->description
, "Final Assembly");
5543 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->disasm_string
) != VK_SUCCESS
)
5544 result
= VK_INCOMPLETE
;
5548 if (!pInternalRepresentations
)
5549 *pInternalRepresentationCount
= p
- pInternalRepresentations
;
5551 result
= VK_INCOMPLETE
;
5552 *pInternalRepresentationCount
= end
- pInternalRepresentations
;
5554 *pInternalRepresentationCount
= p
- pInternalRepresentations
;