2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
34 #include "radv_shader.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
41 #include <llvm-c/Core.h>
42 #include <llvm-c/TargetMachine.h>
45 #include "ac_binary.h"
46 #include "ac_llvm_util.h"
47 #include "ac_nir_to_llvm.h"
48 #include "vk_format.h"
49 #include "util/debug.h"
50 #include "ac_exp_param.h"
51 #include "ac_shader_util.h"
52 #include "main/menums.h"
54 struct radv_blend_state
{
55 uint32_t blend_enable_4bit
;
56 uint32_t need_src_alpha
;
58 uint32_t cb_color_control
;
59 uint32_t cb_target_mask
;
60 uint32_t cb_target_enabled_4bit
;
61 uint32_t sx_mrt_blend_opt
[8];
62 uint32_t cb_blend_control
[8];
64 uint32_t spi_shader_col_format
;
65 uint32_t cb_shader_mask
;
66 uint32_t db_alpha_to_mask
;
68 uint32_t commutative_4bit
;
70 bool single_cb_enable
;
71 bool mrt0_is_dual_src
;
74 struct radv_dsa_order_invariance
{
75 /* Whether the final result in Z/S buffers is guaranteed to be
76 * invariant under changes to the order in which fragments arrive.
80 /* Whether the set of fragments that pass the combined Z/S test is
81 * guaranteed to be invariant under changes to the order in which
87 struct radv_tessellation_state
{
88 uint32_t ls_hs_config
;
94 static const VkPipelineMultisampleStateCreateInfo
*
95 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
97 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
98 return pCreateInfo
->pMultisampleState
;
102 static const VkPipelineTessellationStateCreateInfo
*
103 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
105 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
106 if (pCreateInfo
->pStages
[i
].stage
== VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
||
107 pCreateInfo
->pStages
[i
].stage
== VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
) {
108 return pCreateInfo
->pTessellationState
;
114 static const VkPipelineDepthStencilStateCreateInfo
*
115 radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
117 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
118 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
120 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
121 subpass
->depth_stencil_attachment
)
122 return pCreateInfo
->pDepthStencilState
;
126 static const VkPipelineColorBlendStateCreateInfo
*
127 radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
129 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
130 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
132 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
133 subpass
->has_color_att
)
134 return pCreateInfo
->pColorBlendState
;
138 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
)
140 struct radv_shader_variant
*variant
= NULL
;
141 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
142 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
143 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
144 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
145 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
146 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
149 return variant
->info
.is_ngg
;
152 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline
*pipeline
)
154 assert(radv_pipeline_has_ngg(pipeline
));
156 struct radv_shader_variant
*variant
= NULL
;
157 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
158 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
159 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
160 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
161 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
162 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
165 return variant
->info
.is_ngg_passthrough
;
168 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
)
170 if (!radv_pipeline_has_gs(pipeline
))
173 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
174 * On GFX10, it might be required in rare cases if it's not possible to
177 if (radv_pipeline_has_ngg(pipeline
))
180 assert(pipeline
->gs_copy_shader
);
185 radv_pipeline_destroy(struct radv_device
*device
,
186 struct radv_pipeline
*pipeline
,
187 const VkAllocationCallbacks
* allocator
)
189 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
190 if (pipeline
->shaders
[i
])
191 radv_shader_variant_destroy(device
, pipeline
->shaders
[i
]);
193 if (pipeline
->gs_copy_shader
)
194 radv_shader_variant_destroy(device
, pipeline
->gs_copy_shader
);
197 free(pipeline
->cs
.buf
);
198 vk_free2(&device
->alloc
, allocator
, pipeline
);
201 void radv_DestroyPipeline(
203 VkPipeline _pipeline
,
204 const VkAllocationCallbacks
* pAllocator
)
206 RADV_FROM_HANDLE(radv_device
, device
, _device
);
207 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
212 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
215 static uint32_t get_hash_flags(struct radv_device
*device
)
217 uint32_t hash_flags
= 0;
219 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_NGG
)
220 hash_flags
|= RADV_HASH_SHADER_NO_NGG
;
221 if (device
->instance
->perftest_flags
& RADV_PERFTEST_SISCHED
)
222 hash_flags
|= RADV_HASH_SHADER_SISCHED
;
223 if (device
->physical_device
->cs_wave_size
== 32)
224 hash_flags
|= RADV_HASH_SHADER_CS_WAVE32
;
225 if (device
->physical_device
->ps_wave_size
== 32)
226 hash_flags
|= RADV_HASH_SHADER_PS_WAVE32
;
227 if (device
->physical_device
->ge_wave_size
== 32)
228 hash_flags
|= RADV_HASH_SHADER_GE_WAVE32
;
229 if (device
->physical_device
->use_aco
)
230 hash_flags
|= RADV_HASH_SHADER_ACO
;
235 radv_pipeline_scratch_init(struct radv_device
*device
,
236 struct radv_pipeline
*pipeline
)
238 unsigned scratch_bytes_per_wave
= 0;
239 unsigned max_waves
= 0;
240 unsigned min_waves
= 1;
242 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
243 if (pipeline
->shaders
[i
] &&
244 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
) {
245 unsigned max_stage_waves
= device
->scratch_waves
;
247 scratch_bytes_per_wave
= MAX2(scratch_bytes_per_wave
,
248 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
);
250 max_stage_waves
= MIN2(max_stage_waves
,
251 4 * device
->physical_device
->rad_info
.num_good_compute_units
*
252 (256 / pipeline
->shaders
[i
]->config
.num_vgprs
));
253 max_waves
= MAX2(max_waves
, max_stage_waves
);
257 if (pipeline
->shaders
[MESA_SHADER_COMPUTE
]) {
258 unsigned group_size
= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[0] *
259 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[1] *
260 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[2];
261 min_waves
= MAX2(min_waves
, round_up_u32(group_size
, 64));
264 pipeline
->scratch_bytes_per_wave
= scratch_bytes_per_wave
;
265 pipeline
->max_waves
= max_waves
;
269 static uint32_t si_translate_blend_logic_op(VkLogicOp op
)
272 case VK_LOGIC_OP_CLEAR
:
273 return V_028808_ROP3_CLEAR
;
274 case VK_LOGIC_OP_AND
:
275 return V_028808_ROP3_AND
;
276 case VK_LOGIC_OP_AND_REVERSE
:
277 return V_028808_ROP3_AND_REVERSE
;
278 case VK_LOGIC_OP_COPY
:
279 return V_028808_ROP3_COPY
;
280 case VK_LOGIC_OP_AND_INVERTED
:
281 return V_028808_ROP3_AND_INVERTED
;
282 case VK_LOGIC_OP_NO_OP
:
283 return V_028808_ROP3_NO_OP
;
284 case VK_LOGIC_OP_XOR
:
285 return V_028808_ROP3_XOR
;
287 return V_028808_ROP3_OR
;
288 case VK_LOGIC_OP_NOR
:
289 return V_028808_ROP3_NOR
;
290 case VK_LOGIC_OP_EQUIVALENT
:
291 return V_028808_ROP3_EQUIVALENT
;
292 case VK_LOGIC_OP_INVERT
:
293 return V_028808_ROP3_INVERT
;
294 case VK_LOGIC_OP_OR_REVERSE
:
295 return V_028808_ROP3_OR_REVERSE
;
296 case VK_LOGIC_OP_COPY_INVERTED
:
297 return V_028808_ROP3_COPY_INVERTED
;
298 case VK_LOGIC_OP_OR_INVERTED
:
299 return V_028808_ROP3_OR_INVERTED
;
300 case VK_LOGIC_OP_NAND
:
301 return V_028808_ROP3_NAND
;
302 case VK_LOGIC_OP_SET
:
303 return V_028808_ROP3_SET
;
305 unreachable("Unhandled logic op");
310 static uint32_t si_translate_blend_function(VkBlendOp op
)
313 case VK_BLEND_OP_ADD
:
314 return V_028780_COMB_DST_PLUS_SRC
;
315 case VK_BLEND_OP_SUBTRACT
:
316 return V_028780_COMB_SRC_MINUS_DST
;
317 case VK_BLEND_OP_REVERSE_SUBTRACT
:
318 return V_028780_COMB_DST_MINUS_SRC
;
319 case VK_BLEND_OP_MIN
:
320 return V_028780_COMB_MIN_DST_SRC
;
321 case VK_BLEND_OP_MAX
:
322 return V_028780_COMB_MAX_DST_SRC
;
328 static uint32_t si_translate_blend_factor(VkBlendFactor factor
)
331 case VK_BLEND_FACTOR_ZERO
:
332 return V_028780_BLEND_ZERO
;
333 case VK_BLEND_FACTOR_ONE
:
334 return V_028780_BLEND_ONE
;
335 case VK_BLEND_FACTOR_SRC_COLOR
:
336 return V_028780_BLEND_SRC_COLOR
;
337 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
338 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
339 case VK_BLEND_FACTOR_DST_COLOR
:
340 return V_028780_BLEND_DST_COLOR
;
341 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
342 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
343 case VK_BLEND_FACTOR_SRC_ALPHA
:
344 return V_028780_BLEND_SRC_ALPHA
;
345 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
346 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
347 case VK_BLEND_FACTOR_DST_ALPHA
:
348 return V_028780_BLEND_DST_ALPHA
;
349 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
350 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
351 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
352 return V_028780_BLEND_CONSTANT_COLOR
;
353 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
354 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
355 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
356 return V_028780_BLEND_CONSTANT_ALPHA
;
357 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
358 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
359 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
360 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
361 case VK_BLEND_FACTOR_SRC1_COLOR
:
362 return V_028780_BLEND_SRC1_COLOR
;
363 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
364 return V_028780_BLEND_INV_SRC1_COLOR
;
365 case VK_BLEND_FACTOR_SRC1_ALPHA
:
366 return V_028780_BLEND_SRC1_ALPHA
;
367 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
368 return V_028780_BLEND_INV_SRC1_ALPHA
;
374 static uint32_t si_translate_blend_opt_function(VkBlendOp op
)
377 case VK_BLEND_OP_ADD
:
378 return V_028760_OPT_COMB_ADD
;
379 case VK_BLEND_OP_SUBTRACT
:
380 return V_028760_OPT_COMB_SUBTRACT
;
381 case VK_BLEND_OP_REVERSE_SUBTRACT
:
382 return V_028760_OPT_COMB_REVSUBTRACT
;
383 case VK_BLEND_OP_MIN
:
384 return V_028760_OPT_COMB_MIN
;
385 case VK_BLEND_OP_MAX
:
386 return V_028760_OPT_COMB_MAX
;
388 return V_028760_OPT_COMB_BLEND_DISABLED
;
392 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor
, bool is_alpha
)
395 case VK_BLEND_FACTOR_ZERO
:
396 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
397 case VK_BLEND_FACTOR_ONE
:
398 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
399 case VK_BLEND_FACTOR_SRC_COLOR
:
400 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
401 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
402 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
403 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
404 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
405 case VK_BLEND_FACTOR_SRC_ALPHA
:
406 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
407 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
408 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
409 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
410 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
411 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
413 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
418 * Get rid of DST in the blend factors by commuting the operands:
419 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
421 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
422 unsigned *dst_factor
, unsigned expected_dst
,
423 unsigned replacement_src
)
425 if (*src_factor
== expected_dst
&&
426 *dst_factor
== VK_BLEND_FACTOR_ZERO
) {
427 *src_factor
= VK_BLEND_FACTOR_ZERO
;
428 *dst_factor
= replacement_src
;
430 /* Commuting the operands requires reversing subtractions. */
431 if (*func
== VK_BLEND_OP_SUBTRACT
)
432 *func
= VK_BLEND_OP_REVERSE_SUBTRACT
;
433 else if (*func
== VK_BLEND_OP_REVERSE_SUBTRACT
)
434 *func
= VK_BLEND_OP_SUBTRACT
;
438 static bool si_blend_factor_uses_dst(unsigned factor
)
440 return factor
== VK_BLEND_FACTOR_DST_COLOR
||
441 factor
== VK_BLEND_FACTOR_DST_ALPHA
||
442 factor
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
443 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
||
444 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
;
447 static bool is_dual_src(VkBlendFactor factor
)
450 case VK_BLEND_FACTOR_SRC1_COLOR
:
451 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
452 case VK_BLEND_FACTOR_SRC1_ALPHA
:
453 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
460 static unsigned si_choose_spi_color_format(VkFormat vk_format
,
462 bool blend_need_alpha
)
464 const struct vk_format_description
*desc
= vk_format_description(vk_format
);
465 unsigned format
, ntype
, swap
;
467 /* Alpha is needed for alpha-to-coverage.
468 * Blending may be with or without alpha.
470 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
471 unsigned alpha
= 0; /* exports alpha, but may not support blending */
472 unsigned blend
= 0; /* supports blending, but may not export alpha */
473 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
475 format
= radv_translate_colorformat(vk_format
);
476 ntype
= radv_translate_color_numformat(vk_format
, desc
,
477 vk_format_get_first_non_void_channel(vk_format
));
478 swap
= radv_translate_colorswap(vk_format
, false);
480 /* Choose the SPI color formats. These are required values for Stoney/RB+.
481 * Other chips have multiple choices, though they are not necessarily better.
484 case V_028C70_COLOR_5_6_5
:
485 case V_028C70_COLOR_1_5_5_5
:
486 case V_028C70_COLOR_5_5_5_1
:
487 case V_028C70_COLOR_4_4_4_4
:
488 case V_028C70_COLOR_10_11_11
:
489 case V_028C70_COLOR_11_11_10
:
490 case V_028C70_COLOR_8
:
491 case V_028C70_COLOR_8_8
:
492 case V_028C70_COLOR_8_8_8_8
:
493 case V_028C70_COLOR_10_10_10_2
:
494 case V_028C70_COLOR_2_10_10_10
:
495 if (ntype
== V_028C70_NUMBER_UINT
)
496 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
497 else if (ntype
== V_028C70_NUMBER_SINT
)
498 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
500 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
503 case V_028C70_COLOR_16
:
504 case V_028C70_COLOR_16_16
:
505 case V_028C70_COLOR_16_16_16_16
:
506 if (ntype
== V_028C70_NUMBER_UNORM
||
507 ntype
== V_028C70_NUMBER_SNORM
) {
508 /* UNORM16 and SNORM16 don't support blending */
509 if (ntype
== V_028C70_NUMBER_UNORM
)
510 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
512 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
514 /* Use 32 bits per channel for blending. */
515 if (format
== V_028C70_COLOR_16
) {
516 if (swap
== V_028C70_SWAP_STD
) { /* R */
517 blend
= V_028714_SPI_SHADER_32_R
;
518 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
519 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
520 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
523 } else if (format
== V_028C70_COLOR_16_16
) {
524 if (swap
== V_028C70_SWAP_STD
) { /* RG */
525 blend
= V_028714_SPI_SHADER_32_GR
;
526 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
527 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
528 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
531 } else /* 16_16_16_16 */
532 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
533 } else if (ntype
== V_028C70_NUMBER_UINT
)
534 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
535 else if (ntype
== V_028C70_NUMBER_SINT
)
536 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
537 else if (ntype
== V_028C70_NUMBER_FLOAT
)
538 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
543 case V_028C70_COLOR_32
:
544 if (swap
== V_028C70_SWAP_STD
) { /* R */
545 blend
= normal
= V_028714_SPI_SHADER_32_R
;
546 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
547 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
548 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
553 case V_028C70_COLOR_32_32
:
554 if (swap
== V_028C70_SWAP_STD
) { /* RG */
555 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
556 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
557 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
558 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
563 case V_028C70_COLOR_32_32_32_32
:
564 case V_028C70_COLOR_8_24
:
565 case V_028C70_COLOR_24_8
:
566 case V_028C70_COLOR_X24_8_32_FLOAT
:
567 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
571 unreachable("unhandled blend format");
574 if (blend_enable
&& blend_need_alpha
)
576 else if(blend_need_alpha
)
578 else if(blend_enable
)
585 radv_pipeline_compute_spi_color_formats(struct radv_pipeline
*pipeline
,
586 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
587 struct radv_blend_state
*blend
)
589 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
590 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
591 unsigned col_format
= 0;
592 unsigned num_targets
;
594 for (unsigned i
= 0; i
< (blend
->single_cb_enable
? 1 : subpass
->color_count
); ++i
) {
597 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
598 cf
= V_028714_SPI_SHADER_ZERO
;
600 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
602 blend
->blend_enable_4bit
& (0xfu
<< (i
* 4));
604 cf
= si_choose_spi_color_format(attachment
->format
,
606 blend
->need_src_alpha
& (1 << i
));
609 col_format
|= cf
<< (4 * i
);
612 if (!(col_format
& 0xf) && blend
->need_src_alpha
& (1 << 0)) {
613 /* When a subpass doesn't have any color attachments, write the
614 * alpha channel of MRT0 when alpha coverage is enabled because
615 * the depth attachment needs it.
617 col_format
|= V_028714_SPI_SHADER_32_AR
;
620 /* If the i-th target format is set, all previous target formats must
621 * be non-zero to avoid hangs.
623 num_targets
= (util_last_bit(col_format
) + 3) / 4;
624 for (unsigned i
= 0; i
< num_targets
; i
++) {
625 if (!(col_format
& (0xf << (i
* 4)))) {
626 col_format
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
630 /* The output for dual source blending should have the same format as
633 if (blend
->mrt0_is_dual_src
)
634 col_format
|= (col_format
& 0xf) << 4;
636 blend
->cb_shader_mask
= ac_get_cb_shader_mask(col_format
);
637 blend
->spi_shader_col_format
= col_format
;
641 format_is_int8(VkFormat format
)
643 const struct vk_format_description
*desc
= vk_format_description(format
);
644 int channel
= vk_format_get_first_non_void_channel(format
);
646 return channel
>= 0 && desc
->channel
[channel
].pure_integer
&&
647 desc
->channel
[channel
].size
== 8;
651 format_is_int10(VkFormat format
)
653 const struct vk_format_description
*desc
= vk_format_description(format
);
655 if (desc
->nr_channels
!= 4)
657 for (unsigned i
= 0; i
< 4; i
++) {
658 if (desc
->channel
[i
].pure_integer
&& desc
->channel
[i
].size
== 10)
665 * Ordered so that for each i,
666 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
668 const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
] = {
669 VK_FORMAT_R32_SFLOAT
,
670 VK_FORMAT_R32G32_SFLOAT
,
671 VK_FORMAT_R8G8B8A8_UNORM
,
672 VK_FORMAT_R16G16B16A16_UNORM
,
673 VK_FORMAT_R16G16B16A16_SNORM
,
674 VK_FORMAT_R16G16B16A16_UINT
,
675 VK_FORMAT_R16G16B16A16_SINT
,
676 VK_FORMAT_R32G32B32A32_SFLOAT
,
677 VK_FORMAT_R8G8B8A8_UINT
,
678 VK_FORMAT_R8G8B8A8_SINT
,
679 VK_FORMAT_A2R10G10B10_UINT_PACK32
,
680 VK_FORMAT_A2R10G10B10_SINT_PACK32
,
683 unsigned radv_format_meta_fs_key(VkFormat format
)
685 unsigned col_format
= si_choose_spi_color_format(format
, false, false);
687 assert(col_format
!= V_028714_SPI_SHADER_32_AR
);
688 if (col_format
>= V_028714_SPI_SHADER_32_AR
)
689 --col_format
; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
691 --col_format
; /* Skip V_028714_SPI_SHADER_ZERO */
692 bool is_int8
= format_is_int8(format
);
693 bool is_int10
= format_is_int10(format
);
695 return col_format
+ (is_int8
? 3 : is_int10
? 5 : 0);
699 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
700 unsigned *is_int8
, unsigned *is_int10
)
702 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
703 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
707 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
708 struct radv_render_pass_attachment
*attachment
;
710 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
713 attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
715 if (format_is_int8(attachment
->format
))
717 if (format_is_int10(attachment
->format
))
723 radv_blend_check_commutativity(struct radv_blend_state
*blend
,
724 VkBlendOp op
, VkBlendFactor src
,
725 VkBlendFactor dst
, unsigned chanmask
)
727 /* Src factor is allowed when it does not depend on Dst. */
728 static const uint32_t src_allowed
=
729 (1u << VK_BLEND_FACTOR_ONE
) |
730 (1u << VK_BLEND_FACTOR_SRC_COLOR
) |
731 (1u << VK_BLEND_FACTOR_SRC_ALPHA
) |
732 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
) |
733 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR
) |
734 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA
) |
735 (1u << VK_BLEND_FACTOR_SRC1_COLOR
) |
736 (1u << VK_BLEND_FACTOR_SRC1_ALPHA
) |
737 (1u << VK_BLEND_FACTOR_ZERO
) |
738 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
) |
739 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
) |
740 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
) |
741 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
) |
742 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
) |
743 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
);
745 if (dst
== VK_BLEND_FACTOR_ONE
&&
746 (src_allowed
& (1u << src
))) {
747 /* Addition is commutative, but floating point addition isn't
748 * associative: subtle changes can be introduced via different
749 * rounding. Be conservative, only enable for min and max.
751 if (op
== VK_BLEND_OP_MAX
|| op
== VK_BLEND_OP_MIN
)
752 blend
->commutative_4bit
|= chanmask
;
756 static struct radv_blend_state
757 radv_pipeline_init_blend_state(struct radv_pipeline
*pipeline
,
758 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
759 const struct radv_graphics_pipeline_create_info
*extra
)
761 const VkPipelineColorBlendStateCreateInfo
*vkblend
= radv_pipeline_get_color_blend_state(pCreateInfo
);
762 const VkPipelineMultisampleStateCreateInfo
*vkms
= radv_pipeline_get_multisample_state(pCreateInfo
);
763 struct radv_blend_state blend
= {0};
764 unsigned mode
= V_028808_CB_NORMAL
;
767 if (extra
&& extra
->custom_blend_mode
) {
768 blend
.single_cb_enable
= true;
769 mode
= extra
->custom_blend_mode
;
772 blend
.cb_color_control
= 0;
774 if (vkblend
->logicOpEnable
)
775 blend
.cb_color_control
|= S_028808_ROP3(si_translate_blend_logic_op(vkblend
->logicOp
));
777 blend
.cb_color_control
|= S_028808_ROP3(V_028808_ROP3_COPY
);
780 blend
.db_alpha_to_mask
= S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
781 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
782 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
783 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
784 S_028B70_OFFSET_ROUND(1);
786 if (vkms
&& vkms
->alphaToCoverageEnable
) {
787 blend
.db_alpha_to_mask
|= S_028B70_ALPHA_TO_MASK_ENABLE(1);
788 blend
.need_src_alpha
|= 0x1;
791 blend
.cb_target_mask
= 0;
793 for (i
= 0; i
< vkblend
->attachmentCount
; i
++) {
794 const VkPipelineColorBlendAttachmentState
*att
= &vkblend
->pAttachments
[i
];
795 unsigned blend_cntl
= 0;
796 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
797 VkBlendOp eqRGB
= att
->colorBlendOp
;
798 VkBlendFactor srcRGB
= att
->srcColorBlendFactor
;
799 VkBlendFactor dstRGB
= att
->dstColorBlendFactor
;
800 VkBlendOp eqA
= att
->alphaBlendOp
;
801 VkBlendFactor srcA
= att
->srcAlphaBlendFactor
;
802 VkBlendFactor dstA
= att
->dstAlphaBlendFactor
;
804 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
806 if (!att
->colorWriteMask
)
809 blend
.cb_target_mask
|= (unsigned)att
->colorWriteMask
<< (4 * i
);
810 blend
.cb_target_enabled_4bit
|= 0xf << (4 * i
);
811 if (!att
->blendEnable
) {
812 blend
.cb_blend_control
[i
] = blend_cntl
;
816 if (is_dual_src(srcRGB
) || is_dual_src(dstRGB
) || is_dual_src(srcA
) || is_dual_src(dstA
))
818 blend
.mrt0_is_dual_src
= true;
820 if (eqRGB
== VK_BLEND_OP_MIN
|| eqRGB
== VK_BLEND_OP_MAX
) {
821 srcRGB
= VK_BLEND_FACTOR_ONE
;
822 dstRGB
= VK_BLEND_FACTOR_ONE
;
824 if (eqA
== VK_BLEND_OP_MIN
|| eqA
== VK_BLEND_OP_MAX
) {
825 srcA
= VK_BLEND_FACTOR_ONE
;
826 dstA
= VK_BLEND_FACTOR_ONE
;
829 radv_blend_check_commutativity(&blend
, eqRGB
, srcRGB
, dstRGB
,
831 radv_blend_check_commutativity(&blend
, eqA
, srcA
, dstA
,
834 /* Blending optimizations for RB+.
835 * These transformations don't change the behavior.
837 * First, get rid of DST in the blend factors:
838 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
840 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
841 VK_BLEND_FACTOR_DST_COLOR
,
842 VK_BLEND_FACTOR_SRC_COLOR
);
844 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
845 VK_BLEND_FACTOR_DST_COLOR
,
846 VK_BLEND_FACTOR_SRC_COLOR
);
848 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
849 VK_BLEND_FACTOR_DST_ALPHA
,
850 VK_BLEND_FACTOR_SRC_ALPHA
);
852 /* Look up the ideal settings from tables. */
853 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
854 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
855 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
856 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
858 /* Handle interdependencies. */
859 if (si_blend_factor_uses_dst(srcRGB
))
860 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
861 if (si_blend_factor_uses_dst(srcA
))
862 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
864 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
&&
865 (dstRGB
== VK_BLEND_FACTOR_ZERO
||
866 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
867 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
))
868 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
870 /* Set the final value. */
871 blend
.sx_mrt_blend_opt
[i
] =
872 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
873 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
874 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
875 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
876 S_028760_ALPHA_DST_OPT(dstA_opt
) |
877 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
878 blend_cntl
|= S_028780_ENABLE(1);
880 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
881 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
882 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
883 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
884 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
885 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
886 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
887 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
889 blend
.cb_blend_control
[i
] = blend_cntl
;
891 blend
.blend_enable_4bit
|= 0xfu
<< (i
* 4);
893 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
894 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
895 srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
896 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
897 srcRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
||
898 dstRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
)
899 blend
.need_src_alpha
|= 1 << i
;
901 for (i
= vkblend
->attachmentCount
; i
< 8; i
++) {
902 blend
.cb_blend_control
[i
] = 0;
903 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
907 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
908 /* Disable RB+ blend optimizations for dual source blending. */
909 if (blend
.mrt0_is_dual_src
) {
910 for (i
= 0; i
< 8; i
++) {
911 blend
.sx_mrt_blend_opt
[i
] =
912 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
913 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
917 /* RB+ doesn't work with dual source blending, logic op and
920 if (blend
.mrt0_is_dual_src
||
921 (vkblend
&& vkblend
->logicOpEnable
) ||
922 mode
== V_028808_CB_RESOLVE
)
923 blend
.cb_color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
926 if (blend
.cb_target_mask
)
927 blend
.cb_color_control
|= S_028808_MODE(mode
);
929 blend
.cb_color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
931 radv_pipeline_compute_spi_color_formats(pipeline
, pCreateInfo
, &blend
);
935 static uint32_t si_translate_stencil_op(enum VkStencilOp op
)
938 case VK_STENCIL_OP_KEEP
:
939 return V_02842C_STENCIL_KEEP
;
940 case VK_STENCIL_OP_ZERO
:
941 return V_02842C_STENCIL_ZERO
;
942 case VK_STENCIL_OP_REPLACE
:
943 return V_02842C_STENCIL_REPLACE_TEST
;
944 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
945 return V_02842C_STENCIL_ADD_CLAMP
;
946 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
947 return V_02842C_STENCIL_SUB_CLAMP
;
948 case VK_STENCIL_OP_INVERT
:
949 return V_02842C_STENCIL_INVERT
;
950 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
951 return V_02842C_STENCIL_ADD_WRAP
;
952 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
953 return V_02842C_STENCIL_SUB_WRAP
;
959 static uint32_t si_translate_fill(VkPolygonMode func
)
962 case VK_POLYGON_MODE_FILL
:
963 return V_028814_X_DRAW_TRIANGLES
;
964 case VK_POLYGON_MODE_LINE
:
965 return V_028814_X_DRAW_LINES
;
966 case VK_POLYGON_MODE_POINT
:
967 return V_028814_X_DRAW_POINTS
;
970 return V_028814_X_DRAW_POINTS
;
974 static uint8_t radv_pipeline_get_ps_iter_samples(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
976 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
977 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
978 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
979 uint32_t ps_iter_samples
= 1;
980 uint32_t num_samples
;
982 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
984 * "If the VK_AMD_mixed_attachment_samples extension is enabled and the
985 * subpass uses color attachments, totalSamples is the number of
986 * samples of the color attachments. Otherwise, totalSamples is the
987 * value of VkPipelineMultisampleStateCreateInfo::rasterizationSamples
988 * specified at pipeline creation time."
990 if (subpass
->has_color_att
) {
991 num_samples
= subpass
->color_sample_count
;
993 num_samples
= vkms
->rasterizationSamples
;
996 if (vkms
->sampleShadingEnable
) {
997 ps_iter_samples
= ceil(vkms
->minSampleShading
* num_samples
);
998 ps_iter_samples
= util_next_power_of_two(ps_iter_samples
);
1000 return ps_iter_samples
;
1004 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
1006 return pCreateInfo
->depthTestEnable
&&
1007 pCreateInfo
->depthWriteEnable
&&
1008 pCreateInfo
->depthCompareOp
!= VK_COMPARE_OP_NEVER
;
1012 radv_writes_stencil(const VkStencilOpState
*state
)
1014 return state
->writeMask
&&
1015 (state
->failOp
!= VK_STENCIL_OP_KEEP
||
1016 state
->passOp
!= VK_STENCIL_OP_KEEP
||
1017 state
->depthFailOp
!= VK_STENCIL_OP_KEEP
);
1021 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
1023 return pCreateInfo
->stencilTestEnable
&&
1024 (radv_writes_stencil(&pCreateInfo
->front
) ||
1025 radv_writes_stencil(&pCreateInfo
->back
));
1029 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
1031 return radv_is_depth_write_enabled(pCreateInfo
) ||
1032 radv_is_stencil_write_enabled(pCreateInfo
);
1036 radv_order_invariant_stencil_op(VkStencilOp op
)
1038 /* REPLACE is normally order invariant, except when the stencil
1039 * reference value is written by the fragment shader. Tracking this
1040 * interaction does not seem worth the effort, so be conservative.
1042 return op
!= VK_STENCIL_OP_INCREMENT_AND_CLAMP
&&
1043 op
!= VK_STENCIL_OP_DECREMENT_AND_CLAMP
&&
1044 op
!= VK_STENCIL_OP_REPLACE
;
1048 radv_order_invariant_stencil_state(const VkStencilOpState
*state
)
1050 /* Compute whether, assuming Z writes are disabled, this stencil state
1051 * is order invariant in the sense that the set of passing fragments as
1052 * well as the final stencil buffer result does not depend on the order
1055 return !state
->writeMask
||
1056 /* The following assumes that Z writes are disabled. */
1057 (state
->compareOp
== VK_COMPARE_OP_ALWAYS
&&
1058 radv_order_invariant_stencil_op(state
->passOp
) &&
1059 radv_order_invariant_stencil_op(state
->depthFailOp
)) ||
1060 (state
->compareOp
== VK_COMPARE_OP_NEVER
&&
1061 radv_order_invariant_stencil_op(state
->failOp
));
1065 radv_pipeline_out_of_order_rast(struct radv_pipeline
*pipeline
,
1066 struct radv_blend_state
*blend
,
1067 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1069 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1070 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
1071 const VkPipelineDepthStencilStateCreateInfo
*vkds
= radv_pipeline_get_depth_stencil_state(pCreateInfo
);
1072 const VkPipelineColorBlendStateCreateInfo
*vkblend
= radv_pipeline_get_color_blend_state(pCreateInfo
);
1073 unsigned colormask
= blend
->cb_target_enabled_4bit
;
1075 if (!pipeline
->device
->physical_device
->out_of_order_rast_allowed
)
1078 /* Be conservative if a logic operation is enabled with color buffers. */
1079 if (colormask
&& vkblend
&& vkblend
->logicOpEnable
)
1082 /* Default depth/stencil invariance when no attachment is bound. */
1083 struct radv_dsa_order_invariance dsa_order_invariant
= {
1084 .zs
= true, .pass_set
= true
1088 struct radv_render_pass_attachment
*attachment
=
1089 pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
1090 bool has_stencil
= vk_format_is_stencil(attachment
->format
);
1091 struct radv_dsa_order_invariance order_invariance
[2];
1092 struct radv_shader_variant
*ps
=
1093 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
1095 /* Compute depth/stencil order invariance in order to know if
1096 * it's safe to enable out-of-order.
1098 bool zfunc_is_ordered
=
1099 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
||
1100 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS
||
1101 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS_OR_EQUAL
||
1102 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER
||
1103 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER_OR_EQUAL
;
1105 bool nozwrite_and_order_invariant_stencil
=
1106 !radv_is_ds_write_enabled(vkds
) ||
1107 (!radv_is_depth_write_enabled(vkds
) &&
1108 radv_order_invariant_stencil_state(&vkds
->front
) &&
1109 radv_order_invariant_stencil_state(&vkds
->back
));
1111 order_invariance
[1].zs
=
1112 nozwrite_and_order_invariant_stencil
||
1113 (!radv_is_stencil_write_enabled(vkds
) &&
1115 order_invariance
[0].zs
=
1116 !radv_is_depth_write_enabled(vkds
) || zfunc_is_ordered
;
1118 order_invariance
[1].pass_set
=
1119 nozwrite_and_order_invariant_stencil
||
1120 (!radv_is_stencil_write_enabled(vkds
) &&
1121 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1122 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
));
1123 order_invariance
[0].pass_set
=
1124 !radv_is_depth_write_enabled(vkds
) ||
1125 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1126 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
);
1128 dsa_order_invariant
= order_invariance
[has_stencil
];
1129 if (!dsa_order_invariant
.zs
)
1132 /* The set of PS invocations is always order invariant,
1133 * except when early Z/S tests are requested.
1136 ps
->info
.ps
.writes_memory
&&
1137 ps
->info
.ps
.early_fragment_test
&&
1138 !dsa_order_invariant
.pass_set
)
1141 /* Determine if out-of-order rasterization should be disabled
1142 * when occlusion queries are used.
1144 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
=
1145 !dsa_order_invariant
.pass_set
;
1148 /* No color buffers are enabled for writing. */
1152 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
1155 /* Only commutative blending. */
1156 if (blendmask
& ~blend
->commutative_4bit
)
1159 if (!dsa_order_invariant
.pass_set
)
1163 if (colormask
& ~blendmask
)
1170 radv_pipeline_init_multisample_state(struct radv_pipeline
*pipeline
,
1171 struct radv_blend_state
*blend
,
1172 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1174 const VkPipelineMultisampleStateCreateInfo
*vkms
= radv_pipeline_get_multisample_state(pCreateInfo
);
1175 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
1176 unsigned num_tile_pipes
= pipeline
->device
->physical_device
->rad_info
.num_tile_pipes
;
1177 bool out_of_order_rast
= false;
1178 int ps_iter_samples
= 1;
1179 uint32_t mask
= 0xffff;
1182 ms
->num_samples
= vkms
->rasterizationSamples
;
1184 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1186 * "Sample shading is enabled for a graphics pipeline:
1188 * - If the interface of the fragment shader entry point of the
1189 * graphics pipeline includes an input variable decorated
1190 * with SampleId or SamplePosition. In this case
1191 * minSampleShadingFactor takes the value 1.0.
1192 * - Else if the sampleShadingEnable member of the
1193 * VkPipelineMultisampleStateCreateInfo structure specified
1194 * when creating the graphics pipeline is set to VK_TRUE. In
1195 * this case minSampleShadingFactor takes the value of
1196 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1198 * Otherwise, sample shading is considered disabled."
1200 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.force_persample
) {
1201 ps_iter_samples
= ms
->num_samples
;
1203 ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
);
1206 ms
->num_samples
= 1;
1209 const struct VkPipelineRasterizationStateRasterizationOrderAMD
*raster_order
=
1210 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD
);
1211 if (raster_order
&& raster_order
->rasterizationOrder
== VK_RASTERIZATION_ORDER_RELAXED_AMD
) {
1212 /* Out-of-order rasterization is explicitly enabled by the
1215 out_of_order_rast
= true;
1217 /* Determine if the driver can enable out-of-order
1218 * rasterization internally.
1221 radv_pipeline_out_of_order_rast(pipeline
, blend
, pCreateInfo
);
1224 ms
->pa_sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1225 ms
->pa_sc_aa_config
= 0;
1226 ms
->db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1227 S_028804_INCOHERENT_EQAA_READS(1) |
1228 S_028804_INTERPOLATE_COMP_Z(1) |
1229 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1230 ms
->pa_sc_mode_cntl_1
=
1231 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1232 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
1233 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
1234 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1236 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1237 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1238 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1239 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1240 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1241 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1242 ms
->pa_sc_mode_cntl_0
= S_028A48_ALTERNATE_RBS_PER_TILE(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
1243 S_028A48_VPORT_SCISSOR_ENABLE(1);
1245 const VkPipelineRasterizationLineStateCreateInfoEXT
*rast_line
=
1246 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1247 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1249 ms
->pa_sc_mode_cntl_0
|= S_028A48_LINE_STIPPLE_ENABLE(rast_line
->stippledLineEnable
);
1250 if (rast_line
->lineRasterizationMode
== VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT
) {
1251 /* From the Vulkan spec 1.1.129:
1253 * "When VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT lines
1254 * are being rasterized, sample locations may all be
1255 * treated as being at the pixel center (this may
1256 * affect attribute and depth interpolation)."
1258 ms
->num_samples
= 1;
1262 if (ms
->num_samples
> 1) {
1263 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1264 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1265 uint32_t z_samples
= subpass
->depth_stencil_attachment
? subpass
->depth_sample_count
: ms
->num_samples
;
1266 unsigned log_samples
= util_logbase2(ms
->num_samples
);
1267 unsigned log_z_samples
= util_logbase2(z_samples
);
1268 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
1269 ms
->pa_sc_mode_cntl_0
|= S_028A48_MSAA_ENABLE(1);
1270 ms
->pa_sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1271 ms
->db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples
) |
1272 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
1273 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
1274 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
1275 ms
->pa_sc_aa_config
|= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
1276 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples
)) |
1277 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1278 ms
->pa_sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
1279 if (ps_iter_samples
> 1)
1280 pipeline
->graphics
.spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1283 if (vkms
&& vkms
->pSampleMask
) {
1284 mask
= vkms
->pSampleMask
[0] & 0xffff;
1287 ms
->pa_sc_aa_mask
[0] = mask
| (mask
<< 16);
1288 ms
->pa_sc_aa_mask
[1] = mask
| (mask
<< 16);
1292 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology
)
1295 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1296 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1297 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1298 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1299 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1301 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1302 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1303 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1304 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1305 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1306 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1309 unreachable("unhandled primitive type");
1314 si_translate_prim(enum VkPrimitiveTopology topology
)
1317 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1318 return V_008958_DI_PT_POINTLIST
;
1319 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1320 return V_008958_DI_PT_LINELIST
;
1321 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1322 return V_008958_DI_PT_LINESTRIP
;
1323 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1324 return V_008958_DI_PT_TRILIST
;
1325 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1326 return V_008958_DI_PT_TRISTRIP
;
1327 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1328 return V_008958_DI_PT_TRIFAN
;
1329 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1330 return V_008958_DI_PT_LINELIST_ADJ
;
1331 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1332 return V_008958_DI_PT_LINESTRIP_ADJ
;
1333 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1334 return V_008958_DI_PT_TRILIST_ADJ
;
1335 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1336 return V_008958_DI_PT_TRISTRIP_ADJ
;
1337 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1338 return V_008958_DI_PT_PATCH
;
1346 si_conv_gl_prim_to_gs_out(unsigned gl_prim
)
1349 case 0: /* GL_POINTS */
1350 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1351 case 1: /* GL_LINES */
1352 case 3: /* GL_LINE_STRIP */
1353 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1354 case 0x8E7A: /* GL_ISOLINES */
1355 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1357 case 4: /* GL_TRIANGLES */
1358 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1359 case 5: /* GL_TRIANGLE_STRIP */
1360 case 7: /* GL_QUADS */
1361 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1369 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology
)
1372 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1373 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1374 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1375 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1376 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1377 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1378 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1379 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1380 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1381 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1382 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1383 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1384 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1385 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1392 static unsigned radv_dynamic_state_mask(VkDynamicState state
)
1395 case VK_DYNAMIC_STATE_VIEWPORT
:
1396 return RADV_DYNAMIC_VIEWPORT
;
1397 case VK_DYNAMIC_STATE_SCISSOR
:
1398 return RADV_DYNAMIC_SCISSOR
;
1399 case VK_DYNAMIC_STATE_LINE_WIDTH
:
1400 return RADV_DYNAMIC_LINE_WIDTH
;
1401 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
1402 return RADV_DYNAMIC_DEPTH_BIAS
;
1403 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
1404 return RADV_DYNAMIC_BLEND_CONSTANTS
;
1405 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
1406 return RADV_DYNAMIC_DEPTH_BOUNDS
;
1407 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
1408 return RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
1409 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
1410 return RADV_DYNAMIC_STENCIL_WRITE_MASK
;
1411 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
1412 return RADV_DYNAMIC_STENCIL_REFERENCE
;
1413 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT
:
1414 return RADV_DYNAMIC_DISCARD_RECTANGLE
;
1415 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT
:
1416 return RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1417 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
1418 return RADV_DYNAMIC_LINE_STIPPLE
;
1420 unreachable("Unhandled dynamic state");
1424 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1426 uint32_t states
= RADV_DYNAMIC_ALL
;
1428 /* If rasterization is disabled we do not care about any of the dynamic states,
1429 * since they are all rasterization related only. */
1430 if (pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
1433 if (!pCreateInfo
->pRasterizationState
->depthBiasEnable
)
1434 states
&= ~RADV_DYNAMIC_DEPTH_BIAS
;
1436 if (!pCreateInfo
->pDepthStencilState
||
1437 !pCreateInfo
->pDepthStencilState
->depthBoundsTestEnable
)
1438 states
&= ~RADV_DYNAMIC_DEPTH_BOUNDS
;
1440 if (!pCreateInfo
->pDepthStencilState
||
1441 !pCreateInfo
->pDepthStencilState
->stencilTestEnable
)
1442 states
&= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK
|
1443 RADV_DYNAMIC_STENCIL_WRITE_MASK
|
1444 RADV_DYNAMIC_STENCIL_REFERENCE
);
1446 if (!vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
))
1447 states
&= ~RADV_DYNAMIC_DISCARD_RECTANGLE
;
1449 if (!pCreateInfo
->pMultisampleState
||
1450 !vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1451 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
))
1452 states
&= ~RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1454 if (!pCreateInfo
->pRasterizationState
||
1455 !vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1456 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
))
1457 states
&= ~RADV_DYNAMIC_LINE_STIPPLE
;
1459 /* TODO: blend constants & line width. */
1466 radv_pipeline_init_dynamic_state(struct radv_pipeline
*pipeline
,
1467 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1469 uint32_t needed_states
= radv_pipeline_needed_dynamic_state(pCreateInfo
);
1470 uint32_t states
= needed_states
;
1471 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1472 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1474 pipeline
->dynamic_state
= default_dynamic_state
;
1475 pipeline
->graphics
.needed_dynamic_state
= needed_states
;
1477 if (pCreateInfo
->pDynamicState
) {
1478 /* Remove all of the states that are marked as dynamic */
1479 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1480 for (uint32_t s
= 0; s
< count
; s
++)
1481 states
&= ~radv_dynamic_state_mask(pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1484 struct radv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1486 if (needed_states
& RADV_DYNAMIC_VIEWPORT
) {
1487 assert(pCreateInfo
->pViewportState
);
1489 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1490 if (states
& RADV_DYNAMIC_VIEWPORT
) {
1491 typed_memcpy(dynamic
->viewport
.viewports
,
1492 pCreateInfo
->pViewportState
->pViewports
,
1493 pCreateInfo
->pViewportState
->viewportCount
);
1497 if (needed_states
& RADV_DYNAMIC_SCISSOR
) {
1498 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1499 if (states
& RADV_DYNAMIC_SCISSOR
) {
1500 typed_memcpy(dynamic
->scissor
.scissors
,
1501 pCreateInfo
->pViewportState
->pScissors
,
1502 pCreateInfo
->pViewportState
->scissorCount
);
1506 if (states
& RADV_DYNAMIC_LINE_WIDTH
) {
1507 assert(pCreateInfo
->pRasterizationState
);
1508 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1511 if (states
& RADV_DYNAMIC_DEPTH_BIAS
) {
1512 assert(pCreateInfo
->pRasterizationState
);
1513 dynamic
->depth_bias
.bias
=
1514 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1515 dynamic
->depth_bias
.clamp
=
1516 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1517 dynamic
->depth_bias
.slope
=
1518 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1521 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1523 * pColorBlendState is [...] NULL if the pipeline has rasterization
1524 * disabled or if the subpass of the render pass the pipeline is
1525 * created against does not use any color attachments.
1527 if (subpass
->has_color_att
&& states
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
1528 assert(pCreateInfo
->pColorBlendState
);
1529 typed_memcpy(dynamic
->blend_constants
,
1530 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1533 /* If there is no depthstencil attachment, then don't read
1534 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1535 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1536 * no need to override the depthstencil defaults in
1537 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1539 * Section 9.2 of the Vulkan 1.0.15 spec says:
1541 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1542 * disabled or if the subpass of the render pass the pipeline is created
1543 * against does not use a depth/stencil attachment.
1545 if (needed_states
&& subpass
->depth_stencil_attachment
) {
1546 assert(pCreateInfo
->pDepthStencilState
);
1548 if (states
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
1549 dynamic
->depth_bounds
.min
=
1550 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1551 dynamic
->depth_bounds
.max
=
1552 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1555 if (states
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
1556 dynamic
->stencil_compare_mask
.front
=
1557 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1558 dynamic
->stencil_compare_mask
.back
=
1559 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1562 if (states
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
1563 dynamic
->stencil_write_mask
.front
=
1564 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1565 dynamic
->stencil_write_mask
.back
=
1566 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1569 if (states
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
1570 dynamic
->stencil_reference
.front
=
1571 pCreateInfo
->pDepthStencilState
->front
.reference
;
1572 dynamic
->stencil_reference
.back
=
1573 pCreateInfo
->pDepthStencilState
->back
.reference
;
1577 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
1578 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
1579 if (needed_states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1580 dynamic
->discard_rectangle
.count
= discard_rectangle_info
->discardRectangleCount
;
1581 if (states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1582 typed_memcpy(dynamic
->discard_rectangle
.rectangles
,
1583 discard_rectangle_info
->pDiscardRectangles
,
1584 discard_rectangle_info
->discardRectangleCount
);
1588 if (needed_states
& RADV_DYNAMIC_SAMPLE_LOCATIONS
) {
1589 const VkPipelineSampleLocationsStateCreateInfoEXT
*sample_location_info
=
1590 vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1591 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
);
1592 /* If sampleLocationsEnable is VK_FALSE, the default sample
1593 * locations are used and the values specified in
1594 * sampleLocationsInfo are ignored.
1596 if (sample_location_info
->sampleLocationsEnable
) {
1597 const VkSampleLocationsInfoEXT
*pSampleLocationsInfo
=
1598 &sample_location_info
->sampleLocationsInfo
;
1600 assert(pSampleLocationsInfo
->sampleLocationsCount
<= MAX_SAMPLE_LOCATIONS
);
1602 dynamic
->sample_location
.per_pixel
= pSampleLocationsInfo
->sampleLocationsPerPixel
;
1603 dynamic
->sample_location
.grid_size
= pSampleLocationsInfo
->sampleLocationGridSize
;
1604 dynamic
->sample_location
.count
= pSampleLocationsInfo
->sampleLocationsCount
;
1605 typed_memcpy(&dynamic
->sample_location
.locations
[0],
1606 pSampleLocationsInfo
->pSampleLocations
,
1607 pSampleLocationsInfo
->sampleLocationsCount
);
1611 const VkPipelineRasterizationLineStateCreateInfoEXT
*rast_line_info
=
1612 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1613 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1614 if (needed_states
& RADV_DYNAMIC_LINE_STIPPLE
) {
1615 dynamic
->line_stipple
.factor
= rast_line_info
->lineStippleFactor
;
1616 dynamic
->line_stipple
.pattern
= rast_line_info
->lineStipplePattern
;
1619 pipeline
->dynamic_state
.mask
= states
;
1623 gfx9_get_gs_info(const struct radv_pipeline_key
*key
,
1624 const struct radv_pipeline
*pipeline
,
1626 struct radv_shader_info
*infos
,
1627 struct gfx9_gs_info
*out
)
1629 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1630 struct radv_es_output_info
*es_info
;
1631 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1632 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1634 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ?
1635 &infos
[MESA_SHADER_TESS_EVAL
].tes
.es_info
:
1636 &infos
[MESA_SHADER_VERTEX
].vs
.es_info
;
1638 unsigned gs_num_invocations
= MAX2(gs_info
->gs
.invocations
, 1);
1639 bool uses_adjacency
;
1640 switch(key
->topology
) {
1641 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1642 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1643 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1644 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1645 uses_adjacency
= true;
1648 uses_adjacency
= false;
1652 /* All these are in dwords: */
1653 /* We can't allow using the whole LDS, because GS waves compete with
1654 * other shader stages for LDS space. */
1655 const unsigned max_lds_size
= 8 * 1024;
1656 const unsigned esgs_itemsize
= es_info
->esgs_itemsize
/ 4;
1657 unsigned esgs_lds_size
;
1659 /* All these are per subgroup: */
1660 const unsigned max_out_prims
= 32 * 1024;
1661 const unsigned max_es_verts
= 255;
1662 const unsigned ideal_gs_prims
= 64;
1663 unsigned max_gs_prims
, gs_prims
;
1664 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
1666 if (uses_adjacency
|| gs_num_invocations
> 1)
1667 max_gs_prims
= 127 / gs_num_invocations
;
1671 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1672 * Make sure we don't go over the maximum value.
1674 if (gs_info
->gs
.vertices_out
> 0) {
1675 max_gs_prims
= MIN2(max_gs_prims
,
1677 (gs_info
->gs
.vertices_out
* gs_num_invocations
));
1679 assert(max_gs_prims
> 0);
1681 /* If the primitive has adjacency, halve the number of vertices
1682 * that will be reused in multiple primitives.
1684 min_es_verts
= gs_info
->gs
.vertices_in
/ (uses_adjacency
? 2 : 1);
1686 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
1687 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
1689 /* Compute ESGS LDS size based on the worst case number of ES vertices
1690 * needed to create the target number of GS prims per subgroup.
1692 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1694 /* If total LDS usage is too big, refactor partitions based on ratio
1695 * of ESGS item sizes.
1697 if (esgs_lds_size
> max_lds_size
) {
1698 /* Our target GS Prims Per Subgroup was too large. Calculate
1699 * the maximum number of GS Prims Per Subgroup that will fit
1700 * into LDS, capped by the maximum that the hardware can support.
1702 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
1704 assert(gs_prims
> 0);
1705 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
1708 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1709 assert(esgs_lds_size
<= max_lds_size
);
1712 /* Now calculate remaining ESGS information. */
1714 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
1716 es_verts
= max_es_verts
;
1718 /* Vertices for adjacency primitives are not always reused, so restore
1719 * it for ES_VERTS_PER_SUBGRP.
1721 min_es_verts
= gs_info
->gs
.vertices_in
;
1723 /* For normal primitives, the VGT only checks if they are past the ES
1724 * verts per subgroup after allocating a full GS primitive and if they
1725 * are, kick off a new subgroup. But if those additional ES verts are
1726 * unique (e.g. not reused) we need to make sure there is enough LDS
1727 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1729 es_verts
-= min_es_verts
- 1;
1731 uint32_t es_verts_per_subgroup
= es_verts
;
1732 uint32_t gs_prims_per_subgroup
= gs_prims
;
1733 uint32_t gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
1734 uint32_t max_prims_per_subgroup
= gs_inst_prims_in_subgroup
* gs_info
->gs
.vertices_out
;
1735 out
->lds_size
= align(esgs_lds_size
, 128) / 128;
1736 out
->vgt_gs_onchip_cntl
= S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup
) |
1737 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup
) |
1738 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup
);
1739 out
->vgt_gs_max_prims_per_subgroup
= S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup
);
1740 out
->vgt_esgs_ring_itemsize
= esgs_itemsize
;
1741 assert(max_prims_per_subgroup
<= max_out_prims
);
1744 static void clamp_gsprims_to_esverts(unsigned *max_gsprims
, unsigned max_esverts
,
1745 unsigned min_verts_per_prim
, bool use_adjacency
)
1747 unsigned max_reuse
= max_esverts
- min_verts_per_prim
;
1750 *max_gsprims
= MIN2(*max_gsprims
, 1 + max_reuse
);
1754 radv_get_num_input_vertices(nir_shader
**nir
)
1756 if (nir
[MESA_SHADER_GEOMETRY
]) {
1757 nir_shader
*gs
= nir
[MESA_SHADER_GEOMETRY
];
1759 return gs
->info
.gs
.vertices_in
;
1762 if (nir
[MESA_SHADER_TESS_CTRL
]) {
1763 nir_shader
*tes
= nir
[MESA_SHADER_TESS_EVAL
];
1765 if (tes
->info
.tess
.point_mode
)
1767 if (tes
->info
.tess
.primitive_mode
== GL_ISOLINES
)
1776 gfx10_get_ngg_info(const struct radv_pipeline_key
*key
,
1777 struct radv_pipeline
*pipeline
,
1779 struct radv_shader_info
*infos
,
1780 struct gfx10_ngg_info
*ngg
)
1782 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1783 struct radv_es_output_info
*es_info
=
1784 nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1785 unsigned gs_type
= nir
[MESA_SHADER_GEOMETRY
] ? MESA_SHADER_GEOMETRY
: MESA_SHADER_VERTEX
;
1786 unsigned max_verts_per_prim
= radv_get_num_input_vertices(nir
);
1787 unsigned min_verts_per_prim
=
1788 gs_type
== MESA_SHADER_GEOMETRY
? max_verts_per_prim
: 1;
1789 unsigned gs_num_invocations
= nir
[MESA_SHADER_GEOMETRY
] ? MAX2(gs_info
->gs
.invocations
, 1) : 1;
1790 bool uses_adjacency
;
1791 switch(key
->topology
) {
1792 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1793 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1794 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1795 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1796 uses_adjacency
= true;
1799 uses_adjacency
= false;
1803 /* All these are in dwords: */
1804 /* We can't allow using the whole LDS, because GS waves compete with
1805 * other shader stages for LDS space.
1807 * TODO: We should really take the shader's internal LDS use into
1808 * account. The linker will fail if the size is greater than
1811 const unsigned max_lds_size
= 8 * 1024 - 768;
1812 const unsigned target_lds_size
= max_lds_size
;
1813 unsigned esvert_lds_size
= 0;
1814 unsigned gsprim_lds_size
= 0;
1816 /* All these are per subgroup: */
1817 bool max_vert_out_per_gs_instance
= false;
1818 unsigned max_esverts_base
= 256;
1819 unsigned max_gsprims_base
= 128; /* default prim group size clamp */
1821 /* Hardware has the following non-natural restrictions on the value
1822 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1824 * - at most 252 for any line input primitive type
1825 * - at most 251 for any quad input primitive type
1826 * - at most 251 for triangle strips with adjacency (this happens to
1827 * be the natural limit for triangle *lists* with adjacency)
1829 max_esverts_base
= MIN2(max_esverts_base
, 251 + max_verts_per_prim
- 1);
1831 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1832 unsigned max_out_verts_per_gsprim
=
1833 gs_info
->gs
.vertices_out
* gs_num_invocations
;
1835 if (max_out_verts_per_gsprim
<= 256) {
1836 if (max_out_verts_per_gsprim
) {
1837 max_gsprims_base
= MIN2(max_gsprims_base
,
1838 256 / max_out_verts_per_gsprim
);
1841 /* Use special multi-cycling mode in which each GS
1842 * instance gets its own subgroup. Does not work with
1844 max_vert_out_per_gs_instance
= true;
1845 max_gsprims_base
= 1;
1846 max_out_verts_per_gsprim
= gs_info
->gs
.vertices_out
;
1849 esvert_lds_size
= es_info
->esgs_itemsize
/ 4;
1850 gsprim_lds_size
= (gs_info
->gs
.gsvs_vertex_size
/ 4 + 1) * max_out_verts_per_gsprim
;
1853 /* LDS size for passing data from GS to ES. */
1854 struct radv_streamout_info
*so_info
= nir
[MESA_SHADER_TESS_CTRL
]
1855 ? &infos
[MESA_SHADER_TESS_EVAL
].so
1856 : &infos
[MESA_SHADER_VERTEX
].so
;
1858 if (so_info
->num_outputs
)
1859 esvert_lds_size
= 4 * so_info
->num_outputs
+ 1;
1861 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1862 * corresponding to the ES thread of the provoking vertex. All
1863 * ES threads load and export PrimitiveID for their thread.
1865 if (!nir
[MESA_SHADER_TESS_CTRL
] &&
1866 infos
[MESA_SHADER_VERTEX
].vs
.outinfo
.export_prim_id
)
1867 esvert_lds_size
= MAX2(esvert_lds_size
, 1);
1870 unsigned max_gsprims
= max_gsprims_base
;
1871 unsigned max_esverts
= max_esverts_base
;
1873 if (esvert_lds_size
)
1874 max_esverts
= MIN2(max_esverts
, target_lds_size
/ esvert_lds_size
);
1875 if (gsprim_lds_size
)
1876 max_gsprims
= MIN2(max_gsprims
, target_lds_size
/ gsprim_lds_size
);
1878 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1879 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
, min_verts_per_prim
, uses_adjacency
);
1880 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1882 if (esvert_lds_size
|| gsprim_lds_size
) {
1883 /* Now that we have a rough proportionality between esverts
1884 * and gsprims based on the primitive type, scale both of them
1885 * down simultaneously based on required LDS space.
1887 * We could be smarter about this if we knew how much vertex
1890 unsigned lds_total
= max_esverts
* esvert_lds_size
+
1891 max_gsprims
* gsprim_lds_size
;
1892 if (lds_total
> target_lds_size
) {
1893 max_esverts
= max_esverts
* target_lds_size
/ lds_total
;
1894 max_gsprims
= max_gsprims
* target_lds_size
/ lds_total
;
1896 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1897 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1898 min_verts_per_prim
, uses_adjacency
);
1899 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1903 /* Round up towards full wave sizes for better ALU utilization. */
1904 if (!max_vert_out_per_gs_instance
) {
1905 unsigned orig_max_esverts
;
1906 unsigned orig_max_gsprims
;
1909 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1910 wavesize
= gs_info
->wave_size
;
1912 wavesize
= nir
[MESA_SHADER_TESS_CTRL
]
1913 ? infos
[MESA_SHADER_TESS_EVAL
].wave_size
1914 : infos
[MESA_SHADER_VERTEX
].wave_size
;
1918 orig_max_esverts
= max_esverts
;
1919 orig_max_gsprims
= max_gsprims
;
1921 max_esverts
= align(max_esverts
, wavesize
);
1922 max_esverts
= MIN2(max_esverts
, max_esverts_base
);
1923 if (esvert_lds_size
)
1924 max_esverts
= MIN2(max_esverts
,
1925 (max_lds_size
- max_gsprims
* gsprim_lds_size
) /
1927 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1929 max_gsprims
= align(max_gsprims
, wavesize
);
1930 max_gsprims
= MIN2(max_gsprims
, max_gsprims_base
);
1931 if (gsprim_lds_size
)
1932 max_gsprims
= MIN2(max_gsprims
,
1933 (max_lds_size
- max_esverts
* esvert_lds_size
) /
1935 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1936 min_verts_per_prim
, uses_adjacency
);
1937 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1938 } while (orig_max_esverts
!= max_esverts
|| orig_max_gsprims
!= max_gsprims
);
1941 /* Hardware restriction: minimum value of max_esverts */
1942 max_esverts
= MAX2(max_esverts
, 23 + max_verts_per_prim
);
1944 unsigned max_out_vertices
=
1945 max_vert_out_per_gs_instance
? gs_info
->gs
.vertices_out
:
1946 gs_type
== MESA_SHADER_GEOMETRY
?
1947 max_gsprims
* gs_num_invocations
* gs_info
->gs
.vertices_out
:
1949 assert(max_out_vertices
<= 256);
1951 unsigned prim_amp_factor
= 1;
1952 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1953 /* Number of output primitives per GS input primitive after
1955 prim_amp_factor
= gs_info
->gs
.vertices_out
;
1958 /* The GE only checks against the maximum number of ES verts after
1959 * allocating a full GS primitive. So we need to ensure that whenever
1960 * this check passes, there is enough space for a full primitive without
1963 ngg
->hw_max_esverts
= max_esverts
- max_verts_per_prim
+ 1;
1964 ngg
->max_gsprims
= max_gsprims
;
1965 ngg
->max_out_verts
= max_out_vertices
;
1966 ngg
->prim_amp_factor
= prim_amp_factor
;
1967 ngg
->max_vert_out_per_gs_instance
= max_vert_out_per_gs_instance
;
1968 ngg
->ngg_emit_size
= max_gsprims
* gsprim_lds_size
;
1969 ngg
->esgs_ring_size
= 4 * max_esverts
* esvert_lds_size
;
1971 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1972 ngg
->vgt_esgs_ring_itemsize
= es_info
->esgs_itemsize
/ 4;
1974 ngg
->vgt_esgs_ring_itemsize
= 1;
1977 pipeline
->graphics
.esgs_ring_size
= ngg
->esgs_ring_size
;
1979 assert(ngg
->hw_max_esverts
>= 24); /* HW limitation */
1983 calculate_gs_ring_sizes(struct radv_pipeline
*pipeline
,
1984 const struct gfx9_gs_info
*gs
)
1986 struct radv_device
*device
= pipeline
->device
;
1987 unsigned num_se
= device
->physical_device
->rad_info
.max_se
;
1988 unsigned wave_size
= 64;
1989 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
1990 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1991 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1993 unsigned gs_vertex_reuse
=
1994 (device
->physical_device
->rad_info
.chip_class
>= GFX8
? 32 : 16) * num_se
;
1995 unsigned alignment
= 256 * num_se
;
1996 /* The maximum size is 63.999 MB per SE. */
1997 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
1998 struct radv_shader_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
2000 /* Calculate the minimum size. */
2001 unsigned min_esgs_ring_size
= align(gs
->vgt_esgs_ring_itemsize
* 4 * gs_vertex_reuse
*
2002 wave_size
, alignment
);
2003 /* These are recommended sizes, not minimum sizes. */
2004 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
2005 gs
->vgt_esgs_ring_itemsize
* 4 * gs_info
->gs
.vertices_in
;
2006 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
2007 gs_info
->gs
.max_gsvs_emit_size
;
2009 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
2010 esgs_ring_size
= align(esgs_ring_size
, alignment
);
2011 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
2013 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
2014 pipeline
->graphics
.esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
2016 pipeline
->graphics
.gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
2019 static void si_multiwave_lds_size_workaround(struct radv_device
*device
,
2022 /* If tessellation is all offchip and on-chip GS isn't used, this
2023 * workaround is not needed.
2027 /* SPI barrier management bug:
2028 * Make sure we have at least 4k of LDS in use to avoid the bug.
2029 * It applies to workgroup sizes of more than one wavefront.
2031 if (device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
||
2032 device
->physical_device
->rad_info
.family
== CHIP_KABINI
)
2033 *lds_size
= MAX2(*lds_size
, 8);
2036 struct radv_shader_variant
*
2037 radv_get_shader(struct radv_pipeline
*pipeline
,
2038 gl_shader_stage stage
)
2040 if (stage
== MESA_SHADER_VERTEX
) {
2041 if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
2042 return pipeline
->shaders
[MESA_SHADER_VERTEX
];
2043 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
])
2044 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
2045 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
2046 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
2047 } else if (stage
== MESA_SHADER_TESS_EVAL
) {
2048 if (!radv_pipeline_has_tess(pipeline
))
2050 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
2051 return pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
2052 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
2053 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
2055 return pipeline
->shaders
[stage
];
2058 static struct radv_tessellation_state
2059 calculate_tess_state(struct radv_pipeline
*pipeline
,
2060 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
2062 unsigned num_tcs_input_cp
;
2063 unsigned num_tcs_output_cp
;
2065 unsigned num_patches
;
2066 struct radv_tessellation_state tess
= {0};
2068 num_tcs_input_cp
= pCreateInfo
->pTessellationState
->patchControlPoints
;
2069 num_tcs_output_cp
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.tcs_vertices_out
; //TCS VERTICES OUT
2070 num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2072 lds_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.lds_size
;
2074 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2075 assert(lds_size
<= 65536);
2076 lds_size
= align(lds_size
, 512) / 512;
2078 assert(lds_size
<= 32768);
2079 lds_size
= align(lds_size
, 256) / 256;
2081 si_multiwave_lds_size_workaround(pipeline
->device
, &lds_size
);
2083 tess
.lds_size
= lds_size
;
2085 tess
.ls_hs_config
= S_028B58_NUM_PATCHES(num_patches
) |
2086 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
2087 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
2088 tess
.num_patches
= num_patches
;
2090 struct radv_shader_variant
*tes
= radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
);
2091 unsigned type
= 0, partitioning
= 0, topology
= 0, distribution_mode
= 0;
2093 switch (tes
->info
.tes
.primitive_mode
) {
2095 type
= V_028B6C_TESS_TRIANGLE
;
2098 type
= V_028B6C_TESS_QUAD
;
2101 type
= V_028B6C_TESS_ISOLINE
;
2105 switch (tes
->info
.tes
.spacing
) {
2106 case TESS_SPACING_EQUAL
:
2107 partitioning
= V_028B6C_PART_INTEGER
;
2109 case TESS_SPACING_FRACTIONAL_ODD
:
2110 partitioning
= V_028B6C_PART_FRAC_ODD
;
2112 case TESS_SPACING_FRACTIONAL_EVEN
:
2113 partitioning
= V_028B6C_PART_FRAC_EVEN
;
2119 bool ccw
= tes
->info
.tes
.ccw
;
2120 const VkPipelineTessellationDomainOriginStateCreateInfo
*domain_origin_state
=
2121 vk_find_struct_const(pCreateInfo
->pTessellationState
,
2122 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO
);
2124 if (domain_origin_state
&& domain_origin_state
->domainOrigin
!= VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT
)
2127 if (tes
->info
.tes
.point_mode
)
2128 topology
= V_028B6C_OUTPUT_POINT
;
2129 else if (tes
->info
.tes
.primitive_mode
== GL_ISOLINES
)
2130 topology
= V_028B6C_OUTPUT_LINE
;
2132 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
2134 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
2136 if (pipeline
->device
->physical_device
->rad_info
.has_distributed_tess
) {
2137 if (pipeline
->device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
2138 pipeline
->device
->physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
2139 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
2141 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
2143 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
2145 tess
.tf_param
= S_028B6C_TYPE(type
) |
2146 S_028B6C_PARTITIONING(partitioning
) |
2147 S_028B6C_TOPOLOGY(topology
) |
2148 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
2153 static const struct radv_prim_vertex_count prim_size_table
[] = {
2154 [V_008958_DI_PT_NONE
] = {0, 0},
2155 [V_008958_DI_PT_POINTLIST
] = {1, 1},
2156 [V_008958_DI_PT_LINELIST
] = {2, 2},
2157 [V_008958_DI_PT_LINESTRIP
] = {2, 1},
2158 [V_008958_DI_PT_TRILIST
] = {3, 3},
2159 [V_008958_DI_PT_TRIFAN
] = {3, 1},
2160 [V_008958_DI_PT_TRISTRIP
] = {3, 1},
2161 [V_008958_DI_PT_LINELIST_ADJ
] = {4, 4},
2162 [V_008958_DI_PT_LINESTRIP_ADJ
] = {4, 1},
2163 [V_008958_DI_PT_TRILIST_ADJ
] = {6, 6},
2164 [V_008958_DI_PT_TRISTRIP_ADJ
] = {6, 2},
2165 [V_008958_DI_PT_RECTLIST
] = {3, 3},
2166 [V_008958_DI_PT_LINELOOP
] = {2, 1},
2167 [V_008958_DI_PT_POLYGON
] = {3, 1},
2168 [V_008958_DI_PT_2D_TRI_STRIP
] = {0, 0},
2171 static const struct radv_vs_output_info
*get_vs_output_info(const struct radv_pipeline
*pipeline
)
2173 if (radv_pipeline_has_gs(pipeline
))
2174 if (radv_pipeline_has_ngg(pipeline
))
2175 return &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.vs
.outinfo
;
2177 return &pipeline
->gs_copy_shader
->info
.vs
.outinfo
;
2178 else if (radv_pipeline_has_tess(pipeline
))
2179 return &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.outinfo
;
2181 return &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.outinfo
;
2185 radv_link_shaders(struct radv_pipeline
*pipeline
, nir_shader
**shaders
)
2187 nir_shader
* ordered_shaders
[MESA_SHADER_STAGES
];
2188 int shader_count
= 0;
2190 if(shaders
[MESA_SHADER_FRAGMENT
]) {
2191 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_FRAGMENT
];
2193 if(shaders
[MESA_SHADER_GEOMETRY
]) {
2194 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_GEOMETRY
];
2196 if(shaders
[MESA_SHADER_TESS_EVAL
]) {
2197 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_EVAL
];
2199 if(shaders
[MESA_SHADER_TESS_CTRL
]) {
2200 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_CTRL
];
2202 if(shaders
[MESA_SHADER_VERTEX
]) {
2203 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_VERTEX
];
2206 if (shader_count
> 1) {
2207 unsigned first
= ordered_shaders
[shader_count
- 1]->info
.stage
;
2208 unsigned last
= ordered_shaders
[0]->info
.stage
;
2210 if (ordered_shaders
[0]->info
.stage
== MESA_SHADER_FRAGMENT
&&
2211 ordered_shaders
[1]->info
.has_transform_feedback_varyings
)
2212 nir_link_xfb_varyings(ordered_shaders
[1], ordered_shaders
[0]);
2214 for (int i
= 0; i
< shader_count
; ++i
) {
2215 nir_variable_mode mask
= 0;
2217 if (ordered_shaders
[i
]->info
.stage
!= first
)
2218 mask
= mask
| nir_var_shader_in
;
2220 if (ordered_shaders
[i
]->info
.stage
!= last
)
2221 mask
= mask
| nir_var_shader_out
;
2223 nir_lower_io_to_scalar_early(ordered_shaders
[i
], mask
);
2224 radv_optimize_nir(ordered_shaders
[i
], false, false);
2228 for (int i
= 1; i
< shader_count
; ++i
) {
2229 nir_lower_io_arrays_to_elements(ordered_shaders
[i
],
2230 ordered_shaders
[i
- 1]);
2232 if (nir_link_opt_varyings(ordered_shaders
[i
],
2233 ordered_shaders
[i
- 1]))
2234 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2236 nir_remove_dead_variables(ordered_shaders
[i
],
2237 nir_var_shader_out
);
2238 nir_remove_dead_variables(ordered_shaders
[i
- 1],
2241 bool progress
= nir_remove_unused_varyings(ordered_shaders
[i
],
2242 ordered_shaders
[i
- 1]);
2244 nir_compact_varyings(ordered_shaders
[i
],
2245 ordered_shaders
[i
- 1], true);
2248 if (nir_lower_global_vars_to_local(ordered_shaders
[i
])) {
2249 ac_lower_indirect_derefs(ordered_shaders
[i
],
2250 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2252 radv_optimize_nir(ordered_shaders
[i
], false, false);
2254 if (nir_lower_global_vars_to_local(ordered_shaders
[i
- 1])) {
2255 ac_lower_indirect_derefs(ordered_shaders
[i
- 1],
2256 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2258 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2264 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo
*input_state
,
2265 uint32_t attrib_binding
)
2267 for (uint32_t i
= 0; i
< input_state
->vertexBindingDescriptionCount
; i
++) {
2268 const VkVertexInputBindingDescription
*input_binding
=
2269 &input_state
->pVertexBindingDescriptions
[i
];
2271 if (input_binding
->binding
== attrib_binding
)
2272 return input_binding
->stride
;
2278 static struct radv_pipeline_key
2279 radv_generate_graphics_pipeline_key(struct radv_pipeline
*pipeline
,
2280 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2281 const struct radv_blend_state
*blend
,
2282 bool has_view_index
)
2284 const VkPipelineVertexInputStateCreateInfo
*input_state
=
2285 pCreateInfo
->pVertexInputState
;
2286 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*divisor_state
=
2287 vk_find_struct_const(input_state
->pNext
, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
2289 struct radv_pipeline_key key
;
2290 memset(&key
, 0, sizeof(key
));
2292 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
2293 key
.optimisations_disabled
= 1;
2295 key
.has_multiview_view_index
= has_view_index
;
2297 uint32_t binding_input_rate
= 0;
2298 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
2299 for (unsigned i
= 0; i
< input_state
->vertexBindingDescriptionCount
; ++i
) {
2300 if (input_state
->pVertexBindingDescriptions
[i
].inputRate
) {
2301 unsigned binding
= input_state
->pVertexBindingDescriptions
[i
].binding
;
2302 binding_input_rate
|= 1u << binding
;
2303 instance_rate_divisors
[binding
] = 1;
2306 if (divisor_state
) {
2307 for (unsigned i
= 0; i
< divisor_state
->vertexBindingDivisorCount
; ++i
) {
2308 instance_rate_divisors
[divisor_state
->pVertexBindingDivisors
[i
].binding
] =
2309 divisor_state
->pVertexBindingDivisors
[i
].divisor
;
2313 for (unsigned i
= 0; i
< input_state
->vertexAttributeDescriptionCount
; ++i
) {
2314 const VkVertexInputAttributeDescription
*desc
=
2315 &input_state
->pVertexAttributeDescriptions
[i
];
2316 const struct vk_format_description
*format_desc
;
2317 unsigned location
= desc
->location
;
2318 unsigned binding
= desc
->binding
;
2319 unsigned num_format
, data_format
;
2322 if (binding_input_rate
& (1u << binding
)) {
2323 key
.instance_rate_inputs
|= 1u << location
;
2324 key
.instance_rate_divisors
[location
] = instance_rate_divisors
[binding
];
2327 format_desc
= vk_format_description(desc
->format
);
2328 first_non_void
= vk_format_get_first_non_void_channel(desc
->format
);
2330 num_format
= radv_translate_buffer_numformat(format_desc
, first_non_void
);
2331 data_format
= radv_translate_buffer_dataformat(format_desc
, first_non_void
);
2333 key
.vertex_attribute_formats
[location
] = data_format
| (num_format
<< 4);
2334 key
.vertex_attribute_bindings
[location
] = desc
->binding
;
2335 key
.vertex_attribute_offsets
[location
] = desc
->offset
;
2336 key
.vertex_attribute_strides
[location
] = radv_get_attrib_stride(input_state
, desc
->binding
);
2338 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
&&
2339 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_STONEY
) {
2340 VkFormat format
= input_state
->pVertexAttributeDescriptions
[i
].format
;
2343 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2344 case VK_FORMAT_A2B10G10R10_SNORM_PACK32
:
2345 adjust
= RADV_ALPHA_ADJUST_SNORM
;
2347 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2348 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32
:
2349 adjust
= RADV_ALPHA_ADJUST_SSCALED
;
2351 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2352 case VK_FORMAT_A2B10G10R10_SINT_PACK32
:
2353 adjust
= RADV_ALPHA_ADJUST_SINT
;
2359 key
.vertex_alpha_adjust
|= adjust
<< (2 * location
);
2362 switch (desc
->format
) {
2363 case VK_FORMAT_B8G8R8A8_UNORM
:
2364 case VK_FORMAT_B8G8R8A8_SNORM
:
2365 case VK_FORMAT_B8G8R8A8_USCALED
:
2366 case VK_FORMAT_B8G8R8A8_SSCALED
:
2367 case VK_FORMAT_B8G8R8A8_UINT
:
2368 case VK_FORMAT_B8G8R8A8_SINT
:
2369 case VK_FORMAT_B8G8R8A8_SRGB
:
2370 case VK_FORMAT_A2R10G10B10_UNORM_PACK32
:
2371 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2372 case VK_FORMAT_A2R10G10B10_USCALED_PACK32
:
2373 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2374 case VK_FORMAT_A2R10G10B10_UINT_PACK32
:
2375 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2376 key
.vertex_post_shuffle
|= 1 << location
;
2383 const VkPipelineTessellationStateCreateInfo
*tess
=
2384 radv_pipeline_get_tessellation_state(pCreateInfo
);
2386 key
.tess_input_vertices
= tess
->patchControlPoints
;
2388 const VkPipelineMultisampleStateCreateInfo
*vkms
=
2389 radv_pipeline_get_multisample_state(pCreateInfo
);
2390 if (vkms
&& vkms
->rasterizationSamples
> 1) {
2391 uint32_t num_samples
= vkms
->rasterizationSamples
;
2392 uint32_t ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
);
2393 key
.num_samples
= num_samples
;
2394 key
.log2_ps_iter_samples
= util_logbase2(ps_iter_samples
);
2397 key
.col_format
= blend
->spi_shader_col_format
;
2398 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX8
)
2399 radv_pipeline_compute_get_int_clamp(pCreateInfo
, &key
.is_int8
, &key
.is_int10
);
2401 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
2402 key
.topology
= pCreateInfo
->pInputAssemblyState
->topology
;
2408 radv_nir_stage_uses_xfb(const nir_shader
*nir
)
2410 nir_xfb_info
*xfb
= nir_gather_xfb_info(nir
, NULL
);
2411 bool uses_xfb
= !!xfb
;
2418 radv_fill_shader_keys(struct radv_device
*device
,
2419 struct radv_shader_variant_key
*keys
,
2420 const struct radv_pipeline_key
*key
,
2423 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_inputs
= key
->instance_rate_inputs
;
2424 keys
[MESA_SHADER_VERTEX
].vs
.alpha_adjust
= key
->vertex_alpha_adjust
;
2425 keys
[MESA_SHADER_VERTEX
].vs
.post_shuffle
= key
->vertex_post_shuffle
;
2426 for (unsigned i
= 0; i
< MAX_VERTEX_ATTRIBS
; ++i
) {
2427 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_divisors
[i
] = key
->instance_rate_divisors
[i
];
2428 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_formats
[i
] = key
->vertex_attribute_formats
[i
];
2429 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_bindings
[i
] = key
->vertex_attribute_bindings
[i
];
2430 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_offsets
[i
] = key
->vertex_attribute_offsets
[i
];
2431 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_strides
[i
] = key
->vertex_attribute_strides
[i
];
2433 keys
[MESA_SHADER_VERTEX
].vs
.outprim
= si_conv_prim_to_gs_out(key
->topology
);
2435 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2436 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ls
= true;
2437 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= 0;
2438 keys
[MESA_SHADER_TESS_CTRL
].tcs
.input_vertices
= key
->tess_input_vertices
;
2439 keys
[MESA_SHADER_TESS_CTRL
].tcs
.primitive_mode
= nir
[MESA_SHADER_TESS_EVAL
]->info
.tess
.primitive_mode
;
2441 keys
[MESA_SHADER_TESS_CTRL
].tcs
.tes_reads_tess_factors
= !!(nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
& (VARYING_BIT_TESS_LEVEL_INNER
| VARYING_BIT_TESS_LEVEL_OUTER
));
2444 if (nir
[MESA_SHADER_GEOMETRY
]) {
2445 if (nir
[MESA_SHADER_TESS_CTRL
])
2446 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_es
= true;
2448 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_es
= true;
2451 if (device
->physical_device
->use_ngg
) {
2452 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2453 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= true;
2455 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= true;
2458 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2459 nir
[MESA_SHADER_GEOMETRY
] &&
2460 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.invocations
*
2461 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.vertices_out
> 256) {
2462 /* Fallback to the legacy path if tessellation is
2463 * enabled with extreme geometry because
2464 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2467 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2470 gl_shader_stage last_xfb_stage
= MESA_SHADER_VERTEX
;
2472 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2477 bool uses_xfb
= nir
[last_xfb_stage
] &&
2478 radv_nir_stage_uses_xfb(nir
[last_xfb_stage
]);
2480 if (!device
->physical_device
->use_ngg_streamout
&& uses_xfb
) {
2481 if (nir
[MESA_SHADER_TESS_CTRL
])
2482 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2484 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2487 /* Determine if the pipeline is eligible for the NGG passthrough
2488 * mode. It can't be enabled for geometry shaders, for NGG
2489 * streamout or for vertex shaders that export the primitive ID
2490 * (this is checked later because we don't have the info here.)
2492 if (!nir
[MESA_SHADER_GEOMETRY
] && !uses_xfb
) {
2493 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2494 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
) {
2495 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg_passthrough
= true;
2496 } else if (nir
[MESA_SHADER_VERTEX
] &&
2497 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) {
2498 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg_passthrough
= true;
2503 for(int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
2504 keys
[i
].has_multiview_view_index
= key
->has_multiview_view_index
;
2506 keys
[MESA_SHADER_FRAGMENT
].fs
.col_format
= key
->col_format
;
2507 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int8
= key
->is_int8
;
2508 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int10
= key
->is_int10
;
2509 keys
[MESA_SHADER_FRAGMENT
].fs
.log2_ps_iter_samples
= key
->log2_ps_iter_samples
;
2510 keys
[MESA_SHADER_FRAGMENT
].fs
.num_samples
= key
->num_samples
;
2512 if (nir
[MESA_SHADER_COMPUTE
]) {
2513 keys
[MESA_SHADER_COMPUTE
].cs
.subgroup_size
= key
->compute_subgroup_size
;
2518 radv_get_wave_size(struct radv_device
*device
,
2519 const VkPipelineShaderStageCreateInfo
*pStage
,
2520 gl_shader_stage stage
,
2521 const struct radv_shader_variant_key
*key
)
2523 if (stage
== MESA_SHADER_GEOMETRY
&& !key
->vs_common_out
.as_ngg
)
2525 else if (stage
== MESA_SHADER_COMPUTE
) {
2526 if (key
->cs
.subgroup_size
) {
2527 /* Return the required subgroup size if specified. */
2528 return key
->cs
.subgroup_size
;
2530 return device
->physical_device
->cs_wave_size
;
2532 else if (stage
== MESA_SHADER_FRAGMENT
)
2533 return device
->physical_device
->ps_wave_size
;
2535 return device
->physical_device
->ge_wave_size
;
2539 radv_fill_shader_info(struct radv_pipeline
*pipeline
,
2540 const VkPipelineShaderStageCreateInfo
**pStages
,
2541 struct radv_shader_variant_key
*keys
,
2542 struct radv_shader_info
*infos
,
2545 unsigned active_stages
= 0;
2546 unsigned filled_stages
= 0;
2548 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2550 active_stages
|= (1 << i
);
2553 if (nir
[MESA_SHADER_FRAGMENT
]) {
2554 radv_nir_shader_info_init(&infos
[MESA_SHADER_FRAGMENT
]);
2555 radv_nir_shader_info_pass(nir
[MESA_SHADER_FRAGMENT
],
2557 &keys
[MESA_SHADER_FRAGMENT
],
2558 &infos
[MESA_SHADER_FRAGMENT
]);
2560 /* TODO: These are no longer used as keys we should refactor this */
2561 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
=
2562 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2563 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_layer_id
=
2564 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2565 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_clip_dists
=
2566 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2567 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_prim_id
=
2568 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2569 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_layer_id
=
2570 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2571 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_clip_dists
=
2572 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2574 /* NGG passthrough mode can't be enabled for vertex shaders
2575 * that export the primitive ID.
2577 * TODO: I should really refactor the keys logic.
2579 if (nir
[MESA_SHADER_VERTEX
] &&
2580 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
) {
2581 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg_passthrough
= false;
2584 filled_stages
|= (1 << MESA_SHADER_FRAGMENT
);
2587 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2588 nir
[MESA_SHADER_TESS_CTRL
]) {
2589 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2590 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2591 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2593 radv_nir_shader_info_init(&infos
[MESA_SHADER_TESS_CTRL
]);
2595 for (int i
= 0; i
< 2; i
++) {
2596 radv_nir_shader_info_pass(combined_nir
[i
],
2597 pipeline
->layout
, &key
,
2598 &infos
[MESA_SHADER_TESS_CTRL
]);
2601 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2602 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2603 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2604 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2606 filled_stages
|= (1 << MESA_SHADER_VERTEX
);
2607 filled_stages
|= (1 << MESA_SHADER_TESS_CTRL
);
2610 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2611 nir
[MESA_SHADER_GEOMETRY
]) {
2612 gl_shader_stage pre_stage
= nir
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2613 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2615 radv_nir_shader_info_init(&infos
[MESA_SHADER_GEOMETRY
]);
2617 for (int i
= 0; i
< 2; i
++) {
2618 radv_nir_shader_info_pass(combined_nir
[i
],
2621 &infos
[MESA_SHADER_GEOMETRY
]);
2624 filled_stages
|= (1 << pre_stage
);
2625 filled_stages
|= (1 << MESA_SHADER_GEOMETRY
);
2628 active_stages
^= filled_stages
;
2629 while (active_stages
) {
2630 int i
= u_bit_scan(&active_stages
);
2632 if (i
== MESA_SHADER_TESS_CTRL
) {
2633 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
=
2634 util_last_bit64(infos
[MESA_SHADER_VERTEX
].vs
.ls_outputs_written
);
2637 if (i
== MESA_SHADER_TESS_EVAL
) {
2638 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2639 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2640 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2641 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2644 radv_nir_shader_info_init(&infos
[i
]);
2645 radv_nir_shader_info_pass(nir
[i
], pipeline
->layout
,
2646 &keys
[i
], &infos
[i
]);
2649 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2651 infos
[i
].wave_size
=
2652 radv_get_wave_size(pipeline
->device
, pStages
[i
],
2658 merge_tess_info(struct shader_info
*tes_info
,
2659 const struct shader_info
*tcs_info
)
2661 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2663 * "PointMode. Controls generation of points rather than triangles
2664 * or lines. This functionality defaults to disabled, and is
2665 * enabled if either shader stage includes the execution mode.
2667 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2668 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2669 * and OutputVertices, it says:
2671 * "One mode must be set in at least one of the tessellation
2674 * So, the fields can be set in either the TCS or TES, but they must
2675 * agree if set in both. Our backend looks at TES, so bitwise-or in
2676 * the values from the TCS.
2678 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
2679 tes_info
->tess
.tcs_vertices_out
== 0 ||
2680 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
2681 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
2683 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2684 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2685 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
2686 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
2688 assert(tcs_info
->tess
.primitive_mode
== 0 ||
2689 tes_info
->tess
.primitive_mode
== 0 ||
2690 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
2691 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
2692 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
2693 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
2697 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT
*ext
)
2702 if (ext
->pPipelineCreationFeedback
) {
2703 ext
->pPipelineCreationFeedback
->flags
= 0;
2704 ext
->pPipelineCreationFeedback
->duration
= 0;
2707 for (unsigned i
= 0; i
< ext
->pipelineStageCreationFeedbackCount
; ++i
) {
2708 ext
->pPipelineStageCreationFeedbacks
[i
].flags
= 0;
2709 ext
->pPipelineStageCreationFeedbacks
[i
].duration
= 0;
2714 void radv_start_feedback(VkPipelineCreationFeedbackEXT
*feedback
)
2719 feedback
->duration
-= radv_get_current_time();
2720 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
2724 void radv_stop_feedback(VkPipelineCreationFeedbackEXT
*feedback
, bool cache_hit
)
2729 feedback
->duration
+= radv_get_current_time();
2730 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
|
2731 (cache_hit
? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
: 0);
2735 bool radv_aco_supported_stage(gl_shader_stage stage
, bool has_ts
)
2737 return (stage
== MESA_SHADER_VERTEX
&& !has_ts
) ||
2738 (stage
== MESA_SHADER_GEOMETRY
&& !has_ts
) ||
2739 stage
== MESA_SHADER_FRAGMENT
||
2740 stage
== MESA_SHADER_COMPUTE
;
2743 void radv_create_shaders(struct radv_pipeline
*pipeline
,
2744 struct radv_device
*device
,
2745 struct radv_pipeline_cache
*cache
,
2746 const struct radv_pipeline_key
*key
,
2747 const VkPipelineShaderStageCreateInfo
**pStages
,
2748 const VkPipelineCreateFlags flags
,
2749 VkPipelineCreationFeedbackEXT
*pipeline_feedback
,
2750 VkPipelineCreationFeedbackEXT
**stage_feedbacks
)
2752 struct radv_shader_module fs_m
= {0};
2753 struct radv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
2754 nir_shader
*nir
[MESA_SHADER_STAGES
] = {0};
2755 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2756 struct radv_shader_variant_key keys
[MESA_SHADER_STAGES
] = {{{{{0}}}}};
2757 struct radv_shader_info infos
[MESA_SHADER_STAGES
] = {0};
2758 unsigned char hash
[20], gs_copy_hash
[20];
2759 bool keep_executable_info
= (flags
& VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
) || device
->keep_shader_info
;
2761 radv_start_feedback(pipeline_feedback
);
2763 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2765 modules
[i
] = radv_shader_module_from_handle(pStages
[i
]->module
);
2766 if (modules
[i
]->nir
)
2767 _mesa_sha1_compute(modules
[i
]->nir
->info
.name
,
2768 strlen(modules
[i
]->nir
->info
.name
),
2771 pipeline
->active_stages
|= mesa_to_vk_shader_stage(i
);
2775 radv_hash_shaders(hash
, pStages
, pipeline
->layout
, key
, get_hash_flags(device
));
2776 memcpy(gs_copy_hash
, hash
, 20);
2777 gs_copy_hash
[0] ^= 1;
2779 bool found_in_application_cache
= true;
2780 if (modules
[MESA_SHADER_GEOMETRY
] && !keep_executable_info
) {
2781 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2782 radv_create_shader_variants_from_pipeline_cache(device
, cache
, gs_copy_hash
, variants
,
2783 &found_in_application_cache
);
2784 pipeline
->gs_copy_shader
= variants
[MESA_SHADER_GEOMETRY
];
2787 if (!keep_executable_info
&&
2788 radv_create_shader_variants_from_pipeline_cache(device
, cache
, hash
, pipeline
->shaders
,
2789 &found_in_application_cache
) &&
2790 (!modules
[MESA_SHADER_GEOMETRY
] || pipeline
->gs_copy_shader
)) {
2791 radv_stop_feedback(pipeline_feedback
, found_in_application_cache
);
2795 if (!modules
[MESA_SHADER_FRAGMENT
] && !modules
[MESA_SHADER_COMPUTE
]) {
2797 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
2798 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "noop_fs");
2799 fs_m
.nir
= fs_b
.shader
;
2800 modules
[MESA_SHADER_FRAGMENT
] = &fs_m
;
2803 bool has_ts
= modules
[MESA_SHADER_TESS_CTRL
] || modules
[MESA_SHADER_TESS_EVAL
];
2804 bool use_aco
= device
->physical_device
->use_aco
;
2806 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2807 const VkPipelineShaderStageCreateInfo
*stage
= pStages
[i
];
2812 radv_start_feedback(stage_feedbacks
[i
]);
2814 bool aco
= use_aco
&& radv_aco_supported_stage(i
, has_ts
);
2815 nir
[i
] = radv_shader_compile_to_nir(device
, modules
[i
],
2816 stage
? stage
->pName
: "main", i
,
2817 stage
? stage
->pSpecializationInfo
: NULL
,
2818 flags
, pipeline
->layout
, aco
);
2820 /* We don't want to alter meta shaders IR directly so clone it
2823 if (nir
[i
]->info
.name
) {
2824 nir
[i
] = nir_shader_clone(NULL
, nir
[i
]);
2827 radv_stop_feedback(stage_feedbacks
[i
], false);
2830 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2831 nir_lower_patch_vertices(nir
[MESA_SHADER_TESS_EVAL
], nir
[MESA_SHADER_TESS_CTRL
]->info
.tess
.tcs_vertices_out
, NULL
);
2832 merge_tess_info(&nir
[MESA_SHADER_TESS_EVAL
]->info
, &nir
[MESA_SHADER_TESS_CTRL
]->info
);
2835 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
2836 radv_link_shaders(pipeline
, nir
);
2838 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2840 NIR_PASS_V(nir
[i
], nir_lower_non_uniform_access
,
2841 nir_lower_non_uniform_ubo_access
|
2842 nir_lower_non_uniform_ssbo_access
|
2843 nir_lower_non_uniform_texture_access
|
2844 nir_lower_non_uniform_image_access
);
2846 bool aco
= use_aco
&& radv_aco_supported_stage(i
, has_ts
);
2848 NIR_PASS_V(nir
[i
], nir_lower_bool_to_int32
);
2852 if (nir
[MESA_SHADER_FRAGMENT
])
2853 radv_lower_fs_io(nir
[MESA_SHADER_FRAGMENT
]);
2855 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2856 if (radv_can_dump_shader(device
, modules
[i
], false))
2857 nir_print_shader(nir
[i
], stderr
);
2860 radv_fill_shader_keys(device
, keys
, key
, nir
);
2862 radv_fill_shader_info(pipeline
, pStages
, keys
, infos
, nir
);
2864 if ((nir
[MESA_SHADER_VERTEX
] &&
2865 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) ||
2866 (nir
[MESA_SHADER_TESS_EVAL
] &&
2867 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
)) {
2868 struct gfx10_ngg_info
*ngg_info
;
2870 if (nir
[MESA_SHADER_GEOMETRY
])
2871 ngg_info
= &infos
[MESA_SHADER_GEOMETRY
].ngg_info
;
2872 else if (nir
[MESA_SHADER_TESS_CTRL
])
2873 ngg_info
= &infos
[MESA_SHADER_TESS_EVAL
].ngg_info
;
2875 ngg_info
= &infos
[MESA_SHADER_VERTEX
].ngg_info
;
2877 gfx10_get_ngg_info(key
, pipeline
, nir
, infos
, ngg_info
);
2878 } else if (nir
[MESA_SHADER_GEOMETRY
]) {
2879 struct gfx9_gs_info
*gs_info
=
2880 &infos
[MESA_SHADER_GEOMETRY
].gs_ring_info
;
2882 gfx9_get_gs_info(key
, pipeline
, nir
, infos
, gs_info
);
2885 if(modules
[MESA_SHADER_GEOMETRY
]) {
2886 struct radv_shader_binary
*gs_copy_binary
= NULL
;
2887 if (!pipeline
->gs_copy_shader
&&
2888 !radv_pipeline_has_ngg(pipeline
)) {
2889 struct radv_shader_info info
= {};
2890 struct radv_shader_variant_key key
= {};
2892 key
.has_multiview_view_index
=
2893 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
;
2895 radv_nir_shader_info_pass(nir
[MESA_SHADER_GEOMETRY
],
2896 pipeline
->layout
, &key
,
2898 info
.wave_size
= 64; /* Wave32 not supported. */
2900 pipeline
->gs_copy_shader
= radv_create_gs_copy_shader(
2901 device
, nir
[MESA_SHADER_GEOMETRY
], &info
,
2902 &gs_copy_binary
, keep_executable_info
,
2903 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
,
2907 if (!keep_executable_info
&& pipeline
->gs_copy_shader
) {
2908 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2909 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2911 binaries
[MESA_SHADER_GEOMETRY
] = gs_copy_binary
;
2912 variants
[MESA_SHADER_GEOMETRY
] = pipeline
->gs_copy_shader
;
2914 radv_pipeline_cache_insert_shaders(device
, cache
,
2919 free(gs_copy_binary
);
2922 if (nir
[MESA_SHADER_FRAGMENT
]) {
2923 if (!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]) {
2924 radv_start_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
]);
2926 bool aco
= use_aco
&& radv_aco_supported_stage(MESA_SHADER_FRAGMENT
, has_ts
);
2927 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] =
2928 radv_shader_variant_compile(device
, modules
[MESA_SHADER_FRAGMENT
], &nir
[MESA_SHADER_FRAGMENT
], 1,
2929 pipeline
->layout
, keys
+ MESA_SHADER_FRAGMENT
,
2930 infos
+ MESA_SHADER_FRAGMENT
,
2931 keep_executable_info
, aco
,
2932 &binaries
[MESA_SHADER_FRAGMENT
]);
2934 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
], false);
2938 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_TESS_CTRL
]) {
2939 if (!pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]) {
2940 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2941 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2942 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2944 radv_start_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
]);
2946 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_TESS_CTRL
], combined_nir
, 2,
2948 &key
, &infos
[MESA_SHADER_TESS_CTRL
], keep_executable_info
,
2949 false, &binaries
[MESA_SHADER_TESS_CTRL
]);
2951 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
], false);
2953 modules
[MESA_SHADER_VERTEX
] = NULL
;
2954 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2955 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2958 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_GEOMETRY
]) {
2959 gl_shader_stage pre_stage
= modules
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2960 if (!pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
2961 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2963 radv_start_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
]);
2965 bool aco
= use_aco
&& radv_aco_supported_stage(MESA_SHADER_GEOMETRY
, has_ts
);
2966 pipeline
->shaders
[MESA_SHADER_GEOMETRY
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_GEOMETRY
], combined_nir
, 2,
2968 &keys
[pre_stage
], &infos
[MESA_SHADER_GEOMETRY
], keep_executable_info
,
2969 aco
, &binaries
[MESA_SHADER_GEOMETRY
]);
2971 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
], false);
2973 modules
[pre_stage
] = NULL
;
2976 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2977 if(modules
[i
] && !pipeline
->shaders
[i
]) {
2978 if (i
== MESA_SHADER_TESS_CTRL
) {
2979 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.ls_outputs_written
);
2981 if (i
== MESA_SHADER_TESS_EVAL
) {
2982 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2983 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2986 radv_start_feedback(stage_feedbacks
[i
]);
2988 bool aco
= use_aco
&& radv_aco_supported_stage(i
, has_ts
);
2989 pipeline
->shaders
[i
] = radv_shader_variant_compile(device
, modules
[i
], &nir
[i
], 1,
2991 keys
+ i
, infos
+ i
,keep_executable_info
,
2994 radv_stop_feedback(stage_feedbacks
[i
], false);
2998 if (!keep_executable_info
) {
2999 radv_pipeline_cache_insert_shaders(device
, cache
, hash
, pipeline
->shaders
,
3003 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
3006 ralloc_free(nir
[i
]);
3008 if (radv_can_dump_shader_stats(device
, modules
[i
]))
3009 radv_shader_dump_stats(device
,
3010 pipeline
->shaders
[i
],
3016 ralloc_free(fs_m
.nir
);
3018 radv_stop_feedback(pipeline_feedback
, false);
3022 radv_pipeline_stage_to_user_data_0(struct radv_pipeline
*pipeline
,
3023 gl_shader_stage stage
, enum chip_class chip_class
)
3025 bool has_gs
= radv_pipeline_has_gs(pipeline
);
3026 bool has_tess
= radv_pipeline_has_tess(pipeline
);
3027 bool has_ngg
= radv_pipeline_has_ngg(pipeline
);
3030 case MESA_SHADER_FRAGMENT
:
3031 return R_00B030_SPI_SHADER_USER_DATA_PS_0
;
3032 case MESA_SHADER_VERTEX
:
3034 if (chip_class
>= GFX10
) {
3035 return R_00B430_SPI_SHADER_USER_DATA_HS_0
;
3036 } else if (chip_class
== GFX9
) {
3037 return R_00B430_SPI_SHADER_USER_DATA_LS_0
;
3039 return R_00B530_SPI_SHADER_USER_DATA_LS_0
;
3045 if (chip_class
>= GFX10
) {
3046 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3048 return R_00B330_SPI_SHADER_USER_DATA_ES_0
;
3053 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3055 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3056 case MESA_SHADER_GEOMETRY
:
3057 return chip_class
== GFX9
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
3058 R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3059 case MESA_SHADER_COMPUTE
:
3060 return R_00B900_COMPUTE_USER_DATA_0
;
3061 case MESA_SHADER_TESS_CTRL
:
3062 return chip_class
== GFX9
? R_00B430_SPI_SHADER_USER_DATA_LS_0
:
3063 R_00B430_SPI_SHADER_USER_DATA_HS_0
;
3064 case MESA_SHADER_TESS_EVAL
:
3066 return chip_class
>= GFX10
? R_00B230_SPI_SHADER_USER_DATA_GS_0
:
3067 R_00B330_SPI_SHADER_USER_DATA_ES_0
;
3068 } else if (has_ngg
) {
3069 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3071 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3074 unreachable("unknown shader");
3078 struct radv_bin_size_entry
{
3084 radv_gfx9_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3086 static const struct radv_bin_size_entry color_size_table
[][3][9] = {
3090 /* One shader engine */
3096 { UINT_MAX
, { 0, 0}},
3099 /* Two shader engines */
3105 { UINT_MAX
, { 0, 0}},
3108 /* Four shader engines */
3113 { UINT_MAX
, { 0, 0}},
3119 /* One shader engine */
3125 { UINT_MAX
, { 0, 0}},
3128 /* Two shader engines */
3134 { UINT_MAX
, { 0, 0}},
3137 /* Four shader engines */
3144 { UINT_MAX
, { 0, 0}},
3150 /* One shader engine */
3157 { UINT_MAX
, { 0, 0}},
3160 /* Two shader engines */
3168 { UINT_MAX
, { 0, 0}},
3171 /* Four shader engines */
3179 { UINT_MAX
, { 0, 0}},
3183 static const struct radv_bin_size_entry ds_size_table
[][3][9] = {
3187 // One shader engine
3194 { UINT_MAX
, { 0, 0}},
3197 // Two shader engines
3205 { UINT_MAX
, { 0, 0}},
3208 // Four shader engines
3216 { UINT_MAX
, { 0, 0}},
3222 // One shader engine
3230 { UINT_MAX
, { 0, 0}},
3233 // Two shader engines
3242 { UINT_MAX
, { 0, 0}},
3245 // Four shader engines
3254 { UINT_MAX
, { 0, 0}},
3260 // One shader engine
3268 { UINT_MAX
, { 0, 0}},
3271 // Two shader engines
3280 { UINT_MAX
, { 0, 0}},
3283 // Four shader engines
3291 { UINT_MAX
, { 0, 0}},
3296 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3297 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3298 VkExtent2D extent
= {512, 512};
3300 unsigned log_num_rb_per_se
=
3301 util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.num_render_backends
/
3302 pipeline
->device
->physical_device
->rad_info
.max_se
);
3303 unsigned log_num_se
= util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.max_se
);
3305 unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3306 unsigned ps_iter_samples
= 1u << G_028804_PS_ITER_SAMPLES(pipeline
->graphics
.ms
.db_eqaa
);
3307 unsigned effective_samples
= total_samples
;
3308 unsigned color_bytes_per_pixel
= 0;
3310 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3311 radv_pipeline_get_color_blend_state(pCreateInfo
);
3313 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3314 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3317 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3320 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3321 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3324 /* MSAA images typically don't use all samples all the time. */
3325 if (effective_samples
>= 2 && ps_iter_samples
<= 1)
3326 effective_samples
= 2;
3327 color_bytes_per_pixel
*= effective_samples
;
3330 const struct radv_bin_size_entry
*color_entry
= color_size_table
[log_num_rb_per_se
][log_num_se
];
3331 while(color_entry
[1].bpp
<= color_bytes_per_pixel
)
3334 extent
= color_entry
->extent
;
3336 if (subpass
->depth_stencil_attachment
) {
3337 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3339 /* Coefficients taken from AMDVLK */
3340 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3341 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3342 unsigned ds_bytes_per_pixel
= 4 * (depth_coeff
+ stencil_coeff
) * total_samples
;
3344 const struct radv_bin_size_entry
*ds_entry
= ds_size_table
[log_num_rb_per_se
][log_num_se
];
3345 while(ds_entry
[1].bpp
<= ds_bytes_per_pixel
)
3348 if (ds_entry
->extent
.width
* ds_entry
->extent
.height
< extent
.width
* extent
.height
)
3349 extent
= ds_entry
->extent
;
3356 radv_gfx10_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3358 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3359 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3360 VkExtent2D extent
= {512, 512};
3362 const unsigned db_tag_size
= 64;
3363 const unsigned db_tag_count
= 312;
3364 const unsigned color_tag_size
= 1024;
3365 const unsigned color_tag_count
= 31;
3366 const unsigned fmask_tag_size
= 256;
3367 const unsigned fmask_tag_count
= 44;
3369 const unsigned rb_count
= pipeline
->device
->physical_device
->rad_info
.num_render_backends
;
3370 const unsigned pipe_count
= MAX2(rb_count
, pipeline
->device
->physical_device
->rad_info
.num_sdp_interfaces
);
3372 const unsigned db_tag_part
= (db_tag_count
* rb_count
/ pipe_count
) * db_tag_size
* pipe_count
;
3373 const unsigned color_tag_part
= (color_tag_count
* rb_count
/ pipe_count
) * color_tag_size
* pipe_count
;
3374 const unsigned fmask_tag_part
= (fmask_tag_count
* rb_count
/ pipe_count
) * fmask_tag_size
* pipe_count
;
3376 const unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3377 const unsigned samples_log
= util_logbase2_ceil(total_samples
);
3379 unsigned color_bytes_per_pixel
= 0;
3380 unsigned fmask_bytes_per_pixel
= 0;
3382 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3383 radv_pipeline_get_color_blend_state(pCreateInfo
);
3385 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3386 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3389 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3392 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3393 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3395 if (total_samples
> 1) {
3396 assert(samples_log
<= 3);
3397 const unsigned fmask_array
[] = {0, 1, 1, 4};
3398 fmask_bytes_per_pixel
+= fmask_array
[samples_log
];
3402 color_bytes_per_pixel
*= total_samples
;
3404 color_bytes_per_pixel
= MAX2(color_bytes_per_pixel
, 1);
3406 const unsigned color_pixel_count_log
= util_logbase2(color_tag_part
/ color_bytes_per_pixel
);
3407 extent
.width
= 1ull << ((color_pixel_count_log
+ 1) / 2);
3408 extent
.height
= 1ull << (color_pixel_count_log
/ 2);
3410 if (fmask_bytes_per_pixel
) {
3411 const unsigned fmask_pixel_count_log
= util_logbase2(fmask_tag_part
/ fmask_bytes_per_pixel
);
3413 const VkExtent2D fmask_extent
= (VkExtent2D
){
3414 .width
= 1ull << ((fmask_pixel_count_log
+ 1) / 2),
3415 .height
= 1ull << (color_pixel_count_log
/ 2)
3418 if (fmask_extent
.width
* fmask_extent
.height
< extent
.width
* extent
.height
)
3419 extent
= fmask_extent
;
3422 if (subpass
->depth_stencil_attachment
) {
3423 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3425 /* Coefficients taken from AMDVLK */
3426 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3427 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3428 unsigned db_bytes_per_pixel
= (depth_coeff
+ stencil_coeff
) * total_samples
;
3430 const unsigned db_pixel_count_log
= util_logbase2(db_tag_part
/ db_bytes_per_pixel
);
3432 const VkExtent2D db_extent
= (VkExtent2D
){
3433 .width
= 1ull << ((db_pixel_count_log
+ 1) / 2),
3434 .height
= 1ull << (color_pixel_count_log
/ 2)
3437 if (db_extent
.width
* db_extent
.height
< extent
.width
* extent
.height
)
3441 extent
.width
= MAX2(extent
.width
, 128);
3442 extent
.height
= MAX2(extent
.width
, 64);
3448 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3449 struct radv_pipeline
*pipeline
,
3450 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3452 uint32_t pa_sc_binner_cntl_0
=
3453 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC
) |
3454 S_028C44_DISABLE_START_OF_PRIM(1);
3455 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3457 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3458 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3459 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3460 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3461 radv_pipeline_get_color_blend_state(pCreateInfo
);
3462 unsigned min_bytes_per_pixel
= 0;
3465 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3466 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3469 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3472 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3473 unsigned bytes
= vk_format_get_blocksize(format
);
3474 if (!min_bytes_per_pixel
|| bytes
< min_bytes_per_pixel
)
3475 min_bytes_per_pixel
= bytes
;
3479 pa_sc_binner_cntl_0
=
3480 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC
) |
3481 S_028C44_BIN_SIZE_X(0) |
3482 S_028C44_BIN_SIZE_Y(0) |
3483 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3484 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel
<= 4 ? 2 : 1) | /* 128 or 64 */
3485 S_028C44_DISABLE_START_OF_PRIM(1);
3488 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3489 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3492 struct radv_binning_settings
3493 radv_get_binning_settings(const struct radv_physical_device
*pdev
)
3495 struct radv_binning_settings settings
;
3496 if (pdev
->rad_info
.has_dedicated_vram
) {
3497 settings
.context_states_per_bin
= 1;
3498 settings
.persistent_states_per_bin
= 1;
3499 settings
.fpovs_per_batch
= 63;
3501 /* The context states are affected by the scissor bug. */
3502 settings
.context_states_per_bin
= 6;
3503 /* 32 causes hangs for RAVEN. */
3504 settings
.persistent_states_per_bin
= 16;
3505 settings
.fpovs_per_batch
= 63;
3508 if (pdev
->rad_info
.has_gfx9_scissor_bug
)
3509 settings
.context_states_per_bin
= 1;
3515 radv_pipeline_generate_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3516 struct radv_pipeline
*pipeline
,
3517 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3518 const struct radv_blend_state
*blend
)
3520 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
3523 VkExtent2D bin_size
;
3524 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3525 bin_size
= radv_gfx10_compute_bin_size(pipeline
, pCreateInfo
);
3526 } else if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3527 bin_size
= radv_gfx9_compute_bin_size(pipeline
, pCreateInfo
);
3529 unreachable("Unhandled generation for binning bin size calculation");
3531 if (pipeline
->device
->pbb_allowed
&& bin_size
.width
&& bin_size
.height
) {
3532 struct radv_binning_settings settings
=
3533 radv_get_binning_settings(pipeline
->device
->physical_device
);
3535 bool disable_start_of_prim
= true;
3536 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3538 const struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3540 if (pipeline
->device
->dfsm_allowed
&& ps
&&
3541 !ps
->info
.ps
.can_discard
&&
3542 !ps
->info
.ps
.writes_memory
&&
3543 blend
->cb_target_enabled_4bit
) {
3544 db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_AUTO
);
3545 disable_start_of_prim
= (blend
->blend_enable_4bit
& blend
->cb_target_enabled_4bit
) != 0;
3548 const uint32_t pa_sc_binner_cntl_0
=
3549 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED
) |
3550 S_028C44_BIN_SIZE_X(bin_size
.width
== 16) |
3551 S_028C44_BIN_SIZE_Y(bin_size
.height
== 16) |
3552 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size
.width
, 32)) - 5) |
3553 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size
.height
, 32)) - 5) |
3554 S_028C44_CONTEXT_STATES_PER_BIN(settings
.context_states_per_bin
- 1) |
3555 S_028C44_PERSISTENT_STATES_PER_BIN(settings
.persistent_states_per_bin
- 1) |
3556 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim
) |
3557 S_028C44_FPOVS_PER_BATCH(settings
.fpovs_per_batch
) |
3558 S_028C44_OPTIMAL_BIN_SELECTION(1);
3560 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3561 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3563 radv_pipeline_generate_disabled_binning_state(ctx_cs
, pipeline
, pCreateInfo
);
3568 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf
*ctx_cs
,
3569 struct radv_pipeline
*pipeline
,
3570 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3571 const struct radv_graphics_pipeline_create_info
*extra
)
3573 const VkPipelineDepthStencilStateCreateInfo
*vkds
= radv_pipeline_get_depth_stencil_state(pCreateInfo
);
3574 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3575 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3576 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3577 struct radv_render_pass_attachment
*attachment
= NULL
;
3578 uint32_t db_depth_control
= 0, db_stencil_control
= 0;
3579 uint32_t db_render_control
= 0, db_render_override2
= 0;
3580 uint32_t db_render_override
= 0;
3582 if (subpass
->depth_stencil_attachment
)
3583 attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3585 bool has_depth_attachment
= attachment
&& vk_format_is_depth(attachment
->format
);
3586 bool has_stencil_attachment
= attachment
&& vk_format_is_stencil(attachment
->format
);
3588 if (vkds
&& has_depth_attachment
) {
3589 db_depth_control
= S_028800_Z_ENABLE(vkds
->depthTestEnable
? 1 : 0) |
3590 S_028800_Z_WRITE_ENABLE(vkds
->depthWriteEnable
? 1 : 0) |
3591 S_028800_ZFUNC(vkds
->depthCompareOp
) |
3592 S_028800_DEPTH_BOUNDS_ENABLE(vkds
->depthBoundsTestEnable
? 1 : 0);
3594 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3595 db_render_override2
|= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment
->samples
> 2);
3598 if (has_stencil_attachment
&& vkds
&& vkds
->stencilTestEnable
) {
3599 db_depth_control
|= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3600 db_depth_control
|= S_028800_STENCILFUNC(vkds
->front
.compareOp
);
3601 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds
->front
.failOp
));
3602 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds
->front
.passOp
));
3603 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds
->front
.depthFailOp
));
3605 db_depth_control
|= S_028800_STENCILFUNC_BF(vkds
->back
.compareOp
);
3606 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds
->back
.failOp
));
3607 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds
->back
.passOp
));
3608 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds
->back
.depthFailOp
));
3611 if (attachment
&& extra
) {
3612 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(extra
->db_depth_clear
);
3613 db_render_control
|= S_028000_STENCIL_CLEAR_ENABLE(extra
->db_stencil_clear
);
3615 db_render_control
|= S_028000_RESUMMARIZE_ENABLE(extra
->db_resummarize
);
3616 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(extra
->db_flush_depth_inplace
);
3617 db_render_control
|= S_028000_STENCIL_COMPRESS_DISABLE(extra
->db_flush_stencil_inplace
);
3618 db_render_override2
|= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra
->db_depth_disable_expclear
);
3619 db_render_override2
|= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra
->db_stencil_disable_expclear
);
3622 db_render_override
|= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
3623 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
3625 if (!pCreateInfo
->pRasterizationState
->depthClampEnable
&&
3626 ps
->info
.ps
.writes_z
) {
3627 /* From VK_EXT_depth_range_unrestricted spec:
3629 * "The behavior described in Primitive Clipping still applies.
3630 * If depth clamping is disabled the depth values are still
3631 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3632 * depth clamping is enabled the above equation is ignored and
3633 * the depth values are instead clamped to the VkViewport
3634 * minDepth and maxDepth values, which in the case of this
3635 * extension can be outside of the 0.0 to 1.0 range."
3637 db_render_override
|= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3640 radeon_set_context_reg(ctx_cs
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
3641 radeon_set_context_reg(ctx_cs
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
3643 radeon_set_context_reg(ctx_cs
, R_028000_DB_RENDER_CONTROL
, db_render_control
);
3644 radeon_set_context_reg(ctx_cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
3645 radeon_set_context_reg(ctx_cs
, R_028010_DB_RENDER_OVERRIDE2
, db_render_override2
);
3649 radv_pipeline_generate_blend_state(struct radeon_cmdbuf
*ctx_cs
,
3650 struct radv_pipeline
*pipeline
,
3651 const struct radv_blend_state
*blend
)
3653 radeon_set_context_reg_seq(ctx_cs
, R_028780_CB_BLEND0_CONTROL
, 8);
3654 radeon_emit_array(ctx_cs
, blend
->cb_blend_control
,
3656 radeon_set_context_reg(ctx_cs
, R_028808_CB_COLOR_CONTROL
, blend
->cb_color_control
);
3657 radeon_set_context_reg(ctx_cs
, R_028B70_DB_ALPHA_TO_MASK
, blend
->db_alpha_to_mask
);
3659 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
3661 radeon_set_context_reg_seq(ctx_cs
, R_028760_SX_MRT0_BLEND_OPT
, 8);
3662 radeon_emit_array(ctx_cs
, blend
->sx_mrt_blend_opt
, 8);
3665 radeon_set_context_reg(ctx_cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
3667 radeon_set_context_reg(ctx_cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
3668 radeon_set_context_reg(ctx_cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
3670 pipeline
->graphics
.col_format
= blend
->spi_shader_col_format
;
3671 pipeline
->graphics
.cb_target_mask
= blend
->cb_target_mask
;
3674 static const VkConservativeRasterizationModeEXT
3675 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo
*pCreateInfo
)
3677 const VkPipelineRasterizationConservativeStateCreateInfoEXT
*conservative_raster
=
3678 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT
);
3680 if (!conservative_raster
)
3681 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
;
3682 return conservative_raster
->conservativeRasterizationMode
;
3686 radv_pipeline_generate_raster_state(struct radeon_cmdbuf
*ctx_cs
,
3687 struct radv_pipeline
*pipeline
,
3688 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3690 const VkPipelineRasterizationStateCreateInfo
*vkraster
= pCreateInfo
->pRasterizationState
;
3691 const VkConservativeRasterizationModeEXT mode
=
3692 radv_get_conservative_raster_mode(vkraster
);
3693 uint32_t pa_sc_conservative_rast
= S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3694 bool depth_clip_disable
= vkraster
->depthClampEnable
;
3696 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*depth_clip_state
=
3697 vk_find_struct_const(vkraster
->pNext
, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
3698 if (depth_clip_state
) {
3699 depth_clip_disable
= !depth_clip_state
->depthClipEnable
;
3702 radeon_set_context_reg(ctx_cs
, R_028810_PA_CL_CLIP_CNTL
,
3703 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3704 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable
? 1 : 0) |
3705 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable
? 1 : 0) |
3706 S_028810_DX_RASTERIZATION_KILL(vkraster
->rasterizerDiscardEnable
? 1 : 0) |
3707 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3709 radeon_set_context_reg(ctx_cs
, R_0286D4_SPI_INTERP_CONTROL_0
,
3710 S_0286D4_FLAT_SHADE_ENA(1) |
3711 S_0286D4_PNT_SPRITE_ENA(1) |
3712 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
3713 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
3714 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
3715 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
3716 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3718 radeon_set_context_reg(ctx_cs
, R_028BE4_PA_SU_VTX_CNTL
,
3719 S_028BE4_PIX_CENTER(1) | // TODO verify
3720 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN
) |
3721 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
3723 radeon_set_context_reg(ctx_cs
, R_028814_PA_SU_SC_MODE_CNTL
,
3724 S_028814_FACE(vkraster
->frontFace
) |
3725 S_028814_CULL_FRONT(!!(vkraster
->cullMode
& VK_CULL_MODE_FRONT_BIT
)) |
3726 S_028814_CULL_BACK(!!(vkraster
->cullMode
& VK_CULL_MODE_BACK_BIT
)) |
3727 S_028814_POLY_MODE(vkraster
->polygonMode
!= VK_POLYGON_MODE_FILL
) |
3728 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3729 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3730 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3731 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3732 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster
->depthBiasEnable
? 1 : 0));
3734 /* Conservative rasterization. */
3735 if (mode
!= VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
) {
3736 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3738 ms
->pa_sc_aa_config
|= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3739 ms
->db_eqaa
|= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3740 S_028804_OVERRASTERIZATION_AMOUNT(4);
3742 pa_sc_conservative_rast
= S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3743 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3744 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3746 if (mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT
) {
3747 pa_sc_conservative_rast
|=
3748 S_028C4C_OVER_RAST_ENABLE(1) |
3749 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3750 S_028C4C_UNDER_RAST_ENABLE(0) |
3751 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3752 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3754 assert(mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT
);
3755 pa_sc_conservative_rast
|=
3756 S_028C4C_OVER_RAST_ENABLE(0) |
3757 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3758 S_028C4C_UNDER_RAST_ENABLE(1) |
3759 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3760 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3764 radeon_set_context_reg(ctx_cs
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
3765 pa_sc_conservative_rast
);
3770 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf
*ctx_cs
,
3771 struct radv_pipeline
*pipeline
)
3773 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3775 radeon_set_context_reg_seq(ctx_cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
3776 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[0]);
3777 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[1]);
3779 radeon_set_context_reg(ctx_cs
, R_028804_DB_EQAA
, ms
->db_eqaa
);
3780 radeon_set_context_reg(ctx_cs
, R_028A48_PA_SC_MODE_CNTL_0
, ms
->pa_sc_mode_cntl_0
);
3781 radeon_set_context_reg(ctx_cs
, R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
3782 radeon_set_context_reg(ctx_cs
, R_028BDC_PA_SC_LINE_CNTL
, ms
->pa_sc_line_cntl
);
3783 radeon_set_context_reg(ctx_cs
, R_028BE0_PA_SC_AA_CONFIG
, ms
->pa_sc_aa_config
);
3785 /* The exclusion bits can be set to improve rasterization efficiency
3786 * if no sample lies on the pixel boundary (-8 sample offset). It's
3787 * currently always TRUE because the driver doesn't support 16 samples.
3789 bool exclusion
= pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
3790 radeon_set_context_reg(ctx_cs
, R_02882C_PA_SU_PRIM_FILTER_CNTL
,
3791 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) |
3792 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3794 /* GFX9: Flush DFSM when the AA mode changes. */
3795 if (pipeline
->device
->dfsm_allowed
) {
3796 radeon_emit(ctx_cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3797 radeon_emit(ctx_cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3802 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf
*ctx_cs
,
3803 struct radv_pipeline
*pipeline
)
3805 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3806 const struct radv_shader_variant
*vs
=
3807 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] ?
3808 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] :
3809 pipeline
->shaders
[MESA_SHADER_VERTEX
];
3810 unsigned vgt_primitiveid_en
= 0;
3811 uint32_t vgt_gs_mode
= 0;
3813 if (radv_pipeline_has_ngg(pipeline
))
3816 if (radv_pipeline_has_gs(pipeline
)) {
3817 const struct radv_shader_variant
*gs
=
3818 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3820 vgt_gs_mode
= ac_vgt_gs_mode(gs
->info
.gs
.vertices_out
,
3821 pipeline
->device
->physical_device
->rad_info
.chip_class
);
3822 } else if (outinfo
->export_prim_id
|| vs
->info
.uses_prim_id
) {
3823 vgt_gs_mode
= S_028A40_MODE(V_028A40_GS_SCENARIO_A
);
3824 vgt_primitiveid_en
|= S_028A84_PRIMITIVEID_EN(1);
3827 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
, vgt_primitiveid_en
);
3828 radeon_set_context_reg(ctx_cs
, R_028A40_VGT_GS_MODE
, vgt_gs_mode
);
3832 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf
*ctx_cs
,
3833 struct radeon_cmdbuf
*cs
,
3834 struct radv_pipeline
*pipeline
,
3835 struct radv_shader_variant
*shader
)
3837 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3839 radeon_set_sh_reg_seq(cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
3840 radeon_emit(cs
, va
>> 8);
3841 radeon_emit(cs
, S_00B124_MEM_BASE(va
>> 40));
3842 radeon_emit(cs
, shader
->config
.rsrc1
);
3843 radeon_emit(cs
, shader
->config
.rsrc2
);
3845 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3846 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3847 clip_dist_mask
= outinfo
->clip_dist_mask
;
3848 cull_dist_mask
= outinfo
->cull_dist_mask
;
3849 total_mask
= clip_dist_mask
| cull_dist_mask
;
3850 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3851 outinfo
->writes_layer
||
3852 outinfo
->writes_viewport_index
;
3853 unsigned spi_vs_out_config
, nparams
;
3855 /* VS is required to export at least one param. */
3856 nparams
= MAX2(outinfo
->param_exports
, 1);
3857 spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
3859 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3860 spi_vs_out_config
|= S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0);
3863 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
, spi_vs_out_config
);
3865 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3866 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3867 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3868 V_02870C_SPI_SHADER_4COMP
:
3869 V_02870C_SPI_SHADER_NONE
) |
3870 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3871 V_02870C_SPI_SHADER_4COMP
:
3872 V_02870C_SPI_SHADER_NONE
) |
3873 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3874 V_02870C_SPI_SHADER_4COMP
:
3875 V_02870C_SPI_SHADER_NONE
));
3877 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
3878 S_028818_VTX_W0_FMT(1) |
3879 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3880 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3881 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3883 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3884 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3885 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3886 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3887 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3888 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3889 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3890 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3891 cull_dist_mask
<< 8 |
3894 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
3895 radeon_set_context_reg(ctx_cs
, R_028AB4_VGT_REUSE_OFF
,
3896 outinfo
->writes_viewport_index
);
3900 radv_pipeline_generate_hw_es(struct radeon_cmdbuf
*cs
,
3901 struct radv_pipeline
*pipeline
,
3902 struct radv_shader_variant
*shader
)
3904 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3906 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
3907 radeon_emit(cs
, va
>> 8);
3908 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3909 radeon_emit(cs
, shader
->config
.rsrc1
);
3910 radeon_emit(cs
, shader
->config
.rsrc2
);
3914 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf
*cs
,
3915 struct radv_pipeline
*pipeline
,
3916 struct radv_shader_variant
*shader
,
3917 const struct radv_tessellation_state
*tess
)
3919 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3920 uint32_t rsrc2
= shader
->config
.rsrc2
;
3922 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
3923 radeon_emit(cs
, va
>> 8);
3924 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
3926 rsrc2
|= S_00B52C_LDS_SIZE(tess
->lds_size
);
3927 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX7
&&
3928 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
3929 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
3931 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
3932 radeon_emit(cs
, shader
->config
.rsrc1
);
3933 radeon_emit(cs
, rsrc2
);
3937 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf
*ctx_cs
,
3938 struct radeon_cmdbuf
*cs
,
3939 struct radv_pipeline
*pipeline
,
3940 struct radv_shader_variant
*shader
)
3942 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3943 gl_shader_stage es_type
=
3944 radv_pipeline_has_tess(pipeline
) ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
3945 struct radv_shader_variant
*es
=
3946 es_type
== MESA_SHADER_TESS_EVAL
? pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] : pipeline
->shaders
[MESA_SHADER_VERTEX
];
3947 const struct gfx10_ngg_info
*ngg_state
= &shader
->info
.ngg_info
;
3949 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
3950 radeon_emit(cs
, va
>> 8);
3951 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3952 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
3953 radeon_emit(cs
, shader
->config
.rsrc1
);
3954 radeon_emit(cs
, shader
->config
.rsrc2
);
3956 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3957 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3958 clip_dist_mask
= outinfo
->clip_dist_mask
;
3959 cull_dist_mask
= outinfo
->cull_dist_mask
;
3960 total_mask
= clip_dist_mask
| cull_dist_mask
;
3961 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3962 outinfo
->writes_layer
||
3963 outinfo
->writes_viewport_index
;
3964 bool es_enable_prim_id
= outinfo
->export_prim_id
||
3965 (es
&& es
->info
.uses_prim_id
);
3966 bool break_wave_at_eoi
= false;
3970 if (es_type
== MESA_SHADER_TESS_EVAL
) {
3971 struct radv_shader_variant
*gs
=
3972 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3974 if (es_enable_prim_id
|| (gs
&& gs
->info
.uses_prim_id
))
3975 break_wave_at_eoi
= true;
3978 nparams
= MAX2(outinfo
->param_exports
, 1);
3979 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
3980 S_0286C4_VS_EXPORT_COUNT(nparams
- 1) |
3981 S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0));
3983 radeon_set_context_reg(ctx_cs
, R_028708_SPI_SHADER_IDX_FORMAT
,
3984 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP
));
3985 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3986 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3987 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3988 V_02870C_SPI_SHADER_4COMP
:
3989 V_02870C_SPI_SHADER_NONE
) |
3990 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3991 V_02870C_SPI_SHADER_4COMP
:
3992 V_02870C_SPI_SHADER_NONE
) |
3993 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3994 V_02870C_SPI_SHADER_4COMP
:
3995 V_02870C_SPI_SHADER_NONE
));
3997 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
3998 S_028818_VTX_W0_FMT(1) |
3999 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
4000 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
4001 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
4002 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
4003 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
4004 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
4005 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
4006 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
4007 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
4008 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
4009 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
4010 cull_dist_mask
<< 8 |
4013 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
,
4014 S_028A84_PRIMITIVEID_EN(es_enable_prim_id
) |
4015 S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo
->export_prim_id
));
4017 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
4018 ngg_state
->vgt_esgs_ring_itemsize
);
4020 /* NGG specific registers. */
4021 struct radv_shader_variant
*gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4022 uint32_t gs_num_invocations
= gs
? gs
->info
.gs
.invocations
: 1;
4024 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4025 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state
->hw_max_esverts
) |
4026 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state
->max_gsprims
) |
4027 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state
->max_gsprims
* gs_num_invocations
));
4028 radeon_set_context_reg(ctx_cs
, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP
,
4029 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state
->max_out_verts
));
4030 radeon_set_context_reg(ctx_cs
, R_028B4C_GE_NGG_SUBGRP_CNTL
,
4031 S_028B4C_PRIM_AMP_FACTOR(ngg_state
->prim_amp_factor
) |
4032 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
4033 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
4034 S_028B90_CNT(gs_num_invocations
) |
4035 S_028B90_ENABLE(gs_num_invocations
> 1) |
4036 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state
->max_vert_out_per_gs_instance
));
4038 /* User edge flags are set by the pos exports. If user edge flags are
4039 * not used, we must use hw-generated edge flags and pass them via
4040 * the prim export to prevent drawing lines on internal edges of
4041 * decomposed primitives (such as quads) with polygon mode = lines.
4043 * TODO: We should combine hw-generated edge flags with user edge
4044 * flags in the shader.
4046 radeon_set_context_reg(ctx_cs
, R_028838_PA_CL_NGG_CNTL
,
4047 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline
) &&
4048 !radv_pipeline_has_gs(pipeline
)));
4050 ge_cntl
= S_03096C_PRIM_GRP_SIZE(ngg_state
->max_gsprims
) |
4051 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
4052 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
);
4054 /* Bug workaround for a possible hang with non-tessellation cases.
4055 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
4057 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
4059 if ((pipeline
->device
->physical_device
->rad_info
.family
== CHIP_NAVI10
||
4060 pipeline
->device
->physical_device
->rad_info
.family
== CHIP_NAVI12
||
4061 pipeline
->device
->physical_device
->rad_info
.family
== CHIP_NAVI14
) &&
4062 !radv_pipeline_has_tess(pipeline
) &&
4063 ngg_state
->hw_max_esverts
!= 256) {
4064 ge_cntl
&= C_03096C_VERT_GRP_SIZE
;
4066 if (ngg_state
->hw_max_esverts
> 5) {
4067 ge_cntl
|= S_03096C_VERT_GRP_SIZE(ngg_state
->hw_max_esverts
- 5);
4071 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
, ge_cntl
);
4075 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf
*cs
,
4076 struct radv_pipeline
*pipeline
,
4077 struct radv_shader_variant
*shader
,
4078 const struct radv_tessellation_state
*tess
)
4080 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
4082 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4083 unsigned hs_rsrc2
= shader
->config
.rsrc2
;
4085 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4086 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX10(tess
->lds_size
);
4088 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX9(tess
->lds_size
);
4091 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4092 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
4093 radeon_emit(cs
, va
>> 8);
4094 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
4096 radeon_set_sh_reg_seq(cs
, R_00B410_SPI_SHADER_PGM_LO_LS
, 2);
4097 radeon_emit(cs
, va
>> 8);
4098 radeon_emit(cs
, S_00B414_MEM_BASE(va
>> 40));
4101 radeon_set_sh_reg_seq(cs
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
, 2);
4102 radeon_emit(cs
, shader
->config
.rsrc1
);
4103 radeon_emit(cs
, hs_rsrc2
);
4105 radeon_set_sh_reg_seq(cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
4106 radeon_emit(cs
, va
>> 8);
4107 radeon_emit(cs
, S_00B424_MEM_BASE(va
>> 40));
4108 radeon_emit(cs
, shader
->config
.rsrc1
);
4109 radeon_emit(cs
, shader
->config
.rsrc2
);
4114 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf
*ctx_cs
,
4115 struct radeon_cmdbuf
*cs
,
4116 struct radv_pipeline
*pipeline
,
4117 const struct radv_tessellation_state
*tess
)
4119 struct radv_shader_variant
*vs
;
4121 /* Skip shaders merged into HS/GS */
4122 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
4126 if (vs
->info
.vs
.as_ls
)
4127 radv_pipeline_generate_hw_ls(cs
, pipeline
, vs
, tess
);
4128 else if (vs
->info
.vs
.as_es
)
4129 radv_pipeline_generate_hw_es(cs
, pipeline
, vs
);
4130 else if (vs
->info
.is_ngg
)
4131 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, vs
);
4133 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, vs
);
4137 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf
*ctx_cs
,
4138 struct radeon_cmdbuf
*cs
,
4139 struct radv_pipeline
*pipeline
,
4140 const struct radv_tessellation_state
*tess
)
4142 if (!radv_pipeline_has_tess(pipeline
))
4145 struct radv_shader_variant
*tes
, *tcs
;
4147 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
4148 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
4151 if (tes
->info
.is_ngg
) {
4152 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, tes
);
4153 } else if (tes
->info
.tes
.as_es
)
4154 radv_pipeline_generate_hw_es(cs
, pipeline
, tes
);
4156 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, tes
);
4159 radv_pipeline_generate_hw_hs(cs
, pipeline
, tcs
, tess
);
4161 radeon_set_context_reg(ctx_cs
, R_028B6C_VGT_TF_PARAM
,
4164 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
)
4165 radeon_set_context_reg_idx(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
4166 tess
->ls_hs_config
);
4168 radeon_set_context_reg(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
,
4169 tess
->ls_hs_config
);
4171 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
4172 !radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
4173 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4174 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4175 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4176 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4181 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf
*ctx_cs
,
4182 struct radeon_cmdbuf
*cs
,
4183 struct radv_pipeline
*pipeline
,
4184 struct radv_shader_variant
*gs
)
4186 const struct gfx9_gs_info
*gs_state
= &gs
->info
.gs_ring_info
;
4187 unsigned gs_max_out_vertices
;
4188 uint8_t *num_components
;
4193 gs_max_out_vertices
= gs
->info
.gs
.vertices_out
;
4194 max_stream
= gs
->info
.gs
.max_stream
;
4195 num_components
= gs
->info
.gs
.num_stream_output_components
;
4197 offset
= num_components
[0] * gs_max_out_vertices
;
4199 radeon_set_context_reg_seq(ctx_cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
4200 radeon_emit(ctx_cs
, offset
);
4201 if (max_stream
>= 1)
4202 offset
+= num_components
[1] * gs_max_out_vertices
;
4203 radeon_emit(ctx_cs
, offset
);
4204 if (max_stream
>= 2)
4205 offset
+= num_components
[2] * gs_max_out_vertices
;
4206 radeon_emit(ctx_cs
, offset
);
4207 if (max_stream
>= 3)
4208 offset
+= num_components
[3] * gs_max_out_vertices
;
4209 radeon_set_context_reg(ctx_cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
4211 radeon_set_context_reg_seq(ctx_cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
4212 radeon_emit(ctx_cs
, num_components
[0]);
4213 radeon_emit(ctx_cs
, (max_stream
>= 1) ? num_components
[1] : 0);
4214 radeon_emit(ctx_cs
, (max_stream
>= 2) ? num_components
[2] : 0);
4215 radeon_emit(ctx_cs
, (max_stream
>= 3) ? num_components
[3] : 0);
4217 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
4218 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
4219 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
4220 S_028B90_ENABLE(gs_num_invocations
> 0));
4222 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
4223 gs_state
->vgt_esgs_ring_itemsize
);
4225 va
= radv_buffer_get_va(gs
->bo
) + gs
->bo_offset
;
4227 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4228 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4229 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
4230 radeon_emit(cs
, va
>> 8);
4231 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
4233 radeon_set_sh_reg_seq(cs
, R_00B210_SPI_SHADER_PGM_LO_ES
, 2);
4234 radeon_emit(cs
, va
>> 8);
4235 radeon_emit(cs
, S_00B214_MEM_BASE(va
>> 40));
4238 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
4239 radeon_emit(cs
, gs
->config
.rsrc1
);
4240 radeon_emit(cs
, gs
->config
.rsrc2
| S_00B22C_LDS_SIZE(gs_state
->lds_size
));
4242 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
, gs_state
->vgt_gs_onchip_cntl
);
4243 radeon_set_context_reg(ctx_cs
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
, gs_state
->vgt_gs_max_prims_per_subgroup
);
4245 radeon_set_sh_reg_seq(cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
4246 radeon_emit(cs
, va
>> 8);
4247 radeon_emit(cs
, S_00B224_MEM_BASE(va
>> 40));
4248 radeon_emit(cs
, gs
->config
.rsrc1
);
4249 radeon_emit(cs
, gs
->config
.rsrc2
);
4252 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, pipeline
->gs_copy_shader
);
4256 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf
*ctx_cs
,
4257 struct radeon_cmdbuf
*cs
,
4258 struct radv_pipeline
*pipeline
)
4260 struct radv_shader_variant
*gs
;
4262 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4266 if (gs
->info
.is_ngg
)
4267 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, gs
);
4269 radv_pipeline_generate_hw_gs(ctx_cs
, cs
, pipeline
, gs
);
4271 radeon_set_context_reg(ctx_cs
, R_028B38_VGT_GS_MAX_VERT_OUT
,
4272 gs
->info
.gs
.vertices_out
);
4275 static uint32_t offset_to_ps_input(uint32_t offset
, bool flat_shade
,
4276 bool explicit, bool float16
)
4278 uint32_t ps_input_cntl
;
4279 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
4280 ps_input_cntl
= S_028644_OFFSET(offset
);
4281 if (flat_shade
|| explicit)
4282 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
4284 /* Force parameter cache to be read in passthrough
4287 ps_input_cntl
|= S_028644_OFFSET(1 << 5);
4290 ps_input_cntl
|= S_028644_FP16_INTERP_MODE(1) |
4291 S_028644_ATTR0_VALID(1);
4294 /* The input is a DEFAULT_VAL constant. */
4295 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
4296 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
4297 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
4298 ps_input_cntl
= S_028644_OFFSET(0x20) |
4299 S_028644_DEFAULT_VAL(offset
);
4301 return ps_input_cntl
;
4305 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf
*ctx_cs
,
4306 struct radv_pipeline
*pipeline
)
4308 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4309 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
4310 uint32_t ps_input_cntl
[32];
4312 unsigned ps_offset
= 0;
4314 if (ps
->info
.ps
.prim_id_input
) {
4315 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
];
4316 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4317 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4322 if (ps
->info
.ps
.layer_input
||
4323 ps
->info
.needs_multiview_view_index
) {
4324 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
];
4325 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
4326 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4328 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false, false);
4332 if (ps
->info
.ps
.has_pcoord
) {
4334 val
= S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4335 ps_input_cntl
[ps_offset
] = val
;
4339 if (ps
->info
.ps
.num_input_clips_culls
) {
4342 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST0
];
4343 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4344 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false, false);
4348 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST1
];
4349 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
&&
4350 ps
->info
.ps
.num_input_clips_culls
> 4) {
4351 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false, false);
4356 for (unsigned i
= 0; i
< 32 && (1u << i
) <= ps
->info
.ps
.input_mask
; ++i
) {
4361 if (!(ps
->info
.ps
.input_mask
& (1u << i
)))
4364 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VAR0
+ i
];
4365 if (vs_offset
== AC_EXP_PARAM_UNDEFINED
) {
4366 ps_input_cntl
[ps_offset
] = S_028644_OFFSET(0x20);
4371 flat_shade
= !!(ps
->info
.ps
.flat_shaded_mask
& (1u << ps_offset
));
4372 explicit = !!(ps
->info
.ps
.explicit_shaded_mask
& (1u << ps_offset
));
4373 float16
= !!(ps
->info
.ps
.float16_shaded_mask
& (1u << ps_offset
));
4375 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, flat_shade
, explicit, float16
);
4380 radeon_set_context_reg_seq(ctx_cs
, R_028644_SPI_PS_INPUT_CNTL_0
, ps_offset
);
4381 for (unsigned i
= 0; i
< ps_offset
; i
++) {
4382 radeon_emit(ctx_cs
, ps_input_cntl
[i
]);
4388 radv_compute_db_shader_control(const struct radv_device
*device
,
4389 const struct radv_pipeline
*pipeline
,
4390 const struct radv_shader_variant
*ps
)
4393 if (ps
->info
.ps
.early_fragment_test
|| !ps
->info
.ps
.writes_memory
)
4394 z_order
= V_02880C_EARLY_Z_THEN_LATE_Z
;
4396 z_order
= V_02880C_LATE_Z
;
4398 bool disable_rbplus
= device
->physical_device
->rad_info
.has_rbplus
&&
4399 !device
->physical_device
->rad_info
.rbplus_allowed
;
4401 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4402 * but this appears to break Project Cars (DXVK). See
4403 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4405 bool mask_export_enable
= ps
->info
.ps
.writes_sample_mask
;
4407 return S_02880C_Z_EXPORT_ENABLE(ps
->info
.ps
.writes_z
) |
4408 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps
->info
.ps
.writes_stencil
) |
4409 S_02880C_KILL_ENABLE(!!ps
->info
.ps
.can_discard
) |
4410 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable
) |
4411 S_02880C_Z_ORDER(z_order
) |
4412 S_02880C_DEPTH_BEFORE_SHADER(ps
->info
.ps
.early_fragment_test
) |
4413 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps
->info
.ps
.post_depth_coverage
) |
4414 S_02880C_EXEC_ON_HIER_FAIL(ps
->info
.ps
.writes_memory
) |
4415 S_02880C_EXEC_ON_NOOP(ps
->info
.ps
.writes_memory
) |
4416 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus
);
4420 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf
*ctx_cs
,
4421 struct radeon_cmdbuf
*cs
,
4422 struct radv_pipeline
*pipeline
)
4424 struct radv_shader_variant
*ps
;
4426 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
4428 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4429 va
= radv_buffer_get_va(ps
->bo
) + ps
->bo_offset
;
4431 radeon_set_sh_reg_seq(cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
4432 radeon_emit(cs
, va
>> 8);
4433 radeon_emit(cs
, S_00B024_MEM_BASE(va
>> 40));
4434 radeon_emit(cs
, ps
->config
.rsrc1
);
4435 radeon_emit(cs
, ps
->config
.rsrc2
);
4437 radeon_set_context_reg(ctx_cs
, R_02880C_DB_SHADER_CONTROL
,
4438 radv_compute_db_shader_control(pipeline
->device
,
4441 radeon_set_context_reg(ctx_cs
, R_0286CC_SPI_PS_INPUT_ENA
,
4442 ps
->config
.spi_ps_input_ena
);
4444 radeon_set_context_reg(ctx_cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
4445 ps
->config
.spi_ps_input_addr
);
4447 radeon_set_context_reg(ctx_cs
, R_0286D8_SPI_PS_IN_CONTROL
,
4448 S_0286D8_NUM_INTERP(ps
->info
.ps
.num_interp
) |
4449 S_0286D8_PS_W32_EN(ps
->info
.wave_size
== 32));
4451 radeon_set_context_reg(ctx_cs
, R_0286E0_SPI_BARYC_CNTL
, pipeline
->graphics
.spi_baryc_cntl
);
4453 radeon_set_context_reg(ctx_cs
, R_028710_SPI_SHADER_Z_FORMAT
,
4454 ac_get_spi_shader_z_format(ps
->info
.ps
.writes_z
,
4455 ps
->info
.ps
.writes_stencil
,
4456 ps
->info
.ps
.writes_sample_mask
));
4458 if (pipeline
->device
->dfsm_allowed
) {
4459 /* optimise this? */
4460 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
4461 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
4466 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf
*ctx_cs
,
4467 struct radv_pipeline
*pipeline
)
4469 if (pipeline
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4470 pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
4473 unsigned vtx_reuse_depth
= 30;
4474 if (radv_pipeline_has_tess(pipeline
) &&
4475 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.tes
.spacing
== TESS_SPACING_FRACTIONAL_ODD
) {
4476 vtx_reuse_depth
= 14;
4478 radeon_set_context_reg(ctx_cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
4479 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth
));
4483 radv_compute_vgt_shader_stages_en(const struct radv_pipeline
*pipeline
)
4485 uint32_t stages
= 0;
4486 if (radv_pipeline_has_tess(pipeline
)) {
4487 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
4488 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4490 if (radv_pipeline_has_gs(pipeline
))
4491 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
4493 else if (radv_pipeline_has_ngg(pipeline
))
4494 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
4496 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
4497 } else if (radv_pipeline_has_gs(pipeline
)) {
4498 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
4500 } else if (radv_pipeline_has_ngg(pipeline
)) {
4501 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
4504 if (radv_pipeline_has_ngg(pipeline
)) {
4505 stages
|= S_028B54_PRIMGEN_EN(1);
4506 if (pipeline
->streamout_shader
)
4507 stages
|= S_028B54_NGG_WAVE_ID_EN(1);
4508 if (radv_pipeline_has_ngg_passthrough(pipeline
))
4509 stages
|= S_028B54_PRIMGEN_PASSTHRU_EN(1);
4510 } else if (radv_pipeline_has_gs(pipeline
)) {
4511 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
4514 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
4515 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4517 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4518 uint8_t hs_size
= 64, gs_size
= 64, vs_size
= 64;
4520 if (radv_pipeline_has_tess(pipeline
))
4521 hs_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.wave_size
;
4523 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
4524 vs_size
= gs_size
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.wave_size
;
4525 if (pipeline
->gs_copy_shader
)
4526 vs_size
= pipeline
->gs_copy_shader
->info
.wave_size
;
4527 } else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
4528 vs_size
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.wave_size
;
4529 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
4530 vs_size
= pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.wave_size
;
4532 if (radv_pipeline_has_ngg(pipeline
))
4535 /* legacy GS only supports Wave64 */
4536 stages
|= S_028B54_HS_W32_EN(hs_size
== 32 ? 1 : 0) |
4537 S_028B54_GS_W32_EN(gs_size
== 32 ? 1 : 0) |
4538 S_028B54_VS_W32_EN(vs_size
== 32 ? 1 : 0);
4545 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4547 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
4548 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
4550 if (!discard_rectangle_info
)
4555 for (unsigned i
= 0; i
< (1u << MAX_DISCARD_RECTANGLES
); ++i
) {
4556 /* Interpret i as a bitmask, and then set the bit in the mask if
4557 * that combination of rectangles in which the pixel is contained
4558 * should pass the cliprect test. */
4559 unsigned relevant_subset
= i
& ((1u << discard_rectangle_info
->discardRectangleCount
) - 1);
4561 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT
&&
4565 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT
&&
4576 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf
*ctx_cs
,
4577 struct radv_pipeline
*pipeline
,
4578 const struct radv_tessellation_state
*tess
)
4580 bool break_wave_at_eoi
= false;
4581 unsigned primgroup_size
;
4582 unsigned vertgroup_size
= 256; /* 256 = disable vertex grouping */
4584 if (radv_pipeline_has_tess(pipeline
)) {
4585 primgroup_size
= tess
->num_patches
; /* must be a multiple of NUM_PATCHES */
4586 } else if (radv_pipeline_has_gs(pipeline
)) {
4587 const struct gfx9_gs_info
*gs_state
=
4588 &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs_ring_info
;
4589 unsigned vgt_gs_onchip_cntl
= gs_state
->vgt_gs_onchip_cntl
;
4590 primgroup_size
= G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl
);
4592 primgroup_size
= 128; /* recommended without a GS and tess */
4595 if (radv_pipeline_has_tess(pipeline
)) {
4596 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4597 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4598 break_wave_at_eoi
= true;
4601 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
,
4602 S_03096C_PRIM_GRP_SIZE(primgroup_size
) |
4603 S_03096C_VERT_GRP_SIZE(vertgroup_size
) |
4604 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4605 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
));
4609 radv_pipeline_generate_pm4(struct radv_pipeline
*pipeline
,
4610 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4611 const struct radv_graphics_pipeline_create_info
*extra
,
4612 const struct radv_blend_state
*blend
,
4613 const struct radv_tessellation_state
*tess
,
4614 unsigned prim
, unsigned gs_out
)
4616 struct radeon_cmdbuf
*ctx_cs
= &pipeline
->ctx_cs
;
4617 struct radeon_cmdbuf
*cs
= &pipeline
->cs
;
4620 ctx_cs
->max_dw
= 256;
4621 cs
->buf
= malloc(4 * (cs
->max_dw
+ ctx_cs
->max_dw
));
4622 ctx_cs
->buf
= cs
->buf
+ cs
->max_dw
;
4624 radv_pipeline_generate_depth_stencil_state(ctx_cs
, pipeline
, pCreateInfo
, extra
);
4625 radv_pipeline_generate_blend_state(ctx_cs
, pipeline
, blend
);
4626 radv_pipeline_generate_raster_state(ctx_cs
, pipeline
, pCreateInfo
);
4627 radv_pipeline_generate_multisample_state(ctx_cs
, pipeline
);
4628 radv_pipeline_generate_vgt_gs_mode(ctx_cs
, pipeline
);
4629 radv_pipeline_generate_vertex_shader(ctx_cs
, cs
, pipeline
, tess
);
4630 radv_pipeline_generate_tess_shaders(ctx_cs
, cs
, pipeline
, tess
);
4631 radv_pipeline_generate_geometry_shader(ctx_cs
, cs
, pipeline
);
4632 radv_pipeline_generate_fragment_shader(ctx_cs
, cs
, pipeline
);
4633 radv_pipeline_generate_ps_inputs(ctx_cs
, pipeline
);
4634 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs
, pipeline
);
4635 radv_pipeline_generate_binning_state(ctx_cs
, pipeline
, pCreateInfo
, blend
);
4637 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&& !radv_pipeline_has_ngg(pipeline
))
4638 gfx10_pipeline_generate_ge_cntl(ctx_cs
, pipeline
, tess
);
4640 radeon_set_context_reg(ctx_cs
, R_028B54_VGT_SHADER_STAGES_EN
, radv_compute_vgt_shader_stages_en(pipeline
));
4642 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4643 radeon_set_uconfig_reg_idx(pipeline
->device
->physical_device
,
4644 cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, prim
);
4646 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
4648 radeon_set_context_reg(ctx_cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, gs_out
);
4650 radeon_set_context_reg(ctx_cs
, R_02820C_PA_SC_CLIPRECT_RULE
, radv_compute_cliprect_rule(pCreateInfo
));
4652 pipeline
->ctx_cs_hash
= _mesa_hash_data(ctx_cs
->buf
, ctx_cs
->cdw
* 4);
4654 assert(ctx_cs
->cdw
<= ctx_cs
->max_dw
);
4655 assert(cs
->cdw
<= cs
->max_dw
);
4658 static struct radv_ia_multi_vgt_param_helpers
4659 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline
*pipeline
,
4660 const struct radv_tessellation_state
*tess
,
4663 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
= {0};
4664 const struct radv_device
*device
= pipeline
->device
;
4666 if (radv_pipeline_has_tess(pipeline
))
4667 ia_multi_vgt_param
.primgroup_size
= tess
->num_patches
;
4668 else if (radv_pipeline_has_gs(pipeline
))
4669 ia_multi_vgt_param
.primgroup_size
= 64;
4671 ia_multi_vgt_param
.primgroup_size
= 128; /* recommended without a GS */
4673 /* GS requirement. */
4674 ia_multi_vgt_param
.partial_es_wave
= false;
4675 if (radv_pipeline_has_gs(pipeline
) && device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4676 if (SI_GS_PER_ES
/ ia_multi_vgt_param
.primgroup_size
>= pipeline
->device
->gs_table_depth
- 3)
4677 ia_multi_vgt_param
.partial_es_wave
= true;
4679 ia_multi_vgt_param
.wd_switch_on_eop
= false;
4680 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4681 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
4682 * 4 shader engines. Set 1 to pass the assertion below.
4683 * The other cases are hardware requirements. */
4684 if (device
->physical_device
->rad_info
.max_se
< 4 ||
4685 prim
== V_008958_DI_PT_POLYGON
||
4686 prim
== V_008958_DI_PT_LINELOOP
||
4687 prim
== V_008958_DI_PT_TRIFAN
||
4688 prim
== V_008958_DI_PT_TRISTRIP_ADJ
||
4689 (pipeline
->graphics
.prim_restart_enable
&&
4690 (device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4691 (prim
!= V_008958_DI_PT_POINTLIST
&&
4692 prim
!= V_008958_DI_PT_LINESTRIP
))))
4693 ia_multi_vgt_param
.wd_switch_on_eop
= true;
4696 ia_multi_vgt_param
.ia_switch_on_eoi
= false;
4697 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.prim_id_input
)
4698 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4699 if (radv_pipeline_has_gs(pipeline
) &&
4700 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.uses_prim_id
)
4701 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4702 if (radv_pipeline_has_tess(pipeline
)) {
4703 /* SWITCH_ON_EOI must be set if PrimID is used. */
4704 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4705 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4706 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4709 ia_multi_vgt_param
.partial_vs_wave
= false;
4710 if (radv_pipeline_has_tess(pipeline
)) {
4711 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4712 if ((device
->physical_device
->rad_info
.family
== CHIP_TAHITI
||
4713 device
->physical_device
->rad_info
.family
== CHIP_PITCAIRN
||
4714 device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
) &&
4715 radv_pipeline_has_gs(pipeline
))
4716 ia_multi_vgt_param
.partial_vs_wave
= true;
4717 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4718 if (device
->physical_device
->rad_info
.has_distributed_tess
) {
4719 if (radv_pipeline_has_gs(pipeline
)) {
4720 if (device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4721 ia_multi_vgt_param
.partial_es_wave
= true;
4723 ia_multi_vgt_param
.partial_vs_wave
= true;
4728 /* Workaround for a VGT hang when strip primitive types are used with
4729 * primitive restart.
4731 if (pipeline
->graphics
.prim_restart_enable
&&
4732 (prim
== V_008958_DI_PT_LINESTRIP
||
4733 prim
== V_008958_DI_PT_TRISTRIP
||
4734 prim
== V_008958_DI_PT_LINESTRIP_ADJ
||
4735 prim
== V_008958_DI_PT_TRISTRIP_ADJ
)) {
4736 ia_multi_vgt_param
.partial_vs_wave
= true;
4739 if (radv_pipeline_has_gs(pipeline
)) {
4740 /* On these chips there is the possibility of a hang if the
4741 * pipeline uses a GS and partial_vs_wave is not set.
4743 * This mostly does not hit 4-SE chips, as those typically set
4744 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4745 * with GS due to another workaround.
4747 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4749 if (device
->physical_device
->rad_info
.family
== CHIP_TONGA
||
4750 device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
4751 device
->physical_device
->rad_info
.family
== CHIP_POLARIS10
||
4752 device
->physical_device
->rad_info
.family
== CHIP_POLARIS11
||
4753 device
->physical_device
->rad_info
.family
== CHIP_POLARIS12
||
4754 device
->physical_device
->rad_info
.family
== CHIP_VEGAM
) {
4755 ia_multi_vgt_param
.partial_vs_wave
= true;
4759 ia_multi_vgt_param
.base
=
4760 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param
.primgroup_size
- 1) |
4761 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4762 S_028AA8_MAX_PRIMGRP_IN_WAVE(device
->physical_device
->rad_info
.chip_class
== GFX8
? 2 : 0) |
4763 S_030960_EN_INST_OPT_BASIC(device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
4764 S_030960_EN_INST_OPT_ADV(device
->physical_device
->rad_info
.chip_class
>= GFX9
);
4766 return ia_multi_vgt_param
;
4771 radv_compute_vertex_input_state(struct radv_pipeline
*pipeline
,
4772 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4774 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
4775 pCreateInfo
->pVertexInputState
;
4776 struct radv_vertex_elements_info
*velems
= &pipeline
->vertex_elements
;
4778 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
4779 const VkVertexInputAttributeDescription
*desc
=
4780 &vi_info
->pVertexAttributeDescriptions
[i
];
4781 unsigned loc
= desc
->location
;
4782 const struct vk_format_description
*format_desc
;
4784 format_desc
= vk_format_description(desc
->format
);
4786 velems
->format_size
[loc
] = format_desc
->block
.bits
/ 8;
4789 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
4790 const VkVertexInputBindingDescription
*desc
=
4791 &vi_info
->pVertexBindingDescriptions
[i
];
4793 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
4794 pipeline
->num_vertex_bindings
=
4795 MAX2(pipeline
->num_vertex_bindings
, desc
->binding
+ 1);
4799 static struct radv_shader_variant
*
4800 radv_pipeline_get_streamout_shader(struct radv_pipeline
*pipeline
)
4804 for (i
= MESA_SHADER_GEOMETRY
; i
>= MESA_SHADER_VERTEX
; i
--) {
4805 struct radv_shader_variant
*shader
=
4806 radv_get_shader(pipeline
, i
);
4808 if (shader
&& shader
->info
.so
.num_outputs
> 0)
4816 radv_secure_compile(struct radv_pipeline
*pipeline
,
4817 struct radv_device
*device
,
4818 const struct radv_pipeline_key
*key
,
4819 const VkPipelineShaderStageCreateInfo
**pStages
,
4820 const VkPipelineCreateFlags flags
,
4821 unsigned num_stages
)
4823 uint8_t allowed_pipeline_hashes
[2][20];
4824 radv_hash_shaders(allowed_pipeline_hashes
[0], pStages
,
4825 pipeline
->layout
, key
, get_hash_flags(device
));
4827 /* Generate the GC copy hash */
4828 memcpy(allowed_pipeline_hashes
[1], allowed_pipeline_hashes
[0], 20);
4829 allowed_pipeline_hashes
[1][0] ^= 1;
4831 uint8_t allowed_hashes
[2][20];
4832 for (unsigned i
= 0; i
< 2; ++i
) {
4833 disk_cache_compute_key(device
->physical_device
->disk_cache
,
4834 allowed_pipeline_hashes
[i
], 20,
4838 /* Do an early exit if all cache entries are already there. */
4839 bool may_need_copy_shader
= pStages
[MESA_SHADER_GEOMETRY
];
4840 void *main_entry
= disk_cache_get(device
->physical_device
->disk_cache
, allowed_hashes
[0], NULL
);
4841 void *copy_entry
= NULL
;
4842 if (may_need_copy_shader
)
4843 copy_entry
= disk_cache_get(device
->physical_device
->disk_cache
, allowed_hashes
[1], NULL
);
4845 bool has_all_cache_entries
= main_entry
&& (!may_need_copy_shader
|| copy_entry
);
4849 if(has_all_cache_entries
)
4852 unsigned process
= 0;
4853 uint8_t sc_threads
= device
->instance
->num_sc_threads
;
4855 mtx_lock(&device
->sc_state
->secure_compile_mutex
);
4856 if (device
->sc_state
->secure_compile_thread_counter
< sc_threads
) {
4857 device
->sc_state
->secure_compile_thread_counter
++;
4858 for (unsigned i
= 0; i
< sc_threads
; i
++) {
4859 if (!device
->sc_state
->secure_compile_processes
[i
].in_use
) {
4860 device
->sc_state
->secure_compile_processes
[i
].in_use
= true;
4865 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
4868 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
4871 int fd_secure_input
= device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
;
4872 int fd_secure_output
= device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
;
4874 /* Fork a copy of the slim untainted secure compile process */
4875 enum radv_secure_compile_type sc_type
= RADV_SC_TYPE_FORK_DEVICE
;
4876 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
4878 if (!radv_sc_read(fd_secure_output
, &sc_type
, sizeof(sc_type
), true) ||
4879 sc_type
!= RADV_SC_TYPE_INIT_SUCCESS
)
4880 return VK_ERROR_DEVICE_LOST
;
4882 fd_secure_input
= device
->sc_state
->secure_compile_processes
[process
].fd_server
;
4883 fd_secure_output
= device
->sc_state
->secure_compile_processes
[process
].fd_client
;
4885 /* Write pipeline / shader module out to secure process via pipe */
4886 sc_type
= RADV_SC_TYPE_COMPILE_PIPELINE
;
4887 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
4889 /* Write pipeline layout out to secure process */
4890 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
4891 write(fd_secure_input
, layout
, sizeof(struct radv_pipeline_layout
));
4892 write(fd_secure_input
, &layout
->num_sets
, sizeof(uint32_t));
4893 for (uint32_t set
= 0; set
< layout
->num_sets
; set
++) {
4894 write(fd_secure_input
, &layout
->set
[set
].layout
->layout_size
, sizeof(uint32_t));
4895 write(fd_secure_input
, layout
->set
[set
].layout
, layout
->set
[set
].layout
->layout_size
);
4898 /* Write pipeline key out to secure process */
4899 write(fd_secure_input
, key
, sizeof(struct radv_pipeline_key
));
4901 /* Write pipeline create flags out to secure process */
4902 write(fd_secure_input
, &flags
, sizeof(VkPipelineCreateFlags
));
4904 /* Write stage and shader information out to secure process */
4905 write(fd_secure_input
, &num_stages
, sizeof(uint32_t));
4906 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
4910 /* Write stage out to secure process */
4911 gl_shader_stage stage
= ffs(pStages
[i
]->stage
) - 1;
4912 write(fd_secure_input
, &stage
, sizeof(gl_shader_stage
));
4914 /* Write entry point name out to secure process */
4915 size_t name_size
= strlen(pStages
[i
]->pName
) + 1;
4916 write(fd_secure_input
, &name_size
, sizeof(size_t));
4917 write(fd_secure_input
, pStages
[i
]->pName
, name_size
);
4919 /* Write shader module out to secure process */
4920 struct radv_shader_module
*module
= radv_shader_module_from_handle(pStages
[i
]->module
);
4921 assert(!module
->nir
);
4922 size_t module_size
= sizeof(struct radv_shader_module
) + module
->size
;
4923 write(fd_secure_input
, &module_size
, sizeof(size_t));
4924 write(fd_secure_input
, module
, module_size
);
4926 /* Write specialization info out to secure process */
4927 const VkSpecializationInfo
*specInfo
= pStages
[i
]->pSpecializationInfo
;
4928 bool has_spec_info
= specInfo
? true : false;
4929 write(fd_secure_input
, &has_spec_info
, sizeof(bool));
4931 write(fd_secure_input
, &specInfo
->dataSize
, sizeof(size_t));
4932 write(fd_secure_input
, specInfo
->pData
, specInfo
->dataSize
);
4934 write(fd_secure_input
, &specInfo
->mapEntryCount
, sizeof(uint32_t));
4935 for (uint32_t j
= 0; j
< specInfo
->mapEntryCount
; j
++)
4936 write(fd_secure_input
, &specInfo
->pMapEntries
[j
], sizeof(VkSpecializationMapEntry
));
4940 /* Read the data returned from the secure process */
4941 while (sc_type
!= RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED
) {
4942 if (!radv_sc_read(fd_secure_output
, &sc_type
, sizeof(sc_type
), true))
4943 return VK_ERROR_DEVICE_LOST
;
4945 if (sc_type
== RADV_SC_TYPE_WRITE_DISK_CACHE
) {
4946 assert(device
->physical_device
->disk_cache
);
4948 uint8_t disk_sha1
[20];
4949 if (!radv_sc_read(fd_secure_output
, disk_sha1
, sizeof(uint8_t) * 20, true))
4950 return VK_ERROR_DEVICE_LOST
;
4952 if (memcmp(disk_sha1
, allowed_hashes
[0], 20) &&
4953 memcmp(disk_sha1
, allowed_hashes
[1], 20))
4954 return VK_ERROR_DEVICE_LOST
;
4956 uint32_t entry_size
;
4957 if (!radv_sc_read(fd_secure_output
, &entry_size
, sizeof(uint32_t), true))
4958 return VK_ERROR_DEVICE_LOST
;
4960 struct cache_entry
*entry
= malloc(entry_size
);
4961 if (!radv_sc_read(fd_secure_output
, entry
, entry_size
, true))
4962 return VK_ERROR_DEVICE_LOST
;
4964 disk_cache_put(device
->physical_device
->disk_cache
,
4965 disk_sha1
, entry
, entry_size
,
4969 } else if (sc_type
== RADV_SC_TYPE_READ_DISK_CACHE
) {
4970 uint8_t disk_sha1
[20];
4971 if (!radv_sc_read(fd_secure_output
, disk_sha1
, sizeof(uint8_t) * 20, true))
4972 return VK_ERROR_DEVICE_LOST
;
4974 if (memcmp(disk_sha1
, allowed_hashes
[0], 20) &&
4975 memcmp(disk_sha1
, allowed_hashes
[1], 20))
4976 return VK_ERROR_DEVICE_LOST
;
4979 struct cache_entry
*entry
= (struct cache_entry
*)
4980 disk_cache_get(device
->physical_device
->disk_cache
,
4983 uint8_t found
= entry
? 1 : 0;
4984 write(fd_secure_input
, &found
, sizeof(uint8_t));
4987 write(fd_secure_input
, &size
, sizeof(size_t));
4988 write(fd_secure_input
, entry
, size
);
4995 sc_type
= RADV_SC_TYPE_DESTROY_DEVICE
;
4996 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
4998 mtx_lock(&device
->sc_state
->secure_compile_mutex
);
4999 device
->sc_state
->secure_compile_thread_counter
--;
5000 device
->sc_state
->secure_compile_processes
[process
].in_use
= false;
5001 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
5007 radv_pipeline_init(struct radv_pipeline
*pipeline
,
5008 struct radv_device
*device
,
5009 struct radv_pipeline_cache
*cache
,
5010 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
5011 const struct radv_graphics_pipeline_create_info
*extra
)
5014 bool has_view_index
= false;
5016 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
5017 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
5018 if (subpass
->view_mask
)
5019 has_view_index
= true;
5021 pipeline
->device
= device
;
5022 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
5023 assert(pipeline
->layout
);
5025 struct radv_blend_state blend
= radv_pipeline_init_blend_state(pipeline
, pCreateInfo
, extra
);
5027 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
5028 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
5029 radv_init_feedback(creation_feedback
);
5031 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
5033 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
5034 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
5035 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
5036 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
5037 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
5038 if(creation_feedback
)
5039 stage_feedbacks
[stage
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[i
];
5042 struct radv_pipeline_key key
= radv_generate_graphics_pipeline_key(pipeline
, pCreateInfo
, &blend
, has_view_index
);
5043 if (radv_device_use_secure_compile(device
->instance
)) {
5044 return radv_secure_compile(pipeline
, device
, &key
, pStages
, pCreateInfo
->flags
, pCreateInfo
->stageCount
);
5046 radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
, pCreateInfo
->flags
, pipeline_feedback
, stage_feedbacks
);
5049 pipeline
->graphics
.spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
5050 radv_pipeline_init_multisample_state(pipeline
, &blend
, pCreateInfo
);
5052 uint32_t prim
= si_translate_prim(pCreateInfo
->pInputAssemblyState
->topology
);
5054 pipeline
->graphics
.topology
= pCreateInfo
->pInputAssemblyState
->topology
;
5055 pipeline
->graphics
.can_use_guardband
= radv_prim_can_use_guardband(pCreateInfo
->pInputAssemblyState
->topology
);
5057 if (radv_pipeline_has_gs(pipeline
)) {
5058 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs
.output_prim
);
5059 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
5060 } else if (radv_pipeline_has_tess(pipeline
)) {
5061 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.point_mode
)
5062 gs_out
= V_028A6C_OUTPRIM_TYPE_POINTLIST
;
5064 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.primitive_mode
);
5065 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
5067 gs_out
= si_conv_prim_to_gs_out(pCreateInfo
->pInputAssemblyState
->topology
);
5069 if (extra
&& extra
->use_rectlist
) {
5070 prim
= V_008958_DI_PT_RECTLIST
;
5071 gs_out
= V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
5072 pipeline
->graphics
.can_use_guardband
= true;
5073 if (radv_pipeline_has_ngg(pipeline
))
5074 gs_out
= V_028A6C_VGT_OUT_RECT_V0
;
5076 pipeline
->graphics
.prim_restart_enable
= !!pCreateInfo
->pInputAssemblyState
->primitiveRestartEnable
;
5077 /* prim vertex count will need TESS changes */
5078 pipeline
->graphics
.prim_vertex_count
= prim_size_table
[prim
];
5080 radv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
);
5082 /* Ensure that some export memory is always allocated, for two reasons:
5084 * 1) Correctness: The hardware ignores the EXEC mask if no export
5085 * memory is allocated, so KILL and alpha test do not work correctly
5087 * 2) Performance: Every shader needs at least a NULL export, even when
5088 * it writes no color/depth output. The NULL export instruction
5089 * stalls without this setting.
5091 * Don't add this to CB_SHADER_MASK.
5093 * GFX10 supports pixel shaders without exports by setting both the
5094 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
5095 * instructions if any are present.
5097 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
5098 if ((pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX9
||
5099 ps
->info
.ps
.can_discard
) &&
5100 !blend
.spi_shader_col_format
) {
5101 if (!ps
->info
.ps
.writes_z
&&
5102 !ps
->info
.ps
.writes_stencil
&&
5103 !ps
->info
.ps
.writes_sample_mask
)
5104 blend
.spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
5107 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
5108 if (pipeline
->shaders
[i
]) {
5109 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[i
]->info
.need_indirect_descriptor_sets
;
5113 if (radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
5114 struct radv_shader_variant
*gs
=
5115 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
5117 calculate_gs_ring_sizes(pipeline
, &gs
->info
.gs_ring_info
);
5120 struct radv_tessellation_state tess
= {0};
5121 if (radv_pipeline_has_tess(pipeline
)) {
5122 if (prim
== V_008958_DI_PT_PATCH
) {
5123 pipeline
->graphics
.prim_vertex_count
.min
= pCreateInfo
->pTessellationState
->patchControlPoints
;
5124 pipeline
->graphics
.prim_vertex_count
.incr
= 1;
5126 tess
= calculate_tess_state(pipeline
, pCreateInfo
);
5129 pipeline
->graphics
.ia_multi_vgt_param
= radv_compute_ia_multi_vgt_param_helpers(pipeline
, &tess
, prim
);
5131 radv_compute_vertex_input_state(pipeline
, pCreateInfo
);
5133 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++)
5134 pipeline
->user_data_0
[i
] = radv_pipeline_stage_to_user_data_0(pipeline
, i
, device
->physical_device
->rad_info
.chip_class
);
5136 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
,
5137 AC_UD_VS_BASE_VERTEX_START_INSTANCE
);
5138 if (loc
->sgpr_idx
!= -1) {
5139 pipeline
->graphics
.vtx_base_sgpr
= pipeline
->user_data_0
[MESA_SHADER_VERTEX
];
5140 pipeline
->graphics
.vtx_base_sgpr
+= loc
->sgpr_idx
* 4;
5141 if (radv_get_shader(pipeline
, MESA_SHADER_VERTEX
)->info
.vs
.needs_draw_id
)
5142 pipeline
->graphics
.vtx_emit_num
= 3;
5144 pipeline
->graphics
.vtx_emit_num
= 2;
5147 /* Find the last vertex shader stage that eventually uses streamout. */
5148 pipeline
->streamout_shader
= radv_pipeline_get_streamout_shader(pipeline
);
5150 result
= radv_pipeline_scratch_init(device
, pipeline
);
5151 radv_pipeline_generate_pm4(pipeline
, pCreateInfo
, extra
, &blend
, &tess
, prim
, gs_out
);
5157 radv_graphics_pipeline_create(
5159 VkPipelineCache _cache
,
5160 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
5161 const struct radv_graphics_pipeline_create_info
*extra
,
5162 const VkAllocationCallbacks
*pAllocator
,
5163 VkPipeline
*pPipeline
)
5165 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5166 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
5167 struct radv_pipeline
*pipeline
;
5170 pipeline
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
5171 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5172 if (pipeline
== NULL
)
5173 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5175 result
= radv_pipeline_init(pipeline
, device
, cache
,
5176 pCreateInfo
, extra
);
5177 if (result
!= VK_SUCCESS
) {
5178 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5182 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5187 VkResult
radv_CreateGraphicsPipelines(
5189 VkPipelineCache pipelineCache
,
5191 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
5192 const VkAllocationCallbacks
* pAllocator
,
5193 VkPipeline
* pPipelines
)
5195 VkResult result
= VK_SUCCESS
;
5198 for (; i
< count
; i
++) {
5200 r
= radv_graphics_pipeline_create(_device
,
5203 NULL
, pAllocator
, &pPipelines
[i
]);
5204 if (r
!= VK_SUCCESS
) {
5206 pPipelines
[i
] = VK_NULL_HANDLE
;
5215 radv_compute_generate_pm4(struct radv_pipeline
*pipeline
)
5217 struct radv_shader_variant
*compute_shader
;
5218 struct radv_device
*device
= pipeline
->device
;
5219 unsigned threads_per_threadgroup
;
5220 unsigned threadgroups_per_cu
= 1;
5221 unsigned waves_per_threadgroup
;
5222 unsigned max_waves_per_sh
= 0;
5225 pipeline
->cs
.max_dw
= device
->physical_device
->rad_info
.chip_class
>= GFX10
? 22 : 20;
5226 pipeline
->cs
.buf
= malloc(pipeline
->cs
.max_dw
* 4);
5228 compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
5229 va
= radv_buffer_get_va(compute_shader
->bo
) + compute_shader
->bo_offset
;
5231 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B830_COMPUTE_PGM_LO
, 2);
5232 radeon_emit(&pipeline
->cs
, va
>> 8);
5233 radeon_emit(&pipeline
->cs
, S_00B834_DATA(va
>> 40));
5235 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
5236 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc1
);
5237 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc2
);
5238 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
5239 radeon_set_sh_reg(&pipeline
->cs
, R_00B8A0_COMPUTE_PGM_RSRC3
, compute_shader
->config
.rsrc3
);
5242 /* Calculate best compute resource limits. */
5243 threads_per_threadgroup
= compute_shader
->info
.cs
.block_size
[0] *
5244 compute_shader
->info
.cs
.block_size
[1] *
5245 compute_shader
->info
.cs
.block_size
[2];
5246 waves_per_threadgroup
= DIV_ROUND_UP(threads_per_threadgroup
,
5247 compute_shader
->info
.wave_size
);
5249 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
5250 waves_per_threadgroup
== 1)
5251 threadgroups_per_cu
= 2;
5253 radeon_set_sh_reg(&pipeline
->cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
5254 ac_get_compute_resource_limits(&device
->physical_device
->rad_info
,
5255 waves_per_threadgroup
,
5257 threadgroups_per_cu
));
5259 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
5260 radeon_emit(&pipeline
->cs
,
5261 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]));
5262 radeon_emit(&pipeline
->cs
,
5263 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]));
5264 radeon_emit(&pipeline
->cs
,
5265 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]));
5267 assert(pipeline
->cs
.cdw
<= pipeline
->cs
.max_dw
);
5270 static struct radv_pipeline_key
5271 radv_generate_compute_pipeline_key(struct radv_pipeline
*pipeline
,
5272 const VkComputePipelineCreateInfo
*pCreateInfo
)
5274 const VkPipelineShaderStageCreateInfo
*stage
= &pCreateInfo
->stage
;
5275 struct radv_pipeline_key key
;
5276 memset(&key
, 0, sizeof(key
));
5278 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
5279 key
.optimisations_disabled
= 1;
5281 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*subgroup_size
=
5282 vk_find_struct_const(stage
->pNext
,
5283 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT
);
5285 if (subgroup_size
) {
5286 assert(subgroup_size
->requiredSubgroupSize
== 32 ||
5287 subgroup_size
->requiredSubgroupSize
== 64);
5288 key
.compute_subgroup_size
= subgroup_size
->requiredSubgroupSize
;
5294 static VkResult
radv_compute_pipeline_create(
5296 VkPipelineCache _cache
,
5297 const VkComputePipelineCreateInfo
* pCreateInfo
,
5298 const VkAllocationCallbacks
* pAllocator
,
5299 VkPipeline
* pPipeline
)
5301 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5302 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
5303 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
5304 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
5305 struct radv_pipeline
*pipeline
;
5308 pipeline
= vk_zalloc2(&device
->alloc
, pAllocator
, sizeof(*pipeline
), 8,
5309 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5310 if (pipeline
== NULL
)
5311 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5313 pipeline
->device
= device
;
5314 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
5315 assert(pipeline
->layout
);
5317 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
5318 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
5319 radv_init_feedback(creation_feedback
);
5321 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
5322 if (creation_feedback
)
5323 stage_feedbacks
[MESA_SHADER_COMPUTE
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[0];
5325 pStages
[MESA_SHADER_COMPUTE
] = &pCreateInfo
->stage
;
5327 struct radv_pipeline_key key
=
5328 radv_generate_compute_pipeline_key(pipeline
, pCreateInfo
);
5330 if (radv_device_use_secure_compile(device
->instance
)) {
5331 result
= radv_secure_compile(pipeline
, device
, &key
, pStages
, pCreateInfo
->flags
, 1);
5332 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5336 radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
, pCreateInfo
->flags
, pipeline_feedback
, stage_feedbacks
);
5339 pipeline
->user_data_0
[MESA_SHADER_COMPUTE
] = radv_pipeline_stage_to_user_data_0(pipeline
, MESA_SHADER_COMPUTE
, device
->physical_device
->rad_info
.chip_class
);
5340 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.need_indirect_descriptor_sets
;
5341 result
= radv_pipeline_scratch_init(device
, pipeline
);
5342 if (result
!= VK_SUCCESS
) {
5343 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5347 radv_compute_generate_pm4(pipeline
);
5349 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5354 VkResult
radv_CreateComputePipelines(
5356 VkPipelineCache pipelineCache
,
5358 const VkComputePipelineCreateInfo
* pCreateInfos
,
5359 const VkAllocationCallbacks
* pAllocator
,
5360 VkPipeline
* pPipelines
)
5362 VkResult result
= VK_SUCCESS
;
5365 for (; i
< count
; i
++) {
5367 r
= radv_compute_pipeline_create(_device
, pipelineCache
,
5369 pAllocator
, &pPipelines
[i
]);
5370 if (r
!= VK_SUCCESS
) {
5372 pPipelines
[i
] = VK_NULL_HANDLE
;
5380 static uint32_t radv_get_executable_count(const struct radv_pipeline
*pipeline
)
5383 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5384 if (!pipeline
->shaders
[i
])
5387 if (i
== MESA_SHADER_GEOMETRY
&&
5388 !radv_pipeline_has_ngg(pipeline
)) {
5398 static struct radv_shader_variant
*
5399 radv_get_shader_from_executable_index(const struct radv_pipeline
*pipeline
, int index
, gl_shader_stage
*stage
)
5401 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5402 if (!pipeline
->shaders
[i
])
5406 return pipeline
->shaders
[i
];
5411 if (i
== MESA_SHADER_GEOMETRY
&&
5412 !radv_pipeline_has_ngg(pipeline
)) {
5415 return pipeline
->gs_copy_shader
;
5425 /* Basically strlcpy (which does not exist on linux) specialized for
5427 static void desc_copy(char *desc
, const char *src
) {
5428 int len
= strlen(src
);
5429 assert(len
< VK_MAX_DESCRIPTION_SIZE
);
5430 memcpy(desc
, src
, len
);
5431 memset(desc
+ len
, 0, VK_MAX_DESCRIPTION_SIZE
- len
);
5434 VkResult
radv_GetPipelineExecutablePropertiesKHR(
5436 const VkPipelineInfoKHR
* pPipelineInfo
,
5437 uint32_t* pExecutableCount
,
5438 VkPipelineExecutablePropertiesKHR
* pProperties
)
5440 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pPipelineInfo
->pipeline
);
5441 const uint32_t total_count
= radv_get_executable_count(pipeline
);
5444 *pExecutableCount
= total_count
;
5448 const uint32_t count
= MIN2(total_count
, *pExecutableCount
);
5449 for (unsigned i
= 0, executable_idx
= 0;
5450 i
< MESA_SHADER_STAGES
&& executable_idx
< count
; ++i
) {
5451 if (!pipeline
->shaders
[i
])
5453 pProperties
[executable_idx
].stages
= mesa_to_vk_shader_stage(i
);
5454 const char *name
= NULL
;
5455 const char *description
= NULL
;
5457 case MESA_SHADER_VERTEX
:
5458 name
= "Vertex Shader";
5459 description
= "Vulkan Vertex Shader";
5461 case MESA_SHADER_TESS_CTRL
:
5462 if (!pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5463 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5464 name
= "Vertex + Tessellation Control Shaders";
5465 description
= "Combined Vulkan Vertex and Tessellation Control Shaders";
5467 name
= "Tessellation Control Shader";
5468 description
= "Vulkan Tessellation Control Shader";
5471 case MESA_SHADER_TESS_EVAL
:
5472 name
= "Tessellation Evaluation Shader";
5473 description
= "Vulkan Tessellation Evaluation Shader";
5475 case MESA_SHADER_GEOMETRY
:
5476 if (radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]) {
5477 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
;
5478 name
= "Tessellation Evaluation + Geometry Shaders";
5479 description
= "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5480 } else if (!radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5481 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5482 name
= "Vertex + Geometry Shader";
5483 description
= "Combined Vulkan Vertex and Geometry Shaders";
5485 name
= "Geometry Shader";
5486 description
= "Vulkan Geometry Shader";
5489 case MESA_SHADER_FRAGMENT
:
5490 name
= "Fragment Shader";
5491 description
= "Vulkan Fragment Shader";
5493 case MESA_SHADER_COMPUTE
:
5494 name
= "Compute Shader";
5495 description
= "Vulkan Compute Shader";
5499 pProperties
[executable_idx
].subgroupSize
= pipeline
->shaders
[i
]->info
.wave_size
;
5500 desc_copy(pProperties
[executable_idx
].name
, name
);
5501 desc_copy(pProperties
[executable_idx
].description
, description
);
5504 if (i
== MESA_SHADER_GEOMETRY
&&
5505 !radv_pipeline_has_ngg(pipeline
)) {
5506 assert(pipeline
->gs_copy_shader
);
5507 if (executable_idx
>= count
)
5510 pProperties
[executable_idx
].stages
= VK_SHADER_STAGE_GEOMETRY_BIT
;
5511 pProperties
[executable_idx
].subgroupSize
= 64;
5512 desc_copy(pProperties
[executable_idx
].name
, "GS Copy Shader");
5513 desc_copy(pProperties
[executable_idx
].description
,
5514 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5520 VkResult result
= *pExecutableCount
< total_count
? VK_INCOMPLETE
: VK_SUCCESS
;
5521 *pExecutableCount
= count
;
5525 VkResult
radv_GetPipelineExecutableStatisticsKHR(
5527 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5528 uint32_t* pStatisticCount
,
5529 VkPipelineExecutableStatisticKHR
* pStatistics
)
5531 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5532 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5533 gl_shader_stage stage
;
5534 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5536 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
5537 unsigned lds_increment
= chip_class
>= GFX7
? 512 : 256;
5538 unsigned max_waves
= radv_get_max_waves(device
, shader
, stage
);
5540 VkPipelineExecutableStatisticKHR
*s
= pStatistics
;
5541 VkPipelineExecutableStatisticKHR
*end
= s
+ (pStatistics
? *pStatisticCount
: 0);
5542 VkResult result
= VK_SUCCESS
;
5545 desc_copy(s
->name
, "SGPRs");
5546 desc_copy(s
->description
, "Number of SGPR registers allocated per subgroup");
5547 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5548 s
->value
.u64
= shader
->config
.num_sgprs
;
5553 desc_copy(s
->name
, "VGPRs");
5554 desc_copy(s
->description
, "Number of VGPR registers allocated per subgroup");
5555 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5556 s
->value
.u64
= shader
->config
.num_vgprs
;
5561 desc_copy(s
->name
, "Spilled SGPRs");
5562 desc_copy(s
->description
, "Number of SGPR registers spilled per subgroup");
5563 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5564 s
->value
.u64
= shader
->config
.spilled_sgprs
;
5569 desc_copy(s
->name
, "Spilled VGPRs");
5570 desc_copy(s
->description
, "Number of VGPR registers spilled per subgroup");
5571 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5572 s
->value
.u64
= shader
->config
.spilled_vgprs
;
5577 desc_copy(s
->name
, "PrivMem VGPRs");
5578 desc_copy(s
->description
, "Number of VGPRs stored in private memory per subgroup");
5579 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5580 s
->value
.u64
= shader
->info
.private_mem_vgprs
;
5585 desc_copy(s
->name
, "Code size");
5586 desc_copy(s
->description
, "Code size in bytes");
5587 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5588 s
->value
.u64
= shader
->exec_size
;
5593 desc_copy(s
->name
, "LDS size");
5594 desc_copy(s
->description
, "LDS size in bytes per workgroup");
5595 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5596 s
->value
.u64
= shader
->config
.lds_size
* lds_increment
;
5601 desc_copy(s
->name
, "Scratch size");
5602 desc_copy(s
->description
, "Private memory in bytes per subgroup");
5603 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5604 s
->value
.u64
= shader
->config
.scratch_bytes_per_wave
;
5609 desc_copy(s
->name
, "Subgroups per SIMD");
5610 desc_copy(s
->description
, "The maximum number of subgroups in flight on a SIMD unit");
5611 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5612 s
->value
.u64
= max_waves
;
5617 *pStatisticCount
= s
- pStatistics
;
5619 *pStatisticCount
= end
- pStatistics
;
5620 result
= VK_INCOMPLETE
;
5622 *pStatisticCount
= s
- pStatistics
;
5628 static VkResult
radv_copy_representation(void *data
, size_t *data_size
, const char *src
)
5630 size_t total_size
= strlen(src
) + 1;
5633 *data_size
= total_size
;
5637 size_t size
= MIN2(total_size
, *data_size
);
5639 memcpy(data
, src
, size
);
5641 *((char*)data
+ size
- 1) = 0;
5642 return size
< total_size
? VK_INCOMPLETE
: VK_SUCCESS
;
5645 VkResult
radv_GetPipelineExecutableInternalRepresentationsKHR(
5647 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5648 uint32_t* pInternalRepresentationCount
,
5649 VkPipelineExecutableInternalRepresentationKHR
* pInternalRepresentations
)
5651 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5652 gl_shader_stage stage
;
5653 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5655 VkPipelineExecutableInternalRepresentationKHR
*p
= pInternalRepresentations
;
5656 VkPipelineExecutableInternalRepresentationKHR
*end
= p
+ (pInternalRepresentations
? *pInternalRepresentationCount
: 0);
5657 VkResult result
= VK_SUCCESS
;
5661 desc_copy(p
->name
, "NIR Shader(s)");
5662 desc_copy(p
->description
, "The optimized NIR shader(s)");
5663 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->nir_string
) != VK_SUCCESS
)
5664 result
= VK_INCOMPLETE
;
5671 if (shader
->aco_used
) {
5672 desc_copy(p
->name
, "ACO IR");
5673 desc_copy(p
->description
, "The ACO IR after some optimizations");
5675 desc_copy(p
->name
, "LLVM IR");
5676 desc_copy(p
->description
, "The LLVM IR after some optimizations");
5678 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->ir_string
) != VK_SUCCESS
)
5679 result
= VK_INCOMPLETE
;
5686 desc_copy(p
->name
, "Assembly");
5687 desc_copy(p
->description
, "Final Assembly");
5688 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->disasm_string
) != VK_SUCCESS
)
5689 result
= VK_INCOMPLETE
;
5693 if (!pInternalRepresentations
)
5694 *pInternalRepresentationCount
= p
- pInternalRepresentations
;
5696 result
= VK_INCOMPLETE
;
5697 *pInternalRepresentationCount
= end
- pInternalRepresentations
;
5699 *pInternalRepresentationCount
= p
- pInternalRepresentations
;