2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
34 #include "radv_shader.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
48 #include "ac_shader_util.h"
50 struct radv_blend_state
{
51 uint32_t blend_enable_4bit
;
52 uint32_t need_src_alpha
;
54 uint32_t cb_color_control
;
55 uint32_t cb_target_mask
;
56 uint32_t cb_target_enabled_4bit
;
57 uint32_t sx_mrt_blend_opt
[8];
58 uint32_t cb_blend_control
[8];
60 uint32_t spi_shader_col_format
;
61 uint32_t cb_shader_mask
;
62 uint32_t db_alpha_to_mask
;
64 uint32_t commutative_4bit
;
66 bool single_cb_enable
;
67 bool mrt0_is_dual_src
;
70 struct radv_dsa_order_invariance
{
71 /* Whether the final result in Z/S buffers is guaranteed to be
72 * invariant under changes to the order in which fragments arrive.
76 /* Whether the set of fragments that pass the combined Z/S test is
77 * guaranteed to be invariant under changes to the order in which
83 struct radv_tessellation_state
{
84 uint32_t ls_hs_config
;
90 static const VkPipelineMultisampleStateCreateInfo
*
91 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
93 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
94 return pCreateInfo
->pMultisampleState
;
98 static const VkPipelineTessellationStateCreateInfo
*
99 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
101 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
102 if (pCreateInfo
->pStages
[i
].stage
== VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
||
103 pCreateInfo
->pStages
[i
].stage
== VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
) {
104 return pCreateInfo
->pTessellationState
;
110 static const VkPipelineDepthStencilStateCreateInfo
*
111 radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
113 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
114 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
116 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
117 subpass
->depth_stencil_attachment
)
118 return pCreateInfo
->pDepthStencilState
;
122 static const VkPipelineColorBlendStateCreateInfo
*
123 radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
125 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
126 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
128 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
129 subpass
->has_color_att
)
130 return pCreateInfo
->pColorBlendState
;
134 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
)
136 struct radv_shader_variant
*variant
= NULL
;
137 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
138 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
139 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
140 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
141 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
142 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
145 return variant
->info
.is_ngg
;
148 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline
*pipeline
)
150 assert(radv_pipeline_has_ngg(pipeline
));
152 struct radv_shader_variant
*variant
= NULL
;
153 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
154 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
155 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
156 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
157 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
158 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
161 return variant
->info
.is_ngg_passthrough
;
164 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
)
166 if (!radv_pipeline_has_gs(pipeline
))
169 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
170 * On GFX10, it might be required in rare cases if it's not possible to
173 if (radv_pipeline_has_ngg(pipeline
))
176 assert(pipeline
->gs_copy_shader
);
181 radv_pipeline_destroy(struct radv_device
*device
,
182 struct radv_pipeline
*pipeline
,
183 const VkAllocationCallbacks
* allocator
)
185 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
186 if (pipeline
->shaders
[i
])
187 radv_shader_variant_destroy(device
, pipeline
->shaders
[i
]);
189 if (pipeline
->gs_copy_shader
)
190 radv_shader_variant_destroy(device
, pipeline
->gs_copy_shader
);
193 free(pipeline
->cs
.buf
);
194 vk_free2(&device
->vk
.alloc
, allocator
, pipeline
);
197 void radv_DestroyPipeline(
199 VkPipeline _pipeline
,
200 const VkAllocationCallbacks
* pAllocator
)
202 RADV_FROM_HANDLE(radv_device
, device
, _device
);
203 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
208 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
211 static uint32_t get_hash_flags(struct radv_device
*device
)
213 uint32_t hash_flags
= 0;
215 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_NGG
)
216 hash_flags
|= RADV_HASH_SHADER_NO_NGG
;
217 if (device
->physical_device
->cs_wave_size
== 32)
218 hash_flags
|= RADV_HASH_SHADER_CS_WAVE32
;
219 if (device
->physical_device
->ps_wave_size
== 32)
220 hash_flags
|= RADV_HASH_SHADER_PS_WAVE32
;
221 if (device
->physical_device
->ge_wave_size
== 32)
222 hash_flags
|= RADV_HASH_SHADER_GE_WAVE32
;
223 if (device
->physical_device
->use_aco
)
224 hash_flags
|= RADV_HASH_SHADER_ACO
;
229 radv_pipeline_scratch_init(struct radv_device
*device
,
230 struct radv_pipeline
*pipeline
)
232 unsigned scratch_bytes_per_wave
= 0;
233 unsigned max_waves
= 0;
234 unsigned min_waves
= 1;
236 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
237 if (pipeline
->shaders
[i
] &&
238 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
) {
239 unsigned max_stage_waves
= device
->scratch_waves
;
241 scratch_bytes_per_wave
= MAX2(scratch_bytes_per_wave
,
242 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
);
244 max_stage_waves
= MIN2(max_stage_waves
,
245 4 * device
->physical_device
->rad_info
.num_good_compute_units
*
246 (256 / pipeline
->shaders
[i
]->config
.num_vgprs
));
247 max_waves
= MAX2(max_waves
, max_stage_waves
);
251 if (pipeline
->shaders
[MESA_SHADER_COMPUTE
]) {
252 unsigned group_size
= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[0] *
253 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[1] *
254 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[2];
255 min_waves
= MAX2(min_waves
, round_up_u32(group_size
, 64));
258 pipeline
->scratch_bytes_per_wave
= scratch_bytes_per_wave
;
259 pipeline
->max_waves
= max_waves
;
263 static uint32_t si_translate_blend_logic_op(VkLogicOp op
)
266 case VK_LOGIC_OP_CLEAR
:
267 return V_028808_ROP3_CLEAR
;
268 case VK_LOGIC_OP_AND
:
269 return V_028808_ROP3_AND
;
270 case VK_LOGIC_OP_AND_REVERSE
:
271 return V_028808_ROP3_AND_REVERSE
;
272 case VK_LOGIC_OP_COPY
:
273 return V_028808_ROP3_COPY
;
274 case VK_LOGIC_OP_AND_INVERTED
:
275 return V_028808_ROP3_AND_INVERTED
;
276 case VK_LOGIC_OP_NO_OP
:
277 return V_028808_ROP3_NO_OP
;
278 case VK_LOGIC_OP_XOR
:
279 return V_028808_ROP3_XOR
;
281 return V_028808_ROP3_OR
;
282 case VK_LOGIC_OP_NOR
:
283 return V_028808_ROP3_NOR
;
284 case VK_LOGIC_OP_EQUIVALENT
:
285 return V_028808_ROP3_EQUIVALENT
;
286 case VK_LOGIC_OP_INVERT
:
287 return V_028808_ROP3_INVERT
;
288 case VK_LOGIC_OP_OR_REVERSE
:
289 return V_028808_ROP3_OR_REVERSE
;
290 case VK_LOGIC_OP_COPY_INVERTED
:
291 return V_028808_ROP3_COPY_INVERTED
;
292 case VK_LOGIC_OP_OR_INVERTED
:
293 return V_028808_ROP3_OR_INVERTED
;
294 case VK_LOGIC_OP_NAND
:
295 return V_028808_ROP3_NAND
;
296 case VK_LOGIC_OP_SET
:
297 return V_028808_ROP3_SET
;
299 unreachable("Unhandled logic op");
304 static uint32_t si_translate_blend_function(VkBlendOp op
)
307 case VK_BLEND_OP_ADD
:
308 return V_028780_COMB_DST_PLUS_SRC
;
309 case VK_BLEND_OP_SUBTRACT
:
310 return V_028780_COMB_SRC_MINUS_DST
;
311 case VK_BLEND_OP_REVERSE_SUBTRACT
:
312 return V_028780_COMB_DST_MINUS_SRC
;
313 case VK_BLEND_OP_MIN
:
314 return V_028780_COMB_MIN_DST_SRC
;
315 case VK_BLEND_OP_MAX
:
316 return V_028780_COMB_MAX_DST_SRC
;
322 static uint32_t si_translate_blend_factor(VkBlendFactor factor
)
325 case VK_BLEND_FACTOR_ZERO
:
326 return V_028780_BLEND_ZERO
;
327 case VK_BLEND_FACTOR_ONE
:
328 return V_028780_BLEND_ONE
;
329 case VK_BLEND_FACTOR_SRC_COLOR
:
330 return V_028780_BLEND_SRC_COLOR
;
331 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
332 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
333 case VK_BLEND_FACTOR_DST_COLOR
:
334 return V_028780_BLEND_DST_COLOR
;
335 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
336 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
337 case VK_BLEND_FACTOR_SRC_ALPHA
:
338 return V_028780_BLEND_SRC_ALPHA
;
339 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
340 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
341 case VK_BLEND_FACTOR_DST_ALPHA
:
342 return V_028780_BLEND_DST_ALPHA
;
343 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
344 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
345 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
346 return V_028780_BLEND_CONSTANT_COLOR
;
347 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
348 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
349 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
350 return V_028780_BLEND_CONSTANT_ALPHA
;
351 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
352 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
353 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
354 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
355 case VK_BLEND_FACTOR_SRC1_COLOR
:
356 return V_028780_BLEND_SRC1_COLOR
;
357 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
358 return V_028780_BLEND_INV_SRC1_COLOR
;
359 case VK_BLEND_FACTOR_SRC1_ALPHA
:
360 return V_028780_BLEND_SRC1_ALPHA
;
361 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
362 return V_028780_BLEND_INV_SRC1_ALPHA
;
368 static uint32_t si_translate_blend_opt_function(VkBlendOp op
)
371 case VK_BLEND_OP_ADD
:
372 return V_028760_OPT_COMB_ADD
;
373 case VK_BLEND_OP_SUBTRACT
:
374 return V_028760_OPT_COMB_SUBTRACT
;
375 case VK_BLEND_OP_REVERSE_SUBTRACT
:
376 return V_028760_OPT_COMB_REVSUBTRACT
;
377 case VK_BLEND_OP_MIN
:
378 return V_028760_OPT_COMB_MIN
;
379 case VK_BLEND_OP_MAX
:
380 return V_028760_OPT_COMB_MAX
;
382 return V_028760_OPT_COMB_BLEND_DISABLED
;
386 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor
, bool is_alpha
)
389 case VK_BLEND_FACTOR_ZERO
:
390 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
391 case VK_BLEND_FACTOR_ONE
:
392 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
393 case VK_BLEND_FACTOR_SRC_COLOR
:
394 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
395 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
396 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
397 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
398 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
399 case VK_BLEND_FACTOR_SRC_ALPHA
:
400 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
401 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
402 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
403 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
404 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
405 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
407 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
412 * Get rid of DST in the blend factors by commuting the operands:
413 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
415 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
416 unsigned *dst_factor
, unsigned expected_dst
,
417 unsigned replacement_src
)
419 if (*src_factor
== expected_dst
&&
420 *dst_factor
== VK_BLEND_FACTOR_ZERO
) {
421 *src_factor
= VK_BLEND_FACTOR_ZERO
;
422 *dst_factor
= replacement_src
;
424 /* Commuting the operands requires reversing subtractions. */
425 if (*func
== VK_BLEND_OP_SUBTRACT
)
426 *func
= VK_BLEND_OP_REVERSE_SUBTRACT
;
427 else if (*func
== VK_BLEND_OP_REVERSE_SUBTRACT
)
428 *func
= VK_BLEND_OP_SUBTRACT
;
432 static bool si_blend_factor_uses_dst(unsigned factor
)
434 return factor
== VK_BLEND_FACTOR_DST_COLOR
||
435 factor
== VK_BLEND_FACTOR_DST_ALPHA
||
436 factor
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
437 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
||
438 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
;
441 static bool is_dual_src(VkBlendFactor factor
)
444 case VK_BLEND_FACTOR_SRC1_COLOR
:
445 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
446 case VK_BLEND_FACTOR_SRC1_ALPHA
:
447 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
454 static unsigned si_choose_spi_color_format(VkFormat vk_format
,
456 bool blend_need_alpha
)
458 const struct vk_format_description
*desc
= vk_format_description(vk_format
);
459 unsigned format
, ntype
, swap
;
461 /* Alpha is needed for alpha-to-coverage.
462 * Blending may be with or without alpha.
464 unsigned normal
= 0; /* most optimal, may not support blending or export alpha */
465 unsigned alpha
= 0; /* exports alpha, but may not support blending */
466 unsigned blend
= 0; /* supports blending, but may not export alpha */
467 unsigned blend_alpha
= 0; /* least optimal, supports blending and exports alpha */
469 format
= radv_translate_colorformat(vk_format
);
470 ntype
= radv_translate_color_numformat(vk_format
, desc
,
471 vk_format_get_first_non_void_channel(vk_format
));
472 swap
= radv_translate_colorswap(vk_format
, false);
474 /* Choose the SPI color formats. These are required values for Stoney/RB+.
475 * Other chips have multiple choices, though they are not necessarily better.
478 case V_028C70_COLOR_5_6_5
:
479 case V_028C70_COLOR_1_5_5_5
:
480 case V_028C70_COLOR_5_5_5_1
:
481 case V_028C70_COLOR_4_4_4_4
:
482 case V_028C70_COLOR_10_11_11
:
483 case V_028C70_COLOR_11_11_10
:
484 case V_028C70_COLOR_8
:
485 case V_028C70_COLOR_8_8
:
486 case V_028C70_COLOR_8_8_8_8
:
487 case V_028C70_COLOR_10_10_10_2
:
488 case V_028C70_COLOR_2_10_10_10
:
489 if (ntype
== V_028C70_NUMBER_UINT
)
490 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
491 else if (ntype
== V_028C70_NUMBER_SINT
)
492 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
494 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
497 case V_028C70_COLOR_16
:
498 case V_028C70_COLOR_16_16
:
499 case V_028C70_COLOR_16_16_16_16
:
500 if (ntype
== V_028C70_NUMBER_UNORM
||
501 ntype
== V_028C70_NUMBER_SNORM
) {
502 /* UNORM16 and SNORM16 don't support blending */
503 if (ntype
== V_028C70_NUMBER_UNORM
)
504 normal
= alpha
= V_028714_SPI_SHADER_UNORM16_ABGR
;
506 normal
= alpha
= V_028714_SPI_SHADER_SNORM16_ABGR
;
508 /* Use 32 bits per channel for blending. */
509 if (format
== V_028C70_COLOR_16
) {
510 if (swap
== V_028C70_SWAP_STD
) { /* R */
511 blend
= V_028714_SPI_SHADER_32_R
;
512 blend_alpha
= V_028714_SPI_SHADER_32_AR
;
513 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
514 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
517 } else if (format
== V_028C70_COLOR_16_16
) {
518 if (swap
== V_028C70_SWAP_STD
) { /* RG */
519 blend
= V_028714_SPI_SHADER_32_GR
;
520 blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
521 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
522 blend
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
525 } else /* 16_16_16_16 */
526 blend
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
527 } else if (ntype
== V_028C70_NUMBER_UINT
)
528 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_UINT16_ABGR
;
529 else if (ntype
== V_028C70_NUMBER_SINT
)
530 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_SINT16_ABGR
;
531 else if (ntype
== V_028C70_NUMBER_FLOAT
)
532 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_FP16_ABGR
;
537 case V_028C70_COLOR_32
:
538 if (swap
== V_028C70_SWAP_STD
) { /* R */
539 blend
= normal
= V_028714_SPI_SHADER_32_R
;
540 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_AR
;
541 } else if (swap
== V_028C70_SWAP_ALT_REV
) /* A */
542 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
547 case V_028C70_COLOR_32_32
:
548 if (swap
== V_028C70_SWAP_STD
) { /* RG */
549 blend
= normal
= V_028714_SPI_SHADER_32_GR
;
550 alpha
= blend_alpha
= V_028714_SPI_SHADER_32_ABGR
;
551 } else if (swap
== V_028C70_SWAP_ALT
) /* RA */
552 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_AR
;
557 case V_028C70_COLOR_32_32_32_32
:
558 case V_028C70_COLOR_8_24
:
559 case V_028C70_COLOR_24_8
:
560 case V_028C70_COLOR_X24_8_32_FLOAT
:
561 alpha
= blend
= blend_alpha
= normal
= V_028714_SPI_SHADER_32_ABGR
;
565 unreachable("unhandled blend format");
568 if (blend_enable
&& blend_need_alpha
)
570 else if(blend_need_alpha
)
572 else if(blend_enable
)
579 radv_pipeline_compute_spi_color_formats(struct radv_pipeline
*pipeline
,
580 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
581 struct radv_blend_state
*blend
)
583 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
584 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
585 unsigned col_format
= 0;
586 unsigned num_targets
;
588 for (unsigned i
= 0; i
< (blend
->single_cb_enable
? 1 : subpass
->color_count
); ++i
) {
591 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
592 cf
= V_028714_SPI_SHADER_ZERO
;
594 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
596 blend
->blend_enable_4bit
& (0xfu
<< (i
* 4));
598 cf
= si_choose_spi_color_format(attachment
->format
,
600 blend
->need_src_alpha
& (1 << i
));
603 col_format
|= cf
<< (4 * i
);
606 if (!(col_format
& 0xf) && blend
->need_src_alpha
& (1 << 0)) {
607 /* When a subpass doesn't have any color attachments, write the
608 * alpha channel of MRT0 when alpha coverage is enabled because
609 * the depth attachment needs it.
611 col_format
|= V_028714_SPI_SHADER_32_AR
;
614 /* If the i-th target format is set, all previous target formats must
615 * be non-zero to avoid hangs.
617 num_targets
= (util_last_bit(col_format
) + 3) / 4;
618 for (unsigned i
= 0; i
< num_targets
; i
++) {
619 if (!(col_format
& (0xf << (i
* 4)))) {
620 col_format
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
624 /* The output for dual source blending should have the same format as
627 if (blend
->mrt0_is_dual_src
)
628 col_format
|= (col_format
& 0xf) << 4;
630 blend
->cb_shader_mask
= ac_get_cb_shader_mask(col_format
);
631 blend
->spi_shader_col_format
= col_format
;
635 format_is_int8(VkFormat format
)
637 const struct vk_format_description
*desc
= vk_format_description(format
);
638 int channel
= vk_format_get_first_non_void_channel(format
);
640 return channel
>= 0 && desc
->channel
[channel
].pure_integer
&&
641 desc
->channel
[channel
].size
== 8;
645 format_is_int10(VkFormat format
)
647 const struct vk_format_description
*desc
= vk_format_description(format
);
649 if (desc
->nr_channels
!= 4)
651 for (unsigned i
= 0; i
< 4; i
++) {
652 if (desc
->channel
[i
].pure_integer
&& desc
->channel
[i
].size
== 10)
659 * Ordered so that for each i,
660 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
662 const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
] = {
663 VK_FORMAT_R32_SFLOAT
,
664 VK_FORMAT_R32G32_SFLOAT
,
665 VK_FORMAT_R8G8B8A8_UNORM
,
666 VK_FORMAT_R16G16B16A16_UNORM
,
667 VK_FORMAT_R16G16B16A16_SNORM
,
668 VK_FORMAT_R16G16B16A16_UINT
,
669 VK_FORMAT_R16G16B16A16_SINT
,
670 VK_FORMAT_R32G32B32A32_SFLOAT
,
671 VK_FORMAT_R8G8B8A8_UINT
,
672 VK_FORMAT_R8G8B8A8_SINT
,
673 VK_FORMAT_A2R10G10B10_UINT_PACK32
,
674 VK_FORMAT_A2R10G10B10_SINT_PACK32
,
677 unsigned radv_format_meta_fs_key(VkFormat format
)
679 unsigned col_format
= si_choose_spi_color_format(format
, false, false);
681 assert(col_format
!= V_028714_SPI_SHADER_32_AR
);
682 if (col_format
>= V_028714_SPI_SHADER_32_AR
)
683 --col_format
; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
685 --col_format
; /* Skip V_028714_SPI_SHADER_ZERO */
686 bool is_int8
= format_is_int8(format
);
687 bool is_int10
= format_is_int10(format
);
689 return col_format
+ (is_int8
? 3 : is_int10
? 5 : 0);
693 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
694 unsigned *is_int8
, unsigned *is_int10
)
696 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
697 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
701 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
702 struct radv_render_pass_attachment
*attachment
;
704 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
707 attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
709 if (format_is_int8(attachment
->format
))
711 if (format_is_int10(attachment
->format
))
717 radv_blend_check_commutativity(struct radv_blend_state
*blend
,
718 VkBlendOp op
, VkBlendFactor src
,
719 VkBlendFactor dst
, unsigned chanmask
)
721 /* Src factor is allowed when it does not depend on Dst. */
722 static const uint32_t src_allowed
=
723 (1u << VK_BLEND_FACTOR_ONE
) |
724 (1u << VK_BLEND_FACTOR_SRC_COLOR
) |
725 (1u << VK_BLEND_FACTOR_SRC_ALPHA
) |
726 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
) |
727 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR
) |
728 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA
) |
729 (1u << VK_BLEND_FACTOR_SRC1_COLOR
) |
730 (1u << VK_BLEND_FACTOR_SRC1_ALPHA
) |
731 (1u << VK_BLEND_FACTOR_ZERO
) |
732 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
) |
733 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
) |
734 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
) |
735 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
) |
736 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
) |
737 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
);
739 if (dst
== VK_BLEND_FACTOR_ONE
&&
740 (src_allowed
& (1u << src
))) {
741 /* Addition is commutative, but floating point addition isn't
742 * associative: subtle changes can be introduced via different
743 * rounding. Be conservative, only enable for min and max.
745 if (op
== VK_BLEND_OP_MAX
|| op
== VK_BLEND_OP_MIN
)
746 blend
->commutative_4bit
|= chanmask
;
750 static struct radv_blend_state
751 radv_pipeline_init_blend_state(struct radv_pipeline
*pipeline
,
752 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
753 const struct radv_graphics_pipeline_create_info
*extra
)
755 const VkPipelineColorBlendStateCreateInfo
*vkblend
= radv_pipeline_get_color_blend_state(pCreateInfo
);
756 const VkPipelineMultisampleStateCreateInfo
*vkms
= radv_pipeline_get_multisample_state(pCreateInfo
);
757 struct radv_blend_state blend
= {0};
758 unsigned mode
= V_028808_CB_NORMAL
;
761 if (extra
&& extra
->custom_blend_mode
) {
762 blend
.single_cb_enable
= true;
763 mode
= extra
->custom_blend_mode
;
766 blend
.cb_color_control
= 0;
768 if (vkblend
->logicOpEnable
)
769 blend
.cb_color_control
|= S_028808_ROP3(si_translate_blend_logic_op(vkblend
->logicOp
));
771 blend
.cb_color_control
|= S_028808_ROP3(V_028808_ROP3_COPY
);
774 blend
.db_alpha_to_mask
= S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
775 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
776 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
777 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
778 S_028B70_OFFSET_ROUND(1);
780 if (vkms
&& vkms
->alphaToCoverageEnable
) {
781 blend
.db_alpha_to_mask
|= S_028B70_ALPHA_TO_MASK_ENABLE(1);
782 blend
.need_src_alpha
|= 0x1;
785 blend
.cb_target_mask
= 0;
787 for (i
= 0; i
< vkblend
->attachmentCount
; i
++) {
788 const VkPipelineColorBlendAttachmentState
*att
= &vkblend
->pAttachments
[i
];
789 unsigned blend_cntl
= 0;
790 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
791 VkBlendOp eqRGB
= att
->colorBlendOp
;
792 VkBlendFactor srcRGB
= att
->srcColorBlendFactor
;
793 VkBlendFactor dstRGB
= att
->dstColorBlendFactor
;
794 VkBlendOp eqA
= att
->alphaBlendOp
;
795 VkBlendFactor srcA
= att
->srcAlphaBlendFactor
;
796 VkBlendFactor dstA
= att
->dstAlphaBlendFactor
;
798 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
800 if (!att
->colorWriteMask
)
803 blend
.cb_target_mask
|= (unsigned)att
->colorWriteMask
<< (4 * i
);
804 blend
.cb_target_enabled_4bit
|= 0xf << (4 * i
);
805 if (!att
->blendEnable
) {
806 blend
.cb_blend_control
[i
] = blend_cntl
;
810 if (is_dual_src(srcRGB
) || is_dual_src(dstRGB
) || is_dual_src(srcA
) || is_dual_src(dstA
))
812 blend
.mrt0_is_dual_src
= true;
814 if (eqRGB
== VK_BLEND_OP_MIN
|| eqRGB
== VK_BLEND_OP_MAX
) {
815 srcRGB
= VK_BLEND_FACTOR_ONE
;
816 dstRGB
= VK_BLEND_FACTOR_ONE
;
818 if (eqA
== VK_BLEND_OP_MIN
|| eqA
== VK_BLEND_OP_MAX
) {
819 srcA
= VK_BLEND_FACTOR_ONE
;
820 dstA
= VK_BLEND_FACTOR_ONE
;
823 radv_blend_check_commutativity(&blend
, eqRGB
, srcRGB
, dstRGB
,
825 radv_blend_check_commutativity(&blend
, eqA
, srcA
, dstA
,
828 /* Blending optimizations for RB+.
829 * These transformations don't change the behavior.
831 * First, get rid of DST in the blend factors:
832 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
834 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
835 VK_BLEND_FACTOR_DST_COLOR
,
836 VK_BLEND_FACTOR_SRC_COLOR
);
838 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
839 VK_BLEND_FACTOR_DST_COLOR
,
840 VK_BLEND_FACTOR_SRC_COLOR
);
842 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
843 VK_BLEND_FACTOR_DST_ALPHA
,
844 VK_BLEND_FACTOR_SRC_ALPHA
);
846 /* Look up the ideal settings from tables. */
847 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
848 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
849 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
850 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
852 /* Handle interdependencies. */
853 if (si_blend_factor_uses_dst(srcRGB
))
854 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
855 if (si_blend_factor_uses_dst(srcA
))
856 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
858 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
&&
859 (dstRGB
== VK_BLEND_FACTOR_ZERO
||
860 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
861 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
))
862 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
864 /* Set the final value. */
865 blend
.sx_mrt_blend_opt
[i
] =
866 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
867 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
868 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
869 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
870 S_028760_ALPHA_DST_OPT(dstA_opt
) |
871 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
872 blend_cntl
|= S_028780_ENABLE(1);
874 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
875 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
876 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
877 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
878 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
879 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
880 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
881 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
883 blend
.cb_blend_control
[i
] = blend_cntl
;
885 blend
.blend_enable_4bit
|= 0xfu
<< (i
* 4);
887 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
888 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
889 srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
890 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
891 srcRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
||
892 dstRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
)
893 blend
.need_src_alpha
|= 1 << i
;
895 for (i
= vkblend
->attachmentCount
; i
< 8; i
++) {
896 blend
.cb_blend_control
[i
] = 0;
897 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
901 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
902 /* Disable RB+ blend optimizations for dual source blending. */
903 if (blend
.mrt0_is_dual_src
) {
904 for (i
= 0; i
< 8; i
++) {
905 blend
.sx_mrt_blend_opt
[i
] =
906 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
907 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
911 /* RB+ doesn't work with dual source blending, logic op and
914 if (blend
.mrt0_is_dual_src
||
915 (vkblend
&& vkblend
->logicOpEnable
) ||
916 mode
== V_028808_CB_RESOLVE
)
917 blend
.cb_color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
920 if (blend
.cb_target_mask
)
921 blend
.cb_color_control
|= S_028808_MODE(mode
);
923 blend
.cb_color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
925 radv_pipeline_compute_spi_color_formats(pipeline
, pCreateInfo
, &blend
);
929 static uint32_t si_translate_stencil_op(enum VkStencilOp op
)
932 case VK_STENCIL_OP_KEEP
:
933 return V_02842C_STENCIL_KEEP
;
934 case VK_STENCIL_OP_ZERO
:
935 return V_02842C_STENCIL_ZERO
;
936 case VK_STENCIL_OP_REPLACE
:
937 return V_02842C_STENCIL_REPLACE_TEST
;
938 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
939 return V_02842C_STENCIL_ADD_CLAMP
;
940 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
941 return V_02842C_STENCIL_SUB_CLAMP
;
942 case VK_STENCIL_OP_INVERT
:
943 return V_02842C_STENCIL_INVERT
;
944 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
945 return V_02842C_STENCIL_ADD_WRAP
;
946 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
947 return V_02842C_STENCIL_SUB_WRAP
;
953 static uint32_t si_translate_fill(VkPolygonMode func
)
956 case VK_POLYGON_MODE_FILL
:
957 return V_028814_X_DRAW_TRIANGLES
;
958 case VK_POLYGON_MODE_LINE
:
959 return V_028814_X_DRAW_LINES
;
960 case VK_POLYGON_MODE_POINT
:
961 return V_028814_X_DRAW_POINTS
;
964 return V_028814_X_DRAW_POINTS
;
968 static uint8_t radv_pipeline_get_ps_iter_samples(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
970 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
971 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
972 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
973 uint32_t ps_iter_samples
= 1;
974 uint32_t num_samples
;
976 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
978 * "If the VK_AMD_mixed_attachment_samples extension is enabled and the
979 * subpass uses color attachments, totalSamples is the number of
980 * samples of the color attachments. Otherwise, totalSamples is the
981 * value of VkPipelineMultisampleStateCreateInfo::rasterizationSamples
982 * specified at pipeline creation time."
984 if (subpass
->has_color_att
) {
985 num_samples
= subpass
->color_sample_count
;
987 num_samples
= vkms
->rasterizationSamples
;
990 if (vkms
->sampleShadingEnable
) {
991 ps_iter_samples
= ceilf(vkms
->minSampleShading
* num_samples
);
992 ps_iter_samples
= util_next_power_of_two(ps_iter_samples
);
994 return ps_iter_samples
;
998 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
1000 return pCreateInfo
->depthTestEnable
&&
1001 pCreateInfo
->depthWriteEnable
&&
1002 pCreateInfo
->depthCompareOp
!= VK_COMPARE_OP_NEVER
;
1006 radv_writes_stencil(const VkStencilOpState
*state
)
1008 return state
->writeMask
&&
1009 (state
->failOp
!= VK_STENCIL_OP_KEEP
||
1010 state
->passOp
!= VK_STENCIL_OP_KEEP
||
1011 state
->depthFailOp
!= VK_STENCIL_OP_KEEP
);
1015 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
1017 return pCreateInfo
->stencilTestEnable
&&
1018 (radv_writes_stencil(&pCreateInfo
->front
) ||
1019 radv_writes_stencil(&pCreateInfo
->back
));
1023 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
1025 return radv_is_depth_write_enabled(pCreateInfo
) ||
1026 radv_is_stencil_write_enabled(pCreateInfo
);
1030 radv_order_invariant_stencil_op(VkStencilOp op
)
1032 /* REPLACE is normally order invariant, except when the stencil
1033 * reference value is written by the fragment shader. Tracking this
1034 * interaction does not seem worth the effort, so be conservative.
1036 return op
!= VK_STENCIL_OP_INCREMENT_AND_CLAMP
&&
1037 op
!= VK_STENCIL_OP_DECREMENT_AND_CLAMP
&&
1038 op
!= VK_STENCIL_OP_REPLACE
;
1042 radv_order_invariant_stencil_state(const VkStencilOpState
*state
)
1044 /* Compute whether, assuming Z writes are disabled, this stencil state
1045 * is order invariant in the sense that the set of passing fragments as
1046 * well as the final stencil buffer result does not depend on the order
1049 return !state
->writeMask
||
1050 /* The following assumes that Z writes are disabled. */
1051 (state
->compareOp
== VK_COMPARE_OP_ALWAYS
&&
1052 radv_order_invariant_stencil_op(state
->passOp
) &&
1053 radv_order_invariant_stencil_op(state
->depthFailOp
)) ||
1054 (state
->compareOp
== VK_COMPARE_OP_NEVER
&&
1055 radv_order_invariant_stencil_op(state
->failOp
));
1059 radv_pipeline_out_of_order_rast(struct radv_pipeline
*pipeline
,
1060 struct radv_blend_state
*blend
,
1061 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1063 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1064 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
1065 const VkPipelineDepthStencilStateCreateInfo
*vkds
= radv_pipeline_get_depth_stencil_state(pCreateInfo
);
1066 const VkPipelineColorBlendStateCreateInfo
*vkblend
= radv_pipeline_get_color_blend_state(pCreateInfo
);
1067 unsigned colormask
= blend
->cb_target_enabled_4bit
;
1069 if (!pipeline
->device
->physical_device
->out_of_order_rast_allowed
)
1072 /* Be conservative if a logic operation is enabled with color buffers. */
1073 if (colormask
&& vkblend
&& vkblend
->logicOpEnable
)
1076 /* Default depth/stencil invariance when no attachment is bound. */
1077 struct radv_dsa_order_invariance dsa_order_invariant
= {
1078 .zs
= true, .pass_set
= true
1082 struct radv_render_pass_attachment
*attachment
=
1083 pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
1084 bool has_stencil
= vk_format_is_stencil(attachment
->format
);
1085 struct radv_dsa_order_invariance order_invariance
[2];
1086 struct radv_shader_variant
*ps
=
1087 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
1089 /* Compute depth/stencil order invariance in order to know if
1090 * it's safe to enable out-of-order.
1092 bool zfunc_is_ordered
=
1093 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
||
1094 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS
||
1095 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS_OR_EQUAL
||
1096 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER
||
1097 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER_OR_EQUAL
;
1099 bool nozwrite_and_order_invariant_stencil
=
1100 !radv_is_ds_write_enabled(vkds
) ||
1101 (!radv_is_depth_write_enabled(vkds
) &&
1102 radv_order_invariant_stencil_state(&vkds
->front
) &&
1103 radv_order_invariant_stencil_state(&vkds
->back
));
1105 order_invariance
[1].zs
=
1106 nozwrite_and_order_invariant_stencil
||
1107 (!radv_is_stencil_write_enabled(vkds
) &&
1109 order_invariance
[0].zs
=
1110 !radv_is_depth_write_enabled(vkds
) || zfunc_is_ordered
;
1112 order_invariance
[1].pass_set
=
1113 nozwrite_and_order_invariant_stencil
||
1114 (!radv_is_stencil_write_enabled(vkds
) &&
1115 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1116 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
));
1117 order_invariance
[0].pass_set
=
1118 !radv_is_depth_write_enabled(vkds
) ||
1119 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1120 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
);
1122 dsa_order_invariant
= order_invariance
[has_stencil
];
1123 if (!dsa_order_invariant
.zs
)
1126 /* The set of PS invocations is always order invariant,
1127 * except when early Z/S tests are requested.
1130 ps
->info
.ps
.writes_memory
&&
1131 ps
->info
.ps
.early_fragment_test
&&
1132 !dsa_order_invariant
.pass_set
)
1135 /* Determine if out-of-order rasterization should be disabled
1136 * when occlusion queries are used.
1138 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
=
1139 !dsa_order_invariant
.pass_set
;
1142 /* No color buffers are enabled for writing. */
1146 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
1149 /* Only commutative blending. */
1150 if (blendmask
& ~blend
->commutative_4bit
)
1153 if (!dsa_order_invariant
.pass_set
)
1157 if (colormask
& ~blendmask
)
1164 radv_pipeline_init_multisample_state(struct radv_pipeline
*pipeline
,
1165 struct radv_blend_state
*blend
,
1166 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1168 const VkPipelineMultisampleStateCreateInfo
*vkms
= radv_pipeline_get_multisample_state(pCreateInfo
);
1169 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
1170 unsigned num_tile_pipes
= pipeline
->device
->physical_device
->rad_info
.num_tile_pipes
;
1171 bool out_of_order_rast
= false;
1172 int ps_iter_samples
= 1;
1173 uint32_t mask
= 0xffff;
1176 ms
->num_samples
= vkms
->rasterizationSamples
;
1178 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1180 * "Sample shading is enabled for a graphics pipeline:
1182 * - If the interface of the fragment shader entry point of the
1183 * graphics pipeline includes an input variable decorated
1184 * with SampleId or SamplePosition. In this case
1185 * minSampleShadingFactor takes the value 1.0.
1186 * - Else if the sampleShadingEnable member of the
1187 * VkPipelineMultisampleStateCreateInfo structure specified
1188 * when creating the graphics pipeline is set to VK_TRUE. In
1189 * this case minSampleShadingFactor takes the value of
1190 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1192 * Otherwise, sample shading is considered disabled."
1194 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.force_persample
) {
1195 ps_iter_samples
= ms
->num_samples
;
1197 ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
);
1200 ms
->num_samples
= 1;
1203 const struct VkPipelineRasterizationStateRasterizationOrderAMD
*raster_order
=
1204 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD
);
1205 if (raster_order
&& raster_order
->rasterizationOrder
== VK_RASTERIZATION_ORDER_RELAXED_AMD
) {
1206 /* Out-of-order rasterization is explicitly enabled by the
1209 out_of_order_rast
= true;
1211 /* Determine if the driver can enable out-of-order
1212 * rasterization internally.
1215 radv_pipeline_out_of_order_rast(pipeline
, blend
, pCreateInfo
);
1218 ms
->pa_sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1219 ms
->pa_sc_aa_config
= 0;
1220 ms
->db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1221 S_028804_INCOHERENT_EQAA_READS(1) |
1222 S_028804_INTERPOLATE_COMP_Z(1) |
1223 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1224 ms
->pa_sc_mode_cntl_1
=
1225 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1226 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
1227 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
1228 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1230 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1231 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1232 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1233 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1234 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1235 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1236 ms
->pa_sc_mode_cntl_0
= S_028A48_ALTERNATE_RBS_PER_TILE(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
1237 S_028A48_VPORT_SCISSOR_ENABLE(1);
1239 const VkPipelineRasterizationLineStateCreateInfoEXT
*rast_line
=
1240 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1241 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1243 ms
->pa_sc_mode_cntl_0
|= S_028A48_LINE_STIPPLE_ENABLE(rast_line
->stippledLineEnable
);
1244 if (rast_line
->lineRasterizationMode
== VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT
) {
1245 /* From the Vulkan spec 1.1.129:
1247 * "When VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT lines
1248 * are being rasterized, sample locations may all be
1249 * treated as being at the pixel center (this may
1250 * affect attribute and depth interpolation)."
1252 ms
->num_samples
= 1;
1256 if (ms
->num_samples
> 1) {
1257 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1258 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1259 uint32_t z_samples
= subpass
->depth_stencil_attachment
? subpass
->depth_sample_count
: ms
->num_samples
;
1260 unsigned log_samples
= util_logbase2(ms
->num_samples
);
1261 unsigned log_z_samples
= util_logbase2(z_samples
);
1262 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
1263 ms
->pa_sc_mode_cntl_0
|= S_028A48_MSAA_ENABLE(1);
1264 ms
->pa_sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1265 ms
->db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples
) |
1266 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
1267 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
1268 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
1269 ms
->pa_sc_aa_config
|= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
1270 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples
)) |
1271 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1272 ms
->pa_sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
1273 if (ps_iter_samples
> 1)
1274 pipeline
->graphics
.spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1277 if (vkms
&& vkms
->pSampleMask
) {
1278 mask
= vkms
->pSampleMask
[0] & 0xffff;
1281 ms
->pa_sc_aa_mask
[0] = mask
| (mask
<< 16);
1282 ms
->pa_sc_aa_mask
[1] = mask
| (mask
<< 16);
1286 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology
)
1289 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1290 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1291 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1292 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1293 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1295 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1296 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1297 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1298 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1299 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1300 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1303 unreachable("unhandled primitive type");
1308 si_translate_prim(enum VkPrimitiveTopology topology
)
1311 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1312 return V_008958_DI_PT_POINTLIST
;
1313 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1314 return V_008958_DI_PT_LINELIST
;
1315 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1316 return V_008958_DI_PT_LINESTRIP
;
1317 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1318 return V_008958_DI_PT_TRILIST
;
1319 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1320 return V_008958_DI_PT_TRISTRIP
;
1321 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1322 return V_008958_DI_PT_TRIFAN
;
1323 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1324 return V_008958_DI_PT_LINELIST_ADJ
;
1325 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1326 return V_008958_DI_PT_LINESTRIP_ADJ
;
1327 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1328 return V_008958_DI_PT_TRILIST_ADJ
;
1329 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1330 return V_008958_DI_PT_TRISTRIP_ADJ
;
1331 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1332 return V_008958_DI_PT_PATCH
;
1340 si_conv_gl_prim_to_gs_out(unsigned gl_prim
)
1343 case 0: /* GL_POINTS */
1344 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1345 case 1: /* GL_LINES */
1346 case 3: /* GL_LINE_STRIP */
1347 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1348 case 0x8E7A: /* GL_ISOLINES */
1349 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1351 case 4: /* GL_TRIANGLES */
1352 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1353 case 5: /* GL_TRIANGLE_STRIP */
1354 case 7: /* GL_QUADS */
1355 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1363 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology
)
1366 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1367 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1368 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1369 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1370 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1371 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1372 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1373 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1374 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1375 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1376 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1377 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1378 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1379 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1386 static unsigned radv_dynamic_state_mask(VkDynamicState state
)
1389 case VK_DYNAMIC_STATE_VIEWPORT
:
1390 return RADV_DYNAMIC_VIEWPORT
;
1391 case VK_DYNAMIC_STATE_SCISSOR
:
1392 return RADV_DYNAMIC_SCISSOR
;
1393 case VK_DYNAMIC_STATE_LINE_WIDTH
:
1394 return RADV_DYNAMIC_LINE_WIDTH
;
1395 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
1396 return RADV_DYNAMIC_DEPTH_BIAS
;
1397 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
1398 return RADV_DYNAMIC_BLEND_CONSTANTS
;
1399 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
1400 return RADV_DYNAMIC_DEPTH_BOUNDS
;
1401 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
1402 return RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
1403 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
1404 return RADV_DYNAMIC_STENCIL_WRITE_MASK
;
1405 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
1406 return RADV_DYNAMIC_STENCIL_REFERENCE
;
1407 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT
:
1408 return RADV_DYNAMIC_DISCARD_RECTANGLE
;
1409 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT
:
1410 return RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1411 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
1412 return RADV_DYNAMIC_LINE_STIPPLE
;
1414 unreachable("Unhandled dynamic state");
1418 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1420 uint32_t states
= RADV_DYNAMIC_ALL
;
1422 /* If rasterization is disabled we do not care about any of the dynamic states,
1423 * since they are all rasterization related only. */
1424 if (pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
1427 if (!pCreateInfo
->pRasterizationState
->depthBiasEnable
)
1428 states
&= ~RADV_DYNAMIC_DEPTH_BIAS
;
1430 if (!pCreateInfo
->pDepthStencilState
||
1431 !pCreateInfo
->pDepthStencilState
->depthBoundsTestEnable
)
1432 states
&= ~RADV_DYNAMIC_DEPTH_BOUNDS
;
1434 if (!pCreateInfo
->pDepthStencilState
||
1435 !pCreateInfo
->pDepthStencilState
->stencilTestEnable
)
1436 states
&= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK
|
1437 RADV_DYNAMIC_STENCIL_WRITE_MASK
|
1438 RADV_DYNAMIC_STENCIL_REFERENCE
);
1440 if (!vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
))
1441 states
&= ~RADV_DYNAMIC_DISCARD_RECTANGLE
;
1443 if (!pCreateInfo
->pMultisampleState
||
1444 !vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1445 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
))
1446 states
&= ~RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1448 if (!pCreateInfo
->pRasterizationState
||
1449 !vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1450 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
))
1451 states
&= ~RADV_DYNAMIC_LINE_STIPPLE
;
1453 /* TODO: blend constants & line width. */
1460 radv_pipeline_init_dynamic_state(struct radv_pipeline
*pipeline
,
1461 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1463 uint32_t needed_states
= radv_pipeline_needed_dynamic_state(pCreateInfo
);
1464 uint32_t states
= needed_states
;
1465 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1466 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1468 pipeline
->dynamic_state
= default_dynamic_state
;
1469 pipeline
->graphics
.needed_dynamic_state
= needed_states
;
1471 if (pCreateInfo
->pDynamicState
) {
1472 /* Remove all of the states that are marked as dynamic */
1473 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1474 for (uint32_t s
= 0; s
< count
; s
++)
1475 states
&= ~radv_dynamic_state_mask(pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1478 struct radv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1480 if (needed_states
& RADV_DYNAMIC_VIEWPORT
) {
1481 assert(pCreateInfo
->pViewportState
);
1483 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1484 if (states
& RADV_DYNAMIC_VIEWPORT
) {
1485 typed_memcpy(dynamic
->viewport
.viewports
,
1486 pCreateInfo
->pViewportState
->pViewports
,
1487 pCreateInfo
->pViewportState
->viewportCount
);
1491 if (needed_states
& RADV_DYNAMIC_SCISSOR
) {
1492 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1493 if (states
& RADV_DYNAMIC_SCISSOR
) {
1494 typed_memcpy(dynamic
->scissor
.scissors
,
1495 pCreateInfo
->pViewportState
->pScissors
,
1496 pCreateInfo
->pViewportState
->scissorCount
);
1500 if (states
& RADV_DYNAMIC_LINE_WIDTH
) {
1501 assert(pCreateInfo
->pRasterizationState
);
1502 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1505 if (states
& RADV_DYNAMIC_DEPTH_BIAS
) {
1506 assert(pCreateInfo
->pRasterizationState
);
1507 dynamic
->depth_bias
.bias
=
1508 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1509 dynamic
->depth_bias
.clamp
=
1510 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1511 dynamic
->depth_bias
.slope
=
1512 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1515 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1517 * pColorBlendState is [...] NULL if the pipeline has rasterization
1518 * disabled or if the subpass of the render pass the pipeline is
1519 * created against does not use any color attachments.
1521 if (subpass
->has_color_att
&& states
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
1522 assert(pCreateInfo
->pColorBlendState
);
1523 typed_memcpy(dynamic
->blend_constants
,
1524 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1527 /* If there is no depthstencil attachment, then don't read
1528 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1529 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1530 * no need to override the depthstencil defaults in
1531 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1533 * Section 9.2 of the Vulkan 1.0.15 spec says:
1535 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1536 * disabled or if the subpass of the render pass the pipeline is created
1537 * against does not use a depth/stencil attachment.
1539 if (needed_states
&& subpass
->depth_stencil_attachment
) {
1540 assert(pCreateInfo
->pDepthStencilState
);
1542 if (states
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
1543 dynamic
->depth_bounds
.min
=
1544 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1545 dynamic
->depth_bounds
.max
=
1546 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1549 if (states
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
1550 dynamic
->stencil_compare_mask
.front
=
1551 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1552 dynamic
->stencil_compare_mask
.back
=
1553 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1556 if (states
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
1557 dynamic
->stencil_write_mask
.front
=
1558 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1559 dynamic
->stencil_write_mask
.back
=
1560 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1563 if (states
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
1564 dynamic
->stencil_reference
.front
=
1565 pCreateInfo
->pDepthStencilState
->front
.reference
;
1566 dynamic
->stencil_reference
.back
=
1567 pCreateInfo
->pDepthStencilState
->back
.reference
;
1571 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
1572 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
1573 if (needed_states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1574 dynamic
->discard_rectangle
.count
= discard_rectangle_info
->discardRectangleCount
;
1575 if (states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1576 typed_memcpy(dynamic
->discard_rectangle
.rectangles
,
1577 discard_rectangle_info
->pDiscardRectangles
,
1578 discard_rectangle_info
->discardRectangleCount
);
1582 if (needed_states
& RADV_DYNAMIC_SAMPLE_LOCATIONS
) {
1583 const VkPipelineSampleLocationsStateCreateInfoEXT
*sample_location_info
=
1584 vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1585 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
);
1586 /* If sampleLocationsEnable is VK_FALSE, the default sample
1587 * locations are used and the values specified in
1588 * sampleLocationsInfo are ignored.
1590 if (sample_location_info
->sampleLocationsEnable
) {
1591 const VkSampleLocationsInfoEXT
*pSampleLocationsInfo
=
1592 &sample_location_info
->sampleLocationsInfo
;
1594 assert(pSampleLocationsInfo
->sampleLocationsCount
<= MAX_SAMPLE_LOCATIONS
);
1596 dynamic
->sample_location
.per_pixel
= pSampleLocationsInfo
->sampleLocationsPerPixel
;
1597 dynamic
->sample_location
.grid_size
= pSampleLocationsInfo
->sampleLocationGridSize
;
1598 dynamic
->sample_location
.count
= pSampleLocationsInfo
->sampleLocationsCount
;
1599 typed_memcpy(&dynamic
->sample_location
.locations
[0],
1600 pSampleLocationsInfo
->pSampleLocations
,
1601 pSampleLocationsInfo
->sampleLocationsCount
);
1605 const VkPipelineRasterizationLineStateCreateInfoEXT
*rast_line_info
=
1606 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1607 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1608 if (needed_states
& RADV_DYNAMIC_LINE_STIPPLE
) {
1609 dynamic
->line_stipple
.factor
= rast_line_info
->lineStippleFactor
;
1610 dynamic
->line_stipple
.pattern
= rast_line_info
->lineStipplePattern
;
1613 pipeline
->dynamic_state
.mask
= states
;
1617 gfx9_get_gs_info(const struct radv_pipeline_key
*key
,
1618 const struct radv_pipeline
*pipeline
,
1620 struct radv_shader_info
*infos
,
1621 struct gfx9_gs_info
*out
)
1623 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1624 struct radv_es_output_info
*es_info
;
1625 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1626 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1628 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ?
1629 &infos
[MESA_SHADER_TESS_EVAL
].tes
.es_info
:
1630 &infos
[MESA_SHADER_VERTEX
].vs
.es_info
;
1632 unsigned gs_num_invocations
= MAX2(gs_info
->gs
.invocations
, 1);
1633 bool uses_adjacency
;
1634 switch(key
->topology
) {
1635 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1636 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1637 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1638 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1639 uses_adjacency
= true;
1642 uses_adjacency
= false;
1646 /* All these are in dwords: */
1647 /* We can't allow using the whole LDS, because GS waves compete with
1648 * other shader stages for LDS space. */
1649 const unsigned max_lds_size
= 8 * 1024;
1650 const unsigned esgs_itemsize
= es_info
->esgs_itemsize
/ 4;
1651 unsigned esgs_lds_size
;
1653 /* All these are per subgroup: */
1654 const unsigned max_out_prims
= 32 * 1024;
1655 const unsigned max_es_verts
= 255;
1656 const unsigned ideal_gs_prims
= 64;
1657 unsigned max_gs_prims
, gs_prims
;
1658 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
1660 if (uses_adjacency
|| gs_num_invocations
> 1)
1661 max_gs_prims
= 127 / gs_num_invocations
;
1665 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1666 * Make sure we don't go over the maximum value.
1668 if (gs_info
->gs
.vertices_out
> 0) {
1669 max_gs_prims
= MIN2(max_gs_prims
,
1671 (gs_info
->gs
.vertices_out
* gs_num_invocations
));
1673 assert(max_gs_prims
> 0);
1675 /* If the primitive has adjacency, halve the number of vertices
1676 * that will be reused in multiple primitives.
1678 min_es_verts
= gs_info
->gs
.vertices_in
/ (uses_adjacency
? 2 : 1);
1680 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
1681 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
1683 /* Compute ESGS LDS size based on the worst case number of ES vertices
1684 * needed to create the target number of GS prims per subgroup.
1686 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1688 /* If total LDS usage is too big, refactor partitions based on ratio
1689 * of ESGS item sizes.
1691 if (esgs_lds_size
> max_lds_size
) {
1692 /* Our target GS Prims Per Subgroup was too large. Calculate
1693 * the maximum number of GS Prims Per Subgroup that will fit
1694 * into LDS, capped by the maximum that the hardware can support.
1696 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
1698 assert(gs_prims
> 0);
1699 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
1702 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1703 assert(esgs_lds_size
<= max_lds_size
);
1706 /* Now calculate remaining ESGS information. */
1708 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
1710 es_verts
= max_es_verts
;
1712 /* Vertices for adjacency primitives are not always reused, so restore
1713 * it for ES_VERTS_PER_SUBGRP.
1715 min_es_verts
= gs_info
->gs
.vertices_in
;
1717 /* For normal primitives, the VGT only checks if they are past the ES
1718 * verts per subgroup after allocating a full GS primitive and if they
1719 * are, kick off a new subgroup. But if those additional ES verts are
1720 * unique (e.g. not reused) we need to make sure there is enough LDS
1721 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1723 es_verts
-= min_es_verts
- 1;
1725 uint32_t es_verts_per_subgroup
= es_verts
;
1726 uint32_t gs_prims_per_subgroup
= gs_prims
;
1727 uint32_t gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
1728 uint32_t max_prims_per_subgroup
= gs_inst_prims_in_subgroup
* gs_info
->gs
.vertices_out
;
1729 out
->lds_size
= align(esgs_lds_size
, 128) / 128;
1730 out
->vgt_gs_onchip_cntl
= S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup
) |
1731 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup
) |
1732 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup
);
1733 out
->vgt_gs_max_prims_per_subgroup
= S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup
);
1734 out
->vgt_esgs_ring_itemsize
= esgs_itemsize
;
1735 assert(max_prims_per_subgroup
<= max_out_prims
);
1738 static void clamp_gsprims_to_esverts(unsigned *max_gsprims
, unsigned max_esverts
,
1739 unsigned min_verts_per_prim
, bool use_adjacency
)
1741 unsigned max_reuse
= max_esverts
- min_verts_per_prim
;
1744 *max_gsprims
= MIN2(*max_gsprims
, 1 + max_reuse
);
1748 radv_get_num_input_vertices(nir_shader
**nir
)
1750 if (nir
[MESA_SHADER_GEOMETRY
]) {
1751 nir_shader
*gs
= nir
[MESA_SHADER_GEOMETRY
];
1753 return gs
->info
.gs
.vertices_in
;
1756 if (nir
[MESA_SHADER_TESS_CTRL
]) {
1757 nir_shader
*tes
= nir
[MESA_SHADER_TESS_EVAL
];
1759 if (tes
->info
.tess
.point_mode
)
1761 if (tes
->info
.tess
.primitive_mode
== GL_ISOLINES
)
1770 gfx10_get_ngg_info(const struct radv_pipeline_key
*key
,
1771 struct radv_pipeline
*pipeline
,
1773 struct radv_shader_info
*infos
,
1774 struct gfx10_ngg_info
*ngg
)
1776 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1777 struct radv_es_output_info
*es_info
=
1778 nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1779 unsigned gs_type
= nir
[MESA_SHADER_GEOMETRY
] ? MESA_SHADER_GEOMETRY
: MESA_SHADER_VERTEX
;
1780 unsigned max_verts_per_prim
= radv_get_num_input_vertices(nir
);
1781 unsigned min_verts_per_prim
=
1782 gs_type
== MESA_SHADER_GEOMETRY
? max_verts_per_prim
: 1;
1783 unsigned gs_num_invocations
= nir
[MESA_SHADER_GEOMETRY
] ? MAX2(gs_info
->gs
.invocations
, 1) : 1;
1784 bool uses_adjacency
;
1785 switch(key
->topology
) {
1786 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1787 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1788 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1789 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1790 uses_adjacency
= true;
1793 uses_adjacency
= false;
1797 /* All these are in dwords: */
1798 /* We can't allow using the whole LDS, because GS waves compete with
1799 * other shader stages for LDS space.
1801 * TODO: We should really take the shader's internal LDS use into
1802 * account. The linker will fail if the size is greater than
1805 const unsigned max_lds_size
= 8 * 1024 - 768;
1806 const unsigned target_lds_size
= max_lds_size
;
1807 unsigned esvert_lds_size
= 0;
1808 unsigned gsprim_lds_size
= 0;
1810 /* All these are per subgroup: */
1811 bool max_vert_out_per_gs_instance
= false;
1812 unsigned max_esverts_base
= 256;
1813 unsigned max_gsprims_base
= 128; /* default prim group size clamp */
1815 /* Hardware has the following non-natural restrictions on the value
1816 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1818 * - at most 252 for any line input primitive type
1819 * - at most 251 for any quad input primitive type
1820 * - at most 251 for triangle strips with adjacency (this happens to
1821 * be the natural limit for triangle *lists* with adjacency)
1823 max_esverts_base
= MIN2(max_esverts_base
, 251 + max_verts_per_prim
- 1);
1825 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1826 unsigned max_out_verts_per_gsprim
=
1827 gs_info
->gs
.vertices_out
* gs_num_invocations
;
1829 if (max_out_verts_per_gsprim
<= 256) {
1830 if (max_out_verts_per_gsprim
) {
1831 max_gsprims_base
= MIN2(max_gsprims_base
,
1832 256 / max_out_verts_per_gsprim
);
1835 /* Use special multi-cycling mode in which each GS
1836 * instance gets its own subgroup. Does not work with
1838 max_vert_out_per_gs_instance
= true;
1839 max_gsprims_base
= 1;
1840 max_out_verts_per_gsprim
= gs_info
->gs
.vertices_out
;
1843 esvert_lds_size
= es_info
->esgs_itemsize
/ 4;
1844 gsprim_lds_size
= (gs_info
->gs
.gsvs_vertex_size
/ 4 + 1) * max_out_verts_per_gsprim
;
1847 /* LDS size for passing data from GS to ES. */
1848 struct radv_streamout_info
*so_info
= nir
[MESA_SHADER_TESS_CTRL
]
1849 ? &infos
[MESA_SHADER_TESS_EVAL
].so
1850 : &infos
[MESA_SHADER_VERTEX
].so
;
1852 if (so_info
->num_outputs
)
1853 esvert_lds_size
= 4 * so_info
->num_outputs
+ 1;
1855 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1856 * corresponding to the ES thread of the provoking vertex. All
1857 * ES threads load and export PrimitiveID for their thread.
1859 if (!nir
[MESA_SHADER_TESS_CTRL
] &&
1860 infos
[MESA_SHADER_VERTEX
].vs
.outinfo
.export_prim_id
)
1861 esvert_lds_size
= MAX2(esvert_lds_size
, 1);
1864 unsigned max_gsprims
= max_gsprims_base
;
1865 unsigned max_esverts
= max_esverts_base
;
1867 if (esvert_lds_size
)
1868 max_esverts
= MIN2(max_esverts
, target_lds_size
/ esvert_lds_size
);
1869 if (gsprim_lds_size
)
1870 max_gsprims
= MIN2(max_gsprims
, target_lds_size
/ gsprim_lds_size
);
1872 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1873 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
, min_verts_per_prim
, uses_adjacency
);
1874 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1876 if (esvert_lds_size
|| gsprim_lds_size
) {
1877 /* Now that we have a rough proportionality between esverts
1878 * and gsprims based on the primitive type, scale both of them
1879 * down simultaneously based on required LDS space.
1881 * We could be smarter about this if we knew how much vertex
1884 unsigned lds_total
= max_esverts
* esvert_lds_size
+
1885 max_gsprims
* gsprim_lds_size
;
1886 if (lds_total
> target_lds_size
) {
1887 max_esverts
= max_esverts
* target_lds_size
/ lds_total
;
1888 max_gsprims
= max_gsprims
* target_lds_size
/ lds_total
;
1890 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1891 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1892 min_verts_per_prim
, uses_adjacency
);
1893 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1897 /* Round up towards full wave sizes for better ALU utilization. */
1898 if (!max_vert_out_per_gs_instance
) {
1899 unsigned orig_max_esverts
;
1900 unsigned orig_max_gsprims
;
1903 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1904 wavesize
= gs_info
->wave_size
;
1906 wavesize
= nir
[MESA_SHADER_TESS_CTRL
]
1907 ? infos
[MESA_SHADER_TESS_EVAL
].wave_size
1908 : infos
[MESA_SHADER_VERTEX
].wave_size
;
1912 orig_max_esverts
= max_esverts
;
1913 orig_max_gsprims
= max_gsprims
;
1915 max_esverts
= align(max_esverts
, wavesize
);
1916 max_esverts
= MIN2(max_esverts
, max_esverts_base
);
1917 if (esvert_lds_size
)
1918 max_esverts
= MIN2(max_esverts
,
1919 (max_lds_size
- max_gsprims
* gsprim_lds_size
) /
1921 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1923 max_gsprims
= align(max_gsprims
, wavesize
);
1924 max_gsprims
= MIN2(max_gsprims
, max_gsprims_base
);
1925 if (gsprim_lds_size
)
1926 max_gsprims
= MIN2(max_gsprims
,
1927 (max_lds_size
- max_esverts
* esvert_lds_size
) /
1929 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1930 min_verts_per_prim
, uses_adjacency
);
1931 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1932 } while (orig_max_esverts
!= max_esverts
|| orig_max_gsprims
!= max_gsprims
);
1935 /* Hardware restriction: minimum value of max_esverts */
1936 max_esverts
= MAX2(max_esverts
, 23 + max_verts_per_prim
);
1938 unsigned max_out_vertices
=
1939 max_vert_out_per_gs_instance
? gs_info
->gs
.vertices_out
:
1940 gs_type
== MESA_SHADER_GEOMETRY
?
1941 max_gsprims
* gs_num_invocations
* gs_info
->gs
.vertices_out
:
1943 assert(max_out_vertices
<= 256);
1945 unsigned prim_amp_factor
= 1;
1946 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1947 /* Number of output primitives per GS input primitive after
1949 prim_amp_factor
= gs_info
->gs
.vertices_out
;
1952 /* The GE only checks against the maximum number of ES verts after
1953 * allocating a full GS primitive. So we need to ensure that whenever
1954 * this check passes, there is enough space for a full primitive without
1957 ngg
->hw_max_esverts
= max_esverts
- max_verts_per_prim
+ 1;
1958 ngg
->max_gsprims
= max_gsprims
;
1959 ngg
->max_out_verts
= max_out_vertices
;
1960 ngg
->prim_amp_factor
= prim_amp_factor
;
1961 ngg
->max_vert_out_per_gs_instance
= max_vert_out_per_gs_instance
;
1962 ngg
->ngg_emit_size
= max_gsprims
* gsprim_lds_size
;
1963 ngg
->esgs_ring_size
= 4 * max_esverts
* esvert_lds_size
;
1965 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1966 ngg
->vgt_esgs_ring_itemsize
= es_info
->esgs_itemsize
/ 4;
1968 ngg
->vgt_esgs_ring_itemsize
= 1;
1971 pipeline
->graphics
.esgs_ring_size
= ngg
->esgs_ring_size
;
1973 assert(ngg
->hw_max_esverts
>= 24); /* HW limitation */
1977 calculate_gs_ring_sizes(struct radv_pipeline
*pipeline
,
1978 const struct gfx9_gs_info
*gs
)
1980 struct radv_device
*device
= pipeline
->device
;
1981 unsigned num_se
= device
->physical_device
->rad_info
.max_se
;
1982 unsigned wave_size
= 64;
1983 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
1984 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1985 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1987 unsigned gs_vertex_reuse
=
1988 (device
->physical_device
->rad_info
.chip_class
>= GFX8
? 32 : 16) * num_se
;
1989 unsigned alignment
= 256 * num_se
;
1990 /* The maximum size is 63.999 MB per SE. */
1991 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
1992 struct radv_shader_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
1994 /* Calculate the minimum size. */
1995 unsigned min_esgs_ring_size
= align(gs
->vgt_esgs_ring_itemsize
* 4 * gs_vertex_reuse
*
1996 wave_size
, alignment
);
1997 /* These are recommended sizes, not minimum sizes. */
1998 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
1999 gs
->vgt_esgs_ring_itemsize
* 4 * gs_info
->gs
.vertices_in
;
2000 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
2001 gs_info
->gs
.max_gsvs_emit_size
;
2003 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
2004 esgs_ring_size
= align(esgs_ring_size
, alignment
);
2005 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
2007 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
2008 pipeline
->graphics
.esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
2010 pipeline
->graphics
.gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
2013 static void si_multiwave_lds_size_workaround(struct radv_device
*device
,
2016 /* If tessellation is all offchip and on-chip GS isn't used, this
2017 * workaround is not needed.
2021 /* SPI barrier management bug:
2022 * Make sure we have at least 4k of LDS in use to avoid the bug.
2023 * It applies to workgroup sizes of more than one wavefront.
2025 if (device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
||
2026 device
->physical_device
->rad_info
.family
== CHIP_KABINI
)
2027 *lds_size
= MAX2(*lds_size
, 8);
2030 struct radv_shader_variant
*
2031 radv_get_shader(struct radv_pipeline
*pipeline
,
2032 gl_shader_stage stage
)
2034 if (stage
== MESA_SHADER_VERTEX
) {
2035 if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
2036 return pipeline
->shaders
[MESA_SHADER_VERTEX
];
2037 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
])
2038 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
2039 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
2040 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
2041 } else if (stage
== MESA_SHADER_TESS_EVAL
) {
2042 if (!radv_pipeline_has_tess(pipeline
))
2044 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
2045 return pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
2046 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
2047 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
2049 return pipeline
->shaders
[stage
];
2052 static struct radv_tessellation_state
2053 calculate_tess_state(struct radv_pipeline
*pipeline
,
2054 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
2056 unsigned num_tcs_input_cp
;
2057 unsigned num_tcs_output_cp
;
2059 unsigned num_patches
;
2060 struct radv_tessellation_state tess
= {0};
2062 num_tcs_input_cp
= pCreateInfo
->pTessellationState
->patchControlPoints
;
2063 num_tcs_output_cp
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.tcs_vertices_out
; //TCS VERTICES OUT
2064 num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2066 lds_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.lds_size
;
2068 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
2069 assert(lds_size
<= 65536);
2070 lds_size
= align(lds_size
, 512) / 512;
2072 assert(lds_size
<= 32768);
2073 lds_size
= align(lds_size
, 256) / 256;
2075 si_multiwave_lds_size_workaround(pipeline
->device
, &lds_size
);
2077 tess
.lds_size
= lds_size
;
2079 tess
.ls_hs_config
= S_028B58_NUM_PATCHES(num_patches
) |
2080 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
2081 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
2082 tess
.num_patches
= num_patches
;
2084 struct radv_shader_variant
*tes
= radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
);
2085 unsigned type
= 0, partitioning
= 0, topology
= 0, distribution_mode
= 0;
2087 switch (tes
->info
.tes
.primitive_mode
) {
2089 type
= V_028B6C_TESS_TRIANGLE
;
2092 type
= V_028B6C_TESS_QUAD
;
2095 type
= V_028B6C_TESS_ISOLINE
;
2099 switch (tes
->info
.tes
.spacing
) {
2100 case TESS_SPACING_EQUAL
:
2101 partitioning
= V_028B6C_PART_INTEGER
;
2103 case TESS_SPACING_FRACTIONAL_ODD
:
2104 partitioning
= V_028B6C_PART_FRAC_ODD
;
2106 case TESS_SPACING_FRACTIONAL_EVEN
:
2107 partitioning
= V_028B6C_PART_FRAC_EVEN
;
2113 bool ccw
= tes
->info
.tes
.ccw
;
2114 const VkPipelineTessellationDomainOriginStateCreateInfo
*domain_origin_state
=
2115 vk_find_struct_const(pCreateInfo
->pTessellationState
,
2116 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO
);
2118 if (domain_origin_state
&& domain_origin_state
->domainOrigin
!= VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT
)
2121 if (tes
->info
.tes
.point_mode
)
2122 topology
= V_028B6C_OUTPUT_POINT
;
2123 else if (tes
->info
.tes
.primitive_mode
== GL_ISOLINES
)
2124 topology
= V_028B6C_OUTPUT_LINE
;
2126 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
2128 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
2130 if (pipeline
->device
->physical_device
->rad_info
.has_distributed_tess
) {
2131 if (pipeline
->device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
2132 pipeline
->device
->physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
2133 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
2135 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
2137 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
2139 tess
.tf_param
= S_028B6C_TYPE(type
) |
2140 S_028B6C_PARTITIONING(partitioning
) |
2141 S_028B6C_TOPOLOGY(topology
) |
2142 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
2147 static const struct radv_prim_vertex_count prim_size_table
[] = {
2148 [V_008958_DI_PT_NONE
] = {0, 0},
2149 [V_008958_DI_PT_POINTLIST
] = {1, 1},
2150 [V_008958_DI_PT_LINELIST
] = {2, 2},
2151 [V_008958_DI_PT_LINESTRIP
] = {2, 1},
2152 [V_008958_DI_PT_TRILIST
] = {3, 3},
2153 [V_008958_DI_PT_TRIFAN
] = {3, 1},
2154 [V_008958_DI_PT_TRISTRIP
] = {3, 1},
2155 [V_008958_DI_PT_LINELIST_ADJ
] = {4, 4},
2156 [V_008958_DI_PT_LINESTRIP_ADJ
] = {4, 1},
2157 [V_008958_DI_PT_TRILIST_ADJ
] = {6, 6},
2158 [V_008958_DI_PT_TRISTRIP_ADJ
] = {6, 2},
2159 [V_008958_DI_PT_RECTLIST
] = {3, 3},
2160 [V_008958_DI_PT_LINELOOP
] = {2, 1},
2161 [V_008958_DI_PT_POLYGON
] = {3, 1},
2162 [V_008958_DI_PT_2D_TRI_STRIP
] = {0, 0},
2165 static const struct radv_vs_output_info
*get_vs_output_info(const struct radv_pipeline
*pipeline
)
2167 if (radv_pipeline_has_gs(pipeline
))
2168 if (radv_pipeline_has_ngg(pipeline
))
2169 return &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.vs
.outinfo
;
2171 return &pipeline
->gs_copy_shader
->info
.vs
.outinfo
;
2172 else if (radv_pipeline_has_tess(pipeline
))
2173 return &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.outinfo
;
2175 return &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.outinfo
;
2179 radv_link_shaders(struct radv_pipeline
*pipeline
, nir_shader
**shaders
)
2181 nir_shader
* ordered_shaders
[MESA_SHADER_STAGES
];
2182 int shader_count
= 0;
2184 if(shaders
[MESA_SHADER_FRAGMENT
]) {
2185 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_FRAGMENT
];
2187 if(shaders
[MESA_SHADER_GEOMETRY
]) {
2188 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_GEOMETRY
];
2190 if(shaders
[MESA_SHADER_TESS_EVAL
]) {
2191 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_EVAL
];
2193 if(shaders
[MESA_SHADER_TESS_CTRL
]) {
2194 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_CTRL
];
2196 if(shaders
[MESA_SHADER_VERTEX
]) {
2197 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_VERTEX
];
2200 if (shader_count
> 1) {
2201 unsigned first
= ordered_shaders
[shader_count
- 1]->info
.stage
;
2202 unsigned last
= ordered_shaders
[0]->info
.stage
;
2204 if (ordered_shaders
[0]->info
.stage
== MESA_SHADER_FRAGMENT
&&
2205 ordered_shaders
[1]->info
.has_transform_feedback_varyings
)
2206 nir_link_xfb_varyings(ordered_shaders
[1], ordered_shaders
[0]);
2208 for (int i
= 0; i
< shader_count
; ++i
) {
2209 nir_variable_mode mask
= 0;
2211 if (ordered_shaders
[i
]->info
.stage
!= first
)
2212 mask
= mask
| nir_var_shader_in
;
2214 if (ordered_shaders
[i
]->info
.stage
!= last
)
2215 mask
= mask
| nir_var_shader_out
;
2217 nir_lower_io_to_scalar_early(ordered_shaders
[i
], mask
);
2218 radv_optimize_nir(ordered_shaders
[i
], false, false);
2222 for (int i
= 1; i
< shader_count
; ++i
) {
2223 nir_lower_io_arrays_to_elements(ordered_shaders
[i
],
2224 ordered_shaders
[i
- 1]);
2226 if (nir_link_opt_varyings(ordered_shaders
[i
],
2227 ordered_shaders
[i
- 1]))
2228 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2230 nir_remove_dead_variables(ordered_shaders
[i
],
2231 nir_var_shader_out
);
2232 nir_remove_dead_variables(ordered_shaders
[i
- 1],
2235 bool progress
= nir_remove_unused_varyings(ordered_shaders
[i
],
2236 ordered_shaders
[i
- 1]);
2238 nir_compact_varyings(ordered_shaders
[i
],
2239 ordered_shaders
[i
- 1], true);
2242 if (nir_lower_global_vars_to_local(ordered_shaders
[i
])) {
2243 ac_lower_indirect_derefs(ordered_shaders
[i
],
2244 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2246 radv_optimize_nir(ordered_shaders
[i
], false, false);
2248 if (nir_lower_global_vars_to_local(ordered_shaders
[i
- 1])) {
2249 ac_lower_indirect_derefs(ordered_shaders
[i
- 1],
2250 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2252 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2258 radv_set_linked_driver_locations(struct radv_pipeline
*pipeline
, nir_shader
**shaders
,
2259 struct radv_shader_info infos
[MESA_SHADER_STAGES
])
2261 bool has_tess
= shaders
[MESA_SHADER_TESS_CTRL
];
2262 bool has_gs
= shaders
[MESA_SHADER_GEOMETRY
];
2264 if (!has_tess
&& !has_gs
)
2267 unsigned vs_info_idx
= MESA_SHADER_VERTEX
;
2268 unsigned tes_info_idx
= MESA_SHADER_TESS_EVAL
;
2270 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2271 /* These are merged into the next stage */
2272 vs_info_idx
= has_tess
? MESA_SHADER_TESS_CTRL
: MESA_SHADER_GEOMETRY
;
2273 tes_info_idx
= has_gs
? MESA_SHADER_GEOMETRY
: MESA_SHADER_TESS_EVAL
;
2277 nir_linked_io_var_info vs2tcs
=
2278 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_VERTEX
], shaders
[MESA_SHADER_TESS_CTRL
]);
2279 nir_linked_io_var_info tcs2tes
=
2280 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_TESS_CTRL
], shaders
[MESA_SHADER_TESS_EVAL
]);
2282 infos
[vs_info_idx
].vs
.num_linked_outputs
= vs2tcs
.num_linked_io_vars
;
2283 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_inputs
= vs2tcs
.num_linked_io_vars
;
2284 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_outputs
= tcs2tes
.num_linked_io_vars
;
2285 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_patch_outputs
= tcs2tes
.num_linked_patch_io_vars
;
2286 infos
[tes_info_idx
].tes
.num_linked_inputs
= tcs2tes
.num_linked_io_vars
;
2287 infos
[tes_info_idx
].tes
.num_linked_patch_inputs
= tcs2tes
.num_linked_patch_io_vars
;
2290 nir_linked_io_var_info tes2gs
=
2291 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_TESS_EVAL
], shaders
[MESA_SHADER_GEOMETRY
]);
2293 infos
[tes_info_idx
].tes
.num_linked_outputs
= tes2gs
.num_linked_io_vars
;
2294 infos
[MESA_SHADER_GEOMETRY
].gs
.num_linked_inputs
= tes2gs
.num_linked_io_vars
;
2296 } else if (has_gs
) {
2297 nir_linked_io_var_info vs2gs
=
2298 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_VERTEX
], shaders
[MESA_SHADER_GEOMETRY
]);
2300 infos
[vs_info_idx
].vs
.num_linked_outputs
= vs2gs
.num_linked_io_vars
;
2301 infos
[MESA_SHADER_GEOMETRY
].gs
.num_linked_inputs
= vs2gs
.num_linked_io_vars
;
2306 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo
*input_state
,
2307 uint32_t attrib_binding
)
2309 for (uint32_t i
= 0; i
< input_state
->vertexBindingDescriptionCount
; i
++) {
2310 const VkVertexInputBindingDescription
*input_binding
=
2311 &input_state
->pVertexBindingDescriptions
[i
];
2313 if (input_binding
->binding
== attrib_binding
)
2314 return input_binding
->stride
;
2320 static struct radv_pipeline_key
2321 radv_generate_graphics_pipeline_key(struct radv_pipeline
*pipeline
,
2322 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2323 const struct radv_blend_state
*blend
,
2324 bool has_view_index
)
2326 const VkPipelineVertexInputStateCreateInfo
*input_state
=
2327 pCreateInfo
->pVertexInputState
;
2328 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*divisor_state
=
2329 vk_find_struct_const(input_state
->pNext
, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
2331 struct radv_pipeline_key key
;
2332 memset(&key
, 0, sizeof(key
));
2334 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
2335 key
.optimisations_disabled
= 1;
2337 key
.has_multiview_view_index
= has_view_index
;
2339 uint32_t binding_input_rate
= 0;
2340 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
2341 for (unsigned i
= 0; i
< input_state
->vertexBindingDescriptionCount
; ++i
) {
2342 if (input_state
->pVertexBindingDescriptions
[i
].inputRate
) {
2343 unsigned binding
= input_state
->pVertexBindingDescriptions
[i
].binding
;
2344 binding_input_rate
|= 1u << binding
;
2345 instance_rate_divisors
[binding
] = 1;
2348 if (divisor_state
) {
2349 for (unsigned i
= 0; i
< divisor_state
->vertexBindingDivisorCount
; ++i
) {
2350 instance_rate_divisors
[divisor_state
->pVertexBindingDivisors
[i
].binding
] =
2351 divisor_state
->pVertexBindingDivisors
[i
].divisor
;
2355 for (unsigned i
= 0; i
< input_state
->vertexAttributeDescriptionCount
; ++i
) {
2356 const VkVertexInputAttributeDescription
*desc
=
2357 &input_state
->pVertexAttributeDescriptions
[i
];
2358 const struct vk_format_description
*format_desc
;
2359 unsigned location
= desc
->location
;
2360 unsigned binding
= desc
->binding
;
2361 unsigned num_format
, data_format
;
2364 if (binding_input_rate
& (1u << binding
)) {
2365 key
.instance_rate_inputs
|= 1u << location
;
2366 key
.instance_rate_divisors
[location
] = instance_rate_divisors
[binding
];
2369 format_desc
= vk_format_description(desc
->format
);
2370 first_non_void
= vk_format_get_first_non_void_channel(desc
->format
);
2372 num_format
= radv_translate_buffer_numformat(format_desc
, first_non_void
);
2373 data_format
= radv_translate_buffer_dataformat(format_desc
, first_non_void
);
2375 key
.vertex_attribute_formats
[location
] = data_format
| (num_format
<< 4);
2376 key
.vertex_attribute_bindings
[location
] = desc
->binding
;
2377 key
.vertex_attribute_offsets
[location
] = desc
->offset
;
2378 key
.vertex_attribute_strides
[location
] = radv_get_attrib_stride(input_state
, desc
->binding
);
2380 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
&&
2381 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_STONEY
) {
2382 VkFormat format
= input_state
->pVertexAttributeDescriptions
[i
].format
;
2385 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2386 case VK_FORMAT_A2B10G10R10_SNORM_PACK32
:
2387 adjust
= RADV_ALPHA_ADJUST_SNORM
;
2389 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2390 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32
:
2391 adjust
= RADV_ALPHA_ADJUST_SSCALED
;
2393 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2394 case VK_FORMAT_A2B10G10R10_SINT_PACK32
:
2395 adjust
= RADV_ALPHA_ADJUST_SINT
;
2401 key
.vertex_alpha_adjust
|= adjust
<< (2 * location
);
2404 switch (desc
->format
) {
2405 case VK_FORMAT_B8G8R8A8_UNORM
:
2406 case VK_FORMAT_B8G8R8A8_SNORM
:
2407 case VK_FORMAT_B8G8R8A8_USCALED
:
2408 case VK_FORMAT_B8G8R8A8_SSCALED
:
2409 case VK_FORMAT_B8G8R8A8_UINT
:
2410 case VK_FORMAT_B8G8R8A8_SINT
:
2411 case VK_FORMAT_B8G8R8A8_SRGB
:
2412 case VK_FORMAT_A2R10G10B10_UNORM_PACK32
:
2413 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2414 case VK_FORMAT_A2R10G10B10_USCALED_PACK32
:
2415 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2416 case VK_FORMAT_A2R10G10B10_UINT_PACK32
:
2417 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2418 key
.vertex_post_shuffle
|= 1 << location
;
2425 const VkPipelineTessellationStateCreateInfo
*tess
=
2426 radv_pipeline_get_tessellation_state(pCreateInfo
);
2428 key
.tess_input_vertices
= tess
->patchControlPoints
;
2430 const VkPipelineMultisampleStateCreateInfo
*vkms
=
2431 radv_pipeline_get_multisample_state(pCreateInfo
);
2432 if (vkms
&& vkms
->rasterizationSamples
> 1) {
2433 uint32_t num_samples
= vkms
->rasterizationSamples
;
2434 uint32_t ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
);
2435 key
.num_samples
= num_samples
;
2436 key
.log2_ps_iter_samples
= util_logbase2(ps_iter_samples
);
2439 key
.col_format
= blend
->spi_shader_col_format
;
2440 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX8
)
2441 radv_pipeline_compute_get_int_clamp(pCreateInfo
, &key
.is_int8
, &key
.is_int10
);
2443 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
2444 key
.topology
= pCreateInfo
->pInputAssemblyState
->topology
;
2450 radv_nir_stage_uses_xfb(const nir_shader
*nir
)
2452 nir_xfb_info
*xfb
= nir_gather_xfb_info(nir
, NULL
);
2453 bool uses_xfb
= !!xfb
;
2460 radv_fill_shader_keys(struct radv_device
*device
,
2461 struct radv_shader_variant_key
*keys
,
2462 const struct radv_pipeline_key
*key
,
2465 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_inputs
= key
->instance_rate_inputs
;
2466 keys
[MESA_SHADER_VERTEX
].vs
.alpha_adjust
= key
->vertex_alpha_adjust
;
2467 keys
[MESA_SHADER_VERTEX
].vs
.post_shuffle
= key
->vertex_post_shuffle
;
2468 for (unsigned i
= 0; i
< MAX_VERTEX_ATTRIBS
; ++i
) {
2469 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_divisors
[i
] = key
->instance_rate_divisors
[i
];
2470 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_formats
[i
] = key
->vertex_attribute_formats
[i
];
2471 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_bindings
[i
] = key
->vertex_attribute_bindings
[i
];
2472 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_offsets
[i
] = key
->vertex_attribute_offsets
[i
];
2473 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_strides
[i
] = key
->vertex_attribute_strides
[i
];
2475 keys
[MESA_SHADER_VERTEX
].vs
.outprim
= si_conv_prim_to_gs_out(key
->topology
);
2477 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2478 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ls
= true;
2479 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= 0;
2480 keys
[MESA_SHADER_TESS_CTRL
].tcs
.input_vertices
= key
->tess_input_vertices
;
2481 keys
[MESA_SHADER_TESS_CTRL
].tcs
.primitive_mode
= nir
[MESA_SHADER_TESS_EVAL
]->info
.tess
.primitive_mode
;
2483 keys
[MESA_SHADER_TESS_CTRL
].tcs
.tes_reads_tess_factors
= !!(nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
& (VARYING_BIT_TESS_LEVEL_INNER
| VARYING_BIT_TESS_LEVEL_OUTER
));
2486 if (nir
[MESA_SHADER_GEOMETRY
]) {
2487 if (nir
[MESA_SHADER_TESS_CTRL
])
2488 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_es
= true;
2490 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_es
= true;
2493 if (device
->physical_device
->use_ngg
) {
2494 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2495 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= true;
2497 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= true;
2500 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2501 nir
[MESA_SHADER_GEOMETRY
] &&
2502 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.invocations
*
2503 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.vertices_out
> 256) {
2504 /* Fallback to the legacy path if tessellation is
2505 * enabled with extreme geometry because
2506 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2509 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2512 if (!device
->physical_device
->use_ngg_gs
) {
2513 if (nir
[MESA_SHADER_GEOMETRY
]) {
2514 if (nir
[MESA_SHADER_TESS_CTRL
])
2515 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2517 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2521 gl_shader_stage last_xfb_stage
= MESA_SHADER_VERTEX
;
2523 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2528 bool uses_xfb
= nir
[last_xfb_stage
] &&
2529 radv_nir_stage_uses_xfb(nir
[last_xfb_stage
]);
2531 if (!device
->physical_device
->use_ngg_streamout
&& uses_xfb
) {
2532 if (nir
[MESA_SHADER_TESS_CTRL
])
2533 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2535 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2538 /* Determine if the pipeline is eligible for the NGG passthrough
2539 * mode. It can't be enabled for geometry shaders, for NGG
2540 * streamout or for vertex shaders that export the primitive ID
2541 * (this is checked later because we don't have the info here.)
2543 if (!nir
[MESA_SHADER_GEOMETRY
] && !uses_xfb
) {
2544 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2545 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
) {
2546 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg_passthrough
= true;
2547 } else if (nir
[MESA_SHADER_VERTEX
] &&
2548 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) {
2549 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg_passthrough
= true;
2554 for(int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
2555 keys
[i
].has_multiview_view_index
= key
->has_multiview_view_index
;
2557 keys
[MESA_SHADER_FRAGMENT
].fs
.col_format
= key
->col_format
;
2558 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int8
= key
->is_int8
;
2559 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int10
= key
->is_int10
;
2560 keys
[MESA_SHADER_FRAGMENT
].fs
.log2_ps_iter_samples
= key
->log2_ps_iter_samples
;
2561 keys
[MESA_SHADER_FRAGMENT
].fs
.num_samples
= key
->num_samples
;
2563 if (nir
[MESA_SHADER_COMPUTE
]) {
2564 keys
[MESA_SHADER_COMPUTE
].cs
.subgroup_size
= key
->compute_subgroup_size
;
2569 radv_get_wave_size(struct radv_device
*device
,
2570 const VkPipelineShaderStageCreateInfo
*pStage
,
2571 gl_shader_stage stage
,
2572 const struct radv_shader_variant_key
*key
)
2574 if (stage
== MESA_SHADER_GEOMETRY
&& !key
->vs_common_out
.as_ngg
)
2576 else if (stage
== MESA_SHADER_COMPUTE
) {
2577 if (key
->cs
.subgroup_size
) {
2578 /* Return the required subgroup size if specified. */
2579 return key
->cs
.subgroup_size
;
2581 return device
->physical_device
->cs_wave_size
;
2583 else if (stage
== MESA_SHADER_FRAGMENT
)
2584 return device
->physical_device
->ps_wave_size
;
2586 return device
->physical_device
->ge_wave_size
;
2590 radv_get_ballot_bit_size(struct radv_device
*device
,
2591 const VkPipelineShaderStageCreateInfo
*pStage
,
2592 gl_shader_stage stage
,
2593 const struct radv_shader_variant_key
*key
)
2595 if (stage
== MESA_SHADER_COMPUTE
&& key
->cs
.subgroup_size
)
2596 return key
->cs
.subgroup_size
;
2601 radv_fill_shader_info(struct radv_pipeline
*pipeline
,
2602 const VkPipelineShaderStageCreateInfo
**pStages
,
2603 struct radv_shader_variant_key
*keys
,
2604 struct radv_shader_info
*infos
,
2607 unsigned active_stages
= 0;
2608 unsigned filled_stages
= 0;
2610 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2612 active_stages
|= (1 << i
);
2615 if (nir
[MESA_SHADER_FRAGMENT
]) {
2616 radv_nir_shader_info_init(&infos
[MESA_SHADER_FRAGMENT
]);
2617 radv_nir_shader_info_pass(nir
[MESA_SHADER_FRAGMENT
],
2619 &keys
[MESA_SHADER_FRAGMENT
],
2620 &infos
[MESA_SHADER_FRAGMENT
],
2621 pipeline
->device
->physical_device
->use_aco
);
2623 /* TODO: These are no longer used as keys we should refactor this */
2624 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
=
2625 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2626 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_layer_id
=
2627 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2628 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_clip_dists
=
2629 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2630 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_viewport_index
=
2631 infos
[MESA_SHADER_FRAGMENT
].ps
.viewport_index_input
;
2632 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_prim_id
=
2633 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2634 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_layer_id
=
2635 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2636 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_clip_dists
=
2637 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2638 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_viewport_index
=
2639 infos
[MESA_SHADER_FRAGMENT
].ps
.viewport_index_input
;
2641 /* NGG passthrough mode can't be enabled for vertex shaders
2642 * that export the primitive ID.
2644 * TODO: I should really refactor the keys logic.
2646 if (nir
[MESA_SHADER_VERTEX
] &&
2647 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
) {
2648 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg_passthrough
= false;
2651 filled_stages
|= (1 << MESA_SHADER_FRAGMENT
);
2654 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2655 infos
[MESA_SHADER_TESS_CTRL
].tcs
.tes_inputs_read
=
2656 nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
;
2657 infos
[MESA_SHADER_TESS_CTRL
].tcs
.tes_patch_inputs_read
=
2658 nir
[MESA_SHADER_TESS_EVAL
]->info
.patch_inputs_read
;
2661 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2662 nir
[MESA_SHADER_TESS_CTRL
]) {
2663 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2664 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2665 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2667 radv_nir_shader_info_init(&infos
[MESA_SHADER_TESS_CTRL
]);
2669 for (int i
= 0; i
< 2; i
++) {
2670 radv_nir_shader_info_pass(combined_nir
[i
],
2671 pipeline
->layout
, &key
,
2672 &infos
[MESA_SHADER_TESS_CTRL
],
2673 pipeline
->device
->physical_device
->use_aco
);
2676 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2677 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2678 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2679 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2681 filled_stages
|= (1 << MESA_SHADER_VERTEX
);
2682 filled_stages
|= (1 << MESA_SHADER_TESS_CTRL
);
2685 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2686 nir
[MESA_SHADER_GEOMETRY
]) {
2687 gl_shader_stage pre_stage
= nir
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2688 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2690 radv_nir_shader_info_init(&infos
[MESA_SHADER_GEOMETRY
]);
2692 for (int i
= 0; i
< 2; i
++) {
2693 radv_nir_shader_info_pass(combined_nir
[i
],
2696 &infos
[MESA_SHADER_GEOMETRY
],
2697 pipeline
->device
->physical_device
->use_aco
);
2700 filled_stages
|= (1 << pre_stage
);
2701 filled_stages
|= (1 << MESA_SHADER_GEOMETRY
);
2704 active_stages
^= filled_stages
;
2705 while (active_stages
) {
2706 int i
= u_bit_scan(&active_stages
);
2708 if (i
== MESA_SHADER_TESS_CTRL
) {
2709 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
=
2710 util_last_bit64(infos
[MESA_SHADER_VERTEX
].vs
.ls_outputs_written
);
2713 if (i
== MESA_SHADER_TESS_EVAL
) {
2714 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2715 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2716 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2717 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2720 radv_nir_shader_info_init(&infos
[i
]);
2721 radv_nir_shader_info_pass(nir
[i
], pipeline
->layout
,
2722 &keys
[i
], &infos
[i
], pipeline
->device
->physical_device
->use_aco
);
2725 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2727 infos
[i
].wave_size
=
2728 radv_get_wave_size(pipeline
->device
, pStages
[i
],
2730 infos
[i
].ballot_bit_size
=
2731 radv_get_ballot_bit_size(pipeline
->device
,
2739 merge_tess_info(struct shader_info
*tes_info
,
2740 const struct shader_info
*tcs_info
)
2742 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2744 * "PointMode. Controls generation of points rather than triangles
2745 * or lines. This functionality defaults to disabled, and is
2746 * enabled if either shader stage includes the execution mode.
2748 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2749 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2750 * and OutputVertices, it says:
2752 * "One mode must be set in at least one of the tessellation
2755 * So, the fields can be set in either the TCS or TES, but they must
2756 * agree if set in both. Our backend looks at TES, so bitwise-or in
2757 * the values from the TCS.
2759 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
2760 tes_info
->tess
.tcs_vertices_out
== 0 ||
2761 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
2762 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
2764 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2765 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2766 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
2767 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
2769 assert(tcs_info
->tess
.primitive_mode
== 0 ||
2770 tes_info
->tess
.primitive_mode
== 0 ||
2771 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
2772 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
2773 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
2774 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
2778 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT
*ext
)
2783 if (ext
->pPipelineCreationFeedback
) {
2784 ext
->pPipelineCreationFeedback
->flags
= 0;
2785 ext
->pPipelineCreationFeedback
->duration
= 0;
2788 for (unsigned i
= 0; i
< ext
->pipelineStageCreationFeedbackCount
; ++i
) {
2789 ext
->pPipelineStageCreationFeedbacks
[i
].flags
= 0;
2790 ext
->pPipelineStageCreationFeedbacks
[i
].duration
= 0;
2795 void radv_start_feedback(VkPipelineCreationFeedbackEXT
*feedback
)
2800 feedback
->duration
-= radv_get_current_time();
2801 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
2805 void radv_stop_feedback(VkPipelineCreationFeedbackEXT
*feedback
, bool cache_hit
)
2810 feedback
->duration
+= radv_get_current_time();
2811 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
|
2812 (cache_hit
? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
: 0);
2815 void radv_create_shaders(struct radv_pipeline
*pipeline
,
2816 struct radv_device
*device
,
2817 struct radv_pipeline_cache
*cache
,
2818 const struct radv_pipeline_key
*key
,
2819 const VkPipelineShaderStageCreateInfo
**pStages
,
2820 const VkPipelineCreateFlags flags
,
2821 VkPipelineCreationFeedbackEXT
*pipeline_feedback
,
2822 VkPipelineCreationFeedbackEXT
**stage_feedbacks
)
2824 struct radv_shader_module fs_m
= {0};
2825 struct radv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
2826 nir_shader
*nir
[MESA_SHADER_STAGES
] = {0};
2827 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2828 struct radv_shader_variant_key keys
[MESA_SHADER_STAGES
] = {{{{{0}}}}};
2829 struct radv_shader_info infos
[MESA_SHADER_STAGES
] = {0};
2830 unsigned char hash
[20], gs_copy_hash
[20];
2831 bool keep_executable_info
= (flags
& VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
) || device
->keep_shader_info
;
2832 bool keep_statistic_info
= (flags
& VK_PIPELINE_CREATE_CAPTURE_STATISTICS_BIT_KHR
) || device
->keep_shader_info
;
2834 radv_start_feedback(pipeline_feedback
);
2836 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2838 modules
[i
] = radv_shader_module_from_handle(pStages
[i
]->module
);
2839 if (modules
[i
]->nir
)
2840 _mesa_sha1_compute(modules
[i
]->nir
->info
.name
,
2841 strlen(modules
[i
]->nir
->info
.name
),
2844 pipeline
->active_stages
|= mesa_to_vk_shader_stage(i
);
2848 radv_hash_shaders(hash
, pStages
, pipeline
->layout
, key
, get_hash_flags(device
));
2849 memcpy(gs_copy_hash
, hash
, 20);
2850 gs_copy_hash
[0] ^= 1;
2852 bool found_in_application_cache
= true;
2853 if (modules
[MESA_SHADER_GEOMETRY
] && !keep_executable_info
&& !keep_statistic_info
) {
2854 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2855 radv_create_shader_variants_from_pipeline_cache(device
, cache
, gs_copy_hash
, variants
,
2856 &found_in_application_cache
);
2857 pipeline
->gs_copy_shader
= variants
[MESA_SHADER_GEOMETRY
];
2860 if (!keep_executable_info
&& !keep_statistic_info
&&
2861 radv_create_shader_variants_from_pipeline_cache(device
, cache
, hash
, pipeline
->shaders
,
2862 &found_in_application_cache
) &&
2863 (!modules
[MESA_SHADER_GEOMETRY
] || pipeline
->gs_copy_shader
)) {
2864 radv_stop_feedback(pipeline_feedback
, found_in_application_cache
);
2868 if (!modules
[MESA_SHADER_FRAGMENT
] && !modules
[MESA_SHADER_COMPUTE
]) {
2870 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
2871 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "noop_fs");
2872 fs_m
.nir
= fs_b
.shader
;
2873 modules
[MESA_SHADER_FRAGMENT
] = &fs_m
;
2876 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2877 const VkPipelineShaderStageCreateInfo
*stage
= pStages
[i
];
2878 unsigned subgroup_size
= 64, ballot_bit_size
= 64;
2883 radv_start_feedback(stage_feedbacks
[i
]);
2885 if (key
->compute_subgroup_size
) {
2886 /* Only compute shaders currently support requiring a
2887 * specific subgroup size.
2889 assert(i
== MESA_SHADER_COMPUTE
);
2890 subgroup_size
= key
->compute_subgroup_size
;
2891 ballot_bit_size
= key
->compute_subgroup_size
;
2894 nir
[i
] = radv_shader_compile_to_nir(device
, modules
[i
],
2895 stage
? stage
->pName
: "main", i
,
2896 stage
? stage
->pSpecializationInfo
: NULL
,
2897 flags
, pipeline
->layout
,
2898 subgroup_size
, ballot_bit_size
);
2900 /* We don't want to alter meta shaders IR directly so clone it
2903 if (nir
[i
]->info
.name
) {
2904 nir
[i
] = nir_shader_clone(NULL
, nir
[i
]);
2907 radv_stop_feedback(stage_feedbacks
[i
], false);
2910 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2911 nir_lower_patch_vertices(nir
[MESA_SHADER_TESS_EVAL
], nir
[MESA_SHADER_TESS_CTRL
]->info
.tess
.tcs_vertices_out
, NULL
);
2912 merge_tess_info(&nir
[MESA_SHADER_TESS_EVAL
]->info
, &nir
[MESA_SHADER_TESS_CTRL
]->info
);
2915 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
2916 radv_link_shaders(pipeline
, nir
);
2918 radv_set_linked_driver_locations(pipeline
, nir
, infos
);
2920 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2922 /* do this again since information such as outputs_read can be out-of-date */
2923 nir_shader_gather_info(nir
[i
], nir_shader_get_entrypoint(nir
[i
]));
2925 if (device
->physical_device
->use_aco
) {
2926 NIR_PASS_V(nir
[i
], nir_lower_non_uniform_access
,
2927 nir_lower_non_uniform_ubo_access
|
2928 nir_lower_non_uniform_ssbo_access
|
2929 nir_lower_non_uniform_texture_access
|
2930 nir_lower_non_uniform_image_access
);
2932 NIR_PASS_V(nir
[i
], nir_lower_bool_to_int32
);
2936 if (nir
[MESA_SHADER_FRAGMENT
])
2937 radv_lower_fs_io(nir
[MESA_SHADER_FRAGMENT
]);
2939 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2940 if (radv_can_dump_shader(device
, modules
[i
], false))
2941 nir_print_shader(nir
[i
], stderr
);
2944 radv_fill_shader_keys(device
, keys
, key
, nir
);
2946 radv_fill_shader_info(pipeline
, pStages
, keys
, infos
, nir
);
2948 if ((nir
[MESA_SHADER_VERTEX
] &&
2949 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) ||
2950 (nir
[MESA_SHADER_TESS_EVAL
] &&
2951 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
)) {
2952 struct gfx10_ngg_info
*ngg_info
;
2954 if (nir
[MESA_SHADER_GEOMETRY
])
2955 ngg_info
= &infos
[MESA_SHADER_GEOMETRY
].ngg_info
;
2956 else if (nir
[MESA_SHADER_TESS_CTRL
])
2957 ngg_info
= &infos
[MESA_SHADER_TESS_EVAL
].ngg_info
;
2959 ngg_info
= &infos
[MESA_SHADER_VERTEX
].ngg_info
;
2961 gfx10_get_ngg_info(key
, pipeline
, nir
, infos
, ngg_info
);
2962 } else if (nir
[MESA_SHADER_GEOMETRY
]) {
2963 struct gfx9_gs_info
*gs_info
=
2964 &infos
[MESA_SHADER_GEOMETRY
].gs_ring_info
;
2966 gfx9_get_gs_info(key
, pipeline
, nir
, infos
, gs_info
);
2969 if(modules
[MESA_SHADER_GEOMETRY
]) {
2970 struct radv_shader_binary
*gs_copy_binary
= NULL
;
2971 if (!pipeline
->gs_copy_shader
&&
2972 !radv_pipeline_has_ngg(pipeline
)) {
2973 struct radv_shader_info info
= {};
2974 struct radv_shader_variant_key key
= {};
2976 key
.has_multiview_view_index
=
2977 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
;
2979 radv_nir_shader_info_pass(nir
[MESA_SHADER_GEOMETRY
],
2980 pipeline
->layout
, &key
,
2981 &info
, pipeline
->device
->physical_device
->use_aco
);
2982 info
.wave_size
= 64; /* Wave32 not supported. */
2983 info
.ballot_bit_size
= 64;
2985 pipeline
->gs_copy_shader
= radv_create_gs_copy_shader(
2986 device
, nir
[MESA_SHADER_GEOMETRY
], &info
,
2987 &gs_copy_binary
, keep_executable_info
, keep_statistic_info
,
2988 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
);
2991 if (!keep_executable_info
&& !keep_statistic_info
&& pipeline
->gs_copy_shader
) {
2992 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2993 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2995 binaries
[MESA_SHADER_GEOMETRY
] = gs_copy_binary
;
2996 variants
[MESA_SHADER_GEOMETRY
] = pipeline
->gs_copy_shader
;
2998 radv_pipeline_cache_insert_shaders(device
, cache
,
3003 free(gs_copy_binary
);
3006 if (nir
[MESA_SHADER_FRAGMENT
]) {
3007 if (!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]) {
3008 radv_start_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
]);
3010 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] =
3011 radv_shader_variant_compile(device
, modules
[MESA_SHADER_FRAGMENT
], &nir
[MESA_SHADER_FRAGMENT
], 1,
3012 pipeline
->layout
, keys
+ MESA_SHADER_FRAGMENT
,
3013 infos
+ MESA_SHADER_FRAGMENT
,
3014 keep_executable_info
, keep_statistic_info
,
3015 &binaries
[MESA_SHADER_FRAGMENT
]);
3017 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
], false);
3021 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_TESS_CTRL
]) {
3022 if (!pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]) {
3023 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
3024 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
3025 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
3027 radv_start_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
]);
3029 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_TESS_CTRL
], combined_nir
, 2,
3031 &key
, &infos
[MESA_SHADER_TESS_CTRL
], keep_executable_info
,
3032 keep_statistic_info
, &binaries
[MESA_SHADER_TESS_CTRL
]);
3034 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
], false);
3036 modules
[MESA_SHADER_VERTEX
] = NULL
;
3037 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
3038 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
3041 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_GEOMETRY
]) {
3042 gl_shader_stage pre_stage
= modules
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
3043 if (!pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
3044 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
3046 radv_start_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
]);
3048 pipeline
->shaders
[MESA_SHADER_GEOMETRY
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_GEOMETRY
], combined_nir
, 2,
3050 &keys
[pre_stage
], &infos
[MESA_SHADER_GEOMETRY
], keep_executable_info
,
3051 keep_statistic_info
, &binaries
[MESA_SHADER_GEOMETRY
]);
3053 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
], false);
3055 modules
[pre_stage
] = NULL
;
3058 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
3059 if(modules
[i
] && !pipeline
->shaders
[i
]) {
3060 if (i
== MESA_SHADER_TESS_CTRL
) {
3061 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.ls_outputs_written
);
3063 if (i
== MESA_SHADER_TESS_EVAL
) {
3064 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
3065 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
3068 radv_start_feedback(stage_feedbacks
[i
]);
3070 pipeline
->shaders
[i
] = radv_shader_variant_compile(device
, modules
[i
], &nir
[i
], 1,
3072 keys
+ i
, infos
+ i
, keep_executable_info
,
3073 keep_statistic_info
, &binaries
[i
]);
3075 radv_stop_feedback(stage_feedbacks
[i
], false);
3079 if (!keep_executable_info
&& !keep_statistic_info
) {
3080 radv_pipeline_cache_insert_shaders(device
, cache
, hash
, pipeline
->shaders
,
3084 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
3087 ralloc_free(nir
[i
]);
3089 if (radv_can_dump_shader_stats(device
, modules
[i
]))
3090 radv_shader_dump_stats(device
,
3091 pipeline
->shaders
[i
],
3097 ralloc_free(fs_m
.nir
);
3099 radv_stop_feedback(pipeline_feedback
, false);
3103 radv_pipeline_stage_to_user_data_0(struct radv_pipeline
*pipeline
,
3104 gl_shader_stage stage
, enum chip_class chip_class
)
3106 bool has_gs
= radv_pipeline_has_gs(pipeline
);
3107 bool has_tess
= radv_pipeline_has_tess(pipeline
);
3108 bool has_ngg
= radv_pipeline_has_ngg(pipeline
);
3111 case MESA_SHADER_FRAGMENT
:
3112 return R_00B030_SPI_SHADER_USER_DATA_PS_0
;
3113 case MESA_SHADER_VERTEX
:
3115 if (chip_class
>= GFX10
) {
3116 return R_00B430_SPI_SHADER_USER_DATA_HS_0
;
3117 } else if (chip_class
== GFX9
) {
3118 return R_00B430_SPI_SHADER_USER_DATA_LS_0
;
3120 return R_00B530_SPI_SHADER_USER_DATA_LS_0
;
3126 if (chip_class
>= GFX10
) {
3127 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3129 return R_00B330_SPI_SHADER_USER_DATA_ES_0
;
3134 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3136 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3137 case MESA_SHADER_GEOMETRY
:
3138 return chip_class
== GFX9
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
3139 R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3140 case MESA_SHADER_COMPUTE
:
3141 return R_00B900_COMPUTE_USER_DATA_0
;
3142 case MESA_SHADER_TESS_CTRL
:
3143 return chip_class
== GFX9
? R_00B430_SPI_SHADER_USER_DATA_LS_0
:
3144 R_00B430_SPI_SHADER_USER_DATA_HS_0
;
3145 case MESA_SHADER_TESS_EVAL
:
3147 return chip_class
>= GFX10
? R_00B230_SPI_SHADER_USER_DATA_GS_0
:
3148 R_00B330_SPI_SHADER_USER_DATA_ES_0
;
3149 } else if (has_ngg
) {
3150 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3152 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3155 unreachable("unknown shader");
3159 struct radv_bin_size_entry
{
3165 radv_gfx9_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3167 static const struct radv_bin_size_entry color_size_table
[][3][9] = {
3171 /* One shader engine */
3177 { UINT_MAX
, { 0, 0}},
3180 /* Two shader engines */
3186 { UINT_MAX
, { 0, 0}},
3189 /* Four shader engines */
3194 { UINT_MAX
, { 0, 0}},
3200 /* One shader engine */
3206 { UINT_MAX
, { 0, 0}},
3209 /* Two shader engines */
3215 { UINT_MAX
, { 0, 0}},
3218 /* Four shader engines */
3225 { UINT_MAX
, { 0, 0}},
3231 /* One shader engine */
3238 { UINT_MAX
, { 0, 0}},
3241 /* Two shader engines */
3249 { UINT_MAX
, { 0, 0}},
3252 /* Four shader engines */
3260 { UINT_MAX
, { 0, 0}},
3264 static const struct radv_bin_size_entry ds_size_table
[][3][9] = {
3268 // One shader engine
3275 { UINT_MAX
, { 0, 0}},
3278 // Two shader engines
3286 { UINT_MAX
, { 0, 0}},
3289 // Four shader engines
3297 { UINT_MAX
, { 0, 0}},
3303 // One shader engine
3311 { UINT_MAX
, { 0, 0}},
3314 // Two shader engines
3323 { UINT_MAX
, { 0, 0}},
3326 // Four shader engines
3335 { UINT_MAX
, { 0, 0}},
3341 // One shader engine
3349 { UINT_MAX
, { 0, 0}},
3352 // Two shader engines
3361 { UINT_MAX
, { 0, 0}},
3364 // Four shader engines
3372 { UINT_MAX
, { 0, 0}},
3377 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3378 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3379 VkExtent2D extent
= {512, 512};
3381 unsigned log_num_rb_per_se
=
3382 util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.num_render_backends
/
3383 pipeline
->device
->physical_device
->rad_info
.max_se
);
3384 unsigned log_num_se
= util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.max_se
);
3386 unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3387 unsigned ps_iter_samples
= 1u << G_028804_PS_ITER_SAMPLES(pipeline
->graphics
.ms
.db_eqaa
);
3388 unsigned effective_samples
= total_samples
;
3389 unsigned color_bytes_per_pixel
= 0;
3391 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3392 radv_pipeline_get_color_blend_state(pCreateInfo
);
3394 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3395 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3398 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3401 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3402 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3405 /* MSAA images typically don't use all samples all the time. */
3406 if (effective_samples
>= 2 && ps_iter_samples
<= 1)
3407 effective_samples
= 2;
3408 color_bytes_per_pixel
*= effective_samples
;
3411 const struct radv_bin_size_entry
*color_entry
= color_size_table
[log_num_rb_per_se
][log_num_se
];
3412 while(color_entry
[1].bpp
<= color_bytes_per_pixel
)
3415 extent
= color_entry
->extent
;
3417 if (subpass
->depth_stencil_attachment
) {
3418 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3420 /* Coefficients taken from AMDVLK */
3421 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3422 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3423 unsigned ds_bytes_per_pixel
= 4 * (depth_coeff
+ stencil_coeff
) * total_samples
;
3425 const struct radv_bin_size_entry
*ds_entry
= ds_size_table
[log_num_rb_per_se
][log_num_se
];
3426 while(ds_entry
[1].bpp
<= ds_bytes_per_pixel
)
3429 if (ds_entry
->extent
.width
* ds_entry
->extent
.height
< extent
.width
* extent
.height
)
3430 extent
= ds_entry
->extent
;
3437 radv_gfx10_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3439 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3440 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3441 VkExtent2D extent
= {512, 512};
3443 const unsigned db_tag_size
= 64;
3444 const unsigned db_tag_count
= 312;
3445 const unsigned color_tag_size
= 1024;
3446 const unsigned color_tag_count
= 31;
3447 const unsigned fmask_tag_size
= 256;
3448 const unsigned fmask_tag_count
= 44;
3450 const unsigned rb_count
= pipeline
->device
->physical_device
->rad_info
.num_render_backends
;
3451 const unsigned pipe_count
= MAX2(rb_count
, pipeline
->device
->physical_device
->rad_info
.num_sdp_interfaces
);
3453 const unsigned db_tag_part
= (db_tag_count
* rb_count
/ pipe_count
) * db_tag_size
* pipe_count
;
3454 const unsigned color_tag_part
= (color_tag_count
* rb_count
/ pipe_count
) * color_tag_size
* pipe_count
;
3455 const unsigned fmask_tag_part
= (fmask_tag_count
* rb_count
/ pipe_count
) * fmask_tag_size
* pipe_count
;
3457 const unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3458 const unsigned samples_log
= util_logbase2_ceil(total_samples
);
3460 unsigned color_bytes_per_pixel
= 0;
3461 unsigned fmask_bytes_per_pixel
= 0;
3463 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3464 radv_pipeline_get_color_blend_state(pCreateInfo
);
3466 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3467 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3470 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3473 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3474 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3476 if (total_samples
> 1) {
3477 assert(samples_log
<= 3);
3478 const unsigned fmask_array
[] = {0, 1, 1, 4};
3479 fmask_bytes_per_pixel
+= fmask_array
[samples_log
];
3483 color_bytes_per_pixel
*= total_samples
;
3485 color_bytes_per_pixel
= MAX2(color_bytes_per_pixel
, 1);
3487 const unsigned color_pixel_count_log
= util_logbase2(color_tag_part
/ color_bytes_per_pixel
);
3488 extent
.width
= 1ull << ((color_pixel_count_log
+ 1) / 2);
3489 extent
.height
= 1ull << (color_pixel_count_log
/ 2);
3491 if (fmask_bytes_per_pixel
) {
3492 const unsigned fmask_pixel_count_log
= util_logbase2(fmask_tag_part
/ fmask_bytes_per_pixel
);
3494 const VkExtent2D fmask_extent
= (VkExtent2D
){
3495 .width
= 1ull << ((fmask_pixel_count_log
+ 1) / 2),
3496 .height
= 1ull << (color_pixel_count_log
/ 2)
3499 if (fmask_extent
.width
* fmask_extent
.height
< extent
.width
* extent
.height
)
3500 extent
= fmask_extent
;
3503 if (subpass
->depth_stencil_attachment
) {
3504 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3506 /* Coefficients taken from AMDVLK */
3507 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3508 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3509 unsigned db_bytes_per_pixel
= (depth_coeff
+ stencil_coeff
) * total_samples
;
3511 const unsigned db_pixel_count_log
= util_logbase2(db_tag_part
/ db_bytes_per_pixel
);
3513 const VkExtent2D db_extent
= (VkExtent2D
){
3514 .width
= 1ull << ((db_pixel_count_log
+ 1) / 2),
3515 .height
= 1ull << (color_pixel_count_log
/ 2)
3518 if (db_extent
.width
* db_extent
.height
< extent
.width
* extent
.height
)
3522 extent
.width
= MAX2(extent
.width
, 128);
3523 extent
.height
= MAX2(extent
.width
, 64);
3529 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3530 struct radv_pipeline
*pipeline
,
3531 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3533 uint32_t pa_sc_binner_cntl_0
=
3534 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC
) |
3535 S_028C44_DISABLE_START_OF_PRIM(1);
3536 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3538 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3539 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3540 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3541 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3542 radv_pipeline_get_color_blend_state(pCreateInfo
);
3543 unsigned min_bytes_per_pixel
= 0;
3546 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3547 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3550 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3553 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3554 unsigned bytes
= vk_format_get_blocksize(format
);
3555 if (!min_bytes_per_pixel
|| bytes
< min_bytes_per_pixel
)
3556 min_bytes_per_pixel
= bytes
;
3560 pa_sc_binner_cntl_0
=
3561 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC
) |
3562 S_028C44_BIN_SIZE_X(0) |
3563 S_028C44_BIN_SIZE_Y(0) |
3564 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3565 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel
<= 4 ? 2 : 1) | /* 128 or 64 */
3566 S_028C44_DISABLE_START_OF_PRIM(1);
3569 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3570 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3573 struct radv_binning_settings
3574 radv_get_binning_settings(const struct radv_physical_device
*pdev
)
3576 struct radv_binning_settings settings
;
3577 if (pdev
->rad_info
.has_dedicated_vram
) {
3578 if (pdev
->rad_info
.num_render_backends
> 4) {
3579 settings
.context_states_per_bin
= 1;
3580 settings
.persistent_states_per_bin
= 1;
3582 settings
.context_states_per_bin
= 3;
3583 settings
.persistent_states_per_bin
= 8;
3585 settings
.fpovs_per_batch
= 63;
3587 /* The context states are affected by the scissor bug. */
3588 settings
.context_states_per_bin
= 6;
3589 /* 32 causes hangs for RAVEN. */
3590 settings
.persistent_states_per_bin
= 16;
3591 settings
.fpovs_per_batch
= 63;
3594 if (pdev
->rad_info
.has_gfx9_scissor_bug
)
3595 settings
.context_states_per_bin
= 1;
3601 radv_pipeline_generate_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3602 struct radv_pipeline
*pipeline
,
3603 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3604 const struct radv_blend_state
*blend
)
3606 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
3609 VkExtent2D bin_size
;
3610 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3611 bin_size
= radv_gfx10_compute_bin_size(pipeline
, pCreateInfo
);
3612 } else if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3613 bin_size
= radv_gfx9_compute_bin_size(pipeline
, pCreateInfo
);
3615 unreachable("Unhandled generation for binning bin size calculation");
3617 if (pipeline
->device
->pbb_allowed
&& bin_size
.width
&& bin_size
.height
) {
3618 struct radv_binning_settings settings
=
3619 radv_get_binning_settings(pipeline
->device
->physical_device
);
3621 bool disable_start_of_prim
= true;
3622 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3624 const struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3626 if (pipeline
->device
->dfsm_allowed
&& ps
&&
3627 !ps
->info
.ps
.can_discard
&&
3628 !ps
->info
.ps
.writes_memory
&&
3629 blend
->cb_target_enabled_4bit
) {
3630 db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_AUTO
);
3631 disable_start_of_prim
= (blend
->blend_enable_4bit
& blend
->cb_target_enabled_4bit
) != 0;
3634 const uint32_t pa_sc_binner_cntl_0
=
3635 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED
) |
3636 S_028C44_BIN_SIZE_X(bin_size
.width
== 16) |
3637 S_028C44_BIN_SIZE_Y(bin_size
.height
== 16) |
3638 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size
.width
, 32)) - 5) |
3639 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size
.height
, 32)) - 5) |
3640 S_028C44_CONTEXT_STATES_PER_BIN(settings
.context_states_per_bin
- 1) |
3641 S_028C44_PERSISTENT_STATES_PER_BIN(settings
.persistent_states_per_bin
- 1) |
3642 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim
) |
3643 S_028C44_FPOVS_PER_BATCH(settings
.fpovs_per_batch
) |
3644 S_028C44_OPTIMAL_BIN_SELECTION(1);
3646 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3647 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3649 radv_pipeline_generate_disabled_binning_state(ctx_cs
, pipeline
, pCreateInfo
);
3654 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf
*ctx_cs
,
3655 struct radv_pipeline
*pipeline
,
3656 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3657 const struct radv_graphics_pipeline_create_info
*extra
)
3659 const VkPipelineDepthStencilStateCreateInfo
*vkds
= radv_pipeline_get_depth_stencil_state(pCreateInfo
);
3660 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3661 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3662 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3663 struct radv_render_pass_attachment
*attachment
= NULL
;
3664 uint32_t db_depth_control
= 0, db_stencil_control
= 0;
3665 uint32_t db_render_control
= 0, db_render_override2
= 0;
3666 uint32_t db_render_override
= 0;
3668 if (subpass
->depth_stencil_attachment
)
3669 attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3671 bool has_depth_attachment
= attachment
&& vk_format_is_depth(attachment
->format
);
3672 bool has_stencil_attachment
= attachment
&& vk_format_is_stencil(attachment
->format
);
3674 if (vkds
&& has_depth_attachment
) {
3675 db_depth_control
= S_028800_Z_ENABLE(vkds
->depthTestEnable
? 1 : 0) |
3676 S_028800_Z_WRITE_ENABLE(vkds
->depthWriteEnable
? 1 : 0) |
3677 S_028800_ZFUNC(vkds
->depthCompareOp
) |
3678 S_028800_DEPTH_BOUNDS_ENABLE(vkds
->depthBoundsTestEnable
? 1 : 0);
3680 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3681 db_render_override2
|= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment
->samples
> 2);
3684 if (has_stencil_attachment
&& vkds
&& vkds
->stencilTestEnable
) {
3685 db_depth_control
|= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3686 db_depth_control
|= S_028800_STENCILFUNC(vkds
->front
.compareOp
);
3687 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds
->front
.failOp
));
3688 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds
->front
.passOp
));
3689 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds
->front
.depthFailOp
));
3691 db_depth_control
|= S_028800_STENCILFUNC_BF(vkds
->back
.compareOp
);
3692 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds
->back
.failOp
));
3693 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds
->back
.passOp
));
3694 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds
->back
.depthFailOp
));
3697 if (attachment
&& extra
) {
3698 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(extra
->db_depth_clear
);
3699 db_render_control
|= S_028000_STENCIL_CLEAR_ENABLE(extra
->db_stencil_clear
);
3701 db_render_control
|= S_028000_RESUMMARIZE_ENABLE(extra
->resummarize_enable
);
3702 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(extra
->depth_compress_disable
);
3703 db_render_control
|= S_028000_STENCIL_COMPRESS_DISABLE(extra
->stencil_compress_disable
);
3704 db_render_override2
|= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra
->db_depth_disable_expclear
);
3705 db_render_override2
|= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra
->db_stencil_disable_expclear
);
3708 db_render_override
|= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
3709 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
3711 if (!pCreateInfo
->pRasterizationState
->depthClampEnable
&&
3712 ps
->info
.ps
.writes_z
) {
3713 /* From VK_EXT_depth_range_unrestricted spec:
3715 * "The behavior described in Primitive Clipping still applies.
3716 * If depth clamping is disabled the depth values are still
3717 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3718 * depth clamping is enabled the above equation is ignored and
3719 * the depth values are instead clamped to the VkViewport
3720 * minDepth and maxDepth values, which in the case of this
3721 * extension can be outside of the 0.0 to 1.0 range."
3723 db_render_override
|= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3726 radeon_set_context_reg(ctx_cs
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
3727 radeon_set_context_reg(ctx_cs
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
3729 radeon_set_context_reg(ctx_cs
, R_028000_DB_RENDER_CONTROL
, db_render_control
);
3730 radeon_set_context_reg(ctx_cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
3731 radeon_set_context_reg(ctx_cs
, R_028010_DB_RENDER_OVERRIDE2
, db_render_override2
);
3735 radv_pipeline_generate_blend_state(struct radeon_cmdbuf
*ctx_cs
,
3736 struct radv_pipeline
*pipeline
,
3737 const struct radv_blend_state
*blend
)
3739 radeon_set_context_reg_seq(ctx_cs
, R_028780_CB_BLEND0_CONTROL
, 8);
3740 radeon_emit_array(ctx_cs
, blend
->cb_blend_control
,
3742 radeon_set_context_reg(ctx_cs
, R_028808_CB_COLOR_CONTROL
, blend
->cb_color_control
);
3743 radeon_set_context_reg(ctx_cs
, R_028B70_DB_ALPHA_TO_MASK
, blend
->db_alpha_to_mask
);
3745 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
3747 radeon_set_context_reg_seq(ctx_cs
, R_028760_SX_MRT0_BLEND_OPT
, 8);
3748 radeon_emit_array(ctx_cs
, blend
->sx_mrt_blend_opt
, 8);
3751 radeon_set_context_reg(ctx_cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
3753 radeon_set_context_reg(ctx_cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
3754 radeon_set_context_reg(ctx_cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
3756 pipeline
->graphics
.col_format
= blend
->spi_shader_col_format
;
3757 pipeline
->graphics
.cb_target_mask
= blend
->cb_target_mask
;
3760 static const VkConservativeRasterizationModeEXT
3761 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo
*pCreateInfo
)
3763 const VkPipelineRasterizationConservativeStateCreateInfoEXT
*conservative_raster
=
3764 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT
);
3766 if (!conservative_raster
)
3767 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
;
3768 return conservative_raster
->conservativeRasterizationMode
;
3772 radv_pipeline_generate_raster_state(struct radeon_cmdbuf
*ctx_cs
,
3773 struct radv_pipeline
*pipeline
,
3774 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3776 const VkPipelineRasterizationStateCreateInfo
*vkraster
= pCreateInfo
->pRasterizationState
;
3777 const VkConservativeRasterizationModeEXT mode
=
3778 radv_get_conservative_raster_mode(vkraster
);
3779 uint32_t pa_sc_conservative_rast
= S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3780 bool depth_clip_disable
= vkraster
->depthClampEnable
;
3782 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*depth_clip_state
=
3783 vk_find_struct_const(vkraster
->pNext
, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
3784 if (depth_clip_state
) {
3785 depth_clip_disable
= !depth_clip_state
->depthClipEnable
;
3788 radeon_set_context_reg(ctx_cs
, R_028810_PA_CL_CLIP_CNTL
,
3789 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3790 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable
? 1 : 0) |
3791 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable
? 1 : 0) |
3792 S_028810_DX_RASTERIZATION_KILL(vkraster
->rasterizerDiscardEnable
? 1 : 0) |
3793 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3795 radeon_set_context_reg(ctx_cs
, R_0286D4_SPI_INTERP_CONTROL_0
,
3796 S_0286D4_FLAT_SHADE_ENA(1) |
3797 S_0286D4_PNT_SPRITE_ENA(1) |
3798 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
3799 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
3800 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
3801 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
3802 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3804 radeon_set_context_reg(ctx_cs
, R_028BE4_PA_SU_VTX_CNTL
,
3805 S_028BE4_PIX_CENTER(1) | // TODO verify
3806 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN
) |
3807 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
3809 radeon_set_context_reg(ctx_cs
, R_028814_PA_SU_SC_MODE_CNTL
,
3810 S_028814_FACE(vkraster
->frontFace
) |
3811 S_028814_CULL_FRONT(!!(vkraster
->cullMode
& VK_CULL_MODE_FRONT_BIT
)) |
3812 S_028814_CULL_BACK(!!(vkraster
->cullMode
& VK_CULL_MODE_BACK_BIT
)) |
3813 S_028814_POLY_MODE(vkraster
->polygonMode
!= VK_POLYGON_MODE_FILL
) |
3814 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3815 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3816 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3817 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3818 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster
->depthBiasEnable
? 1 : 0));
3820 /* Conservative rasterization. */
3821 if (mode
!= VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
) {
3822 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3824 ms
->pa_sc_aa_config
|= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3825 ms
->db_eqaa
|= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3826 S_028804_OVERRASTERIZATION_AMOUNT(4);
3828 pa_sc_conservative_rast
= S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3829 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3830 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3832 if (mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT
) {
3833 pa_sc_conservative_rast
|=
3834 S_028C4C_OVER_RAST_ENABLE(1) |
3835 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3836 S_028C4C_UNDER_RAST_ENABLE(0) |
3837 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3838 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3840 assert(mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT
);
3841 pa_sc_conservative_rast
|=
3842 S_028C4C_OVER_RAST_ENABLE(0) |
3843 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3844 S_028C4C_UNDER_RAST_ENABLE(1) |
3845 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3846 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3850 radeon_set_context_reg(ctx_cs
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
3851 pa_sc_conservative_rast
);
3856 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf
*ctx_cs
,
3857 struct radv_pipeline
*pipeline
)
3859 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3861 radeon_set_context_reg_seq(ctx_cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
3862 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[0]);
3863 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[1]);
3865 radeon_set_context_reg(ctx_cs
, R_028804_DB_EQAA
, ms
->db_eqaa
);
3866 radeon_set_context_reg(ctx_cs
, R_028A48_PA_SC_MODE_CNTL_0
, ms
->pa_sc_mode_cntl_0
);
3867 radeon_set_context_reg(ctx_cs
, R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
3868 radeon_set_context_reg(ctx_cs
, R_028BDC_PA_SC_LINE_CNTL
, ms
->pa_sc_line_cntl
);
3869 radeon_set_context_reg(ctx_cs
, R_028BE0_PA_SC_AA_CONFIG
, ms
->pa_sc_aa_config
);
3871 /* The exclusion bits can be set to improve rasterization efficiency
3872 * if no sample lies on the pixel boundary (-8 sample offset). It's
3873 * currently always TRUE because the driver doesn't support 16 samples.
3875 bool exclusion
= pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
3876 radeon_set_context_reg(ctx_cs
, R_02882C_PA_SU_PRIM_FILTER_CNTL
,
3877 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) |
3878 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3880 /* GFX9: Flush DFSM when the AA mode changes. */
3881 if (pipeline
->device
->dfsm_allowed
) {
3882 radeon_emit(ctx_cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3883 radeon_emit(ctx_cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3888 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf
*ctx_cs
,
3889 struct radv_pipeline
*pipeline
)
3891 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3892 const struct radv_shader_variant
*vs
=
3893 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] ?
3894 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] :
3895 pipeline
->shaders
[MESA_SHADER_VERTEX
];
3896 unsigned vgt_primitiveid_en
= 0;
3897 uint32_t vgt_gs_mode
= 0;
3899 if (radv_pipeline_has_ngg(pipeline
))
3902 if (radv_pipeline_has_gs(pipeline
)) {
3903 const struct radv_shader_variant
*gs
=
3904 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3906 vgt_gs_mode
= ac_vgt_gs_mode(gs
->info
.gs
.vertices_out
,
3907 pipeline
->device
->physical_device
->rad_info
.chip_class
);
3908 } else if (outinfo
->export_prim_id
|| vs
->info
.uses_prim_id
) {
3909 vgt_gs_mode
= S_028A40_MODE(V_028A40_GS_SCENARIO_A
);
3910 vgt_primitiveid_en
|= S_028A84_PRIMITIVEID_EN(1);
3913 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
, vgt_primitiveid_en
);
3914 radeon_set_context_reg(ctx_cs
, R_028A40_VGT_GS_MODE
, vgt_gs_mode
);
3918 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf
*ctx_cs
,
3919 struct radeon_cmdbuf
*cs
,
3920 struct radv_pipeline
*pipeline
,
3921 struct radv_shader_variant
*shader
)
3923 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3925 radeon_set_sh_reg_seq(cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
3926 radeon_emit(cs
, va
>> 8);
3927 radeon_emit(cs
, S_00B124_MEM_BASE(va
>> 40));
3928 radeon_emit(cs
, shader
->config
.rsrc1
);
3929 radeon_emit(cs
, shader
->config
.rsrc2
);
3931 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3932 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3933 clip_dist_mask
= outinfo
->clip_dist_mask
;
3934 cull_dist_mask
= outinfo
->cull_dist_mask
;
3935 total_mask
= clip_dist_mask
| cull_dist_mask
;
3936 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3937 outinfo
->writes_layer
||
3938 outinfo
->writes_viewport_index
;
3939 unsigned spi_vs_out_config
, nparams
;
3941 /* VS is required to export at least one param. */
3942 nparams
= MAX2(outinfo
->param_exports
, 1);
3943 spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
3945 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3946 spi_vs_out_config
|= S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0);
3949 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
, spi_vs_out_config
);
3951 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3952 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3953 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3954 V_02870C_SPI_SHADER_4COMP
:
3955 V_02870C_SPI_SHADER_NONE
) |
3956 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3957 V_02870C_SPI_SHADER_4COMP
:
3958 V_02870C_SPI_SHADER_NONE
) |
3959 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3960 V_02870C_SPI_SHADER_4COMP
:
3961 V_02870C_SPI_SHADER_NONE
));
3963 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
3964 S_028818_VTX_W0_FMT(1) |
3965 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3966 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3967 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3969 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3970 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3971 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3972 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3973 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3974 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3975 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3976 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3977 cull_dist_mask
<< 8 |
3980 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
3981 radeon_set_context_reg(ctx_cs
, R_028AB4_VGT_REUSE_OFF
,
3982 outinfo
->writes_viewport_index
);
3986 radv_pipeline_generate_hw_es(struct radeon_cmdbuf
*cs
,
3987 struct radv_pipeline
*pipeline
,
3988 struct radv_shader_variant
*shader
)
3990 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3992 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
3993 radeon_emit(cs
, va
>> 8);
3994 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3995 radeon_emit(cs
, shader
->config
.rsrc1
);
3996 radeon_emit(cs
, shader
->config
.rsrc2
);
4000 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf
*cs
,
4001 struct radv_pipeline
*pipeline
,
4002 struct radv_shader_variant
*shader
,
4003 const struct radv_tessellation_state
*tess
)
4005 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
4006 uint32_t rsrc2
= shader
->config
.rsrc2
;
4008 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
4009 radeon_emit(cs
, va
>> 8);
4010 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
4012 rsrc2
|= S_00B52C_LDS_SIZE(tess
->lds_size
);
4013 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX7
&&
4014 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
4015 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
4017 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
4018 radeon_emit(cs
, shader
->config
.rsrc1
);
4019 radeon_emit(cs
, rsrc2
);
4023 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf
*ctx_cs
,
4024 struct radeon_cmdbuf
*cs
,
4025 struct radv_pipeline
*pipeline
,
4026 struct radv_shader_variant
*shader
)
4028 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
4029 gl_shader_stage es_type
=
4030 radv_pipeline_has_tess(pipeline
) ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
4031 struct radv_shader_variant
*es
=
4032 es_type
== MESA_SHADER_TESS_EVAL
? pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] : pipeline
->shaders
[MESA_SHADER_VERTEX
];
4033 const struct gfx10_ngg_info
*ngg_state
= &shader
->info
.ngg_info
;
4035 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
4036 radeon_emit(cs
, va
>> 8);
4037 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
4038 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
4039 radeon_emit(cs
, shader
->config
.rsrc1
);
4040 radeon_emit(cs
, shader
->config
.rsrc2
);
4042 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
4043 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
4044 clip_dist_mask
= outinfo
->clip_dist_mask
;
4045 cull_dist_mask
= outinfo
->cull_dist_mask
;
4046 total_mask
= clip_dist_mask
| cull_dist_mask
;
4047 bool misc_vec_ena
= outinfo
->writes_pointsize
||
4048 outinfo
->writes_layer
||
4049 outinfo
->writes_viewport_index
;
4050 bool es_enable_prim_id
= outinfo
->export_prim_id
||
4051 (es
&& es
->info
.uses_prim_id
);
4052 bool break_wave_at_eoi
= false;
4056 if (es_type
== MESA_SHADER_TESS_EVAL
) {
4057 struct radv_shader_variant
*gs
=
4058 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4060 if (es_enable_prim_id
|| (gs
&& gs
->info
.uses_prim_id
))
4061 break_wave_at_eoi
= true;
4064 nparams
= MAX2(outinfo
->param_exports
, 1);
4065 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
4066 S_0286C4_VS_EXPORT_COUNT(nparams
- 1) |
4067 S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0));
4069 radeon_set_context_reg(ctx_cs
, R_028708_SPI_SHADER_IDX_FORMAT
,
4070 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP
));
4071 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
4072 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
4073 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
4074 V_02870C_SPI_SHADER_4COMP
:
4075 V_02870C_SPI_SHADER_NONE
) |
4076 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
4077 V_02870C_SPI_SHADER_4COMP
:
4078 V_02870C_SPI_SHADER_NONE
) |
4079 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
4080 V_02870C_SPI_SHADER_4COMP
:
4081 V_02870C_SPI_SHADER_NONE
));
4083 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
4084 S_028818_VTX_W0_FMT(1) |
4085 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
4086 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
4087 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
4088 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
4089 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
4090 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
4091 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
4092 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
4093 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
4094 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
4095 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
4096 cull_dist_mask
<< 8 |
4099 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
,
4100 S_028A84_PRIMITIVEID_EN(es_enable_prim_id
) |
4101 S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo
->export_prim_id
));
4103 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
4104 ngg_state
->vgt_esgs_ring_itemsize
);
4106 /* NGG specific registers. */
4107 struct radv_shader_variant
*gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4108 uint32_t gs_num_invocations
= gs
? gs
->info
.gs
.invocations
: 1;
4110 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4111 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state
->hw_max_esverts
) |
4112 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state
->max_gsprims
) |
4113 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state
->max_gsprims
* gs_num_invocations
));
4114 radeon_set_context_reg(ctx_cs
, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP
,
4115 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state
->max_out_verts
));
4116 radeon_set_context_reg(ctx_cs
, R_028B4C_GE_NGG_SUBGRP_CNTL
,
4117 S_028B4C_PRIM_AMP_FACTOR(ngg_state
->prim_amp_factor
) |
4118 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
4119 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
4120 S_028B90_CNT(gs_num_invocations
) |
4121 S_028B90_ENABLE(gs_num_invocations
> 1) |
4122 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state
->max_vert_out_per_gs_instance
));
4124 /* User edge flags are set by the pos exports. If user edge flags are
4125 * not used, we must use hw-generated edge flags and pass them via
4126 * the prim export to prevent drawing lines on internal edges of
4127 * decomposed primitives (such as quads) with polygon mode = lines.
4129 * TODO: We should combine hw-generated edge flags with user edge
4130 * flags in the shader.
4132 radeon_set_context_reg(ctx_cs
, R_028838_PA_CL_NGG_CNTL
,
4133 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline
) &&
4134 !radv_pipeline_has_gs(pipeline
)));
4136 ge_cntl
= S_03096C_PRIM_GRP_SIZE(ngg_state
->max_gsprims
) |
4137 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
4138 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
);
4140 /* Bug workaround for a possible hang with non-tessellation cases.
4141 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
4143 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
4145 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX10
&&
4146 !radv_pipeline_has_tess(pipeline
) &&
4147 ngg_state
->hw_max_esverts
!= 256) {
4148 ge_cntl
&= C_03096C_VERT_GRP_SIZE
;
4150 if (ngg_state
->hw_max_esverts
> 5) {
4151 ge_cntl
|= S_03096C_VERT_GRP_SIZE(ngg_state
->hw_max_esverts
- 5);
4155 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
, ge_cntl
);
4159 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf
*cs
,
4160 struct radv_pipeline
*pipeline
,
4161 struct radv_shader_variant
*shader
,
4162 const struct radv_tessellation_state
*tess
)
4164 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
4166 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4167 unsigned hs_rsrc2
= shader
->config
.rsrc2
;
4169 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4170 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX10(tess
->lds_size
);
4172 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX9(tess
->lds_size
);
4175 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4176 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
4177 radeon_emit(cs
, va
>> 8);
4178 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
4180 radeon_set_sh_reg_seq(cs
, R_00B410_SPI_SHADER_PGM_LO_LS
, 2);
4181 radeon_emit(cs
, va
>> 8);
4182 radeon_emit(cs
, S_00B414_MEM_BASE(va
>> 40));
4185 radeon_set_sh_reg_seq(cs
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
, 2);
4186 radeon_emit(cs
, shader
->config
.rsrc1
);
4187 radeon_emit(cs
, hs_rsrc2
);
4189 radeon_set_sh_reg_seq(cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
4190 radeon_emit(cs
, va
>> 8);
4191 radeon_emit(cs
, S_00B424_MEM_BASE(va
>> 40));
4192 radeon_emit(cs
, shader
->config
.rsrc1
);
4193 radeon_emit(cs
, shader
->config
.rsrc2
);
4198 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf
*ctx_cs
,
4199 struct radeon_cmdbuf
*cs
,
4200 struct radv_pipeline
*pipeline
,
4201 const struct radv_tessellation_state
*tess
)
4203 struct radv_shader_variant
*vs
;
4205 /* Skip shaders merged into HS/GS */
4206 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
4210 if (vs
->info
.vs
.as_ls
)
4211 radv_pipeline_generate_hw_ls(cs
, pipeline
, vs
, tess
);
4212 else if (vs
->info
.vs
.as_es
)
4213 radv_pipeline_generate_hw_es(cs
, pipeline
, vs
);
4214 else if (vs
->info
.is_ngg
)
4215 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, vs
);
4217 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, vs
);
4221 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf
*ctx_cs
,
4222 struct radeon_cmdbuf
*cs
,
4223 struct radv_pipeline
*pipeline
,
4224 const struct radv_tessellation_state
*tess
)
4226 if (!radv_pipeline_has_tess(pipeline
))
4229 struct radv_shader_variant
*tes
, *tcs
;
4231 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
4232 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
4235 if (tes
->info
.is_ngg
) {
4236 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, tes
);
4237 } else if (tes
->info
.tes
.as_es
)
4238 radv_pipeline_generate_hw_es(cs
, pipeline
, tes
);
4240 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, tes
);
4243 radv_pipeline_generate_hw_hs(cs
, pipeline
, tcs
, tess
);
4245 radeon_set_context_reg(ctx_cs
, R_028B6C_VGT_TF_PARAM
,
4248 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
)
4249 radeon_set_context_reg_idx(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
4250 tess
->ls_hs_config
);
4252 radeon_set_context_reg(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
,
4253 tess
->ls_hs_config
);
4255 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
4256 !radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
4257 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4258 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4259 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4260 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4265 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf
*ctx_cs
,
4266 struct radeon_cmdbuf
*cs
,
4267 struct radv_pipeline
*pipeline
,
4268 struct radv_shader_variant
*gs
)
4270 const struct gfx9_gs_info
*gs_state
= &gs
->info
.gs_ring_info
;
4271 unsigned gs_max_out_vertices
;
4272 uint8_t *num_components
;
4277 gs_max_out_vertices
= gs
->info
.gs
.vertices_out
;
4278 max_stream
= gs
->info
.gs
.max_stream
;
4279 num_components
= gs
->info
.gs
.num_stream_output_components
;
4281 offset
= num_components
[0] * gs_max_out_vertices
;
4283 radeon_set_context_reg_seq(ctx_cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
4284 radeon_emit(ctx_cs
, offset
);
4285 if (max_stream
>= 1)
4286 offset
+= num_components
[1] * gs_max_out_vertices
;
4287 radeon_emit(ctx_cs
, offset
);
4288 if (max_stream
>= 2)
4289 offset
+= num_components
[2] * gs_max_out_vertices
;
4290 radeon_emit(ctx_cs
, offset
);
4291 if (max_stream
>= 3)
4292 offset
+= num_components
[3] * gs_max_out_vertices
;
4293 radeon_set_context_reg(ctx_cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
4295 radeon_set_context_reg_seq(ctx_cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
4296 radeon_emit(ctx_cs
, num_components
[0]);
4297 radeon_emit(ctx_cs
, (max_stream
>= 1) ? num_components
[1] : 0);
4298 radeon_emit(ctx_cs
, (max_stream
>= 2) ? num_components
[2] : 0);
4299 radeon_emit(ctx_cs
, (max_stream
>= 3) ? num_components
[3] : 0);
4301 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
4302 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
4303 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
4304 S_028B90_ENABLE(gs_num_invocations
> 0));
4306 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
4307 gs_state
->vgt_esgs_ring_itemsize
);
4309 va
= radv_buffer_get_va(gs
->bo
) + gs
->bo_offset
;
4311 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4312 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4313 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
4314 radeon_emit(cs
, va
>> 8);
4315 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
4317 radeon_set_sh_reg_seq(cs
, R_00B210_SPI_SHADER_PGM_LO_ES
, 2);
4318 radeon_emit(cs
, va
>> 8);
4319 radeon_emit(cs
, S_00B214_MEM_BASE(va
>> 40));
4322 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
4323 radeon_emit(cs
, gs
->config
.rsrc1
);
4324 radeon_emit(cs
, gs
->config
.rsrc2
| S_00B22C_LDS_SIZE(gs_state
->lds_size
));
4326 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
, gs_state
->vgt_gs_onchip_cntl
);
4327 radeon_set_context_reg(ctx_cs
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
, gs_state
->vgt_gs_max_prims_per_subgroup
);
4329 radeon_set_sh_reg_seq(cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
4330 radeon_emit(cs
, va
>> 8);
4331 radeon_emit(cs
, S_00B224_MEM_BASE(va
>> 40));
4332 radeon_emit(cs
, gs
->config
.rsrc1
);
4333 radeon_emit(cs
, gs
->config
.rsrc2
);
4336 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, pipeline
->gs_copy_shader
);
4340 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf
*ctx_cs
,
4341 struct radeon_cmdbuf
*cs
,
4342 struct radv_pipeline
*pipeline
)
4344 struct radv_shader_variant
*gs
;
4346 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4350 if (gs
->info
.is_ngg
)
4351 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, gs
);
4353 radv_pipeline_generate_hw_gs(ctx_cs
, cs
, pipeline
, gs
);
4355 radeon_set_context_reg(ctx_cs
, R_028B38_VGT_GS_MAX_VERT_OUT
,
4356 gs
->info
.gs
.vertices_out
);
4359 static uint32_t offset_to_ps_input(uint32_t offset
, bool flat_shade
,
4360 bool explicit, bool float16
)
4362 uint32_t ps_input_cntl
;
4363 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
4364 ps_input_cntl
= S_028644_OFFSET(offset
);
4365 if (flat_shade
|| explicit)
4366 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
4368 /* Force parameter cache to be read in passthrough
4371 ps_input_cntl
|= S_028644_OFFSET(1 << 5);
4374 ps_input_cntl
|= S_028644_FP16_INTERP_MODE(1) |
4375 S_028644_ATTR0_VALID(1);
4378 /* The input is a DEFAULT_VAL constant. */
4379 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
4380 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
4381 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
4382 ps_input_cntl
= S_028644_OFFSET(0x20) |
4383 S_028644_DEFAULT_VAL(offset
);
4385 return ps_input_cntl
;
4389 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf
*ctx_cs
,
4390 struct radv_pipeline
*pipeline
)
4392 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4393 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
4394 uint32_t ps_input_cntl
[32];
4396 unsigned ps_offset
= 0;
4398 if (ps
->info
.ps
.prim_id_input
) {
4399 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
];
4400 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4401 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4406 if (ps
->info
.ps
.layer_input
||
4407 ps
->info
.needs_multiview_view_index
) {
4408 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
];
4409 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
4410 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4412 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false, false);
4416 if (ps
->info
.ps
.viewport_index_input
) {
4417 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VIEWPORT
];
4418 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
4419 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4421 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false, false);
4425 if (ps
->info
.ps
.has_pcoord
) {
4427 val
= S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4428 ps_input_cntl
[ps_offset
] = val
;
4432 if (ps
->info
.ps
.num_input_clips_culls
) {
4435 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST0
];
4436 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4437 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false, false);
4441 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST1
];
4442 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
&&
4443 ps
->info
.ps
.num_input_clips_culls
> 4) {
4444 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false, false);
4449 for (unsigned i
= 0; i
< 32 && (1u << i
) <= ps
->info
.ps
.input_mask
; ++i
) {
4454 if (!(ps
->info
.ps
.input_mask
& (1u << i
)))
4457 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VAR0
+ i
];
4458 if (vs_offset
== AC_EXP_PARAM_UNDEFINED
) {
4459 ps_input_cntl
[ps_offset
] = S_028644_OFFSET(0x20);
4464 flat_shade
= !!(ps
->info
.ps
.flat_shaded_mask
& (1u << ps_offset
));
4465 explicit = !!(ps
->info
.ps
.explicit_shaded_mask
& (1u << ps_offset
));
4466 float16
= !!(ps
->info
.ps
.float16_shaded_mask
& (1u << ps_offset
));
4468 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, flat_shade
, explicit, float16
);
4473 radeon_set_context_reg_seq(ctx_cs
, R_028644_SPI_PS_INPUT_CNTL_0
, ps_offset
);
4474 for (unsigned i
= 0; i
< ps_offset
; i
++) {
4475 radeon_emit(ctx_cs
, ps_input_cntl
[i
]);
4481 radv_compute_db_shader_control(const struct radv_device
*device
,
4482 const struct radv_pipeline
*pipeline
,
4483 const struct radv_shader_variant
*ps
)
4486 if (ps
->info
.ps
.early_fragment_test
|| !ps
->info
.ps
.writes_memory
)
4487 z_order
= V_02880C_EARLY_Z_THEN_LATE_Z
;
4489 z_order
= V_02880C_LATE_Z
;
4491 bool disable_rbplus
= device
->physical_device
->rad_info
.has_rbplus
&&
4492 !device
->physical_device
->rad_info
.rbplus_allowed
;
4494 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4495 * but this appears to break Project Cars (DXVK). See
4496 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4498 bool mask_export_enable
= ps
->info
.ps
.writes_sample_mask
;
4500 return S_02880C_Z_EXPORT_ENABLE(ps
->info
.ps
.writes_z
) |
4501 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps
->info
.ps
.writes_stencil
) |
4502 S_02880C_KILL_ENABLE(!!ps
->info
.ps
.can_discard
) |
4503 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable
) |
4504 S_02880C_Z_ORDER(z_order
) |
4505 S_02880C_DEPTH_BEFORE_SHADER(ps
->info
.ps
.early_fragment_test
) |
4506 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps
->info
.ps
.post_depth_coverage
) |
4507 S_02880C_EXEC_ON_HIER_FAIL(ps
->info
.ps
.writes_memory
) |
4508 S_02880C_EXEC_ON_NOOP(ps
->info
.ps
.writes_memory
) |
4509 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus
);
4513 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf
*ctx_cs
,
4514 struct radeon_cmdbuf
*cs
,
4515 struct radv_pipeline
*pipeline
)
4517 struct radv_shader_variant
*ps
;
4519 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
4521 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4522 va
= radv_buffer_get_va(ps
->bo
) + ps
->bo_offset
;
4524 radeon_set_sh_reg_seq(cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
4525 radeon_emit(cs
, va
>> 8);
4526 radeon_emit(cs
, S_00B024_MEM_BASE(va
>> 40));
4527 radeon_emit(cs
, ps
->config
.rsrc1
);
4528 radeon_emit(cs
, ps
->config
.rsrc2
);
4530 radeon_set_context_reg(ctx_cs
, R_02880C_DB_SHADER_CONTROL
,
4531 radv_compute_db_shader_control(pipeline
->device
,
4534 radeon_set_context_reg(ctx_cs
, R_0286CC_SPI_PS_INPUT_ENA
,
4535 ps
->config
.spi_ps_input_ena
);
4537 radeon_set_context_reg(ctx_cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
4538 ps
->config
.spi_ps_input_addr
);
4540 radeon_set_context_reg(ctx_cs
, R_0286D8_SPI_PS_IN_CONTROL
,
4541 S_0286D8_NUM_INTERP(ps
->info
.ps
.num_interp
) |
4542 S_0286D8_PS_W32_EN(ps
->info
.wave_size
== 32));
4544 radeon_set_context_reg(ctx_cs
, R_0286E0_SPI_BARYC_CNTL
, pipeline
->graphics
.spi_baryc_cntl
);
4546 radeon_set_context_reg(ctx_cs
, R_028710_SPI_SHADER_Z_FORMAT
,
4547 ac_get_spi_shader_z_format(ps
->info
.ps
.writes_z
,
4548 ps
->info
.ps
.writes_stencil
,
4549 ps
->info
.ps
.writes_sample_mask
));
4551 if (pipeline
->device
->dfsm_allowed
) {
4552 /* optimise this? */
4553 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
4554 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
4559 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf
*ctx_cs
,
4560 struct radv_pipeline
*pipeline
)
4562 if (pipeline
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4563 pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
4566 unsigned vtx_reuse_depth
= 30;
4567 if (radv_pipeline_has_tess(pipeline
) &&
4568 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.tes
.spacing
== TESS_SPACING_FRACTIONAL_ODD
) {
4569 vtx_reuse_depth
= 14;
4571 radeon_set_context_reg(ctx_cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
4572 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth
));
4576 radv_compute_vgt_shader_stages_en(const struct radv_pipeline
*pipeline
)
4578 uint32_t stages
= 0;
4579 if (radv_pipeline_has_tess(pipeline
)) {
4580 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
4581 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4583 if (radv_pipeline_has_gs(pipeline
))
4584 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
4586 else if (radv_pipeline_has_ngg(pipeline
))
4587 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
4589 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
4590 } else if (radv_pipeline_has_gs(pipeline
)) {
4591 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
4593 } else if (radv_pipeline_has_ngg(pipeline
)) {
4594 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
4597 if (radv_pipeline_has_ngg(pipeline
)) {
4598 stages
|= S_028B54_PRIMGEN_EN(1);
4599 if (pipeline
->streamout_shader
)
4600 stages
|= S_028B54_NGG_WAVE_ID_EN(1);
4601 if (radv_pipeline_has_ngg_passthrough(pipeline
))
4602 stages
|= S_028B54_PRIMGEN_PASSTHRU_EN(1);
4603 } else if (radv_pipeline_has_gs(pipeline
)) {
4604 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
4607 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
4608 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4610 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4611 uint8_t hs_size
= 64, gs_size
= 64, vs_size
= 64;
4613 if (radv_pipeline_has_tess(pipeline
))
4614 hs_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.wave_size
;
4616 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
4617 vs_size
= gs_size
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.wave_size
;
4618 if (pipeline
->gs_copy_shader
)
4619 vs_size
= pipeline
->gs_copy_shader
->info
.wave_size
;
4620 } else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
4621 vs_size
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.wave_size
;
4622 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
4623 vs_size
= pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.wave_size
;
4625 if (radv_pipeline_has_ngg(pipeline
))
4628 /* legacy GS only supports Wave64 */
4629 stages
|= S_028B54_HS_W32_EN(hs_size
== 32 ? 1 : 0) |
4630 S_028B54_GS_W32_EN(gs_size
== 32 ? 1 : 0) |
4631 S_028B54_VS_W32_EN(vs_size
== 32 ? 1 : 0);
4638 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4640 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
4641 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
4643 if (!discard_rectangle_info
)
4648 for (unsigned i
= 0; i
< (1u << MAX_DISCARD_RECTANGLES
); ++i
) {
4649 /* Interpret i as a bitmask, and then set the bit in the mask if
4650 * that combination of rectangles in which the pixel is contained
4651 * should pass the cliprect test. */
4652 unsigned relevant_subset
= i
& ((1u << discard_rectangle_info
->discardRectangleCount
) - 1);
4654 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT
&&
4658 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT
&&
4669 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf
*ctx_cs
,
4670 struct radv_pipeline
*pipeline
,
4671 const struct radv_tessellation_state
*tess
)
4673 bool break_wave_at_eoi
= false;
4674 unsigned primgroup_size
;
4675 unsigned vertgroup_size
= 256; /* 256 = disable vertex grouping */
4677 if (radv_pipeline_has_tess(pipeline
)) {
4678 primgroup_size
= tess
->num_patches
; /* must be a multiple of NUM_PATCHES */
4679 } else if (radv_pipeline_has_gs(pipeline
)) {
4680 const struct gfx9_gs_info
*gs_state
=
4681 &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs_ring_info
;
4682 unsigned vgt_gs_onchip_cntl
= gs_state
->vgt_gs_onchip_cntl
;
4683 primgroup_size
= G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl
);
4685 primgroup_size
= 128; /* recommended without a GS and tess */
4688 if (radv_pipeline_has_tess(pipeline
)) {
4689 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4690 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4691 break_wave_at_eoi
= true;
4694 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
,
4695 S_03096C_PRIM_GRP_SIZE(primgroup_size
) |
4696 S_03096C_VERT_GRP_SIZE(vertgroup_size
) |
4697 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4698 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
));
4702 radv_pipeline_generate_pm4(struct radv_pipeline
*pipeline
,
4703 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4704 const struct radv_graphics_pipeline_create_info
*extra
,
4705 const struct radv_blend_state
*blend
,
4706 const struct radv_tessellation_state
*tess
,
4707 unsigned prim
, unsigned gs_out
)
4709 struct radeon_cmdbuf
*ctx_cs
= &pipeline
->ctx_cs
;
4710 struct radeon_cmdbuf
*cs
= &pipeline
->cs
;
4713 ctx_cs
->max_dw
= 256;
4714 cs
->buf
= malloc(4 * (cs
->max_dw
+ ctx_cs
->max_dw
));
4715 ctx_cs
->buf
= cs
->buf
+ cs
->max_dw
;
4717 radv_pipeline_generate_depth_stencil_state(ctx_cs
, pipeline
, pCreateInfo
, extra
);
4718 radv_pipeline_generate_blend_state(ctx_cs
, pipeline
, blend
);
4719 radv_pipeline_generate_raster_state(ctx_cs
, pipeline
, pCreateInfo
);
4720 radv_pipeline_generate_multisample_state(ctx_cs
, pipeline
);
4721 radv_pipeline_generate_vgt_gs_mode(ctx_cs
, pipeline
);
4722 radv_pipeline_generate_vertex_shader(ctx_cs
, cs
, pipeline
, tess
);
4723 radv_pipeline_generate_tess_shaders(ctx_cs
, cs
, pipeline
, tess
);
4724 radv_pipeline_generate_geometry_shader(ctx_cs
, cs
, pipeline
);
4725 radv_pipeline_generate_fragment_shader(ctx_cs
, cs
, pipeline
);
4726 radv_pipeline_generate_ps_inputs(ctx_cs
, pipeline
);
4727 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs
, pipeline
);
4728 radv_pipeline_generate_binning_state(ctx_cs
, pipeline
, pCreateInfo
, blend
);
4730 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&& !radv_pipeline_has_ngg(pipeline
))
4731 gfx10_pipeline_generate_ge_cntl(ctx_cs
, pipeline
, tess
);
4733 radeon_set_context_reg(ctx_cs
, R_028B54_VGT_SHADER_STAGES_EN
, radv_compute_vgt_shader_stages_en(pipeline
));
4735 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4736 radeon_set_uconfig_reg_idx(pipeline
->device
->physical_device
,
4737 cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, prim
);
4739 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
4741 radeon_set_context_reg(ctx_cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, gs_out
);
4743 radeon_set_context_reg(ctx_cs
, R_02820C_PA_SC_CLIPRECT_RULE
, radv_compute_cliprect_rule(pCreateInfo
));
4745 pipeline
->ctx_cs_hash
= _mesa_hash_data(ctx_cs
->buf
, ctx_cs
->cdw
* 4);
4747 assert(ctx_cs
->cdw
<= ctx_cs
->max_dw
);
4748 assert(cs
->cdw
<= cs
->max_dw
);
4751 static struct radv_ia_multi_vgt_param_helpers
4752 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline
*pipeline
,
4753 const struct radv_tessellation_state
*tess
,
4756 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
= {0};
4757 const struct radv_device
*device
= pipeline
->device
;
4759 if (radv_pipeline_has_tess(pipeline
))
4760 ia_multi_vgt_param
.primgroup_size
= tess
->num_patches
;
4761 else if (radv_pipeline_has_gs(pipeline
))
4762 ia_multi_vgt_param
.primgroup_size
= 64;
4764 ia_multi_vgt_param
.primgroup_size
= 128; /* recommended without a GS */
4766 /* GS requirement. */
4767 ia_multi_vgt_param
.partial_es_wave
= false;
4768 if (radv_pipeline_has_gs(pipeline
) && device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4769 if (SI_GS_PER_ES
/ ia_multi_vgt_param
.primgroup_size
>= pipeline
->device
->gs_table_depth
- 3)
4770 ia_multi_vgt_param
.partial_es_wave
= true;
4772 ia_multi_vgt_param
.wd_switch_on_eop
= false;
4773 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4774 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
4775 * 4 shader engines. Set 1 to pass the assertion below.
4776 * The other cases are hardware requirements. */
4777 if (device
->physical_device
->rad_info
.max_se
< 4 ||
4778 prim
== V_008958_DI_PT_POLYGON
||
4779 prim
== V_008958_DI_PT_LINELOOP
||
4780 prim
== V_008958_DI_PT_TRIFAN
||
4781 prim
== V_008958_DI_PT_TRISTRIP_ADJ
||
4782 (pipeline
->graphics
.prim_restart_enable
&&
4783 (device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4784 (prim
!= V_008958_DI_PT_POINTLIST
&&
4785 prim
!= V_008958_DI_PT_LINESTRIP
))))
4786 ia_multi_vgt_param
.wd_switch_on_eop
= true;
4789 ia_multi_vgt_param
.ia_switch_on_eoi
= false;
4790 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.prim_id_input
)
4791 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4792 if (radv_pipeline_has_gs(pipeline
) &&
4793 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.uses_prim_id
)
4794 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4795 if (radv_pipeline_has_tess(pipeline
)) {
4796 /* SWITCH_ON_EOI must be set if PrimID is used. */
4797 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4798 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4799 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4802 ia_multi_vgt_param
.partial_vs_wave
= false;
4803 if (radv_pipeline_has_tess(pipeline
)) {
4804 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4805 if ((device
->physical_device
->rad_info
.family
== CHIP_TAHITI
||
4806 device
->physical_device
->rad_info
.family
== CHIP_PITCAIRN
||
4807 device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
) &&
4808 radv_pipeline_has_gs(pipeline
))
4809 ia_multi_vgt_param
.partial_vs_wave
= true;
4810 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4811 if (device
->physical_device
->rad_info
.has_distributed_tess
) {
4812 if (radv_pipeline_has_gs(pipeline
)) {
4813 if (device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4814 ia_multi_vgt_param
.partial_es_wave
= true;
4816 ia_multi_vgt_param
.partial_vs_wave
= true;
4821 /* Workaround for a VGT hang when strip primitive types are used with
4822 * primitive restart.
4824 if (pipeline
->graphics
.prim_restart_enable
&&
4825 (prim
== V_008958_DI_PT_LINESTRIP
||
4826 prim
== V_008958_DI_PT_TRISTRIP
||
4827 prim
== V_008958_DI_PT_LINESTRIP_ADJ
||
4828 prim
== V_008958_DI_PT_TRISTRIP_ADJ
)) {
4829 ia_multi_vgt_param
.partial_vs_wave
= true;
4832 if (radv_pipeline_has_gs(pipeline
)) {
4833 /* On these chips there is the possibility of a hang if the
4834 * pipeline uses a GS and partial_vs_wave is not set.
4836 * This mostly does not hit 4-SE chips, as those typically set
4837 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4838 * with GS due to another workaround.
4840 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4842 if (device
->physical_device
->rad_info
.family
== CHIP_TONGA
||
4843 device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
4844 device
->physical_device
->rad_info
.family
== CHIP_POLARIS10
||
4845 device
->physical_device
->rad_info
.family
== CHIP_POLARIS11
||
4846 device
->physical_device
->rad_info
.family
== CHIP_POLARIS12
||
4847 device
->physical_device
->rad_info
.family
== CHIP_VEGAM
) {
4848 ia_multi_vgt_param
.partial_vs_wave
= true;
4852 ia_multi_vgt_param
.base
=
4853 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param
.primgroup_size
- 1) |
4854 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4855 S_028AA8_MAX_PRIMGRP_IN_WAVE(device
->physical_device
->rad_info
.chip_class
== GFX8
? 2 : 0) |
4856 S_030960_EN_INST_OPT_BASIC(device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
4857 S_030960_EN_INST_OPT_ADV(device
->physical_device
->rad_info
.chip_class
>= GFX9
);
4859 return ia_multi_vgt_param
;
4864 radv_compute_vertex_input_state(struct radv_pipeline
*pipeline
,
4865 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4867 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
4868 pCreateInfo
->pVertexInputState
;
4869 struct radv_vertex_elements_info
*velems
= &pipeline
->vertex_elements
;
4871 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
4872 const VkVertexInputAttributeDescription
*desc
=
4873 &vi_info
->pVertexAttributeDescriptions
[i
];
4874 unsigned loc
= desc
->location
;
4875 const struct vk_format_description
*format_desc
;
4877 format_desc
= vk_format_description(desc
->format
);
4879 velems
->format_size
[loc
] = format_desc
->block
.bits
/ 8;
4882 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
4883 const VkVertexInputBindingDescription
*desc
=
4884 &vi_info
->pVertexBindingDescriptions
[i
];
4886 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
4887 pipeline
->num_vertex_bindings
=
4888 MAX2(pipeline
->num_vertex_bindings
, desc
->binding
+ 1);
4892 static struct radv_shader_variant
*
4893 radv_pipeline_get_streamout_shader(struct radv_pipeline
*pipeline
)
4897 for (i
= MESA_SHADER_GEOMETRY
; i
>= MESA_SHADER_VERTEX
; i
--) {
4898 struct radv_shader_variant
*shader
=
4899 radv_get_shader(pipeline
, i
);
4901 if (shader
&& shader
->info
.so
.num_outputs
> 0)
4909 radv_secure_compile(struct radv_pipeline
*pipeline
,
4910 struct radv_device
*device
,
4911 const struct radv_pipeline_key
*key
,
4912 const VkPipelineShaderStageCreateInfo
**pStages
,
4913 const VkPipelineCreateFlags flags
,
4914 unsigned num_stages
)
4916 uint8_t allowed_pipeline_hashes
[2][20];
4917 radv_hash_shaders(allowed_pipeline_hashes
[0], pStages
,
4918 pipeline
->layout
, key
, get_hash_flags(device
));
4920 /* Generate the GC copy hash */
4921 memcpy(allowed_pipeline_hashes
[1], allowed_pipeline_hashes
[0], 20);
4922 allowed_pipeline_hashes
[1][0] ^= 1;
4924 uint8_t allowed_hashes
[2][20];
4925 for (unsigned i
= 0; i
< 2; ++i
) {
4926 disk_cache_compute_key(device
->physical_device
->disk_cache
,
4927 allowed_pipeline_hashes
[i
], 20,
4931 /* Do an early exit if all cache entries are already there. */
4932 bool may_need_copy_shader
= pStages
[MESA_SHADER_GEOMETRY
];
4933 void *main_entry
= disk_cache_get(device
->physical_device
->disk_cache
, allowed_hashes
[0], NULL
);
4934 void *copy_entry
= NULL
;
4935 if (may_need_copy_shader
)
4936 copy_entry
= disk_cache_get(device
->physical_device
->disk_cache
, allowed_hashes
[1], NULL
);
4938 bool has_all_cache_entries
= main_entry
&& (!may_need_copy_shader
|| copy_entry
);
4942 if(has_all_cache_entries
)
4945 unsigned process
= 0;
4946 uint8_t sc_threads
= device
->instance
->num_sc_threads
;
4948 mtx_lock(&device
->sc_state
->secure_compile_mutex
);
4949 if (device
->sc_state
->secure_compile_thread_counter
< sc_threads
) {
4950 device
->sc_state
->secure_compile_thread_counter
++;
4951 for (unsigned i
= 0; i
< sc_threads
; i
++) {
4952 if (!device
->sc_state
->secure_compile_processes
[i
].in_use
) {
4953 device
->sc_state
->secure_compile_processes
[i
].in_use
= true;
4958 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
4961 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
4964 int fd_secure_input
= device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
;
4965 int fd_secure_output
= device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
;
4967 /* Fork a copy of the slim untainted secure compile process */
4968 enum radv_secure_compile_type sc_type
= RADV_SC_TYPE_FORK_DEVICE
;
4969 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
4971 if (!radv_sc_read(fd_secure_output
, &sc_type
, sizeof(sc_type
), true) ||
4972 sc_type
!= RADV_SC_TYPE_INIT_SUCCESS
)
4973 return VK_ERROR_DEVICE_LOST
;
4975 fd_secure_input
= device
->sc_state
->secure_compile_processes
[process
].fd_server
;
4976 fd_secure_output
= device
->sc_state
->secure_compile_processes
[process
].fd_client
;
4978 /* Write pipeline / shader module out to secure process via pipe */
4979 sc_type
= RADV_SC_TYPE_COMPILE_PIPELINE
;
4980 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
4982 /* Write pipeline layout out to secure process */
4983 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
4984 write(fd_secure_input
, layout
, sizeof(struct radv_pipeline_layout
));
4985 write(fd_secure_input
, &layout
->num_sets
, sizeof(uint32_t));
4986 for (uint32_t set
= 0; set
< layout
->num_sets
; set
++) {
4987 write(fd_secure_input
, &layout
->set
[set
].layout
->layout_size
, sizeof(uint32_t));
4988 write(fd_secure_input
, layout
->set
[set
].layout
, layout
->set
[set
].layout
->layout_size
);
4991 /* Write pipeline key out to secure process */
4992 write(fd_secure_input
, key
, sizeof(struct radv_pipeline_key
));
4994 /* Write pipeline create flags out to secure process */
4995 write(fd_secure_input
, &flags
, sizeof(VkPipelineCreateFlags
));
4997 /* Write stage and shader information out to secure process */
4998 write(fd_secure_input
, &num_stages
, sizeof(uint32_t));
4999 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
5003 /* Write stage out to secure process */
5004 gl_shader_stage stage
= ffs(pStages
[i
]->stage
) - 1;
5005 write(fd_secure_input
, &stage
, sizeof(gl_shader_stage
));
5007 /* Write entry point name out to secure process */
5008 size_t name_size
= strlen(pStages
[i
]->pName
) + 1;
5009 write(fd_secure_input
, &name_size
, sizeof(size_t));
5010 write(fd_secure_input
, pStages
[i
]->pName
, name_size
);
5012 /* Write shader module out to secure process */
5013 struct radv_shader_module
*module
= radv_shader_module_from_handle(pStages
[i
]->module
);
5014 assert(!module
->nir
);
5015 size_t module_size
= sizeof(struct radv_shader_module
) + module
->size
;
5016 write(fd_secure_input
, &module_size
, sizeof(size_t));
5017 write(fd_secure_input
, module
, module_size
);
5019 /* Write specialization info out to secure process */
5020 const VkSpecializationInfo
*specInfo
= pStages
[i
]->pSpecializationInfo
;
5021 bool has_spec_info
= specInfo
? true : false;
5022 write(fd_secure_input
, &has_spec_info
, sizeof(bool));
5024 write(fd_secure_input
, &specInfo
->dataSize
, sizeof(size_t));
5025 write(fd_secure_input
, specInfo
->pData
, specInfo
->dataSize
);
5027 write(fd_secure_input
, &specInfo
->mapEntryCount
, sizeof(uint32_t));
5028 for (uint32_t j
= 0; j
< specInfo
->mapEntryCount
; j
++)
5029 write(fd_secure_input
, &specInfo
->pMapEntries
[j
], sizeof(VkSpecializationMapEntry
));
5033 /* Read the data returned from the secure process */
5034 while (sc_type
!= RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED
) {
5035 if (!radv_sc_read(fd_secure_output
, &sc_type
, sizeof(sc_type
), true))
5036 return VK_ERROR_DEVICE_LOST
;
5038 if (sc_type
== RADV_SC_TYPE_WRITE_DISK_CACHE
) {
5039 assert(device
->physical_device
->disk_cache
);
5041 uint8_t disk_sha1
[20];
5042 if (!radv_sc_read(fd_secure_output
, disk_sha1
, sizeof(uint8_t) * 20, true))
5043 return VK_ERROR_DEVICE_LOST
;
5045 if (memcmp(disk_sha1
, allowed_hashes
[0], 20) &&
5046 memcmp(disk_sha1
, allowed_hashes
[1], 20))
5047 return VK_ERROR_DEVICE_LOST
;
5049 uint32_t entry_size
;
5050 if (!radv_sc_read(fd_secure_output
, &entry_size
, sizeof(uint32_t), true))
5051 return VK_ERROR_DEVICE_LOST
;
5053 struct cache_entry
*entry
= malloc(entry_size
);
5054 if (!radv_sc_read(fd_secure_output
, entry
, entry_size
, true))
5055 return VK_ERROR_DEVICE_LOST
;
5057 disk_cache_put(device
->physical_device
->disk_cache
,
5058 disk_sha1
, entry
, entry_size
,
5062 } else if (sc_type
== RADV_SC_TYPE_READ_DISK_CACHE
) {
5063 uint8_t disk_sha1
[20];
5064 if (!radv_sc_read(fd_secure_output
, disk_sha1
, sizeof(uint8_t) * 20, true))
5065 return VK_ERROR_DEVICE_LOST
;
5067 if (memcmp(disk_sha1
, allowed_hashes
[0], 20) &&
5068 memcmp(disk_sha1
, allowed_hashes
[1], 20))
5069 return VK_ERROR_DEVICE_LOST
;
5072 struct cache_entry
*entry
= (struct cache_entry
*)
5073 disk_cache_get(device
->physical_device
->disk_cache
,
5076 uint8_t found
= entry
? 1 : 0;
5077 write(fd_secure_input
, &found
, sizeof(uint8_t));
5080 write(fd_secure_input
, &size
, sizeof(size_t));
5081 write(fd_secure_input
, entry
, size
);
5088 sc_type
= RADV_SC_TYPE_DESTROY_DEVICE
;
5089 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
5091 mtx_lock(&device
->sc_state
->secure_compile_mutex
);
5092 device
->sc_state
->secure_compile_thread_counter
--;
5093 device
->sc_state
->secure_compile_processes
[process
].in_use
= false;
5094 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
5100 radv_pipeline_init(struct radv_pipeline
*pipeline
,
5101 struct radv_device
*device
,
5102 struct radv_pipeline_cache
*cache
,
5103 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
5104 const struct radv_graphics_pipeline_create_info
*extra
)
5107 bool has_view_index
= false;
5109 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
5110 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
5111 if (subpass
->view_mask
)
5112 has_view_index
= true;
5114 pipeline
->device
= device
;
5115 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
5116 assert(pipeline
->layout
);
5118 struct radv_blend_state blend
= radv_pipeline_init_blend_state(pipeline
, pCreateInfo
, extra
);
5120 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
5121 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
5122 radv_init_feedback(creation_feedback
);
5124 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
5126 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
5127 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
5128 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
5129 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
5130 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
5131 if(creation_feedback
)
5132 stage_feedbacks
[stage
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[i
];
5135 struct radv_pipeline_key key
= radv_generate_graphics_pipeline_key(pipeline
, pCreateInfo
, &blend
, has_view_index
);
5136 if (radv_device_use_secure_compile(device
->instance
)) {
5137 return radv_secure_compile(pipeline
, device
, &key
, pStages
, pCreateInfo
->flags
, pCreateInfo
->stageCount
);
5139 radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
, pCreateInfo
->flags
, pipeline_feedback
, stage_feedbacks
);
5142 pipeline
->graphics
.spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
5143 radv_pipeline_init_multisample_state(pipeline
, &blend
, pCreateInfo
);
5145 uint32_t prim
= si_translate_prim(pCreateInfo
->pInputAssemblyState
->topology
);
5147 pipeline
->graphics
.topology
= pCreateInfo
->pInputAssemblyState
->topology
;
5148 pipeline
->graphics
.can_use_guardband
= radv_prim_can_use_guardband(pCreateInfo
->pInputAssemblyState
->topology
);
5150 if (radv_pipeline_has_gs(pipeline
)) {
5151 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs
.output_prim
);
5152 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
5153 } else if (radv_pipeline_has_tess(pipeline
)) {
5154 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.point_mode
)
5155 gs_out
= V_028A6C_OUTPRIM_TYPE_POINTLIST
;
5157 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.primitive_mode
);
5158 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
5160 gs_out
= si_conv_prim_to_gs_out(pCreateInfo
->pInputAssemblyState
->topology
);
5162 if (extra
&& extra
->use_rectlist
) {
5163 prim
= V_008958_DI_PT_RECTLIST
;
5164 gs_out
= V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
5165 pipeline
->graphics
.can_use_guardband
= true;
5166 if (radv_pipeline_has_ngg(pipeline
))
5167 gs_out
= V_028A6C_VGT_OUT_RECT_V0
;
5169 pipeline
->graphics
.prim_restart_enable
= !!pCreateInfo
->pInputAssemblyState
->primitiveRestartEnable
;
5170 /* prim vertex count will need TESS changes */
5171 pipeline
->graphics
.prim_vertex_count
= prim_size_table
[prim
];
5173 radv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
);
5175 /* Ensure that some export memory is always allocated, for two reasons:
5177 * 1) Correctness: The hardware ignores the EXEC mask if no export
5178 * memory is allocated, so KILL and alpha test do not work correctly
5180 * 2) Performance: Every shader needs at least a NULL export, even when
5181 * it writes no color/depth output. The NULL export instruction
5182 * stalls without this setting.
5184 * Don't add this to CB_SHADER_MASK.
5186 * GFX10 supports pixel shaders without exports by setting both the
5187 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
5188 * instructions if any are present.
5190 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
5191 if ((pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX9
||
5192 ps
->info
.ps
.can_discard
) &&
5193 !blend
.spi_shader_col_format
) {
5194 if (!ps
->info
.ps
.writes_z
&&
5195 !ps
->info
.ps
.writes_stencil
&&
5196 !ps
->info
.ps
.writes_sample_mask
)
5197 blend
.spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
5200 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
5201 if (pipeline
->shaders
[i
]) {
5202 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[i
]->info
.need_indirect_descriptor_sets
;
5206 if (radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
5207 struct radv_shader_variant
*gs
=
5208 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
5210 calculate_gs_ring_sizes(pipeline
, &gs
->info
.gs_ring_info
);
5213 struct radv_tessellation_state tess
= {0};
5214 if (radv_pipeline_has_tess(pipeline
)) {
5215 if (prim
== V_008958_DI_PT_PATCH
) {
5216 pipeline
->graphics
.prim_vertex_count
.min
= pCreateInfo
->pTessellationState
->patchControlPoints
;
5217 pipeline
->graphics
.prim_vertex_count
.incr
= 1;
5219 tess
= calculate_tess_state(pipeline
, pCreateInfo
);
5222 pipeline
->graphics
.ia_multi_vgt_param
= radv_compute_ia_multi_vgt_param_helpers(pipeline
, &tess
, prim
);
5224 radv_compute_vertex_input_state(pipeline
, pCreateInfo
);
5226 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++)
5227 pipeline
->user_data_0
[i
] = radv_pipeline_stage_to_user_data_0(pipeline
, i
, device
->physical_device
->rad_info
.chip_class
);
5229 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
,
5230 AC_UD_VS_BASE_VERTEX_START_INSTANCE
);
5231 if (loc
->sgpr_idx
!= -1) {
5232 pipeline
->graphics
.vtx_base_sgpr
= pipeline
->user_data_0
[MESA_SHADER_VERTEX
];
5233 pipeline
->graphics
.vtx_base_sgpr
+= loc
->sgpr_idx
* 4;
5234 if (radv_get_shader(pipeline
, MESA_SHADER_VERTEX
)->info
.vs
.needs_draw_id
)
5235 pipeline
->graphics
.vtx_emit_num
= 3;
5237 pipeline
->graphics
.vtx_emit_num
= 2;
5240 /* Find the last vertex shader stage that eventually uses streamout. */
5241 pipeline
->streamout_shader
= radv_pipeline_get_streamout_shader(pipeline
);
5243 result
= radv_pipeline_scratch_init(device
, pipeline
);
5244 radv_pipeline_generate_pm4(pipeline
, pCreateInfo
, extra
, &blend
, &tess
, prim
, gs_out
);
5250 radv_graphics_pipeline_create(
5252 VkPipelineCache _cache
,
5253 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
5254 const struct radv_graphics_pipeline_create_info
*extra
,
5255 const VkAllocationCallbacks
*pAllocator
,
5256 VkPipeline
*pPipeline
)
5258 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5259 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
5260 struct radv_pipeline
*pipeline
;
5263 pipeline
= vk_zalloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*pipeline
), 8,
5264 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5265 if (pipeline
== NULL
)
5266 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5268 result
= radv_pipeline_init(pipeline
, device
, cache
,
5269 pCreateInfo
, extra
);
5270 if (result
!= VK_SUCCESS
) {
5271 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5275 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5280 VkResult
radv_CreateGraphicsPipelines(
5282 VkPipelineCache pipelineCache
,
5284 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
5285 const VkAllocationCallbacks
* pAllocator
,
5286 VkPipeline
* pPipelines
)
5288 VkResult result
= VK_SUCCESS
;
5291 for (; i
< count
; i
++) {
5293 r
= radv_graphics_pipeline_create(_device
,
5296 NULL
, pAllocator
, &pPipelines
[i
]);
5297 if (r
!= VK_SUCCESS
) {
5299 pPipelines
[i
] = VK_NULL_HANDLE
;
5308 radv_compute_generate_pm4(struct radv_pipeline
*pipeline
)
5310 struct radv_shader_variant
*compute_shader
;
5311 struct radv_device
*device
= pipeline
->device
;
5312 unsigned threads_per_threadgroup
;
5313 unsigned threadgroups_per_cu
= 1;
5314 unsigned waves_per_threadgroup
;
5315 unsigned max_waves_per_sh
= 0;
5318 pipeline
->cs
.max_dw
= device
->physical_device
->rad_info
.chip_class
>= GFX10
? 22 : 20;
5319 pipeline
->cs
.buf
= malloc(pipeline
->cs
.max_dw
* 4);
5321 compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
5322 va
= radv_buffer_get_va(compute_shader
->bo
) + compute_shader
->bo_offset
;
5324 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B830_COMPUTE_PGM_LO
, 2);
5325 radeon_emit(&pipeline
->cs
, va
>> 8);
5326 radeon_emit(&pipeline
->cs
, S_00B834_DATA(va
>> 40));
5328 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
5329 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc1
);
5330 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc2
);
5331 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
5332 radeon_set_sh_reg(&pipeline
->cs
, R_00B8A0_COMPUTE_PGM_RSRC3
, compute_shader
->config
.rsrc3
);
5335 /* Calculate best compute resource limits. */
5336 threads_per_threadgroup
= compute_shader
->info
.cs
.block_size
[0] *
5337 compute_shader
->info
.cs
.block_size
[1] *
5338 compute_shader
->info
.cs
.block_size
[2];
5339 waves_per_threadgroup
= DIV_ROUND_UP(threads_per_threadgroup
,
5340 compute_shader
->info
.wave_size
);
5342 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
5343 waves_per_threadgroup
== 1)
5344 threadgroups_per_cu
= 2;
5346 radeon_set_sh_reg(&pipeline
->cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
5347 ac_get_compute_resource_limits(&device
->physical_device
->rad_info
,
5348 waves_per_threadgroup
,
5350 threadgroups_per_cu
));
5352 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
5353 radeon_emit(&pipeline
->cs
,
5354 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]));
5355 radeon_emit(&pipeline
->cs
,
5356 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]));
5357 radeon_emit(&pipeline
->cs
,
5358 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]));
5360 assert(pipeline
->cs
.cdw
<= pipeline
->cs
.max_dw
);
5363 static struct radv_pipeline_key
5364 radv_generate_compute_pipeline_key(struct radv_pipeline
*pipeline
,
5365 const VkComputePipelineCreateInfo
*pCreateInfo
)
5367 const VkPipelineShaderStageCreateInfo
*stage
= &pCreateInfo
->stage
;
5368 struct radv_pipeline_key key
;
5369 memset(&key
, 0, sizeof(key
));
5371 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
5372 key
.optimisations_disabled
= 1;
5374 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*subgroup_size
=
5375 vk_find_struct_const(stage
->pNext
,
5376 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT
);
5378 if (subgroup_size
) {
5379 assert(subgroup_size
->requiredSubgroupSize
== 32 ||
5380 subgroup_size
->requiredSubgroupSize
== 64);
5381 key
.compute_subgroup_size
= subgroup_size
->requiredSubgroupSize
;
5387 static VkResult
radv_compute_pipeline_create(
5389 VkPipelineCache _cache
,
5390 const VkComputePipelineCreateInfo
* pCreateInfo
,
5391 const VkAllocationCallbacks
* pAllocator
,
5392 VkPipeline
* pPipeline
)
5394 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5395 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
5396 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
5397 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
5398 struct radv_pipeline
*pipeline
;
5401 pipeline
= vk_zalloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*pipeline
), 8,
5402 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5403 if (pipeline
== NULL
)
5404 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5406 pipeline
->device
= device
;
5407 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
5408 assert(pipeline
->layout
);
5410 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
5411 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
5412 radv_init_feedback(creation_feedback
);
5414 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
5415 if (creation_feedback
)
5416 stage_feedbacks
[MESA_SHADER_COMPUTE
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[0];
5418 pStages
[MESA_SHADER_COMPUTE
] = &pCreateInfo
->stage
;
5420 struct radv_pipeline_key key
=
5421 radv_generate_compute_pipeline_key(pipeline
, pCreateInfo
);
5423 if (radv_device_use_secure_compile(device
->instance
)) {
5424 result
= radv_secure_compile(pipeline
, device
, &key
, pStages
, pCreateInfo
->flags
, 1);
5425 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5429 radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
, pCreateInfo
->flags
, pipeline_feedback
, stage_feedbacks
);
5432 pipeline
->user_data_0
[MESA_SHADER_COMPUTE
] = radv_pipeline_stage_to_user_data_0(pipeline
, MESA_SHADER_COMPUTE
, device
->physical_device
->rad_info
.chip_class
);
5433 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.need_indirect_descriptor_sets
;
5434 result
= radv_pipeline_scratch_init(device
, pipeline
);
5435 if (result
!= VK_SUCCESS
) {
5436 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5440 radv_compute_generate_pm4(pipeline
);
5442 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5447 VkResult
radv_CreateComputePipelines(
5449 VkPipelineCache pipelineCache
,
5451 const VkComputePipelineCreateInfo
* pCreateInfos
,
5452 const VkAllocationCallbacks
* pAllocator
,
5453 VkPipeline
* pPipelines
)
5455 VkResult result
= VK_SUCCESS
;
5458 for (; i
< count
; i
++) {
5460 r
= radv_compute_pipeline_create(_device
, pipelineCache
,
5462 pAllocator
, &pPipelines
[i
]);
5463 if (r
!= VK_SUCCESS
) {
5465 pPipelines
[i
] = VK_NULL_HANDLE
;
5473 static uint32_t radv_get_executable_count(const struct radv_pipeline
*pipeline
)
5476 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5477 if (!pipeline
->shaders
[i
])
5480 if (i
== MESA_SHADER_GEOMETRY
&&
5481 !radv_pipeline_has_ngg(pipeline
)) {
5491 static struct radv_shader_variant
*
5492 radv_get_shader_from_executable_index(const struct radv_pipeline
*pipeline
, int index
, gl_shader_stage
*stage
)
5494 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5495 if (!pipeline
->shaders
[i
])
5499 return pipeline
->shaders
[i
];
5504 if (i
== MESA_SHADER_GEOMETRY
&&
5505 !radv_pipeline_has_ngg(pipeline
)) {
5508 return pipeline
->gs_copy_shader
;
5518 /* Basically strlcpy (which does not exist on linux) specialized for
5520 static void desc_copy(char *desc
, const char *src
) {
5521 int len
= strlen(src
);
5522 assert(len
< VK_MAX_DESCRIPTION_SIZE
);
5523 memcpy(desc
, src
, len
);
5524 memset(desc
+ len
, 0, VK_MAX_DESCRIPTION_SIZE
- len
);
5527 VkResult
radv_GetPipelineExecutablePropertiesKHR(
5529 const VkPipelineInfoKHR
* pPipelineInfo
,
5530 uint32_t* pExecutableCount
,
5531 VkPipelineExecutablePropertiesKHR
* pProperties
)
5533 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pPipelineInfo
->pipeline
);
5534 const uint32_t total_count
= radv_get_executable_count(pipeline
);
5537 *pExecutableCount
= total_count
;
5541 const uint32_t count
= MIN2(total_count
, *pExecutableCount
);
5542 for (unsigned i
= 0, executable_idx
= 0;
5543 i
< MESA_SHADER_STAGES
&& executable_idx
< count
; ++i
) {
5544 if (!pipeline
->shaders
[i
])
5546 pProperties
[executable_idx
].stages
= mesa_to_vk_shader_stage(i
);
5547 const char *name
= NULL
;
5548 const char *description
= NULL
;
5550 case MESA_SHADER_VERTEX
:
5551 name
= "Vertex Shader";
5552 description
= "Vulkan Vertex Shader";
5554 case MESA_SHADER_TESS_CTRL
:
5555 if (!pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5556 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5557 name
= "Vertex + Tessellation Control Shaders";
5558 description
= "Combined Vulkan Vertex and Tessellation Control Shaders";
5560 name
= "Tessellation Control Shader";
5561 description
= "Vulkan Tessellation Control Shader";
5564 case MESA_SHADER_TESS_EVAL
:
5565 name
= "Tessellation Evaluation Shader";
5566 description
= "Vulkan Tessellation Evaluation Shader";
5568 case MESA_SHADER_GEOMETRY
:
5569 if (radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]) {
5570 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
;
5571 name
= "Tessellation Evaluation + Geometry Shaders";
5572 description
= "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5573 } else if (!radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5574 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5575 name
= "Vertex + Geometry Shader";
5576 description
= "Combined Vulkan Vertex and Geometry Shaders";
5578 name
= "Geometry Shader";
5579 description
= "Vulkan Geometry Shader";
5582 case MESA_SHADER_FRAGMENT
:
5583 name
= "Fragment Shader";
5584 description
= "Vulkan Fragment Shader";
5586 case MESA_SHADER_COMPUTE
:
5587 name
= "Compute Shader";
5588 description
= "Vulkan Compute Shader";
5592 pProperties
[executable_idx
].subgroupSize
= pipeline
->shaders
[i
]->info
.wave_size
;
5593 desc_copy(pProperties
[executable_idx
].name
, name
);
5594 desc_copy(pProperties
[executable_idx
].description
, description
);
5597 if (i
== MESA_SHADER_GEOMETRY
&&
5598 !radv_pipeline_has_ngg(pipeline
)) {
5599 assert(pipeline
->gs_copy_shader
);
5600 if (executable_idx
>= count
)
5603 pProperties
[executable_idx
].stages
= VK_SHADER_STAGE_GEOMETRY_BIT
;
5604 pProperties
[executable_idx
].subgroupSize
= 64;
5605 desc_copy(pProperties
[executable_idx
].name
, "GS Copy Shader");
5606 desc_copy(pProperties
[executable_idx
].description
,
5607 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5613 VkResult result
= *pExecutableCount
< total_count
? VK_INCOMPLETE
: VK_SUCCESS
;
5614 *pExecutableCount
= count
;
5618 VkResult
radv_GetPipelineExecutableStatisticsKHR(
5620 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5621 uint32_t* pStatisticCount
,
5622 VkPipelineExecutableStatisticKHR
* pStatistics
)
5624 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5625 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5626 gl_shader_stage stage
;
5627 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5629 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
5630 unsigned lds_increment
= chip_class
>= GFX7
? 512 : 256;
5631 unsigned max_waves
= radv_get_max_waves(device
, shader
, stage
);
5633 VkPipelineExecutableStatisticKHR
*s
= pStatistics
;
5634 VkPipelineExecutableStatisticKHR
*end
= s
+ (pStatistics
? *pStatisticCount
: 0);
5635 VkResult result
= VK_SUCCESS
;
5638 desc_copy(s
->name
, "SGPRs");
5639 desc_copy(s
->description
, "Number of SGPR registers allocated per subgroup");
5640 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5641 s
->value
.u64
= shader
->config
.num_sgprs
;
5646 desc_copy(s
->name
, "VGPRs");
5647 desc_copy(s
->description
, "Number of VGPR registers allocated per subgroup");
5648 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5649 s
->value
.u64
= shader
->config
.num_vgprs
;
5654 desc_copy(s
->name
, "Spilled SGPRs");
5655 desc_copy(s
->description
, "Number of SGPR registers spilled per subgroup");
5656 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5657 s
->value
.u64
= shader
->config
.spilled_sgprs
;
5662 desc_copy(s
->name
, "Spilled VGPRs");
5663 desc_copy(s
->description
, "Number of VGPR registers spilled per subgroup");
5664 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5665 s
->value
.u64
= shader
->config
.spilled_vgprs
;
5670 desc_copy(s
->name
, "PrivMem VGPRs");
5671 desc_copy(s
->description
, "Number of VGPRs stored in private memory per subgroup");
5672 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5673 s
->value
.u64
= shader
->info
.private_mem_vgprs
;
5678 desc_copy(s
->name
, "Code size");
5679 desc_copy(s
->description
, "Code size in bytes");
5680 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5681 s
->value
.u64
= shader
->exec_size
;
5686 desc_copy(s
->name
, "LDS size");
5687 desc_copy(s
->description
, "LDS size in bytes per workgroup");
5688 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5689 s
->value
.u64
= shader
->config
.lds_size
* lds_increment
;
5694 desc_copy(s
->name
, "Scratch size");
5695 desc_copy(s
->description
, "Private memory in bytes per subgroup");
5696 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5697 s
->value
.u64
= shader
->config
.scratch_bytes_per_wave
;
5702 desc_copy(s
->name
, "Subgroups per SIMD");
5703 desc_copy(s
->description
, "The maximum number of subgroups in flight on a SIMD unit");
5704 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5705 s
->value
.u64
= max_waves
;
5709 if (shader
->statistics
) {
5710 for (unsigned i
= 0; i
< shader
->statistics
->count
; i
++) {
5711 struct radv_compiler_statistic_info
*info
= &shader
->statistics
->infos
[i
];
5712 uint32_t value
= shader
->statistics
->values
[i
];
5714 desc_copy(s
->name
, info
->name
);
5715 desc_copy(s
->description
, info
->desc
);
5716 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5717 s
->value
.u64
= value
;
5724 *pStatisticCount
= s
- pStatistics
;
5726 *pStatisticCount
= end
- pStatistics
;
5727 result
= VK_INCOMPLETE
;
5729 *pStatisticCount
= s
- pStatistics
;
5735 static VkResult
radv_copy_representation(void *data
, size_t *data_size
, const char *src
)
5737 size_t total_size
= strlen(src
) + 1;
5740 *data_size
= total_size
;
5744 size_t size
= MIN2(total_size
, *data_size
);
5746 memcpy(data
, src
, size
);
5748 *((char*)data
+ size
- 1) = 0;
5749 return size
< total_size
? VK_INCOMPLETE
: VK_SUCCESS
;
5752 VkResult
radv_GetPipelineExecutableInternalRepresentationsKHR(
5754 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5755 uint32_t* pInternalRepresentationCount
,
5756 VkPipelineExecutableInternalRepresentationKHR
* pInternalRepresentations
)
5758 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5759 gl_shader_stage stage
;
5760 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5762 VkPipelineExecutableInternalRepresentationKHR
*p
= pInternalRepresentations
;
5763 VkPipelineExecutableInternalRepresentationKHR
*end
= p
+ (pInternalRepresentations
? *pInternalRepresentationCount
: 0);
5764 VkResult result
= VK_SUCCESS
;
5768 desc_copy(p
->name
, "NIR Shader(s)");
5769 desc_copy(p
->description
, "The optimized NIR shader(s)");
5770 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->nir_string
) != VK_SUCCESS
)
5771 result
= VK_INCOMPLETE
;
5778 if (pipeline
->device
->physical_device
->use_aco
) {
5779 desc_copy(p
->name
, "ACO IR");
5780 desc_copy(p
->description
, "The ACO IR after some optimizations");
5782 desc_copy(p
->name
, "LLVM IR");
5783 desc_copy(p
->description
, "The LLVM IR after some optimizations");
5785 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->ir_string
) != VK_SUCCESS
)
5786 result
= VK_INCOMPLETE
;
5793 desc_copy(p
->name
, "Assembly");
5794 desc_copy(p
->description
, "Final Assembly");
5795 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->disasm_string
) != VK_SUCCESS
)
5796 result
= VK_INCOMPLETE
;
5800 if (!pInternalRepresentations
)
5801 *pInternalRepresentationCount
= p
- pInternalRepresentations
;
5803 result
= VK_INCOMPLETE
;
5804 *pInternalRepresentationCount
= end
- pInternalRepresentations
;
5806 *pInternalRepresentationCount
= p
- pInternalRepresentations
;