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radv: compute CB_SHADER_MASK from the fragment shader outputs
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
33 #include "radv_cs.h"
34 #include "radv_shader.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
39 #include "vk_util.h"
40
41 #include "sid.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
48 #include "ac_shader_util.h"
49
50 struct radv_blend_state {
51 uint32_t blend_enable_4bit;
52 uint32_t need_src_alpha;
53
54 uint32_t cb_color_control;
55 uint32_t cb_target_mask;
56 uint32_t cb_target_enabled_4bit;
57 uint32_t sx_mrt_blend_opt[8];
58 uint32_t cb_blend_control[8];
59
60 uint32_t spi_shader_col_format;
61 uint32_t cb_shader_mask;
62 uint32_t db_alpha_to_mask;
63
64 uint32_t commutative_4bit;
65
66 bool single_cb_enable;
67 bool mrt0_is_dual_src;
68 };
69
70 struct radv_dsa_order_invariance {
71 /* Whether the final result in Z/S buffers is guaranteed to be
72 * invariant under changes to the order in which fragments arrive.
73 */
74 bool zs;
75
76 /* Whether the set of fragments that pass the combined Z/S test is
77 * guaranteed to be invariant under changes to the order in which
78 * fragments arrive.
79 */
80 bool pass_set;
81 };
82
83 struct radv_tessellation_state {
84 uint32_t ls_hs_config;
85 unsigned num_patches;
86 unsigned lds_size;
87 uint32_t tf_param;
88 };
89
90 static const VkPipelineMultisampleStateCreateInfo *
91 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
92 {
93 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
94 return pCreateInfo->pMultisampleState;
95 return NULL;
96 }
97
98 static const VkPipelineTessellationStateCreateInfo *
99 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
100 {
101 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
102 if (pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT ||
103 pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) {
104 return pCreateInfo->pTessellationState;
105 }
106 }
107 return NULL;
108 }
109
110 static const VkPipelineDepthStencilStateCreateInfo *
111 radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
112 {
113 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
114 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
115
116 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
117 subpass->depth_stencil_attachment)
118 return pCreateInfo->pDepthStencilState;
119 return NULL;
120 }
121
122 static const VkPipelineColorBlendStateCreateInfo *
123 radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
124 {
125 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
126 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
127
128 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
129 subpass->has_color_att)
130 return pCreateInfo->pColorBlendState;
131 return NULL;
132 }
133
134 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline)
135 {
136 struct radv_shader_variant *variant = NULL;
137 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
138 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
139 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
140 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
141 else if (pipeline->shaders[MESA_SHADER_VERTEX])
142 variant = pipeline->shaders[MESA_SHADER_VERTEX];
143 else
144 return false;
145 return variant->info.is_ngg;
146 }
147
148 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline *pipeline)
149 {
150 assert(radv_pipeline_has_ngg(pipeline));
151
152 struct radv_shader_variant *variant = NULL;
153 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
154 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
155 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
156 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
157 else if (pipeline->shaders[MESA_SHADER_VERTEX])
158 variant = pipeline->shaders[MESA_SHADER_VERTEX];
159 else
160 return false;
161 return variant->info.is_ngg_passthrough;
162 }
163
164 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline)
165 {
166 if (!radv_pipeline_has_gs(pipeline))
167 return false;
168
169 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
170 * On GFX10, it might be required in rare cases if it's not possible to
171 * enable NGG.
172 */
173 if (radv_pipeline_has_ngg(pipeline))
174 return false;
175
176 assert(pipeline->gs_copy_shader);
177 return true;
178 }
179
180 static void
181 radv_pipeline_destroy(struct radv_device *device,
182 struct radv_pipeline *pipeline,
183 const VkAllocationCallbacks* allocator)
184 {
185 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
186 if (pipeline->shaders[i])
187 radv_shader_variant_destroy(device, pipeline->shaders[i]);
188
189 if (pipeline->gs_copy_shader)
190 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
191
192 if(pipeline->cs.buf)
193 free(pipeline->cs.buf);
194
195 vk_object_base_finish(&pipeline->base);
196 vk_free2(&device->vk.alloc, allocator, pipeline);
197 }
198
199 void radv_DestroyPipeline(
200 VkDevice _device,
201 VkPipeline _pipeline,
202 const VkAllocationCallbacks* pAllocator)
203 {
204 RADV_FROM_HANDLE(radv_device, device, _device);
205 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
206
207 if (!_pipeline)
208 return;
209
210 radv_pipeline_destroy(device, pipeline, pAllocator);
211 }
212
213 static uint32_t get_hash_flags(struct radv_device *device)
214 {
215 uint32_t hash_flags = 0;
216
217 if (device->instance->debug_flags & RADV_DEBUG_NO_NGG)
218 hash_flags |= RADV_HASH_SHADER_NO_NGG;
219 if (device->physical_device->cs_wave_size == 32)
220 hash_flags |= RADV_HASH_SHADER_CS_WAVE32;
221 if (device->physical_device->ps_wave_size == 32)
222 hash_flags |= RADV_HASH_SHADER_PS_WAVE32;
223 if (device->physical_device->ge_wave_size == 32)
224 hash_flags |= RADV_HASH_SHADER_GE_WAVE32;
225 if (device->physical_device->use_aco)
226 hash_flags |= RADV_HASH_SHADER_ACO;
227 return hash_flags;
228 }
229
230 static VkResult
231 radv_pipeline_scratch_init(struct radv_device *device,
232 struct radv_pipeline *pipeline)
233 {
234 unsigned scratch_bytes_per_wave = 0;
235 unsigned max_waves = 0;
236 unsigned min_waves = 1;
237
238 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
239 if (pipeline->shaders[i] &&
240 pipeline->shaders[i]->config.scratch_bytes_per_wave) {
241 unsigned max_stage_waves = device->scratch_waves;
242
243 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
244 pipeline->shaders[i]->config.scratch_bytes_per_wave);
245
246 max_stage_waves = MIN2(max_stage_waves,
247 4 * device->physical_device->rad_info.num_good_compute_units *
248 (256 / pipeline->shaders[i]->config.num_vgprs));
249 max_waves = MAX2(max_waves, max_stage_waves);
250 }
251 }
252
253 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
254 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
255 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
256 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
257 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
258 }
259
260 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
261 pipeline->max_waves = max_waves;
262 return VK_SUCCESS;
263 }
264
265 static uint32_t si_translate_blend_logic_op(VkLogicOp op)
266 {
267 switch (op) {
268 case VK_LOGIC_OP_CLEAR:
269 return V_028808_ROP3_CLEAR;
270 case VK_LOGIC_OP_AND:
271 return V_028808_ROP3_AND;
272 case VK_LOGIC_OP_AND_REVERSE:
273 return V_028808_ROP3_AND_REVERSE;
274 case VK_LOGIC_OP_COPY:
275 return V_028808_ROP3_COPY;
276 case VK_LOGIC_OP_AND_INVERTED:
277 return V_028808_ROP3_AND_INVERTED;
278 case VK_LOGIC_OP_NO_OP:
279 return V_028808_ROP3_NO_OP;
280 case VK_LOGIC_OP_XOR:
281 return V_028808_ROP3_XOR;
282 case VK_LOGIC_OP_OR:
283 return V_028808_ROP3_OR;
284 case VK_LOGIC_OP_NOR:
285 return V_028808_ROP3_NOR;
286 case VK_LOGIC_OP_EQUIVALENT:
287 return V_028808_ROP3_EQUIVALENT;
288 case VK_LOGIC_OP_INVERT:
289 return V_028808_ROP3_INVERT;
290 case VK_LOGIC_OP_OR_REVERSE:
291 return V_028808_ROP3_OR_REVERSE;
292 case VK_LOGIC_OP_COPY_INVERTED:
293 return V_028808_ROP3_COPY_INVERTED;
294 case VK_LOGIC_OP_OR_INVERTED:
295 return V_028808_ROP3_OR_INVERTED;
296 case VK_LOGIC_OP_NAND:
297 return V_028808_ROP3_NAND;
298 case VK_LOGIC_OP_SET:
299 return V_028808_ROP3_SET;
300 default:
301 unreachable("Unhandled logic op");
302 }
303 }
304
305
306 static uint32_t si_translate_blend_function(VkBlendOp op)
307 {
308 switch (op) {
309 case VK_BLEND_OP_ADD:
310 return V_028780_COMB_DST_PLUS_SRC;
311 case VK_BLEND_OP_SUBTRACT:
312 return V_028780_COMB_SRC_MINUS_DST;
313 case VK_BLEND_OP_REVERSE_SUBTRACT:
314 return V_028780_COMB_DST_MINUS_SRC;
315 case VK_BLEND_OP_MIN:
316 return V_028780_COMB_MIN_DST_SRC;
317 case VK_BLEND_OP_MAX:
318 return V_028780_COMB_MAX_DST_SRC;
319 default:
320 return 0;
321 }
322 }
323
324 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
325 {
326 switch (factor) {
327 case VK_BLEND_FACTOR_ZERO:
328 return V_028780_BLEND_ZERO;
329 case VK_BLEND_FACTOR_ONE:
330 return V_028780_BLEND_ONE;
331 case VK_BLEND_FACTOR_SRC_COLOR:
332 return V_028780_BLEND_SRC_COLOR;
333 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
334 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
335 case VK_BLEND_FACTOR_DST_COLOR:
336 return V_028780_BLEND_DST_COLOR;
337 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
338 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
339 case VK_BLEND_FACTOR_SRC_ALPHA:
340 return V_028780_BLEND_SRC_ALPHA;
341 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
342 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
343 case VK_BLEND_FACTOR_DST_ALPHA:
344 return V_028780_BLEND_DST_ALPHA;
345 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
346 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
347 case VK_BLEND_FACTOR_CONSTANT_COLOR:
348 return V_028780_BLEND_CONSTANT_COLOR;
349 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
350 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
351 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
352 return V_028780_BLEND_CONSTANT_ALPHA;
353 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
354 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
355 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
356 return V_028780_BLEND_SRC_ALPHA_SATURATE;
357 case VK_BLEND_FACTOR_SRC1_COLOR:
358 return V_028780_BLEND_SRC1_COLOR;
359 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
360 return V_028780_BLEND_INV_SRC1_COLOR;
361 case VK_BLEND_FACTOR_SRC1_ALPHA:
362 return V_028780_BLEND_SRC1_ALPHA;
363 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
364 return V_028780_BLEND_INV_SRC1_ALPHA;
365 default:
366 return 0;
367 }
368 }
369
370 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
371 {
372 switch (op) {
373 case VK_BLEND_OP_ADD:
374 return V_028760_OPT_COMB_ADD;
375 case VK_BLEND_OP_SUBTRACT:
376 return V_028760_OPT_COMB_SUBTRACT;
377 case VK_BLEND_OP_REVERSE_SUBTRACT:
378 return V_028760_OPT_COMB_REVSUBTRACT;
379 case VK_BLEND_OP_MIN:
380 return V_028760_OPT_COMB_MIN;
381 case VK_BLEND_OP_MAX:
382 return V_028760_OPT_COMB_MAX;
383 default:
384 return V_028760_OPT_COMB_BLEND_DISABLED;
385 }
386 }
387
388 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
389 {
390 switch (factor) {
391 case VK_BLEND_FACTOR_ZERO:
392 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
393 case VK_BLEND_FACTOR_ONE:
394 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
395 case VK_BLEND_FACTOR_SRC_COLOR:
396 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
397 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
398 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
399 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
400 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
401 case VK_BLEND_FACTOR_SRC_ALPHA:
402 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
403 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
404 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
405 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
406 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
407 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
408 default:
409 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
410 }
411 }
412
413 /**
414 * Get rid of DST in the blend factors by commuting the operands:
415 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
416 */
417 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
418 unsigned *dst_factor, unsigned expected_dst,
419 unsigned replacement_src)
420 {
421 if (*src_factor == expected_dst &&
422 *dst_factor == VK_BLEND_FACTOR_ZERO) {
423 *src_factor = VK_BLEND_FACTOR_ZERO;
424 *dst_factor = replacement_src;
425
426 /* Commuting the operands requires reversing subtractions. */
427 if (*func == VK_BLEND_OP_SUBTRACT)
428 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
429 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
430 *func = VK_BLEND_OP_SUBTRACT;
431 }
432 }
433
434 static bool si_blend_factor_uses_dst(unsigned factor)
435 {
436 return factor == VK_BLEND_FACTOR_DST_COLOR ||
437 factor == VK_BLEND_FACTOR_DST_ALPHA ||
438 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
439 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
440 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
441 }
442
443 static bool is_dual_src(VkBlendFactor factor)
444 {
445 switch (factor) {
446 case VK_BLEND_FACTOR_SRC1_COLOR:
447 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
448 case VK_BLEND_FACTOR_SRC1_ALPHA:
449 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
450 return true;
451 default:
452 return false;
453 }
454 }
455
456 static unsigned radv_choose_spi_color_format(VkFormat vk_format,
457 bool blend_enable,
458 bool blend_need_alpha)
459 {
460 const struct vk_format_description *desc = vk_format_description(vk_format);
461 struct ac_spi_color_formats formats = {};
462 unsigned format, ntype, swap;
463
464 format = radv_translate_colorformat(vk_format);
465 ntype = radv_translate_color_numformat(vk_format, desc,
466 vk_format_get_first_non_void_channel(vk_format));
467 swap = radv_translate_colorswap(vk_format, false);
468
469 ac_choose_spi_color_formats(format, swap, ntype, false, &formats);
470
471 if (blend_enable && blend_need_alpha)
472 return formats.blend_alpha;
473 else if(blend_need_alpha)
474 return formats.alpha;
475 else if(blend_enable)
476 return formats.blend;
477 else
478 return formats.normal;
479 }
480
481 static void
482 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
483 const VkGraphicsPipelineCreateInfo *pCreateInfo,
484 struct radv_blend_state *blend)
485 {
486 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
487 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
488 unsigned col_format = 0;
489 unsigned num_targets;
490
491 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
492 unsigned cf;
493
494 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
495 cf = V_028714_SPI_SHADER_ZERO;
496 } else {
497 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
498 bool blend_enable =
499 blend->blend_enable_4bit & (0xfu << (i * 4));
500
501 cf = radv_choose_spi_color_format(attachment->format,
502 blend_enable,
503 blend->need_src_alpha & (1 << i));
504 }
505
506 col_format |= cf << (4 * i);
507 }
508
509 if (!(col_format & 0xf) && blend->need_src_alpha & (1 << 0)) {
510 /* When a subpass doesn't have any color attachments, write the
511 * alpha channel of MRT0 when alpha coverage is enabled because
512 * the depth attachment needs it.
513 */
514 col_format |= V_028714_SPI_SHADER_32_AR;
515 }
516
517 /* If the i-th target format is set, all previous target formats must
518 * be non-zero to avoid hangs.
519 */
520 num_targets = (util_last_bit(col_format) + 3) / 4;
521 for (unsigned i = 0; i < num_targets; i++) {
522 if (!(col_format & (0xf << (i * 4)))) {
523 col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
524 }
525 }
526
527 /* The output for dual source blending should have the same format as
528 * the first output.
529 */
530 if (blend->mrt0_is_dual_src)
531 col_format |= (col_format & 0xf) << 4;
532
533 blend->spi_shader_col_format = col_format;
534 }
535
536 static bool
537 format_is_int8(VkFormat format)
538 {
539 const struct vk_format_description *desc = vk_format_description(format);
540 int channel = vk_format_get_first_non_void_channel(format);
541
542 return channel >= 0 && desc->channel[channel].pure_integer &&
543 desc->channel[channel].size == 8;
544 }
545
546 static bool
547 format_is_int10(VkFormat format)
548 {
549 const struct vk_format_description *desc = vk_format_description(format);
550
551 if (desc->nr_channels != 4)
552 return false;
553 for (unsigned i = 0; i < 4; i++) {
554 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
555 return true;
556 }
557 return false;
558 }
559
560 /*
561 * Ordered so that for each i,
562 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
563 */
564 const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = {
565 VK_FORMAT_R32_SFLOAT,
566 VK_FORMAT_R32G32_SFLOAT,
567 VK_FORMAT_R8G8B8A8_UNORM,
568 VK_FORMAT_R16G16B16A16_UNORM,
569 VK_FORMAT_R16G16B16A16_SNORM,
570 VK_FORMAT_R16G16B16A16_UINT,
571 VK_FORMAT_R16G16B16A16_SINT,
572 VK_FORMAT_R32G32B32A32_SFLOAT,
573 VK_FORMAT_R8G8B8A8_UINT,
574 VK_FORMAT_R8G8B8A8_SINT,
575 VK_FORMAT_A2R10G10B10_UINT_PACK32,
576 VK_FORMAT_A2R10G10B10_SINT_PACK32,
577 };
578
579 unsigned radv_format_meta_fs_key(VkFormat format)
580 {
581 unsigned col_format = radv_choose_spi_color_format(format, false, false);
582
583 assert(col_format != V_028714_SPI_SHADER_32_AR);
584 if (col_format >= V_028714_SPI_SHADER_32_AR)
585 --col_format; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
586
587 --col_format; /* Skip V_028714_SPI_SHADER_ZERO */
588 bool is_int8 = format_is_int8(format);
589 bool is_int10 = format_is_int10(format);
590
591 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
592 }
593
594 static void
595 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
596 unsigned *is_int8, unsigned *is_int10)
597 {
598 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
599 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
600 *is_int8 = 0;
601 *is_int10 = 0;
602
603 for (unsigned i = 0; i < subpass->color_count; ++i) {
604 struct radv_render_pass_attachment *attachment;
605
606 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
607 continue;
608
609 attachment = pass->attachments + subpass->color_attachments[i].attachment;
610
611 if (format_is_int8(attachment->format))
612 *is_int8 |= 1 << i;
613 if (format_is_int10(attachment->format))
614 *is_int10 |= 1 << i;
615 }
616 }
617
618 static void
619 radv_blend_check_commutativity(struct radv_blend_state *blend,
620 VkBlendOp op, VkBlendFactor src,
621 VkBlendFactor dst, unsigned chanmask)
622 {
623 /* Src factor is allowed when it does not depend on Dst. */
624 static const uint32_t src_allowed =
625 (1u << VK_BLEND_FACTOR_ONE) |
626 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
627 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
628 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
629 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
630 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
631 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
632 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
633 (1u << VK_BLEND_FACTOR_ZERO) |
634 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
635 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
636 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
637 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
638 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
639 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
640
641 if (dst == VK_BLEND_FACTOR_ONE &&
642 (src_allowed & (1u << src))) {
643 /* Addition is commutative, but floating point addition isn't
644 * associative: subtle changes can be introduced via different
645 * rounding. Be conservative, only enable for min and max.
646 */
647 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
648 blend->commutative_4bit |= chanmask;
649 }
650 }
651
652 static struct radv_blend_state
653 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
654 const VkGraphicsPipelineCreateInfo *pCreateInfo,
655 const struct radv_graphics_pipeline_create_info *extra)
656 {
657 const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
658 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
659 struct radv_blend_state blend = {0};
660 unsigned mode = V_028808_CB_NORMAL;
661 int i;
662
663 if (extra && extra->custom_blend_mode) {
664 blend.single_cb_enable = true;
665 mode = extra->custom_blend_mode;
666 }
667
668 blend.cb_color_control = 0;
669 if (vkblend) {
670 if (vkblend->logicOpEnable)
671 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
672 else
673 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
674 }
675
676 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
677 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
678 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
679 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
680 S_028B70_OFFSET_ROUND(1);
681
682 if (vkms && vkms->alphaToCoverageEnable) {
683 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
684 blend.need_src_alpha |= 0x1;
685 }
686
687 blend.cb_target_mask = 0;
688 if (vkblend) {
689 for (i = 0; i < vkblend->attachmentCount; i++) {
690 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
691 unsigned blend_cntl = 0;
692 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
693 VkBlendOp eqRGB = att->colorBlendOp;
694 VkBlendFactor srcRGB = att->srcColorBlendFactor;
695 VkBlendFactor dstRGB = att->dstColorBlendFactor;
696 VkBlendOp eqA = att->alphaBlendOp;
697 VkBlendFactor srcA = att->srcAlphaBlendFactor;
698 VkBlendFactor dstA = att->dstAlphaBlendFactor;
699
700 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
701
702 if (!att->colorWriteMask)
703 continue;
704
705 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
706 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
707 if (!att->blendEnable) {
708 blend.cb_blend_control[i] = blend_cntl;
709 continue;
710 }
711
712 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
713 if (i == 0)
714 blend.mrt0_is_dual_src = true;
715
716 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
717 srcRGB = VK_BLEND_FACTOR_ONE;
718 dstRGB = VK_BLEND_FACTOR_ONE;
719 }
720 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
721 srcA = VK_BLEND_FACTOR_ONE;
722 dstA = VK_BLEND_FACTOR_ONE;
723 }
724
725 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
726 0x7 << (4 * i));
727 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
728 0x8 << (4 * i));
729
730 /* Blending optimizations for RB+.
731 * These transformations don't change the behavior.
732 *
733 * First, get rid of DST in the blend factors:
734 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
735 */
736 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
737 VK_BLEND_FACTOR_DST_COLOR,
738 VK_BLEND_FACTOR_SRC_COLOR);
739
740 si_blend_remove_dst(&eqA, &srcA, &dstA,
741 VK_BLEND_FACTOR_DST_COLOR,
742 VK_BLEND_FACTOR_SRC_COLOR);
743
744 si_blend_remove_dst(&eqA, &srcA, &dstA,
745 VK_BLEND_FACTOR_DST_ALPHA,
746 VK_BLEND_FACTOR_SRC_ALPHA);
747
748 /* Look up the ideal settings from tables. */
749 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
750 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
751 srcA_opt = si_translate_blend_opt_factor(srcA, true);
752 dstA_opt = si_translate_blend_opt_factor(dstA, true);
753
754 /* Handle interdependencies. */
755 if (si_blend_factor_uses_dst(srcRGB))
756 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
757 if (si_blend_factor_uses_dst(srcA))
758 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
759
760 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
761 (dstRGB == VK_BLEND_FACTOR_ZERO ||
762 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
763 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
764 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
765
766 /* Set the final value. */
767 blend.sx_mrt_blend_opt[i] =
768 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
769 S_028760_COLOR_DST_OPT(dstRGB_opt) |
770 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
771 S_028760_ALPHA_SRC_OPT(srcA_opt) |
772 S_028760_ALPHA_DST_OPT(dstA_opt) |
773 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
774 blend_cntl |= S_028780_ENABLE(1);
775
776 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
777 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
778 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
779 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
780 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
781 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
782 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
783 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
784 }
785 blend.cb_blend_control[i] = blend_cntl;
786
787 blend.blend_enable_4bit |= 0xfu << (i * 4);
788
789 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
790 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
791 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
792 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
793 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
794 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
795 blend.need_src_alpha |= 1 << i;
796 }
797 for (i = vkblend->attachmentCount; i < 8; i++) {
798 blend.cb_blend_control[i] = 0;
799 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
800 }
801 }
802
803 if (pipeline->device->physical_device->rad_info.has_rbplus) {
804 /* Disable RB+ blend optimizations for dual source blending. */
805 if (blend.mrt0_is_dual_src) {
806 for (i = 0; i < 8; i++) {
807 blend.sx_mrt_blend_opt[i] =
808 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
809 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
810 }
811 }
812
813 /* RB+ doesn't work with dual source blending, logic op and
814 * RESOLVE.
815 */
816 if (blend.mrt0_is_dual_src ||
817 (vkblend && vkblend->logicOpEnable) ||
818 mode == V_028808_CB_RESOLVE)
819 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
820 }
821
822 if (blend.cb_target_mask)
823 blend.cb_color_control |= S_028808_MODE(mode);
824 else
825 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
826
827 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
828 return blend;
829 }
830
831 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
832 {
833 switch (op) {
834 case VK_STENCIL_OP_KEEP:
835 return V_02842C_STENCIL_KEEP;
836 case VK_STENCIL_OP_ZERO:
837 return V_02842C_STENCIL_ZERO;
838 case VK_STENCIL_OP_REPLACE:
839 return V_02842C_STENCIL_REPLACE_TEST;
840 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
841 return V_02842C_STENCIL_ADD_CLAMP;
842 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
843 return V_02842C_STENCIL_SUB_CLAMP;
844 case VK_STENCIL_OP_INVERT:
845 return V_02842C_STENCIL_INVERT;
846 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
847 return V_02842C_STENCIL_ADD_WRAP;
848 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
849 return V_02842C_STENCIL_SUB_WRAP;
850 default:
851 return 0;
852 }
853 }
854
855 static uint32_t si_translate_fill(VkPolygonMode func)
856 {
857 switch(func) {
858 case VK_POLYGON_MODE_FILL:
859 return V_028814_X_DRAW_TRIANGLES;
860 case VK_POLYGON_MODE_LINE:
861 return V_028814_X_DRAW_LINES;
862 case VK_POLYGON_MODE_POINT:
863 return V_028814_X_DRAW_POINTS;
864 default:
865 assert(0);
866 return V_028814_X_DRAW_POINTS;
867 }
868 }
869
870 static uint8_t radv_pipeline_get_ps_iter_samples(const VkGraphicsPipelineCreateInfo *pCreateInfo)
871 {
872 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
873 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
874 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
875 uint32_t ps_iter_samples = 1;
876 uint32_t num_samples;
877
878 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
879 *
880 * "If the VK_AMD_mixed_attachment_samples extension is enabled and the
881 * subpass uses color attachments, totalSamples is the number of
882 * samples of the color attachments. Otherwise, totalSamples is the
883 * value of VkPipelineMultisampleStateCreateInfo::rasterizationSamples
884 * specified at pipeline creation time."
885 */
886 if (subpass->has_color_att) {
887 num_samples = subpass->color_sample_count;
888 } else {
889 num_samples = vkms->rasterizationSamples;
890 }
891
892 if (vkms->sampleShadingEnable) {
893 ps_iter_samples = ceilf(vkms->minSampleShading * num_samples);
894 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
895 }
896 return ps_iter_samples;
897 }
898
899 static bool
900 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
901 {
902 return pCreateInfo->depthTestEnable &&
903 pCreateInfo->depthWriteEnable &&
904 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
905 }
906
907 static bool
908 radv_writes_stencil(const VkStencilOpState *state)
909 {
910 return state->writeMask &&
911 (state->failOp != VK_STENCIL_OP_KEEP ||
912 state->passOp != VK_STENCIL_OP_KEEP ||
913 state->depthFailOp != VK_STENCIL_OP_KEEP);
914 }
915
916 static bool
917 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
918 {
919 return pCreateInfo->stencilTestEnable &&
920 (radv_writes_stencil(&pCreateInfo->front) ||
921 radv_writes_stencil(&pCreateInfo->back));
922 }
923
924 static bool
925 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
926 {
927 return radv_is_depth_write_enabled(pCreateInfo) ||
928 radv_is_stencil_write_enabled(pCreateInfo);
929 }
930
931 static bool
932 radv_order_invariant_stencil_op(VkStencilOp op)
933 {
934 /* REPLACE is normally order invariant, except when the stencil
935 * reference value is written by the fragment shader. Tracking this
936 * interaction does not seem worth the effort, so be conservative.
937 */
938 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
939 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
940 op != VK_STENCIL_OP_REPLACE;
941 }
942
943 static bool
944 radv_order_invariant_stencil_state(const VkStencilOpState *state)
945 {
946 /* Compute whether, assuming Z writes are disabled, this stencil state
947 * is order invariant in the sense that the set of passing fragments as
948 * well as the final stencil buffer result does not depend on the order
949 * of fragments.
950 */
951 return !state->writeMask ||
952 /* The following assumes that Z writes are disabled. */
953 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
954 radv_order_invariant_stencil_op(state->passOp) &&
955 radv_order_invariant_stencil_op(state->depthFailOp)) ||
956 (state->compareOp == VK_COMPARE_OP_NEVER &&
957 radv_order_invariant_stencil_op(state->failOp));
958 }
959
960 static bool
961 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
962 struct radv_blend_state *blend,
963 const VkGraphicsPipelineCreateInfo *pCreateInfo)
964 {
965 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
966 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
967 const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
968 const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
969 unsigned colormask = blend->cb_target_enabled_4bit;
970
971 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
972 return false;
973
974 /* Be conservative if a logic operation is enabled with color buffers. */
975 if (colormask && vkblend && vkblend->logicOpEnable)
976 return false;
977
978 /* Default depth/stencil invariance when no attachment is bound. */
979 struct radv_dsa_order_invariance dsa_order_invariant = {
980 .zs = true, .pass_set = true
981 };
982
983 if (vkds) {
984 struct radv_render_pass_attachment *attachment =
985 pass->attachments + subpass->depth_stencil_attachment->attachment;
986 bool has_stencil = vk_format_is_stencil(attachment->format);
987 struct radv_dsa_order_invariance order_invariance[2];
988 struct radv_shader_variant *ps =
989 pipeline->shaders[MESA_SHADER_FRAGMENT];
990
991 /* Compute depth/stencil order invariance in order to know if
992 * it's safe to enable out-of-order.
993 */
994 bool zfunc_is_ordered =
995 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
996 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
997 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
998 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
999 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
1000
1001 bool nozwrite_and_order_invariant_stencil =
1002 !radv_is_ds_write_enabled(vkds) ||
1003 (!radv_is_depth_write_enabled(vkds) &&
1004 radv_order_invariant_stencil_state(&vkds->front) &&
1005 radv_order_invariant_stencil_state(&vkds->back));
1006
1007 order_invariance[1].zs =
1008 nozwrite_and_order_invariant_stencil ||
1009 (!radv_is_stencil_write_enabled(vkds) &&
1010 zfunc_is_ordered);
1011 order_invariance[0].zs =
1012 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
1013
1014 order_invariance[1].pass_set =
1015 nozwrite_and_order_invariant_stencil ||
1016 (!radv_is_stencil_write_enabled(vkds) &&
1017 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1018 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
1019 order_invariance[0].pass_set =
1020 !radv_is_depth_write_enabled(vkds) ||
1021 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1022 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
1023
1024 dsa_order_invariant = order_invariance[has_stencil];
1025 if (!dsa_order_invariant.zs)
1026 return false;
1027
1028 /* The set of PS invocations is always order invariant,
1029 * except when early Z/S tests are requested.
1030 */
1031 if (ps &&
1032 ps->info.ps.writes_memory &&
1033 ps->info.ps.early_fragment_test &&
1034 !dsa_order_invariant.pass_set)
1035 return false;
1036
1037 /* Determine if out-of-order rasterization should be disabled
1038 * when occlusion queries are used.
1039 */
1040 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
1041 !dsa_order_invariant.pass_set;
1042 }
1043
1044 /* No color buffers are enabled for writing. */
1045 if (!colormask)
1046 return true;
1047
1048 unsigned blendmask = colormask & blend->blend_enable_4bit;
1049
1050 if (blendmask) {
1051 /* Only commutative blending. */
1052 if (blendmask & ~blend->commutative_4bit)
1053 return false;
1054
1055 if (!dsa_order_invariant.pass_set)
1056 return false;
1057 }
1058
1059 if (colormask & ~blendmask)
1060 return false;
1061
1062 return true;
1063 }
1064
1065 static void
1066 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1067 struct radv_blend_state *blend,
1068 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1069 {
1070 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
1071 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1072 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1073 bool out_of_order_rast = false;
1074 int ps_iter_samples = 1;
1075 uint32_t mask = 0xffff;
1076
1077 if (vkms) {
1078 ms->num_samples = vkms->rasterizationSamples;
1079
1080 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1081 *
1082 * "Sample shading is enabled for a graphics pipeline:
1083 *
1084 * - If the interface of the fragment shader entry point of the
1085 * graphics pipeline includes an input variable decorated
1086 * with SampleId or SamplePosition. In this case
1087 * minSampleShadingFactor takes the value 1.0.
1088 * - Else if the sampleShadingEnable member of the
1089 * VkPipelineMultisampleStateCreateInfo structure specified
1090 * when creating the graphics pipeline is set to VK_TRUE. In
1091 * this case minSampleShadingFactor takes the value of
1092 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1093 *
1094 * Otherwise, sample shading is considered disabled."
1095 */
1096 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.force_persample) {
1097 ps_iter_samples = ms->num_samples;
1098 } else {
1099 ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
1100 }
1101 } else {
1102 ms->num_samples = 1;
1103 }
1104
1105 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1106 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1107 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1108 /* Out-of-order rasterization is explicitly enabled by the
1109 * application.
1110 */
1111 out_of_order_rast = true;
1112 } else {
1113 /* Determine if the driver can enable out-of-order
1114 * rasterization internally.
1115 */
1116 out_of_order_rast =
1117 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1118 }
1119
1120 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1121 ms->pa_sc_aa_config = 0;
1122 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1123 S_028804_INCOHERENT_EQAA_READS(1) |
1124 S_028804_INTERPOLATE_COMP_Z(1) |
1125 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1126 ms->pa_sc_mode_cntl_1 =
1127 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1128 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1129 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
1130 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1131 /* always 1: */
1132 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1133 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1134 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1135 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1136 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1137 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1138 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1139 S_028A48_VPORT_SCISSOR_ENABLE(1);
1140
1141 const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line =
1142 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1143 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
1144 if (rast_line) {
1145 ms->pa_sc_mode_cntl_0 |= S_028A48_LINE_STIPPLE_ENABLE(rast_line->stippledLineEnable);
1146 if (rast_line->lineRasterizationMode == VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT) {
1147 /* From the Vulkan spec 1.1.129:
1148 *
1149 * "When VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT lines
1150 * are being rasterized, sample locations may all be
1151 * treated as being at the pixel center (this may
1152 * affect attribute and depth interpolation)."
1153 */
1154 ms->num_samples = 1;
1155 }
1156 }
1157
1158 if (ms->num_samples > 1) {
1159 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1160 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1161 uint32_t z_samples = subpass->depth_stencil_attachment ? subpass->depth_sample_count : ms->num_samples;
1162 unsigned log_samples = util_logbase2(ms->num_samples);
1163 unsigned log_z_samples = util_logbase2(z_samples);
1164 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1165 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1166 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1167 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
1168 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1169 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1170 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1171 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1172 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) |
1173 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1174 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1175 if (ps_iter_samples > 1)
1176 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1177 }
1178
1179 if (vkms && vkms->pSampleMask) {
1180 mask = vkms->pSampleMask[0] & 0xffff;
1181 }
1182
1183 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1184 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1185 }
1186
1187 static bool
1188 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1189 {
1190 switch (topology) {
1191 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1192 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1193 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1194 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1195 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1196 return false;
1197 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1198 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1199 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1200 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1201 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1202 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1203 return true;
1204 default:
1205 unreachable("unhandled primitive type");
1206 }
1207 }
1208
1209 static uint32_t
1210 si_translate_prim(enum VkPrimitiveTopology topology)
1211 {
1212 switch (topology) {
1213 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1214 return V_008958_DI_PT_POINTLIST;
1215 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1216 return V_008958_DI_PT_LINELIST;
1217 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1218 return V_008958_DI_PT_LINESTRIP;
1219 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1220 return V_008958_DI_PT_TRILIST;
1221 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1222 return V_008958_DI_PT_TRISTRIP;
1223 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1224 return V_008958_DI_PT_TRIFAN;
1225 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1226 return V_008958_DI_PT_LINELIST_ADJ;
1227 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1228 return V_008958_DI_PT_LINESTRIP_ADJ;
1229 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1230 return V_008958_DI_PT_TRILIST_ADJ;
1231 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1232 return V_008958_DI_PT_TRISTRIP_ADJ;
1233 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1234 return V_008958_DI_PT_PATCH;
1235 default:
1236 assert(0);
1237 return 0;
1238 }
1239 }
1240
1241 static uint32_t
1242 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1243 {
1244 switch (gl_prim) {
1245 case 0: /* GL_POINTS */
1246 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1247 case 1: /* GL_LINES */
1248 case 3: /* GL_LINE_STRIP */
1249 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1250 case 0x8E7A: /* GL_ISOLINES */
1251 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1252
1253 case 4: /* GL_TRIANGLES */
1254 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1255 case 5: /* GL_TRIANGLE_STRIP */
1256 case 7: /* GL_QUADS */
1257 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1258 default:
1259 assert(0);
1260 return 0;
1261 }
1262 }
1263
1264 static uint32_t
1265 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1266 {
1267 switch (topology) {
1268 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1269 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1270 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1271 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1272 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1273 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1274 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1275 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1276 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1277 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1278 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1279 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1280 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1281 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1282 default:
1283 assert(0);
1284 return 0;
1285 }
1286 }
1287
1288 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1289 {
1290 switch(state) {
1291 case VK_DYNAMIC_STATE_VIEWPORT:
1292 return RADV_DYNAMIC_VIEWPORT;
1293 case VK_DYNAMIC_STATE_SCISSOR:
1294 return RADV_DYNAMIC_SCISSOR;
1295 case VK_DYNAMIC_STATE_LINE_WIDTH:
1296 return RADV_DYNAMIC_LINE_WIDTH;
1297 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1298 return RADV_DYNAMIC_DEPTH_BIAS;
1299 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1300 return RADV_DYNAMIC_BLEND_CONSTANTS;
1301 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1302 return RADV_DYNAMIC_DEPTH_BOUNDS;
1303 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1304 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1305 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1306 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1307 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1308 return RADV_DYNAMIC_STENCIL_REFERENCE;
1309 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1310 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1311 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
1312 return RADV_DYNAMIC_SAMPLE_LOCATIONS;
1313 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT:
1314 return RADV_DYNAMIC_LINE_STIPPLE;
1315 default:
1316 unreachable("Unhandled dynamic state");
1317 }
1318 }
1319
1320 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1321 {
1322 uint32_t states = RADV_DYNAMIC_ALL;
1323
1324 /* If rasterization is disabled we do not care about any of the dynamic states,
1325 * since they are all rasterization related only. */
1326 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1327 return 0;
1328
1329 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1330 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1331
1332 if (!pCreateInfo->pDepthStencilState ||
1333 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1334 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1335
1336 if (!pCreateInfo->pDepthStencilState ||
1337 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1338 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1339 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1340 RADV_DYNAMIC_STENCIL_REFERENCE);
1341
1342 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1343 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1344
1345 if (!pCreateInfo->pMultisampleState ||
1346 !vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1347 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT))
1348 states &= ~RADV_DYNAMIC_SAMPLE_LOCATIONS;
1349
1350 if (!pCreateInfo->pRasterizationState ||
1351 !vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1352 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT))
1353 states &= ~RADV_DYNAMIC_LINE_STIPPLE;
1354
1355 /* TODO: blend constants & line width. */
1356
1357 return states;
1358 }
1359
1360
1361 static void
1362 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1363 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1364 {
1365 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1366 uint32_t states = needed_states;
1367 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1368 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1369
1370 pipeline->dynamic_state = default_dynamic_state;
1371 pipeline->graphics.needed_dynamic_state = needed_states;
1372
1373 if (pCreateInfo->pDynamicState) {
1374 /* Remove all of the states that are marked as dynamic */
1375 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1376 for (uint32_t s = 0; s < count; s++)
1377 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1378 }
1379
1380 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1381
1382 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1383 assert(pCreateInfo->pViewportState);
1384
1385 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1386 if (states & RADV_DYNAMIC_VIEWPORT) {
1387 typed_memcpy(dynamic->viewport.viewports,
1388 pCreateInfo->pViewportState->pViewports,
1389 pCreateInfo->pViewportState->viewportCount);
1390 }
1391 }
1392
1393 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1394 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1395 if (states & RADV_DYNAMIC_SCISSOR) {
1396 typed_memcpy(dynamic->scissor.scissors,
1397 pCreateInfo->pViewportState->pScissors,
1398 pCreateInfo->pViewportState->scissorCount);
1399 }
1400 }
1401
1402 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1403 assert(pCreateInfo->pRasterizationState);
1404 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1405 }
1406
1407 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1408 assert(pCreateInfo->pRasterizationState);
1409 dynamic->depth_bias.bias =
1410 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1411 dynamic->depth_bias.clamp =
1412 pCreateInfo->pRasterizationState->depthBiasClamp;
1413 dynamic->depth_bias.slope =
1414 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1415 }
1416
1417 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1418 *
1419 * pColorBlendState is [...] NULL if the pipeline has rasterization
1420 * disabled or if the subpass of the render pass the pipeline is
1421 * created against does not use any color attachments.
1422 */
1423 if (subpass->has_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1424 assert(pCreateInfo->pColorBlendState);
1425 typed_memcpy(dynamic->blend_constants,
1426 pCreateInfo->pColorBlendState->blendConstants, 4);
1427 }
1428
1429 /* If there is no depthstencil attachment, then don't read
1430 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1431 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1432 * no need to override the depthstencil defaults in
1433 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1434 *
1435 * Section 9.2 of the Vulkan 1.0.15 spec says:
1436 *
1437 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1438 * disabled or if the subpass of the render pass the pipeline is created
1439 * against does not use a depth/stencil attachment.
1440 */
1441 if (needed_states && subpass->depth_stencil_attachment) {
1442 assert(pCreateInfo->pDepthStencilState);
1443
1444 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1445 dynamic->depth_bounds.min =
1446 pCreateInfo->pDepthStencilState->minDepthBounds;
1447 dynamic->depth_bounds.max =
1448 pCreateInfo->pDepthStencilState->maxDepthBounds;
1449 }
1450
1451 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1452 dynamic->stencil_compare_mask.front =
1453 pCreateInfo->pDepthStencilState->front.compareMask;
1454 dynamic->stencil_compare_mask.back =
1455 pCreateInfo->pDepthStencilState->back.compareMask;
1456 }
1457
1458 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1459 dynamic->stencil_write_mask.front =
1460 pCreateInfo->pDepthStencilState->front.writeMask;
1461 dynamic->stencil_write_mask.back =
1462 pCreateInfo->pDepthStencilState->back.writeMask;
1463 }
1464
1465 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1466 dynamic->stencil_reference.front =
1467 pCreateInfo->pDepthStencilState->front.reference;
1468 dynamic->stencil_reference.back =
1469 pCreateInfo->pDepthStencilState->back.reference;
1470 }
1471 }
1472
1473 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1474 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1475 if (needed_states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1476 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1477 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1478 typed_memcpy(dynamic->discard_rectangle.rectangles,
1479 discard_rectangle_info->pDiscardRectangles,
1480 discard_rectangle_info->discardRectangleCount);
1481 }
1482 }
1483
1484 if (needed_states & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
1485 const VkPipelineSampleLocationsStateCreateInfoEXT *sample_location_info =
1486 vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1487 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1488 /* If sampleLocationsEnable is VK_FALSE, the default sample
1489 * locations are used and the values specified in
1490 * sampleLocationsInfo are ignored.
1491 */
1492 if (sample_location_info->sampleLocationsEnable) {
1493 const VkSampleLocationsInfoEXT *pSampleLocationsInfo =
1494 &sample_location_info->sampleLocationsInfo;
1495
1496 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
1497
1498 dynamic->sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
1499 dynamic->sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
1500 dynamic->sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
1501 typed_memcpy(&dynamic->sample_location.locations[0],
1502 pSampleLocationsInfo->pSampleLocations,
1503 pSampleLocationsInfo->sampleLocationsCount);
1504 }
1505 }
1506
1507 const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line_info =
1508 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1509 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
1510 if (needed_states & RADV_DYNAMIC_LINE_STIPPLE) {
1511 dynamic->line_stipple.factor = rast_line_info->lineStippleFactor;
1512 dynamic->line_stipple.pattern = rast_line_info->lineStipplePattern;
1513 }
1514
1515 pipeline->dynamic_state.mask = states;
1516 }
1517
1518 static void
1519 gfx9_get_gs_info(const struct radv_pipeline_key *key,
1520 const struct radv_pipeline *pipeline,
1521 nir_shader **nir,
1522 struct radv_shader_info *infos,
1523 struct gfx9_gs_info *out)
1524 {
1525 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1526 struct radv_es_output_info *es_info;
1527 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1528 es_info = nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1529 else
1530 es_info = nir[MESA_SHADER_TESS_CTRL] ?
1531 &infos[MESA_SHADER_TESS_EVAL].tes.es_info :
1532 &infos[MESA_SHADER_VERTEX].vs.es_info;
1533
1534 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1535 bool uses_adjacency;
1536 switch(key->topology) {
1537 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1538 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1539 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1540 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1541 uses_adjacency = true;
1542 break;
1543 default:
1544 uses_adjacency = false;
1545 break;
1546 }
1547
1548 /* All these are in dwords: */
1549 /* We can't allow using the whole LDS, because GS waves compete with
1550 * other shader stages for LDS space. */
1551 const unsigned max_lds_size = 8 * 1024;
1552 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1553 unsigned esgs_lds_size;
1554
1555 /* All these are per subgroup: */
1556 const unsigned max_out_prims = 32 * 1024;
1557 const unsigned max_es_verts = 255;
1558 const unsigned ideal_gs_prims = 64;
1559 unsigned max_gs_prims, gs_prims;
1560 unsigned min_es_verts, es_verts, worst_case_es_verts;
1561
1562 if (uses_adjacency || gs_num_invocations > 1)
1563 max_gs_prims = 127 / gs_num_invocations;
1564 else
1565 max_gs_prims = 255;
1566
1567 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1568 * Make sure we don't go over the maximum value.
1569 */
1570 if (gs_info->gs.vertices_out > 0) {
1571 max_gs_prims = MIN2(max_gs_prims,
1572 max_out_prims /
1573 (gs_info->gs.vertices_out * gs_num_invocations));
1574 }
1575 assert(max_gs_prims > 0);
1576
1577 /* If the primitive has adjacency, halve the number of vertices
1578 * that will be reused in multiple primitives.
1579 */
1580 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1581
1582 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1583 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1584
1585 /* Compute ESGS LDS size based on the worst case number of ES vertices
1586 * needed to create the target number of GS prims per subgroup.
1587 */
1588 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1589
1590 /* If total LDS usage is too big, refactor partitions based on ratio
1591 * of ESGS item sizes.
1592 */
1593 if (esgs_lds_size > max_lds_size) {
1594 /* Our target GS Prims Per Subgroup was too large. Calculate
1595 * the maximum number of GS Prims Per Subgroup that will fit
1596 * into LDS, capped by the maximum that the hardware can support.
1597 */
1598 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1599 max_gs_prims);
1600 assert(gs_prims > 0);
1601 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1602 max_es_verts);
1603
1604 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1605 assert(esgs_lds_size <= max_lds_size);
1606 }
1607
1608 /* Now calculate remaining ESGS information. */
1609 if (esgs_lds_size)
1610 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1611 else
1612 es_verts = max_es_verts;
1613
1614 /* Vertices for adjacency primitives are not always reused, so restore
1615 * it for ES_VERTS_PER_SUBGRP.
1616 */
1617 min_es_verts = gs_info->gs.vertices_in;
1618
1619 /* For normal primitives, the VGT only checks if they are past the ES
1620 * verts per subgroup after allocating a full GS primitive and if they
1621 * are, kick off a new subgroup. But if those additional ES verts are
1622 * unique (e.g. not reused) we need to make sure there is enough LDS
1623 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1624 */
1625 es_verts -= min_es_verts - 1;
1626
1627 uint32_t es_verts_per_subgroup = es_verts;
1628 uint32_t gs_prims_per_subgroup = gs_prims;
1629 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1630 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1631 out->lds_size = align(esgs_lds_size, 128) / 128;
1632 out->vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1633 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1634 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1635 out->vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1636 out->vgt_esgs_ring_itemsize = esgs_itemsize;
1637 assert(max_prims_per_subgroup <= max_out_prims);
1638 }
1639
1640 static void clamp_gsprims_to_esverts(unsigned *max_gsprims, unsigned max_esverts,
1641 unsigned min_verts_per_prim, bool use_adjacency)
1642 {
1643 unsigned max_reuse = max_esverts - min_verts_per_prim;
1644 if (use_adjacency)
1645 max_reuse /= 2;
1646 *max_gsprims = MIN2(*max_gsprims, 1 + max_reuse);
1647 }
1648
1649 static unsigned
1650 radv_get_num_input_vertices(nir_shader **nir)
1651 {
1652 if (nir[MESA_SHADER_GEOMETRY]) {
1653 nir_shader *gs = nir[MESA_SHADER_GEOMETRY];
1654
1655 return gs->info.gs.vertices_in;
1656 }
1657
1658 if (nir[MESA_SHADER_TESS_CTRL]) {
1659 nir_shader *tes = nir[MESA_SHADER_TESS_EVAL];
1660
1661 if (tes->info.tess.point_mode)
1662 return 1;
1663 if (tes->info.tess.primitive_mode == GL_ISOLINES)
1664 return 2;
1665 return 3;
1666 }
1667
1668 return 3;
1669 }
1670
1671 static void
1672 gfx10_get_ngg_info(const struct radv_pipeline_key *key,
1673 struct radv_pipeline *pipeline,
1674 nir_shader **nir,
1675 struct radv_shader_info *infos,
1676 struct gfx10_ngg_info *ngg)
1677 {
1678 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1679 struct radv_es_output_info *es_info =
1680 nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1681 unsigned gs_type = nir[MESA_SHADER_GEOMETRY] ? MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX;
1682 unsigned max_verts_per_prim = radv_get_num_input_vertices(nir);
1683 unsigned min_verts_per_prim =
1684 gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1;
1685 unsigned gs_num_invocations = nir[MESA_SHADER_GEOMETRY] ? MAX2(gs_info->gs.invocations, 1) : 1;
1686 bool uses_adjacency;
1687 switch(key->topology) {
1688 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1689 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1690 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1691 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1692 uses_adjacency = true;
1693 break;
1694 default:
1695 uses_adjacency = false;
1696 break;
1697 }
1698
1699 /* All these are in dwords: */
1700 /* We can't allow using the whole LDS, because GS waves compete with
1701 * other shader stages for LDS space.
1702 *
1703 * TODO: We should really take the shader's internal LDS use into
1704 * account. The linker will fail if the size is greater than
1705 * 8K dwords.
1706 */
1707 const unsigned max_lds_size = 8 * 1024 - 768;
1708 const unsigned target_lds_size = max_lds_size;
1709 unsigned esvert_lds_size = 0;
1710 unsigned gsprim_lds_size = 0;
1711
1712 /* All these are per subgroup: */
1713 bool max_vert_out_per_gs_instance = false;
1714 unsigned max_esverts_base = 256;
1715 unsigned max_gsprims_base = 128; /* default prim group size clamp */
1716
1717 /* Hardware has the following non-natural restrictions on the value
1718 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1719 * the draw:
1720 * - at most 252 for any line input primitive type
1721 * - at most 251 for any quad input primitive type
1722 * - at most 251 for triangle strips with adjacency (this happens to
1723 * be the natural limit for triangle *lists* with adjacency)
1724 */
1725 max_esverts_base = MIN2(max_esverts_base, 251 + max_verts_per_prim - 1);
1726
1727 if (gs_type == MESA_SHADER_GEOMETRY) {
1728 unsigned max_out_verts_per_gsprim =
1729 gs_info->gs.vertices_out * gs_num_invocations;
1730
1731 if (max_out_verts_per_gsprim <= 256) {
1732 if (max_out_verts_per_gsprim) {
1733 max_gsprims_base = MIN2(max_gsprims_base,
1734 256 / max_out_verts_per_gsprim);
1735 }
1736 } else {
1737 /* Use special multi-cycling mode in which each GS
1738 * instance gets its own subgroup. Does not work with
1739 * tessellation. */
1740 max_vert_out_per_gs_instance = true;
1741 max_gsprims_base = 1;
1742 max_out_verts_per_gsprim = gs_info->gs.vertices_out;
1743 }
1744
1745 esvert_lds_size = es_info->esgs_itemsize / 4;
1746 gsprim_lds_size = (gs_info->gs.gsvs_vertex_size / 4 + 1) * max_out_verts_per_gsprim;
1747 } else {
1748 /* VS and TES. */
1749 /* LDS size for passing data from GS to ES. */
1750 struct radv_streamout_info *so_info = nir[MESA_SHADER_TESS_CTRL]
1751 ? &infos[MESA_SHADER_TESS_EVAL].so
1752 : &infos[MESA_SHADER_VERTEX].so;
1753
1754 if (so_info->num_outputs)
1755 esvert_lds_size = 4 * so_info->num_outputs + 1;
1756
1757 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1758 * corresponding to the ES thread of the provoking vertex. All
1759 * ES threads load and export PrimitiveID for their thread.
1760 */
1761 if (!nir[MESA_SHADER_TESS_CTRL] &&
1762 infos[MESA_SHADER_VERTEX].vs.outinfo.export_prim_id)
1763 esvert_lds_size = MAX2(esvert_lds_size, 1);
1764 }
1765
1766 unsigned max_gsprims = max_gsprims_base;
1767 unsigned max_esverts = max_esverts_base;
1768
1769 if (esvert_lds_size)
1770 max_esverts = MIN2(max_esverts, target_lds_size / esvert_lds_size);
1771 if (gsprim_lds_size)
1772 max_gsprims = MIN2(max_gsprims, target_lds_size / gsprim_lds_size);
1773
1774 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1775 clamp_gsprims_to_esverts(&max_gsprims, max_esverts, min_verts_per_prim, uses_adjacency);
1776 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1777
1778 if (esvert_lds_size || gsprim_lds_size) {
1779 /* Now that we have a rough proportionality between esverts
1780 * and gsprims based on the primitive type, scale both of them
1781 * down simultaneously based on required LDS space.
1782 *
1783 * We could be smarter about this if we knew how much vertex
1784 * reuse to expect.
1785 */
1786 unsigned lds_total = max_esverts * esvert_lds_size +
1787 max_gsprims * gsprim_lds_size;
1788 if (lds_total > target_lds_size) {
1789 max_esverts = max_esverts * target_lds_size / lds_total;
1790 max_gsprims = max_gsprims * target_lds_size / lds_total;
1791
1792 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1793 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1794 min_verts_per_prim, uses_adjacency);
1795 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1796 }
1797 }
1798
1799 /* Round up towards full wave sizes for better ALU utilization. */
1800 if (!max_vert_out_per_gs_instance) {
1801 unsigned orig_max_esverts;
1802 unsigned orig_max_gsprims;
1803 unsigned wavesize;
1804
1805 if (gs_type == MESA_SHADER_GEOMETRY) {
1806 wavesize = gs_info->wave_size;
1807 } else {
1808 wavesize = nir[MESA_SHADER_TESS_CTRL]
1809 ? infos[MESA_SHADER_TESS_EVAL].wave_size
1810 : infos[MESA_SHADER_VERTEX].wave_size;
1811 }
1812
1813 do {
1814 orig_max_esverts = max_esverts;
1815 orig_max_gsprims = max_gsprims;
1816
1817 max_esverts = align(max_esverts, wavesize);
1818 max_esverts = MIN2(max_esverts, max_esverts_base);
1819 if (esvert_lds_size)
1820 max_esverts = MIN2(max_esverts,
1821 (max_lds_size - max_gsprims * gsprim_lds_size) /
1822 esvert_lds_size);
1823 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1824
1825 max_gsprims = align(max_gsprims, wavesize);
1826 max_gsprims = MIN2(max_gsprims, max_gsprims_base);
1827 if (gsprim_lds_size)
1828 max_gsprims = MIN2(max_gsprims,
1829 (max_lds_size - max_esverts * esvert_lds_size) /
1830 gsprim_lds_size);
1831 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1832 min_verts_per_prim, uses_adjacency);
1833 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1834 } while (orig_max_esverts != max_esverts || orig_max_gsprims != max_gsprims);
1835 }
1836
1837 /* Hardware restriction: minimum value of max_esverts */
1838 max_esverts = MAX2(max_esverts, 23 + max_verts_per_prim);
1839
1840 unsigned max_out_vertices =
1841 max_vert_out_per_gs_instance ? gs_info->gs.vertices_out :
1842 gs_type == MESA_SHADER_GEOMETRY ?
1843 max_gsprims * gs_num_invocations * gs_info->gs.vertices_out :
1844 max_esverts;
1845 assert(max_out_vertices <= 256);
1846
1847 unsigned prim_amp_factor = 1;
1848 if (gs_type == MESA_SHADER_GEOMETRY) {
1849 /* Number of output primitives per GS input primitive after
1850 * GS instancing. */
1851 prim_amp_factor = gs_info->gs.vertices_out;
1852 }
1853
1854 /* The GE only checks against the maximum number of ES verts after
1855 * allocating a full GS primitive. So we need to ensure that whenever
1856 * this check passes, there is enough space for a full primitive without
1857 * vertex reuse.
1858 */
1859 ngg->hw_max_esverts = max_esverts - max_verts_per_prim + 1;
1860 ngg->max_gsprims = max_gsprims;
1861 ngg->max_out_verts = max_out_vertices;
1862 ngg->prim_amp_factor = prim_amp_factor;
1863 ngg->max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
1864 ngg->ngg_emit_size = max_gsprims * gsprim_lds_size;
1865 ngg->esgs_ring_size = 4 * max_esverts * esvert_lds_size;
1866
1867 if (gs_type == MESA_SHADER_GEOMETRY) {
1868 ngg->vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
1869 } else {
1870 ngg->vgt_esgs_ring_itemsize = 1;
1871 }
1872
1873 pipeline->graphics.esgs_ring_size = ngg->esgs_ring_size;
1874
1875 assert(ngg->hw_max_esverts >= 24); /* HW limitation */
1876 }
1877
1878 static void
1879 calculate_gs_ring_sizes(struct radv_pipeline *pipeline,
1880 const struct gfx9_gs_info *gs)
1881 {
1882 struct radv_device *device = pipeline->device;
1883 unsigned num_se = device->physical_device->rad_info.max_se;
1884 unsigned wave_size = 64;
1885 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1886 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1887 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1888 */
1889 unsigned gs_vertex_reuse =
1890 (device->physical_device->rad_info.chip_class >= GFX8 ? 32 : 16) * num_se;
1891 unsigned alignment = 256 * num_se;
1892 /* The maximum size is 63.999 MB per SE. */
1893 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1894 struct radv_shader_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1895
1896 /* Calculate the minimum size. */
1897 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1898 wave_size, alignment);
1899 /* These are recommended sizes, not minimum sizes. */
1900 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1901 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1902 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1903 gs_info->gs.max_gsvs_emit_size;
1904
1905 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1906 esgs_ring_size = align(esgs_ring_size, alignment);
1907 gsvs_ring_size = align(gsvs_ring_size, alignment);
1908
1909 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
1910 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1911
1912 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1913 }
1914
1915 static void si_multiwave_lds_size_workaround(struct radv_device *device,
1916 unsigned *lds_size)
1917 {
1918 /* If tessellation is all offchip and on-chip GS isn't used, this
1919 * workaround is not needed.
1920 */
1921 return;
1922
1923 /* SPI barrier management bug:
1924 * Make sure we have at least 4k of LDS in use to avoid the bug.
1925 * It applies to workgroup sizes of more than one wavefront.
1926 */
1927 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
1928 device->physical_device->rad_info.family == CHIP_KABINI)
1929 *lds_size = MAX2(*lds_size, 8);
1930 }
1931
1932 struct radv_shader_variant *
1933 radv_get_shader(struct radv_pipeline *pipeline,
1934 gl_shader_stage stage)
1935 {
1936 if (stage == MESA_SHADER_VERTEX) {
1937 if (pipeline->shaders[MESA_SHADER_VERTEX])
1938 return pipeline->shaders[MESA_SHADER_VERTEX];
1939 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1940 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1941 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1942 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1943 } else if (stage == MESA_SHADER_TESS_EVAL) {
1944 if (!radv_pipeline_has_tess(pipeline))
1945 return NULL;
1946 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1947 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1948 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1949 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1950 }
1951 return pipeline->shaders[stage];
1952 }
1953
1954 static struct radv_tessellation_state
1955 calculate_tess_state(struct radv_pipeline *pipeline,
1956 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1957 {
1958 unsigned num_tcs_input_cp;
1959 unsigned num_tcs_output_cp;
1960 unsigned lds_size;
1961 unsigned num_patches;
1962 struct radv_tessellation_state tess = {0};
1963
1964 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1965 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
1966 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
1967
1968 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
1969
1970 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
1971 assert(lds_size <= 65536);
1972 lds_size = align(lds_size, 512) / 512;
1973 } else {
1974 assert(lds_size <= 32768);
1975 lds_size = align(lds_size, 256) / 256;
1976 }
1977 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
1978
1979 tess.lds_size = lds_size;
1980
1981 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
1982 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
1983 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
1984 tess.num_patches = num_patches;
1985
1986 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
1987 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
1988
1989 switch (tes->info.tes.primitive_mode) {
1990 case GL_TRIANGLES:
1991 type = V_028B6C_TESS_TRIANGLE;
1992 break;
1993 case GL_QUADS:
1994 type = V_028B6C_TESS_QUAD;
1995 break;
1996 case GL_ISOLINES:
1997 type = V_028B6C_TESS_ISOLINE;
1998 break;
1999 }
2000
2001 switch (tes->info.tes.spacing) {
2002 case TESS_SPACING_EQUAL:
2003 partitioning = V_028B6C_PART_INTEGER;
2004 break;
2005 case TESS_SPACING_FRACTIONAL_ODD:
2006 partitioning = V_028B6C_PART_FRAC_ODD;
2007 break;
2008 case TESS_SPACING_FRACTIONAL_EVEN:
2009 partitioning = V_028B6C_PART_FRAC_EVEN;
2010 break;
2011 default:
2012 break;
2013 }
2014
2015 bool ccw = tes->info.tes.ccw;
2016 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_origin_state =
2017 vk_find_struct_const(pCreateInfo->pTessellationState,
2018 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
2019
2020 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT)
2021 ccw = !ccw;
2022
2023 if (tes->info.tes.point_mode)
2024 topology = V_028B6C_OUTPUT_POINT;
2025 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
2026 topology = V_028B6C_OUTPUT_LINE;
2027 else if (ccw)
2028 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2029 else
2030 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2031
2032 if (pipeline->device->physical_device->rad_info.has_distributed_tess) {
2033 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
2034 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
2035 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
2036 else
2037 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
2038 } else
2039 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
2040
2041 tess.tf_param = S_028B6C_TYPE(type) |
2042 S_028B6C_PARTITIONING(partitioning) |
2043 S_028B6C_TOPOLOGY(topology) |
2044 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
2045
2046 return tess;
2047 }
2048
2049 static const struct radv_prim_vertex_count prim_size_table[] = {
2050 [V_008958_DI_PT_NONE] = {0, 0},
2051 [V_008958_DI_PT_POINTLIST] = {1, 1},
2052 [V_008958_DI_PT_LINELIST] = {2, 2},
2053 [V_008958_DI_PT_LINESTRIP] = {2, 1},
2054 [V_008958_DI_PT_TRILIST] = {3, 3},
2055 [V_008958_DI_PT_TRIFAN] = {3, 1},
2056 [V_008958_DI_PT_TRISTRIP] = {3, 1},
2057 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
2058 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
2059 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
2060 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
2061 [V_008958_DI_PT_RECTLIST] = {3, 3},
2062 [V_008958_DI_PT_LINELOOP] = {2, 1},
2063 [V_008958_DI_PT_POLYGON] = {3, 1},
2064 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
2065 };
2066
2067 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
2068 {
2069 if (radv_pipeline_has_gs(pipeline))
2070 if (radv_pipeline_has_ngg(pipeline))
2071 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
2072 else
2073 return &pipeline->gs_copy_shader->info.vs.outinfo;
2074 else if (radv_pipeline_has_tess(pipeline))
2075 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
2076 else
2077 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
2078 }
2079
2080 static void
2081 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
2082 {
2083 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
2084 int shader_count = 0;
2085
2086 if(shaders[MESA_SHADER_FRAGMENT]) {
2087 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
2088 }
2089 if(shaders[MESA_SHADER_GEOMETRY]) {
2090 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
2091 }
2092 if(shaders[MESA_SHADER_TESS_EVAL]) {
2093 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
2094 }
2095 if(shaders[MESA_SHADER_TESS_CTRL]) {
2096 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
2097 }
2098 if(shaders[MESA_SHADER_VERTEX]) {
2099 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
2100 }
2101
2102 if (shader_count > 1) {
2103 unsigned first = ordered_shaders[shader_count - 1]->info.stage;
2104 unsigned last = ordered_shaders[0]->info.stage;
2105
2106 if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
2107 ordered_shaders[1]->info.has_transform_feedback_varyings)
2108 nir_link_xfb_varyings(ordered_shaders[1], ordered_shaders[0]);
2109
2110 for (int i = 0; i < shader_count; ++i) {
2111 nir_variable_mode mask = 0;
2112
2113 if (ordered_shaders[i]->info.stage != first)
2114 mask = mask | nir_var_shader_in;
2115
2116 if (ordered_shaders[i]->info.stage != last)
2117 mask = mask | nir_var_shader_out;
2118
2119 nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
2120 radv_optimize_nir(ordered_shaders[i], false, false);
2121 }
2122 }
2123
2124 for (int i = 1; i < shader_count; ++i) {
2125 nir_lower_io_arrays_to_elements(ordered_shaders[i],
2126 ordered_shaders[i - 1]);
2127
2128 if (nir_link_opt_varyings(ordered_shaders[i],
2129 ordered_shaders[i - 1]))
2130 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2131
2132 nir_remove_dead_variables(ordered_shaders[i],
2133 nir_var_shader_out, NULL);
2134 nir_remove_dead_variables(ordered_shaders[i - 1],
2135 nir_var_shader_in, NULL);
2136
2137 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
2138 ordered_shaders[i - 1]);
2139
2140 nir_compact_varyings(ordered_shaders[i],
2141 ordered_shaders[i - 1], true);
2142
2143 if (progress) {
2144 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
2145 ac_lower_indirect_derefs(ordered_shaders[i],
2146 pipeline->device->physical_device->rad_info.chip_class);
2147 }
2148 radv_optimize_nir(ordered_shaders[i], false, false);
2149
2150 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
2151 ac_lower_indirect_derefs(ordered_shaders[i - 1],
2152 pipeline->device->physical_device->rad_info.chip_class);
2153 }
2154 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2155 }
2156 }
2157 }
2158
2159 static void
2160 radv_set_linked_driver_locations(struct radv_pipeline *pipeline, nir_shader **shaders,
2161 struct radv_shader_info infos[MESA_SHADER_STAGES])
2162 {
2163 bool has_tess = shaders[MESA_SHADER_TESS_CTRL];
2164 bool has_gs = shaders[MESA_SHADER_GEOMETRY];
2165
2166 if (!has_tess && !has_gs)
2167 return;
2168
2169 unsigned vs_info_idx = MESA_SHADER_VERTEX;
2170 unsigned tes_info_idx = MESA_SHADER_TESS_EVAL;
2171
2172 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2173 /* These are merged into the next stage */
2174 vs_info_idx = has_tess ? MESA_SHADER_TESS_CTRL : MESA_SHADER_GEOMETRY;
2175 tes_info_idx = has_gs ? MESA_SHADER_GEOMETRY : MESA_SHADER_TESS_EVAL;
2176 }
2177
2178 if (has_tess) {
2179 nir_linked_io_var_info vs2tcs =
2180 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_VERTEX], shaders[MESA_SHADER_TESS_CTRL]);
2181 nir_linked_io_var_info tcs2tes =
2182 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_TESS_CTRL], shaders[MESA_SHADER_TESS_EVAL]);
2183
2184 infos[vs_info_idx].vs.num_linked_outputs = vs2tcs.num_linked_io_vars;
2185 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_inputs = vs2tcs.num_linked_io_vars;
2186 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_outputs = tcs2tes.num_linked_io_vars;
2187 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_patch_outputs = tcs2tes.num_linked_patch_io_vars;
2188 infos[tes_info_idx].tes.num_linked_inputs = tcs2tes.num_linked_io_vars;
2189 infos[tes_info_idx].tes.num_linked_patch_inputs = tcs2tes.num_linked_patch_io_vars;
2190
2191 if (has_gs) {
2192 nir_linked_io_var_info tes2gs =
2193 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_TESS_EVAL], shaders[MESA_SHADER_GEOMETRY]);
2194
2195 infos[tes_info_idx].tes.num_linked_outputs = tes2gs.num_linked_io_vars;
2196 infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = tes2gs.num_linked_io_vars;
2197 }
2198 } else if (has_gs) {
2199 nir_linked_io_var_info vs2gs =
2200 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_VERTEX], shaders[MESA_SHADER_GEOMETRY]);
2201
2202 infos[vs_info_idx].vs.num_linked_outputs = vs2gs.num_linked_io_vars;
2203 infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = vs2gs.num_linked_io_vars;
2204 }
2205 }
2206
2207 static uint32_t
2208 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo *input_state,
2209 uint32_t attrib_binding)
2210 {
2211 for (uint32_t i = 0; i < input_state->vertexBindingDescriptionCount; i++) {
2212 const VkVertexInputBindingDescription *input_binding =
2213 &input_state->pVertexBindingDescriptions[i];
2214
2215 if (input_binding->binding == attrib_binding)
2216 return input_binding->stride;
2217 }
2218
2219 return 0;
2220 }
2221
2222 static struct radv_pipeline_key
2223 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
2224 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2225 const struct radv_blend_state *blend,
2226 bool has_view_index)
2227 {
2228 const VkPipelineVertexInputStateCreateInfo *input_state =
2229 pCreateInfo->pVertexInputState;
2230 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
2231 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
2232
2233 struct radv_pipeline_key key;
2234 memset(&key, 0, sizeof(key));
2235
2236 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
2237 key.optimisations_disabled = 1;
2238
2239 key.has_multiview_view_index = has_view_index;
2240
2241 uint32_t binding_input_rate = 0;
2242 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
2243 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
2244 if (input_state->pVertexBindingDescriptions[i].inputRate) {
2245 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
2246 binding_input_rate |= 1u << binding;
2247 instance_rate_divisors[binding] = 1;
2248 }
2249 }
2250 if (divisor_state) {
2251 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
2252 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
2253 divisor_state->pVertexBindingDivisors[i].divisor;
2254 }
2255 }
2256
2257 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
2258 const VkVertexInputAttributeDescription *desc =
2259 &input_state->pVertexAttributeDescriptions[i];
2260 const struct vk_format_description *format_desc;
2261 unsigned location = desc->location;
2262 unsigned binding = desc->binding;
2263 unsigned num_format, data_format;
2264 int first_non_void;
2265
2266 if (binding_input_rate & (1u << binding)) {
2267 key.instance_rate_inputs |= 1u << location;
2268 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
2269 }
2270
2271 format_desc = vk_format_description(desc->format);
2272 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2273
2274 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2275 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2276
2277 key.vertex_attribute_formats[location] = data_format | (num_format << 4);
2278 key.vertex_attribute_bindings[location] = desc->binding;
2279 key.vertex_attribute_offsets[location] = desc->offset;
2280 key.vertex_attribute_strides[location] = radv_get_attrib_stride(input_state, desc->binding);
2281
2282 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8 &&
2283 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
2284 VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
2285 uint64_t adjust;
2286 switch(format) {
2287 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2288 case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
2289 adjust = RADV_ALPHA_ADJUST_SNORM;
2290 break;
2291 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2292 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
2293 adjust = RADV_ALPHA_ADJUST_SSCALED;
2294 break;
2295 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2296 case VK_FORMAT_A2B10G10R10_SINT_PACK32:
2297 adjust = RADV_ALPHA_ADJUST_SINT;
2298 break;
2299 default:
2300 adjust = 0;
2301 break;
2302 }
2303 key.vertex_alpha_adjust |= adjust << (2 * location);
2304 }
2305
2306 switch (desc->format) {
2307 case VK_FORMAT_B8G8R8A8_UNORM:
2308 case VK_FORMAT_B8G8R8A8_SNORM:
2309 case VK_FORMAT_B8G8R8A8_USCALED:
2310 case VK_FORMAT_B8G8R8A8_SSCALED:
2311 case VK_FORMAT_B8G8R8A8_UINT:
2312 case VK_FORMAT_B8G8R8A8_SINT:
2313 case VK_FORMAT_B8G8R8A8_SRGB:
2314 case VK_FORMAT_A2R10G10B10_UNORM_PACK32:
2315 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2316 case VK_FORMAT_A2R10G10B10_USCALED_PACK32:
2317 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2318 case VK_FORMAT_A2R10G10B10_UINT_PACK32:
2319 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2320 key.vertex_post_shuffle |= 1 << location;
2321 break;
2322 default:
2323 break;
2324 }
2325 }
2326
2327 const VkPipelineTessellationStateCreateInfo *tess =
2328 radv_pipeline_get_tessellation_state(pCreateInfo);
2329 if (tess)
2330 key.tess_input_vertices = tess->patchControlPoints;
2331
2332 const VkPipelineMultisampleStateCreateInfo *vkms =
2333 radv_pipeline_get_multisample_state(pCreateInfo);
2334 if (vkms && vkms->rasterizationSamples > 1) {
2335 uint32_t num_samples = vkms->rasterizationSamples;
2336 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
2337 key.num_samples = num_samples;
2338 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
2339 }
2340
2341 key.col_format = blend->spi_shader_col_format;
2342 if (pipeline->device->physical_device->rad_info.chip_class < GFX8)
2343 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
2344
2345 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10)
2346 key.topology = pCreateInfo->pInputAssemblyState->topology;
2347
2348 return key;
2349 }
2350
2351 static bool
2352 radv_nir_stage_uses_xfb(const nir_shader *nir)
2353 {
2354 nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
2355 bool uses_xfb = !!xfb;
2356
2357 ralloc_free(xfb);
2358 return uses_xfb;
2359 }
2360
2361 static void
2362 radv_fill_shader_keys(struct radv_device *device,
2363 struct radv_shader_variant_key *keys,
2364 const struct radv_pipeline_key *key,
2365 nir_shader **nir)
2366 {
2367 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
2368 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
2369 keys[MESA_SHADER_VERTEX].vs.post_shuffle = key->vertex_post_shuffle;
2370 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) {
2371 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
2372 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_formats[i] = key->vertex_attribute_formats[i];
2373 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_bindings[i] = key->vertex_attribute_bindings[i];
2374 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i];
2375 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i];
2376 }
2377 keys[MESA_SHADER_VERTEX].vs.outprim = si_conv_prim_to_gs_out(key->topology);
2378
2379 if (nir[MESA_SHADER_TESS_CTRL]) {
2380 keys[MESA_SHADER_VERTEX].vs_common_out.as_ls = true;
2381 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
2382 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
2383 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
2384
2385 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
2386 }
2387
2388 if (nir[MESA_SHADER_GEOMETRY]) {
2389 if (nir[MESA_SHADER_TESS_CTRL])
2390 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_es = true;
2391 else
2392 keys[MESA_SHADER_VERTEX].vs_common_out.as_es = true;
2393 }
2394
2395 if (device->physical_device->use_ngg) {
2396 if (nir[MESA_SHADER_TESS_CTRL]) {
2397 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = true;
2398 } else {
2399 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = true;
2400 }
2401
2402 if (nir[MESA_SHADER_TESS_CTRL] &&
2403 nir[MESA_SHADER_GEOMETRY] &&
2404 nir[MESA_SHADER_GEOMETRY]->info.gs.invocations *
2405 nir[MESA_SHADER_GEOMETRY]->info.gs.vertices_out > 256) {
2406 /* Fallback to the legacy path if tessellation is
2407 * enabled with extreme geometry because
2408 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2409 * might hang.
2410 */
2411 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2412 }
2413
2414 if (!device->physical_device->use_ngg_gs) {
2415 if (nir[MESA_SHADER_GEOMETRY]) {
2416 if (nir[MESA_SHADER_TESS_CTRL])
2417 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2418 else
2419 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2420 }
2421 }
2422
2423 gl_shader_stage last_xfb_stage = MESA_SHADER_VERTEX;
2424
2425 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
2426 if (nir[i])
2427 last_xfb_stage = i;
2428 }
2429
2430 bool uses_xfb = nir[last_xfb_stage] &&
2431 radv_nir_stage_uses_xfb(nir[last_xfb_stage]);
2432
2433 if (!device->physical_device->use_ngg_streamout && uses_xfb) {
2434 if (nir[MESA_SHADER_TESS_CTRL])
2435 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2436 else
2437 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2438 }
2439
2440 /* Determine if the pipeline is eligible for the NGG passthrough
2441 * mode. It can't be enabled for geometry shaders, for NGG
2442 * streamout or for vertex shaders that export the primitive ID
2443 * (this is checked later because we don't have the info here.)
2444 */
2445 if (!nir[MESA_SHADER_GEOMETRY] && !uses_xfb) {
2446 if (nir[MESA_SHADER_TESS_CTRL] &&
2447 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg) {
2448 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg_passthrough = true;
2449 } else if (nir[MESA_SHADER_VERTEX] &&
2450 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) {
2451 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = true;
2452 }
2453 }
2454 }
2455
2456 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
2457 keys[i].has_multiview_view_index = key->has_multiview_view_index;
2458
2459 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
2460 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
2461 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
2462 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
2463 keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples;
2464
2465 if (nir[MESA_SHADER_COMPUTE]) {
2466 keys[MESA_SHADER_COMPUTE].cs.subgroup_size = key->compute_subgroup_size;
2467 }
2468 }
2469
2470 static uint8_t
2471 radv_get_wave_size(struct radv_device *device,
2472 const VkPipelineShaderStageCreateInfo *pStage,
2473 gl_shader_stage stage,
2474 const struct radv_shader_variant_key *key)
2475 {
2476 if (stage == MESA_SHADER_GEOMETRY && !key->vs_common_out.as_ngg)
2477 return 64;
2478 else if (stage == MESA_SHADER_COMPUTE) {
2479 if (key->cs.subgroup_size) {
2480 /* Return the required subgroup size if specified. */
2481 return key->cs.subgroup_size;
2482 }
2483 return device->physical_device->cs_wave_size;
2484 }
2485 else if (stage == MESA_SHADER_FRAGMENT)
2486 return device->physical_device->ps_wave_size;
2487 else
2488 return device->physical_device->ge_wave_size;
2489 }
2490
2491 static uint8_t
2492 radv_get_ballot_bit_size(struct radv_device *device,
2493 const VkPipelineShaderStageCreateInfo *pStage,
2494 gl_shader_stage stage,
2495 const struct radv_shader_variant_key *key)
2496 {
2497 if (stage == MESA_SHADER_COMPUTE && key->cs.subgroup_size)
2498 return key->cs.subgroup_size;
2499 return 64;
2500 }
2501
2502 static void
2503 radv_fill_shader_info(struct radv_pipeline *pipeline,
2504 const VkPipelineShaderStageCreateInfo **pStages,
2505 struct radv_shader_variant_key *keys,
2506 struct radv_shader_info *infos,
2507 nir_shader **nir)
2508 {
2509 unsigned active_stages = 0;
2510 unsigned filled_stages = 0;
2511
2512 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2513 if (nir[i])
2514 active_stages |= (1 << i);
2515 }
2516
2517 if (nir[MESA_SHADER_FRAGMENT]) {
2518 radv_nir_shader_info_init(&infos[MESA_SHADER_FRAGMENT]);
2519 radv_nir_shader_info_pass(nir[MESA_SHADER_FRAGMENT],
2520 pipeline->layout,
2521 &keys[MESA_SHADER_FRAGMENT],
2522 &infos[MESA_SHADER_FRAGMENT],
2523 pipeline->device->physical_device->use_aco);
2524
2525 /* TODO: These are no longer used as keys we should refactor this */
2526 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2527 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2528 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2529 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2530 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2531 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2532 keys[MESA_SHADER_VERTEX].vs_common_out.export_viewport_index =
2533 infos[MESA_SHADER_FRAGMENT].ps.viewport_index_input;
2534 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2535 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2536 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2537 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2538 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2539 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2540 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_viewport_index =
2541 infos[MESA_SHADER_FRAGMENT].ps.viewport_index_input;
2542
2543 /* NGG passthrough mode can't be enabled for vertex shaders
2544 * that export the primitive ID.
2545 *
2546 * TODO: I should really refactor the keys logic.
2547 */
2548 if (nir[MESA_SHADER_VERTEX] &&
2549 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id) {
2550 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = false;
2551 }
2552
2553 filled_stages |= (1 << MESA_SHADER_FRAGMENT);
2554 }
2555
2556 if (nir[MESA_SHADER_TESS_CTRL]) {
2557 infos[MESA_SHADER_TESS_CTRL].tcs.tes_inputs_read =
2558 nir[MESA_SHADER_TESS_EVAL]->info.inputs_read;
2559 infos[MESA_SHADER_TESS_CTRL].tcs.tes_patch_inputs_read =
2560 nir[MESA_SHADER_TESS_EVAL]->info.patch_inputs_read;
2561 }
2562
2563 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2564 nir[MESA_SHADER_TESS_CTRL]) {
2565 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2566 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2567 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2568
2569 radv_nir_shader_info_init(&infos[MESA_SHADER_TESS_CTRL]);
2570
2571 for (int i = 0; i < 2; i++) {
2572 radv_nir_shader_info_pass(combined_nir[i],
2573 pipeline->layout, &key,
2574 &infos[MESA_SHADER_TESS_CTRL],
2575 pipeline->device->physical_device->use_aco);
2576 }
2577
2578 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2579 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2580 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2581 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2582
2583 filled_stages |= (1 << MESA_SHADER_VERTEX);
2584 filled_stages |= (1 << MESA_SHADER_TESS_CTRL);
2585 }
2586
2587 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2588 nir[MESA_SHADER_GEOMETRY]) {
2589 gl_shader_stage pre_stage = nir[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2590 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2591
2592 radv_nir_shader_info_init(&infos[MESA_SHADER_GEOMETRY]);
2593
2594 for (int i = 0; i < 2; i++) {
2595 radv_nir_shader_info_pass(combined_nir[i],
2596 pipeline->layout,
2597 &keys[pre_stage],
2598 &infos[MESA_SHADER_GEOMETRY],
2599 pipeline->device->physical_device->use_aco);
2600 }
2601
2602 filled_stages |= (1 << pre_stage);
2603 filled_stages |= (1 << MESA_SHADER_GEOMETRY);
2604 }
2605
2606 active_stages ^= filled_stages;
2607 while (active_stages) {
2608 int i = u_bit_scan(&active_stages);
2609
2610 if (i == MESA_SHADER_TESS_CTRL) {
2611 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs =
2612 util_last_bit64(infos[MESA_SHADER_VERTEX].vs.ls_outputs_written);
2613 }
2614
2615 if (i == MESA_SHADER_TESS_EVAL) {
2616 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2617 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2618 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2619 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2620 }
2621
2622 radv_nir_shader_info_init(&infos[i]);
2623 radv_nir_shader_info_pass(nir[i], pipeline->layout,
2624 &keys[i], &infos[i], pipeline->device->physical_device->use_aco);
2625 }
2626
2627 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2628 if (nir[i]) {
2629 infos[i].wave_size =
2630 radv_get_wave_size(pipeline->device, pStages[i],
2631 i, &keys[i]);
2632 infos[i].ballot_bit_size =
2633 radv_get_ballot_bit_size(pipeline->device,
2634 pStages[i], i,
2635 &keys[i]);
2636 }
2637 }
2638 }
2639
2640 static void
2641 merge_tess_info(struct shader_info *tes_info,
2642 const struct shader_info *tcs_info)
2643 {
2644 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2645 *
2646 * "PointMode. Controls generation of points rather than triangles
2647 * or lines. This functionality defaults to disabled, and is
2648 * enabled if either shader stage includes the execution mode.
2649 *
2650 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2651 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2652 * and OutputVertices, it says:
2653 *
2654 * "One mode must be set in at least one of the tessellation
2655 * shader stages."
2656 *
2657 * So, the fields can be set in either the TCS or TES, but they must
2658 * agree if set in both. Our backend looks at TES, so bitwise-or in
2659 * the values from the TCS.
2660 */
2661 assert(tcs_info->tess.tcs_vertices_out == 0 ||
2662 tes_info->tess.tcs_vertices_out == 0 ||
2663 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
2664 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
2665
2666 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2667 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2668 tcs_info->tess.spacing == tes_info->tess.spacing);
2669 tes_info->tess.spacing |= tcs_info->tess.spacing;
2670
2671 assert(tcs_info->tess.primitive_mode == 0 ||
2672 tes_info->tess.primitive_mode == 0 ||
2673 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
2674 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
2675 tes_info->tess.ccw |= tcs_info->tess.ccw;
2676 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
2677 }
2678
2679 static
2680 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT *ext)
2681 {
2682 if (!ext)
2683 return;
2684
2685 if (ext->pPipelineCreationFeedback) {
2686 ext->pPipelineCreationFeedback->flags = 0;
2687 ext->pPipelineCreationFeedback->duration = 0;
2688 }
2689
2690 for (unsigned i = 0; i < ext->pipelineStageCreationFeedbackCount; ++i) {
2691 ext->pPipelineStageCreationFeedbacks[i].flags = 0;
2692 ext->pPipelineStageCreationFeedbacks[i].duration = 0;
2693 }
2694 }
2695
2696 static
2697 void radv_start_feedback(VkPipelineCreationFeedbackEXT *feedback)
2698 {
2699 if (!feedback)
2700 return;
2701
2702 feedback->duration -= radv_get_current_time();
2703 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT;
2704 }
2705
2706 static
2707 void radv_stop_feedback(VkPipelineCreationFeedbackEXT *feedback, bool cache_hit)
2708 {
2709 if (!feedback)
2710 return;
2711
2712 feedback->duration += radv_get_current_time();
2713 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT |
2714 (cache_hit ? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT : 0);
2715 }
2716
2717 VkResult radv_create_shaders(struct radv_pipeline *pipeline,
2718 struct radv_device *device,
2719 struct radv_pipeline_cache *cache,
2720 const struct radv_pipeline_key *key,
2721 const VkPipelineShaderStageCreateInfo **pStages,
2722 const VkPipelineCreateFlags flags,
2723 VkPipelineCreationFeedbackEXT *pipeline_feedback,
2724 VkPipelineCreationFeedbackEXT **stage_feedbacks)
2725 {
2726 struct radv_shader_module fs_m = {0};
2727 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2728 nir_shader *nir[MESA_SHADER_STAGES] = {0};
2729 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2730 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{{0}}}}};
2731 struct radv_shader_info infos[MESA_SHADER_STAGES] = {0};
2732 unsigned char hash[20], gs_copy_hash[20];
2733 bool keep_executable_info = (flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR) || device->keep_shader_info;
2734 bool keep_statistic_info = (flags & VK_PIPELINE_CREATE_CAPTURE_STATISTICS_BIT_KHR) ||
2735 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) ||
2736 device->keep_shader_info;
2737
2738 radv_start_feedback(pipeline_feedback);
2739
2740 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2741 if (pStages[i]) {
2742 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
2743 if (modules[i]->nir)
2744 _mesa_sha1_compute(modules[i]->nir->info.name,
2745 strlen(modules[i]->nir->info.name),
2746 modules[i]->sha1);
2747
2748 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
2749 }
2750 }
2751
2752 radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device));
2753 memcpy(gs_copy_hash, hash, 20);
2754 gs_copy_hash[0] ^= 1;
2755
2756 bool found_in_application_cache = true;
2757 if (modules[MESA_SHADER_GEOMETRY] && !keep_executable_info && !keep_statistic_info) {
2758 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2759 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants,
2760 &found_in_application_cache);
2761 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
2762 }
2763
2764 if (!keep_executable_info && !keep_statistic_info &&
2765 radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders,
2766 &found_in_application_cache) &&
2767 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
2768 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2769 return VK_SUCCESS;
2770 }
2771
2772 if (flags & VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_EXT) {
2773 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2774 return VK_PIPELINE_COMPILE_REQUIRED_EXT;
2775 }
2776
2777 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
2778 nir_builder fs_b;
2779 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2780 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2781 fs_m.nir = fs_b.shader;
2782 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2783 }
2784
2785 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2786 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
2787 unsigned subgroup_size = 64, ballot_bit_size = 64;
2788
2789 if (!modules[i])
2790 continue;
2791
2792 radv_start_feedback(stage_feedbacks[i]);
2793
2794 if (key->compute_subgroup_size) {
2795 /* Only compute shaders currently support requiring a
2796 * specific subgroup size.
2797 */
2798 assert(i == MESA_SHADER_COMPUTE);
2799 subgroup_size = key->compute_subgroup_size;
2800 ballot_bit_size = key->compute_subgroup_size;
2801 }
2802
2803 nir[i] = radv_shader_compile_to_nir(device, modules[i],
2804 stage ? stage->pName : "main", i,
2805 stage ? stage->pSpecializationInfo : NULL,
2806 flags, pipeline->layout,
2807 subgroup_size, ballot_bit_size);
2808
2809 /* We don't want to alter meta shaders IR directly so clone it
2810 * first.
2811 */
2812 if (nir[i]->info.name) {
2813 nir[i] = nir_shader_clone(NULL, nir[i]);
2814 }
2815
2816 radv_stop_feedback(stage_feedbacks[i], false);
2817 }
2818
2819 if (nir[MESA_SHADER_TESS_CTRL]) {
2820 nir_lower_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
2821 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
2822 }
2823
2824 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
2825 radv_link_shaders(pipeline, nir);
2826
2827 radv_set_linked_driver_locations(pipeline, nir, infos);
2828
2829 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2830 if (nir[i]) {
2831 /* do this again since information such as outputs_read can be out-of-date */
2832 nir_shader_gather_info(nir[i], nir_shader_get_entrypoint(nir[i]));
2833
2834 if (device->physical_device->use_aco) {
2835 NIR_PASS_V(nir[i], nir_lower_non_uniform_access,
2836 nir_lower_non_uniform_ubo_access |
2837 nir_lower_non_uniform_ssbo_access |
2838 nir_lower_non_uniform_texture_access |
2839 nir_lower_non_uniform_image_access);
2840 } else
2841 NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
2842 }
2843 }
2844
2845 if (nir[MESA_SHADER_FRAGMENT])
2846 radv_lower_fs_io(nir[MESA_SHADER_FRAGMENT]);
2847
2848 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2849 if (radv_can_dump_shader(device, modules[i], false))
2850 nir_print_shader(nir[i], stderr);
2851 }
2852
2853 radv_fill_shader_keys(device, keys, key, nir);
2854
2855 radv_fill_shader_info(pipeline, pStages, keys, infos, nir);
2856
2857 if ((nir[MESA_SHADER_VERTEX] &&
2858 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) ||
2859 (nir[MESA_SHADER_TESS_EVAL] &&
2860 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg)) {
2861 struct gfx10_ngg_info *ngg_info;
2862
2863 if (nir[MESA_SHADER_GEOMETRY])
2864 ngg_info = &infos[MESA_SHADER_GEOMETRY].ngg_info;
2865 else if (nir[MESA_SHADER_TESS_CTRL])
2866 ngg_info = &infos[MESA_SHADER_TESS_EVAL].ngg_info;
2867 else
2868 ngg_info = &infos[MESA_SHADER_VERTEX].ngg_info;
2869
2870 gfx10_get_ngg_info(key, pipeline, nir, infos, ngg_info);
2871 } else if (nir[MESA_SHADER_GEOMETRY]) {
2872 struct gfx9_gs_info *gs_info =
2873 &infos[MESA_SHADER_GEOMETRY].gs_ring_info;
2874
2875 gfx9_get_gs_info(key, pipeline, nir, infos, gs_info);
2876 }
2877
2878 if(modules[MESA_SHADER_GEOMETRY]) {
2879 struct radv_shader_binary *gs_copy_binary = NULL;
2880 if (!pipeline->gs_copy_shader &&
2881 !radv_pipeline_has_ngg(pipeline)) {
2882 struct radv_shader_info info = {};
2883 struct radv_shader_variant_key key = {};
2884
2885 key.has_multiview_view_index =
2886 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index;
2887
2888 radv_nir_shader_info_pass(nir[MESA_SHADER_GEOMETRY],
2889 pipeline->layout, &key,
2890 &info, pipeline->device->physical_device->use_aco);
2891 info.wave_size = 64; /* Wave32 not supported. */
2892 info.ballot_bit_size = 64;
2893
2894 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2895 device, nir[MESA_SHADER_GEOMETRY], &info,
2896 &gs_copy_binary, keep_executable_info, keep_statistic_info,
2897 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2898 }
2899
2900 if (!keep_executable_info && !keep_statistic_info && pipeline->gs_copy_shader) {
2901 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2902 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2903
2904 binaries[MESA_SHADER_GEOMETRY] = gs_copy_binary;
2905 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2906
2907 radv_pipeline_cache_insert_shaders(device, cache,
2908 gs_copy_hash,
2909 variants,
2910 binaries);
2911 }
2912 free(gs_copy_binary);
2913 }
2914
2915 if (nir[MESA_SHADER_FRAGMENT]) {
2916 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
2917 radv_start_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT]);
2918
2919 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2920 radv_shader_variant_compile(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
2921 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
2922 infos + MESA_SHADER_FRAGMENT,
2923 keep_executable_info, keep_statistic_info,
2924 &binaries[MESA_SHADER_FRAGMENT]);
2925
2926 radv_stop_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT], false);
2927 }
2928 }
2929
2930 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
2931 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
2932 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2933 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2934 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2935
2936 radv_start_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL]);
2937
2938 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
2939 pipeline->layout,
2940 &key, &infos[MESA_SHADER_TESS_CTRL], keep_executable_info,
2941 keep_statistic_info, &binaries[MESA_SHADER_TESS_CTRL]);
2942
2943 radv_stop_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL], false);
2944 }
2945 modules[MESA_SHADER_VERTEX] = NULL;
2946 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2947 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2948 }
2949
2950 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
2951 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2952 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
2953 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2954
2955 radv_start_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY]);
2956
2957 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2958 pipeline->layout,
2959 &keys[pre_stage], &infos[MESA_SHADER_GEOMETRY], keep_executable_info,
2960 keep_statistic_info, &binaries[MESA_SHADER_GEOMETRY]);
2961
2962 radv_stop_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY], false);
2963 }
2964 modules[pre_stage] = NULL;
2965 }
2966
2967 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2968 if(modules[i] && !pipeline->shaders[i]) {
2969 if (i == MESA_SHADER_TESS_CTRL) {
2970 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.ls_outputs_written);
2971 }
2972 if (i == MESA_SHADER_TESS_EVAL) {
2973 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2974 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2975 }
2976
2977 radv_start_feedback(stage_feedbacks[i]);
2978
2979 pipeline->shaders[i] = radv_shader_variant_compile(device, modules[i], &nir[i], 1,
2980 pipeline->layout,
2981 keys + i, infos + i, keep_executable_info,
2982 keep_statistic_info, &binaries[i]);
2983
2984 radv_stop_feedback(stage_feedbacks[i], false);
2985 }
2986 }
2987
2988 if (!keep_executable_info && !keep_statistic_info) {
2989 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
2990 binaries);
2991 }
2992
2993 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2994 free(binaries[i]);
2995 if (nir[i]) {
2996 ralloc_free(nir[i]);
2997
2998 if (radv_can_dump_shader_stats(device, modules[i]))
2999 radv_shader_dump_stats(device,
3000 pipeline->shaders[i],
3001 i, stderr);
3002 }
3003 }
3004
3005 if (fs_m.nir)
3006 ralloc_free(fs_m.nir);
3007
3008 radv_stop_feedback(pipeline_feedback, false);
3009 return VK_SUCCESS;
3010 }
3011
3012 static uint32_t
3013 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
3014 gl_shader_stage stage, enum chip_class chip_class)
3015 {
3016 bool has_gs = radv_pipeline_has_gs(pipeline);
3017 bool has_tess = radv_pipeline_has_tess(pipeline);
3018 bool has_ngg = radv_pipeline_has_ngg(pipeline);
3019
3020 switch (stage) {
3021 case MESA_SHADER_FRAGMENT:
3022 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
3023 case MESA_SHADER_VERTEX:
3024 if (has_tess) {
3025 if (chip_class >= GFX10) {
3026 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
3027 } else if (chip_class == GFX9) {
3028 return R_00B430_SPI_SHADER_USER_DATA_LS_0;
3029 } else {
3030 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
3031 }
3032
3033 }
3034
3035 if (has_gs) {
3036 if (chip_class >= GFX10) {
3037 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3038 } else {
3039 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
3040 }
3041 }
3042
3043 if (has_ngg)
3044 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3045
3046 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
3047 case MESA_SHADER_GEOMETRY:
3048 return chip_class == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
3049 R_00B230_SPI_SHADER_USER_DATA_GS_0;
3050 case MESA_SHADER_COMPUTE:
3051 return R_00B900_COMPUTE_USER_DATA_0;
3052 case MESA_SHADER_TESS_CTRL:
3053 return chip_class == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
3054 R_00B430_SPI_SHADER_USER_DATA_HS_0;
3055 case MESA_SHADER_TESS_EVAL:
3056 if (has_gs) {
3057 return chip_class >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0 :
3058 R_00B330_SPI_SHADER_USER_DATA_ES_0;
3059 } else if (has_ngg) {
3060 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3061 } else {
3062 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
3063 }
3064 default:
3065 unreachable("unknown shader");
3066 }
3067 }
3068
3069 struct radv_bin_size_entry {
3070 unsigned bpp;
3071 VkExtent2D extent;
3072 };
3073
3074 static VkExtent2D
3075 radv_gfx9_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3076 {
3077 static const struct radv_bin_size_entry color_size_table[][3][9] = {
3078 {
3079 /* One RB / SE */
3080 {
3081 /* One shader engine */
3082 { 0, {128, 128}},
3083 { 1, { 64, 128}},
3084 { 2, { 32, 128}},
3085 { 3, { 16, 128}},
3086 { 17, { 0, 0}},
3087 { UINT_MAX, { 0, 0}},
3088 },
3089 {
3090 /* Two shader engines */
3091 { 0, {128, 128}},
3092 { 2, { 64, 128}},
3093 { 3, { 32, 128}},
3094 { 5, { 16, 128}},
3095 { 17, { 0, 0}},
3096 { UINT_MAX, { 0, 0}},
3097 },
3098 {
3099 /* Four shader engines */
3100 { 0, {128, 128}},
3101 { 3, { 64, 128}},
3102 { 5, { 16, 128}},
3103 { 17, { 0, 0}},
3104 { UINT_MAX, { 0, 0}},
3105 },
3106 },
3107 {
3108 /* Two RB / SE */
3109 {
3110 /* One shader engine */
3111 { 0, {128, 128}},
3112 { 2, { 64, 128}},
3113 { 3, { 32, 128}},
3114 { 5, { 16, 128}},
3115 { 33, { 0, 0}},
3116 { UINT_MAX, { 0, 0}},
3117 },
3118 {
3119 /* Two shader engines */
3120 { 0, {128, 128}},
3121 { 3, { 64, 128}},
3122 { 5, { 32, 128}},
3123 { 9, { 16, 128}},
3124 { 33, { 0, 0}},
3125 { UINT_MAX, { 0, 0}},
3126 },
3127 {
3128 /* Four shader engines */
3129 { 0, {256, 256}},
3130 { 2, {128, 256}},
3131 { 3, {128, 128}},
3132 { 5, { 64, 128}},
3133 { 9, { 16, 128}},
3134 { 33, { 0, 0}},
3135 { UINT_MAX, { 0, 0}},
3136 },
3137 },
3138 {
3139 /* Four RB / SE */
3140 {
3141 /* One shader engine */
3142 { 0, {128, 256}},
3143 { 2, {128, 128}},
3144 { 3, { 64, 128}},
3145 { 5, { 32, 128}},
3146 { 9, { 16, 128}},
3147 { 33, { 0, 0}},
3148 { UINT_MAX, { 0, 0}},
3149 },
3150 {
3151 /* Two shader engines */
3152 { 0, {256, 256}},
3153 { 2, {128, 256}},
3154 { 3, {128, 128}},
3155 { 5, { 64, 128}},
3156 { 9, { 32, 128}},
3157 { 17, { 16, 128}},
3158 { 33, { 0, 0}},
3159 { UINT_MAX, { 0, 0}},
3160 },
3161 {
3162 /* Four shader engines */
3163 { 0, {256, 512}},
3164 { 2, {256, 256}},
3165 { 3, {128, 256}},
3166 { 5, {128, 128}},
3167 { 9, { 64, 128}},
3168 { 17, { 16, 128}},
3169 { 33, { 0, 0}},
3170 { UINT_MAX, { 0, 0}},
3171 },
3172 },
3173 };
3174 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
3175 {
3176 // One RB / SE
3177 {
3178 // One shader engine
3179 { 0, {128, 256}},
3180 { 2, {128, 128}},
3181 { 4, { 64, 128}},
3182 { 7, { 32, 128}},
3183 { 13, { 16, 128}},
3184 { 49, { 0, 0}},
3185 { UINT_MAX, { 0, 0}},
3186 },
3187 {
3188 // Two shader engines
3189 { 0, {256, 256}},
3190 { 2, {128, 256}},
3191 { 4, {128, 128}},
3192 { 7, { 64, 128}},
3193 { 13, { 32, 128}},
3194 { 25, { 16, 128}},
3195 { 49, { 0, 0}},
3196 { UINT_MAX, { 0, 0}},
3197 },
3198 {
3199 // Four shader engines
3200 { 0, {256, 512}},
3201 { 2, {256, 256}},
3202 { 4, {128, 256}},
3203 { 7, {128, 128}},
3204 { 13, { 64, 128}},
3205 { 25, { 16, 128}},
3206 { 49, { 0, 0}},
3207 { UINT_MAX, { 0, 0}},
3208 },
3209 },
3210 {
3211 // Two RB / SE
3212 {
3213 // One shader engine
3214 { 0, {256, 256}},
3215 { 2, {128, 256}},
3216 { 4, {128, 128}},
3217 { 7, { 64, 128}},
3218 { 13, { 32, 128}},
3219 { 25, { 16, 128}},
3220 { 97, { 0, 0}},
3221 { UINT_MAX, { 0, 0}},
3222 },
3223 {
3224 // Two shader engines
3225 { 0, {256, 512}},
3226 { 2, {256, 256}},
3227 { 4, {128, 256}},
3228 { 7, {128, 128}},
3229 { 13, { 64, 128}},
3230 { 25, { 32, 128}},
3231 { 49, { 16, 128}},
3232 { 97, { 0, 0}},
3233 { UINT_MAX, { 0, 0}},
3234 },
3235 {
3236 // Four shader engines
3237 { 0, {512, 512}},
3238 { 2, {256, 512}},
3239 { 4, {256, 256}},
3240 { 7, {128, 256}},
3241 { 13, {128, 128}},
3242 { 25, { 64, 128}},
3243 { 49, { 16, 128}},
3244 { 97, { 0, 0}},
3245 { UINT_MAX, { 0, 0}},
3246 },
3247 },
3248 {
3249 // Four RB / SE
3250 {
3251 // One shader engine
3252 { 0, {256, 512}},
3253 { 2, {256, 256}},
3254 { 4, {128, 256}},
3255 { 7, {128, 128}},
3256 { 13, { 64, 128}},
3257 { 25, { 32, 128}},
3258 { 49, { 16, 128}},
3259 { UINT_MAX, { 0, 0}},
3260 },
3261 {
3262 // Two shader engines
3263 { 0, {512, 512}},
3264 { 2, {256, 512}},
3265 { 4, {256, 256}},
3266 { 7, {128, 256}},
3267 { 13, {128, 128}},
3268 { 25, { 64, 128}},
3269 { 49, { 32, 128}},
3270 { 97, { 16, 128}},
3271 { UINT_MAX, { 0, 0}},
3272 },
3273 {
3274 // Four shader engines
3275 { 0, {512, 512}},
3276 { 4, {256, 512}},
3277 { 7, {256, 256}},
3278 { 13, {128, 256}},
3279 { 25, {128, 128}},
3280 { 49, { 64, 128}},
3281 { 97, { 16, 128}},
3282 { UINT_MAX, { 0, 0}},
3283 },
3284 },
3285 };
3286
3287 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3288 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3289 VkExtent2D extent = {512, 512};
3290
3291 unsigned log_num_rb_per_se =
3292 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
3293 pipeline->device->physical_device->rad_info.max_se);
3294 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
3295
3296 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3297 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
3298 unsigned effective_samples = total_samples;
3299 unsigned color_bytes_per_pixel = 0;
3300
3301 const VkPipelineColorBlendStateCreateInfo *vkblend =
3302 radv_pipeline_get_color_blend_state(pCreateInfo);
3303 if (vkblend) {
3304 for (unsigned i = 0; i < subpass->color_count; i++) {
3305 if (!vkblend->pAttachments[i].colorWriteMask)
3306 continue;
3307
3308 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3309 continue;
3310
3311 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3312 color_bytes_per_pixel += vk_format_get_blocksize(format);
3313 }
3314
3315 /* MSAA images typically don't use all samples all the time. */
3316 if (effective_samples >= 2 && ps_iter_samples <= 1)
3317 effective_samples = 2;
3318 color_bytes_per_pixel *= effective_samples;
3319 }
3320
3321 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
3322 while(color_entry[1].bpp <= color_bytes_per_pixel)
3323 ++color_entry;
3324
3325 extent = color_entry->extent;
3326
3327 if (subpass->depth_stencil_attachment) {
3328 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3329
3330 /* Coefficients taken from AMDVLK */
3331 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3332 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3333 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
3334
3335 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
3336 while(ds_entry[1].bpp <= ds_bytes_per_pixel)
3337 ++ds_entry;
3338
3339 if (ds_entry->extent.width * ds_entry->extent.height < extent.width * extent.height)
3340 extent = ds_entry->extent;
3341 }
3342
3343 return extent;
3344 }
3345
3346 static VkExtent2D
3347 radv_gfx10_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3348 {
3349 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3350 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3351 VkExtent2D extent = {512, 512};
3352
3353 const unsigned db_tag_size = 64;
3354 const unsigned db_tag_count = 312;
3355 const unsigned color_tag_size = 1024;
3356 const unsigned color_tag_count = 31;
3357 const unsigned fmask_tag_size = 256;
3358 const unsigned fmask_tag_count = 44;
3359
3360 const unsigned rb_count = pipeline->device->physical_device->rad_info.num_render_backends;
3361 const unsigned pipe_count = MAX2(rb_count, pipeline->device->physical_device->rad_info.num_sdp_interfaces);
3362
3363 const unsigned db_tag_part = (db_tag_count * rb_count / pipe_count) * db_tag_size * pipe_count;
3364 const unsigned color_tag_part = (color_tag_count * rb_count / pipe_count) * color_tag_size * pipe_count;
3365 const unsigned fmask_tag_part = (fmask_tag_count * rb_count / pipe_count) * fmask_tag_size * pipe_count;
3366
3367 const unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3368 const unsigned samples_log = util_logbase2_ceil(total_samples);
3369
3370 unsigned color_bytes_per_pixel = 0;
3371 unsigned fmask_bytes_per_pixel = 0;
3372
3373 const VkPipelineColorBlendStateCreateInfo *vkblend =
3374 radv_pipeline_get_color_blend_state(pCreateInfo);
3375 if (vkblend) {
3376 for (unsigned i = 0; i < subpass->color_count; i++) {
3377 if (!vkblend->pAttachments[i].colorWriteMask)
3378 continue;
3379
3380 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3381 continue;
3382
3383 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3384 color_bytes_per_pixel += vk_format_get_blocksize(format);
3385
3386 if (total_samples > 1) {
3387 assert(samples_log <= 3);
3388 const unsigned fmask_array[] = {0, 1, 1, 4};
3389 fmask_bytes_per_pixel += fmask_array[samples_log];
3390 }
3391 }
3392
3393 color_bytes_per_pixel *= total_samples;
3394 }
3395 color_bytes_per_pixel = MAX2(color_bytes_per_pixel, 1);
3396
3397 const unsigned color_pixel_count_log = util_logbase2(color_tag_part / color_bytes_per_pixel);
3398 extent.width = 1ull << ((color_pixel_count_log + 1) / 2);
3399 extent.height = 1ull << (color_pixel_count_log / 2);
3400
3401 if (fmask_bytes_per_pixel) {
3402 const unsigned fmask_pixel_count_log = util_logbase2(fmask_tag_part / fmask_bytes_per_pixel);
3403
3404 const VkExtent2D fmask_extent = (VkExtent2D){
3405 .width = 1ull << ((fmask_pixel_count_log + 1) / 2),
3406 .height = 1ull << (color_pixel_count_log / 2)
3407 };
3408
3409 if (fmask_extent.width * fmask_extent.height < extent.width * extent.height)
3410 extent = fmask_extent;
3411 }
3412
3413 if (subpass->depth_stencil_attachment) {
3414 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3415
3416 /* Coefficients taken from AMDVLK */
3417 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3418 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3419 unsigned db_bytes_per_pixel = (depth_coeff + stencil_coeff) * total_samples;
3420
3421 const unsigned db_pixel_count_log = util_logbase2(db_tag_part / db_bytes_per_pixel);
3422
3423 const VkExtent2D db_extent = (VkExtent2D){
3424 .width = 1ull << ((db_pixel_count_log + 1) / 2),
3425 .height = 1ull << (color_pixel_count_log / 2)
3426 };
3427
3428 if (db_extent.width * db_extent.height < extent.width * extent.height)
3429 extent = db_extent;
3430 }
3431
3432 extent.width = MAX2(extent.width, 128);
3433 extent.height = MAX2(extent.width, 64);
3434
3435 return extent;
3436 }
3437
3438 static void
3439 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf *ctx_cs,
3440 struct radv_pipeline *pipeline,
3441 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3442 {
3443 uint32_t pa_sc_binner_cntl_0 =
3444 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
3445 S_028C44_DISABLE_START_OF_PRIM(1);
3446 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3447
3448 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3449 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3450 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3451 const VkPipelineColorBlendStateCreateInfo *vkblend =
3452 radv_pipeline_get_color_blend_state(pCreateInfo);
3453 unsigned min_bytes_per_pixel = 0;
3454
3455 if (vkblend) {
3456 for (unsigned i = 0; i < subpass->color_count; i++) {
3457 if (!vkblend->pAttachments[i].colorWriteMask)
3458 continue;
3459
3460 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3461 continue;
3462
3463 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3464 unsigned bytes = vk_format_get_blocksize(format);
3465 if (!min_bytes_per_pixel || bytes < min_bytes_per_pixel)
3466 min_bytes_per_pixel = bytes;
3467 }
3468 }
3469
3470 pa_sc_binner_cntl_0 =
3471 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) |
3472 S_028C44_BIN_SIZE_X(0) |
3473 S_028C44_BIN_SIZE_Y(0) |
3474 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3475 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel <= 4 ? 2 : 1) | /* 128 or 64 */
3476 S_028C44_DISABLE_START_OF_PRIM(1);
3477 }
3478
3479 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3480 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3481 }
3482
3483 struct radv_binning_settings
3484 radv_get_binning_settings(const struct radv_physical_device *pdev)
3485 {
3486 struct radv_binning_settings settings;
3487 if (pdev->rad_info.has_dedicated_vram) {
3488 if (pdev->rad_info.num_render_backends > 4) {
3489 settings.context_states_per_bin = 1;
3490 settings.persistent_states_per_bin = 1;
3491 } else {
3492 settings.context_states_per_bin = 3;
3493 settings.persistent_states_per_bin = 8;
3494 }
3495 settings.fpovs_per_batch = 63;
3496 } else {
3497 /* The context states are affected by the scissor bug. */
3498 settings.context_states_per_bin = 6;
3499 /* 32 causes hangs for RAVEN. */
3500 settings.persistent_states_per_bin = 16;
3501 settings.fpovs_per_batch = 63;
3502 }
3503
3504 if (pdev->rad_info.has_gfx9_scissor_bug)
3505 settings.context_states_per_bin = 1;
3506
3507 return settings;
3508 }
3509
3510 static void
3511 radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs,
3512 struct radv_pipeline *pipeline,
3513 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3514 const struct radv_blend_state *blend)
3515 {
3516 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
3517 return;
3518
3519 VkExtent2D bin_size;
3520 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3521 bin_size = radv_gfx10_compute_bin_size(pipeline, pCreateInfo);
3522 } else if (pipeline->device->physical_device->rad_info.chip_class == GFX9) {
3523 bin_size = radv_gfx9_compute_bin_size(pipeline, pCreateInfo);
3524 } else
3525 unreachable("Unhandled generation for binning bin size calculation");
3526
3527 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
3528 struct radv_binning_settings settings =
3529 radv_get_binning_settings(pipeline->device->physical_device);
3530
3531 bool disable_start_of_prim = true;
3532 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3533
3534 const struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3535
3536 if (pipeline->device->dfsm_allowed && ps &&
3537 !ps->info.ps.can_discard &&
3538 !ps->info.ps.writes_memory &&
3539 blend->cb_target_enabled_4bit) {
3540 db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_AUTO);
3541 disable_start_of_prim = (blend->blend_enable_4bit & blend->cb_target_enabled_4bit) != 0;
3542 }
3543
3544 const uint32_t pa_sc_binner_cntl_0 =
3545 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
3546 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
3547 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
3548 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
3549 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
3550 S_028C44_CONTEXT_STATES_PER_BIN(settings.context_states_per_bin - 1) |
3551 S_028C44_PERSISTENT_STATES_PER_BIN(settings.persistent_states_per_bin - 1) |
3552 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim) |
3553 S_028C44_FPOVS_PER_BATCH(settings.fpovs_per_batch) |
3554 S_028C44_OPTIMAL_BIN_SELECTION(1);
3555
3556 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3557 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3558 } else
3559 radv_pipeline_generate_disabled_binning_state(ctx_cs, pipeline, pCreateInfo);
3560 }
3561
3562
3563 static void
3564 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs,
3565 struct radv_pipeline *pipeline,
3566 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3567 const struct radv_graphics_pipeline_create_info *extra)
3568 {
3569 const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
3570 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3571 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3572 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3573 struct radv_render_pass_attachment *attachment = NULL;
3574 uint32_t db_depth_control = 0, db_stencil_control = 0;
3575 uint32_t db_render_control = 0, db_render_override2 = 0;
3576 uint32_t db_render_override = 0;
3577
3578 if (subpass->depth_stencil_attachment)
3579 attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3580
3581 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
3582 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
3583
3584 if (vkds && has_depth_attachment) {
3585 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
3586 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
3587 S_028800_ZFUNC(vkds->depthCompareOp) |
3588 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
3589
3590 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3591 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
3592 }
3593
3594 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
3595 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3596 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
3597 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
3598 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
3599 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
3600
3601 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
3602 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
3603 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
3604 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
3605 }
3606
3607 if (attachment && extra) {
3608 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
3609 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
3610
3611 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->resummarize_enable);
3612 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->depth_compress_disable);
3613 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->stencil_compress_disable);
3614 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
3615 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
3616 }
3617
3618 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3619 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
3620
3621 if (!pCreateInfo->pRasterizationState->depthClampEnable &&
3622 ps->info.ps.writes_z) {
3623 /* From VK_EXT_depth_range_unrestricted spec:
3624 *
3625 * "The behavior described in Primitive Clipping still applies.
3626 * If depth clamping is disabled the depth values are still
3627 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3628 * depth clamping is enabled the above equation is ignored and
3629 * the depth values are instead clamped to the VkViewport
3630 * minDepth and maxDepth values, which in the case of this
3631 * extension can be outside of the 0.0 to 1.0 range."
3632 */
3633 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3634 }
3635
3636 radeon_set_context_reg(ctx_cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
3637 radeon_set_context_reg(ctx_cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
3638
3639 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control);
3640 radeon_set_context_reg(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
3641 radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
3642 }
3643
3644 static void
3645 radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
3646 struct radv_pipeline *pipeline,
3647 const struct radv_blend_state *blend)
3648 {
3649 radeon_set_context_reg_seq(ctx_cs, R_028780_CB_BLEND0_CONTROL, 8);
3650 radeon_emit_array(ctx_cs, blend->cb_blend_control,
3651 8);
3652 radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
3653 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
3654
3655 if (pipeline->device->physical_device->rad_info.has_rbplus) {
3656
3657 radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
3658 radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
3659 }
3660
3661 radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
3662
3663 radeon_set_context_reg(ctx_cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
3664 radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
3665
3666 pipeline->graphics.col_format = blend->spi_shader_col_format;
3667 pipeline->graphics.cb_target_mask = blend->cb_target_mask;
3668 }
3669
3670 static const VkConservativeRasterizationModeEXT
3671 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo)
3672 {
3673 const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster =
3674 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT);
3675
3676 if (!conservative_raster)
3677 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT;
3678 return conservative_raster->conservativeRasterizationMode;
3679 }
3680
3681 static void
3682 radv_pipeline_generate_raster_state(struct radeon_cmdbuf *ctx_cs,
3683 struct radv_pipeline *pipeline,
3684 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3685 {
3686 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
3687 const VkConservativeRasterizationModeEXT mode =
3688 radv_get_conservative_raster_mode(vkraster);
3689 uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3690 bool depth_clip_disable = vkraster->depthClampEnable;
3691
3692 const VkPipelineRasterizationDepthClipStateCreateInfoEXT *depth_clip_state =
3693 vk_find_struct_const(vkraster->pNext, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT);
3694 if (depth_clip_state) {
3695 depth_clip_disable = !depth_clip_state->depthClipEnable;
3696 }
3697
3698 radeon_set_context_reg(ctx_cs, R_028810_PA_CL_CLIP_CNTL,
3699 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3700 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable ? 1 : 0) |
3701 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable ? 1 : 0) |
3702 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
3703 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3704
3705 radeon_set_context_reg(ctx_cs, R_0286D4_SPI_INTERP_CONTROL_0,
3706 S_0286D4_FLAT_SHADE_ENA(1) |
3707 S_0286D4_PNT_SPRITE_ENA(1) |
3708 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
3709 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
3710 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
3711 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
3712 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3713
3714 radeon_set_context_reg(ctx_cs, R_028BE4_PA_SU_VTX_CNTL,
3715 S_028BE4_PIX_CENTER(1) | // TODO verify
3716 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
3717 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
3718
3719 radeon_set_context_reg(ctx_cs, R_028814_PA_SU_SC_MODE_CNTL,
3720 S_028814_FACE(vkraster->frontFace) |
3721 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
3722 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
3723 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
3724 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3725 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3726 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3727 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3728 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
3729
3730 /* Conservative rasterization. */
3731 if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
3732 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3733
3734 ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3735 ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3736 S_028804_OVERRASTERIZATION_AMOUNT(4);
3737
3738 pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3739 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3740 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3741
3742 if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) {
3743 pa_sc_conservative_rast |=
3744 S_028C4C_OVER_RAST_ENABLE(1) |
3745 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3746 S_028C4C_UNDER_RAST_ENABLE(0) |
3747 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3748 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3749 } else {
3750 assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT);
3751 pa_sc_conservative_rast |=
3752 S_028C4C_OVER_RAST_ENABLE(0) |
3753 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3754 S_028C4C_UNDER_RAST_ENABLE(1) |
3755 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3756 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3757 }
3758 }
3759
3760 radeon_set_context_reg(ctx_cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
3761 pa_sc_conservative_rast);
3762 }
3763
3764
3765 static void
3766 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
3767 struct radv_pipeline *pipeline)
3768 {
3769 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3770
3771 radeon_set_context_reg_seq(ctx_cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3772 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[0]);
3773 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]);
3774
3775 radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa);
3776 radeon_set_context_reg(ctx_cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
3777 radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
3778 radeon_set_context_reg(ctx_cs, R_028BDC_PA_SC_LINE_CNTL, ms->pa_sc_line_cntl);
3779 radeon_set_context_reg(ctx_cs, R_028BE0_PA_SC_AA_CONFIG, ms->pa_sc_aa_config);
3780
3781 /* The exclusion bits can be set to improve rasterization efficiency
3782 * if no sample lies on the pixel boundary (-8 sample offset). It's
3783 * currently always TRUE because the driver doesn't support 16 samples.
3784 */
3785 bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= GFX7;
3786 radeon_set_context_reg(ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3787 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3788 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3789
3790 /* GFX9: Flush DFSM when the AA mode changes. */
3791 if (pipeline->device->dfsm_allowed) {
3792 radeon_emit(ctx_cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3793 radeon_emit(ctx_cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3794 }
3795 }
3796
3797 static void
3798 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
3799 struct radv_pipeline *pipeline)
3800 {
3801 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3802 const struct radv_shader_variant *vs =
3803 pipeline->shaders[MESA_SHADER_TESS_EVAL] ?
3804 pipeline->shaders[MESA_SHADER_TESS_EVAL] :
3805 pipeline->shaders[MESA_SHADER_VERTEX];
3806 unsigned vgt_primitiveid_en = 0;
3807 uint32_t vgt_gs_mode = 0;
3808
3809 if (radv_pipeline_has_ngg(pipeline))
3810 return;
3811
3812 if (radv_pipeline_has_gs(pipeline)) {
3813 const struct radv_shader_variant *gs =
3814 pipeline->shaders[MESA_SHADER_GEOMETRY];
3815
3816 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
3817 pipeline->device->physical_device->rad_info.chip_class);
3818 } else if (outinfo->export_prim_id || vs->info.uses_prim_id) {
3819 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
3820 vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(1);
3821 }
3822
3823 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
3824 radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
3825 }
3826
3827 static void
3828 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
3829 struct radeon_cmdbuf *cs,
3830 struct radv_pipeline *pipeline,
3831 struct radv_shader_variant *shader)
3832 {
3833 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3834
3835 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
3836 radeon_emit(cs, va >> 8);
3837 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
3838 radeon_emit(cs, shader->config.rsrc1);
3839 radeon_emit(cs, shader->config.rsrc2);
3840
3841 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3842 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3843 clip_dist_mask = outinfo->clip_dist_mask;
3844 cull_dist_mask = outinfo->cull_dist_mask;
3845 total_mask = clip_dist_mask | cull_dist_mask;
3846 bool misc_vec_ena = outinfo->writes_pointsize ||
3847 outinfo->writes_layer ||
3848 outinfo->writes_viewport_index;
3849 unsigned spi_vs_out_config, nparams;
3850
3851 /* VS is required to export at least one param. */
3852 nparams = MAX2(outinfo->param_exports, 1);
3853 spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
3854
3855 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3856 spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0);
3857 }
3858
3859 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, spi_vs_out_config);
3860
3861 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3862 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3863 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3864 V_02870C_SPI_SHADER_4COMP :
3865 V_02870C_SPI_SHADER_NONE) |
3866 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3867 V_02870C_SPI_SHADER_4COMP :
3868 V_02870C_SPI_SHADER_NONE) |
3869 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3870 V_02870C_SPI_SHADER_4COMP :
3871 V_02870C_SPI_SHADER_NONE));
3872
3873 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3874 S_028818_VTX_W0_FMT(1) |
3875 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3876 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3877 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3878
3879 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3880 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3881 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3882 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3883 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3884 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3885 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3886 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3887 cull_dist_mask << 8 |
3888 clip_dist_mask);
3889
3890 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
3891 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
3892 outinfo->writes_viewport_index);
3893 }
3894
3895 static void
3896 radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs,
3897 struct radv_pipeline *pipeline,
3898 struct radv_shader_variant *shader)
3899 {
3900 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3901
3902 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
3903 radeon_emit(cs, va >> 8);
3904 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3905 radeon_emit(cs, shader->config.rsrc1);
3906 radeon_emit(cs, shader->config.rsrc2);
3907 }
3908
3909 static void
3910 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs,
3911 struct radv_pipeline *pipeline,
3912 struct radv_shader_variant *shader,
3913 const struct radv_tessellation_state *tess)
3914 {
3915 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3916 uint32_t rsrc2 = shader->config.rsrc2;
3917
3918 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3919 radeon_emit(cs, va >> 8);
3920 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3921
3922 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
3923 if (pipeline->device->physical_device->rad_info.chip_class == GFX7 &&
3924 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
3925 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
3926
3927 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
3928 radeon_emit(cs, shader->config.rsrc1);
3929 radeon_emit(cs, rsrc2);
3930 }
3931
3932 static void
3933 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
3934 struct radeon_cmdbuf *cs,
3935 struct radv_pipeline *pipeline,
3936 struct radv_shader_variant *shader)
3937 {
3938 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3939 gl_shader_stage es_type =
3940 radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
3941 struct radv_shader_variant *es =
3942 es_type == MESA_SHADER_TESS_EVAL ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX];
3943 const struct gfx10_ngg_info *ngg_state = &shader->info.ngg_info;
3944
3945 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
3946 radeon_emit(cs, va >> 8);
3947 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3948 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
3949 radeon_emit(cs, shader->config.rsrc1);
3950 radeon_emit(cs, shader->config.rsrc2);
3951
3952 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3953 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3954 clip_dist_mask = outinfo->clip_dist_mask;
3955 cull_dist_mask = outinfo->cull_dist_mask;
3956 total_mask = clip_dist_mask | cull_dist_mask;
3957 bool misc_vec_ena = outinfo->writes_pointsize ||
3958 outinfo->writes_layer ||
3959 outinfo->writes_viewport_index;
3960 bool es_enable_prim_id = outinfo->export_prim_id ||
3961 (es && es->info.uses_prim_id);
3962 bool break_wave_at_eoi = false;
3963 unsigned ge_cntl;
3964 unsigned nparams;
3965
3966 if (es_type == MESA_SHADER_TESS_EVAL) {
3967 struct radv_shader_variant *gs =
3968 pipeline->shaders[MESA_SHADER_GEOMETRY];
3969
3970 if (es_enable_prim_id || (gs && gs->info.uses_prim_id))
3971 break_wave_at_eoi = true;
3972 }
3973
3974 nparams = MAX2(outinfo->param_exports, 1);
3975 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG,
3976 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
3977 S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0));
3978
3979 radeon_set_context_reg(ctx_cs, R_028708_SPI_SHADER_IDX_FORMAT,
3980 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP));
3981 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3982 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3983 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3984 V_02870C_SPI_SHADER_4COMP :
3985 V_02870C_SPI_SHADER_NONE) |
3986 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3987 V_02870C_SPI_SHADER_4COMP :
3988 V_02870C_SPI_SHADER_NONE) |
3989 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3990 V_02870C_SPI_SHADER_4COMP :
3991 V_02870C_SPI_SHADER_NONE));
3992
3993 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3994 S_028818_VTX_W0_FMT(1) |
3995 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3996 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3997 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3998 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3999 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
4000 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
4001 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
4002 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
4003 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
4004 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
4005 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
4006 cull_dist_mask << 8 |
4007 clip_dist_mask);
4008
4009 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN,
4010 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
4011 S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo->export_prim_id));
4012
4013 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
4014 ngg_state->vgt_esgs_ring_itemsize);
4015
4016 /* NGG specific registers. */
4017 struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
4018 uint32_t gs_num_invocations = gs ? gs->info.gs.invocations : 1;
4019
4020 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
4021 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state->hw_max_esverts) |
4022 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state->max_gsprims) |
4023 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state->max_gsprims * gs_num_invocations));
4024 radeon_set_context_reg(ctx_cs, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
4025 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state->max_out_verts));
4026 radeon_set_context_reg(ctx_cs, R_028B4C_GE_NGG_SUBGRP_CNTL,
4027 S_028B4C_PRIM_AMP_FACTOR(ngg_state->prim_amp_factor) |
4028 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
4029 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
4030 S_028B90_CNT(gs_num_invocations) |
4031 S_028B90_ENABLE(gs_num_invocations > 1) |
4032 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state->max_vert_out_per_gs_instance));
4033
4034 /* User edge flags are set by the pos exports. If user edge flags are
4035 * not used, we must use hw-generated edge flags and pass them via
4036 * the prim export to prevent drawing lines on internal edges of
4037 * decomposed primitives (such as quads) with polygon mode = lines.
4038 *
4039 * TODO: We should combine hw-generated edge flags with user edge
4040 * flags in the shader.
4041 */
4042 radeon_set_context_reg(ctx_cs, R_028838_PA_CL_NGG_CNTL,
4043 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) &&
4044 !radv_pipeline_has_gs(pipeline)));
4045
4046 ge_cntl = S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) |
4047 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
4048 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
4049
4050 /* Bug workaround for a possible hang with non-tessellation cases.
4051 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
4052 *
4053 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
4054 */
4055 if (pipeline->device->physical_device->rad_info.chip_class == GFX10 &&
4056 !radv_pipeline_has_tess(pipeline) &&
4057 ngg_state->hw_max_esverts != 256) {
4058 ge_cntl &= C_03096C_VERT_GRP_SIZE;
4059
4060 if (ngg_state->hw_max_esverts > 5) {
4061 ge_cntl |= S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts - 5);
4062 }
4063 }
4064
4065 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, ge_cntl);
4066 }
4067
4068 static void
4069 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
4070 struct radv_pipeline *pipeline,
4071 struct radv_shader_variant *shader,
4072 const struct radv_tessellation_state *tess)
4073 {
4074 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
4075
4076 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4077 unsigned hs_rsrc2 = shader->config.rsrc2;
4078
4079 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4080 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(tess->lds_size);
4081 } else {
4082 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(tess->lds_size);
4083 }
4084
4085 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4086 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
4087 radeon_emit(cs, va >> 8);
4088 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
4089 } else {
4090 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
4091 radeon_emit(cs, va >> 8);
4092 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
4093 }
4094
4095 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
4096 radeon_emit(cs, shader->config.rsrc1);
4097 radeon_emit(cs, hs_rsrc2);
4098 } else {
4099 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
4100 radeon_emit(cs, va >> 8);
4101 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
4102 radeon_emit(cs, shader->config.rsrc1);
4103 radeon_emit(cs, shader->config.rsrc2);
4104 }
4105 }
4106
4107 static void
4108 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *ctx_cs,
4109 struct radeon_cmdbuf *cs,
4110 struct radv_pipeline *pipeline,
4111 const struct radv_tessellation_state *tess)
4112 {
4113 struct radv_shader_variant *vs;
4114
4115 /* Skip shaders merged into HS/GS */
4116 vs = pipeline->shaders[MESA_SHADER_VERTEX];
4117 if (!vs)
4118 return;
4119
4120 if (vs->info.vs.as_ls)
4121 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
4122 else if (vs->info.vs.as_es)
4123 radv_pipeline_generate_hw_es(cs, pipeline, vs);
4124 else if (vs->info.is_ngg)
4125 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, vs);
4126 else
4127 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, vs);
4128 }
4129
4130 static void
4131 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs,
4132 struct radeon_cmdbuf *cs,
4133 struct radv_pipeline *pipeline,
4134 const struct radv_tessellation_state *tess)
4135 {
4136 if (!radv_pipeline_has_tess(pipeline))
4137 return;
4138
4139 struct radv_shader_variant *tes, *tcs;
4140
4141 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
4142 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
4143
4144 if (tes) {
4145 if (tes->info.is_ngg) {
4146 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, tes);
4147 } else if (tes->info.tes.as_es)
4148 radv_pipeline_generate_hw_es(cs, pipeline, tes);
4149 else
4150 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes);
4151 }
4152
4153 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
4154
4155 radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM,
4156 tess->tf_param);
4157
4158 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7)
4159 radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, 2,
4160 tess->ls_hs_config);
4161 else
4162 radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG,
4163 tess->ls_hs_config);
4164
4165 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 &&
4166 !radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
4167 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
4168 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4169 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4170 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4171 }
4172 }
4173
4174 static void
4175 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs,
4176 struct radeon_cmdbuf *cs,
4177 struct radv_pipeline *pipeline,
4178 struct radv_shader_variant *gs)
4179 {
4180 const struct gfx9_gs_info *gs_state = &gs->info.gs_ring_info;
4181 unsigned gs_max_out_vertices;
4182 uint8_t *num_components;
4183 uint8_t max_stream;
4184 unsigned offset;
4185 uint64_t va;
4186
4187 gs_max_out_vertices = gs->info.gs.vertices_out;
4188 max_stream = gs->info.gs.max_stream;
4189 num_components = gs->info.gs.num_stream_output_components;
4190
4191 offset = num_components[0] * gs_max_out_vertices;
4192
4193 radeon_set_context_reg_seq(ctx_cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
4194 radeon_emit(ctx_cs, offset);
4195 if (max_stream >= 1)
4196 offset += num_components[1] * gs_max_out_vertices;
4197 radeon_emit(ctx_cs, offset);
4198 if (max_stream >= 2)
4199 offset += num_components[2] * gs_max_out_vertices;
4200 radeon_emit(ctx_cs, offset);
4201 if (max_stream >= 3)
4202 offset += num_components[3] * gs_max_out_vertices;
4203 radeon_set_context_reg(ctx_cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
4204
4205 radeon_set_context_reg_seq(ctx_cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
4206 radeon_emit(ctx_cs, num_components[0]);
4207 radeon_emit(ctx_cs, (max_stream >= 1) ? num_components[1] : 0);
4208 radeon_emit(ctx_cs, (max_stream >= 2) ? num_components[2] : 0);
4209 radeon_emit(ctx_cs, (max_stream >= 3) ? num_components[3] : 0);
4210
4211 uint32_t gs_num_invocations = gs->info.gs.invocations;
4212 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
4213 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
4214 S_028B90_ENABLE(gs_num_invocations > 0));
4215
4216 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
4217 gs_state->vgt_esgs_ring_itemsize);
4218
4219 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
4220
4221 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4222 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4223 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
4224 radeon_emit(cs, va >> 8);
4225 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
4226 } else {
4227 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
4228 radeon_emit(cs, va >> 8);
4229 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
4230 }
4231
4232 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
4233 radeon_emit(cs, gs->config.rsrc1);
4234 radeon_emit(cs, gs->config.rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
4235
4236 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
4237 radeon_set_context_reg(ctx_cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
4238 } else {
4239 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
4240 radeon_emit(cs, va >> 8);
4241 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
4242 radeon_emit(cs, gs->config.rsrc1);
4243 radeon_emit(cs, gs->config.rsrc2);
4244 }
4245
4246 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, pipeline->gs_copy_shader);
4247 }
4248
4249 static void
4250 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
4251 struct radeon_cmdbuf *cs,
4252 struct radv_pipeline *pipeline)
4253 {
4254 struct radv_shader_variant *gs;
4255
4256 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
4257 if (!gs)
4258 return;
4259
4260 if (gs->info.is_ngg)
4261 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, gs);
4262 else
4263 radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs);
4264
4265 radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT,
4266 gs->info.gs.vertices_out);
4267 }
4268
4269 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade,
4270 bool explicit, bool float16)
4271 {
4272 uint32_t ps_input_cntl;
4273 if (offset <= AC_EXP_PARAM_OFFSET_31) {
4274 ps_input_cntl = S_028644_OFFSET(offset);
4275 if (flat_shade || explicit)
4276 ps_input_cntl |= S_028644_FLAT_SHADE(1);
4277 if (explicit) {
4278 /* Force parameter cache to be read in passthrough
4279 * mode.
4280 */
4281 ps_input_cntl |= S_028644_OFFSET(1 << 5);
4282 }
4283 if (float16) {
4284 ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) |
4285 S_028644_ATTR0_VALID(1);
4286 }
4287 } else {
4288 /* The input is a DEFAULT_VAL constant. */
4289 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
4290 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
4291 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
4292 ps_input_cntl = S_028644_OFFSET(0x20) |
4293 S_028644_DEFAULT_VAL(offset);
4294 }
4295 return ps_input_cntl;
4296 }
4297
4298 static void
4299 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
4300 struct radv_pipeline *pipeline)
4301 {
4302 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4303 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
4304 uint32_t ps_input_cntl[32];
4305
4306 unsigned ps_offset = 0;
4307
4308 if (ps->info.ps.prim_id_input) {
4309 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
4310 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4311 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4312 ++ps_offset;
4313 }
4314 }
4315
4316 if (ps->info.ps.layer_input ||
4317 ps->info.needs_multiview_view_index) {
4318 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
4319 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4320 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4321 else
4322 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false, false);
4323 ++ps_offset;
4324 }
4325
4326 if (ps->info.ps.viewport_index_input) {
4327 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VIEWPORT];
4328 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4329 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4330 else
4331 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false, false);
4332 ++ps_offset;
4333 }
4334
4335 if (ps->info.ps.has_pcoord) {
4336 unsigned val;
4337 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4338 ps_input_cntl[ps_offset] = val;
4339 ps_offset++;
4340 }
4341
4342 if (ps->info.ps.num_input_clips_culls) {
4343 unsigned vs_offset;
4344
4345 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
4346 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4347 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false, false);
4348 ++ps_offset;
4349 }
4350
4351 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
4352 if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
4353 ps->info.ps.num_input_clips_culls > 4) {
4354 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false, false);
4355 ++ps_offset;
4356 }
4357 }
4358
4359 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.ps.input_mask; ++i) {
4360 unsigned vs_offset;
4361 bool flat_shade;
4362 bool explicit;
4363 bool float16;
4364 if (!(ps->info.ps.input_mask & (1u << i)))
4365 continue;
4366
4367 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
4368 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
4369 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
4370 ++ps_offset;
4371 continue;
4372 }
4373
4374 flat_shade = !!(ps->info.ps.flat_shaded_mask & (1u << ps_offset));
4375 explicit = !!(ps->info.ps.explicit_shaded_mask & (1u << ps_offset));
4376 float16 = !!(ps->info.ps.float16_shaded_mask & (1u << ps_offset));
4377
4378 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade, explicit, float16);
4379 ++ps_offset;
4380 }
4381
4382 if (ps_offset) {
4383 radeon_set_context_reg_seq(ctx_cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
4384 for (unsigned i = 0; i < ps_offset; i++) {
4385 radeon_emit(ctx_cs, ps_input_cntl[i]);
4386 }
4387 }
4388 }
4389
4390 static uint32_t
4391 radv_compute_db_shader_control(const struct radv_device *device,
4392 const struct radv_pipeline *pipeline,
4393 const struct radv_shader_variant *ps)
4394 {
4395 unsigned conservative_z_export = V_02880C_EXPORT_ANY_Z;
4396 unsigned z_order;
4397 if (ps->info.ps.early_fragment_test || !ps->info.ps.writes_memory)
4398 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
4399 else
4400 z_order = V_02880C_LATE_Z;
4401
4402 if (ps->info.ps.depth_layout == FRAG_DEPTH_LAYOUT_GREATER)
4403 conservative_z_export = V_02880C_EXPORT_GREATER_THAN_Z;
4404 else if (ps->info.ps.depth_layout == FRAG_DEPTH_LAYOUT_LESS)
4405 conservative_z_export = V_02880C_EXPORT_LESS_THAN_Z;
4406
4407 bool disable_rbplus = device->physical_device->rad_info.has_rbplus &&
4408 !device->physical_device->rad_info.rbplus_allowed;
4409
4410 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4411 * but this appears to break Project Cars (DXVK). See
4412 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4413 */
4414 bool mask_export_enable = ps->info.ps.writes_sample_mask;
4415
4416 return S_02880C_Z_EXPORT_ENABLE(ps->info.ps.writes_z) |
4417 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.ps.writes_stencil) |
4418 S_02880C_KILL_ENABLE(!!ps->info.ps.can_discard) |
4419 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
4420 S_02880C_CONSERVATIVE_Z_EXPORT(conservative_z_export) |
4421 S_02880C_Z_ORDER(z_order) |
4422 S_02880C_DEPTH_BEFORE_SHADER(ps->info.ps.early_fragment_test) |
4423 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps->info.ps.post_depth_coverage) |
4424 S_02880C_EXEC_ON_HIER_FAIL(ps->info.ps.writes_memory) |
4425 S_02880C_EXEC_ON_NOOP(ps->info.ps.writes_memory) |
4426 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
4427 }
4428
4429 static void
4430 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs,
4431 struct radeon_cmdbuf *cs,
4432 struct radv_pipeline *pipeline)
4433 {
4434 struct radv_shader_variant *ps;
4435 uint64_t va;
4436 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
4437
4438 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4439 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
4440
4441 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
4442 radeon_emit(cs, va >> 8);
4443 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
4444 radeon_emit(cs, ps->config.rsrc1);
4445 radeon_emit(cs, ps->config.rsrc2);
4446
4447 radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL,
4448 radv_compute_db_shader_control(pipeline->device,
4449 pipeline, ps));
4450
4451 radeon_set_context_reg(ctx_cs, R_0286CC_SPI_PS_INPUT_ENA,
4452 ps->config.spi_ps_input_ena);
4453
4454 radeon_set_context_reg(ctx_cs, R_0286D0_SPI_PS_INPUT_ADDR,
4455 ps->config.spi_ps_input_addr);
4456
4457 radeon_set_context_reg(ctx_cs, R_0286D8_SPI_PS_IN_CONTROL,
4458 S_0286D8_NUM_INTERP(ps->info.ps.num_interp) |
4459 S_0286D8_PS_W32_EN(ps->info.wave_size == 32));
4460
4461 radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
4462
4463 radeon_set_context_reg(ctx_cs, R_028710_SPI_SHADER_Z_FORMAT,
4464 ac_get_spi_shader_z_format(ps->info.ps.writes_z,
4465 ps->info.ps.writes_stencil,
4466 ps->info.ps.writes_sample_mask));
4467
4468 if (pipeline->device->dfsm_allowed) {
4469 /* optimise this? */
4470 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4471 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
4472 }
4473 }
4474
4475 static void
4476 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs,
4477 struct radv_pipeline *pipeline)
4478 {
4479 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4480 pipeline->device->physical_device->rad_info.chip_class >= GFX10)
4481 return;
4482
4483 unsigned vtx_reuse_depth = 30;
4484 if (radv_pipeline_has_tess(pipeline) &&
4485 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
4486 vtx_reuse_depth = 14;
4487 }
4488 radeon_set_context_reg(ctx_cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
4489 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
4490 }
4491
4492 static uint32_t
4493 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
4494 {
4495 uint32_t stages = 0;
4496 if (radv_pipeline_has_tess(pipeline)) {
4497 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
4498 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4499
4500 if (radv_pipeline_has_gs(pipeline))
4501 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
4502 S_028B54_GS_EN(1);
4503 else if (radv_pipeline_has_ngg(pipeline))
4504 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
4505 else
4506 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
4507 } else if (radv_pipeline_has_gs(pipeline)) {
4508 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
4509 S_028B54_GS_EN(1);
4510 } else if (radv_pipeline_has_ngg(pipeline)) {
4511 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
4512 }
4513
4514 if (radv_pipeline_has_ngg(pipeline)) {
4515 stages |= S_028B54_PRIMGEN_EN(1);
4516 if (pipeline->streamout_shader)
4517 stages |= S_028B54_NGG_WAVE_ID_EN(1);
4518 if (radv_pipeline_has_ngg_passthrough(pipeline))
4519 stages |= S_028B54_PRIMGEN_PASSTHRU_EN(1);
4520 } else if (radv_pipeline_has_gs(pipeline)) {
4521 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
4522 }
4523
4524 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
4525 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4526
4527 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4528 uint8_t hs_size = 64, gs_size = 64, vs_size = 64;
4529
4530 if (radv_pipeline_has_tess(pipeline))
4531 hs_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.wave_size;
4532
4533 if (pipeline->shaders[MESA_SHADER_GEOMETRY]) {
4534 vs_size = gs_size = pipeline->shaders[MESA_SHADER_GEOMETRY]->info.wave_size;
4535 if (pipeline->gs_copy_shader)
4536 vs_size = pipeline->gs_copy_shader->info.wave_size;
4537 } else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
4538 vs_size = pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.wave_size;
4539 else if (pipeline->shaders[MESA_SHADER_VERTEX])
4540 vs_size = pipeline->shaders[MESA_SHADER_VERTEX]->info.wave_size;
4541
4542 if (radv_pipeline_has_ngg(pipeline))
4543 gs_size = vs_size;
4544
4545 /* legacy GS only supports Wave64 */
4546 stages |= S_028B54_HS_W32_EN(hs_size == 32 ? 1 : 0) |
4547 S_028B54_GS_W32_EN(gs_size == 32 ? 1 : 0) |
4548 S_028B54_VS_W32_EN(vs_size == 32 ? 1 : 0);
4549 }
4550
4551 return stages;
4552 }
4553
4554 static uint32_t
4555 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
4556 {
4557 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
4558 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
4559
4560 if (!discard_rectangle_info)
4561 return 0xffff;
4562
4563 unsigned mask = 0;
4564
4565 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
4566 /* Interpret i as a bitmask, and then set the bit in the mask if
4567 * that combination of rectangles in which the pixel is contained
4568 * should pass the cliprect test. */
4569 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
4570
4571 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
4572 !relevant_subset)
4573 continue;
4574
4575 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
4576 relevant_subset)
4577 continue;
4578
4579 mask |= 1u << i;
4580 }
4581
4582 return mask;
4583 }
4584
4585 static void
4586 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf *ctx_cs,
4587 struct radv_pipeline *pipeline,
4588 const struct radv_tessellation_state *tess)
4589 {
4590 bool break_wave_at_eoi = false;
4591 unsigned primgroup_size;
4592 unsigned vertgroup_size = 256; /* 256 = disable vertex grouping */
4593
4594 if (radv_pipeline_has_tess(pipeline)) {
4595 primgroup_size = tess->num_patches; /* must be a multiple of NUM_PATCHES */
4596 } else if (radv_pipeline_has_gs(pipeline)) {
4597 const struct gfx9_gs_info *gs_state =
4598 &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs_ring_info;
4599 unsigned vgt_gs_onchip_cntl = gs_state->vgt_gs_onchip_cntl;
4600 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
4601 } else {
4602 primgroup_size = 128; /* recommended without a GS and tess */
4603 }
4604
4605 if (radv_pipeline_has_tess(pipeline)) {
4606 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4607 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4608 break_wave_at_eoi = true;
4609 }
4610
4611 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL,
4612 S_03096C_PRIM_GRP_SIZE(primgroup_size) |
4613 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
4614 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4615 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi));
4616 }
4617
4618 static void
4619 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
4620 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4621 const struct radv_graphics_pipeline_create_info *extra,
4622 const struct radv_blend_state *blend,
4623 const struct radv_tessellation_state *tess,
4624 unsigned prim, unsigned gs_out)
4625 {
4626 struct radeon_cmdbuf *ctx_cs = &pipeline->ctx_cs;
4627 struct radeon_cmdbuf *cs = &pipeline->cs;
4628
4629 cs->max_dw = 64;
4630 ctx_cs->max_dw = 256;
4631 cs->buf = malloc(4 * (cs->max_dw + ctx_cs->max_dw));
4632 ctx_cs->buf = cs->buf + cs->max_dw;
4633
4634 radv_pipeline_generate_depth_stencil_state(ctx_cs, pipeline, pCreateInfo, extra);
4635 radv_pipeline_generate_blend_state(ctx_cs, pipeline, blend);
4636 radv_pipeline_generate_raster_state(ctx_cs, pipeline, pCreateInfo);
4637 radv_pipeline_generate_multisample_state(ctx_cs, pipeline);
4638 radv_pipeline_generate_vgt_gs_mode(ctx_cs, pipeline);
4639 radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline, tess);
4640 radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline, tess);
4641 radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline);
4642 radv_pipeline_generate_fragment_shader(ctx_cs, cs, pipeline);
4643 radv_pipeline_generate_ps_inputs(ctx_cs, pipeline);
4644 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline);
4645 radv_pipeline_generate_binning_state(ctx_cs, pipeline, pCreateInfo, blend);
4646
4647 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && !radv_pipeline_has_ngg(pipeline))
4648 gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline, tess);
4649
4650 radeon_set_context_reg(ctx_cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
4651
4652 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
4653 radeon_set_uconfig_reg_idx(pipeline->device->physical_device,
4654 cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
4655 } else {
4656 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
4657 }
4658 radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
4659
4660 radeon_set_context_reg(ctx_cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
4661
4662 pipeline->ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4);
4663
4664 assert(ctx_cs->cdw <= ctx_cs->max_dw);
4665 assert(cs->cdw <= cs->max_dw);
4666 }
4667
4668 static struct radv_ia_multi_vgt_param_helpers
4669 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
4670 const struct radv_tessellation_state *tess,
4671 uint32_t prim)
4672 {
4673 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
4674 const struct radv_device *device = pipeline->device;
4675
4676 if (radv_pipeline_has_tess(pipeline))
4677 ia_multi_vgt_param.primgroup_size = tess->num_patches;
4678 else if (radv_pipeline_has_gs(pipeline))
4679 ia_multi_vgt_param.primgroup_size = 64;
4680 else
4681 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
4682
4683 /* GS requirement. */
4684 ia_multi_vgt_param.partial_es_wave = false;
4685 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= GFX8)
4686 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
4687 ia_multi_vgt_param.partial_es_wave = true;
4688
4689 ia_multi_vgt_param.wd_switch_on_eop = false;
4690 if (device->physical_device->rad_info.chip_class >= GFX7) {
4691 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
4692 * 4 shader engines. Set 1 to pass the assertion below.
4693 * The other cases are hardware requirements. */
4694 if (device->physical_device->rad_info.max_se < 4 ||
4695 prim == V_008958_DI_PT_POLYGON ||
4696 prim == V_008958_DI_PT_LINELOOP ||
4697 prim == V_008958_DI_PT_TRIFAN ||
4698 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
4699 (pipeline->graphics.prim_restart_enable &&
4700 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4701 (prim != V_008958_DI_PT_POINTLIST &&
4702 prim != V_008958_DI_PT_LINESTRIP))))
4703 ia_multi_vgt_param.wd_switch_on_eop = true;
4704 }
4705
4706 ia_multi_vgt_param.ia_switch_on_eoi = false;
4707 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input)
4708 ia_multi_vgt_param.ia_switch_on_eoi = true;
4709 if (radv_pipeline_has_gs(pipeline) &&
4710 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.uses_prim_id)
4711 ia_multi_vgt_param.ia_switch_on_eoi = true;
4712 if (radv_pipeline_has_tess(pipeline)) {
4713 /* SWITCH_ON_EOI must be set if PrimID is used. */
4714 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4715 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4716 ia_multi_vgt_param.ia_switch_on_eoi = true;
4717 }
4718
4719 ia_multi_vgt_param.partial_vs_wave = false;
4720 if (radv_pipeline_has_tess(pipeline)) {
4721 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4722 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
4723 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
4724 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
4725 radv_pipeline_has_gs(pipeline))
4726 ia_multi_vgt_param.partial_vs_wave = true;
4727 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4728 if (device->physical_device->rad_info.has_distributed_tess) {
4729 if (radv_pipeline_has_gs(pipeline)) {
4730 if (device->physical_device->rad_info.chip_class <= GFX8)
4731 ia_multi_vgt_param.partial_es_wave = true;
4732 } else {
4733 ia_multi_vgt_param.partial_vs_wave = true;
4734 }
4735 }
4736 }
4737
4738 /* Workaround for a VGT hang when strip primitive types are used with
4739 * primitive restart.
4740 */
4741 if (pipeline->graphics.prim_restart_enable &&
4742 (prim == V_008958_DI_PT_LINESTRIP ||
4743 prim == V_008958_DI_PT_TRISTRIP ||
4744 prim == V_008958_DI_PT_LINESTRIP_ADJ ||
4745 prim == V_008958_DI_PT_TRISTRIP_ADJ)) {
4746 ia_multi_vgt_param.partial_vs_wave = true;
4747 }
4748
4749 if (radv_pipeline_has_gs(pipeline)) {
4750 /* On these chips there is the possibility of a hang if the
4751 * pipeline uses a GS and partial_vs_wave is not set.
4752 *
4753 * This mostly does not hit 4-SE chips, as those typically set
4754 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4755 * with GS due to another workaround.
4756 *
4757 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4758 */
4759 if (device->physical_device->rad_info.family == CHIP_TONGA ||
4760 device->physical_device->rad_info.family == CHIP_FIJI ||
4761 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
4762 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
4763 device->physical_device->rad_info.family == CHIP_POLARIS12 ||
4764 device->physical_device->rad_info.family == CHIP_VEGAM) {
4765 ia_multi_vgt_param.partial_vs_wave = true;
4766 }
4767 }
4768
4769 ia_multi_vgt_param.base =
4770 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
4771 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4772 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == GFX8 ? 2 : 0) |
4773 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
4774 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
4775
4776 return ia_multi_vgt_param;
4777 }
4778
4779
4780 static void
4781 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
4782 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4783 {
4784 const VkPipelineVertexInputStateCreateInfo *vi_info =
4785 pCreateInfo->pVertexInputState;
4786 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
4787
4788 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
4789 const VkVertexInputAttributeDescription *desc =
4790 &vi_info->pVertexAttributeDescriptions[i];
4791 unsigned loc = desc->location;
4792 const struct vk_format_description *format_desc;
4793
4794 format_desc = vk_format_description(desc->format);
4795
4796 velems->format_size[loc] = format_desc->block.bits / 8;
4797 }
4798
4799 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
4800 const VkVertexInputBindingDescription *desc =
4801 &vi_info->pVertexBindingDescriptions[i];
4802
4803 pipeline->binding_stride[desc->binding] = desc->stride;
4804 pipeline->num_vertex_bindings =
4805 MAX2(pipeline->num_vertex_bindings, desc->binding + 1);
4806 }
4807 }
4808
4809 static struct radv_shader_variant *
4810 radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline)
4811 {
4812 int i;
4813
4814 for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) {
4815 struct radv_shader_variant *shader =
4816 radv_get_shader(pipeline, i);
4817
4818 if (shader && shader->info.so.num_outputs > 0)
4819 return shader;
4820 }
4821
4822 return NULL;
4823 }
4824
4825 static VkResult
4826 radv_secure_compile(struct radv_pipeline *pipeline,
4827 struct radv_device *device,
4828 const struct radv_pipeline_key *key,
4829 const VkPipelineShaderStageCreateInfo **pStages,
4830 const VkPipelineCreateFlags flags,
4831 unsigned num_stages)
4832 {
4833 uint8_t allowed_pipeline_hashes[2][20];
4834 radv_hash_shaders(allowed_pipeline_hashes[0], pStages,
4835 pipeline->layout, key, get_hash_flags(device));
4836
4837 /* Generate the GC copy hash */
4838 memcpy(allowed_pipeline_hashes[1], allowed_pipeline_hashes[0], 20);
4839 allowed_pipeline_hashes[1][0] ^= 1;
4840
4841 uint8_t allowed_hashes[2][20];
4842 for (unsigned i = 0; i < 2; ++i) {
4843 disk_cache_compute_key(device->physical_device->disk_cache,
4844 allowed_pipeline_hashes[i], 20,
4845 allowed_hashes[i]);
4846 }
4847
4848 /* Do an early exit if all cache entries are already there. */
4849 bool may_need_copy_shader = pStages[MESA_SHADER_GEOMETRY];
4850 void *main_entry = disk_cache_get(device->physical_device->disk_cache, allowed_hashes[0], NULL);
4851 void *copy_entry = NULL;
4852 if (may_need_copy_shader)
4853 copy_entry = disk_cache_get(device->physical_device->disk_cache, allowed_hashes[1], NULL);
4854
4855 bool has_all_cache_entries = main_entry && (!may_need_copy_shader || copy_entry);
4856 free(main_entry);
4857 free(copy_entry);
4858
4859 if(has_all_cache_entries)
4860 return VK_SUCCESS;
4861
4862 unsigned process = 0;
4863 uint8_t sc_threads = device->instance->num_sc_threads;
4864 while (true) {
4865 mtx_lock(&device->sc_state->secure_compile_mutex);
4866 if (device->sc_state->secure_compile_thread_counter < sc_threads) {
4867 device->sc_state->secure_compile_thread_counter++;
4868 for (unsigned i = 0; i < sc_threads; i++) {
4869 if (!device->sc_state->secure_compile_processes[i].in_use) {
4870 device->sc_state->secure_compile_processes[i].in_use = true;
4871 process = i;
4872 break;
4873 }
4874 }
4875 mtx_unlock(&device->sc_state->secure_compile_mutex);
4876 break;
4877 }
4878 mtx_unlock(&device->sc_state->secure_compile_mutex);
4879 }
4880
4881 int fd_secure_input = device->sc_state->secure_compile_processes[process].fd_secure_input;
4882 int fd_secure_output = device->sc_state->secure_compile_processes[process].fd_secure_output;
4883
4884 /* Fork a copy of the slim untainted secure compile process */
4885 enum radv_secure_compile_type sc_type = RADV_SC_TYPE_FORK_DEVICE;
4886 write(fd_secure_input, &sc_type, sizeof(sc_type));
4887
4888 if (!radv_sc_read(fd_secure_output, &sc_type, sizeof(sc_type), true) ||
4889 sc_type != RADV_SC_TYPE_INIT_SUCCESS)
4890 return VK_ERROR_DEVICE_LOST;
4891
4892 fd_secure_input = device->sc_state->secure_compile_processes[process].fd_server;
4893 fd_secure_output = device->sc_state->secure_compile_processes[process].fd_client;
4894
4895 /* Write pipeline / shader module out to secure process via pipe */
4896 sc_type = RADV_SC_TYPE_COMPILE_PIPELINE;
4897 write(fd_secure_input, &sc_type, sizeof(sc_type));
4898
4899 /* Write pipeline layout out to secure process */
4900 struct radv_pipeline_layout *layout = pipeline->layout;
4901 write(fd_secure_input, layout, sizeof(struct radv_pipeline_layout));
4902 write(fd_secure_input, &layout->num_sets, sizeof(uint32_t));
4903 for (uint32_t set = 0; set < layout->num_sets; set++) {
4904 write(fd_secure_input, &layout->set[set].layout->layout_size, sizeof(uint32_t));
4905 write(fd_secure_input, layout->set[set].layout, layout->set[set].layout->layout_size);
4906 }
4907
4908 /* Write pipeline key out to secure process */
4909 write(fd_secure_input, key, sizeof(struct radv_pipeline_key));
4910
4911 /* Write pipeline create flags out to secure process */
4912 write(fd_secure_input, &flags, sizeof(VkPipelineCreateFlags));
4913
4914 /* Write stage and shader information out to secure process */
4915 write(fd_secure_input, &num_stages, sizeof(uint32_t));
4916 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
4917 if (!pStages[i])
4918 continue;
4919
4920 /* Write stage out to secure process */
4921 gl_shader_stage stage = ffs(pStages[i]->stage) - 1;
4922 write(fd_secure_input, &stage, sizeof(gl_shader_stage));
4923
4924 /* Write entry point name out to secure process */
4925 size_t name_size = strlen(pStages[i]->pName) + 1;
4926 write(fd_secure_input, &name_size, sizeof(size_t));
4927 write(fd_secure_input, pStages[i]->pName, name_size);
4928
4929 /* Write shader module out to secure process */
4930 struct radv_shader_module *module = radv_shader_module_from_handle(pStages[i]->module);
4931 assert(!module->nir);
4932 size_t module_size = sizeof(struct radv_shader_module) + module->size;
4933 write(fd_secure_input, &module_size, sizeof(size_t));
4934 write(fd_secure_input, module, module_size);
4935
4936 /* Write specialization info out to secure process */
4937 const VkSpecializationInfo *specInfo = pStages[i]->pSpecializationInfo;
4938 bool has_spec_info = specInfo ? true : false;
4939 write(fd_secure_input, &has_spec_info, sizeof(bool));
4940 if (specInfo) {
4941 write(fd_secure_input, &specInfo->dataSize, sizeof(size_t));
4942 write(fd_secure_input, specInfo->pData, specInfo->dataSize);
4943
4944 write(fd_secure_input, &specInfo->mapEntryCount, sizeof(uint32_t));
4945 for (uint32_t j = 0; j < specInfo->mapEntryCount; j++)
4946 write(fd_secure_input, &specInfo->pMapEntries[j], sizeof(VkSpecializationMapEntry));
4947 }
4948 }
4949
4950 /* Read the data returned from the secure process */
4951 while (sc_type != RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED) {
4952 if (!radv_sc_read(fd_secure_output, &sc_type, sizeof(sc_type), true))
4953 return VK_ERROR_DEVICE_LOST;
4954
4955 if (sc_type == RADV_SC_TYPE_WRITE_DISK_CACHE) {
4956 assert(device->physical_device->disk_cache);
4957
4958 uint8_t disk_sha1[20];
4959 if (!radv_sc_read(fd_secure_output, disk_sha1, sizeof(uint8_t) * 20, true))
4960 return VK_ERROR_DEVICE_LOST;
4961
4962 if (memcmp(disk_sha1, allowed_hashes[0], 20) &&
4963 memcmp(disk_sha1, allowed_hashes[1], 20))
4964 return VK_ERROR_DEVICE_LOST;
4965
4966 uint32_t entry_size;
4967 if (!radv_sc_read(fd_secure_output, &entry_size, sizeof(uint32_t), true))
4968 return VK_ERROR_DEVICE_LOST;
4969
4970 struct cache_entry *entry = malloc(entry_size);
4971 if (!radv_sc_read(fd_secure_output, entry, entry_size, true))
4972 return VK_ERROR_DEVICE_LOST;
4973
4974 disk_cache_put(device->physical_device->disk_cache,
4975 disk_sha1, entry, entry_size,
4976 NULL);
4977
4978 free(entry);
4979 } else if (sc_type == RADV_SC_TYPE_READ_DISK_CACHE) {
4980 uint8_t disk_sha1[20];
4981 if (!radv_sc_read(fd_secure_output, disk_sha1, sizeof(uint8_t) * 20, true))
4982 return VK_ERROR_DEVICE_LOST;
4983
4984 if (memcmp(disk_sha1, allowed_hashes[0], 20) &&
4985 memcmp(disk_sha1, allowed_hashes[1], 20))
4986 return VK_ERROR_DEVICE_LOST;
4987
4988 size_t size;
4989 struct cache_entry *entry = (struct cache_entry *)
4990 disk_cache_get(device->physical_device->disk_cache,
4991 disk_sha1, &size);
4992
4993 uint8_t found = entry ? 1 : 0;
4994 write(fd_secure_input, &found, sizeof(uint8_t));
4995
4996 if (found) {
4997 write(fd_secure_input, &size, sizeof(size_t));
4998 write(fd_secure_input, entry, size);
4999 }
5000
5001 free(entry);
5002 }
5003 }
5004
5005 sc_type = RADV_SC_TYPE_DESTROY_DEVICE;
5006 write(fd_secure_input, &sc_type, sizeof(sc_type));
5007
5008 mtx_lock(&device->sc_state->secure_compile_mutex);
5009 device->sc_state->secure_compile_thread_counter--;
5010 device->sc_state->secure_compile_processes[process].in_use = false;
5011 mtx_unlock(&device->sc_state->secure_compile_mutex);
5012
5013 return VK_SUCCESS;
5014 }
5015
5016 static VkResult
5017 radv_pipeline_init(struct radv_pipeline *pipeline,
5018 struct radv_device *device,
5019 struct radv_pipeline_cache *cache,
5020 const VkGraphicsPipelineCreateInfo *pCreateInfo,
5021 const struct radv_graphics_pipeline_create_info *extra)
5022 {
5023 VkResult result;
5024 bool has_view_index = false;
5025
5026 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
5027 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
5028 if (subpass->view_mask)
5029 has_view_index = true;
5030
5031 pipeline->device = device;
5032 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
5033 assert(pipeline->layout);
5034
5035 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
5036
5037 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
5038 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
5039 radv_init_feedback(creation_feedback);
5040
5041 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
5042
5043 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
5044 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
5045 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
5046 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
5047 pStages[stage] = &pCreateInfo->pStages[i];
5048 if(creation_feedback)
5049 stage_feedbacks[stage] = &creation_feedback->pPipelineStageCreationFeedbacks[i];
5050 }
5051
5052 struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index);
5053 if (radv_device_use_secure_compile(device->instance)) {
5054 return radv_secure_compile(pipeline, device, &key, pStages, pCreateInfo->flags, pCreateInfo->stageCount);
5055 } else {
5056 result = radv_create_shaders(pipeline, device, cache, &key, pStages,
5057 pCreateInfo->flags, pipeline_feedback,
5058 stage_feedbacks);
5059 if (result != VK_SUCCESS)
5060 return result;
5061 }
5062
5063 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
5064 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
5065 uint32_t gs_out;
5066 uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
5067
5068 pipeline->graphics.topology = pCreateInfo->pInputAssemblyState->topology;
5069 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
5070
5071 if (radv_pipeline_has_gs(pipeline)) {
5072 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
5073 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
5074 } else if (radv_pipeline_has_tess(pipeline)) {
5075 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode)
5076 gs_out = V_028A6C_OUTPRIM_TYPE_POINTLIST;
5077 else
5078 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.primitive_mode);
5079 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
5080 } else {
5081 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
5082 }
5083 if (extra && extra->use_rectlist) {
5084 prim = V_008958_DI_PT_RECTLIST;
5085 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
5086 pipeline->graphics.can_use_guardband = true;
5087 if (radv_pipeline_has_ngg(pipeline))
5088 gs_out = V_028A6C_VGT_OUT_RECT_V0;
5089 }
5090 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
5091 /* prim vertex count will need TESS changes */
5092 pipeline->graphics.prim_vertex_count = prim_size_table[prim];
5093
5094 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
5095
5096 /* Ensure that some export memory is always allocated, for two reasons:
5097 *
5098 * 1) Correctness: The hardware ignores the EXEC mask if no export
5099 * memory is allocated, so KILL and alpha test do not work correctly
5100 * without this.
5101 * 2) Performance: Every shader needs at least a NULL export, even when
5102 * it writes no color/depth output. The NULL export instruction
5103 * stalls without this setting.
5104 *
5105 * Don't add this to CB_SHADER_MASK.
5106 *
5107 * GFX10 supports pixel shaders without exports by setting both the
5108 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
5109 * instructions if any are present.
5110 */
5111 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
5112 if ((pipeline->device->physical_device->rad_info.chip_class <= GFX9 ||
5113 ps->info.ps.can_discard) &&
5114 !blend.spi_shader_col_format) {
5115 if (!ps->info.ps.writes_z &&
5116 !ps->info.ps.writes_stencil &&
5117 !ps->info.ps.writes_sample_mask)
5118 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
5119 }
5120
5121 blend.cb_shader_mask = ps->info.ps.cb_shader_mask;
5122 if (blend.mrt0_is_dual_src) {
5123 blend.cb_shader_mask |= (blend.cb_shader_mask & 0xf) << 4;
5124 }
5125
5126 if (extra &&
5127 (extra->custom_blend_mode == V_028808_CB_ELIMINATE_FAST_CLEAR ||
5128 extra->custom_blend_mode == V_028808_CB_FMASK_DECOMPRESS ||
5129 extra->custom_blend_mode == V_028808_CB_DCC_DECOMPRESS ||
5130 extra->custom_blend_mode == V_028808_CB_RESOLVE)) {
5131 /* According to the CB spec states, CB_SHADER_MASK should be
5132 * set to enable writes to all four channels of MRT0.
5133 */
5134 blend.cb_shader_mask = 0xf;
5135 }
5136
5137 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
5138 if (pipeline->shaders[i]) {
5139 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
5140 }
5141 }
5142
5143 if (radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
5144 struct radv_shader_variant *gs =
5145 pipeline->shaders[MESA_SHADER_GEOMETRY];
5146
5147 calculate_gs_ring_sizes(pipeline, &gs->info.gs_ring_info);
5148 }
5149
5150 struct radv_tessellation_state tess = {0};
5151 if (radv_pipeline_has_tess(pipeline)) {
5152 if (prim == V_008958_DI_PT_PATCH) {
5153 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
5154 pipeline->graphics.prim_vertex_count.incr = 1;
5155 }
5156 tess = calculate_tess_state(pipeline, pCreateInfo);
5157 }
5158
5159 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim);
5160
5161 radv_compute_vertex_input_state(pipeline, pCreateInfo);
5162
5163 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
5164 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
5165
5166 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
5167 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
5168 if (loc->sgpr_idx != -1) {
5169 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
5170 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
5171 if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id)
5172 pipeline->graphics.vtx_emit_num = 3;
5173 else
5174 pipeline->graphics.vtx_emit_num = 2;
5175 }
5176
5177 /* Find the last vertex shader stage that eventually uses streamout. */
5178 pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline);
5179
5180 result = radv_pipeline_scratch_init(device, pipeline);
5181 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, prim, gs_out);
5182
5183 return result;
5184 }
5185
5186 VkResult
5187 radv_graphics_pipeline_create(
5188 VkDevice _device,
5189 VkPipelineCache _cache,
5190 const VkGraphicsPipelineCreateInfo *pCreateInfo,
5191 const struct radv_graphics_pipeline_create_info *extra,
5192 const VkAllocationCallbacks *pAllocator,
5193 VkPipeline *pPipeline)
5194 {
5195 RADV_FROM_HANDLE(radv_device, device, _device);
5196 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
5197 struct radv_pipeline *pipeline;
5198 VkResult result;
5199
5200 pipeline = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8,
5201 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5202 if (pipeline == NULL)
5203 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5204
5205 vk_object_base_init(&device->vk, &pipeline->base,
5206 VK_OBJECT_TYPE_PIPELINE);
5207
5208 result = radv_pipeline_init(pipeline, device, cache,
5209 pCreateInfo, extra);
5210 if (result != VK_SUCCESS) {
5211 radv_pipeline_destroy(device, pipeline, pAllocator);
5212 return result;
5213 }
5214
5215 *pPipeline = radv_pipeline_to_handle(pipeline);
5216
5217 return VK_SUCCESS;
5218 }
5219
5220 VkResult radv_CreateGraphicsPipelines(
5221 VkDevice _device,
5222 VkPipelineCache pipelineCache,
5223 uint32_t count,
5224 const VkGraphicsPipelineCreateInfo* pCreateInfos,
5225 const VkAllocationCallbacks* pAllocator,
5226 VkPipeline* pPipelines)
5227 {
5228 VkResult result = VK_SUCCESS;
5229 unsigned i = 0;
5230
5231 for (; i < count; i++) {
5232 VkResult r;
5233 r = radv_graphics_pipeline_create(_device,
5234 pipelineCache,
5235 &pCreateInfos[i],
5236 NULL, pAllocator, &pPipelines[i]);
5237 if (r != VK_SUCCESS) {
5238 result = r;
5239 pPipelines[i] = VK_NULL_HANDLE;
5240
5241 if (pCreateInfos[i].flags & VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT)
5242 break;
5243 }
5244 }
5245
5246 for (; i < count; ++i)
5247 pPipelines[i] = VK_NULL_HANDLE;
5248
5249 return result;
5250 }
5251
5252
5253 static void
5254 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
5255 {
5256 struct radv_shader_variant *compute_shader;
5257 struct radv_device *device = pipeline->device;
5258 unsigned threads_per_threadgroup;
5259 unsigned threadgroups_per_cu = 1;
5260 unsigned waves_per_threadgroup;
5261 unsigned max_waves_per_sh = 0;
5262 uint64_t va;
5263
5264 pipeline->cs.max_dw = device->physical_device->rad_info.chip_class >= GFX10 ? 22 : 20;
5265 pipeline->cs.buf = malloc(pipeline->cs.max_dw * 4);
5266
5267 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5268 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
5269
5270 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
5271 radeon_emit(&pipeline->cs, va >> 8);
5272 radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40));
5273
5274 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
5275 radeon_emit(&pipeline->cs, compute_shader->config.rsrc1);
5276 radeon_emit(&pipeline->cs, compute_shader->config.rsrc2);
5277 if (device->physical_device->rad_info.chip_class >= GFX10) {
5278 radeon_set_sh_reg(&pipeline->cs, R_00B8A0_COMPUTE_PGM_RSRC3, compute_shader->config.rsrc3);
5279 }
5280
5281 /* Calculate best compute resource limits. */
5282 threads_per_threadgroup = compute_shader->info.cs.block_size[0] *
5283 compute_shader->info.cs.block_size[1] *
5284 compute_shader->info.cs.block_size[2];
5285 waves_per_threadgroup = DIV_ROUND_UP(threads_per_threadgroup,
5286 compute_shader->info.wave_size);
5287
5288 if (device->physical_device->rad_info.chip_class >= GFX10 &&
5289 waves_per_threadgroup == 1)
5290 threadgroups_per_cu = 2;
5291
5292 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
5293 ac_get_compute_resource_limits(&device->physical_device->rad_info,
5294 waves_per_threadgroup,
5295 max_waves_per_sh,
5296 threadgroups_per_cu));
5297
5298 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5299 radeon_emit(&pipeline->cs,
5300 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
5301 radeon_emit(&pipeline->cs,
5302 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
5303 radeon_emit(&pipeline->cs,
5304 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
5305
5306 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
5307 }
5308
5309 static struct radv_pipeline_key
5310 radv_generate_compute_pipeline_key(struct radv_pipeline *pipeline,
5311 const VkComputePipelineCreateInfo *pCreateInfo)
5312 {
5313 const VkPipelineShaderStageCreateInfo *stage = &pCreateInfo->stage;
5314 struct radv_pipeline_key key;
5315 memset(&key, 0, sizeof(key));
5316
5317 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
5318 key.optimisations_disabled = 1;
5319
5320 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT *subgroup_size =
5321 vk_find_struct_const(stage->pNext,
5322 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT);
5323
5324 if (subgroup_size) {
5325 assert(subgroup_size->requiredSubgroupSize == 32 ||
5326 subgroup_size->requiredSubgroupSize == 64);
5327 key.compute_subgroup_size = subgroup_size->requiredSubgroupSize;
5328 }
5329
5330 return key;
5331 }
5332
5333 static VkResult radv_compute_pipeline_create(
5334 VkDevice _device,
5335 VkPipelineCache _cache,
5336 const VkComputePipelineCreateInfo* pCreateInfo,
5337 const VkAllocationCallbacks* pAllocator,
5338 VkPipeline* pPipeline)
5339 {
5340 RADV_FROM_HANDLE(radv_device, device, _device);
5341 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
5342 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
5343 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
5344 struct radv_pipeline *pipeline;
5345 VkResult result;
5346
5347 pipeline = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8,
5348 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5349 if (pipeline == NULL)
5350 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5351
5352 vk_object_base_init(&device->vk, &pipeline->base,
5353 VK_OBJECT_TYPE_PIPELINE);
5354
5355 pipeline->device = device;
5356 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
5357 assert(pipeline->layout);
5358
5359 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
5360 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
5361 radv_init_feedback(creation_feedback);
5362
5363 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
5364 if (creation_feedback)
5365 stage_feedbacks[MESA_SHADER_COMPUTE] = &creation_feedback->pPipelineStageCreationFeedbacks[0];
5366
5367 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
5368
5369 struct radv_pipeline_key key =
5370 radv_generate_compute_pipeline_key(pipeline, pCreateInfo);
5371
5372 if (radv_device_use_secure_compile(device->instance)) {
5373 result = radv_secure_compile(pipeline, device, &key, pStages, pCreateInfo->flags, 1);
5374 *pPipeline = radv_pipeline_to_handle(pipeline);
5375
5376 return result;
5377 } else {
5378 result = radv_create_shaders(pipeline, device, cache, &key, pStages,
5379 pCreateInfo->flags, pipeline_feedback,
5380 stage_feedbacks);
5381 if (result != VK_SUCCESS) {
5382 radv_pipeline_destroy(device, pipeline, pAllocator);
5383 return result;
5384 }
5385 }
5386
5387 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
5388 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
5389 result = radv_pipeline_scratch_init(device, pipeline);
5390 if (result != VK_SUCCESS) {
5391 radv_pipeline_destroy(device, pipeline, pAllocator);
5392 return result;
5393 }
5394
5395 radv_compute_generate_pm4(pipeline);
5396
5397 *pPipeline = radv_pipeline_to_handle(pipeline);
5398
5399 return VK_SUCCESS;
5400 }
5401
5402 VkResult radv_CreateComputePipelines(
5403 VkDevice _device,
5404 VkPipelineCache pipelineCache,
5405 uint32_t count,
5406 const VkComputePipelineCreateInfo* pCreateInfos,
5407 const VkAllocationCallbacks* pAllocator,
5408 VkPipeline* pPipelines)
5409 {
5410 VkResult result = VK_SUCCESS;
5411
5412 unsigned i = 0;
5413 for (; i < count; i++) {
5414 VkResult r;
5415 r = radv_compute_pipeline_create(_device, pipelineCache,
5416 &pCreateInfos[i],
5417 pAllocator, &pPipelines[i]);
5418 if (r != VK_SUCCESS) {
5419 result = r;
5420 pPipelines[i] = VK_NULL_HANDLE;
5421
5422 if (pCreateInfos[i].flags & VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT)
5423 break;
5424 }
5425 }
5426
5427 for (; i < count; ++i)
5428 pPipelines[i] = VK_NULL_HANDLE;
5429
5430 return result;
5431 }
5432
5433
5434 static uint32_t radv_get_executable_count(const struct radv_pipeline *pipeline)
5435 {
5436 uint32_t ret = 0;
5437 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5438 if (!pipeline->shaders[i])
5439 continue;
5440
5441 if (i == MESA_SHADER_GEOMETRY &&
5442 !radv_pipeline_has_ngg(pipeline)) {
5443 ret += 2u;
5444 } else {
5445 ret += 1u;
5446 }
5447
5448 }
5449 return ret;
5450 }
5451
5452 static struct radv_shader_variant *
5453 radv_get_shader_from_executable_index(const struct radv_pipeline *pipeline, int index, gl_shader_stage *stage)
5454 {
5455 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5456 if (!pipeline->shaders[i])
5457 continue;
5458 if (!index) {
5459 *stage = i;
5460 return pipeline->shaders[i];
5461 }
5462
5463 --index;
5464
5465 if (i == MESA_SHADER_GEOMETRY &&
5466 !radv_pipeline_has_ngg(pipeline)) {
5467 if (!index) {
5468 *stage = i;
5469 return pipeline->gs_copy_shader;
5470 }
5471 --index;
5472 }
5473 }
5474
5475 *stage = -1;
5476 return NULL;
5477 }
5478
5479 /* Basically strlcpy (which does not exist on linux) specialized for
5480 * descriptions. */
5481 static void desc_copy(char *desc, const char *src) {
5482 int len = strlen(src);
5483 assert(len < VK_MAX_DESCRIPTION_SIZE);
5484 memcpy(desc, src, len);
5485 memset(desc + len, 0, VK_MAX_DESCRIPTION_SIZE - len);
5486 }
5487
5488 VkResult radv_GetPipelineExecutablePropertiesKHR(
5489 VkDevice _device,
5490 const VkPipelineInfoKHR* pPipelineInfo,
5491 uint32_t* pExecutableCount,
5492 VkPipelineExecutablePropertiesKHR* pProperties)
5493 {
5494 RADV_FROM_HANDLE(radv_pipeline, pipeline, pPipelineInfo->pipeline);
5495 const uint32_t total_count = radv_get_executable_count(pipeline);
5496
5497 if (!pProperties) {
5498 *pExecutableCount = total_count;
5499 return VK_SUCCESS;
5500 }
5501
5502 const uint32_t count = MIN2(total_count, *pExecutableCount);
5503 for (unsigned i = 0, executable_idx = 0;
5504 i < MESA_SHADER_STAGES && executable_idx < count; ++i) {
5505 if (!pipeline->shaders[i])
5506 continue;
5507 pProperties[executable_idx].stages = mesa_to_vk_shader_stage(i);
5508 const char *name = NULL;
5509 const char *description = NULL;
5510 switch(i) {
5511 case MESA_SHADER_VERTEX:
5512 name = "Vertex Shader";
5513 description = "Vulkan Vertex Shader";
5514 break;
5515 case MESA_SHADER_TESS_CTRL:
5516 if (!pipeline->shaders[MESA_SHADER_VERTEX]) {
5517 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5518 name = "Vertex + Tessellation Control Shaders";
5519 description = "Combined Vulkan Vertex and Tessellation Control Shaders";
5520 } else {
5521 name = "Tessellation Control Shader";
5522 description = "Vulkan Tessellation Control Shader";
5523 }
5524 break;
5525 case MESA_SHADER_TESS_EVAL:
5526 name = "Tessellation Evaluation Shader";
5527 description = "Vulkan Tessellation Evaluation Shader";
5528 break;
5529 case MESA_SHADER_GEOMETRY:
5530 if (radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
5531 pProperties[executable_idx].stages |= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT;
5532 name = "Tessellation Evaluation + Geometry Shaders";
5533 description = "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5534 } else if (!radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_VERTEX]) {
5535 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5536 name = "Vertex + Geometry Shader";
5537 description = "Combined Vulkan Vertex and Geometry Shaders";
5538 } else {
5539 name = "Geometry Shader";
5540 description = "Vulkan Geometry Shader";
5541 }
5542 break;
5543 case MESA_SHADER_FRAGMENT:
5544 name = "Fragment Shader";
5545 description = "Vulkan Fragment Shader";
5546 break;
5547 case MESA_SHADER_COMPUTE:
5548 name = "Compute Shader";
5549 description = "Vulkan Compute Shader";
5550 break;
5551 }
5552
5553 pProperties[executable_idx].subgroupSize = pipeline->shaders[i]->info.wave_size;
5554 desc_copy(pProperties[executable_idx].name, name);
5555 desc_copy(pProperties[executable_idx].description, description);
5556
5557 ++executable_idx;
5558 if (i == MESA_SHADER_GEOMETRY &&
5559 !radv_pipeline_has_ngg(pipeline)) {
5560 assert(pipeline->gs_copy_shader);
5561 if (executable_idx >= count)
5562 break;
5563
5564 pProperties[executable_idx].stages = VK_SHADER_STAGE_GEOMETRY_BIT;
5565 pProperties[executable_idx].subgroupSize = 64;
5566 desc_copy(pProperties[executable_idx].name, "GS Copy Shader");
5567 desc_copy(pProperties[executable_idx].description,
5568 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5569
5570 ++executable_idx;
5571 }
5572 }
5573
5574 VkResult result = *pExecutableCount < total_count ? VK_INCOMPLETE : VK_SUCCESS;
5575 *pExecutableCount = count;
5576 return result;
5577 }
5578
5579 VkResult radv_GetPipelineExecutableStatisticsKHR(
5580 VkDevice _device,
5581 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5582 uint32_t* pStatisticCount,
5583 VkPipelineExecutableStatisticKHR* pStatistics)
5584 {
5585 RADV_FROM_HANDLE(radv_device, device, _device);
5586 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5587 gl_shader_stage stage;
5588 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5589
5590 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
5591 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
5592 unsigned max_waves = radv_get_max_waves(device, shader, stage);
5593
5594 VkPipelineExecutableStatisticKHR *s = pStatistics;
5595 VkPipelineExecutableStatisticKHR *end = s + (pStatistics ? *pStatisticCount : 0);
5596 VkResult result = VK_SUCCESS;
5597
5598 if (s < end) {
5599 desc_copy(s->name, "SGPRs");
5600 desc_copy(s->description, "Number of SGPR registers allocated per subgroup");
5601 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5602 s->value.u64 = shader->config.num_sgprs;
5603 }
5604 ++s;
5605
5606 if (s < end) {
5607 desc_copy(s->name, "VGPRs");
5608 desc_copy(s->description, "Number of VGPR registers allocated per subgroup");
5609 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5610 s->value.u64 = shader->config.num_vgprs;
5611 }
5612 ++s;
5613
5614 if (s < end) {
5615 desc_copy(s->name, "Spilled SGPRs");
5616 desc_copy(s->description, "Number of SGPR registers spilled per subgroup");
5617 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5618 s->value.u64 = shader->config.spilled_sgprs;
5619 }
5620 ++s;
5621
5622 if (s < end) {
5623 desc_copy(s->name, "Spilled VGPRs");
5624 desc_copy(s->description, "Number of VGPR registers spilled per subgroup");
5625 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5626 s->value.u64 = shader->config.spilled_vgprs;
5627 }
5628 ++s;
5629
5630 if (s < end) {
5631 desc_copy(s->name, "PrivMem VGPRs");
5632 desc_copy(s->description, "Number of VGPRs stored in private memory per subgroup");
5633 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5634 s->value.u64 = shader->info.private_mem_vgprs;
5635 }
5636 ++s;
5637
5638 if (s < end) {
5639 desc_copy(s->name, "Code size");
5640 desc_copy(s->description, "Code size in bytes");
5641 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5642 s->value.u64 = shader->exec_size;
5643 }
5644 ++s;
5645
5646 if (s < end) {
5647 desc_copy(s->name, "LDS size");
5648 desc_copy(s->description, "LDS size in bytes per workgroup");
5649 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5650 s->value.u64 = shader->config.lds_size * lds_increment;
5651 }
5652 ++s;
5653
5654 if (s < end) {
5655 desc_copy(s->name, "Scratch size");
5656 desc_copy(s->description, "Private memory in bytes per subgroup");
5657 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5658 s->value.u64 = shader->config.scratch_bytes_per_wave;
5659 }
5660 ++s;
5661
5662 if (s < end) {
5663 desc_copy(s->name, "Subgroups per SIMD");
5664 desc_copy(s->description, "The maximum number of subgroups in flight on a SIMD unit");
5665 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5666 s->value.u64 = max_waves;
5667 }
5668 ++s;
5669
5670 if (shader->statistics) {
5671 for (unsigned i = 0; i < shader->statistics->count; i++) {
5672 struct radv_compiler_statistic_info *info = &shader->statistics->infos[i];
5673 uint32_t value = shader->statistics->values[i];
5674 if (s < end) {
5675 desc_copy(s->name, info->name);
5676 desc_copy(s->description, info->desc);
5677 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5678 s->value.u64 = value;
5679 }
5680 ++s;
5681 }
5682 }
5683
5684 if (!pStatistics)
5685 *pStatisticCount = s - pStatistics;
5686 else if (s > end) {
5687 *pStatisticCount = end - pStatistics;
5688 result = VK_INCOMPLETE;
5689 } else {
5690 *pStatisticCount = s - pStatistics;
5691 }
5692
5693 return result;
5694 }
5695
5696 static VkResult radv_copy_representation(void *data, size_t *data_size, const char *src)
5697 {
5698 size_t total_size = strlen(src) + 1;
5699
5700 if (!data) {
5701 *data_size = total_size;
5702 return VK_SUCCESS;
5703 }
5704
5705 size_t size = MIN2(total_size, *data_size);
5706
5707 memcpy(data, src, size);
5708 if (size)
5709 *((char*)data + size - 1) = 0;
5710 return size < total_size ? VK_INCOMPLETE : VK_SUCCESS;
5711 }
5712
5713 VkResult radv_GetPipelineExecutableInternalRepresentationsKHR(
5714 VkDevice device,
5715 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5716 uint32_t* pInternalRepresentationCount,
5717 VkPipelineExecutableInternalRepresentationKHR* pInternalRepresentations)
5718 {
5719 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5720 gl_shader_stage stage;
5721 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5722
5723 VkPipelineExecutableInternalRepresentationKHR *p = pInternalRepresentations;
5724 VkPipelineExecutableInternalRepresentationKHR *end = p + (pInternalRepresentations ? *pInternalRepresentationCount : 0);
5725 VkResult result = VK_SUCCESS;
5726 /* optimized NIR */
5727 if (p < end) {
5728 p->isText = true;
5729 desc_copy(p->name, "NIR Shader(s)");
5730 desc_copy(p->description, "The optimized NIR shader(s)");
5731 if (radv_copy_representation(p->pData, &p->dataSize, shader->nir_string) != VK_SUCCESS)
5732 result = VK_INCOMPLETE;
5733 }
5734 ++p;
5735
5736 /* backend IR */
5737 if (p < end) {
5738 p->isText = true;
5739 if (pipeline->device->physical_device->use_aco) {
5740 desc_copy(p->name, "ACO IR");
5741 desc_copy(p->description, "The ACO IR after some optimizations");
5742 } else {
5743 desc_copy(p->name, "LLVM IR");
5744 desc_copy(p->description, "The LLVM IR after some optimizations");
5745 }
5746 if (radv_copy_representation(p->pData, &p->dataSize, shader->ir_string) != VK_SUCCESS)
5747 result = VK_INCOMPLETE;
5748 }
5749 ++p;
5750
5751 /* Disassembler */
5752 if (p < end) {
5753 p->isText = true;
5754 desc_copy(p->name, "Assembly");
5755 desc_copy(p->description, "Final Assembly");
5756 if (radv_copy_representation(p->pData, &p->dataSize, shader->disasm_string) != VK_SUCCESS)
5757 result = VK_INCOMPLETE;
5758 }
5759 ++p;
5760
5761 if (!pInternalRepresentations)
5762 *pInternalRepresentationCount = p - pInternalRepresentations;
5763 else if(p > end) {
5764 result = VK_INCOMPLETE;
5765 *pInternalRepresentationCount = end - pInternalRepresentations;
5766 } else {
5767 *pInternalRepresentationCount = p - pInternalRepresentations;
5768 }
5769
5770 return result;
5771 }