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radv: remove one unnecessary param to radv_generate_graphics_pipeline_key()
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
33 #include "radv_cs.h"
34 #include "radv_shader.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
39 #include "vk_util.h"
40
41 #include "sid.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
48 #include "ac_shader_util.h"
49
50 struct radv_blend_state {
51 uint32_t blend_enable_4bit;
52 uint32_t need_src_alpha;
53
54 uint32_t cb_color_control;
55 uint32_t cb_target_mask;
56 uint32_t cb_target_enabled_4bit;
57 uint32_t sx_mrt_blend_opt[8];
58 uint32_t cb_blend_control[8];
59
60 uint32_t spi_shader_col_format;
61 uint32_t col_format_is_int8;
62 uint32_t col_format_is_int10;
63 uint32_t cb_shader_mask;
64 uint32_t db_alpha_to_mask;
65
66 uint32_t commutative_4bit;
67
68 bool single_cb_enable;
69 bool mrt0_is_dual_src;
70 };
71
72 struct radv_dsa_order_invariance {
73 /* Whether the final result in Z/S buffers is guaranteed to be
74 * invariant under changes to the order in which fragments arrive.
75 */
76 bool zs;
77
78 /* Whether the set of fragments that pass the combined Z/S test is
79 * guaranteed to be invariant under changes to the order in which
80 * fragments arrive.
81 */
82 bool pass_set;
83 };
84
85 struct radv_tessellation_state {
86 uint32_t ls_hs_config;
87 unsigned lds_size;
88 uint32_t tf_param;
89 };
90
91 static const VkPipelineMultisampleStateCreateInfo *
92 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
93 {
94 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
95 return pCreateInfo->pMultisampleState;
96 return NULL;
97 }
98
99 static const VkPipelineTessellationStateCreateInfo *
100 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
101 {
102 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
103 if (pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT ||
104 pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) {
105 return pCreateInfo->pTessellationState;
106 }
107 }
108 return NULL;
109 }
110
111 static const VkPipelineDepthStencilStateCreateInfo *
112 radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
113 {
114 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
115 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
116
117 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
118 subpass->depth_stencil_attachment)
119 return pCreateInfo->pDepthStencilState;
120 return NULL;
121 }
122
123 static const VkPipelineColorBlendStateCreateInfo *
124 radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
125 {
126 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
127 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
128
129 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
130 subpass->has_color_att)
131 return pCreateInfo->pColorBlendState;
132 return NULL;
133 }
134
135 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline)
136 {
137 struct radv_shader_variant *variant = NULL;
138 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
139 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
140 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
141 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
142 else if (pipeline->shaders[MESA_SHADER_VERTEX])
143 variant = pipeline->shaders[MESA_SHADER_VERTEX];
144 else
145 return false;
146 return variant->info.is_ngg;
147 }
148
149 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline *pipeline)
150 {
151 assert(radv_pipeline_has_ngg(pipeline));
152
153 struct radv_shader_variant *variant = NULL;
154 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
155 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
156 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
157 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
158 else if (pipeline->shaders[MESA_SHADER_VERTEX])
159 variant = pipeline->shaders[MESA_SHADER_VERTEX];
160 else
161 return false;
162 return variant->info.is_ngg_passthrough;
163 }
164
165 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline)
166 {
167 if (!radv_pipeline_has_gs(pipeline))
168 return false;
169
170 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
171 * On GFX10, it might be required in rare cases if it's not possible to
172 * enable NGG.
173 */
174 if (radv_pipeline_has_ngg(pipeline))
175 return false;
176
177 assert(pipeline->gs_copy_shader);
178 return true;
179 }
180
181 static void
182 radv_pipeline_destroy(struct radv_device *device,
183 struct radv_pipeline *pipeline,
184 const VkAllocationCallbacks* allocator)
185 {
186 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
187 if (pipeline->shaders[i])
188 radv_shader_variant_destroy(device, pipeline->shaders[i]);
189
190 if (pipeline->gs_copy_shader)
191 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
192
193 if(pipeline->cs.buf)
194 free(pipeline->cs.buf);
195
196 vk_object_base_finish(&pipeline->base);
197 vk_free2(&device->vk.alloc, allocator, pipeline);
198 }
199
200 void radv_DestroyPipeline(
201 VkDevice _device,
202 VkPipeline _pipeline,
203 const VkAllocationCallbacks* pAllocator)
204 {
205 RADV_FROM_HANDLE(radv_device, device, _device);
206 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
207
208 if (!_pipeline)
209 return;
210
211 radv_pipeline_destroy(device, pipeline, pAllocator);
212 }
213
214 static uint32_t get_hash_flags(struct radv_device *device)
215 {
216 uint32_t hash_flags = 0;
217
218 if (device->instance->debug_flags & RADV_DEBUG_NO_NGG)
219 hash_flags |= RADV_HASH_SHADER_NO_NGG;
220 if (device->physical_device->cs_wave_size == 32)
221 hash_flags |= RADV_HASH_SHADER_CS_WAVE32;
222 if (device->physical_device->ps_wave_size == 32)
223 hash_flags |= RADV_HASH_SHADER_PS_WAVE32;
224 if (device->physical_device->ge_wave_size == 32)
225 hash_flags |= RADV_HASH_SHADER_GE_WAVE32;
226 if (device->physical_device->use_llvm)
227 hash_flags |= RADV_HASH_SHADER_LLVM;
228 return hash_flags;
229 }
230
231 static VkResult
232 radv_pipeline_scratch_init(struct radv_device *device,
233 struct radv_pipeline *pipeline)
234 {
235 unsigned scratch_bytes_per_wave = 0;
236 unsigned max_waves = 0;
237 unsigned min_waves = 1;
238
239 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
240 if (pipeline->shaders[i] &&
241 pipeline->shaders[i]->config.scratch_bytes_per_wave) {
242 unsigned max_stage_waves = device->scratch_waves;
243
244 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
245 pipeline->shaders[i]->config.scratch_bytes_per_wave);
246
247 max_stage_waves = MIN2(max_stage_waves,
248 4 * device->physical_device->rad_info.num_good_compute_units *
249 (256 / pipeline->shaders[i]->config.num_vgprs));
250 max_waves = MAX2(max_waves, max_stage_waves);
251 }
252 }
253
254 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
255 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
256 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
257 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
258 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
259 }
260
261 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
262 pipeline->max_waves = max_waves;
263 return VK_SUCCESS;
264 }
265
266 static uint32_t si_translate_blend_logic_op(VkLogicOp op)
267 {
268 switch (op) {
269 case VK_LOGIC_OP_CLEAR:
270 return V_028808_ROP3_CLEAR;
271 case VK_LOGIC_OP_AND:
272 return V_028808_ROP3_AND;
273 case VK_LOGIC_OP_AND_REVERSE:
274 return V_028808_ROP3_AND_REVERSE;
275 case VK_LOGIC_OP_COPY:
276 return V_028808_ROP3_COPY;
277 case VK_LOGIC_OP_AND_INVERTED:
278 return V_028808_ROP3_AND_INVERTED;
279 case VK_LOGIC_OP_NO_OP:
280 return V_028808_ROP3_NO_OP;
281 case VK_LOGIC_OP_XOR:
282 return V_028808_ROP3_XOR;
283 case VK_LOGIC_OP_OR:
284 return V_028808_ROP3_OR;
285 case VK_LOGIC_OP_NOR:
286 return V_028808_ROP3_NOR;
287 case VK_LOGIC_OP_EQUIVALENT:
288 return V_028808_ROP3_EQUIVALENT;
289 case VK_LOGIC_OP_INVERT:
290 return V_028808_ROP3_INVERT;
291 case VK_LOGIC_OP_OR_REVERSE:
292 return V_028808_ROP3_OR_REVERSE;
293 case VK_LOGIC_OP_COPY_INVERTED:
294 return V_028808_ROP3_COPY_INVERTED;
295 case VK_LOGIC_OP_OR_INVERTED:
296 return V_028808_ROP3_OR_INVERTED;
297 case VK_LOGIC_OP_NAND:
298 return V_028808_ROP3_NAND;
299 case VK_LOGIC_OP_SET:
300 return V_028808_ROP3_SET;
301 default:
302 unreachable("Unhandled logic op");
303 }
304 }
305
306
307 static uint32_t si_translate_blend_function(VkBlendOp op)
308 {
309 switch (op) {
310 case VK_BLEND_OP_ADD:
311 return V_028780_COMB_DST_PLUS_SRC;
312 case VK_BLEND_OP_SUBTRACT:
313 return V_028780_COMB_SRC_MINUS_DST;
314 case VK_BLEND_OP_REVERSE_SUBTRACT:
315 return V_028780_COMB_DST_MINUS_SRC;
316 case VK_BLEND_OP_MIN:
317 return V_028780_COMB_MIN_DST_SRC;
318 case VK_BLEND_OP_MAX:
319 return V_028780_COMB_MAX_DST_SRC;
320 default:
321 return 0;
322 }
323 }
324
325 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
326 {
327 switch (factor) {
328 case VK_BLEND_FACTOR_ZERO:
329 return V_028780_BLEND_ZERO;
330 case VK_BLEND_FACTOR_ONE:
331 return V_028780_BLEND_ONE;
332 case VK_BLEND_FACTOR_SRC_COLOR:
333 return V_028780_BLEND_SRC_COLOR;
334 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
335 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
336 case VK_BLEND_FACTOR_DST_COLOR:
337 return V_028780_BLEND_DST_COLOR;
338 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
339 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
340 case VK_BLEND_FACTOR_SRC_ALPHA:
341 return V_028780_BLEND_SRC_ALPHA;
342 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
343 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
344 case VK_BLEND_FACTOR_DST_ALPHA:
345 return V_028780_BLEND_DST_ALPHA;
346 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
347 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
348 case VK_BLEND_FACTOR_CONSTANT_COLOR:
349 return V_028780_BLEND_CONSTANT_COLOR;
350 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
351 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
352 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
353 return V_028780_BLEND_CONSTANT_ALPHA;
354 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
355 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
356 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
357 return V_028780_BLEND_SRC_ALPHA_SATURATE;
358 case VK_BLEND_FACTOR_SRC1_COLOR:
359 return V_028780_BLEND_SRC1_COLOR;
360 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
361 return V_028780_BLEND_INV_SRC1_COLOR;
362 case VK_BLEND_FACTOR_SRC1_ALPHA:
363 return V_028780_BLEND_SRC1_ALPHA;
364 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
365 return V_028780_BLEND_INV_SRC1_ALPHA;
366 default:
367 return 0;
368 }
369 }
370
371 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
372 {
373 switch (op) {
374 case VK_BLEND_OP_ADD:
375 return V_028760_OPT_COMB_ADD;
376 case VK_BLEND_OP_SUBTRACT:
377 return V_028760_OPT_COMB_SUBTRACT;
378 case VK_BLEND_OP_REVERSE_SUBTRACT:
379 return V_028760_OPT_COMB_REVSUBTRACT;
380 case VK_BLEND_OP_MIN:
381 return V_028760_OPT_COMB_MIN;
382 case VK_BLEND_OP_MAX:
383 return V_028760_OPT_COMB_MAX;
384 default:
385 return V_028760_OPT_COMB_BLEND_DISABLED;
386 }
387 }
388
389 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
390 {
391 switch (factor) {
392 case VK_BLEND_FACTOR_ZERO:
393 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
394 case VK_BLEND_FACTOR_ONE:
395 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
396 case VK_BLEND_FACTOR_SRC_COLOR:
397 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
398 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
399 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
400 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
401 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
402 case VK_BLEND_FACTOR_SRC_ALPHA:
403 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
404 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
405 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
406 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
407 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
408 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
409 default:
410 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
411 }
412 }
413
414 /**
415 * Get rid of DST in the blend factors by commuting the operands:
416 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
417 */
418 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
419 unsigned *dst_factor, unsigned expected_dst,
420 unsigned replacement_src)
421 {
422 if (*src_factor == expected_dst &&
423 *dst_factor == VK_BLEND_FACTOR_ZERO) {
424 *src_factor = VK_BLEND_FACTOR_ZERO;
425 *dst_factor = replacement_src;
426
427 /* Commuting the operands requires reversing subtractions. */
428 if (*func == VK_BLEND_OP_SUBTRACT)
429 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
430 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
431 *func = VK_BLEND_OP_SUBTRACT;
432 }
433 }
434
435 static bool si_blend_factor_uses_dst(unsigned factor)
436 {
437 return factor == VK_BLEND_FACTOR_DST_COLOR ||
438 factor == VK_BLEND_FACTOR_DST_ALPHA ||
439 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
440 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
441 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
442 }
443
444 static bool is_dual_src(VkBlendFactor factor)
445 {
446 switch (factor) {
447 case VK_BLEND_FACTOR_SRC1_COLOR:
448 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
449 case VK_BLEND_FACTOR_SRC1_ALPHA:
450 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
451 return true;
452 default:
453 return false;
454 }
455 }
456
457 static unsigned radv_choose_spi_color_format(VkFormat vk_format,
458 bool blend_enable,
459 bool blend_need_alpha)
460 {
461 const struct vk_format_description *desc = vk_format_description(vk_format);
462 struct ac_spi_color_formats formats = {};
463 unsigned format, ntype, swap;
464
465 format = radv_translate_colorformat(vk_format);
466 ntype = radv_translate_color_numformat(vk_format, desc,
467 vk_format_get_first_non_void_channel(vk_format));
468 swap = radv_translate_colorswap(vk_format, false);
469
470 ac_choose_spi_color_formats(format, swap, ntype, false, &formats);
471
472 if (blend_enable && blend_need_alpha)
473 return formats.blend_alpha;
474 else if(blend_need_alpha)
475 return formats.alpha;
476 else if(blend_enable)
477 return formats.blend;
478 else
479 return formats.normal;
480 }
481
482 static bool
483 format_is_int8(VkFormat format)
484 {
485 const struct vk_format_description *desc = vk_format_description(format);
486 int channel = vk_format_get_first_non_void_channel(format);
487
488 return channel >= 0 && desc->channel[channel].pure_integer &&
489 desc->channel[channel].size == 8;
490 }
491
492 static bool
493 format_is_int10(VkFormat format)
494 {
495 const struct vk_format_description *desc = vk_format_description(format);
496
497 if (desc->nr_channels != 4)
498 return false;
499 for (unsigned i = 0; i < 4; i++) {
500 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
501 return true;
502 }
503 return false;
504 }
505
506 static void
507 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
508 const VkGraphicsPipelineCreateInfo *pCreateInfo,
509 struct radv_blend_state *blend)
510 {
511 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
512 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
513 unsigned col_format = 0, is_int8 = 0, is_int10 = 0;
514 unsigned num_targets;
515
516 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
517 unsigned cf;
518
519 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED ||
520 !(blend->cb_target_mask & (0xfu << (i * 4)))) {
521 cf = V_028714_SPI_SHADER_ZERO;
522 } else {
523 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
524 bool blend_enable =
525 blend->blend_enable_4bit & (0xfu << (i * 4));
526
527 cf = radv_choose_spi_color_format(attachment->format,
528 blend_enable,
529 blend->need_src_alpha & (1 << i));
530
531 if (format_is_int8(attachment->format))
532 is_int8 |= 1 << i;
533 if (format_is_int10(attachment->format))
534 is_int10 |= 1 << i;
535 }
536
537 col_format |= cf << (4 * i);
538 }
539
540 if (!(col_format & 0xf) && blend->need_src_alpha & (1 << 0)) {
541 /* When a subpass doesn't have any color attachments, write the
542 * alpha channel of MRT0 when alpha coverage is enabled because
543 * the depth attachment needs it.
544 */
545 col_format |= V_028714_SPI_SHADER_32_AR;
546 }
547
548 /* If the i-th target format is set, all previous target formats must
549 * be non-zero to avoid hangs.
550 */
551 num_targets = (util_last_bit(col_format) + 3) / 4;
552 for (unsigned i = 0; i < num_targets; i++) {
553 if (!(col_format & (0xf << (i * 4)))) {
554 col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
555 }
556 }
557
558 /* The output for dual source blending should have the same format as
559 * the first output.
560 */
561 if (blend->mrt0_is_dual_src)
562 col_format |= (col_format & 0xf) << 4;
563
564 blend->spi_shader_col_format = col_format;
565 blend->col_format_is_int8 = is_int8;
566 blend->col_format_is_int10 = is_int10;
567 }
568
569 /*
570 * Ordered so that for each i,
571 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
572 */
573 const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = {
574 VK_FORMAT_R32_SFLOAT,
575 VK_FORMAT_R32G32_SFLOAT,
576 VK_FORMAT_R8G8B8A8_UNORM,
577 VK_FORMAT_R16G16B16A16_UNORM,
578 VK_FORMAT_R16G16B16A16_SNORM,
579 VK_FORMAT_R16G16B16A16_UINT,
580 VK_FORMAT_R16G16B16A16_SINT,
581 VK_FORMAT_R32G32B32A32_SFLOAT,
582 VK_FORMAT_R8G8B8A8_UINT,
583 VK_FORMAT_R8G8B8A8_SINT,
584 VK_FORMAT_A2R10G10B10_UINT_PACK32,
585 VK_FORMAT_A2R10G10B10_SINT_PACK32,
586 };
587
588 unsigned radv_format_meta_fs_key(VkFormat format)
589 {
590 unsigned col_format = radv_choose_spi_color_format(format, false, false);
591
592 assert(col_format != V_028714_SPI_SHADER_32_AR);
593 if (col_format >= V_028714_SPI_SHADER_32_AR)
594 --col_format; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
595
596 --col_format; /* Skip V_028714_SPI_SHADER_ZERO */
597 bool is_int8 = format_is_int8(format);
598 bool is_int10 = format_is_int10(format);
599
600 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
601 }
602
603 static void
604 radv_blend_check_commutativity(struct radv_blend_state *blend,
605 VkBlendOp op, VkBlendFactor src,
606 VkBlendFactor dst, unsigned chanmask)
607 {
608 /* Src factor is allowed when it does not depend on Dst. */
609 static const uint32_t src_allowed =
610 (1u << VK_BLEND_FACTOR_ONE) |
611 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
612 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
613 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
614 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
615 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
616 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
617 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
618 (1u << VK_BLEND_FACTOR_ZERO) |
619 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
620 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
621 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
622 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
623 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
624 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
625
626 if (dst == VK_BLEND_FACTOR_ONE &&
627 (src_allowed & (1u << src))) {
628 /* Addition is commutative, but floating point addition isn't
629 * associative: subtle changes can be introduced via different
630 * rounding. Be conservative, only enable for min and max.
631 */
632 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
633 blend->commutative_4bit |= chanmask;
634 }
635 }
636
637 static struct radv_blend_state
638 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
639 const VkGraphicsPipelineCreateInfo *pCreateInfo,
640 const struct radv_graphics_pipeline_create_info *extra)
641 {
642 const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
643 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
644 struct radv_blend_state blend = {0};
645 unsigned mode = V_028808_CB_NORMAL;
646 int i;
647
648 if (extra && extra->custom_blend_mode) {
649 blend.single_cb_enable = true;
650 mode = extra->custom_blend_mode;
651 }
652
653 blend.cb_color_control = 0;
654 if (vkblend) {
655 if (vkblend->logicOpEnable)
656 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
657 else
658 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
659 }
660
661 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
662 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
663 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
664 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
665 S_028B70_OFFSET_ROUND(1);
666
667 if (vkms && vkms->alphaToCoverageEnable) {
668 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
669 blend.need_src_alpha |= 0x1;
670 }
671
672 blend.cb_target_mask = 0;
673 if (vkblend) {
674 for (i = 0; i < vkblend->attachmentCount; i++) {
675 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
676 unsigned blend_cntl = 0;
677 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
678 VkBlendOp eqRGB = att->colorBlendOp;
679 VkBlendFactor srcRGB = att->srcColorBlendFactor;
680 VkBlendFactor dstRGB = att->dstColorBlendFactor;
681 VkBlendOp eqA = att->alphaBlendOp;
682 VkBlendFactor srcA = att->srcAlphaBlendFactor;
683 VkBlendFactor dstA = att->dstAlphaBlendFactor;
684
685 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
686
687 if (!att->colorWriteMask)
688 continue;
689
690 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
691 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
692 if (!att->blendEnable) {
693 blend.cb_blend_control[i] = blend_cntl;
694 continue;
695 }
696
697 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
698 if (i == 0)
699 blend.mrt0_is_dual_src = true;
700
701 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
702 srcRGB = VK_BLEND_FACTOR_ONE;
703 dstRGB = VK_BLEND_FACTOR_ONE;
704 }
705 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
706 srcA = VK_BLEND_FACTOR_ONE;
707 dstA = VK_BLEND_FACTOR_ONE;
708 }
709
710 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
711 0x7 << (4 * i));
712 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
713 0x8 << (4 * i));
714
715 /* Blending optimizations for RB+.
716 * These transformations don't change the behavior.
717 *
718 * First, get rid of DST in the blend factors:
719 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
720 */
721 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
722 VK_BLEND_FACTOR_DST_COLOR,
723 VK_BLEND_FACTOR_SRC_COLOR);
724
725 si_blend_remove_dst(&eqA, &srcA, &dstA,
726 VK_BLEND_FACTOR_DST_COLOR,
727 VK_BLEND_FACTOR_SRC_COLOR);
728
729 si_blend_remove_dst(&eqA, &srcA, &dstA,
730 VK_BLEND_FACTOR_DST_ALPHA,
731 VK_BLEND_FACTOR_SRC_ALPHA);
732
733 /* Look up the ideal settings from tables. */
734 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
735 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
736 srcA_opt = si_translate_blend_opt_factor(srcA, true);
737 dstA_opt = si_translate_blend_opt_factor(dstA, true);
738
739 /* Handle interdependencies. */
740 if (si_blend_factor_uses_dst(srcRGB))
741 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
742 if (si_blend_factor_uses_dst(srcA))
743 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
744
745 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
746 (dstRGB == VK_BLEND_FACTOR_ZERO ||
747 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
748 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
749 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
750
751 /* Set the final value. */
752 blend.sx_mrt_blend_opt[i] =
753 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
754 S_028760_COLOR_DST_OPT(dstRGB_opt) |
755 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
756 S_028760_ALPHA_SRC_OPT(srcA_opt) |
757 S_028760_ALPHA_DST_OPT(dstA_opt) |
758 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
759 blend_cntl |= S_028780_ENABLE(1);
760
761 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
762 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
763 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
764 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
765 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
766 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
767 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
768 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
769 }
770 blend.cb_blend_control[i] = blend_cntl;
771
772 blend.blend_enable_4bit |= 0xfu << (i * 4);
773
774 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
775 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
776 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
777 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
778 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
779 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
780 blend.need_src_alpha |= 1 << i;
781 }
782 for (i = vkblend->attachmentCount; i < 8; i++) {
783 blend.cb_blend_control[i] = 0;
784 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
785 }
786 }
787
788 if (pipeline->device->physical_device->rad_info.has_rbplus) {
789 /* Disable RB+ blend optimizations for dual source blending. */
790 if (blend.mrt0_is_dual_src) {
791 for (i = 0; i < 8; i++) {
792 blend.sx_mrt_blend_opt[i] =
793 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
794 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
795 }
796 }
797
798 /* RB+ doesn't work with dual source blending, logic op and
799 * RESOLVE.
800 */
801 if (blend.mrt0_is_dual_src ||
802 (vkblend && vkblend->logicOpEnable) ||
803 mode == V_028808_CB_RESOLVE)
804 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
805 }
806
807 if (blend.cb_target_mask)
808 blend.cb_color_control |= S_028808_MODE(mode);
809 else
810 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
811
812 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
813 return blend;
814 }
815
816 static uint32_t si_translate_fill(VkPolygonMode func)
817 {
818 switch(func) {
819 case VK_POLYGON_MODE_FILL:
820 return V_028814_X_DRAW_TRIANGLES;
821 case VK_POLYGON_MODE_LINE:
822 return V_028814_X_DRAW_LINES;
823 case VK_POLYGON_MODE_POINT:
824 return V_028814_X_DRAW_POINTS;
825 default:
826 assert(0);
827 return V_028814_X_DRAW_POINTS;
828 }
829 }
830
831 static uint8_t radv_pipeline_get_ps_iter_samples(const VkGraphicsPipelineCreateInfo *pCreateInfo)
832 {
833 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
834 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
835 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
836 uint32_t ps_iter_samples = 1;
837 uint32_t num_samples;
838
839 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
840 *
841 * "If the VK_AMD_mixed_attachment_samples extension is enabled and the
842 * subpass uses color attachments, totalSamples is the number of
843 * samples of the color attachments. Otherwise, totalSamples is the
844 * value of VkPipelineMultisampleStateCreateInfo::rasterizationSamples
845 * specified at pipeline creation time."
846 */
847 if (subpass->has_color_att) {
848 num_samples = subpass->color_sample_count;
849 } else {
850 num_samples = vkms->rasterizationSamples;
851 }
852
853 if (vkms->sampleShadingEnable) {
854 ps_iter_samples = ceilf(vkms->minSampleShading * num_samples);
855 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
856 }
857 return ps_iter_samples;
858 }
859
860 static bool
861 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
862 {
863 return pCreateInfo->depthTestEnable &&
864 pCreateInfo->depthWriteEnable &&
865 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
866 }
867
868 static bool
869 radv_writes_stencil(const VkStencilOpState *state)
870 {
871 return state->writeMask &&
872 (state->failOp != VK_STENCIL_OP_KEEP ||
873 state->passOp != VK_STENCIL_OP_KEEP ||
874 state->depthFailOp != VK_STENCIL_OP_KEEP);
875 }
876
877 static bool
878 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
879 {
880 return pCreateInfo->stencilTestEnable &&
881 (radv_writes_stencil(&pCreateInfo->front) ||
882 radv_writes_stencil(&pCreateInfo->back));
883 }
884
885 static bool
886 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
887 {
888 return radv_is_depth_write_enabled(pCreateInfo) ||
889 radv_is_stencil_write_enabled(pCreateInfo);
890 }
891
892 static bool
893 radv_order_invariant_stencil_op(VkStencilOp op)
894 {
895 /* REPLACE is normally order invariant, except when the stencil
896 * reference value is written by the fragment shader. Tracking this
897 * interaction does not seem worth the effort, so be conservative.
898 */
899 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
900 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
901 op != VK_STENCIL_OP_REPLACE;
902 }
903
904 static bool
905 radv_order_invariant_stencil_state(const VkStencilOpState *state)
906 {
907 /* Compute whether, assuming Z writes are disabled, this stencil state
908 * is order invariant in the sense that the set of passing fragments as
909 * well as the final stencil buffer result does not depend on the order
910 * of fragments.
911 */
912 return !state->writeMask ||
913 /* The following assumes that Z writes are disabled. */
914 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
915 radv_order_invariant_stencil_op(state->passOp) &&
916 radv_order_invariant_stencil_op(state->depthFailOp)) ||
917 (state->compareOp == VK_COMPARE_OP_NEVER &&
918 radv_order_invariant_stencil_op(state->failOp));
919 }
920
921 static bool
922 radv_pipeline_has_dynamic_ds_states(const VkGraphicsPipelineCreateInfo *pCreateInfo)
923 {
924 VkDynamicState ds_states[] = {
925 VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT,
926 VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT,
927 VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT,
928 VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT,
929 VK_DYNAMIC_STATE_STENCIL_OP_EXT,
930 };
931
932 if (pCreateInfo->pDynamicState) {
933 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
934 for (uint32_t i = 0; i < count; i++) {
935 for (uint32_t j = 0; j < ARRAY_SIZE(ds_states); j++) {
936 if (pCreateInfo->pDynamicState->pDynamicStates[i] == ds_states[j])
937 return true;
938 }
939 }
940 }
941
942 return false;
943 }
944
945 static bool
946 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
947 struct radv_blend_state *blend,
948 const VkGraphicsPipelineCreateInfo *pCreateInfo)
949 {
950 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
951 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
952 const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
953 const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
954 unsigned colormask = blend->cb_target_enabled_4bit;
955
956 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
957 return false;
958
959 /* Be conservative if a logic operation is enabled with color buffers. */
960 if (colormask && vkblend && vkblend->logicOpEnable)
961 return false;
962
963 /* Be conservative if an extended dynamic depth/stencil state is
964 * enabled because the driver can't update out-of-order rasterization
965 * dynamically.
966 */
967 if (radv_pipeline_has_dynamic_ds_states(pCreateInfo))
968 return false;
969
970 /* Default depth/stencil invariance when no attachment is bound. */
971 struct radv_dsa_order_invariance dsa_order_invariant = {
972 .zs = true, .pass_set = true
973 };
974
975 if (vkds) {
976 struct radv_render_pass_attachment *attachment =
977 pass->attachments + subpass->depth_stencil_attachment->attachment;
978 bool has_stencil = vk_format_is_stencil(attachment->format);
979 struct radv_dsa_order_invariance order_invariance[2];
980 struct radv_shader_variant *ps =
981 pipeline->shaders[MESA_SHADER_FRAGMENT];
982
983 /* Compute depth/stencil order invariance in order to know if
984 * it's safe to enable out-of-order.
985 */
986 bool zfunc_is_ordered =
987 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
988 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
989 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
990 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
991 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
992
993 bool nozwrite_and_order_invariant_stencil =
994 !radv_is_ds_write_enabled(vkds) ||
995 (!radv_is_depth_write_enabled(vkds) &&
996 radv_order_invariant_stencil_state(&vkds->front) &&
997 radv_order_invariant_stencil_state(&vkds->back));
998
999 order_invariance[1].zs =
1000 nozwrite_and_order_invariant_stencil ||
1001 (!radv_is_stencil_write_enabled(vkds) &&
1002 zfunc_is_ordered);
1003 order_invariance[0].zs =
1004 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
1005
1006 order_invariance[1].pass_set =
1007 nozwrite_and_order_invariant_stencil ||
1008 (!radv_is_stencil_write_enabled(vkds) &&
1009 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1010 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
1011 order_invariance[0].pass_set =
1012 !radv_is_depth_write_enabled(vkds) ||
1013 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1014 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
1015
1016 dsa_order_invariant = order_invariance[has_stencil];
1017 if (!dsa_order_invariant.zs)
1018 return false;
1019
1020 /* The set of PS invocations is always order invariant,
1021 * except when early Z/S tests are requested.
1022 */
1023 if (ps &&
1024 ps->info.ps.writes_memory &&
1025 ps->info.ps.early_fragment_test &&
1026 !dsa_order_invariant.pass_set)
1027 return false;
1028
1029 /* Determine if out-of-order rasterization should be disabled
1030 * when occlusion queries are used.
1031 */
1032 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
1033 !dsa_order_invariant.pass_set;
1034 }
1035
1036 /* No color buffers are enabled for writing. */
1037 if (!colormask)
1038 return true;
1039
1040 unsigned blendmask = colormask & blend->blend_enable_4bit;
1041
1042 if (blendmask) {
1043 /* Only commutative blending. */
1044 if (blendmask & ~blend->commutative_4bit)
1045 return false;
1046
1047 if (!dsa_order_invariant.pass_set)
1048 return false;
1049 }
1050
1051 if (colormask & ~blendmask)
1052 return false;
1053
1054 return true;
1055 }
1056
1057 static void
1058 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1059 struct radv_blend_state *blend,
1060 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1061 {
1062 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
1063 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1064 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1065 bool out_of_order_rast = false;
1066 int ps_iter_samples = 1;
1067 uint32_t mask = 0xffff;
1068
1069 if (vkms) {
1070 ms->num_samples = vkms->rasterizationSamples;
1071
1072 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1073 *
1074 * "Sample shading is enabled for a graphics pipeline:
1075 *
1076 * - If the interface of the fragment shader entry point of the
1077 * graphics pipeline includes an input variable decorated
1078 * with SampleId or SamplePosition. In this case
1079 * minSampleShadingFactor takes the value 1.0.
1080 * - Else if the sampleShadingEnable member of the
1081 * VkPipelineMultisampleStateCreateInfo structure specified
1082 * when creating the graphics pipeline is set to VK_TRUE. In
1083 * this case minSampleShadingFactor takes the value of
1084 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1085 *
1086 * Otherwise, sample shading is considered disabled."
1087 */
1088 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.force_persample) {
1089 ps_iter_samples = ms->num_samples;
1090 } else {
1091 ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
1092 }
1093 } else {
1094 ms->num_samples = 1;
1095 }
1096
1097 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1098 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1099 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1100 /* Out-of-order rasterization is explicitly enabled by the
1101 * application.
1102 */
1103 out_of_order_rast = true;
1104 } else {
1105 /* Determine if the driver can enable out-of-order
1106 * rasterization internally.
1107 */
1108 out_of_order_rast =
1109 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1110 }
1111
1112 ms->pa_sc_aa_config = 0;
1113 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1114 S_028804_INCOHERENT_EQAA_READS(1) |
1115 S_028804_INTERPOLATE_COMP_Z(1) |
1116 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1117 ms->pa_sc_mode_cntl_1 =
1118 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1119 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1120 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
1121 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1122 /* always 1: */
1123 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1124 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1125 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1126 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1127 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1128 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1129 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1130 S_028A48_VPORT_SCISSOR_ENABLE(1);
1131
1132 const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line =
1133 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1134 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
1135 if (rast_line) {
1136 ms->pa_sc_mode_cntl_0 |= S_028A48_LINE_STIPPLE_ENABLE(rast_line->stippledLineEnable);
1137 if (rast_line->lineRasterizationMode == VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT) {
1138 /* From the Vulkan spec 1.1.129:
1139 *
1140 * "When VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT lines
1141 * are being rasterized, sample locations may all be
1142 * treated as being at the pixel center (this may
1143 * affect attribute and depth interpolation)."
1144 */
1145 ms->num_samples = 1;
1146 }
1147 }
1148
1149 if (ms->num_samples > 1) {
1150 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1151 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1152 uint32_t z_samples = subpass->depth_stencil_attachment ? subpass->depth_sample_count : ms->num_samples;
1153 unsigned log_samples = util_logbase2(ms->num_samples);
1154 unsigned log_z_samples = util_logbase2(z_samples);
1155 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1156 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1157 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
1158 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1159 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1160 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1161 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1162 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) |
1163 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples) | /* CM_R_028BE0_PA_SC_AA_CONFIG */
1164 S_028BE0_COVERED_CENTROID_IS_CENTER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3);
1165 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1166 if (ps_iter_samples > 1)
1167 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1168 }
1169
1170 if (vkms && vkms->pSampleMask) {
1171 mask = vkms->pSampleMask[0] & 0xffff;
1172 }
1173
1174 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1175 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1176 }
1177
1178 static bool
1179 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1180 {
1181 switch (topology) {
1182 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1183 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1184 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1185 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1186 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1187 return false;
1188 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1189 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1190 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1191 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1192 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1193 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1194 return true;
1195 default:
1196 unreachable("unhandled primitive type");
1197 }
1198 }
1199
1200 static uint32_t
1201 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1202 {
1203 switch (gl_prim) {
1204 case 0: /* GL_POINTS */
1205 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1206 case 1: /* GL_LINES */
1207 case 3: /* GL_LINE_STRIP */
1208 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1209 case 0x8E7A: /* GL_ISOLINES */
1210 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1211
1212 case 4: /* GL_TRIANGLES */
1213 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1214 case 5: /* GL_TRIANGLE_STRIP */
1215 case 7: /* GL_QUADS */
1216 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1217 default:
1218 assert(0);
1219 return 0;
1220 }
1221 }
1222
1223 static uint32_t
1224 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1225 {
1226 switch (topology) {
1227 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1228 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1229 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1230 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1231 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1232 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1233 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1234 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1235 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1236 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1237 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1238 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1239 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1240 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1241 default:
1242 assert(0);
1243 return 0;
1244 }
1245 }
1246
1247 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1248 {
1249 switch(state) {
1250 case VK_DYNAMIC_STATE_VIEWPORT:
1251 case VK_DYNAMIC_STATE_VIEWPORT_WITH_COUNT_EXT:
1252 return RADV_DYNAMIC_VIEWPORT;
1253 case VK_DYNAMIC_STATE_SCISSOR:
1254 case VK_DYNAMIC_STATE_SCISSOR_WITH_COUNT_EXT:
1255 return RADV_DYNAMIC_SCISSOR;
1256 case VK_DYNAMIC_STATE_LINE_WIDTH:
1257 return RADV_DYNAMIC_LINE_WIDTH;
1258 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1259 return RADV_DYNAMIC_DEPTH_BIAS;
1260 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1261 return RADV_DYNAMIC_BLEND_CONSTANTS;
1262 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1263 return RADV_DYNAMIC_DEPTH_BOUNDS;
1264 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1265 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1266 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1267 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1268 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1269 return RADV_DYNAMIC_STENCIL_REFERENCE;
1270 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1271 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1272 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
1273 return RADV_DYNAMIC_SAMPLE_LOCATIONS;
1274 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT:
1275 return RADV_DYNAMIC_LINE_STIPPLE;
1276 case VK_DYNAMIC_STATE_CULL_MODE_EXT:
1277 return RADV_DYNAMIC_CULL_MODE;
1278 case VK_DYNAMIC_STATE_FRONT_FACE_EXT:
1279 return RADV_DYNAMIC_FRONT_FACE;
1280 case VK_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY_EXT:
1281 return RADV_DYNAMIC_PRIMITIVE_TOPOLOGY;
1282 case VK_DYNAMIC_STATE_DEPTH_TEST_ENABLE_EXT:
1283 return RADV_DYNAMIC_DEPTH_TEST_ENABLE;
1284 case VK_DYNAMIC_STATE_DEPTH_WRITE_ENABLE_EXT:
1285 return RADV_DYNAMIC_DEPTH_WRITE_ENABLE;
1286 case VK_DYNAMIC_STATE_DEPTH_COMPARE_OP_EXT:
1287 return RADV_DYNAMIC_DEPTH_COMPARE_OP;
1288 case VK_DYNAMIC_STATE_DEPTH_BOUNDS_TEST_ENABLE_EXT:
1289 return RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE;
1290 case VK_DYNAMIC_STATE_STENCIL_TEST_ENABLE_EXT:
1291 return RADV_DYNAMIC_STENCIL_TEST_ENABLE;
1292 case VK_DYNAMIC_STATE_STENCIL_OP_EXT:
1293 return RADV_DYNAMIC_STENCIL_OP;
1294 case VK_DYNAMIC_STATE_VERTEX_INPUT_BINDING_STRIDE_EXT:
1295 return RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE;
1296 default:
1297 unreachable("Unhandled dynamic state");
1298 }
1299 }
1300
1301 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1302 {
1303 uint32_t states = RADV_DYNAMIC_ALL;
1304
1305 /* If rasterization is disabled we do not care about any of the
1306 * dynamic states, since they are all rasterization related only,
1307 * except primitive topology and vertex binding stride.
1308 */
1309 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1310 return RADV_DYNAMIC_PRIMITIVE_TOPOLOGY |
1311 RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE;
1312
1313 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1314 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1315
1316 if (!pCreateInfo->pDepthStencilState ||
1317 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1318 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1319
1320 if (!pCreateInfo->pDepthStencilState ||
1321 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1322 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1323 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1324 RADV_DYNAMIC_STENCIL_REFERENCE);
1325
1326 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1327 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1328
1329 if (!pCreateInfo->pMultisampleState ||
1330 !vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1331 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT))
1332 states &= ~RADV_DYNAMIC_SAMPLE_LOCATIONS;
1333
1334 if (!pCreateInfo->pRasterizationState ||
1335 !vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1336 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT))
1337 states &= ~RADV_DYNAMIC_LINE_STIPPLE;
1338
1339 /* TODO: blend constants & line width. */
1340
1341 return states;
1342 }
1343
1344
1345 static void
1346 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1347 const VkGraphicsPipelineCreateInfo *pCreateInfo,
1348 const struct radv_graphics_pipeline_create_info *extra)
1349 {
1350 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1351 uint32_t states = needed_states;
1352 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1353 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1354
1355 pipeline->dynamic_state = default_dynamic_state;
1356 pipeline->graphics.needed_dynamic_state = needed_states;
1357
1358 if (pCreateInfo->pDynamicState) {
1359 /* Remove all of the states that are marked as dynamic */
1360 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1361 for (uint32_t s = 0; s < count; s++)
1362 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1363 }
1364
1365 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1366
1367 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1368 assert(pCreateInfo->pViewportState);
1369
1370 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1371 if (states & RADV_DYNAMIC_VIEWPORT) {
1372 typed_memcpy(dynamic->viewport.viewports,
1373 pCreateInfo->pViewportState->pViewports,
1374 pCreateInfo->pViewportState->viewportCount);
1375 }
1376 }
1377
1378 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1379 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1380 if (states & RADV_DYNAMIC_SCISSOR) {
1381 typed_memcpy(dynamic->scissor.scissors,
1382 pCreateInfo->pViewportState->pScissors,
1383 pCreateInfo->pViewportState->scissorCount);
1384 }
1385 }
1386
1387 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1388 assert(pCreateInfo->pRasterizationState);
1389 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1390 }
1391
1392 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1393 assert(pCreateInfo->pRasterizationState);
1394 dynamic->depth_bias.bias =
1395 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1396 dynamic->depth_bias.clamp =
1397 pCreateInfo->pRasterizationState->depthBiasClamp;
1398 dynamic->depth_bias.slope =
1399 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1400 }
1401
1402 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1403 *
1404 * pColorBlendState is [...] NULL if the pipeline has rasterization
1405 * disabled or if the subpass of the render pass the pipeline is
1406 * created against does not use any color attachments.
1407 */
1408 if (subpass->has_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1409 assert(pCreateInfo->pColorBlendState);
1410 typed_memcpy(dynamic->blend_constants,
1411 pCreateInfo->pColorBlendState->blendConstants, 4);
1412 }
1413
1414 if (states & RADV_DYNAMIC_CULL_MODE) {
1415 dynamic->cull_mode =
1416 pCreateInfo->pRasterizationState->cullMode;
1417 }
1418
1419 if (states & RADV_DYNAMIC_FRONT_FACE) {
1420 dynamic->front_face =
1421 pCreateInfo->pRasterizationState->frontFace;
1422 }
1423
1424 if (states & RADV_DYNAMIC_PRIMITIVE_TOPOLOGY) {
1425 dynamic->primitive_topology =
1426 si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
1427 if (extra && extra->use_rectlist) {
1428 dynamic->primitive_topology = V_008958_DI_PT_RECTLIST;
1429 }
1430 }
1431
1432 /* If there is no depthstencil attachment, then don't read
1433 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1434 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1435 * no need to override the depthstencil defaults in
1436 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1437 *
1438 * Section 9.2 of the Vulkan 1.0.15 spec says:
1439 *
1440 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1441 * disabled or if the subpass of the render pass the pipeline is created
1442 * against does not use a depth/stencil attachment.
1443 */
1444 if (needed_states && subpass->depth_stencil_attachment) {
1445 assert(pCreateInfo->pDepthStencilState);
1446
1447 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1448 dynamic->depth_bounds.min =
1449 pCreateInfo->pDepthStencilState->minDepthBounds;
1450 dynamic->depth_bounds.max =
1451 pCreateInfo->pDepthStencilState->maxDepthBounds;
1452 }
1453
1454 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1455 dynamic->stencil_compare_mask.front =
1456 pCreateInfo->pDepthStencilState->front.compareMask;
1457 dynamic->stencil_compare_mask.back =
1458 pCreateInfo->pDepthStencilState->back.compareMask;
1459 }
1460
1461 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1462 dynamic->stencil_write_mask.front =
1463 pCreateInfo->pDepthStencilState->front.writeMask;
1464 dynamic->stencil_write_mask.back =
1465 pCreateInfo->pDepthStencilState->back.writeMask;
1466 }
1467
1468 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1469 dynamic->stencil_reference.front =
1470 pCreateInfo->pDepthStencilState->front.reference;
1471 dynamic->stencil_reference.back =
1472 pCreateInfo->pDepthStencilState->back.reference;
1473 }
1474
1475 if (states & RADV_DYNAMIC_DEPTH_TEST_ENABLE) {
1476 dynamic->depth_test_enable =
1477 pCreateInfo->pDepthStencilState->depthTestEnable;
1478 }
1479
1480 if (states & RADV_DYNAMIC_DEPTH_WRITE_ENABLE) {
1481 dynamic->depth_write_enable =
1482 pCreateInfo->pDepthStencilState->depthWriteEnable;
1483 }
1484
1485 if (states & RADV_DYNAMIC_DEPTH_COMPARE_OP) {
1486 dynamic->depth_compare_op =
1487 pCreateInfo->pDepthStencilState->depthCompareOp;
1488 }
1489
1490 if (states & RADV_DYNAMIC_DEPTH_BOUNDS_TEST_ENABLE) {
1491 dynamic->depth_bounds_test_enable =
1492 pCreateInfo->pDepthStencilState->depthBoundsTestEnable;
1493 }
1494
1495 if (states & RADV_DYNAMIC_STENCIL_TEST_ENABLE) {
1496 dynamic->stencil_test_enable =
1497 pCreateInfo->pDepthStencilState->stencilTestEnable;
1498 }
1499
1500 if (states & RADV_DYNAMIC_STENCIL_OP) {
1501 dynamic->stencil_op.front.compare_op =
1502 pCreateInfo->pDepthStencilState->front.compareOp;
1503 dynamic->stencil_op.front.fail_op =
1504 pCreateInfo->pDepthStencilState->front.failOp;
1505 dynamic->stencil_op.front.pass_op =
1506 pCreateInfo->pDepthStencilState->front.passOp;
1507 dynamic->stencil_op.front.depth_fail_op =
1508 pCreateInfo->pDepthStencilState->front.depthFailOp;
1509
1510 dynamic->stencil_op.back.compare_op =
1511 pCreateInfo->pDepthStencilState->back.compareOp;
1512 dynamic->stencil_op.back.fail_op =
1513 pCreateInfo->pDepthStencilState->back.failOp;
1514 dynamic->stencil_op.back.pass_op =
1515 pCreateInfo->pDepthStencilState->back.passOp;
1516 dynamic->stencil_op.back.depth_fail_op =
1517 pCreateInfo->pDepthStencilState->back.depthFailOp;
1518 }
1519 }
1520
1521 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1522 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1523 if (needed_states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1524 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1525 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1526 typed_memcpy(dynamic->discard_rectangle.rectangles,
1527 discard_rectangle_info->pDiscardRectangles,
1528 discard_rectangle_info->discardRectangleCount);
1529 }
1530 }
1531
1532 if (needed_states & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
1533 const VkPipelineSampleLocationsStateCreateInfoEXT *sample_location_info =
1534 vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1535 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1536 /* If sampleLocationsEnable is VK_FALSE, the default sample
1537 * locations are used and the values specified in
1538 * sampleLocationsInfo are ignored.
1539 */
1540 if (sample_location_info->sampleLocationsEnable) {
1541 const VkSampleLocationsInfoEXT *pSampleLocationsInfo =
1542 &sample_location_info->sampleLocationsInfo;
1543
1544 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
1545
1546 dynamic->sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
1547 dynamic->sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
1548 dynamic->sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
1549 typed_memcpy(&dynamic->sample_location.locations[0],
1550 pSampleLocationsInfo->pSampleLocations,
1551 pSampleLocationsInfo->sampleLocationsCount);
1552 }
1553 }
1554
1555 const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line_info =
1556 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1557 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
1558 if (needed_states & RADV_DYNAMIC_LINE_STIPPLE) {
1559 dynamic->line_stipple.factor = rast_line_info->lineStippleFactor;
1560 dynamic->line_stipple.pattern = rast_line_info->lineStipplePattern;
1561 }
1562
1563 if (!(states & RADV_DYNAMIC_VERTEX_INPUT_BINDING_STRIDE))
1564 pipeline->graphics.uses_dynamic_stride = true;
1565
1566 pipeline->dynamic_state.mask = states;
1567 }
1568
1569 static void
1570 gfx9_get_gs_info(const struct radv_pipeline_key *key,
1571 const struct radv_pipeline *pipeline,
1572 nir_shader **nir,
1573 struct radv_shader_info *infos,
1574 struct gfx9_gs_info *out)
1575 {
1576 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1577 struct radv_es_output_info *es_info;
1578 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1579 es_info = nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1580 else
1581 es_info = nir[MESA_SHADER_TESS_CTRL] ?
1582 &infos[MESA_SHADER_TESS_EVAL].tes.es_info :
1583 &infos[MESA_SHADER_VERTEX].vs.es_info;
1584
1585 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1586 bool uses_adjacency;
1587 switch(key->topology) {
1588 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1589 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1590 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1591 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1592 uses_adjacency = true;
1593 break;
1594 default:
1595 uses_adjacency = false;
1596 break;
1597 }
1598
1599 /* All these are in dwords: */
1600 /* We can't allow using the whole LDS, because GS waves compete with
1601 * other shader stages for LDS space. */
1602 const unsigned max_lds_size = 8 * 1024;
1603 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1604 unsigned esgs_lds_size;
1605
1606 /* All these are per subgroup: */
1607 const unsigned max_out_prims = 32 * 1024;
1608 const unsigned max_es_verts = 255;
1609 const unsigned ideal_gs_prims = 64;
1610 unsigned max_gs_prims, gs_prims;
1611 unsigned min_es_verts, es_verts, worst_case_es_verts;
1612
1613 if (uses_adjacency || gs_num_invocations > 1)
1614 max_gs_prims = 127 / gs_num_invocations;
1615 else
1616 max_gs_prims = 255;
1617
1618 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1619 * Make sure we don't go over the maximum value.
1620 */
1621 if (gs_info->gs.vertices_out > 0) {
1622 max_gs_prims = MIN2(max_gs_prims,
1623 max_out_prims /
1624 (gs_info->gs.vertices_out * gs_num_invocations));
1625 }
1626 assert(max_gs_prims > 0);
1627
1628 /* If the primitive has adjacency, halve the number of vertices
1629 * that will be reused in multiple primitives.
1630 */
1631 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1632
1633 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1634 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1635
1636 /* Compute ESGS LDS size based on the worst case number of ES vertices
1637 * needed to create the target number of GS prims per subgroup.
1638 */
1639 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1640
1641 /* If total LDS usage is too big, refactor partitions based on ratio
1642 * of ESGS item sizes.
1643 */
1644 if (esgs_lds_size > max_lds_size) {
1645 /* Our target GS Prims Per Subgroup was too large. Calculate
1646 * the maximum number of GS Prims Per Subgroup that will fit
1647 * into LDS, capped by the maximum that the hardware can support.
1648 */
1649 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1650 max_gs_prims);
1651 assert(gs_prims > 0);
1652 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1653 max_es_verts);
1654
1655 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1656 assert(esgs_lds_size <= max_lds_size);
1657 }
1658
1659 /* Now calculate remaining ESGS information. */
1660 if (esgs_lds_size)
1661 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1662 else
1663 es_verts = max_es_verts;
1664
1665 /* Vertices for adjacency primitives are not always reused, so restore
1666 * it for ES_VERTS_PER_SUBGRP.
1667 */
1668 min_es_verts = gs_info->gs.vertices_in;
1669
1670 /* For normal primitives, the VGT only checks if they are past the ES
1671 * verts per subgroup after allocating a full GS primitive and if they
1672 * are, kick off a new subgroup. But if those additional ES verts are
1673 * unique (e.g. not reused) we need to make sure there is enough LDS
1674 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1675 */
1676 es_verts -= min_es_verts - 1;
1677
1678 uint32_t es_verts_per_subgroup = es_verts;
1679 uint32_t gs_prims_per_subgroup = gs_prims;
1680 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1681 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1682 out->lds_size = align(esgs_lds_size, 128) / 128;
1683 out->vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1684 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1685 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1686 out->vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1687 out->vgt_esgs_ring_itemsize = esgs_itemsize;
1688 assert(max_prims_per_subgroup <= max_out_prims);
1689 }
1690
1691 static void clamp_gsprims_to_esverts(unsigned *max_gsprims, unsigned max_esverts,
1692 unsigned min_verts_per_prim, bool use_adjacency)
1693 {
1694 unsigned max_reuse = max_esverts - min_verts_per_prim;
1695 if (use_adjacency)
1696 max_reuse /= 2;
1697 *max_gsprims = MIN2(*max_gsprims, 1 + max_reuse);
1698 }
1699
1700 static unsigned
1701 radv_get_num_input_vertices(nir_shader **nir)
1702 {
1703 if (nir[MESA_SHADER_GEOMETRY]) {
1704 nir_shader *gs = nir[MESA_SHADER_GEOMETRY];
1705
1706 return gs->info.gs.vertices_in;
1707 }
1708
1709 if (nir[MESA_SHADER_TESS_CTRL]) {
1710 nir_shader *tes = nir[MESA_SHADER_TESS_EVAL];
1711
1712 if (tes->info.tess.point_mode)
1713 return 1;
1714 if (tes->info.tess.primitive_mode == GL_ISOLINES)
1715 return 2;
1716 return 3;
1717 }
1718
1719 return 3;
1720 }
1721
1722 static void
1723 gfx10_get_ngg_info(const struct radv_pipeline_key *key,
1724 struct radv_pipeline *pipeline,
1725 nir_shader **nir,
1726 struct radv_shader_info *infos,
1727 struct gfx10_ngg_info *ngg)
1728 {
1729 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1730 struct radv_es_output_info *es_info =
1731 nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1732 unsigned gs_type = nir[MESA_SHADER_GEOMETRY] ? MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX;
1733 unsigned max_verts_per_prim = radv_get_num_input_vertices(nir);
1734 unsigned min_verts_per_prim =
1735 gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1;
1736 unsigned gs_num_invocations = nir[MESA_SHADER_GEOMETRY] ? MAX2(gs_info->gs.invocations, 1) : 1;
1737 bool uses_adjacency;
1738 switch(key->topology) {
1739 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1740 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1741 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1742 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1743 uses_adjacency = true;
1744 break;
1745 default:
1746 uses_adjacency = false;
1747 break;
1748 }
1749
1750 /* All these are in dwords: */
1751 /* We can't allow using the whole LDS, because GS waves compete with
1752 * other shader stages for LDS space.
1753 *
1754 * TODO: We should really take the shader's internal LDS use into
1755 * account. The linker will fail if the size is greater than
1756 * 8K dwords.
1757 */
1758 const unsigned max_lds_size = 8 * 1024 - 768;
1759 const unsigned target_lds_size = max_lds_size;
1760 unsigned esvert_lds_size = 0;
1761 unsigned gsprim_lds_size = 0;
1762
1763 /* All these are per subgroup: */
1764 bool max_vert_out_per_gs_instance = false;
1765 unsigned max_esverts_base = 256;
1766 unsigned max_gsprims_base = 128; /* default prim group size clamp */
1767
1768 /* Hardware has the following non-natural restrictions on the value
1769 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1770 * the draw:
1771 * - at most 252 for any line input primitive type
1772 * - at most 251 for any quad input primitive type
1773 * - at most 251 for triangle strips with adjacency (this happens to
1774 * be the natural limit for triangle *lists* with adjacency)
1775 */
1776 max_esverts_base = MIN2(max_esverts_base, 251 + max_verts_per_prim - 1);
1777
1778 if (gs_type == MESA_SHADER_GEOMETRY) {
1779 unsigned max_out_verts_per_gsprim =
1780 gs_info->gs.vertices_out * gs_num_invocations;
1781
1782 if (max_out_verts_per_gsprim <= 256) {
1783 if (max_out_verts_per_gsprim) {
1784 max_gsprims_base = MIN2(max_gsprims_base,
1785 256 / max_out_verts_per_gsprim);
1786 }
1787 } else {
1788 /* Use special multi-cycling mode in which each GS
1789 * instance gets its own subgroup. Does not work with
1790 * tessellation. */
1791 max_vert_out_per_gs_instance = true;
1792 max_gsprims_base = 1;
1793 max_out_verts_per_gsprim = gs_info->gs.vertices_out;
1794 }
1795
1796 esvert_lds_size = es_info->esgs_itemsize / 4;
1797 gsprim_lds_size = (gs_info->gs.gsvs_vertex_size / 4 + 1) * max_out_verts_per_gsprim;
1798 } else {
1799 /* VS and TES. */
1800 /* LDS size for passing data from GS to ES. */
1801 struct radv_streamout_info *so_info = nir[MESA_SHADER_TESS_CTRL]
1802 ? &infos[MESA_SHADER_TESS_EVAL].so
1803 : &infos[MESA_SHADER_VERTEX].so;
1804
1805 if (so_info->num_outputs)
1806 esvert_lds_size = 4 * so_info->num_outputs + 1;
1807
1808 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1809 * corresponding to the ES thread of the provoking vertex. All
1810 * ES threads load and export PrimitiveID for their thread.
1811 */
1812 if (!nir[MESA_SHADER_TESS_CTRL] &&
1813 infos[MESA_SHADER_VERTEX].vs.outinfo.export_prim_id)
1814 esvert_lds_size = MAX2(esvert_lds_size, 1);
1815 }
1816
1817 unsigned max_gsprims = max_gsprims_base;
1818 unsigned max_esverts = max_esverts_base;
1819
1820 if (esvert_lds_size)
1821 max_esverts = MIN2(max_esverts, target_lds_size / esvert_lds_size);
1822 if (gsprim_lds_size)
1823 max_gsprims = MIN2(max_gsprims, target_lds_size / gsprim_lds_size);
1824
1825 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1826 clamp_gsprims_to_esverts(&max_gsprims, max_esverts, min_verts_per_prim, uses_adjacency);
1827 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1828
1829 if (esvert_lds_size || gsprim_lds_size) {
1830 /* Now that we have a rough proportionality between esverts
1831 * and gsprims based on the primitive type, scale both of them
1832 * down simultaneously based on required LDS space.
1833 *
1834 * We could be smarter about this if we knew how much vertex
1835 * reuse to expect.
1836 */
1837 unsigned lds_total = max_esverts * esvert_lds_size +
1838 max_gsprims * gsprim_lds_size;
1839 if (lds_total > target_lds_size) {
1840 max_esverts = max_esverts * target_lds_size / lds_total;
1841 max_gsprims = max_gsprims * target_lds_size / lds_total;
1842
1843 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1844 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1845 min_verts_per_prim, uses_adjacency);
1846 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1847 }
1848 }
1849
1850 /* Round up towards full wave sizes for better ALU utilization. */
1851 if (!max_vert_out_per_gs_instance) {
1852 unsigned orig_max_esverts;
1853 unsigned orig_max_gsprims;
1854 unsigned wavesize;
1855
1856 if (gs_type == MESA_SHADER_GEOMETRY) {
1857 wavesize = gs_info->wave_size;
1858 } else {
1859 wavesize = nir[MESA_SHADER_TESS_CTRL]
1860 ? infos[MESA_SHADER_TESS_EVAL].wave_size
1861 : infos[MESA_SHADER_VERTEX].wave_size;
1862 }
1863
1864 do {
1865 orig_max_esverts = max_esverts;
1866 orig_max_gsprims = max_gsprims;
1867
1868 max_esverts = align(max_esverts, wavesize);
1869 max_esverts = MIN2(max_esverts, max_esverts_base);
1870 if (esvert_lds_size)
1871 max_esverts = MIN2(max_esverts,
1872 (max_lds_size - max_gsprims * gsprim_lds_size) /
1873 esvert_lds_size);
1874 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1875
1876 max_gsprims = align(max_gsprims, wavesize);
1877 max_gsprims = MIN2(max_gsprims, max_gsprims_base);
1878 if (gsprim_lds_size)
1879 max_gsprims = MIN2(max_gsprims,
1880 (max_lds_size - max_esverts * esvert_lds_size) /
1881 gsprim_lds_size);
1882 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1883 min_verts_per_prim, uses_adjacency);
1884 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1885 } while (orig_max_esverts != max_esverts || orig_max_gsprims != max_gsprims);
1886 }
1887
1888 /* Hardware restriction: minimum value of max_esverts */
1889 max_esverts = MAX2(max_esverts, 23 + max_verts_per_prim);
1890
1891 unsigned max_out_vertices =
1892 max_vert_out_per_gs_instance ? gs_info->gs.vertices_out :
1893 gs_type == MESA_SHADER_GEOMETRY ?
1894 max_gsprims * gs_num_invocations * gs_info->gs.vertices_out :
1895 max_esverts;
1896 assert(max_out_vertices <= 256);
1897
1898 unsigned prim_amp_factor = 1;
1899 if (gs_type == MESA_SHADER_GEOMETRY) {
1900 /* Number of output primitives per GS input primitive after
1901 * GS instancing. */
1902 prim_amp_factor = gs_info->gs.vertices_out;
1903 }
1904
1905 /* The GE only checks against the maximum number of ES verts after
1906 * allocating a full GS primitive. So we need to ensure that whenever
1907 * this check passes, there is enough space for a full primitive without
1908 * vertex reuse.
1909 */
1910 ngg->hw_max_esverts = max_esverts - max_verts_per_prim + 1;
1911 ngg->max_gsprims = max_gsprims;
1912 ngg->max_out_verts = max_out_vertices;
1913 ngg->prim_amp_factor = prim_amp_factor;
1914 ngg->max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
1915 ngg->ngg_emit_size = max_gsprims * gsprim_lds_size;
1916 ngg->esgs_ring_size = 4 * max_esverts * esvert_lds_size;
1917
1918 if (gs_type == MESA_SHADER_GEOMETRY) {
1919 ngg->vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
1920 } else {
1921 ngg->vgt_esgs_ring_itemsize = 1;
1922 }
1923
1924 pipeline->graphics.esgs_ring_size = ngg->esgs_ring_size;
1925
1926 assert(ngg->hw_max_esverts >= 24); /* HW limitation */
1927 }
1928
1929 static void
1930 calculate_gs_ring_sizes(struct radv_pipeline *pipeline,
1931 const struct gfx9_gs_info *gs)
1932 {
1933 struct radv_device *device = pipeline->device;
1934 unsigned num_se = device->physical_device->rad_info.max_se;
1935 unsigned wave_size = 64;
1936 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1937 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1938 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1939 */
1940 unsigned gs_vertex_reuse =
1941 (device->physical_device->rad_info.chip_class >= GFX8 ? 32 : 16) * num_se;
1942 unsigned alignment = 256 * num_se;
1943 /* The maximum size is 63.999 MB per SE. */
1944 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1945 struct radv_shader_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1946
1947 /* Calculate the minimum size. */
1948 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1949 wave_size, alignment);
1950 /* These are recommended sizes, not minimum sizes. */
1951 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1952 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
1953 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
1954 gs_info->gs.max_gsvs_emit_size;
1955
1956 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
1957 esgs_ring_size = align(esgs_ring_size, alignment);
1958 gsvs_ring_size = align(gsvs_ring_size, alignment);
1959
1960 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
1961 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
1962
1963 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
1964 }
1965
1966 struct radv_shader_variant *
1967 radv_get_shader(struct radv_pipeline *pipeline,
1968 gl_shader_stage stage)
1969 {
1970 if (stage == MESA_SHADER_VERTEX) {
1971 if (pipeline->shaders[MESA_SHADER_VERTEX])
1972 return pipeline->shaders[MESA_SHADER_VERTEX];
1973 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
1974 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
1975 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1976 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1977 } else if (stage == MESA_SHADER_TESS_EVAL) {
1978 if (!radv_pipeline_has_tess(pipeline))
1979 return NULL;
1980 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
1981 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
1982 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
1983 return pipeline->shaders[MESA_SHADER_GEOMETRY];
1984 }
1985 return pipeline->shaders[stage];
1986 }
1987
1988 static struct radv_tessellation_state
1989 calculate_tess_state(struct radv_pipeline *pipeline,
1990 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1991 {
1992 unsigned num_tcs_input_cp;
1993 unsigned num_tcs_output_cp;
1994 unsigned lds_size;
1995 unsigned num_patches;
1996 struct radv_tessellation_state tess = {0};
1997
1998 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
1999 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
2000 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2001
2002 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
2003
2004 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
2005 assert(lds_size <= 65536);
2006 lds_size = align(lds_size, 512) / 512;
2007 } else {
2008 assert(lds_size <= 32768);
2009 lds_size = align(lds_size, 256) / 256;
2010 }
2011
2012 tess.lds_size = lds_size;
2013
2014 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
2015 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
2016 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
2017
2018 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
2019 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
2020
2021 switch (tes->info.tes.primitive_mode) {
2022 case GL_TRIANGLES:
2023 type = V_028B6C_TESS_TRIANGLE;
2024 break;
2025 case GL_QUADS:
2026 type = V_028B6C_TESS_QUAD;
2027 break;
2028 case GL_ISOLINES:
2029 type = V_028B6C_TESS_ISOLINE;
2030 break;
2031 }
2032
2033 switch (tes->info.tes.spacing) {
2034 case TESS_SPACING_EQUAL:
2035 partitioning = V_028B6C_PART_INTEGER;
2036 break;
2037 case TESS_SPACING_FRACTIONAL_ODD:
2038 partitioning = V_028B6C_PART_FRAC_ODD;
2039 break;
2040 case TESS_SPACING_FRACTIONAL_EVEN:
2041 partitioning = V_028B6C_PART_FRAC_EVEN;
2042 break;
2043 default:
2044 break;
2045 }
2046
2047 bool ccw = tes->info.tes.ccw;
2048 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_origin_state =
2049 vk_find_struct_const(pCreateInfo->pTessellationState,
2050 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
2051
2052 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT)
2053 ccw = !ccw;
2054
2055 if (tes->info.tes.point_mode)
2056 topology = V_028B6C_OUTPUT_POINT;
2057 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
2058 topology = V_028B6C_OUTPUT_LINE;
2059 else if (ccw)
2060 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2061 else
2062 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2063
2064 if (pipeline->device->physical_device->rad_info.has_distributed_tess) {
2065 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
2066 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
2067 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
2068 else
2069 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
2070 } else
2071 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
2072
2073 tess.tf_param = S_028B6C_TYPE(type) |
2074 S_028B6C_PARTITIONING(partitioning) |
2075 S_028B6C_TOPOLOGY(topology) |
2076 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
2077
2078 return tess;
2079 }
2080
2081 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
2082 {
2083 if (radv_pipeline_has_gs(pipeline))
2084 if (radv_pipeline_has_ngg(pipeline))
2085 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
2086 else
2087 return &pipeline->gs_copy_shader->info.vs.outinfo;
2088 else if (radv_pipeline_has_tess(pipeline))
2089 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
2090 else
2091 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
2092 }
2093
2094 static void
2095 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
2096 {
2097 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
2098 int shader_count = 0;
2099
2100 if(shaders[MESA_SHADER_FRAGMENT]) {
2101 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
2102 }
2103 if(shaders[MESA_SHADER_GEOMETRY]) {
2104 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
2105 }
2106 if(shaders[MESA_SHADER_TESS_EVAL]) {
2107 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
2108 }
2109 if(shaders[MESA_SHADER_TESS_CTRL]) {
2110 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
2111 }
2112 if(shaders[MESA_SHADER_VERTEX]) {
2113 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
2114 }
2115
2116 if (shader_count > 1) {
2117 unsigned first = ordered_shaders[shader_count - 1]->info.stage;
2118 unsigned last = ordered_shaders[0]->info.stage;
2119
2120 if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
2121 ordered_shaders[1]->info.has_transform_feedback_varyings)
2122 nir_link_xfb_varyings(ordered_shaders[1], ordered_shaders[0]);
2123
2124 for (int i = 0; i < shader_count; ++i) {
2125 nir_variable_mode mask = 0;
2126
2127 if (ordered_shaders[i]->info.stage != first)
2128 mask = mask | nir_var_shader_in;
2129
2130 if (ordered_shaders[i]->info.stage != last)
2131 mask = mask | nir_var_shader_out;
2132
2133 nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
2134 radv_optimize_nir(ordered_shaders[i], false, false);
2135 }
2136 }
2137
2138 for (int i = 1; i < shader_count; ++i) {
2139 nir_lower_io_arrays_to_elements(ordered_shaders[i],
2140 ordered_shaders[i - 1]);
2141
2142 if (nir_link_opt_varyings(ordered_shaders[i],
2143 ordered_shaders[i - 1]))
2144 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2145
2146 nir_remove_dead_variables(ordered_shaders[i],
2147 nir_var_shader_out, NULL);
2148 nir_remove_dead_variables(ordered_shaders[i - 1],
2149 nir_var_shader_in, NULL);
2150
2151 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
2152 ordered_shaders[i - 1]);
2153
2154 nir_compact_varyings(ordered_shaders[i],
2155 ordered_shaders[i - 1], true);
2156
2157 if (progress) {
2158 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
2159 ac_lower_indirect_derefs(ordered_shaders[i],
2160 pipeline->device->physical_device->rad_info.chip_class);
2161 }
2162 radv_optimize_nir(ordered_shaders[i], false, false);
2163
2164 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
2165 ac_lower_indirect_derefs(ordered_shaders[i - 1],
2166 pipeline->device->physical_device->rad_info.chip_class);
2167 }
2168 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2169 }
2170 }
2171 }
2172
2173 static void
2174 radv_set_linked_driver_locations(struct radv_pipeline *pipeline, nir_shader **shaders,
2175 struct radv_shader_info infos[MESA_SHADER_STAGES])
2176 {
2177 bool has_tess = shaders[MESA_SHADER_TESS_CTRL];
2178 bool has_gs = shaders[MESA_SHADER_GEOMETRY];
2179
2180 if (!has_tess && !has_gs)
2181 return;
2182
2183 unsigned vs_info_idx = MESA_SHADER_VERTEX;
2184 unsigned tes_info_idx = MESA_SHADER_TESS_EVAL;
2185
2186 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
2187 /* These are merged into the next stage */
2188 vs_info_idx = has_tess ? MESA_SHADER_TESS_CTRL : MESA_SHADER_GEOMETRY;
2189 tes_info_idx = has_gs ? MESA_SHADER_GEOMETRY : MESA_SHADER_TESS_EVAL;
2190 }
2191
2192 if (has_tess) {
2193 nir_linked_io_var_info vs2tcs =
2194 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_VERTEX], shaders[MESA_SHADER_TESS_CTRL]);
2195 nir_linked_io_var_info tcs2tes =
2196 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_TESS_CTRL], shaders[MESA_SHADER_TESS_EVAL]);
2197
2198 infos[vs_info_idx].vs.num_linked_outputs = vs2tcs.num_linked_io_vars;
2199 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_inputs = vs2tcs.num_linked_io_vars;
2200 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_outputs = tcs2tes.num_linked_io_vars;
2201 infos[MESA_SHADER_TESS_CTRL].tcs.num_linked_patch_outputs = tcs2tes.num_linked_patch_io_vars;
2202 infos[tes_info_idx].tes.num_linked_inputs = tcs2tes.num_linked_io_vars;
2203 infos[tes_info_idx].tes.num_linked_patch_inputs = tcs2tes.num_linked_patch_io_vars;
2204
2205 if (has_gs) {
2206 nir_linked_io_var_info tes2gs =
2207 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_TESS_EVAL], shaders[MESA_SHADER_GEOMETRY]);
2208
2209 infos[tes_info_idx].tes.num_linked_outputs = tes2gs.num_linked_io_vars;
2210 infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = tes2gs.num_linked_io_vars;
2211 }
2212 } else if (has_gs) {
2213 nir_linked_io_var_info vs2gs =
2214 nir_assign_linked_io_var_locations(shaders[MESA_SHADER_VERTEX], shaders[MESA_SHADER_GEOMETRY]);
2215
2216 infos[vs_info_idx].vs.num_linked_outputs = vs2gs.num_linked_io_vars;
2217 infos[MESA_SHADER_GEOMETRY].gs.num_linked_inputs = vs2gs.num_linked_io_vars;
2218 }
2219 }
2220
2221 static uint32_t
2222 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo *input_state,
2223 uint32_t attrib_binding)
2224 {
2225 for (uint32_t i = 0; i < input_state->vertexBindingDescriptionCount; i++) {
2226 const VkVertexInputBindingDescription *input_binding =
2227 &input_state->pVertexBindingDescriptions[i];
2228
2229 if (input_binding->binding == attrib_binding)
2230 return input_binding->stride;
2231 }
2232
2233 return 0;
2234 }
2235
2236 static struct radv_pipeline_key
2237 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
2238 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2239 const struct radv_blend_state *blend)
2240 {
2241 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
2242 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
2243 const VkPipelineVertexInputStateCreateInfo *input_state =
2244 pCreateInfo->pVertexInputState;
2245 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
2246 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
2247
2248 struct radv_pipeline_key key;
2249 memset(&key, 0, sizeof(key));
2250
2251 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
2252 key.optimisations_disabled = 1;
2253
2254 key.has_multiview_view_index = !!subpass->view_mask;
2255
2256 uint32_t binding_input_rate = 0;
2257 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
2258 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
2259 if (input_state->pVertexBindingDescriptions[i].inputRate) {
2260 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
2261 binding_input_rate |= 1u << binding;
2262 instance_rate_divisors[binding] = 1;
2263 }
2264 }
2265 if (divisor_state) {
2266 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
2267 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
2268 divisor_state->pVertexBindingDivisors[i].divisor;
2269 }
2270 }
2271
2272 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
2273 const VkVertexInputAttributeDescription *desc =
2274 &input_state->pVertexAttributeDescriptions[i];
2275 const struct vk_format_description *format_desc;
2276 unsigned location = desc->location;
2277 unsigned binding = desc->binding;
2278 unsigned num_format, data_format;
2279 int first_non_void;
2280
2281 if (binding_input_rate & (1u << binding)) {
2282 key.instance_rate_inputs |= 1u << location;
2283 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
2284 }
2285
2286 format_desc = vk_format_description(desc->format);
2287 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2288
2289 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2290 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2291
2292 key.vertex_attribute_formats[location] = data_format | (num_format << 4);
2293 key.vertex_attribute_bindings[location] = desc->binding;
2294 key.vertex_attribute_offsets[location] = desc->offset;
2295 key.vertex_attribute_strides[location] = radv_get_attrib_stride(input_state, desc->binding);
2296
2297 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8 &&
2298 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
2299 VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
2300 uint64_t adjust;
2301 switch(format) {
2302 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2303 case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
2304 adjust = RADV_ALPHA_ADJUST_SNORM;
2305 break;
2306 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2307 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
2308 adjust = RADV_ALPHA_ADJUST_SSCALED;
2309 break;
2310 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2311 case VK_FORMAT_A2B10G10R10_SINT_PACK32:
2312 adjust = RADV_ALPHA_ADJUST_SINT;
2313 break;
2314 default:
2315 adjust = 0;
2316 break;
2317 }
2318 key.vertex_alpha_adjust |= adjust << (2 * location);
2319 }
2320
2321 switch (desc->format) {
2322 case VK_FORMAT_B8G8R8A8_UNORM:
2323 case VK_FORMAT_B8G8R8A8_SNORM:
2324 case VK_FORMAT_B8G8R8A8_USCALED:
2325 case VK_FORMAT_B8G8R8A8_SSCALED:
2326 case VK_FORMAT_B8G8R8A8_UINT:
2327 case VK_FORMAT_B8G8R8A8_SINT:
2328 case VK_FORMAT_B8G8R8A8_SRGB:
2329 case VK_FORMAT_A2R10G10B10_UNORM_PACK32:
2330 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2331 case VK_FORMAT_A2R10G10B10_USCALED_PACK32:
2332 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2333 case VK_FORMAT_A2R10G10B10_UINT_PACK32:
2334 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2335 key.vertex_post_shuffle |= 1 << location;
2336 break;
2337 default:
2338 break;
2339 }
2340 }
2341
2342 const VkPipelineTessellationStateCreateInfo *tess =
2343 radv_pipeline_get_tessellation_state(pCreateInfo);
2344 if (tess)
2345 key.tess_input_vertices = tess->patchControlPoints;
2346
2347 const VkPipelineMultisampleStateCreateInfo *vkms =
2348 radv_pipeline_get_multisample_state(pCreateInfo);
2349 if (vkms && vkms->rasterizationSamples > 1) {
2350 uint32_t num_samples = vkms->rasterizationSamples;
2351 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
2352 key.num_samples = num_samples;
2353 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
2354 }
2355
2356 key.col_format = blend->spi_shader_col_format;
2357 key.is_dual_src = blend->mrt0_is_dual_src;
2358 if (pipeline->device->physical_device->rad_info.chip_class < GFX8) {
2359 key.is_int8 = blend->col_format_is_int8;
2360 key.is_int10 = blend->col_format_is_int10;
2361 }
2362
2363 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10)
2364 key.topology = pCreateInfo->pInputAssemblyState->topology;
2365
2366 return key;
2367 }
2368
2369 static bool
2370 radv_nir_stage_uses_xfb(const nir_shader *nir)
2371 {
2372 nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
2373 bool uses_xfb = !!xfb;
2374
2375 ralloc_free(xfb);
2376 return uses_xfb;
2377 }
2378
2379 static void
2380 radv_fill_shader_keys(struct radv_device *device,
2381 struct radv_shader_variant_key *keys,
2382 const struct radv_pipeline_key *key,
2383 nir_shader **nir)
2384 {
2385 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
2386 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
2387 keys[MESA_SHADER_VERTEX].vs.post_shuffle = key->vertex_post_shuffle;
2388 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) {
2389 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
2390 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_formats[i] = key->vertex_attribute_formats[i];
2391 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_bindings[i] = key->vertex_attribute_bindings[i];
2392 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i];
2393 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i];
2394 }
2395 keys[MESA_SHADER_VERTEX].vs.outprim = si_conv_prim_to_gs_out(key->topology);
2396
2397 if (nir[MESA_SHADER_TESS_CTRL]) {
2398 keys[MESA_SHADER_VERTEX].vs_common_out.as_ls = true;
2399 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
2400 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
2401 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
2402
2403 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
2404 }
2405
2406 if (nir[MESA_SHADER_GEOMETRY]) {
2407 if (nir[MESA_SHADER_TESS_CTRL])
2408 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_es = true;
2409 else
2410 keys[MESA_SHADER_VERTEX].vs_common_out.as_es = true;
2411 }
2412
2413 if (device->physical_device->use_ngg) {
2414 if (nir[MESA_SHADER_TESS_CTRL]) {
2415 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = true;
2416 } else {
2417 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = true;
2418 }
2419
2420 if (nir[MESA_SHADER_TESS_CTRL] &&
2421 nir[MESA_SHADER_GEOMETRY] &&
2422 nir[MESA_SHADER_GEOMETRY]->info.gs.invocations *
2423 nir[MESA_SHADER_GEOMETRY]->info.gs.vertices_out > 256) {
2424 /* Fallback to the legacy path if tessellation is
2425 * enabled with extreme geometry because
2426 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2427 * might hang.
2428 */
2429 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2430 }
2431
2432 if (!device->physical_device->use_ngg_gs) {
2433 if (nir[MESA_SHADER_GEOMETRY]) {
2434 if (nir[MESA_SHADER_TESS_CTRL])
2435 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2436 else
2437 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2438 }
2439 }
2440
2441 gl_shader_stage last_xfb_stage = MESA_SHADER_VERTEX;
2442
2443 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
2444 if (nir[i])
2445 last_xfb_stage = i;
2446 }
2447
2448 bool uses_xfb = nir[last_xfb_stage] &&
2449 radv_nir_stage_uses_xfb(nir[last_xfb_stage]);
2450
2451 if (!device->physical_device->use_ngg_streamout && uses_xfb) {
2452 if (nir[MESA_SHADER_TESS_CTRL])
2453 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2454 else
2455 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2456 }
2457
2458 /* Determine if the pipeline is eligible for the NGG passthrough
2459 * mode. It can't be enabled for geometry shaders, for NGG
2460 * streamout or for vertex shaders that export the primitive ID
2461 * (this is checked later because we don't have the info here.)
2462 */
2463 if (!nir[MESA_SHADER_GEOMETRY] && !uses_xfb) {
2464 if (nir[MESA_SHADER_TESS_CTRL] &&
2465 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg) {
2466 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg_passthrough = true;
2467 } else if (nir[MESA_SHADER_VERTEX] &&
2468 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) {
2469 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = true;
2470 }
2471 }
2472 }
2473
2474 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
2475 keys[i].has_multiview_view_index = key->has_multiview_view_index;
2476
2477 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
2478 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
2479 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
2480 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
2481 keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples;
2482 keys[MESA_SHADER_FRAGMENT].fs.is_dual_src = key->is_dual_src;
2483
2484 if (nir[MESA_SHADER_COMPUTE]) {
2485 keys[MESA_SHADER_COMPUTE].cs.subgroup_size = key->compute_subgroup_size;
2486 }
2487 }
2488
2489 static uint8_t
2490 radv_get_wave_size(struct radv_device *device,
2491 const VkPipelineShaderStageCreateInfo *pStage,
2492 gl_shader_stage stage,
2493 const struct radv_shader_variant_key *key)
2494 {
2495 if (stage == MESA_SHADER_GEOMETRY && !key->vs_common_out.as_ngg)
2496 return 64;
2497 else if (stage == MESA_SHADER_COMPUTE) {
2498 if (key->cs.subgroup_size) {
2499 /* Return the required subgroup size if specified. */
2500 return key->cs.subgroup_size;
2501 }
2502 return device->physical_device->cs_wave_size;
2503 }
2504 else if (stage == MESA_SHADER_FRAGMENT)
2505 return device->physical_device->ps_wave_size;
2506 else
2507 return device->physical_device->ge_wave_size;
2508 }
2509
2510 static uint8_t
2511 radv_get_ballot_bit_size(struct radv_device *device,
2512 const VkPipelineShaderStageCreateInfo *pStage,
2513 gl_shader_stage stage,
2514 const struct radv_shader_variant_key *key)
2515 {
2516 if (stage == MESA_SHADER_COMPUTE && key->cs.subgroup_size)
2517 return key->cs.subgroup_size;
2518 return 64;
2519 }
2520
2521 static void
2522 radv_fill_shader_info(struct radv_pipeline *pipeline,
2523 const VkPipelineShaderStageCreateInfo **pStages,
2524 struct radv_shader_variant_key *keys,
2525 struct radv_shader_info *infos,
2526 nir_shader **nir)
2527 {
2528 unsigned active_stages = 0;
2529 unsigned filled_stages = 0;
2530
2531 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2532 if (nir[i])
2533 active_stages |= (1 << i);
2534 }
2535
2536 if (nir[MESA_SHADER_FRAGMENT]) {
2537 radv_nir_shader_info_init(&infos[MESA_SHADER_FRAGMENT]);
2538 radv_nir_shader_info_pass(nir[MESA_SHADER_FRAGMENT],
2539 pipeline->layout,
2540 &keys[MESA_SHADER_FRAGMENT],
2541 &infos[MESA_SHADER_FRAGMENT],
2542 pipeline->device->physical_device->use_llvm);
2543
2544 /* TODO: These are no longer used as keys we should refactor this */
2545 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2546 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2547 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2548 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2549 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2550 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2551 keys[MESA_SHADER_VERTEX].vs_common_out.export_viewport_index =
2552 infos[MESA_SHADER_FRAGMENT].ps.viewport_index_input;
2553 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2554 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2555 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2556 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2557 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2558 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2559 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_viewport_index =
2560 infos[MESA_SHADER_FRAGMENT].ps.viewport_index_input;
2561
2562 /* NGG passthrough mode can't be enabled for vertex shaders
2563 * that export the primitive ID.
2564 *
2565 * TODO: I should really refactor the keys logic.
2566 */
2567 if (nir[MESA_SHADER_VERTEX] &&
2568 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id) {
2569 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = false;
2570 }
2571
2572 filled_stages |= (1 << MESA_SHADER_FRAGMENT);
2573 }
2574
2575 if (nir[MESA_SHADER_TESS_CTRL]) {
2576 infos[MESA_SHADER_TESS_CTRL].tcs.tes_inputs_read =
2577 nir[MESA_SHADER_TESS_EVAL]->info.inputs_read;
2578 infos[MESA_SHADER_TESS_CTRL].tcs.tes_patch_inputs_read =
2579 nir[MESA_SHADER_TESS_EVAL]->info.patch_inputs_read;
2580 }
2581
2582 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2583 nir[MESA_SHADER_TESS_CTRL]) {
2584 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2585 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2586 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2587
2588 radv_nir_shader_info_init(&infos[MESA_SHADER_TESS_CTRL]);
2589
2590 for (int i = 0; i < 2; i++) {
2591 radv_nir_shader_info_pass(combined_nir[i],
2592 pipeline->layout, &key,
2593 &infos[MESA_SHADER_TESS_CTRL],
2594 pipeline->device->physical_device->use_llvm);
2595 }
2596
2597 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2598 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2599 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2600 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2601
2602 filled_stages |= (1 << MESA_SHADER_VERTEX);
2603 filled_stages |= (1 << MESA_SHADER_TESS_CTRL);
2604 }
2605
2606 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2607 nir[MESA_SHADER_GEOMETRY]) {
2608 gl_shader_stage pre_stage = nir[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2609 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2610
2611 radv_nir_shader_info_init(&infos[MESA_SHADER_GEOMETRY]);
2612
2613 for (int i = 0; i < 2; i++) {
2614 radv_nir_shader_info_pass(combined_nir[i],
2615 pipeline->layout,
2616 &keys[pre_stage],
2617 &infos[MESA_SHADER_GEOMETRY],
2618 pipeline->device->physical_device->use_llvm);
2619 }
2620
2621 filled_stages |= (1 << pre_stage);
2622 filled_stages |= (1 << MESA_SHADER_GEOMETRY);
2623 }
2624
2625 active_stages ^= filled_stages;
2626 while (active_stages) {
2627 int i = u_bit_scan(&active_stages);
2628
2629 if (i == MESA_SHADER_TESS_CTRL) {
2630 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs =
2631 util_last_bit64(infos[MESA_SHADER_VERTEX].vs.ls_outputs_written);
2632 }
2633
2634 if (i == MESA_SHADER_TESS_EVAL) {
2635 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2636 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2637 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2638 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2639 }
2640
2641 radv_nir_shader_info_init(&infos[i]);
2642 radv_nir_shader_info_pass(nir[i], pipeline->layout,
2643 &keys[i], &infos[i], pipeline->device->physical_device->use_llvm);
2644 }
2645
2646 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2647 if (nir[i]) {
2648 infos[i].wave_size =
2649 radv_get_wave_size(pipeline->device, pStages[i],
2650 i, &keys[i]);
2651 infos[i].ballot_bit_size =
2652 radv_get_ballot_bit_size(pipeline->device,
2653 pStages[i], i,
2654 &keys[i]);
2655 }
2656 }
2657 }
2658
2659 static void
2660 merge_tess_info(struct shader_info *tes_info,
2661 const struct shader_info *tcs_info)
2662 {
2663 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2664 *
2665 * "PointMode. Controls generation of points rather than triangles
2666 * or lines. This functionality defaults to disabled, and is
2667 * enabled if either shader stage includes the execution mode.
2668 *
2669 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2670 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2671 * and OutputVertices, it says:
2672 *
2673 * "One mode must be set in at least one of the tessellation
2674 * shader stages."
2675 *
2676 * So, the fields can be set in either the TCS or TES, but they must
2677 * agree if set in both. Our backend looks at TES, so bitwise-or in
2678 * the values from the TCS.
2679 */
2680 assert(tcs_info->tess.tcs_vertices_out == 0 ||
2681 tes_info->tess.tcs_vertices_out == 0 ||
2682 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
2683 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
2684
2685 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2686 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2687 tcs_info->tess.spacing == tes_info->tess.spacing);
2688 tes_info->tess.spacing |= tcs_info->tess.spacing;
2689
2690 assert(tcs_info->tess.primitive_mode == 0 ||
2691 tes_info->tess.primitive_mode == 0 ||
2692 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
2693 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
2694 tes_info->tess.ccw |= tcs_info->tess.ccw;
2695 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
2696 }
2697
2698 static
2699 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT *ext)
2700 {
2701 if (!ext)
2702 return;
2703
2704 if (ext->pPipelineCreationFeedback) {
2705 ext->pPipelineCreationFeedback->flags = 0;
2706 ext->pPipelineCreationFeedback->duration = 0;
2707 }
2708
2709 for (unsigned i = 0; i < ext->pipelineStageCreationFeedbackCount; ++i) {
2710 ext->pPipelineStageCreationFeedbacks[i].flags = 0;
2711 ext->pPipelineStageCreationFeedbacks[i].duration = 0;
2712 }
2713 }
2714
2715 static
2716 void radv_start_feedback(VkPipelineCreationFeedbackEXT *feedback)
2717 {
2718 if (!feedback)
2719 return;
2720
2721 feedback->duration -= radv_get_current_time();
2722 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT;
2723 }
2724
2725 static
2726 void radv_stop_feedback(VkPipelineCreationFeedbackEXT *feedback, bool cache_hit)
2727 {
2728 if (!feedback)
2729 return;
2730
2731 feedback->duration += radv_get_current_time();
2732 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT |
2733 (cache_hit ? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT : 0);
2734 }
2735
2736 VkResult radv_create_shaders(struct radv_pipeline *pipeline,
2737 struct radv_device *device,
2738 struct radv_pipeline_cache *cache,
2739 const struct radv_pipeline_key *key,
2740 const VkPipelineShaderStageCreateInfo **pStages,
2741 const VkPipelineCreateFlags flags,
2742 VkPipelineCreationFeedbackEXT *pipeline_feedback,
2743 VkPipelineCreationFeedbackEXT **stage_feedbacks)
2744 {
2745 struct radv_shader_module fs_m = {0};
2746 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2747 nir_shader *nir[MESA_SHADER_STAGES] = {0};
2748 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2749 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{{0}}}}};
2750 struct radv_shader_info infos[MESA_SHADER_STAGES] = {0};
2751 unsigned char hash[20], gs_copy_hash[20];
2752 bool keep_executable_info = (flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR) || device->keep_shader_info;
2753 bool keep_statistic_info = (flags & VK_PIPELINE_CREATE_CAPTURE_STATISTICS_BIT_KHR) ||
2754 (device->instance->debug_flags & RADV_DEBUG_DUMP_SHADER_STATS) ||
2755 device->keep_shader_info;
2756
2757 radv_start_feedback(pipeline_feedback);
2758
2759 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2760 if (pStages[i]) {
2761 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
2762 if (modules[i]->nir)
2763 _mesa_sha1_compute(modules[i]->nir->info.name,
2764 strlen(modules[i]->nir->info.name),
2765 modules[i]->sha1);
2766
2767 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
2768 }
2769 }
2770
2771 radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device));
2772 memcpy(gs_copy_hash, hash, 20);
2773 gs_copy_hash[0] ^= 1;
2774
2775 bool found_in_application_cache = true;
2776 if (modules[MESA_SHADER_GEOMETRY] && !keep_executable_info && !keep_statistic_info) {
2777 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2778 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants,
2779 &found_in_application_cache);
2780 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
2781 }
2782
2783 if (!keep_executable_info && !keep_statistic_info &&
2784 radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders,
2785 &found_in_application_cache) &&
2786 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
2787 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2788 return VK_SUCCESS;
2789 }
2790
2791 if (flags & VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_EXT) {
2792 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2793 return VK_PIPELINE_COMPILE_REQUIRED_EXT;
2794 }
2795
2796 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
2797 nir_builder fs_b;
2798 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2799 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2800 fs_m.nir = fs_b.shader;
2801 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2802 }
2803
2804 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2805 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
2806 unsigned subgroup_size = 64, ballot_bit_size = 64;
2807
2808 if (!modules[i])
2809 continue;
2810
2811 radv_start_feedback(stage_feedbacks[i]);
2812
2813 if (key->compute_subgroup_size) {
2814 /* Only compute shaders currently support requiring a
2815 * specific subgroup size.
2816 */
2817 assert(i == MESA_SHADER_COMPUTE);
2818 subgroup_size = key->compute_subgroup_size;
2819 ballot_bit_size = key->compute_subgroup_size;
2820 }
2821
2822 nir[i] = radv_shader_compile_to_nir(device, modules[i],
2823 stage ? stage->pName : "main", i,
2824 stage ? stage->pSpecializationInfo : NULL,
2825 flags, pipeline->layout,
2826 subgroup_size, ballot_bit_size);
2827
2828 /* We don't want to alter meta shaders IR directly so clone it
2829 * first.
2830 */
2831 if (nir[i]->info.name) {
2832 nir[i] = nir_shader_clone(NULL, nir[i]);
2833 }
2834
2835 radv_stop_feedback(stage_feedbacks[i], false);
2836 }
2837
2838 if (nir[MESA_SHADER_TESS_CTRL]) {
2839 nir_lower_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
2840 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
2841 }
2842
2843 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
2844 radv_link_shaders(pipeline, nir);
2845
2846 radv_set_linked_driver_locations(pipeline, nir, infos);
2847
2848 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2849 if (nir[i]) {
2850 /* do this again since information such as outputs_read can be out-of-date */
2851 nir_shader_gather_info(nir[i], nir_shader_get_entrypoint(nir[i]));
2852
2853 if (device->physical_device->use_llvm) {
2854 NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
2855 } else {
2856 NIR_PASS_V(nir[i], nir_lower_non_uniform_access,
2857 nir_lower_non_uniform_ubo_access |
2858 nir_lower_non_uniform_ssbo_access |
2859 nir_lower_non_uniform_texture_access |
2860 nir_lower_non_uniform_image_access);
2861 }
2862 }
2863 }
2864
2865 if (nir[MESA_SHADER_FRAGMENT])
2866 radv_lower_fs_io(nir[MESA_SHADER_FRAGMENT]);
2867
2868 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2869 if (radv_can_dump_shader(device, modules[i], false))
2870 nir_print_shader(nir[i], stderr);
2871 }
2872
2873 radv_fill_shader_keys(device, keys, key, nir);
2874
2875 radv_fill_shader_info(pipeline, pStages, keys, infos, nir);
2876
2877 if ((nir[MESA_SHADER_VERTEX] &&
2878 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) ||
2879 (nir[MESA_SHADER_TESS_EVAL] &&
2880 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg)) {
2881 struct gfx10_ngg_info *ngg_info;
2882
2883 if (nir[MESA_SHADER_GEOMETRY])
2884 ngg_info = &infos[MESA_SHADER_GEOMETRY].ngg_info;
2885 else if (nir[MESA_SHADER_TESS_CTRL])
2886 ngg_info = &infos[MESA_SHADER_TESS_EVAL].ngg_info;
2887 else
2888 ngg_info = &infos[MESA_SHADER_VERTEX].ngg_info;
2889
2890 gfx10_get_ngg_info(key, pipeline, nir, infos, ngg_info);
2891 } else if (nir[MESA_SHADER_GEOMETRY]) {
2892 struct gfx9_gs_info *gs_info =
2893 &infos[MESA_SHADER_GEOMETRY].gs_ring_info;
2894
2895 gfx9_get_gs_info(key, pipeline, nir, infos, gs_info);
2896 }
2897
2898 if(modules[MESA_SHADER_GEOMETRY]) {
2899 struct radv_shader_binary *gs_copy_binary = NULL;
2900 if (!pipeline->gs_copy_shader &&
2901 !radv_pipeline_has_ngg(pipeline)) {
2902 struct radv_shader_info info = {};
2903 struct radv_shader_variant_key key = {};
2904
2905 key.has_multiview_view_index =
2906 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index;
2907
2908 radv_nir_shader_info_pass(nir[MESA_SHADER_GEOMETRY],
2909 pipeline->layout, &key,
2910 &info, pipeline->device->physical_device->use_llvm);
2911 info.wave_size = 64; /* Wave32 not supported. */
2912 info.ballot_bit_size = 64;
2913
2914 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2915 device, nir[MESA_SHADER_GEOMETRY], &info,
2916 &gs_copy_binary, keep_executable_info, keep_statistic_info,
2917 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2918 }
2919
2920 if (!keep_executable_info && !keep_statistic_info && pipeline->gs_copy_shader) {
2921 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2922 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2923
2924 binaries[MESA_SHADER_GEOMETRY] = gs_copy_binary;
2925 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2926
2927 radv_pipeline_cache_insert_shaders(device, cache,
2928 gs_copy_hash,
2929 variants,
2930 binaries);
2931 }
2932 free(gs_copy_binary);
2933 }
2934
2935 if (nir[MESA_SHADER_FRAGMENT]) {
2936 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
2937 radv_start_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT]);
2938
2939 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2940 radv_shader_variant_compile(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
2941 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
2942 infos + MESA_SHADER_FRAGMENT,
2943 keep_executable_info, keep_statistic_info,
2944 &binaries[MESA_SHADER_FRAGMENT]);
2945
2946 radv_stop_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT], false);
2947 }
2948 }
2949
2950 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
2951 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
2952 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2953 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2954 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2955
2956 radv_start_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL]);
2957
2958 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
2959 pipeline->layout,
2960 &key, &infos[MESA_SHADER_TESS_CTRL], keep_executable_info,
2961 keep_statistic_info, &binaries[MESA_SHADER_TESS_CTRL]);
2962
2963 radv_stop_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL], false);
2964 }
2965 modules[MESA_SHADER_VERTEX] = NULL;
2966 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2967 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2968 }
2969
2970 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
2971 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2972 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
2973 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2974
2975 radv_start_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY]);
2976
2977 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2978 pipeline->layout,
2979 &keys[pre_stage], &infos[MESA_SHADER_GEOMETRY], keep_executable_info,
2980 keep_statistic_info, &binaries[MESA_SHADER_GEOMETRY]);
2981
2982 radv_stop_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY], false);
2983 }
2984 modules[pre_stage] = NULL;
2985 }
2986
2987 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2988 if(modules[i] && !pipeline->shaders[i]) {
2989 if (i == MESA_SHADER_TESS_CTRL) {
2990 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.ls_outputs_written);
2991 }
2992 if (i == MESA_SHADER_TESS_EVAL) {
2993 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2994 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2995 }
2996
2997 radv_start_feedback(stage_feedbacks[i]);
2998
2999 pipeline->shaders[i] = radv_shader_variant_compile(device, modules[i], &nir[i], 1,
3000 pipeline->layout,
3001 keys + i, infos + i, keep_executable_info,
3002 keep_statistic_info, &binaries[i]);
3003
3004 radv_stop_feedback(stage_feedbacks[i], false);
3005 }
3006 }
3007
3008 if (!keep_executable_info && !keep_statistic_info) {
3009 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
3010 binaries);
3011 }
3012
3013 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
3014 free(binaries[i]);
3015 if (nir[i]) {
3016 ralloc_free(nir[i]);
3017
3018 if (radv_can_dump_shader_stats(device, modules[i]))
3019 radv_shader_dump_stats(device,
3020 pipeline->shaders[i],
3021 i, stderr);
3022 }
3023 }
3024
3025 if (fs_m.nir)
3026 ralloc_free(fs_m.nir);
3027
3028 radv_stop_feedback(pipeline_feedback, false);
3029 return VK_SUCCESS;
3030 }
3031
3032 static uint32_t
3033 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
3034 gl_shader_stage stage, enum chip_class chip_class)
3035 {
3036 bool has_gs = radv_pipeline_has_gs(pipeline);
3037 bool has_tess = radv_pipeline_has_tess(pipeline);
3038 bool has_ngg = radv_pipeline_has_ngg(pipeline);
3039
3040 switch (stage) {
3041 case MESA_SHADER_FRAGMENT:
3042 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
3043 case MESA_SHADER_VERTEX:
3044 if (has_tess) {
3045 if (chip_class >= GFX10) {
3046 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
3047 } else if (chip_class == GFX9) {
3048 return R_00B430_SPI_SHADER_USER_DATA_LS_0;
3049 } else {
3050 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
3051 }
3052
3053 }
3054
3055 if (has_gs) {
3056 if (chip_class >= GFX10) {
3057 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3058 } else {
3059 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
3060 }
3061 }
3062
3063 if (has_ngg)
3064 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3065
3066 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
3067 case MESA_SHADER_GEOMETRY:
3068 return chip_class == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
3069 R_00B230_SPI_SHADER_USER_DATA_GS_0;
3070 case MESA_SHADER_COMPUTE:
3071 return R_00B900_COMPUTE_USER_DATA_0;
3072 case MESA_SHADER_TESS_CTRL:
3073 return chip_class == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
3074 R_00B430_SPI_SHADER_USER_DATA_HS_0;
3075 case MESA_SHADER_TESS_EVAL:
3076 if (has_gs) {
3077 return chip_class >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0 :
3078 R_00B330_SPI_SHADER_USER_DATA_ES_0;
3079 } else if (has_ngg) {
3080 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3081 } else {
3082 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
3083 }
3084 default:
3085 unreachable("unknown shader");
3086 }
3087 }
3088
3089 struct radv_bin_size_entry {
3090 unsigned bpp;
3091 VkExtent2D extent;
3092 };
3093
3094 static VkExtent2D
3095 radv_gfx9_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3096 {
3097 static const struct radv_bin_size_entry color_size_table[][3][9] = {
3098 {
3099 /* One RB / SE */
3100 {
3101 /* One shader engine */
3102 { 0, {128, 128}},
3103 { 1, { 64, 128}},
3104 { 2, { 32, 128}},
3105 { 3, { 16, 128}},
3106 { 17, { 0, 0}},
3107 { UINT_MAX, { 0, 0}},
3108 },
3109 {
3110 /* Two shader engines */
3111 { 0, {128, 128}},
3112 { 2, { 64, 128}},
3113 { 3, { 32, 128}},
3114 { 5, { 16, 128}},
3115 { 17, { 0, 0}},
3116 { UINT_MAX, { 0, 0}},
3117 },
3118 {
3119 /* Four shader engines */
3120 { 0, {128, 128}},
3121 { 3, { 64, 128}},
3122 { 5, { 16, 128}},
3123 { 17, { 0, 0}},
3124 { UINT_MAX, { 0, 0}},
3125 },
3126 },
3127 {
3128 /* Two RB / SE */
3129 {
3130 /* One shader engine */
3131 { 0, {128, 128}},
3132 { 2, { 64, 128}},
3133 { 3, { 32, 128}},
3134 { 5, { 16, 128}},
3135 { 33, { 0, 0}},
3136 { UINT_MAX, { 0, 0}},
3137 },
3138 {
3139 /* Two shader engines */
3140 { 0, {128, 128}},
3141 { 3, { 64, 128}},
3142 { 5, { 32, 128}},
3143 { 9, { 16, 128}},
3144 { 33, { 0, 0}},
3145 { UINT_MAX, { 0, 0}},
3146 },
3147 {
3148 /* Four shader engines */
3149 { 0, {256, 256}},
3150 { 2, {128, 256}},
3151 { 3, {128, 128}},
3152 { 5, { 64, 128}},
3153 { 9, { 16, 128}},
3154 { 33, { 0, 0}},
3155 { UINT_MAX, { 0, 0}},
3156 },
3157 },
3158 {
3159 /* Four RB / SE */
3160 {
3161 /* One shader engine */
3162 { 0, {128, 256}},
3163 { 2, {128, 128}},
3164 { 3, { 64, 128}},
3165 { 5, { 32, 128}},
3166 { 9, { 16, 128}},
3167 { 33, { 0, 0}},
3168 { UINT_MAX, { 0, 0}},
3169 },
3170 {
3171 /* Two shader engines */
3172 { 0, {256, 256}},
3173 { 2, {128, 256}},
3174 { 3, {128, 128}},
3175 { 5, { 64, 128}},
3176 { 9, { 32, 128}},
3177 { 17, { 16, 128}},
3178 { 33, { 0, 0}},
3179 { UINT_MAX, { 0, 0}},
3180 },
3181 {
3182 /* Four shader engines */
3183 { 0, {256, 512}},
3184 { 2, {256, 256}},
3185 { 3, {128, 256}},
3186 { 5, {128, 128}},
3187 { 9, { 64, 128}},
3188 { 17, { 16, 128}},
3189 { 33, { 0, 0}},
3190 { UINT_MAX, { 0, 0}},
3191 },
3192 },
3193 };
3194 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
3195 {
3196 // One RB / SE
3197 {
3198 // One shader engine
3199 { 0, {128, 256}},
3200 { 2, {128, 128}},
3201 { 4, { 64, 128}},
3202 { 7, { 32, 128}},
3203 { 13, { 16, 128}},
3204 { 49, { 0, 0}},
3205 { UINT_MAX, { 0, 0}},
3206 },
3207 {
3208 // Two shader engines
3209 { 0, {256, 256}},
3210 { 2, {128, 256}},
3211 { 4, {128, 128}},
3212 { 7, { 64, 128}},
3213 { 13, { 32, 128}},
3214 { 25, { 16, 128}},
3215 { 49, { 0, 0}},
3216 { UINT_MAX, { 0, 0}},
3217 },
3218 {
3219 // Four shader engines
3220 { 0, {256, 512}},
3221 { 2, {256, 256}},
3222 { 4, {128, 256}},
3223 { 7, {128, 128}},
3224 { 13, { 64, 128}},
3225 { 25, { 16, 128}},
3226 { 49, { 0, 0}},
3227 { UINT_MAX, { 0, 0}},
3228 },
3229 },
3230 {
3231 // Two RB / SE
3232 {
3233 // One shader engine
3234 { 0, {256, 256}},
3235 { 2, {128, 256}},
3236 { 4, {128, 128}},
3237 { 7, { 64, 128}},
3238 { 13, { 32, 128}},
3239 { 25, { 16, 128}},
3240 { 97, { 0, 0}},
3241 { UINT_MAX, { 0, 0}},
3242 },
3243 {
3244 // Two shader engines
3245 { 0, {256, 512}},
3246 { 2, {256, 256}},
3247 { 4, {128, 256}},
3248 { 7, {128, 128}},
3249 { 13, { 64, 128}},
3250 { 25, { 32, 128}},
3251 { 49, { 16, 128}},
3252 { 97, { 0, 0}},
3253 { UINT_MAX, { 0, 0}},
3254 },
3255 {
3256 // Four shader engines
3257 { 0, {512, 512}},
3258 { 2, {256, 512}},
3259 { 4, {256, 256}},
3260 { 7, {128, 256}},
3261 { 13, {128, 128}},
3262 { 25, { 64, 128}},
3263 { 49, { 16, 128}},
3264 { 97, { 0, 0}},
3265 { UINT_MAX, { 0, 0}},
3266 },
3267 },
3268 {
3269 // Four RB / SE
3270 {
3271 // One shader engine
3272 { 0, {256, 512}},
3273 { 2, {256, 256}},
3274 { 4, {128, 256}},
3275 { 7, {128, 128}},
3276 { 13, { 64, 128}},
3277 { 25, { 32, 128}},
3278 { 49, { 16, 128}},
3279 { UINT_MAX, { 0, 0}},
3280 },
3281 {
3282 // Two shader engines
3283 { 0, {512, 512}},
3284 { 2, {256, 512}},
3285 { 4, {256, 256}},
3286 { 7, {128, 256}},
3287 { 13, {128, 128}},
3288 { 25, { 64, 128}},
3289 { 49, { 32, 128}},
3290 { 97, { 16, 128}},
3291 { UINT_MAX, { 0, 0}},
3292 },
3293 {
3294 // Four shader engines
3295 { 0, {512, 512}},
3296 { 4, {256, 512}},
3297 { 7, {256, 256}},
3298 { 13, {128, 256}},
3299 { 25, {128, 128}},
3300 { 49, { 64, 128}},
3301 { 97, { 16, 128}},
3302 { UINT_MAX, { 0, 0}},
3303 },
3304 },
3305 };
3306
3307 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3308 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3309 VkExtent2D extent = {512, 512};
3310
3311 unsigned log_num_rb_per_se =
3312 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
3313 pipeline->device->physical_device->rad_info.max_se);
3314 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
3315
3316 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3317 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
3318 unsigned effective_samples = total_samples;
3319 unsigned color_bytes_per_pixel = 0;
3320
3321 const VkPipelineColorBlendStateCreateInfo *vkblend =
3322 radv_pipeline_get_color_blend_state(pCreateInfo);
3323 if (vkblend) {
3324 for (unsigned i = 0; i < subpass->color_count; i++) {
3325 if (!vkblend->pAttachments[i].colorWriteMask)
3326 continue;
3327
3328 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3329 continue;
3330
3331 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3332 color_bytes_per_pixel += vk_format_get_blocksize(format);
3333 }
3334
3335 /* MSAA images typically don't use all samples all the time. */
3336 if (effective_samples >= 2 && ps_iter_samples <= 1)
3337 effective_samples = 2;
3338 color_bytes_per_pixel *= effective_samples;
3339 }
3340
3341 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
3342 while(color_entry[1].bpp <= color_bytes_per_pixel)
3343 ++color_entry;
3344
3345 extent = color_entry->extent;
3346
3347 if (subpass->depth_stencil_attachment) {
3348 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3349
3350 /* Coefficients taken from AMDVLK */
3351 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3352 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3353 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
3354
3355 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
3356 while(ds_entry[1].bpp <= ds_bytes_per_pixel)
3357 ++ds_entry;
3358
3359 if (ds_entry->extent.width * ds_entry->extent.height < extent.width * extent.height)
3360 extent = ds_entry->extent;
3361 }
3362
3363 return extent;
3364 }
3365
3366 static VkExtent2D
3367 radv_gfx10_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3368 {
3369 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3370 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3371 VkExtent2D extent = {512, 512};
3372
3373 const unsigned db_tag_size = 64;
3374 const unsigned db_tag_count = 312;
3375 const unsigned color_tag_size = 1024;
3376 const unsigned color_tag_count = 31;
3377 const unsigned fmask_tag_size = 256;
3378 const unsigned fmask_tag_count = 44;
3379
3380 const unsigned rb_count = pipeline->device->physical_device->rad_info.num_render_backends;
3381 const unsigned pipe_count = MAX2(rb_count, pipeline->device->physical_device->rad_info.num_sdp_interfaces);
3382
3383 const unsigned db_tag_part = (db_tag_count * rb_count / pipe_count) * db_tag_size * pipe_count;
3384 const unsigned color_tag_part = (color_tag_count * rb_count / pipe_count) * color_tag_size * pipe_count;
3385 const unsigned fmask_tag_part = (fmask_tag_count * rb_count / pipe_count) * fmask_tag_size * pipe_count;
3386
3387 const unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3388 const unsigned samples_log = util_logbase2_ceil(total_samples);
3389
3390 unsigned color_bytes_per_pixel = 0;
3391 unsigned fmask_bytes_per_pixel = 0;
3392
3393 const VkPipelineColorBlendStateCreateInfo *vkblend =
3394 radv_pipeline_get_color_blend_state(pCreateInfo);
3395 if (vkblend) {
3396 for (unsigned i = 0; i < subpass->color_count; i++) {
3397 if (!vkblend->pAttachments[i].colorWriteMask)
3398 continue;
3399
3400 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3401 continue;
3402
3403 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3404 color_bytes_per_pixel += vk_format_get_blocksize(format);
3405
3406 if (total_samples > 1) {
3407 assert(samples_log <= 3);
3408 const unsigned fmask_array[] = {0, 1, 1, 4};
3409 fmask_bytes_per_pixel += fmask_array[samples_log];
3410 }
3411 }
3412
3413 color_bytes_per_pixel *= total_samples;
3414 }
3415 color_bytes_per_pixel = MAX2(color_bytes_per_pixel, 1);
3416
3417 const unsigned color_pixel_count_log = util_logbase2(color_tag_part / color_bytes_per_pixel);
3418 extent.width = 1ull << ((color_pixel_count_log + 1) / 2);
3419 extent.height = 1ull << (color_pixel_count_log / 2);
3420
3421 if (fmask_bytes_per_pixel) {
3422 const unsigned fmask_pixel_count_log = util_logbase2(fmask_tag_part / fmask_bytes_per_pixel);
3423
3424 const VkExtent2D fmask_extent = (VkExtent2D){
3425 .width = 1ull << ((fmask_pixel_count_log + 1) / 2),
3426 .height = 1ull << (color_pixel_count_log / 2)
3427 };
3428
3429 if (fmask_extent.width * fmask_extent.height < extent.width * extent.height)
3430 extent = fmask_extent;
3431 }
3432
3433 if (subpass->depth_stencil_attachment) {
3434 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3435
3436 /* Coefficients taken from AMDVLK */
3437 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3438 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3439 unsigned db_bytes_per_pixel = (depth_coeff + stencil_coeff) * total_samples;
3440
3441 const unsigned db_pixel_count_log = util_logbase2(db_tag_part / db_bytes_per_pixel);
3442
3443 const VkExtent2D db_extent = (VkExtent2D){
3444 .width = 1ull << ((db_pixel_count_log + 1) / 2),
3445 .height = 1ull << (color_pixel_count_log / 2)
3446 };
3447
3448 if (db_extent.width * db_extent.height < extent.width * extent.height)
3449 extent = db_extent;
3450 }
3451
3452 extent.width = MAX2(extent.width, 128);
3453 extent.height = MAX2(extent.width, 64);
3454
3455 return extent;
3456 }
3457
3458 static void
3459 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf *ctx_cs,
3460 struct radv_pipeline *pipeline,
3461 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3462 {
3463 uint32_t pa_sc_binner_cntl_0 =
3464 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
3465 S_028C44_DISABLE_START_OF_PRIM(1);
3466 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3467
3468 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3469 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3470 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3471 const VkPipelineColorBlendStateCreateInfo *vkblend =
3472 radv_pipeline_get_color_blend_state(pCreateInfo);
3473 unsigned min_bytes_per_pixel = 0;
3474
3475 if (vkblend) {
3476 for (unsigned i = 0; i < subpass->color_count; i++) {
3477 if (!vkblend->pAttachments[i].colorWriteMask)
3478 continue;
3479
3480 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3481 continue;
3482
3483 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3484 unsigned bytes = vk_format_get_blocksize(format);
3485 if (!min_bytes_per_pixel || bytes < min_bytes_per_pixel)
3486 min_bytes_per_pixel = bytes;
3487 }
3488 }
3489
3490 pa_sc_binner_cntl_0 =
3491 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) |
3492 S_028C44_BIN_SIZE_X(0) |
3493 S_028C44_BIN_SIZE_Y(0) |
3494 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3495 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel <= 4 ? 2 : 1) | /* 128 or 64 */
3496 S_028C44_DISABLE_START_OF_PRIM(1);
3497 }
3498
3499 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3500 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3501 }
3502
3503 struct radv_binning_settings
3504 radv_get_binning_settings(const struct radv_physical_device *pdev)
3505 {
3506 struct radv_binning_settings settings;
3507 if (pdev->rad_info.has_dedicated_vram) {
3508 if (pdev->rad_info.num_render_backends > 4) {
3509 settings.context_states_per_bin = 1;
3510 settings.persistent_states_per_bin = 1;
3511 } else {
3512 settings.context_states_per_bin = 3;
3513 settings.persistent_states_per_bin = 8;
3514 }
3515 settings.fpovs_per_batch = 63;
3516 } else {
3517 /* The context states are affected by the scissor bug. */
3518 settings.context_states_per_bin = 6;
3519 /* 32 causes hangs for RAVEN. */
3520 settings.persistent_states_per_bin = 16;
3521 settings.fpovs_per_batch = 63;
3522 }
3523
3524 if (pdev->rad_info.has_gfx9_scissor_bug)
3525 settings.context_states_per_bin = 1;
3526
3527 return settings;
3528 }
3529
3530 static void
3531 radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs,
3532 struct radv_pipeline *pipeline,
3533 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3534 const struct radv_blend_state *blend)
3535 {
3536 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
3537 return;
3538
3539 VkExtent2D bin_size;
3540 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3541 bin_size = radv_gfx10_compute_bin_size(pipeline, pCreateInfo);
3542 } else if (pipeline->device->physical_device->rad_info.chip_class == GFX9) {
3543 bin_size = radv_gfx9_compute_bin_size(pipeline, pCreateInfo);
3544 } else
3545 unreachable("Unhandled generation for binning bin size calculation");
3546
3547 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
3548 struct radv_binning_settings settings =
3549 radv_get_binning_settings(pipeline->device->physical_device);
3550
3551 bool disable_start_of_prim = true;
3552 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3553
3554 const struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3555
3556 if (pipeline->device->dfsm_allowed && ps &&
3557 !ps->info.ps.can_discard &&
3558 !ps->info.ps.writes_memory &&
3559 blend->cb_target_enabled_4bit) {
3560 db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_AUTO);
3561 disable_start_of_prim = (blend->blend_enable_4bit & blend->cb_target_enabled_4bit) != 0;
3562 }
3563
3564 const uint32_t pa_sc_binner_cntl_0 =
3565 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
3566 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
3567 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
3568 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
3569 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
3570 S_028C44_CONTEXT_STATES_PER_BIN(settings.context_states_per_bin - 1) |
3571 S_028C44_PERSISTENT_STATES_PER_BIN(settings.persistent_states_per_bin - 1) |
3572 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim) |
3573 S_028C44_FPOVS_PER_BATCH(settings.fpovs_per_batch) |
3574 S_028C44_OPTIMAL_BIN_SELECTION(1);
3575
3576 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3577 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3578 } else
3579 radv_pipeline_generate_disabled_binning_state(ctx_cs, pipeline, pCreateInfo);
3580 }
3581
3582
3583 static void
3584 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs,
3585 struct radv_pipeline *pipeline,
3586 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3587 const struct radv_graphics_pipeline_create_info *extra)
3588 {
3589 const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
3590 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3591 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3592 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3593 struct radv_render_pass_attachment *attachment = NULL;
3594 uint32_t db_depth_control = 0;
3595 uint32_t db_render_control = 0, db_render_override2 = 0;
3596 uint32_t db_render_override = 0;
3597
3598 if (subpass->depth_stencil_attachment)
3599 attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3600
3601 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
3602 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
3603
3604 if (vkds && has_depth_attachment) {
3605 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
3606 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
3607 S_028800_ZFUNC(vkds->depthCompareOp) |
3608 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
3609
3610 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3611 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
3612
3613 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10_3)
3614 db_render_override2 |= S_028010_CENTROID_COMPUTATION_MODE_GFX103(2);
3615 }
3616
3617 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
3618 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3619 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
3620
3621 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
3622 }
3623
3624 if (attachment && extra) {
3625 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
3626 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
3627
3628 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->resummarize_enable);
3629 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->depth_compress_disable);
3630 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->stencil_compress_disable);
3631 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
3632 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
3633 }
3634
3635 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3636 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
3637
3638 if (!pCreateInfo->pRasterizationState->depthClampEnable &&
3639 ps->info.ps.writes_z) {
3640 /* From VK_EXT_depth_range_unrestricted spec:
3641 *
3642 * "The behavior described in Primitive Clipping still applies.
3643 * If depth clamping is disabled the depth values are still
3644 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3645 * depth clamping is enabled the above equation is ignored and
3646 * the depth values are instead clamped to the VkViewport
3647 * minDepth and maxDepth values, which in the case of this
3648 * extension can be outside of the 0.0 to 1.0 range."
3649 */
3650 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3651 }
3652
3653 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control);
3654 radeon_set_context_reg(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
3655 radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
3656
3657 pipeline->graphics.db_depth_control = db_depth_control;
3658 }
3659
3660 static void
3661 radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
3662 struct radv_pipeline *pipeline,
3663 const struct radv_blend_state *blend)
3664 {
3665 radeon_set_context_reg_seq(ctx_cs, R_028780_CB_BLEND0_CONTROL, 8);
3666 radeon_emit_array(ctx_cs, blend->cb_blend_control,
3667 8);
3668 radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
3669 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
3670
3671 if (pipeline->device->physical_device->rad_info.has_rbplus) {
3672
3673 radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
3674 radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
3675 }
3676
3677 radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
3678
3679 radeon_set_context_reg(ctx_cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
3680 radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
3681
3682 pipeline->graphics.col_format = blend->spi_shader_col_format;
3683 pipeline->graphics.cb_target_mask = blend->cb_target_mask;
3684 }
3685
3686 static const VkConservativeRasterizationModeEXT
3687 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo)
3688 {
3689 const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster =
3690 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT);
3691
3692 if (!conservative_raster)
3693 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT;
3694 return conservative_raster->conservativeRasterizationMode;
3695 }
3696
3697 static void
3698 radv_pipeline_generate_raster_state(struct radeon_cmdbuf *ctx_cs,
3699 struct radv_pipeline *pipeline,
3700 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3701 {
3702 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
3703 const VkConservativeRasterizationModeEXT mode =
3704 radv_get_conservative_raster_mode(vkraster);
3705 uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3706 bool depth_clip_disable = vkraster->depthClampEnable;
3707
3708 const VkPipelineRasterizationDepthClipStateCreateInfoEXT *depth_clip_state =
3709 vk_find_struct_const(vkraster->pNext, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT);
3710 if (depth_clip_state) {
3711 depth_clip_disable = !depth_clip_state->depthClipEnable;
3712 }
3713
3714 radeon_set_context_reg(ctx_cs, R_028810_PA_CL_CLIP_CNTL,
3715 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3716 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable ? 1 : 0) |
3717 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable ? 1 : 0) |
3718 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
3719 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3720
3721 pipeline->graphics.pa_su_sc_mode_cntl =
3722 S_028814_FACE(vkraster->frontFace) |
3723 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
3724 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
3725 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
3726 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3727 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3728 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3729 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3730 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0);
3731
3732 radeon_set_context_reg(ctx_cs, R_028BDC_PA_SC_LINE_CNTL,
3733 S_028BDC_DX10_DIAMOND_TEST_ENA(1));
3734
3735 /* Conservative rasterization. */
3736 if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
3737 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3738
3739 ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3740 ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3741 S_028804_OVERRASTERIZATION_AMOUNT(4);
3742
3743 pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3744 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3745 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3746
3747 if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) {
3748 pa_sc_conservative_rast |=
3749 S_028C4C_OVER_RAST_ENABLE(1) |
3750 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3751 S_028C4C_UNDER_RAST_ENABLE(0) |
3752 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3753 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3754 } else {
3755 assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT);
3756 pa_sc_conservative_rast |=
3757 S_028C4C_OVER_RAST_ENABLE(0) |
3758 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3759 S_028C4C_UNDER_RAST_ENABLE(1) |
3760 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3761 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3762 }
3763 }
3764
3765 radeon_set_context_reg(ctx_cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
3766 pa_sc_conservative_rast);
3767 }
3768
3769
3770 static void
3771 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
3772 struct radv_pipeline *pipeline)
3773 {
3774 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3775
3776 radeon_set_context_reg_seq(ctx_cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3777 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[0]);
3778 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]);
3779
3780 radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa);
3781 radeon_set_context_reg(ctx_cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
3782 radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
3783 radeon_set_context_reg(ctx_cs, R_028BE0_PA_SC_AA_CONFIG, ms->pa_sc_aa_config);
3784
3785 /* The exclusion bits can be set to improve rasterization efficiency
3786 * if no sample lies on the pixel boundary (-8 sample offset). It's
3787 * currently always TRUE because the driver doesn't support 16 samples.
3788 */
3789 bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= GFX7;
3790 radeon_set_context_reg(ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3791 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3792 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3793
3794 /* GFX9: Flush DFSM when the AA mode changes. */
3795 if (pipeline->device->dfsm_allowed) {
3796 radeon_emit(ctx_cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3797 radeon_emit(ctx_cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3798 }
3799 }
3800
3801 static void
3802 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
3803 struct radv_pipeline *pipeline)
3804 {
3805 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3806 const struct radv_shader_variant *vs =
3807 pipeline->shaders[MESA_SHADER_TESS_EVAL] ?
3808 pipeline->shaders[MESA_SHADER_TESS_EVAL] :
3809 pipeline->shaders[MESA_SHADER_VERTEX];
3810 unsigned vgt_primitiveid_en = 0;
3811 uint32_t vgt_gs_mode = 0;
3812
3813 if (radv_pipeline_has_ngg(pipeline))
3814 return;
3815
3816 if (radv_pipeline_has_gs(pipeline)) {
3817 const struct radv_shader_variant *gs =
3818 pipeline->shaders[MESA_SHADER_GEOMETRY];
3819
3820 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
3821 pipeline->device->physical_device->rad_info.chip_class);
3822 } else if (outinfo->export_prim_id || vs->info.uses_prim_id) {
3823 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
3824 vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(1);
3825 }
3826
3827 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
3828 radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
3829 }
3830
3831 static void
3832 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
3833 struct radeon_cmdbuf *cs,
3834 struct radv_pipeline *pipeline,
3835 struct radv_shader_variant *shader)
3836 {
3837 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3838
3839 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
3840 radeon_emit(cs, va >> 8);
3841 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
3842 radeon_emit(cs, shader->config.rsrc1);
3843 radeon_emit(cs, shader->config.rsrc2);
3844
3845 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3846 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3847 clip_dist_mask = outinfo->clip_dist_mask;
3848 cull_dist_mask = outinfo->cull_dist_mask;
3849 total_mask = clip_dist_mask | cull_dist_mask;
3850 bool misc_vec_ena = outinfo->writes_pointsize ||
3851 outinfo->writes_layer ||
3852 outinfo->writes_viewport_index;
3853 unsigned spi_vs_out_config, nparams;
3854
3855 /* VS is required to export at least one param. */
3856 nparams = MAX2(outinfo->param_exports, 1);
3857 spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
3858
3859 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3860 spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0);
3861 }
3862
3863 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, spi_vs_out_config);
3864
3865 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3866 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3867 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3868 V_02870C_SPI_SHADER_4COMP :
3869 V_02870C_SPI_SHADER_NONE) |
3870 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3871 V_02870C_SPI_SHADER_4COMP :
3872 V_02870C_SPI_SHADER_NONE) |
3873 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3874 V_02870C_SPI_SHADER_4COMP :
3875 V_02870C_SPI_SHADER_NONE));
3876
3877 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3878 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3879 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3880 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3881 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3882 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3883 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3884 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3885 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) |
3886 cull_dist_mask << 8 |
3887 clip_dist_mask);
3888
3889 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
3890 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
3891 outinfo->writes_viewport_index);
3892 }
3893
3894 static void
3895 radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs,
3896 struct radv_pipeline *pipeline,
3897 struct radv_shader_variant *shader)
3898 {
3899 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3900
3901 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
3902 radeon_emit(cs, va >> 8);
3903 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3904 radeon_emit(cs, shader->config.rsrc1);
3905 radeon_emit(cs, shader->config.rsrc2);
3906 }
3907
3908 static void
3909 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs,
3910 struct radv_pipeline *pipeline,
3911 struct radv_shader_variant *shader,
3912 const struct radv_tessellation_state *tess)
3913 {
3914 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3915 uint32_t rsrc2 = shader->config.rsrc2;
3916
3917 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3918 radeon_emit(cs, va >> 8);
3919 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3920
3921 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
3922 if (pipeline->device->physical_device->rad_info.chip_class == GFX7 &&
3923 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
3924 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
3925
3926 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
3927 radeon_emit(cs, shader->config.rsrc1);
3928 radeon_emit(cs, rsrc2);
3929 }
3930
3931 static void
3932 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
3933 struct radeon_cmdbuf *cs,
3934 struct radv_pipeline *pipeline,
3935 struct radv_shader_variant *shader)
3936 {
3937 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3938 gl_shader_stage es_type =
3939 radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
3940 struct radv_shader_variant *es =
3941 es_type == MESA_SHADER_TESS_EVAL ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX];
3942 const struct gfx10_ngg_info *ngg_state = &shader->info.ngg_info;
3943
3944 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
3945 radeon_emit(cs, va >> 8);
3946 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3947 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
3948 radeon_emit(cs, shader->config.rsrc1);
3949 radeon_emit(cs, shader->config.rsrc2);
3950
3951 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3952 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3953 clip_dist_mask = outinfo->clip_dist_mask;
3954 cull_dist_mask = outinfo->cull_dist_mask;
3955 total_mask = clip_dist_mask | cull_dist_mask;
3956 bool misc_vec_ena = outinfo->writes_pointsize ||
3957 outinfo->writes_layer ||
3958 outinfo->writes_viewport_index;
3959 bool es_enable_prim_id = outinfo->export_prim_id ||
3960 (es && es->info.uses_prim_id);
3961 bool break_wave_at_eoi = false;
3962 unsigned ge_cntl;
3963 unsigned nparams;
3964
3965 if (es_type == MESA_SHADER_TESS_EVAL) {
3966 struct radv_shader_variant *gs =
3967 pipeline->shaders[MESA_SHADER_GEOMETRY];
3968
3969 if (es_enable_prim_id || (gs && gs->info.uses_prim_id))
3970 break_wave_at_eoi = true;
3971 }
3972
3973 nparams = MAX2(outinfo->param_exports, 1);
3974 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG,
3975 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
3976 S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0));
3977
3978 radeon_set_context_reg(ctx_cs, R_028708_SPI_SHADER_IDX_FORMAT,
3979 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP));
3980 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3981 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3982 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3983 V_02870C_SPI_SHADER_4COMP :
3984 V_02870C_SPI_SHADER_NONE) |
3985 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3986 V_02870C_SPI_SHADER_4COMP :
3987 V_02870C_SPI_SHADER_NONE) |
3988 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3989 V_02870C_SPI_SHADER_4COMP :
3990 V_02870C_SPI_SHADER_NONE));
3991
3992 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3993 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3994 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3995 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3996 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3997 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3998 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3999 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
4000 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3) |
4001 cull_dist_mask << 8 |
4002 clip_dist_mask);
4003
4004 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN,
4005 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
4006 S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo->export_prim_id));
4007
4008 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
4009 ngg_state->vgt_esgs_ring_itemsize);
4010
4011 /* NGG specific registers. */
4012 struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
4013 uint32_t gs_num_invocations = gs ? gs->info.gs.invocations : 1;
4014
4015 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
4016 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state->hw_max_esverts) |
4017 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state->max_gsprims) |
4018 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state->max_gsprims * gs_num_invocations));
4019 radeon_set_context_reg(ctx_cs, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
4020 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state->max_out_verts));
4021 radeon_set_context_reg(ctx_cs, R_028B4C_GE_NGG_SUBGRP_CNTL,
4022 S_028B4C_PRIM_AMP_FACTOR(ngg_state->prim_amp_factor) |
4023 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
4024 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
4025 S_028B90_CNT(gs_num_invocations) |
4026 S_028B90_ENABLE(gs_num_invocations > 1) |
4027 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state->max_vert_out_per_gs_instance));
4028
4029 /* User edge flags are set by the pos exports. If user edge flags are
4030 * not used, we must use hw-generated edge flags and pass them via
4031 * the prim export to prevent drawing lines on internal edges of
4032 * decomposed primitives (such as quads) with polygon mode = lines.
4033 *
4034 * TODO: We should combine hw-generated edge flags with user edge
4035 * flags in the shader.
4036 */
4037 radeon_set_context_reg(ctx_cs, R_028838_PA_CL_NGG_CNTL,
4038 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) &&
4039 !radv_pipeline_has_gs(pipeline)) |
4040 /* Reuse for NGG. */
4041 S_028838_VERTEX_REUSE_DEPTH_GFX103(pipeline->device->physical_device->rad_info.chip_class >= GFX10_3 ? 30 : 0));
4042
4043 ge_cntl = S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) |
4044 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
4045 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
4046
4047 /* Bug workaround for a possible hang with non-tessellation cases.
4048 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
4049 *
4050 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
4051 */
4052 if (pipeline->device->physical_device->rad_info.chip_class == GFX10 &&
4053 !radv_pipeline_has_tess(pipeline) &&
4054 ngg_state->hw_max_esverts != 256) {
4055 ge_cntl &= C_03096C_VERT_GRP_SIZE;
4056
4057 if (ngg_state->hw_max_esverts > 5) {
4058 ge_cntl |= S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts - 5);
4059 }
4060 }
4061
4062 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, ge_cntl);
4063 }
4064
4065 static void
4066 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
4067 struct radv_pipeline *pipeline,
4068 struct radv_shader_variant *shader,
4069 const struct radv_tessellation_state *tess)
4070 {
4071 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
4072
4073 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4074 unsigned hs_rsrc2 = shader->config.rsrc2;
4075
4076 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4077 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(tess->lds_size);
4078 } else {
4079 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(tess->lds_size);
4080 }
4081
4082 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4083 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
4084 radeon_emit(cs, va >> 8);
4085 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
4086 } else {
4087 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
4088 radeon_emit(cs, va >> 8);
4089 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
4090 }
4091
4092 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
4093 radeon_emit(cs, shader->config.rsrc1);
4094 radeon_emit(cs, hs_rsrc2);
4095 } else {
4096 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
4097 radeon_emit(cs, va >> 8);
4098 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
4099 radeon_emit(cs, shader->config.rsrc1);
4100 radeon_emit(cs, shader->config.rsrc2);
4101 }
4102 }
4103
4104 static void
4105 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *ctx_cs,
4106 struct radeon_cmdbuf *cs,
4107 struct radv_pipeline *pipeline,
4108 const struct radv_tessellation_state *tess)
4109 {
4110 struct radv_shader_variant *vs;
4111
4112 /* Skip shaders merged into HS/GS */
4113 vs = pipeline->shaders[MESA_SHADER_VERTEX];
4114 if (!vs)
4115 return;
4116
4117 if (vs->info.vs.as_ls)
4118 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
4119 else if (vs->info.vs.as_es)
4120 radv_pipeline_generate_hw_es(cs, pipeline, vs);
4121 else if (vs->info.is_ngg)
4122 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, vs);
4123 else
4124 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, vs);
4125 }
4126
4127 static void
4128 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs,
4129 struct radeon_cmdbuf *cs,
4130 struct radv_pipeline *pipeline,
4131 const struct radv_tessellation_state *tess)
4132 {
4133 if (!radv_pipeline_has_tess(pipeline))
4134 return;
4135
4136 struct radv_shader_variant *tes, *tcs;
4137
4138 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
4139 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
4140
4141 if (tes) {
4142 if (tes->info.is_ngg) {
4143 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, tes);
4144 } else if (tes->info.tes.as_es)
4145 radv_pipeline_generate_hw_es(cs, pipeline, tes);
4146 else
4147 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes);
4148 }
4149
4150 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
4151
4152 radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM,
4153 tess->tf_param);
4154
4155 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7)
4156 radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, 2,
4157 tess->ls_hs_config);
4158 else
4159 radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG,
4160 tess->ls_hs_config);
4161
4162 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 &&
4163 !radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
4164 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
4165 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4166 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4167 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4168 }
4169 }
4170
4171 static void
4172 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs,
4173 struct radeon_cmdbuf *cs,
4174 struct radv_pipeline *pipeline,
4175 struct radv_shader_variant *gs)
4176 {
4177 const struct gfx9_gs_info *gs_state = &gs->info.gs_ring_info;
4178 unsigned gs_max_out_vertices;
4179 uint8_t *num_components;
4180 uint8_t max_stream;
4181 unsigned offset;
4182 uint64_t va;
4183
4184 gs_max_out_vertices = gs->info.gs.vertices_out;
4185 max_stream = gs->info.gs.max_stream;
4186 num_components = gs->info.gs.num_stream_output_components;
4187
4188 offset = num_components[0] * gs_max_out_vertices;
4189
4190 radeon_set_context_reg_seq(ctx_cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
4191 radeon_emit(ctx_cs, offset);
4192 if (max_stream >= 1)
4193 offset += num_components[1] * gs_max_out_vertices;
4194 radeon_emit(ctx_cs, offset);
4195 if (max_stream >= 2)
4196 offset += num_components[2] * gs_max_out_vertices;
4197 radeon_emit(ctx_cs, offset);
4198 if (max_stream >= 3)
4199 offset += num_components[3] * gs_max_out_vertices;
4200 radeon_set_context_reg(ctx_cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
4201
4202 radeon_set_context_reg_seq(ctx_cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
4203 radeon_emit(ctx_cs, num_components[0]);
4204 radeon_emit(ctx_cs, (max_stream >= 1) ? num_components[1] : 0);
4205 radeon_emit(ctx_cs, (max_stream >= 2) ? num_components[2] : 0);
4206 radeon_emit(ctx_cs, (max_stream >= 3) ? num_components[3] : 0);
4207
4208 uint32_t gs_num_invocations = gs->info.gs.invocations;
4209 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
4210 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
4211 S_028B90_ENABLE(gs_num_invocations > 0));
4212
4213 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
4214 gs_state->vgt_esgs_ring_itemsize);
4215
4216 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
4217
4218 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4219 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4220 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
4221 radeon_emit(cs, va >> 8);
4222 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
4223 } else {
4224 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
4225 radeon_emit(cs, va >> 8);
4226 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
4227 }
4228
4229 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
4230 radeon_emit(cs, gs->config.rsrc1);
4231 radeon_emit(cs, gs->config.rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
4232
4233 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
4234 radeon_set_context_reg(ctx_cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
4235 } else {
4236 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
4237 radeon_emit(cs, va >> 8);
4238 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
4239 radeon_emit(cs, gs->config.rsrc1);
4240 radeon_emit(cs, gs->config.rsrc2);
4241 }
4242
4243 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, pipeline->gs_copy_shader);
4244 }
4245
4246 static void
4247 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
4248 struct radeon_cmdbuf *cs,
4249 struct radv_pipeline *pipeline)
4250 {
4251 struct radv_shader_variant *gs;
4252
4253 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
4254 if (!gs)
4255 return;
4256
4257 if (gs->info.is_ngg)
4258 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, gs);
4259 else
4260 radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs);
4261
4262 radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT,
4263 gs->info.gs.vertices_out);
4264 }
4265
4266 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade,
4267 bool explicit, bool float16)
4268 {
4269 uint32_t ps_input_cntl;
4270 if (offset <= AC_EXP_PARAM_OFFSET_31) {
4271 ps_input_cntl = S_028644_OFFSET(offset);
4272 if (flat_shade || explicit)
4273 ps_input_cntl |= S_028644_FLAT_SHADE(1);
4274 if (explicit) {
4275 /* Force parameter cache to be read in passthrough
4276 * mode.
4277 */
4278 ps_input_cntl |= S_028644_OFFSET(1 << 5);
4279 }
4280 if (float16) {
4281 ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) |
4282 S_028644_ATTR0_VALID(1);
4283 }
4284 } else {
4285 /* The input is a DEFAULT_VAL constant. */
4286 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
4287 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
4288 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
4289 ps_input_cntl = S_028644_OFFSET(0x20) |
4290 S_028644_DEFAULT_VAL(offset);
4291 }
4292 return ps_input_cntl;
4293 }
4294
4295 static void
4296 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
4297 struct radv_pipeline *pipeline)
4298 {
4299 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4300 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
4301 uint32_t ps_input_cntl[32];
4302
4303 unsigned ps_offset = 0;
4304
4305 if (ps->info.ps.prim_id_input) {
4306 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
4307 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4308 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4309 ++ps_offset;
4310 }
4311 }
4312
4313 if (ps->info.ps.layer_input ||
4314 ps->info.needs_multiview_view_index) {
4315 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
4316 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4317 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4318 else
4319 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false, false);
4320 ++ps_offset;
4321 }
4322
4323 if (ps->info.ps.viewport_index_input) {
4324 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VIEWPORT];
4325 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4326 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4327 else
4328 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false, false);
4329 ++ps_offset;
4330 }
4331
4332 if (ps->info.ps.has_pcoord) {
4333 unsigned val;
4334 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4335 ps_input_cntl[ps_offset] = val;
4336 ps_offset++;
4337 }
4338
4339 if (ps->info.ps.num_input_clips_culls) {
4340 unsigned vs_offset;
4341
4342 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
4343 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4344 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false, false);
4345 ++ps_offset;
4346 }
4347
4348 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
4349 if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
4350 ps->info.ps.num_input_clips_culls > 4) {
4351 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false, false);
4352 ++ps_offset;
4353 }
4354 }
4355
4356 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.ps.input_mask; ++i) {
4357 unsigned vs_offset;
4358 bool flat_shade;
4359 bool explicit;
4360 bool float16;
4361 if (!(ps->info.ps.input_mask & (1u << i)))
4362 continue;
4363
4364 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
4365 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
4366 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
4367 ++ps_offset;
4368 continue;
4369 }
4370
4371 flat_shade = !!(ps->info.ps.flat_shaded_mask & (1u << ps_offset));
4372 explicit = !!(ps->info.ps.explicit_shaded_mask & (1u << ps_offset));
4373 float16 = !!(ps->info.ps.float16_shaded_mask & (1u << ps_offset));
4374
4375 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade, explicit, float16);
4376 ++ps_offset;
4377 }
4378
4379 if (ps_offset) {
4380 radeon_set_context_reg_seq(ctx_cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
4381 for (unsigned i = 0; i < ps_offset; i++) {
4382 radeon_emit(ctx_cs, ps_input_cntl[i]);
4383 }
4384 }
4385 }
4386
4387 static uint32_t
4388 radv_compute_db_shader_control(const struct radv_device *device,
4389 const struct radv_pipeline *pipeline,
4390 const struct radv_shader_variant *ps)
4391 {
4392 unsigned conservative_z_export = V_02880C_EXPORT_ANY_Z;
4393 unsigned z_order;
4394 if (ps->info.ps.early_fragment_test || !ps->info.ps.writes_memory)
4395 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
4396 else
4397 z_order = V_02880C_LATE_Z;
4398
4399 if (ps->info.ps.depth_layout == FRAG_DEPTH_LAYOUT_GREATER)
4400 conservative_z_export = V_02880C_EXPORT_GREATER_THAN_Z;
4401 else if (ps->info.ps.depth_layout == FRAG_DEPTH_LAYOUT_LESS)
4402 conservative_z_export = V_02880C_EXPORT_LESS_THAN_Z;
4403
4404 bool disable_rbplus = device->physical_device->rad_info.has_rbplus &&
4405 !device->physical_device->rad_info.rbplus_allowed;
4406
4407 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4408 * but this appears to break Project Cars (DXVK). See
4409 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4410 */
4411 bool mask_export_enable = ps->info.ps.writes_sample_mask;
4412
4413 return S_02880C_Z_EXPORT_ENABLE(ps->info.ps.writes_z) |
4414 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.ps.writes_stencil) |
4415 S_02880C_KILL_ENABLE(!!ps->info.ps.can_discard) |
4416 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
4417 S_02880C_CONSERVATIVE_Z_EXPORT(conservative_z_export) |
4418 S_02880C_Z_ORDER(z_order) |
4419 S_02880C_DEPTH_BEFORE_SHADER(ps->info.ps.early_fragment_test) |
4420 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps->info.ps.post_depth_coverage) |
4421 S_02880C_EXEC_ON_HIER_FAIL(ps->info.ps.writes_memory) |
4422 S_02880C_EXEC_ON_NOOP(ps->info.ps.writes_memory) |
4423 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
4424 }
4425
4426 static void
4427 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs,
4428 struct radeon_cmdbuf *cs,
4429 struct radv_pipeline *pipeline)
4430 {
4431 struct radv_shader_variant *ps;
4432 uint64_t va;
4433 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
4434
4435 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4436 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
4437
4438 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
4439 radeon_emit(cs, va >> 8);
4440 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
4441 radeon_emit(cs, ps->config.rsrc1);
4442 radeon_emit(cs, ps->config.rsrc2);
4443
4444 radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL,
4445 radv_compute_db_shader_control(pipeline->device,
4446 pipeline, ps));
4447
4448 radeon_set_context_reg(ctx_cs, R_0286CC_SPI_PS_INPUT_ENA,
4449 ps->config.spi_ps_input_ena);
4450
4451 radeon_set_context_reg(ctx_cs, R_0286D0_SPI_PS_INPUT_ADDR,
4452 ps->config.spi_ps_input_addr);
4453
4454 radeon_set_context_reg(ctx_cs, R_0286D8_SPI_PS_IN_CONTROL,
4455 S_0286D8_NUM_INTERP(ps->info.ps.num_interp) |
4456 S_0286D8_PS_W32_EN(ps->info.wave_size == 32));
4457
4458 radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
4459
4460 radeon_set_context_reg(ctx_cs, R_028710_SPI_SHADER_Z_FORMAT,
4461 ac_get_spi_shader_z_format(ps->info.ps.writes_z,
4462 ps->info.ps.writes_stencil,
4463 ps->info.ps.writes_sample_mask));
4464
4465 if (pipeline->device->dfsm_allowed) {
4466 /* optimise this? */
4467 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4468 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
4469 }
4470 }
4471
4472 static void
4473 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs,
4474 struct radv_pipeline *pipeline)
4475 {
4476 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4477 pipeline->device->physical_device->rad_info.chip_class >= GFX10)
4478 return;
4479
4480 unsigned vtx_reuse_depth = 30;
4481 if (radv_pipeline_has_tess(pipeline) &&
4482 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
4483 vtx_reuse_depth = 14;
4484 }
4485 radeon_set_context_reg(ctx_cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
4486 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
4487 }
4488
4489 static void
4490 radv_pipeline_generate_vgt_shader_config(struct radeon_cmdbuf *ctx_cs,
4491 const struct radv_pipeline *pipeline)
4492 {
4493 uint32_t stages = 0;
4494 if (radv_pipeline_has_tess(pipeline)) {
4495 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
4496 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4497
4498 if (radv_pipeline_has_gs(pipeline))
4499 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
4500 S_028B54_GS_EN(1);
4501 else if (radv_pipeline_has_ngg(pipeline))
4502 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
4503 else
4504 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
4505 } else if (radv_pipeline_has_gs(pipeline)) {
4506 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
4507 S_028B54_GS_EN(1);
4508 } else if (radv_pipeline_has_ngg(pipeline)) {
4509 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
4510 }
4511
4512 if (radv_pipeline_has_ngg(pipeline)) {
4513 stages |= S_028B54_PRIMGEN_EN(1);
4514 if (pipeline->streamout_shader)
4515 stages |= S_028B54_NGG_WAVE_ID_EN(1);
4516 if (radv_pipeline_has_ngg_passthrough(pipeline))
4517 stages |= S_028B54_PRIMGEN_PASSTHRU_EN(1);
4518 } else if (radv_pipeline_has_gs(pipeline)) {
4519 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
4520 }
4521
4522 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
4523 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4524
4525 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4526 uint8_t hs_size = 64, gs_size = 64, vs_size = 64;
4527
4528 if (radv_pipeline_has_tess(pipeline))
4529 hs_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.wave_size;
4530
4531 if (pipeline->shaders[MESA_SHADER_GEOMETRY]) {
4532 vs_size = gs_size = pipeline->shaders[MESA_SHADER_GEOMETRY]->info.wave_size;
4533 if (pipeline->gs_copy_shader)
4534 vs_size = pipeline->gs_copy_shader->info.wave_size;
4535 } else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
4536 vs_size = pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.wave_size;
4537 else if (pipeline->shaders[MESA_SHADER_VERTEX])
4538 vs_size = pipeline->shaders[MESA_SHADER_VERTEX]->info.wave_size;
4539
4540 if (radv_pipeline_has_ngg(pipeline))
4541 gs_size = vs_size;
4542
4543 /* legacy GS only supports Wave64 */
4544 stages |= S_028B54_HS_W32_EN(hs_size == 32 ? 1 : 0) |
4545 S_028B54_GS_W32_EN(gs_size == 32 ? 1 : 0) |
4546 S_028B54_VS_W32_EN(vs_size == 32 ? 1 : 0);
4547 }
4548
4549 radeon_set_context_reg(ctx_cs, R_028B54_VGT_SHADER_STAGES_EN, stages);
4550 }
4551
4552 static void
4553 radv_pipeline_generate_cliprect_rule(struct radeon_cmdbuf *ctx_cs,
4554 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4555 {
4556 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
4557 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
4558 uint32_t cliprect_rule = 0;
4559
4560 if (!discard_rectangle_info) {
4561 cliprect_rule = 0xffff;
4562 } else {
4563 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
4564 /* Interpret i as a bitmask, and then set the bit in
4565 * the mask if that combination of rectangles in which
4566 * the pixel is contained should pass the cliprect
4567 * test.
4568 */
4569 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
4570
4571 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
4572 !relevant_subset)
4573 continue;
4574
4575 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
4576 relevant_subset)
4577 continue;
4578
4579 cliprect_rule |= 1u << i;
4580 }
4581 }
4582
4583 radeon_set_context_reg(ctx_cs, R_02820C_PA_SC_CLIPRECT_RULE, cliprect_rule);
4584 }
4585
4586 static void
4587 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf *ctx_cs,
4588 struct radv_pipeline *pipeline)
4589 {
4590 bool break_wave_at_eoi = false;
4591 unsigned primgroup_size;
4592 unsigned vertgroup_size = 256; /* 256 = disable vertex grouping */
4593
4594 if (radv_pipeline_has_tess(pipeline)) {
4595 primgroup_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
4596 } else if (radv_pipeline_has_gs(pipeline)) {
4597 const struct gfx9_gs_info *gs_state =
4598 &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs_ring_info;
4599 unsigned vgt_gs_onchip_cntl = gs_state->vgt_gs_onchip_cntl;
4600 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
4601 } else {
4602 primgroup_size = 128; /* recommended without a GS and tess */
4603 }
4604
4605 if (radv_pipeline_has_tess(pipeline)) {
4606 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4607 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4608 break_wave_at_eoi = true;
4609 }
4610
4611 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL,
4612 S_03096C_PRIM_GRP_SIZE(primgroup_size) |
4613 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
4614 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4615 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi));
4616 }
4617
4618 static void
4619 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
4620 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4621 const struct radv_graphics_pipeline_create_info *extra,
4622 const struct radv_blend_state *blend,
4623 const struct radv_tessellation_state *tess,
4624 unsigned gs_out)
4625 {
4626 struct radeon_cmdbuf *ctx_cs = &pipeline->ctx_cs;
4627 struct radeon_cmdbuf *cs = &pipeline->cs;
4628
4629 cs->max_dw = 64;
4630 ctx_cs->max_dw = 256;
4631 cs->buf = malloc(4 * (cs->max_dw + ctx_cs->max_dw));
4632 ctx_cs->buf = cs->buf + cs->max_dw;
4633
4634 radv_pipeline_generate_depth_stencil_state(ctx_cs, pipeline, pCreateInfo, extra);
4635 radv_pipeline_generate_blend_state(ctx_cs, pipeline, blend);
4636 radv_pipeline_generate_raster_state(ctx_cs, pipeline, pCreateInfo);
4637 radv_pipeline_generate_multisample_state(ctx_cs, pipeline);
4638 radv_pipeline_generate_vgt_gs_mode(ctx_cs, pipeline);
4639 radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline, tess);
4640 radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline, tess);
4641 radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline);
4642 radv_pipeline_generate_fragment_shader(ctx_cs, cs, pipeline);
4643 radv_pipeline_generate_ps_inputs(ctx_cs, pipeline);
4644 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline);
4645 radv_pipeline_generate_binning_state(ctx_cs, pipeline, pCreateInfo, blend);
4646 radv_pipeline_generate_vgt_shader_config(ctx_cs, pipeline);
4647 radv_pipeline_generate_cliprect_rule(ctx_cs, pCreateInfo);
4648
4649 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && !radv_pipeline_has_ngg(pipeline))
4650 gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline);
4651
4652 radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
4653
4654 pipeline->ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4);
4655
4656 assert(ctx_cs->cdw <= ctx_cs->max_dw);
4657 assert(cs->cdw <= cs->max_dw);
4658 }
4659
4660 static struct radv_ia_multi_vgt_param_helpers
4661 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline)
4662 {
4663 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
4664 const struct radv_device *device = pipeline->device;
4665
4666 if (radv_pipeline_has_tess(pipeline))
4667 ia_multi_vgt_param.primgroup_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
4668 else if (radv_pipeline_has_gs(pipeline))
4669 ia_multi_vgt_param.primgroup_size = 64;
4670 else
4671 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
4672
4673 /* GS requirement. */
4674 ia_multi_vgt_param.partial_es_wave = false;
4675 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= GFX8)
4676 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
4677 ia_multi_vgt_param.partial_es_wave = true;
4678
4679 ia_multi_vgt_param.ia_switch_on_eoi = false;
4680 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input)
4681 ia_multi_vgt_param.ia_switch_on_eoi = true;
4682 if (radv_pipeline_has_gs(pipeline) &&
4683 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.uses_prim_id)
4684 ia_multi_vgt_param.ia_switch_on_eoi = true;
4685 if (radv_pipeline_has_tess(pipeline)) {
4686 /* SWITCH_ON_EOI must be set if PrimID is used. */
4687 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4688 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4689 ia_multi_vgt_param.ia_switch_on_eoi = true;
4690 }
4691
4692 ia_multi_vgt_param.partial_vs_wave = false;
4693 if (radv_pipeline_has_tess(pipeline)) {
4694 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4695 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
4696 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
4697 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
4698 radv_pipeline_has_gs(pipeline))
4699 ia_multi_vgt_param.partial_vs_wave = true;
4700 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4701 if (device->physical_device->rad_info.has_distributed_tess) {
4702 if (radv_pipeline_has_gs(pipeline)) {
4703 if (device->physical_device->rad_info.chip_class <= GFX8)
4704 ia_multi_vgt_param.partial_es_wave = true;
4705 } else {
4706 ia_multi_vgt_param.partial_vs_wave = true;
4707 }
4708 }
4709 }
4710
4711 if (radv_pipeline_has_gs(pipeline)) {
4712 /* On these chips there is the possibility of a hang if the
4713 * pipeline uses a GS and partial_vs_wave is not set.
4714 *
4715 * This mostly does not hit 4-SE chips, as those typically set
4716 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4717 * with GS due to another workaround.
4718 *
4719 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4720 */
4721 if (device->physical_device->rad_info.family == CHIP_TONGA ||
4722 device->physical_device->rad_info.family == CHIP_FIJI ||
4723 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
4724 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
4725 device->physical_device->rad_info.family == CHIP_POLARIS12 ||
4726 device->physical_device->rad_info.family == CHIP_VEGAM) {
4727 ia_multi_vgt_param.partial_vs_wave = true;
4728 }
4729 }
4730
4731 ia_multi_vgt_param.base =
4732 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
4733 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4734 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == GFX8 ? 2 : 0) |
4735 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
4736 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
4737
4738 return ia_multi_vgt_param;
4739 }
4740
4741
4742 static void
4743 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
4744 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4745 {
4746 const VkPipelineVertexInputStateCreateInfo *vi_info =
4747 pCreateInfo->pVertexInputState;
4748
4749 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
4750 const VkVertexInputBindingDescription *desc =
4751 &vi_info->pVertexBindingDescriptions[i];
4752
4753 pipeline->binding_stride[desc->binding] = desc->stride;
4754 pipeline->num_vertex_bindings =
4755 MAX2(pipeline->num_vertex_bindings, desc->binding + 1);
4756 }
4757 }
4758
4759 static struct radv_shader_variant *
4760 radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline)
4761 {
4762 int i;
4763
4764 for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) {
4765 struct radv_shader_variant *shader =
4766 radv_get_shader(pipeline, i);
4767
4768 if (shader && shader->info.so.num_outputs > 0)
4769 return shader;
4770 }
4771
4772 return NULL;
4773 }
4774
4775 static VkResult
4776 radv_pipeline_init(struct radv_pipeline *pipeline,
4777 struct radv_device *device,
4778 struct radv_pipeline_cache *cache,
4779 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4780 const struct radv_graphics_pipeline_create_info *extra)
4781 {
4782 VkResult result;
4783
4784 pipeline->device = device;
4785 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
4786 assert(pipeline->layout);
4787
4788 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
4789
4790 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
4791 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
4792 radv_init_feedback(creation_feedback);
4793
4794 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
4795
4796 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
4797 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
4798 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
4799 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
4800 pStages[stage] = &pCreateInfo->pStages[i];
4801 if(creation_feedback)
4802 stage_feedbacks[stage] = &creation_feedback->pPipelineStageCreationFeedbacks[i];
4803 }
4804
4805 struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend);
4806
4807 result = radv_create_shaders(pipeline, device, cache, &key, pStages,
4808 pCreateInfo->flags, pipeline_feedback,
4809 stage_feedbacks);
4810 if (result != VK_SUCCESS)
4811 return result;
4812
4813 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
4814 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
4815 uint32_t gs_out;
4816
4817 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
4818
4819 if (radv_pipeline_has_gs(pipeline)) {
4820 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
4821 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4822 } else if (radv_pipeline_has_tess(pipeline)) {
4823 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode)
4824 gs_out = V_028A6C_OUTPRIM_TYPE_POINTLIST;
4825 else
4826 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.primitive_mode);
4827 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4828 } else {
4829 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
4830 }
4831 if (extra && extra->use_rectlist) {
4832 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
4833 pipeline->graphics.can_use_guardband = true;
4834 if (radv_pipeline_has_ngg(pipeline))
4835 gs_out = V_028A6C_VGT_OUT_RECT_V0;
4836 }
4837 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
4838
4839 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo, extra);
4840
4841 /* Ensure that some export memory is always allocated, for two reasons:
4842 *
4843 * 1) Correctness: The hardware ignores the EXEC mask if no export
4844 * memory is allocated, so KILL and alpha test do not work correctly
4845 * without this.
4846 * 2) Performance: Every shader needs at least a NULL export, even when
4847 * it writes no color/depth output. The NULL export instruction
4848 * stalls without this setting.
4849 *
4850 * Don't add this to CB_SHADER_MASK.
4851 *
4852 * GFX10 supports pixel shaders without exports by setting both the
4853 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
4854 * instructions if any are present.
4855 */
4856 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4857 if ((pipeline->device->physical_device->rad_info.chip_class <= GFX9 ||
4858 ps->info.ps.can_discard) &&
4859 !blend.spi_shader_col_format) {
4860 if (!ps->info.ps.writes_z &&
4861 !ps->info.ps.writes_stencil &&
4862 !ps->info.ps.writes_sample_mask)
4863 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
4864 }
4865
4866 blend.cb_shader_mask = ps->info.ps.cb_shader_mask;
4867
4868 if (extra &&
4869 (extra->custom_blend_mode == V_028808_CB_ELIMINATE_FAST_CLEAR ||
4870 extra->custom_blend_mode == V_028808_CB_FMASK_DECOMPRESS ||
4871 extra->custom_blend_mode == V_028808_CB_DCC_DECOMPRESS ||
4872 extra->custom_blend_mode == V_028808_CB_RESOLVE)) {
4873 /* According to the CB spec states, CB_SHADER_MASK should be
4874 * set to enable writes to all four channels of MRT0.
4875 */
4876 blend.cb_shader_mask = 0xf;
4877 }
4878
4879 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
4880 if (pipeline->shaders[i]) {
4881 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
4882 }
4883 }
4884
4885 if (radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
4886 struct radv_shader_variant *gs =
4887 pipeline->shaders[MESA_SHADER_GEOMETRY];
4888
4889 calculate_gs_ring_sizes(pipeline, &gs->info.gs_ring_info);
4890 }
4891
4892 struct radv_tessellation_state tess = {0};
4893 if (radv_pipeline_has_tess(pipeline)) {
4894 pipeline->graphics.tess_patch_control_points =
4895 pCreateInfo->pTessellationState->patchControlPoints;
4896 tess = calculate_tess_state(pipeline, pCreateInfo);
4897 }
4898
4899 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline);
4900
4901 radv_compute_vertex_input_state(pipeline, pCreateInfo);
4902
4903 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
4904 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
4905
4906 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
4907 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
4908 if (loc->sgpr_idx != -1) {
4909 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
4910 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
4911 if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id)
4912 pipeline->graphics.vtx_emit_num = 3;
4913 else
4914 pipeline->graphics.vtx_emit_num = 2;
4915 }
4916
4917 /* Find the last vertex shader stage that eventually uses streamout. */
4918 pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline);
4919
4920 result = radv_pipeline_scratch_init(device, pipeline);
4921 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, gs_out);
4922
4923 return result;
4924 }
4925
4926 VkResult
4927 radv_graphics_pipeline_create(
4928 VkDevice _device,
4929 VkPipelineCache _cache,
4930 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4931 const struct radv_graphics_pipeline_create_info *extra,
4932 const VkAllocationCallbacks *pAllocator,
4933 VkPipeline *pPipeline)
4934 {
4935 RADV_FROM_HANDLE(radv_device, device, _device);
4936 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
4937 struct radv_pipeline *pipeline;
4938 VkResult result;
4939
4940 pipeline = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8,
4941 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
4942 if (pipeline == NULL)
4943 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
4944
4945 vk_object_base_init(&device->vk, &pipeline->base,
4946 VK_OBJECT_TYPE_PIPELINE);
4947
4948 result = radv_pipeline_init(pipeline, device, cache,
4949 pCreateInfo, extra);
4950 if (result != VK_SUCCESS) {
4951 radv_pipeline_destroy(device, pipeline, pAllocator);
4952 return result;
4953 }
4954
4955 *pPipeline = radv_pipeline_to_handle(pipeline);
4956
4957 return VK_SUCCESS;
4958 }
4959
4960 VkResult radv_CreateGraphicsPipelines(
4961 VkDevice _device,
4962 VkPipelineCache pipelineCache,
4963 uint32_t count,
4964 const VkGraphicsPipelineCreateInfo* pCreateInfos,
4965 const VkAllocationCallbacks* pAllocator,
4966 VkPipeline* pPipelines)
4967 {
4968 VkResult result = VK_SUCCESS;
4969 unsigned i = 0;
4970
4971 for (; i < count; i++) {
4972 VkResult r;
4973 r = radv_graphics_pipeline_create(_device,
4974 pipelineCache,
4975 &pCreateInfos[i],
4976 NULL, pAllocator, &pPipelines[i]);
4977 if (r != VK_SUCCESS) {
4978 result = r;
4979 pPipelines[i] = VK_NULL_HANDLE;
4980
4981 if (pCreateInfos[i].flags & VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT)
4982 break;
4983 }
4984 }
4985
4986 for (; i < count; ++i)
4987 pPipelines[i] = VK_NULL_HANDLE;
4988
4989 return result;
4990 }
4991
4992 static void
4993 radv_pipeline_generate_hw_cs(struct radeon_cmdbuf *cs,
4994 struct radv_pipeline *pipeline)
4995 {
4996 struct radv_shader_variant *shader = pipeline->shaders[MESA_SHADER_COMPUTE];
4997 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
4998 struct radv_device *device = pipeline->device;
4999
5000 radeon_set_sh_reg_seq(cs, R_00B830_COMPUTE_PGM_LO, 2);
5001 radeon_emit(cs, va >> 8);
5002 radeon_emit(cs, S_00B834_DATA(va >> 40));
5003
5004 radeon_set_sh_reg_seq(cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
5005 radeon_emit(cs, shader->config.rsrc1);
5006 radeon_emit(cs, shader->config.rsrc2);
5007 if (device->physical_device->rad_info.chip_class >= GFX10) {
5008 radeon_set_sh_reg(cs, R_00B8A0_COMPUTE_PGM_RSRC3, shader->config.rsrc3);
5009 }
5010 }
5011
5012 static void
5013 radv_pipeline_generate_compute_state(struct radeon_cmdbuf *cs,
5014 struct radv_pipeline *pipeline)
5015 {
5016 struct radv_shader_variant *shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5017 struct radv_device *device = pipeline->device;
5018 unsigned threads_per_threadgroup;
5019 unsigned threadgroups_per_cu = 1;
5020 unsigned waves_per_threadgroup;
5021 unsigned max_waves_per_sh = 0;
5022
5023 /* Calculate best compute resource limits. */
5024 threads_per_threadgroup = shader->info.cs.block_size[0] *
5025 shader->info.cs.block_size[1] *
5026 shader->info.cs.block_size[2];
5027 waves_per_threadgroup = DIV_ROUND_UP(threads_per_threadgroup,
5028 shader->info.wave_size);
5029
5030 if (device->physical_device->rad_info.chip_class >= GFX10 &&
5031 waves_per_threadgroup == 1)
5032 threadgroups_per_cu = 2;
5033
5034 radeon_set_sh_reg(cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
5035 ac_get_compute_resource_limits(&device->physical_device->rad_info,
5036 waves_per_threadgroup,
5037 max_waves_per_sh,
5038 threadgroups_per_cu));
5039
5040 radeon_set_sh_reg_seq(cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5041 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(shader->info.cs.block_size[0]));
5042 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(shader->info.cs.block_size[1]));
5043 radeon_emit(cs, S_00B81C_NUM_THREAD_FULL(shader->info.cs.block_size[2]));
5044 }
5045
5046 static void
5047 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
5048 {
5049 struct radv_device *device = pipeline->device;
5050 struct radeon_cmdbuf *cs = &pipeline->cs;
5051
5052 cs->max_dw = device->physical_device->rad_info.chip_class >= GFX10 ? 19 : 16;
5053 cs->buf = malloc(cs->max_dw * 4);
5054
5055 radv_pipeline_generate_hw_cs(cs, pipeline);
5056 radv_pipeline_generate_compute_state(cs, pipeline);
5057
5058 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
5059 }
5060
5061 static struct radv_pipeline_key
5062 radv_generate_compute_pipeline_key(struct radv_pipeline *pipeline,
5063 const VkComputePipelineCreateInfo *pCreateInfo)
5064 {
5065 const VkPipelineShaderStageCreateInfo *stage = &pCreateInfo->stage;
5066 struct radv_pipeline_key key;
5067 memset(&key, 0, sizeof(key));
5068
5069 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
5070 key.optimisations_disabled = 1;
5071
5072 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT *subgroup_size =
5073 vk_find_struct_const(stage->pNext,
5074 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT);
5075
5076 if (subgroup_size) {
5077 assert(subgroup_size->requiredSubgroupSize == 32 ||
5078 subgroup_size->requiredSubgroupSize == 64);
5079 key.compute_subgroup_size = subgroup_size->requiredSubgroupSize;
5080 }
5081
5082 return key;
5083 }
5084
5085 static VkResult radv_compute_pipeline_create(
5086 VkDevice _device,
5087 VkPipelineCache _cache,
5088 const VkComputePipelineCreateInfo* pCreateInfo,
5089 const VkAllocationCallbacks* pAllocator,
5090 VkPipeline* pPipeline)
5091 {
5092 RADV_FROM_HANDLE(radv_device, device, _device);
5093 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
5094 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
5095 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
5096 struct radv_pipeline *pipeline;
5097 VkResult result;
5098
5099 pipeline = vk_zalloc2(&device->vk.alloc, pAllocator, sizeof(*pipeline), 8,
5100 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5101 if (pipeline == NULL)
5102 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5103
5104 vk_object_base_init(&device->vk, &pipeline->base,
5105 VK_OBJECT_TYPE_PIPELINE);
5106
5107 pipeline->device = device;
5108 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
5109 assert(pipeline->layout);
5110
5111 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
5112 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
5113 radv_init_feedback(creation_feedback);
5114
5115 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
5116 if (creation_feedback)
5117 stage_feedbacks[MESA_SHADER_COMPUTE] = &creation_feedback->pPipelineStageCreationFeedbacks[0];
5118
5119 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
5120
5121 struct radv_pipeline_key key =
5122 radv_generate_compute_pipeline_key(pipeline, pCreateInfo);
5123
5124 result = radv_create_shaders(pipeline, device, cache, &key, pStages,
5125 pCreateInfo->flags, pipeline_feedback,
5126 stage_feedbacks);
5127 if (result != VK_SUCCESS) {
5128 radv_pipeline_destroy(device, pipeline, pAllocator);
5129 return result;
5130 }
5131
5132 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
5133 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
5134 result = radv_pipeline_scratch_init(device, pipeline);
5135 if (result != VK_SUCCESS) {
5136 radv_pipeline_destroy(device, pipeline, pAllocator);
5137 return result;
5138 }
5139
5140 radv_compute_generate_pm4(pipeline);
5141
5142 *pPipeline = radv_pipeline_to_handle(pipeline);
5143
5144 return VK_SUCCESS;
5145 }
5146
5147 VkResult radv_CreateComputePipelines(
5148 VkDevice _device,
5149 VkPipelineCache pipelineCache,
5150 uint32_t count,
5151 const VkComputePipelineCreateInfo* pCreateInfos,
5152 const VkAllocationCallbacks* pAllocator,
5153 VkPipeline* pPipelines)
5154 {
5155 VkResult result = VK_SUCCESS;
5156
5157 unsigned i = 0;
5158 for (; i < count; i++) {
5159 VkResult r;
5160 r = radv_compute_pipeline_create(_device, pipelineCache,
5161 &pCreateInfos[i],
5162 pAllocator, &pPipelines[i]);
5163 if (r != VK_SUCCESS) {
5164 result = r;
5165 pPipelines[i] = VK_NULL_HANDLE;
5166
5167 if (pCreateInfos[i].flags & VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT)
5168 break;
5169 }
5170 }
5171
5172 for (; i < count; ++i)
5173 pPipelines[i] = VK_NULL_HANDLE;
5174
5175 return result;
5176 }
5177
5178
5179 static uint32_t radv_get_executable_count(const struct radv_pipeline *pipeline)
5180 {
5181 uint32_t ret = 0;
5182 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5183 if (!pipeline->shaders[i])
5184 continue;
5185
5186 if (i == MESA_SHADER_GEOMETRY &&
5187 !radv_pipeline_has_ngg(pipeline)) {
5188 ret += 2u;
5189 } else {
5190 ret += 1u;
5191 }
5192
5193 }
5194 return ret;
5195 }
5196
5197 static struct radv_shader_variant *
5198 radv_get_shader_from_executable_index(const struct radv_pipeline *pipeline, int index, gl_shader_stage *stage)
5199 {
5200 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5201 if (!pipeline->shaders[i])
5202 continue;
5203 if (!index) {
5204 *stage = i;
5205 return pipeline->shaders[i];
5206 }
5207
5208 --index;
5209
5210 if (i == MESA_SHADER_GEOMETRY &&
5211 !radv_pipeline_has_ngg(pipeline)) {
5212 if (!index) {
5213 *stage = i;
5214 return pipeline->gs_copy_shader;
5215 }
5216 --index;
5217 }
5218 }
5219
5220 *stage = -1;
5221 return NULL;
5222 }
5223
5224 /* Basically strlcpy (which does not exist on linux) specialized for
5225 * descriptions. */
5226 static void desc_copy(char *desc, const char *src) {
5227 int len = strlen(src);
5228 assert(len < VK_MAX_DESCRIPTION_SIZE);
5229 memcpy(desc, src, len);
5230 memset(desc + len, 0, VK_MAX_DESCRIPTION_SIZE - len);
5231 }
5232
5233 VkResult radv_GetPipelineExecutablePropertiesKHR(
5234 VkDevice _device,
5235 const VkPipelineInfoKHR* pPipelineInfo,
5236 uint32_t* pExecutableCount,
5237 VkPipelineExecutablePropertiesKHR* pProperties)
5238 {
5239 RADV_FROM_HANDLE(radv_pipeline, pipeline, pPipelineInfo->pipeline);
5240 const uint32_t total_count = radv_get_executable_count(pipeline);
5241
5242 if (!pProperties) {
5243 *pExecutableCount = total_count;
5244 return VK_SUCCESS;
5245 }
5246
5247 const uint32_t count = MIN2(total_count, *pExecutableCount);
5248 for (unsigned i = 0, executable_idx = 0;
5249 i < MESA_SHADER_STAGES && executable_idx < count; ++i) {
5250 if (!pipeline->shaders[i])
5251 continue;
5252 pProperties[executable_idx].stages = mesa_to_vk_shader_stage(i);
5253 const char *name = NULL;
5254 const char *description = NULL;
5255 switch(i) {
5256 case MESA_SHADER_VERTEX:
5257 name = "Vertex Shader";
5258 description = "Vulkan Vertex Shader";
5259 break;
5260 case MESA_SHADER_TESS_CTRL:
5261 if (!pipeline->shaders[MESA_SHADER_VERTEX]) {
5262 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5263 name = "Vertex + Tessellation Control Shaders";
5264 description = "Combined Vulkan Vertex and Tessellation Control Shaders";
5265 } else {
5266 name = "Tessellation Control Shader";
5267 description = "Vulkan Tessellation Control Shader";
5268 }
5269 break;
5270 case MESA_SHADER_TESS_EVAL:
5271 name = "Tessellation Evaluation Shader";
5272 description = "Vulkan Tessellation Evaluation Shader";
5273 break;
5274 case MESA_SHADER_GEOMETRY:
5275 if (radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
5276 pProperties[executable_idx].stages |= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT;
5277 name = "Tessellation Evaluation + Geometry Shaders";
5278 description = "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5279 } else if (!radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_VERTEX]) {
5280 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5281 name = "Vertex + Geometry Shader";
5282 description = "Combined Vulkan Vertex and Geometry Shaders";
5283 } else {
5284 name = "Geometry Shader";
5285 description = "Vulkan Geometry Shader";
5286 }
5287 break;
5288 case MESA_SHADER_FRAGMENT:
5289 name = "Fragment Shader";
5290 description = "Vulkan Fragment Shader";
5291 break;
5292 case MESA_SHADER_COMPUTE:
5293 name = "Compute Shader";
5294 description = "Vulkan Compute Shader";
5295 break;
5296 }
5297
5298 pProperties[executable_idx].subgroupSize = pipeline->shaders[i]->info.wave_size;
5299 desc_copy(pProperties[executable_idx].name, name);
5300 desc_copy(pProperties[executable_idx].description, description);
5301
5302 ++executable_idx;
5303 if (i == MESA_SHADER_GEOMETRY &&
5304 !radv_pipeline_has_ngg(pipeline)) {
5305 assert(pipeline->gs_copy_shader);
5306 if (executable_idx >= count)
5307 break;
5308
5309 pProperties[executable_idx].stages = VK_SHADER_STAGE_GEOMETRY_BIT;
5310 pProperties[executable_idx].subgroupSize = 64;
5311 desc_copy(pProperties[executable_idx].name, "GS Copy Shader");
5312 desc_copy(pProperties[executable_idx].description,
5313 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5314
5315 ++executable_idx;
5316 }
5317 }
5318
5319 VkResult result = *pExecutableCount < total_count ? VK_INCOMPLETE : VK_SUCCESS;
5320 *pExecutableCount = count;
5321 return result;
5322 }
5323
5324 VkResult radv_GetPipelineExecutableStatisticsKHR(
5325 VkDevice _device,
5326 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5327 uint32_t* pStatisticCount,
5328 VkPipelineExecutableStatisticKHR* pStatistics)
5329 {
5330 RADV_FROM_HANDLE(radv_device, device, _device);
5331 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5332 gl_shader_stage stage;
5333 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5334
5335 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
5336 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
5337 unsigned max_waves = radv_get_max_waves(device, shader, stage);
5338
5339 VkPipelineExecutableStatisticKHR *s = pStatistics;
5340 VkPipelineExecutableStatisticKHR *end = s + (pStatistics ? *pStatisticCount : 0);
5341 VkResult result = VK_SUCCESS;
5342
5343 if (s < end) {
5344 desc_copy(s->name, "SGPRs");
5345 desc_copy(s->description, "Number of SGPR registers allocated per subgroup");
5346 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5347 s->value.u64 = shader->config.num_sgprs;
5348 }
5349 ++s;
5350
5351 if (s < end) {
5352 desc_copy(s->name, "VGPRs");
5353 desc_copy(s->description, "Number of VGPR registers allocated per subgroup");
5354 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5355 s->value.u64 = shader->config.num_vgprs;
5356 }
5357 ++s;
5358
5359 if (s < end) {
5360 desc_copy(s->name, "Spilled SGPRs");
5361 desc_copy(s->description, "Number of SGPR registers spilled per subgroup");
5362 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5363 s->value.u64 = shader->config.spilled_sgprs;
5364 }
5365 ++s;
5366
5367 if (s < end) {
5368 desc_copy(s->name, "Spilled VGPRs");
5369 desc_copy(s->description, "Number of VGPR registers spilled per subgroup");
5370 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5371 s->value.u64 = shader->config.spilled_vgprs;
5372 }
5373 ++s;
5374
5375 if (s < end) {
5376 desc_copy(s->name, "PrivMem VGPRs");
5377 desc_copy(s->description, "Number of VGPRs stored in private memory per subgroup");
5378 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5379 s->value.u64 = shader->info.private_mem_vgprs;
5380 }
5381 ++s;
5382
5383 if (s < end) {
5384 desc_copy(s->name, "Code size");
5385 desc_copy(s->description, "Code size in bytes");
5386 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5387 s->value.u64 = shader->exec_size;
5388 }
5389 ++s;
5390
5391 if (s < end) {
5392 desc_copy(s->name, "LDS size");
5393 desc_copy(s->description, "LDS size in bytes per workgroup");
5394 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5395 s->value.u64 = shader->config.lds_size * lds_increment;
5396 }
5397 ++s;
5398
5399 if (s < end) {
5400 desc_copy(s->name, "Scratch size");
5401 desc_copy(s->description, "Private memory in bytes per subgroup");
5402 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5403 s->value.u64 = shader->config.scratch_bytes_per_wave;
5404 }
5405 ++s;
5406
5407 if (s < end) {
5408 desc_copy(s->name, "Subgroups per SIMD");
5409 desc_copy(s->description, "The maximum number of subgroups in flight on a SIMD unit");
5410 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5411 s->value.u64 = max_waves;
5412 }
5413 ++s;
5414
5415 if (shader->statistics) {
5416 for (unsigned i = 0; i < shader->statistics->count; i++) {
5417 struct radv_compiler_statistic_info *info = &shader->statistics->infos[i];
5418 uint32_t value = shader->statistics->values[i];
5419 if (s < end) {
5420 desc_copy(s->name, info->name);
5421 desc_copy(s->description, info->desc);
5422 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5423 s->value.u64 = value;
5424 }
5425 ++s;
5426 }
5427 }
5428
5429 if (!pStatistics)
5430 *pStatisticCount = s - pStatistics;
5431 else if (s > end) {
5432 *pStatisticCount = end - pStatistics;
5433 result = VK_INCOMPLETE;
5434 } else {
5435 *pStatisticCount = s - pStatistics;
5436 }
5437
5438 return result;
5439 }
5440
5441 static VkResult radv_copy_representation(void *data, size_t *data_size, const char *src)
5442 {
5443 size_t total_size = strlen(src) + 1;
5444
5445 if (!data) {
5446 *data_size = total_size;
5447 return VK_SUCCESS;
5448 }
5449
5450 size_t size = MIN2(total_size, *data_size);
5451
5452 memcpy(data, src, size);
5453 if (size)
5454 *((char*)data + size - 1) = 0;
5455 return size < total_size ? VK_INCOMPLETE : VK_SUCCESS;
5456 }
5457
5458 VkResult radv_GetPipelineExecutableInternalRepresentationsKHR(
5459 VkDevice device,
5460 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5461 uint32_t* pInternalRepresentationCount,
5462 VkPipelineExecutableInternalRepresentationKHR* pInternalRepresentations)
5463 {
5464 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5465 gl_shader_stage stage;
5466 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5467
5468 VkPipelineExecutableInternalRepresentationKHR *p = pInternalRepresentations;
5469 VkPipelineExecutableInternalRepresentationKHR *end = p + (pInternalRepresentations ? *pInternalRepresentationCount : 0);
5470 VkResult result = VK_SUCCESS;
5471 /* optimized NIR */
5472 if (p < end) {
5473 p->isText = true;
5474 desc_copy(p->name, "NIR Shader(s)");
5475 desc_copy(p->description, "The optimized NIR shader(s)");
5476 if (radv_copy_representation(p->pData, &p->dataSize, shader->nir_string) != VK_SUCCESS)
5477 result = VK_INCOMPLETE;
5478 }
5479 ++p;
5480
5481 /* backend IR */
5482 if (p < end) {
5483 p->isText = true;
5484 if (pipeline->device->physical_device->use_llvm) {
5485 desc_copy(p->name, "LLVM IR");
5486 desc_copy(p->description, "The LLVM IR after some optimizations");
5487 } else {
5488 desc_copy(p->name, "ACO IR");
5489 desc_copy(p->description, "The ACO IR after some optimizations");
5490 }
5491 if (radv_copy_representation(p->pData, &p->dataSize, shader->ir_string) != VK_SUCCESS)
5492 result = VK_INCOMPLETE;
5493 }
5494 ++p;
5495
5496 /* Disassembler */
5497 if (p < end) {
5498 p->isText = true;
5499 desc_copy(p->name, "Assembly");
5500 desc_copy(p->description, "Final Assembly");
5501 if (radv_copy_representation(p->pData, &p->dataSize, shader->disasm_string) != VK_SUCCESS)
5502 result = VK_INCOMPLETE;
5503 }
5504 ++p;
5505
5506 if (!pInternalRepresentations)
5507 *pInternalRepresentationCount = p - pInternalRepresentations;
5508 else if(p > end) {
5509 result = VK_INCOMPLETE;
5510 *pInternalRepresentationCount = end - pInternalRepresentations;
5511 } else {
5512 *pInternalRepresentationCount = p - pInternalRepresentations;
5513 }
5514
5515 return result;
5516 }