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radv: add code for exposing compiler statistics
[mesa.git] / src / amd / vulkan / radv_pipeline.c
1 /*
2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
4 *
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
7 *
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
14 *
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
17 * Software.
18 *
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
25 * IN THE SOFTWARE.
26 */
27
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
33 #include "radv_cs.h"
34 #include "radv_shader.h"
35 #include "nir/nir.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
39 #include "vk_util.h"
40
41 #include "sid.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
48 #include "ac_shader_util.h"
49
50 struct radv_blend_state {
51 uint32_t blend_enable_4bit;
52 uint32_t need_src_alpha;
53
54 uint32_t cb_color_control;
55 uint32_t cb_target_mask;
56 uint32_t cb_target_enabled_4bit;
57 uint32_t sx_mrt_blend_opt[8];
58 uint32_t cb_blend_control[8];
59
60 uint32_t spi_shader_col_format;
61 uint32_t cb_shader_mask;
62 uint32_t db_alpha_to_mask;
63
64 uint32_t commutative_4bit;
65
66 bool single_cb_enable;
67 bool mrt0_is_dual_src;
68 };
69
70 struct radv_dsa_order_invariance {
71 /* Whether the final result in Z/S buffers is guaranteed to be
72 * invariant under changes to the order in which fragments arrive.
73 */
74 bool zs;
75
76 /* Whether the set of fragments that pass the combined Z/S test is
77 * guaranteed to be invariant under changes to the order in which
78 * fragments arrive.
79 */
80 bool pass_set;
81 };
82
83 struct radv_tessellation_state {
84 uint32_t ls_hs_config;
85 unsigned num_patches;
86 unsigned lds_size;
87 uint32_t tf_param;
88 };
89
90 static const VkPipelineMultisampleStateCreateInfo *
91 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
92 {
93 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
94 return pCreateInfo->pMultisampleState;
95 return NULL;
96 }
97
98 static const VkPipelineTessellationStateCreateInfo *
99 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
100 {
101 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
102 if (pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT ||
103 pCreateInfo->pStages[i].stage == VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT) {
104 return pCreateInfo->pTessellationState;
105 }
106 }
107 return NULL;
108 }
109
110 static const VkPipelineDepthStencilStateCreateInfo *
111 radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
112 {
113 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
114 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
115
116 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
117 subpass->depth_stencil_attachment)
118 return pCreateInfo->pDepthStencilState;
119 return NULL;
120 }
121
122 static const VkPipelineColorBlendStateCreateInfo *
123 radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
124 {
125 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
126 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
127
128 if (!pCreateInfo->pRasterizationState->rasterizerDiscardEnable &&
129 subpass->has_color_att)
130 return pCreateInfo->pColorBlendState;
131 return NULL;
132 }
133
134 bool radv_pipeline_has_ngg(const struct radv_pipeline *pipeline)
135 {
136 struct radv_shader_variant *variant = NULL;
137 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
138 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
139 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
140 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
141 else if (pipeline->shaders[MESA_SHADER_VERTEX])
142 variant = pipeline->shaders[MESA_SHADER_VERTEX];
143 else
144 return false;
145 return variant->info.is_ngg;
146 }
147
148 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline *pipeline)
149 {
150 assert(radv_pipeline_has_ngg(pipeline));
151
152 struct radv_shader_variant *variant = NULL;
153 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
154 variant = pipeline->shaders[MESA_SHADER_GEOMETRY];
155 else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
156 variant = pipeline->shaders[MESA_SHADER_TESS_EVAL];
157 else if (pipeline->shaders[MESA_SHADER_VERTEX])
158 variant = pipeline->shaders[MESA_SHADER_VERTEX];
159 else
160 return false;
161 return variant->info.is_ngg_passthrough;
162 }
163
164 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline *pipeline)
165 {
166 if (!radv_pipeline_has_gs(pipeline))
167 return false;
168
169 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
170 * On GFX10, it might be required in rare cases if it's not possible to
171 * enable NGG.
172 */
173 if (radv_pipeline_has_ngg(pipeline))
174 return false;
175
176 assert(pipeline->gs_copy_shader);
177 return true;
178 }
179
180 static void
181 radv_pipeline_destroy(struct radv_device *device,
182 struct radv_pipeline *pipeline,
183 const VkAllocationCallbacks* allocator)
184 {
185 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i)
186 if (pipeline->shaders[i])
187 radv_shader_variant_destroy(device, pipeline->shaders[i]);
188
189 if (pipeline->gs_copy_shader)
190 radv_shader_variant_destroy(device, pipeline->gs_copy_shader);
191
192 if(pipeline->cs.buf)
193 free(pipeline->cs.buf);
194 vk_free2(&device->alloc, allocator, pipeline);
195 }
196
197 void radv_DestroyPipeline(
198 VkDevice _device,
199 VkPipeline _pipeline,
200 const VkAllocationCallbacks* pAllocator)
201 {
202 RADV_FROM_HANDLE(radv_device, device, _device);
203 RADV_FROM_HANDLE(radv_pipeline, pipeline, _pipeline);
204
205 if (!_pipeline)
206 return;
207
208 radv_pipeline_destroy(device, pipeline, pAllocator);
209 }
210
211 static uint32_t get_hash_flags(struct radv_device *device)
212 {
213 uint32_t hash_flags = 0;
214
215 if (device->instance->debug_flags & RADV_DEBUG_NO_NGG)
216 hash_flags |= RADV_HASH_SHADER_NO_NGG;
217 if (device->physical_device->cs_wave_size == 32)
218 hash_flags |= RADV_HASH_SHADER_CS_WAVE32;
219 if (device->physical_device->ps_wave_size == 32)
220 hash_flags |= RADV_HASH_SHADER_PS_WAVE32;
221 if (device->physical_device->ge_wave_size == 32)
222 hash_flags |= RADV_HASH_SHADER_GE_WAVE32;
223 if (device->physical_device->use_aco)
224 hash_flags |= RADV_HASH_SHADER_ACO;
225 return hash_flags;
226 }
227
228 static VkResult
229 radv_pipeline_scratch_init(struct radv_device *device,
230 struct radv_pipeline *pipeline)
231 {
232 unsigned scratch_bytes_per_wave = 0;
233 unsigned max_waves = 0;
234 unsigned min_waves = 1;
235
236 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
237 if (pipeline->shaders[i] &&
238 pipeline->shaders[i]->config.scratch_bytes_per_wave) {
239 unsigned max_stage_waves = device->scratch_waves;
240
241 scratch_bytes_per_wave = MAX2(scratch_bytes_per_wave,
242 pipeline->shaders[i]->config.scratch_bytes_per_wave);
243
244 max_stage_waves = MIN2(max_stage_waves,
245 4 * device->physical_device->rad_info.num_good_compute_units *
246 (256 / pipeline->shaders[i]->config.num_vgprs));
247 max_waves = MAX2(max_waves, max_stage_waves);
248 }
249 }
250
251 if (pipeline->shaders[MESA_SHADER_COMPUTE]) {
252 unsigned group_size = pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[0] *
253 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[1] *
254 pipeline->shaders[MESA_SHADER_COMPUTE]->info.cs.block_size[2];
255 min_waves = MAX2(min_waves, round_up_u32(group_size, 64));
256 }
257
258 pipeline->scratch_bytes_per_wave = scratch_bytes_per_wave;
259 pipeline->max_waves = max_waves;
260 return VK_SUCCESS;
261 }
262
263 static uint32_t si_translate_blend_logic_op(VkLogicOp op)
264 {
265 switch (op) {
266 case VK_LOGIC_OP_CLEAR:
267 return V_028808_ROP3_CLEAR;
268 case VK_LOGIC_OP_AND:
269 return V_028808_ROP3_AND;
270 case VK_LOGIC_OP_AND_REVERSE:
271 return V_028808_ROP3_AND_REVERSE;
272 case VK_LOGIC_OP_COPY:
273 return V_028808_ROP3_COPY;
274 case VK_LOGIC_OP_AND_INVERTED:
275 return V_028808_ROP3_AND_INVERTED;
276 case VK_LOGIC_OP_NO_OP:
277 return V_028808_ROP3_NO_OP;
278 case VK_LOGIC_OP_XOR:
279 return V_028808_ROP3_XOR;
280 case VK_LOGIC_OP_OR:
281 return V_028808_ROP3_OR;
282 case VK_LOGIC_OP_NOR:
283 return V_028808_ROP3_NOR;
284 case VK_LOGIC_OP_EQUIVALENT:
285 return V_028808_ROP3_EQUIVALENT;
286 case VK_LOGIC_OP_INVERT:
287 return V_028808_ROP3_INVERT;
288 case VK_LOGIC_OP_OR_REVERSE:
289 return V_028808_ROP3_OR_REVERSE;
290 case VK_LOGIC_OP_COPY_INVERTED:
291 return V_028808_ROP3_COPY_INVERTED;
292 case VK_LOGIC_OP_OR_INVERTED:
293 return V_028808_ROP3_OR_INVERTED;
294 case VK_LOGIC_OP_NAND:
295 return V_028808_ROP3_NAND;
296 case VK_LOGIC_OP_SET:
297 return V_028808_ROP3_SET;
298 default:
299 unreachable("Unhandled logic op");
300 }
301 }
302
303
304 static uint32_t si_translate_blend_function(VkBlendOp op)
305 {
306 switch (op) {
307 case VK_BLEND_OP_ADD:
308 return V_028780_COMB_DST_PLUS_SRC;
309 case VK_BLEND_OP_SUBTRACT:
310 return V_028780_COMB_SRC_MINUS_DST;
311 case VK_BLEND_OP_REVERSE_SUBTRACT:
312 return V_028780_COMB_DST_MINUS_SRC;
313 case VK_BLEND_OP_MIN:
314 return V_028780_COMB_MIN_DST_SRC;
315 case VK_BLEND_OP_MAX:
316 return V_028780_COMB_MAX_DST_SRC;
317 default:
318 return 0;
319 }
320 }
321
322 static uint32_t si_translate_blend_factor(VkBlendFactor factor)
323 {
324 switch (factor) {
325 case VK_BLEND_FACTOR_ZERO:
326 return V_028780_BLEND_ZERO;
327 case VK_BLEND_FACTOR_ONE:
328 return V_028780_BLEND_ONE;
329 case VK_BLEND_FACTOR_SRC_COLOR:
330 return V_028780_BLEND_SRC_COLOR;
331 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
332 return V_028780_BLEND_ONE_MINUS_SRC_COLOR;
333 case VK_BLEND_FACTOR_DST_COLOR:
334 return V_028780_BLEND_DST_COLOR;
335 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR:
336 return V_028780_BLEND_ONE_MINUS_DST_COLOR;
337 case VK_BLEND_FACTOR_SRC_ALPHA:
338 return V_028780_BLEND_SRC_ALPHA;
339 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
340 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA;
341 case VK_BLEND_FACTOR_DST_ALPHA:
342 return V_028780_BLEND_DST_ALPHA;
343 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA:
344 return V_028780_BLEND_ONE_MINUS_DST_ALPHA;
345 case VK_BLEND_FACTOR_CONSTANT_COLOR:
346 return V_028780_BLEND_CONSTANT_COLOR;
347 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR:
348 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR;
349 case VK_BLEND_FACTOR_CONSTANT_ALPHA:
350 return V_028780_BLEND_CONSTANT_ALPHA;
351 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA:
352 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA;
353 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
354 return V_028780_BLEND_SRC_ALPHA_SATURATE;
355 case VK_BLEND_FACTOR_SRC1_COLOR:
356 return V_028780_BLEND_SRC1_COLOR;
357 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
358 return V_028780_BLEND_INV_SRC1_COLOR;
359 case VK_BLEND_FACTOR_SRC1_ALPHA:
360 return V_028780_BLEND_SRC1_ALPHA;
361 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
362 return V_028780_BLEND_INV_SRC1_ALPHA;
363 default:
364 return 0;
365 }
366 }
367
368 static uint32_t si_translate_blend_opt_function(VkBlendOp op)
369 {
370 switch (op) {
371 case VK_BLEND_OP_ADD:
372 return V_028760_OPT_COMB_ADD;
373 case VK_BLEND_OP_SUBTRACT:
374 return V_028760_OPT_COMB_SUBTRACT;
375 case VK_BLEND_OP_REVERSE_SUBTRACT:
376 return V_028760_OPT_COMB_REVSUBTRACT;
377 case VK_BLEND_OP_MIN:
378 return V_028760_OPT_COMB_MIN;
379 case VK_BLEND_OP_MAX:
380 return V_028760_OPT_COMB_MAX;
381 default:
382 return V_028760_OPT_COMB_BLEND_DISABLED;
383 }
384 }
385
386 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor, bool is_alpha)
387 {
388 switch (factor) {
389 case VK_BLEND_FACTOR_ZERO:
390 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL;
391 case VK_BLEND_FACTOR_ONE:
392 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE;
393 case VK_BLEND_FACTOR_SRC_COLOR:
394 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
395 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0;
396 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR:
397 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
398 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1;
399 case VK_BLEND_FACTOR_SRC_ALPHA:
400 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0;
401 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA:
402 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1;
403 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE:
404 return is_alpha ? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
405 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
406 default:
407 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
408 }
409 }
410
411 /**
412 * Get rid of DST in the blend factors by commuting the operands:
413 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
414 */
415 static void si_blend_remove_dst(unsigned *func, unsigned *src_factor,
416 unsigned *dst_factor, unsigned expected_dst,
417 unsigned replacement_src)
418 {
419 if (*src_factor == expected_dst &&
420 *dst_factor == VK_BLEND_FACTOR_ZERO) {
421 *src_factor = VK_BLEND_FACTOR_ZERO;
422 *dst_factor = replacement_src;
423
424 /* Commuting the operands requires reversing subtractions. */
425 if (*func == VK_BLEND_OP_SUBTRACT)
426 *func = VK_BLEND_OP_REVERSE_SUBTRACT;
427 else if (*func == VK_BLEND_OP_REVERSE_SUBTRACT)
428 *func = VK_BLEND_OP_SUBTRACT;
429 }
430 }
431
432 static bool si_blend_factor_uses_dst(unsigned factor)
433 {
434 return factor == VK_BLEND_FACTOR_DST_COLOR ||
435 factor == VK_BLEND_FACTOR_DST_ALPHA ||
436 factor == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
437 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA ||
438 factor == VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR;
439 }
440
441 static bool is_dual_src(VkBlendFactor factor)
442 {
443 switch (factor) {
444 case VK_BLEND_FACTOR_SRC1_COLOR:
445 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR:
446 case VK_BLEND_FACTOR_SRC1_ALPHA:
447 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA:
448 return true;
449 default:
450 return false;
451 }
452 }
453
454 static unsigned si_choose_spi_color_format(VkFormat vk_format,
455 bool blend_enable,
456 bool blend_need_alpha)
457 {
458 const struct vk_format_description *desc = vk_format_description(vk_format);
459 unsigned format, ntype, swap;
460
461 /* Alpha is needed for alpha-to-coverage.
462 * Blending may be with or without alpha.
463 */
464 unsigned normal = 0; /* most optimal, may not support blending or export alpha */
465 unsigned alpha = 0; /* exports alpha, but may not support blending */
466 unsigned blend = 0; /* supports blending, but may not export alpha */
467 unsigned blend_alpha = 0; /* least optimal, supports blending and exports alpha */
468
469 format = radv_translate_colorformat(vk_format);
470 ntype = radv_translate_color_numformat(vk_format, desc,
471 vk_format_get_first_non_void_channel(vk_format));
472 swap = radv_translate_colorswap(vk_format, false);
473
474 /* Choose the SPI color formats. These are required values for Stoney/RB+.
475 * Other chips have multiple choices, though they are not necessarily better.
476 */
477 switch (format) {
478 case V_028C70_COLOR_5_6_5:
479 case V_028C70_COLOR_1_5_5_5:
480 case V_028C70_COLOR_5_5_5_1:
481 case V_028C70_COLOR_4_4_4_4:
482 case V_028C70_COLOR_10_11_11:
483 case V_028C70_COLOR_11_11_10:
484 case V_028C70_COLOR_8:
485 case V_028C70_COLOR_8_8:
486 case V_028C70_COLOR_8_8_8_8:
487 case V_028C70_COLOR_10_10_10_2:
488 case V_028C70_COLOR_2_10_10_10:
489 if (ntype == V_028C70_NUMBER_UINT)
490 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
491 else if (ntype == V_028C70_NUMBER_SINT)
492 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
493 else
494 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
495 break;
496
497 case V_028C70_COLOR_16:
498 case V_028C70_COLOR_16_16:
499 case V_028C70_COLOR_16_16_16_16:
500 if (ntype == V_028C70_NUMBER_UNORM ||
501 ntype == V_028C70_NUMBER_SNORM) {
502 /* UNORM16 and SNORM16 don't support blending */
503 if (ntype == V_028C70_NUMBER_UNORM)
504 normal = alpha = V_028714_SPI_SHADER_UNORM16_ABGR;
505 else
506 normal = alpha = V_028714_SPI_SHADER_SNORM16_ABGR;
507
508 /* Use 32 bits per channel for blending. */
509 if (format == V_028C70_COLOR_16) {
510 if (swap == V_028C70_SWAP_STD) { /* R */
511 blend = V_028714_SPI_SHADER_32_R;
512 blend_alpha = V_028714_SPI_SHADER_32_AR;
513 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
514 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
515 else
516 assert(0);
517 } else if (format == V_028C70_COLOR_16_16) {
518 if (swap == V_028C70_SWAP_STD) { /* RG */
519 blend = V_028714_SPI_SHADER_32_GR;
520 blend_alpha = V_028714_SPI_SHADER_32_ABGR;
521 } else if (swap == V_028C70_SWAP_ALT) /* RA */
522 blend = blend_alpha = V_028714_SPI_SHADER_32_AR;
523 else
524 assert(0);
525 } else /* 16_16_16_16 */
526 blend = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
527 } else if (ntype == V_028C70_NUMBER_UINT)
528 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_UINT16_ABGR;
529 else if (ntype == V_028C70_NUMBER_SINT)
530 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_SINT16_ABGR;
531 else if (ntype == V_028C70_NUMBER_FLOAT)
532 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_FP16_ABGR;
533 else
534 assert(0);
535 break;
536
537 case V_028C70_COLOR_32:
538 if (swap == V_028C70_SWAP_STD) { /* R */
539 blend = normal = V_028714_SPI_SHADER_32_R;
540 alpha = blend_alpha = V_028714_SPI_SHADER_32_AR;
541 } else if (swap == V_028C70_SWAP_ALT_REV) /* A */
542 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
543 else
544 assert(0);
545 break;
546
547 case V_028C70_COLOR_32_32:
548 if (swap == V_028C70_SWAP_STD) { /* RG */
549 blend = normal = V_028714_SPI_SHADER_32_GR;
550 alpha = blend_alpha = V_028714_SPI_SHADER_32_ABGR;
551 } else if (swap == V_028C70_SWAP_ALT) /* RA */
552 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_AR;
553 else
554 assert(0);
555 break;
556
557 case V_028C70_COLOR_32_32_32_32:
558 case V_028C70_COLOR_8_24:
559 case V_028C70_COLOR_24_8:
560 case V_028C70_COLOR_X24_8_32_FLOAT:
561 alpha = blend = blend_alpha = normal = V_028714_SPI_SHADER_32_ABGR;
562 break;
563
564 default:
565 unreachable("unhandled blend format");
566 }
567
568 if (blend_enable && blend_need_alpha)
569 return blend_alpha;
570 else if(blend_need_alpha)
571 return alpha;
572 else if(blend_enable)
573 return blend;
574 else
575 return normal;
576 }
577
578 static void
579 radv_pipeline_compute_spi_color_formats(struct radv_pipeline *pipeline,
580 const VkGraphicsPipelineCreateInfo *pCreateInfo,
581 struct radv_blend_state *blend)
582 {
583 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
584 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
585 unsigned col_format = 0;
586 unsigned num_targets;
587
588 for (unsigned i = 0; i < (blend->single_cb_enable ? 1 : subpass->color_count); ++i) {
589 unsigned cf;
590
591 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED) {
592 cf = V_028714_SPI_SHADER_ZERO;
593 } else {
594 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->color_attachments[i].attachment;
595 bool blend_enable =
596 blend->blend_enable_4bit & (0xfu << (i * 4));
597
598 cf = si_choose_spi_color_format(attachment->format,
599 blend_enable,
600 blend->need_src_alpha & (1 << i));
601 }
602
603 col_format |= cf << (4 * i);
604 }
605
606 if (!(col_format & 0xf) && blend->need_src_alpha & (1 << 0)) {
607 /* When a subpass doesn't have any color attachments, write the
608 * alpha channel of MRT0 when alpha coverage is enabled because
609 * the depth attachment needs it.
610 */
611 col_format |= V_028714_SPI_SHADER_32_AR;
612 }
613
614 /* If the i-th target format is set, all previous target formats must
615 * be non-zero to avoid hangs.
616 */
617 num_targets = (util_last_bit(col_format) + 3) / 4;
618 for (unsigned i = 0; i < num_targets; i++) {
619 if (!(col_format & (0xf << (i * 4)))) {
620 col_format |= V_028714_SPI_SHADER_32_R << (i * 4);
621 }
622 }
623
624 /* The output for dual source blending should have the same format as
625 * the first output.
626 */
627 if (blend->mrt0_is_dual_src)
628 col_format |= (col_format & 0xf) << 4;
629
630 blend->cb_shader_mask = ac_get_cb_shader_mask(col_format);
631 blend->spi_shader_col_format = col_format;
632 }
633
634 static bool
635 format_is_int8(VkFormat format)
636 {
637 const struct vk_format_description *desc = vk_format_description(format);
638 int channel = vk_format_get_first_non_void_channel(format);
639
640 return channel >= 0 && desc->channel[channel].pure_integer &&
641 desc->channel[channel].size == 8;
642 }
643
644 static bool
645 format_is_int10(VkFormat format)
646 {
647 const struct vk_format_description *desc = vk_format_description(format);
648
649 if (desc->nr_channels != 4)
650 return false;
651 for (unsigned i = 0; i < 4; i++) {
652 if (desc->channel[i].pure_integer && desc->channel[i].size == 10)
653 return true;
654 }
655 return false;
656 }
657
658 /*
659 * Ordered so that for each i,
660 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
661 */
662 const VkFormat radv_fs_key_format_exemplars[NUM_META_FS_KEYS] = {
663 VK_FORMAT_R32_SFLOAT,
664 VK_FORMAT_R32G32_SFLOAT,
665 VK_FORMAT_R8G8B8A8_UNORM,
666 VK_FORMAT_R16G16B16A16_UNORM,
667 VK_FORMAT_R16G16B16A16_SNORM,
668 VK_FORMAT_R16G16B16A16_UINT,
669 VK_FORMAT_R16G16B16A16_SINT,
670 VK_FORMAT_R32G32B32A32_SFLOAT,
671 VK_FORMAT_R8G8B8A8_UINT,
672 VK_FORMAT_R8G8B8A8_SINT,
673 VK_FORMAT_A2R10G10B10_UINT_PACK32,
674 VK_FORMAT_A2R10G10B10_SINT_PACK32,
675 };
676
677 unsigned radv_format_meta_fs_key(VkFormat format)
678 {
679 unsigned col_format = si_choose_spi_color_format(format, false, false);
680
681 assert(col_format != V_028714_SPI_SHADER_32_AR);
682 if (col_format >= V_028714_SPI_SHADER_32_AR)
683 --col_format; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
684
685 --col_format; /* Skip V_028714_SPI_SHADER_ZERO */
686 bool is_int8 = format_is_int8(format);
687 bool is_int10 = format_is_int10(format);
688
689 return col_format + (is_int8 ? 3 : is_int10 ? 5 : 0);
690 }
691
692 static void
693 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo *pCreateInfo,
694 unsigned *is_int8, unsigned *is_int10)
695 {
696 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
697 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
698 *is_int8 = 0;
699 *is_int10 = 0;
700
701 for (unsigned i = 0; i < subpass->color_count; ++i) {
702 struct radv_render_pass_attachment *attachment;
703
704 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
705 continue;
706
707 attachment = pass->attachments + subpass->color_attachments[i].attachment;
708
709 if (format_is_int8(attachment->format))
710 *is_int8 |= 1 << i;
711 if (format_is_int10(attachment->format))
712 *is_int10 |= 1 << i;
713 }
714 }
715
716 static void
717 radv_blend_check_commutativity(struct radv_blend_state *blend,
718 VkBlendOp op, VkBlendFactor src,
719 VkBlendFactor dst, unsigned chanmask)
720 {
721 /* Src factor is allowed when it does not depend on Dst. */
722 static const uint32_t src_allowed =
723 (1u << VK_BLEND_FACTOR_ONE) |
724 (1u << VK_BLEND_FACTOR_SRC_COLOR) |
725 (1u << VK_BLEND_FACTOR_SRC_ALPHA) |
726 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE) |
727 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR) |
728 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA) |
729 (1u << VK_BLEND_FACTOR_SRC1_COLOR) |
730 (1u << VK_BLEND_FACTOR_SRC1_ALPHA) |
731 (1u << VK_BLEND_FACTOR_ZERO) |
732 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR) |
733 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA) |
734 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR) |
735 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA) |
736 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR) |
737 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA);
738
739 if (dst == VK_BLEND_FACTOR_ONE &&
740 (src_allowed & (1u << src))) {
741 /* Addition is commutative, but floating point addition isn't
742 * associative: subtle changes can be introduced via different
743 * rounding. Be conservative, only enable for min and max.
744 */
745 if (op == VK_BLEND_OP_MAX || op == VK_BLEND_OP_MIN)
746 blend->commutative_4bit |= chanmask;
747 }
748 }
749
750 static struct radv_blend_state
751 radv_pipeline_init_blend_state(struct radv_pipeline *pipeline,
752 const VkGraphicsPipelineCreateInfo *pCreateInfo,
753 const struct radv_graphics_pipeline_create_info *extra)
754 {
755 const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
756 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
757 struct radv_blend_state blend = {0};
758 unsigned mode = V_028808_CB_NORMAL;
759 int i;
760
761 if (extra && extra->custom_blend_mode) {
762 blend.single_cb_enable = true;
763 mode = extra->custom_blend_mode;
764 }
765
766 blend.cb_color_control = 0;
767 if (vkblend) {
768 if (vkblend->logicOpEnable)
769 blend.cb_color_control |= S_028808_ROP3(si_translate_blend_logic_op(vkblend->logicOp));
770 else
771 blend.cb_color_control |= S_028808_ROP3(V_028808_ROP3_COPY);
772 }
773
774 blend.db_alpha_to_mask = S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
775 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
776 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
777 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
778 S_028B70_OFFSET_ROUND(1);
779
780 if (vkms && vkms->alphaToCoverageEnable) {
781 blend.db_alpha_to_mask |= S_028B70_ALPHA_TO_MASK_ENABLE(1);
782 blend.need_src_alpha |= 0x1;
783 }
784
785 blend.cb_target_mask = 0;
786 if (vkblend) {
787 for (i = 0; i < vkblend->attachmentCount; i++) {
788 const VkPipelineColorBlendAttachmentState *att = &vkblend->pAttachments[i];
789 unsigned blend_cntl = 0;
790 unsigned srcRGB_opt, dstRGB_opt, srcA_opt, dstA_opt;
791 VkBlendOp eqRGB = att->colorBlendOp;
792 VkBlendFactor srcRGB = att->srcColorBlendFactor;
793 VkBlendFactor dstRGB = att->dstColorBlendFactor;
794 VkBlendOp eqA = att->alphaBlendOp;
795 VkBlendFactor srcA = att->srcAlphaBlendFactor;
796 VkBlendFactor dstA = att->dstAlphaBlendFactor;
797
798 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
799
800 if (!att->colorWriteMask)
801 continue;
802
803 blend.cb_target_mask |= (unsigned)att->colorWriteMask << (4 * i);
804 blend.cb_target_enabled_4bit |= 0xf << (4 * i);
805 if (!att->blendEnable) {
806 blend.cb_blend_control[i] = blend_cntl;
807 continue;
808 }
809
810 if (is_dual_src(srcRGB) || is_dual_src(dstRGB) || is_dual_src(srcA) || is_dual_src(dstA))
811 if (i == 0)
812 blend.mrt0_is_dual_src = true;
813
814 if (eqRGB == VK_BLEND_OP_MIN || eqRGB == VK_BLEND_OP_MAX) {
815 srcRGB = VK_BLEND_FACTOR_ONE;
816 dstRGB = VK_BLEND_FACTOR_ONE;
817 }
818 if (eqA == VK_BLEND_OP_MIN || eqA == VK_BLEND_OP_MAX) {
819 srcA = VK_BLEND_FACTOR_ONE;
820 dstA = VK_BLEND_FACTOR_ONE;
821 }
822
823 radv_blend_check_commutativity(&blend, eqRGB, srcRGB, dstRGB,
824 0x7 << (4 * i));
825 radv_blend_check_commutativity(&blend, eqA, srcA, dstA,
826 0x8 << (4 * i));
827
828 /* Blending optimizations for RB+.
829 * These transformations don't change the behavior.
830 *
831 * First, get rid of DST in the blend factors:
832 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
833 */
834 si_blend_remove_dst(&eqRGB, &srcRGB, &dstRGB,
835 VK_BLEND_FACTOR_DST_COLOR,
836 VK_BLEND_FACTOR_SRC_COLOR);
837
838 si_blend_remove_dst(&eqA, &srcA, &dstA,
839 VK_BLEND_FACTOR_DST_COLOR,
840 VK_BLEND_FACTOR_SRC_COLOR);
841
842 si_blend_remove_dst(&eqA, &srcA, &dstA,
843 VK_BLEND_FACTOR_DST_ALPHA,
844 VK_BLEND_FACTOR_SRC_ALPHA);
845
846 /* Look up the ideal settings from tables. */
847 srcRGB_opt = si_translate_blend_opt_factor(srcRGB, false);
848 dstRGB_opt = si_translate_blend_opt_factor(dstRGB, false);
849 srcA_opt = si_translate_blend_opt_factor(srcA, true);
850 dstA_opt = si_translate_blend_opt_factor(dstA, true);
851
852 /* Handle interdependencies. */
853 if (si_blend_factor_uses_dst(srcRGB))
854 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
855 if (si_blend_factor_uses_dst(srcA))
856 dstA_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE;
857
858 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE &&
859 (dstRGB == VK_BLEND_FACTOR_ZERO ||
860 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
861 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE))
862 dstRGB_opt = V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0;
863
864 /* Set the final value. */
865 blend.sx_mrt_blend_opt[i] =
866 S_028760_COLOR_SRC_OPT(srcRGB_opt) |
867 S_028760_COLOR_DST_OPT(dstRGB_opt) |
868 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB)) |
869 S_028760_ALPHA_SRC_OPT(srcA_opt) |
870 S_028760_ALPHA_DST_OPT(dstA_opt) |
871 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA));
872 blend_cntl |= S_028780_ENABLE(1);
873
874 blend_cntl |= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB));
875 blend_cntl |= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB));
876 blend_cntl |= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB));
877 if (srcA != srcRGB || dstA != dstRGB || eqA != eqRGB) {
878 blend_cntl |= S_028780_SEPARATE_ALPHA_BLEND(1);
879 blend_cntl |= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA));
880 blend_cntl |= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA));
881 blend_cntl |= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA));
882 }
883 blend.cb_blend_control[i] = blend_cntl;
884
885 blend.blend_enable_4bit |= 0xfu << (i * 4);
886
887 if (srcRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
888 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA ||
889 srcRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
890 dstRGB == VK_BLEND_FACTOR_SRC_ALPHA_SATURATE ||
891 srcRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA ||
892 dstRGB == VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA)
893 blend.need_src_alpha |= 1 << i;
894 }
895 for (i = vkblend->attachmentCount; i < 8; i++) {
896 blend.cb_blend_control[i] = 0;
897 blend.sx_mrt_blend_opt[i] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED);
898 }
899 }
900
901 if (pipeline->device->physical_device->rad_info.has_rbplus) {
902 /* Disable RB+ blend optimizations for dual source blending. */
903 if (blend.mrt0_is_dual_src) {
904 for (i = 0; i < 8; i++) {
905 blend.sx_mrt_blend_opt[i] =
906 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE) |
907 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE);
908 }
909 }
910
911 /* RB+ doesn't work with dual source blending, logic op and
912 * RESOLVE.
913 */
914 if (blend.mrt0_is_dual_src ||
915 (vkblend && vkblend->logicOpEnable) ||
916 mode == V_028808_CB_RESOLVE)
917 blend.cb_color_control |= S_028808_DISABLE_DUAL_QUAD(1);
918 }
919
920 if (blend.cb_target_mask)
921 blend.cb_color_control |= S_028808_MODE(mode);
922 else
923 blend.cb_color_control |= S_028808_MODE(V_028808_CB_DISABLE);
924
925 radv_pipeline_compute_spi_color_formats(pipeline, pCreateInfo, &blend);
926 return blend;
927 }
928
929 static uint32_t si_translate_stencil_op(enum VkStencilOp op)
930 {
931 switch (op) {
932 case VK_STENCIL_OP_KEEP:
933 return V_02842C_STENCIL_KEEP;
934 case VK_STENCIL_OP_ZERO:
935 return V_02842C_STENCIL_ZERO;
936 case VK_STENCIL_OP_REPLACE:
937 return V_02842C_STENCIL_REPLACE_TEST;
938 case VK_STENCIL_OP_INCREMENT_AND_CLAMP:
939 return V_02842C_STENCIL_ADD_CLAMP;
940 case VK_STENCIL_OP_DECREMENT_AND_CLAMP:
941 return V_02842C_STENCIL_SUB_CLAMP;
942 case VK_STENCIL_OP_INVERT:
943 return V_02842C_STENCIL_INVERT;
944 case VK_STENCIL_OP_INCREMENT_AND_WRAP:
945 return V_02842C_STENCIL_ADD_WRAP;
946 case VK_STENCIL_OP_DECREMENT_AND_WRAP:
947 return V_02842C_STENCIL_SUB_WRAP;
948 default:
949 return 0;
950 }
951 }
952
953 static uint32_t si_translate_fill(VkPolygonMode func)
954 {
955 switch(func) {
956 case VK_POLYGON_MODE_FILL:
957 return V_028814_X_DRAW_TRIANGLES;
958 case VK_POLYGON_MODE_LINE:
959 return V_028814_X_DRAW_LINES;
960 case VK_POLYGON_MODE_POINT:
961 return V_028814_X_DRAW_POINTS;
962 default:
963 assert(0);
964 return V_028814_X_DRAW_POINTS;
965 }
966 }
967
968 static uint8_t radv_pipeline_get_ps_iter_samples(const VkGraphicsPipelineCreateInfo *pCreateInfo)
969 {
970 const VkPipelineMultisampleStateCreateInfo *vkms = pCreateInfo->pMultisampleState;
971 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
972 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
973 uint32_t ps_iter_samples = 1;
974 uint32_t num_samples;
975
976 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
977 *
978 * "If the VK_AMD_mixed_attachment_samples extension is enabled and the
979 * subpass uses color attachments, totalSamples is the number of
980 * samples of the color attachments. Otherwise, totalSamples is the
981 * value of VkPipelineMultisampleStateCreateInfo::rasterizationSamples
982 * specified at pipeline creation time."
983 */
984 if (subpass->has_color_att) {
985 num_samples = subpass->color_sample_count;
986 } else {
987 num_samples = vkms->rasterizationSamples;
988 }
989
990 if (vkms->sampleShadingEnable) {
991 ps_iter_samples = ceil(vkms->minSampleShading * num_samples);
992 ps_iter_samples = util_next_power_of_two(ps_iter_samples);
993 }
994 return ps_iter_samples;
995 }
996
997 static bool
998 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
999 {
1000 return pCreateInfo->depthTestEnable &&
1001 pCreateInfo->depthWriteEnable &&
1002 pCreateInfo->depthCompareOp != VK_COMPARE_OP_NEVER;
1003 }
1004
1005 static bool
1006 radv_writes_stencil(const VkStencilOpState *state)
1007 {
1008 return state->writeMask &&
1009 (state->failOp != VK_STENCIL_OP_KEEP ||
1010 state->passOp != VK_STENCIL_OP_KEEP ||
1011 state->depthFailOp != VK_STENCIL_OP_KEEP);
1012 }
1013
1014 static bool
1015 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
1016 {
1017 return pCreateInfo->stencilTestEnable &&
1018 (radv_writes_stencil(&pCreateInfo->front) ||
1019 radv_writes_stencil(&pCreateInfo->back));
1020 }
1021
1022 static bool
1023 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo *pCreateInfo)
1024 {
1025 return radv_is_depth_write_enabled(pCreateInfo) ||
1026 radv_is_stencil_write_enabled(pCreateInfo);
1027 }
1028
1029 static bool
1030 radv_order_invariant_stencil_op(VkStencilOp op)
1031 {
1032 /* REPLACE is normally order invariant, except when the stencil
1033 * reference value is written by the fragment shader. Tracking this
1034 * interaction does not seem worth the effort, so be conservative.
1035 */
1036 return op != VK_STENCIL_OP_INCREMENT_AND_CLAMP &&
1037 op != VK_STENCIL_OP_DECREMENT_AND_CLAMP &&
1038 op != VK_STENCIL_OP_REPLACE;
1039 }
1040
1041 static bool
1042 radv_order_invariant_stencil_state(const VkStencilOpState *state)
1043 {
1044 /* Compute whether, assuming Z writes are disabled, this stencil state
1045 * is order invariant in the sense that the set of passing fragments as
1046 * well as the final stencil buffer result does not depend on the order
1047 * of fragments.
1048 */
1049 return !state->writeMask ||
1050 /* The following assumes that Z writes are disabled. */
1051 (state->compareOp == VK_COMPARE_OP_ALWAYS &&
1052 radv_order_invariant_stencil_op(state->passOp) &&
1053 radv_order_invariant_stencil_op(state->depthFailOp)) ||
1054 (state->compareOp == VK_COMPARE_OP_NEVER &&
1055 radv_order_invariant_stencil_op(state->failOp));
1056 }
1057
1058 static bool
1059 radv_pipeline_out_of_order_rast(struct radv_pipeline *pipeline,
1060 struct radv_blend_state *blend,
1061 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1062 {
1063 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1064 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
1065 const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
1066 const VkPipelineColorBlendStateCreateInfo *vkblend = radv_pipeline_get_color_blend_state(pCreateInfo);
1067 unsigned colormask = blend->cb_target_enabled_4bit;
1068
1069 if (!pipeline->device->physical_device->out_of_order_rast_allowed)
1070 return false;
1071
1072 /* Be conservative if a logic operation is enabled with color buffers. */
1073 if (colormask && vkblend && vkblend->logicOpEnable)
1074 return false;
1075
1076 /* Default depth/stencil invariance when no attachment is bound. */
1077 struct radv_dsa_order_invariance dsa_order_invariant = {
1078 .zs = true, .pass_set = true
1079 };
1080
1081 if (vkds) {
1082 struct radv_render_pass_attachment *attachment =
1083 pass->attachments + subpass->depth_stencil_attachment->attachment;
1084 bool has_stencil = vk_format_is_stencil(attachment->format);
1085 struct radv_dsa_order_invariance order_invariance[2];
1086 struct radv_shader_variant *ps =
1087 pipeline->shaders[MESA_SHADER_FRAGMENT];
1088
1089 /* Compute depth/stencil order invariance in order to know if
1090 * it's safe to enable out-of-order.
1091 */
1092 bool zfunc_is_ordered =
1093 vkds->depthCompareOp == VK_COMPARE_OP_NEVER ||
1094 vkds->depthCompareOp == VK_COMPARE_OP_LESS ||
1095 vkds->depthCompareOp == VK_COMPARE_OP_LESS_OR_EQUAL ||
1096 vkds->depthCompareOp == VK_COMPARE_OP_GREATER ||
1097 vkds->depthCompareOp == VK_COMPARE_OP_GREATER_OR_EQUAL;
1098
1099 bool nozwrite_and_order_invariant_stencil =
1100 !radv_is_ds_write_enabled(vkds) ||
1101 (!radv_is_depth_write_enabled(vkds) &&
1102 radv_order_invariant_stencil_state(&vkds->front) &&
1103 radv_order_invariant_stencil_state(&vkds->back));
1104
1105 order_invariance[1].zs =
1106 nozwrite_and_order_invariant_stencil ||
1107 (!radv_is_stencil_write_enabled(vkds) &&
1108 zfunc_is_ordered);
1109 order_invariance[0].zs =
1110 !radv_is_depth_write_enabled(vkds) || zfunc_is_ordered;
1111
1112 order_invariance[1].pass_set =
1113 nozwrite_and_order_invariant_stencil ||
1114 (!radv_is_stencil_write_enabled(vkds) &&
1115 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1116 vkds->depthCompareOp == VK_COMPARE_OP_NEVER));
1117 order_invariance[0].pass_set =
1118 !radv_is_depth_write_enabled(vkds) ||
1119 (vkds->depthCompareOp == VK_COMPARE_OP_ALWAYS ||
1120 vkds->depthCompareOp == VK_COMPARE_OP_NEVER);
1121
1122 dsa_order_invariant = order_invariance[has_stencil];
1123 if (!dsa_order_invariant.zs)
1124 return false;
1125
1126 /* The set of PS invocations is always order invariant,
1127 * except when early Z/S tests are requested.
1128 */
1129 if (ps &&
1130 ps->info.ps.writes_memory &&
1131 ps->info.ps.early_fragment_test &&
1132 !dsa_order_invariant.pass_set)
1133 return false;
1134
1135 /* Determine if out-of-order rasterization should be disabled
1136 * when occlusion queries are used.
1137 */
1138 pipeline->graphics.disable_out_of_order_rast_for_occlusion =
1139 !dsa_order_invariant.pass_set;
1140 }
1141
1142 /* No color buffers are enabled for writing. */
1143 if (!colormask)
1144 return true;
1145
1146 unsigned blendmask = colormask & blend->blend_enable_4bit;
1147
1148 if (blendmask) {
1149 /* Only commutative blending. */
1150 if (blendmask & ~blend->commutative_4bit)
1151 return false;
1152
1153 if (!dsa_order_invariant.pass_set)
1154 return false;
1155 }
1156
1157 if (colormask & ~blendmask)
1158 return false;
1159
1160 return true;
1161 }
1162
1163 static void
1164 radv_pipeline_init_multisample_state(struct radv_pipeline *pipeline,
1165 struct radv_blend_state *blend,
1166 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1167 {
1168 const VkPipelineMultisampleStateCreateInfo *vkms = radv_pipeline_get_multisample_state(pCreateInfo);
1169 struct radv_multisample_state *ms = &pipeline->graphics.ms;
1170 unsigned num_tile_pipes = pipeline->device->physical_device->rad_info.num_tile_pipes;
1171 bool out_of_order_rast = false;
1172 int ps_iter_samples = 1;
1173 uint32_t mask = 0xffff;
1174
1175 if (vkms) {
1176 ms->num_samples = vkms->rasterizationSamples;
1177
1178 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1179 *
1180 * "Sample shading is enabled for a graphics pipeline:
1181 *
1182 * - If the interface of the fragment shader entry point of the
1183 * graphics pipeline includes an input variable decorated
1184 * with SampleId or SamplePosition. In this case
1185 * minSampleShadingFactor takes the value 1.0.
1186 * - Else if the sampleShadingEnable member of the
1187 * VkPipelineMultisampleStateCreateInfo structure specified
1188 * when creating the graphics pipeline is set to VK_TRUE. In
1189 * this case minSampleShadingFactor takes the value of
1190 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1191 *
1192 * Otherwise, sample shading is considered disabled."
1193 */
1194 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.force_persample) {
1195 ps_iter_samples = ms->num_samples;
1196 } else {
1197 ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
1198 }
1199 } else {
1200 ms->num_samples = 1;
1201 }
1202
1203 const struct VkPipelineRasterizationStateRasterizationOrderAMD *raster_order =
1204 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD);
1205 if (raster_order && raster_order->rasterizationOrder == VK_RASTERIZATION_ORDER_RELAXED_AMD) {
1206 /* Out-of-order rasterization is explicitly enabled by the
1207 * application.
1208 */
1209 out_of_order_rast = true;
1210 } else {
1211 /* Determine if the driver can enable out-of-order
1212 * rasterization internally.
1213 */
1214 out_of_order_rast =
1215 radv_pipeline_out_of_order_rast(pipeline, blend, pCreateInfo);
1216 }
1217
1218 ms->pa_sc_line_cntl = S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1219 ms->pa_sc_aa_config = 0;
1220 ms->db_eqaa = S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1221 S_028804_INCOHERENT_EQAA_READS(1) |
1222 S_028804_INTERPOLATE_COMP_Z(1) |
1223 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1224 ms->pa_sc_mode_cntl_1 =
1225 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1226 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes == 2 ? 2 : 3) |
1227 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast) |
1228 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1229 /* always 1: */
1230 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1231 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1232 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1233 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1234 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1235 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1236 ms->pa_sc_mode_cntl_0 = S_028A48_ALTERNATE_RBS_PER_TILE(pipeline->device->physical_device->rad_info.chip_class >= GFX9) |
1237 S_028A48_VPORT_SCISSOR_ENABLE(1);
1238
1239 const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line =
1240 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1241 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
1242 if (rast_line) {
1243 ms->pa_sc_mode_cntl_0 |= S_028A48_LINE_STIPPLE_ENABLE(rast_line->stippledLineEnable);
1244 if (rast_line->lineRasterizationMode == VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT) {
1245 /* From the Vulkan spec 1.1.129:
1246 *
1247 * "When VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT lines
1248 * are being rasterized, sample locations may all be
1249 * treated as being at the pixel center (this may
1250 * affect attribute and depth interpolation)."
1251 */
1252 ms->num_samples = 1;
1253 }
1254 }
1255
1256 if (ms->num_samples > 1) {
1257 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1258 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1259 uint32_t z_samples = subpass->depth_stencil_attachment ? subpass->depth_sample_count : ms->num_samples;
1260 unsigned log_samples = util_logbase2(ms->num_samples);
1261 unsigned log_z_samples = util_logbase2(z_samples);
1262 unsigned log_ps_iter_samples = util_logbase2(ps_iter_samples);
1263 ms->pa_sc_mode_cntl_0 |= S_028A48_MSAA_ENABLE(1);
1264 ms->pa_sc_line_cntl |= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1265 ms->db_eqaa |= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples) |
1266 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples) |
1267 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples) |
1268 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples);
1269 ms->pa_sc_aa_config |= S_028BE0_MSAA_NUM_SAMPLES(log_samples) |
1270 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples)) |
1271 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1272 ms->pa_sc_mode_cntl_1 |= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples > 1);
1273 if (ps_iter_samples > 1)
1274 pipeline->graphics.spi_baryc_cntl |= S_0286E0_POS_FLOAT_LOCATION(2);
1275 }
1276
1277 if (vkms && vkms->pSampleMask) {
1278 mask = vkms->pSampleMask[0] & 0xffff;
1279 }
1280
1281 ms->pa_sc_aa_mask[0] = mask | (mask << 16);
1282 ms->pa_sc_aa_mask[1] = mask | (mask << 16);
1283 }
1284
1285 static bool
1286 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology)
1287 {
1288 switch (topology) {
1289 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1290 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1291 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1292 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1293 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1294 return false;
1295 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1296 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1297 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1298 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1299 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1300 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1301 return true;
1302 default:
1303 unreachable("unhandled primitive type");
1304 }
1305 }
1306
1307 static uint32_t
1308 si_translate_prim(enum VkPrimitiveTopology topology)
1309 {
1310 switch (topology) {
1311 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1312 return V_008958_DI_PT_POINTLIST;
1313 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1314 return V_008958_DI_PT_LINELIST;
1315 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1316 return V_008958_DI_PT_LINESTRIP;
1317 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1318 return V_008958_DI_PT_TRILIST;
1319 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1320 return V_008958_DI_PT_TRISTRIP;
1321 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1322 return V_008958_DI_PT_TRIFAN;
1323 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1324 return V_008958_DI_PT_LINELIST_ADJ;
1325 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1326 return V_008958_DI_PT_LINESTRIP_ADJ;
1327 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1328 return V_008958_DI_PT_TRILIST_ADJ;
1329 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1330 return V_008958_DI_PT_TRISTRIP_ADJ;
1331 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1332 return V_008958_DI_PT_PATCH;
1333 default:
1334 assert(0);
1335 return 0;
1336 }
1337 }
1338
1339 static uint32_t
1340 si_conv_gl_prim_to_gs_out(unsigned gl_prim)
1341 {
1342 switch (gl_prim) {
1343 case 0: /* GL_POINTS */
1344 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1345 case 1: /* GL_LINES */
1346 case 3: /* GL_LINE_STRIP */
1347 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1348 case 0x8E7A: /* GL_ISOLINES */
1349 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1350
1351 case 4: /* GL_TRIANGLES */
1352 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1353 case 5: /* GL_TRIANGLE_STRIP */
1354 case 7: /* GL_QUADS */
1355 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1356 default:
1357 assert(0);
1358 return 0;
1359 }
1360 }
1361
1362 static uint32_t
1363 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology)
1364 {
1365 switch (topology) {
1366 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST:
1367 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST:
1368 return V_028A6C_OUTPRIM_TYPE_POINTLIST;
1369 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST:
1370 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP:
1371 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1372 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1373 return V_028A6C_OUTPRIM_TYPE_LINESTRIP;
1374 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST:
1375 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP:
1376 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN:
1377 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1378 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1379 return V_028A6C_OUTPRIM_TYPE_TRISTRIP;
1380 default:
1381 assert(0);
1382 return 0;
1383 }
1384 }
1385
1386 static unsigned radv_dynamic_state_mask(VkDynamicState state)
1387 {
1388 switch(state) {
1389 case VK_DYNAMIC_STATE_VIEWPORT:
1390 return RADV_DYNAMIC_VIEWPORT;
1391 case VK_DYNAMIC_STATE_SCISSOR:
1392 return RADV_DYNAMIC_SCISSOR;
1393 case VK_DYNAMIC_STATE_LINE_WIDTH:
1394 return RADV_DYNAMIC_LINE_WIDTH;
1395 case VK_DYNAMIC_STATE_DEPTH_BIAS:
1396 return RADV_DYNAMIC_DEPTH_BIAS;
1397 case VK_DYNAMIC_STATE_BLEND_CONSTANTS:
1398 return RADV_DYNAMIC_BLEND_CONSTANTS;
1399 case VK_DYNAMIC_STATE_DEPTH_BOUNDS:
1400 return RADV_DYNAMIC_DEPTH_BOUNDS;
1401 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK:
1402 return RADV_DYNAMIC_STENCIL_COMPARE_MASK;
1403 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK:
1404 return RADV_DYNAMIC_STENCIL_WRITE_MASK;
1405 case VK_DYNAMIC_STATE_STENCIL_REFERENCE:
1406 return RADV_DYNAMIC_STENCIL_REFERENCE;
1407 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT:
1408 return RADV_DYNAMIC_DISCARD_RECTANGLE;
1409 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT:
1410 return RADV_DYNAMIC_SAMPLE_LOCATIONS;
1411 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT:
1412 return RADV_DYNAMIC_LINE_STIPPLE;
1413 default:
1414 unreachable("Unhandled dynamic state");
1415 }
1416 }
1417
1418 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo *pCreateInfo)
1419 {
1420 uint32_t states = RADV_DYNAMIC_ALL;
1421
1422 /* If rasterization is disabled we do not care about any of the dynamic states,
1423 * since they are all rasterization related only. */
1424 if (pCreateInfo->pRasterizationState->rasterizerDiscardEnable)
1425 return 0;
1426
1427 if (!pCreateInfo->pRasterizationState->depthBiasEnable)
1428 states &= ~RADV_DYNAMIC_DEPTH_BIAS;
1429
1430 if (!pCreateInfo->pDepthStencilState ||
1431 !pCreateInfo->pDepthStencilState->depthBoundsTestEnable)
1432 states &= ~RADV_DYNAMIC_DEPTH_BOUNDS;
1433
1434 if (!pCreateInfo->pDepthStencilState ||
1435 !pCreateInfo->pDepthStencilState->stencilTestEnable)
1436 states &= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK |
1437 RADV_DYNAMIC_STENCIL_WRITE_MASK |
1438 RADV_DYNAMIC_STENCIL_REFERENCE);
1439
1440 if (!vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT))
1441 states &= ~RADV_DYNAMIC_DISCARD_RECTANGLE;
1442
1443 if (!pCreateInfo->pMultisampleState ||
1444 !vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1445 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT))
1446 states &= ~RADV_DYNAMIC_SAMPLE_LOCATIONS;
1447
1448 if (!pCreateInfo->pRasterizationState ||
1449 !vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1450 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT))
1451 states &= ~RADV_DYNAMIC_LINE_STIPPLE;
1452
1453 /* TODO: blend constants & line width. */
1454
1455 return states;
1456 }
1457
1458
1459 static void
1460 radv_pipeline_init_dynamic_state(struct radv_pipeline *pipeline,
1461 const VkGraphicsPipelineCreateInfo *pCreateInfo)
1462 {
1463 uint32_t needed_states = radv_pipeline_needed_dynamic_state(pCreateInfo);
1464 uint32_t states = needed_states;
1465 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
1466 struct radv_subpass *subpass = &pass->subpasses[pCreateInfo->subpass];
1467
1468 pipeline->dynamic_state = default_dynamic_state;
1469 pipeline->graphics.needed_dynamic_state = needed_states;
1470
1471 if (pCreateInfo->pDynamicState) {
1472 /* Remove all of the states that are marked as dynamic */
1473 uint32_t count = pCreateInfo->pDynamicState->dynamicStateCount;
1474 for (uint32_t s = 0; s < count; s++)
1475 states &= ~radv_dynamic_state_mask(pCreateInfo->pDynamicState->pDynamicStates[s]);
1476 }
1477
1478 struct radv_dynamic_state *dynamic = &pipeline->dynamic_state;
1479
1480 if (needed_states & RADV_DYNAMIC_VIEWPORT) {
1481 assert(pCreateInfo->pViewportState);
1482
1483 dynamic->viewport.count = pCreateInfo->pViewportState->viewportCount;
1484 if (states & RADV_DYNAMIC_VIEWPORT) {
1485 typed_memcpy(dynamic->viewport.viewports,
1486 pCreateInfo->pViewportState->pViewports,
1487 pCreateInfo->pViewportState->viewportCount);
1488 }
1489 }
1490
1491 if (needed_states & RADV_DYNAMIC_SCISSOR) {
1492 dynamic->scissor.count = pCreateInfo->pViewportState->scissorCount;
1493 if (states & RADV_DYNAMIC_SCISSOR) {
1494 typed_memcpy(dynamic->scissor.scissors,
1495 pCreateInfo->pViewportState->pScissors,
1496 pCreateInfo->pViewportState->scissorCount);
1497 }
1498 }
1499
1500 if (states & RADV_DYNAMIC_LINE_WIDTH) {
1501 assert(pCreateInfo->pRasterizationState);
1502 dynamic->line_width = pCreateInfo->pRasterizationState->lineWidth;
1503 }
1504
1505 if (states & RADV_DYNAMIC_DEPTH_BIAS) {
1506 assert(pCreateInfo->pRasterizationState);
1507 dynamic->depth_bias.bias =
1508 pCreateInfo->pRasterizationState->depthBiasConstantFactor;
1509 dynamic->depth_bias.clamp =
1510 pCreateInfo->pRasterizationState->depthBiasClamp;
1511 dynamic->depth_bias.slope =
1512 pCreateInfo->pRasterizationState->depthBiasSlopeFactor;
1513 }
1514
1515 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1516 *
1517 * pColorBlendState is [...] NULL if the pipeline has rasterization
1518 * disabled or if the subpass of the render pass the pipeline is
1519 * created against does not use any color attachments.
1520 */
1521 if (subpass->has_color_att && states & RADV_DYNAMIC_BLEND_CONSTANTS) {
1522 assert(pCreateInfo->pColorBlendState);
1523 typed_memcpy(dynamic->blend_constants,
1524 pCreateInfo->pColorBlendState->blendConstants, 4);
1525 }
1526
1527 /* If there is no depthstencil attachment, then don't read
1528 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1529 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1530 * no need to override the depthstencil defaults in
1531 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1532 *
1533 * Section 9.2 of the Vulkan 1.0.15 spec says:
1534 *
1535 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1536 * disabled or if the subpass of the render pass the pipeline is created
1537 * against does not use a depth/stencil attachment.
1538 */
1539 if (needed_states && subpass->depth_stencil_attachment) {
1540 assert(pCreateInfo->pDepthStencilState);
1541
1542 if (states & RADV_DYNAMIC_DEPTH_BOUNDS) {
1543 dynamic->depth_bounds.min =
1544 pCreateInfo->pDepthStencilState->minDepthBounds;
1545 dynamic->depth_bounds.max =
1546 pCreateInfo->pDepthStencilState->maxDepthBounds;
1547 }
1548
1549 if (states & RADV_DYNAMIC_STENCIL_COMPARE_MASK) {
1550 dynamic->stencil_compare_mask.front =
1551 pCreateInfo->pDepthStencilState->front.compareMask;
1552 dynamic->stencil_compare_mask.back =
1553 pCreateInfo->pDepthStencilState->back.compareMask;
1554 }
1555
1556 if (states & RADV_DYNAMIC_STENCIL_WRITE_MASK) {
1557 dynamic->stencil_write_mask.front =
1558 pCreateInfo->pDepthStencilState->front.writeMask;
1559 dynamic->stencil_write_mask.back =
1560 pCreateInfo->pDepthStencilState->back.writeMask;
1561 }
1562
1563 if (states & RADV_DYNAMIC_STENCIL_REFERENCE) {
1564 dynamic->stencil_reference.front =
1565 pCreateInfo->pDepthStencilState->front.reference;
1566 dynamic->stencil_reference.back =
1567 pCreateInfo->pDepthStencilState->back.reference;
1568 }
1569 }
1570
1571 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
1572 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
1573 if (needed_states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1574 dynamic->discard_rectangle.count = discard_rectangle_info->discardRectangleCount;
1575 if (states & RADV_DYNAMIC_DISCARD_RECTANGLE) {
1576 typed_memcpy(dynamic->discard_rectangle.rectangles,
1577 discard_rectangle_info->pDiscardRectangles,
1578 discard_rectangle_info->discardRectangleCount);
1579 }
1580 }
1581
1582 if (needed_states & RADV_DYNAMIC_SAMPLE_LOCATIONS) {
1583 const VkPipelineSampleLocationsStateCreateInfoEXT *sample_location_info =
1584 vk_find_struct_const(pCreateInfo->pMultisampleState->pNext,
1585 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT);
1586 /* If sampleLocationsEnable is VK_FALSE, the default sample
1587 * locations are used and the values specified in
1588 * sampleLocationsInfo are ignored.
1589 */
1590 if (sample_location_info->sampleLocationsEnable) {
1591 const VkSampleLocationsInfoEXT *pSampleLocationsInfo =
1592 &sample_location_info->sampleLocationsInfo;
1593
1594 assert(pSampleLocationsInfo->sampleLocationsCount <= MAX_SAMPLE_LOCATIONS);
1595
1596 dynamic->sample_location.per_pixel = pSampleLocationsInfo->sampleLocationsPerPixel;
1597 dynamic->sample_location.grid_size = pSampleLocationsInfo->sampleLocationGridSize;
1598 dynamic->sample_location.count = pSampleLocationsInfo->sampleLocationsCount;
1599 typed_memcpy(&dynamic->sample_location.locations[0],
1600 pSampleLocationsInfo->pSampleLocations,
1601 pSampleLocationsInfo->sampleLocationsCount);
1602 }
1603 }
1604
1605 const VkPipelineRasterizationLineStateCreateInfoEXT *rast_line_info =
1606 vk_find_struct_const(pCreateInfo->pRasterizationState->pNext,
1607 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT);
1608 if (needed_states & RADV_DYNAMIC_LINE_STIPPLE) {
1609 dynamic->line_stipple.factor = rast_line_info->lineStippleFactor;
1610 dynamic->line_stipple.pattern = rast_line_info->lineStipplePattern;
1611 }
1612
1613 pipeline->dynamic_state.mask = states;
1614 }
1615
1616 static void
1617 gfx9_get_gs_info(const struct radv_pipeline_key *key,
1618 const struct radv_pipeline *pipeline,
1619 nir_shader **nir,
1620 struct radv_shader_info *infos,
1621 struct gfx9_gs_info *out)
1622 {
1623 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1624 struct radv_es_output_info *es_info;
1625 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
1626 es_info = nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1627 else
1628 es_info = nir[MESA_SHADER_TESS_CTRL] ?
1629 &infos[MESA_SHADER_TESS_EVAL].tes.es_info :
1630 &infos[MESA_SHADER_VERTEX].vs.es_info;
1631
1632 unsigned gs_num_invocations = MAX2(gs_info->gs.invocations, 1);
1633 bool uses_adjacency;
1634 switch(key->topology) {
1635 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1636 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1637 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1638 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1639 uses_adjacency = true;
1640 break;
1641 default:
1642 uses_adjacency = false;
1643 break;
1644 }
1645
1646 /* All these are in dwords: */
1647 /* We can't allow using the whole LDS, because GS waves compete with
1648 * other shader stages for LDS space. */
1649 const unsigned max_lds_size = 8 * 1024;
1650 const unsigned esgs_itemsize = es_info->esgs_itemsize / 4;
1651 unsigned esgs_lds_size;
1652
1653 /* All these are per subgroup: */
1654 const unsigned max_out_prims = 32 * 1024;
1655 const unsigned max_es_verts = 255;
1656 const unsigned ideal_gs_prims = 64;
1657 unsigned max_gs_prims, gs_prims;
1658 unsigned min_es_verts, es_verts, worst_case_es_verts;
1659
1660 if (uses_adjacency || gs_num_invocations > 1)
1661 max_gs_prims = 127 / gs_num_invocations;
1662 else
1663 max_gs_prims = 255;
1664
1665 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1666 * Make sure we don't go over the maximum value.
1667 */
1668 if (gs_info->gs.vertices_out > 0) {
1669 max_gs_prims = MIN2(max_gs_prims,
1670 max_out_prims /
1671 (gs_info->gs.vertices_out * gs_num_invocations));
1672 }
1673 assert(max_gs_prims > 0);
1674
1675 /* If the primitive has adjacency, halve the number of vertices
1676 * that will be reused in multiple primitives.
1677 */
1678 min_es_verts = gs_info->gs.vertices_in / (uses_adjacency ? 2 : 1);
1679
1680 gs_prims = MIN2(ideal_gs_prims, max_gs_prims);
1681 worst_case_es_verts = MIN2(min_es_verts * gs_prims, max_es_verts);
1682
1683 /* Compute ESGS LDS size based on the worst case number of ES vertices
1684 * needed to create the target number of GS prims per subgroup.
1685 */
1686 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1687
1688 /* If total LDS usage is too big, refactor partitions based on ratio
1689 * of ESGS item sizes.
1690 */
1691 if (esgs_lds_size > max_lds_size) {
1692 /* Our target GS Prims Per Subgroup was too large. Calculate
1693 * the maximum number of GS Prims Per Subgroup that will fit
1694 * into LDS, capped by the maximum that the hardware can support.
1695 */
1696 gs_prims = MIN2((max_lds_size / (esgs_itemsize * min_es_verts)),
1697 max_gs_prims);
1698 assert(gs_prims > 0);
1699 worst_case_es_verts = MIN2(min_es_verts * gs_prims,
1700 max_es_verts);
1701
1702 esgs_lds_size = esgs_itemsize * worst_case_es_verts;
1703 assert(esgs_lds_size <= max_lds_size);
1704 }
1705
1706 /* Now calculate remaining ESGS information. */
1707 if (esgs_lds_size)
1708 es_verts = MIN2(esgs_lds_size / esgs_itemsize, max_es_verts);
1709 else
1710 es_verts = max_es_verts;
1711
1712 /* Vertices for adjacency primitives are not always reused, so restore
1713 * it for ES_VERTS_PER_SUBGRP.
1714 */
1715 min_es_verts = gs_info->gs.vertices_in;
1716
1717 /* For normal primitives, the VGT only checks if they are past the ES
1718 * verts per subgroup after allocating a full GS primitive and if they
1719 * are, kick off a new subgroup. But if those additional ES verts are
1720 * unique (e.g. not reused) we need to make sure there is enough LDS
1721 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1722 */
1723 es_verts -= min_es_verts - 1;
1724
1725 uint32_t es_verts_per_subgroup = es_verts;
1726 uint32_t gs_prims_per_subgroup = gs_prims;
1727 uint32_t gs_inst_prims_in_subgroup = gs_prims * gs_num_invocations;
1728 uint32_t max_prims_per_subgroup = gs_inst_prims_in_subgroup * gs_info->gs.vertices_out;
1729 out->lds_size = align(esgs_lds_size, 128) / 128;
1730 out->vgt_gs_onchip_cntl = S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup) |
1731 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup) |
1732 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup);
1733 out->vgt_gs_max_prims_per_subgroup = S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup);
1734 out->vgt_esgs_ring_itemsize = esgs_itemsize;
1735 assert(max_prims_per_subgroup <= max_out_prims);
1736 }
1737
1738 static void clamp_gsprims_to_esverts(unsigned *max_gsprims, unsigned max_esverts,
1739 unsigned min_verts_per_prim, bool use_adjacency)
1740 {
1741 unsigned max_reuse = max_esverts - min_verts_per_prim;
1742 if (use_adjacency)
1743 max_reuse /= 2;
1744 *max_gsprims = MIN2(*max_gsprims, 1 + max_reuse);
1745 }
1746
1747 static unsigned
1748 radv_get_num_input_vertices(nir_shader **nir)
1749 {
1750 if (nir[MESA_SHADER_GEOMETRY]) {
1751 nir_shader *gs = nir[MESA_SHADER_GEOMETRY];
1752
1753 return gs->info.gs.vertices_in;
1754 }
1755
1756 if (nir[MESA_SHADER_TESS_CTRL]) {
1757 nir_shader *tes = nir[MESA_SHADER_TESS_EVAL];
1758
1759 if (tes->info.tess.point_mode)
1760 return 1;
1761 if (tes->info.tess.primitive_mode == GL_ISOLINES)
1762 return 2;
1763 return 3;
1764 }
1765
1766 return 3;
1767 }
1768
1769 static void
1770 gfx10_get_ngg_info(const struct radv_pipeline_key *key,
1771 struct radv_pipeline *pipeline,
1772 nir_shader **nir,
1773 struct radv_shader_info *infos,
1774 struct gfx10_ngg_info *ngg)
1775 {
1776 struct radv_shader_info *gs_info = &infos[MESA_SHADER_GEOMETRY];
1777 struct radv_es_output_info *es_info =
1778 nir[MESA_SHADER_TESS_CTRL] ? &gs_info->tes.es_info : &gs_info->vs.es_info;
1779 unsigned gs_type = nir[MESA_SHADER_GEOMETRY] ? MESA_SHADER_GEOMETRY : MESA_SHADER_VERTEX;
1780 unsigned max_verts_per_prim = radv_get_num_input_vertices(nir);
1781 unsigned min_verts_per_prim =
1782 gs_type == MESA_SHADER_GEOMETRY ? max_verts_per_prim : 1;
1783 unsigned gs_num_invocations = nir[MESA_SHADER_GEOMETRY] ? MAX2(gs_info->gs.invocations, 1) : 1;
1784 bool uses_adjacency;
1785 switch(key->topology) {
1786 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY:
1787 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY:
1788 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY:
1789 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY:
1790 uses_adjacency = true;
1791 break;
1792 default:
1793 uses_adjacency = false;
1794 break;
1795 }
1796
1797 /* All these are in dwords: */
1798 /* We can't allow using the whole LDS, because GS waves compete with
1799 * other shader stages for LDS space.
1800 *
1801 * TODO: We should really take the shader's internal LDS use into
1802 * account. The linker will fail if the size is greater than
1803 * 8K dwords.
1804 */
1805 const unsigned max_lds_size = 8 * 1024 - 768;
1806 const unsigned target_lds_size = max_lds_size;
1807 unsigned esvert_lds_size = 0;
1808 unsigned gsprim_lds_size = 0;
1809
1810 /* All these are per subgroup: */
1811 bool max_vert_out_per_gs_instance = false;
1812 unsigned max_esverts_base = 256;
1813 unsigned max_gsprims_base = 128; /* default prim group size clamp */
1814
1815 /* Hardware has the following non-natural restrictions on the value
1816 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1817 * the draw:
1818 * - at most 252 for any line input primitive type
1819 * - at most 251 for any quad input primitive type
1820 * - at most 251 for triangle strips with adjacency (this happens to
1821 * be the natural limit for triangle *lists* with adjacency)
1822 */
1823 max_esverts_base = MIN2(max_esverts_base, 251 + max_verts_per_prim - 1);
1824
1825 if (gs_type == MESA_SHADER_GEOMETRY) {
1826 unsigned max_out_verts_per_gsprim =
1827 gs_info->gs.vertices_out * gs_num_invocations;
1828
1829 if (max_out_verts_per_gsprim <= 256) {
1830 if (max_out_verts_per_gsprim) {
1831 max_gsprims_base = MIN2(max_gsprims_base,
1832 256 / max_out_verts_per_gsprim);
1833 }
1834 } else {
1835 /* Use special multi-cycling mode in which each GS
1836 * instance gets its own subgroup. Does not work with
1837 * tessellation. */
1838 max_vert_out_per_gs_instance = true;
1839 max_gsprims_base = 1;
1840 max_out_verts_per_gsprim = gs_info->gs.vertices_out;
1841 }
1842
1843 esvert_lds_size = es_info->esgs_itemsize / 4;
1844 gsprim_lds_size = (gs_info->gs.gsvs_vertex_size / 4 + 1) * max_out_verts_per_gsprim;
1845 } else {
1846 /* VS and TES. */
1847 /* LDS size for passing data from GS to ES. */
1848 struct radv_streamout_info *so_info = nir[MESA_SHADER_TESS_CTRL]
1849 ? &infos[MESA_SHADER_TESS_EVAL].so
1850 : &infos[MESA_SHADER_VERTEX].so;
1851
1852 if (so_info->num_outputs)
1853 esvert_lds_size = 4 * so_info->num_outputs + 1;
1854
1855 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1856 * corresponding to the ES thread of the provoking vertex. All
1857 * ES threads load and export PrimitiveID for their thread.
1858 */
1859 if (!nir[MESA_SHADER_TESS_CTRL] &&
1860 infos[MESA_SHADER_VERTEX].vs.outinfo.export_prim_id)
1861 esvert_lds_size = MAX2(esvert_lds_size, 1);
1862 }
1863
1864 unsigned max_gsprims = max_gsprims_base;
1865 unsigned max_esverts = max_esverts_base;
1866
1867 if (esvert_lds_size)
1868 max_esverts = MIN2(max_esverts, target_lds_size / esvert_lds_size);
1869 if (gsprim_lds_size)
1870 max_gsprims = MIN2(max_gsprims, target_lds_size / gsprim_lds_size);
1871
1872 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1873 clamp_gsprims_to_esverts(&max_gsprims, max_esverts, min_verts_per_prim, uses_adjacency);
1874 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1875
1876 if (esvert_lds_size || gsprim_lds_size) {
1877 /* Now that we have a rough proportionality between esverts
1878 * and gsprims based on the primitive type, scale both of them
1879 * down simultaneously based on required LDS space.
1880 *
1881 * We could be smarter about this if we knew how much vertex
1882 * reuse to expect.
1883 */
1884 unsigned lds_total = max_esverts * esvert_lds_size +
1885 max_gsprims * gsprim_lds_size;
1886 if (lds_total > target_lds_size) {
1887 max_esverts = max_esverts * target_lds_size / lds_total;
1888 max_gsprims = max_gsprims * target_lds_size / lds_total;
1889
1890 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1891 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1892 min_verts_per_prim, uses_adjacency);
1893 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1894 }
1895 }
1896
1897 /* Round up towards full wave sizes for better ALU utilization. */
1898 if (!max_vert_out_per_gs_instance) {
1899 unsigned orig_max_esverts;
1900 unsigned orig_max_gsprims;
1901 unsigned wavesize;
1902
1903 if (gs_type == MESA_SHADER_GEOMETRY) {
1904 wavesize = gs_info->wave_size;
1905 } else {
1906 wavesize = nir[MESA_SHADER_TESS_CTRL]
1907 ? infos[MESA_SHADER_TESS_EVAL].wave_size
1908 : infos[MESA_SHADER_VERTEX].wave_size;
1909 }
1910
1911 do {
1912 orig_max_esverts = max_esverts;
1913 orig_max_gsprims = max_gsprims;
1914
1915 max_esverts = align(max_esverts, wavesize);
1916 max_esverts = MIN2(max_esverts, max_esverts_base);
1917 if (esvert_lds_size)
1918 max_esverts = MIN2(max_esverts,
1919 (max_lds_size - max_gsprims * gsprim_lds_size) /
1920 esvert_lds_size);
1921 max_esverts = MIN2(max_esverts, max_gsprims * max_verts_per_prim);
1922
1923 max_gsprims = align(max_gsprims, wavesize);
1924 max_gsprims = MIN2(max_gsprims, max_gsprims_base);
1925 if (gsprim_lds_size)
1926 max_gsprims = MIN2(max_gsprims,
1927 (max_lds_size - max_esverts * esvert_lds_size) /
1928 gsprim_lds_size);
1929 clamp_gsprims_to_esverts(&max_gsprims, max_esverts,
1930 min_verts_per_prim, uses_adjacency);
1931 assert(max_esverts >= max_verts_per_prim && max_gsprims >= 1);
1932 } while (orig_max_esverts != max_esverts || orig_max_gsprims != max_gsprims);
1933 }
1934
1935 /* Hardware restriction: minimum value of max_esverts */
1936 max_esverts = MAX2(max_esverts, 23 + max_verts_per_prim);
1937
1938 unsigned max_out_vertices =
1939 max_vert_out_per_gs_instance ? gs_info->gs.vertices_out :
1940 gs_type == MESA_SHADER_GEOMETRY ?
1941 max_gsprims * gs_num_invocations * gs_info->gs.vertices_out :
1942 max_esverts;
1943 assert(max_out_vertices <= 256);
1944
1945 unsigned prim_amp_factor = 1;
1946 if (gs_type == MESA_SHADER_GEOMETRY) {
1947 /* Number of output primitives per GS input primitive after
1948 * GS instancing. */
1949 prim_amp_factor = gs_info->gs.vertices_out;
1950 }
1951
1952 /* The GE only checks against the maximum number of ES verts after
1953 * allocating a full GS primitive. So we need to ensure that whenever
1954 * this check passes, there is enough space for a full primitive without
1955 * vertex reuse.
1956 */
1957 ngg->hw_max_esverts = max_esverts - max_verts_per_prim + 1;
1958 ngg->max_gsprims = max_gsprims;
1959 ngg->max_out_verts = max_out_vertices;
1960 ngg->prim_amp_factor = prim_amp_factor;
1961 ngg->max_vert_out_per_gs_instance = max_vert_out_per_gs_instance;
1962 ngg->ngg_emit_size = max_gsprims * gsprim_lds_size;
1963 ngg->esgs_ring_size = 4 * max_esverts * esvert_lds_size;
1964
1965 if (gs_type == MESA_SHADER_GEOMETRY) {
1966 ngg->vgt_esgs_ring_itemsize = es_info->esgs_itemsize / 4;
1967 } else {
1968 ngg->vgt_esgs_ring_itemsize = 1;
1969 }
1970
1971 pipeline->graphics.esgs_ring_size = ngg->esgs_ring_size;
1972
1973 assert(ngg->hw_max_esverts >= 24); /* HW limitation */
1974 }
1975
1976 static void
1977 calculate_gs_ring_sizes(struct radv_pipeline *pipeline,
1978 const struct gfx9_gs_info *gs)
1979 {
1980 struct radv_device *device = pipeline->device;
1981 unsigned num_se = device->physical_device->rad_info.max_se;
1982 unsigned wave_size = 64;
1983 unsigned max_gs_waves = 32 * num_se; /* max 32 per SE on GCN */
1984 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1985 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1986 */
1987 unsigned gs_vertex_reuse =
1988 (device->physical_device->rad_info.chip_class >= GFX8 ? 32 : 16) * num_se;
1989 unsigned alignment = 256 * num_se;
1990 /* The maximum size is 63.999 MB per SE. */
1991 unsigned max_size = ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se;
1992 struct radv_shader_info *gs_info = &pipeline->shaders[MESA_SHADER_GEOMETRY]->info;
1993
1994 /* Calculate the minimum size. */
1995 unsigned min_esgs_ring_size = align(gs->vgt_esgs_ring_itemsize * 4 * gs_vertex_reuse *
1996 wave_size, alignment);
1997 /* These are recommended sizes, not minimum sizes. */
1998 unsigned esgs_ring_size = max_gs_waves * 2 * wave_size *
1999 gs->vgt_esgs_ring_itemsize * 4 * gs_info->gs.vertices_in;
2000 unsigned gsvs_ring_size = max_gs_waves * 2 * wave_size *
2001 gs_info->gs.max_gsvs_emit_size;
2002
2003 min_esgs_ring_size = align(min_esgs_ring_size, alignment);
2004 esgs_ring_size = align(esgs_ring_size, alignment);
2005 gsvs_ring_size = align(gsvs_ring_size, alignment);
2006
2007 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
2008 pipeline->graphics.esgs_ring_size = CLAMP(esgs_ring_size, min_esgs_ring_size, max_size);
2009
2010 pipeline->graphics.gsvs_ring_size = MIN2(gsvs_ring_size, max_size);
2011 }
2012
2013 static void si_multiwave_lds_size_workaround(struct radv_device *device,
2014 unsigned *lds_size)
2015 {
2016 /* If tessellation is all offchip and on-chip GS isn't used, this
2017 * workaround is not needed.
2018 */
2019 return;
2020
2021 /* SPI barrier management bug:
2022 * Make sure we have at least 4k of LDS in use to avoid the bug.
2023 * It applies to workgroup sizes of more than one wavefront.
2024 */
2025 if (device->physical_device->rad_info.family == CHIP_BONAIRE ||
2026 device->physical_device->rad_info.family == CHIP_KABINI)
2027 *lds_size = MAX2(*lds_size, 8);
2028 }
2029
2030 struct radv_shader_variant *
2031 radv_get_shader(struct radv_pipeline *pipeline,
2032 gl_shader_stage stage)
2033 {
2034 if (stage == MESA_SHADER_VERTEX) {
2035 if (pipeline->shaders[MESA_SHADER_VERTEX])
2036 return pipeline->shaders[MESA_SHADER_VERTEX];
2037 if (pipeline->shaders[MESA_SHADER_TESS_CTRL])
2038 return pipeline->shaders[MESA_SHADER_TESS_CTRL];
2039 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
2040 return pipeline->shaders[MESA_SHADER_GEOMETRY];
2041 } else if (stage == MESA_SHADER_TESS_EVAL) {
2042 if (!radv_pipeline_has_tess(pipeline))
2043 return NULL;
2044 if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
2045 return pipeline->shaders[MESA_SHADER_TESS_EVAL];
2046 if (pipeline->shaders[MESA_SHADER_GEOMETRY])
2047 return pipeline->shaders[MESA_SHADER_GEOMETRY];
2048 }
2049 return pipeline->shaders[stage];
2050 }
2051
2052 static struct radv_tessellation_state
2053 calculate_tess_state(struct radv_pipeline *pipeline,
2054 const VkGraphicsPipelineCreateInfo *pCreateInfo)
2055 {
2056 unsigned num_tcs_input_cp;
2057 unsigned num_tcs_output_cp;
2058 unsigned lds_size;
2059 unsigned num_patches;
2060 struct radv_tessellation_state tess = {0};
2061
2062 num_tcs_input_cp = pCreateInfo->pTessellationState->patchControlPoints;
2063 num_tcs_output_cp = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.tcs_vertices_out; //TCS VERTICES OUT
2064 num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2065
2066 lds_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.lds_size;
2067
2068 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
2069 assert(lds_size <= 65536);
2070 lds_size = align(lds_size, 512) / 512;
2071 } else {
2072 assert(lds_size <= 32768);
2073 lds_size = align(lds_size, 256) / 256;
2074 }
2075 si_multiwave_lds_size_workaround(pipeline->device, &lds_size);
2076
2077 tess.lds_size = lds_size;
2078
2079 tess.ls_hs_config = S_028B58_NUM_PATCHES(num_patches) |
2080 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp) |
2081 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp);
2082 tess.num_patches = num_patches;
2083
2084 struct radv_shader_variant *tes = radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL);
2085 unsigned type = 0, partitioning = 0, topology = 0, distribution_mode = 0;
2086
2087 switch (tes->info.tes.primitive_mode) {
2088 case GL_TRIANGLES:
2089 type = V_028B6C_TESS_TRIANGLE;
2090 break;
2091 case GL_QUADS:
2092 type = V_028B6C_TESS_QUAD;
2093 break;
2094 case GL_ISOLINES:
2095 type = V_028B6C_TESS_ISOLINE;
2096 break;
2097 }
2098
2099 switch (tes->info.tes.spacing) {
2100 case TESS_SPACING_EQUAL:
2101 partitioning = V_028B6C_PART_INTEGER;
2102 break;
2103 case TESS_SPACING_FRACTIONAL_ODD:
2104 partitioning = V_028B6C_PART_FRAC_ODD;
2105 break;
2106 case TESS_SPACING_FRACTIONAL_EVEN:
2107 partitioning = V_028B6C_PART_FRAC_EVEN;
2108 break;
2109 default:
2110 break;
2111 }
2112
2113 bool ccw = tes->info.tes.ccw;
2114 const VkPipelineTessellationDomainOriginStateCreateInfo *domain_origin_state =
2115 vk_find_struct_const(pCreateInfo->pTessellationState,
2116 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO);
2117
2118 if (domain_origin_state && domain_origin_state->domainOrigin != VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT)
2119 ccw = !ccw;
2120
2121 if (tes->info.tes.point_mode)
2122 topology = V_028B6C_OUTPUT_POINT;
2123 else if (tes->info.tes.primitive_mode == GL_ISOLINES)
2124 topology = V_028B6C_OUTPUT_LINE;
2125 else if (ccw)
2126 topology = V_028B6C_OUTPUT_TRIANGLE_CCW;
2127 else
2128 topology = V_028B6C_OUTPUT_TRIANGLE_CW;
2129
2130 if (pipeline->device->physical_device->rad_info.has_distributed_tess) {
2131 if (pipeline->device->physical_device->rad_info.family == CHIP_FIJI ||
2132 pipeline->device->physical_device->rad_info.family >= CHIP_POLARIS10)
2133 distribution_mode = V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS;
2134 else
2135 distribution_mode = V_028B6C_DISTRIBUTION_MODE_DONUTS;
2136 } else
2137 distribution_mode = V_028B6C_DISTRIBUTION_MODE_NO_DIST;
2138
2139 tess.tf_param = S_028B6C_TYPE(type) |
2140 S_028B6C_PARTITIONING(partitioning) |
2141 S_028B6C_TOPOLOGY(topology) |
2142 S_028B6C_DISTRIBUTION_MODE(distribution_mode);
2143
2144 return tess;
2145 }
2146
2147 static const struct radv_prim_vertex_count prim_size_table[] = {
2148 [V_008958_DI_PT_NONE] = {0, 0},
2149 [V_008958_DI_PT_POINTLIST] = {1, 1},
2150 [V_008958_DI_PT_LINELIST] = {2, 2},
2151 [V_008958_DI_PT_LINESTRIP] = {2, 1},
2152 [V_008958_DI_PT_TRILIST] = {3, 3},
2153 [V_008958_DI_PT_TRIFAN] = {3, 1},
2154 [V_008958_DI_PT_TRISTRIP] = {3, 1},
2155 [V_008958_DI_PT_LINELIST_ADJ] = {4, 4},
2156 [V_008958_DI_PT_LINESTRIP_ADJ] = {4, 1},
2157 [V_008958_DI_PT_TRILIST_ADJ] = {6, 6},
2158 [V_008958_DI_PT_TRISTRIP_ADJ] = {6, 2},
2159 [V_008958_DI_PT_RECTLIST] = {3, 3},
2160 [V_008958_DI_PT_LINELOOP] = {2, 1},
2161 [V_008958_DI_PT_POLYGON] = {3, 1},
2162 [V_008958_DI_PT_2D_TRI_STRIP] = {0, 0},
2163 };
2164
2165 static const struct radv_vs_output_info *get_vs_output_info(const struct radv_pipeline *pipeline)
2166 {
2167 if (radv_pipeline_has_gs(pipeline))
2168 if (radv_pipeline_has_ngg(pipeline))
2169 return &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.vs.outinfo;
2170 else
2171 return &pipeline->gs_copy_shader->info.vs.outinfo;
2172 else if (radv_pipeline_has_tess(pipeline))
2173 return &pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.outinfo;
2174 else
2175 return &pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.outinfo;
2176 }
2177
2178 static void
2179 radv_link_shaders(struct radv_pipeline *pipeline, nir_shader **shaders)
2180 {
2181 nir_shader* ordered_shaders[MESA_SHADER_STAGES];
2182 int shader_count = 0;
2183
2184 if(shaders[MESA_SHADER_FRAGMENT]) {
2185 ordered_shaders[shader_count++] = shaders[MESA_SHADER_FRAGMENT];
2186 }
2187 if(shaders[MESA_SHADER_GEOMETRY]) {
2188 ordered_shaders[shader_count++] = shaders[MESA_SHADER_GEOMETRY];
2189 }
2190 if(shaders[MESA_SHADER_TESS_EVAL]) {
2191 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_EVAL];
2192 }
2193 if(shaders[MESA_SHADER_TESS_CTRL]) {
2194 ordered_shaders[shader_count++] = shaders[MESA_SHADER_TESS_CTRL];
2195 }
2196 if(shaders[MESA_SHADER_VERTEX]) {
2197 ordered_shaders[shader_count++] = shaders[MESA_SHADER_VERTEX];
2198 }
2199
2200 if (shader_count > 1) {
2201 unsigned first = ordered_shaders[shader_count - 1]->info.stage;
2202 unsigned last = ordered_shaders[0]->info.stage;
2203
2204 if (ordered_shaders[0]->info.stage == MESA_SHADER_FRAGMENT &&
2205 ordered_shaders[1]->info.has_transform_feedback_varyings)
2206 nir_link_xfb_varyings(ordered_shaders[1], ordered_shaders[0]);
2207
2208 for (int i = 0; i < shader_count; ++i) {
2209 nir_variable_mode mask = 0;
2210
2211 if (ordered_shaders[i]->info.stage != first)
2212 mask = mask | nir_var_shader_in;
2213
2214 if (ordered_shaders[i]->info.stage != last)
2215 mask = mask | nir_var_shader_out;
2216
2217 nir_lower_io_to_scalar_early(ordered_shaders[i], mask);
2218 radv_optimize_nir(ordered_shaders[i], false, false);
2219 }
2220 }
2221
2222 for (int i = 1; i < shader_count; ++i) {
2223 nir_lower_io_arrays_to_elements(ordered_shaders[i],
2224 ordered_shaders[i - 1]);
2225
2226 if (nir_link_opt_varyings(ordered_shaders[i],
2227 ordered_shaders[i - 1]))
2228 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2229
2230 nir_remove_dead_variables(ordered_shaders[i],
2231 nir_var_shader_out);
2232 nir_remove_dead_variables(ordered_shaders[i - 1],
2233 nir_var_shader_in);
2234
2235 bool progress = nir_remove_unused_varyings(ordered_shaders[i],
2236 ordered_shaders[i - 1]);
2237
2238 nir_compact_varyings(ordered_shaders[i],
2239 ordered_shaders[i - 1], true);
2240
2241 if (progress) {
2242 if (nir_lower_global_vars_to_local(ordered_shaders[i])) {
2243 ac_lower_indirect_derefs(ordered_shaders[i],
2244 pipeline->device->physical_device->rad_info.chip_class);
2245 }
2246 radv_optimize_nir(ordered_shaders[i], false, false);
2247
2248 if (nir_lower_global_vars_to_local(ordered_shaders[i - 1])) {
2249 ac_lower_indirect_derefs(ordered_shaders[i - 1],
2250 pipeline->device->physical_device->rad_info.chip_class);
2251 }
2252 radv_optimize_nir(ordered_shaders[i - 1], false, false);
2253 }
2254 }
2255 }
2256
2257 static uint32_t
2258 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo *input_state,
2259 uint32_t attrib_binding)
2260 {
2261 for (uint32_t i = 0; i < input_state->vertexBindingDescriptionCount; i++) {
2262 const VkVertexInputBindingDescription *input_binding =
2263 &input_state->pVertexBindingDescriptions[i];
2264
2265 if (input_binding->binding == attrib_binding)
2266 return input_binding->stride;
2267 }
2268
2269 return 0;
2270 }
2271
2272 static struct radv_pipeline_key
2273 radv_generate_graphics_pipeline_key(struct radv_pipeline *pipeline,
2274 const VkGraphicsPipelineCreateInfo *pCreateInfo,
2275 const struct radv_blend_state *blend,
2276 bool has_view_index)
2277 {
2278 const VkPipelineVertexInputStateCreateInfo *input_state =
2279 pCreateInfo->pVertexInputState;
2280 const VkPipelineVertexInputDivisorStateCreateInfoEXT *divisor_state =
2281 vk_find_struct_const(input_state->pNext, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT);
2282
2283 struct radv_pipeline_key key;
2284 memset(&key, 0, sizeof(key));
2285
2286 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
2287 key.optimisations_disabled = 1;
2288
2289 key.has_multiview_view_index = has_view_index;
2290
2291 uint32_t binding_input_rate = 0;
2292 uint32_t instance_rate_divisors[MAX_VERTEX_ATTRIBS];
2293 for (unsigned i = 0; i < input_state->vertexBindingDescriptionCount; ++i) {
2294 if (input_state->pVertexBindingDescriptions[i].inputRate) {
2295 unsigned binding = input_state->pVertexBindingDescriptions[i].binding;
2296 binding_input_rate |= 1u << binding;
2297 instance_rate_divisors[binding] = 1;
2298 }
2299 }
2300 if (divisor_state) {
2301 for (unsigned i = 0; i < divisor_state->vertexBindingDivisorCount; ++i) {
2302 instance_rate_divisors[divisor_state->pVertexBindingDivisors[i].binding] =
2303 divisor_state->pVertexBindingDivisors[i].divisor;
2304 }
2305 }
2306
2307 for (unsigned i = 0; i < input_state->vertexAttributeDescriptionCount; ++i) {
2308 const VkVertexInputAttributeDescription *desc =
2309 &input_state->pVertexAttributeDescriptions[i];
2310 const struct vk_format_description *format_desc;
2311 unsigned location = desc->location;
2312 unsigned binding = desc->binding;
2313 unsigned num_format, data_format;
2314 int first_non_void;
2315
2316 if (binding_input_rate & (1u << binding)) {
2317 key.instance_rate_inputs |= 1u << location;
2318 key.instance_rate_divisors[location] = instance_rate_divisors[binding];
2319 }
2320
2321 format_desc = vk_format_description(desc->format);
2322 first_non_void = vk_format_get_first_non_void_channel(desc->format);
2323
2324 num_format = radv_translate_buffer_numformat(format_desc, first_non_void);
2325 data_format = radv_translate_buffer_dataformat(format_desc, first_non_void);
2326
2327 key.vertex_attribute_formats[location] = data_format | (num_format << 4);
2328 key.vertex_attribute_bindings[location] = desc->binding;
2329 key.vertex_attribute_offsets[location] = desc->offset;
2330 key.vertex_attribute_strides[location] = radv_get_attrib_stride(input_state, desc->binding);
2331
2332 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8 &&
2333 pipeline->device->physical_device->rad_info.family != CHIP_STONEY) {
2334 VkFormat format = input_state->pVertexAttributeDescriptions[i].format;
2335 uint64_t adjust;
2336 switch(format) {
2337 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2338 case VK_FORMAT_A2B10G10R10_SNORM_PACK32:
2339 adjust = RADV_ALPHA_ADJUST_SNORM;
2340 break;
2341 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2342 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32:
2343 adjust = RADV_ALPHA_ADJUST_SSCALED;
2344 break;
2345 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2346 case VK_FORMAT_A2B10G10R10_SINT_PACK32:
2347 adjust = RADV_ALPHA_ADJUST_SINT;
2348 break;
2349 default:
2350 adjust = 0;
2351 break;
2352 }
2353 key.vertex_alpha_adjust |= adjust << (2 * location);
2354 }
2355
2356 switch (desc->format) {
2357 case VK_FORMAT_B8G8R8A8_UNORM:
2358 case VK_FORMAT_B8G8R8A8_SNORM:
2359 case VK_FORMAT_B8G8R8A8_USCALED:
2360 case VK_FORMAT_B8G8R8A8_SSCALED:
2361 case VK_FORMAT_B8G8R8A8_UINT:
2362 case VK_FORMAT_B8G8R8A8_SINT:
2363 case VK_FORMAT_B8G8R8A8_SRGB:
2364 case VK_FORMAT_A2R10G10B10_UNORM_PACK32:
2365 case VK_FORMAT_A2R10G10B10_SNORM_PACK32:
2366 case VK_FORMAT_A2R10G10B10_USCALED_PACK32:
2367 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32:
2368 case VK_FORMAT_A2R10G10B10_UINT_PACK32:
2369 case VK_FORMAT_A2R10G10B10_SINT_PACK32:
2370 key.vertex_post_shuffle |= 1 << location;
2371 break;
2372 default:
2373 break;
2374 }
2375 }
2376
2377 const VkPipelineTessellationStateCreateInfo *tess =
2378 radv_pipeline_get_tessellation_state(pCreateInfo);
2379 if (tess)
2380 key.tess_input_vertices = tess->patchControlPoints;
2381
2382 const VkPipelineMultisampleStateCreateInfo *vkms =
2383 radv_pipeline_get_multisample_state(pCreateInfo);
2384 if (vkms && vkms->rasterizationSamples > 1) {
2385 uint32_t num_samples = vkms->rasterizationSamples;
2386 uint32_t ps_iter_samples = radv_pipeline_get_ps_iter_samples(pCreateInfo);
2387 key.num_samples = num_samples;
2388 key.log2_ps_iter_samples = util_logbase2(ps_iter_samples);
2389 }
2390
2391 key.col_format = blend->spi_shader_col_format;
2392 if (pipeline->device->physical_device->rad_info.chip_class < GFX8)
2393 radv_pipeline_compute_get_int_clamp(pCreateInfo, &key.is_int8, &key.is_int10);
2394
2395 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10)
2396 key.topology = pCreateInfo->pInputAssemblyState->topology;
2397
2398 return key;
2399 }
2400
2401 static bool
2402 radv_nir_stage_uses_xfb(const nir_shader *nir)
2403 {
2404 nir_xfb_info *xfb = nir_gather_xfb_info(nir, NULL);
2405 bool uses_xfb = !!xfb;
2406
2407 ralloc_free(xfb);
2408 return uses_xfb;
2409 }
2410
2411 static void
2412 radv_fill_shader_keys(struct radv_device *device,
2413 struct radv_shader_variant_key *keys,
2414 const struct radv_pipeline_key *key,
2415 nir_shader **nir)
2416 {
2417 keys[MESA_SHADER_VERTEX].vs.instance_rate_inputs = key->instance_rate_inputs;
2418 keys[MESA_SHADER_VERTEX].vs.alpha_adjust = key->vertex_alpha_adjust;
2419 keys[MESA_SHADER_VERTEX].vs.post_shuffle = key->vertex_post_shuffle;
2420 for (unsigned i = 0; i < MAX_VERTEX_ATTRIBS; ++i) {
2421 keys[MESA_SHADER_VERTEX].vs.instance_rate_divisors[i] = key->instance_rate_divisors[i];
2422 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_formats[i] = key->vertex_attribute_formats[i];
2423 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_bindings[i] = key->vertex_attribute_bindings[i];
2424 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_offsets[i] = key->vertex_attribute_offsets[i];
2425 keys[MESA_SHADER_VERTEX].vs.vertex_attribute_strides[i] = key->vertex_attribute_strides[i];
2426 }
2427 keys[MESA_SHADER_VERTEX].vs.outprim = si_conv_prim_to_gs_out(key->topology);
2428
2429 if (nir[MESA_SHADER_TESS_CTRL]) {
2430 keys[MESA_SHADER_VERTEX].vs_common_out.as_ls = true;
2431 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = 0;
2432 keys[MESA_SHADER_TESS_CTRL].tcs.input_vertices = key->tess_input_vertices;
2433 keys[MESA_SHADER_TESS_CTRL].tcs.primitive_mode = nir[MESA_SHADER_TESS_EVAL]->info.tess.primitive_mode;
2434
2435 keys[MESA_SHADER_TESS_CTRL].tcs.tes_reads_tess_factors = !!(nir[MESA_SHADER_TESS_EVAL]->info.inputs_read & (VARYING_BIT_TESS_LEVEL_INNER | VARYING_BIT_TESS_LEVEL_OUTER));
2436 }
2437
2438 if (nir[MESA_SHADER_GEOMETRY]) {
2439 if (nir[MESA_SHADER_TESS_CTRL])
2440 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_es = true;
2441 else
2442 keys[MESA_SHADER_VERTEX].vs_common_out.as_es = true;
2443 }
2444
2445 if (device->physical_device->use_ngg) {
2446 if (nir[MESA_SHADER_TESS_CTRL]) {
2447 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = true;
2448 } else {
2449 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = true;
2450 }
2451
2452 if (nir[MESA_SHADER_TESS_CTRL] &&
2453 nir[MESA_SHADER_GEOMETRY] &&
2454 nir[MESA_SHADER_GEOMETRY]->info.gs.invocations *
2455 nir[MESA_SHADER_GEOMETRY]->info.gs.vertices_out > 256) {
2456 /* Fallback to the legacy path if tessellation is
2457 * enabled with extreme geometry because
2458 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2459 * might hang.
2460 */
2461 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2462 }
2463
2464 gl_shader_stage last_xfb_stage = MESA_SHADER_VERTEX;
2465
2466 for (int i = MESA_SHADER_VERTEX; i <= MESA_SHADER_GEOMETRY; i++) {
2467 if (nir[i])
2468 last_xfb_stage = i;
2469 }
2470
2471 bool uses_xfb = nir[last_xfb_stage] &&
2472 radv_nir_stage_uses_xfb(nir[last_xfb_stage]);
2473
2474 if (!device->physical_device->use_ngg_streamout && uses_xfb) {
2475 if (nir[MESA_SHADER_TESS_CTRL])
2476 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg = false;
2477 else
2478 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg = false;
2479 }
2480
2481 /* Determine if the pipeline is eligible for the NGG passthrough
2482 * mode. It can't be enabled for geometry shaders, for NGG
2483 * streamout or for vertex shaders that export the primitive ID
2484 * (this is checked later because we don't have the info here.)
2485 */
2486 if (!nir[MESA_SHADER_GEOMETRY] && !uses_xfb) {
2487 if (nir[MESA_SHADER_TESS_CTRL] &&
2488 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg) {
2489 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg_passthrough = true;
2490 } else if (nir[MESA_SHADER_VERTEX] &&
2491 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) {
2492 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = true;
2493 }
2494 }
2495 }
2496
2497 for(int i = 0; i < MESA_SHADER_STAGES; ++i)
2498 keys[i].has_multiview_view_index = key->has_multiview_view_index;
2499
2500 keys[MESA_SHADER_FRAGMENT].fs.col_format = key->col_format;
2501 keys[MESA_SHADER_FRAGMENT].fs.is_int8 = key->is_int8;
2502 keys[MESA_SHADER_FRAGMENT].fs.is_int10 = key->is_int10;
2503 keys[MESA_SHADER_FRAGMENT].fs.log2_ps_iter_samples = key->log2_ps_iter_samples;
2504 keys[MESA_SHADER_FRAGMENT].fs.num_samples = key->num_samples;
2505
2506 if (nir[MESA_SHADER_COMPUTE]) {
2507 keys[MESA_SHADER_COMPUTE].cs.subgroup_size = key->compute_subgroup_size;
2508 }
2509 }
2510
2511 static uint8_t
2512 radv_get_wave_size(struct radv_device *device,
2513 const VkPipelineShaderStageCreateInfo *pStage,
2514 gl_shader_stage stage,
2515 const struct radv_shader_variant_key *key)
2516 {
2517 if (stage == MESA_SHADER_GEOMETRY && !key->vs_common_out.as_ngg)
2518 return 64;
2519 else if (stage == MESA_SHADER_COMPUTE) {
2520 if (key->cs.subgroup_size) {
2521 /* Return the required subgroup size if specified. */
2522 return key->cs.subgroup_size;
2523 }
2524 return device->physical_device->cs_wave_size;
2525 }
2526 else if (stage == MESA_SHADER_FRAGMENT)
2527 return device->physical_device->ps_wave_size;
2528 else
2529 return device->physical_device->ge_wave_size;
2530 }
2531
2532 static uint8_t
2533 radv_get_ballot_bit_size(struct radv_device *device,
2534 const VkPipelineShaderStageCreateInfo *pStage,
2535 gl_shader_stage stage,
2536 const struct radv_shader_variant_key *key)
2537 {
2538 if (stage == MESA_SHADER_COMPUTE && key->cs.subgroup_size)
2539 return key->cs.subgroup_size;
2540 return 64;
2541 }
2542
2543 static void
2544 radv_fill_shader_info(struct radv_pipeline *pipeline,
2545 const VkPipelineShaderStageCreateInfo **pStages,
2546 struct radv_shader_variant_key *keys,
2547 struct radv_shader_info *infos,
2548 nir_shader **nir)
2549 {
2550 unsigned active_stages = 0;
2551 unsigned filled_stages = 0;
2552
2553 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2554 if (nir[i])
2555 active_stages |= (1 << i);
2556 }
2557
2558 if (nir[MESA_SHADER_FRAGMENT]) {
2559 radv_nir_shader_info_init(&infos[MESA_SHADER_FRAGMENT]);
2560 radv_nir_shader_info_pass(nir[MESA_SHADER_FRAGMENT],
2561 pipeline->layout,
2562 &keys[MESA_SHADER_FRAGMENT],
2563 &infos[MESA_SHADER_FRAGMENT]);
2564
2565 /* TODO: These are no longer used as keys we should refactor this */
2566 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id =
2567 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2568 keys[MESA_SHADER_VERTEX].vs_common_out.export_layer_id =
2569 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2570 keys[MESA_SHADER_VERTEX].vs_common_out.export_clip_dists =
2571 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2572 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_prim_id =
2573 infos[MESA_SHADER_FRAGMENT].ps.prim_id_input;
2574 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_layer_id =
2575 infos[MESA_SHADER_FRAGMENT].ps.layer_input;
2576 keys[MESA_SHADER_TESS_EVAL].vs_common_out.export_clip_dists =
2577 !!infos[MESA_SHADER_FRAGMENT].ps.num_input_clips_culls;
2578
2579 /* NGG passthrough mode can't be enabled for vertex shaders
2580 * that export the primitive ID.
2581 *
2582 * TODO: I should really refactor the keys logic.
2583 */
2584 if (nir[MESA_SHADER_VERTEX] &&
2585 keys[MESA_SHADER_VERTEX].vs_common_out.export_prim_id) {
2586 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg_passthrough = false;
2587 }
2588
2589 filled_stages |= (1 << MESA_SHADER_FRAGMENT);
2590 }
2591
2592 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2593 nir[MESA_SHADER_TESS_CTRL]) {
2594 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2595 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2596 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2597
2598 radv_nir_shader_info_init(&infos[MESA_SHADER_TESS_CTRL]);
2599
2600 for (int i = 0; i < 2; i++) {
2601 radv_nir_shader_info_pass(combined_nir[i],
2602 pipeline->layout, &key,
2603 &infos[MESA_SHADER_TESS_CTRL]);
2604 }
2605
2606 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2607 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2608 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2609 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2610
2611 filled_stages |= (1 << MESA_SHADER_VERTEX);
2612 filled_stages |= (1 << MESA_SHADER_TESS_CTRL);
2613 }
2614
2615 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9 &&
2616 nir[MESA_SHADER_GEOMETRY]) {
2617 gl_shader_stage pre_stage = nir[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2618 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2619
2620 radv_nir_shader_info_init(&infos[MESA_SHADER_GEOMETRY]);
2621
2622 for (int i = 0; i < 2; i++) {
2623 radv_nir_shader_info_pass(combined_nir[i],
2624 pipeline->layout,
2625 &keys[pre_stage],
2626 &infos[MESA_SHADER_GEOMETRY]);
2627 }
2628
2629 filled_stages |= (1 << pre_stage);
2630 filled_stages |= (1 << MESA_SHADER_GEOMETRY);
2631 }
2632
2633 active_stages ^= filled_stages;
2634 while (active_stages) {
2635 int i = u_bit_scan(&active_stages);
2636
2637 if (i == MESA_SHADER_TESS_CTRL) {
2638 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs =
2639 util_last_bit64(infos[MESA_SHADER_VERTEX].vs.ls_outputs_written);
2640 }
2641
2642 if (i == MESA_SHADER_TESS_EVAL) {
2643 keys[MESA_SHADER_TESS_EVAL].tes.num_patches =
2644 infos[MESA_SHADER_TESS_CTRL].tcs.num_patches;
2645 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs =
2646 util_last_bit64(infos[MESA_SHADER_TESS_CTRL].tcs.outputs_written);
2647 }
2648
2649 radv_nir_shader_info_init(&infos[i]);
2650 radv_nir_shader_info_pass(nir[i], pipeline->layout,
2651 &keys[i], &infos[i]);
2652 }
2653
2654 for (int i = 0; i < MESA_SHADER_STAGES; i++) {
2655 if (nir[i]) {
2656 infos[i].wave_size =
2657 radv_get_wave_size(pipeline->device, pStages[i],
2658 i, &keys[i]);
2659 infos[i].ballot_bit_size =
2660 radv_get_ballot_bit_size(pipeline->device,
2661 pStages[i], i,
2662 &keys[i]);
2663 }
2664 }
2665 }
2666
2667 static void
2668 merge_tess_info(struct shader_info *tes_info,
2669 const struct shader_info *tcs_info)
2670 {
2671 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2672 *
2673 * "PointMode. Controls generation of points rather than triangles
2674 * or lines. This functionality defaults to disabled, and is
2675 * enabled if either shader stage includes the execution mode.
2676 *
2677 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2678 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2679 * and OutputVertices, it says:
2680 *
2681 * "One mode must be set in at least one of the tessellation
2682 * shader stages."
2683 *
2684 * So, the fields can be set in either the TCS or TES, but they must
2685 * agree if set in both. Our backend looks at TES, so bitwise-or in
2686 * the values from the TCS.
2687 */
2688 assert(tcs_info->tess.tcs_vertices_out == 0 ||
2689 tes_info->tess.tcs_vertices_out == 0 ||
2690 tcs_info->tess.tcs_vertices_out == tes_info->tess.tcs_vertices_out);
2691 tes_info->tess.tcs_vertices_out |= tcs_info->tess.tcs_vertices_out;
2692
2693 assert(tcs_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2694 tes_info->tess.spacing == TESS_SPACING_UNSPECIFIED ||
2695 tcs_info->tess.spacing == tes_info->tess.spacing);
2696 tes_info->tess.spacing |= tcs_info->tess.spacing;
2697
2698 assert(tcs_info->tess.primitive_mode == 0 ||
2699 tes_info->tess.primitive_mode == 0 ||
2700 tcs_info->tess.primitive_mode == tes_info->tess.primitive_mode);
2701 tes_info->tess.primitive_mode |= tcs_info->tess.primitive_mode;
2702 tes_info->tess.ccw |= tcs_info->tess.ccw;
2703 tes_info->tess.point_mode |= tcs_info->tess.point_mode;
2704 }
2705
2706 static
2707 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT *ext)
2708 {
2709 if (!ext)
2710 return;
2711
2712 if (ext->pPipelineCreationFeedback) {
2713 ext->pPipelineCreationFeedback->flags = 0;
2714 ext->pPipelineCreationFeedback->duration = 0;
2715 }
2716
2717 for (unsigned i = 0; i < ext->pipelineStageCreationFeedbackCount; ++i) {
2718 ext->pPipelineStageCreationFeedbacks[i].flags = 0;
2719 ext->pPipelineStageCreationFeedbacks[i].duration = 0;
2720 }
2721 }
2722
2723 static
2724 void radv_start_feedback(VkPipelineCreationFeedbackEXT *feedback)
2725 {
2726 if (!feedback)
2727 return;
2728
2729 feedback->duration -= radv_get_current_time();
2730 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT;
2731 }
2732
2733 static
2734 void radv_stop_feedback(VkPipelineCreationFeedbackEXT *feedback, bool cache_hit)
2735 {
2736 if (!feedback)
2737 return;
2738
2739 feedback->duration += radv_get_current_time();
2740 feedback ->flags = VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT |
2741 (cache_hit ? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT : 0);
2742 }
2743
2744 void radv_create_shaders(struct radv_pipeline *pipeline,
2745 struct radv_device *device,
2746 struct radv_pipeline_cache *cache,
2747 const struct radv_pipeline_key *key,
2748 const VkPipelineShaderStageCreateInfo **pStages,
2749 const VkPipelineCreateFlags flags,
2750 VkPipelineCreationFeedbackEXT *pipeline_feedback,
2751 VkPipelineCreationFeedbackEXT **stage_feedbacks)
2752 {
2753 struct radv_shader_module fs_m = {0};
2754 struct radv_shader_module *modules[MESA_SHADER_STAGES] = { 0, };
2755 nir_shader *nir[MESA_SHADER_STAGES] = {0};
2756 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2757 struct radv_shader_variant_key keys[MESA_SHADER_STAGES] = {{{{{0}}}}};
2758 struct radv_shader_info infos[MESA_SHADER_STAGES] = {0};
2759 unsigned char hash[20], gs_copy_hash[20];
2760 bool keep_executable_info = (flags & VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR) || device->keep_shader_info;
2761
2762 radv_start_feedback(pipeline_feedback);
2763
2764 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2765 if (pStages[i]) {
2766 modules[i] = radv_shader_module_from_handle(pStages[i]->module);
2767 if (modules[i]->nir)
2768 _mesa_sha1_compute(modules[i]->nir->info.name,
2769 strlen(modules[i]->nir->info.name),
2770 modules[i]->sha1);
2771
2772 pipeline->active_stages |= mesa_to_vk_shader_stage(i);
2773 }
2774 }
2775
2776 radv_hash_shaders(hash, pStages, pipeline->layout, key, get_hash_flags(device));
2777 memcpy(gs_copy_hash, hash, 20);
2778 gs_copy_hash[0] ^= 1;
2779
2780 bool found_in_application_cache = true;
2781 if (modules[MESA_SHADER_GEOMETRY] && !keep_executable_info) {
2782 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2783 radv_create_shader_variants_from_pipeline_cache(device, cache, gs_copy_hash, variants,
2784 &found_in_application_cache);
2785 pipeline->gs_copy_shader = variants[MESA_SHADER_GEOMETRY];
2786 }
2787
2788 if (!keep_executable_info &&
2789 radv_create_shader_variants_from_pipeline_cache(device, cache, hash, pipeline->shaders,
2790 &found_in_application_cache) &&
2791 (!modules[MESA_SHADER_GEOMETRY] || pipeline->gs_copy_shader)) {
2792 radv_stop_feedback(pipeline_feedback, found_in_application_cache);
2793 return;
2794 }
2795
2796 if (!modules[MESA_SHADER_FRAGMENT] && !modules[MESA_SHADER_COMPUTE]) {
2797 nir_builder fs_b;
2798 nir_builder_init_simple_shader(&fs_b, NULL, MESA_SHADER_FRAGMENT, NULL);
2799 fs_b.shader->info.name = ralloc_strdup(fs_b.shader, "noop_fs");
2800 fs_m.nir = fs_b.shader;
2801 modules[MESA_SHADER_FRAGMENT] = &fs_m;
2802 }
2803
2804 for (unsigned i = 0; i < MESA_SHADER_STAGES; ++i) {
2805 const VkPipelineShaderStageCreateInfo *stage = pStages[i];
2806 unsigned subgroup_size = 64, ballot_bit_size = 64;
2807
2808 if (!modules[i])
2809 continue;
2810
2811 radv_start_feedback(stage_feedbacks[i]);
2812
2813 if (key->compute_subgroup_size) {
2814 /* Only compute shaders currently support requiring a
2815 * specific subgroup size.
2816 */
2817 assert(i == MESA_SHADER_COMPUTE);
2818 subgroup_size = key->compute_subgroup_size;
2819 ballot_bit_size = key->compute_subgroup_size;
2820 }
2821
2822 nir[i] = radv_shader_compile_to_nir(device, modules[i],
2823 stage ? stage->pName : "main", i,
2824 stage ? stage->pSpecializationInfo : NULL,
2825 flags, pipeline->layout,
2826 subgroup_size, ballot_bit_size);
2827
2828 /* We don't want to alter meta shaders IR directly so clone it
2829 * first.
2830 */
2831 if (nir[i]->info.name) {
2832 nir[i] = nir_shader_clone(NULL, nir[i]);
2833 }
2834
2835 radv_stop_feedback(stage_feedbacks[i], false);
2836 }
2837
2838 if (nir[MESA_SHADER_TESS_CTRL]) {
2839 nir_lower_patch_vertices(nir[MESA_SHADER_TESS_EVAL], nir[MESA_SHADER_TESS_CTRL]->info.tess.tcs_vertices_out, NULL);
2840 merge_tess_info(&nir[MESA_SHADER_TESS_EVAL]->info, &nir[MESA_SHADER_TESS_CTRL]->info);
2841 }
2842
2843 if (!(flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT))
2844 radv_link_shaders(pipeline, nir);
2845
2846 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2847 if (nir[i]) {
2848 /* do this again since information such as outputs_read can be out-of-date */
2849 nir_shader_gather_info(nir[i], nir_shader_get_entrypoint(nir[i]));
2850
2851 if (device->physical_device->use_aco) {
2852 NIR_PASS_V(nir[i], nir_lower_non_uniform_access,
2853 nir_lower_non_uniform_ubo_access |
2854 nir_lower_non_uniform_ssbo_access |
2855 nir_lower_non_uniform_texture_access |
2856 nir_lower_non_uniform_image_access);
2857 } else
2858 NIR_PASS_V(nir[i], nir_lower_bool_to_int32);
2859 }
2860 }
2861
2862 if (nir[MESA_SHADER_FRAGMENT])
2863 radv_lower_fs_io(nir[MESA_SHADER_FRAGMENT]);
2864
2865 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2866 if (radv_can_dump_shader(device, modules[i], false))
2867 nir_print_shader(nir[i], stderr);
2868 }
2869
2870 radv_fill_shader_keys(device, keys, key, nir);
2871
2872 radv_fill_shader_info(pipeline, pStages, keys, infos, nir);
2873
2874 if ((nir[MESA_SHADER_VERTEX] &&
2875 keys[MESA_SHADER_VERTEX].vs_common_out.as_ngg) ||
2876 (nir[MESA_SHADER_TESS_EVAL] &&
2877 keys[MESA_SHADER_TESS_EVAL].vs_common_out.as_ngg)) {
2878 struct gfx10_ngg_info *ngg_info;
2879
2880 if (nir[MESA_SHADER_GEOMETRY])
2881 ngg_info = &infos[MESA_SHADER_GEOMETRY].ngg_info;
2882 else if (nir[MESA_SHADER_TESS_CTRL])
2883 ngg_info = &infos[MESA_SHADER_TESS_EVAL].ngg_info;
2884 else
2885 ngg_info = &infos[MESA_SHADER_VERTEX].ngg_info;
2886
2887 gfx10_get_ngg_info(key, pipeline, nir, infos, ngg_info);
2888 } else if (nir[MESA_SHADER_GEOMETRY]) {
2889 struct gfx9_gs_info *gs_info =
2890 &infos[MESA_SHADER_GEOMETRY].gs_ring_info;
2891
2892 gfx9_get_gs_info(key, pipeline, nir, infos, gs_info);
2893 }
2894
2895 if(modules[MESA_SHADER_GEOMETRY]) {
2896 struct radv_shader_binary *gs_copy_binary = NULL;
2897 if (!pipeline->gs_copy_shader &&
2898 !radv_pipeline_has_ngg(pipeline)) {
2899 struct radv_shader_info info = {};
2900 struct radv_shader_variant_key key = {};
2901
2902 key.has_multiview_view_index =
2903 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index;
2904
2905 radv_nir_shader_info_pass(nir[MESA_SHADER_GEOMETRY],
2906 pipeline->layout, &key,
2907 &info);
2908 info.wave_size = 64; /* Wave32 not supported. */
2909 info.ballot_bit_size = 64;
2910
2911 pipeline->gs_copy_shader = radv_create_gs_copy_shader(
2912 device, nir[MESA_SHADER_GEOMETRY], &info,
2913 &gs_copy_binary, keep_executable_info,
2914 keys[MESA_SHADER_GEOMETRY].has_multiview_view_index);
2915 }
2916
2917 if (!keep_executable_info && pipeline->gs_copy_shader) {
2918 struct radv_shader_binary *binaries[MESA_SHADER_STAGES] = {NULL};
2919 struct radv_shader_variant *variants[MESA_SHADER_STAGES] = {0};
2920
2921 binaries[MESA_SHADER_GEOMETRY] = gs_copy_binary;
2922 variants[MESA_SHADER_GEOMETRY] = pipeline->gs_copy_shader;
2923
2924 radv_pipeline_cache_insert_shaders(device, cache,
2925 gs_copy_hash,
2926 variants,
2927 binaries);
2928 }
2929 free(gs_copy_binary);
2930 }
2931
2932 if (nir[MESA_SHADER_FRAGMENT]) {
2933 if (!pipeline->shaders[MESA_SHADER_FRAGMENT]) {
2934 radv_start_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT]);
2935
2936 pipeline->shaders[MESA_SHADER_FRAGMENT] =
2937 radv_shader_variant_compile(device, modules[MESA_SHADER_FRAGMENT], &nir[MESA_SHADER_FRAGMENT], 1,
2938 pipeline->layout, keys + MESA_SHADER_FRAGMENT,
2939 infos + MESA_SHADER_FRAGMENT,
2940 keep_executable_info,
2941 &binaries[MESA_SHADER_FRAGMENT]);
2942
2943 radv_stop_feedback(stage_feedbacks[MESA_SHADER_FRAGMENT], false);
2944 }
2945 }
2946
2947 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_TESS_CTRL]) {
2948 if (!pipeline->shaders[MESA_SHADER_TESS_CTRL]) {
2949 struct nir_shader *combined_nir[] = {nir[MESA_SHADER_VERTEX], nir[MESA_SHADER_TESS_CTRL]};
2950 struct radv_shader_variant_key key = keys[MESA_SHADER_TESS_CTRL];
2951 key.tcs.vs_key = keys[MESA_SHADER_VERTEX].vs;
2952
2953 radv_start_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL]);
2954
2955 pipeline->shaders[MESA_SHADER_TESS_CTRL] = radv_shader_variant_compile(device, modules[MESA_SHADER_TESS_CTRL], combined_nir, 2,
2956 pipeline->layout,
2957 &key, &infos[MESA_SHADER_TESS_CTRL], keep_executable_info,
2958 &binaries[MESA_SHADER_TESS_CTRL]);
2959
2960 radv_stop_feedback(stage_feedbacks[MESA_SHADER_TESS_CTRL], false);
2961 }
2962 modules[MESA_SHADER_VERTEX] = NULL;
2963 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2964 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2965 }
2966
2967 if (device->physical_device->rad_info.chip_class >= GFX9 && modules[MESA_SHADER_GEOMETRY]) {
2968 gl_shader_stage pre_stage = modules[MESA_SHADER_TESS_EVAL] ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
2969 if (!pipeline->shaders[MESA_SHADER_GEOMETRY]) {
2970 struct nir_shader *combined_nir[] = {nir[pre_stage], nir[MESA_SHADER_GEOMETRY]};
2971
2972 radv_start_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY]);
2973
2974 pipeline->shaders[MESA_SHADER_GEOMETRY] = radv_shader_variant_compile(device, modules[MESA_SHADER_GEOMETRY], combined_nir, 2,
2975 pipeline->layout,
2976 &keys[pre_stage], &infos[MESA_SHADER_GEOMETRY], keep_executable_info,
2977 &binaries[MESA_SHADER_GEOMETRY]);
2978
2979 radv_stop_feedback(stage_feedbacks[MESA_SHADER_GEOMETRY], false);
2980 }
2981 modules[pre_stage] = NULL;
2982 }
2983
2984 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
2985 if(modules[i] && !pipeline->shaders[i]) {
2986 if (i == MESA_SHADER_TESS_CTRL) {
2987 keys[MESA_SHADER_TESS_CTRL].tcs.num_inputs = util_last_bit64(pipeline->shaders[MESA_SHADER_VERTEX]->info.vs.ls_outputs_written);
2988 }
2989 if (i == MESA_SHADER_TESS_EVAL) {
2990 keys[MESA_SHADER_TESS_EVAL].tes.num_patches = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.num_patches;
2991 keys[MESA_SHADER_TESS_EVAL].tes.tcs_num_outputs = util_last_bit64(pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.tcs.outputs_written);
2992 }
2993
2994 radv_start_feedback(stage_feedbacks[i]);
2995
2996 pipeline->shaders[i] = radv_shader_variant_compile(device, modules[i], &nir[i], 1,
2997 pipeline->layout,
2998 keys + i, infos + i,keep_executable_info,
2999 &binaries[i]);
3000
3001 radv_stop_feedback(stage_feedbacks[i], false);
3002 }
3003 }
3004
3005 if (!keep_executable_info) {
3006 radv_pipeline_cache_insert_shaders(device, cache, hash, pipeline->shaders,
3007 binaries);
3008 }
3009
3010 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
3011 free(binaries[i]);
3012 if (nir[i]) {
3013 ralloc_free(nir[i]);
3014
3015 if (radv_can_dump_shader_stats(device, modules[i]))
3016 radv_shader_dump_stats(device,
3017 pipeline->shaders[i],
3018 i, stderr);
3019 }
3020 }
3021
3022 if (fs_m.nir)
3023 ralloc_free(fs_m.nir);
3024
3025 radv_stop_feedback(pipeline_feedback, false);
3026 }
3027
3028 static uint32_t
3029 radv_pipeline_stage_to_user_data_0(struct radv_pipeline *pipeline,
3030 gl_shader_stage stage, enum chip_class chip_class)
3031 {
3032 bool has_gs = radv_pipeline_has_gs(pipeline);
3033 bool has_tess = radv_pipeline_has_tess(pipeline);
3034 bool has_ngg = radv_pipeline_has_ngg(pipeline);
3035
3036 switch (stage) {
3037 case MESA_SHADER_FRAGMENT:
3038 return R_00B030_SPI_SHADER_USER_DATA_PS_0;
3039 case MESA_SHADER_VERTEX:
3040 if (has_tess) {
3041 if (chip_class >= GFX10) {
3042 return R_00B430_SPI_SHADER_USER_DATA_HS_0;
3043 } else if (chip_class == GFX9) {
3044 return R_00B430_SPI_SHADER_USER_DATA_LS_0;
3045 } else {
3046 return R_00B530_SPI_SHADER_USER_DATA_LS_0;
3047 }
3048
3049 }
3050
3051 if (has_gs) {
3052 if (chip_class >= GFX10) {
3053 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3054 } else {
3055 return R_00B330_SPI_SHADER_USER_DATA_ES_0;
3056 }
3057 }
3058
3059 if (has_ngg)
3060 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3061
3062 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
3063 case MESA_SHADER_GEOMETRY:
3064 return chip_class == GFX9 ? R_00B330_SPI_SHADER_USER_DATA_ES_0 :
3065 R_00B230_SPI_SHADER_USER_DATA_GS_0;
3066 case MESA_SHADER_COMPUTE:
3067 return R_00B900_COMPUTE_USER_DATA_0;
3068 case MESA_SHADER_TESS_CTRL:
3069 return chip_class == GFX9 ? R_00B430_SPI_SHADER_USER_DATA_LS_0 :
3070 R_00B430_SPI_SHADER_USER_DATA_HS_0;
3071 case MESA_SHADER_TESS_EVAL:
3072 if (has_gs) {
3073 return chip_class >= GFX10 ? R_00B230_SPI_SHADER_USER_DATA_GS_0 :
3074 R_00B330_SPI_SHADER_USER_DATA_ES_0;
3075 } else if (has_ngg) {
3076 return R_00B230_SPI_SHADER_USER_DATA_GS_0;
3077 } else {
3078 return R_00B130_SPI_SHADER_USER_DATA_VS_0;
3079 }
3080 default:
3081 unreachable("unknown shader");
3082 }
3083 }
3084
3085 struct radv_bin_size_entry {
3086 unsigned bpp;
3087 VkExtent2D extent;
3088 };
3089
3090 static VkExtent2D
3091 radv_gfx9_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3092 {
3093 static const struct radv_bin_size_entry color_size_table[][3][9] = {
3094 {
3095 /* One RB / SE */
3096 {
3097 /* One shader engine */
3098 { 0, {128, 128}},
3099 { 1, { 64, 128}},
3100 { 2, { 32, 128}},
3101 { 3, { 16, 128}},
3102 { 17, { 0, 0}},
3103 { UINT_MAX, { 0, 0}},
3104 },
3105 {
3106 /* Two shader engines */
3107 { 0, {128, 128}},
3108 { 2, { 64, 128}},
3109 { 3, { 32, 128}},
3110 { 5, { 16, 128}},
3111 { 17, { 0, 0}},
3112 { UINT_MAX, { 0, 0}},
3113 },
3114 {
3115 /* Four shader engines */
3116 { 0, {128, 128}},
3117 { 3, { 64, 128}},
3118 { 5, { 16, 128}},
3119 { 17, { 0, 0}},
3120 { UINT_MAX, { 0, 0}},
3121 },
3122 },
3123 {
3124 /* Two RB / SE */
3125 {
3126 /* One shader engine */
3127 { 0, {128, 128}},
3128 { 2, { 64, 128}},
3129 { 3, { 32, 128}},
3130 { 5, { 16, 128}},
3131 { 33, { 0, 0}},
3132 { UINT_MAX, { 0, 0}},
3133 },
3134 {
3135 /* Two shader engines */
3136 { 0, {128, 128}},
3137 { 3, { 64, 128}},
3138 { 5, { 32, 128}},
3139 { 9, { 16, 128}},
3140 { 33, { 0, 0}},
3141 { UINT_MAX, { 0, 0}},
3142 },
3143 {
3144 /* Four shader engines */
3145 { 0, {256, 256}},
3146 { 2, {128, 256}},
3147 { 3, {128, 128}},
3148 { 5, { 64, 128}},
3149 { 9, { 16, 128}},
3150 { 33, { 0, 0}},
3151 { UINT_MAX, { 0, 0}},
3152 },
3153 },
3154 {
3155 /* Four RB / SE */
3156 {
3157 /* One shader engine */
3158 { 0, {128, 256}},
3159 { 2, {128, 128}},
3160 { 3, { 64, 128}},
3161 { 5, { 32, 128}},
3162 { 9, { 16, 128}},
3163 { 33, { 0, 0}},
3164 { UINT_MAX, { 0, 0}},
3165 },
3166 {
3167 /* Two shader engines */
3168 { 0, {256, 256}},
3169 { 2, {128, 256}},
3170 { 3, {128, 128}},
3171 { 5, { 64, 128}},
3172 { 9, { 32, 128}},
3173 { 17, { 16, 128}},
3174 { 33, { 0, 0}},
3175 { UINT_MAX, { 0, 0}},
3176 },
3177 {
3178 /* Four shader engines */
3179 { 0, {256, 512}},
3180 { 2, {256, 256}},
3181 { 3, {128, 256}},
3182 { 5, {128, 128}},
3183 { 9, { 64, 128}},
3184 { 17, { 16, 128}},
3185 { 33, { 0, 0}},
3186 { UINT_MAX, { 0, 0}},
3187 },
3188 },
3189 };
3190 static const struct radv_bin_size_entry ds_size_table[][3][9] = {
3191 {
3192 // One RB / SE
3193 {
3194 // One shader engine
3195 { 0, {128, 256}},
3196 { 2, {128, 128}},
3197 { 4, { 64, 128}},
3198 { 7, { 32, 128}},
3199 { 13, { 16, 128}},
3200 { 49, { 0, 0}},
3201 { UINT_MAX, { 0, 0}},
3202 },
3203 {
3204 // Two shader engines
3205 { 0, {256, 256}},
3206 { 2, {128, 256}},
3207 { 4, {128, 128}},
3208 { 7, { 64, 128}},
3209 { 13, { 32, 128}},
3210 { 25, { 16, 128}},
3211 { 49, { 0, 0}},
3212 { UINT_MAX, { 0, 0}},
3213 },
3214 {
3215 // Four shader engines
3216 { 0, {256, 512}},
3217 { 2, {256, 256}},
3218 { 4, {128, 256}},
3219 { 7, {128, 128}},
3220 { 13, { 64, 128}},
3221 { 25, { 16, 128}},
3222 { 49, { 0, 0}},
3223 { UINT_MAX, { 0, 0}},
3224 },
3225 },
3226 {
3227 // Two RB / SE
3228 {
3229 // One shader engine
3230 { 0, {256, 256}},
3231 { 2, {128, 256}},
3232 { 4, {128, 128}},
3233 { 7, { 64, 128}},
3234 { 13, { 32, 128}},
3235 { 25, { 16, 128}},
3236 { 97, { 0, 0}},
3237 { UINT_MAX, { 0, 0}},
3238 },
3239 {
3240 // Two shader engines
3241 { 0, {256, 512}},
3242 { 2, {256, 256}},
3243 { 4, {128, 256}},
3244 { 7, {128, 128}},
3245 { 13, { 64, 128}},
3246 { 25, { 32, 128}},
3247 { 49, { 16, 128}},
3248 { 97, { 0, 0}},
3249 { UINT_MAX, { 0, 0}},
3250 },
3251 {
3252 // Four shader engines
3253 { 0, {512, 512}},
3254 { 2, {256, 512}},
3255 { 4, {256, 256}},
3256 { 7, {128, 256}},
3257 { 13, {128, 128}},
3258 { 25, { 64, 128}},
3259 { 49, { 16, 128}},
3260 { 97, { 0, 0}},
3261 { UINT_MAX, { 0, 0}},
3262 },
3263 },
3264 {
3265 // Four RB / SE
3266 {
3267 // One shader engine
3268 { 0, {256, 512}},
3269 { 2, {256, 256}},
3270 { 4, {128, 256}},
3271 { 7, {128, 128}},
3272 { 13, { 64, 128}},
3273 { 25, { 32, 128}},
3274 { 49, { 16, 128}},
3275 { UINT_MAX, { 0, 0}},
3276 },
3277 {
3278 // Two shader engines
3279 { 0, {512, 512}},
3280 { 2, {256, 512}},
3281 { 4, {256, 256}},
3282 { 7, {128, 256}},
3283 { 13, {128, 128}},
3284 { 25, { 64, 128}},
3285 { 49, { 32, 128}},
3286 { 97, { 16, 128}},
3287 { UINT_MAX, { 0, 0}},
3288 },
3289 {
3290 // Four shader engines
3291 { 0, {512, 512}},
3292 { 4, {256, 512}},
3293 { 7, {256, 256}},
3294 { 13, {128, 256}},
3295 { 25, {128, 128}},
3296 { 49, { 64, 128}},
3297 { 97, { 16, 128}},
3298 { UINT_MAX, { 0, 0}},
3299 },
3300 },
3301 };
3302
3303 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3304 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3305 VkExtent2D extent = {512, 512};
3306
3307 unsigned log_num_rb_per_se =
3308 util_logbase2_ceil(pipeline->device->physical_device->rad_info.num_render_backends /
3309 pipeline->device->physical_device->rad_info.max_se);
3310 unsigned log_num_se = util_logbase2_ceil(pipeline->device->physical_device->rad_info.max_se);
3311
3312 unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3313 unsigned ps_iter_samples = 1u << G_028804_PS_ITER_SAMPLES(pipeline->graphics.ms.db_eqaa);
3314 unsigned effective_samples = total_samples;
3315 unsigned color_bytes_per_pixel = 0;
3316
3317 const VkPipelineColorBlendStateCreateInfo *vkblend =
3318 radv_pipeline_get_color_blend_state(pCreateInfo);
3319 if (vkblend) {
3320 for (unsigned i = 0; i < subpass->color_count; i++) {
3321 if (!vkblend->pAttachments[i].colorWriteMask)
3322 continue;
3323
3324 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3325 continue;
3326
3327 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3328 color_bytes_per_pixel += vk_format_get_blocksize(format);
3329 }
3330
3331 /* MSAA images typically don't use all samples all the time. */
3332 if (effective_samples >= 2 && ps_iter_samples <= 1)
3333 effective_samples = 2;
3334 color_bytes_per_pixel *= effective_samples;
3335 }
3336
3337 const struct radv_bin_size_entry *color_entry = color_size_table[log_num_rb_per_se][log_num_se];
3338 while(color_entry[1].bpp <= color_bytes_per_pixel)
3339 ++color_entry;
3340
3341 extent = color_entry->extent;
3342
3343 if (subpass->depth_stencil_attachment) {
3344 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3345
3346 /* Coefficients taken from AMDVLK */
3347 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3348 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3349 unsigned ds_bytes_per_pixel = 4 * (depth_coeff + stencil_coeff) * total_samples;
3350
3351 const struct radv_bin_size_entry *ds_entry = ds_size_table[log_num_rb_per_se][log_num_se];
3352 while(ds_entry[1].bpp <= ds_bytes_per_pixel)
3353 ++ds_entry;
3354
3355 if (ds_entry->extent.width * ds_entry->extent.height < extent.width * extent.height)
3356 extent = ds_entry->extent;
3357 }
3358
3359 return extent;
3360 }
3361
3362 static VkExtent2D
3363 radv_gfx10_compute_bin_size(struct radv_pipeline *pipeline, const VkGraphicsPipelineCreateInfo *pCreateInfo)
3364 {
3365 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3366 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3367 VkExtent2D extent = {512, 512};
3368
3369 const unsigned db_tag_size = 64;
3370 const unsigned db_tag_count = 312;
3371 const unsigned color_tag_size = 1024;
3372 const unsigned color_tag_count = 31;
3373 const unsigned fmask_tag_size = 256;
3374 const unsigned fmask_tag_count = 44;
3375
3376 const unsigned rb_count = pipeline->device->physical_device->rad_info.num_render_backends;
3377 const unsigned pipe_count = MAX2(rb_count, pipeline->device->physical_device->rad_info.num_sdp_interfaces);
3378
3379 const unsigned db_tag_part = (db_tag_count * rb_count / pipe_count) * db_tag_size * pipe_count;
3380 const unsigned color_tag_part = (color_tag_count * rb_count / pipe_count) * color_tag_size * pipe_count;
3381 const unsigned fmask_tag_part = (fmask_tag_count * rb_count / pipe_count) * fmask_tag_size * pipe_count;
3382
3383 const unsigned total_samples = 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline->graphics.ms.pa_sc_aa_config);
3384 const unsigned samples_log = util_logbase2_ceil(total_samples);
3385
3386 unsigned color_bytes_per_pixel = 0;
3387 unsigned fmask_bytes_per_pixel = 0;
3388
3389 const VkPipelineColorBlendStateCreateInfo *vkblend =
3390 radv_pipeline_get_color_blend_state(pCreateInfo);
3391 if (vkblend) {
3392 for (unsigned i = 0; i < subpass->color_count; i++) {
3393 if (!vkblend->pAttachments[i].colorWriteMask)
3394 continue;
3395
3396 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3397 continue;
3398
3399 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3400 color_bytes_per_pixel += vk_format_get_blocksize(format);
3401
3402 if (total_samples > 1) {
3403 assert(samples_log <= 3);
3404 const unsigned fmask_array[] = {0, 1, 1, 4};
3405 fmask_bytes_per_pixel += fmask_array[samples_log];
3406 }
3407 }
3408
3409 color_bytes_per_pixel *= total_samples;
3410 }
3411 color_bytes_per_pixel = MAX2(color_bytes_per_pixel, 1);
3412
3413 const unsigned color_pixel_count_log = util_logbase2(color_tag_part / color_bytes_per_pixel);
3414 extent.width = 1ull << ((color_pixel_count_log + 1) / 2);
3415 extent.height = 1ull << (color_pixel_count_log / 2);
3416
3417 if (fmask_bytes_per_pixel) {
3418 const unsigned fmask_pixel_count_log = util_logbase2(fmask_tag_part / fmask_bytes_per_pixel);
3419
3420 const VkExtent2D fmask_extent = (VkExtent2D){
3421 .width = 1ull << ((fmask_pixel_count_log + 1) / 2),
3422 .height = 1ull << (color_pixel_count_log / 2)
3423 };
3424
3425 if (fmask_extent.width * fmask_extent.height < extent.width * extent.height)
3426 extent = fmask_extent;
3427 }
3428
3429 if (subpass->depth_stencil_attachment) {
3430 struct radv_render_pass_attachment *attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3431
3432 /* Coefficients taken from AMDVLK */
3433 unsigned depth_coeff = vk_format_is_depth(attachment->format) ? 5 : 0;
3434 unsigned stencil_coeff = vk_format_is_stencil(attachment->format) ? 1 : 0;
3435 unsigned db_bytes_per_pixel = (depth_coeff + stencil_coeff) * total_samples;
3436
3437 const unsigned db_pixel_count_log = util_logbase2(db_tag_part / db_bytes_per_pixel);
3438
3439 const VkExtent2D db_extent = (VkExtent2D){
3440 .width = 1ull << ((db_pixel_count_log + 1) / 2),
3441 .height = 1ull << (color_pixel_count_log / 2)
3442 };
3443
3444 if (db_extent.width * db_extent.height < extent.width * extent.height)
3445 extent = db_extent;
3446 }
3447
3448 extent.width = MAX2(extent.width, 128);
3449 extent.height = MAX2(extent.width, 64);
3450
3451 return extent;
3452 }
3453
3454 static void
3455 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf *ctx_cs,
3456 struct radv_pipeline *pipeline,
3457 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3458 {
3459 uint32_t pa_sc_binner_cntl_0 =
3460 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC) |
3461 S_028C44_DISABLE_START_OF_PRIM(1);
3462 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3463
3464 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3465 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3466 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3467 const VkPipelineColorBlendStateCreateInfo *vkblend =
3468 radv_pipeline_get_color_blend_state(pCreateInfo);
3469 unsigned min_bytes_per_pixel = 0;
3470
3471 if (vkblend) {
3472 for (unsigned i = 0; i < subpass->color_count; i++) {
3473 if (!vkblend->pAttachments[i].colorWriteMask)
3474 continue;
3475
3476 if (subpass->color_attachments[i].attachment == VK_ATTACHMENT_UNUSED)
3477 continue;
3478
3479 VkFormat format = pass->attachments[subpass->color_attachments[i].attachment].format;
3480 unsigned bytes = vk_format_get_blocksize(format);
3481 if (!min_bytes_per_pixel || bytes < min_bytes_per_pixel)
3482 min_bytes_per_pixel = bytes;
3483 }
3484 }
3485
3486 pa_sc_binner_cntl_0 =
3487 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC) |
3488 S_028C44_BIN_SIZE_X(0) |
3489 S_028C44_BIN_SIZE_Y(0) |
3490 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3491 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel <= 4 ? 2 : 1) | /* 128 or 64 */
3492 S_028C44_DISABLE_START_OF_PRIM(1);
3493 }
3494
3495 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3496 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3497 }
3498
3499 struct radv_binning_settings
3500 radv_get_binning_settings(const struct radv_physical_device *pdev)
3501 {
3502 struct radv_binning_settings settings;
3503 if (pdev->rad_info.has_dedicated_vram) {
3504 if (pdev->rad_info.num_render_backends > 4) {
3505 settings.context_states_per_bin = 1;
3506 settings.persistent_states_per_bin = 1;
3507 } else {
3508 settings.context_states_per_bin = 3;
3509 settings.persistent_states_per_bin = 8;
3510 }
3511 settings.fpovs_per_batch = 63;
3512 } else {
3513 /* The context states are affected by the scissor bug. */
3514 settings.context_states_per_bin = 6;
3515 /* 32 causes hangs for RAVEN. */
3516 settings.persistent_states_per_bin = 16;
3517 settings.fpovs_per_batch = 63;
3518 }
3519
3520 if (pdev->rad_info.has_gfx9_scissor_bug)
3521 settings.context_states_per_bin = 1;
3522
3523 return settings;
3524 }
3525
3526 static void
3527 radv_pipeline_generate_binning_state(struct radeon_cmdbuf *ctx_cs,
3528 struct radv_pipeline *pipeline,
3529 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3530 const struct radv_blend_state *blend)
3531 {
3532 if (pipeline->device->physical_device->rad_info.chip_class < GFX9)
3533 return;
3534
3535 VkExtent2D bin_size;
3536 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3537 bin_size = radv_gfx10_compute_bin_size(pipeline, pCreateInfo);
3538 } else if (pipeline->device->physical_device->rad_info.chip_class == GFX9) {
3539 bin_size = radv_gfx9_compute_bin_size(pipeline, pCreateInfo);
3540 } else
3541 unreachable("Unhandled generation for binning bin size calculation");
3542
3543 if (pipeline->device->pbb_allowed && bin_size.width && bin_size.height) {
3544 struct radv_binning_settings settings =
3545 radv_get_binning_settings(pipeline->device->physical_device);
3546
3547 bool disable_start_of_prim = true;
3548 uint32_t db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF);
3549
3550 const struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3551
3552 if (pipeline->device->dfsm_allowed && ps &&
3553 !ps->info.ps.can_discard &&
3554 !ps->info.ps.writes_memory &&
3555 blend->cb_target_enabled_4bit) {
3556 db_dfsm_control = S_028060_PUNCHOUT_MODE(V_028060_AUTO);
3557 disable_start_of_prim = (blend->blend_enable_4bit & blend->cb_target_enabled_4bit) != 0;
3558 }
3559
3560 const uint32_t pa_sc_binner_cntl_0 =
3561 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED) |
3562 S_028C44_BIN_SIZE_X(bin_size.width == 16) |
3563 S_028C44_BIN_SIZE_Y(bin_size.height == 16) |
3564 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size.width, 32)) - 5) |
3565 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size.height, 32)) - 5) |
3566 S_028C44_CONTEXT_STATES_PER_BIN(settings.context_states_per_bin - 1) |
3567 S_028C44_PERSISTENT_STATES_PER_BIN(settings.persistent_states_per_bin - 1) |
3568 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim) |
3569 S_028C44_FPOVS_PER_BATCH(settings.fpovs_per_batch) |
3570 S_028C44_OPTIMAL_BIN_SELECTION(1);
3571
3572 pipeline->graphics.binning.pa_sc_binner_cntl_0 = pa_sc_binner_cntl_0;
3573 pipeline->graphics.binning.db_dfsm_control = db_dfsm_control;
3574 } else
3575 radv_pipeline_generate_disabled_binning_state(ctx_cs, pipeline, pCreateInfo);
3576 }
3577
3578
3579 static void
3580 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf *ctx_cs,
3581 struct radv_pipeline *pipeline,
3582 const VkGraphicsPipelineCreateInfo *pCreateInfo,
3583 const struct radv_graphics_pipeline_create_info *extra)
3584 {
3585 const VkPipelineDepthStencilStateCreateInfo *vkds = radv_pipeline_get_depth_stencil_state(pCreateInfo);
3586 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
3587 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
3588 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
3589 struct radv_render_pass_attachment *attachment = NULL;
3590 uint32_t db_depth_control = 0, db_stencil_control = 0;
3591 uint32_t db_render_control = 0, db_render_override2 = 0;
3592 uint32_t db_render_override = 0;
3593
3594 if (subpass->depth_stencil_attachment)
3595 attachment = pass->attachments + subpass->depth_stencil_attachment->attachment;
3596
3597 bool has_depth_attachment = attachment && vk_format_is_depth(attachment->format);
3598 bool has_stencil_attachment = attachment && vk_format_is_stencil(attachment->format);
3599
3600 if (vkds && has_depth_attachment) {
3601 db_depth_control = S_028800_Z_ENABLE(vkds->depthTestEnable ? 1 : 0) |
3602 S_028800_Z_WRITE_ENABLE(vkds->depthWriteEnable ? 1 : 0) |
3603 S_028800_ZFUNC(vkds->depthCompareOp) |
3604 S_028800_DEPTH_BOUNDS_ENABLE(vkds->depthBoundsTestEnable ? 1 : 0);
3605
3606 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3607 db_render_override2 |= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment->samples > 2);
3608 }
3609
3610 if (has_stencil_attachment && vkds && vkds->stencilTestEnable) {
3611 db_depth_control |= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3612 db_depth_control |= S_028800_STENCILFUNC(vkds->front.compareOp);
3613 db_stencil_control |= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds->front.failOp));
3614 db_stencil_control |= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds->front.passOp));
3615 db_stencil_control |= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds->front.depthFailOp));
3616
3617 db_depth_control |= S_028800_STENCILFUNC_BF(vkds->back.compareOp);
3618 db_stencil_control |= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds->back.failOp));
3619 db_stencil_control |= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds->back.passOp));
3620 db_stencil_control |= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds->back.depthFailOp));
3621 }
3622
3623 if (attachment && extra) {
3624 db_render_control |= S_028000_DEPTH_CLEAR_ENABLE(extra->db_depth_clear);
3625 db_render_control |= S_028000_STENCIL_CLEAR_ENABLE(extra->db_stencil_clear);
3626
3627 db_render_control |= S_028000_RESUMMARIZE_ENABLE(extra->db_resummarize);
3628 db_render_control |= S_028000_DEPTH_COMPRESS_DISABLE(extra->db_flush_depth_inplace);
3629 db_render_control |= S_028000_STENCIL_COMPRESS_DISABLE(extra->db_flush_stencil_inplace);
3630 db_render_override2 |= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra->db_depth_disable_expclear);
3631 db_render_override2 |= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra->db_stencil_disable_expclear);
3632 }
3633
3634 db_render_override |= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE) |
3635 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE);
3636
3637 if (!pCreateInfo->pRasterizationState->depthClampEnable &&
3638 ps->info.ps.writes_z) {
3639 /* From VK_EXT_depth_range_unrestricted spec:
3640 *
3641 * "The behavior described in Primitive Clipping still applies.
3642 * If depth clamping is disabled the depth values are still
3643 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3644 * depth clamping is enabled the above equation is ignored and
3645 * the depth values are instead clamped to the VkViewport
3646 * minDepth and maxDepth values, which in the case of this
3647 * extension can be outside of the 0.0 to 1.0 range."
3648 */
3649 db_render_override |= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3650 }
3651
3652 radeon_set_context_reg(ctx_cs, R_028800_DB_DEPTH_CONTROL, db_depth_control);
3653 radeon_set_context_reg(ctx_cs, R_02842C_DB_STENCIL_CONTROL, db_stencil_control);
3654
3655 radeon_set_context_reg(ctx_cs, R_028000_DB_RENDER_CONTROL, db_render_control);
3656 radeon_set_context_reg(ctx_cs, R_02800C_DB_RENDER_OVERRIDE, db_render_override);
3657 radeon_set_context_reg(ctx_cs, R_028010_DB_RENDER_OVERRIDE2, db_render_override2);
3658 }
3659
3660 static void
3661 radv_pipeline_generate_blend_state(struct radeon_cmdbuf *ctx_cs,
3662 struct radv_pipeline *pipeline,
3663 const struct radv_blend_state *blend)
3664 {
3665 radeon_set_context_reg_seq(ctx_cs, R_028780_CB_BLEND0_CONTROL, 8);
3666 radeon_emit_array(ctx_cs, blend->cb_blend_control,
3667 8);
3668 radeon_set_context_reg(ctx_cs, R_028808_CB_COLOR_CONTROL, blend->cb_color_control);
3669 radeon_set_context_reg(ctx_cs, R_028B70_DB_ALPHA_TO_MASK, blend->db_alpha_to_mask);
3670
3671 if (pipeline->device->physical_device->rad_info.has_rbplus) {
3672
3673 radeon_set_context_reg_seq(ctx_cs, R_028760_SX_MRT0_BLEND_OPT, 8);
3674 radeon_emit_array(ctx_cs, blend->sx_mrt_blend_opt, 8);
3675 }
3676
3677 radeon_set_context_reg(ctx_cs, R_028714_SPI_SHADER_COL_FORMAT, blend->spi_shader_col_format);
3678
3679 radeon_set_context_reg(ctx_cs, R_028238_CB_TARGET_MASK, blend->cb_target_mask);
3680 radeon_set_context_reg(ctx_cs, R_02823C_CB_SHADER_MASK, blend->cb_shader_mask);
3681
3682 pipeline->graphics.col_format = blend->spi_shader_col_format;
3683 pipeline->graphics.cb_target_mask = blend->cb_target_mask;
3684 }
3685
3686 static const VkConservativeRasterizationModeEXT
3687 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo *pCreateInfo)
3688 {
3689 const VkPipelineRasterizationConservativeStateCreateInfoEXT *conservative_raster =
3690 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT);
3691
3692 if (!conservative_raster)
3693 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT;
3694 return conservative_raster->conservativeRasterizationMode;
3695 }
3696
3697 static void
3698 radv_pipeline_generate_raster_state(struct radeon_cmdbuf *ctx_cs,
3699 struct radv_pipeline *pipeline,
3700 const VkGraphicsPipelineCreateInfo *pCreateInfo)
3701 {
3702 const VkPipelineRasterizationStateCreateInfo *vkraster = pCreateInfo->pRasterizationState;
3703 const VkConservativeRasterizationModeEXT mode =
3704 radv_get_conservative_raster_mode(vkraster);
3705 uint32_t pa_sc_conservative_rast = S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3706 bool depth_clip_disable = vkraster->depthClampEnable;
3707
3708 const VkPipelineRasterizationDepthClipStateCreateInfoEXT *depth_clip_state =
3709 vk_find_struct_const(vkraster->pNext, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT);
3710 if (depth_clip_state) {
3711 depth_clip_disable = !depth_clip_state->depthClipEnable;
3712 }
3713
3714 radeon_set_context_reg(ctx_cs, R_028810_PA_CL_CLIP_CNTL,
3715 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3716 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable ? 1 : 0) |
3717 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable ? 1 : 0) |
3718 S_028810_DX_RASTERIZATION_KILL(vkraster->rasterizerDiscardEnable ? 1 : 0) |
3719 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3720
3721 radeon_set_context_reg(ctx_cs, R_0286D4_SPI_INTERP_CONTROL_0,
3722 S_0286D4_FLAT_SHADE_ENA(1) |
3723 S_0286D4_PNT_SPRITE_ENA(1) |
3724 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S) |
3725 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T) |
3726 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0) |
3727 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1) |
3728 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3729
3730 radeon_set_context_reg(ctx_cs, R_028BE4_PA_SU_VTX_CNTL,
3731 S_028BE4_PIX_CENTER(1) | // TODO verify
3732 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN) |
3733 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH));
3734
3735 radeon_set_context_reg(ctx_cs, R_028814_PA_SU_SC_MODE_CNTL,
3736 S_028814_FACE(vkraster->frontFace) |
3737 S_028814_CULL_FRONT(!!(vkraster->cullMode & VK_CULL_MODE_FRONT_BIT)) |
3738 S_028814_CULL_BACK(!!(vkraster->cullMode & VK_CULL_MODE_BACK_BIT)) |
3739 S_028814_POLY_MODE(vkraster->polygonMode != VK_POLYGON_MODE_FILL) |
3740 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3741 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster->polygonMode)) |
3742 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3743 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster->depthBiasEnable ? 1 : 0) |
3744 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster->depthBiasEnable ? 1 : 0));
3745
3746 /* Conservative rasterization. */
3747 if (mode != VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT) {
3748 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3749
3750 ms->pa_sc_aa_config |= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3751 ms->db_eqaa |= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3752 S_028804_OVERRASTERIZATION_AMOUNT(4);
3753
3754 pa_sc_conservative_rast = S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3755 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3756 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3757
3758 if (mode == VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT) {
3759 pa_sc_conservative_rast |=
3760 S_028C4C_OVER_RAST_ENABLE(1) |
3761 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3762 S_028C4C_UNDER_RAST_ENABLE(0) |
3763 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3764 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3765 } else {
3766 assert(mode == VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT);
3767 pa_sc_conservative_rast |=
3768 S_028C4C_OVER_RAST_ENABLE(0) |
3769 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3770 S_028C4C_UNDER_RAST_ENABLE(1) |
3771 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3772 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3773 }
3774 }
3775
3776 radeon_set_context_reg(ctx_cs, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL,
3777 pa_sc_conservative_rast);
3778 }
3779
3780
3781 static void
3782 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf *ctx_cs,
3783 struct radv_pipeline *pipeline)
3784 {
3785 struct radv_multisample_state *ms = &pipeline->graphics.ms;
3786
3787 radeon_set_context_reg_seq(ctx_cs, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0, 2);
3788 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[0]);
3789 radeon_emit(ctx_cs, ms->pa_sc_aa_mask[1]);
3790
3791 radeon_set_context_reg(ctx_cs, R_028804_DB_EQAA, ms->db_eqaa);
3792 radeon_set_context_reg(ctx_cs, R_028A48_PA_SC_MODE_CNTL_0, ms->pa_sc_mode_cntl_0);
3793 radeon_set_context_reg(ctx_cs, R_028A4C_PA_SC_MODE_CNTL_1, ms->pa_sc_mode_cntl_1);
3794 radeon_set_context_reg(ctx_cs, R_028BDC_PA_SC_LINE_CNTL, ms->pa_sc_line_cntl);
3795 radeon_set_context_reg(ctx_cs, R_028BE0_PA_SC_AA_CONFIG, ms->pa_sc_aa_config);
3796
3797 /* The exclusion bits can be set to improve rasterization efficiency
3798 * if no sample lies on the pixel boundary (-8 sample offset). It's
3799 * currently always TRUE because the driver doesn't support 16 samples.
3800 */
3801 bool exclusion = pipeline->device->physical_device->rad_info.chip_class >= GFX7;
3802 radeon_set_context_reg(ctx_cs, R_02882C_PA_SU_PRIM_FILTER_CNTL,
3803 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion) |
3804 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion));
3805
3806 /* GFX9: Flush DFSM when the AA mode changes. */
3807 if (pipeline->device->dfsm_allowed) {
3808 radeon_emit(ctx_cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
3809 radeon_emit(ctx_cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
3810 }
3811 }
3812
3813 static void
3814 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf *ctx_cs,
3815 struct radv_pipeline *pipeline)
3816 {
3817 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3818 const struct radv_shader_variant *vs =
3819 pipeline->shaders[MESA_SHADER_TESS_EVAL] ?
3820 pipeline->shaders[MESA_SHADER_TESS_EVAL] :
3821 pipeline->shaders[MESA_SHADER_VERTEX];
3822 unsigned vgt_primitiveid_en = 0;
3823 uint32_t vgt_gs_mode = 0;
3824
3825 if (radv_pipeline_has_ngg(pipeline))
3826 return;
3827
3828 if (radv_pipeline_has_gs(pipeline)) {
3829 const struct radv_shader_variant *gs =
3830 pipeline->shaders[MESA_SHADER_GEOMETRY];
3831
3832 vgt_gs_mode = ac_vgt_gs_mode(gs->info.gs.vertices_out,
3833 pipeline->device->physical_device->rad_info.chip_class);
3834 } else if (outinfo->export_prim_id || vs->info.uses_prim_id) {
3835 vgt_gs_mode = S_028A40_MODE(V_028A40_GS_SCENARIO_A);
3836 vgt_primitiveid_en |= S_028A84_PRIMITIVEID_EN(1);
3837 }
3838
3839 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN, vgt_primitiveid_en);
3840 radeon_set_context_reg(ctx_cs, R_028A40_VGT_GS_MODE, vgt_gs_mode);
3841 }
3842
3843 static void
3844 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf *ctx_cs,
3845 struct radeon_cmdbuf *cs,
3846 struct radv_pipeline *pipeline,
3847 struct radv_shader_variant *shader)
3848 {
3849 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3850
3851 radeon_set_sh_reg_seq(cs, R_00B120_SPI_SHADER_PGM_LO_VS, 4);
3852 radeon_emit(cs, va >> 8);
3853 radeon_emit(cs, S_00B124_MEM_BASE(va >> 40));
3854 radeon_emit(cs, shader->config.rsrc1);
3855 radeon_emit(cs, shader->config.rsrc2);
3856
3857 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3858 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3859 clip_dist_mask = outinfo->clip_dist_mask;
3860 cull_dist_mask = outinfo->cull_dist_mask;
3861 total_mask = clip_dist_mask | cull_dist_mask;
3862 bool misc_vec_ena = outinfo->writes_pointsize ||
3863 outinfo->writes_layer ||
3864 outinfo->writes_viewport_index;
3865 unsigned spi_vs_out_config, nparams;
3866
3867 /* VS is required to export at least one param. */
3868 nparams = MAX2(outinfo->param_exports, 1);
3869 spi_vs_out_config = S_0286C4_VS_EXPORT_COUNT(nparams - 1);
3870
3871 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
3872 spi_vs_out_config |= S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0);
3873 }
3874
3875 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG, spi_vs_out_config);
3876
3877 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3878 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3879 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
3880 V_02870C_SPI_SHADER_4COMP :
3881 V_02870C_SPI_SHADER_NONE) |
3882 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
3883 V_02870C_SPI_SHADER_4COMP :
3884 V_02870C_SPI_SHADER_NONE) |
3885 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
3886 V_02870C_SPI_SHADER_4COMP :
3887 V_02870C_SPI_SHADER_NONE));
3888
3889 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
3890 S_028818_VTX_W0_FMT(1) |
3891 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3892 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3893 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3894
3895 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
3896 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
3897 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
3898 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
3899 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
3900 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
3901 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
3902 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
3903 cull_dist_mask << 8 |
3904 clip_dist_mask);
3905
3906 if (pipeline->device->physical_device->rad_info.chip_class <= GFX8)
3907 radeon_set_context_reg(ctx_cs, R_028AB4_VGT_REUSE_OFF,
3908 outinfo->writes_viewport_index);
3909 }
3910
3911 static void
3912 radv_pipeline_generate_hw_es(struct radeon_cmdbuf *cs,
3913 struct radv_pipeline *pipeline,
3914 struct radv_shader_variant *shader)
3915 {
3916 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3917
3918 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 4);
3919 radeon_emit(cs, va >> 8);
3920 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3921 radeon_emit(cs, shader->config.rsrc1);
3922 radeon_emit(cs, shader->config.rsrc2);
3923 }
3924
3925 static void
3926 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf *cs,
3927 struct radv_pipeline *pipeline,
3928 struct radv_shader_variant *shader,
3929 const struct radv_tessellation_state *tess)
3930 {
3931 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3932 uint32_t rsrc2 = shader->config.rsrc2;
3933
3934 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
3935 radeon_emit(cs, va >> 8);
3936 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
3937
3938 rsrc2 |= S_00B52C_LDS_SIZE(tess->lds_size);
3939 if (pipeline->device->physical_device->rad_info.chip_class == GFX7 &&
3940 pipeline->device->physical_device->rad_info.family != CHIP_HAWAII)
3941 radeon_set_sh_reg(cs, R_00B52C_SPI_SHADER_PGM_RSRC2_LS, rsrc2);
3942
3943 radeon_set_sh_reg_seq(cs, R_00B528_SPI_SHADER_PGM_RSRC1_LS, 2);
3944 radeon_emit(cs, shader->config.rsrc1);
3945 radeon_emit(cs, rsrc2);
3946 }
3947
3948 static void
3949 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf *ctx_cs,
3950 struct radeon_cmdbuf *cs,
3951 struct radv_pipeline *pipeline,
3952 struct radv_shader_variant *shader)
3953 {
3954 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
3955 gl_shader_stage es_type =
3956 radv_pipeline_has_tess(pipeline) ? MESA_SHADER_TESS_EVAL : MESA_SHADER_VERTEX;
3957 struct radv_shader_variant *es =
3958 es_type == MESA_SHADER_TESS_EVAL ? pipeline->shaders[MESA_SHADER_TESS_EVAL] : pipeline->shaders[MESA_SHADER_VERTEX];
3959 const struct gfx10_ngg_info *ngg_state = &shader->info.ngg_info;
3960
3961 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
3962 radeon_emit(cs, va >> 8);
3963 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
3964 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
3965 radeon_emit(cs, shader->config.rsrc1);
3966 radeon_emit(cs, shader->config.rsrc2);
3967
3968 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
3969 unsigned clip_dist_mask, cull_dist_mask, total_mask;
3970 clip_dist_mask = outinfo->clip_dist_mask;
3971 cull_dist_mask = outinfo->cull_dist_mask;
3972 total_mask = clip_dist_mask | cull_dist_mask;
3973 bool misc_vec_ena = outinfo->writes_pointsize ||
3974 outinfo->writes_layer ||
3975 outinfo->writes_viewport_index;
3976 bool es_enable_prim_id = outinfo->export_prim_id ||
3977 (es && es->info.uses_prim_id);
3978 bool break_wave_at_eoi = false;
3979 unsigned ge_cntl;
3980 unsigned nparams;
3981
3982 if (es_type == MESA_SHADER_TESS_EVAL) {
3983 struct radv_shader_variant *gs =
3984 pipeline->shaders[MESA_SHADER_GEOMETRY];
3985
3986 if (es_enable_prim_id || (gs && gs->info.uses_prim_id))
3987 break_wave_at_eoi = true;
3988 }
3989
3990 nparams = MAX2(outinfo->param_exports, 1);
3991 radeon_set_context_reg(ctx_cs, R_0286C4_SPI_VS_OUT_CONFIG,
3992 S_0286C4_VS_EXPORT_COUNT(nparams - 1) |
3993 S_0286C4_NO_PC_EXPORT(outinfo->param_exports == 0));
3994
3995 radeon_set_context_reg(ctx_cs, R_028708_SPI_SHADER_IDX_FORMAT,
3996 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP));
3997 radeon_set_context_reg(ctx_cs, R_02870C_SPI_SHADER_POS_FORMAT,
3998 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP) |
3999 S_02870C_POS1_EXPORT_FORMAT(outinfo->pos_exports > 1 ?
4000 V_02870C_SPI_SHADER_4COMP :
4001 V_02870C_SPI_SHADER_NONE) |
4002 S_02870C_POS2_EXPORT_FORMAT(outinfo->pos_exports > 2 ?
4003 V_02870C_SPI_SHADER_4COMP :
4004 V_02870C_SPI_SHADER_NONE) |
4005 S_02870C_POS3_EXPORT_FORMAT(outinfo->pos_exports > 3 ?
4006 V_02870C_SPI_SHADER_4COMP :
4007 V_02870C_SPI_SHADER_NONE));
4008
4009 radeon_set_context_reg(ctx_cs, R_028818_PA_CL_VTE_CNTL,
4010 S_028818_VTX_W0_FMT(1) |
4011 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
4012 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
4013 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
4014 radeon_set_context_reg(ctx_cs, R_02881C_PA_CL_VS_OUT_CNTL,
4015 S_02881C_USE_VTX_POINT_SIZE(outinfo->writes_pointsize) |
4016 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo->writes_layer) |
4017 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo->writes_viewport_index) |
4018 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena) |
4019 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena) |
4020 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask & 0x0f) != 0) |
4021 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask & 0xf0) != 0) |
4022 cull_dist_mask << 8 |
4023 clip_dist_mask);
4024
4025 radeon_set_context_reg(ctx_cs, R_028A84_VGT_PRIMITIVEID_EN,
4026 S_028A84_PRIMITIVEID_EN(es_enable_prim_id) |
4027 S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo->export_prim_id));
4028
4029 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
4030 ngg_state->vgt_esgs_ring_itemsize);
4031
4032 /* NGG specific registers. */
4033 struct radv_shader_variant *gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
4034 uint32_t gs_num_invocations = gs ? gs->info.gs.invocations : 1;
4035
4036 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
4037 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state->hw_max_esverts) |
4038 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state->max_gsprims) |
4039 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state->max_gsprims * gs_num_invocations));
4040 radeon_set_context_reg(ctx_cs, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP,
4041 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state->max_out_verts));
4042 radeon_set_context_reg(ctx_cs, R_028B4C_GE_NGG_SUBGRP_CNTL,
4043 S_028B4C_PRIM_AMP_FACTOR(ngg_state->prim_amp_factor) |
4044 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
4045 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
4046 S_028B90_CNT(gs_num_invocations) |
4047 S_028B90_ENABLE(gs_num_invocations > 1) |
4048 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state->max_vert_out_per_gs_instance));
4049
4050 /* User edge flags are set by the pos exports. If user edge flags are
4051 * not used, we must use hw-generated edge flags and pass them via
4052 * the prim export to prevent drawing lines on internal edges of
4053 * decomposed primitives (such as quads) with polygon mode = lines.
4054 *
4055 * TODO: We should combine hw-generated edge flags with user edge
4056 * flags in the shader.
4057 */
4058 radeon_set_context_reg(ctx_cs, R_028838_PA_CL_NGG_CNTL,
4059 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline) &&
4060 !radv_pipeline_has_gs(pipeline)));
4061
4062 ge_cntl = S_03096C_PRIM_GRP_SIZE(ngg_state->max_gsprims) |
4063 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
4064 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi);
4065
4066 /* Bug workaround for a possible hang with non-tessellation cases.
4067 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
4068 *
4069 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
4070 */
4071 if ((pipeline->device->physical_device->rad_info.family == CHIP_NAVI10 ||
4072 pipeline->device->physical_device->rad_info.family == CHIP_NAVI12 ||
4073 pipeline->device->physical_device->rad_info.family == CHIP_NAVI14) &&
4074 !radv_pipeline_has_tess(pipeline) &&
4075 ngg_state->hw_max_esverts != 256) {
4076 ge_cntl &= C_03096C_VERT_GRP_SIZE;
4077
4078 if (ngg_state->hw_max_esverts > 5) {
4079 ge_cntl |= S_03096C_VERT_GRP_SIZE(ngg_state->hw_max_esverts - 5);
4080 }
4081 }
4082
4083 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL, ge_cntl);
4084 }
4085
4086 static void
4087 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf *cs,
4088 struct radv_pipeline *pipeline,
4089 struct radv_shader_variant *shader,
4090 const struct radv_tessellation_state *tess)
4091 {
4092 uint64_t va = radv_buffer_get_va(shader->bo) + shader->bo_offset;
4093
4094 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4095 unsigned hs_rsrc2 = shader->config.rsrc2;
4096
4097 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4098 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX10(tess->lds_size);
4099 } else {
4100 hs_rsrc2 |= S_00B42C_LDS_SIZE_GFX9(tess->lds_size);
4101 }
4102
4103 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4104 radeon_set_sh_reg_seq(cs, R_00B520_SPI_SHADER_PGM_LO_LS, 2);
4105 radeon_emit(cs, va >> 8);
4106 radeon_emit(cs, S_00B524_MEM_BASE(va >> 40));
4107 } else {
4108 radeon_set_sh_reg_seq(cs, R_00B410_SPI_SHADER_PGM_LO_LS, 2);
4109 radeon_emit(cs, va >> 8);
4110 radeon_emit(cs, S_00B414_MEM_BASE(va >> 40));
4111 }
4112
4113 radeon_set_sh_reg_seq(cs, R_00B428_SPI_SHADER_PGM_RSRC1_HS, 2);
4114 radeon_emit(cs, shader->config.rsrc1);
4115 radeon_emit(cs, hs_rsrc2);
4116 } else {
4117 radeon_set_sh_reg_seq(cs, R_00B420_SPI_SHADER_PGM_LO_HS, 4);
4118 radeon_emit(cs, va >> 8);
4119 radeon_emit(cs, S_00B424_MEM_BASE(va >> 40));
4120 radeon_emit(cs, shader->config.rsrc1);
4121 radeon_emit(cs, shader->config.rsrc2);
4122 }
4123 }
4124
4125 static void
4126 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf *ctx_cs,
4127 struct radeon_cmdbuf *cs,
4128 struct radv_pipeline *pipeline,
4129 const struct radv_tessellation_state *tess)
4130 {
4131 struct radv_shader_variant *vs;
4132
4133 /* Skip shaders merged into HS/GS */
4134 vs = pipeline->shaders[MESA_SHADER_VERTEX];
4135 if (!vs)
4136 return;
4137
4138 if (vs->info.vs.as_ls)
4139 radv_pipeline_generate_hw_ls(cs, pipeline, vs, tess);
4140 else if (vs->info.vs.as_es)
4141 radv_pipeline_generate_hw_es(cs, pipeline, vs);
4142 else if (vs->info.is_ngg)
4143 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, vs);
4144 else
4145 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, vs);
4146 }
4147
4148 static void
4149 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf *ctx_cs,
4150 struct radeon_cmdbuf *cs,
4151 struct radv_pipeline *pipeline,
4152 const struct radv_tessellation_state *tess)
4153 {
4154 if (!radv_pipeline_has_tess(pipeline))
4155 return;
4156
4157 struct radv_shader_variant *tes, *tcs;
4158
4159 tcs = pipeline->shaders[MESA_SHADER_TESS_CTRL];
4160 tes = pipeline->shaders[MESA_SHADER_TESS_EVAL];
4161
4162 if (tes) {
4163 if (tes->info.is_ngg) {
4164 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, tes);
4165 } else if (tes->info.tes.as_es)
4166 radv_pipeline_generate_hw_es(cs, pipeline, tes);
4167 else
4168 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, tes);
4169 }
4170
4171 radv_pipeline_generate_hw_hs(cs, pipeline, tcs, tess);
4172
4173 radeon_set_context_reg(ctx_cs, R_028B6C_VGT_TF_PARAM,
4174 tess->tf_param);
4175
4176 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7)
4177 radeon_set_context_reg_idx(ctx_cs, R_028B58_VGT_LS_HS_CONFIG, 2,
4178 tess->ls_hs_config);
4179 else
4180 radeon_set_context_reg(ctx_cs, R_028B58_VGT_LS_HS_CONFIG,
4181 tess->ls_hs_config);
4182
4183 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 &&
4184 !radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
4185 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL,
4186 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4187 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4188 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4189 }
4190 }
4191
4192 static void
4193 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf *ctx_cs,
4194 struct radeon_cmdbuf *cs,
4195 struct radv_pipeline *pipeline,
4196 struct radv_shader_variant *gs)
4197 {
4198 const struct gfx9_gs_info *gs_state = &gs->info.gs_ring_info;
4199 unsigned gs_max_out_vertices;
4200 uint8_t *num_components;
4201 uint8_t max_stream;
4202 unsigned offset;
4203 uint64_t va;
4204
4205 gs_max_out_vertices = gs->info.gs.vertices_out;
4206 max_stream = gs->info.gs.max_stream;
4207 num_components = gs->info.gs.num_stream_output_components;
4208
4209 offset = num_components[0] * gs_max_out_vertices;
4210
4211 radeon_set_context_reg_seq(ctx_cs, R_028A60_VGT_GSVS_RING_OFFSET_1, 3);
4212 radeon_emit(ctx_cs, offset);
4213 if (max_stream >= 1)
4214 offset += num_components[1] * gs_max_out_vertices;
4215 radeon_emit(ctx_cs, offset);
4216 if (max_stream >= 2)
4217 offset += num_components[2] * gs_max_out_vertices;
4218 radeon_emit(ctx_cs, offset);
4219 if (max_stream >= 3)
4220 offset += num_components[3] * gs_max_out_vertices;
4221 radeon_set_context_reg(ctx_cs, R_028AB0_VGT_GSVS_RING_ITEMSIZE, offset);
4222
4223 radeon_set_context_reg_seq(ctx_cs, R_028B5C_VGT_GS_VERT_ITEMSIZE, 4);
4224 radeon_emit(ctx_cs, num_components[0]);
4225 radeon_emit(ctx_cs, (max_stream >= 1) ? num_components[1] : 0);
4226 radeon_emit(ctx_cs, (max_stream >= 2) ? num_components[2] : 0);
4227 radeon_emit(ctx_cs, (max_stream >= 3) ? num_components[3] : 0);
4228
4229 uint32_t gs_num_invocations = gs->info.gs.invocations;
4230 radeon_set_context_reg(ctx_cs, R_028B90_VGT_GS_INSTANCE_CNT,
4231 S_028B90_CNT(MIN2(gs_num_invocations, 127)) |
4232 S_028B90_ENABLE(gs_num_invocations > 0));
4233
4234 radeon_set_context_reg(ctx_cs, R_028AAC_VGT_ESGS_RING_ITEMSIZE,
4235 gs_state->vgt_esgs_ring_itemsize);
4236
4237 va = radv_buffer_get_va(gs->bo) + gs->bo_offset;
4238
4239 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9) {
4240 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4241 radeon_set_sh_reg_seq(cs, R_00B320_SPI_SHADER_PGM_LO_ES, 2);
4242 radeon_emit(cs, va >> 8);
4243 radeon_emit(cs, S_00B324_MEM_BASE(va >> 40));
4244 } else {
4245 radeon_set_sh_reg_seq(cs, R_00B210_SPI_SHADER_PGM_LO_ES, 2);
4246 radeon_emit(cs, va >> 8);
4247 radeon_emit(cs, S_00B214_MEM_BASE(va >> 40));
4248 }
4249
4250 radeon_set_sh_reg_seq(cs, R_00B228_SPI_SHADER_PGM_RSRC1_GS, 2);
4251 radeon_emit(cs, gs->config.rsrc1);
4252 radeon_emit(cs, gs->config.rsrc2 | S_00B22C_LDS_SIZE(gs_state->lds_size));
4253
4254 radeon_set_context_reg(ctx_cs, R_028A44_VGT_GS_ONCHIP_CNTL, gs_state->vgt_gs_onchip_cntl);
4255 radeon_set_context_reg(ctx_cs, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP, gs_state->vgt_gs_max_prims_per_subgroup);
4256 } else {
4257 radeon_set_sh_reg_seq(cs, R_00B220_SPI_SHADER_PGM_LO_GS, 4);
4258 radeon_emit(cs, va >> 8);
4259 radeon_emit(cs, S_00B224_MEM_BASE(va >> 40));
4260 radeon_emit(cs, gs->config.rsrc1);
4261 radeon_emit(cs, gs->config.rsrc2);
4262 }
4263
4264 radv_pipeline_generate_hw_vs(ctx_cs, cs, pipeline, pipeline->gs_copy_shader);
4265 }
4266
4267 static void
4268 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf *ctx_cs,
4269 struct radeon_cmdbuf *cs,
4270 struct radv_pipeline *pipeline)
4271 {
4272 struct radv_shader_variant *gs;
4273
4274 gs = pipeline->shaders[MESA_SHADER_GEOMETRY];
4275 if (!gs)
4276 return;
4277
4278 if (gs->info.is_ngg)
4279 radv_pipeline_generate_hw_ngg(ctx_cs, cs, pipeline, gs);
4280 else
4281 radv_pipeline_generate_hw_gs(ctx_cs, cs, pipeline, gs);
4282
4283 radeon_set_context_reg(ctx_cs, R_028B38_VGT_GS_MAX_VERT_OUT,
4284 gs->info.gs.vertices_out);
4285 }
4286
4287 static uint32_t offset_to_ps_input(uint32_t offset, bool flat_shade,
4288 bool explicit, bool float16)
4289 {
4290 uint32_t ps_input_cntl;
4291 if (offset <= AC_EXP_PARAM_OFFSET_31) {
4292 ps_input_cntl = S_028644_OFFSET(offset);
4293 if (flat_shade || explicit)
4294 ps_input_cntl |= S_028644_FLAT_SHADE(1);
4295 if (explicit) {
4296 /* Force parameter cache to be read in passthrough
4297 * mode.
4298 */
4299 ps_input_cntl |= S_028644_OFFSET(1 << 5);
4300 }
4301 if (float16) {
4302 ps_input_cntl |= S_028644_FP16_INTERP_MODE(1) |
4303 S_028644_ATTR0_VALID(1);
4304 }
4305 } else {
4306 /* The input is a DEFAULT_VAL constant. */
4307 assert(offset >= AC_EXP_PARAM_DEFAULT_VAL_0000 &&
4308 offset <= AC_EXP_PARAM_DEFAULT_VAL_1111);
4309 offset -= AC_EXP_PARAM_DEFAULT_VAL_0000;
4310 ps_input_cntl = S_028644_OFFSET(0x20) |
4311 S_028644_DEFAULT_VAL(offset);
4312 }
4313 return ps_input_cntl;
4314 }
4315
4316 static void
4317 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf *ctx_cs,
4318 struct radv_pipeline *pipeline)
4319 {
4320 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4321 const struct radv_vs_output_info *outinfo = get_vs_output_info(pipeline);
4322 uint32_t ps_input_cntl[32];
4323
4324 unsigned ps_offset = 0;
4325
4326 if (ps->info.ps.prim_id_input) {
4327 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_PRIMITIVE_ID];
4328 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4329 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4330 ++ps_offset;
4331 }
4332 }
4333
4334 if (ps->info.ps.layer_input ||
4335 ps->info.needs_multiview_view_index) {
4336 unsigned vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_LAYER];
4337 if (vs_offset != AC_EXP_PARAM_UNDEFINED)
4338 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, true, false, false);
4339 else
4340 ps_input_cntl[ps_offset] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000, true, false, false);
4341 ++ps_offset;
4342 }
4343
4344 if (ps->info.ps.has_pcoord) {
4345 unsigned val;
4346 val = S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4347 ps_input_cntl[ps_offset] = val;
4348 ps_offset++;
4349 }
4350
4351 if (ps->info.ps.num_input_clips_culls) {
4352 unsigned vs_offset;
4353
4354 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST0];
4355 if (vs_offset != AC_EXP_PARAM_UNDEFINED) {
4356 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false, false);
4357 ++ps_offset;
4358 }
4359
4360 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_CLIP_DIST1];
4361 if (vs_offset != AC_EXP_PARAM_UNDEFINED &&
4362 ps->info.ps.num_input_clips_culls > 4) {
4363 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, false, false, false);
4364 ++ps_offset;
4365 }
4366 }
4367
4368 for (unsigned i = 0; i < 32 && (1u << i) <= ps->info.ps.input_mask; ++i) {
4369 unsigned vs_offset;
4370 bool flat_shade;
4371 bool explicit;
4372 bool float16;
4373 if (!(ps->info.ps.input_mask & (1u << i)))
4374 continue;
4375
4376 vs_offset = outinfo->vs_output_param_offset[VARYING_SLOT_VAR0 + i];
4377 if (vs_offset == AC_EXP_PARAM_UNDEFINED) {
4378 ps_input_cntl[ps_offset] = S_028644_OFFSET(0x20);
4379 ++ps_offset;
4380 continue;
4381 }
4382
4383 flat_shade = !!(ps->info.ps.flat_shaded_mask & (1u << ps_offset));
4384 explicit = !!(ps->info.ps.explicit_shaded_mask & (1u << ps_offset));
4385 float16 = !!(ps->info.ps.float16_shaded_mask & (1u << ps_offset));
4386
4387 ps_input_cntl[ps_offset] = offset_to_ps_input(vs_offset, flat_shade, explicit, float16);
4388 ++ps_offset;
4389 }
4390
4391 if (ps_offset) {
4392 radeon_set_context_reg_seq(ctx_cs, R_028644_SPI_PS_INPUT_CNTL_0, ps_offset);
4393 for (unsigned i = 0; i < ps_offset; i++) {
4394 radeon_emit(ctx_cs, ps_input_cntl[i]);
4395 }
4396 }
4397 }
4398
4399 static uint32_t
4400 radv_compute_db_shader_control(const struct radv_device *device,
4401 const struct radv_pipeline *pipeline,
4402 const struct radv_shader_variant *ps)
4403 {
4404 unsigned z_order;
4405 if (ps->info.ps.early_fragment_test || !ps->info.ps.writes_memory)
4406 z_order = V_02880C_EARLY_Z_THEN_LATE_Z;
4407 else
4408 z_order = V_02880C_LATE_Z;
4409
4410 bool disable_rbplus = device->physical_device->rad_info.has_rbplus &&
4411 !device->physical_device->rad_info.rbplus_allowed;
4412
4413 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4414 * but this appears to break Project Cars (DXVK). See
4415 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4416 */
4417 bool mask_export_enable = ps->info.ps.writes_sample_mask;
4418
4419 return S_02880C_Z_EXPORT_ENABLE(ps->info.ps.writes_z) |
4420 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps->info.ps.writes_stencil) |
4421 S_02880C_KILL_ENABLE(!!ps->info.ps.can_discard) |
4422 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable) |
4423 S_02880C_Z_ORDER(z_order) |
4424 S_02880C_DEPTH_BEFORE_SHADER(ps->info.ps.early_fragment_test) |
4425 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps->info.ps.post_depth_coverage) |
4426 S_02880C_EXEC_ON_HIER_FAIL(ps->info.ps.writes_memory) |
4427 S_02880C_EXEC_ON_NOOP(ps->info.ps.writes_memory) |
4428 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus);
4429 }
4430
4431 static void
4432 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf *ctx_cs,
4433 struct radeon_cmdbuf *cs,
4434 struct radv_pipeline *pipeline)
4435 {
4436 struct radv_shader_variant *ps;
4437 uint64_t va;
4438 assert (pipeline->shaders[MESA_SHADER_FRAGMENT]);
4439
4440 ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
4441 va = radv_buffer_get_va(ps->bo) + ps->bo_offset;
4442
4443 radeon_set_sh_reg_seq(cs, R_00B020_SPI_SHADER_PGM_LO_PS, 4);
4444 radeon_emit(cs, va >> 8);
4445 radeon_emit(cs, S_00B024_MEM_BASE(va >> 40));
4446 radeon_emit(cs, ps->config.rsrc1);
4447 radeon_emit(cs, ps->config.rsrc2);
4448
4449 radeon_set_context_reg(ctx_cs, R_02880C_DB_SHADER_CONTROL,
4450 radv_compute_db_shader_control(pipeline->device,
4451 pipeline, ps));
4452
4453 radeon_set_context_reg(ctx_cs, R_0286CC_SPI_PS_INPUT_ENA,
4454 ps->config.spi_ps_input_ena);
4455
4456 radeon_set_context_reg(ctx_cs, R_0286D0_SPI_PS_INPUT_ADDR,
4457 ps->config.spi_ps_input_addr);
4458
4459 radeon_set_context_reg(ctx_cs, R_0286D8_SPI_PS_IN_CONTROL,
4460 S_0286D8_NUM_INTERP(ps->info.ps.num_interp) |
4461 S_0286D8_PS_W32_EN(ps->info.wave_size == 32));
4462
4463 radeon_set_context_reg(ctx_cs, R_0286E0_SPI_BARYC_CNTL, pipeline->graphics.spi_baryc_cntl);
4464
4465 radeon_set_context_reg(ctx_cs, R_028710_SPI_SHADER_Z_FORMAT,
4466 ac_get_spi_shader_z_format(ps->info.ps.writes_z,
4467 ps->info.ps.writes_stencil,
4468 ps->info.ps.writes_sample_mask));
4469
4470 if (pipeline->device->dfsm_allowed) {
4471 /* optimise this? */
4472 radeon_emit(cs, PKT3(PKT3_EVENT_WRITE, 0, 0));
4473 radeon_emit(cs, EVENT_TYPE(V_028A90_FLUSH_DFSM) | EVENT_INDEX(0));
4474 }
4475 }
4476
4477 static void
4478 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf *ctx_cs,
4479 struct radv_pipeline *pipeline)
4480 {
4481 if (pipeline->device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4482 pipeline->device->physical_device->rad_info.chip_class >= GFX10)
4483 return;
4484
4485 unsigned vtx_reuse_depth = 30;
4486 if (radv_pipeline_has_tess(pipeline) &&
4487 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.tes.spacing == TESS_SPACING_FRACTIONAL_ODD) {
4488 vtx_reuse_depth = 14;
4489 }
4490 radeon_set_context_reg(ctx_cs, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL,
4491 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth));
4492 }
4493
4494 static uint32_t
4495 radv_compute_vgt_shader_stages_en(const struct radv_pipeline *pipeline)
4496 {
4497 uint32_t stages = 0;
4498 if (radv_pipeline_has_tess(pipeline)) {
4499 stages |= S_028B54_LS_EN(V_028B54_LS_STAGE_ON) |
4500 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4501
4502 if (radv_pipeline_has_gs(pipeline))
4503 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS) |
4504 S_028B54_GS_EN(1);
4505 else if (radv_pipeline_has_ngg(pipeline))
4506 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_DS);
4507 else
4508 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_DS);
4509 } else if (radv_pipeline_has_gs(pipeline)) {
4510 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL) |
4511 S_028B54_GS_EN(1);
4512 } else if (radv_pipeline_has_ngg(pipeline)) {
4513 stages |= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL);
4514 }
4515
4516 if (radv_pipeline_has_ngg(pipeline)) {
4517 stages |= S_028B54_PRIMGEN_EN(1);
4518 if (pipeline->streamout_shader)
4519 stages |= S_028B54_NGG_WAVE_ID_EN(1);
4520 if (radv_pipeline_has_ngg_passthrough(pipeline))
4521 stages |= S_028B54_PRIMGEN_PASSTHRU_EN(1);
4522 } else if (radv_pipeline_has_gs(pipeline)) {
4523 stages |= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER);
4524 }
4525
4526 if (pipeline->device->physical_device->rad_info.chip_class >= GFX9)
4527 stages |= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4528
4529 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10) {
4530 uint8_t hs_size = 64, gs_size = 64, vs_size = 64;
4531
4532 if (radv_pipeline_has_tess(pipeline))
4533 hs_size = pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.wave_size;
4534
4535 if (pipeline->shaders[MESA_SHADER_GEOMETRY]) {
4536 vs_size = gs_size = pipeline->shaders[MESA_SHADER_GEOMETRY]->info.wave_size;
4537 if (pipeline->gs_copy_shader)
4538 vs_size = pipeline->gs_copy_shader->info.wave_size;
4539 } else if (pipeline->shaders[MESA_SHADER_TESS_EVAL])
4540 vs_size = pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.wave_size;
4541 else if (pipeline->shaders[MESA_SHADER_VERTEX])
4542 vs_size = pipeline->shaders[MESA_SHADER_VERTEX]->info.wave_size;
4543
4544 if (radv_pipeline_has_ngg(pipeline))
4545 gs_size = vs_size;
4546
4547 /* legacy GS only supports Wave64 */
4548 stages |= S_028B54_HS_W32_EN(hs_size == 32 ? 1 : 0) |
4549 S_028B54_GS_W32_EN(gs_size == 32 ? 1 : 0) |
4550 S_028B54_VS_W32_EN(vs_size == 32 ? 1 : 0);
4551 }
4552
4553 return stages;
4554 }
4555
4556 static uint32_t
4557 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo *pCreateInfo)
4558 {
4559 const VkPipelineDiscardRectangleStateCreateInfoEXT *discard_rectangle_info =
4560 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT);
4561
4562 if (!discard_rectangle_info)
4563 return 0xffff;
4564
4565 unsigned mask = 0;
4566
4567 for (unsigned i = 0; i < (1u << MAX_DISCARD_RECTANGLES); ++i) {
4568 /* Interpret i as a bitmask, and then set the bit in the mask if
4569 * that combination of rectangles in which the pixel is contained
4570 * should pass the cliprect test. */
4571 unsigned relevant_subset = i & ((1u << discard_rectangle_info->discardRectangleCount) - 1);
4572
4573 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT &&
4574 !relevant_subset)
4575 continue;
4576
4577 if (discard_rectangle_info->discardRectangleMode == VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT &&
4578 relevant_subset)
4579 continue;
4580
4581 mask |= 1u << i;
4582 }
4583
4584 return mask;
4585 }
4586
4587 static void
4588 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf *ctx_cs,
4589 struct radv_pipeline *pipeline,
4590 const struct radv_tessellation_state *tess)
4591 {
4592 bool break_wave_at_eoi = false;
4593 unsigned primgroup_size;
4594 unsigned vertgroup_size = 256; /* 256 = disable vertex grouping */
4595
4596 if (radv_pipeline_has_tess(pipeline)) {
4597 primgroup_size = tess->num_patches; /* must be a multiple of NUM_PATCHES */
4598 } else if (radv_pipeline_has_gs(pipeline)) {
4599 const struct gfx9_gs_info *gs_state =
4600 &pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs_ring_info;
4601 unsigned vgt_gs_onchip_cntl = gs_state->vgt_gs_onchip_cntl;
4602 primgroup_size = G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl);
4603 } else {
4604 primgroup_size = 128; /* recommended without a GS and tess */
4605 }
4606
4607 if (radv_pipeline_has_tess(pipeline)) {
4608 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4609 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4610 break_wave_at_eoi = true;
4611 }
4612
4613 radeon_set_uconfig_reg(ctx_cs, R_03096C_GE_CNTL,
4614 S_03096C_PRIM_GRP_SIZE(primgroup_size) |
4615 S_03096C_VERT_GRP_SIZE(vertgroup_size) |
4616 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4617 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi));
4618 }
4619
4620 static void
4621 radv_pipeline_generate_pm4(struct radv_pipeline *pipeline,
4622 const VkGraphicsPipelineCreateInfo *pCreateInfo,
4623 const struct radv_graphics_pipeline_create_info *extra,
4624 const struct radv_blend_state *blend,
4625 const struct radv_tessellation_state *tess,
4626 unsigned prim, unsigned gs_out)
4627 {
4628 struct radeon_cmdbuf *ctx_cs = &pipeline->ctx_cs;
4629 struct radeon_cmdbuf *cs = &pipeline->cs;
4630
4631 cs->max_dw = 64;
4632 ctx_cs->max_dw = 256;
4633 cs->buf = malloc(4 * (cs->max_dw + ctx_cs->max_dw));
4634 ctx_cs->buf = cs->buf + cs->max_dw;
4635
4636 radv_pipeline_generate_depth_stencil_state(ctx_cs, pipeline, pCreateInfo, extra);
4637 radv_pipeline_generate_blend_state(ctx_cs, pipeline, blend);
4638 radv_pipeline_generate_raster_state(ctx_cs, pipeline, pCreateInfo);
4639 radv_pipeline_generate_multisample_state(ctx_cs, pipeline);
4640 radv_pipeline_generate_vgt_gs_mode(ctx_cs, pipeline);
4641 radv_pipeline_generate_vertex_shader(ctx_cs, cs, pipeline, tess);
4642 radv_pipeline_generate_tess_shaders(ctx_cs, cs, pipeline, tess);
4643 radv_pipeline_generate_geometry_shader(ctx_cs, cs, pipeline);
4644 radv_pipeline_generate_fragment_shader(ctx_cs, cs, pipeline);
4645 radv_pipeline_generate_ps_inputs(ctx_cs, pipeline);
4646 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs, pipeline);
4647 radv_pipeline_generate_binning_state(ctx_cs, pipeline, pCreateInfo, blend);
4648
4649 if (pipeline->device->physical_device->rad_info.chip_class >= GFX10 && !radv_pipeline_has_ngg(pipeline))
4650 gfx10_pipeline_generate_ge_cntl(ctx_cs, pipeline, tess);
4651
4652 radeon_set_context_reg(ctx_cs, R_028B54_VGT_SHADER_STAGES_EN, radv_compute_vgt_shader_stages_en(pipeline));
4653
4654 if (pipeline->device->physical_device->rad_info.chip_class >= GFX7) {
4655 radeon_set_uconfig_reg_idx(pipeline->device->physical_device,
4656 cs, R_030908_VGT_PRIMITIVE_TYPE, 1, prim);
4657 } else {
4658 radeon_set_config_reg(cs, R_008958_VGT_PRIMITIVE_TYPE, prim);
4659 }
4660 radeon_set_context_reg(ctx_cs, R_028A6C_VGT_GS_OUT_PRIM_TYPE, gs_out);
4661
4662 radeon_set_context_reg(ctx_cs, R_02820C_PA_SC_CLIPRECT_RULE, radv_compute_cliprect_rule(pCreateInfo));
4663
4664 pipeline->ctx_cs_hash = _mesa_hash_data(ctx_cs->buf, ctx_cs->cdw * 4);
4665
4666 assert(ctx_cs->cdw <= ctx_cs->max_dw);
4667 assert(cs->cdw <= cs->max_dw);
4668 }
4669
4670 static struct radv_ia_multi_vgt_param_helpers
4671 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline *pipeline,
4672 const struct radv_tessellation_state *tess,
4673 uint32_t prim)
4674 {
4675 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param = {0};
4676 const struct radv_device *device = pipeline->device;
4677
4678 if (radv_pipeline_has_tess(pipeline))
4679 ia_multi_vgt_param.primgroup_size = tess->num_patches;
4680 else if (radv_pipeline_has_gs(pipeline))
4681 ia_multi_vgt_param.primgroup_size = 64;
4682 else
4683 ia_multi_vgt_param.primgroup_size = 128; /* recommended without a GS */
4684
4685 /* GS requirement. */
4686 ia_multi_vgt_param.partial_es_wave = false;
4687 if (radv_pipeline_has_gs(pipeline) && device->physical_device->rad_info.chip_class <= GFX8)
4688 if (SI_GS_PER_ES / ia_multi_vgt_param.primgroup_size >= pipeline->device->gs_table_depth - 3)
4689 ia_multi_vgt_param.partial_es_wave = true;
4690
4691 ia_multi_vgt_param.wd_switch_on_eop = false;
4692 if (device->physical_device->rad_info.chip_class >= GFX7) {
4693 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
4694 * 4 shader engines. Set 1 to pass the assertion below.
4695 * The other cases are hardware requirements. */
4696 if (device->physical_device->rad_info.max_se < 4 ||
4697 prim == V_008958_DI_PT_POLYGON ||
4698 prim == V_008958_DI_PT_LINELOOP ||
4699 prim == V_008958_DI_PT_TRIFAN ||
4700 prim == V_008958_DI_PT_TRISTRIP_ADJ ||
4701 (pipeline->graphics.prim_restart_enable &&
4702 (device->physical_device->rad_info.family < CHIP_POLARIS10 ||
4703 (prim != V_008958_DI_PT_POINTLIST &&
4704 prim != V_008958_DI_PT_LINESTRIP))))
4705 ia_multi_vgt_param.wd_switch_on_eop = true;
4706 }
4707
4708 ia_multi_vgt_param.ia_switch_on_eoi = false;
4709 if (pipeline->shaders[MESA_SHADER_FRAGMENT]->info.ps.prim_id_input)
4710 ia_multi_vgt_param.ia_switch_on_eoi = true;
4711 if (radv_pipeline_has_gs(pipeline) &&
4712 pipeline->shaders[MESA_SHADER_GEOMETRY]->info.uses_prim_id)
4713 ia_multi_vgt_param.ia_switch_on_eoi = true;
4714 if (radv_pipeline_has_tess(pipeline)) {
4715 /* SWITCH_ON_EOI must be set if PrimID is used. */
4716 if (pipeline->shaders[MESA_SHADER_TESS_CTRL]->info.uses_prim_id ||
4717 radv_get_shader(pipeline, MESA_SHADER_TESS_EVAL)->info.uses_prim_id)
4718 ia_multi_vgt_param.ia_switch_on_eoi = true;
4719 }
4720
4721 ia_multi_vgt_param.partial_vs_wave = false;
4722 if (radv_pipeline_has_tess(pipeline)) {
4723 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4724 if ((device->physical_device->rad_info.family == CHIP_TAHITI ||
4725 device->physical_device->rad_info.family == CHIP_PITCAIRN ||
4726 device->physical_device->rad_info.family == CHIP_BONAIRE) &&
4727 radv_pipeline_has_gs(pipeline))
4728 ia_multi_vgt_param.partial_vs_wave = true;
4729 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4730 if (device->physical_device->rad_info.has_distributed_tess) {
4731 if (radv_pipeline_has_gs(pipeline)) {
4732 if (device->physical_device->rad_info.chip_class <= GFX8)
4733 ia_multi_vgt_param.partial_es_wave = true;
4734 } else {
4735 ia_multi_vgt_param.partial_vs_wave = true;
4736 }
4737 }
4738 }
4739
4740 /* Workaround for a VGT hang when strip primitive types are used with
4741 * primitive restart.
4742 */
4743 if (pipeline->graphics.prim_restart_enable &&
4744 (prim == V_008958_DI_PT_LINESTRIP ||
4745 prim == V_008958_DI_PT_TRISTRIP ||
4746 prim == V_008958_DI_PT_LINESTRIP_ADJ ||
4747 prim == V_008958_DI_PT_TRISTRIP_ADJ)) {
4748 ia_multi_vgt_param.partial_vs_wave = true;
4749 }
4750
4751 if (radv_pipeline_has_gs(pipeline)) {
4752 /* On these chips there is the possibility of a hang if the
4753 * pipeline uses a GS and partial_vs_wave is not set.
4754 *
4755 * This mostly does not hit 4-SE chips, as those typically set
4756 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4757 * with GS due to another workaround.
4758 *
4759 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4760 */
4761 if (device->physical_device->rad_info.family == CHIP_TONGA ||
4762 device->physical_device->rad_info.family == CHIP_FIJI ||
4763 device->physical_device->rad_info.family == CHIP_POLARIS10 ||
4764 device->physical_device->rad_info.family == CHIP_POLARIS11 ||
4765 device->physical_device->rad_info.family == CHIP_POLARIS12 ||
4766 device->physical_device->rad_info.family == CHIP_VEGAM) {
4767 ia_multi_vgt_param.partial_vs_wave = true;
4768 }
4769 }
4770
4771 ia_multi_vgt_param.base =
4772 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param.primgroup_size - 1) |
4773 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4774 S_028AA8_MAX_PRIMGRP_IN_WAVE(device->physical_device->rad_info.chip_class == GFX8 ? 2 : 0) |
4775 S_030960_EN_INST_OPT_BASIC(device->physical_device->rad_info.chip_class >= GFX9) |
4776 S_030960_EN_INST_OPT_ADV(device->physical_device->rad_info.chip_class >= GFX9);
4777
4778 return ia_multi_vgt_param;
4779 }
4780
4781
4782 static void
4783 radv_compute_vertex_input_state(struct radv_pipeline *pipeline,
4784 const VkGraphicsPipelineCreateInfo *pCreateInfo)
4785 {
4786 const VkPipelineVertexInputStateCreateInfo *vi_info =
4787 pCreateInfo->pVertexInputState;
4788 struct radv_vertex_elements_info *velems = &pipeline->vertex_elements;
4789
4790 for (uint32_t i = 0; i < vi_info->vertexAttributeDescriptionCount; i++) {
4791 const VkVertexInputAttributeDescription *desc =
4792 &vi_info->pVertexAttributeDescriptions[i];
4793 unsigned loc = desc->location;
4794 const struct vk_format_description *format_desc;
4795
4796 format_desc = vk_format_description(desc->format);
4797
4798 velems->format_size[loc] = format_desc->block.bits / 8;
4799 }
4800
4801 for (uint32_t i = 0; i < vi_info->vertexBindingDescriptionCount; i++) {
4802 const VkVertexInputBindingDescription *desc =
4803 &vi_info->pVertexBindingDescriptions[i];
4804
4805 pipeline->binding_stride[desc->binding] = desc->stride;
4806 pipeline->num_vertex_bindings =
4807 MAX2(pipeline->num_vertex_bindings, desc->binding + 1);
4808 }
4809 }
4810
4811 static struct radv_shader_variant *
4812 radv_pipeline_get_streamout_shader(struct radv_pipeline *pipeline)
4813 {
4814 int i;
4815
4816 for (i = MESA_SHADER_GEOMETRY; i >= MESA_SHADER_VERTEX; i--) {
4817 struct radv_shader_variant *shader =
4818 radv_get_shader(pipeline, i);
4819
4820 if (shader && shader->info.so.num_outputs > 0)
4821 return shader;
4822 }
4823
4824 return NULL;
4825 }
4826
4827 static VkResult
4828 radv_secure_compile(struct radv_pipeline *pipeline,
4829 struct radv_device *device,
4830 const struct radv_pipeline_key *key,
4831 const VkPipelineShaderStageCreateInfo **pStages,
4832 const VkPipelineCreateFlags flags,
4833 unsigned num_stages)
4834 {
4835 uint8_t allowed_pipeline_hashes[2][20];
4836 radv_hash_shaders(allowed_pipeline_hashes[0], pStages,
4837 pipeline->layout, key, get_hash_flags(device));
4838
4839 /* Generate the GC copy hash */
4840 memcpy(allowed_pipeline_hashes[1], allowed_pipeline_hashes[0], 20);
4841 allowed_pipeline_hashes[1][0] ^= 1;
4842
4843 uint8_t allowed_hashes[2][20];
4844 for (unsigned i = 0; i < 2; ++i) {
4845 disk_cache_compute_key(device->physical_device->disk_cache,
4846 allowed_pipeline_hashes[i], 20,
4847 allowed_hashes[i]);
4848 }
4849
4850 /* Do an early exit if all cache entries are already there. */
4851 bool may_need_copy_shader = pStages[MESA_SHADER_GEOMETRY];
4852 void *main_entry = disk_cache_get(device->physical_device->disk_cache, allowed_hashes[0], NULL);
4853 void *copy_entry = NULL;
4854 if (may_need_copy_shader)
4855 copy_entry = disk_cache_get(device->physical_device->disk_cache, allowed_hashes[1], NULL);
4856
4857 bool has_all_cache_entries = main_entry && (!may_need_copy_shader || copy_entry);
4858 free(main_entry);
4859 free(copy_entry);
4860
4861 if(has_all_cache_entries)
4862 return VK_SUCCESS;
4863
4864 unsigned process = 0;
4865 uint8_t sc_threads = device->instance->num_sc_threads;
4866 while (true) {
4867 mtx_lock(&device->sc_state->secure_compile_mutex);
4868 if (device->sc_state->secure_compile_thread_counter < sc_threads) {
4869 device->sc_state->secure_compile_thread_counter++;
4870 for (unsigned i = 0; i < sc_threads; i++) {
4871 if (!device->sc_state->secure_compile_processes[i].in_use) {
4872 device->sc_state->secure_compile_processes[i].in_use = true;
4873 process = i;
4874 break;
4875 }
4876 }
4877 mtx_unlock(&device->sc_state->secure_compile_mutex);
4878 break;
4879 }
4880 mtx_unlock(&device->sc_state->secure_compile_mutex);
4881 }
4882
4883 int fd_secure_input = device->sc_state->secure_compile_processes[process].fd_secure_input;
4884 int fd_secure_output = device->sc_state->secure_compile_processes[process].fd_secure_output;
4885
4886 /* Fork a copy of the slim untainted secure compile process */
4887 enum radv_secure_compile_type sc_type = RADV_SC_TYPE_FORK_DEVICE;
4888 write(fd_secure_input, &sc_type, sizeof(sc_type));
4889
4890 if (!radv_sc_read(fd_secure_output, &sc_type, sizeof(sc_type), true) ||
4891 sc_type != RADV_SC_TYPE_INIT_SUCCESS)
4892 return VK_ERROR_DEVICE_LOST;
4893
4894 fd_secure_input = device->sc_state->secure_compile_processes[process].fd_server;
4895 fd_secure_output = device->sc_state->secure_compile_processes[process].fd_client;
4896
4897 /* Write pipeline / shader module out to secure process via pipe */
4898 sc_type = RADV_SC_TYPE_COMPILE_PIPELINE;
4899 write(fd_secure_input, &sc_type, sizeof(sc_type));
4900
4901 /* Write pipeline layout out to secure process */
4902 struct radv_pipeline_layout *layout = pipeline->layout;
4903 write(fd_secure_input, layout, sizeof(struct radv_pipeline_layout));
4904 write(fd_secure_input, &layout->num_sets, sizeof(uint32_t));
4905 for (uint32_t set = 0; set < layout->num_sets; set++) {
4906 write(fd_secure_input, &layout->set[set].layout->layout_size, sizeof(uint32_t));
4907 write(fd_secure_input, layout->set[set].layout, layout->set[set].layout->layout_size);
4908 }
4909
4910 /* Write pipeline key out to secure process */
4911 write(fd_secure_input, key, sizeof(struct radv_pipeline_key));
4912
4913 /* Write pipeline create flags out to secure process */
4914 write(fd_secure_input, &flags, sizeof(VkPipelineCreateFlags));
4915
4916 /* Write stage and shader information out to secure process */
4917 write(fd_secure_input, &num_stages, sizeof(uint32_t));
4918 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++) {
4919 if (!pStages[i])
4920 continue;
4921
4922 /* Write stage out to secure process */
4923 gl_shader_stage stage = ffs(pStages[i]->stage) - 1;
4924 write(fd_secure_input, &stage, sizeof(gl_shader_stage));
4925
4926 /* Write entry point name out to secure process */
4927 size_t name_size = strlen(pStages[i]->pName) + 1;
4928 write(fd_secure_input, &name_size, sizeof(size_t));
4929 write(fd_secure_input, pStages[i]->pName, name_size);
4930
4931 /* Write shader module out to secure process */
4932 struct radv_shader_module *module = radv_shader_module_from_handle(pStages[i]->module);
4933 assert(!module->nir);
4934 size_t module_size = sizeof(struct radv_shader_module) + module->size;
4935 write(fd_secure_input, &module_size, sizeof(size_t));
4936 write(fd_secure_input, module, module_size);
4937
4938 /* Write specialization info out to secure process */
4939 const VkSpecializationInfo *specInfo = pStages[i]->pSpecializationInfo;
4940 bool has_spec_info = specInfo ? true : false;
4941 write(fd_secure_input, &has_spec_info, sizeof(bool));
4942 if (specInfo) {
4943 write(fd_secure_input, &specInfo->dataSize, sizeof(size_t));
4944 write(fd_secure_input, specInfo->pData, specInfo->dataSize);
4945
4946 write(fd_secure_input, &specInfo->mapEntryCount, sizeof(uint32_t));
4947 for (uint32_t j = 0; j < specInfo->mapEntryCount; j++)
4948 write(fd_secure_input, &specInfo->pMapEntries[j], sizeof(VkSpecializationMapEntry));
4949 }
4950 }
4951
4952 /* Read the data returned from the secure process */
4953 while (sc_type != RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED) {
4954 if (!radv_sc_read(fd_secure_output, &sc_type, sizeof(sc_type), true))
4955 return VK_ERROR_DEVICE_LOST;
4956
4957 if (sc_type == RADV_SC_TYPE_WRITE_DISK_CACHE) {
4958 assert(device->physical_device->disk_cache);
4959
4960 uint8_t disk_sha1[20];
4961 if (!radv_sc_read(fd_secure_output, disk_sha1, sizeof(uint8_t) * 20, true))
4962 return VK_ERROR_DEVICE_LOST;
4963
4964 if (memcmp(disk_sha1, allowed_hashes[0], 20) &&
4965 memcmp(disk_sha1, allowed_hashes[1], 20))
4966 return VK_ERROR_DEVICE_LOST;
4967
4968 uint32_t entry_size;
4969 if (!radv_sc_read(fd_secure_output, &entry_size, sizeof(uint32_t), true))
4970 return VK_ERROR_DEVICE_LOST;
4971
4972 struct cache_entry *entry = malloc(entry_size);
4973 if (!radv_sc_read(fd_secure_output, entry, entry_size, true))
4974 return VK_ERROR_DEVICE_LOST;
4975
4976 disk_cache_put(device->physical_device->disk_cache,
4977 disk_sha1, entry, entry_size,
4978 NULL);
4979
4980 free(entry);
4981 } else if (sc_type == RADV_SC_TYPE_READ_DISK_CACHE) {
4982 uint8_t disk_sha1[20];
4983 if (!radv_sc_read(fd_secure_output, disk_sha1, sizeof(uint8_t) * 20, true))
4984 return VK_ERROR_DEVICE_LOST;
4985
4986 if (memcmp(disk_sha1, allowed_hashes[0], 20) &&
4987 memcmp(disk_sha1, allowed_hashes[1], 20))
4988 return VK_ERROR_DEVICE_LOST;
4989
4990 size_t size;
4991 struct cache_entry *entry = (struct cache_entry *)
4992 disk_cache_get(device->physical_device->disk_cache,
4993 disk_sha1, &size);
4994
4995 uint8_t found = entry ? 1 : 0;
4996 write(fd_secure_input, &found, sizeof(uint8_t));
4997
4998 if (found) {
4999 write(fd_secure_input, &size, sizeof(size_t));
5000 write(fd_secure_input, entry, size);
5001 }
5002
5003 free(entry);
5004 }
5005 }
5006
5007 sc_type = RADV_SC_TYPE_DESTROY_DEVICE;
5008 write(fd_secure_input, &sc_type, sizeof(sc_type));
5009
5010 mtx_lock(&device->sc_state->secure_compile_mutex);
5011 device->sc_state->secure_compile_thread_counter--;
5012 device->sc_state->secure_compile_processes[process].in_use = false;
5013 mtx_unlock(&device->sc_state->secure_compile_mutex);
5014
5015 return VK_SUCCESS;
5016 }
5017
5018 static VkResult
5019 radv_pipeline_init(struct radv_pipeline *pipeline,
5020 struct radv_device *device,
5021 struct radv_pipeline_cache *cache,
5022 const VkGraphicsPipelineCreateInfo *pCreateInfo,
5023 const struct radv_graphics_pipeline_create_info *extra)
5024 {
5025 VkResult result;
5026 bool has_view_index = false;
5027
5028 RADV_FROM_HANDLE(radv_render_pass, pass, pCreateInfo->renderPass);
5029 struct radv_subpass *subpass = pass->subpasses + pCreateInfo->subpass;
5030 if (subpass->view_mask)
5031 has_view_index = true;
5032
5033 pipeline->device = device;
5034 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
5035 assert(pipeline->layout);
5036
5037 struct radv_blend_state blend = radv_pipeline_init_blend_state(pipeline, pCreateInfo, extra);
5038
5039 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
5040 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
5041 radv_init_feedback(creation_feedback);
5042
5043 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
5044
5045 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
5046 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
5047 for (uint32_t i = 0; i < pCreateInfo->stageCount; i++) {
5048 gl_shader_stage stage = ffs(pCreateInfo->pStages[i].stage) - 1;
5049 pStages[stage] = &pCreateInfo->pStages[i];
5050 if(creation_feedback)
5051 stage_feedbacks[stage] = &creation_feedback->pPipelineStageCreationFeedbacks[i];
5052 }
5053
5054 struct radv_pipeline_key key = radv_generate_graphics_pipeline_key(pipeline, pCreateInfo, &blend, has_view_index);
5055 if (radv_device_use_secure_compile(device->instance)) {
5056 return radv_secure_compile(pipeline, device, &key, pStages, pCreateInfo->flags, pCreateInfo->stageCount);
5057 } else {
5058 radv_create_shaders(pipeline, device, cache, &key, pStages, pCreateInfo->flags, pipeline_feedback, stage_feedbacks);
5059 }
5060
5061 pipeline->graphics.spi_baryc_cntl = S_0286E0_FRONT_FACE_ALL_BITS(1);
5062 radv_pipeline_init_multisample_state(pipeline, &blend, pCreateInfo);
5063 uint32_t gs_out;
5064 uint32_t prim = si_translate_prim(pCreateInfo->pInputAssemblyState->topology);
5065
5066 pipeline->graphics.topology = pCreateInfo->pInputAssemblyState->topology;
5067 pipeline->graphics.can_use_guardband = radv_prim_can_use_guardband(pCreateInfo->pInputAssemblyState->topology);
5068
5069 if (radv_pipeline_has_gs(pipeline)) {
5070 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_GEOMETRY]->info.gs.output_prim);
5071 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
5072 } else if (radv_pipeline_has_tess(pipeline)) {
5073 if (pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.point_mode)
5074 gs_out = V_028A6C_OUTPRIM_TYPE_POINTLIST;
5075 else
5076 gs_out = si_conv_gl_prim_to_gs_out(pipeline->shaders[MESA_SHADER_TESS_EVAL]->info.tes.primitive_mode);
5077 pipeline->graphics.can_use_guardband = gs_out == V_028A6C_OUTPRIM_TYPE_TRISTRIP;
5078 } else {
5079 gs_out = si_conv_prim_to_gs_out(pCreateInfo->pInputAssemblyState->topology);
5080 }
5081 if (extra && extra->use_rectlist) {
5082 prim = V_008958_DI_PT_RECTLIST;
5083 gs_out = V_028A6C_OUTPRIM_TYPE_TRISTRIP;
5084 pipeline->graphics.can_use_guardband = true;
5085 if (radv_pipeline_has_ngg(pipeline))
5086 gs_out = V_028A6C_VGT_OUT_RECT_V0;
5087 }
5088 pipeline->graphics.prim_restart_enable = !!pCreateInfo->pInputAssemblyState->primitiveRestartEnable;
5089 /* prim vertex count will need TESS changes */
5090 pipeline->graphics.prim_vertex_count = prim_size_table[prim];
5091
5092 radv_pipeline_init_dynamic_state(pipeline, pCreateInfo);
5093
5094 /* Ensure that some export memory is always allocated, for two reasons:
5095 *
5096 * 1) Correctness: The hardware ignores the EXEC mask if no export
5097 * memory is allocated, so KILL and alpha test do not work correctly
5098 * without this.
5099 * 2) Performance: Every shader needs at least a NULL export, even when
5100 * it writes no color/depth output. The NULL export instruction
5101 * stalls without this setting.
5102 *
5103 * Don't add this to CB_SHADER_MASK.
5104 *
5105 * GFX10 supports pixel shaders without exports by setting both the
5106 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
5107 * instructions if any are present.
5108 */
5109 struct radv_shader_variant *ps = pipeline->shaders[MESA_SHADER_FRAGMENT];
5110 if ((pipeline->device->physical_device->rad_info.chip_class <= GFX9 ||
5111 ps->info.ps.can_discard) &&
5112 !blend.spi_shader_col_format) {
5113 if (!ps->info.ps.writes_z &&
5114 !ps->info.ps.writes_stencil &&
5115 !ps->info.ps.writes_sample_mask)
5116 blend.spi_shader_col_format = V_028714_SPI_SHADER_32_R;
5117 }
5118
5119 for (unsigned i = 0; i < MESA_SHADER_STAGES; i++) {
5120 if (pipeline->shaders[i]) {
5121 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[i]->info.need_indirect_descriptor_sets;
5122 }
5123 }
5124
5125 if (radv_pipeline_has_gs(pipeline) && !radv_pipeline_has_ngg(pipeline)) {
5126 struct radv_shader_variant *gs =
5127 pipeline->shaders[MESA_SHADER_GEOMETRY];
5128
5129 calculate_gs_ring_sizes(pipeline, &gs->info.gs_ring_info);
5130 }
5131
5132 struct radv_tessellation_state tess = {0};
5133 if (radv_pipeline_has_tess(pipeline)) {
5134 if (prim == V_008958_DI_PT_PATCH) {
5135 pipeline->graphics.prim_vertex_count.min = pCreateInfo->pTessellationState->patchControlPoints;
5136 pipeline->graphics.prim_vertex_count.incr = 1;
5137 }
5138 tess = calculate_tess_state(pipeline, pCreateInfo);
5139 }
5140
5141 pipeline->graphics.ia_multi_vgt_param = radv_compute_ia_multi_vgt_param_helpers(pipeline, &tess, prim);
5142
5143 radv_compute_vertex_input_state(pipeline, pCreateInfo);
5144
5145 for (uint32_t i = 0; i < MESA_SHADER_STAGES; i++)
5146 pipeline->user_data_0[i] = radv_pipeline_stage_to_user_data_0(pipeline, i, device->physical_device->rad_info.chip_class);
5147
5148 struct radv_userdata_info *loc = radv_lookup_user_sgpr(pipeline, MESA_SHADER_VERTEX,
5149 AC_UD_VS_BASE_VERTEX_START_INSTANCE);
5150 if (loc->sgpr_idx != -1) {
5151 pipeline->graphics.vtx_base_sgpr = pipeline->user_data_0[MESA_SHADER_VERTEX];
5152 pipeline->graphics.vtx_base_sgpr += loc->sgpr_idx * 4;
5153 if (radv_get_shader(pipeline, MESA_SHADER_VERTEX)->info.vs.needs_draw_id)
5154 pipeline->graphics.vtx_emit_num = 3;
5155 else
5156 pipeline->graphics.vtx_emit_num = 2;
5157 }
5158
5159 /* Find the last vertex shader stage that eventually uses streamout. */
5160 pipeline->streamout_shader = radv_pipeline_get_streamout_shader(pipeline);
5161
5162 result = radv_pipeline_scratch_init(device, pipeline);
5163 radv_pipeline_generate_pm4(pipeline, pCreateInfo, extra, &blend, &tess, prim, gs_out);
5164
5165 return result;
5166 }
5167
5168 VkResult
5169 radv_graphics_pipeline_create(
5170 VkDevice _device,
5171 VkPipelineCache _cache,
5172 const VkGraphicsPipelineCreateInfo *pCreateInfo,
5173 const struct radv_graphics_pipeline_create_info *extra,
5174 const VkAllocationCallbacks *pAllocator,
5175 VkPipeline *pPipeline)
5176 {
5177 RADV_FROM_HANDLE(radv_device, device, _device);
5178 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
5179 struct radv_pipeline *pipeline;
5180 VkResult result;
5181
5182 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
5183 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5184 if (pipeline == NULL)
5185 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5186
5187 result = radv_pipeline_init(pipeline, device, cache,
5188 pCreateInfo, extra);
5189 if (result != VK_SUCCESS) {
5190 radv_pipeline_destroy(device, pipeline, pAllocator);
5191 return result;
5192 }
5193
5194 *pPipeline = radv_pipeline_to_handle(pipeline);
5195
5196 return VK_SUCCESS;
5197 }
5198
5199 VkResult radv_CreateGraphicsPipelines(
5200 VkDevice _device,
5201 VkPipelineCache pipelineCache,
5202 uint32_t count,
5203 const VkGraphicsPipelineCreateInfo* pCreateInfos,
5204 const VkAllocationCallbacks* pAllocator,
5205 VkPipeline* pPipelines)
5206 {
5207 VkResult result = VK_SUCCESS;
5208 unsigned i = 0;
5209
5210 for (; i < count; i++) {
5211 VkResult r;
5212 r = radv_graphics_pipeline_create(_device,
5213 pipelineCache,
5214 &pCreateInfos[i],
5215 NULL, pAllocator, &pPipelines[i]);
5216 if (r != VK_SUCCESS) {
5217 result = r;
5218 pPipelines[i] = VK_NULL_HANDLE;
5219 }
5220 }
5221
5222 return result;
5223 }
5224
5225
5226 static void
5227 radv_compute_generate_pm4(struct radv_pipeline *pipeline)
5228 {
5229 struct radv_shader_variant *compute_shader;
5230 struct radv_device *device = pipeline->device;
5231 unsigned threads_per_threadgroup;
5232 unsigned threadgroups_per_cu = 1;
5233 unsigned waves_per_threadgroup;
5234 unsigned max_waves_per_sh = 0;
5235 uint64_t va;
5236
5237 pipeline->cs.max_dw = device->physical_device->rad_info.chip_class >= GFX10 ? 22 : 20;
5238 pipeline->cs.buf = malloc(pipeline->cs.max_dw * 4);
5239
5240 compute_shader = pipeline->shaders[MESA_SHADER_COMPUTE];
5241 va = radv_buffer_get_va(compute_shader->bo) + compute_shader->bo_offset;
5242
5243 radeon_set_sh_reg_seq(&pipeline->cs, R_00B830_COMPUTE_PGM_LO, 2);
5244 radeon_emit(&pipeline->cs, va >> 8);
5245 radeon_emit(&pipeline->cs, S_00B834_DATA(va >> 40));
5246
5247 radeon_set_sh_reg_seq(&pipeline->cs, R_00B848_COMPUTE_PGM_RSRC1, 2);
5248 radeon_emit(&pipeline->cs, compute_shader->config.rsrc1);
5249 radeon_emit(&pipeline->cs, compute_shader->config.rsrc2);
5250 if (device->physical_device->rad_info.chip_class >= GFX10) {
5251 radeon_set_sh_reg(&pipeline->cs, R_00B8A0_COMPUTE_PGM_RSRC3, compute_shader->config.rsrc3);
5252 }
5253
5254 /* Calculate best compute resource limits. */
5255 threads_per_threadgroup = compute_shader->info.cs.block_size[0] *
5256 compute_shader->info.cs.block_size[1] *
5257 compute_shader->info.cs.block_size[2];
5258 waves_per_threadgroup = DIV_ROUND_UP(threads_per_threadgroup,
5259 compute_shader->info.wave_size);
5260
5261 if (device->physical_device->rad_info.chip_class >= GFX10 &&
5262 waves_per_threadgroup == 1)
5263 threadgroups_per_cu = 2;
5264
5265 radeon_set_sh_reg(&pipeline->cs, R_00B854_COMPUTE_RESOURCE_LIMITS,
5266 ac_get_compute_resource_limits(&device->physical_device->rad_info,
5267 waves_per_threadgroup,
5268 max_waves_per_sh,
5269 threadgroups_per_cu));
5270
5271 radeon_set_sh_reg_seq(&pipeline->cs, R_00B81C_COMPUTE_NUM_THREAD_X, 3);
5272 radeon_emit(&pipeline->cs,
5273 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[0]));
5274 radeon_emit(&pipeline->cs,
5275 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[1]));
5276 radeon_emit(&pipeline->cs,
5277 S_00B81C_NUM_THREAD_FULL(compute_shader->info.cs.block_size[2]));
5278
5279 assert(pipeline->cs.cdw <= pipeline->cs.max_dw);
5280 }
5281
5282 static struct radv_pipeline_key
5283 radv_generate_compute_pipeline_key(struct radv_pipeline *pipeline,
5284 const VkComputePipelineCreateInfo *pCreateInfo)
5285 {
5286 const VkPipelineShaderStageCreateInfo *stage = &pCreateInfo->stage;
5287 struct radv_pipeline_key key;
5288 memset(&key, 0, sizeof(key));
5289
5290 if (pCreateInfo->flags & VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT)
5291 key.optimisations_disabled = 1;
5292
5293 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT *subgroup_size =
5294 vk_find_struct_const(stage->pNext,
5295 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT);
5296
5297 if (subgroup_size) {
5298 assert(subgroup_size->requiredSubgroupSize == 32 ||
5299 subgroup_size->requiredSubgroupSize == 64);
5300 key.compute_subgroup_size = subgroup_size->requiredSubgroupSize;
5301 }
5302
5303 return key;
5304 }
5305
5306 static VkResult radv_compute_pipeline_create(
5307 VkDevice _device,
5308 VkPipelineCache _cache,
5309 const VkComputePipelineCreateInfo* pCreateInfo,
5310 const VkAllocationCallbacks* pAllocator,
5311 VkPipeline* pPipeline)
5312 {
5313 RADV_FROM_HANDLE(radv_device, device, _device);
5314 RADV_FROM_HANDLE(radv_pipeline_cache, cache, _cache);
5315 const VkPipelineShaderStageCreateInfo *pStages[MESA_SHADER_STAGES] = { 0, };
5316 VkPipelineCreationFeedbackEXT *stage_feedbacks[MESA_SHADER_STAGES] = { 0 };
5317 struct radv_pipeline *pipeline;
5318 VkResult result;
5319
5320 pipeline = vk_zalloc2(&device->alloc, pAllocator, sizeof(*pipeline), 8,
5321 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT);
5322 if (pipeline == NULL)
5323 return vk_error(device->instance, VK_ERROR_OUT_OF_HOST_MEMORY);
5324
5325 pipeline->device = device;
5326 pipeline->layout = radv_pipeline_layout_from_handle(pCreateInfo->layout);
5327 assert(pipeline->layout);
5328
5329 const VkPipelineCreationFeedbackCreateInfoEXT *creation_feedback =
5330 vk_find_struct_const(pCreateInfo->pNext, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT);
5331 radv_init_feedback(creation_feedback);
5332
5333 VkPipelineCreationFeedbackEXT *pipeline_feedback = creation_feedback ? creation_feedback->pPipelineCreationFeedback : NULL;
5334 if (creation_feedback)
5335 stage_feedbacks[MESA_SHADER_COMPUTE] = &creation_feedback->pPipelineStageCreationFeedbacks[0];
5336
5337 pStages[MESA_SHADER_COMPUTE] = &pCreateInfo->stage;
5338
5339 struct radv_pipeline_key key =
5340 radv_generate_compute_pipeline_key(pipeline, pCreateInfo);
5341
5342 if (radv_device_use_secure_compile(device->instance)) {
5343 result = radv_secure_compile(pipeline, device, &key, pStages, pCreateInfo->flags, 1);
5344 *pPipeline = radv_pipeline_to_handle(pipeline);
5345
5346 return result;
5347 } else {
5348 radv_create_shaders(pipeline, device, cache, &key, pStages, pCreateInfo->flags, pipeline_feedback, stage_feedbacks);
5349 }
5350
5351 pipeline->user_data_0[MESA_SHADER_COMPUTE] = radv_pipeline_stage_to_user_data_0(pipeline, MESA_SHADER_COMPUTE, device->physical_device->rad_info.chip_class);
5352 pipeline->need_indirect_descriptor_sets |= pipeline->shaders[MESA_SHADER_COMPUTE]->info.need_indirect_descriptor_sets;
5353 result = radv_pipeline_scratch_init(device, pipeline);
5354 if (result != VK_SUCCESS) {
5355 radv_pipeline_destroy(device, pipeline, pAllocator);
5356 return result;
5357 }
5358
5359 radv_compute_generate_pm4(pipeline);
5360
5361 *pPipeline = radv_pipeline_to_handle(pipeline);
5362
5363 return VK_SUCCESS;
5364 }
5365
5366 VkResult radv_CreateComputePipelines(
5367 VkDevice _device,
5368 VkPipelineCache pipelineCache,
5369 uint32_t count,
5370 const VkComputePipelineCreateInfo* pCreateInfos,
5371 const VkAllocationCallbacks* pAllocator,
5372 VkPipeline* pPipelines)
5373 {
5374 VkResult result = VK_SUCCESS;
5375
5376 unsigned i = 0;
5377 for (; i < count; i++) {
5378 VkResult r;
5379 r = radv_compute_pipeline_create(_device, pipelineCache,
5380 &pCreateInfos[i],
5381 pAllocator, &pPipelines[i]);
5382 if (r != VK_SUCCESS) {
5383 result = r;
5384 pPipelines[i] = VK_NULL_HANDLE;
5385 }
5386 }
5387
5388 return result;
5389 }
5390
5391
5392 static uint32_t radv_get_executable_count(const struct radv_pipeline *pipeline)
5393 {
5394 uint32_t ret = 0;
5395 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5396 if (!pipeline->shaders[i])
5397 continue;
5398
5399 if (i == MESA_SHADER_GEOMETRY &&
5400 !radv_pipeline_has_ngg(pipeline)) {
5401 ret += 2u;
5402 } else {
5403 ret += 1u;
5404 }
5405
5406 }
5407 return ret;
5408 }
5409
5410 static struct radv_shader_variant *
5411 radv_get_shader_from_executable_index(const struct radv_pipeline *pipeline, int index, gl_shader_stage *stage)
5412 {
5413 for (int i = 0; i < MESA_SHADER_STAGES; ++i) {
5414 if (!pipeline->shaders[i])
5415 continue;
5416 if (!index) {
5417 *stage = i;
5418 return pipeline->shaders[i];
5419 }
5420
5421 --index;
5422
5423 if (i == MESA_SHADER_GEOMETRY &&
5424 !radv_pipeline_has_ngg(pipeline)) {
5425 if (!index) {
5426 *stage = i;
5427 return pipeline->gs_copy_shader;
5428 }
5429 --index;
5430 }
5431 }
5432
5433 *stage = -1;
5434 return NULL;
5435 }
5436
5437 /* Basically strlcpy (which does not exist on linux) specialized for
5438 * descriptions. */
5439 static void desc_copy(char *desc, const char *src) {
5440 int len = strlen(src);
5441 assert(len < VK_MAX_DESCRIPTION_SIZE);
5442 memcpy(desc, src, len);
5443 memset(desc + len, 0, VK_MAX_DESCRIPTION_SIZE - len);
5444 }
5445
5446 VkResult radv_GetPipelineExecutablePropertiesKHR(
5447 VkDevice _device,
5448 const VkPipelineInfoKHR* pPipelineInfo,
5449 uint32_t* pExecutableCount,
5450 VkPipelineExecutablePropertiesKHR* pProperties)
5451 {
5452 RADV_FROM_HANDLE(radv_pipeline, pipeline, pPipelineInfo->pipeline);
5453 const uint32_t total_count = radv_get_executable_count(pipeline);
5454
5455 if (!pProperties) {
5456 *pExecutableCount = total_count;
5457 return VK_SUCCESS;
5458 }
5459
5460 const uint32_t count = MIN2(total_count, *pExecutableCount);
5461 for (unsigned i = 0, executable_idx = 0;
5462 i < MESA_SHADER_STAGES && executable_idx < count; ++i) {
5463 if (!pipeline->shaders[i])
5464 continue;
5465 pProperties[executable_idx].stages = mesa_to_vk_shader_stage(i);
5466 const char *name = NULL;
5467 const char *description = NULL;
5468 switch(i) {
5469 case MESA_SHADER_VERTEX:
5470 name = "Vertex Shader";
5471 description = "Vulkan Vertex Shader";
5472 break;
5473 case MESA_SHADER_TESS_CTRL:
5474 if (!pipeline->shaders[MESA_SHADER_VERTEX]) {
5475 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5476 name = "Vertex + Tessellation Control Shaders";
5477 description = "Combined Vulkan Vertex and Tessellation Control Shaders";
5478 } else {
5479 name = "Tessellation Control Shader";
5480 description = "Vulkan Tessellation Control Shader";
5481 }
5482 break;
5483 case MESA_SHADER_TESS_EVAL:
5484 name = "Tessellation Evaluation Shader";
5485 description = "Vulkan Tessellation Evaluation Shader";
5486 break;
5487 case MESA_SHADER_GEOMETRY:
5488 if (radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_TESS_EVAL]) {
5489 pProperties[executable_idx].stages |= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT;
5490 name = "Tessellation Evaluation + Geometry Shaders";
5491 description = "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5492 } else if (!radv_pipeline_has_tess(pipeline) && !pipeline->shaders[MESA_SHADER_VERTEX]) {
5493 pProperties[executable_idx].stages |= VK_SHADER_STAGE_VERTEX_BIT;
5494 name = "Vertex + Geometry Shader";
5495 description = "Combined Vulkan Vertex and Geometry Shaders";
5496 } else {
5497 name = "Geometry Shader";
5498 description = "Vulkan Geometry Shader";
5499 }
5500 break;
5501 case MESA_SHADER_FRAGMENT:
5502 name = "Fragment Shader";
5503 description = "Vulkan Fragment Shader";
5504 break;
5505 case MESA_SHADER_COMPUTE:
5506 name = "Compute Shader";
5507 description = "Vulkan Compute Shader";
5508 break;
5509 }
5510
5511 pProperties[executable_idx].subgroupSize = pipeline->shaders[i]->info.wave_size;
5512 desc_copy(pProperties[executable_idx].name, name);
5513 desc_copy(pProperties[executable_idx].description, description);
5514
5515 ++executable_idx;
5516 if (i == MESA_SHADER_GEOMETRY &&
5517 !radv_pipeline_has_ngg(pipeline)) {
5518 assert(pipeline->gs_copy_shader);
5519 if (executable_idx >= count)
5520 break;
5521
5522 pProperties[executable_idx].stages = VK_SHADER_STAGE_GEOMETRY_BIT;
5523 pProperties[executable_idx].subgroupSize = 64;
5524 desc_copy(pProperties[executable_idx].name, "GS Copy Shader");
5525 desc_copy(pProperties[executable_idx].description,
5526 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5527
5528 ++executable_idx;
5529 }
5530 }
5531
5532 VkResult result = *pExecutableCount < total_count ? VK_INCOMPLETE : VK_SUCCESS;
5533 *pExecutableCount = count;
5534 return result;
5535 }
5536
5537 VkResult radv_GetPipelineExecutableStatisticsKHR(
5538 VkDevice _device,
5539 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5540 uint32_t* pStatisticCount,
5541 VkPipelineExecutableStatisticKHR* pStatistics)
5542 {
5543 RADV_FROM_HANDLE(radv_device, device, _device);
5544 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5545 gl_shader_stage stage;
5546 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5547
5548 enum chip_class chip_class = device->physical_device->rad_info.chip_class;
5549 unsigned lds_increment = chip_class >= GFX7 ? 512 : 256;
5550 unsigned max_waves = radv_get_max_waves(device, shader, stage);
5551
5552 VkPipelineExecutableStatisticKHR *s = pStatistics;
5553 VkPipelineExecutableStatisticKHR *end = s + (pStatistics ? *pStatisticCount : 0);
5554 VkResult result = VK_SUCCESS;
5555
5556 if (s < end) {
5557 desc_copy(s->name, "SGPRs");
5558 desc_copy(s->description, "Number of SGPR registers allocated per subgroup");
5559 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5560 s->value.u64 = shader->config.num_sgprs;
5561 }
5562 ++s;
5563
5564 if (s < end) {
5565 desc_copy(s->name, "VGPRs");
5566 desc_copy(s->description, "Number of VGPR registers allocated per subgroup");
5567 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5568 s->value.u64 = shader->config.num_vgprs;
5569 }
5570 ++s;
5571
5572 if (s < end) {
5573 desc_copy(s->name, "Spilled SGPRs");
5574 desc_copy(s->description, "Number of SGPR registers spilled per subgroup");
5575 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5576 s->value.u64 = shader->config.spilled_sgprs;
5577 }
5578 ++s;
5579
5580 if (s < end) {
5581 desc_copy(s->name, "Spilled VGPRs");
5582 desc_copy(s->description, "Number of VGPR registers spilled per subgroup");
5583 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5584 s->value.u64 = shader->config.spilled_vgprs;
5585 }
5586 ++s;
5587
5588 if (s < end) {
5589 desc_copy(s->name, "PrivMem VGPRs");
5590 desc_copy(s->description, "Number of VGPRs stored in private memory per subgroup");
5591 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5592 s->value.u64 = shader->info.private_mem_vgprs;
5593 }
5594 ++s;
5595
5596 if (s < end) {
5597 desc_copy(s->name, "Code size");
5598 desc_copy(s->description, "Code size in bytes");
5599 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5600 s->value.u64 = shader->exec_size;
5601 }
5602 ++s;
5603
5604 if (s < end) {
5605 desc_copy(s->name, "LDS size");
5606 desc_copy(s->description, "LDS size in bytes per workgroup");
5607 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5608 s->value.u64 = shader->config.lds_size * lds_increment;
5609 }
5610 ++s;
5611
5612 if (s < end) {
5613 desc_copy(s->name, "Scratch size");
5614 desc_copy(s->description, "Private memory in bytes per subgroup");
5615 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5616 s->value.u64 = shader->config.scratch_bytes_per_wave;
5617 }
5618 ++s;
5619
5620 if (s < end) {
5621 desc_copy(s->name, "Subgroups per SIMD");
5622 desc_copy(s->description, "The maximum number of subgroups in flight on a SIMD unit");
5623 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5624 s->value.u64 = max_waves;
5625 }
5626 ++s;
5627
5628 if (shader->statistics) {
5629 for (unsigned i = 0; i < shader->statistics->count; i++) {
5630 struct radv_compiler_statistic_info *info = &shader->statistics->infos[i];
5631 uint32_t value = shader->statistics->values[i];
5632 if (s < end) {
5633 desc_copy(s->name, info->name);
5634 desc_copy(s->description, info->desc);
5635 s->format = VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR;
5636 s->value.u64 = value;
5637 }
5638 ++s;
5639 }
5640 }
5641
5642 if (!pStatistics)
5643 *pStatisticCount = s - pStatistics;
5644 else if (s > end) {
5645 *pStatisticCount = end - pStatistics;
5646 result = VK_INCOMPLETE;
5647 } else {
5648 *pStatisticCount = s - pStatistics;
5649 }
5650
5651 return result;
5652 }
5653
5654 static VkResult radv_copy_representation(void *data, size_t *data_size, const char *src)
5655 {
5656 size_t total_size = strlen(src) + 1;
5657
5658 if (!data) {
5659 *data_size = total_size;
5660 return VK_SUCCESS;
5661 }
5662
5663 size_t size = MIN2(total_size, *data_size);
5664
5665 memcpy(data, src, size);
5666 if (size)
5667 *((char*)data + size - 1) = 0;
5668 return size < total_size ? VK_INCOMPLETE : VK_SUCCESS;
5669 }
5670
5671 VkResult radv_GetPipelineExecutableInternalRepresentationsKHR(
5672 VkDevice device,
5673 const VkPipelineExecutableInfoKHR* pExecutableInfo,
5674 uint32_t* pInternalRepresentationCount,
5675 VkPipelineExecutableInternalRepresentationKHR* pInternalRepresentations)
5676 {
5677 RADV_FROM_HANDLE(radv_pipeline, pipeline, pExecutableInfo->pipeline);
5678 gl_shader_stage stage;
5679 struct radv_shader_variant *shader = radv_get_shader_from_executable_index(pipeline, pExecutableInfo->executableIndex, &stage);
5680
5681 VkPipelineExecutableInternalRepresentationKHR *p = pInternalRepresentations;
5682 VkPipelineExecutableInternalRepresentationKHR *end = p + (pInternalRepresentations ? *pInternalRepresentationCount : 0);
5683 VkResult result = VK_SUCCESS;
5684 /* optimized NIR */
5685 if (p < end) {
5686 p->isText = true;
5687 desc_copy(p->name, "NIR Shader(s)");
5688 desc_copy(p->description, "The optimized NIR shader(s)");
5689 if (radv_copy_representation(p->pData, &p->dataSize, shader->nir_string) != VK_SUCCESS)
5690 result = VK_INCOMPLETE;
5691 }
5692 ++p;
5693
5694 /* backend IR */
5695 if (p < end) {
5696 p->isText = true;
5697 if (pipeline->device->physical_device->use_aco) {
5698 desc_copy(p->name, "ACO IR");
5699 desc_copy(p->description, "The ACO IR after some optimizations");
5700 } else {
5701 desc_copy(p->name, "LLVM IR");
5702 desc_copy(p->description, "The LLVM IR after some optimizations");
5703 }
5704 if (radv_copy_representation(p->pData, &p->dataSize, shader->ir_string) != VK_SUCCESS)
5705 result = VK_INCOMPLETE;
5706 }
5707 ++p;
5708
5709 /* Disassembler */
5710 if (p < end) {
5711 p->isText = true;
5712 desc_copy(p->name, "Assembly");
5713 desc_copy(p->description, "Final Assembly");
5714 if (radv_copy_representation(p->pData, &p->dataSize, shader->disasm_string) != VK_SUCCESS)
5715 result = VK_INCOMPLETE;
5716 }
5717 ++p;
5718
5719 if (!pInternalRepresentations)
5720 *pInternalRepresentationCount = p - pInternalRepresentations;
5721 else if(p > end) {
5722 result = VK_INCOMPLETE;
5723 *pInternalRepresentationCount = end - pInternalRepresentations;
5724 } else {
5725 *pInternalRepresentationCount = p - pInternalRepresentations;
5726 }
5727
5728 return result;
5729 }