2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
34 #include "radv_shader.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
48 #include "ac_shader_util.h"
50 struct radv_blend_state
{
51 uint32_t blend_enable_4bit
;
52 uint32_t need_src_alpha
;
54 uint32_t cb_color_control
;
55 uint32_t cb_target_mask
;
56 uint32_t cb_target_enabled_4bit
;
57 uint32_t sx_mrt_blend_opt
[8];
58 uint32_t cb_blend_control
[8];
60 uint32_t spi_shader_col_format
;
61 uint32_t cb_shader_mask
;
62 uint32_t db_alpha_to_mask
;
64 uint32_t commutative_4bit
;
66 bool single_cb_enable
;
67 bool mrt0_is_dual_src
;
70 struct radv_dsa_order_invariance
{
71 /* Whether the final result in Z/S buffers is guaranteed to be
72 * invariant under changes to the order in which fragments arrive.
76 /* Whether the set of fragments that pass the combined Z/S test is
77 * guaranteed to be invariant under changes to the order in which
83 struct radv_tessellation_state
{
84 uint32_t ls_hs_config
;
90 static const VkPipelineMultisampleStateCreateInfo
*
91 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
93 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
94 return pCreateInfo
->pMultisampleState
;
98 static const VkPipelineTessellationStateCreateInfo
*
99 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
101 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
102 if (pCreateInfo
->pStages
[i
].stage
== VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
||
103 pCreateInfo
->pStages
[i
].stage
== VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
) {
104 return pCreateInfo
->pTessellationState
;
110 static const VkPipelineDepthStencilStateCreateInfo
*
111 radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
113 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
114 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
116 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
117 subpass
->depth_stencil_attachment
)
118 return pCreateInfo
->pDepthStencilState
;
122 static const VkPipelineColorBlendStateCreateInfo
*
123 radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
125 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
126 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
128 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
129 subpass
->has_color_att
)
130 return pCreateInfo
->pColorBlendState
;
134 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
)
136 struct radv_shader_variant
*variant
= NULL
;
137 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
138 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
139 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
140 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
141 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
142 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
145 return variant
->info
.is_ngg
;
148 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline
*pipeline
)
150 assert(radv_pipeline_has_ngg(pipeline
));
152 struct radv_shader_variant
*variant
= NULL
;
153 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
154 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
155 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
156 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
157 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
158 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
161 return variant
->info
.is_ngg_passthrough
;
164 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
)
166 if (!radv_pipeline_has_gs(pipeline
))
169 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
170 * On GFX10, it might be required in rare cases if it's not possible to
173 if (radv_pipeline_has_ngg(pipeline
))
176 assert(pipeline
->gs_copy_shader
);
181 radv_pipeline_destroy(struct radv_device
*device
,
182 struct radv_pipeline
*pipeline
,
183 const VkAllocationCallbacks
* allocator
)
185 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
186 if (pipeline
->shaders
[i
])
187 radv_shader_variant_destroy(device
, pipeline
->shaders
[i
]);
189 if (pipeline
->gs_copy_shader
)
190 radv_shader_variant_destroy(device
, pipeline
->gs_copy_shader
);
193 free(pipeline
->cs
.buf
);
195 vk_object_base_finish(&pipeline
->base
);
196 vk_free2(&device
->vk
.alloc
, allocator
, pipeline
);
199 void radv_DestroyPipeline(
201 VkPipeline _pipeline
,
202 const VkAllocationCallbacks
* pAllocator
)
204 RADV_FROM_HANDLE(radv_device
, device
, _device
);
205 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
210 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
213 static uint32_t get_hash_flags(struct radv_device
*device
)
215 uint32_t hash_flags
= 0;
217 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_NGG
)
218 hash_flags
|= RADV_HASH_SHADER_NO_NGG
;
219 if (device
->physical_device
->cs_wave_size
== 32)
220 hash_flags
|= RADV_HASH_SHADER_CS_WAVE32
;
221 if (device
->physical_device
->ps_wave_size
== 32)
222 hash_flags
|= RADV_HASH_SHADER_PS_WAVE32
;
223 if (device
->physical_device
->ge_wave_size
== 32)
224 hash_flags
|= RADV_HASH_SHADER_GE_WAVE32
;
225 if (device
->physical_device
->use_aco
)
226 hash_flags
|= RADV_HASH_SHADER_ACO
;
231 radv_pipeline_scratch_init(struct radv_device
*device
,
232 struct radv_pipeline
*pipeline
)
234 unsigned scratch_bytes_per_wave
= 0;
235 unsigned max_waves
= 0;
236 unsigned min_waves
= 1;
238 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
239 if (pipeline
->shaders
[i
] &&
240 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
) {
241 unsigned max_stage_waves
= device
->scratch_waves
;
243 scratch_bytes_per_wave
= MAX2(scratch_bytes_per_wave
,
244 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
);
246 max_stage_waves
= MIN2(max_stage_waves
,
247 4 * device
->physical_device
->rad_info
.num_good_compute_units
*
248 (256 / pipeline
->shaders
[i
]->config
.num_vgprs
));
249 max_waves
= MAX2(max_waves
, max_stage_waves
);
253 if (pipeline
->shaders
[MESA_SHADER_COMPUTE
]) {
254 unsigned group_size
= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[0] *
255 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[1] *
256 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[2];
257 min_waves
= MAX2(min_waves
, round_up_u32(group_size
, 64));
260 pipeline
->scratch_bytes_per_wave
= scratch_bytes_per_wave
;
261 pipeline
->max_waves
= max_waves
;
265 static uint32_t si_translate_blend_logic_op(VkLogicOp op
)
268 case VK_LOGIC_OP_CLEAR
:
269 return V_028808_ROP3_CLEAR
;
270 case VK_LOGIC_OP_AND
:
271 return V_028808_ROP3_AND
;
272 case VK_LOGIC_OP_AND_REVERSE
:
273 return V_028808_ROP3_AND_REVERSE
;
274 case VK_LOGIC_OP_COPY
:
275 return V_028808_ROP3_COPY
;
276 case VK_LOGIC_OP_AND_INVERTED
:
277 return V_028808_ROP3_AND_INVERTED
;
278 case VK_LOGIC_OP_NO_OP
:
279 return V_028808_ROP3_NO_OP
;
280 case VK_LOGIC_OP_XOR
:
281 return V_028808_ROP3_XOR
;
283 return V_028808_ROP3_OR
;
284 case VK_LOGIC_OP_NOR
:
285 return V_028808_ROP3_NOR
;
286 case VK_LOGIC_OP_EQUIVALENT
:
287 return V_028808_ROP3_EQUIVALENT
;
288 case VK_LOGIC_OP_INVERT
:
289 return V_028808_ROP3_INVERT
;
290 case VK_LOGIC_OP_OR_REVERSE
:
291 return V_028808_ROP3_OR_REVERSE
;
292 case VK_LOGIC_OP_COPY_INVERTED
:
293 return V_028808_ROP3_COPY_INVERTED
;
294 case VK_LOGIC_OP_OR_INVERTED
:
295 return V_028808_ROP3_OR_INVERTED
;
296 case VK_LOGIC_OP_NAND
:
297 return V_028808_ROP3_NAND
;
298 case VK_LOGIC_OP_SET
:
299 return V_028808_ROP3_SET
;
301 unreachable("Unhandled logic op");
306 static uint32_t si_translate_blend_function(VkBlendOp op
)
309 case VK_BLEND_OP_ADD
:
310 return V_028780_COMB_DST_PLUS_SRC
;
311 case VK_BLEND_OP_SUBTRACT
:
312 return V_028780_COMB_SRC_MINUS_DST
;
313 case VK_BLEND_OP_REVERSE_SUBTRACT
:
314 return V_028780_COMB_DST_MINUS_SRC
;
315 case VK_BLEND_OP_MIN
:
316 return V_028780_COMB_MIN_DST_SRC
;
317 case VK_BLEND_OP_MAX
:
318 return V_028780_COMB_MAX_DST_SRC
;
324 static uint32_t si_translate_blend_factor(VkBlendFactor factor
)
327 case VK_BLEND_FACTOR_ZERO
:
328 return V_028780_BLEND_ZERO
;
329 case VK_BLEND_FACTOR_ONE
:
330 return V_028780_BLEND_ONE
;
331 case VK_BLEND_FACTOR_SRC_COLOR
:
332 return V_028780_BLEND_SRC_COLOR
;
333 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
334 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
335 case VK_BLEND_FACTOR_DST_COLOR
:
336 return V_028780_BLEND_DST_COLOR
;
337 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
338 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
339 case VK_BLEND_FACTOR_SRC_ALPHA
:
340 return V_028780_BLEND_SRC_ALPHA
;
341 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
342 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
343 case VK_BLEND_FACTOR_DST_ALPHA
:
344 return V_028780_BLEND_DST_ALPHA
;
345 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
346 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
347 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
348 return V_028780_BLEND_CONSTANT_COLOR
;
349 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
350 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
351 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
352 return V_028780_BLEND_CONSTANT_ALPHA
;
353 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
354 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
355 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
356 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
357 case VK_BLEND_FACTOR_SRC1_COLOR
:
358 return V_028780_BLEND_SRC1_COLOR
;
359 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
360 return V_028780_BLEND_INV_SRC1_COLOR
;
361 case VK_BLEND_FACTOR_SRC1_ALPHA
:
362 return V_028780_BLEND_SRC1_ALPHA
;
363 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
364 return V_028780_BLEND_INV_SRC1_ALPHA
;
370 static uint32_t si_translate_blend_opt_function(VkBlendOp op
)
373 case VK_BLEND_OP_ADD
:
374 return V_028760_OPT_COMB_ADD
;
375 case VK_BLEND_OP_SUBTRACT
:
376 return V_028760_OPT_COMB_SUBTRACT
;
377 case VK_BLEND_OP_REVERSE_SUBTRACT
:
378 return V_028760_OPT_COMB_REVSUBTRACT
;
379 case VK_BLEND_OP_MIN
:
380 return V_028760_OPT_COMB_MIN
;
381 case VK_BLEND_OP_MAX
:
382 return V_028760_OPT_COMB_MAX
;
384 return V_028760_OPT_COMB_BLEND_DISABLED
;
388 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor
, bool is_alpha
)
391 case VK_BLEND_FACTOR_ZERO
:
392 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
393 case VK_BLEND_FACTOR_ONE
:
394 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
395 case VK_BLEND_FACTOR_SRC_COLOR
:
396 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
397 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
398 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
399 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
400 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
401 case VK_BLEND_FACTOR_SRC_ALPHA
:
402 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
403 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
404 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
405 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
406 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
407 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
409 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
414 * Get rid of DST in the blend factors by commuting the operands:
415 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
417 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
418 unsigned *dst_factor
, unsigned expected_dst
,
419 unsigned replacement_src
)
421 if (*src_factor
== expected_dst
&&
422 *dst_factor
== VK_BLEND_FACTOR_ZERO
) {
423 *src_factor
= VK_BLEND_FACTOR_ZERO
;
424 *dst_factor
= replacement_src
;
426 /* Commuting the operands requires reversing subtractions. */
427 if (*func
== VK_BLEND_OP_SUBTRACT
)
428 *func
= VK_BLEND_OP_REVERSE_SUBTRACT
;
429 else if (*func
== VK_BLEND_OP_REVERSE_SUBTRACT
)
430 *func
= VK_BLEND_OP_SUBTRACT
;
434 static bool si_blend_factor_uses_dst(unsigned factor
)
436 return factor
== VK_BLEND_FACTOR_DST_COLOR
||
437 factor
== VK_BLEND_FACTOR_DST_ALPHA
||
438 factor
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
439 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
||
440 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
;
443 static bool is_dual_src(VkBlendFactor factor
)
446 case VK_BLEND_FACTOR_SRC1_COLOR
:
447 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
448 case VK_BLEND_FACTOR_SRC1_ALPHA
:
449 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
456 static unsigned radv_choose_spi_color_format(VkFormat vk_format
,
458 bool blend_need_alpha
)
460 const struct vk_format_description
*desc
= vk_format_description(vk_format
);
461 struct ac_spi_color_formats formats
= {};
462 unsigned format
, ntype
, swap
;
464 format
= radv_translate_colorformat(vk_format
);
465 ntype
= radv_translate_color_numformat(vk_format
, desc
,
466 vk_format_get_first_non_void_channel(vk_format
));
467 swap
= radv_translate_colorswap(vk_format
, false);
469 ac_choose_spi_color_formats(format
, swap
, ntype
, false, &formats
);
471 if (blend_enable
&& blend_need_alpha
)
472 return formats
.blend_alpha
;
473 else if(blend_need_alpha
)
474 return formats
.alpha
;
475 else if(blend_enable
)
476 return formats
.blend
;
478 return formats
.normal
;
482 radv_pipeline_compute_spi_color_formats(struct radv_pipeline
*pipeline
,
483 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
484 struct radv_blend_state
*blend
)
486 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
487 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
488 unsigned col_format
= 0;
489 unsigned num_targets
;
491 for (unsigned i
= 0; i
< (blend
->single_cb_enable
? 1 : subpass
->color_count
); ++i
) {
494 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
) {
495 cf
= V_028714_SPI_SHADER_ZERO
;
497 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
499 blend
->blend_enable_4bit
& (0xfu
<< (i
* 4));
501 cf
= radv_choose_spi_color_format(attachment
->format
,
503 blend
->need_src_alpha
& (1 << i
));
506 col_format
|= cf
<< (4 * i
);
509 if (!(col_format
& 0xf) && blend
->need_src_alpha
& (1 << 0)) {
510 /* When a subpass doesn't have any color attachments, write the
511 * alpha channel of MRT0 when alpha coverage is enabled because
512 * the depth attachment needs it.
514 col_format
|= V_028714_SPI_SHADER_32_AR
;
517 /* If the i-th target format is set, all previous target formats must
518 * be non-zero to avoid hangs.
520 num_targets
= (util_last_bit(col_format
) + 3) / 4;
521 for (unsigned i
= 0; i
< num_targets
; i
++) {
522 if (!(col_format
& (0xf << (i
* 4)))) {
523 col_format
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
527 /* The output for dual source blending should have the same format as
530 if (blend
->mrt0_is_dual_src
)
531 col_format
|= (col_format
& 0xf) << 4;
533 blend
->cb_shader_mask
= ac_get_cb_shader_mask(col_format
);
534 blend
->spi_shader_col_format
= col_format
;
538 format_is_int8(VkFormat format
)
540 const struct vk_format_description
*desc
= vk_format_description(format
);
541 int channel
= vk_format_get_first_non_void_channel(format
);
543 return channel
>= 0 && desc
->channel
[channel
].pure_integer
&&
544 desc
->channel
[channel
].size
== 8;
548 format_is_int10(VkFormat format
)
550 const struct vk_format_description
*desc
= vk_format_description(format
);
552 if (desc
->nr_channels
!= 4)
554 for (unsigned i
= 0; i
< 4; i
++) {
555 if (desc
->channel
[i
].pure_integer
&& desc
->channel
[i
].size
== 10)
562 * Ordered so that for each i,
563 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
565 const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
] = {
566 VK_FORMAT_R32_SFLOAT
,
567 VK_FORMAT_R32G32_SFLOAT
,
568 VK_FORMAT_R8G8B8A8_UNORM
,
569 VK_FORMAT_R16G16B16A16_UNORM
,
570 VK_FORMAT_R16G16B16A16_SNORM
,
571 VK_FORMAT_R16G16B16A16_UINT
,
572 VK_FORMAT_R16G16B16A16_SINT
,
573 VK_FORMAT_R32G32B32A32_SFLOAT
,
574 VK_FORMAT_R8G8B8A8_UINT
,
575 VK_FORMAT_R8G8B8A8_SINT
,
576 VK_FORMAT_A2R10G10B10_UINT_PACK32
,
577 VK_FORMAT_A2R10G10B10_SINT_PACK32
,
580 unsigned radv_format_meta_fs_key(VkFormat format
)
582 unsigned col_format
= radv_choose_spi_color_format(format
, false, false);
584 assert(col_format
!= V_028714_SPI_SHADER_32_AR
);
585 if (col_format
>= V_028714_SPI_SHADER_32_AR
)
586 --col_format
; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
588 --col_format
; /* Skip V_028714_SPI_SHADER_ZERO */
589 bool is_int8
= format_is_int8(format
);
590 bool is_int10
= format_is_int10(format
);
592 return col_format
+ (is_int8
? 3 : is_int10
? 5 : 0);
596 radv_pipeline_compute_get_int_clamp(const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
597 unsigned *is_int8
, unsigned *is_int10
)
599 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
600 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
604 for (unsigned i
= 0; i
< subpass
->color_count
; ++i
) {
605 struct radv_render_pass_attachment
*attachment
;
607 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
610 attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
612 if (format_is_int8(attachment
->format
))
614 if (format_is_int10(attachment
->format
))
620 radv_blend_check_commutativity(struct radv_blend_state
*blend
,
621 VkBlendOp op
, VkBlendFactor src
,
622 VkBlendFactor dst
, unsigned chanmask
)
624 /* Src factor is allowed when it does not depend on Dst. */
625 static const uint32_t src_allowed
=
626 (1u << VK_BLEND_FACTOR_ONE
) |
627 (1u << VK_BLEND_FACTOR_SRC_COLOR
) |
628 (1u << VK_BLEND_FACTOR_SRC_ALPHA
) |
629 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
) |
630 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR
) |
631 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA
) |
632 (1u << VK_BLEND_FACTOR_SRC1_COLOR
) |
633 (1u << VK_BLEND_FACTOR_SRC1_ALPHA
) |
634 (1u << VK_BLEND_FACTOR_ZERO
) |
635 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
) |
636 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
) |
637 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
) |
638 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
) |
639 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
) |
640 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
);
642 if (dst
== VK_BLEND_FACTOR_ONE
&&
643 (src_allowed
& (1u << src
))) {
644 /* Addition is commutative, but floating point addition isn't
645 * associative: subtle changes can be introduced via different
646 * rounding. Be conservative, only enable for min and max.
648 if (op
== VK_BLEND_OP_MAX
|| op
== VK_BLEND_OP_MIN
)
649 blend
->commutative_4bit
|= chanmask
;
653 static struct radv_blend_state
654 radv_pipeline_init_blend_state(struct radv_pipeline
*pipeline
,
655 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
656 const struct radv_graphics_pipeline_create_info
*extra
)
658 const VkPipelineColorBlendStateCreateInfo
*vkblend
= radv_pipeline_get_color_blend_state(pCreateInfo
);
659 const VkPipelineMultisampleStateCreateInfo
*vkms
= radv_pipeline_get_multisample_state(pCreateInfo
);
660 struct radv_blend_state blend
= {0};
661 unsigned mode
= V_028808_CB_NORMAL
;
664 if (extra
&& extra
->custom_blend_mode
) {
665 blend
.single_cb_enable
= true;
666 mode
= extra
->custom_blend_mode
;
669 blend
.cb_color_control
= 0;
671 if (vkblend
->logicOpEnable
)
672 blend
.cb_color_control
|= S_028808_ROP3(si_translate_blend_logic_op(vkblend
->logicOp
));
674 blend
.cb_color_control
|= S_028808_ROP3(V_028808_ROP3_COPY
);
677 blend
.db_alpha_to_mask
= S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
678 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
679 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
680 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
681 S_028B70_OFFSET_ROUND(1);
683 if (vkms
&& vkms
->alphaToCoverageEnable
) {
684 blend
.db_alpha_to_mask
|= S_028B70_ALPHA_TO_MASK_ENABLE(1);
685 blend
.need_src_alpha
|= 0x1;
688 blend
.cb_target_mask
= 0;
690 for (i
= 0; i
< vkblend
->attachmentCount
; i
++) {
691 const VkPipelineColorBlendAttachmentState
*att
= &vkblend
->pAttachments
[i
];
692 unsigned blend_cntl
= 0;
693 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
694 VkBlendOp eqRGB
= att
->colorBlendOp
;
695 VkBlendFactor srcRGB
= att
->srcColorBlendFactor
;
696 VkBlendFactor dstRGB
= att
->dstColorBlendFactor
;
697 VkBlendOp eqA
= att
->alphaBlendOp
;
698 VkBlendFactor srcA
= att
->srcAlphaBlendFactor
;
699 VkBlendFactor dstA
= att
->dstAlphaBlendFactor
;
701 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
703 if (!att
->colorWriteMask
)
706 blend
.cb_target_mask
|= (unsigned)att
->colorWriteMask
<< (4 * i
);
707 blend
.cb_target_enabled_4bit
|= 0xf << (4 * i
);
708 if (!att
->blendEnable
) {
709 blend
.cb_blend_control
[i
] = blend_cntl
;
713 if (is_dual_src(srcRGB
) || is_dual_src(dstRGB
) || is_dual_src(srcA
) || is_dual_src(dstA
))
715 blend
.mrt0_is_dual_src
= true;
717 if (eqRGB
== VK_BLEND_OP_MIN
|| eqRGB
== VK_BLEND_OP_MAX
) {
718 srcRGB
= VK_BLEND_FACTOR_ONE
;
719 dstRGB
= VK_BLEND_FACTOR_ONE
;
721 if (eqA
== VK_BLEND_OP_MIN
|| eqA
== VK_BLEND_OP_MAX
) {
722 srcA
= VK_BLEND_FACTOR_ONE
;
723 dstA
= VK_BLEND_FACTOR_ONE
;
726 radv_blend_check_commutativity(&blend
, eqRGB
, srcRGB
, dstRGB
,
728 radv_blend_check_commutativity(&blend
, eqA
, srcA
, dstA
,
731 /* Blending optimizations for RB+.
732 * These transformations don't change the behavior.
734 * First, get rid of DST in the blend factors:
735 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
737 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
738 VK_BLEND_FACTOR_DST_COLOR
,
739 VK_BLEND_FACTOR_SRC_COLOR
);
741 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
742 VK_BLEND_FACTOR_DST_COLOR
,
743 VK_BLEND_FACTOR_SRC_COLOR
);
745 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
746 VK_BLEND_FACTOR_DST_ALPHA
,
747 VK_BLEND_FACTOR_SRC_ALPHA
);
749 /* Look up the ideal settings from tables. */
750 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
751 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
752 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
753 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
755 /* Handle interdependencies. */
756 if (si_blend_factor_uses_dst(srcRGB
))
757 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
758 if (si_blend_factor_uses_dst(srcA
))
759 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
761 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
&&
762 (dstRGB
== VK_BLEND_FACTOR_ZERO
||
763 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
764 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
))
765 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
767 /* Set the final value. */
768 blend
.sx_mrt_blend_opt
[i
] =
769 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
770 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
771 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
772 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
773 S_028760_ALPHA_DST_OPT(dstA_opt
) |
774 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
775 blend_cntl
|= S_028780_ENABLE(1);
777 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
778 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
779 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
780 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
781 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
782 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
783 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
784 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
786 blend
.cb_blend_control
[i
] = blend_cntl
;
788 blend
.blend_enable_4bit
|= 0xfu
<< (i
* 4);
790 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
791 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
792 srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
793 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
794 srcRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
||
795 dstRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
)
796 blend
.need_src_alpha
|= 1 << i
;
798 for (i
= vkblend
->attachmentCount
; i
< 8; i
++) {
799 blend
.cb_blend_control
[i
] = 0;
800 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
804 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
805 /* Disable RB+ blend optimizations for dual source blending. */
806 if (blend
.mrt0_is_dual_src
) {
807 for (i
= 0; i
< 8; i
++) {
808 blend
.sx_mrt_blend_opt
[i
] =
809 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
810 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
814 /* RB+ doesn't work with dual source blending, logic op and
817 if (blend
.mrt0_is_dual_src
||
818 (vkblend
&& vkblend
->logicOpEnable
) ||
819 mode
== V_028808_CB_RESOLVE
)
820 blend
.cb_color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
823 if (blend
.cb_target_mask
)
824 blend
.cb_color_control
|= S_028808_MODE(mode
);
826 blend
.cb_color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
828 radv_pipeline_compute_spi_color_formats(pipeline
, pCreateInfo
, &blend
);
832 static uint32_t si_translate_stencil_op(enum VkStencilOp op
)
835 case VK_STENCIL_OP_KEEP
:
836 return V_02842C_STENCIL_KEEP
;
837 case VK_STENCIL_OP_ZERO
:
838 return V_02842C_STENCIL_ZERO
;
839 case VK_STENCIL_OP_REPLACE
:
840 return V_02842C_STENCIL_REPLACE_TEST
;
841 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
842 return V_02842C_STENCIL_ADD_CLAMP
;
843 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
844 return V_02842C_STENCIL_SUB_CLAMP
;
845 case VK_STENCIL_OP_INVERT
:
846 return V_02842C_STENCIL_INVERT
;
847 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
848 return V_02842C_STENCIL_ADD_WRAP
;
849 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
850 return V_02842C_STENCIL_SUB_WRAP
;
856 static uint32_t si_translate_fill(VkPolygonMode func
)
859 case VK_POLYGON_MODE_FILL
:
860 return V_028814_X_DRAW_TRIANGLES
;
861 case VK_POLYGON_MODE_LINE
:
862 return V_028814_X_DRAW_LINES
;
863 case VK_POLYGON_MODE_POINT
:
864 return V_028814_X_DRAW_POINTS
;
867 return V_028814_X_DRAW_POINTS
;
871 static uint8_t radv_pipeline_get_ps_iter_samples(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
873 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
874 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
875 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
876 uint32_t ps_iter_samples
= 1;
877 uint32_t num_samples
;
879 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
881 * "If the VK_AMD_mixed_attachment_samples extension is enabled and the
882 * subpass uses color attachments, totalSamples is the number of
883 * samples of the color attachments. Otherwise, totalSamples is the
884 * value of VkPipelineMultisampleStateCreateInfo::rasterizationSamples
885 * specified at pipeline creation time."
887 if (subpass
->has_color_att
) {
888 num_samples
= subpass
->color_sample_count
;
890 num_samples
= vkms
->rasterizationSamples
;
893 if (vkms
->sampleShadingEnable
) {
894 ps_iter_samples
= ceilf(vkms
->minSampleShading
* num_samples
);
895 ps_iter_samples
= util_next_power_of_two(ps_iter_samples
);
897 return ps_iter_samples
;
901 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
903 return pCreateInfo
->depthTestEnable
&&
904 pCreateInfo
->depthWriteEnable
&&
905 pCreateInfo
->depthCompareOp
!= VK_COMPARE_OP_NEVER
;
909 radv_writes_stencil(const VkStencilOpState
*state
)
911 return state
->writeMask
&&
912 (state
->failOp
!= VK_STENCIL_OP_KEEP
||
913 state
->passOp
!= VK_STENCIL_OP_KEEP
||
914 state
->depthFailOp
!= VK_STENCIL_OP_KEEP
);
918 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
920 return pCreateInfo
->stencilTestEnable
&&
921 (radv_writes_stencil(&pCreateInfo
->front
) ||
922 radv_writes_stencil(&pCreateInfo
->back
));
926 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
928 return radv_is_depth_write_enabled(pCreateInfo
) ||
929 radv_is_stencil_write_enabled(pCreateInfo
);
933 radv_order_invariant_stencil_op(VkStencilOp op
)
935 /* REPLACE is normally order invariant, except when the stencil
936 * reference value is written by the fragment shader. Tracking this
937 * interaction does not seem worth the effort, so be conservative.
939 return op
!= VK_STENCIL_OP_INCREMENT_AND_CLAMP
&&
940 op
!= VK_STENCIL_OP_DECREMENT_AND_CLAMP
&&
941 op
!= VK_STENCIL_OP_REPLACE
;
945 radv_order_invariant_stencil_state(const VkStencilOpState
*state
)
947 /* Compute whether, assuming Z writes are disabled, this stencil state
948 * is order invariant in the sense that the set of passing fragments as
949 * well as the final stencil buffer result does not depend on the order
952 return !state
->writeMask
||
953 /* The following assumes that Z writes are disabled. */
954 (state
->compareOp
== VK_COMPARE_OP_ALWAYS
&&
955 radv_order_invariant_stencil_op(state
->passOp
) &&
956 radv_order_invariant_stencil_op(state
->depthFailOp
)) ||
957 (state
->compareOp
== VK_COMPARE_OP_NEVER
&&
958 radv_order_invariant_stencil_op(state
->failOp
));
962 radv_pipeline_out_of_order_rast(struct radv_pipeline
*pipeline
,
963 struct radv_blend_state
*blend
,
964 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
966 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
967 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
968 const VkPipelineDepthStencilStateCreateInfo
*vkds
= radv_pipeline_get_depth_stencil_state(pCreateInfo
);
969 const VkPipelineColorBlendStateCreateInfo
*vkblend
= radv_pipeline_get_color_blend_state(pCreateInfo
);
970 unsigned colormask
= blend
->cb_target_enabled_4bit
;
972 if (!pipeline
->device
->physical_device
->out_of_order_rast_allowed
)
975 /* Be conservative if a logic operation is enabled with color buffers. */
976 if (colormask
&& vkblend
&& vkblend
->logicOpEnable
)
979 /* Default depth/stencil invariance when no attachment is bound. */
980 struct radv_dsa_order_invariance dsa_order_invariant
= {
981 .zs
= true, .pass_set
= true
985 struct radv_render_pass_attachment
*attachment
=
986 pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
987 bool has_stencil
= vk_format_is_stencil(attachment
->format
);
988 struct radv_dsa_order_invariance order_invariance
[2];
989 struct radv_shader_variant
*ps
=
990 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
992 /* Compute depth/stencil order invariance in order to know if
993 * it's safe to enable out-of-order.
995 bool zfunc_is_ordered
=
996 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
||
997 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS
||
998 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS_OR_EQUAL
||
999 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER
||
1000 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER_OR_EQUAL
;
1002 bool nozwrite_and_order_invariant_stencil
=
1003 !radv_is_ds_write_enabled(vkds
) ||
1004 (!radv_is_depth_write_enabled(vkds
) &&
1005 radv_order_invariant_stencil_state(&vkds
->front
) &&
1006 radv_order_invariant_stencil_state(&vkds
->back
));
1008 order_invariance
[1].zs
=
1009 nozwrite_and_order_invariant_stencil
||
1010 (!radv_is_stencil_write_enabled(vkds
) &&
1012 order_invariance
[0].zs
=
1013 !radv_is_depth_write_enabled(vkds
) || zfunc_is_ordered
;
1015 order_invariance
[1].pass_set
=
1016 nozwrite_and_order_invariant_stencil
||
1017 (!radv_is_stencil_write_enabled(vkds
) &&
1018 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1019 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
));
1020 order_invariance
[0].pass_set
=
1021 !radv_is_depth_write_enabled(vkds
) ||
1022 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1023 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
);
1025 dsa_order_invariant
= order_invariance
[has_stencil
];
1026 if (!dsa_order_invariant
.zs
)
1029 /* The set of PS invocations is always order invariant,
1030 * except when early Z/S tests are requested.
1033 ps
->info
.ps
.writes_memory
&&
1034 ps
->info
.ps
.early_fragment_test
&&
1035 !dsa_order_invariant
.pass_set
)
1038 /* Determine if out-of-order rasterization should be disabled
1039 * when occlusion queries are used.
1041 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
=
1042 !dsa_order_invariant
.pass_set
;
1045 /* No color buffers are enabled for writing. */
1049 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
1052 /* Only commutative blending. */
1053 if (blendmask
& ~blend
->commutative_4bit
)
1056 if (!dsa_order_invariant
.pass_set
)
1060 if (colormask
& ~blendmask
)
1067 radv_pipeline_init_multisample_state(struct radv_pipeline
*pipeline
,
1068 struct radv_blend_state
*blend
,
1069 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1071 const VkPipelineMultisampleStateCreateInfo
*vkms
= radv_pipeline_get_multisample_state(pCreateInfo
);
1072 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
1073 unsigned num_tile_pipes
= pipeline
->device
->physical_device
->rad_info
.num_tile_pipes
;
1074 bool out_of_order_rast
= false;
1075 int ps_iter_samples
= 1;
1076 uint32_t mask
= 0xffff;
1079 ms
->num_samples
= vkms
->rasterizationSamples
;
1081 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1083 * "Sample shading is enabled for a graphics pipeline:
1085 * - If the interface of the fragment shader entry point of the
1086 * graphics pipeline includes an input variable decorated
1087 * with SampleId or SamplePosition. In this case
1088 * minSampleShadingFactor takes the value 1.0.
1089 * - Else if the sampleShadingEnable member of the
1090 * VkPipelineMultisampleStateCreateInfo structure specified
1091 * when creating the graphics pipeline is set to VK_TRUE. In
1092 * this case minSampleShadingFactor takes the value of
1093 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1095 * Otherwise, sample shading is considered disabled."
1097 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.force_persample
) {
1098 ps_iter_samples
= ms
->num_samples
;
1100 ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
);
1103 ms
->num_samples
= 1;
1106 const struct VkPipelineRasterizationStateRasterizationOrderAMD
*raster_order
=
1107 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD
);
1108 if (raster_order
&& raster_order
->rasterizationOrder
== VK_RASTERIZATION_ORDER_RELAXED_AMD
) {
1109 /* Out-of-order rasterization is explicitly enabled by the
1112 out_of_order_rast
= true;
1114 /* Determine if the driver can enable out-of-order
1115 * rasterization internally.
1118 radv_pipeline_out_of_order_rast(pipeline
, blend
, pCreateInfo
);
1121 ms
->pa_sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1122 ms
->pa_sc_aa_config
= 0;
1123 ms
->db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1124 S_028804_INCOHERENT_EQAA_READS(1) |
1125 S_028804_INTERPOLATE_COMP_Z(1) |
1126 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1127 ms
->pa_sc_mode_cntl_1
=
1128 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1129 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
1130 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
1131 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1133 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1134 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1135 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1136 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1137 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1138 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1139 ms
->pa_sc_mode_cntl_0
= S_028A48_ALTERNATE_RBS_PER_TILE(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
1140 S_028A48_VPORT_SCISSOR_ENABLE(1);
1142 const VkPipelineRasterizationLineStateCreateInfoEXT
*rast_line
=
1143 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1144 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1146 ms
->pa_sc_mode_cntl_0
|= S_028A48_LINE_STIPPLE_ENABLE(rast_line
->stippledLineEnable
);
1147 if (rast_line
->lineRasterizationMode
== VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT
) {
1148 /* From the Vulkan spec 1.1.129:
1150 * "When VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT lines
1151 * are being rasterized, sample locations may all be
1152 * treated as being at the pixel center (this may
1153 * affect attribute and depth interpolation)."
1155 ms
->num_samples
= 1;
1159 if (ms
->num_samples
> 1) {
1160 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1161 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1162 uint32_t z_samples
= subpass
->depth_stencil_attachment
? subpass
->depth_sample_count
: ms
->num_samples
;
1163 unsigned log_samples
= util_logbase2(ms
->num_samples
);
1164 unsigned log_z_samples
= util_logbase2(z_samples
);
1165 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
1166 ms
->pa_sc_mode_cntl_0
|= S_028A48_MSAA_ENABLE(1);
1167 ms
->pa_sc_line_cntl
|= S_028BDC_EXPAND_LINE_WIDTH(1); /* CM_R_028BDC_PA_SC_LINE_CNTL */
1168 ms
->db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples
) |
1169 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
1170 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
1171 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
1172 ms
->pa_sc_aa_config
|= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
1173 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples
)) |
1174 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
); /* CM_R_028BE0_PA_SC_AA_CONFIG */
1175 ms
->pa_sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
1176 if (ps_iter_samples
> 1)
1177 pipeline
->graphics
.spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1180 if (vkms
&& vkms
->pSampleMask
) {
1181 mask
= vkms
->pSampleMask
[0] & 0xffff;
1184 ms
->pa_sc_aa_mask
[0] = mask
| (mask
<< 16);
1185 ms
->pa_sc_aa_mask
[1] = mask
| (mask
<< 16);
1189 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology
)
1192 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1193 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1194 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1195 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1196 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1198 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1199 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1200 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1201 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1202 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1203 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1206 unreachable("unhandled primitive type");
1211 si_translate_prim(enum VkPrimitiveTopology topology
)
1214 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1215 return V_008958_DI_PT_POINTLIST
;
1216 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1217 return V_008958_DI_PT_LINELIST
;
1218 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1219 return V_008958_DI_PT_LINESTRIP
;
1220 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1221 return V_008958_DI_PT_TRILIST
;
1222 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1223 return V_008958_DI_PT_TRISTRIP
;
1224 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1225 return V_008958_DI_PT_TRIFAN
;
1226 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1227 return V_008958_DI_PT_LINELIST_ADJ
;
1228 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1229 return V_008958_DI_PT_LINESTRIP_ADJ
;
1230 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1231 return V_008958_DI_PT_TRILIST_ADJ
;
1232 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1233 return V_008958_DI_PT_TRISTRIP_ADJ
;
1234 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1235 return V_008958_DI_PT_PATCH
;
1243 si_conv_gl_prim_to_gs_out(unsigned gl_prim
)
1246 case 0: /* GL_POINTS */
1247 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1248 case 1: /* GL_LINES */
1249 case 3: /* GL_LINE_STRIP */
1250 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1251 case 0x8E7A: /* GL_ISOLINES */
1252 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1254 case 4: /* GL_TRIANGLES */
1255 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1256 case 5: /* GL_TRIANGLE_STRIP */
1257 case 7: /* GL_QUADS */
1258 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1266 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology
)
1269 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1270 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1271 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1272 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1273 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1274 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1275 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1276 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1277 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1278 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1279 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1280 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1281 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1282 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1289 static unsigned radv_dynamic_state_mask(VkDynamicState state
)
1292 case VK_DYNAMIC_STATE_VIEWPORT
:
1293 return RADV_DYNAMIC_VIEWPORT
;
1294 case VK_DYNAMIC_STATE_SCISSOR
:
1295 return RADV_DYNAMIC_SCISSOR
;
1296 case VK_DYNAMIC_STATE_LINE_WIDTH
:
1297 return RADV_DYNAMIC_LINE_WIDTH
;
1298 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
1299 return RADV_DYNAMIC_DEPTH_BIAS
;
1300 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
1301 return RADV_DYNAMIC_BLEND_CONSTANTS
;
1302 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
1303 return RADV_DYNAMIC_DEPTH_BOUNDS
;
1304 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
1305 return RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
1306 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
1307 return RADV_DYNAMIC_STENCIL_WRITE_MASK
;
1308 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
1309 return RADV_DYNAMIC_STENCIL_REFERENCE
;
1310 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT
:
1311 return RADV_DYNAMIC_DISCARD_RECTANGLE
;
1312 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT
:
1313 return RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1314 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
1315 return RADV_DYNAMIC_LINE_STIPPLE
;
1317 unreachable("Unhandled dynamic state");
1321 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1323 uint32_t states
= RADV_DYNAMIC_ALL
;
1325 /* If rasterization is disabled we do not care about any of the dynamic states,
1326 * since they are all rasterization related only. */
1327 if (pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
1330 if (!pCreateInfo
->pRasterizationState
->depthBiasEnable
)
1331 states
&= ~RADV_DYNAMIC_DEPTH_BIAS
;
1333 if (!pCreateInfo
->pDepthStencilState
||
1334 !pCreateInfo
->pDepthStencilState
->depthBoundsTestEnable
)
1335 states
&= ~RADV_DYNAMIC_DEPTH_BOUNDS
;
1337 if (!pCreateInfo
->pDepthStencilState
||
1338 !pCreateInfo
->pDepthStencilState
->stencilTestEnable
)
1339 states
&= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK
|
1340 RADV_DYNAMIC_STENCIL_WRITE_MASK
|
1341 RADV_DYNAMIC_STENCIL_REFERENCE
);
1343 if (!vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
))
1344 states
&= ~RADV_DYNAMIC_DISCARD_RECTANGLE
;
1346 if (!pCreateInfo
->pMultisampleState
||
1347 !vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1348 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
))
1349 states
&= ~RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1351 if (!pCreateInfo
->pRasterizationState
||
1352 !vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1353 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
))
1354 states
&= ~RADV_DYNAMIC_LINE_STIPPLE
;
1356 /* TODO: blend constants & line width. */
1363 radv_pipeline_init_dynamic_state(struct radv_pipeline
*pipeline
,
1364 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1366 uint32_t needed_states
= radv_pipeline_needed_dynamic_state(pCreateInfo
);
1367 uint32_t states
= needed_states
;
1368 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1369 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1371 pipeline
->dynamic_state
= default_dynamic_state
;
1372 pipeline
->graphics
.needed_dynamic_state
= needed_states
;
1374 if (pCreateInfo
->pDynamicState
) {
1375 /* Remove all of the states that are marked as dynamic */
1376 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1377 for (uint32_t s
= 0; s
< count
; s
++)
1378 states
&= ~radv_dynamic_state_mask(pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1381 struct radv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1383 if (needed_states
& RADV_DYNAMIC_VIEWPORT
) {
1384 assert(pCreateInfo
->pViewportState
);
1386 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1387 if (states
& RADV_DYNAMIC_VIEWPORT
) {
1388 typed_memcpy(dynamic
->viewport
.viewports
,
1389 pCreateInfo
->pViewportState
->pViewports
,
1390 pCreateInfo
->pViewportState
->viewportCount
);
1394 if (needed_states
& RADV_DYNAMIC_SCISSOR
) {
1395 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1396 if (states
& RADV_DYNAMIC_SCISSOR
) {
1397 typed_memcpy(dynamic
->scissor
.scissors
,
1398 pCreateInfo
->pViewportState
->pScissors
,
1399 pCreateInfo
->pViewportState
->scissorCount
);
1403 if (states
& RADV_DYNAMIC_LINE_WIDTH
) {
1404 assert(pCreateInfo
->pRasterizationState
);
1405 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1408 if (states
& RADV_DYNAMIC_DEPTH_BIAS
) {
1409 assert(pCreateInfo
->pRasterizationState
);
1410 dynamic
->depth_bias
.bias
=
1411 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1412 dynamic
->depth_bias
.clamp
=
1413 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1414 dynamic
->depth_bias
.slope
=
1415 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1418 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1420 * pColorBlendState is [...] NULL if the pipeline has rasterization
1421 * disabled or if the subpass of the render pass the pipeline is
1422 * created against does not use any color attachments.
1424 if (subpass
->has_color_att
&& states
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
1425 assert(pCreateInfo
->pColorBlendState
);
1426 typed_memcpy(dynamic
->blend_constants
,
1427 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1430 /* If there is no depthstencil attachment, then don't read
1431 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1432 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1433 * no need to override the depthstencil defaults in
1434 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1436 * Section 9.2 of the Vulkan 1.0.15 spec says:
1438 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1439 * disabled or if the subpass of the render pass the pipeline is created
1440 * against does not use a depth/stencil attachment.
1442 if (needed_states
&& subpass
->depth_stencil_attachment
) {
1443 assert(pCreateInfo
->pDepthStencilState
);
1445 if (states
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
1446 dynamic
->depth_bounds
.min
=
1447 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1448 dynamic
->depth_bounds
.max
=
1449 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1452 if (states
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
1453 dynamic
->stencil_compare_mask
.front
=
1454 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1455 dynamic
->stencil_compare_mask
.back
=
1456 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1459 if (states
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
1460 dynamic
->stencil_write_mask
.front
=
1461 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1462 dynamic
->stencil_write_mask
.back
=
1463 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1466 if (states
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
1467 dynamic
->stencil_reference
.front
=
1468 pCreateInfo
->pDepthStencilState
->front
.reference
;
1469 dynamic
->stencil_reference
.back
=
1470 pCreateInfo
->pDepthStencilState
->back
.reference
;
1474 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
1475 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
1476 if (needed_states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1477 dynamic
->discard_rectangle
.count
= discard_rectangle_info
->discardRectangleCount
;
1478 if (states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1479 typed_memcpy(dynamic
->discard_rectangle
.rectangles
,
1480 discard_rectangle_info
->pDiscardRectangles
,
1481 discard_rectangle_info
->discardRectangleCount
);
1485 if (needed_states
& RADV_DYNAMIC_SAMPLE_LOCATIONS
) {
1486 const VkPipelineSampleLocationsStateCreateInfoEXT
*sample_location_info
=
1487 vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1488 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
);
1489 /* If sampleLocationsEnable is VK_FALSE, the default sample
1490 * locations are used and the values specified in
1491 * sampleLocationsInfo are ignored.
1493 if (sample_location_info
->sampleLocationsEnable
) {
1494 const VkSampleLocationsInfoEXT
*pSampleLocationsInfo
=
1495 &sample_location_info
->sampleLocationsInfo
;
1497 assert(pSampleLocationsInfo
->sampleLocationsCount
<= MAX_SAMPLE_LOCATIONS
);
1499 dynamic
->sample_location
.per_pixel
= pSampleLocationsInfo
->sampleLocationsPerPixel
;
1500 dynamic
->sample_location
.grid_size
= pSampleLocationsInfo
->sampleLocationGridSize
;
1501 dynamic
->sample_location
.count
= pSampleLocationsInfo
->sampleLocationsCount
;
1502 typed_memcpy(&dynamic
->sample_location
.locations
[0],
1503 pSampleLocationsInfo
->pSampleLocations
,
1504 pSampleLocationsInfo
->sampleLocationsCount
);
1508 const VkPipelineRasterizationLineStateCreateInfoEXT
*rast_line_info
=
1509 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1510 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1511 if (needed_states
& RADV_DYNAMIC_LINE_STIPPLE
) {
1512 dynamic
->line_stipple
.factor
= rast_line_info
->lineStippleFactor
;
1513 dynamic
->line_stipple
.pattern
= rast_line_info
->lineStipplePattern
;
1516 pipeline
->dynamic_state
.mask
= states
;
1520 gfx9_get_gs_info(const struct radv_pipeline_key
*key
,
1521 const struct radv_pipeline
*pipeline
,
1523 struct radv_shader_info
*infos
,
1524 struct gfx9_gs_info
*out
)
1526 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1527 struct radv_es_output_info
*es_info
;
1528 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1529 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1531 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ?
1532 &infos
[MESA_SHADER_TESS_EVAL
].tes
.es_info
:
1533 &infos
[MESA_SHADER_VERTEX
].vs
.es_info
;
1535 unsigned gs_num_invocations
= MAX2(gs_info
->gs
.invocations
, 1);
1536 bool uses_adjacency
;
1537 switch(key
->topology
) {
1538 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1539 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1540 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1541 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1542 uses_adjacency
= true;
1545 uses_adjacency
= false;
1549 /* All these are in dwords: */
1550 /* We can't allow using the whole LDS, because GS waves compete with
1551 * other shader stages for LDS space. */
1552 const unsigned max_lds_size
= 8 * 1024;
1553 const unsigned esgs_itemsize
= es_info
->esgs_itemsize
/ 4;
1554 unsigned esgs_lds_size
;
1556 /* All these are per subgroup: */
1557 const unsigned max_out_prims
= 32 * 1024;
1558 const unsigned max_es_verts
= 255;
1559 const unsigned ideal_gs_prims
= 64;
1560 unsigned max_gs_prims
, gs_prims
;
1561 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
1563 if (uses_adjacency
|| gs_num_invocations
> 1)
1564 max_gs_prims
= 127 / gs_num_invocations
;
1568 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1569 * Make sure we don't go over the maximum value.
1571 if (gs_info
->gs
.vertices_out
> 0) {
1572 max_gs_prims
= MIN2(max_gs_prims
,
1574 (gs_info
->gs
.vertices_out
* gs_num_invocations
));
1576 assert(max_gs_prims
> 0);
1578 /* If the primitive has adjacency, halve the number of vertices
1579 * that will be reused in multiple primitives.
1581 min_es_verts
= gs_info
->gs
.vertices_in
/ (uses_adjacency
? 2 : 1);
1583 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
1584 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
1586 /* Compute ESGS LDS size based on the worst case number of ES vertices
1587 * needed to create the target number of GS prims per subgroup.
1589 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1591 /* If total LDS usage is too big, refactor partitions based on ratio
1592 * of ESGS item sizes.
1594 if (esgs_lds_size
> max_lds_size
) {
1595 /* Our target GS Prims Per Subgroup was too large. Calculate
1596 * the maximum number of GS Prims Per Subgroup that will fit
1597 * into LDS, capped by the maximum that the hardware can support.
1599 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
1601 assert(gs_prims
> 0);
1602 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
1605 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1606 assert(esgs_lds_size
<= max_lds_size
);
1609 /* Now calculate remaining ESGS information. */
1611 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
1613 es_verts
= max_es_verts
;
1615 /* Vertices for adjacency primitives are not always reused, so restore
1616 * it for ES_VERTS_PER_SUBGRP.
1618 min_es_verts
= gs_info
->gs
.vertices_in
;
1620 /* For normal primitives, the VGT only checks if they are past the ES
1621 * verts per subgroup after allocating a full GS primitive and if they
1622 * are, kick off a new subgroup. But if those additional ES verts are
1623 * unique (e.g. not reused) we need to make sure there is enough LDS
1624 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1626 es_verts
-= min_es_verts
- 1;
1628 uint32_t es_verts_per_subgroup
= es_verts
;
1629 uint32_t gs_prims_per_subgroup
= gs_prims
;
1630 uint32_t gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
1631 uint32_t max_prims_per_subgroup
= gs_inst_prims_in_subgroup
* gs_info
->gs
.vertices_out
;
1632 out
->lds_size
= align(esgs_lds_size
, 128) / 128;
1633 out
->vgt_gs_onchip_cntl
= S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup
) |
1634 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup
) |
1635 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup
);
1636 out
->vgt_gs_max_prims_per_subgroup
= S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup
);
1637 out
->vgt_esgs_ring_itemsize
= esgs_itemsize
;
1638 assert(max_prims_per_subgroup
<= max_out_prims
);
1641 static void clamp_gsprims_to_esverts(unsigned *max_gsprims
, unsigned max_esverts
,
1642 unsigned min_verts_per_prim
, bool use_adjacency
)
1644 unsigned max_reuse
= max_esverts
- min_verts_per_prim
;
1647 *max_gsprims
= MIN2(*max_gsprims
, 1 + max_reuse
);
1651 radv_get_num_input_vertices(nir_shader
**nir
)
1653 if (nir
[MESA_SHADER_GEOMETRY
]) {
1654 nir_shader
*gs
= nir
[MESA_SHADER_GEOMETRY
];
1656 return gs
->info
.gs
.vertices_in
;
1659 if (nir
[MESA_SHADER_TESS_CTRL
]) {
1660 nir_shader
*tes
= nir
[MESA_SHADER_TESS_EVAL
];
1662 if (tes
->info
.tess
.point_mode
)
1664 if (tes
->info
.tess
.primitive_mode
== GL_ISOLINES
)
1673 gfx10_get_ngg_info(const struct radv_pipeline_key
*key
,
1674 struct radv_pipeline
*pipeline
,
1676 struct radv_shader_info
*infos
,
1677 struct gfx10_ngg_info
*ngg
)
1679 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1680 struct radv_es_output_info
*es_info
=
1681 nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1682 unsigned gs_type
= nir
[MESA_SHADER_GEOMETRY
] ? MESA_SHADER_GEOMETRY
: MESA_SHADER_VERTEX
;
1683 unsigned max_verts_per_prim
= radv_get_num_input_vertices(nir
);
1684 unsigned min_verts_per_prim
=
1685 gs_type
== MESA_SHADER_GEOMETRY
? max_verts_per_prim
: 1;
1686 unsigned gs_num_invocations
= nir
[MESA_SHADER_GEOMETRY
] ? MAX2(gs_info
->gs
.invocations
, 1) : 1;
1687 bool uses_adjacency
;
1688 switch(key
->topology
) {
1689 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1690 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1691 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1692 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1693 uses_adjacency
= true;
1696 uses_adjacency
= false;
1700 /* All these are in dwords: */
1701 /* We can't allow using the whole LDS, because GS waves compete with
1702 * other shader stages for LDS space.
1704 * TODO: We should really take the shader's internal LDS use into
1705 * account. The linker will fail if the size is greater than
1708 const unsigned max_lds_size
= 8 * 1024 - 768;
1709 const unsigned target_lds_size
= max_lds_size
;
1710 unsigned esvert_lds_size
= 0;
1711 unsigned gsprim_lds_size
= 0;
1713 /* All these are per subgroup: */
1714 bool max_vert_out_per_gs_instance
= false;
1715 unsigned max_esverts_base
= 256;
1716 unsigned max_gsprims_base
= 128; /* default prim group size clamp */
1718 /* Hardware has the following non-natural restrictions on the value
1719 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1721 * - at most 252 for any line input primitive type
1722 * - at most 251 for any quad input primitive type
1723 * - at most 251 for triangle strips with adjacency (this happens to
1724 * be the natural limit for triangle *lists* with adjacency)
1726 max_esverts_base
= MIN2(max_esverts_base
, 251 + max_verts_per_prim
- 1);
1728 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1729 unsigned max_out_verts_per_gsprim
=
1730 gs_info
->gs
.vertices_out
* gs_num_invocations
;
1732 if (max_out_verts_per_gsprim
<= 256) {
1733 if (max_out_verts_per_gsprim
) {
1734 max_gsprims_base
= MIN2(max_gsprims_base
,
1735 256 / max_out_verts_per_gsprim
);
1738 /* Use special multi-cycling mode in which each GS
1739 * instance gets its own subgroup. Does not work with
1741 max_vert_out_per_gs_instance
= true;
1742 max_gsprims_base
= 1;
1743 max_out_verts_per_gsprim
= gs_info
->gs
.vertices_out
;
1746 esvert_lds_size
= es_info
->esgs_itemsize
/ 4;
1747 gsprim_lds_size
= (gs_info
->gs
.gsvs_vertex_size
/ 4 + 1) * max_out_verts_per_gsprim
;
1750 /* LDS size for passing data from GS to ES. */
1751 struct radv_streamout_info
*so_info
= nir
[MESA_SHADER_TESS_CTRL
]
1752 ? &infos
[MESA_SHADER_TESS_EVAL
].so
1753 : &infos
[MESA_SHADER_VERTEX
].so
;
1755 if (so_info
->num_outputs
)
1756 esvert_lds_size
= 4 * so_info
->num_outputs
+ 1;
1758 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1759 * corresponding to the ES thread of the provoking vertex. All
1760 * ES threads load and export PrimitiveID for their thread.
1762 if (!nir
[MESA_SHADER_TESS_CTRL
] &&
1763 infos
[MESA_SHADER_VERTEX
].vs
.outinfo
.export_prim_id
)
1764 esvert_lds_size
= MAX2(esvert_lds_size
, 1);
1767 unsigned max_gsprims
= max_gsprims_base
;
1768 unsigned max_esverts
= max_esverts_base
;
1770 if (esvert_lds_size
)
1771 max_esverts
= MIN2(max_esverts
, target_lds_size
/ esvert_lds_size
);
1772 if (gsprim_lds_size
)
1773 max_gsprims
= MIN2(max_gsprims
, target_lds_size
/ gsprim_lds_size
);
1775 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1776 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
, min_verts_per_prim
, uses_adjacency
);
1777 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1779 if (esvert_lds_size
|| gsprim_lds_size
) {
1780 /* Now that we have a rough proportionality between esverts
1781 * and gsprims based on the primitive type, scale both of them
1782 * down simultaneously based on required LDS space.
1784 * We could be smarter about this if we knew how much vertex
1787 unsigned lds_total
= max_esverts
* esvert_lds_size
+
1788 max_gsprims
* gsprim_lds_size
;
1789 if (lds_total
> target_lds_size
) {
1790 max_esverts
= max_esverts
* target_lds_size
/ lds_total
;
1791 max_gsprims
= max_gsprims
* target_lds_size
/ lds_total
;
1793 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1794 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1795 min_verts_per_prim
, uses_adjacency
);
1796 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1800 /* Round up towards full wave sizes for better ALU utilization. */
1801 if (!max_vert_out_per_gs_instance
) {
1802 unsigned orig_max_esverts
;
1803 unsigned orig_max_gsprims
;
1806 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1807 wavesize
= gs_info
->wave_size
;
1809 wavesize
= nir
[MESA_SHADER_TESS_CTRL
]
1810 ? infos
[MESA_SHADER_TESS_EVAL
].wave_size
1811 : infos
[MESA_SHADER_VERTEX
].wave_size
;
1815 orig_max_esverts
= max_esverts
;
1816 orig_max_gsprims
= max_gsprims
;
1818 max_esverts
= align(max_esverts
, wavesize
);
1819 max_esverts
= MIN2(max_esverts
, max_esverts_base
);
1820 if (esvert_lds_size
)
1821 max_esverts
= MIN2(max_esverts
,
1822 (max_lds_size
- max_gsprims
* gsprim_lds_size
) /
1824 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1826 max_gsprims
= align(max_gsprims
, wavesize
);
1827 max_gsprims
= MIN2(max_gsprims
, max_gsprims_base
);
1828 if (gsprim_lds_size
)
1829 max_gsprims
= MIN2(max_gsprims
,
1830 (max_lds_size
- max_esverts
* esvert_lds_size
) /
1832 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1833 min_verts_per_prim
, uses_adjacency
);
1834 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1835 } while (orig_max_esverts
!= max_esverts
|| orig_max_gsprims
!= max_gsprims
);
1838 /* Hardware restriction: minimum value of max_esverts */
1839 max_esverts
= MAX2(max_esverts
, 23 + max_verts_per_prim
);
1841 unsigned max_out_vertices
=
1842 max_vert_out_per_gs_instance
? gs_info
->gs
.vertices_out
:
1843 gs_type
== MESA_SHADER_GEOMETRY
?
1844 max_gsprims
* gs_num_invocations
* gs_info
->gs
.vertices_out
:
1846 assert(max_out_vertices
<= 256);
1848 unsigned prim_amp_factor
= 1;
1849 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1850 /* Number of output primitives per GS input primitive after
1852 prim_amp_factor
= gs_info
->gs
.vertices_out
;
1855 /* The GE only checks against the maximum number of ES verts after
1856 * allocating a full GS primitive. So we need to ensure that whenever
1857 * this check passes, there is enough space for a full primitive without
1860 ngg
->hw_max_esverts
= max_esverts
- max_verts_per_prim
+ 1;
1861 ngg
->max_gsprims
= max_gsprims
;
1862 ngg
->max_out_verts
= max_out_vertices
;
1863 ngg
->prim_amp_factor
= prim_amp_factor
;
1864 ngg
->max_vert_out_per_gs_instance
= max_vert_out_per_gs_instance
;
1865 ngg
->ngg_emit_size
= max_gsprims
* gsprim_lds_size
;
1866 ngg
->esgs_ring_size
= 4 * max_esverts
* esvert_lds_size
;
1868 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1869 ngg
->vgt_esgs_ring_itemsize
= es_info
->esgs_itemsize
/ 4;
1871 ngg
->vgt_esgs_ring_itemsize
= 1;
1874 pipeline
->graphics
.esgs_ring_size
= ngg
->esgs_ring_size
;
1876 assert(ngg
->hw_max_esverts
>= 24); /* HW limitation */
1880 calculate_gs_ring_sizes(struct radv_pipeline
*pipeline
,
1881 const struct gfx9_gs_info
*gs
)
1883 struct radv_device
*device
= pipeline
->device
;
1884 unsigned num_se
= device
->physical_device
->rad_info
.max_se
;
1885 unsigned wave_size
= 64;
1886 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
1887 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1888 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1890 unsigned gs_vertex_reuse
=
1891 (device
->physical_device
->rad_info
.chip_class
>= GFX8
? 32 : 16) * num_se
;
1892 unsigned alignment
= 256 * num_se
;
1893 /* The maximum size is 63.999 MB per SE. */
1894 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
1895 struct radv_shader_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
1897 /* Calculate the minimum size. */
1898 unsigned min_esgs_ring_size
= align(gs
->vgt_esgs_ring_itemsize
* 4 * gs_vertex_reuse
*
1899 wave_size
, alignment
);
1900 /* These are recommended sizes, not minimum sizes. */
1901 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
1902 gs
->vgt_esgs_ring_itemsize
* 4 * gs_info
->gs
.vertices_in
;
1903 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
1904 gs_info
->gs
.max_gsvs_emit_size
;
1906 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
1907 esgs_ring_size
= align(esgs_ring_size
, alignment
);
1908 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
1910 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
1911 pipeline
->graphics
.esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
1913 pipeline
->graphics
.gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
1916 static void si_multiwave_lds_size_workaround(struct radv_device
*device
,
1919 /* If tessellation is all offchip and on-chip GS isn't used, this
1920 * workaround is not needed.
1924 /* SPI barrier management bug:
1925 * Make sure we have at least 4k of LDS in use to avoid the bug.
1926 * It applies to workgroup sizes of more than one wavefront.
1928 if (device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
||
1929 device
->physical_device
->rad_info
.family
== CHIP_KABINI
)
1930 *lds_size
= MAX2(*lds_size
, 8);
1933 struct radv_shader_variant
*
1934 radv_get_shader(struct radv_pipeline
*pipeline
,
1935 gl_shader_stage stage
)
1937 if (stage
== MESA_SHADER_VERTEX
) {
1938 if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
1939 return pipeline
->shaders
[MESA_SHADER_VERTEX
];
1940 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
])
1941 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
1942 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1943 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1944 } else if (stage
== MESA_SHADER_TESS_EVAL
) {
1945 if (!radv_pipeline_has_tess(pipeline
))
1947 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
1948 return pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
1949 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1950 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1952 return pipeline
->shaders
[stage
];
1955 static struct radv_tessellation_state
1956 calculate_tess_state(struct radv_pipeline
*pipeline
,
1957 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1959 unsigned num_tcs_input_cp
;
1960 unsigned num_tcs_output_cp
;
1962 unsigned num_patches
;
1963 struct radv_tessellation_state tess
= {0};
1965 num_tcs_input_cp
= pCreateInfo
->pTessellationState
->patchControlPoints
;
1966 num_tcs_output_cp
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.tcs_vertices_out
; //TCS VERTICES OUT
1967 num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
1969 lds_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.lds_size
;
1971 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
1972 assert(lds_size
<= 65536);
1973 lds_size
= align(lds_size
, 512) / 512;
1975 assert(lds_size
<= 32768);
1976 lds_size
= align(lds_size
, 256) / 256;
1978 si_multiwave_lds_size_workaround(pipeline
->device
, &lds_size
);
1980 tess
.lds_size
= lds_size
;
1982 tess
.ls_hs_config
= S_028B58_NUM_PATCHES(num_patches
) |
1983 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
1984 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
1985 tess
.num_patches
= num_patches
;
1987 struct radv_shader_variant
*tes
= radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
);
1988 unsigned type
= 0, partitioning
= 0, topology
= 0, distribution_mode
= 0;
1990 switch (tes
->info
.tes
.primitive_mode
) {
1992 type
= V_028B6C_TESS_TRIANGLE
;
1995 type
= V_028B6C_TESS_QUAD
;
1998 type
= V_028B6C_TESS_ISOLINE
;
2002 switch (tes
->info
.tes
.spacing
) {
2003 case TESS_SPACING_EQUAL
:
2004 partitioning
= V_028B6C_PART_INTEGER
;
2006 case TESS_SPACING_FRACTIONAL_ODD
:
2007 partitioning
= V_028B6C_PART_FRAC_ODD
;
2009 case TESS_SPACING_FRACTIONAL_EVEN
:
2010 partitioning
= V_028B6C_PART_FRAC_EVEN
;
2016 bool ccw
= tes
->info
.tes
.ccw
;
2017 const VkPipelineTessellationDomainOriginStateCreateInfo
*domain_origin_state
=
2018 vk_find_struct_const(pCreateInfo
->pTessellationState
,
2019 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO
);
2021 if (domain_origin_state
&& domain_origin_state
->domainOrigin
!= VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT
)
2024 if (tes
->info
.tes
.point_mode
)
2025 topology
= V_028B6C_OUTPUT_POINT
;
2026 else if (tes
->info
.tes
.primitive_mode
== GL_ISOLINES
)
2027 topology
= V_028B6C_OUTPUT_LINE
;
2029 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
2031 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
2033 if (pipeline
->device
->physical_device
->rad_info
.has_distributed_tess
) {
2034 if (pipeline
->device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
2035 pipeline
->device
->physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
2036 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
2038 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
2040 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
2042 tess
.tf_param
= S_028B6C_TYPE(type
) |
2043 S_028B6C_PARTITIONING(partitioning
) |
2044 S_028B6C_TOPOLOGY(topology
) |
2045 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
2050 static const struct radv_prim_vertex_count prim_size_table
[] = {
2051 [V_008958_DI_PT_NONE
] = {0, 0},
2052 [V_008958_DI_PT_POINTLIST
] = {1, 1},
2053 [V_008958_DI_PT_LINELIST
] = {2, 2},
2054 [V_008958_DI_PT_LINESTRIP
] = {2, 1},
2055 [V_008958_DI_PT_TRILIST
] = {3, 3},
2056 [V_008958_DI_PT_TRIFAN
] = {3, 1},
2057 [V_008958_DI_PT_TRISTRIP
] = {3, 1},
2058 [V_008958_DI_PT_LINELIST_ADJ
] = {4, 4},
2059 [V_008958_DI_PT_LINESTRIP_ADJ
] = {4, 1},
2060 [V_008958_DI_PT_TRILIST_ADJ
] = {6, 6},
2061 [V_008958_DI_PT_TRISTRIP_ADJ
] = {6, 2},
2062 [V_008958_DI_PT_RECTLIST
] = {3, 3},
2063 [V_008958_DI_PT_LINELOOP
] = {2, 1},
2064 [V_008958_DI_PT_POLYGON
] = {3, 1},
2065 [V_008958_DI_PT_2D_TRI_STRIP
] = {0, 0},
2068 static const struct radv_vs_output_info
*get_vs_output_info(const struct radv_pipeline
*pipeline
)
2070 if (radv_pipeline_has_gs(pipeline
))
2071 if (radv_pipeline_has_ngg(pipeline
))
2072 return &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.vs
.outinfo
;
2074 return &pipeline
->gs_copy_shader
->info
.vs
.outinfo
;
2075 else if (radv_pipeline_has_tess(pipeline
))
2076 return &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.outinfo
;
2078 return &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.outinfo
;
2082 radv_link_shaders(struct radv_pipeline
*pipeline
, nir_shader
**shaders
)
2084 nir_shader
* ordered_shaders
[MESA_SHADER_STAGES
];
2085 int shader_count
= 0;
2087 if(shaders
[MESA_SHADER_FRAGMENT
]) {
2088 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_FRAGMENT
];
2090 if(shaders
[MESA_SHADER_GEOMETRY
]) {
2091 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_GEOMETRY
];
2093 if(shaders
[MESA_SHADER_TESS_EVAL
]) {
2094 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_EVAL
];
2096 if(shaders
[MESA_SHADER_TESS_CTRL
]) {
2097 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_CTRL
];
2099 if(shaders
[MESA_SHADER_VERTEX
]) {
2100 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_VERTEX
];
2103 if (shader_count
> 1) {
2104 unsigned first
= ordered_shaders
[shader_count
- 1]->info
.stage
;
2105 unsigned last
= ordered_shaders
[0]->info
.stage
;
2107 if (ordered_shaders
[0]->info
.stage
== MESA_SHADER_FRAGMENT
&&
2108 ordered_shaders
[1]->info
.has_transform_feedback_varyings
)
2109 nir_link_xfb_varyings(ordered_shaders
[1], ordered_shaders
[0]);
2111 for (int i
= 0; i
< shader_count
; ++i
) {
2112 nir_variable_mode mask
= 0;
2114 if (ordered_shaders
[i
]->info
.stage
!= first
)
2115 mask
= mask
| nir_var_shader_in
;
2117 if (ordered_shaders
[i
]->info
.stage
!= last
)
2118 mask
= mask
| nir_var_shader_out
;
2120 nir_lower_io_to_scalar_early(ordered_shaders
[i
], mask
);
2121 radv_optimize_nir(ordered_shaders
[i
], false, false);
2125 for (int i
= 1; i
< shader_count
; ++i
) {
2126 nir_lower_io_arrays_to_elements(ordered_shaders
[i
],
2127 ordered_shaders
[i
- 1]);
2129 if (nir_link_opt_varyings(ordered_shaders
[i
],
2130 ordered_shaders
[i
- 1]))
2131 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2133 nir_remove_dead_variables(ordered_shaders
[i
],
2134 nir_var_shader_out
, NULL
);
2135 nir_remove_dead_variables(ordered_shaders
[i
- 1],
2136 nir_var_shader_in
, NULL
);
2138 bool progress
= nir_remove_unused_varyings(ordered_shaders
[i
],
2139 ordered_shaders
[i
- 1]);
2141 nir_compact_varyings(ordered_shaders
[i
],
2142 ordered_shaders
[i
- 1], true);
2145 if (nir_lower_global_vars_to_local(ordered_shaders
[i
])) {
2146 ac_lower_indirect_derefs(ordered_shaders
[i
],
2147 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2149 radv_optimize_nir(ordered_shaders
[i
], false, false);
2151 if (nir_lower_global_vars_to_local(ordered_shaders
[i
- 1])) {
2152 ac_lower_indirect_derefs(ordered_shaders
[i
- 1],
2153 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2155 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2161 radv_set_linked_driver_locations(struct radv_pipeline
*pipeline
, nir_shader
**shaders
,
2162 struct radv_shader_info infos
[MESA_SHADER_STAGES
])
2164 bool has_tess
= shaders
[MESA_SHADER_TESS_CTRL
];
2165 bool has_gs
= shaders
[MESA_SHADER_GEOMETRY
];
2167 if (!has_tess
&& !has_gs
)
2170 unsigned vs_info_idx
= MESA_SHADER_VERTEX
;
2171 unsigned tes_info_idx
= MESA_SHADER_TESS_EVAL
;
2173 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2174 /* These are merged into the next stage */
2175 vs_info_idx
= has_tess
? MESA_SHADER_TESS_CTRL
: MESA_SHADER_GEOMETRY
;
2176 tes_info_idx
= has_gs
? MESA_SHADER_GEOMETRY
: MESA_SHADER_TESS_EVAL
;
2180 nir_linked_io_var_info vs2tcs
=
2181 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_VERTEX
], shaders
[MESA_SHADER_TESS_CTRL
]);
2182 nir_linked_io_var_info tcs2tes
=
2183 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_TESS_CTRL
], shaders
[MESA_SHADER_TESS_EVAL
]);
2185 infos
[vs_info_idx
].vs
.num_linked_outputs
= vs2tcs
.num_linked_io_vars
;
2186 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_inputs
= vs2tcs
.num_linked_io_vars
;
2187 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_outputs
= tcs2tes
.num_linked_io_vars
;
2188 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_patch_outputs
= tcs2tes
.num_linked_patch_io_vars
;
2189 infos
[tes_info_idx
].tes
.num_linked_inputs
= tcs2tes
.num_linked_io_vars
;
2190 infos
[tes_info_idx
].tes
.num_linked_patch_inputs
= tcs2tes
.num_linked_patch_io_vars
;
2193 nir_linked_io_var_info tes2gs
=
2194 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_TESS_EVAL
], shaders
[MESA_SHADER_GEOMETRY
]);
2196 infos
[tes_info_idx
].tes
.num_linked_outputs
= tes2gs
.num_linked_io_vars
;
2197 infos
[MESA_SHADER_GEOMETRY
].gs
.num_linked_inputs
= tes2gs
.num_linked_io_vars
;
2199 } else if (has_gs
) {
2200 nir_linked_io_var_info vs2gs
=
2201 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_VERTEX
], shaders
[MESA_SHADER_GEOMETRY
]);
2203 infos
[vs_info_idx
].vs
.num_linked_outputs
= vs2gs
.num_linked_io_vars
;
2204 infos
[MESA_SHADER_GEOMETRY
].gs
.num_linked_inputs
= vs2gs
.num_linked_io_vars
;
2209 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo
*input_state
,
2210 uint32_t attrib_binding
)
2212 for (uint32_t i
= 0; i
< input_state
->vertexBindingDescriptionCount
; i
++) {
2213 const VkVertexInputBindingDescription
*input_binding
=
2214 &input_state
->pVertexBindingDescriptions
[i
];
2216 if (input_binding
->binding
== attrib_binding
)
2217 return input_binding
->stride
;
2223 static struct radv_pipeline_key
2224 radv_generate_graphics_pipeline_key(struct radv_pipeline
*pipeline
,
2225 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2226 const struct radv_blend_state
*blend
,
2227 bool has_view_index
)
2229 const VkPipelineVertexInputStateCreateInfo
*input_state
=
2230 pCreateInfo
->pVertexInputState
;
2231 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*divisor_state
=
2232 vk_find_struct_const(input_state
->pNext
, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
2234 struct radv_pipeline_key key
;
2235 memset(&key
, 0, sizeof(key
));
2237 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
2238 key
.optimisations_disabled
= 1;
2240 key
.has_multiview_view_index
= has_view_index
;
2242 uint32_t binding_input_rate
= 0;
2243 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
2244 for (unsigned i
= 0; i
< input_state
->vertexBindingDescriptionCount
; ++i
) {
2245 if (input_state
->pVertexBindingDescriptions
[i
].inputRate
) {
2246 unsigned binding
= input_state
->pVertexBindingDescriptions
[i
].binding
;
2247 binding_input_rate
|= 1u << binding
;
2248 instance_rate_divisors
[binding
] = 1;
2251 if (divisor_state
) {
2252 for (unsigned i
= 0; i
< divisor_state
->vertexBindingDivisorCount
; ++i
) {
2253 instance_rate_divisors
[divisor_state
->pVertexBindingDivisors
[i
].binding
] =
2254 divisor_state
->pVertexBindingDivisors
[i
].divisor
;
2258 for (unsigned i
= 0; i
< input_state
->vertexAttributeDescriptionCount
; ++i
) {
2259 const VkVertexInputAttributeDescription
*desc
=
2260 &input_state
->pVertexAttributeDescriptions
[i
];
2261 const struct vk_format_description
*format_desc
;
2262 unsigned location
= desc
->location
;
2263 unsigned binding
= desc
->binding
;
2264 unsigned num_format
, data_format
;
2267 if (binding_input_rate
& (1u << binding
)) {
2268 key
.instance_rate_inputs
|= 1u << location
;
2269 key
.instance_rate_divisors
[location
] = instance_rate_divisors
[binding
];
2272 format_desc
= vk_format_description(desc
->format
);
2273 first_non_void
= vk_format_get_first_non_void_channel(desc
->format
);
2275 num_format
= radv_translate_buffer_numformat(format_desc
, first_non_void
);
2276 data_format
= radv_translate_buffer_dataformat(format_desc
, first_non_void
);
2278 key
.vertex_attribute_formats
[location
] = data_format
| (num_format
<< 4);
2279 key
.vertex_attribute_bindings
[location
] = desc
->binding
;
2280 key
.vertex_attribute_offsets
[location
] = desc
->offset
;
2281 key
.vertex_attribute_strides
[location
] = radv_get_attrib_stride(input_state
, desc
->binding
);
2283 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
&&
2284 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_STONEY
) {
2285 VkFormat format
= input_state
->pVertexAttributeDescriptions
[i
].format
;
2288 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2289 case VK_FORMAT_A2B10G10R10_SNORM_PACK32
:
2290 adjust
= RADV_ALPHA_ADJUST_SNORM
;
2292 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2293 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32
:
2294 adjust
= RADV_ALPHA_ADJUST_SSCALED
;
2296 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2297 case VK_FORMAT_A2B10G10R10_SINT_PACK32
:
2298 adjust
= RADV_ALPHA_ADJUST_SINT
;
2304 key
.vertex_alpha_adjust
|= adjust
<< (2 * location
);
2307 switch (desc
->format
) {
2308 case VK_FORMAT_B8G8R8A8_UNORM
:
2309 case VK_FORMAT_B8G8R8A8_SNORM
:
2310 case VK_FORMAT_B8G8R8A8_USCALED
:
2311 case VK_FORMAT_B8G8R8A8_SSCALED
:
2312 case VK_FORMAT_B8G8R8A8_UINT
:
2313 case VK_FORMAT_B8G8R8A8_SINT
:
2314 case VK_FORMAT_B8G8R8A8_SRGB
:
2315 case VK_FORMAT_A2R10G10B10_UNORM_PACK32
:
2316 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2317 case VK_FORMAT_A2R10G10B10_USCALED_PACK32
:
2318 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2319 case VK_FORMAT_A2R10G10B10_UINT_PACK32
:
2320 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2321 key
.vertex_post_shuffle
|= 1 << location
;
2328 const VkPipelineTessellationStateCreateInfo
*tess
=
2329 radv_pipeline_get_tessellation_state(pCreateInfo
);
2331 key
.tess_input_vertices
= tess
->patchControlPoints
;
2333 const VkPipelineMultisampleStateCreateInfo
*vkms
=
2334 radv_pipeline_get_multisample_state(pCreateInfo
);
2335 if (vkms
&& vkms
->rasterizationSamples
> 1) {
2336 uint32_t num_samples
= vkms
->rasterizationSamples
;
2337 uint32_t ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
);
2338 key
.num_samples
= num_samples
;
2339 key
.log2_ps_iter_samples
= util_logbase2(ps_iter_samples
);
2342 key
.col_format
= blend
->spi_shader_col_format
;
2343 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX8
)
2344 radv_pipeline_compute_get_int_clamp(pCreateInfo
, &key
.is_int8
, &key
.is_int10
);
2346 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
2347 key
.topology
= pCreateInfo
->pInputAssemblyState
->topology
;
2353 radv_nir_stage_uses_xfb(const nir_shader
*nir
)
2355 nir_xfb_info
*xfb
= nir_gather_xfb_info(nir
, NULL
);
2356 bool uses_xfb
= !!xfb
;
2363 radv_fill_shader_keys(struct radv_device
*device
,
2364 struct radv_shader_variant_key
*keys
,
2365 const struct radv_pipeline_key
*key
,
2368 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_inputs
= key
->instance_rate_inputs
;
2369 keys
[MESA_SHADER_VERTEX
].vs
.alpha_adjust
= key
->vertex_alpha_adjust
;
2370 keys
[MESA_SHADER_VERTEX
].vs
.post_shuffle
= key
->vertex_post_shuffle
;
2371 for (unsigned i
= 0; i
< MAX_VERTEX_ATTRIBS
; ++i
) {
2372 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_divisors
[i
] = key
->instance_rate_divisors
[i
];
2373 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_formats
[i
] = key
->vertex_attribute_formats
[i
];
2374 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_bindings
[i
] = key
->vertex_attribute_bindings
[i
];
2375 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_offsets
[i
] = key
->vertex_attribute_offsets
[i
];
2376 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_strides
[i
] = key
->vertex_attribute_strides
[i
];
2378 keys
[MESA_SHADER_VERTEX
].vs
.outprim
= si_conv_prim_to_gs_out(key
->topology
);
2380 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2381 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ls
= true;
2382 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= 0;
2383 keys
[MESA_SHADER_TESS_CTRL
].tcs
.input_vertices
= key
->tess_input_vertices
;
2384 keys
[MESA_SHADER_TESS_CTRL
].tcs
.primitive_mode
= nir
[MESA_SHADER_TESS_EVAL
]->info
.tess
.primitive_mode
;
2386 keys
[MESA_SHADER_TESS_CTRL
].tcs
.tes_reads_tess_factors
= !!(nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
& (VARYING_BIT_TESS_LEVEL_INNER
| VARYING_BIT_TESS_LEVEL_OUTER
));
2389 if (nir
[MESA_SHADER_GEOMETRY
]) {
2390 if (nir
[MESA_SHADER_TESS_CTRL
])
2391 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_es
= true;
2393 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_es
= true;
2396 if (device
->physical_device
->use_ngg
) {
2397 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2398 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= true;
2400 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= true;
2403 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2404 nir
[MESA_SHADER_GEOMETRY
] &&
2405 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.invocations
*
2406 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.vertices_out
> 256) {
2407 /* Fallback to the legacy path if tessellation is
2408 * enabled with extreme geometry because
2409 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2412 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2415 if (!device
->physical_device
->use_ngg_gs
) {
2416 if (nir
[MESA_SHADER_GEOMETRY
]) {
2417 if (nir
[MESA_SHADER_TESS_CTRL
])
2418 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2420 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2424 gl_shader_stage last_xfb_stage
= MESA_SHADER_VERTEX
;
2426 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2431 bool uses_xfb
= nir
[last_xfb_stage
] &&
2432 radv_nir_stage_uses_xfb(nir
[last_xfb_stage
]);
2434 if (!device
->physical_device
->use_ngg_streamout
&& uses_xfb
) {
2435 if (nir
[MESA_SHADER_TESS_CTRL
])
2436 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2438 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2441 /* Determine if the pipeline is eligible for the NGG passthrough
2442 * mode. It can't be enabled for geometry shaders, for NGG
2443 * streamout or for vertex shaders that export the primitive ID
2444 * (this is checked later because we don't have the info here.)
2446 if (!nir
[MESA_SHADER_GEOMETRY
] && !uses_xfb
) {
2447 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2448 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
) {
2449 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg_passthrough
= true;
2450 } else if (nir
[MESA_SHADER_VERTEX
] &&
2451 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) {
2452 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg_passthrough
= true;
2457 for(int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
2458 keys
[i
].has_multiview_view_index
= key
->has_multiview_view_index
;
2460 keys
[MESA_SHADER_FRAGMENT
].fs
.col_format
= key
->col_format
;
2461 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int8
= key
->is_int8
;
2462 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int10
= key
->is_int10
;
2463 keys
[MESA_SHADER_FRAGMENT
].fs
.log2_ps_iter_samples
= key
->log2_ps_iter_samples
;
2464 keys
[MESA_SHADER_FRAGMENT
].fs
.num_samples
= key
->num_samples
;
2466 if (nir
[MESA_SHADER_COMPUTE
]) {
2467 keys
[MESA_SHADER_COMPUTE
].cs
.subgroup_size
= key
->compute_subgroup_size
;
2472 radv_get_wave_size(struct radv_device
*device
,
2473 const VkPipelineShaderStageCreateInfo
*pStage
,
2474 gl_shader_stage stage
,
2475 const struct radv_shader_variant_key
*key
)
2477 if (stage
== MESA_SHADER_GEOMETRY
&& !key
->vs_common_out
.as_ngg
)
2479 else if (stage
== MESA_SHADER_COMPUTE
) {
2480 if (key
->cs
.subgroup_size
) {
2481 /* Return the required subgroup size if specified. */
2482 return key
->cs
.subgroup_size
;
2484 return device
->physical_device
->cs_wave_size
;
2486 else if (stage
== MESA_SHADER_FRAGMENT
)
2487 return device
->physical_device
->ps_wave_size
;
2489 return device
->physical_device
->ge_wave_size
;
2493 radv_get_ballot_bit_size(struct radv_device
*device
,
2494 const VkPipelineShaderStageCreateInfo
*pStage
,
2495 gl_shader_stage stage
,
2496 const struct radv_shader_variant_key
*key
)
2498 if (stage
== MESA_SHADER_COMPUTE
&& key
->cs
.subgroup_size
)
2499 return key
->cs
.subgroup_size
;
2504 radv_fill_shader_info(struct radv_pipeline
*pipeline
,
2505 const VkPipelineShaderStageCreateInfo
**pStages
,
2506 struct radv_shader_variant_key
*keys
,
2507 struct radv_shader_info
*infos
,
2510 unsigned active_stages
= 0;
2511 unsigned filled_stages
= 0;
2513 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2515 active_stages
|= (1 << i
);
2518 if (nir
[MESA_SHADER_FRAGMENT
]) {
2519 radv_nir_shader_info_init(&infos
[MESA_SHADER_FRAGMENT
]);
2520 radv_nir_shader_info_pass(nir
[MESA_SHADER_FRAGMENT
],
2522 &keys
[MESA_SHADER_FRAGMENT
],
2523 &infos
[MESA_SHADER_FRAGMENT
],
2524 pipeline
->device
->physical_device
->use_aco
);
2526 /* TODO: These are no longer used as keys we should refactor this */
2527 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
=
2528 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2529 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_layer_id
=
2530 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2531 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_clip_dists
=
2532 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2533 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_viewport_index
=
2534 infos
[MESA_SHADER_FRAGMENT
].ps
.viewport_index_input
;
2535 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_prim_id
=
2536 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2537 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_layer_id
=
2538 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2539 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_clip_dists
=
2540 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2541 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_viewport_index
=
2542 infos
[MESA_SHADER_FRAGMENT
].ps
.viewport_index_input
;
2544 /* NGG passthrough mode can't be enabled for vertex shaders
2545 * that export the primitive ID.
2547 * TODO: I should really refactor the keys logic.
2549 if (nir
[MESA_SHADER_VERTEX
] &&
2550 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
) {
2551 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg_passthrough
= false;
2554 filled_stages
|= (1 << MESA_SHADER_FRAGMENT
);
2557 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2558 infos
[MESA_SHADER_TESS_CTRL
].tcs
.tes_inputs_read
=
2559 nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
;
2560 infos
[MESA_SHADER_TESS_CTRL
].tcs
.tes_patch_inputs_read
=
2561 nir
[MESA_SHADER_TESS_EVAL
]->info
.patch_inputs_read
;
2564 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2565 nir
[MESA_SHADER_TESS_CTRL
]) {
2566 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2567 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2568 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2570 radv_nir_shader_info_init(&infos
[MESA_SHADER_TESS_CTRL
]);
2572 for (int i
= 0; i
< 2; i
++) {
2573 radv_nir_shader_info_pass(combined_nir
[i
],
2574 pipeline
->layout
, &key
,
2575 &infos
[MESA_SHADER_TESS_CTRL
],
2576 pipeline
->device
->physical_device
->use_aco
);
2579 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2580 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2581 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2582 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2584 filled_stages
|= (1 << MESA_SHADER_VERTEX
);
2585 filled_stages
|= (1 << MESA_SHADER_TESS_CTRL
);
2588 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2589 nir
[MESA_SHADER_GEOMETRY
]) {
2590 gl_shader_stage pre_stage
= nir
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2591 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2593 radv_nir_shader_info_init(&infos
[MESA_SHADER_GEOMETRY
]);
2595 for (int i
= 0; i
< 2; i
++) {
2596 radv_nir_shader_info_pass(combined_nir
[i
],
2599 &infos
[MESA_SHADER_GEOMETRY
],
2600 pipeline
->device
->physical_device
->use_aco
);
2603 filled_stages
|= (1 << pre_stage
);
2604 filled_stages
|= (1 << MESA_SHADER_GEOMETRY
);
2607 active_stages
^= filled_stages
;
2608 while (active_stages
) {
2609 int i
= u_bit_scan(&active_stages
);
2611 if (i
== MESA_SHADER_TESS_CTRL
) {
2612 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
=
2613 util_last_bit64(infos
[MESA_SHADER_VERTEX
].vs
.ls_outputs_written
);
2616 if (i
== MESA_SHADER_TESS_EVAL
) {
2617 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2618 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2619 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2620 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2623 radv_nir_shader_info_init(&infos
[i
]);
2624 radv_nir_shader_info_pass(nir
[i
], pipeline
->layout
,
2625 &keys
[i
], &infos
[i
], pipeline
->device
->physical_device
->use_aco
);
2628 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2630 infos
[i
].wave_size
=
2631 radv_get_wave_size(pipeline
->device
, pStages
[i
],
2633 infos
[i
].ballot_bit_size
=
2634 radv_get_ballot_bit_size(pipeline
->device
,
2642 merge_tess_info(struct shader_info
*tes_info
,
2643 const struct shader_info
*tcs_info
)
2645 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2647 * "PointMode. Controls generation of points rather than triangles
2648 * or lines. This functionality defaults to disabled, and is
2649 * enabled if either shader stage includes the execution mode.
2651 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2652 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2653 * and OutputVertices, it says:
2655 * "One mode must be set in at least one of the tessellation
2658 * So, the fields can be set in either the TCS or TES, but they must
2659 * agree if set in both. Our backend looks at TES, so bitwise-or in
2660 * the values from the TCS.
2662 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
2663 tes_info
->tess
.tcs_vertices_out
== 0 ||
2664 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
2665 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
2667 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2668 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2669 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
2670 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
2672 assert(tcs_info
->tess
.primitive_mode
== 0 ||
2673 tes_info
->tess
.primitive_mode
== 0 ||
2674 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
2675 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
2676 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
2677 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
2681 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT
*ext
)
2686 if (ext
->pPipelineCreationFeedback
) {
2687 ext
->pPipelineCreationFeedback
->flags
= 0;
2688 ext
->pPipelineCreationFeedback
->duration
= 0;
2691 for (unsigned i
= 0; i
< ext
->pipelineStageCreationFeedbackCount
; ++i
) {
2692 ext
->pPipelineStageCreationFeedbacks
[i
].flags
= 0;
2693 ext
->pPipelineStageCreationFeedbacks
[i
].duration
= 0;
2698 void radv_start_feedback(VkPipelineCreationFeedbackEXT
*feedback
)
2703 feedback
->duration
-= radv_get_current_time();
2704 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
2708 void radv_stop_feedback(VkPipelineCreationFeedbackEXT
*feedback
, bool cache_hit
)
2713 feedback
->duration
+= radv_get_current_time();
2714 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
|
2715 (cache_hit
? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
: 0);
2718 VkResult
radv_create_shaders(struct radv_pipeline
*pipeline
,
2719 struct radv_device
*device
,
2720 struct radv_pipeline_cache
*cache
,
2721 const struct radv_pipeline_key
*key
,
2722 const VkPipelineShaderStageCreateInfo
**pStages
,
2723 const VkPipelineCreateFlags flags
,
2724 VkPipelineCreationFeedbackEXT
*pipeline_feedback
,
2725 VkPipelineCreationFeedbackEXT
**stage_feedbacks
)
2727 struct radv_shader_module fs_m
= {0};
2728 struct radv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
2729 nir_shader
*nir
[MESA_SHADER_STAGES
] = {0};
2730 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2731 struct radv_shader_variant_key keys
[MESA_SHADER_STAGES
] = {{{{{0}}}}};
2732 struct radv_shader_info infos
[MESA_SHADER_STAGES
] = {0};
2733 unsigned char hash
[20], gs_copy_hash
[20];
2734 bool keep_executable_info
= (flags
& VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
) || device
->keep_shader_info
;
2735 bool keep_statistic_info
= (flags
& VK_PIPELINE_CREATE_CAPTURE_STATISTICS_BIT_KHR
) ||
2736 (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SHADER_STATS
) ||
2737 device
->keep_shader_info
;
2739 radv_start_feedback(pipeline_feedback
);
2741 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2743 modules
[i
] = radv_shader_module_from_handle(pStages
[i
]->module
);
2744 if (modules
[i
]->nir
)
2745 _mesa_sha1_compute(modules
[i
]->nir
->info
.name
,
2746 strlen(modules
[i
]->nir
->info
.name
),
2749 pipeline
->active_stages
|= mesa_to_vk_shader_stage(i
);
2753 radv_hash_shaders(hash
, pStages
, pipeline
->layout
, key
, get_hash_flags(device
));
2754 memcpy(gs_copy_hash
, hash
, 20);
2755 gs_copy_hash
[0] ^= 1;
2757 bool found_in_application_cache
= true;
2758 if (modules
[MESA_SHADER_GEOMETRY
] && !keep_executable_info
&& !keep_statistic_info
) {
2759 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2760 radv_create_shader_variants_from_pipeline_cache(device
, cache
, gs_copy_hash
, variants
,
2761 &found_in_application_cache
);
2762 pipeline
->gs_copy_shader
= variants
[MESA_SHADER_GEOMETRY
];
2765 if (!keep_executable_info
&& !keep_statistic_info
&&
2766 radv_create_shader_variants_from_pipeline_cache(device
, cache
, hash
, pipeline
->shaders
,
2767 &found_in_application_cache
) &&
2768 (!modules
[MESA_SHADER_GEOMETRY
] || pipeline
->gs_copy_shader
)) {
2769 radv_stop_feedback(pipeline_feedback
, found_in_application_cache
);
2773 if (flags
& VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_EXT
) {
2774 radv_stop_feedback(pipeline_feedback
, found_in_application_cache
);
2775 return VK_PIPELINE_COMPILE_REQUIRED_EXT
;
2778 if (!modules
[MESA_SHADER_FRAGMENT
] && !modules
[MESA_SHADER_COMPUTE
]) {
2780 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
2781 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "noop_fs");
2782 fs_m
.nir
= fs_b
.shader
;
2783 modules
[MESA_SHADER_FRAGMENT
] = &fs_m
;
2786 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2787 const VkPipelineShaderStageCreateInfo
*stage
= pStages
[i
];
2788 unsigned subgroup_size
= 64, ballot_bit_size
= 64;
2793 radv_start_feedback(stage_feedbacks
[i
]);
2795 if (key
->compute_subgroup_size
) {
2796 /* Only compute shaders currently support requiring a
2797 * specific subgroup size.
2799 assert(i
== MESA_SHADER_COMPUTE
);
2800 subgroup_size
= key
->compute_subgroup_size
;
2801 ballot_bit_size
= key
->compute_subgroup_size
;
2804 nir
[i
] = radv_shader_compile_to_nir(device
, modules
[i
],
2805 stage
? stage
->pName
: "main", i
,
2806 stage
? stage
->pSpecializationInfo
: NULL
,
2807 flags
, pipeline
->layout
,
2808 subgroup_size
, ballot_bit_size
);
2810 /* We don't want to alter meta shaders IR directly so clone it
2813 if (nir
[i
]->info
.name
) {
2814 nir
[i
] = nir_shader_clone(NULL
, nir
[i
]);
2817 radv_stop_feedback(stage_feedbacks
[i
], false);
2820 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2821 nir_lower_patch_vertices(nir
[MESA_SHADER_TESS_EVAL
], nir
[MESA_SHADER_TESS_CTRL
]->info
.tess
.tcs_vertices_out
, NULL
);
2822 merge_tess_info(&nir
[MESA_SHADER_TESS_EVAL
]->info
, &nir
[MESA_SHADER_TESS_CTRL
]->info
);
2825 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
2826 radv_link_shaders(pipeline
, nir
);
2828 radv_set_linked_driver_locations(pipeline
, nir
, infos
);
2830 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2832 /* do this again since information such as outputs_read can be out-of-date */
2833 nir_shader_gather_info(nir
[i
], nir_shader_get_entrypoint(nir
[i
]));
2835 if (device
->physical_device
->use_aco
) {
2836 NIR_PASS_V(nir
[i
], nir_lower_non_uniform_access
,
2837 nir_lower_non_uniform_ubo_access
|
2838 nir_lower_non_uniform_ssbo_access
|
2839 nir_lower_non_uniform_texture_access
|
2840 nir_lower_non_uniform_image_access
);
2842 NIR_PASS_V(nir
[i
], nir_lower_bool_to_int32
);
2846 if (nir
[MESA_SHADER_FRAGMENT
])
2847 radv_lower_fs_io(nir
[MESA_SHADER_FRAGMENT
]);
2849 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2850 if (radv_can_dump_shader(device
, modules
[i
], false))
2851 nir_print_shader(nir
[i
], stderr
);
2854 radv_fill_shader_keys(device
, keys
, key
, nir
);
2856 radv_fill_shader_info(pipeline
, pStages
, keys
, infos
, nir
);
2858 if ((nir
[MESA_SHADER_VERTEX
] &&
2859 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) ||
2860 (nir
[MESA_SHADER_TESS_EVAL
] &&
2861 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
)) {
2862 struct gfx10_ngg_info
*ngg_info
;
2864 if (nir
[MESA_SHADER_GEOMETRY
])
2865 ngg_info
= &infos
[MESA_SHADER_GEOMETRY
].ngg_info
;
2866 else if (nir
[MESA_SHADER_TESS_CTRL
])
2867 ngg_info
= &infos
[MESA_SHADER_TESS_EVAL
].ngg_info
;
2869 ngg_info
= &infos
[MESA_SHADER_VERTEX
].ngg_info
;
2871 gfx10_get_ngg_info(key
, pipeline
, nir
, infos
, ngg_info
);
2872 } else if (nir
[MESA_SHADER_GEOMETRY
]) {
2873 struct gfx9_gs_info
*gs_info
=
2874 &infos
[MESA_SHADER_GEOMETRY
].gs_ring_info
;
2876 gfx9_get_gs_info(key
, pipeline
, nir
, infos
, gs_info
);
2879 if(modules
[MESA_SHADER_GEOMETRY
]) {
2880 struct radv_shader_binary
*gs_copy_binary
= NULL
;
2881 if (!pipeline
->gs_copy_shader
&&
2882 !radv_pipeline_has_ngg(pipeline
)) {
2883 struct radv_shader_info info
= {};
2884 struct radv_shader_variant_key key
= {};
2886 key
.has_multiview_view_index
=
2887 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
;
2889 radv_nir_shader_info_pass(nir
[MESA_SHADER_GEOMETRY
],
2890 pipeline
->layout
, &key
,
2891 &info
, pipeline
->device
->physical_device
->use_aco
);
2892 info
.wave_size
= 64; /* Wave32 not supported. */
2893 info
.ballot_bit_size
= 64;
2895 pipeline
->gs_copy_shader
= radv_create_gs_copy_shader(
2896 device
, nir
[MESA_SHADER_GEOMETRY
], &info
,
2897 &gs_copy_binary
, keep_executable_info
, keep_statistic_info
,
2898 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
);
2901 if (!keep_executable_info
&& !keep_statistic_info
&& pipeline
->gs_copy_shader
) {
2902 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2903 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2905 binaries
[MESA_SHADER_GEOMETRY
] = gs_copy_binary
;
2906 variants
[MESA_SHADER_GEOMETRY
] = pipeline
->gs_copy_shader
;
2908 radv_pipeline_cache_insert_shaders(device
, cache
,
2913 free(gs_copy_binary
);
2916 if (nir
[MESA_SHADER_FRAGMENT
]) {
2917 if (!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]) {
2918 radv_start_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
]);
2920 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] =
2921 radv_shader_variant_compile(device
, modules
[MESA_SHADER_FRAGMENT
], &nir
[MESA_SHADER_FRAGMENT
], 1,
2922 pipeline
->layout
, keys
+ MESA_SHADER_FRAGMENT
,
2923 infos
+ MESA_SHADER_FRAGMENT
,
2924 keep_executable_info
, keep_statistic_info
,
2925 &binaries
[MESA_SHADER_FRAGMENT
]);
2927 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
], false);
2931 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_TESS_CTRL
]) {
2932 if (!pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]) {
2933 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2934 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2935 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2937 radv_start_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
]);
2939 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_TESS_CTRL
], combined_nir
, 2,
2941 &key
, &infos
[MESA_SHADER_TESS_CTRL
], keep_executable_info
,
2942 keep_statistic_info
, &binaries
[MESA_SHADER_TESS_CTRL
]);
2944 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
], false);
2946 modules
[MESA_SHADER_VERTEX
] = NULL
;
2947 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2948 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2951 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_GEOMETRY
]) {
2952 gl_shader_stage pre_stage
= modules
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2953 if (!pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
2954 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2956 radv_start_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
]);
2958 pipeline
->shaders
[MESA_SHADER_GEOMETRY
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_GEOMETRY
], combined_nir
, 2,
2960 &keys
[pre_stage
], &infos
[MESA_SHADER_GEOMETRY
], keep_executable_info
,
2961 keep_statistic_info
, &binaries
[MESA_SHADER_GEOMETRY
]);
2963 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
], false);
2965 modules
[pre_stage
] = NULL
;
2968 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2969 if(modules
[i
] && !pipeline
->shaders
[i
]) {
2970 if (i
== MESA_SHADER_TESS_CTRL
) {
2971 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.ls_outputs_written
);
2973 if (i
== MESA_SHADER_TESS_EVAL
) {
2974 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2975 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2978 radv_start_feedback(stage_feedbacks
[i
]);
2980 pipeline
->shaders
[i
] = radv_shader_variant_compile(device
, modules
[i
], &nir
[i
], 1,
2982 keys
+ i
, infos
+ i
, keep_executable_info
,
2983 keep_statistic_info
, &binaries
[i
]);
2985 radv_stop_feedback(stage_feedbacks
[i
], false);
2989 if (!keep_executable_info
&& !keep_statistic_info
) {
2990 radv_pipeline_cache_insert_shaders(device
, cache
, hash
, pipeline
->shaders
,
2994 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2997 ralloc_free(nir
[i
]);
2999 if (radv_can_dump_shader_stats(device
, modules
[i
]))
3000 radv_shader_dump_stats(device
,
3001 pipeline
->shaders
[i
],
3007 ralloc_free(fs_m
.nir
);
3009 radv_stop_feedback(pipeline_feedback
, false);
3014 radv_pipeline_stage_to_user_data_0(struct radv_pipeline
*pipeline
,
3015 gl_shader_stage stage
, enum chip_class chip_class
)
3017 bool has_gs
= radv_pipeline_has_gs(pipeline
);
3018 bool has_tess
= radv_pipeline_has_tess(pipeline
);
3019 bool has_ngg
= radv_pipeline_has_ngg(pipeline
);
3022 case MESA_SHADER_FRAGMENT
:
3023 return R_00B030_SPI_SHADER_USER_DATA_PS_0
;
3024 case MESA_SHADER_VERTEX
:
3026 if (chip_class
>= GFX10
) {
3027 return R_00B430_SPI_SHADER_USER_DATA_HS_0
;
3028 } else if (chip_class
== GFX9
) {
3029 return R_00B430_SPI_SHADER_USER_DATA_LS_0
;
3031 return R_00B530_SPI_SHADER_USER_DATA_LS_0
;
3037 if (chip_class
>= GFX10
) {
3038 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3040 return R_00B330_SPI_SHADER_USER_DATA_ES_0
;
3045 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3047 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3048 case MESA_SHADER_GEOMETRY
:
3049 return chip_class
== GFX9
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
3050 R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3051 case MESA_SHADER_COMPUTE
:
3052 return R_00B900_COMPUTE_USER_DATA_0
;
3053 case MESA_SHADER_TESS_CTRL
:
3054 return chip_class
== GFX9
? R_00B430_SPI_SHADER_USER_DATA_LS_0
:
3055 R_00B430_SPI_SHADER_USER_DATA_HS_0
;
3056 case MESA_SHADER_TESS_EVAL
:
3058 return chip_class
>= GFX10
? R_00B230_SPI_SHADER_USER_DATA_GS_0
:
3059 R_00B330_SPI_SHADER_USER_DATA_ES_0
;
3060 } else if (has_ngg
) {
3061 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3063 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3066 unreachable("unknown shader");
3070 struct radv_bin_size_entry
{
3076 radv_gfx9_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3078 static const struct radv_bin_size_entry color_size_table
[][3][9] = {
3082 /* One shader engine */
3088 { UINT_MAX
, { 0, 0}},
3091 /* Two shader engines */
3097 { UINT_MAX
, { 0, 0}},
3100 /* Four shader engines */
3105 { UINT_MAX
, { 0, 0}},
3111 /* One shader engine */
3117 { UINT_MAX
, { 0, 0}},
3120 /* Two shader engines */
3126 { UINT_MAX
, { 0, 0}},
3129 /* Four shader engines */
3136 { UINT_MAX
, { 0, 0}},
3142 /* One shader engine */
3149 { UINT_MAX
, { 0, 0}},
3152 /* Two shader engines */
3160 { UINT_MAX
, { 0, 0}},
3163 /* Four shader engines */
3171 { UINT_MAX
, { 0, 0}},
3175 static const struct radv_bin_size_entry ds_size_table
[][3][9] = {
3179 // One shader engine
3186 { UINT_MAX
, { 0, 0}},
3189 // Two shader engines
3197 { UINT_MAX
, { 0, 0}},
3200 // Four shader engines
3208 { UINT_MAX
, { 0, 0}},
3214 // One shader engine
3222 { UINT_MAX
, { 0, 0}},
3225 // Two shader engines
3234 { UINT_MAX
, { 0, 0}},
3237 // Four shader engines
3246 { UINT_MAX
, { 0, 0}},
3252 // One shader engine
3260 { UINT_MAX
, { 0, 0}},
3263 // Two shader engines
3272 { UINT_MAX
, { 0, 0}},
3275 // Four shader engines
3283 { UINT_MAX
, { 0, 0}},
3288 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3289 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3290 VkExtent2D extent
= {512, 512};
3292 unsigned log_num_rb_per_se
=
3293 util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.num_render_backends
/
3294 pipeline
->device
->physical_device
->rad_info
.max_se
);
3295 unsigned log_num_se
= util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.max_se
);
3297 unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3298 unsigned ps_iter_samples
= 1u << G_028804_PS_ITER_SAMPLES(pipeline
->graphics
.ms
.db_eqaa
);
3299 unsigned effective_samples
= total_samples
;
3300 unsigned color_bytes_per_pixel
= 0;
3302 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3303 radv_pipeline_get_color_blend_state(pCreateInfo
);
3305 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3306 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3309 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3312 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3313 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3316 /* MSAA images typically don't use all samples all the time. */
3317 if (effective_samples
>= 2 && ps_iter_samples
<= 1)
3318 effective_samples
= 2;
3319 color_bytes_per_pixel
*= effective_samples
;
3322 const struct radv_bin_size_entry
*color_entry
= color_size_table
[log_num_rb_per_se
][log_num_se
];
3323 while(color_entry
[1].bpp
<= color_bytes_per_pixel
)
3326 extent
= color_entry
->extent
;
3328 if (subpass
->depth_stencil_attachment
) {
3329 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3331 /* Coefficients taken from AMDVLK */
3332 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3333 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3334 unsigned ds_bytes_per_pixel
= 4 * (depth_coeff
+ stencil_coeff
) * total_samples
;
3336 const struct radv_bin_size_entry
*ds_entry
= ds_size_table
[log_num_rb_per_se
][log_num_se
];
3337 while(ds_entry
[1].bpp
<= ds_bytes_per_pixel
)
3340 if (ds_entry
->extent
.width
* ds_entry
->extent
.height
< extent
.width
* extent
.height
)
3341 extent
= ds_entry
->extent
;
3348 radv_gfx10_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3350 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3351 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3352 VkExtent2D extent
= {512, 512};
3354 const unsigned db_tag_size
= 64;
3355 const unsigned db_tag_count
= 312;
3356 const unsigned color_tag_size
= 1024;
3357 const unsigned color_tag_count
= 31;
3358 const unsigned fmask_tag_size
= 256;
3359 const unsigned fmask_tag_count
= 44;
3361 const unsigned rb_count
= pipeline
->device
->physical_device
->rad_info
.num_render_backends
;
3362 const unsigned pipe_count
= MAX2(rb_count
, pipeline
->device
->physical_device
->rad_info
.num_sdp_interfaces
);
3364 const unsigned db_tag_part
= (db_tag_count
* rb_count
/ pipe_count
) * db_tag_size
* pipe_count
;
3365 const unsigned color_tag_part
= (color_tag_count
* rb_count
/ pipe_count
) * color_tag_size
* pipe_count
;
3366 const unsigned fmask_tag_part
= (fmask_tag_count
* rb_count
/ pipe_count
) * fmask_tag_size
* pipe_count
;
3368 const unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3369 const unsigned samples_log
= util_logbase2_ceil(total_samples
);
3371 unsigned color_bytes_per_pixel
= 0;
3372 unsigned fmask_bytes_per_pixel
= 0;
3374 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3375 radv_pipeline_get_color_blend_state(pCreateInfo
);
3377 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3378 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3381 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3384 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3385 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3387 if (total_samples
> 1) {
3388 assert(samples_log
<= 3);
3389 const unsigned fmask_array
[] = {0, 1, 1, 4};
3390 fmask_bytes_per_pixel
+= fmask_array
[samples_log
];
3394 color_bytes_per_pixel
*= total_samples
;
3396 color_bytes_per_pixel
= MAX2(color_bytes_per_pixel
, 1);
3398 const unsigned color_pixel_count_log
= util_logbase2(color_tag_part
/ color_bytes_per_pixel
);
3399 extent
.width
= 1ull << ((color_pixel_count_log
+ 1) / 2);
3400 extent
.height
= 1ull << (color_pixel_count_log
/ 2);
3402 if (fmask_bytes_per_pixel
) {
3403 const unsigned fmask_pixel_count_log
= util_logbase2(fmask_tag_part
/ fmask_bytes_per_pixel
);
3405 const VkExtent2D fmask_extent
= (VkExtent2D
){
3406 .width
= 1ull << ((fmask_pixel_count_log
+ 1) / 2),
3407 .height
= 1ull << (color_pixel_count_log
/ 2)
3410 if (fmask_extent
.width
* fmask_extent
.height
< extent
.width
* extent
.height
)
3411 extent
= fmask_extent
;
3414 if (subpass
->depth_stencil_attachment
) {
3415 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3417 /* Coefficients taken from AMDVLK */
3418 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3419 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3420 unsigned db_bytes_per_pixel
= (depth_coeff
+ stencil_coeff
) * total_samples
;
3422 const unsigned db_pixel_count_log
= util_logbase2(db_tag_part
/ db_bytes_per_pixel
);
3424 const VkExtent2D db_extent
= (VkExtent2D
){
3425 .width
= 1ull << ((db_pixel_count_log
+ 1) / 2),
3426 .height
= 1ull << (color_pixel_count_log
/ 2)
3429 if (db_extent
.width
* db_extent
.height
< extent
.width
* extent
.height
)
3433 extent
.width
= MAX2(extent
.width
, 128);
3434 extent
.height
= MAX2(extent
.width
, 64);
3440 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3441 struct radv_pipeline
*pipeline
,
3442 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3444 uint32_t pa_sc_binner_cntl_0
=
3445 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC
) |
3446 S_028C44_DISABLE_START_OF_PRIM(1);
3447 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3449 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3450 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3451 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3452 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3453 radv_pipeline_get_color_blend_state(pCreateInfo
);
3454 unsigned min_bytes_per_pixel
= 0;
3457 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3458 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3461 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3464 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3465 unsigned bytes
= vk_format_get_blocksize(format
);
3466 if (!min_bytes_per_pixel
|| bytes
< min_bytes_per_pixel
)
3467 min_bytes_per_pixel
= bytes
;
3471 pa_sc_binner_cntl_0
=
3472 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC
) |
3473 S_028C44_BIN_SIZE_X(0) |
3474 S_028C44_BIN_SIZE_Y(0) |
3475 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3476 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel
<= 4 ? 2 : 1) | /* 128 or 64 */
3477 S_028C44_DISABLE_START_OF_PRIM(1);
3480 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3481 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3484 struct radv_binning_settings
3485 radv_get_binning_settings(const struct radv_physical_device
*pdev
)
3487 struct radv_binning_settings settings
;
3488 if (pdev
->rad_info
.has_dedicated_vram
) {
3489 if (pdev
->rad_info
.num_render_backends
> 4) {
3490 settings
.context_states_per_bin
= 1;
3491 settings
.persistent_states_per_bin
= 1;
3493 settings
.context_states_per_bin
= 3;
3494 settings
.persistent_states_per_bin
= 8;
3496 settings
.fpovs_per_batch
= 63;
3498 /* The context states are affected by the scissor bug. */
3499 settings
.context_states_per_bin
= 6;
3500 /* 32 causes hangs for RAVEN. */
3501 settings
.persistent_states_per_bin
= 16;
3502 settings
.fpovs_per_batch
= 63;
3505 if (pdev
->rad_info
.has_gfx9_scissor_bug
)
3506 settings
.context_states_per_bin
= 1;
3512 radv_pipeline_generate_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3513 struct radv_pipeline
*pipeline
,
3514 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3515 const struct radv_blend_state
*blend
)
3517 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
3520 VkExtent2D bin_size
;
3521 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3522 bin_size
= radv_gfx10_compute_bin_size(pipeline
, pCreateInfo
);
3523 } else if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3524 bin_size
= radv_gfx9_compute_bin_size(pipeline
, pCreateInfo
);
3526 unreachable("Unhandled generation for binning bin size calculation");
3528 if (pipeline
->device
->pbb_allowed
&& bin_size
.width
&& bin_size
.height
) {
3529 struct radv_binning_settings settings
=
3530 radv_get_binning_settings(pipeline
->device
->physical_device
);
3532 bool disable_start_of_prim
= true;
3533 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3535 const struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3537 if (pipeline
->device
->dfsm_allowed
&& ps
&&
3538 !ps
->info
.ps
.can_discard
&&
3539 !ps
->info
.ps
.writes_memory
&&
3540 blend
->cb_target_enabled_4bit
) {
3541 db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_AUTO
);
3542 disable_start_of_prim
= (blend
->blend_enable_4bit
& blend
->cb_target_enabled_4bit
) != 0;
3545 const uint32_t pa_sc_binner_cntl_0
=
3546 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED
) |
3547 S_028C44_BIN_SIZE_X(bin_size
.width
== 16) |
3548 S_028C44_BIN_SIZE_Y(bin_size
.height
== 16) |
3549 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size
.width
, 32)) - 5) |
3550 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size
.height
, 32)) - 5) |
3551 S_028C44_CONTEXT_STATES_PER_BIN(settings
.context_states_per_bin
- 1) |
3552 S_028C44_PERSISTENT_STATES_PER_BIN(settings
.persistent_states_per_bin
- 1) |
3553 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim
) |
3554 S_028C44_FPOVS_PER_BATCH(settings
.fpovs_per_batch
) |
3555 S_028C44_OPTIMAL_BIN_SELECTION(1);
3557 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3558 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3560 radv_pipeline_generate_disabled_binning_state(ctx_cs
, pipeline
, pCreateInfo
);
3565 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf
*ctx_cs
,
3566 struct radv_pipeline
*pipeline
,
3567 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3568 const struct radv_graphics_pipeline_create_info
*extra
)
3570 const VkPipelineDepthStencilStateCreateInfo
*vkds
= radv_pipeline_get_depth_stencil_state(pCreateInfo
);
3571 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3572 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3573 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3574 struct radv_render_pass_attachment
*attachment
= NULL
;
3575 uint32_t db_depth_control
= 0, db_stencil_control
= 0;
3576 uint32_t db_render_control
= 0, db_render_override2
= 0;
3577 uint32_t db_render_override
= 0;
3579 if (subpass
->depth_stencil_attachment
)
3580 attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3582 bool has_depth_attachment
= attachment
&& vk_format_is_depth(attachment
->format
);
3583 bool has_stencil_attachment
= attachment
&& vk_format_is_stencil(attachment
->format
);
3585 if (vkds
&& has_depth_attachment
) {
3586 db_depth_control
= S_028800_Z_ENABLE(vkds
->depthTestEnable
? 1 : 0) |
3587 S_028800_Z_WRITE_ENABLE(vkds
->depthWriteEnable
? 1 : 0) |
3588 S_028800_ZFUNC(vkds
->depthCompareOp
) |
3589 S_028800_DEPTH_BOUNDS_ENABLE(vkds
->depthBoundsTestEnable
? 1 : 0);
3591 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3592 db_render_override2
|= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment
->samples
> 2);
3595 if (has_stencil_attachment
&& vkds
&& vkds
->stencilTestEnable
) {
3596 db_depth_control
|= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3597 db_depth_control
|= S_028800_STENCILFUNC(vkds
->front
.compareOp
);
3598 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds
->front
.failOp
));
3599 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds
->front
.passOp
));
3600 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds
->front
.depthFailOp
));
3602 db_depth_control
|= S_028800_STENCILFUNC_BF(vkds
->back
.compareOp
);
3603 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds
->back
.failOp
));
3604 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds
->back
.passOp
));
3605 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds
->back
.depthFailOp
));
3608 if (attachment
&& extra
) {
3609 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(extra
->db_depth_clear
);
3610 db_render_control
|= S_028000_STENCIL_CLEAR_ENABLE(extra
->db_stencil_clear
);
3612 db_render_control
|= S_028000_RESUMMARIZE_ENABLE(extra
->resummarize_enable
);
3613 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(extra
->depth_compress_disable
);
3614 db_render_control
|= S_028000_STENCIL_COMPRESS_DISABLE(extra
->stencil_compress_disable
);
3615 db_render_override2
|= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra
->db_depth_disable_expclear
);
3616 db_render_override2
|= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra
->db_stencil_disable_expclear
);
3619 db_render_override
|= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
3620 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
3622 if (!pCreateInfo
->pRasterizationState
->depthClampEnable
&&
3623 ps
->info
.ps
.writes_z
) {
3624 /* From VK_EXT_depth_range_unrestricted spec:
3626 * "The behavior described in Primitive Clipping still applies.
3627 * If depth clamping is disabled the depth values are still
3628 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3629 * depth clamping is enabled the above equation is ignored and
3630 * the depth values are instead clamped to the VkViewport
3631 * minDepth and maxDepth values, which in the case of this
3632 * extension can be outside of the 0.0 to 1.0 range."
3634 db_render_override
|= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3637 radeon_set_context_reg(ctx_cs
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
3638 radeon_set_context_reg(ctx_cs
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
3640 radeon_set_context_reg(ctx_cs
, R_028000_DB_RENDER_CONTROL
, db_render_control
);
3641 radeon_set_context_reg(ctx_cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
3642 radeon_set_context_reg(ctx_cs
, R_028010_DB_RENDER_OVERRIDE2
, db_render_override2
);
3646 radv_pipeline_generate_blend_state(struct radeon_cmdbuf
*ctx_cs
,
3647 struct radv_pipeline
*pipeline
,
3648 const struct radv_blend_state
*blend
)
3650 radeon_set_context_reg_seq(ctx_cs
, R_028780_CB_BLEND0_CONTROL
, 8);
3651 radeon_emit_array(ctx_cs
, blend
->cb_blend_control
,
3653 radeon_set_context_reg(ctx_cs
, R_028808_CB_COLOR_CONTROL
, blend
->cb_color_control
);
3654 radeon_set_context_reg(ctx_cs
, R_028B70_DB_ALPHA_TO_MASK
, blend
->db_alpha_to_mask
);
3656 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
3658 radeon_set_context_reg_seq(ctx_cs
, R_028760_SX_MRT0_BLEND_OPT
, 8);
3659 radeon_emit_array(ctx_cs
, blend
->sx_mrt_blend_opt
, 8);
3662 radeon_set_context_reg(ctx_cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
3664 radeon_set_context_reg(ctx_cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
3665 radeon_set_context_reg(ctx_cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
3667 pipeline
->graphics
.col_format
= blend
->spi_shader_col_format
;
3668 pipeline
->graphics
.cb_target_mask
= blend
->cb_target_mask
;
3671 static const VkConservativeRasterizationModeEXT
3672 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo
*pCreateInfo
)
3674 const VkPipelineRasterizationConservativeStateCreateInfoEXT
*conservative_raster
=
3675 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT
);
3677 if (!conservative_raster
)
3678 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
;
3679 return conservative_raster
->conservativeRasterizationMode
;
3683 radv_pipeline_generate_raster_state(struct radeon_cmdbuf
*ctx_cs
,
3684 struct radv_pipeline
*pipeline
,
3685 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3687 const VkPipelineRasterizationStateCreateInfo
*vkraster
= pCreateInfo
->pRasterizationState
;
3688 const VkConservativeRasterizationModeEXT mode
=
3689 radv_get_conservative_raster_mode(vkraster
);
3690 uint32_t pa_sc_conservative_rast
= S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3691 bool depth_clip_disable
= vkraster
->depthClampEnable
;
3693 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*depth_clip_state
=
3694 vk_find_struct_const(vkraster
->pNext
, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
3695 if (depth_clip_state
) {
3696 depth_clip_disable
= !depth_clip_state
->depthClipEnable
;
3699 radeon_set_context_reg(ctx_cs
, R_028810_PA_CL_CLIP_CNTL
,
3700 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3701 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable
? 1 : 0) |
3702 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable
? 1 : 0) |
3703 S_028810_DX_RASTERIZATION_KILL(vkraster
->rasterizerDiscardEnable
? 1 : 0) |
3704 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3706 radeon_set_context_reg(ctx_cs
, R_0286D4_SPI_INTERP_CONTROL_0
,
3707 S_0286D4_FLAT_SHADE_ENA(1) |
3708 S_0286D4_PNT_SPRITE_ENA(1) |
3709 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
3710 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
3711 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
3712 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
3713 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3715 radeon_set_context_reg(ctx_cs
, R_028BE4_PA_SU_VTX_CNTL
,
3716 S_028BE4_PIX_CENTER(1) | // TODO verify
3717 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN
) |
3718 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
3720 radeon_set_context_reg(ctx_cs
, R_028814_PA_SU_SC_MODE_CNTL
,
3721 S_028814_FACE(vkraster
->frontFace
) |
3722 S_028814_CULL_FRONT(!!(vkraster
->cullMode
& VK_CULL_MODE_FRONT_BIT
)) |
3723 S_028814_CULL_BACK(!!(vkraster
->cullMode
& VK_CULL_MODE_BACK_BIT
)) |
3724 S_028814_POLY_MODE(vkraster
->polygonMode
!= VK_POLYGON_MODE_FILL
) |
3725 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3726 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3727 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3728 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3729 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster
->depthBiasEnable
? 1 : 0));
3731 /* Conservative rasterization. */
3732 if (mode
!= VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
) {
3733 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3735 ms
->pa_sc_aa_config
|= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3736 ms
->db_eqaa
|= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3737 S_028804_OVERRASTERIZATION_AMOUNT(4);
3739 pa_sc_conservative_rast
= S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3740 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3741 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3743 if (mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT
) {
3744 pa_sc_conservative_rast
|=
3745 S_028C4C_OVER_RAST_ENABLE(1) |
3746 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3747 S_028C4C_UNDER_RAST_ENABLE(0) |
3748 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3749 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3751 assert(mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT
);
3752 pa_sc_conservative_rast
|=
3753 S_028C4C_OVER_RAST_ENABLE(0) |
3754 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3755 S_028C4C_UNDER_RAST_ENABLE(1) |
3756 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3757 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3761 radeon_set_context_reg(ctx_cs
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
3762 pa_sc_conservative_rast
);
3767 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf
*ctx_cs
,
3768 struct radv_pipeline
*pipeline
)
3770 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3772 radeon_set_context_reg_seq(ctx_cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
3773 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[0]);
3774 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[1]);
3776 radeon_set_context_reg(ctx_cs
, R_028804_DB_EQAA
, ms
->db_eqaa
);
3777 radeon_set_context_reg(ctx_cs
, R_028A48_PA_SC_MODE_CNTL_0
, ms
->pa_sc_mode_cntl_0
);
3778 radeon_set_context_reg(ctx_cs
, R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
3779 radeon_set_context_reg(ctx_cs
, R_028BDC_PA_SC_LINE_CNTL
, ms
->pa_sc_line_cntl
);
3780 radeon_set_context_reg(ctx_cs
, R_028BE0_PA_SC_AA_CONFIG
, ms
->pa_sc_aa_config
);
3782 /* The exclusion bits can be set to improve rasterization efficiency
3783 * if no sample lies on the pixel boundary (-8 sample offset). It's
3784 * currently always TRUE because the driver doesn't support 16 samples.
3786 bool exclusion
= pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
3787 radeon_set_context_reg(ctx_cs
, R_02882C_PA_SU_PRIM_FILTER_CNTL
,
3788 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) |
3789 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3791 /* GFX9: Flush DFSM when the AA mode changes. */
3792 if (pipeline
->device
->dfsm_allowed
) {
3793 radeon_emit(ctx_cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3794 radeon_emit(ctx_cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3799 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf
*ctx_cs
,
3800 struct radv_pipeline
*pipeline
)
3802 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3803 const struct radv_shader_variant
*vs
=
3804 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] ?
3805 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] :
3806 pipeline
->shaders
[MESA_SHADER_VERTEX
];
3807 unsigned vgt_primitiveid_en
= 0;
3808 uint32_t vgt_gs_mode
= 0;
3810 if (radv_pipeline_has_ngg(pipeline
))
3813 if (radv_pipeline_has_gs(pipeline
)) {
3814 const struct radv_shader_variant
*gs
=
3815 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3817 vgt_gs_mode
= ac_vgt_gs_mode(gs
->info
.gs
.vertices_out
,
3818 pipeline
->device
->physical_device
->rad_info
.chip_class
);
3819 } else if (outinfo
->export_prim_id
|| vs
->info
.uses_prim_id
) {
3820 vgt_gs_mode
= S_028A40_MODE(V_028A40_GS_SCENARIO_A
);
3821 vgt_primitiveid_en
|= S_028A84_PRIMITIVEID_EN(1);
3824 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
, vgt_primitiveid_en
);
3825 radeon_set_context_reg(ctx_cs
, R_028A40_VGT_GS_MODE
, vgt_gs_mode
);
3829 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf
*ctx_cs
,
3830 struct radeon_cmdbuf
*cs
,
3831 struct radv_pipeline
*pipeline
,
3832 struct radv_shader_variant
*shader
)
3834 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3836 radeon_set_sh_reg_seq(cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
3837 radeon_emit(cs
, va
>> 8);
3838 radeon_emit(cs
, S_00B124_MEM_BASE(va
>> 40));
3839 radeon_emit(cs
, shader
->config
.rsrc1
);
3840 radeon_emit(cs
, shader
->config
.rsrc2
);
3842 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3843 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3844 clip_dist_mask
= outinfo
->clip_dist_mask
;
3845 cull_dist_mask
= outinfo
->cull_dist_mask
;
3846 total_mask
= clip_dist_mask
| cull_dist_mask
;
3847 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3848 outinfo
->writes_layer
||
3849 outinfo
->writes_viewport_index
;
3850 unsigned spi_vs_out_config
, nparams
;
3852 /* VS is required to export at least one param. */
3853 nparams
= MAX2(outinfo
->param_exports
, 1);
3854 spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
3856 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3857 spi_vs_out_config
|= S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0);
3860 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
, spi_vs_out_config
);
3862 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3863 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3864 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3865 V_02870C_SPI_SHADER_4COMP
:
3866 V_02870C_SPI_SHADER_NONE
) |
3867 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3868 V_02870C_SPI_SHADER_4COMP
:
3869 V_02870C_SPI_SHADER_NONE
) |
3870 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3871 V_02870C_SPI_SHADER_4COMP
:
3872 V_02870C_SPI_SHADER_NONE
));
3874 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
3875 S_028818_VTX_W0_FMT(1) |
3876 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3877 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3878 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3880 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3881 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3882 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3883 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3884 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3885 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3886 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3887 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3888 cull_dist_mask
<< 8 |
3891 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
3892 radeon_set_context_reg(ctx_cs
, R_028AB4_VGT_REUSE_OFF
,
3893 outinfo
->writes_viewport_index
);
3897 radv_pipeline_generate_hw_es(struct radeon_cmdbuf
*cs
,
3898 struct radv_pipeline
*pipeline
,
3899 struct radv_shader_variant
*shader
)
3901 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3903 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
3904 radeon_emit(cs
, va
>> 8);
3905 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3906 radeon_emit(cs
, shader
->config
.rsrc1
);
3907 radeon_emit(cs
, shader
->config
.rsrc2
);
3911 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf
*cs
,
3912 struct radv_pipeline
*pipeline
,
3913 struct radv_shader_variant
*shader
,
3914 const struct radv_tessellation_state
*tess
)
3916 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3917 uint32_t rsrc2
= shader
->config
.rsrc2
;
3919 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
3920 radeon_emit(cs
, va
>> 8);
3921 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
3923 rsrc2
|= S_00B52C_LDS_SIZE(tess
->lds_size
);
3924 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX7
&&
3925 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
3926 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
3928 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
3929 radeon_emit(cs
, shader
->config
.rsrc1
);
3930 radeon_emit(cs
, rsrc2
);
3934 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf
*ctx_cs
,
3935 struct radeon_cmdbuf
*cs
,
3936 struct radv_pipeline
*pipeline
,
3937 struct radv_shader_variant
*shader
)
3939 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3940 gl_shader_stage es_type
=
3941 radv_pipeline_has_tess(pipeline
) ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
3942 struct radv_shader_variant
*es
=
3943 es_type
== MESA_SHADER_TESS_EVAL
? pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] : pipeline
->shaders
[MESA_SHADER_VERTEX
];
3944 const struct gfx10_ngg_info
*ngg_state
= &shader
->info
.ngg_info
;
3946 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
3947 radeon_emit(cs
, va
>> 8);
3948 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3949 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
3950 radeon_emit(cs
, shader
->config
.rsrc1
);
3951 radeon_emit(cs
, shader
->config
.rsrc2
);
3953 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3954 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3955 clip_dist_mask
= outinfo
->clip_dist_mask
;
3956 cull_dist_mask
= outinfo
->cull_dist_mask
;
3957 total_mask
= clip_dist_mask
| cull_dist_mask
;
3958 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3959 outinfo
->writes_layer
||
3960 outinfo
->writes_viewport_index
;
3961 bool es_enable_prim_id
= outinfo
->export_prim_id
||
3962 (es
&& es
->info
.uses_prim_id
);
3963 bool break_wave_at_eoi
= false;
3967 if (es_type
== MESA_SHADER_TESS_EVAL
) {
3968 struct radv_shader_variant
*gs
=
3969 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3971 if (es_enable_prim_id
|| (gs
&& gs
->info
.uses_prim_id
))
3972 break_wave_at_eoi
= true;
3975 nparams
= MAX2(outinfo
->param_exports
, 1);
3976 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
3977 S_0286C4_VS_EXPORT_COUNT(nparams
- 1) |
3978 S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0));
3980 radeon_set_context_reg(ctx_cs
, R_028708_SPI_SHADER_IDX_FORMAT
,
3981 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP
));
3982 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3983 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3984 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3985 V_02870C_SPI_SHADER_4COMP
:
3986 V_02870C_SPI_SHADER_NONE
) |
3987 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3988 V_02870C_SPI_SHADER_4COMP
:
3989 V_02870C_SPI_SHADER_NONE
) |
3990 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3991 V_02870C_SPI_SHADER_4COMP
:
3992 V_02870C_SPI_SHADER_NONE
));
3994 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
3995 S_028818_VTX_W0_FMT(1) |
3996 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3997 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3998 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3999 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
4000 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
4001 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
4002 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
4003 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
4004 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
4005 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
4006 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
4007 cull_dist_mask
<< 8 |
4010 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
,
4011 S_028A84_PRIMITIVEID_EN(es_enable_prim_id
) |
4012 S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo
->export_prim_id
));
4014 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
4015 ngg_state
->vgt_esgs_ring_itemsize
);
4017 /* NGG specific registers. */
4018 struct radv_shader_variant
*gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4019 uint32_t gs_num_invocations
= gs
? gs
->info
.gs
.invocations
: 1;
4021 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4022 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state
->hw_max_esverts
) |
4023 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state
->max_gsprims
) |
4024 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state
->max_gsprims
* gs_num_invocations
));
4025 radeon_set_context_reg(ctx_cs
, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP
,
4026 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state
->max_out_verts
));
4027 radeon_set_context_reg(ctx_cs
, R_028B4C_GE_NGG_SUBGRP_CNTL
,
4028 S_028B4C_PRIM_AMP_FACTOR(ngg_state
->prim_amp_factor
) |
4029 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
4030 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
4031 S_028B90_CNT(gs_num_invocations
) |
4032 S_028B90_ENABLE(gs_num_invocations
> 1) |
4033 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state
->max_vert_out_per_gs_instance
));
4035 /* User edge flags are set by the pos exports. If user edge flags are
4036 * not used, we must use hw-generated edge flags and pass them via
4037 * the prim export to prevent drawing lines on internal edges of
4038 * decomposed primitives (such as quads) with polygon mode = lines.
4040 * TODO: We should combine hw-generated edge flags with user edge
4041 * flags in the shader.
4043 radeon_set_context_reg(ctx_cs
, R_028838_PA_CL_NGG_CNTL
,
4044 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline
) &&
4045 !radv_pipeline_has_gs(pipeline
)));
4047 ge_cntl
= S_03096C_PRIM_GRP_SIZE(ngg_state
->max_gsprims
) |
4048 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
4049 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
);
4051 /* Bug workaround for a possible hang with non-tessellation cases.
4052 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
4054 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
4056 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX10
&&
4057 !radv_pipeline_has_tess(pipeline
) &&
4058 ngg_state
->hw_max_esverts
!= 256) {
4059 ge_cntl
&= C_03096C_VERT_GRP_SIZE
;
4061 if (ngg_state
->hw_max_esverts
> 5) {
4062 ge_cntl
|= S_03096C_VERT_GRP_SIZE(ngg_state
->hw_max_esverts
- 5);
4066 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
, ge_cntl
);
4070 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf
*cs
,
4071 struct radv_pipeline
*pipeline
,
4072 struct radv_shader_variant
*shader
,
4073 const struct radv_tessellation_state
*tess
)
4075 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
4077 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4078 unsigned hs_rsrc2
= shader
->config
.rsrc2
;
4080 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4081 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX10(tess
->lds_size
);
4083 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX9(tess
->lds_size
);
4086 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4087 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
4088 radeon_emit(cs
, va
>> 8);
4089 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
4091 radeon_set_sh_reg_seq(cs
, R_00B410_SPI_SHADER_PGM_LO_LS
, 2);
4092 radeon_emit(cs
, va
>> 8);
4093 radeon_emit(cs
, S_00B414_MEM_BASE(va
>> 40));
4096 radeon_set_sh_reg_seq(cs
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
, 2);
4097 radeon_emit(cs
, shader
->config
.rsrc1
);
4098 radeon_emit(cs
, hs_rsrc2
);
4100 radeon_set_sh_reg_seq(cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
4101 radeon_emit(cs
, va
>> 8);
4102 radeon_emit(cs
, S_00B424_MEM_BASE(va
>> 40));
4103 radeon_emit(cs
, shader
->config
.rsrc1
);
4104 radeon_emit(cs
, shader
->config
.rsrc2
);
4109 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf
*ctx_cs
,
4110 struct radeon_cmdbuf
*cs
,
4111 struct radv_pipeline
*pipeline
,
4112 const struct radv_tessellation_state
*tess
)
4114 struct radv_shader_variant
*vs
;
4116 /* Skip shaders merged into HS/GS */
4117 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
4121 if (vs
->info
.vs
.as_ls
)
4122 radv_pipeline_generate_hw_ls(cs
, pipeline
, vs
, tess
);
4123 else if (vs
->info
.vs
.as_es
)
4124 radv_pipeline_generate_hw_es(cs
, pipeline
, vs
);
4125 else if (vs
->info
.is_ngg
)
4126 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, vs
);
4128 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, vs
);
4132 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf
*ctx_cs
,
4133 struct radeon_cmdbuf
*cs
,
4134 struct radv_pipeline
*pipeline
,
4135 const struct radv_tessellation_state
*tess
)
4137 if (!radv_pipeline_has_tess(pipeline
))
4140 struct radv_shader_variant
*tes
, *tcs
;
4142 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
4143 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
4146 if (tes
->info
.is_ngg
) {
4147 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, tes
);
4148 } else if (tes
->info
.tes
.as_es
)
4149 radv_pipeline_generate_hw_es(cs
, pipeline
, tes
);
4151 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, tes
);
4154 radv_pipeline_generate_hw_hs(cs
, pipeline
, tcs
, tess
);
4156 radeon_set_context_reg(ctx_cs
, R_028B6C_VGT_TF_PARAM
,
4159 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
)
4160 radeon_set_context_reg_idx(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
4161 tess
->ls_hs_config
);
4163 radeon_set_context_reg(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
,
4164 tess
->ls_hs_config
);
4166 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
4167 !radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
4168 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4169 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4170 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4171 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4176 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf
*ctx_cs
,
4177 struct radeon_cmdbuf
*cs
,
4178 struct radv_pipeline
*pipeline
,
4179 struct radv_shader_variant
*gs
)
4181 const struct gfx9_gs_info
*gs_state
= &gs
->info
.gs_ring_info
;
4182 unsigned gs_max_out_vertices
;
4183 uint8_t *num_components
;
4188 gs_max_out_vertices
= gs
->info
.gs
.vertices_out
;
4189 max_stream
= gs
->info
.gs
.max_stream
;
4190 num_components
= gs
->info
.gs
.num_stream_output_components
;
4192 offset
= num_components
[0] * gs_max_out_vertices
;
4194 radeon_set_context_reg_seq(ctx_cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
4195 radeon_emit(ctx_cs
, offset
);
4196 if (max_stream
>= 1)
4197 offset
+= num_components
[1] * gs_max_out_vertices
;
4198 radeon_emit(ctx_cs
, offset
);
4199 if (max_stream
>= 2)
4200 offset
+= num_components
[2] * gs_max_out_vertices
;
4201 radeon_emit(ctx_cs
, offset
);
4202 if (max_stream
>= 3)
4203 offset
+= num_components
[3] * gs_max_out_vertices
;
4204 radeon_set_context_reg(ctx_cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
4206 radeon_set_context_reg_seq(ctx_cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
4207 radeon_emit(ctx_cs
, num_components
[0]);
4208 radeon_emit(ctx_cs
, (max_stream
>= 1) ? num_components
[1] : 0);
4209 radeon_emit(ctx_cs
, (max_stream
>= 2) ? num_components
[2] : 0);
4210 radeon_emit(ctx_cs
, (max_stream
>= 3) ? num_components
[3] : 0);
4212 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
4213 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
4214 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
4215 S_028B90_ENABLE(gs_num_invocations
> 0));
4217 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
4218 gs_state
->vgt_esgs_ring_itemsize
);
4220 va
= radv_buffer_get_va(gs
->bo
) + gs
->bo_offset
;
4222 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4223 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4224 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
4225 radeon_emit(cs
, va
>> 8);
4226 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
4228 radeon_set_sh_reg_seq(cs
, R_00B210_SPI_SHADER_PGM_LO_ES
, 2);
4229 radeon_emit(cs
, va
>> 8);
4230 radeon_emit(cs
, S_00B214_MEM_BASE(va
>> 40));
4233 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
4234 radeon_emit(cs
, gs
->config
.rsrc1
);
4235 radeon_emit(cs
, gs
->config
.rsrc2
| S_00B22C_LDS_SIZE(gs_state
->lds_size
));
4237 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
, gs_state
->vgt_gs_onchip_cntl
);
4238 radeon_set_context_reg(ctx_cs
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
, gs_state
->vgt_gs_max_prims_per_subgroup
);
4240 radeon_set_sh_reg_seq(cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
4241 radeon_emit(cs
, va
>> 8);
4242 radeon_emit(cs
, S_00B224_MEM_BASE(va
>> 40));
4243 radeon_emit(cs
, gs
->config
.rsrc1
);
4244 radeon_emit(cs
, gs
->config
.rsrc2
);
4247 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, pipeline
->gs_copy_shader
);
4251 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf
*ctx_cs
,
4252 struct radeon_cmdbuf
*cs
,
4253 struct radv_pipeline
*pipeline
)
4255 struct radv_shader_variant
*gs
;
4257 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4261 if (gs
->info
.is_ngg
)
4262 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, gs
);
4264 radv_pipeline_generate_hw_gs(ctx_cs
, cs
, pipeline
, gs
);
4266 radeon_set_context_reg(ctx_cs
, R_028B38_VGT_GS_MAX_VERT_OUT
,
4267 gs
->info
.gs
.vertices_out
);
4270 static uint32_t offset_to_ps_input(uint32_t offset
, bool flat_shade
,
4271 bool explicit, bool float16
)
4273 uint32_t ps_input_cntl
;
4274 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
4275 ps_input_cntl
= S_028644_OFFSET(offset
);
4276 if (flat_shade
|| explicit)
4277 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
4279 /* Force parameter cache to be read in passthrough
4282 ps_input_cntl
|= S_028644_OFFSET(1 << 5);
4285 ps_input_cntl
|= S_028644_FP16_INTERP_MODE(1) |
4286 S_028644_ATTR0_VALID(1);
4289 /* The input is a DEFAULT_VAL constant. */
4290 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
4291 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
4292 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
4293 ps_input_cntl
= S_028644_OFFSET(0x20) |
4294 S_028644_DEFAULT_VAL(offset
);
4296 return ps_input_cntl
;
4300 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf
*ctx_cs
,
4301 struct radv_pipeline
*pipeline
)
4303 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4304 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
4305 uint32_t ps_input_cntl
[32];
4307 unsigned ps_offset
= 0;
4309 if (ps
->info
.ps
.prim_id_input
) {
4310 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
];
4311 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4312 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4317 if (ps
->info
.ps
.layer_input
||
4318 ps
->info
.needs_multiview_view_index
) {
4319 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
];
4320 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
4321 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4323 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false, false);
4327 if (ps
->info
.ps
.viewport_index_input
) {
4328 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VIEWPORT
];
4329 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
4330 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4332 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false, false);
4336 if (ps
->info
.ps
.has_pcoord
) {
4338 val
= S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4339 ps_input_cntl
[ps_offset
] = val
;
4343 if (ps
->info
.ps
.num_input_clips_culls
) {
4346 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST0
];
4347 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4348 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false, false);
4352 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST1
];
4353 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
&&
4354 ps
->info
.ps
.num_input_clips_culls
> 4) {
4355 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false, false);
4360 for (unsigned i
= 0; i
< 32 && (1u << i
) <= ps
->info
.ps
.input_mask
; ++i
) {
4365 if (!(ps
->info
.ps
.input_mask
& (1u << i
)))
4368 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VAR0
+ i
];
4369 if (vs_offset
== AC_EXP_PARAM_UNDEFINED
) {
4370 ps_input_cntl
[ps_offset
] = S_028644_OFFSET(0x20);
4375 flat_shade
= !!(ps
->info
.ps
.flat_shaded_mask
& (1u << ps_offset
));
4376 explicit = !!(ps
->info
.ps
.explicit_shaded_mask
& (1u << ps_offset
));
4377 float16
= !!(ps
->info
.ps
.float16_shaded_mask
& (1u << ps_offset
));
4379 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, flat_shade
, explicit, float16
);
4384 radeon_set_context_reg_seq(ctx_cs
, R_028644_SPI_PS_INPUT_CNTL_0
, ps_offset
);
4385 for (unsigned i
= 0; i
< ps_offset
; i
++) {
4386 radeon_emit(ctx_cs
, ps_input_cntl
[i
]);
4392 radv_compute_db_shader_control(const struct radv_device
*device
,
4393 const struct radv_pipeline
*pipeline
,
4394 const struct radv_shader_variant
*ps
)
4396 unsigned conservative_z_export
= V_02880C_EXPORT_ANY_Z
;
4398 if (ps
->info
.ps
.early_fragment_test
|| !ps
->info
.ps
.writes_memory
)
4399 z_order
= V_02880C_EARLY_Z_THEN_LATE_Z
;
4401 z_order
= V_02880C_LATE_Z
;
4403 if (ps
->info
.ps
.depth_layout
== FRAG_DEPTH_LAYOUT_GREATER
)
4404 conservative_z_export
= V_02880C_EXPORT_GREATER_THAN_Z
;
4405 else if (ps
->info
.ps
.depth_layout
== FRAG_DEPTH_LAYOUT_LESS
)
4406 conservative_z_export
= V_02880C_EXPORT_LESS_THAN_Z
;
4408 bool disable_rbplus
= device
->physical_device
->rad_info
.has_rbplus
&&
4409 !device
->physical_device
->rad_info
.rbplus_allowed
;
4411 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4412 * but this appears to break Project Cars (DXVK). See
4413 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4415 bool mask_export_enable
= ps
->info
.ps
.writes_sample_mask
;
4417 return S_02880C_Z_EXPORT_ENABLE(ps
->info
.ps
.writes_z
) |
4418 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps
->info
.ps
.writes_stencil
) |
4419 S_02880C_KILL_ENABLE(!!ps
->info
.ps
.can_discard
) |
4420 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable
) |
4421 S_02880C_CONSERVATIVE_Z_EXPORT(conservative_z_export
) |
4422 S_02880C_Z_ORDER(z_order
) |
4423 S_02880C_DEPTH_BEFORE_SHADER(ps
->info
.ps
.early_fragment_test
) |
4424 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps
->info
.ps
.post_depth_coverage
) |
4425 S_02880C_EXEC_ON_HIER_FAIL(ps
->info
.ps
.writes_memory
) |
4426 S_02880C_EXEC_ON_NOOP(ps
->info
.ps
.writes_memory
) |
4427 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus
);
4431 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf
*ctx_cs
,
4432 struct radeon_cmdbuf
*cs
,
4433 struct radv_pipeline
*pipeline
)
4435 struct radv_shader_variant
*ps
;
4437 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
4439 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4440 va
= radv_buffer_get_va(ps
->bo
) + ps
->bo_offset
;
4442 radeon_set_sh_reg_seq(cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
4443 radeon_emit(cs
, va
>> 8);
4444 radeon_emit(cs
, S_00B024_MEM_BASE(va
>> 40));
4445 radeon_emit(cs
, ps
->config
.rsrc1
);
4446 radeon_emit(cs
, ps
->config
.rsrc2
);
4448 radeon_set_context_reg(ctx_cs
, R_02880C_DB_SHADER_CONTROL
,
4449 radv_compute_db_shader_control(pipeline
->device
,
4452 radeon_set_context_reg(ctx_cs
, R_0286CC_SPI_PS_INPUT_ENA
,
4453 ps
->config
.spi_ps_input_ena
);
4455 radeon_set_context_reg(ctx_cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
4456 ps
->config
.spi_ps_input_addr
);
4458 radeon_set_context_reg(ctx_cs
, R_0286D8_SPI_PS_IN_CONTROL
,
4459 S_0286D8_NUM_INTERP(ps
->info
.ps
.num_interp
) |
4460 S_0286D8_PS_W32_EN(ps
->info
.wave_size
== 32));
4462 radeon_set_context_reg(ctx_cs
, R_0286E0_SPI_BARYC_CNTL
, pipeline
->graphics
.spi_baryc_cntl
);
4464 radeon_set_context_reg(ctx_cs
, R_028710_SPI_SHADER_Z_FORMAT
,
4465 ac_get_spi_shader_z_format(ps
->info
.ps
.writes_z
,
4466 ps
->info
.ps
.writes_stencil
,
4467 ps
->info
.ps
.writes_sample_mask
));
4469 if (pipeline
->device
->dfsm_allowed
) {
4470 /* optimise this? */
4471 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
4472 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
4477 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf
*ctx_cs
,
4478 struct radv_pipeline
*pipeline
)
4480 if (pipeline
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4481 pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
4484 unsigned vtx_reuse_depth
= 30;
4485 if (radv_pipeline_has_tess(pipeline
) &&
4486 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.tes
.spacing
== TESS_SPACING_FRACTIONAL_ODD
) {
4487 vtx_reuse_depth
= 14;
4489 radeon_set_context_reg(ctx_cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
4490 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth
));
4494 radv_compute_vgt_shader_stages_en(const struct radv_pipeline
*pipeline
)
4496 uint32_t stages
= 0;
4497 if (radv_pipeline_has_tess(pipeline
)) {
4498 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
4499 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4501 if (radv_pipeline_has_gs(pipeline
))
4502 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
4504 else if (radv_pipeline_has_ngg(pipeline
))
4505 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
4507 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
4508 } else if (radv_pipeline_has_gs(pipeline
)) {
4509 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
4511 } else if (radv_pipeline_has_ngg(pipeline
)) {
4512 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
4515 if (radv_pipeline_has_ngg(pipeline
)) {
4516 stages
|= S_028B54_PRIMGEN_EN(1);
4517 if (pipeline
->streamout_shader
)
4518 stages
|= S_028B54_NGG_WAVE_ID_EN(1);
4519 if (radv_pipeline_has_ngg_passthrough(pipeline
))
4520 stages
|= S_028B54_PRIMGEN_PASSTHRU_EN(1);
4521 } else if (radv_pipeline_has_gs(pipeline
)) {
4522 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
4525 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
4526 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4528 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4529 uint8_t hs_size
= 64, gs_size
= 64, vs_size
= 64;
4531 if (radv_pipeline_has_tess(pipeline
))
4532 hs_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.wave_size
;
4534 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
4535 vs_size
= gs_size
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.wave_size
;
4536 if (pipeline
->gs_copy_shader
)
4537 vs_size
= pipeline
->gs_copy_shader
->info
.wave_size
;
4538 } else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
4539 vs_size
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.wave_size
;
4540 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
4541 vs_size
= pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.wave_size
;
4543 if (radv_pipeline_has_ngg(pipeline
))
4546 /* legacy GS only supports Wave64 */
4547 stages
|= S_028B54_HS_W32_EN(hs_size
== 32 ? 1 : 0) |
4548 S_028B54_GS_W32_EN(gs_size
== 32 ? 1 : 0) |
4549 S_028B54_VS_W32_EN(vs_size
== 32 ? 1 : 0);
4556 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4558 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
4559 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
4561 if (!discard_rectangle_info
)
4566 for (unsigned i
= 0; i
< (1u << MAX_DISCARD_RECTANGLES
); ++i
) {
4567 /* Interpret i as a bitmask, and then set the bit in the mask if
4568 * that combination of rectangles in which the pixel is contained
4569 * should pass the cliprect test. */
4570 unsigned relevant_subset
= i
& ((1u << discard_rectangle_info
->discardRectangleCount
) - 1);
4572 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT
&&
4576 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT
&&
4587 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf
*ctx_cs
,
4588 struct radv_pipeline
*pipeline
,
4589 const struct radv_tessellation_state
*tess
)
4591 bool break_wave_at_eoi
= false;
4592 unsigned primgroup_size
;
4593 unsigned vertgroup_size
= 256; /* 256 = disable vertex grouping */
4595 if (radv_pipeline_has_tess(pipeline
)) {
4596 primgroup_size
= tess
->num_patches
; /* must be a multiple of NUM_PATCHES */
4597 } else if (radv_pipeline_has_gs(pipeline
)) {
4598 const struct gfx9_gs_info
*gs_state
=
4599 &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs_ring_info
;
4600 unsigned vgt_gs_onchip_cntl
= gs_state
->vgt_gs_onchip_cntl
;
4601 primgroup_size
= G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl
);
4603 primgroup_size
= 128; /* recommended without a GS and tess */
4606 if (radv_pipeline_has_tess(pipeline
)) {
4607 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4608 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4609 break_wave_at_eoi
= true;
4612 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
,
4613 S_03096C_PRIM_GRP_SIZE(primgroup_size
) |
4614 S_03096C_VERT_GRP_SIZE(vertgroup_size
) |
4615 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4616 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
));
4620 radv_pipeline_generate_pm4(struct radv_pipeline
*pipeline
,
4621 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4622 const struct radv_graphics_pipeline_create_info
*extra
,
4623 const struct radv_blend_state
*blend
,
4624 const struct radv_tessellation_state
*tess
,
4625 unsigned prim
, unsigned gs_out
)
4627 struct radeon_cmdbuf
*ctx_cs
= &pipeline
->ctx_cs
;
4628 struct radeon_cmdbuf
*cs
= &pipeline
->cs
;
4631 ctx_cs
->max_dw
= 256;
4632 cs
->buf
= malloc(4 * (cs
->max_dw
+ ctx_cs
->max_dw
));
4633 ctx_cs
->buf
= cs
->buf
+ cs
->max_dw
;
4635 radv_pipeline_generate_depth_stencil_state(ctx_cs
, pipeline
, pCreateInfo
, extra
);
4636 radv_pipeline_generate_blend_state(ctx_cs
, pipeline
, blend
);
4637 radv_pipeline_generate_raster_state(ctx_cs
, pipeline
, pCreateInfo
);
4638 radv_pipeline_generate_multisample_state(ctx_cs
, pipeline
);
4639 radv_pipeline_generate_vgt_gs_mode(ctx_cs
, pipeline
);
4640 radv_pipeline_generate_vertex_shader(ctx_cs
, cs
, pipeline
, tess
);
4641 radv_pipeline_generate_tess_shaders(ctx_cs
, cs
, pipeline
, tess
);
4642 radv_pipeline_generate_geometry_shader(ctx_cs
, cs
, pipeline
);
4643 radv_pipeline_generate_fragment_shader(ctx_cs
, cs
, pipeline
);
4644 radv_pipeline_generate_ps_inputs(ctx_cs
, pipeline
);
4645 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs
, pipeline
);
4646 radv_pipeline_generate_binning_state(ctx_cs
, pipeline
, pCreateInfo
, blend
);
4648 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&& !radv_pipeline_has_ngg(pipeline
))
4649 gfx10_pipeline_generate_ge_cntl(ctx_cs
, pipeline
, tess
);
4651 radeon_set_context_reg(ctx_cs
, R_028B54_VGT_SHADER_STAGES_EN
, radv_compute_vgt_shader_stages_en(pipeline
));
4653 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4654 radeon_set_uconfig_reg_idx(pipeline
->device
->physical_device
,
4655 cs
, R_030908_VGT_PRIMITIVE_TYPE
, 1, prim
);
4657 radeon_set_config_reg(cs
, R_008958_VGT_PRIMITIVE_TYPE
, prim
);
4659 radeon_set_context_reg(ctx_cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, gs_out
);
4661 radeon_set_context_reg(ctx_cs
, R_02820C_PA_SC_CLIPRECT_RULE
, radv_compute_cliprect_rule(pCreateInfo
));
4663 pipeline
->ctx_cs_hash
= _mesa_hash_data(ctx_cs
->buf
, ctx_cs
->cdw
* 4);
4665 assert(ctx_cs
->cdw
<= ctx_cs
->max_dw
);
4666 assert(cs
->cdw
<= cs
->max_dw
);
4669 static struct radv_ia_multi_vgt_param_helpers
4670 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline
*pipeline
,
4671 const struct radv_tessellation_state
*tess
,
4674 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
= {0};
4675 const struct radv_device
*device
= pipeline
->device
;
4677 if (radv_pipeline_has_tess(pipeline
))
4678 ia_multi_vgt_param
.primgroup_size
= tess
->num_patches
;
4679 else if (radv_pipeline_has_gs(pipeline
))
4680 ia_multi_vgt_param
.primgroup_size
= 64;
4682 ia_multi_vgt_param
.primgroup_size
= 128; /* recommended without a GS */
4684 /* GS requirement. */
4685 ia_multi_vgt_param
.partial_es_wave
= false;
4686 if (radv_pipeline_has_gs(pipeline
) && device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4687 if (SI_GS_PER_ES
/ ia_multi_vgt_param
.primgroup_size
>= pipeline
->device
->gs_table_depth
- 3)
4688 ia_multi_vgt_param
.partial_es_wave
= true;
4690 ia_multi_vgt_param
.wd_switch_on_eop
= false;
4691 if (device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
4692 /* WD_SWITCH_ON_EOP has no effect on GPUs with less than
4693 * 4 shader engines. Set 1 to pass the assertion below.
4694 * The other cases are hardware requirements. */
4695 if (device
->physical_device
->rad_info
.max_se
< 4 ||
4696 prim
== V_008958_DI_PT_POLYGON
||
4697 prim
== V_008958_DI_PT_LINELOOP
||
4698 prim
== V_008958_DI_PT_TRIFAN
||
4699 prim
== V_008958_DI_PT_TRISTRIP_ADJ
||
4700 (pipeline
->graphics
.prim_restart_enable
&&
4701 (device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4702 (prim
!= V_008958_DI_PT_POINTLIST
&&
4703 prim
!= V_008958_DI_PT_LINESTRIP
))))
4704 ia_multi_vgt_param
.wd_switch_on_eop
= true;
4707 ia_multi_vgt_param
.ia_switch_on_eoi
= false;
4708 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.prim_id_input
)
4709 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4710 if (radv_pipeline_has_gs(pipeline
) &&
4711 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.uses_prim_id
)
4712 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4713 if (radv_pipeline_has_tess(pipeline
)) {
4714 /* SWITCH_ON_EOI must be set if PrimID is used. */
4715 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4716 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4717 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4720 ia_multi_vgt_param
.partial_vs_wave
= false;
4721 if (radv_pipeline_has_tess(pipeline
)) {
4722 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4723 if ((device
->physical_device
->rad_info
.family
== CHIP_TAHITI
||
4724 device
->physical_device
->rad_info
.family
== CHIP_PITCAIRN
||
4725 device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
) &&
4726 radv_pipeline_has_gs(pipeline
))
4727 ia_multi_vgt_param
.partial_vs_wave
= true;
4728 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4729 if (device
->physical_device
->rad_info
.has_distributed_tess
) {
4730 if (radv_pipeline_has_gs(pipeline
)) {
4731 if (device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4732 ia_multi_vgt_param
.partial_es_wave
= true;
4734 ia_multi_vgt_param
.partial_vs_wave
= true;
4739 /* Workaround for a VGT hang when strip primitive types are used with
4740 * primitive restart.
4742 if (pipeline
->graphics
.prim_restart_enable
&&
4743 (prim
== V_008958_DI_PT_LINESTRIP
||
4744 prim
== V_008958_DI_PT_TRISTRIP
||
4745 prim
== V_008958_DI_PT_LINESTRIP_ADJ
||
4746 prim
== V_008958_DI_PT_TRISTRIP_ADJ
)) {
4747 ia_multi_vgt_param
.partial_vs_wave
= true;
4750 if (radv_pipeline_has_gs(pipeline
)) {
4751 /* On these chips there is the possibility of a hang if the
4752 * pipeline uses a GS and partial_vs_wave is not set.
4754 * This mostly does not hit 4-SE chips, as those typically set
4755 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4756 * with GS due to another workaround.
4758 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4760 if (device
->physical_device
->rad_info
.family
== CHIP_TONGA
||
4761 device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
4762 device
->physical_device
->rad_info
.family
== CHIP_POLARIS10
||
4763 device
->physical_device
->rad_info
.family
== CHIP_POLARIS11
||
4764 device
->physical_device
->rad_info
.family
== CHIP_POLARIS12
||
4765 device
->physical_device
->rad_info
.family
== CHIP_VEGAM
) {
4766 ia_multi_vgt_param
.partial_vs_wave
= true;
4770 ia_multi_vgt_param
.base
=
4771 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param
.primgroup_size
- 1) |
4772 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4773 S_028AA8_MAX_PRIMGRP_IN_WAVE(device
->physical_device
->rad_info
.chip_class
== GFX8
? 2 : 0) |
4774 S_030960_EN_INST_OPT_BASIC(device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
4775 S_030960_EN_INST_OPT_ADV(device
->physical_device
->rad_info
.chip_class
>= GFX9
);
4777 return ia_multi_vgt_param
;
4782 radv_compute_vertex_input_state(struct radv_pipeline
*pipeline
,
4783 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4785 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
4786 pCreateInfo
->pVertexInputState
;
4787 struct radv_vertex_elements_info
*velems
= &pipeline
->vertex_elements
;
4789 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
4790 const VkVertexInputAttributeDescription
*desc
=
4791 &vi_info
->pVertexAttributeDescriptions
[i
];
4792 unsigned loc
= desc
->location
;
4793 const struct vk_format_description
*format_desc
;
4795 format_desc
= vk_format_description(desc
->format
);
4797 velems
->format_size
[loc
] = format_desc
->block
.bits
/ 8;
4800 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
4801 const VkVertexInputBindingDescription
*desc
=
4802 &vi_info
->pVertexBindingDescriptions
[i
];
4804 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
4805 pipeline
->num_vertex_bindings
=
4806 MAX2(pipeline
->num_vertex_bindings
, desc
->binding
+ 1);
4810 static struct radv_shader_variant
*
4811 radv_pipeline_get_streamout_shader(struct radv_pipeline
*pipeline
)
4815 for (i
= MESA_SHADER_GEOMETRY
; i
>= MESA_SHADER_VERTEX
; i
--) {
4816 struct radv_shader_variant
*shader
=
4817 radv_get_shader(pipeline
, i
);
4819 if (shader
&& shader
->info
.so
.num_outputs
> 0)
4827 radv_secure_compile(struct radv_pipeline
*pipeline
,
4828 struct radv_device
*device
,
4829 const struct radv_pipeline_key
*key
,
4830 const VkPipelineShaderStageCreateInfo
**pStages
,
4831 const VkPipelineCreateFlags flags
,
4832 unsigned num_stages
)
4834 uint8_t allowed_pipeline_hashes
[2][20];
4835 radv_hash_shaders(allowed_pipeline_hashes
[0], pStages
,
4836 pipeline
->layout
, key
, get_hash_flags(device
));
4838 /* Generate the GC copy hash */
4839 memcpy(allowed_pipeline_hashes
[1], allowed_pipeline_hashes
[0], 20);
4840 allowed_pipeline_hashes
[1][0] ^= 1;
4842 uint8_t allowed_hashes
[2][20];
4843 for (unsigned i
= 0; i
< 2; ++i
) {
4844 disk_cache_compute_key(device
->physical_device
->disk_cache
,
4845 allowed_pipeline_hashes
[i
], 20,
4849 /* Do an early exit if all cache entries are already there. */
4850 bool may_need_copy_shader
= pStages
[MESA_SHADER_GEOMETRY
];
4851 void *main_entry
= disk_cache_get(device
->physical_device
->disk_cache
, allowed_hashes
[0], NULL
);
4852 void *copy_entry
= NULL
;
4853 if (may_need_copy_shader
)
4854 copy_entry
= disk_cache_get(device
->physical_device
->disk_cache
, allowed_hashes
[1], NULL
);
4856 bool has_all_cache_entries
= main_entry
&& (!may_need_copy_shader
|| copy_entry
);
4860 if(has_all_cache_entries
)
4863 unsigned process
= 0;
4864 uint8_t sc_threads
= device
->instance
->num_sc_threads
;
4866 mtx_lock(&device
->sc_state
->secure_compile_mutex
);
4867 if (device
->sc_state
->secure_compile_thread_counter
< sc_threads
) {
4868 device
->sc_state
->secure_compile_thread_counter
++;
4869 for (unsigned i
= 0; i
< sc_threads
; i
++) {
4870 if (!device
->sc_state
->secure_compile_processes
[i
].in_use
) {
4871 device
->sc_state
->secure_compile_processes
[i
].in_use
= true;
4876 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
4879 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
4882 int fd_secure_input
= device
->sc_state
->secure_compile_processes
[process
].fd_secure_input
;
4883 int fd_secure_output
= device
->sc_state
->secure_compile_processes
[process
].fd_secure_output
;
4885 /* Fork a copy of the slim untainted secure compile process */
4886 enum radv_secure_compile_type sc_type
= RADV_SC_TYPE_FORK_DEVICE
;
4887 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
4889 if (!radv_sc_read(fd_secure_output
, &sc_type
, sizeof(sc_type
), true) ||
4890 sc_type
!= RADV_SC_TYPE_INIT_SUCCESS
)
4891 return VK_ERROR_DEVICE_LOST
;
4893 fd_secure_input
= device
->sc_state
->secure_compile_processes
[process
].fd_server
;
4894 fd_secure_output
= device
->sc_state
->secure_compile_processes
[process
].fd_client
;
4896 /* Write pipeline / shader module out to secure process via pipe */
4897 sc_type
= RADV_SC_TYPE_COMPILE_PIPELINE
;
4898 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
4900 /* Write pipeline layout out to secure process */
4901 struct radv_pipeline_layout
*layout
= pipeline
->layout
;
4902 write(fd_secure_input
, layout
, sizeof(struct radv_pipeline_layout
));
4903 write(fd_secure_input
, &layout
->num_sets
, sizeof(uint32_t));
4904 for (uint32_t set
= 0; set
< layout
->num_sets
; set
++) {
4905 write(fd_secure_input
, &layout
->set
[set
].layout
->layout_size
, sizeof(uint32_t));
4906 write(fd_secure_input
, layout
->set
[set
].layout
, layout
->set
[set
].layout
->layout_size
);
4909 /* Write pipeline key out to secure process */
4910 write(fd_secure_input
, key
, sizeof(struct radv_pipeline_key
));
4912 /* Write pipeline create flags out to secure process */
4913 write(fd_secure_input
, &flags
, sizeof(VkPipelineCreateFlags
));
4915 /* Write stage and shader information out to secure process */
4916 write(fd_secure_input
, &num_stages
, sizeof(uint32_t));
4917 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
4921 /* Write stage out to secure process */
4922 gl_shader_stage stage
= ffs(pStages
[i
]->stage
) - 1;
4923 write(fd_secure_input
, &stage
, sizeof(gl_shader_stage
));
4925 /* Write entry point name out to secure process */
4926 size_t name_size
= strlen(pStages
[i
]->pName
) + 1;
4927 write(fd_secure_input
, &name_size
, sizeof(size_t));
4928 write(fd_secure_input
, pStages
[i
]->pName
, name_size
);
4930 /* Write shader module out to secure process */
4931 struct radv_shader_module
*module
= radv_shader_module_from_handle(pStages
[i
]->module
);
4932 assert(!module
->nir
);
4933 size_t module_size
= sizeof(struct radv_shader_module
) + module
->size
;
4934 write(fd_secure_input
, &module_size
, sizeof(size_t));
4935 write(fd_secure_input
, module
, module_size
);
4937 /* Write specialization info out to secure process */
4938 const VkSpecializationInfo
*specInfo
= pStages
[i
]->pSpecializationInfo
;
4939 bool has_spec_info
= specInfo
? true : false;
4940 write(fd_secure_input
, &has_spec_info
, sizeof(bool));
4942 write(fd_secure_input
, &specInfo
->dataSize
, sizeof(size_t));
4943 write(fd_secure_input
, specInfo
->pData
, specInfo
->dataSize
);
4945 write(fd_secure_input
, &specInfo
->mapEntryCount
, sizeof(uint32_t));
4946 for (uint32_t j
= 0; j
< specInfo
->mapEntryCount
; j
++)
4947 write(fd_secure_input
, &specInfo
->pMapEntries
[j
], sizeof(VkSpecializationMapEntry
));
4951 /* Read the data returned from the secure process */
4952 while (sc_type
!= RADV_SC_TYPE_COMPILE_PIPELINE_FINISHED
) {
4953 if (!radv_sc_read(fd_secure_output
, &sc_type
, sizeof(sc_type
), true))
4954 return VK_ERROR_DEVICE_LOST
;
4956 if (sc_type
== RADV_SC_TYPE_WRITE_DISK_CACHE
) {
4957 assert(device
->physical_device
->disk_cache
);
4959 uint8_t disk_sha1
[20];
4960 if (!radv_sc_read(fd_secure_output
, disk_sha1
, sizeof(uint8_t) * 20, true))
4961 return VK_ERROR_DEVICE_LOST
;
4963 if (memcmp(disk_sha1
, allowed_hashes
[0], 20) &&
4964 memcmp(disk_sha1
, allowed_hashes
[1], 20))
4965 return VK_ERROR_DEVICE_LOST
;
4967 uint32_t entry_size
;
4968 if (!radv_sc_read(fd_secure_output
, &entry_size
, sizeof(uint32_t), true))
4969 return VK_ERROR_DEVICE_LOST
;
4971 struct cache_entry
*entry
= malloc(entry_size
);
4972 if (!radv_sc_read(fd_secure_output
, entry
, entry_size
, true))
4973 return VK_ERROR_DEVICE_LOST
;
4975 disk_cache_put(device
->physical_device
->disk_cache
,
4976 disk_sha1
, entry
, entry_size
,
4980 } else if (sc_type
== RADV_SC_TYPE_READ_DISK_CACHE
) {
4981 uint8_t disk_sha1
[20];
4982 if (!radv_sc_read(fd_secure_output
, disk_sha1
, sizeof(uint8_t) * 20, true))
4983 return VK_ERROR_DEVICE_LOST
;
4985 if (memcmp(disk_sha1
, allowed_hashes
[0], 20) &&
4986 memcmp(disk_sha1
, allowed_hashes
[1], 20))
4987 return VK_ERROR_DEVICE_LOST
;
4990 struct cache_entry
*entry
= (struct cache_entry
*)
4991 disk_cache_get(device
->physical_device
->disk_cache
,
4994 uint8_t found
= entry
? 1 : 0;
4995 write(fd_secure_input
, &found
, sizeof(uint8_t));
4998 write(fd_secure_input
, &size
, sizeof(size_t));
4999 write(fd_secure_input
, entry
, size
);
5006 sc_type
= RADV_SC_TYPE_DESTROY_DEVICE
;
5007 write(fd_secure_input
, &sc_type
, sizeof(sc_type
));
5009 mtx_lock(&device
->sc_state
->secure_compile_mutex
);
5010 device
->sc_state
->secure_compile_thread_counter
--;
5011 device
->sc_state
->secure_compile_processes
[process
].in_use
= false;
5012 mtx_unlock(&device
->sc_state
->secure_compile_mutex
);
5018 radv_pipeline_init(struct radv_pipeline
*pipeline
,
5019 struct radv_device
*device
,
5020 struct radv_pipeline_cache
*cache
,
5021 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
5022 const struct radv_graphics_pipeline_create_info
*extra
)
5025 bool has_view_index
= false;
5027 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
5028 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
5029 if (subpass
->view_mask
)
5030 has_view_index
= true;
5032 pipeline
->device
= device
;
5033 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
5034 assert(pipeline
->layout
);
5036 struct radv_blend_state blend
= radv_pipeline_init_blend_state(pipeline
, pCreateInfo
, extra
);
5038 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
5039 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
5040 radv_init_feedback(creation_feedback
);
5042 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
5044 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
5045 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
5046 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
5047 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
5048 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
5049 if(creation_feedback
)
5050 stage_feedbacks
[stage
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[i
];
5053 struct radv_pipeline_key key
= radv_generate_graphics_pipeline_key(pipeline
, pCreateInfo
, &blend
, has_view_index
);
5054 if (radv_device_use_secure_compile(device
->instance
)) {
5055 return radv_secure_compile(pipeline
, device
, &key
, pStages
, pCreateInfo
->flags
, pCreateInfo
->stageCount
);
5057 result
= radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
,
5058 pCreateInfo
->flags
, pipeline_feedback
,
5060 if (result
!= VK_SUCCESS
)
5064 pipeline
->graphics
.spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
5065 radv_pipeline_init_multisample_state(pipeline
, &blend
, pCreateInfo
);
5067 uint32_t prim
= si_translate_prim(pCreateInfo
->pInputAssemblyState
->topology
);
5069 pipeline
->graphics
.topology
= pCreateInfo
->pInputAssemblyState
->topology
;
5070 pipeline
->graphics
.can_use_guardband
= radv_prim_can_use_guardband(pCreateInfo
->pInputAssemblyState
->topology
);
5072 if (radv_pipeline_has_gs(pipeline
)) {
5073 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs
.output_prim
);
5074 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
5075 } else if (radv_pipeline_has_tess(pipeline
)) {
5076 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.point_mode
)
5077 gs_out
= V_028A6C_OUTPRIM_TYPE_POINTLIST
;
5079 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.primitive_mode
);
5080 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
5082 gs_out
= si_conv_prim_to_gs_out(pCreateInfo
->pInputAssemblyState
->topology
);
5084 if (extra
&& extra
->use_rectlist
) {
5085 prim
= V_008958_DI_PT_RECTLIST
;
5086 gs_out
= V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
5087 pipeline
->graphics
.can_use_guardband
= true;
5088 if (radv_pipeline_has_ngg(pipeline
))
5089 gs_out
= V_028A6C_VGT_OUT_RECT_V0
;
5091 pipeline
->graphics
.prim_restart_enable
= !!pCreateInfo
->pInputAssemblyState
->primitiveRestartEnable
;
5092 /* prim vertex count will need TESS changes */
5093 pipeline
->graphics
.prim_vertex_count
= prim_size_table
[prim
];
5095 radv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
);
5097 /* Ensure that some export memory is always allocated, for two reasons:
5099 * 1) Correctness: The hardware ignores the EXEC mask if no export
5100 * memory is allocated, so KILL and alpha test do not work correctly
5102 * 2) Performance: Every shader needs at least a NULL export, even when
5103 * it writes no color/depth output. The NULL export instruction
5104 * stalls without this setting.
5106 * Don't add this to CB_SHADER_MASK.
5108 * GFX10 supports pixel shaders without exports by setting both the
5109 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
5110 * instructions if any are present.
5112 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
5113 if ((pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX9
||
5114 ps
->info
.ps
.can_discard
) &&
5115 !blend
.spi_shader_col_format
) {
5116 if (!ps
->info
.ps
.writes_z
&&
5117 !ps
->info
.ps
.writes_stencil
&&
5118 !ps
->info
.ps
.writes_sample_mask
)
5119 blend
.spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
5123 (extra
->custom_blend_mode
== V_028808_CB_ELIMINATE_FAST_CLEAR
||
5124 extra
->custom_blend_mode
== V_028808_CB_FMASK_DECOMPRESS
||
5125 extra
->custom_blend_mode
== V_028808_CB_DCC_DECOMPRESS
||
5126 extra
->custom_blend_mode
== V_028808_CB_RESOLVE
)) {
5127 /* According to the CB spec states, CB_SHADER_MASK should be
5128 * set to enable writes to all four channels of MRT0.
5130 blend
.cb_shader_mask
= 0xf;
5133 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
5134 if (pipeline
->shaders
[i
]) {
5135 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[i
]->info
.need_indirect_descriptor_sets
;
5139 if (radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
5140 struct radv_shader_variant
*gs
=
5141 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
5143 calculate_gs_ring_sizes(pipeline
, &gs
->info
.gs_ring_info
);
5146 struct radv_tessellation_state tess
= {0};
5147 if (radv_pipeline_has_tess(pipeline
)) {
5148 if (prim
== V_008958_DI_PT_PATCH
) {
5149 pipeline
->graphics
.prim_vertex_count
.min
= pCreateInfo
->pTessellationState
->patchControlPoints
;
5150 pipeline
->graphics
.prim_vertex_count
.incr
= 1;
5152 tess
= calculate_tess_state(pipeline
, pCreateInfo
);
5155 pipeline
->graphics
.ia_multi_vgt_param
= radv_compute_ia_multi_vgt_param_helpers(pipeline
, &tess
, prim
);
5157 radv_compute_vertex_input_state(pipeline
, pCreateInfo
);
5159 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++)
5160 pipeline
->user_data_0
[i
] = radv_pipeline_stage_to_user_data_0(pipeline
, i
, device
->physical_device
->rad_info
.chip_class
);
5162 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
,
5163 AC_UD_VS_BASE_VERTEX_START_INSTANCE
);
5164 if (loc
->sgpr_idx
!= -1) {
5165 pipeline
->graphics
.vtx_base_sgpr
= pipeline
->user_data_0
[MESA_SHADER_VERTEX
];
5166 pipeline
->graphics
.vtx_base_sgpr
+= loc
->sgpr_idx
* 4;
5167 if (radv_get_shader(pipeline
, MESA_SHADER_VERTEX
)->info
.vs
.needs_draw_id
)
5168 pipeline
->graphics
.vtx_emit_num
= 3;
5170 pipeline
->graphics
.vtx_emit_num
= 2;
5173 /* Find the last vertex shader stage that eventually uses streamout. */
5174 pipeline
->streamout_shader
= radv_pipeline_get_streamout_shader(pipeline
);
5176 result
= radv_pipeline_scratch_init(device
, pipeline
);
5177 radv_pipeline_generate_pm4(pipeline
, pCreateInfo
, extra
, &blend
, &tess
, prim
, gs_out
);
5183 radv_graphics_pipeline_create(
5185 VkPipelineCache _cache
,
5186 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
5187 const struct radv_graphics_pipeline_create_info
*extra
,
5188 const VkAllocationCallbacks
*pAllocator
,
5189 VkPipeline
*pPipeline
)
5191 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5192 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
5193 struct radv_pipeline
*pipeline
;
5196 pipeline
= vk_zalloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*pipeline
), 8,
5197 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5198 if (pipeline
== NULL
)
5199 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5201 vk_object_base_init(&device
->vk
, &pipeline
->base
,
5202 VK_OBJECT_TYPE_PIPELINE
);
5204 result
= radv_pipeline_init(pipeline
, device
, cache
,
5205 pCreateInfo
, extra
);
5206 if (result
!= VK_SUCCESS
) {
5207 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5211 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5216 VkResult
radv_CreateGraphicsPipelines(
5218 VkPipelineCache pipelineCache
,
5220 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
5221 const VkAllocationCallbacks
* pAllocator
,
5222 VkPipeline
* pPipelines
)
5224 VkResult result
= VK_SUCCESS
;
5227 for (; i
< count
; i
++) {
5229 r
= radv_graphics_pipeline_create(_device
,
5232 NULL
, pAllocator
, &pPipelines
[i
]);
5233 if (r
!= VK_SUCCESS
) {
5235 pPipelines
[i
] = VK_NULL_HANDLE
;
5237 if (pCreateInfos
[i
].flags
& VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT
)
5242 for (; i
< count
; ++i
)
5243 pPipelines
[i
] = VK_NULL_HANDLE
;
5250 radv_compute_generate_pm4(struct radv_pipeline
*pipeline
)
5252 struct radv_shader_variant
*compute_shader
;
5253 struct radv_device
*device
= pipeline
->device
;
5254 unsigned threads_per_threadgroup
;
5255 unsigned threadgroups_per_cu
= 1;
5256 unsigned waves_per_threadgroup
;
5257 unsigned max_waves_per_sh
= 0;
5260 pipeline
->cs
.max_dw
= device
->physical_device
->rad_info
.chip_class
>= GFX10
? 22 : 20;
5261 pipeline
->cs
.buf
= malloc(pipeline
->cs
.max_dw
* 4);
5263 compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
5264 va
= radv_buffer_get_va(compute_shader
->bo
) + compute_shader
->bo_offset
;
5266 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B830_COMPUTE_PGM_LO
, 2);
5267 radeon_emit(&pipeline
->cs
, va
>> 8);
5268 radeon_emit(&pipeline
->cs
, S_00B834_DATA(va
>> 40));
5270 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
5271 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc1
);
5272 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc2
);
5273 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
5274 radeon_set_sh_reg(&pipeline
->cs
, R_00B8A0_COMPUTE_PGM_RSRC3
, compute_shader
->config
.rsrc3
);
5277 /* Calculate best compute resource limits. */
5278 threads_per_threadgroup
= compute_shader
->info
.cs
.block_size
[0] *
5279 compute_shader
->info
.cs
.block_size
[1] *
5280 compute_shader
->info
.cs
.block_size
[2];
5281 waves_per_threadgroup
= DIV_ROUND_UP(threads_per_threadgroup
,
5282 compute_shader
->info
.wave_size
);
5284 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
5285 waves_per_threadgroup
== 1)
5286 threadgroups_per_cu
= 2;
5288 radeon_set_sh_reg(&pipeline
->cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
5289 ac_get_compute_resource_limits(&device
->physical_device
->rad_info
,
5290 waves_per_threadgroup
,
5292 threadgroups_per_cu
));
5294 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
5295 radeon_emit(&pipeline
->cs
,
5296 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]));
5297 radeon_emit(&pipeline
->cs
,
5298 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]));
5299 radeon_emit(&pipeline
->cs
,
5300 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]));
5302 assert(pipeline
->cs
.cdw
<= pipeline
->cs
.max_dw
);
5305 static struct radv_pipeline_key
5306 radv_generate_compute_pipeline_key(struct radv_pipeline
*pipeline
,
5307 const VkComputePipelineCreateInfo
*pCreateInfo
)
5309 const VkPipelineShaderStageCreateInfo
*stage
= &pCreateInfo
->stage
;
5310 struct radv_pipeline_key key
;
5311 memset(&key
, 0, sizeof(key
));
5313 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
5314 key
.optimisations_disabled
= 1;
5316 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*subgroup_size
=
5317 vk_find_struct_const(stage
->pNext
,
5318 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT
);
5320 if (subgroup_size
) {
5321 assert(subgroup_size
->requiredSubgroupSize
== 32 ||
5322 subgroup_size
->requiredSubgroupSize
== 64);
5323 key
.compute_subgroup_size
= subgroup_size
->requiredSubgroupSize
;
5329 static VkResult
radv_compute_pipeline_create(
5331 VkPipelineCache _cache
,
5332 const VkComputePipelineCreateInfo
* pCreateInfo
,
5333 const VkAllocationCallbacks
* pAllocator
,
5334 VkPipeline
* pPipeline
)
5336 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5337 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
5338 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
5339 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
5340 struct radv_pipeline
*pipeline
;
5343 pipeline
= vk_zalloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*pipeline
), 8,
5344 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5345 if (pipeline
== NULL
)
5346 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5348 vk_object_base_init(&device
->vk
, &pipeline
->base
,
5349 VK_OBJECT_TYPE_PIPELINE
);
5351 pipeline
->device
= device
;
5352 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
5353 assert(pipeline
->layout
);
5355 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
5356 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
5357 radv_init_feedback(creation_feedback
);
5359 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
5360 if (creation_feedback
)
5361 stage_feedbacks
[MESA_SHADER_COMPUTE
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[0];
5363 pStages
[MESA_SHADER_COMPUTE
] = &pCreateInfo
->stage
;
5365 struct radv_pipeline_key key
=
5366 radv_generate_compute_pipeline_key(pipeline
, pCreateInfo
);
5368 if (radv_device_use_secure_compile(device
->instance
)) {
5369 result
= radv_secure_compile(pipeline
, device
, &key
, pStages
, pCreateInfo
->flags
, 1);
5370 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5374 result
= radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
,
5375 pCreateInfo
->flags
, pipeline_feedback
,
5377 if (result
!= VK_SUCCESS
) {
5378 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5383 pipeline
->user_data_0
[MESA_SHADER_COMPUTE
] = radv_pipeline_stage_to_user_data_0(pipeline
, MESA_SHADER_COMPUTE
, device
->physical_device
->rad_info
.chip_class
);
5384 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.need_indirect_descriptor_sets
;
5385 result
= radv_pipeline_scratch_init(device
, pipeline
);
5386 if (result
!= VK_SUCCESS
) {
5387 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5391 radv_compute_generate_pm4(pipeline
);
5393 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5398 VkResult
radv_CreateComputePipelines(
5400 VkPipelineCache pipelineCache
,
5402 const VkComputePipelineCreateInfo
* pCreateInfos
,
5403 const VkAllocationCallbacks
* pAllocator
,
5404 VkPipeline
* pPipelines
)
5406 VkResult result
= VK_SUCCESS
;
5409 for (; i
< count
; i
++) {
5411 r
= radv_compute_pipeline_create(_device
, pipelineCache
,
5413 pAllocator
, &pPipelines
[i
]);
5414 if (r
!= VK_SUCCESS
) {
5416 pPipelines
[i
] = VK_NULL_HANDLE
;
5418 if (pCreateInfos
[i
].flags
& VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT
)
5423 for (; i
< count
; ++i
)
5424 pPipelines
[i
] = VK_NULL_HANDLE
;
5430 static uint32_t radv_get_executable_count(const struct radv_pipeline
*pipeline
)
5433 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5434 if (!pipeline
->shaders
[i
])
5437 if (i
== MESA_SHADER_GEOMETRY
&&
5438 !radv_pipeline_has_ngg(pipeline
)) {
5448 static struct radv_shader_variant
*
5449 radv_get_shader_from_executable_index(const struct radv_pipeline
*pipeline
, int index
, gl_shader_stage
*stage
)
5451 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5452 if (!pipeline
->shaders
[i
])
5456 return pipeline
->shaders
[i
];
5461 if (i
== MESA_SHADER_GEOMETRY
&&
5462 !radv_pipeline_has_ngg(pipeline
)) {
5465 return pipeline
->gs_copy_shader
;
5475 /* Basically strlcpy (which does not exist on linux) specialized for
5477 static void desc_copy(char *desc
, const char *src
) {
5478 int len
= strlen(src
);
5479 assert(len
< VK_MAX_DESCRIPTION_SIZE
);
5480 memcpy(desc
, src
, len
);
5481 memset(desc
+ len
, 0, VK_MAX_DESCRIPTION_SIZE
- len
);
5484 VkResult
radv_GetPipelineExecutablePropertiesKHR(
5486 const VkPipelineInfoKHR
* pPipelineInfo
,
5487 uint32_t* pExecutableCount
,
5488 VkPipelineExecutablePropertiesKHR
* pProperties
)
5490 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pPipelineInfo
->pipeline
);
5491 const uint32_t total_count
= radv_get_executable_count(pipeline
);
5494 *pExecutableCount
= total_count
;
5498 const uint32_t count
= MIN2(total_count
, *pExecutableCount
);
5499 for (unsigned i
= 0, executable_idx
= 0;
5500 i
< MESA_SHADER_STAGES
&& executable_idx
< count
; ++i
) {
5501 if (!pipeline
->shaders
[i
])
5503 pProperties
[executable_idx
].stages
= mesa_to_vk_shader_stage(i
);
5504 const char *name
= NULL
;
5505 const char *description
= NULL
;
5507 case MESA_SHADER_VERTEX
:
5508 name
= "Vertex Shader";
5509 description
= "Vulkan Vertex Shader";
5511 case MESA_SHADER_TESS_CTRL
:
5512 if (!pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5513 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5514 name
= "Vertex + Tessellation Control Shaders";
5515 description
= "Combined Vulkan Vertex and Tessellation Control Shaders";
5517 name
= "Tessellation Control Shader";
5518 description
= "Vulkan Tessellation Control Shader";
5521 case MESA_SHADER_TESS_EVAL
:
5522 name
= "Tessellation Evaluation Shader";
5523 description
= "Vulkan Tessellation Evaluation Shader";
5525 case MESA_SHADER_GEOMETRY
:
5526 if (radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]) {
5527 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
;
5528 name
= "Tessellation Evaluation + Geometry Shaders";
5529 description
= "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5530 } else if (!radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5531 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5532 name
= "Vertex + Geometry Shader";
5533 description
= "Combined Vulkan Vertex and Geometry Shaders";
5535 name
= "Geometry Shader";
5536 description
= "Vulkan Geometry Shader";
5539 case MESA_SHADER_FRAGMENT
:
5540 name
= "Fragment Shader";
5541 description
= "Vulkan Fragment Shader";
5543 case MESA_SHADER_COMPUTE
:
5544 name
= "Compute Shader";
5545 description
= "Vulkan Compute Shader";
5549 pProperties
[executable_idx
].subgroupSize
= pipeline
->shaders
[i
]->info
.wave_size
;
5550 desc_copy(pProperties
[executable_idx
].name
, name
);
5551 desc_copy(pProperties
[executable_idx
].description
, description
);
5554 if (i
== MESA_SHADER_GEOMETRY
&&
5555 !radv_pipeline_has_ngg(pipeline
)) {
5556 assert(pipeline
->gs_copy_shader
);
5557 if (executable_idx
>= count
)
5560 pProperties
[executable_idx
].stages
= VK_SHADER_STAGE_GEOMETRY_BIT
;
5561 pProperties
[executable_idx
].subgroupSize
= 64;
5562 desc_copy(pProperties
[executable_idx
].name
, "GS Copy Shader");
5563 desc_copy(pProperties
[executable_idx
].description
,
5564 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5570 VkResult result
= *pExecutableCount
< total_count
? VK_INCOMPLETE
: VK_SUCCESS
;
5571 *pExecutableCount
= count
;
5575 VkResult
radv_GetPipelineExecutableStatisticsKHR(
5577 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5578 uint32_t* pStatisticCount
,
5579 VkPipelineExecutableStatisticKHR
* pStatistics
)
5581 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5582 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5583 gl_shader_stage stage
;
5584 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5586 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
5587 unsigned lds_increment
= chip_class
>= GFX7
? 512 : 256;
5588 unsigned max_waves
= radv_get_max_waves(device
, shader
, stage
);
5590 VkPipelineExecutableStatisticKHR
*s
= pStatistics
;
5591 VkPipelineExecutableStatisticKHR
*end
= s
+ (pStatistics
? *pStatisticCount
: 0);
5592 VkResult result
= VK_SUCCESS
;
5595 desc_copy(s
->name
, "SGPRs");
5596 desc_copy(s
->description
, "Number of SGPR registers allocated per subgroup");
5597 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5598 s
->value
.u64
= shader
->config
.num_sgprs
;
5603 desc_copy(s
->name
, "VGPRs");
5604 desc_copy(s
->description
, "Number of VGPR registers allocated per subgroup");
5605 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5606 s
->value
.u64
= shader
->config
.num_vgprs
;
5611 desc_copy(s
->name
, "Spilled SGPRs");
5612 desc_copy(s
->description
, "Number of SGPR registers spilled per subgroup");
5613 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5614 s
->value
.u64
= shader
->config
.spilled_sgprs
;
5619 desc_copy(s
->name
, "Spilled VGPRs");
5620 desc_copy(s
->description
, "Number of VGPR registers spilled per subgroup");
5621 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5622 s
->value
.u64
= shader
->config
.spilled_vgprs
;
5627 desc_copy(s
->name
, "PrivMem VGPRs");
5628 desc_copy(s
->description
, "Number of VGPRs stored in private memory per subgroup");
5629 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5630 s
->value
.u64
= shader
->info
.private_mem_vgprs
;
5635 desc_copy(s
->name
, "Code size");
5636 desc_copy(s
->description
, "Code size in bytes");
5637 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5638 s
->value
.u64
= shader
->exec_size
;
5643 desc_copy(s
->name
, "LDS size");
5644 desc_copy(s
->description
, "LDS size in bytes per workgroup");
5645 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5646 s
->value
.u64
= shader
->config
.lds_size
* lds_increment
;
5651 desc_copy(s
->name
, "Scratch size");
5652 desc_copy(s
->description
, "Private memory in bytes per subgroup");
5653 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5654 s
->value
.u64
= shader
->config
.scratch_bytes_per_wave
;
5659 desc_copy(s
->name
, "Subgroups per SIMD");
5660 desc_copy(s
->description
, "The maximum number of subgroups in flight on a SIMD unit");
5661 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5662 s
->value
.u64
= max_waves
;
5666 if (shader
->statistics
) {
5667 for (unsigned i
= 0; i
< shader
->statistics
->count
; i
++) {
5668 struct radv_compiler_statistic_info
*info
= &shader
->statistics
->infos
[i
];
5669 uint32_t value
= shader
->statistics
->values
[i
];
5671 desc_copy(s
->name
, info
->name
);
5672 desc_copy(s
->description
, info
->desc
);
5673 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5674 s
->value
.u64
= value
;
5681 *pStatisticCount
= s
- pStatistics
;
5683 *pStatisticCount
= end
- pStatistics
;
5684 result
= VK_INCOMPLETE
;
5686 *pStatisticCount
= s
- pStatistics
;
5692 static VkResult
radv_copy_representation(void *data
, size_t *data_size
, const char *src
)
5694 size_t total_size
= strlen(src
) + 1;
5697 *data_size
= total_size
;
5701 size_t size
= MIN2(total_size
, *data_size
);
5703 memcpy(data
, src
, size
);
5705 *((char*)data
+ size
- 1) = 0;
5706 return size
< total_size
? VK_INCOMPLETE
: VK_SUCCESS
;
5709 VkResult
radv_GetPipelineExecutableInternalRepresentationsKHR(
5711 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5712 uint32_t* pInternalRepresentationCount
,
5713 VkPipelineExecutableInternalRepresentationKHR
* pInternalRepresentations
)
5715 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5716 gl_shader_stage stage
;
5717 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5719 VkPipelineExecutableInternalRepresentationKHR
*p
= pInternalRepresentations
;
5720 VkPipelineExecutableInternalRepresentationKHR
*end
= p
+ (pInternalRepresentations
? *pInternalRepresentationCount
: 0);
5721 VkResult result
= VK_SUCCESS
;
5725 desc_copy(p
->name
, "NIR Shader(s)");
5726 desc_copy(p
->description
, "The optimized NIR shader(s)");
5727 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->nir_string
) != VK_SUCCESS
)
5728 result
= VK_INCOMPLETE
;
5735 if (pipeline
->device
->physical_device
->use_aco
) {
5736 desc_copy(p
->name
, "ACO IR");
5737 desc_copy(p
->description
, "The ACO IR after some optimizations");
5739 desc_copy(p
->name
, "LLVM IR");
5740 desc_copy(p
->description
, "The LLVM IR after some optimizations");
5742 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->ir_string
) != VK_SUCCESS
)
5743 result
= VK_INCOMPLETE
;
5750 desc_copy(p
->name
, "Assembly");
5751 desc_copy(p
->description
, "Final Assembly");
5752 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->disasm_string
) != VK_SUCCESS
)
5753 result
= VK_INCOMPLETE
;
5757 if (!pInternalRepresentations
)
5758 *pInternalRepresentationCount
= p
- pInternalRepresentations
;
5760 result
= VK_INCOMPLETE
;
5761 *pInternalRepresentationCount
= end
- pInternalRepresentations
;
5763 *pInternalRepresentationCount
= p
- pInternalRepresentations
;