2 * Copyright © 2016 Red Hat.
3 * Copyright © 2016 Bas Nieuwenhuizen
5 * based in part on anv driver which is:
6 * Copyright © 2015 Intel Corporation
8 * Permission is hereby granted, free of charge, to any person obtaining a
9 * copy of this software and associated documentation files (the "Software"),
10 * to deal in the Software without restriction, including without limitation
11 * the rights to use, copy, modify, merge, publish, distribute, sublicense,
12 * and/or sell copies of the Software, and to permit persons to whom the
13 * Software is furnished to do so, subject to the following conditions:
15 * The above copyright notice and this permission notice (including the next
16 * paragraph) shall be included in all copies or substantial portions of the
19 * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR
20 * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY,
21 * FITNESS FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL
22 * THE AUTHORS OR COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER
23 * LIABILITY, WHETHER IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING
24 * FROM, OUT OF OR IN CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS
28 #include "util/disk_cache.h"
29 #include "util/mesa-sha1.h"
30 #include "util/u_atomic.h"
31 #include "radv_debug.h"
32 #include "radv_private.h"
34 #include "radv_shader.h"
36 #include "nir/nir_builder.h"
37 #include "nir/nir_xfb_info.h"
38 #include "spirv/nir_spirv.h"
42 #include "ac_binary.h"
43 #include "ac_llvm_util.h"
44 #include "ac_nir_to_llvm.h"
45 #include "vk_format.h"
46 #include "util/debug.h"
47 #include "ac_exp_param.h"
48 #include "ac_shader_util.h"
50 struct radv_blend_state
{
51 uint32_t blend_enable_4bit
;
52 uint32_t need_src_alpha
;
54 uint32_t cb_color_control
;
55 uint32_t cb_target_mask
;
56 uint32_t cb_target_enabled_4bit
;
57 uint32_t sx_mrt_blend_opt
[8];
58 uint32_t cb_blend_control
[8];
60 uint32_t spi_shader_col_format
;
61 uint32_t col_format_is_int8
;
62 uint32_t col_format_is_int10
;
63 uint32_t cb_shader_mask
;
64 uint32_t db_alpha_to_mask
;
66 uint32_t commutative_4bit
;
68 bool single_cb_enable
;
69 bool mrt0_is_dual_src
;
72 struct radv_dsa_order_invariance
{
73 /* Whether the final result in Z/S buffers is guaranteed to be
74 * invariant under changes to the order in which fragments arrive.
78 /* Whether the set of fragments that pass the combined Z/S test is
79 * guaranteed to be invariant under changes to the order in which
85 struct radv_tessellation_state
{
86 uint32_t ls_hs_config
;
92 static const VkPipelineMultisampleStateCreateInfo
*
93 radv_pipeline_get_multisample_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
95 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
96 return pCreateInfo
->pMultisampleState
;
100 static const VkPipelineTessellationStateCreateInfo
*
101 radv_pipeline_get_tessellation_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
103 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
104 if (pCreateInfo
->pStages
[i
].stage
== VK_SHADER_STAGE_TESSELLATION_CONTROL_BIT
||
105 pCreateInfo
->pStages
[i
].stage
== VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
) {
106 return pCreateInfo
->pTessellationState
;
112 static const VkPipelineDepthStencilStateCreateInfo
*
113 radv_pipeline_get_depth_stencil_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
115 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
116 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
118 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
119 subpass
->depth_stencil_attachment
)
120 return pCreateInfo
->pDepthStencilState
;
124 static const VkPipelineColorBlendStateCreateInfo
*
125 radv_pipeline_get_color_blend_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
127 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
128 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
130 if (!pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
&&
131 subpass
->has_color_att
)
132 return pCreateInfo
->pColorBlendState
;
136 bool radv_pipeline_has_ngg(const struct radv_pipeline
*pipeline
)
138 struct radv_shader_variant
*variant
= NULL
;
139 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
140 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
141 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
142 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
143 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
144 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
147 return variant
->info
.is_ngg
;
150 bool radv_pipeline_has_ngg_passthrough(const struct radv_pipeline
*pipeline
)
152 assert(radv_pipeline_has_ngg(pipeline
));
154 struct radv_shader_variant
*variant
= NULL
;
155 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
156 variant
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
157 else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
158 variant
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
159 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
160 variant
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
163 return variant
->info
.is_ngg_passthrough
;
166 bool radv_pipeline_has_gs_copy_shader(const struct radv_pipeline
*pipeline
)
168 if (!radv_pipeline_has_gs(pipeline
))
171 /* The GS copy shader is required if the pipeline has GS on GFX6-GFX9.
172 * On GFX10, it might be required in rare cases if it's not possible to
175 if (radv_pipeline_has_ngg(pipeline
))
178 assert(pipeline
->gs_copy_shader
);
183 radv_pipeline_destroy(struct radv_device
*device
,
184 struct radv_pipeline
*pipeline
,
185 const VkAllocationCallbacks
* allocator
)
187 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
188 if (pipeline
->shaders
[i
])
189 radv_shader_variant_destroy(device
, pipeline
->shaders
[i
]);
191 if (pipeline
->gs_copy_shader
)
192 radv_shader_variant_destroy(device
, pipeline
->gs_copy_shader
);
195 free(pipeline
->cs
.buf
);
197 vk_object_base_finish(&pipeline
->base
);
198 vk_free2(&device
->vk
.alloc
, allocator
, pipeline
);
201 void radv_DestroyPipeline(
203 VkPipeline _pipeline
,
204 const VkAllocationCallbacks
* pAllocator
)
206 RADV_FROM_HANDLE(radv_device
, device
, _device
);
207 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, _pipeline
);
212 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
215 static uint32_t get_hash_flags(struct radv_device
*device
)
217 uint32_t hash_flags
= 0;
219 if (device
->instance
->debug_flags
& RADV_DEBUG_NO_NGG
)
220 hash_flags
|= RADV_HASH_SHADER_NO_NGG
;
221 if (device
->physical_device
->cs_wave_size
== 32)
222 hash_flags
|= RADV_HASH_SHADER_CS_WAVE32
;
223 if (device
->physical_device
->ps_wave_size
== 32)
224 hash_flags
|= RADV_HASH_SHADER_PS_WAVE32
;
225 if (device
->physical_device
->ge_wave_size
== 32)
226 hash_flags
|= RADV_HASH_SHADER_GE_WAVE32
;
227 if (device
->physical_device
->use_llvm
)
228 hash_flags
|= RADV_HASH_SHADER_LLVM
;
233 radv_pipeline_scratch_init(struct radv_device
*device
,
234 struct radv_pipeline
*pipeline
)
236 unsigned scratch_bytes_per_wave
= 0;
237 unsigned max_waves
= 0;
238 unsigned min_waves
= 1;
240 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
241 if (pipeline
->shaders
[i
] &&
242 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
) {
243 unsigned max_stage_waves
= device
->scratch_waves
;
245 scratch_bytes_per_wave
= MAX2(scratch_bytes_per_wave
,
246 pipeline
->shaders
[i
]->config
.scratch_bytes_per_wave
);
248 max_stage_waves
= MIN2(max_stage_waves
,
249 4 * device
->physical_device
->rad_info
.num_good_compute_units
*
250 (256 / pipeline
->shaders
[i
]->config
.num_vgprs
));
251 max_waves
= MAX2(max_waves
, max_stage_waves
);
255 if (pipeline
->shaders
[MESA_SHADER_COMPUTE
]) {
256 unsigned group_size
= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[0] *
257 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[1] *
258 pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.cs
.block_size
[2];
259 min_waves
= MAX2(min_waves
, round_up_u32(group_size
, 64));
262 pipeline
->scratch_bytes_per_wave
= scratch_bytes_per_wave
;
263 pipeline
->max_waves
= max_waves
;
267 static uint32_t si_translate_blend_logic_op(VkLogicOp op
)
270 case VK_LOGIC_OP_CLEAR
:
271 return V_028808_ROP3_CLEAR
;
272 case VK_LOGIC_OP_AND
:
273 return V_028808_ROP3_AND
;
274 case VK_LOGIC_OP_AND_REVERSE
:
275 return V_028808_ROP3_AND_REVERSE
;
276 case VK_LOGIC_OP_COPY
:
277 return V_028808_ROP3_COPY
;
278 case VK_LOGIC_OP_AND_INVERTED
:
279 return V_028808_ROP3_AND_INVERTED
;
280 case VK_LOGIC_OP_NO_OP
:
281 return V_028808_ROP3_NO_OP
;
282 case VK_LOGIC_OP_XOR
:
283 return V_028808_ROP3_XOR
;
285 return V_028808_ROP3_OR
;
286 case VK_LOGIC_OP_NOR
:
287 return V_028808_ROP3_NOR
;
288 case VK_LOGIC_OP_EQUIVALENT
:
289 return V_028808_ROP3_EQUIVALENT
;
290 case VK_LOGIC_OP_INVERT
:
291 return V_028808_ROP3_INVERT
;
292 case VK_LOGIC_OP_OR_REVERSE
:
293 return V_028808_ROP3_OR_REVERSE
;
294 case VK_LOGIC_OP_COPY_INVERTED
:
295 return V_028808_ROP3_COPY_INVERTED
;
296 case VK_LOGIC_OP_OR_INVERTED
:
297 return V_028808_ROP3_OR_INVERTED
;
298 case VK_LOGIC_OP_NAND
:
299 return V_028808_ROP3_NAND
;
300 case VK_LOGIC_OP_SET
:
301 return V_028808_ROP3_SET
;
303 unreachable("Unhandled logic op");
308 static uint32_t si_translate_blend_function(VkBlendOp op
)
311 case VK_BLEND_OP_ADD
:
312 return V_028780_COMB_DST_PLUS_SRC
;
313 case VK_BLEND_OP_SUBTRACT
:
314 return V_028780_COMB_SRC_MINUS_DST
;
315 case VK_BLEND_OP_REVERSE_SUBTRACT
:
316 return V_028780_COMB_DST_MINUS_SRC
;
317 case VK_BLEND_OP_MIN
:
318 return V_028780_COMB_MIN_DST_SRC
;
319 case VK_BLEND_OP_MAX
:
320 return V_028780_COMB_MAX_DST_SRC
;
326 static uint32_t si_translate_blend_factor(VkBlendFactor factor
)
329 case VK_BLEND_FACTOR_ZERO
:
330 return V_028780_BLEND_ZERO
;
331 case VK_BLEND_FACTOR_ONE
:
332 return V_028780_BLEND_ONE
;
333 case VK_BLEND_FACTOR_SRC_COLOR
:
334 return V_028780_BLEND_SRC_COLOR
;
335 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
336 return V_028780_BLEND_ONE_MINUS_SRC_COLOR
;
337 case VK_BLEND_FACTOR_DST_COLOR
:
338 return V_028780_BLEND_DST_COLOR
;
339 case VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
:
340 return V_028780_BLEND_ONE_MINUS_DST_COLOR
;
341 case VK_BLEND_FACTOR_SRC_ALPHA
:
342 return V_028780_BLEND_SRC_ALPHA
;
343 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
344 return V_028780_BLEND_ONE_MINUS_SRC_ALPHA
;
345 case VK_BLEND_FACTOR_DST_ALPHA
:
346 return V_028780_BLEND_DST_ALPHA
;
347 case VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
:
348 return V_028780_BLEND_ONE_MINUS_DST_ALPHA
;
349 case VK_BLEND_FACTOR_CONSTANT_COLOR
:
350 return V_028780_BLEND_CONSTANT_COLOR
;
351 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
:
352 return V_028780_BLEND_ONE_MINUS_CONSTANT_COLOR
;
353 case VK_BLEND_FACTOR_CONSTANT_ALPHA
:
354 return V_028780_BLEND_CONSTANT_ALPHA
;
355 case VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
:
356 return V_028780_BLEND_ONE_MINUS_CONSTANT_ALPHA
;
357 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
358 return V_028780_BLEND_SRC_ALPHA_SATURATE
;
359 case VK_BLEND_FACTOR_SRC1_COLOR
:
360 return V_028780_BLEND_SRC1_COLOR
;
361 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
362 return V_028780_BLEND_INV_SRC1_COLOR
;
363 case VK_BLEND_FACTOR_SRC1_ALPHA
:
364 return V_028780_BLEND_SRC1_ALPHA
;
365 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
366 return V_028780_BLEND_INV_SRC1_ALPHA
;
372 static uint32_t si_translate_blend_opt_function(VkBlendOp op
)
375 case VK_BLEND_OP_ADD
:
376 return V_028760_OPT_COMB_ADD
;
377 case VK_BLEND_OP_SUBTRACT
:
378 return V_028760_OPT_COMB_SUBTRACT
;
379 case VK_BLEND_OP_REVERSE_SUBTRACT
:
380 return V_028760_OPT_COMB_REVSUBTRACT
;
381 case VK_BLEND_OP_MIN
:
382 return V_028760_OPT_COMB_MIN
;
383 case VK_BLEND_OP_MAX
:
384 return V_028760_OPT_COMB_MAX
;
386 return V_028760_OPT_COMB_BLEND_DISABLED
;
390 static uint32_t si_translate_blend_opt_factor(VkBlendFactor factor
, bool is_alpha
)
393 case VK_BLEND_FACTOR_ZERO
:
394 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_ALL
;
395 case VK_BLEND_FACTOR_ONE
:
396 return V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
;
397 case VK_BLEND_FACTOR_SRC_COLOR
:
398 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
399 : V_028760_BLEND_OPT_PRESERVE_C1_IGNORE_C0
;
400 case VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
:
401 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
402 : V_028760_BLEND_OPT_PRESERVE_C0_IGNORE_C1
;
403 case VK_BLEND_FACTOR_SRC_ALPHA
:
404 return V_028760_BLEND_OPT_PRESERVE_A1_IGNORE_A0
;
405 case VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
:
406 return V_028760_BLEND_OPT_PRESERVE_A0_IGNORE_A1
;
407 case VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
:
408 return is_alpha
? V_028760_BLEND_OPT_PRESERVE_ALL_IGNORE_NONE
409 : V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
411 return V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
416 * Get rid of DST in the blend factors by commuting the operands:
417 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
419 static void si_blend_remove_dst(unsigned *func
, unsigned *src_factor
,
420 unsigned *dst_factor
, unsigned expected_dst
,
421 unsigned replacement_src
)
423 if (*src_factor
== expected_dst
&&
424 *dst_factor
== VK_BLEND_FACTOR_ZERO
) {
425 *src_factor
= VK_BLEND_FACTOR_ZERO
;
426 *dst_factor
= replacement_src
;
428 /* Commuting the operands requires reversing subtractions. */
429 if (*func
== VK_BLEND_OP_SUBTRACT
)
430 *func
= VK_BLEND_OP_REVERSE_SUBTRACT
;
431 else if (*func
== VK_BLEND_OP_REVERSE_SUBTRACT
)
432 *func
= VK_BLEND_OP_SUBTRACT
;
436 static bool si_blend_factor_uses_dst(unsigned factor
)
438 return factor
== VK_BLEND_FACTOR_DST_COLOR
||
439 factor
== VK_BLEND_FACTOR_DST_ALPHA
||
440 factor
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
441 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_ALPHA
||
442 factor
== VK_BLEND_FACTOR_ONE_MINUS_DST_COLOR
;
445 static bool is_dual_src(VkBlendFactor factor
)
448 case VK_BLEND_FACTOR_SRC1_COLOR
:
449 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
:
450 case VK_BLEND_FACTOR_SRC1_ALPHA
:
451 case VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
:
458 static unsigned radv_choose_spi_color_format(VkFormat vk_format
,
460 bool blend_need_alpha
)
462 const struct vk_format_description
*desc
= vk_format_description(vk_format
);
463 struct ac_spi_color_formats formats
= {};
464 unsigned format
, ntype
, swap
;
466 format
= radv_translate_colorformat(vk_format
);
467 ntype
= radv_translate_color_numformat(vk_format
, desc
,
468 vk_format_get_first_non_void_channel(vk_format
));
469 swap
= radv_translate_colorswap(vk_format
, false);
471 ac_choose_spi_color_formats(format
, swap
, ntype
, false, &formats
);
473 if (blend_enable
&& blend_need_alpha
)
474 return formats
.blend_alpha
;
475 else if(blend_need_alpha
)
476 return formats
.alpha
;
477 else if(blend_enable
)
478 return formats
.blend
;
480 return formats
.normal
;
484 format_is_int8(VkFormat format
)
486 const struct vk_format_description
*desc
= vk_format_description(format
);
487 int channel
= vk_format_get_first_non_void_channel(format
);
489 return channel
>= 0 && desc
->channel
[channel
].pure_integer
&&
490 desc
->channel
[channel
].size
== 8;
494 format_is_int10(VkFormat format
)
496 const struct vk_format_description
*desc
= vk_format_description(format
);
498 if (desc
->nr_channels
!= 4)
500 for (unsigned i
= 0; i
< 4; i
++) {
501 if (desc
->channel
[i
].pure_integer
&& desc
->channel
[i
].size
== 10)
508 radv_pipeline_compute_spi_color_formats(struct radv_pipeline
*pipeline
,
509 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
510 struct radv_blend_state
*blend
)
512 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
513 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
514 unsigned col_format
= 0, is_int8
= 0, is_int10
= 0;
515 unsigned num_targets
;
517 for (unsigned i
= 0; i
< (blend
->single_cb_enable
? 1 : subpass
->color_count
); ++i
) {
520 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
||
521 !(blend
->cb_target_mask
& (0xfu
<< (i
* 4)))) {
522 cf
= V_028714_SPI_SHADER_ZERO
;
524 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->color_attachments
[i
].attachment
;
526 blend
->blend_enable_4bit
& (0xfu
<< (i
* 4));
528 cf
= radv_choose_spi_color_format(attachment
->format
,
530 blend
->need_src_alpha
& (1 << i
));
532 if (format_is_int8(attachment
->format
))
534 if (format_is_int10(attachment
->format
))
538 col_format
|= cf
<< (4 * i
);
541 if (!(col_format
& 0xf) && blend
->need_src_alpha
& (1 << 0)) {
542 /* When a subpass doesn't have any color attachments, write the
543 * alpha channel of MRT0 when alpha coverage is enabled because
544 * the depth attachment needs it.
546 col_format
|= V_028714_SPI_SHADER_32_AR
;
549 /* If the i-th target format is set, all previous target formats must
550 * be non-zero to avoid hangs.
552 num_targets
= (util_last_bit(col_format
) + 3) / 4;
553 for (unsigned i
= 0; i
< num_targets
; i
++) {
554 if (!(col_format
& (0xf << (i
* 4)))) {
555 col_format
|= V_028714_SPI_SHADER_32_R
<< (i
* 4);
559 /* The output for dual source blending should have the same format as
562 if (blend
->mrt0_is_dual_src
)
563 col_format
|= (col_format
& 0xf) << 4;
565 blend
->spi_shader_col_format
= col_format
;
566 blend
->col_format_is_int8
= is_int8
;
567 blend
->col_format_is_int10
= is_int10
;
571 * Ordered so that for each i,
572 * radv_format_meta_fs_key(radv_fs_key_format_exemplars[i]) == i.
574 const VkFormat radv_fs_key_format_exemplars
[NUM_META_FS_KEYS
] = {
575 VK_FORMAT_R32_SFLOAT
,
576 VK_FORMAT_R32G32_SFLOAT
,
577 VK_FORMAT_R8G8B8A8_UNORM
,
578 VK_FORMAT_R16G16B16A16_UNORM
,
579 VK_FORMAT_R16G16B16A16_SNORM
,
580 VK_FORMAT_R16G16B16A16_UINT
,
581 VK_FORMAT_R16G16B16A16_SINT
,
582 VK_FORMAT_R32G32B32A32_SFLOAT
,
583 VK_FORMAT_R8G8B8A8_UINT
,
584 VK_FORMAT_R8G8B8A8_SINT
,
585 VK_FORMAT_A2R10G10B10_UINT_PACK32
,
586 VK_FORMAT_A2R10G10B10_SINT_PACK32
,
589 unsigned radv_format_meta_fs_key(VkFormat format
)
591 unsigned col_format
= radv_choose_spi_color_format(format
, false, false);
593 assert(col_format
!= V_028714_SPI_SHADER_32_AR
);
594 if (col_format
>= V_028714_SPI_SHADER_32_AR
)
595 --col_format
; /* Skip V_028714_SPI_SHADER_32_AR since there is no such VkFormat */
597 --col_format
; /* Skip V_028714_SPI_SHADER_ZERO */
598 bool is_int8
= format_is_int8(format
);
599 bool is_int10
= format_is_int10(format
);
601 return col_format
+ (is_int8
? 3 : is_int10
? 5 : 0);
605 radv_blend_check_commutativity(struct radv_blend_state
*blend
,
606 VkBlendOp op
, VkBlendFactor src
,
607 VkBlendFactor dst
, unsigned chanmask
)
609 /* Src factor is allowed when it does not depend on Dst. */
610 static const uint32_t src_allowed
=
611 (1u << VK_BLEND_FACTOR_ONE
) |
612 (1u << VK_BLEND_FACTOR_SRC_COLOR
) |
613 (1u << VK_BLEND_FACTOR_SRC_ALPHA
) |
614 (1u << VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
) |
615 (1u << VK_BLEND_FACTOR_CONSTANT_COLOR
) |
616 (1u << VK_BLEND_FACTOR_CONSTANT_ALPHA
) |
617 (1u << VK_BLEND_FACTOR_SRC1_COLOR
) |
618 (1u << VK_BLEND_FACTOR_SRC1_ALPHA
) |
619 (1u << VK_BLEND_FACTOR_ZERO
) |
620 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_COLOR
) |
621 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
) |
622 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_COLOR
) |
623 (1u << VK_BLEND_FACTOR_ONE_MINUS_CONSTANT_ALPHA
) |
624 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_COLOR
) |
625 (1u << VK_BLEND_FACTOR_ONE_MINUS_SRC1_ALPHA
);
627 if (dst
== VK_BLEND_FACTOR_ONE
&&
628 (src_allowed
& (1u << src
))) {
629 /* Addition is commutative, but floating point addition isn't
630 * associative: subtle changes can be introduced via different
631 * rounding. Be conservative, only enable for min and max.
633 if (op
== VK_BLEND_OP_MAX
|| op
== VK_BLEND_OP_MIN
)
634 blend
->commutative_4bit
|= chanmask
;
638 static struct radv_blend_state
639 radv_pipeline_init_blend_state(struct radv_pipeline
*pipeline
,
640 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
641 const struct radv_graphics_pipeline_create_info
*extra
)
643 const VkPipelineColorBlendStateCreateInfo
*vkblend
= radv_pipeline_get_color_blend_state(pCreateInfo
);
644 const VkPipelineMultisampleStateCreateInfo
*vkms
= radv_pipeline_get_multisample_state(pCreateInfo
);
645 struct radv_blend_state blend
= {0};
646 unsigned mode
= V_028808_CB_NORMAL
;
649 if (extra
&& extra
->custom_blend_mode
) {
650 blend
.single_cb_enable
= true;
651 mode
= extra
->custom_blend_mode
;
654 blend
.cb_color_control
= 0;
656 if (vkblend
->logicOpEnable
)
657 blend
.cb_color_control
|= S_028808_ROP3(si_translate_blend_logic_op(vkblend
->logicOp
));
659 blend
.cb_color_control
|= S_028808_ROP3(V_028808_ROP3_COPY
);
662 blend
.db_alpha_to_mask
= S_028B70_ALPHA_TO_MASK_OFFSET0(3) |
663 S_028B70_ALPHA_TO_MASK_OFFSET1(1) |
664 S_028B70_ALPHA_TO_MASK_OFFSET2(0) |
665 S_028B70_ALPHA_TO_MASK_OFFSET3(2) |
666 S_028B70_OFFSET_ROUND(1);
668 if (vkms
&& vkms
->alphaToCoverageEnable
) {
669 blend
.db_alpha_to_mask
|= S_028B70_ALPHA_TO_MASK_ENABLE(1);
670 blend
.need_src_alpha
|= 0x1;
673 blend
.cb_target_mask
= 0;
675 for (i
= 0; i
< vkblend
->attachmentCount
; i
++) {
676 const VkPipelineColorBlendAttachmentState
*att
= &vkblend
->pAttachments
[i
];
677 unsigned blend_cntl
= 0;
678 unsigned srcRGB_opt
, dstRGB_opt
, srcA_opt
, dstA_opt
;
679 VkBlendOp eqRGB
= att
->colorBlendOp
;
680 VkBlendFactor srcRGB
= att
->srcColorBlendFactor
;
681 VkBlendFactor dstRGB
= att
->dstColorBlendFactor
;
682 VkBlendOp eqA
= att
->alphaBlendOp
;
683 VkBlendFactor srcA
= att
->srcAlphaBlendFactor
;
684 VkBlendFactor dstA
= att
->dstAlphaBlendFactor
;
686 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
688 if (!att
->colorWriteMask
)
691 blend
.cb_target_mask
|= (unsigned)att
->colorWriteMask
<< (4 * i
);
692 blend
.cb_target_enabled_4bit
|= 0xf << (4 * i
);
693 if (!att
->blendEnable
) {
694 blend
.cb_blend_control
[i
] = blend_cntl
;
698 if (is_dual_src(srcRGB
) || is_dual_src(dstRGB
) || is_dual_src(srcA
) || is_dual_src(dstA
))
700 blend
.mrt0_is_dual_src
= true;
702 if (eqRGB
== VK_BLEND_OP_MIN
|| eqRGB
== VK_BLEND_OP_MAX
) {
703 srcRGB
= VK_BLEND_FACTOR_ONE
;
704 dstRGB
= VK_BLEND_FACTOR_ONE
;
706 if (eqA
== VK_BLEND_OP_MIN
|| eqA
== VK_BLEND_OP_MAX
) {
707 srcA
= VK_BLEND_FACTOR_ONE
;
708 dstA
= VK_BLEND_FACTOR_ONE
;
711 radv_blend_check_commutativity(&blend
, eqRGB
, srcRGB
, dstRGB
,
713 radv_blend_check_commutativity(&blend
, eqA
, srcA
, dstA
,
716 /* Blending optimizations for RB+.
717 * These transformations don't change the behavior.
719 * First, get rid of DST in the blend factors:
720 * func(src * DST, dst * 0) ---> func(src * 0, dst * SRC)
722 si_blend_remove_dst(&eqRGB
, &srcRGB
, &dstRGB
,
723 VK_BLEND_FACTOR_DST_COLOR
,
724 VK_BLEND_FACTOR_SRC_COLOR
);
726 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
727 VK_BLEND_FACTOR_DST_COLOR
,
728 VK_BLEND_FACTOR_SRC_COLOR
);
730 si_blend_remove_dst(&eqA
, &srcA
, &dstA
,
731 VK_BLEND_FACTOR_DST_ALPHA
,
732 VK_BLEND_FACTOR_SRC_ALPHA
);
734 /* Look up the ideal settings from tables. */
735 srcRGB_opt
= si_translate_blend_opt_factor(srcRGB
, false);
736 dstRGB_opt
= si_translate_blend_opt_factor(dstRGB
, false);
737 srcA_opt
= si_translate_blend_opt_factor(srcA
, true);
738 dstA_opt
= si_translate_blend_opt_factor(dstA
, true);
740 /* Handle interdependencies. */
741 if (si_blend_factor_uses_dst(srcRGB
))
742 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
743 if (si_blend_factor_uses_dst(srcA
))
744 dstA_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_NONE
;
746 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
&&
747 (dstRGB
== VK_BLEND_FACTOR_ZERO
||
748 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
749 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
))
750 dstRGB_opt
= V_028760_BLEND_OPT_PRESERVE_NONE_IGNORE_A0
;
752 /* Set the final value. */
753 blend
.sx_mrt_blend_opt
[i
] =
754 S_028760_COLOR_SRC_OPT(srcRGB_opt
) |
755 S_028760_COLOR_DST_OPT(dstRGB_opt
) |
756 S_028760_COLOR_COMB_FCN(si_translate_blend_opt_function(eqRGB
)) |
757 S_028760_ALPHA_SRC_OPT(srcA_opt
) |
758 S_028760_ALPHA_DST_OPT(dstA_opt
) |
759 S_028760_ALPHA_COMB_FCN(si_translate_blend_opt_function(eqA
));
760 blend_cntl
|= S_028780_ENABLE(1);
762 blend_cntl
|= S_028780_COLOR_COMB_FCN(si_translate_blend_function(eqRGB
));
763 blend_cntl
|= S_028780_COLOR_SRCBLEND(si_translate_blend_factor(srcRGB
));
764 blend_cntl
|= S_028780_COLOR_DESTBLEND(si_translate_blend_factor(dstRGB
));
765 if (srcA
!= srcRGB
|| dstA
!= dstRGB
|| eqA
!= eqRGB
) {
766 blend_cntl
|= S_028780_SEPARATE_ALPHA_BLEND(1);
767 blend_cntl
|= S_028780_ALPHA_COMB_FCN(si_translate_blend_function(eqA
));
768 blend_cntl
|= S_028780_ALPHA_SRCBLEND(si_translate_blend_factor(srcA
));
769 blend_cntl
|= S_028780_ALPHA_DESTBLEND(si_translate_blend_factor(dstA
));
771 blend
.cb_blend_control
[i
] = blend_cntl
;
773 blend
.blend_enable_4bit
|= 0xfu
<< (i
* 4);
775 if (srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
776 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA
||
777 srcRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
778 dstRGB
== VK_BLEND_FACTOR_SRC_ALPHA_SATURATE
||
779 srcRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
||
780 dstRGB
== VK_BLEND_FACTOR_ONE_MINUS_SRC_ALPHA
)
781 blend
.need_src_alpha
|= 1 << i
;
783 for (i
= vkblend
->attachmentCount
; i
< 8; i
++) {
784 blend
.cb_blend_control
[i
] = 0;
785 blend
.sx_mrt_blend_opt
[i
] = S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
) | S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_BLEND_DISABLED
);
789 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
790 /* Disable RB+ blend optimizations for dual source blending. */
791 if (blend
.mrt0_is_dual_src
) {
792 for (i
= 0; i
< 8; i
++) {
793 blend
.sx_mrt_blend_opt
[i
] =
794 S_028760_COLOR_COMB_FCN(V_028760_OPT_COMB_NONE
) |
795 S_028760_ALPHA_COMB_FCN(V_028760_OPT_COMB_NONE
);
799 /* RB+ doesn't work with dual source blending, logic op and
802 if (blend
.mrt0_is_dual_src
||
803 (vkblend
&& vkblend
->logicOpEnable
) ||
804 mode
== V_028808_CB_RESOLVE
)
805 blend
.cb_color_control
|= S_028808_DISABLE_DUAL_QUAD(1);
808 if (blend
.cb_target_mask
)
809 blend
.cb_color_control
|= S_028808_MODE(mode
);
811 blend
.cb_color_control
|= S_028808_MODE(V_028808_CB_DISABLE
);
813 radv_pipeline_compute_spi_color_formats(pipeline
, pCreateInfo
, &blend
);
817 static uint32_t si_translate_stencil_op(enum VkStencilOp op
)
820 case VK_STENCIL_OP_KEEP
:
821 return V_02842C_STENCIL_KEEP
;
822 case VK_STENCIL_OP_ZERO
:
823 return V_02842C_STENCIL_ZERO
;
824 case VK_STENCIL_OP_REPLACE
:
825 return V_02842C_STENCIL_REPLACE_TEST
;
826 case VK_STENCIL_OP_INCREMENT_AND_CLAMP
:
827 return V_02842C_STENCIL_ADD_CLAMP
;
828 case VK_STENCIL_OP_DECREMENT_AND_CLAMP
:
829 return V_02842C_STENCIL_SUB_CLAMP
;
830 case VK_STENCIL_OP_INVERT
:
831 return V_02842C_STENCIL_INVERT
;
832 case VK_STENCIL_OP_INCREMENT_AND_WRAP
:
833 return V_02842C_STENCIL_ADD_WRAP
;
834 case VK_STENCIL_OP_DECREMENT_AND_WRAP
:
835 return V_02842C_STENCIL_SUB_WRAP
;
841 static uint32_t si_translate_fill(VkPolygonMode func
)
844 case VK_POLYGON_MODE_FILL
:
845 return V_028814_X_DRAW_TRIANGLES
;
846 case VK_POLYGON_MODE_LINE
:
847 return V_028814_X_DRAW_LINES
;
848 case VK_POLYGON_MODE_POINT
:
849 return V_028814_X_DRAW_POINTS
;
852 return V_028814_X_DRAW_POINTS
;
856 static uint8_t radv_pipeline_get_ps_iter_samples(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
858 const VkPipelineMultisampleStateCreateInfo
*vkms
= pCreateInfo
->pMultisampleState
;
859 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
860 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
861 uint32_t ps_iter_samples
= 1;
862 uint32_t num_samples
;
864 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
866 * "If the VK_AMD_mixed_attachment_samples extension is enabled and the
867 * subpass uses color attachments, totalSamples is the number of
868 * samples of the color attachments. Otherwise, totalSamples is the
869 * value of VkPipelineMultisampleStateCreateInfo::rasterizationSamples
870 * specified at pipeline creation time."
872 if (subpass
->has_color_att
) {
873 num_samples
= subpass
->color_sample_count
;
875 num_samples
= vkms
->rasterizationSamples
;
878 if (vkms
->sampleShadingEnable
) {
879 ps_iter_samples
= ceilf(vkms
->minSampleShading
* num_samples
);
880 ps_iter_samples
= util_next_power_of_two(ps_iter_samples
);
882 return ps_iter_samples
;
886 radv_is_depth_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
888 return pCreateInfo
->depthTestEnable
&&
889 pCreateInfo
->depthWriteEnable
&&
890 pCreateInfo
->depthCompareOp
!= VK_COMPARE_OP_NEVER
;
894 radv_writes_stencil(const VkStencilOpState
*state
)
896 return state
->writeMask
&&
897 (state
->failOp
!= VK_STENCIL_OP_KEEP
||
898 state
->passOp
!= VK_STENCIL_OP_KEEP
||
899 state
->depthFailOp
!= VK_STENCIL_OP_KEEP
);
903 radv_is_stencil_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
905 return pCreateInfo
->stencilTestEnable
&&
906 (radv_writes_stencil(&pCreateInfo
->front
) ||
907 radv_writes_stencil(&pCreateInfo
->back
));
911 radv_is_ds_write_enabled(const VkPipelineDepthStencilStateCreateInfo
*pCreateInfo
)
913 return radv_is_depth_write_enabled(pCreateInfo
) ||
914 radv_is_stencil_write_enabled(pCreateInfo
);
918 radv_order_invariant_stencil_op(VkStencilOp op
)
920 /* REPLACE is normally order invariant, except when the stencil
921 * reference value is written by the fragment shader. Tracking this
922 * interaction does not seem worth the effort, so be conservative.
924 return op
!= VK_STENCIL_OP_INCREMENT_AND_CLAMP
&&
925 op
!= VK_STENCIL_OP_DECREMENT_AND_CLAMP
&&
926 op
!= VK_STENCIL_OP_REPLACE
;
930 radv_order_invariant_stencil_state(const VkStencilOpState
*state
)
932 /* Compute whether, assuming Z writes are disabled, this stencil state
933 * is order invariant in the sense that the set of passing fragments as
934 * well as the final stencil buffer result does not depend on the order
937 return !state
->writeMask
||
938 /* The following assumes that Z writes are disabled. */
939 (state
->compareOp
== VK_COMPARE_OP_ALWAYS
&&
940 radv_order_invariant_stencil_op(state
->passOp
) &&
941 radv_order_invariant_stencil_op(state
->depthFailOp
)) ||
942 (state
->compareOp
== VK_COMPARE_OP_NEVER
&&
943 radv_order_invariant_stencil_op(state
->failOp
));
947 radv_pipeline_out_of_order_rast(struct radv_pipeline
*pipeline
,
948 struct radv_blend_state
*blend
,
949 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
951 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
952 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
953 const VkPipelineDepthStencilStateCreateInfo
*vkds
= radv_pipeline_get_depth_stencil_state(pCreateInfo
);
954 const VkPipelineColorBlendStateCreateInfo
*vkblend
= radv_pipeline_get_color_blend_state(pCreateInfo
);
955 unsigned colormask
= blend
->cb_target_enabled_4bit
;
957 if (!pipeline
->device
->physical_device
->out_of_order_rast_allowed
)
960 /* Be conservative if a logic operation is enabled with color buffers. */
961 if (colormask
&& vkblend
&& vkblend
->logicOpEnable
)
964 /* Default depth/stencil invariance when no attachment is bound. */
965 struct radv_dsa_order_invariance dsa_order_invariant
= {
966 .zs
= true, .pass_set
= true
970 struct radv_render_pass_attachment
*attachment
=
971 pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
972 bool has_stencil
= vk_format_is_stencil(attachment
->format
);
973 struct radv_dsa_order_invariance order_invariance
[2];
974 struct radv_shader_variant
*ps
=
975 pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
977 /* Compute depth/stencil order invariance in order to know if
978 * it's safe to enable out-of-order.
980 bool zfunc_is_ordered
=
981 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
||
982 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS
||
983 vkds
->depthCompareOp
== VK_COMPARE_OP_LESS_OR_EQUAL
||
984 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER
||
985 vkds
->depthCompareOp
== VK_COMPARE_OP_GREATER_OR_EQUAL
;
987 bool nozwrite_and_order_invariant_stencil
=
988 !radv_is_ds_write_enabled(vkds
) ||
989 (!radv_is_depth_write_enabled(vkds
) &&
990 radv_order_invariant_stencil_state(&vkds
->front
) &&
991 radv_order_invariant_stencil_state(&vkds
->back
));
993 order_invariance
[1].zs
=
994 nozwrite_and_order_invariant_stencil
||
995 (!radv_is_stencil_write_enabled(vkds
) &&
997 order_invariance
[0].zs
=
998 !radv_is_depth_write_enabled(vkds
) || zfunc_is_ordered
;
1000 order_invariance
[1].pass_set
=
1001 nozwrite_and_order_invariant_stencil
||
1002 (!radv_is_stencil_write_enabled(vkds
) &&
1003 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1004 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
));
1005 order_invariance
[0].pass_set
=
1006 !radv_is_depth_write_enabled(vkds
) ||
1007 (vkds
->depthCompareOp
== VK_COMPARE_OP_ALWAYS
||
1008 vkds
->depthCompareOp
== VK_COMPARE_OP_NEVER
);
1010 dsa_order_invariant
= order_invariance
[has_stencil
];
1011 if (!dsa_order_invariant
.zs
)
1014 /* The set of PS invocations is always order invariant,
1015 * except when early Z/S tests are requested.
1018 ps
->info
.ps
.writes_memory
&&
1019 ps
->info
.ps
.early_fragment_test
&&
1020 !dsa_order_invariant
.pass_set
)
1023 /* Determine if out-of-order rasterization should be disabled
1024 * when occlusion queries are used.
1026 pipeline
->graphics
.disable_out_of_order_rast_for_occlusion
=
1027 !dsa_order_invariant
.pass_set
;
1030 /* No color buffers are enabled for writing. */
1034 unsigned blendmask
= colormask
& blend
->blend_enable_4bit
;
1037 /* Only commutative blending. */
1038 if (blendmask
& ~blend
->commutative_4bit
)
1041 if (!dsa_order_invariant
.pass_set
)
1045 if (colormask
& ~blendmask
)
1052 radv_pipeline_init_multisample_state(struct radv_pipeline
*pipeline
,
1053 struct radv_blend_state
*blend
,
1054 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1056 const VkPipelineMultisampleStateCreateInfo
*vkms
= radv_pipeline_get_multisample_state(pCreateInfo
);
1057 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
1058 unsigned num_tile_pipes
= pipeline
->device
->physical_device
->rad_info
.num_tile_pipes
;
1059 bool out_of_order_rast
= false;
1060 int ps_iter_samples
= 1;
1061 uint32_t mask
= 0xffff;
1064 ms
->num_samples
= vkms
->rasterizationSamples
;
1066 /* From the Vulkan 1.1.129 spec, 26.7. Sample Shading:
1068 * "Sample shading is enabled for a graphics pipeline:
1070 * - If the interface of the fragment shader entry point of the
1071 * graphics pipeline includes an input variable decorated
1072 * with SampleId or SamplePosition. In this case
1073 * minSampleShadingFactor takes the value 1.0.
1074 * - Else if the sampleShadingEnable member of the
1075 * VkPipelineMultisampleStateCreateInfo structure specified
1076 * when creating the graphics pipeline is set to VK_TRUE. In
1077 * this case minSampleShadingFactor takes the value of
1078 * VkPipelineMultisampleStateCreateInfo::minSampleShading.
1080 * Otherwise, sample shading is considered disabled."
1082 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.force_persample
) {
1083 ps_iter_samples
= ms
->num_samples
;
1085 ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
);
1088 ms
->num_samples
= 1;
1091 const struct VkPipelineRasterizationStateRasterizationOrderAMD
*raster_order
=
1092 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
, PIPELINE_RASTERIZATION_STATE_RASTERIZATION_ORDER_AMD
);
1093 if (raster_order
&& raster_order
->rasterizationOrder
== VK_RASTERIZATION_ORDER_RELAXED_AMD
) {
1094 /* Out-of-order rasterization is explicitly enabled by the
1097 out_of_order_rast
= true;
1099 /* Determine if the driver can enable out-of-order
1100 * rasterization internally.
1103 radv_pipeline_out_of_order_rast(pipeline
, blend
, pCreateInfo
);
1106 ms
->pa_sc_line_cntl
= S_028BDC_DX10_DIAMOND_TEST_ENA(1);
1107 ms
->pa_sc_aa_config
= 0;
1108 ms
->db_eqaa
= S_028804_HIGH_QUALITY_INTERSECTIONS(1) |
1109 S_028804_INCOHERENT_EQAA_READS(1) |
1110 S_028804_INTERPOLATE_COMP_Z(1) |
1111 S_028804_STATIC_ANCHOR_ASSOCIATIONS(1);
1112 ms
->pa_sc_mode_cntl_1
=
1113 S_028A4C_WALK_FENCE_ENABLE(1) | //TODO linear dst fixes
1114 S_028A4C_WALK_FENCE_SIZE(num_tile_pipes
== 2 ? 2 : 3) |
1115 S_028A4C_OUT_OF_ORDER_PRIMITIVE_ENABLE(out_of_order_rast
) |
1116 S_028A4C_OUT_OF_ORDER_WATER_MARK(0x7) |
1118 S_028A4C_WALK_ALIGN8_PRIM_FITS_ST(1) |
1119 S_028A4C_SUPERTILE_WALK_ORDER_ENABLE(1) |
1120 S_028A4C_TILE_WALK_ORDER_ENABLE(1) |
1121 S_028A4C_MULTI_SHADER_ENGINE_PRIM_DISCARD_ENABLE(1) |
1122 S_028A4C_FORCE_EOV_CNTDWN_ENABLE(1) |
1123 S_028A4C_FORCE_EOV_REZ_ENABLE(1);
1124 ms
->pa_sc_mode_cntl_0
= S_028A48_ALTERNATE_RBS_PER_TILE(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
1125 S_028A48_VPORT_SCISSOR_ENABLE(1);
1127 const VkPipelineRasterizationLineStateCreateInfoEXT
*rast_line
=
1128 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1129 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1131 ms
->pa_sc_mode_cntl_0
|= S_028A48_LINE_STIPPLE_ENABLE(rast_line
->stippledLineEnable
);
1132 if (rast_line
->lineRasterizationMode
== VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT
) {
1133 /* From the Vulkan spec 1.1.129:
1135 * "When VK_LINE_RASTERIZATION_MODE_BRESENHAM_EXT lines
1136 * are being rasterized, sample locations may all be
1137 * treated as being at the pixel center (this may
1138 * affect attribute and depth interpolation)."
1140 ms
->num_samples
= 1;
1144 if (ms
->num_samples
> 1) {
1145 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1146 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1147 uint32_t z_samples
= subpass
->depth_stencil_attachment
? subpass
->depth_sample_count
: ms
->num_samples
;
1148 unsigned log_samples
= util_logbase2(ms
->num_samples
);
1149 unsigned log_z_samples
= util_logbase2(z_samples
);
1150 unsigned log_ps_iter_samples
= util_logbase2(ps_iter_samples
);
1151 ms
->pa_sc_mode_cntl_0
|= S_028A48_MSAA_ENABLE(1);
1152 ms
->db_eqaa
|= S_028804_MAX_ANCHOR_SAMPLES(log_z_samples
) |
1153 S_028804_PS_ITER_SAMPLES(log_ps_iter_samples
) |
1154 S_028804_MASK_EXPORT_NUM_SAMPLES(log_samples
) |
1155 S_028804_ALPHA_TO_MASK_NUM_SAMPLES(log_samples
);
1156 ms
->pa_sc_aa_config
|= S_028BE0_MSAA_NUM_SAMPLES(log_samples
) |
1157 S_028BE0_MAX_SAMPLE_DIST(radv_get_default_max_sample_dist(log_samples
)) |
1158 S_028BE0_MSAA_EXPOSED_SAMPLES(log_samples
) | /* CM_R_028BE0_PA_SC_AA_CONFIG */
1159 S_028BE0_COVERED_CENTROID_IS_CENTER_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
);
1160 ms
->pa_sc_mode_cntl_1
|= S_028A4C_PS_ITER_SAMPLE(ps_iter_samples
> 1);
1161 if (ps_iter_samples
> 1)
1162 pipeline
->graphics
.spi_baryc_cntl
|= S_0286E0_POS_FLOAT_LOCATION(2);
1165 if (vkms
&& vkms
->pSampleMask
) {
1166 mask
= vkms
->pSampleMask
[0] & 0xffff;
1169 ms
->pa_sc_aa_mask
[0] = mask
| (mask
<< 16);
1170 ms
->pa_sc_aa_mask
[1] = mask
| (mask
<< 16);
1174 radv_prim_can_use_guardband(enum VkPrimitiveTopology topology
)
1177 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1178 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1179 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1180 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1181 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1183 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1184 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1185 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1186 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1187 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1188 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1191 unreachable("unhandled primitive type");
1196 si_conv_gl_prim_to_gs_out(unsigned gl_prim
)
1199 case 0: /* GL_POINTS */
1200 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1201 case 1: /* GL_LINES */
1202 case 3: /* GL_LINE_STRIP */
1203 case 0xA: /* GL_LINE_STRIP_ADJACENCY_ARB */
1204 case 0x8E7A: /* GL_ISOLINES */
1205 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1207 case 4: /* GL_TRIANGLES */
1208 case 0xc: /* GL_TRIANGLES_ADJACENCY_ARB */
1209 case 5: /* GL_TRIANGLE_STRIP */
1210 case 7: /* GL_QUADS */
1211 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1219 si_conv_prim_to_gs_out(enum VkPrimitiveTopology topology
)
1222 case VK_PRIMITIVE_TOPOLOGY_POINT_LIST
:
1223 case VK_PRIMITIVE_TOPOLOGY_PATCH_LIST
:
1224 return V_028A6C_OUTPRIM_TYPE_POINTLIST
;
1225 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST
:
1226 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP
:
1227 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1228 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1229 return V_028A6C_OUTPRIM_TYPE_LINESTRIP
;
1230 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST
:
1231 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP
:
1232 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_FAN
:
1233 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1234 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1235 return V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
1242 static unsigned radv_dynamic_state_mask(VkDynamicState state
)
1245 case VK_DYNAMIC_STATE_VIEWPORT
:
1246 return RADV_DYNAMIC_VIEWPORT
;
1247 case VK_DYNAMIC_STATE_SCISSOR
:
1248 return RADV_DYNAMIC_SCISSOR
;
1249 case VK_DYNAMIC_STATE_LINE_WIDTH
:
1250 return RADV_DYNAMIC_LINE_WIDTH
;
1251 case VK_DYNAMIC_STATE_DEPTH_BIAS
:
1252 return RADV_DYNAMIC_DEPTH_BIAS
;
1253 case VK_DYNAMIC_STATE_BLEND_CONSTANTS
:
1254 return RADV_DYNAMIC_BLEND_CONSTANTS
;
1255 case VK_DYNAMIC_STATE_DEPTH_BOUNDS
:
1256 return RADV_DYNAMIC_DEPTH_BOUNDS
;
1257 case VK_DYNAMIC_STATE_STENCIL_COMPARE_MASK
:
1258 return RADV_DYNAMIC_STENCIL_COMPARE_MASK
;
1259 case VK_DYNAMIC_STATE_STENCIL_WRITE_MASK
:
1260 return RADV_DYNAMIC_STENCIL_WRITE_MASK
;
1261 case VK_DYNAMIC_STATE_STENCIL_REFERENCE
:
1262 return RADV_DYNAMIC_STENCIL_REFERENCE
;
1263 case VK_DYNAMIC_STATE_DISCARD_RECTANGLE_EXT
:
1264 return RADV_DYNAMIC_DISCARD_RECTANGLE
;
1265 case VK_DYNAMIC_STATE_SAMPLE_LOCATIONS_EXT
:
1266 return RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1267 case VK_DYNAMIC_STATE_LINE_STIPPLE_EXT
:
1268 return RADV_DYNAMIC_LINE_STIPPLE
;
1269 case VK_DYNAMIC_STATE_CULL_MODE_EXT
:
1270 return RADV_DYNAMIC_CULL_MODE
;
1271 case VK_DYNAMIC_STATE_FRONT_FACE_EXT
:
1272 return RADV_DYNAMIC_FRONT_FACE
;
1273 case VK_DYNAMIC_STATE_PRIMITIVE_TOPOLOGY_EXT
:
1274 return RADV_DYNAMIC_PRIMITIVE_TOPOLOGY
;
1276 unreachable("Unhandled dynamic state");
1280 static uint32_t radv_pipeline_needed_dynamic_state(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1282 uint32_t states
= RADV_DYNAMIC_ALL
;
1284 /* If rasterization is disabled we do not care about any of the
1285 * dynamic states, since they are all rasterization related only,
1286 * except primitive topology.
1288 if (pCreateInfo
->pRasterizationState
->rasterizerDiscardEnable
)
1289 return RADV_DYNAMIC_PRIMITIVE_TOPOLOGY
;
1291 if (!pCreateInfo
->pRasterizationState
->depthBiasEnable
)
1292 states
&= ~RADV_DYNAMIC_DEPTH_BIAS
;
1294 if (!pCreateInfo
->pDepthStencilState
||
1295 !pCreateInfo
->pDepthStencilState
->depthBoundsTestEnable
)
1296 states
&= ~RADV_DYNAMIC_DEPTH_BOUNDS
;
1298 if (!pCreateInfo
->pDepthStencilState
||
1299 !pCreateInfo
->pDepthStencilState
->stencilTestEnable
)
1300 states
&= ~(RADV_DYNAMIC_STENCIL_COMPARE_MASK
|
1301 RADV_DYNAMIC_STENCIL_WRITE_MASK
|
1302 RADV_DYNAMIC_STENCIL_REFERENCE
);
1304 if (!vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
))
1305 states
&= ~RADV_DYNAMIC_DISCARD_RECTANGLE
;
1307 if (!pCreateInfo
->pMultisampleState
||
1308 !vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1309 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
))
1310 states
&= ~RADV_DYNAMIC_SAMPLE_LOCATIONS
;
1312 if (!pCreateInfo
->pRasterizationState
||
1313 !vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1314 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
))
1315 states
&= ~RADV_DYNAMIC_LINE_STIPPLE
;
1317 /* TODO: blend constants & line width. */
1324 radv_pipeline_init_dynamic_state(struct radv_pipeline
*pipeline
,
1325 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
1326 const struct radv_graphics_pipeline_create_info
*extra
)
1328 uint32_t needed_states
= radv_pipeline_needed_dynamic_state(pCreateInfo
);
1329 uint32_t states
= needed_states
;
1330 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
1331 struct radv_subpass
*subpass
= &pass
->subpasses
[pCreateInfo
->subpass
];
1333 pipeline
->dynamic_state
= default_dynamic_state
;
1334 pipeline
->graphics
.needed_dynamic_state
= needed_states
;
1336 if (pCreateInfo
->pDynamicState
) {
1337 /* Remove all of the states that are marked as dynamic */
1338 uint32_t count
= pCreateInfo
->pDynamicState
->dynamicStateCount
;
1339 for (uint32_t s
= 0; s
< count
; s
++)
1340 states
&= ~radv_dynamic_state_mask(pCreateInfo
->pDynamicState
->pDynamicStates
[s
]);
1343 struct radv_dynamic_state
*dynamic
= &pipeline
->dynamic_state
;
1345 if (needed_states
& RADV_DYNAMIC_VIEWPORT
) {
1346 assert(pCreateInfo
->pViewportState
);
1348 dynamic
->viewport
.count
= pCreateInfo
->pViewportState
->viewportCount
;
1349 if (states
& RADV_DYNAMIC_VIEWPORT
) {
1350 typed_memcpy(dynamic
->viewport
.viewports
,
1351 pCreateInfo
->pViewportState
->pViewports
,
1352 pCreateInfo
->pViewportState
->viewportCount
);
1356 if (needed_states
& RADV_DYNAMIC_SCISSOR
) {
1357 dynamic
->scissor
.count
= pCreateInfo
->pViewportState
->scissorCount
;
1358 if (states
& RADV_DYNAMIC_SCISSOR
) {
1359 typed_memcpy(dynamic
->scissor
.scissors
,
1360 pCreateInfo
->pViewportState
->pScissors
,
1361 pCreateInfo
->pViewportState
->scissorCount
);
1365 if (states
& RADV_DYNAMIC_LINE_WIDTH
) {
1366 assert(pCreateInfo
->pRasterizationState
);
1367 dynamic
->line_width
= pCreateInfo
->pRasterizationState
->lineWidth
;
1370 if (states
& RADV_DYNAMIC_DEPTH_BIAS
) {
1371 assert(pCreateInfo
->pRasterizationState
);
1372 dynamic
->depth_bias
.bias
=
1373 pCreateInfo
->pRasterizationState
->depthBiasConstantFactor
;
1374 dynamic
->depth_bias
.clamp
=
1375 pCreateInfo
->pRasterizationState
->depthBiasClamp
;
1376 dynamic
->depth_bias
.slope
=
1377 pCreateInfo
->pRasterizationState
->depthBiasSlopeFactor
;
1380 /* Section 9.2 of the Vulkan 1.0.15 spec says:
1382 * pColorBlendState is [...] NULL if the pipeline has rasterization
1383 * disabled or if the subpass of the render pass the pipeline is
1384 * created against does not use any color attachments.
1386 if (subpass
->has_color_att
&& states
& RADV_DYNAMIC_BLEND_CONSTANTS
) {
1387 assert(pCreateInfo
->pColorBlendState
);
1388 typed_memcpy(dynamic
->blend_constants
,
1389 pCreateInfo
->pColorBlendState
->blendConstants
, 4);
1392 if (states
& RADV_DYNAMIC_CULL_MODE
) {
1393 dynamic
->cull_mode
=
1394 pCreateInfo
->pRasterizationState
->cullMode
;
1397 if (states
& RADV_DYNAMIC_FRONT_FACE
) {
1398 dynamic
->front_face
=
1399 pCreateInfo
->pRasterizationState
->frontFace
;
1402 if (states
& RADV_DYNAMIC_PRIMITIVE_TOPOLOGY
) {
1403 dynamic
->primitive_topology
=
1404 si_translate_prim(pCreateInfo
->pInputAssemblyState
->topology
);
1405 if (extra
&& extra
->use_rectlist
) {
1406 dynamic
->primitive_topology
= V_008958_DI_PT_RECTLIST
;
1410 /* If there is no depthstencil attachment, then don't read
1411 * pDepthStencilState. The Vulkan spec states that pDepthStencilState may
1412 * be NULL in this case. Even if pDepthStencilState is non-NULL, there is
1413 * no need to override the depthstencil defaults in
1414 * radv_pipeline::dynamic_state when there is no depthstencil attachment.
1416 * Section 9.2 of the Vulkan 1.0.15 spec says:
1418 * pDepthStencilState is [...] NULL if the pipeline has rasterization
1419 * disabled or if the subpass of the render pass the pipeline is created
1420 * against does not use a depth/stencil attachment.
1422 if (needed_states
&& subpass
->depth_stencil_attachment
) {
1423 assert(pCreateInfo
->pDepthStencilState
);
1425 if (states
& RADV_DYNAMIC_DEPTH_BOUNDS
) {
1426 dynamic
->depth_bounds
.min
=
1427 pCreateInfo
->pDepthStencilState
->minDepthBounds
;
1428 dynamic
->depth_bounds
.max
=
1429 pCreateInfo
->pDepthStencilState
->maxDepthBounds
;
1432 if (states
& RADV_DYNAMIC_STENCIL_COMPARE_MASK
) {
1433 dynamic
->stencil_compare_mask
.front
=
1434 pCreateInfo
->pDepthStencilState
->front
.compareMask
;
1435 dynamic
->stencil_compare_mask
.back
=
1436 pCreateInfo
->pDepthStencilState
->back
.compareMask
;
1439 if (states
& RADV_DYNAMIC_STENCIL_WRITE_MASK
) {
1440 dynamic
->stencil_write_mask
.front
=
1441 pCreateInfo
->pDepthStencilState
->front
.writeMask
;
1442 dynamic
->stencil_write_mask
.back
=
1443 pCreateInfo
->pDepthStencilState
->back
.writeMask
;
1446 if (states
& RADV_DYNAMIC_STENCIL_REFERENCE
) {
1447 dynamic
->stencil_reference
.front
=
1448 pCreateInfo
->pDepthStencilState
->front
.reference
;
1449 dynamic
->stencil_reference
.back
=
1450 pCreateInfo
->pDepthStencilState
->back
.reference
;
1454 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
1455 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
1456 if (needed_states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1457 dynamic
->discard_rectangle
.count
= discard_rectangle_info
->discardRectangleCount
;
1458 if (states
& RADV_DYNAMIC_DISCARD_RECTANGLE
) {
1459 typed_memcpy(dynamic
->discard_rectangle
.rectangles
,
1460 discard_rectangle_info
->pDiscardRectangles
,
1461 discard_rectangle_info
->discardRectangleCount
);
1465 if (needed_states
& RADV_DYNAMIC_SAMPLE_LOCATIONS
) {
1466 const VkPipelineSampleLocationsStateCreateInfoEXT
*sample_location_info
=
1467 vk_find_struct_const(pCreateInfo
->pMultisampleState
->pNext
,
1468 PIPELINE_SAMPLE_LOCATIONS_STATE_CREATE_INFO_EXT
);
1469 /* If sampleLocationsEnable is VK_FALSE, the default sample
1470 * locations are used and the values specified in
1471 * sampleLocationsInfo are ignored.
1473 if (sample_location_info
->sampleLocationsEnable
) {
1474 const VkSampleLocationsInfoEXT
*pSampleLocationsInfo
=
1475 &sample_location_info
->sampleLocationsInfo
;
1477 assert(pSampleLocationsInfo
->sampleLocationsCount
<= MAX_SAMPLE_LOCATIONS
);
1479 dynamic
->sample_location
.per_pixel
= pSampleLocationsInfo
->sampleLocationsPerPixel
;
1480 dynamic
->sample_location
.grid_size
= pSampleLocationsInfo
->sampleLocationGridSize
;
1481 dynamic
->sample_location
.count
= pSampleLocationsInfo
->sampleLocationsCount
;
1482 typed_memcpy(&dynamic
->sample_location
.locations
[0],
1483 pSampleLocationsInfo
->pSampleLocations
,
1484 pSampleLocationsInfo
->sampleLocationsCount
);
1488 const VkPipelineRasterizationLineStateCreateInfoEXT
*rast_line_info
=
1489 vk_find_struct_const(pCreateInfo
->pRasterizationState
->pNext
,
1490 PIPELINE_RASTERIZATION_LINE_STATE_CREATE_INFO_EXT
);
1491 if (needed_states
& RADV_DYNAMIC_LINE_STIPPLE
) {
1492 dynamic
->line_stipple
.factor
= rast_line_info
->lineStippleFactor
;
1493 dynamic
->line_stipple
.pattern
= rast_line_info
->lineStipplePattern
;
1496 pipeline
->dynamic_state
.mask
= states
;
1500 gfx9_get_gs_info(const struct radv_pipeline_key
*key
,
1501 const struct radv_pipeline
*pipeline
,
1503 struct radv_shader_info
*infos
,
1504 struct gfx9_gs_info
*out
)
1506 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1507 struct radv_es_output_info
*es_info
;
1508 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
1509 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1511 es_info
= nir
[MESA_SHADER_TESS_CTRL
] ?
1512 &infos
[MESA_SHADER_TESS_EVAL
].tes
.es_info
:
1513 &infos
[MESA_SHADER_VERTEX
].vs
.es_info
;
1515 unsigned gs_num_invocations
= MAX2(gs_info
->gs
.invocations
, 1);
1516 bool uses_adjacency
;
1517 switch(key
->topology
) {
1518 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1519 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1520 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1521 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1522 uses_adjacency
= true;
1525 uses_adjacency
= false;
1529 /* All these are in dwords: */
1530 /* We can't allow using the whole LDS, because GS waves compete with
1531 * other shader stages for LDS space. */
1532 const unsigned max_lds_size
= 8 * 1024;
1533 const unsigned esgs_itemsize
= es_info
->esgs_itemsize
/ 4;
1534 unsigned esgs_lds_size
;
1536 /* All these are per subgroup: */
1537 const unsigned max_out_prims
= 32 * 1024;
1538 const unsigned max_es_verts
= 255;
1539 const unsigned ideal_gs_prims
= 64;
1540 unsigned max_gs_prims
, gs_prims
;
1541 unsigned min_es_verts
, es_verts
, worst_case_es_verts
;
1543 if (uses_adjacency
|| gs_num_invocations
> 1)
1544 max_gs_prims
= 127 / gs_num_invocations
;
1548 /* MAX_PRIMS_PER_SUBGROUP = gs_prims * max_vert_out * gs_invocations.
1549 * Make sure we don't go over the maximum value.
1551 if (gs_info
->gs
.vertices_out
> 0) {
1552 max_gs_prims
= MIN2(max_gs_prims
,
1554 (gs_info
->gs
.vertices_out
* gs_num_invocations
));
1556 assert(max_gs_prims
> 0);
1558 /* If the primitive has adjacency, halve the number of vertices
1559 * that will be reused in multiple primitives.
1561 min_es_verts
= gs_info
->gs
.vertices_in
/ (uses_adjacency
? 2 : 1);
1563 gs_prims
= MIN2(ideal_gs_prims
, max_gs_prims
);
1564 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
, max_es_verts
);
1566 /* Compute ESGS LDS size based on the worst case number of ES vertices
1567 * needed to create the target number of GS prims per subgroup.
1569 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1571 /* If total LDS usage is too big, refactor partitions based on ratio
1572 * of ESGS item sizes.
1574 if (esgs_lds_size
> max_lds_size
) {
1575 /* Our target GS Prims Per Subgroup was too large. Calculate
1576 * the maximum number of GS Prims Per Subgroup that will fit
1577 * into LDS, capped by the maximum that the hardware can support.
1579 gs_prims
= MIN2((max_lds_size
/ (esgs_itemsize
* min_es_verts
)),
1581 assert(gs_prims
> 0);
1582 worst_case_es_verts
= MIN2(min_es_verts
* gs_prims
,
1585 esgs_lds_size
= esgs_itemsize
* worst_case_es_verts
;
1586 assert(esgs_lds_size
<= max_lds_size
);
1589 /* Now calculate remaining ESGS information. */
1591 es_verts
= MIN2(esgs_lds_size
/ esgs_itemsize
, max_es_verts
);
1593 es_verts
= max_es_verts
;
1595 /* Vertices for adjacency primitives are not always reused, so restore
1596 * it for ES_VERTS_PER_SUBGRP.
1598 min_es_verts
= gs_info
->gs
.vertices_in
;
1600 /* For normal primitives, the VGT only checks if they are past the ES
1601 * verts per subgroup after allocating a full GS primitive and if they
1602 * are, kick off a new subgroup. But if those additional ES verts are
1603 * unique (e.g. not reused) we need to make sure there is enough LDS
1604 * space to account for those ES verts beyond ES_VERTS_PER_SUBGRP.
1606 es_verts
-= min_es_verts
- 1;
1608 uint32_t es_verts_per_subgroup
= es_verts
;
1609 uint32_t gs_prims_per_subgroup
= gs_prims
;
1610 uint32_t gs_inst_prims_in_subgroup
= gs_prims
* gs_num_invocations
;
1611 uint32_t max_prims_per_subgroup
= gs_inst_prims_in_subgroup
* gs_info
->gs
.vertices_out
;
1612 out
->lds_size
= align(esgs_lds_size
, 128) / 128;
1613 out
->vgt_gs_onchip_cntl
= S_028A44_ES_VERTS_PER_SUBGRP(es_verts_per_subgroup
) |
1614 S_028A44_GS_PRIMS_PER_SUBGRP(gs_prims_per_subgroup
) |
1615 S_028A44_GS_INST_PRIMS_IN_SUBGRP(gs_inst_prims_in_subgroup
);
1616 out
->vgt_gs_max_prims_per_subgroup
= S_028A94_MAX_PRIMS_PER_SUBGROUP(max_prims_per_subgroup
);
1617 out
->vgt_esgs_ring_itemsize
= esgs_itemsize
;
1618 assert(max_prims_per_subgroup
<= max_out_prims
);
1621 static void clamp_gsprims_to_esverts(unsigned *max_gsprims
, unsigned max_esverts
,
1622 unsigned min_verts_per_prim
, bool use_adjacency
)
1624 unsigned max_reuse
= max_esverts
- min_verts_per_prim
;
1627 *max_gsprims
= MIN2(*max_gsprims
, 1 + max_reuse
);
1631 radv_get_num_input_vertices(nir_shader
**nir
)
1633 if (nir
[MESA_SHADER_GEOMETRY
]) {
1634 nir_shader
*gs
= nir
[MESA_SHADER_GEOMETRY
];
1636 return gs
->info
.gs
.vertices_in
;
1639 if (nir
[MESA_SHADER_TESS_CTRL
]) {
1640 nir_shader
*tes
= nir
[MESA_SHADER_TESS_EVAL
];
1642 if (tes
->info
.tess
.point_mode
)
1644 if (tes
->info
.tess
.primitive_mode
== GL_ISOLINES
)
1653 gfx10_get_ngg_info(const struct radv_pipeline_key
*key
,
1654 struct radv_pipeline
*pipeline
,
1656 struct radv_shader_info
*infos
,
1657 struct gfx10_ngg_info
*ngg
)
1659 struct radv_shader_info
*gs_info
= &infos
[MESA_SHADER_GEOMETRY
];
1660 struct radv_es_output_info
*es_info
=
1661 nir
[MESA_SHADER_TESS_CTRL
] ? &gs_info
->tes
.es_info
: &gs_info
->vs
.es_info
;
1662 unsigned gs_type
= nir
[MESA_SHADER_GEOMETRY
] ? MESA_SHADER_GEOMETRY
: MESA_SHADER_VERTEX
;
1663 unsigned max_verts_per_prim
= radv_get_num_input_vertices(nir
);
1664 unsigned min_verts_per_prim
=
1665 gs_type
== MESA_SHADER_GEOMETRY
? max_verts_per_prim
: 1;
1666 unsigned gs_num_invocations
= nir
[MESA_SHADER_GEOMETRY
] ? MAX2(gs_info
->gs
.invocations
, 1) : 1;
1667 bool uses_adjacency
;
1668 switch(key
->topology
) {
1669 case VK_PRIMITIVE_TOPOLOGY_LINE_LIST_WITH_ADJACENCY
:
1670 case VK_PRIMITIVE_TOPOLOGY_LINE_STRIP_WITH_ADJACENCY
:
1671 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_LIST_WITH_ADJACENCY
:
1672 case VK_PRIMITIVE_TOPOLOGY_TRIANGLE_STRIP_WITH_ADJACENCY
:
1673 uses_adjacency
= true;
1676 uses_adjacency
= false;
1680 /* All these are in dwords: */
1681 /* We can't allow using the whole LDS, because GS waves compete with
1682 * other shader stages for LDS space.
1684 * TODO: We should really take the shader's internal LDS use into
1685 * account. The linker will fail if the size is greater than
1688 const unsigned max_lds_size
= 8 * 1024 - 768;
1689 const unsigned target_lds_size
= max_lds_size
;
1690 unsigned esvert_lds_size
= 0;
1691 unsigned gsprim_lds_size
= 0;
1693 /* All these are per subgroup: */
1694 bool max_vert_out_per_gs_instance
= false;
1695 unsigned max_esverts_base
= 256;
1696 unsigned max_gsprims_base
= 128; /* default prim group size clamp */
1698 /* Hardware has the following non-natural restrictions on the value
1699 * of GE_CNTL.VERT_GRP_SIZE based on based on the primitive type of
1701 * - at most 252 for any line input primitive type
1702 * - at most 251 for any quad input primitive type
1703 * - at most 251 for triangle strips with adjacency (this happens to
1704 * be the natural limit for triangle *lists* with adjacency)
1706 max_esverts_base
= MIN2(max_esverts_base
, 251 + max_verts_per_prim
- 1);
1708 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1709 unsigned max_out_verts_per_gsprim
=
1710 gs_info
->gs
.vertices_out
* gs_num_invocations
;
1712 if (max_out_verts_per_gsprim
<= 256) {
1713 if (max_out_verts_per_gsprim
) {
1714 max_gsprims_base
= MIN2(max_gsprims_base
,
1715 256 / max_out_verts_per_gsprim
);
1718 /* Use special multi-cycling mode in which each GS
1719 * instance gets its own subgroup. Does not work with
1721 max_vert_out_per_gs_instance
= true;
1722 max_gsprims_base
= 1;
1723 max_out_verts_per_gsprim
= gs_info
->gs
.vertices_out
;
1726 esvert_lds_size
= es_info
->esgs_itemsize
/ 4;
1727 gsprim_lds_size
= (gs_info
->gs
.gsvs_vertex_size
/ 4 + 1) * max_out_verts_per_gsprim
;
1730 /* LDS size for passing data from GS to ES. */
1731 struct radv_streamout_info
*so_info
= nir
[MESA_SHADER_TESS_CTRL
]
1732 ? &infos
[MESA_SHADER_TESS_EVAL
].so
1733 : &infos
[MESA_SHADER_VERTEX
].so
;
1735 if (so_info
->num_outputs
)
1736 esvert_lds_size
= 4 * so_info
->num_outputs
+ 1;
1738 /* GS stores Primitive IDs (one DWORD) into LDS at the address
1739 * corresponding to the ES thread of the provoking vertex. All
1740 * ES threads load and export PrimitiveID for their thread.
1742 if (!nir
[MESA_SHADER_TESS_CTRL
] &&
1743 infos
[MESA_SHADER_VERTEX
].vs
.outinfo
.export_prim_id
)
1744 esvert_lds_size
= MAX2(esvert_lds_size
, 1);
1747 unsigned max_gsprims
= max_gsprims_base
;
1748 unsigned max_esverts
= max_esverts_base
;
1750 if (esvert_lds_size
)
1751 max_esverts
= MIN2(max_esverts
, target_lds_size
/ esvert_lds_size
);
1752 if (gsprim_lds_size
)
1753 max_gsprims
= MIN2(max_gsprims
, target_lds_size
/ gsprim_lds_size
);
1755 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1756 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
, min_verts_per_prim
, uses_adjacency
);
1757 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1759 if (esvert_lds_size
|| gsprim_lds_size
) {
1760 /* Now that we have a rough proportionality between esverts
1761 * and gsprims based on the primitive type, scale both of them
1762 * down simultaneously based on required LDS space.
1764 * We could be smarter about this if we knew how much vertex
1767 unsigned lds_total
= max_esverts
* esvert_lds_size
+
1768 max_gsprims
* gsprim_lds_size
;
1769 if (lds_total
> target_lds_size
) {
1770 max_esverts
= max_esverts
* target_lds_size
/ lds_total
;
1771 max_gsprims
= max_gsprims
* target_lds_size
/ lds_total
;
1773 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1774 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1775 min_verts_per_prim
, uses_adjacency
);
1776 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1780 /* Round up towards full wave sizes for better ALU utilization. */
1781 if (!max_vert_out_per_gs_instance
) {
1782 unsigned orig_max_esverts
;
1783 unsigned orig_max_gsprims
;
1786 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1787 wavesize
= gs_info
->wave_size
;
1789 wavesize
= nir
[MESA_SHADER_TESS_CTRL
]
1790 ? infos
[MESA_SHADER_TESS_EVAL
].wave_size
1791 : infos
[MESA_SHADER_VERTEX
].wave_size
;
1795 orig_max_esverts
= max_esverts
;
1796 orig_max_gsprims
= max_gsprims
;
1798 max_esverts
= align(max_esverts
, wavesize
);
1799 max_esverts
= MIN2(max_esverts
, max_esverts_base
);
1800 if (esvert_lds_size
)
1801 max_esverts
= MIN2(max_esverts
,
1802 (max_lds_size
- max_gsprims
* gsprim_lds_size
) /
1804 max_esverts
= MIN2(max_esverts
, max_gsprims
* max_verts_per_prim
);
1806 max_gsprims
= align(max_gsprims
, wavesize
);
1807 max_gsprims
= MIN2(max_gsprims
, max_gsprims_base
);
1808 if (gsprim_lds_size
)
1809 max_gsprims
= MIN2(max_gsprims
,
1810 (max_lds_size
- max_esverts
* esvert_lds_size
) /
1812 clamp_gsprims_to_esverts(&max_gsprims
, max_esverts
,
1813 min_verts_per_prim
, uses_adjacency
);
1814 assert(max_esverts
>= max_verts_per_prim
&& max_gsprims
>= 1);
1815 } while (orig_max_esverts
!= max_esverts
|| orig_max_gsprims
!= max_gsprims
);
1818 /* Hardware restriction: minimum value of max_esverts */
1819 max_esverts
= MAX2(max_esverts
, 23 + max_verts_per_prim
);
1821 unsigned max_out_vertices
=
1822 max_vert_out_per_gs_instance
? gs_info
->gs
.vertices_out
:
1823 gs_type
== MESA_SHADER_GEOMETRY
?
1824 max_gsprims
* gs_num_invocations
* gs_info
->gs
.vertices_out
:
1826 assert(max_out_vertices
<= 256);
1828 unsigned prim_amp_factor
= 1;
1829 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1830 /* Number of output primitives per GS input primitive after
1832 prim_amp_factor
= gs_info
->gs
.vertices_out
;
1835 /* The GE only checks against the maximum number of ES verts after
1836 * allocating a full GS primitive. So we need to ensure that whenever
1837 * this check passes, there is enough space for a full primitive without
1840 ngg
->hw_max_esverts
= max_esverts
- max_verts_per_prim
+ 1;
1841 ngg
->max_gsprims
= max_gsprims
;
1842 ngg
->max_out_verts
= max_out_vertices
;
1843 ngg
->prim_amp_factor
= prim_amp_factor
;
1844 ngg
->max_vert_out_per_gs_instance
= max_vert_out_per_gs_instance
;
1845 ngg
->ngg_emit_size
= max_gsprims
* gsprim_lds_size
;
1846 ngg
->esgs_ring_size
= 4 * max_esverts
* esvert_lds_size
;
1848 if (gs_type
== MESA_SHADER_GEOMETRY
) {
1849 ngg
->vgt_esgs_ring_itemsize
= es_info
->esgs_itemsize
/ 4;
1851 ngg
->vgt_esgs_ring_itemsize
= 1;
1854 pipeline
->graphics
.esgs_ring_size
= ngg
->esgs_ring_size
;
1856 assert(ngg
->hw_max_esverts
>= 24); /* HW limitation */
1860 calculate_gs_ring_sizes(struct radv_pipeline
*pipeline
,
1861 const struct gfx9_gs_info
*gs
)
1863 struct radv_device
*device
= pipeline
->device
;
1864 unsigned num_se
= device
->physical_device
->rad_info
.max_se
;
1865 unsigned wave_size
= 64;
1866 unsigned max_gs_waves
= 32 * num_se
; /* max 32 per SE on GCN */
1867 /* On GFX6-GFX7, the value comes from VGT_GS_VERTEX_REUSE = 16.
1868 * On GFX8+, the value comes from VGT_VERTEX_REUSE_BLOCK_CNTL = 30 (+2).
1870 unsigned gs_vertex_reuse
=
1871 (device
->physical_device
->rad_info
.chip_class
>= GFX8
? 32 : 16) * num_se
;
1872 unsigned alignment
= 256 * num_se
;
1873 /* The maximum size is 63.999 MB per SE. */
1874 unsigned max_size
= ((unsigned)(63.999 * 1024 * 1024) & ~255) * num_se
;
1875 struct radv_shader_info
*gs_info
= &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
;
1877 /* Calculate the minimum size. */
1878 unsigned min_esgs_ring_size
= align(gs
->vgt_esgs_ring_itemsize
* 4 * gs_vertex_reuse
*
1879 wave_size
, alignment
);
1880 /* These are recommended sizes, not minimum sizes. */
1881 unsigned esgs_ring_size
= max_gs_waves
* 2 * wave_size
*
1882 gs
->vgt_esgs_ring_itemsize
* 4 * gs_info
->gs
.vertices_in
;
1883 unsigned gsvs_ring_size
= max_gs_waves
* 2 * wave_size
*
1884 gs_info
->gs
.max_gsvs_emit_size
;
1886 min_esgs_ring_size
= align(min_esgs_ring_size
, alignment
);
1887 esgs_ring_size
= align(esgs_ring_size
, alignment
);
1888 gsvs_ring_size
= align(gsvs_ring_size
, alignment
);
1890 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
1891 pipeline
->graphics
.esgs_ring_size
= CLAMP(esgs_ring_size
, min_esgs_ring_size
, max_size
);
1893 pipeline
->graphics
.gsvs_ring_size
= MIN2(gsvs_ring_size
, max_size
);
1896 static void si_multiwave_lds_size_workaround(struct radv_device
*device
,
1899 /* If tessellation is all offchip and on-chip GS isn't used, this
1900 * workaround is not needed.
1904 /* SPI barrier management bug:
1905 * Make sure we have at least 4k of LDS in use to avoid the bug.
1906 * It applies to workgroup sizes of more than one wavefront.
1908 if (device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
||
1909 device
->physical_device
->rad_info
.family
== CHIP_KABINI
)
1910 *lds_size
= MAX2(*lds_size
, 8);
1913 struct radv_shader_variant
*
1914 radv_get_shader(struct radv_pipeline
*pipeline
,
1915 gl_shader_stage stage
)
1917 if (stage
== MESA_SHADER_VERTEX
) {
1918 if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
1919 return pipeline
->shaders
[MESA_SHADER_VERTEX
];
1920 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
])
1921 return pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
1922 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1923 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1924 } else if (stage
== MESA_SHADER_TESS_EVAL
) {
1925 if (!radv_pipeline_has_tess(pipeline
))
1927 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
1928 return pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
1929 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
])
1930 return pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
1932 return pipeline
->shaders
[stage
];
1935 static struct radv_tessellation_state
1936 calculate_tess_state(struct radv_pipeline
*pipeline
,
1937 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
1939 unsigned num_tcs_input_cp
;
1940 unsigned num_tcs_output_cp
;
1942 unsigned num_patches
;
1943 struct radv_tessellation_state tess
= {0};
1945 num_tcs_input_cp
= pCreateInfo
->pTessellationState
->patchControlPoints
;
1946 num_tcs_output_cp
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.tcs_vertices_out
; //TCS VERTICES OUT
1947 num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
1949 lds_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.lds_size
;
1951 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
) {
1952 assert(lds_size
<= 65536);
1953 lds_size
= align(lds_size
, 512) / 512;
1955 assert(lds_size
<= 32768);
1956 lds_size
= align(lds_size
, 256) / 256;
1958 si_multiwave_lds_size_workaround(pipeline
->device
, &lds_size
);
1960 tess
.lds_size
= lds_size
;
1962 tess
.ls_hs_config
= S_028B58_NUM_PATCHES(num_patches
) |
1963 S_028B58_HS_NUM_INPUT_CP(num_tcs_input_cp
) |
1964 S_028B58_HS_NUM_OUTPUT_CP(num_tcs_output_cp
);
1965 tess
.num_patches
= num_patches
;
1967 struct radv_shader_variant
*tes
= radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
);
1968 unsigned type
= 0, partitioning
= 0, topology
= 0, distribution_mode
= 0;
1970 switch (tes
->info
.tes
.primitive_mode
) {
1972 type
= V_028B6C_TESS_TRIANGLE
;
1975 type
= V_028B6C_TESS_QUAD
;
1978 type
= V_028B6C_TESS_ISOLINE
;
1982 switch (tes
->info
.tes
.spacing
) {
1983 case TESS_SPACING_EQUAL
:
1984 partitioning
= V_028B6C_PART_INTEGER
;
1986 case TESS_SPACING_FRACTIONAL_ODD
:
1987 partitioning
= V_028B6C_PART_FRAC_ODD
;
1989 case TESS_SPACING_FRACTIONAL_EVEN
:
1990 partitioning
= V_028B6C_PART_FRAC_EVEN
;
1996 bool ccw
= tes
->info
.tes
.ccw
;
1997 const VkPipelineTessellationDomainOriginStateCreateInfo
*domain_origin_state
=
1998 vk_find_struct_const(pCreateInfo
->pTessellationState
,
1999 PIPELINE_TESSELLATION_DOMAIN_ORIGIN_STATE_CREATE_INFO
);
2001 if (domain_origin_state
&& domain_origin_state
->domainOrigin
!= VK_TESSELLATION_DOMAIN_ORIGIN_UPPER_LEFT
)
2004 if (tes
->info
.tes
.point_mode
)
2005 topology
= V_028B6C_OUTPUT_POINT
;
2006 else if (tes
->info
.tes
.primitive_mode
== GL_ISOLINES
)
2007 topology
= V_028B6C_OUTPUT_LINE
;
2009 topology
= V_028B6C_OUTPUT_TRIANGLE_CCW
;
2011 topology
= V_028B6C_OUTPUT_TRIANGLE_CW
;
2013 if (pipeline
->device
->physical_device
->rad_info
.has_distributed_tess
) {
2014 if (pipeline
->device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
2015 pipeline
->device
->physical_device
->rad_info
.family
>= CHIP_POLARIS10
)
2016 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_TRAPEZOIDS
;
2018 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_DONUTS
;
2020 distribution_mode
= V_028B6C_DISTRIBUTION_MODE_NO_DIST
;
2022 tess
.tf_param
= S_028B6C_TYPE(type
) |
2023 S_028B6C_PARTITIONING(partitioning
) |
2024 S_028B6C_TOPOLOGY(topology
) |
2025 S_028B6C_DISTRIBUTION_MODE(distribution_mode
);
2030 static const struct radv_vs_output_info
*get_vs_output_info(const struct radv_pipeline
*pipeline
)
2032 if (radv_pipeline_has_gs(pipeline
))
2033 if (radv_pipeline_has_ngg(pipeline
))
2034 return &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.vs
.outinfo
;
2036 return &pipeline
->gs_copy_shader
->info
.vs
.outinfo
;
2037 else if (radv_pipeline_has_tess(pipeline
))
2038 return &pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.outinfo
;
2040 return &pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.outinfo
;
2044 radv_link_shaders(struct radv_pipeline
*pipeline
, nir_shader
**shaders
)
2046 nir_shader
* ordered_shaders
[MESA_SHADER_STAGES
];
2047 int shader_count
= 0;
2049 if(shaders
[MESA_SHADER_FRAGMENT
]) {
2050 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_FRAGMENT
];
2052 if(shaders
[MESA_SHADER_GEOMETRY
]) {
2053 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_GEOMETRY
];
2055 if(shaders
[MESA_SHADER_TESS_EVAL
]) {
2056 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_EVAL
];
2058 if(shaders
[MESA_SHADER_TESS_CTRL
]) {
2059 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_TESS_CTRL
];
2061 if(shaders
[MESA_SHADER_VERTEX
]) {
2062 ordered_shaders
[shader_count
++] = shaders
[MESA_SHADER_VERTEX
];
2065 if (shader_count
> 1) {
2066 unsigned first
= ordered_shaders
[shader_count
- 1]->info
.stage
;
2067 unsigned last
= ordered_shaders
[0]->info
.stage
;
2069 if (ordered_shaders
[0]->info
.stage
== MESA_SHADER_FRAGMENT
&&
2070 ordered_shaders
[1]->info
.has_transform_feedback_varyings
)
2071 nir_link_xfb_varyings(ordered_shaders
[1], ordered_shaders
[0]);
2073 for (int i
= 0; i
< shader_count
; ++i
) {
2074 nir_variable_mode mask
= 0;
2076 if (ordered_shaders
[i
]->info
.stage
!= first
)
2077 mask
= mask
| nir_var_shader_in
;
2079 if (ordered_shaders
[i
]->info
.stage
!= last
)
2080 mask
= mask
| nir_var_shader_out
;
2082 nir_lower_io_to_scalar_early(ordered_shaders
[i
], mask
);
2083 radv_optimize_nir(ordered_shaders
[i
], false, false);
2087 for (int i
= 1; i
< shader_count
; ++i
) {
2088 nir_lower_io_arrays_to_elements(ordered_shaders
[i
],
2089 ordered_shaders
[i
- 1]);
2091 if (nir_link_opt_varyings(ordered_shaders
[i
],
2092 ordered_shaders
[i
- 1]))
2093 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2095 nir_remove_dead_variables(ordered_shaders
[i
],
2096 nir_var_shader_out
, NULL
);
2097 nir_remove_dead_variables(ordered_shaders
[i
- 1],
2098 nir_var_shader_in
, NULL
);
2100 bool progress
= nir_remove_unused_varyings(ordered_shaders
[i
],
2101 ordered_shaders
[i
- 1]);
2103 nir_compact_varyings(ordered_shaders
[i
],
2104 ordered_shaders
[i
- 1], true);
2107 if (nir_lower_global_vars_to_local(ordered_shaders
[i
])) {
2108 ac_lower_indirect_derefs(ordered_shaders
[i
],
2109 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2111 radv_optimize_nir(ordered_shaders
[i
], false, false);
2113 if (nir_lower_global_vars_to_local(ordered_shaders
[i
- 1])) {
2114 ac_lower_indirect_derefs(ordered_shaders
[i
- 1],
2115 pipeline
->device
->physical_device
->rad_info
.chip_class
);
2117 radv_optimize_nir(ordered_shaders
[i
- 1], false, false);
2123 radv_set_linked_driver_locations(struct radv_pipeline
*pipeline
, nir_shader
**shaders
,
2124 struct radv_shader_info infos
[MESA_SHADER_STAGES
])
2126 bool has_tess
= shaders
[MESA_SHADER_TESS_CTRL
];
2127 bool has_gs
= shaders
[MESA_SHADER_GEOMETRY
];
2129 if (!has_tess
&& !has_gs
)
2132 unsigned vs_info_idx
= MESA_SHADER_VERTEX
;
2133 unsigned tes_info_idx
= MESA_SHADER_TESS_EVAL
;
2135 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
2136 /* These are merged into the next stage */
2137 vs_info_idx
= has_tess
? MESA_SHADER_TESS_CTRL
: MESA_SHADER_GEOMETRY
;
2138 tes_info_idx
= has_gs
? MESA_SHADER_GEOMETRY
: MESA_SHADER_TESS_EVAL
;
2142 nir_linked_io_var_info vs2tcs
=
2143 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_VERTEX
], shaders
[MESA_SHADER_TESS_CTRL
]);
2144 nir_linked_io_var_info tcs2tes
=
2145 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_TESS_CTRL
], shaders
[MESA_SHADER_TESS_EVAL
]);
2147 infos
[vs_info_idx
].vs
.num_linked_outputs
= vs2tcs
.num_linked_io_vars
;
2148 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_inputs
= vs2tcs
.num_linked_io_vars
;
2149 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_outputs
= tcs2tes
.num_linked_io_vars
;
2150 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_linked_patch_outputs
= tcs2tes
.num_linked_patch_io_vars
;
2151 infos
[tes_info_idx
].tes
.num_linked_inputs
= tcs2tes
.num_linked_io_vars
;
2152 infos
[tes_info_idx
].tes
.num_linked_patch_inputs
= tcs2tes
.num_linked_patch_io_vars
;
2155 nir_linked_io_var_info tes2gs
=
2156 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_TESS_EVAL
], shaders
[MESA_SHADER_GEOMETRY
]);
2158 infos
[tes_info_idx
].tes
.num_linked_outputs
= tes2gs
.num_linked_io_vars
;
2159 infos
[MESA_SHADER_GEOMETRY
].gs
.num_linked_inputs
= tes2gs
.num_linked_io_vars
;
2161 } else if (has_gs
) {
2162 nir_linked_io_var_info vs2gs
=
2163 nir_assign_linked_io_var_locations(shaders
[MESA_SHADER_VERTEX
], shaders
[MESA_SHADER_GEOMETRY
]);
2165 infos
[vs_info_idx
].vs
.num_linked_outputs
= vs2gs
.num_linked_io_vars
;
2166 infos
[MESA_SHADER_GEOMETRY
].gs
.num_linked_inputs
= vs2gs
.num_linked_io_vars
;
2171 radv_get_attrib_stride(const VkPipelineVertexInputStateCreateInfo
*input_state
,
2172 uint32_t attrib_binding
)
2174 for (uint32_t i
= 0; i
< input_state
->vertexBindingDescriptionCount
; i
++) {
2175 const VkVertexInputBindingDescription
*input_binding
=
2176 &input_state
->pVertexBindingDescriptions
[i
];
2178 if (input_binding
->binding
== attrib_binding
)
2179 return input_binding
->stride
;
2185 static struct radv_pipeline_key
2186 radv_generate_graphics_pipeline_key(struct radv_pipeline
*pipeline
,
2187 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
2188 const struct radv_blend_state
*blend
,
2189 bool has_view_index
)
2191 const VkPipelineVertexInputStateCreateInfo
*input_state
=
2192 pCreateInfo
->pVertexInputState
;
2193 const VkPipelineVertexInputDivisorStateCreateInfoEXT
*divisor_state
=
2194 vk_find_struct_const(input_state
->pNext
, PIPELINE_VERTEX_INPUT_DIVISOR_STATE_CREATE_INFO_EXT
);
2196 struct radv_pipeline_key key
;
2197 memset(&key
, 0, sizeof(key
));
2199 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
2200 key
.optimisations_disabled
= 1;
2202 key
.has_multiview_view_index
= has_view_index
;
2204 uint32_t binding_input_rate
= 0;
2205 uint32_t instance_rate_divisors
[MAX_VERTEX_ATTRIBS
];
2206 for (unsigned i
= 0; i
< input_state
->vertexBindingDescriptionCount
; ++i
) {
2207 if (input_state
->pVertexBindingDescriptions
[i
].inputRate
) {
2208 unsigned binding
= input_state
->pVertexBindingDescriptions
[i
].binding
;
2209 binding_input_rate
|= 1u << binding
;
2210 instance_rate_divisors
[binding
] = 1;
2213 if (divisor_state
) {
2214 for (unsigned i
= 0; i
< divisor_state
->vertexBindingDivisorCount
; ++i
) {
2215 instance_rate_divisors
[divisor_state
->pVertexBindingDivisors
[i
].binding
] =
2216 divisor_state
->pVertexBindingDivisors
[i
].divisor
;
2220 for (unsigned i
= 0; i
< input_state
->vertexAttributeDescriptionCount
; ++i
) {
2221 const VkVertexInputAttributeDescription
*desc
=
2222 &input_state
->pVertexAttributeDescriptions
[i
];
2223 const struct vk_format_description
*format_desc
;
2224 unsigned location
= desc
->location
;
2225 unsigned binding
= desc
->binding
;
2226 unsigned num_format
, data_format
;
2229 if (binding_input_rate
& (1u << binding
)) {
2230 key
.instance_rate_inputs
|= 1u << location
;
2231 key
.instance_rate_divisors
[location
] = instance_rate_divisors
[binding
];
2234 format_desc
= vk_format_description(desc
->format
);
2235 first_non_void
= vk_format_get_first_non_void_channel(desc
->format
);
2237 num_format
= radv_translate_buffer_numformat(format_desc
, first_non_void
);
2238 data_format
= radv_translate_buffer_dataformat(format_desc
, first_non_void
);
2240 key
.vertex_attribute_formats
[location
] = data_format
| (num_format
<< 4);
2241 key
.vertex_attribute_bindings
[location
] = desc
->binding
;
2242 key
.vertex_attribute_offsets
[location
] = desc
->offset
;
2243 key
.vertex_attribute_strides
[location
] = radv_get_attrib_stride(input_state
, desc
->binding
);
2245 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
&&
2246 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_STONEY
) {
2247 VkFormat format
= input_state
->pVertexAttributeDescriptions
[i
].format
;
2250 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2251 case VK_FORMAT_A2B10G10R10_SNORM_PACK32
:
2252 adjust
= RADV_ALPHA_ADJUST_SNORM
;
2254 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2255 case VK_FORMAT_A2B10G10R10_SSCALED_PACK32
:
2256 adjust
= RADV_ALPHA_ADJUST_SSCALED
;
2258 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2259 case VK_FORMAT_A2B10G10R10_SINT_PACK32
:
2260 adjust
= RADV_ALPHA_ADJUST_SINT
;
2266 key
.vertex_alpha_adjust
|= adjust
<< (2 * location
);
2269 switch (desc
->format
) {
2270 case VK_FORMAT_B8G8R8A8_UNORM
:
2271 case VK_FORMAT_B8G8R8A8_SNORM
:
2272 case VK_FORMAT_B8G8R8A8_USCALED
:
2273 case VK_FORMAT_B8G8R8A8_SSCALED
:
2274 case VK_FORMAT_B8G8R8A8_UINT
:
2275 case VK_FORMAT_B8G8R8A8_SINT
:
2276 case VK_FORMAT_B8G8R8A8_SRGB
:
2277 case VK_FORMAT_A2R10G10B10_UNORM_PACK32
:
2278 case VK_FORMAT_A2R10G10B10_SNORM_PACK32
:
2279 case VK_FORMAT_A2R10G10B10_USCALED_PACK32
:
2280 case VK_FORMAT_A2R10G10B10_SSCALED_PACK32
:
2281 case VK_FORMAT_A2R10G10B10_UINT_PACK32
:
2282 case VK_FORMAT_A2R10G10B10_SINT_PACK32
:
2283 key
.vertex_post_shuffle
|= 1 << location
;
2290 const VkPipelineTessellationStateCreateInfo
*tess
=
2291 radv_pipeline_get_tessellation_state(pCreateInfo
);
2293 key
.tess_input_vertices
= tess
->patchControlPoints
;
2295 const VkPipelineMultisampleStateCreateInfo
*vkms
=
2296 radv_pipeline_get_multisample_state(pCreateInfo
);
2297 if (vkms
&& vkms
->rasterizationSamples
> 1) {
2298 uint32_t num_samples
= vkms
->rasterizationSamples
;
2299 uint32_t ps_iter_samples
= radv_pipeline_get_ps_iter_samples(pCreateInfo
);
2300 key
.num_samples
= num_samples
;
2301 key
.log2_ps_iter_samples
= util_logbase2(ps_iter_samples
);
2304 key
.col_format
= blend
->spi_shader_col_format
;
2305 key
.is_dual_src
= blend
->mrt0_is_dual_src
;
2306 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX8
) {
2307 key
.is_int8
= blend
->col_format_is_int8
;
2308 key
.is_int10
= blend
->col_format_is_int10
;
2311 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
2312 key
.topology
= pCreateInfo
->pInputAssemblyState
->topology
;
2318 radv_nir_stage_uses_xfb(const nir_shader
*nir
)
2320 nir_xfb_info
*xfb
= nir_gather_xfb_info(nir
, NULL
);
2321 bool uses_xfb
= !!xfb
;
2328 radv_fill_shader_keys(struct radv_device
*device
,
2329 struct radv_shader_variant_key
*keys
,
2330 const struct radv_pipeline_key
*key
,
2333 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_inputs
= key
->instance_rate_inputs
;
2334 keys
[MESA_SHADER_VERTEX
].vs
.alpha_adjust
= key
->vertex_alpha_adjust
;
2335 keys
[MESA_SHADER_VERTEX
].vs
.post_shuffle
= key
->vertex_post_shuffle
;
2336 for (unsigned i
= 0; i
< MAX_VERTEX_ATTRIBS
; ++i
) {
2337 keys
[MESA_SHADER_VERTEX
].vs
.instance_rate_divisors
[i
] = key
->instance_rate_divisors
[i
];
2338 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_formats
[i
] = key
->vertex_attribute_formats
[i
];
2339 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_bindings
[i
] = key
->vertex_attribute_bindings
[i
];
2340 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_offsets
[i
] = key
->vertex_attribute_offsets
[i
];
2341 keys
[MESA_SHADER_VERTEX
].vs
.vertex_attribute_strides
[i
] = key
->vertex_attribute_strides
[i
];
2343 keys
[MESA_SHADER_VERTEX
].vs
.outprim
= si_conv_prim_to_gs_out(key
->topology
);
2345 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2346 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ls
= true;
2347 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= 0;
2348 keys
[MESA_SHADER_TESS_CTRL
].tcs
.input_vertices
= key
->tess_input_vertices
;
2349 keys
[MESA_SHADER_TESS_CTRL
].tcs
.primitive_mode
= nir
[MESA_SHADER_TESS_EVAL
]->info
.tess
.primitive_mode
;
2351 keys
[MESA_SHADER_TESS_CTRL
].tcs
.tes_reads_tess_factors
= !!(nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
& (VARYING_BIT_TESS_LEVEL_INNER
| VARYING_BIT_TESS_LEVEL_OUTER
));
2354 if (nir
[MESA_SHADER_GEOMETRY
]) {
2355 if (nir
[MESA_SHADER_TESS_CTRL
])
2356 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_es
= true;
2358 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_es
= true;
2361 if (device
->physical_device
->use_ngg
) {
2362 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2363 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= true;
2365 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= true;
2368 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2369 nir
[MESA_SHADER_GEOMETRY
] &&
2370 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.invocations
*
2371 nir
[MESA_SHADER_GEOMETRY
]->info
.gs
.vertices_out
> 256) {
2372 /* Fallback to the legacy path if tessellation is
2373 * enabled with extreme geometry because
2374 * EN_MAX_VERT_OUT_PER_GS_INSTANCE doesn't work and it
2377 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2380 if (!device
->physical_device
->use_ngg_gs
) {
2381 if (nir
[MESA_SHADER_GEOMETRY
]) {
2382 if (nir
[MESA_SHADER_TESS_CTRL
])
2383 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2385 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2389 gl_shader_stage last_xfb_stage
= MESA_SHADER_VERTEX
;
2391 for (int i
= MESA_SHADER_VERTEX
; i
<= MESA_SHADER_GEOMETRY
; i
++) {
2396 bool uses_xfb
= nir
[last_xfb_stage
] &&
2397 radv_nir_stage_uses_xfb(nir
[last_xfb_stage
]);
2399 if (!device
->physical_device
->use_ngg_streamout
&& uses_xfb
) {
2400 if (nir
[MESA_SHADER_TESS_CTRL
])
2401 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
= false;
2403 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
= false;
2406 /* Determine if the pipeline is eligible for the NGG passthrough
2407 * mode. It can't be enabled for geometry shaders, for NGG
2408 * streamout or for vertex shaders that export the primitive ID
2409 * (this is checked later because we don't have the info here.)
2411 if (!nir
[MESA_SHADER_GEOMETRY
] && !uses_xfb
) {
2412 if (nir
[MESA_SHADER_TESS_CTRL
] &&
2413 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
) {
2414 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg_passthrough
= true;
2415 } else if (nir
[MESA_SHADER_VERTEX
] &&
2416 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) {
2417 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg_passthrough
= true;
2422 for(int i
= 0; i
< MESA_SHADER_STAGES
; ++i
)
2423 keys
[i
].has_multiview_view_index
= key
->has_multiview_view_index
;
2425 keys
[MESA_SHADER_FRAGMENT
].fs
.col_format
= key
->col_format
;
2426 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int8
= key
->is_int8
;
2427 keys
[MESA_SHADER_FRAGMENT
].fs
.is_int10
= key
->is_int10
;
2428 keys
[MESA_SHADER_FRAGMENT
].fs
.log2_ps_iter_samples
= key
->log2_ps_iter_samples
;
2429 keys
[MESA_SHADER_FRAGMENT
].fs
.num_samples
= key
->num_samples
;
2430 keys
[MESA_SHADER_FRAGMENT
].fs
.is_dual_src
= key
->is_dual_src
;
2432 if (nir
[MESA_SHADER_COMPUTE
]) {
2433 keys
[MESA_SHADER_COMPUTE
].cs
.subgroup_size
= key
->compute_subgroup_size
;
2438 radv_get_wave_size(struct radv_device
*device
,
2439 const VkPipelineShaderStageCreateInfo
*pStage
,
2440 gl_shader_stage stage
,
2441 const struct radv_shader_variant_key
*key
)
2443 if (stage
== MESA_SHADER_GEOMETRY
&& !key
->vs_common_out
.as_ngg
)
2445 else if (stage
== MESA_SHADER_COMPUTE
) {
2446 if (key
->cs
.subgroup_size
) {
2447 /* Return the required subgroup size if specified. */
2448 return key
->cs
.subgroup_size
;
2450 return device
->physical_device
->cs_wave_size
;
2452 else if (stage
== MESA_SHADER_FRAGMENT
)
2453 return device
->physical_device
->ps_wave_size
;
2455 return device
->physical_device
->ge_wave_size
;
2459 radv_get_ballot_bit_size(struct radv_device
*device
,
2460 const VkPipelineShaderStageCreateInfo
*pStage
,
2461 gl_shader_stage stage
,
2462 const struct radv_shader_variant_key
*key
)
2464 if (stage
== MESA_SHADER_COMPUTE
&& key
->cs
.subgroup_size
)
2465 return key
->cs
.subgroup_size
;
2470 radv_fill_shader_info(struct radv_pipeline
*pipeline
,
2471 const VkPipelineShaderStageCreateInfo
**pStages
,
2472 struct radv_shader_variant_key
*keys
,
2473 struct radv_shader_info
*infos
,
2476 unsigned active_stages
= 0;
2477 unsigned filled_stages
= 0;
2479 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2481 active_stages
|= (1 << i
);
2484 if (nir
[MESA_SHADER_FRAGMENT
]) {
2485 radv_nir_shader_info_init(&infos
[MESA_SHADER_FRAGMENT
]);
2486 radv_nir_shader_info_pass(nir
[MESA_SHADER_FRAGMENT
],
2488 &keys
[MESA_SHADER_FRAGMENT
],
2489 &infos
[MESA_SHADER_FRAGMENT
],
2490 pipeline
->device
->physical_device
->use_llvm
);
2492 /* TODO: These are no longer used as keys we should refactor this */
2493 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
=
2494 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2495 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_layer_id
=
2496 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2497 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_clip_dists
=
2498 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2499 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_viewport_index
=
2500 infos
[MESA_SHADER_FRAGMENT
].ps
.viewport_index_input
;
2501 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_prim_id
=
2502 infos
[MESA_SHADER_FRAGMENT
].ps
.prim_id_input
;
2503 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_layer_id
=
2504 infos
[MESA_SHADER_FRAGMENT
].ps
.layer_input
;
2505 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_clip_dists
=
2506 !!infos
[MESA_SHADER_FRAGMENT
].ps
.num_input_clips_culls
;
2507 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.export_viewport_index
=
2508 infos
[MESA_SHADER_FRAGMENT
].ps
.viewport_index_input
;
2510 /* NGG passthrough mode can't be enabled for vertex shaders
2511 * that export the primitive ID.
2513 * TODO: I should really refactor the keys logic.
2515 if (nir
[MESA_SHADER_VERTEX
] &&
2516 keys
[MESA_SHADER_VERTEX
].vs_common_out
.export_prim_id
) {
2517 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg_passthrough
= false;
2520 filled_stages
|= (1 << MESA_SHADER_FRAGMENT
);
2523 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2524 infos
[MESA_SHADER_TESS_CTRL
].tcs
.tes_inputs_read
=
2525 nir
[MESA_SHADER_TESS_EVAL
]->info
.inputs_read
;
2526 infos
[MESA_SHADER_TESS_CTRL
].tcs
.tes_patch_inputs_read
=
2527 nir
[MESA_SHADER_TESS_EVAL
]->info
.patch_inputs_read
;
2530 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2531 nir
[MESA_SHADER_TESS_CTRL
]) {
2532 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2533 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2534 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2536 radv_nir_shader_info_init(&infos
[MESA_SHADER_TESS_CTRL
]);
2538 for (int i
= 0; i
< 2; i
++) {
2539 radv_nir_shader_info_pass(combined_nir
[i
],
2540 pipeline
->layout
, &key
,
2541 &infos
[MESA_SHADER_TESS_CTRL
],
2542 pipeline
->device
->physical_device
->use_llvm
);
2545 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2546 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2547 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2548 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2550 filled_stages
|= (1 << MESA_SHADER_VERTEX
);
2551 filled_stages
|= (1 << MESA_SHADER_TESS_CTRL
);
2554 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
&&
2555 nir
[MESA_SHADER_GEOMETRY
]) {
2556 gl_shader_stage pre_stage
= nir
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2557 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2559 radv_nir_shader_info_init(&infos
[MESA_SHADER_GEOMETRY
]);
2561 for (int i
= 0; i
< 2; i
++) {
2562 radv_nir_shader_info_pass(combined_nir
[i
],
2565 &infos
[MESA_SHADER_GEOMETRY
],
2566 pipeline
->device
->physical_device
->use_llvm
);
2569 filled_stages
|= (1 << pre_stage
);
2570 filled_stages
|= (1 << MESA_SHADER_GEOMETRY
);
2573 active_stages
^= filled_stages
;
2574 while (active_stages
) {
2575 int i
= u_bit_scan(&active_stages
);
2577 if (i
== MESA_SHADER_TESS_CTRL
) {
2578 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
=
2579 util_last_bit64(infos
[MESA_SHADER_VERTEX
].vs
.ls_outputs_written
);
2582 if (i
== MESA_SHADER_TESS_EVAL
) {
2583 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
=
2584 infos
[MESA_SHADER_TESS_CTRL
].tcs
.num_patches
;
2585 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
=
2586 util_last_bit64(infos
[MESA_SHADER_TESS_CTRL
].tcs
.outputs_written
);
2589 radv_nir_shader_info_init(&infos
[i
]);
2590 radv_nir_shader_info_pass(nir
[i
], pipeline
->layout
,
2591 &keys
[i
], &infos
[i
], pipeline
->device
->physical_device
->use_llvm
);
2594 for (int i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
2596 infos
[i
].wave_size
=
2597 radv_get_wave_size(pipeline
->device
, pStages
[i
],
2599 infos
[i
].ballot_bit_size
=
2600 radv_get_ballot_bit_size(pipeline
->device
,
2608 merge_tess_info(struct shader_info
*tes_info
,
2609 const struct shader_info
*tcs_info
)
2611 /* The Vulkan 1.0.38 spec, section 21.1 Tessellator says:
2613 * "PointMode. Controls generation of points rather than triangles
2614 * or lines. This functionality defaults to disabled, and is
2615 * enabled if either shader stage includes the execution mode.
2617 * and about Triangles, Quads, IsoLines, VertexOrderCw, VertexOrderCcw,
2618 * PointMode, SpacingEqual, SpacingFractionalEven, SpacingFractionalOdd,
2619 * and OutputVertices, it says:
2621 * "One mode must be set in at least one of the tessellation
2624 * So, the fields can be set in either the TCS or TES, but they must
2625 * agree if set in both. Our backend looks at TES, so bitwise-or in
2626 * the values from the TCS.
2628 assert(tcs_info
->tess
.tcs_vertices_out
== 0 ||
2629 tes_info
->tess
.tcs_vertices_out
== 0 ||
2630 tcs_info
->tess
.tcs_vertices_out
== tes_info
->tess
.tcs_vertices_out
);
2631 tes_info
->tess
.tcs_vertices_out
|= tcs_info
->tess
.tcs_vertices_out
;
2633 assert(tcs_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2634 tes_info
->tess
.spacing
== TESS_SPACING_UNSPECIFIED
||
2635 tcs_info
->tess
.spacing
== tes_info
->tess
.spacing
);
2636 tes_info
->tess
.spacing
|= tcs_info
->tess
.spacing
;
2638 assert(tcs_info
->tess
.primitive_mode
== 0 ||
2639 tes_info
->tess
.primitive_mode
== 0 ||
2640 tcs_info
->tess
.primitive_mode
== tes_info
->tess
.primitive_mode
);
2641 tes_info
->tess
.primitive_mode
|= tcs_info
->tess
.primitive_mode
;
2642 tes_info
->tess
.ccw
|= tcs_info
->tess
.ccw
;
2643 tes_info
->tess
.point_mode
|= tcs_info
->tess
.point_mode
;
2647 void radv_init_feedback(const VkPipelineCreationFeedbackCreateInfoEXT
*ext
)
2652 if (ext
->pPipelineCreationFeedback
) {
2653 ext
->pPipelineCreationFeedback
->flags
= 0;
2654 ext
->pPipelineCreationFeedback
->duration
= 0;
2657 for (unsigned i
= 0; i
< ext
->pipelineStageCreationFeedbackCount
; ++i
) {
2658 ext
->pPipelineStageCreationFeedbacks
[i
].flags
= 0;
2659 ext
->pPipelineStageCreationFeedbacks
[i
].duration
= 0;
2664 void radv_start_feedback(VkPipelineCreationFeedbackEXT
*feedback
)
2669 feedback
->duration
-= radv_get_current_time();
2670 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
;
2674 void radv_stop_feedback(VkPipelineCreationFeedbackEXT
*feedback
, bool cache_hit
)
2679 feedback
->duration
+= radv_get_current_time();
2680 feedback
->flags
= VK_PIPELINE_CREATION_FEEDBACK_VALID_BIT_EXT
|
2681 (cache_hit
? VK_PIPELINE_CREATION_FEEDBACK_APPLICATION_PIPELINE_CACHE_HIT_BIT_EXT
: 0);
2684 VkResult
radv_create_shaders(struct radv_pipeline
*pipeline
,
2685 struct radv_device
*device
,
2686 struct radv_pipeline_cache
*cache
,
2687 const struct radv_pipeline_key
*key
,
2688 const VkPipelineShaderStageCreateInfo
**pStages
,
2689 const VkPipelineCreateFlags flags
,
2690 VkPipelineCreationFeedbackEXT
*pipeline_feedback
,
2691 VkPipelineCreationFeedbackEXT
**stage_feedbacks
)
2693 struct radv_shader_module fs_m
= {0};
2694 struct radv_shader_module
*modules
[MESA_SHADER_STAGES
] = { 0, };
2695 nir_shader
*nir
[MESA_SHADER_STAGES
] = {0};
2696 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2697 struct radv_shader_variant_key keys
[MESA_SHADER_STAGES
] = {{{{{0}}}}};
2698 struct radv_shader_info infos
[MESA_SHADER_STAGES
] = {0};
2699 unsigned char hash
[20], gs_copy_hash
[20];
2700 bool keep_executable_info
= (flags
& VK_PIPELINE_CREATE_CAPTURE_INTERNAL_REPRESENTATIONS_BIT_KHR
) || device
->keep_shader_info
;
2701 bool keep_statistic_info
= (flags
& VK_PIPELINE_CREATE_CAPTURE_STATISTICS_BIT_KHR
) ||
2702 (device
->instance
->debug_flags
& RADV_DEBUG_DUMP_SHADER_STATS
) ||
2703 device
->keep_shader_info
;
2705 radv_start_feedback(pipeline_feedback
);
2707 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2709 modules
[i
] = radv_shader_module_from_handle(pStages
[i
]->module
);
2710 if (modules
[i
]->nir
)
2711 _mesa_sha1_compute(modules
[i
]->nir
->info
.name
,
2712 strlen(modules
[i
]->nir
->info
.name
),
2715 pipeline
->active_stages
|= mesa_to_vk_shader_stage(i
);
2719 radv_hash_shaders(hash
, pStages
, pipeline
->layout
, key
, get_hash_flags(device
));
2720 memcpy(gs_copy_hash
, hash
, 20);
2721 gs_copy_hash
[0] ^= 1;
2723 bool found_in_application_cache
= true;
2724 if (modules
[MESA_SHADER_GEOMETRY
] && !keep_executable_info
&& !keep_statistic_info
) {
2725 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2726 radv_create_shader_variants_from_pipeline_cache(device
, cache
, gs_copy_hash
, variants
,
2727 &found_in_application_cache
);
2728 pipeline
->gs_copy_shader
= variants
[MESA_SHADER_GEOMETRY
];
2731 if (!keep_executable_info
&& !keep_statistic_info
&&
2732 radv_create_shader_variants_from_pipeline_cache(device
, cache
, hash
, pipeline
->shaders
,
2733 &found_in_application_cache
) &&
2734 (!modules
[MESA_SHADER_GEOMETRY
] || pipeline
->gs_copy_shader
)) {
2735 radv_stop_feedback(pipeline_feedback
, found_in_application_cache
);
2739 if (flags
& VK_PIPELINE_CREATE_FAIL_ON_PIPELINE_COMPILE_REQUIRED_BIT_EXT
) {
2740 radv_stop_feedback(pipeline_feedback
, found_in_application_cache
);
2741 return VK_PIPELINE_COMPILE_REQUIRED_EXT
;
2744 if (!modules
[MESA_SHADER_FRAGMENT
] && !modules
[MESA_SHADER_COMPUTE
]) {
2746 nir_builder_init_simple_shader(&fs_b
, NULL
, MESA_SHADER_FRAGMENT
, NULL
);
2747 fs_b
.shader
->info
.name
= ralloc_strdup(fs_b
.shader
, "noop_fs");
2748 fs_m
.nir
= fs_b
.shader
;
2749 modules
[MESA_SHADER_FRAGMENT
] = &fs_m
;
2752 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2753 const VkPipelineShaderStageCreateInfo
*stage
= pStages
[i
];
2754 unsigned subgroup_size
= 64, ballot_bit_size
= 64;
2759 radv_start_feedback(stage_feedbacks
[i
]);
2761 if (key
->compute_subgroup_size
) {
2762 /* Only compute shaders currently support requiring a
2763 * specific subgroup size.
2765 assert(i
== MESA_SHADER_COMPUTE
);
2766 subgroup_size
= key
->compute_subgroup_size
;
2767 ballot_bit_size
= key
->compute_subgroup_size
;
2770 nir
[i
] = radv_shader_compile_to_nir(device
, modules
[i
],
2771 stage
? stage
->pName
: "main", i
,
2772 stage
? stage
->pSpecializationInfo
: NULL
,
2773 flags
, pipeline
->layout
,
2774 subgroup_size
, ballot_bit_size
);
2776 /* We don't want to alter meta shaders IR directly so clone it
2779 if (nir
[i
]->info
.name
) {
2780 nir
[i
] = nir_shader_clone(NULL
, nir
[i
]);
2783 radv_stop_feedback(stage_feedbacks
[i
], false);
2786 if (nir
[MESA_SHADER_TESS_CTRL
]) {
2787 nir_lower_patch_vertices(nir
[MESA_SHADER_TESS_EVAL
], nir
[MESA_SHADER_TESS_CTRL
]->info
.tess
.tcs_vertices_out
, NULL
);
2788 merge_tess_info(&nir
[MESA_SHADER_TESS_EVAL
]->info
, &nir
[MESA_SHADER_TESS_CTRL
]->info
);
2791 if (!(flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
))
2792 radv_link_shaders(pipeline
, nir
);
2794 radv_set_linked_driver_locations(pipeline
, nir
, infos
);
2796 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2798 /* do this again since information such as outputs_read can be out-of-date */
2799 nir_shader_gather_info(nir
[i
], nir_shader_get_entrypoint(nir
[i
]));
2801 if (device
->physical_device
->use_llvm
) {
2802 NIR_PASS_V(nir
[i
], nir_lower_bool_to_int32
);
2804 NIR_PASS_V(nir
[i
], nir_lower_non_uniform_access
,
2805 nir_lower_non_uniform_ubo_access
|
2806 nir_lower_non_uniform_ssbo_access
|
2807 nir_lower_non_uniform_texture_access
|
2808 nir_lower_non_uniform_image_access
);
2813 if (nir
[MESA_SHADER_FRAGMENT
])
2814 radv_lower_fs_io(nir
[MESA_SHADER_FRAGMENT
]);
2816 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2817 if (radv_can_dump_shader(device
, modules
[i
], false))
2818 nir_print_shader(nir
[i
], stderr
);
2821 radv_fill_shader_keys(device
, keys
, key
, nir
);
2823 radv_fill_shader_info(pipeline
, pStages
, keys
, infos
, nir
);
2825 if ((nir
[MESA_SHADER_VERTEX
] &&
2826 keys
[MESA_SHADER_VERTEX
].vs_common_out
.as_ngg
) ||
2827 (nir
[MESA_SHADER_TESS_EVAL
] &&
2828 keys
[MESA_SHADER_TESS_EVAL
].vs_common_out
.as_ngg
)) {
2829 struct gfx10_ngg_info
*ngg_info
;
2831 if (nir
[MESA_SHADER_GEOMETRY
])
2832 ngg_info
= &infos
[MESA_SHADER_GEOMETRY
].ngg_info
;
2833 else if (nir
[MESA_SHADER_TESS_CTRL
])
2834 ngg_info
= &infos
[MESA_SHADER_TESS_EVAL
].ngg_info
;
2836 ngg_info
= &infos
[MESA_SHADER_VERTEX
].ngg_info
;
2838 gfx10_get_ngg_info(key
, pipeline
, nir
, infos
, ngg_info
);
2839 } else if (nir
[MESA_SHADER_GEOMETRY
]) {
2840 struct gfx9_gs_info
*gs_info
=
2841 &infos
[MESA_SHADER_GEOMETRY
].gs_ring_info
;
2843 gfx9_get_gs_info(key
, pipeline
, nir
, infos
, gs_info
);
2846 if(modules
[MESA_SHADER_GEOMETRY
]) {
2847 struct radv_shader_binary
*gs_copy_binary
= NULL
;
2848 if (!pipeline
->gs_copy_shader
&&
2849 !radv_pipeline_has_ngg(pipeline
)) {
2850 struct radv_shader_info info
= {};
2851 struct radv_shader_variant_key key
= {};
2853 key
.has_multiview_view_index
=
2854 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
;
2856 radv_nir_shader_info_pass(nir
[MESA_SHADER_GEOMETRY
],
2857 pipeline
->layout
, &key
,
2858 &info
, pipeline
->device
->physical_device
->use_llvm
);
2859 info
.wave_size
= 64; /* Wave32 not supported. */
2860 info
.ballot_bit_size
= 64;
2862 pipeline
->gs_copy_shader
= radv_create_gs_copy_shader(
2863 device
, nir
[MESA_SHADER_GEOMETRY
], &info
,
2864 &gs_copy_binary
, keep_executable_info
, keep_statistic_info
,
2865 keys
[MESA_SHADER_GEOMETRY
].has_multiview_view_index
);
2868 if (!keep_executable_info
&& !keep_statistic_info
&& pipeline
->gs_copy_shader
) {
2869 struct radv_shader_binary
*binaries
[MESA_SHADER_STAGES
] = {NULL
};
2870 struct radv_shader_variant
*variants
[MESA_SHADER_STAGES
] = {0};
2872 binaries
[MESA_SHADER_GEOMETRY
] = gs_copy_binary
;
2873 variants
[MESA_SHADER_GEOMETRY
] = pipeline
->gs_copy_shader
;
2875 radv_pipeline_cache_insert_shaders(device
, cache
,
2880 free(gs_copy_binary
);
2883 if (nir
[MESA_SHADER_FRAGMENT
]) {
2884 if (!pipeline
->shaders
[MESA_SHADER_FRAGMENT
]) {
2885 radv_start_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
]);
2887 pipeline
->shaders
[MESA_SHADER_FRAGMENT
] =
2888 radv_shader_variant_compile(device
, modules
[MESA_SHADER_FRAGMENT
], &nir
[MESA_SHADER_FRAGMENT
], 1,
2889 pipeline
->layout
, keys
+ MESA_SHADER_FRAGMENT
,
2890 infos
+ MESA_SHADER_FRAGMENT
,
2891 keep_executable_info
, keep_statistic_info
,
2892 &binaries
[MESA_SHADER_FRAGMENT
]);
2894 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_FRAGMENT
], false);
2898 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_TESS_CTRL
]) {
2899 if (!pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]) {
2900 struct nir_shader
*combined_nir
[] = {nir
[MESA_SHADER_VERTEX
], nir
[MESA_SHADER_TESS_CTRL
]};
2901 struct radv_shader_variant_key key
= keys
[MESA_SHADER_TESS_CTRL
];
2902 key
.tcs
.vs_key
= keys
[MESA_SHADER_VERTEX
].vs
;
2904 radv_start_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
]);
2906 pipeline
->shaders
[MESA_SHADER_TESS_CTRL
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_TESS_CTRL
], combined_nir
, 2,
2908 &key
, &infos
[MESA_SHADER_TESS_CTRL
], keep_executable_info
,
2909 keep_statistic_info
, &binaries
[MESA_SHADER_TESS_CTRL
]);
2911 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_TESS_CTRL
], false);
2913 modules
[MESA_SHADER_VERTEX
] = NULL
;
2914 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2915 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2918 if (device
->physical_device
->rad_info
.chip_class
>= GFX9
&& modules
[MESA_SHADER_GEOMETRY
]) {
2919 gl_shader_stage pre_stage
= modules
[MESA_SHADER_TESS_EVAL
] ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
2920 if (!pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
2921 struct nir_shader
*combined_nir
[] = {nir
[pre_stage
], nir
[MESA_SHADER_GEOMETRY
]};
2923 radv_start_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
]);
2925 pipeline
->shaders
[MESA_SHADER_GEOMETRY
] = radv_shader_variant_compile(device
, modules
[MESA_SHADER_GEOMETRY
], combined_nir
, 2,
2927 &keys
[pre_stage
], &infos
[MESA_SHADER_GEOMETRY
], keep_executable_info
,
2928 keep_statistic_info
, &binaries
[MESA_SHADER_GEOMETRY
]);
2930 radv_stop_feedback(stage_feedbacks
[MESA_SHADER_GEOMETRY
], false);
2932 modules
[pre_stage
] = NULL
;
2935 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2936 if(modules
[i
] && !pipeline
->shaders
[i
]) {
2937 if (i
== MESA_SHADER_TESS_CTRL
) {
2938 keys
[MESA_SHADER_TESS_CTRL
].tcs
.num_inputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.vs
.ls_outputs_written
);
2940 if (i
== MESA_SHADER_TESS_EVAL
) {
2941 keys
[MESA_SHADER_TESS_EVAL
].tes
.num_patches
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.num_patches
;
2942 keys
[MESA_SHADER_TESS_EVAL
].tes
.tcs_num_outputs
= util_last_bit64(pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.tcs
.outputs_written
);
2945 radv_start_feedback(stage_feedbacks
[i
]);
2947 pipeline
->shaders
[i
] = radv_shader_variant_compile(device
, modules
[i
], &nir
[i
], 1,
2949 keys
+ i
, infos
+ i
, keep_executable_info
,
2950 keep_statistic_info
, &binaries
[i
]);
2952 radv_stop_feedback(stage_feedbacks
[i
], false);
2956 if (!keep_executable_info
&& !keep_statistic_info
) {
2957 radv_pipeline_cache_insert_shaders(device
, cache
, hash
, pipeline
->shaders
,
2961 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
2964 ralloc_free(nir
[i
]);
2966 if (radv_can_dump_shader_stats(device
, modules
[i
]))
2967 radv_shader_dump_stats(device
,
2968 pipeline
->shaders
[i
],
2974 ralloc_free(fs_m
.nir
);
2976 radv_stop_feedback(pipeline_feedback
, false);
2981 radv_pipeline_stage_to_user_data_0(struct radv_pipeline
*pipeline
,
2982 gl_shader_stage stage
, enum chip_class chip_class
)
2984 bool has_gs
= radv_pipeline_has_gs(pipeline
);
2985 bool has_tess
= radv_pipeline_has_tess(pipeline
);
2986 bool has_ngg
= radv_pipeline_has_ngg(pipeline
);
2989 case MESA_SHADER_FRAGMENT
:
2990 return R_00B030_SPI_SHADER_USER_DATA_PS_0
;
2991 case MESA_SHADER_VERTEX
:
2993 if (chip_class
>= GFX10
) {
2994 return R_00B430_SPI_SHADER_USER_DATA_HS_0
;
2995 } else if (chip_class
== GFX9
) {
2996 return R_00B430_SPI_SHADER_USER_DATA_LS_0
;
2998 return R_00B530_SPI_SHADER_USER_DATA_LS_0
;
3004 if (chip_class
>= GFX10
) {
3005 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3007 return R_00B330_SPI_SHADER_USER_DATA_ES_0
;
3012 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3014 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3015 case MESA_SHADER_GEOMETRY
:
3016 return chip_class
== GFX9
? R_00B330_SPI_SHADER_USER_DATA_ES_0
:
3017 R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3018 case MESA_SHADER_COMPUTE
:
3019 return R_00B900_COMPUTE_USER_DATA_0
;
3020 case MESA_SHADER_TESS_CTRL
:
3021 return chip_class
== GFX9
? R_00B430_SPI_SHADER_USER_DATA_LS_0
:
3022 R_00B430_SPI_SHADER_USER_DATA_HS_0
;
3023 case MESA_SHADER_TESS_EVAL
:
3025 return chip_class
>= GFX10
? R_00B230_SPI_SHADER_USER_DATA_GS_0
:
3026 R_00B330_SPI_SHADER_USER_DATA_ES_0
;
3027 } else if (has_ngg
) {
3028 return R_00B230_SPI_SHADER_USER_DATA_GS_0
;
3030 return R_00B130_SPI_SHADER_USER_DATA_VS_0
;
3033 unreachable("unknown shader");
3037 struct radv_bin_size_entry
{
3043 radv_gfx9_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3045 static const struct radv_bin_size_entry color_size_table
[][3][9] = {
3049 /* One shader engine */
3055 { UINT_MAX
, { 0, 0}},
3058 /* Two shader engines */
3064 { UINT_MAX
, { 0, 0}},
3067 /* Four shader engines */
3072 { UINT_MAX
, { 0, 0}},
3078 /* One shader engine */
3084 { UINT_MAX
, { 0, 0}},
3087 /* Two shader engines */
3093 { UINT_MAX
, { 0, 0}},
3096 /* Four shader engines */
3103 { UINT_MAX
, { 0, 0}},
3109 /* One shader engine */
3116 { UINT_MAX
, { 0, 0}},
3119 /* Two shader engines */
3127 { UINT_MAX
, { 0, 0}},
3130 /* Four shader engines */
3138 { UINT_MAX
, { 0, 0}},
3142 static const struct radv_bin_size_entry ds_size_table
[][3][9] = {
3146 // One shader engine
3153 { UINT_MAX
, { 0, 0}},
3156 // Two shader engines
3164 { UINT_MAX
, { 0, 0}},
3167 // Four shader engines
3175 { UINT_MAX
, { 0, 0}},
3181 // One shader engine
3189 { UINT_MAX
, { 0, 0}},
3192 // Two shader engines
3201 { UINT_MAX
, { 0, 0}},
3204 // Four shader engines
3213 { UINT_MAX
, { 0, 0}},
3219 // One shader engine
3227 { UINT_MAX
, { 0, 0}},
3230 // Two shader engines
3239 { UINT_MAX
, { 0, 0}},
3242 // Four shader engines
3250 { UINT_MAX
, { 0, 0}},
3255 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3256 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3257 VkExtent2D extent
= {512, 512};
3259 unsigned log_num_rb_per_se
=
3260 util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.num_render_backends
/
3261 pipeline
->device
->physical_device
->rad_info
.max_se
);
3262 unsigned log_num_se
= util_logbase2_ceil(pipeline
->device
->physical_device
->rad_info
.max_se
);
3264 unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3265 unsigned ps_iter_samples
= 1u << G_028804_PS_ITER_SAMPLES(pipeline
->graphics
.ms
.db_eqaa
);
3266 unsigned effective_samples
= total_samples
;
3267 unsigned color_bytes_per_pixel
= 0;
3269 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3270 radv_pipeline_get_color_blend_state(pCreateInfo
);
3272 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3273 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3276 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3279 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3280 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3283 /* MSAA images typically don't use all samples all the time. */
3284 if (effective_samples
>= 2 && ps_iter_samples
<= 1)
3285 effective_samples
= 2;
3286 color_bytes_per_pixel
*= effective_samples
;
3289 const struct radv_bin_size_entry
*color_entry
= color_size_table
[log_num_rb_per_se
][log_num_se
];
3290 while(color_entry
[1].bpp
<= color_bytes_per_pixel
)
3293 extent
= color_entry
->extent
;
3295 if (subpass
->depth_stencil_attachment
) {
3296 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3298 /* Coefficients taken from AMDVLK */
3299 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3300 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3301 unsigned ds_bytes_per_pixel
= 4 * (depth_coeff
+ stencil_coeff
) * total_samples
;
3303 const struct radv_bin_size_entry
*ds_entry
= ds_size_table
[log_num_rb_per_se
][log_num_se
];
3304 while(ds_entry
[1].bpp
<= ds_bytes_per_pixel
)
3307 if (ds_entry
->extent
.width
* ds_entry
->extent
.height
< extent
.width
* extent
.height
)
3308 extent
= ds_entry
->extent
;
3315 radv_gfx10_compute_bin_size(struct radv_pipeline
*pipeline
, const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3317 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3318 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3319 VkExtent2D extent
= {512, 512};
3321 const unsigned db_tag_size
= 64;
3322 const unsigned db_tag_count
= 312;
3323 const unsigned color_tag_size
= 1024;
3324 const unsigned color_tag_count
= 31;
3325 const unsigned fmask_tag_size
= 256;
3326 const unsigned fmask_tag_count
= 44;
3328 const unsigned rb_count
= pipeline
->device
->physical_device
->rad_info
.num_render_backends
;
3329 const unsigned pipe_count
= MAX2(rb_count
, pipeline
->device
->physical_device
->rad_info
.num_sdp_interfaces
);
3331 const unsigned db_tag_part
= (db_tag_count
* rb_count
/ pipe_count
) * db_tag_size
* pipe_count
;
3332 const unsigned color_tag_part
= (color_tag_count
* rb_count
/ pipe_count
) * color_tag_size
* pipe_count
;
3333 const unsigned fmask_tag_part
= (fmask_tag_count
* rb_count
/ pipe_count
) * fmask_tag_size
* pipe_count
;
3335 const unsigned total_samples
= 1u << G_028BE0_MSAA_NUM_SAMPLES(pipeline
->graphics
.ms
.pa_sc_aa_config
);
3336 const unsigned samples_log
= util_logbase2_ceil(total_samples
);
3338 unsigned color_bytes_per_pixel
= 0;
3339 unsigned fmask_bytes_per_pixel
= 0;
3341 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3342 radv_pipeline_get_color_blend_state(pCreateInfo
);
3344 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3345 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3348 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3351 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3352 color_bytes_per_pixel
+= vk_format_get_blocksize(format
);
3354 if (total_samples
> 1) {
3355 assert(samples_log
<= 3);
3356 const unsigned fmask_array
[] = {0, 1, 1, 4};
3357 fmask_bytes_per_pixel
+= fmask_array
[samples_log
];
3361 color_bytes_per_pixel
*= total_samples
;
3363 color_bytes_per_pixel
= MAX2(color_bytes_per_pixel
, 1);
3365 const unsigned color_pixel_count_log
= util_logbase2(color_tag_part
/ color_bytes_per_pixel
);
3366 extent
.width
= 1ull << ((color_pixel_count_log
+ 1) / 2);
3367 extent
.height
= 1ull << (color_pixel_count_log
/ 2);
3369 if (fmask_bytes_per_pixel
) {
3370 const unsigned fmask_pixel_count_log
= util_logbase2(fmask_tag_part
/ fmask_bytes_per_pixel
);
3372 const VkExtent2D fmask_extent
= (VkExtent2D
){
3373 .width
= 1ull << ((fmask_pixel_count_log
+ 1) / 2),
3374 .height
= 1ull << (color_pixel_count_log
/ 2)
3377 if (fmask_extent
.width
* fmask_extent
.height
< extent
.width
* extent
.height
)
3378 extent
= fmask_extent
;
3381 if (subpass
->depth_stencil_attachment
) {
3382 struct radv_render_pass_attachment
*attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3384 /* Coefficients taken from AMDVLK */
3385 unsigned depth_coeff
= vk_format_is_depth(attachment
->format
) ? 5 : 0;
3386 unsigned stencil_coeff
= vk_format_is_stencil(attachment
->format
) ? 1 : 0;
3387 unsigned db_bytes_per_pixel
= (depth_coeff
+ stencil_coeff
) * total_samples
;
3389 const unsigned db_pixel_count_log
= util_logbase2(db_tag_part
/ db_bytes_per_pixel
);
3391 const VkExtent2D db_extent
= (VkExtent2D
){
3392 .width
= 1ull << ((db_pixel_count_log
+ 1) / 2),
3393 .height
= 1ull << (color_pixel_count_log
/ 2)
3396 if (db_extent
.width
* db_extent
.height
< extent
.width
* extent
.height
)
3400 extent
.width
= MAX2(extent
.width
, 128);
3401 extent
.height
= MAX2(extent
.width
, 64);
3407 radv_pipeline_generate_disabled_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3408 struct radv_pipeline
*pipeline
,
3409 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3411 uint32_t pa_sc_binner_cntl_0
=
3412 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_LEGACY_SC
) |
3413 S_028C44_DISABLE_START_OF_PRIM(1);
3414 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3416 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3417 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3418 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3419 const VkPipelineColorBlendStateCreateInfo
*vkblend
=
3420 radv_pipeline_get_color_blend_state(pCreateInfo
);
3421 unsigned min_bytes_per_pixel
= 0;
3424 for (unsigned i
= 0; i
< subpass
->color_count
; i
++) {
3425 if (!vkblend
->pAttachments
[i
].colorWriteMask
)
3428 if (subpass
->color_attachments
[i
].attachment
== VK_ATTACHMENT_UNUSED
)
3431 VkFormat format
= pass
->attachments
[subpass
->color_attachments
[i
].attachment
].format
;
3432 unsigned bytes
= vk_format_get_blocksize(format
);
3433 if (!min_bytes_per_pixel
|| bytes
< min_bytes_per_pixel
)
3434 min_bytes_per_pixel
= bytes
;
3438 pa_sc_binner_cntl_0
=
3439 S_028C44_BINNING_MODE(V_028C44_DISABLE_BINNING_USE_NEW_SC
) |
3440 S_028C44_BIN_SIZE_X(0) |
3441 S_028C44_BIN_SIZE_Y(0) |
3442 S_028C44_BIN_SIZE_X_EXTEND(2) | /* 128 */
3443 S_028C44_BIN_SIZE_Y_EXTEND(min_bytes_per_pixel
<= 4 ? 2 : 1) | /* 128 or 64 */
3444 S_028C44_DISABLE_START_OF_PRIM(1);
3447 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3448 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3451 struct radv_binning_settings
3452 radv_get_binning_settings(const struct radv_physical_device
*pdev
)
3454 struct radv_binning_settings settings
;
3455 if (pdev
->rad_info
.has_dedicated_vram
) {
3456 if (pdev
->rad_info
.num_render_backends
> 4) {
3457 settings
.context_states_per_bin
= 1;
3458 settings
.persistent_states_per_bin
= 1;
3460 settings
.context_states_per_bin
= 3;
3461 settings
.persistent_states_per_bin
= 8;
3463 settings
.fpovs_per_batch
= 63;
3465 /* The context states are affected by the scissor bug. */
3466 settings
.context_states_per_bin
= 6;
3467 /* 32 causes hangs for RAVEN. */
3468 settings
.persistent_states_per_bin
= 16;
3469 settings
.fpovs_per_batch
= 63;
3472 if (pdev
->rad_info
.has_gfx9_scissor_bug
)
3473 settings
.context_states_per_bin
= 1;
3479 radv_pipeline_generate_binning_state(struct radeon_cmdbuf
*ctx_cs
,
3480 struct radv_pipeline
*pipeline
,
3481 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3482 const struct radv_blend_state
*blend
)
3484 if (pipeline
->device
->physical_device
->rad_info
.chip_class
< GFX9
)
3487 VkExtent2D bin_size
;
3488 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3489 bin_size
= radv_gfx10_compute_bin_size(pipeline
, pCreateInfo
);
3490 } else if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX9
) {
3491 bin_size
= radv_gfx9_compute_bin_size(pipeline
, pCreateInfo
);
3493 unreachable("Unhandled generation for binning bin size calculation");
3495 if (pipeline
->device
->pbb_allowed
&& bin_size
.width
&& bin_size
.height
) {
3496 struct radv_binning_settings settings
=
3497 radv_get_binning_settings(pipeline
->device
->physical_device
);
3499 bool disable_start_of_prim
= true;
3500 uint32_t db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_FORCE_OFF
);
3502 const struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3504 if (pipeline
->device
->dfsm_allowed
&& ps
&&
3505 !ps
->info
.ps
.can_discard
&&
3506 !ps
->info
.ps
.writes_memory
&&
3507 blend
->cb_target_enabled_4bit
) {
3508 db_dfsm_control
= S_028060_PUNCHOUT_MODE(V_028060_AUTO
);
3509 disable_start_of_prim
= (blend
->blend_enable_4bit
& blend
->cb_target_enabled_4bit
) != 0;
3512 const uint32_t pa_sc_binner_cntl_0
=
3513 S_028C44_BINNING_MODE(V_028C44_BINNING_ALLOWED
) |
3514 S_028C44_BIN_SIZE_X(bin_size
.width
== 16) |
3515 S_028C44_BIN_SIZE_Y(bin_size
.height
== 16) |
3516 S_028C44_BIN_SIZE_X_EXTEND(util_logbase2(MAX2(bin_size
.width
, 32)) - 5) |
3517 S_028C44_BIN_SIZE_Y_EXTEND(util_logbase2(MAX2(bin_size
.height
, 32)) - 5) |
3518 S_028C44_CONTEXT_STATES_PER_BIN(settings
.context_states_per_bin
- 1) |
3519 S_028C44_PERSISTENT_STATES_PER_BIN(settings
.persistent_states_per_bin
- 1) |
3520 S_028C44_DISABLE_START_OF_PRIM(disable_start_of_prim
) |
3521 S_028C44_FPOVS_PER_BATCH(settings
.fpovs_per_batch
) |
3522 S_028C44_OPTIMAL_BIN_SELECTION(1);
3524 pipeline
->graphics
.binning
.pa_sc_binner_cntl_0
= pa_sc_binner_cntl_0
;
3525 pipeline
->graphics
.binning
.db_dfsm_control
= db_dfsm_control
;
3527 radv_pipeline_generate_disabled_binning_state(ctx_cs
, pipeline
, pCreateInfo
);
3532 radv_pipeline_generate_depth_stencil_state(struct radeon_cmdbuf
*ctx_cs
,
3533 struct radv_pipeline
*pipeline
,
3534 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
3535 const struct radv_graphics_pipeline_create_info
*extra
)
3537 const VkPipelineDepthStencilStateCreateInfo
*vkds
= radv_pipeline_get_depth_stencil_state(pCreateInfo
);
3538 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
3539 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
3540 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
3541 struct radv_render_pass_attachment
*attachment
= NULL
;
3542 uint32_t db_depth_control
= 0, db_stencil_control
= 0;
3543 uint32_t db_render_control
= 0, db_render_override2
= 0;
3544 uint32_t db_render_override
= 0;
3546 if (subpass
->depth_stencil_attachment
)
3547 attachment
= pass
->attachments
+ subpass
->depth_stencil_attachment
->attachment
;
3549 bool has_depth_attachment
= attachment
&& vk_format_is_depth(attachment
->format
);
3550 bool has_stencil_attachment
= attachment
&& vk_format_is_stencil(attachment
->format
);
3552 if (vkds
&& has_depth_attachment
) {
3553 db_depth_control
= S_028800_Z_ENABLE(vkds
->depthTestEnable
? 1 : 0) |
3554 S_028800_Z_WRITE_ENABLE(vkds
->depthWriteEnable
? 1 : 0) |
3555 S_028800_ZFUNC(vkds
->depthCompareOp
) |
3556 S_028800_DEPTH_BOUNDS_ENABLE(vkds
->depthBoundsTestEnable
? 1 : 0);
3558 /* from amdvlk: For 4xAA and 8xAA need to decompress on flush for better performance */
3559 db_render_override2
|= S_028010_DECOMPRESS_Z_ON_FLUSH(attachment
->samples
> 2);
3561 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
)
3562 db_render_override2
|= S_028010_CENTROID_COMPUTATION_MODE_GFX103(2);
3565 if (has_stencil_attachment
&& vkds
&& vkds
->stencilTestEnable
) {
3566 db_depth_control
|= S_028800_STENCIL_ENABLE(1) | S_028800_BACKFACE_ENABLE(1);
3567 db_depth_control
|= S_028800_STENCILFUNC(vkds
->front
.compareOp
);
3568 db_stencil_control
|= S_02842C_STENCILFAIL(si_translate_stencil_op(vkds
->front
.failOp
));
3569 db_stencil_control
|= S_02842C_STENCILZPASS(si_translate_stencil_op(vkds
->front
.passOp
));
3570 db_stencil_control
|= S_02842C_STENCILZFAIL(si_translate_stencil_op(vkds
->front
.depthFailOp
));
3572 db_depth_control
|= S_028800_STENCILFUNC_BF(vkds
->back
.compareOp
);
3573 db_stencil_control
|= S_02842C_STENCILFAIL_BF(si_translate_stencil_op(vkds
->back
.failOp
));
3574 db_stencil_control
|= S_02842C_STENCILZPASS_BF(si_translate_stencil_op(vkds
->back
.passOp
));
3575 db_stencil_control
|= S_02842C_STENCILZFAIL_BF(si_translate_stencil_op(vkds
->back
.depthFailOp
));
3578 if (attachment
&& extra
) {
3579 db_render_control
|= S_028000_DEPTH_CLEAR_ENABLE(extra
->db_depth_clear
);
3580 db_render_control
|= S_028000_STENCIL_CLEAR_ENABLE(extra
->db_stencil_clear
);
3582 db_render_control
|= S_028000_RESUMMARIZE_ENABLE(extra
->resummarize_enable
);
3583 db_render_control
|= S_028000_DEPTH_COMPRESS_DISABLE(extra
->depth_compress_disable
);
3584 db_render_control
|= S_028000_STENCIL_COMPRESS_DISABLE(extra
->stencil_compress_disable
);
3585 db_render_override2
|= S_028010_DISABLE_ZMASK_EXPCLEAR_OPTIMIZATION(extra
->db_depth_disable_expclear
);
3586 db_render_override2
|= S_028010_DISABLE_SMEM_EXPCLEAR_OPTIMIZATION(extra
->db_stencil_disable_expclear
);
3589 db_render_override
|= S_02800C_FORCE_HIS_ENABLE0(V_02800C_FORCE_DISABLE
) |
3590 S_02800C_FORCE_HIS_ENABLE1(V_02800C_FORCE_DISABLE
);
3592 if (!pCreateInfo
->pRasterizationState
->depthClampEnable
&&
3593 ps
->info
.ps
.writes_z
) {
3594 /* From VK_EXT_depth_range_unrestricted spec:
3596 * "The behavior described in Primitive Clipping still applies.
3597 * If depth clamping is disabled the depth values are still
3598 * clipped to 0 ≤ zc ≤ wc before the viewport transform. If
3599 * depth clamping is enabled the above equation is ignored and
3600 * the depth values are instead clamped to the VkViewport
3601 * minDepth and maxDepth values, which in the case of this
3602 * extension can be outside of the 0.0 to 1.0 range."
3604 db_render_override
|= S_02800C_DISABLE_VIEWPORT_CLAMP(1);
3607 radeon_set_context_reg(ctx_cs
, R_028800_DB_DEPTH_CONTROL
, db_depth_control
);
3608 radeon_set_context_reg(ctx_cs
, R_02842C_DB_STENCIL_CONTROL
, db_stencil_control
);
3610 radeon_set_context_reg(ctx_cs
, R_028000_DB_RENDER_CONTROL
, db_render_control
);
3611 radeon_set_context_reg(ctx_cs
, R_02800C_DB_RENDER_OVERRIDE
, db_render_override
);
3612 radeon_set_context_reg(ctx_cs
, R_028010_DB_RENDER_OVERRIDE2
, db_render_override2
);
3616 radv_pipeline_generate_blend_state(struct radeon_cmdbuf
*ctx_cs
,
3617 struct radv_pipeline
*pipeline
,
3618 const struct radv_blend_state
*blend
)
3620 radeon_set_context_reg_seq(ctx_cs
, R_028780_CB_BLEND0_CONTROL
, 8);
3621 radeon_emit_array(ctx_cs
, blend
->cb_blend_control
,
3623 radeon_set_context_reg(ctx_cs
, R_028808_CB_COLOR_CONTROL
, blend
->cb_color_control
);
3624 radeon_set_context_reg(ctx_cs
, R_028B70_DB_ALPHA_TO_MASK
, blend
->db_alpha_to_mask
);
3626 if (pipeline
->device
->physical_device
->rad_info
.has_rbplus
) {
3628 radeon_set_context_reg_seq(ctx_cs
, R_028760_SX_MRT0_BLEND_OPT
, 8);
3629 radeon_emit_array(ctx_cs
, blend
->sx_mrt_blend_opt
, 8);
3632 radeon_set_context_reg(ctx_cs
, R_028714_SPI_SHADER_COL_FORMAT
, blend
->spi_shader_col_format
);
3634 radeon_set_context_reg(ctx_cs
, R_028238_CB_TARGET_MASK
, blend
->cb_target_mask
);
3635 radeon_set_context_reg(ctx_cs
, R_02823C_CB_SHADER_MASK
, blend
->cb_shader_mask
);
3637 pipeline
->graphics
.col_format
= blend
->spi_shader_col_format
;
3638 pipeline
->graphics
.cb_target_mask
= blend
->cb_target_mask
;
3641 static const VkConservativeRasterizationModeEXT
3642 radv_get_conservative_raster_mode(const VkPipelineRasterizationStateCreateInfo
*pCreateInfo
)
3644 const VkPipelineRasterizationConservativeStateCreateInfoEXT
*conservative_raster
=
3645 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_RASTERIZATION_CONSERVATIVE_STATE_CREATE_INFO_EXT
);
3647 if (!conservative_raster
)
3648 return VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
;
3649 return conservative_raster
->conservativeRasterizationMode
;
3653 radv_pipeline_generate_raster_state(struct radeon_cmdbuf
*ctx_cs
,
3654 struct radv_pipeline
*pipeline
,
3655 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
3657 const VkPipelineRasterizationStateCreateInfo
*vkraster
= pCreateInfo
->pRasterizationState
;
3658 const VkConservativeRasterizationModeEXT mode
=
3659 radv_get_conservative_raster_mode(vkraster
);
3660 uint32_t pa_sc_conservative_rast
= S_028C4C_NULL_SQUAD_AA_MASK_ENABLE(1);
3661 bool depth_clip_disable
= vkraster
->depthClampEnable
;
3663 const VkPipelineRasterizationDepthClipStateCreateInfoEXT
*depth_clip_state
=
3664 vk_find_struct_const(vkraster
->pNext
, PIPELINE_RASTERIZATION_DEPTH_CLIP_STATE_CREATE_INFO_EXT
);
3665 if (depth_clip_state
) {
3666 depth_clip_disable
= !depth_clip_state
->depthClipEnable
;
3669 radeon_set_context_reg(ctx_cs
, R_028810_PA_CL_CLIP_CNTL
,
3670 S_028810_DX_CLIP_SPACE_DEF(1) | // vulkan uses DX conventions.
3671 S_028810_ZCLIP_NEAR_DISABLE(depth_clip_disable
? 1 : 0) |
3672 S_028810_ZCLIP_FAR_DISABLE(depth_clip_disable
? 1 : 0) |
3673 S_028810_DX_RASTERIZATION_KILL(vkraster
->rasterizerDiscardEnable
? 1 : 0) |
3674 S_028810_DX_LINEAR_ATTR_CLIP_ENA(1));
3676 radeon_set_context_reg(ctx_cs
, R_0286D4_SPI_INTERP_CONTROL_0
,
3677 S_0286D4_FLAT_SHADE_ENA(1) |
3678 S_0286D4_PNT_SPRITE_ENA(1) |
3679 S_0286D4_PNT_SPRITE_OVRD_X(V_0286D4_SPI_PNT_SPRITE_SEL_S
) |
3680 S_0286D4_PNT_SPRITE_OVRD_Y(V_0286D4_SPI_PNT_SPRITE_SEL_T
) |
3681 S_0286D4_PNT_SPRITE_OVRD_Z(V_0286D4_SPI_PNT_SPRITE_SEL_0
) |
3682 S_0286D4_PNT_SPRITE_OVRD_W(V_0286D4_SPI_PNT_SPRITE_SEL_1
) |
3683 S_0286D4_PNT_SPRITE_TOP_1(0)); /* vulkan is top to bottom - 1.0 at bottom */
3685 radeon_set_context_reg(ctx_cs
, R_028BE4_PA_SU_VTX_CNTL
,
3686 S_028BE4_PIX_CENTER(1) | // TODO verify
3687 S_028BE4_ROUND_MODE(V_028BE4_X_ROUND_TO_EVEN
) |
3688 S_028BE4_QUANT_MODE(V_028BE4_X_16_8_FIXED_POINT_1_256TH
));
3690 pipeline
->graphics
.pa_su_sc_mode_cntl
=
3691 S_028814_FACE(vkraster
->frontFace
) |
3692 S_028814_CULL_FRONT(!!(vkraster
->cullMode
& VK_CULL_MODE_FRONT_BIT
)) |
3693 S_028814_CULL_BACK(!!(vkraster
->cullMode
& VK_CULL_MODE_BACK_BIT
)) |
3694 S_028814_POLY_MODE(vkraster
->polygonMode
!= VK_POLYGON_MODE_FILL
) |
3695 S_028814_POLYMODE_FRONT_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3696 S_028814_POLYMODE_BACK_PTYPE(si_translate_fill(vkraster
->polygonMode
)) |
3697 S_028814_POLY_OFFSET_FRONT_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3698 S_028814_POLY_OFFSET_BACK_ENABLE(vkraster
->depthBiasEnable
? 1 : 0) |
3699 S_028814_POLY_OFFSET_PARA_ENABLE(vkraster
->depthBiasEnable
? 1 : 0);
3701 /* Conservative rasterization. */
3702 if (mode
!= VK_CONSERVATIVE_RASTERIZATION_MODE_DISABLED_EXT
) {
3703 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3705 ms
->pa_sc_aa_config
|= S_028BE0_AA_MASK_CENTROID_DTMN(1);
3706 ms
->db_eqaa
|= S_028804_ENABLE_POSTZ_OVERRASTERIZATION(1) |
3707 S_028804_OVERRASTERIZATION_AMOUNT(4);
3709 pa_sc_conservative_rast
= S_028C4C_PREZ_AA_MASK_ENABLE(1) |
3710 S_028C4C_POSTZ_AA_MASK_ENABLE(1) |
3711 S_028C4C_CENTROID_SAMPLE_OVERRIDE(1);
3713 if (mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_OVERESTIMATE_EXT
) {
3714 pa_sc_conservative_rast
|=
3715 S_028C4C_OVER_RAST_ENABLE(1) |
3716 S_028C4C_OVER_RAST_SAMPLE_SELECT(0) |
3717 S_028C4C_UNDER_RAST_ENABLE(0) |
3718 S_028C4C_UNDER_RAST_SAMPLE_SELECT(1) |
3719 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(1);
3721 assert(mode
== VK_CONSERVATIVE_RASTERIZATION_MODE_UNDERESTIMATE_EXT
);
3722 pa_sc_conservative_rast
|=
3723 S_028C4C_OVER_RAST_ENABLE(0) |
3724 S_028C4C_OVER_RAST_SAMPLE_SELECT(1) |
3725 S_028C4C_UNDER_RAST_ENABLE(1) |
3726 S_028C4C_UNDER_RAST_SAMPLE_SELECT(0) |
3727 S_028C4C_PBB_UNCERTAINTY_REGION_ENABLE(0);
3731 radeon_set_context_reg(ctx_cs
, R_028C4C_PA_SC_CONSERVATIVE_RASTERIZATION_CNTL
,
3732 pa_sc_conservative_rast
);
3737 radv_pipeline_generate_multisample_state(struct radeon_cmdbuf
*ctx_cs
,
3738 struct radv_pipeline
*pipeline
)
3740 struct radv_multisample_state
*ms
= &pipeline
->graphics
.ms
;
3742 radeon_set_context_reg_seq(ctx_cs
, R_028C38_PA_SC_AA_MASK_X0Y0_X1Y0
, 2);
3743 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[0]);
3744 radeon_emit(ctx_cs
, ms
->pa_sc_aa_mask
[1]);
3746 radeon_set_context_reg(ctx_cs
, R_028804_DB_EQAA
, ms
->db_eqaa
);
3747 radeon_set_context_reg(ctx_cs
, R_028A48_PA_SC_MODE_CNTL_0
, ms
->pa_sc_mode_cntl_0
);
3748 radeon_set_context_reg(ctx_cs
, R_028A4C_PA_SC_MODE_CNTL_1
, ms
->pa_sc_mode_cntl_1
);
3749 radeon_set_context_reg(ctx_cs
, R_028BDC_PA_SC_LINE_CNTL
, ms
->pa_sc_line_cntl
);
3750 radeon_set_context_reg(ctx_cs
, R_028BE0_PA_SC_AA_CONFIG
, ms
->pa_sc_aa_config
);
3752 /* The exclusion bits can be set to improve rasterization efficiency
3753 * if no sample lies on the pixel boundary (-8 sample offset). It's
3754 * currently always TRUE because the driver doesn't support 16 samples.
3756 bool exclusion
= pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
;
3757 radeon_set_context_reg(ctx_cs
, R_02882C_PA_SU_PRIM_FILTER_CNTL
,
3758 S_02882C_XMAX_RIGHT_EXCLUSION(exclusion
) |
3759 S_02882C_YMAX_BOTTOM_EXCLUSION(exclusion
));
3761 /* GFX9: Flush DFSM when the AA mode changes. */
3762 if (pipeline
->device
->dfsm_allowed
) {
3763 radeon_emit(ctx_cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
3764 radeon_emit(ctx_cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
3769 radv_pipeline_generate_vgt_gs_mode(struct radeon_cmdbuf
*ctx_cs
,
3770 struct radv_pipeline
*pipeline
)
3772 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3773 const struct radv_shader_variant
*vs
=
3774 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] ?
3775 pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] :
3776 pipeline
->shaders
[MESA_SHADER_VERTEX
];
3777 unsigned vgt_primitiveid_en
= 0;
3778 uint32_t vgt_gs_mode
= 0;
3780 if (radv_pipeline_has_ngg(pipeline
))
3783 if (radv_pipeline_has_gs(pipeline
)) {
3784 const struct radv_shader_variant
*gs
=
3785 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3787 vgt_gs_mode
= ac_vgt_gs_mode(gs
->info
.gs
.vertices_out
,
3788 pipeline
->device
->physical_device
->rad_info
.chip_class
);
3789 } else if (outinfo
->export_prim_id
|| vs
->info
.uses_prim_id
) {
3790 vgt_gs_mode
= S_028A40_MODE(V_028A40_GS_SCENARIO_A
);
3791 vgt_primitiveid_en
|= S_028A84_PRIMITIVEID_EN(1);
3794 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
, vgt_primitiveid_en
);
3795 radeon_set_context_reg(ctx_cs
, R_028A40_VGT_GS_MODE
, vgt_gs_mode
);
3799 radv_pipeline_generate_hw_vs(struct radeon_cmdbuf
*ctx_cs
,
3800 struct radeon_cmdbuf
*cs
,
3801 struct radv_pipeline
*pipeline
,
3802 struct radv_shader_variant
*shader
)
3804 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3806 radeon_set_sh_reg_seq(cs
, R_00B120_SPI_SHADER_PGM_LO_VS
, 4);
3807 radeon_emit(cs
, va
>> 8);
3808 radeon_emit(cs
, S_00B124_MEM_BASE(va
>> 40));
3809 radeon_emit(cs
, shader
->config
.rsrc1
);
3810 radeon_emit(cs
, shader
->config
.rsrc2
);
3812 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3813 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3814 clip_dist_mask
= outinfo
->clip_dist_mask
;
3815 cull_dist_mask
= outinfo
->cull_dist_mask
;
3816 total_mask
= clip_dist_mask
| cull_dist_mask
;
3817 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3818 outinfo
->writes_layer
||
3819 outinfo
->writes_viewport_index
;
3820 unsigned spi_vs_out_config
, nparams
;
3822 /* VS is required to export at least one param. */
3823 nparams
= MAX2(outinfo
->param_exports
, 1);
3824 spi_vs_out_config
= S_0286C4_VS_EXPORT_COUNT(nparams
- 1);
3826 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
3827 spi_vs_out_config
|= S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0);
3830 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
, spi_vs_out_config
);
3832 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3833 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3834 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3835 V_02870C_SPI_SHADER_4COMP
:
3836 V_02870C_SPI_SHADER_NONE
) |
3837 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3838 V_02870C_SPI_SHADER_4COMP
:
3839 V_02870C_SPI_SHADER_NONE
) |
3840 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3841 V_02870C_SPI_SHADER_4COMP
:
3842 V_02870C_SPI_SHADER_NONE
));
3844 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
3845 S_028818_VTX_W0_FMT(1) |
3846 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3847 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3848 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3850 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3851 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3852 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3853 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3854 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3855 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3856 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3857 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3858 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
) |
3859 cull_dist_mask
<< 8 |
3862 if (pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX8
)
3863 radeon_set_context_reg(ctx_cs
, R_028AB4_VGT_REUSE_OFF
,
3864 outinfo
->writes_viewport_index
);
3868 radv_pipeline_generate_hw_es(struct radeon_cmdbuf
*cs
,
3869 struct radv_pipeline
*pipeline
,
3870 struct radv_shader_variant
*shader
)
3872 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3874 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 4);
3875 radeon_emit(cs
, va
>> 8);
3876 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3877 radeon_emit(cs
, shader
->config
.rsrc1
);
3878 radeon_emit(cs
, shader
->config
.rsrc2
);
3882 radv_pipeline_generate_hw_ls(struct radeon_cmdbuf
*cs
,
3883 struct radv_pipeline
*pipeline
,
3884 struct radv_shader_variant
*shader
,
3885 const struct radv_tessellation_state
*tess
)
3887 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3888 uint32_t rsrc2
= shader
->config
.rsrc2
;
3890 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
3891 radeon_emit(cs
, va
>> 8);
3892 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
3894 rsrc2
|= S_00B52C_LDS_SIZE(tess
->lds_size
);
3895 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX7
&&
3896 pipeline
->device
->physical_device
->rad_info
.family
!= CHIP_HAWAII
)
3897 radeon_set_sh_reg(cs
, R_00B52C_SPI_SHADER_PGM_RSRC2_LS
, rsrc2
);
3899 radeon_set_sh_reg_seq(cs
, R_00B528_SPI_SHADER_PGM_RSRC1_LS
, 2);
3900 radeon_emit(cs
, shader
->config
.rsrc1
);
3901 radeon_emit(cs
, rsrc2
);
3905 radv_pipeline_generate_hw_ngg(struct radeon_cmdbuf
*ctx_cs
,
3906 struct radeon_cmdbuf
*cs
,
3907 struct radv_pipeline
*pipeline
,
3908 struct radv_shader_variant
*shader
)
3910 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
3911 gl_shader_stage es_type
=
3912 radv_pipeline_has_tess(pipeline
) ? MESA_SHADER_TESS_EVAL
: MESA_SHADER_VERTEX
;
3913 struct radv_shader_variant
*es
=
3914 es_type
== MESA_SHADER_TESS_EVAL
? pipeline
->shaders
[MESA_SHADER_TESS_EVAL
] : pipeline
->shaders
[MESA_SHADER_VERTEX
];
3915 const struct gfx10_ngg_info
*ngg_state
= &shader
->info
.ngg_info
;
3917 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
3918 radeon_emit(cs
, va
>> 8);
3919 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
3920 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
3921 radeon_emit(cs
, shader
->config
.rsrc1
);
3922 radeon_emit(cs
, shader
->config
.rsrc2
);
3924 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
3925 unsigned clip_dist_mask
, cull_dist_mask
, total_mask
;
3926 clip_dist_mask
= outinfo
->clip_dist_mask
;
3927 cull_dist_mask
= outinfo
->cull_dist_mask
;
3928 total_mask
= clip_dist_mask
| cull_dist_mask
;
3929 bool misc_vec_ena
= outinfo
->writes_pointsize
||
3930 outinfo
->writes_layer
||
3931 outinfo
->writes_viewport_index
;
3932 bool es_enable_prim_id
= outinfo
->export_prim_id
||
3933 (es
&& es
->info
.uses_prim_id
);
3934 bool break_wave_at_eoi
= false;
3938 if (es_type
== MESA_SHADER_TESS_EVAL
) {
3939 struct radv_shader_variant
*gs
=
3940 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3942 if (es_enable_prim_id
|| (gs
&& gs
->info
.uses_prim_id
))
3943 break_wave_at_eoi
= true;
3946 nparams
= MAX2(outinfo
->param_exports
, 1);
3947 radeon_set_context_reg(ctx_cs
, R_0286C4_SPI_VS_OUT_CONFIG
,
3948 S_0286C4_VS_EXPORT_COUNT(nparams
- 1) |
3949 S_0286C4_NO_PC_EXPORT(outinfo
->param_exports
== 0));
3951 radeon_set_context_reg(ctx_cs
, R_028708_SPI_SHADER_IDX_FORMAT
,
3952 S_028708_IDX0_EXPORT_FORMAT(V_028708_SPI_SHADER_1COMP
));
3953 radeon_set_context_reg(ctx_cs
, R_02870C_SPI_SHADER_POS_FORMAT
,
3954 S_02870C_POS0_EXPORT_FORMAT(V_02870C_SPI_SHADER_4COMP
) |
3955 S_02870C_POS1_EXPORT_FORMAT(outinfo
->pos_exports
> 1 ?
3956 V_02870C_SPI_SHADER_4COMP
:
3957 V_02870C_SPI_SHADER_NONE
) |
3958 S_02870C_POS2_EXPORT_FORMAT(outinfo
->pos_exports
> 2 ?
3959 V_02870C_SPI_SHADER_4COMP
:
3960 V_02870C_SPI_SHADER_NONE
) |
3961 S_02870C_POS3_EXPORT_FORMAT(outinfo
->pos_exports
> 3 ?
3962 V_02870C_SPI_SHADER_4COMP
:
3963 V_02870C_SPI_SHADER_NONE
));
3965 radeon_set_context_reg(ctx_cs
, R_028818_PA_CL_VTE_CNTL
,
3966 S_028818_VTX_W0_FMT(1) |
3967 S_028818_VPORT_X_SCALE_ENA(1) | S_028818_VPORT_X_OFFSET_ENA(1) |
3968 S_028818_VPORT_Y_SCALE_ENA(1) | S_028818_VPORT_Y_OFFSET_ENA(1) |
3969 S_028818_VPORT_Z_SCALE_ENA(1) | S_028818_VPORT_Z_OFFSET_ENA(1));
3970 radeon_set_context_reg(ctx_cs
, R_02881C_PA_CL_VS_OUT_CNTL
,
3971 S_02881C_USE_VTX_POINT_SIZE(outinfo
->writes_pointsize
) |
3972 S_02881C_USE_VTX_RENDER_TARGET_INDX(outinfo
->writes_layer
) |
3973 S_02881C_USE_VTX_VIEWPORT_INDX(outinfo
->writes_viewport_index
) |
3974 S_02881C_VS_OUT_MISC_VEC_ENA(misc_vec_ena
) |
3975 S_02881C_VS_OUT_MISC_SIDE_BUS_ENA(misc_vec_ena
) |
3976 S_02881C_VS_OUT_CCDIST0_VEC_ENA((total_mask
& 0x0f) != 0) |
3977 S_02881C_VS_OUT_CCDIST1_VEC_ENA((total_mask
& 0xf0) != 0) |
3978 S_02881C_BYPASS_PRIM_RATE_COMBINER_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
) |
3979 cull_dist_mask
<< 8 |
3982 radeon_set_context_reg(ctx_cs
, R_028A84_VGT_PRIMITIVEID_EN
,
3983 S_028A84_PRIMITIVEID_EN(es_enable_prim_id
) |
3984 S_028A84_NGG_DISABLE_PROVOK_REUSE(outinfo
->export_prim_id
));
3986 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
3987 ngg_state
->vgt_esgs_ring_itemsize
);
3989 /* NGG specific registers. */
3990 struct radv_shader_variant
*gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
3991 uint32_t gs_num_invocations
= gs
? gs
->info
.gs
.invocations
: 1;
3993 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
3994 S_028A44_ES_VERTS_PER_SUBGRP(ngg_state
->hw_max_esverts
) |
3995 S_028A44_GS_PRIMS_PER_SUBGRP(ngg_state
->max_gsprims
) |
3996 S_028A44_GS_INST_PRIMS_IN_SUBGRP(ngg_state
->max_gsprims
* gs_num_invocations
));
3997 radeon_set_context_reg(ctx_cs
, R_0287FC_GE_MAX_OUTPUT_PER_SUBGROUP
,
3998 S_0287FC_MAX_VERTS_PER_SUBGROUP(ngg_state
->max_out_verts
));
3999 radeon_set_context_reg(ctx_cs
, R_028B4C_GE_NGG_SUBGRP_CNTL
,
4000 S_028B4C_PRIM_AMP_FACTOR(ngg_state
->prim_amp_factor
) |
4001 S_028B4C_THDS_PER_SUBGRP(0)); /* for fast launch */
4002 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
4003 S_028B90_CNT(gs_num_invocations
) |
4004 S_028B90_ENABLE(gs_num_invocations
> 1) |
4005 S_028B90_EN_MAX_VERT_OUT_PER_GS_INSTANCE(ngg_state
->max_vert_out_per_gs_instance
));
4007 /* User edge flags are set by the pos exports. If user edge flags are
4008 * not used, we must use hw-generated edge flags and pass them via
4009 * the prim export to prevent drawing lines on internal edges of
4010 * decomposed primitives (such as quads) with polygon mode = lines.
4012 * TODO: We should combine hw-generated edge flags with user edge
4013 * flags in the shader.
4015 radeon_set_context_reg(ctx_cs
, R_028838_PA_CL_NGG_CNTL
,
4016 S_028838_INDEX_BUF_EDGE_FLAG_ENA(!radv_pipeline_has_tess(pipeline
) &&
4017 !radv_pipeline_has_gs(pipeline
)) |
4018 /* Reuse for NGG. */
4019 S_028838_VERTEX_REUSE_DEPTH_GFX103(pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10_3
? 30 : 0));
4021 ge_cntl
= S_03096C_PRIM_GRP_SIZE(ngg_state
->max_gsprims
) |
4022 S_03096C_VERT_GRP_SIZE(256) | /* 256 = disable vertex grouping */
4023 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
);
4025 /* Bug workaround for a possible hang with non-tessellation cases.
4026 * Tessellation always sets GE_CNTL.VERT_GRP_SIZE = 0
4028 * Requirement: GE_CNTL.VERT_GRP_SIZE = VGT_GS_ONCHIP_CNTL.ES_VERTS_PER_SUBGRP - 5
4030 if (pipeline
->device
->physical_device
->rad_info
.chip_class
== GFX10
&&
4031 !radv_pipeline_has_tess(pipeline
) &&
4032 ngg_state
->hw_max_esverts
!= 256) {
4033 ge_cntl
&= C_03096C_VERT_GRP_SIZE
;
4035 if (ngg_state
->hw_max_esverts
> 5) {
4036 ge_cntl
|= S_03096C_VERT_GRP_SIZE(ngg_state
->hw_max_esverts
- 5);
4040 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
, ge_cntl
);
4044 radv_pipeline_generate_hw_hs(struct radeon_cmdbuf
*cs
,
4045 struct radv_pipeline
*pipeline
,
4046 struct radv_shader_variant
*shader
,
4047 const struct radv_tessellation_state
*tess
)
4049 uint64_t va
= radv_buffer_get_va(shader
->bo
) + shader
->bo_offset
;
4051 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4052 unsigned hs_rsrc2
= shader
->config
.rsrc2
;
4054 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4055 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX10(tess
->lds_size
);
4057 hs_rsrc2
|= S_00B42C_LDS_SIZE_GFX9(tess
->lds_size
);
4060 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4061 radeon_set_sh_reg_seq(cs
, R_00B520_SPI_SHADER_PGM_LO_LS
, 2);
4062 radeon_emit(cs
, va
>> 8);
4063 radeon_emit(cs
, S_00B524_MEM_BASE(va
>> 40));
4065 radeon_set_sh_reg_seq(cs
, R_00B410_SPI_SHADER_PGM_LO_LS
, 2);
4066 radeon_emit(cs
, va
>> 8);
4067 radeon_emit(cs
, S_00B414_MEM_BASE(va
>> 40));
4070 radeon_set_sh_reg_seq(cs
, R_00B428_SPI_SHADER_PGM_RSRC1_HS
, 2);
4071 radeon_emit(cs
, shader
->config
.rsrc1
);
4072 radeon_emit(cs
, hs_rsrc2
);
4074 radeon_set_sh_reg_seq(cs
, R_00B420_SPI_SHADER_PGM_LO_HS
, 4);
4075 radeon_emit(cs
, va
>> 8);
4076 radeon_emit(cs
, S_00B424_MEM_BASE(va
>> 40));
4077 radeon_emit(cs
, shader
->config
.rsrc1
);
4078 radeon_emit(cs
, shader
->config
.rsrc2
);
4083 radv_pipeline_generate_vertex_shader(struct radeon_cmdbuf
*ctx_cs
,
4084 struct radeon_cmdbuf
*cs
,
4085 struct radv_pipeline
*pipeline
,
4086 const struct radv_tessellation_state
*tess
)
4088 struct radv_shader_variant
*vs
;
4090 /* Skip shaders merged into HS/GS */
4091 vs
= pipeline
->shaders
[MESA_SHADER_VERTEX
];
4095 if (vs
->info
.vs
.as_ls
)
4096 radv_pipeline_generate_hw_ls(cs
, pipeline
, vs
, tess
);
4097 else if (vs
->info
.vs
.as_es
)
4098 radv_pipeline_generate_hw_es(cs
, pipeline
, vs
);
4099 else if (vs
->info
.is_ngg
)
4100 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, vs
);
4102 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, vs
);
4106 radv_pipeline_generate_tess_shaders(struct radeon_cmdbuf
*ctx_cs
,
4107 struct radeon_cmdbuf
*cs
,
4108 struct radv_pipeline
*pipeline
,
4109 const struct radv_tessellation_state
*tess
)
4111 if (!radv_pipeline_has_tess(pipeline
))
4114 struct radv_shader_variant
*tes
, *tcs
;
4116 tcs
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
];
4117 tes
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
];
4120 if (tes
->info
.is_ngg
) {
4121 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, tes
);
4122 } else if (tes
->info
.tes
.as_es
)
4123 radv_pipeline_generate_hw_es(cs
, pipeline
, tes
);
4125 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, tes
);
4128 radv_pipeline_generate_hw_hs(cs
, pipeline
, tcs
, tess
);
4130 radeon_set_context_reg(ctx_cs
, R_028B6C_VGT_TF_PARAM
,
4133 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX7
)
4134 radeon_set_context_reg_idx(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
, 2,
4135 tess
->ls_hs_config
);
4137 radeon_set_context_reg(ctx_cs
, R_028B58_VGT_LS_HS_CONFIG
,
4138 tess
->ls_hs_config
);
4140 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
4141 !radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
4142 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
,
4143 S_028A44_ES_VERTS_PER_SUBGRP(250) |
4144 S_028A44_GS_PRIMS_PER_SUBGRP(126) |
4145 S_028A44_GS_INST_PRIMS_IN_SUBGRP(126));
4150 radv_pipeline_generate_hw_gs(struct radeon_cmdbuf
*ctx_cs
,
4151 struct radeon_cmdbuf
*cs
,
4152 struct radv_pipeline
*pipeline
,
4153 struct radv_shader_variant
*gs
)
4155 const struct gfx9_gs_info
*gs_state
= &gs
->info
.gs_ring_info
;
4156 unsigned gs_max_out_vertices
;
4157 uint8_t *num_components
;
4162 gs_max_out_vertices
= gs
->info
.gs
.vertices_out
;
4163 max_stream
= gs
->info
.gs
.max_stream
;
4164 num_components
= gs
->info
.gs
.num_stream_output_components
;
4166 offset
= num_components
[0] * gs_max_out_vertices
;
4168 radeon_set_context_reg_seq(ctx_cs
, R_028A60_VGT_GSVS_RING_OFFSET_1
, 3);
4169 radeon_emit(ctx_cs
, offset
);
4170 if (max_stream
>= 1)
4171 offset
+= num_components
[1] * gs_max_out_vertices
;
4172 radeon_emit(ctx_cs
, offset
);
4173 if (max_stream
>= 2)
4174 offset
+= num_components
[2] * gs_max_out_vertices
;
4175 radeon_emit(ctx_cs
, offset
);
4176 if (max_stream
>= 3)
4177 offset
+= num_components
[3] * gs_max_out_vertices
;
4178 radeon_set_context_reg(ctx_cs
, R_028AB0_VGT_GSVS_RING_ITEMSIZE
, offset
);
4180 radeon_set_context_reg_seq(ctx_cs
, R_028B5C_VGT_GS_VERT_ITEMSIZE
, 4);
4181 radeon_emit(ctx_cs
, num_components
[0]);
4182 radeon_emit(ctx_cs
, (max_stream
>= 1) ? num_components
[1] : 0);
4183 radeon_emit(ctx_cs
, (max_stream
>= 2) ? num_components
[2] : 0);
4184 radeon_emit(ctx_cs
, (max_stream
>= 3) ? num_components
[3] : 0);
4186 uint32_t gs_num_invocations
= gs
->info
.gs
.invocations
;
4187 radeon_set_context_reg(ctx_cs
, R_028B90_VGT_GS_INSTANCE_CNT
,
4188 S_028B90_CNT(MIN2(gs_num_invocations
, 127)) |
4189 S_028B90_ENABLE(gs_num_invocations
> 0));
4191 radeon_set_context_reg(ctx_cs
, R_028AAC_VGT_ESGS_RING_ITEMSIZE
,
4192 gs_state
->vgt_esgs_ring_itemsize
);
4194 va
= radv_buffer_get_va(gs
->bo
) + gs
->bo_offset
;
4196 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
) {
4197 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4198 radeon_set_sh_reg_seq(cs
, R_00B320_SPI_SHADER_PGM_LO_ES
, 2);
4199 radeon_emit(cs
, va
>> 8);
4200 radeon_emit(cs
, S_00B324_MEM_BASE(va
>> 40));
4202 radeon_set_sh_reg_seq(cs
, R_00B210_SPI_SHADER_PGM_LO_ES
, 2);
4203 radeon_emit(cs
, va
>> 8);
4204 radeon_emit(cs
, S_00B214_MEM_BASE(va
>> 40));
4207 radeon_set_sh_reg_seq(cs
, R_00B228_SPI_SHADER_PGM_RSRC1_GS
, 2);
4208 radeon_emit(cs
, gs
->config
.rsrc1
);
4209 radeon_emit(cs
, gs
->config
.rsrc2
| S_00B22C_LDS_SIZE(gs_state
->lds_size
));
4211 radeon_set_context_reg(ctx_cs
, R_028A44_VGT_GS_ONCHIP_CNTL
, gs_state
->vgt_gs_onchip_cntl
);
4212 radeon_set_context_reg(ctx_cs
, R_028A94_VGT_GS_MAX_PRIMS_PER_SUBGROUP
, gs_state
->vgt_gs_max_prims_per_subgroup
);
4214 radeon_set_sh_reg_seq(cs
, R_00B220_SPI_SHADER_PGM_LO_GS
, 4);
4215 radeon_emit(cs
, va
>> 8);
4216 radeon_emit(cs
, S_00B224_MEM_BASE(va
>> 40));
4217 radeon_emit(cs
, gs
->config
.rsrc1
);
4218 radeon_emit(cs
, gs
->config
.rsrc2
);
4221 radv_pipeline_generate_hw_vs(ctx_cs
, cs
, pipeline
, pipeline
->gs_copy_shader
);
4225 radv_pipeline_generate_geometry_shader(struct radeon_cmdbuf
*ctx_cs
,
4226 struct radeon_cmdbuf
*cs
,
4227 struct radv_pipeline
*pipeline
)
4229 struct radv_shader_variant
*gs
;
4231 gs
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4235 if (gs
->info
.is_ngg
)
4236 radv_pipeline_generate_hw_ngg(ctx_cs
, cs
, pipeline
, gs
);
4238 radv_pipeline_generate_hw_gs(ctx_cs
, cs
, pipeline
, gs
);
4240 radeon_set_context_reg(ctx_cs
, R_028B38_VGT_GS_MAX_VERT_OUT
,
4241 gs
->info
.gs
.vertices_out
);
4244 static uint32_t offset_to_ps_input(uint32_t offset
, bool flat_shade
,
4245 bool explicit, bool float16
)
4247 uint32_t ps_input_cntl
;
4248 if (offset
<= AC_EXP_PARAM_OFFSET_31
) {
4249 ps_input_cntl
= S_028644_OFFSET(offset
);
4250 if (flat_shade
|| explicit)
4251 ps_input_cntl
|= S_028644_FLAT_SHADE(1);
4253 /* Force parameter cache to be read in passthrough
4256 ps_input_cntl
|= S_028644_OFFSET(1 << 5);
4259 ps_input_cntl
|= S_028644_FP16_INTERP_MODE(1) |
4260 S_028644_ATTR0_VALID(1);
4263 /* The input is a DEFAULT_VAL constant. */
4264 assert(offset
>= AC_EXP_PARAM_DEFAULT_VAL_0000
&&
4265 offset
<= AC_EXP_PARAM_DEFAULT_VAL_1111
);
4266 offset
-= AC_EXP_PARAM_DEFAULT_VAL_0000
;
4267 ps_input_cntl
= S_028644_OFFSET(0x20) |
4268 S_028644_DEFAULT_VAL(offset
);
4270 return ps_input_cntl
;
4274 radv_pipeline_generate_ps_inputs(struct radeon_cmdbuf
*ctx_cs
,
4275 struct radv_pipeline
*pipeline
)
4277 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4278 const struct radv_vs_output_info
*outinfo
= get_vs_output_info(pipeline
);
4279 uint32_t ps_input_cntl
[32];
4281 unsigned ps_offset
= 0;
4283 if (ps
->info
.ps
.prim_id_input
) {
4284 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_PRIMITIVE_ID
];
4285 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4286 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4291 if (ps
->info
.ps
.layer_input
||
4292 ps
->info
.needs_multiview_view_index
) {
4293 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_LAYER
];
4294 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
4295 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4297 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false, false);
4301 if (ps
->info
.ps
.viewport_index_input
) {
4302 unsigned vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VIEWPORT
];
4303 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
)
4304 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, true, false, false);
4306 ps_input_cntl
[ps_offset
] = offset_to_ps_input(AC_EXP_PARAM_DEFAULT_VAL_0000
, true, false, false);
4310 if (ps
->info
.ps
.has_pcoord
) {
4312 val
= S_028644_PT_SPRITE_TEX(1) | S_028644_OFFSET(0x20);
4313 ps_input_cntl
[ps_offset
] = val
;
4317 if (ps
->info
.ps
.num_input_clips_culls
) {
4320 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST0
];
4321 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
) {
4322 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false, false);
4326 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_CLIP_DIST1
];
4327 if (vs_offset
!= AC_EXP_PARAM_UNDEFINED
&&
4328 ps
->info
.ps
.num_input_clips_culls
> 4) {
4329 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, false, false, false);
4334 for (unsigned i
= 0; i
< 32 && (1u << i
) <= ps
->info
.ps
.input_mask
; ++i
) {
4339 if (!(ps
->info
.ps
.input_mask
& (1u << i
)))
4342 vs_offset
= outinfo
->vs_output_param_offset
[VARYING_SLOT_VAR0
+ i
];
4343 if (vs_offset
== AC_EXP_PARAM_UNDEFINED
) {
4344 ps_input_cntl
[ps_offset
] = S_028644_OFFSET(0x20);
4349 flat_shade
= !!(ps
->info
.ps
.flat_shaded_mask
& (1u << ps_offset
));
4350 explicit = !!(ps
->info
.ps
.explicit_shaded_mask
& (1u << ps_offset
));
4351 float16
= !!(ps
->info
.ps
.float16_shaded_mask
& (1u << ps_offset
));
4353 ps_input_cntl
[ps_offset
] = offset_to_ps_input(vs_offset
, flat_shade
, explicit, float16
);
4358 radeon_set_context_reg_seq(ctx_cs
, R_028644_SPI_PS_INPUT_CNTL_0
, ps_offset
);
4359 for (unsigned i
= 0; i
< ps_offset
; i
++) {
4360 radeon_emit(ctx_cs
, ps_input_cntl
[i
]);
4366 radv_compute_db_shader_control(const struct radv_device
*device
,
4367 const struct radv_pipeline
*pipeline
,
4368 const struct radv_shader_variant
*ps
)
4370 unsigned conservative_z_export
= V_02880C_EXPORT_ANY_Z
;
4372 if (ps
->info
.ps
.early_fragment_test
|| !ps
->info
.ps
.writes_memory
)
4373 z_order
= V_02880C_EARLY_Z_THEN_LATE_Z
;
4375 z_order
= V_02880C_LATE_Z
;
4377 if (ps
->info
.ps
.depth_layout
== FRAG_DEPTH_LAYOUT_GREATER
)
4378 conservative_z_export
= V_02880C_EXPORT_GREATER_THAN_Z
;
4379 else if (ps
->info
.ps
.depth_layout
== FRAG_DEPTH_LAYOUT_LESS
)
4380 conservative_z_export
= V_02880C_EXPORT_LESS_THAN_Z
;
4382 bool disable_rbplus
= device
->physical_device
->rad_info
.has_rbplus
&&
4383 !device
->physical_device
->rad_info
.rbplus_allowed
;
4385 /* It shouldn't be needed to export gl_SampleMask when MSAA is disabled
4386 * but this appears to break Project Cars (DXVK). See
4387 * https://bugs.freedesktop.org/show_bug.cgi?id=109401
4389 bool mask_export_enable
= ps
->info
.ps
.writes_sample_mask
;
4391 return S_02880C_Z_EXPORT_ENABLE(ps
->info
.ps
.writes_z
) |
4392 S_02880C_STENCIL_TEST_VAL_EXPORT_ENABLE(ps
->info
.ps
.writes_stencil
) |
4393 S_02880C_KILL_ENABLE(!!ps
->info
.ps
.can_discard
) |
4394 S_02880C_MASK_EXPORT_ENABLE(mask_export_enable
) |
4395 S_02880C_CONSERVATIVE_Z_EXPORT(conservative_z_export
) |
4396 S_02880C_Z_ORDER(z_order
) |
4397 S_02880C_DEPTH_BEFORE_SHADER(ps
->info
.ps
.early_fragment_test
) |
4398 S_02880C_PRE_SHADER_DEPTH_COVERAGE_ENABLE(ps
->info
.ps
.post_depth_coverage
) |
4399 S_02880C_EXEC_ON_HIER_FAIL(ps
->info
.ps
.writes_memory
) |
4400 S_02880C_EXEC_ON_NOOP(ps
->info
.ps
.writes_memory
) |
4401 S_02880C_DUAL_QUAD_DISABLE(disable_rbplus
);
4405 radv_pipeline_generate_fragment_shader(struct radeon_cmdbuf
*ctx_cs
,
4406 struct radeon_cmdbuf
*cs
,
4407 struct radv_pipeline
*pipeline
)
4409 struct radv_shader_variant
*ps
;
4411 assert (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]);
4413 ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4414 va
= radv_buffer_get_va(ps
->bo
) + ps
->bo_offset
;
4416 radeon_set_sh_reg_seq(cs
, R_00B020_SPI_SHADER_PGM_LO_PS
, 4);
4417 radeon_emit(cs
, va
>> 8);
4418 radeon_emit(cs
, S_00B024_MEM_BASE(va
>> 40));
4419 radeon_emit(cs
, ps
->config
.rsrc1
);
4420 radeon_emit(cs
, ps
->config
.rsrc2
);
4422 radeon_set_context_reg(ctx_cs
, R_02880C_DB_SHADER_CONTROL
,
4423 radv_compute_db_shader_control(pipeline
->device
,
4426 radeon_set_context_reg(ctx_cs
, R_0286CC_SPI_PS_INPUT_ENA
,
4427 ps
->config
.spi_ps_input_ena
);
4429 radeon_set_context_reg(ctx_cs
, R_0286D0_SPI_PS_INPUT_ADDR
,
4430 ps
->config
.spi_ps_input_addr
);
4432 radeon_set_context_reg(ctx_cs
, R_0286D8_SPI_PS_IN_CONTROL
,
4433 S_0286D8_NUM_INTERP(ps
->info
.ps
.num_interp
) |
4434 S_0286D8_PS_W32_EN(ps
->info
.wave_size
== 32));
4436 radeon_set_context_reg(ctx_cs
, R_0286E0_SPI_BARYC_CNTL
, pipeline
->graphics
.spi_baryc_cntl
);
4438 radeon_set_context_reg(ctx_cs
, R_028710_SPI_SHADER_Z_FORMAT
,
4439 ac_get_spi_shader_z_format(ps
->info
.ps
.writes_z
,
4440 ps
->info
.ps
.writes_stencil
,
4441 ps
->info
.ps
.writes_sample_mask
));
4443 if (pipeline
->device
->dfsm_allowed
) {
4444 /* optimise this? */
4445 radeon_emit(cs
, PKT3(PKT3_EVENT_WRITE
, 0, 0));
4446 radeon_emit(cs
, EVENT_TYPE(V_028A90_FLUSH_DFSM
) | EVENT_INDEX(0));
4451 radv_pipeline_generate_vgt_vertex_reuse(struct radeon_cmdbuf
*ctx_cs
,
4452 struct radv_pipeline
*pipeline
)
4454 if (pipeline
->device
->physical_device
->rad_info
.family
< CHIP_POLARIS10
||
4455 pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
)
4458 unsigned vtx_reuse_depth
= 30;
4459 if (radv_pipeline_has_tess(pipeline
) &&
4460 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.tes
.spacing
== TESS_SPACING_FRACTIONAL_ODD
) {
4461 vtx_reuse_depth
= 14;
4463 radeon_set_context_reg(ctx_cs
, R_028C58_VGT_VERTEX_REUSE_BLOCK_CNTL
,
4464 S_028C58_VTX_REUSE_DEPTH(vtx_reuse_depth
));
4468 radv_compute_vgt_shader_stages_en(const struct radv_pipeline
*pipeline
)
4470 uint32_t stages
= 0;
4471 if (radv_pipeline_has_tess(pipeline
)) {
4472 stages
|= S_028B54_LS_EN(V_028B54_LS_STAGE_ON
) |
4473 S_028B54_HS_EN(1) | S_028B54_DYNAMIC_HS(1);
4475 if (radv_pipeline_has_gs(pipeline
))
4476 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
) |
4478 else if (radv_pipeline_has_ngg(pipeline
))
4479 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_DS
);
4481 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_DS
);
4482 } else if (radv_pipeline_has_gs(pipeline
)) {
4483 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
) |
4485 } else if (radv_pipeline_has_ngg(pipeline
)) {
4486 stages
|= S_028B54_ES_EN(V_028B54_ES_STAGE_REAL
);
4489 if (radv_pipeline_has_ngg(pipeline
)) {
4490 stages
|= S_028B54_PRIMGEN_EN(1);
4491 if (pipeline
->streamout_shader
)
4492 stages
|= S_028B54_NGG_WAVE_ID_EN(1);
4493 if (radv_pipeline_has_ngg_passthrough(pipeline
))
4494 stages
|= S_028B54_PRIMGEN_PASSTHRU_EN(1);
4495 } else if (radv_pipeline_has_gs(pipeline
)) {
4496 stages
|= S_028B54_VS_EN(V_028B54_VS_STAGE_COPY_SHADER
);
4499 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX9
)
4500 stages
|= S_028B54_MAX_PRIMGRP_IN_WAVE(2);
4502 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
4503 uint8_t hs_size
= 64, gs_size
= 64, vs_size
= 64;
4505 if (radv_pipeline_has_tess(pipeline
))
4506 hs_size
= pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.wave_size
;
4508 if (pipeline
->shaders
[MESA_SHADER_GEOMETRY
]) {
4509 vs_size
= gs_size
= pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.wave_size
;
4510 if (pipeline
->gs_copy_shader
)
4511 vs_size
= pipeline
->gs_copy_shader
->info
.wave_size
;
4512 } else if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
])
4513 vs_size
= pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.wave_size
;
4514 else if (pipeline
->shaders
[MESA_SHADER_VERTEX
])
4515 vs_size
= pipeline
->shaders
[MESA_SHADER_VERTEX
]->info
.wave_size
;
4517 if (radv_pipeline_has_ngg(pipeline
))
4520 /* legacy GS only supports Wave64 */
4521 stages
|= S_028B54_HS_W32_EN(hs_size
== 32 ? 1 : 0) |
4522 S_028B54_GS_W32_EN(gs_size
== 32 ? 1 : 0) |
4523 S_028B54_VS_W32_EN(vs_size
== 32 ? 1 : 0);
4530 radv_compute_cliprect_rule(const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4532 const VkPipelineDiscardRectangleStateCreateInfoEXT
*discard_rectangle_info
=
4533 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_DISCARD_RECTANGLE_STATE_CREATE_INFO_EXT
);
4535 if (!discard_rectangle_info
)
4540 for (unsigned i
= 0; i
< (1u << MAX_DISCARD_RECTANGLES
); ++i
) {
4541 /* Interpret i as a bitmask, and then set the bit in the mask if
4542 * that combination of rectangles in which the pixel is contained
4543 * should pass the cliprect test. */
4544 unsigned relevant_subset
= i
& ((1u << discard_rectangle_info
->discardRectangleCount
) - 1);
4546 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_INCLUSIVE_EXT
&&
4550 if (discard_rectangle_info
->discardRectangleMode
== VK_DISCARD_RECTANGLE_MODE_EXCLUSIVE_EXT
&&
4561 gfx10_pipeline_generate_ge_cntl(struct radeon_cmdbuf
*ctx_cs
,
4562 struct radv_pipeline
*pipeline
,
4563 const struct radv_tessellation_state
*tess
)
4565 bool break_wave_at_eoi
= false;
4566 unsigned primgroup_size
;
4567 unsigned vertgroup_size
= 256; /* 256 = disable vertex grouping */
4569 if (radv_pipeline_has_tess(pipeline
)) {
4570 primgroup_size
= tess
->num_patches
; /* must be a multiple of NUM_PATCHES */
4571 } else if (radv_pipeline_has_gs(pipeline
)) {
4572 const struct gfx9_gs_info
*gs_state
=
4573 &pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs_ring_info
;
4574 unsigned vgt_gs_onchip_cntl
= gs_state
->vgt_gs_onchip_cntl
;
4575 primgroup_size
= G_028A44_GS_PRIMS_PER_SUBGRP(vgt_gs_onchip_cntl
);
4577 primgroup_size
= 128; /* recommended without a GS and tess */
4580 if (radv_pipeline_has_tess(pipeline
)) {
4581 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4582 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4583 break_wave_at_eoi
= true;
4586 radeon_set_uconfig_reg(ctx_cs
, R_03096C_GE_CNTL
,
4587 S_03096C_PRIM_GRP_SIZE(primgroup_size
) |
4588 S_03096C_VERT_GRP_SIZE(vertgroup_size
) |
4589 S_03096C_PACKET_TO_ONE_PA(0) /* line stipple */ |
4590 S_03096C_BREAK_WAVE_AT_EOI(break_wave_at_eoi
));
4594 radv_pipeline_generate_pm4(struct radv_pipeline
*pipeline
,
4595 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4596 const struct radv_graphics_pipeline_create_info
*extra
,
4597 const struct radv_blend_state
*blend
,
4598 const struct radv_tessellation_state
*tess
,
4601 struct radeon_cmdbuf
*ctx_cs
= &pipeline
->ctx_cs
;
4602 struct radeon_cmdbuf
*cs
= &pipeline
->cs
;
4605 ctx_cs
->max_dw
= 256;
4606 cs
->buf
= malloc(4 * (cs
->max_dw
+ ctx_cs
->max_dw
));
4607 ctx_cs
->buf
= cs
->buf
+ cs
->max_dw
;
4609 radv_pipeline_generate_depth_stencil_state(ctx_cs
, pipeline
, pCreateInfo
, extra
);
4610 radv_pipeline_generate_blend_state(ctx_cs
, pipeline
, blend
);
4611 radv_pipeline_generate_raster_state(ctx_cs
, pipeline
, pCreateInfo
);
4612 radv_pipeline_generate_multisample_state(ctx_cs
, pipeline
);
4613 radv_pipeline_generate_vgt_gs_mode(ctx_cs
, pipeline
);
4614 radv_pipeline_generate_vertex_shader(ctx_cs
, cs
, pipeline
, tess
);
4615 radv_pipeline_generate_tess_shaders(ctx_cs
, cs
, pipeline
, tess
);
4616 radv_pipeline_generate_geometry_shader(ctx_cs
, cs
, pipeline
);
4617 radv_pipeline_generate_fragment_shader(ctx_cs
, cs
, pipeline
);
4618 radv_pipeline_generate_ps_inputs(ctx_cs
, pipeline
);
4619 radv_pipeline_generate_vgt_vertex_reuse(ctx_cs
, pipeline
);
4620 radv_pipeline_generate_binning_state(ctx_cs
, pipeline
, pCreateInfo
, blend
);
4622 if (pipeline
->device
->physical_device
->rad_info
.chip_class
>= GFX10
&& !radv_pipeline_has_ngg(pipeline
))
4623 gfx10_pipeline_generate_ge_cntl(ctx_cs
, pipeline
, tess
);
4625 radeon_set_context_reg(ctx_cs
, R_028B54_VGT_SHADER_STAGES_EN
, radv_compute_vgt_shader_stages_en(pipeline
));
4626 radeon_set_context_reg(ctx_cs
, R_028A6C_VGT_GS_OUT_PRIM_TYPE
, gs_out
);
4628 radeon_set_context_reg(ctx_cs
, R_02820C_PA_SC_CLIPRECT_RULE
, radv_compute_cliprect_rule(pCreateInfo
));
4630 pipeline
->ctx_cs_hash
= _mesa_hash_data(ctx_cs
->buf
, ctx_cs
->cdw
* 4);
4632 assert(ctx_cs
->cdw
<= ctx_cs
->max_dw
);
4633 assert(cs
->cdw
<= cs
->max_dw
);
4636 static struct radv_ia_multi_vgt_param_helpers
4637 radv_compute_ia_multi_vgt_param_helpers(struct radv_pipeline
*pipeline
,
4638 const struct radv_tessellation_state
*tess
)
4640 struct radv_ia_multi_vgt_param_helpers ia_multi_vgt_param
= {0};
4641 const struct radv_device
*device
= pipeline
->device
;
4643 if (radv_pipeline_has_tess(pipeline
))
4644 ia_multi_vgt_param
.primgroup_size
= tess
->num_patches
;
4645 else if (radv_pipeline_has_gs(pipeline
))
4646 ia_multi_vgt_param
.primgroup_size
= 64;
4648 ia_multi_vgt_param
.primgroup_size
= 128; /* recommended without a GS */
4650 /* GS requirement. */
4651 ia_multi_vgt_param
.partial_es_wave
= false;
4652 if (radv_pipeline_has_gs(pipeline
) && device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4653 if (SI_GS_PER_ES
/ ia_multi_vgt_param
.primgroup_size
>= pipeline
->device
->gs_table_depth
- 3)
4654 ia_multi_vgt_param
.partial_es_wave
= true;
4656 ia_multi_vgt_param
.ia_switch_on_eoi
= false;
4657 if (pipeline
->shaders
[MESA_SHADER_FRAGMENT
]->info
.ps
.prim_id_input
)
4658 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4659 if (radv_pipeline_has_gs(pipeline
) &&
4660 pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.uses_prim_id
)
4661 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4662 if (radv_pipeline_has_tess(pipeline
)) {
4663 /* SWITCH_ON_EOI must be set if PrimID is used. */
4664 if (pipeline
->shaders
[MESA_SHADER_TESS_CTRL
]->info
.uses_prim_id
||
4665 radv_get_shader(pipeline
, MESA_SHADER_TESS_EVAL
)->info
.uses_prim_id
)
4666 ia_multi_vgt_param
.ia_switch_on_eoi
= true;
4669 ia_multi_vgt_param
.partial_vs_wave
= false;
4670 if (radv_pipeline_has_tess(pipeline
)) {
4671 /* Bug with tessellation and GS on Bonaire and older 2 SE chips. */
4672 if ((device
->physical_device
->rad_info
.family
== CHIP_TAHITI
||
4673 device
->physical_device
->rad_info
.family
== CHIP_PITCAIRN
||
4674 device
->physical_device
->rad_info
.family
== CHIP_BONAIRE
) &&
4675 radv_pipeline_has_gs(pipeline
))
4676 ia_multi_vgt_param
.partial_vs_wave
= true;
4677 /* Needed for 028B6C_DISTRIBUTION_MODE != 0 */
4678 if (device
->physical_device
->rad_info
.has_distributed_tess
) {
4679 if (radv_pipeline_has_gs(pipeline
)) {
4680 if (device
->physical_device
->rad_info
.chip_class
<= GFX8
)
4681 ia_multi_vgt_param
.partial_es_wave
= true;
4683 ia_multi_vgt_param
.partial_vs_wave
= true;
4688 if (radv_pipeline_has_gs(pipeline
)) {
4689 /* On these chips there is the possibility of a hang if the
4690 * pipeline uses a GS and partial_vs_wave is not set.
4692 * This mostly does not hit 4-SE chips, as those typically set
4693 * ia_switch_on_eoi and then partial_vs_wave is set for pipelines
4694 * with GS due to another workaround.
4696 * Reproducer: https://bugs.freedesktop.org/show_bug.cgi?id=109242
4698 if (device
->physical_device
->rad_info
.family
== CHIP_TONGA
||
4699 device
->physical_device
->rad_info
.family
== CHIP_FIJI
||
4700 device
->physical_device
->rad_info
.family
== CHIP_POLARIS10
||
4701 device
->physical_device
->rad_info
.family
== CHIP_POLARIS11
||
4702 device
->physical_device
->rad_info
.family
== CHIP_POLARIS12
||
4703 device
->physical_device
->rad_info
.family
== CHIP_VEGAM
) {
4704 ia_multi_vgt_param
.partial_vs_wave
= true;
4708 ia_multi_vgt_param
.base
=
4709 S_028AA8_PRIMGROUP_SIZE(ia_multi_vgt_param
.primgroup_size
- 1) |
4710 /* The following field was moved to VGT_SHADER_STAGES_EN in GFX9. */
4711 S_028AA8_MAX_PRIMGRP_IN_WAVE(device
->physical_device
->rad_info
.chip_class
== GFX8
? 2 : 0) |
4712 S_030960_EN_INST_OPT_BASIC(device
->physical_device
->rad_info
.chip_class
>= GFX9
) |
4713 S_030960_EN_INST_OPT_ADV(device
->physical_device
->rad_info
.chip_class
>= GFX9
);
4715 return ia_multi_vgt_param
;
4720 radv_compute_vertex_input_state(struct radv_pipeline
*pipeline
,
4721 const VkGraphicsPipelineCreateInfo
*pCreateInfo
)
4723 const VkPipelineVertexInputStateCreateInfo
*vi_info
=
4724 pCreateInfo
->pVertexInputState
;
4725 struct radv_vertex_elements_info
*velems
= &pipeline
->vertex_elements
;
4727 for (uint32_t i
= 0; i
< vi_info
->vertexAttributeDescriptionCount
; i
++) {
4728 const VkVertexInputAttributeDescription
*desc
=
4729 &vi_info
->pVertexAttributeDescriptions
[i
];
4730 unsigned loc
= desc
->location
;
4731 const struct vk_format_description
*format_desc
;
4733 format_desc
= vk_format_description(desc
->format
);
4735 velems
->format_size
[loc
] = format_desc
->block
.bits
/ 8;
4738 for (uint32_t i
= 0; i
< vi_info
->vertexBindingDescriptionCount
; i
++) {
4739 const VkVertexInputBindingDescription
*desc
=
4740 &vi_info
->pVertexBindingDescriptions
[i
];
4742 pipeline
->binding_stride
[desc
->binding
] = desc
->stride
;
4743 pipeline
->num_vertex_bindings
=
4744 MAX2(pipeline
->num_vertex_bindings
, desc
->binding
+ 1);
4748 static struct radv_shader_variant
*
4749 radv_pipeline_get_streamout_shader(struct radv_pipeline
*pipeline
)
4753 for (i
= MESA_SHADER_GEOMETRY
; i
>= MESA_SHADER_VERTEX
; i
--) {
4754 struct radv_shader_variant
*shader
=
4755 radv_get_shader(pipeline
, i
);
4757 if (shader
&& shader
->info
.so
.num_outputs
> 0)
4765 radv_pipeline_init(struct radv_pipeline
*pipeline
,
4766 struct radv_device
*device
,
4767 struct radv_pipeline_cache
*cache
,
4768 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4769 const struct radv_graphics_pipeline_create_info
*extra
)
4772 bool has_view_index
= false;
4774 RADV_FROM_HANDLE(radv_render_pass
, pass
, pCreateInfo
->renderPass
);
4775 struct radv_subpass
*subpass
= pass
->subpasses
+ pCreateInfo
->subpass
;
4776 if (subpass
->view_mask
)
4777 has_view_index
= true;
4779 pipeline
->device
= device
;
4780 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
4781 assert(pipeline
->layout
);
4783 struct radv_blend_state blend
= radv_pipeline_init_blend_state(pipeline
, pCreateInfo
, extra
);
4785 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
4786 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
4787 radv_init_feedback(creation_feedback
);
4789 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
4791 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
4792 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
4793 for (uint32_t i
= 0; i
< pCreateInfo
->stageCount
; i
++) {
4794 gl_shader_stage stage
= ffs(pCreateInfo
->pStages
[i
].stage
) - 1;
4795 pStages
[stage
] = &pCreateInfo
->pStages
[i
];
4796 if(creation_feedback
)
4797 stage_feedbacks
[stage
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[i
];
4800 struct radv_pipeline_key key
= radv_generate_graphics_pipeline_key(pipeline
, pCreateInfo
, &blend
, has_view_index
);
4802 result
= radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
,
4803 pCreateInfo
->flags
, pipeline_feedback
,
4805 if (result
!= VK_SUCCESS
)
4808 pipeline
->graphics
.spi_baryc_cntl
= S_0286E0_FRONT_FACE_ALL_BITS(1);
4809 radv_pipeline_init_multisample_state(pipeline
, &blend
, pCreateInfo
);
4812 pipeline
->graphics
.can_use_guardband
= radv_prim_can_use_guardband(pCreateInfo
->pInputAssemblyState
->topology
);
4814 if (radv_pipeline_has_gs(pipeline
)) {
4815 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_GEOMETRY
]->info
.gs
.output_prim
);
4816 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4817 } else if (radv_pipeline_has_tess(pipeline
)) {
4818 if (pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.point_mode
)
4819 gs_out
= V_028A6C_OUTPRIM_TYPE_POINTLIST
;
4821 gs_out
= si_conv_gl_prim_to_gs_out(pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]->info
.tes
.primitive_mode
);
4822 pipeline
->graphics
.can_use_guardband
= gs_out
== V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4824 gs_out
= si_conv_prim_to_gs_out(pCreateInfo
->pInputAssemblyState
->topology
);
4826 if (extra
&& extra
->use_rectlist
) {
4827 gs_out
= V_028A6C_OUTPRIM_TYPE_TRISTRIP
;
4828 pipeline
->graphics
.can_use_guardband
= true;
4829 if (radv_pipeline_has_ngg(pipeline
))
4830 gs_out
= V_028A6C_VGT_OUT_RECT_V0
;
4832 pipeline
->graphics
.prim_restart_enable
= !!pCreateInfo
->pInputAssemblyState
->primitiveRestartEnable
;
4834 radv_pipeline_init_dynamic_state(pipeline
, pCreateInfo
, extra
);
4836 /* Ensure that some export memory is always allocated, for two reasons:
4838 * 1) Correctness: The hardware ignores the EXEC mask if no export
4839 * memory is allocated, so KILL and alpha test do not work correctly
4841 * 2) Performance: Every shader needs at least a NULL export, even when
4842 * it writes no color/depth output. The NULL export instruction
4843 * stalls without this setting.
4845 * Don't add this to CB_SHADER_MASK.
4847 * GFX10 supports pixel shaders without exports by setting both the
4848 * color and Z formats to SPI_SHADER_ZERO. The hw will skip export
4849 * instructions if any are present.
4851 struct radv_shader_variant
*ps
= pipeline
->shaders
[MESA_SHADER_FRAGMENT
];
4852 if ((pipeline
->device
->physical_device
->rad_info
.chip_class
<= GFX9
||
4853 ps
->info
.ps
.can_discard
) &&
4854 !blend
.spi_shader_col_format
) {
4855 if (!ps
->info
.ps
.writes_z
&&
4856 !ps
->info
.ps
.writes_stencil
&&
4857 !ps
->info
.ps
.writes_sample_mask
)
4858 blend
.spi_shader_col_format
= V_028714_SPI_SHADER_32_R
;
4861 blend
.cb_shader_mask
= ps
->info
.ps
.cb_shader_mask
;
4864 (extra
->custom_blend_mode
== V_028808_CB_ELIMINATE_FAST_CLEAR
||
4865 extra
->custom_blend_mode
== V_028808_CB_FMASK_DECOMPRESS
||
4866 extra
->custom_blend_mode
== V_028808_CB_DCC_DECOMPRESS
||
4867 extra
->custom_blend_mode
== V_028808_CB_RESOLVE
)) {
4868 /* According to the CB spec states, CB_SHADER_MASK should be
4869 * set to enable writes to all four channels of MRT0.
4871 blend
.cb_shader_mask
= 0xf;
4874 for (unsigned i
= 0; i
< MESA_SHADER_STAGES
; i
++) {
4875 if (pipeline
->shaders
[i
]) {
4876 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[i
]->info
.need_indirect_descriptor_sets
;
4880 if (radv_pipeline_has_gs(pipeline
) && !radv_pipeline_has_ngg(pipeline
)) {
4881 struct radv_shader_variant
*gs
=
4882 pipeline
->shaders
[MESA_SHADER_GEOMETRY
];
4884 calculate_gs_ring_sizes(pipeline
, &gs
->info
.gs_ring_info
);
4887 struct radv_tessellation_state tess
= {0};
4888 if (radv_pipeline_has_tess(pipeline
)) {
4889 pipeline
->graphics
.tess_patch_control_points
=
4890 pCreateInfo
->pTessellationState
->patchControlPoints
;
4891 tess
= calculate_tess_state(pipeline
, pCreateInfo
);
4894 pipeline
->graphics
.ia_multi_vgt_param
= radv_compute_ia_multi_vgt_param_helpers(pipeline
, &tess
);
4896 radv_compute_vertex_input_state(pipeline
, pCreateInfo
);
4898 for (uint32_t i
= 0; i
< MESA_SHADER_STAGES
; i
++)
4899 pipeline
->user_data_0
[i
] = radv_pipeline_stage_to_user_data_0(pipeline
, i
, device
->physical_device
->rad_info
.chip_class
);
4901 struct radv_userdata_info
*loc
= radv_lookup_user_sgpr(pipeline
, MESA_SHADER_VERTEX
,
4902 AC_UD_VS_BASE_VERTEX_START_INSTANCE
);
4903 if (loc
->sgpr_idx
!= -1) {
4904 pipeline
->graphics
.vtx_base_sgpr
= pipeline
->user_data_0
[MESA_SHADER_VERTEX
];
4905 pipeline
->graphics
.vtx_base_sgpr
+= loc
->sgpr_idx
* 4;
4906 if (radv_get_shader(pipeline
, MESA_SHADER_VERTEX
)->info
.vs
.needs_draw_id
)
4907 pipeline
->graphics
.vtx_emit_num
= 3;
4909 pipeline
->graphics
.vtx_emit_num
= 2;
4912 /* Find the last vertex shader stage that eventually uses streamout. */
4913 pipeline
->streamout_shader
= radv_pipeline_get_streamout_shader(pipeline
);
4915 result
= radv_pipeline_scratch_init(device
, pipeline
);
4916 radv_pipeline_generate_pm4(pipeline
, pCreateInfo
, extra
, &blend
, &tess
, gs_out
);
4922 radv_graphics_pipeline_create(
4924 VkPipelineCache _cache
,
4925 const VkGraphicsPipelineCreateInfo
*pCreateInfo
,
4926 const struct radv_graphics_pipeline_create_info
*extra
,
4927 const VkAllocationCallbacks
*pAllocator
,
4928 VkPipeline
*pPipeline
)
4930 RADV_FROM_HANDLE(radv_device
, device
, _device
);
4931 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
4932 struct radv_pipeline
*pipeline
;
4935 pipeline
= vk_zalloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*pipeline
), 8,
4936 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
4937 if (pipeline
== NULL
)
4938 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
4940 vk_object_base_init(&device
->vk
, &pipeline
->base
,
4941 VK_OBJECT_TYPE_PIPELINE
);
4943 result
= radv_pipeline_init(pipeline
, device
, cache
,
4944 pCreateInfo
, extra
);
4945 if (result
!= VK_SUCCESS
) {
4946 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
4950 *pPipeline
= radv_pipeline_to_handle(pipeline
);
4955 VkResult
radv_CreateGraphicsPipelines(
4957 VkPipelineCache pipelineCache
,
4959 const VkGraphicsPipelineCreateInfo
* pCreateInfos
,
4960 const VkAllocationCallbacks
* pAllocator
,
4961 VkPipeline
* pPipelines
)
4963 VkResult result
= VK_SUCCESS
;
4966 for (; i
< count
; i
++) {
4968 r
= radv_graphics_pipeline_create(_device
,
4971 NULL
, pAllocator
, &pPipelines
[i
]);
4972 if (r
!= VK_SUCCESS
) {
4974 pPipelines
[i
] = VK_NULL_HANDLE
;
4976 if (pCreateInfos
[i
].flags
& VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT
)
4981 for (; i
< count
; ++i
)
4982 pPipelines
[i
] = VK_NULL_HANDLE
;
4989 radv_compute_generate_pm4(struct radv_pipeline
*pipeline
)
4991 struct radv_shader_variant
*compute_shader
;
4992 struct radv_device
*device
= pipeline
->device
;
4993 unsigned threads_per_threadgroup
;
4994 unsigned threadgroups_per_cu
= 1;
4995 unsigned waves_per_threadgroup
;
4996 unsigned max_waves_per_sh
= 0;
4999 pipeline
->cs
.max_dw
= device
->physical_device
->rad_info
.chip_class
>= GFX10
? 22 : 20;
5000 pipeline
->cs
.buf
= malloc(pipeline
->cs
.max_dw
* 4);
5002 compute_shader
= pipeline
->shaders
[MESA_SHADER_COMPUTE
];
5003 va
= radv_buffer_get_va(compute_shader
->bo
) + compute_shader
->bo_offset
;
5005 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B830_COMPUTE_PGM_LO
, 2);
5006 radeon_emit(&pipeline
->cs
, va
>> 8);
5007 radeon_emit(&pipeline
->cs
, S_00B834_DATA(va
>> 40));
5009 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B848_COMPUTE_PGM_RSRC1
, 2);
5010 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc1
);
5011 radeon_emit(&pipeline
->cs
, compute_shader
->config
.rsrc2
);
5012 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
) {
5013 radeon_set_sh_reg(&pipeline
->cs
, R_00B8A0_COMPUTE_PGM_RSRC3
, compute_shader
->config
.rsrc3
);
5016 /* Calculate best compute resource limits. */
5017 threads_per_threadgroup
= compute_shader
->info
.cs
.block_size
[0] *
5018 compute_shader
->info
.cs
.block_size
[1] *
5019 compute_shader
->info
.cs
.block_size
[2];
5020 waves_per_threadgroup
= DIV_ROUND_UP(threads_per_threadgroup
,
5021 compute_shader
->info
.wave_size
);
5023 if (device
->physical_device
->rad_info
.chip_class
>= GFX10
&&
5024 waves_per_threadgroup
== 1)
5025 threadgroups_per_cu
= 2;
5027 radeon_set_sh_reg(&pipeline
->cs
, R_00B854_COMPUTE_RESOURCE_LIMITS
,
5028 ac_get_compute_resource_limits(&device
->physical_device
->rad_info
,
5029 waves_per_threadgroup
,
5031 threadgroups_per_cu
));
5033 radeon_set_sh_reg_seq(&pipeline
->cs
, R_00B81C_COMPUTE_NUM_THREAD_X
, 3);
5034 radeon_emit(&pipeline
->cs
,
5035 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[0]));
5036 radeon_emit(&pipeline
->cs
,
5037 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[1]));
5038 radeon_emit(&pipeline
->cs
,
5039 S_00B81C_NUM_THREAD_FULL(compute_shader
->info
.cs
.block_size
[2]));
5041 assert(pipeline
->cs
.cdw
<= pipeline
->cs
.max_dw
);
5044 static struct radv_pipeline_key
5045 radv_generate_compute_pipeline_key(struct radv_pipeline
*pipeline
,
5046 const VkComputePipelineCreateInfo
*pCreateInfo
)
5048 const VkPipelineShaderStageCreateInfo
*stage
= &pCreateInfo
->stage
;
5049 struct radv_pipeline_key key
;
5050 memset(&key
, 0, sizeof(key
));
5052 if (pCreateInfo
->flags
& VK_PIPELINE_CREATE_DISABLE_OPTIMIZATION_BIT
)
5053 key
.optimisations_disabled
= 1;
5055 const VkPipelineShaderStageRequiredSubgroupSizeCreateInfoEXT
*subgroup_size
=
5056 vk_find_struct_const(stage
->pNext
,
5057 PIPELINE_SHADER_STAGE_REQUIRED_SUBGROUP_SIZE_CREATE_INFO_EXT
);
5059 if (subgroup_size
) {
5060 assert(subgroup_size
->requiredSubgroupSize
== 32 ||
5061 subgroup_size
->requiredSubgroupSize
== 64);
5062 key
.compute_subgroup_size
= subgroup_size
->requiredSubgroupSize
;
5068 static VkResult
radv_compute_pipeline_create(
5070 VkPipelineCache _cache
,
5071 const VkComputePipelineCreateInfo
* pCreateInfo
,
5072 const VkAllocationCallbacks
* pAllocator
,
5073 VkPipeline
* pPipeline
)
5075 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5076 RADV_FROM_HANDLE(radv_pipeline_cache
, cache
, _cache
);
5077 const VkPipelineShaderStageCreateInfo
*pStages
[MESA_SHADER_STAGES
] = { 0, };
5078 VkPipelineCreationFeedbackEXT
*stage_feedbacks
[MESA_SHADER_STAGES
] = { 0 };
5079 struct radv_pipeline
*pipeline
;
5082 pipeline
= vk_zalloc2(&device
->vk
.alloc
, pAllocator
, sizeof(*pipeline
), 8,
5083 VK_SYSTEM_ALLOCATION_SCOPE_OBJECT
);
5084 if (pipeline
== NULL
)
5085 return vk_error(device
->instance
, VK_ERROR_OUT_OF_HOST_MEMORY
);
5087 vk_object_base_init(&device
->vk
, &pipeline
->base
,
5088 VK_OBJECT_TYPE_PIPELINE
);
5090 pipeline
->device
= device
;
5091 pipeline
->layout
= radv_pipeline_layout_from_handle(pCreateInfo
->layout
);
5092 assert(pipeline
->layout
);
5094 const VkPipelineCreationFeedbackCreateInfoEXT
*creation_feedback
=
5095 vk_find_struct_const(pCreateInfo
->pNext
, PIPELINE_CREATION_FEEDBACK_CREATE_INFO_EXT
);
5096 radv_init_feedback(creation_feedback
);
5098 VkPipelineCreationFeedbackEXT
*pipeline_feedback
= creation_feedback
? creation_feedback
->pPipelineCreationFeedback
: NULL
;
5099 if (creation_feedback
)
5100 stage_feedbacks
[MESA_SHADER_COMPUTE
] = &creation_feedback
->pPipelineStageCreationFeedbacks
[0];
5102 pStages
[MESA_SHADER_COMPUTE
] = &pCreateInfo
->stage
;
5104 struct radv_pipeline_key key
=
5105 radv_generate_compute_pipeline_key(pipeline
, pCreateInfo
);
5107 result
= radv_create_shaders(pipeline
, device
, cache
, &key
, pStages
,
5108 pCreateInfo
->flags
, pipeline_feedback
,
5110 if (result
!= VK_SUCCESS
) {
5111 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5115 pipeline
->user_data_0
[MESA_SHADER_COMPUTE
] = radv_pipeline_stage_to_user_data_0(pipeline
, MESA_SHADER_COMPUTE
, device
->physical_device
->rad_info
.chip_class
);
5116 pipeline
->need_indirect_descriptor_sets
|= pipeline
->shaders
[MESA_SHADER_COMPUTE
]->info
.need_indirect_descriptor_sets
;
5117 result
= radv_pipeline_scratch_init(device
, pipeline
);
5118 if (result
!= VK_SUCCESS
) {
5119 radv_pipeline_destroy(device
, pipeline
, pAllocator
);
5123 radv_compute_generate_pm4(pipeline
);
5125 *pPipeline
= radv_pipeline_to_handle(pipeline
);
5130 VkResult
radv_CreateComputePipelines(
5132 VkPipelineCache pipelineCache
,
5134 const VkComputePipelineCreateInfo
* pCreateInfos
,
5135 const VkAllocationCallbacks
* pAllocator
,
5136 VkPipeline
* pPipelines
)
5138 VkResult result
= VK_SUCCESS
;
5141 for (; i
< count
; i
++) {
5143 r
= radv_compute_pipeline_create(_device
, pipelineCache
,
5145 pAllocator
, &pPipelines
[i
]);
5146 if (r
!= VK_SUCCESS
) {
5148 pPipelines
[i
] = VK_NULL_HANDLE
;
5150 if (pCreateInfos
[i
].flags
& VK_PIPELINE_CREATE_EARLY_RETURN_ON_FAILURE_BIT_EXT
)
5155 for (; i
< count
; ++i
)
5156 pPipelines
[i
] = VK_NULL_HANDLE
;
5162 static uint32_t radv_get_executable_count(const struct radv_pipeline
*pipeline
)
5165 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5166 if (!pipeline
->shaders
[i
])
5169 if (i
== MESA_SHADER_GEOMETRY
&&
5170 !radv_pipeline_has_ngg(pipeline
)) {
5180 static struct radv_shader_variant
*
5181 radv_get_shader_from_executable_index(const struct radv_pipeline
*pipeline
, int index
, gl_shader_stage
*stage
)
5183 for (int i
= 0; i
< MESA_SHADER_STAGES
; ++i
) {
5184 if (!pipeline
->shaders
[i
])
5188 return pipeline
->shaders
[i
];
5193 if (i
== MESA_SHADER_GEOMETRY
&&
5194 !radv_pipeline_has_ngg(pipeline
)) {
5197 return pipeline
->gs_copy_shader
;
5207 /* Basically strlcpy (which does not exist on linux) specialized for
5209 static void desc_copy(char *desc
, const char *src
) {
5210 int len
= strlen(src
);
5211 assert(len
< VK_MAX_DESCRIPTION_SIZE
);
5212 memcpy(desc
, src
, len
);
5213 memset(desc
+ len
, 0, VK_MAX_DESCRIPTION_SIZE
- len
);
5216 VkResult
radv_GetPipelineExecutablePropertiesKHR(
5218 const VkPipelineInfoKHR
* pPipelineInfo
,
5219 uint32_t* pExecutableCount
,
5220 VkPipelineExecutablePropertiesKHR
* pProperties
)
5222 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pPipelineInfo
->pipeline
);
5223 const uint32_t total_count
= radv_get_executable_count(pipeline
);
5226 *pExecutableCount
= total_count
;
5230 const uint32_t count
= MIN2(total_count
, *pExecutableCount
);
5231 for (unsigned i
= 0, executable_idx
= 0;
5232 i
< MESA_SHADER_STAGES
&& executable_idx
< count
; ++i
) {
5233 if (!pipeline
->shaders
[i
])
5235 pProperties
[executable_idx
].stages
= mesa_to_vk_shader_stage(i
);
5236 const char *name
= NULL
;
5237 const char *description
= NULL
;
5239 case MESA_SHADER_VERTEX
:
5240 name
= "Vertex Shader";
5241 description
= "Vulkan Vertex Shader";
5243 case MESA_SHADER_TESS_CTRL
:
5244 if (!pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5245 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5246 name
= "Vertex + Tessellation Control Shaders";
5247 description
= "Combined Vulkan Vertex and Tessellation Control Shaders";
5249 name
= "Tessellation Control Shader";
5250 description
= "Vulkan Tessellation Control Shader";
5253 case MESA_SHADER_TESS_EVAL
:
5254 name
= "Tessellation Evaluation Shader";
5255 description
= "Vulkan Tessellation Evaluation Shader";
5257 case MESA_SHADER_GEOMETRY
:
5258 if (radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_TESS_EVAL
]) {
5259 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_TESSELLATION_EVALUATION_BIT
;
5260 name
= "Tessellation Evaluation + Geometry Shaders";
5261 description
= "Combined Vulkan Tessellation Evaluation and Geometry Shaders";
5262 } else if (!radv_pipeline_has_tess(pipeline
) && !pipeline
->shaders
[MESA_SHADER_VERTEX
]) {
5263 pProperties
[executable_idx
].stages
|= VK_SHADER_STAGE_VERTEX_BIT
;
5264 name
= "Vertex + Geometry Shader";
5265 description
= "Combined Vulkan Vertex and Geometry Shaders";
5267 name
= "Geometry Shader";
5268 description
= "Vulkan Geometry Shader";
5271 case MESA_SHADER_FRAGMENT
:
5272 name
= "Fragment Shader";
5273 description
= "Vulkan Fragment Shader";
5275 case MESA_SHADER_COMPUTE
:
5276 name
= "Compute Shader";
5277 description
= "Vulkan Compute Shader";
5281 pProperties
[executable_idx
].subgroupSize
= pipeline
->shaders
[i
]->info
.wave_size
;
5282 desc_copy(pProperties
[executable_idx
].name
, name
);
5283 desc_copy(pProperties
[executable_idx
].description
, description
);
5286 if (i
== MESA_SHADER_GEOMETRY
&&
5287 !radv_pipeline_has_ngg(pipeline
)) {
5288 assert(pipeline
->gs_copy_shader
);
5289 if (executable_idx
>= count
)
5292 pProperties
[executable_idx
].stages
= VK_SHADER_STAGE_GEOMETRY_BIT
;
5293 pProperties
[executable_idx
].subgroupSize
= 64;
5294 desc_copy(pProperties
[executable_idx
].name
, "GS Copy Shader");
5295 desc_copy(pProperties
[executable_idx
].description
,
5296 "Extra shader stage that loads the GS output ringbuffer into the rasterizer");
5302 VkResult result
= *pExecutableCount
< total_count
? VK_INCOMPLETE
: VK_SUCCESS
;
5303 *pExecutableCount
= count
;
5307 VkResult
radv_GetPipelineExecutableStatisticsKHR(
5309 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5310 uint32_t* pStatisticCount
,
5311 VkPipelineExecutableStatisticKHR
* pStatistics
)
5313 RADV_FROM_HANDLE(radv_device
, device
, _device
);
5314 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5315 gl_shader_stage stage
;
5316 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5318 enum chip_class chip_class
= device
->physical_device
->rad_info
.chip_class
;
5319 unsigned lds_increment
= chip_class
>= GFX7
? 512 : 256;
5320 unsigned max_waves
= radv_get_max_waves(device
, shader
, stage
);
5322 VkPipelineExecutableStatisticKHR
*s
= pStatistics
;
5323 VkPipelineExecutableStatisticKHR
*end
= s
+ (pStatistics
? *pStatisticCount
: 0);
5324 VkResult result
= VK_SUCCESS
;
5327 desc_copy(s
->name
, "SGPRs");
5328 desc_copy(s
->description
, "Number of SGPR registers allocated per subgroup");
5329 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5330 s
->value
.u64
= shader
->config
.num_sgprs
;
5335 desc_copy(s
->name
, "VGPRs");
5336 desc_copy(s
->description
, "Number of VGPR registers allocated per subgroup");
5337 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5338 s
->value
.u64
= shader
->config
.num_vgprs
;
5343 desc_copy(s
->name
, "Spilled SGPRs");
5344 desc_copy(s
->description
, "Number of SGPR registers spilled per subgroup");
5345 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5346 s
->value
.u64
= shader
->config
.spilled_sgprs
;
5351 desc_copy(s
->name
, "Spilled VGPRs");
5352 desc_copy(s
->description
, "Number of VGPR registers spilled per subgroup");
5353 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5354 s
->value
.u64
= shader
->config
.spilled_vgprs
;
5359 desc_copy(s
->name
, "PrivMem VGPRs");
5360 desc_copy(s
->description
, "Number of VGPRs stored in private memory per subgroup");
5361 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5362 s
->value
.u64
= shader
->info
.private_mem_vgprs
;
5367 desc_copy(s
->name
, "Code size");
5368 desc_copy(s
->description
, "Code size in bytes");
5369 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5370 s
->value
.u64
= shader
->exec_size
;
5375 desc_copy(s
->name
, "LDS size");
5376 desc_copy(s
->description
, "LDS size in bytes per workgroup");
5377 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5378 s
->value
.u64
= shader
->config
.lds_size
* lds_increment
;
5383 desc_copy(s
->name
, "Scratch size");
5384 desc_copy(s
->description
, "Private memory in bytes per subgroup");
5385 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5386 s
->value
.u64
= shader
->config
.scratch_bytes_per_wave
;
5391 desc_copy(s
->name
, "Subgroups per SIMD");
5392 desc_copy(s
->description
, "The maximum number of subgroups in flight on a SIMD unit");
5393 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5394 s
->value
.u64
= max_waves
;
5398 if (shader
->statistics
) {
5399 for (unsigned i
= 0; i
< shader
->statistics
->count
; i
++) {
5400 struct radv_compiler_statistic_info
*info
= &shader
->statistics
->infos
[i
];
5401 uint32_t value
= shader
->statistics
->values
[i
];
5403 desc_copy(s
->name
, info
->name
);
5404 desc_copy(s
->description
, info
->desc
);
5405 s
->format
= VK_PIPELINE_EXECUTABLE_STATISTIC_FORMAT_UINT64_KHR
;
5406 s
->value
.u64
= value
;
5413 *pStatisticCount
= s
- pStatistics
;
5415 *pStatisticCount
= end
- pStatistics
;
5416 result
= VK_INCOMPLETE
;
5418 *pStatisticCount
= s
- pStatistics
;
5424 static VkResult
radv_copy_representation(void *data
, size_t *data_size
, const char *src
)
5426 size_t total_size
= strlen(src
) + 1;
5429 *data_size
= total_size
;
5433 size_t size
= MIN2(total_size
, *data_size
);
5435 memcpy(data
, src
, size
);
5437 *((char*)data
+ size
- 1) = 0;
5438 return size
< total_size
? VK_INCOMPLETE
: VK_SUCCESS
;
5441 VkResult
radv_GetPipelineExecutableInternalRepresentationsKHR(
5443 const VkPipelineExecutableInfoKHR
* pExecutableInfo
,
5444 uint32_t* pInternalRepresentationCount
,
5445 VkPipelineExecutableInternalRepresentationKHR
* pInternalRepresentations
)
5447 RADV_FROM_HANDLE(radv_pipeline
, pipeline
, pExecutableInfo
->pipeline
);
5448 gl_shader_stage stage
;
5449 struct radv_shader_variant
*shader
= radv_get_shader_from_executable_index(pipeline
, pExecutableInfo
->executableIndex
, &stage
);
5451 VkPipelineExecutableInternalRepresentationKHR
*p
= pInternalRepresentations
;
5452 VkPipelineExecutableInternalRepresentationKHR
*end
= p
+ (pInternalRepresentations
? *pInternalRepresentationCount
: 0);
5453 VkResult result
= VK_SUCCESS
;
5457 desc_copy(p
->name
, "NIR Shader(s)");
5458 desc_copy(p
->description
, "The optimized NIR shader(s)");
5459 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->nir_string
) != VK_SUCCESS
)
5460 result
= VK_INCOMPLETE
;
5467 if (pipeline
->device
->physical_device
->use_llvm
) {
5468 desc_copy(p
->name
, "LLVM IR");
5469 desc_copy(p
->description
, "The LLVM IR after some optimizations");
5471 desc_copy(p
->name
, "ACO IR");
5472 desc_copy(p
->description
, "The ACO IR after some optimizations");
5474 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->ir_string
) != VK_SUCCESS
)
5475 result
= VK_INCOMPLETE
;
5482 desc_copy(p
->name
, "Assembly");
5483 desc_copy(p
->description
, "Final Assembly");
5484 if (radv_copy_representation(p
->pData
, &p
->dataSize
, shader
->disasm_string
) != VK_SUCCESS
)
5485 result
= VK_INCOMPLETE
;
5489 if (!pInternalRepresentations
)
5490 *pInternalRepresentationCount
= p
- pInternalRepresentations
;
5492 result
= VK_INCOMPLETE
;
5493 *pInternalRepresentationCount
= end
- pInternalRepresentations
;
5495 *pInternalRepresentationCount
= p
- pInternalRepresentations
;